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058e97ec | 1 | /* Integrated Register Allocator (IRA) entry point. |
2805e6c0 | 2 | Copyright (C) 2006, 2007, 2008, 2009, 2010, 2011, 2012 |
058e97ec VM |
3 | Free Software Foundation, Inc. |
4 | Contributed by Vladimir Makarov <vmakarov@redhat.com>. | |
5 | ||
6 | This file is part of GCC. | |
7 | ||
8 | GCC is free software; you can redistribute it and/or modify it under | |
9 | the terms of the GNU General Public License as published by the Free | |
10 | Software Foundation; either version 3, or (at your option) any later | |
11 | version. | |
12 | ||
13 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
14 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GCC; see the file COPYING3. If not see | |
20 | <http://www.gnu.org/licenses/>. */ | |
21 | ||
22 | /* The integrated register allocator (IRA) is a | |
23 | regional register allocator performing graph coloring on a top-down | |
24 | traversal of nested regions. Graph coloring in a region is based | |
25 | on Chaitin-Briggs algorithm. It is called integrated because | |
26 | register coalescing, register live range splitting, and choosing a | |
27 | better hard register are done on-the-fly during coloring. Register | |
28 | coalescing and choosing a cheaper hard register is done by hard | |
29 | register preferencing during hard register assigning. The live | |
30 | range splitting is a byproduct of the regional register allocation. | |
31 | ||
32 | Major IRA notions are: | |
33 | ||
34 | o *Region* is a part of CFG where graph coloring based on | |
35 | Chaitin-Briggs algorithm is done. IRA can work on any set of | |
36 | nested CFG regions forming a tree. Currently the regions are | |
37 | the entire function for the root region and natural loops for | |
38 | the other regions. Therefore data structure representing a | |
39 | region is called loop_tree_node. | |
40 | ||
1756cb66 VM |
41 | o *Allocno class* is a register class used for allocation of |
42 | given allocno. It means that only hard register of given | |
43 | register class can be assigned to given allocno. In reality, | |
44 | even smaller subset of (*profitable*) hard registers can be | |
45 | assigned. In rare cases, the subset can be even smaller | |
46 | because our modification of Chaitin-Briggs algorithm requires | |
47 | that sets of hard registers can be assigned to allocnos forms a | |
48 | forest, i.e. the sets can be ordered in a way where any | |
49 | previous set is not intersected with given set or is a superset | |
50 | of given set. | |
51 | ||
52 | o *Pressure class* is a register class belonging to a set of | |
53 | register classes containing all of the hard-registers available | |
54 | for register allocation. The set of all pressure classes for a | |
55 | target is defined in the corresponding machine-description file | |
56 | according some criteria. Register pressure is calculated only | |
57 | for pressure classes and it affects some IRA decisions as | |
58 | forming allocation regions. | |
058e97ec VM |
59 | |
60 | o *Allocno* represents the live range of a pseudo-register in a | |
61 | region. Besides the obvious attributes like the corresponding | |
1756cb66 | 62 | pseudo-register number, allocno class, conflicting allocnos and |
058e97ec VM |
63 | conflicting hard-registers, there are a few allocno attributes |
64 | which are important for understanding the allocation algorithm: | |
65 | ||
1756cb66 VM |
66 | - *Live ranges*. This is a list of ranges of *program points* |
67 | where the allocno lives. Program points represent places | |
68 | where a pseudo can be born or become dead (there are | |
058e97ec VM |
69 | approximately two times more program points than the insns) |
70 | and they are represented by integers starting with 0. The | |
1756cb66 VM |
71 | live ranges are used to find conflicts between allocnos. |
72 | They also play very important role for the transformation of | |
73 | the IRA internal representation of several regions into a one | |
74 | region representation. The later is used during the reload | |
75 | pass work because each allocno represents all of the | |
76 | corresponding pseudo-registers. | |
058e97ec VM |
77 | |
78 | - *Hard-register costs*. This is a vector of size equal to the | |
1756cb66 VM |
79 | number of available hard-registers of the allocno class. The |
80 | cost of a callee-clobbered hard-register for an allocno is | |
81 | increased by the cost of save/restore code around the calls | |
82 | through the given allocno's life. If the allocno is a move | |
83 | instruction operand and another operand is a hard-register of | |
84 | the allocno class, the cost of the hard-register is decreased | |
85 | by the move cost. | |
058e97ec VM |
86 | |
87 | When an allocno is assigned, the hard-register with minimal | |
88 | full cost is used. Initially, a hard-register's full cost is | |
89 | the corresponding value from the hard-register's cost vector. | |
90 | If the allocno is connected by a *copy* (see below) to | |
91 | another allocno which has just received a hard-register, the | |
92 | cost of the hard-register is decreased. Before choosing a | |
93 | hard-register for an allocno, the allocno's current costs of | |
94 | the hard-registers are modified by the conflict hard-register | |
95 | costs of all of the conflicting allocnos which are not | |
96 | assigned yet. | |
97 | ||
98 | - *Conflict hard-register costs*. This is a vector of the same | |
99 | size as the hard-register costs vector. To permit an | |
100 | unassigned allocno to get a better hard-register, IRA uses | |
101 | this vector to calculate the final full cost of the | |
102 | available hard-registers. Conflict hard-register costs of an | |
103 | unassigned allocno are also changed with a change of the | |
104 | hard-register cost of the allocno when a copy involving the | |
105 | allocno is processed as described above. This is done to | |
106 | show other unassigned allocnos that a given allocno prefers | |
107 | some hard-registers in order to remove the move instruction | |
108 | corresponding to the copy. | |
109 | ||
110 | o *Cap*. If a pseudo-register does not live in a region but | |
111 | lives in a nested region, IRA creates a special allocno called | |
112 | a cap in the outer region. A region cap is also created for a | |
113 | subregion cap. | |
114 | ||
115 | o *Copy*. Allocnos can be connected by copies. Copies are used | |
116 | to modify hard-register costs for allocnos during coloring. | |
117 | Such modifications reflects a preference to use the same | |
118 | hard-register for the allocnos connected by copies. Usually | |
119 | copies are created for move insns (in this case it results in | |
120 | register coalescing). But IRA also creates copies for operands | |
121 | of an insn which should be assigned to the same hard-register | |
122 | due to constraints in the machine description (it usually | |
123 | results in removing a move generated in reload to satisfy | |
124 | the constraints) and copies referring to the allocno which is | |
125 | the output operand of an instruction and the allocno which is | |
126 | an input operand dying in the instruction (creation of such | |
127 | copies results in less register shuffling). IRA *does not* | |
128 | create copies between the same register allocnos from different | |
129 | regions because we use another technique for propagating | |
130 | hard-register preference on the borders of regions. | |
131 | ||
132 | Allocnos (including caps) for the upper region in the region tree | |
133 | *accumulate* information important for coloring from allocnos with | |
134 | the same pseudo-register from nested regions. This includes | |
135 | hard-register and memory costs, conflicts with hard-registers, | |
136 | allocno conflicts, allocno copies and more. *Thus, attributes for | |
137 | allocnos in a region have the same values as if the region had no | |
138 | subregions*. It means that attributes for allocnos in the | |
139 | outermost region corresponding to the function have the same values | |
140 | as though the allocation used only one region which is the entire | |
141 | function. It also means that we can look at IRA work as if the | |
142 | first IRA did allocation for all function then it improved the | |
143 | allocation for loops then their subloops and so on. | |
144 | ||
145 | IRA major passes are: | |
146 | ||
147 | o Building IRA internal representation which consists of the | |
148 | following subpasses: | |
149 | ||
150 | * First, IRA builds regions and creates allocnos (file | |
151 | ira-build.c) and initializes most of their attributes. | |
152 | ||
1756cb66 VM |
153 | * Then IRA finds an allocno class for each allocno and |
154 | calculates its initial (non-accumulated) cost of memory and | |
155 | each hard-register of its allocno class (file ira-cost.c). | |
058e97ec VM |
156 | |
157 | * IRA creates live ranges of each allocno, calulates register | |
1756cb66 | 158 | pressure for each pressure class in each region, sets up |
058e97ec VM |
159 | conflict hard registers for each allocno and info about calls |
160 | the allocno lives through (file ira-lives.c). | |
161 | ||
162 | * IRA removes low register pressure loops from the regions | |
163 | mostly to speed IRA up (file ira-build.c). | |
164 | ||
165 | * IRA propagates accumulated allocno info from lower region | |
166 | allocnos to corresponding upper region allocnos (file | |
167 | ira-build.c). | |
168 | ||
169 | * IRA creates all caps (file ira-build.c). | |
170 | ||
1756cb66 VM |
171 | * Having live-ranges of allocnos and their classes, IRA creates |
172 | conflicting allocnos for each allocno. Conflicting allocnos | |
173 | are stored as a bit vector or array of pointers to the | |
174 | conflicting allocnos whatever is more profitable (file | |
175 | ira-conflicts.c). At this point IRA creates allocno copies. | |
058e97ec VM |
176 | |
177 | o Coloring. Now IRA has all necessary info to start graph coloring | |
178 | process. It is done in each region on top-down traverse of the | |
179 | region tree (file ira-color.c). There are following subpasses: | |
b8698a0f | 180 | |
1756cb66 VM |
181 | * Finding profitable hard registers of corresponding allocno |
182 | class for each allocno. For example, only callee-saved hard | |
183 | registers are frequently profitable for allocnos living | |
184 | through colors. If the profitable hard register set of | |
185 | allocno does not form a tree based on subset relation, we use | |
186 | some approximation to form the tree. This approximation is | |
187 | used to figure out trivial colorability of allocnos. The | |
188 | approximation is a pretty rare case. | |
189 | ||
058e97ec VM |
190 | * Putting allocnos onto the coloring stack. IRA uses Briggs |
191 | optimistic coloring which is a major improvement over | |
192 | Chaitin's coloring. Therefore IRA does not spill allocnos at | |
193 | this point. There is some freedom in the order of putting | |
194 | allocnos on the stack which can affect the final result of | |
1756cb66 VM |
195 | the allocation. IRA uses some heuristics to improve the |
196 | order. | |
197 | ||
198 | We also use a modification of Chaitin-Briggs algorithm which | |
199 | works for intersected register classes of allocnos. To | |
200 | figure out trivial colorability of allocnos, the mentioned | |
201 | above tree of hard register sets is used. To get an idea how | |
202 | the algorithm works in i386 example, let us consider an | |
203 | allocno to which any general hard register can be assigned. | |
204 | If the allocno conflicts with eight allocnos to which only | |
205 | EAX register can be assigned, given allocno is still | |
206 | trivially colorable because all conflicting allocnos might be | |
207 | assigned only to EAX and all other general hard registers are | |
208 | still free. | |
209 | ||
210 | To get an idea of the used trivial colorability criterion, it | |
211 | is also useful to read article "Graph-Coloring Register | |
212 | Allocation for Irregular Architectures" by Michael D. Smith | |
213 | and Glen Holloway. Major difference between the article | |
214 | approach and approach used in IRA is that Smith's approach | |
215 | takes register classes only from machine description and IRA | |
216 | calculate register classes from intermediate code too | |
217 | (e.g. an explicit usage of hard registers in RTL code for | |
218 | parameter passing can result in creation of additional | |
219 | register classes which contain or exclude the hard | |
220 | registers). That makes IRA approach useful for improving | |
221 | coloring even for architectures with regular register files | |
222 | and in fact some benchmarking shows the improvement for | |
223 | regular class architectures is even bigger than for irregular | |
224 | ones. Another difference is that Smith's approach chooses | |
225 | intersection of classes of all insn operands in which a given | |
226 | pseudo occurs. IRA can use bigger classes if it is still | |
227 | more profitable than memory usage. | |
058e97ec VM |
228 | |
229 | * Popping the allocnos from the stack and assigning them hard | |
230 | registers. If IRA can not assign a hard register to an | |
231 | allocno and the allocno is coalesced, IRA undoes the | |
232 | coalescing and puts the uncoalesced allocnos onto the stack in | |
233 | the hope that some such allocnos will get a hard register | |
234 | separately. If IRA fails to assign hard register or memory | |
235 | is more profitable for it, IRA spills the allocno. IRA | |
236 | assigns the allocno the hard-register with minimal full | |
237 | allocation cost which reflects the cost of usage of the | |
238 | hard-register for the allocno and cost of usage of the | |
239 | hard-register for allocnos conflicting with given allocno. | |
240 | ||
1756cb66 VM |
241 | * Chaitin-Briggs coloring assigns as many pseudos as possible |
242 | to hard registers. After coloringh we try to improve | |
243 | allocation with cost point of view. We improve the | |
244 | allocation by spilling some allocnos and assigning the freed | |
245 | hard registers to other allocnos if it decreases the overall | |
246 | allocation cost. | |
247 | ||
058e97ec VM |
248 | * After allono assigning in the region, IRA modifies the hard |
249 | register and memory costs for the corresponding allocnos in | |
250 | the subregions to reflect the cost of possible loads, stores, | |
251 | or moves on the border of the region and its subregions. | |
252 | When default regional allocation algorithm is used | |
253 | (-fira-algorithm=mixed), IRA just propagates the assignment | |
254 | for allocnos if the register pressure in the region for the | |
1756cb66 VM |
255 | corresponding pressure class is less than number of available |
256 | hard registers for given pressure class. | |
058e97ec VM |
257 | |
258 | o Spill/restore code moving. When IRA performs an allocation | |
259 | by traversing regions in top-down order, it does not know what | |
260 | happens below in the region tree. Therefore, sometimes IRA | |
261 | misses opportunities to perform a better allocation. A simple | |
262 | optimization tries to improve allocation in a region having | |
263 | subregions and containing in another region. If the | |
264 | corresponding allocnos in the subregion are spilled, it spills | |
265 | the region allocno if it is profitable. The optimization | |
266 | implements a simple iterative algorithm performing profitable | |
267 | transformations while they are still possible. It is fast in | |
268 | practice, so there is no real need for a better time complexity | |
269 | algorithm. | |
270 | ||
1756cb66 VM |
271 | o Code change. After coloring, two allocnos representing the |
272 | same pseudo-register outside and inside a region respectively | |
273 | may be assigned to different locations (hard-registers or | |
274 | memory). In this case IRA creates and uses a new | |
275 | pseudo-register inside the region and adds code to move allocno | |
276 | values on the region's borders. This is done during top-down | |
277 | traversal of the regions (file ira-emit.c). In some | |
278 | complicated cases IRA can create a new allocno to move allocno | |
279 | values (e.g. when a swap of values stored in two hard-registers | |
280 | is needed). At this stage, the new allocno is marked as | |
281 | spilled. IRA still creates the pseudo-register and the moves | |
282 | on the region borders even when both allocnos were assigned to | |
283 | the same hard-register. If the reload pass spills a | |
284 | pseudo-register for some reason, the effect will be smaller | |
285 | because another allocno will still be in the hard-register. In | |
286 | most cases, this is better then spilling both allocnos. If | |
287 | reload does not change the allocation for the two | |
288 | pseudo-registers, the trivial move will be removed by | |
289 | post-reload optimizations. IRA does not generate moves for | |
058e97ec VM |
290 | allocnos assigned to the same hard register when the default |
291 | regional allocation algorithm is used and the register pressure | |
1756cb66 VM |
292 | in the region for the corresponding pressure class is less than |
293 | number of available hard registers for given pressure class. | |
058e97ec VM |
294 | IRA also does some optimizations to remove redundant stores and |
295 | to reduce code duplication on the region borders. | |
296 | ||
297 | o Flattening internal representation. After changing code, IRA | |
298 | transforms its internal representation for several regions into | |
299 | one region representation (file ira-build.c). This process is | |
300 | called IR flattening. Such process is more complicated than IR | |
301 | rebuilding would be, but is much faster. | |
302 | ||
303 | o After IR flattening, IRA tries to assign hard registers to all | |
304 | spilled allocnos. This is impelemented by a simple and fast | |
305 | priority coloring algorithm (see function | |
306 | ira_reassign_conflict_allocnos::ira-color.c). Here new allocnos | |
307 | created during the code change pass can be assigned to hard | |
308 | registers. | |
309 | ||
310 | o At the end IRA calls the reload pass. The reload pass | |
311 | communicates with IRA through several functions in file | |
312 | ira-color.c to improve its decisions in | |
313 | ||
314 | * sharing stack slots for the spilled pseudos based on IRA info | |
315 | about pseudo-register conflicts. | |
316 | ||
317 | * reassigning hard-registers to all spilled pseudos at the end | |
318 | of each reload iteration. | |
319 | ||
320 | * choosing a better hard-register to spill based on IRA info | |
321 | about pseudo-register live ranges and the register pressure | |
322 | in places where the pseudo-register lives. | |
323 | ||
324 | IRA uses a lot of data representing the target processors. These | |
325 | data are initilized in file ira.c. | |
326 | ||
327 | If function has no loops (or the loops are ignored when | |
328 | -fira-algorithm=CB is used), we have classic Chaitin-Briggs | |
329 | coloring (only instead of separate pass of coalescing, we use hard | |
330 | register preferencing). In such case, IRA works much faster | |
331 | because many things are not made (like IR flattening, the | |
332 | spill/restore optimization, and the code change). | |
333 | ||
334 | Literature is worth to read for better understanding the code: | |
335 | ||
336 | o Preston Briggs, Keith D. Cooper, Linda Torczon. Improvements to | |
337 | Graph Coloring Register Allocation. | |
338 | ||
339 | o David Callahan, Brian Koblenz. Register allocation via | |
340 | hierarchical graph coloring. | |
341 | ||
342 | o Keith Cooper, Anshuman Dasgupta, Jason Eckhardt. Revisiting Graph | |
343 | Coloring Register Allocation: A Study of the Chaitin-Briggs and | |
344 | Callahan-Koblenz Algorithms. | |
345 | ||
346 | o Guei-Yuan Lueh, Thomas Gross, and Ali-Reza Adl-Tabatabai. Global | |
347 | Register Allocation Based on Graph Fusion. | |
348 | ||
1756cb66 VM |
349 | o Michael D. Smith and Glenn Holloway. Graph-Coloring Register |
350 | Allocation for Irregular Architectures | |
351 | ||
058e97ec VM |
352 | o Vladimir Makarov. The Integrated Register Allocator for GCC. |
353 | ||
354 | o Vladimir Makarov. The top-down register allocator for irregular | |
355 | register file architectures. | |
356 | ||
357 | */ | |
358 | ||
359 | ||
360 | #include "config.h" | |
361 | #include "system.h" | |
362 | #include "coretypes.h" | |
363 | #include "tm.h" | |
364 | #include "regs.h" | |
365 | #include "rtl.h" | |
366 | #include "tm_p.h" | |
367 | #include "target.h" | |
368 | #include "flags.h" | |
369 | #include "obstack.h" | |
370 | #include "bitmap.h" | |
371 | #include "hard-reg-set.h" | |
372 | #include "basic-block.h" | |
7a8cba34 | 373 | #include "df.h" |
058e97ec VM |
374 | #include "expr.h" |
375 | #include "recog.h" | |
376 | #include "params.h" | |
058e97ec VM |
377 | #include "tree-pass.h" |
378 | #include "output.h" | |
2af2dbdc | 379 | #include "except.h" |
058e97ec | 380 | #include "reload.h" |
718f9c0f | 381 | #include "diagnostic-core.h" |
6399c0ab | 382 | #include "function.h" |
058e97ec VM |
383 | #include "ggc.h" |
384 | #include "ira-int.h" | |
55a2c322 | 385 | #include "lra.h" |
b0c11403 | 386 | #include "dce.h" |
acf41a74 | 387 | #include "dbgcnt.h" |
058e97ec | 388 | |
afcc66c4 RS |
389 | struct target_ira default_target_ira; |
390 | struct target_ira_int default_target_ira_int; | |
391 | #if SWITCHABLE_TARGET | |
392 | struct target_ira *this_target_ira = &default_target_ira; | |
393 | struct target_ira_int *this_target_ira_int = &default_target_ira_int; | |
394 | #endif | |
395 | ||
058e97ec VM |
396 | /* A modified value of flag `-fira-verbose' used internally. */ |
397 | int internal_flag_ira_verbose; | |
398 | ||
399 | /* Dump file of the allocator if it is not NULL. */ | |
400 | FILE *ira_dump_file; | |
401 | ||
058e97ec VM |
402 | /* The number of elements in the following array. */ |
403 | int ira_spilled_reg_stack_slots_num; | |
404 | ||
405 | /* The following array contains info about spilled pseudo-registers | |
406 | stack slots used in current function so far. */ | |
407 | struct ira_spilled_reg_stack_slot *ira_spilled_reg_stack_slots; | |
408 | ||
ae2b9cb6 BS |
409 | /* Correspondingly overall cost of the allocation, overall cost before |
410 | reload, cost of the allocnos assigned to hard-registers, cost of | |
411 | the allocnos assigned to memory, cost of loads, stores and register | |
412 | move insns generated for pseudo-register live range splitting (see | |
413 | ira-emit.c). */ | |
414 | int ira_overall_cost, overall_cost_before; | |
058e97ec VM |
415 | int ira_reg_cost, ira_mem_cost; |
416 | int ira_load_cost, ira_store_cost, ira_shuffle_cost; | |
417 | int ira_move_loops_num, ira_additional_jumps_num; | |
418 | ||
2af2dbdc VM |
419 | /* All registers that can be eliminated. */ |
420 | ||
421 | HARD_REG_SET eliminable_regset; | |
422 | ||
058e97ec VM |
423 | /* Temporary hard reg set used for a different calculation. */ |
424 | static HARD_REG_SET temp_hard_regset; | |
425 | ||
e80ccebc RS |
426 | #define last_mode_for_init_move_cost \ |
427 | (this_target_ira_int->x_last_mode_for_init_move_cost) | |
058e97ec VM |
428 | \f |
429 | ||
430 | /* The function sets up the map IRA_REG_MODE_HARD_REGSET. */ | |
431 | static void | |
432 | setup_reg_mode_hard_regset (void) | |
433 | { | |
434 | int i, m, hard_regno; | |
435 | ||
436 | for (m = 0; m < NUM_MACHINE_MODES; m++) | |
437 | for (hard_regno = 0; hard_regno < FIRST_PSEUDO_REGISTER; hard_regno++) | |
438 | { | |
439 | CLEAR_HARD_REG_SET (ira_reg_mode_hard_regset[hard_regno][m]); | |
440 | for (i = hard_regno_nregs[hard_regno][m] - 1; i >= 0; i--) | |
441 | if (hard_regno + i < FIRST_PSEUDO_REGISTER) | |
442 | SET_HARD_REG_BIT (ira_reg_mode_hard_regset[hard_regno][m], | |
443 | hard_regno + i); | |
444 | } | |
445 | } | |
446 | ||
447 | \f | |
afcc66c4 RS |
448 | #define no_unit_alloc_regs \ |
449 | (this_target_ira_int->x_no_unit_alloc_regs) | |
058e97ec VM |
450 | |
451 | /* The function sets up the three arrays declared above. */ | |
452 | static void | |
453 | setup_class_hard_regs (void) | |
454 | { | |
455 | int cl, i, hard_regno, n; | |
456 | HARD_REG_SET processed_hard_reg_set; | |
457 | ||
458 | ira_assert (SHRT_MAX >= FIRST_PSEUDO_REGISTER); | |
058e97ec VM |
459 | for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) |
460 | { | |
461 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); | |
462 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
463 | CLEAR_HARD_REG_SET (processed_hard_reg_set); | |
7db7ed3c | 464 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
0583835c | 465 | { |
854edfcd VM |
466 | ira_non_ordered_class_hard_regs[cl][i] = -1; |
467 | ira_class_hard_reg_index[cl][i] = -1; | |
0583835c | 468 | } |
058e97ec VM |
469 | for (n = 0, i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
470 | { | |
471 | #ifdef REG_ALLOC_ORDER | |
472 | hard_regno = reg_alloc_order[i]; | |
473 | #else | |
474 | hard_regno = i; | |
b8698a0f | 475 | #endif |
058e97ec VM |
476 | if (TEST_HARD_REG_BIT (processed_hard_reg_set, hard_regno)) |
477 | continue; | |
478 | SET_HARD_REG_BIT (processed_hard_reg_set, hard_regno); | |
479 | if (! TEST_HARD_REG_BIT (temp_hard_regset, hard_regno)) | |
480 | ira_class_hard_reg_index[cl][hard_regno] = -1; | |
481 | else | |
482 | { | |
483 | ira_class_hard_reg_index[cl][hard_regno] = n; | |
484 | ira_class_hard_regs[cl][n++] = hard_regno; | |
485 | } | |
486 | } | |
487 | ira_class_hard_regs_num[cl] = n; | |
0583835c VM |
488 | for (n = 0, i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
489 | if (TEST_HARD_REG_BIT (temp_hard_regset, i)) | |
490 | ira_non_ordered_class_hard_regs[cl][n++] = i; | |
491 | ira_assert (ira_class_hard_regs_num[cl] == n); | |
058e97ec VM |
492 | } |
493 | } | |
494 | ||
058e97ec VM |
495 | /* Set up global variables defining info about hard registers for the |
496 | allocation. These depend on USE_HARD_FRAME_P whose TRUE value means | |
497 | that we can use the hard frame pointer for the allocation. */ | |
498 | static void | |
499 | setup_alloc_regs (bool use_hard_frame_p) | |
500 | { | |
5a733826 BS |
501 | #ifdef ADJUST_REG_ALLOC_ORDER |
502 | ADJUST_REG_ALLOC_ORDER; | |
503 | #endif | |
058e97ec VM |
504 | COPY_HARD_REG_SET (no_unit_alloc_regs, fixed_reg_set); |
505 | if (! use_hard_frame_p) | |
506 | SET_HARD_REG_BIT (no_unit_alloc_regs, HARD_FRAME_POINTER_REGNUM); | |
507 | setup_class_hard_regs (); | |
058e97ec VM |
508 | } |
509 | ||
510 | \f | |
511 | ||
1756cb66 VM |
512 | #define alloc_reg_class_subclasses \ |
513 | (this_target_ira_int->x_alloc_reg_class_subclasses) | |
514 | ||
515 | /* Initialize the table of subclasses of each reg class. */ | |
516 | static void | |
517 | setup_reg_subclasses (void) | |
518 | { | |
519 | int i, j; | |
520 | HARD_REG_SET temp_hard_regset2; | |
521 | ||
522 | for (i = 0; i < N_REG_CLASSES; i++) | |
523 | for (j = 0; j < N_REG_CLASSES; j++) | |
524 | alloc_reg_class_subclasses[i][j] = LIM_REG_CLASSES; | |
525 | ||
526 | for (i = 0; i < N_REG_CLASSES; i++) | |
527 | { | |
528 | if (i == (int) NO_REGS) | |
529 | continue; | |
530 | ||
531 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[i]); | |
532 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
533 | if (hard_reg_set_empty_p (temp_hard_regset)) | |
534 | continue; | |
535 | for (j = 0; j < N_REG_CLASSES; j++) | |
536 | if (i != j) | |
537 | { | |
538 | enum reg_class *p; | |
539 | ||
540 | COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[j]); | |
541 | AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs); | |
542 | if (! hard_reg_set_subset_p (temp_hard_regset, | |
543 | temp_hard_regset2)) | |
544 | continue; | |
545 | p = &alloc_reg_class_subclasses[j][0]; | |
546 | while (*p != LIM_REG_CLASSES) p++; | |
547 | *p = (enum reg_class) i; | |
548 | } | |
549 | } | |
550 | } | |
551 | ||
552 | \f | |
553 | ||
554 | /* Set up IRA_MEMORY_MOVE_COST and IRA_MAX_MEMORY_MOVE_COST. */ | |
058e97ec VM |
555 | static void |
556 | setup_class_subset_and_memory_move_costs (void) | |
557 | { | |
1756cb66 | 558 | int cl, cl2, mode, cost; |
058e97ec VM |
559 | HARD_REG_SET temp_hard_regset2; |
560 | ||
561 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
562 | ira_memory_move_cost[mode][NO_REGS][0] | |
563 | = ira_memory_move_cost[mode][NO_REGS][1] = SHRT_MAX; | |
564 | for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) | |
565 | { | |
566 | if (cl != (int) NO_REGS) | |
567 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
568 | { | |
1756cb66 VM |
569 | ira_max_memory_move_cost[mode][cl][0] |
570 | = ira_memory_move_cost[mode][cl][0] | |
571 | = memory_move_cost ((enum machine_mode) mode, | |
6f76a878 | 572 | (reg_class_t) cl, false); |
1756cb66 VM |
573 | ira_max_memory_move_cost[mode][cl][1] |
574 | = ira_memory_move_cost[mode][cl][1] | |
575 | = memory_move_cost ((enum machine_mode) mode, | |
6f76a878 | 576 | (reg_class_t) cl, true); |
058e97ec VM |
577 | /* Costs for NO_REGS are used in cost calculation on the |
578 | 1st pass when the preferred register classes are not | |
579 | known yet. In this case we take the best scenario. */ | |
580 | if (ira_memory_move_cost[mode][NO_REGS][0] | |
581 | > ira_memory_move_cost[mode][cl][0]) | |
1756cb66 VM |
582 | ira_max_memory_move_cost[mode][NO_REGS][0] |
583 | = ira_memory_move_cost[mode][NO_REGS][0] | |
058e97ec VM |
584 | = ira_memory_move_cost[mode][cl][0]; |
585 | if (ira_memory_move_cost[mode][NO_REGS][1] | |
586 | > ira_memory_move_cost[mode][cl][1]) | |
1756cb66 VM |
587 | ira_max_memory_move_cost[mode][NO_REGS][1] |
588 | = ira_memory_move_cost[mode][NO_REGS][1] | |
058e97ec VM |
589 | = ira_memory_move_cost[mode][cl][1]; |
590 | } | |
058e97ec | 591 | } |
1756cb66 VM |
592 | for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) |
593 | for (cl2 = (int) N_REG_CLASSES - 1; cl2 >= 0; cl2--) | |
594 | { | |
595 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); | |
596 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
597 | COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl2]); | |
598 | AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs); | |
599 | ira_class_subset_p[cl][cl2] | |
600 | = hard_reg_set_subset_p (temp_hard_regset, temp_hard_regset2); | |
601 | if (! hard_reg_set_empty_p (temp_hard_regset2) | |
602 | && hard_reg_set_subset_p (reg_class_contents[cl2], | |
603 | reg_class_contents[cl])) | |
604 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
605 | { | |
606 | cost = ira_memory_move_cost[mode][cl2][0]; | |
607 | if (cost > ira_max_memory_move_cost[mode][cl][0]) | |
608 | ira_max_memory_move_cost[mode][cl][0] = cost; | |
609 | cost = ira_memory_move_cost[mode][cl2][1]; | |
610 | if (cost > ira_max_memory_move_cost[mode][cl][1]) | |
611 | ira_max_memory_move_cost[mode][cl][1] = cost; | |
612 | } | |
613 | } | |
614 | for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) | |
615 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
616 | { | |
617 | ira_memory_move_cost[mode][cl][0] | |
618 | = ira_max_memory_move_cost[mode][cl][0]; | |
619 | ira_memory_move_cost[mode][cl][1] | |
620 | = ira_max_memory_move_cost[mode][cl][1]; | |
621 | } | |
622 | setup_reg_subclasses (); | |
058e97ec VM |
623 | } |
624 | ||
625 | \f | |
626 | ||
627 | /* Define the following macro if allocation through malloc if | |
628 | preferable. */ | |
629 | #define IRA_NO_OBSTACK | |
630 | ||
631 | #ifndef IRA_NO_OBSTACK | |
632 | /* Obstack used for storing all dynamic data (except bitmaps) of the | |
633 | IRA. */ | |
634 | static struct obstack ira_obstack; | |
635 | #endif | |
636 | ||
637 | /* Obstack used for storing all bitmaps of the IRA. */ | |
638 | static struct bitmap_obstack ira_bitmap_obstack; | |
639 | ||
640 | /* Allocate memory of size LEN for IRA data. */ | |
641 | void * | |
642 | ira_allocate (size_t len) | |
643 | { | |
644 | void *res; | |
645 | ||
646 | #ifndef IRA_NO_OBSTACK | |
647 | res = obstack_alloc (&ira_obstack, len); | |
648 | #else | |
649 | res = xmalloc (len); | |
650 | #endif | |
651 | return res; | |
652 | } | |
653 | ||
058e97ec VM |
654 | /* Free memory ADDR allocated for IRA data. */ |
655 | void | |
656 | ira_free (void *addr ATTRIBUTE_UNUSED) | |
657 | { | |
658 | #ifndef IRA_NO_OBSTACK | |
659 | /* do nothing */ | |
660 | #else | |
661 | free (addr); | |
662 | #endif | |
663 | } | |
664 | ||
665 | ||
666 | /* Allocate and returns bitmap for IRA. */ | |
667 | bitmap | |
668 | ira_allocate_bitmap (void) | |
669 | { | |
670 | return BITMAP_ALLOC (&ira_bitmap_obstack); | |
671 | } | |
672 | ||
673 | /* Free bitmap B allocated for IRA. */ | |
674 | void | |
675 | ira_free_bitmap (bitmap b ATTRIBUTE_UNUSED) | |
676 | { | |
677 | /* do nothing */ | |
678 | } | |
679 | ||
680 | \f | |
681 | ||
682 | /* Output information about allocation of all allocnos (except for | |
683 | caps) into file F. */ | |
684 | void | |
685 | ira_print_disposition (FILE *f) | |
686 | { | |
687 | int i, n, max_regno; | |
688 | ira_allocno_t a; | |
689 | basic_block bb; | |
690 | ||
691 | fprintf (f, "Disposition:"); | |
692 | max_regno = max_reg_num (); | |
693 | for (n = 0, i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
694 | for (a = ira_regno_allocno_map[i]; | |
695 | a != NULL; | |
696 | a = ALLOCNO_NEXT_REGNO_ALLOCNO (a)) | |
697 | { | |
698 | if (n % 4 == 0) | |
699 | fprintf (f, "\n"); | |
700 | n++; | |
701 | fprintf (f, " %4d:r%-4d", ALLOCNO_NUM (a), ALLOCNO_REGNO (a)); | |
702 | if ((bb = ALLOCNO_LOOP_TREE_NODE (a)->bb) != NULL) | |
703 | fprintf (f, "b%-3d", bb->index); | |
704 | else | |
2608d841 | 705 | fprintf (f, "l%-3d", ALLOCNO_LOOP_TREE_NODE (a)->loop_num); |
058e97ec VM |
706 | if (ALLOCNO_HARD_REGNO (a) >= 0) |
707 | fprintf (f, " %3d", ALLOCNO_HARD_REGNO (a)); | |
708 | else | |
709 | fprintf (f, " mem"); | |
710 | } | |
711 | fprintf (f, "\n"); | |
712 | } | |
713 | ||
714 | /* Outputs information about allocation of all allocnos into | |
715 | stderr. */ | |
716 | void | |
717 | ira_debug_disposition (void) | |
718 | { | |
719 | ira_print_disposition (stderr); | |
720 | } | |
721 | ||
722 | \f | |
058e97ec | 723 | |
1756cb66 VM |
724 | /* Set up ira_stack_reg_pressure_class which is the biggest pressure |
725 | register class containing stack registers or NO_REGS if there are | |
726 | no stack registers. To find this class, we iterate through all | |
727 | register pressure classes and choose the first register pressure | |
728 | class containing all the stack registers and having the biggest | |
729 | size. */ | |
fe82cdfb | 730 | static void |
1756cb66 VM |
731 | setup_stack_reg_pressure_class (void) |
732 | { | |
733 | ira_stack_reg_pressure_class = NO_REGS; | |
734 | #ifdef STACK_REGS | |
735 | { | |
736 | int i, best, size; | |
737 | enum reg_class cl; | |
738 | HARD_REG_SET temp_hard_regset2; | |
739 | ||
740 | CLEAR_HARD_REG_SET (temp_hard_regset); | |
741 | for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++) | |
742 | SET_HARD_REG_BIT (temp_hard_regset, i); | |
743 | best = 0; | |
744 | for (i = 0; i < ira_pressure_classes_num; i++) | |
745 | { | |
746 | cl = ira_pressure_classes[i]; | |
747 | COPY_HARD_REG_SET (temp_hard_regset2, temp_hard_regset); | |
748 | AND_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl]); | |
749 | size = hard_reg_set_size (temp_hard_regset2); | |
750 | if (best < size) | |
751 | { | |
752 | best = size; | |
753 | ira_stack_reg_pressure_class = cl; | |
754 | } | |
755 | } | |
756 | } | |
757 | #endif | |
758 | } | |
759 | ||
760 | /* Find pressure classes which are register classes for which we | |
761 | calculate register pressure in IRA, register pressure sensitive | |
762 | insn scheduling, and register pressure sensitive loop invariant | |
763 | motion. | |
764 | ||
765 | To make register pressure calculation easy, we always use | |
766 | non-intersected register pressure classes. A move of hard | |
767 | registers from one register pressure class is not more expensive | |
768 | than load and store of the hard registers. Most likely an allocno | |
769 | class will be a subset of a register pressure class and in many | |
770 | cases a register pressure class. That makes usage of register | |
771 | pressure classes a good approximation to find a high register | |
772 | pressure. */ | |
773 | static void | |
774 | setup_pressure_classes (void) | |
058e97ec | 775 | { |
1756cb66 VM |
776 | int cost, i, n, curr; |
777 | int cl, cl2; | |
778 | enum reg_class pressure_classes[N_REG_CLASSES]; | |
779 | int m; | |
058e97ec | 780 | HARD_REG_SET temp_hard_regset2; |
1756cb66 | 781 | bool insert_p; |
058e97ec | 782 | |
1756cb66 VM |
783 | n = 0; |
784 | for (cl = 0; cl < N_REG_CLASSES; cl++) | |
058e97ec | 785 | { |
f508f827 | 786 | if (ira_class_hard_regs_num[cl] == 0) |
058e97ec | 787 | continue; |
f508f827 | 788 | if (ira_class_hard_regs_num[cl] != 1 |
574e418a VM |
789 | /* A register class without subclasses may contain a few |
790 | hard registers and movement between them is costly | |
791 | (e.g. SPARC FPCC registers). We still should consider it | |
792 | as a candidate for a pressure class. */ | |
af2b97c4 | 793 | && alloc_reg_class_subclasses[cl][0] < cl) |
1756cb66 | 794 | { |
113a5be6 VM |
795 | /* Check that the moves between any hard registers of the |
796 | current class are not more expensive for a legal mode | |
797 | than load/store of the hard registers of the current | |
798 | class. Such class is a potential candidate to be a | |
799 | register pressure class. */ | |
800 | for (m = 0; m < NUM_MACHINE_MODES; m++) | |
801 | { | |
802 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); | |
803 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
804 | AND_COMPL_HARD_REG_SET (temp_hard_regset, | |
805 | ira_prohibited_class_mode_regs[cl][m]); | |
806 | if (hard_reg_set_empty_p (temp_hard_regset)) | |
807 | continue; | |
808 | ira_init_register_move_cost_if_necessary ((enum machine_mode) m); | |
809 | cost = ira_register_move_cost[m][cl][cl]; | |
810 | if (cost <= ira_max_memory_move_cost[m][cl][1] | |
811 | || cost <= ira_max_memory_move_cost[m][cl][0]) | |
812 | break; | |
813 | } | |
814 | if (m >= NUM_MACHINE_MODES) | |
1756cb66 | 815 | continue; |
1756cb66 | 816 | } |
1756cb66 VM |
817 | curr = 0; |
818 | insert_p = true; | |
819 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); | |
820 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
821 | /* Remove so far added pressure classes which are subset of the | |
822 | current candidate class. Prefer GENERAL_REGS as a pressure | |
823 | register class to another class containing the same | |
824 | allocatable hard registers. We do this because machine | |
825 | dependent cost hooks might give wrong costs for the latter | |
826 | class but always give the right cost for the former class | |
827 | (GENERAL_REGS). */ | |
828 | for (i = 0; i < n; i++) | |
829 | { | |
830 | cl2 = pressure_classes[i]; | |
831 | COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl2]); | |
832 | AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs); | |
833 | if (hard_reg_set_subset_p (temp_hard_regset, temp_hard_regset2) | |
834 | && (! hard_reg_set_equal_p (temp_hard_regset, temp_hard_regset2) | |
835 | || cl2 == (int) GENERAL_REGS)) | |
836 | { | |
837 | pressure_classes[curr++] = (enum reg_class) cl2; | |
838 | insert_p = false; | |
058e97ec | 839 | continue; |
1756cb66 VM |
840 | } |
841 | if (hard_reg_set_subset_p (temp_hard_regset2, temp_hard_regset) | |
842 | && (! hard_reg_set_equal_p (temp_hard_regset2, temp_hard_regset) | |
843 | || cl == (int) GENERAL_REGS)) | |
844 | continue; | |
113a5be6 VM |
845 | if (hard_reg_set_equal_p (temp_hard_regset2, temp_hard_regset)) |
846 | insert_p = false; | |
1756cb66 VM |
847 | pressure_classes[curr++] = (enum reg_class) cl2; |
848 | } | |
849 | /* If the current candidate is a subset of a so far added | |
850 | pressure class, don't add it to the list of the pressure | |
851 | classes. */ | |
852 | if (insert_p) | |
853 | pressure_classes[curr++] = (enum reg_class) cl; | |
854 | n = curr; | |
fe82cdfb | 855 | } |
1756cb66 | 856 | #ifdef ENABLE_IRA_CHECKING |
113a5be6 VM |
857 | { |
858 | HARD_REG_SET ignore_hard_regs; | |
859 | ||
860 | /* Check pressure classes correctness: here we check that hard | |
861 | registers from all register pressure classes contains all hard | |
862 | registers available for the allocation. */ | |
863 | CLEAR_HARD_REG_SET (temp_hard_regset); | |
864 | CLEAR_HARD_REG_SET (temp_hard_regset2); | |
865 | COPY_HARD_REG_SET (ignore_hard_regs, no_unit_alloc_regs); | |
866 | for (cl = 0; cl < LIM_REG_CLASSES; cl++) | |
867 | { | |
868 | /* For some targets (like MIPS with MD_REGS), there are some | |
869 | classes with hard registers available for allocation but | |
870 | not able to hold value of any mode. */ | |
871 | for (m = 0; m < NUM_MACHINE_MODES; m++) | |
872 | if (contains_reg_of_mode[cl][m]) | |
873 | break; | |
874 | if (m >= NUM_MACHINE_MODES) | |
875 | { | |
876 | IOR_HARD_REG_SET (ignore_hard_regs, reg_class_contents[cl]); | |
877 | continue; | |
878 | } | |
879 | for (i = 0; i < n; i++) | |
880 | if ((int) pressure_classes[i] == cl) | |
881 | break; | |
882 | IOR_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl]); | |
883 | if (i < n) | |
884 | IOR_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); | |
885 | } | |
886 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
887 | /* Some targets (like SPARC with ICC reg) have alocatable regs | |
888 | for which no reg class is defined. */ | |
889 | if (REGNO_REG_CLASS (i) == NO_REGS) | |
890 | SET_HARD_REG_BIT (ignore_hard_regs, i); | |
891 | AND_COMPL_HARD_REG_SET (temp_hard_regset, ignore_hard_regs); | |
892 | AND_COMPL_HARD_REG_SET (temp_hard_regset2, ignore_hard_regs); | |
893 | ira_assert (hard_reg_set_subset_p (temp_hard_regset2, temp_hard_regset)); | |
894 | } | |
1756cb66 VM |
895 | #endif |
896 | ira_pressure_classes_num = 0; | |
897 | for (i = 0; i < n; i++) | |
898 | { | |
899 | cl = (int) pressure_classes[i]; | |
900 | ira_reg_pressure_class_p[cl] = true; | |
901 | ira_pressure_classes[ira_pressure_classes_num++] = (enum reg_class) cl; | |
902 | } | |
903 | setup_stack_reg_pressure_class (); | |
058e97ec VM |
904 | } |
905 | ||
165f639c VM |
906 | /* Set up IRA_UNIFORM_CLASS_P. Uniform class is a register class |
907 | whose register move cost between any registers of the class is the | |
908 | same as for all its subclasses. We use the data to speed up the | |
909 | 2nd pass of calculations of allocno costs. */ | |
910 | static void | |
911 | setup_uniform_class_p (void) | |
912 | { | |
913 | int i, cl, cl2, m; | |
914 | ||
915 | for (cl = 0; cl < N_REG_CLASSES; cl++) | |
916 | { | |
917 | ira_uniform_class_p[cl] = false; | |
918 | if (ira_class_hard_regs_num[cl] == 0) | |
919 | continue; | |
920 | /* We can not use alloc_reg_class_subclasses here because move | |
921 | cost hooks does not take into account that some registers are | |
922 | unavailable for the subtarget. E.g. for i686, INT_SSE_REGS | |
923 | is element of alloc_reg_class_subclasses for GENERAL_REGS | |
924 | because SSE regs are unavailable. */ | |
925 | for (i = 0; (cl2 = reg_class_subclasses[cl][i]) != LIM_REG_CLASSES; i++) | |
926 | { | |
927 | if (ira_class_hard_regs_num[cl2] == 0) | |
928 | continue; | |
929 | for (m = 0; m < NUM_MACHINE_MODES; m++) | |
930 | if (contains_reg_of_mode[cl][m] && contains_reg_of_mode[cl2][m]) | |
931 | { | |
932 | ira_init_register_move_cost_if_necessary ((enum machine_mode) m); | |
933 | if (ira_register_move_cost[m][cl][cl] | |
934 | != ira_register_move_cost[m][cl2][cl2]) | |
935 | break; | |
936 | } | |
937 | if (m < NUM_MACHINE_MODES) | |
938 | break; | |
939 | } | |
940 | if (cl2 == LIM_REG_CLASSES) | |
941 | ira_uniform_class_p[cl] = true; | |
942 | } | |
943 | } | |
944 | ||
1756cb66 VM |
945 | /* Set up IRA_ALLOCNO_CLASSES, IRA_ALLOCNO_CLASSES_NUM, |
946 | IRA_IMPORTANT_CLASSES, and IRA_IMPORTANT_CLASSES_NUM. | |
947 | ||
948 | Target may have many subtargets and not all target hard regiters can | |
949 | be used for allocation, e.g. x86 port in 32-bit mode can not use | |
950 | hard registers introduced in x86-64 like r8-r15). Some classes | |
951 | might have the same allocatable hard registers, e.g. INDEX_REGS | |
952 | and GENERAL_REGS in x86 port in 32-bit mode. To decrease different | |
953 | calculations efforts we introduce allocno classes which contain | |
954 | unique non-empty sets of allocatable hard-registers. | |
955 | ||
956 | Pseudo class cost calculation in ira-costs.c is very expensive. | |
957 | Therefore we are trying to decrease number of classes involved in | |
958 | such calculation. Register classes used in the cost calculation | |
959 | are called important classes. They are allocno classes and other | |
960 | non-empty classes whose allocatable hard register sets are inside | |
961 | of an allocno class hard register set. From the first sight, it | |
962 | looks like that they are just allocno classes. It is not true. In | |
963 | example of x86-port in 32-bit mode, allocno classes will contain | |
964 | GENERAL_REGS but not LEGACY_REGS (because allocatable hard | |
965 | registers are the same for the both classes). The important | |
966 | classes will contain GENERAL_REGS and LEGACY_REGS. It is done | |
967 | because a machine description insn constraint may refers for | |
968 | LEGACY_REGS and code in ira-costs.c is mostly base on investigation | |
969 | of the insn constraints. */ | |
058e97ec | 970 | static void |
1756cb66 | 971 | setup_allocno_and_important_classes (void) |
058e97ec | 972 | { |
32e8bb8e | 973 | int i, j, n, cl; |
db1a8d98 | 974 | bool set_p; |
058e97ec | 975 | HARD_REG_SET temp_hard_regset2; |
7db7ed3c VM |
976 | static enum reg_class classes[LIM_REG_CLASSES + 1]; |
977 | ||
1756cb66 VM |
978 | n = 0; |
979 | /* Collect classes which contain unique sets of allocatable hard | |
980 | registers. Prefer GENERAL_REGS to other classes containing the | |
981 | same set of hard registers. */ | |
a58dfa49 | 982 | for (i = 0; i < LIM_REG_CLASSES; i++) |
99710245 | 983 | { |
1756cb66 VM |
984 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[i]); |
985 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
986 | for (j = 0; j < n; j++) | |
7db7ed3c | 987 | { |
1756cb66 VM |
988 | cl = classes[j]; |
989 | COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl]); | |
990 | AND_COMPL_HARD_REG_SET (temp_hard_regset2, | |
991 | no_unit_alloc_regs); | |
992 | if (hard_reg_set_equal_p (temp_hard_regset, | |
993 | temp_hard_regset2)) | |
994 | break; | |
7db7ed3c | 995 | } |
1756cb66 VM |
996 | if (j >= n) |
997 | classes[n++] = (enum reg_class) i; | |
998 | else if (i == GENERAL_REGS) | |
999 | /* Prefer general regs. For i386 example, it means that | |
1000 | we prefer GENERAL_REGS over INDEX_REGS or LEGACY_REGS | |
1001 | (all of them consists of the same available hard | |
1002 | registers). */ | |
1003 | classes[j] = (enum reg_class) i; | |
7db7ed3c | 1004 | } |
1756cb66 | 1005 | classes[n] = LIM_REG_CLASSES; |
058e97ec | 1006 | |
1756cb66 VM |
1007 | /* Set up classes which can be used for allocnos as classes |
1008 | conatining non-empty unique sets of allocatable hard | |
1009 | registers. */ | |
1010 | ira_allocno_classes_num = 0; | |
058e97ec | 1011 | for (i = 0; (cl = classes[i]) != LIM_REG_CLASSES; i++) |
3e575fe2 | 1012 | if (ira_class_hard_regs_num[cl] > 0) |
1756cb66 | 1013 | ira_allocno_classes[ira_allocno_classes_num++] = (enum reg_class) cl; |
058e97ec | 1014 | ira_important_classes_num = 0; |
1756cb66 VM |
1015 | /* Add non-allocno classes containing to non-empty set of |
1016 | allocatable hard regs. */ | |
058e97ec | 1017 | for (cl = 0; cl < N_REG_CLASSES; cl++) |
3e575fe2 RS |
1018 | if (ira_class_hard_regs_num[cl] > 0) |
1019 | { | |
1020 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); | |
1021 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
1022 | set_p = false; | |
1023 | for (j = 0; j < ira_allocno_classes_num; j++) | |
1024 | { | |
1025 | COPY_HARD_REG_SET (temp_hard_regset2, | |
1026 | reg_class_contents[ira_allocno_classes[j]]); | |
1027 | AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs); | |
1028 | if ((enum reg_class) cl == ira_allocno_classes[j]) | |
1029 | break; | |
1030 | else if (hard_reg_set_subset_p (temp_hard_regset, | |
1031 | temp_hard_regset2)) | |
1032 | set_p = true; | |
1033 | } | |
1034 | if (set_p && j >= ira_allocno_classes_num) | |
1035 | ira_important_classes[ira_important_classes_num++] | |
1036 | = (enum reg_class) cl; | |
1037 | } | |
1756cb66 VM |
1038 | /* Now add allocno classes to the important classes. */ |
1039 | for (j = 0; j < ira_allocno_classes_num; j++) | |
db1a8d98 | 1040 | ira_important_classes[ira_important_classes_num++] |
1756cb66 VM |
1041 | = ira_allocno_classes[j]; |
1042 | for (cl = 0; cl < N_REG_CLASSES; cl++) | |
1043 | { | |
1044 | ira_reg_allocno_class_p[cl] = false; | |
1045 | ira_reg_pressure_class_p[cl] = false; | |
1046 | } | |
1047 | for (j = 0; j < ira_allocno_classes_num; j++) | |
1048 | ira_reg_allocno_class_p[ira_allocno_classes[j]] = true; | |
1049 | setup_pressure_classes (); | |
165f639c | 1050 | setup_uniform_class_p (); |
058e97ec | 1051 | } |
058e97ec | 1052 | |
1756cb66 VM |
1053 | /* Setup translation in CLASS_TRANSLATE of all classes into a class |
1054 | given by array CLASSES of length CLASSES_NUM. The function is used | |
1055 | make translation any reg class to an allocno class or to an | |
1056 | pressure class. This translation is necessary for some | |
1057 | calculations when we can use only allocno or pressure classes and | |
1058 | such translation represents an approximate representation of all | |
1059 | classes. | |
1060 | ||
1061 | The translation in case when allocatable hard register set of a | |
1062 | given class is subset of allocatable hard register set of a class | |
1063 | in CLASSES is pretty simple. We use smallest classes from CLASSES | |
1064 | containing a given class. If allocatable hard register set of a | |
1065 | given class is not a subset of any corresponding set of a class | |
1066 | from CLASSES, we use the cheapest (with load/store point of view) | |
1067 | class from CLASSES whose set intersects with given class set */ | |
058e97ec | 1068 | static void |
1756cb66 VM |
1069 | setup_class_translate_array (enum reg_class *class_translate, |
1070 | int classes_num, enum reg_class *classes) | |
058e97ec | 1071 | { |
32e8bb8e | 1072 | int cl, mode; |
1756cb66 | 1073 | enum reg_class aclass, best_class, *cl_ptr; |
058e97ec VM |
1074 | int i, cost, min_cost, best_cost; |
1075 | ||
1076 | for (cl = 0; cl < N_REG_CLASSES; cl++) | |
1756cb66 | 1077 | class_translate[cl] = NO_REGS; |
b8698a0f | 1078 | |
1756cb66 | 1079 | for (i = 0; i < classes_num; i++) |
058e97ec | 1080 | { |
1756cb66 VM |
1081 | aclass = classes[i]; |
1082 | for (cl_ptr = &alloc_reg_class_subclasses[aclass][0]; | |
1083 | (cl = *cl_ptr) != LIM_REG_CLASSES; | |
1084 | cl_ptr++) | |
1085 | if (class_translate[cl] == NO_REGS) | |
1086 | class_translate[cl] = aclass; | |
1087 | class_translate[aclass] = aclass; | |
058e97ec | 1088 | } |
1756cb66 VM |
1089 | /* For classes which are not fully covered by one of given classes |
1090 | (in other words covered by more one given class), use the | |
1091 | cheapest class. */ | |
058e97ec VM |
1092 | for (cl = 0; cl < N_REG_CLASSES; cl++) |
1093 | { | |
1756cb66 | 1094 | if (cl == NO_REGS || class_translate[cl] != NO_REGS) |
058e97ec VM |
1095 | continue; |
1096 | best_class = NO_REGS; | |
1097 | best_cost = INT_MAX; | |
1756cb66 | 1098 | for (i = 0; i < classes_num; i++) |
058e97ec | 1099 | { |
1756cb66 | 1100 | aclass = classes[i]; |
058e97ec | 1101 | COPY_HARD_REG_SET (temp_hard_regset, |
1756cb66 | 1102 | reg_class_contents[aclass]); |
058e97ec VM |
1103 | AND_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); |
1104 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
4f341ea0 | 1105 | if (! hard_reg_set_empty_p (temp_hard_regset)) |
058e97ec VM |
1106 | { |
1107 | min_cost = INT_MAX; | |
1108 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
1109 | { | |
1110 | cost = (ira_memory_move_cost[mode][cl][0] | |
1111 | + ira_memory_move_cost[mode][cl][1]); | |
1112 | if (min_cost > cost) | |
1113 | min_cost = cost; | |
1114 | } | |
1115 | if (best_class == NO_REGS || best_cost > min_cost) | |
1116 | { | |
1756cb66 | 1117 | best_class = aclass; |
058e97ec VM |
1118 | best_cost = min_cost; |
1119 | } | |
1120 | } | |
1121 | } | |
1756cb66 | 1122 | class_translate[cl] = best_class; |
058e97ec VM |
1123 | } |
1124 | } | |
058e97ec | 1125 | |
1756cb66 VM |
1126 | /* Set up array IRA_ALLOCNO_CLASS_TRANSLATE and |
1127 | IRA_PRESSURE_CLASS_TRANSLATE. */ | |
1128 | static void | |
1129 | setup_class_translate (void) | |
1130 | { | |
1131 | setup_class_translate_array (ira_allocno_class_translate, | |
1132 | ira_allocno_classes_num, ira_allocno_classes); | |
1133 | setup_class_translate_array (ira_pressure_class_translate, | |
1134 | ira_pressure_classes_num, ira_pressure_classes); | |
1135 | } | |
1136 | ||
1137 | /* Order numbers of allocno classes in original target allocno class | |
1138 | array, -1 for non-allocno classes. */ | |
1139 | static int allocno_class_order[N_REG_CLASSES]; | |
db1a8d98 VM |
1140 | |
1141 | /* The function used to sort the important classes. */ | |
1142 | static int | |
1143 | comp_reg_classes_func (const void *v1p, const void *v2p) | |
1144 | { | |
1145 | enum reg_class cl1 = *(const enum reg_class *) v1p; | |
1146 | enum reg_class cl2 = *(const enum reg_class *) v2p; | |
1756cb66 | 1147 | enum reg_class tcl1, tcl2; |
db1a8d98 VM |
1148 | int diff; |
1149 | ||
1756cb66 VM |
1150 | tcl1 = ira_allocno_class_translate[cl1]; |
1151 | tcl2 = ira_allocno_class_translate[cl2]; | |
1152 | if (tcl1 != NO_REGS && tcl2 != NO_REGS | |
1153 | && (diff = allocno_class_order[tcl1] - allocno_class_order[tcl2]) != 0) | |
db1a8d98 VM |
1154 | return diff; |
1155 | return (int) cl1 - (int) cl2; | |
1156 | } | |
1157 | ||
1756cb66 VM |
1158 | /* For correct work of function setup_reg_class_relation we need to |
1159 | reorder important classes according to the order of their allocno | |
1160 | classes. It places important classes containing the same | |
1161 | allocatable hard register set adjacent to each other and allocno | |
1162 | class with the allocatable hard register set right after the other | |
1163 | important classes with the same set. | |
1164 | ||
1165 | In example from comments of function | |
1166 | setup_allocno_and_important_classes, it places LEGACY_REGS and | |
1167 | GENERAL_REGS close to each other and GENERAL_REGS is after | |
1168 | LEGACY_REGS. */ | |
db1a8d98 VM |
1169 | static void |
1170 | reorder_important_classes (void) | |
1171 | { | |
1172 | int i; | |
1173 | ||
1174 | for (i = 0; i < N_REG_CLASSES; i++) | |
1756cb66 VM |
1175 | allocno_class_order[i] = -1; |
1176 | for (i = 0; i < ira_allocno_classes_num; i++) | |
1177 | allocno_class_order[ira_allocno_classes[i]] = i; | |
db1a8d98 VM |
1178 | qsort (ira_important_classes, ira_important_classes_num, |
1179 | sizeof (enum reg_class), comp_reg_classes_func); | |
1756cb66 VM |
1180 | for (i = 0; i < ira_important_classes_num; i++) |
1181 | ira_important_class_nums[ira_important_classes[i]] = i; | |
db1a8d98 VM |
1182 | } |
1183 | ||
1756cb66 VM |
1184 | /* Set up IRA_REG_CLASS_SUBUNION, IRA_REG_CLASS_SUPERUNION, |
1185 | IRA_REG_CLASS_SUPER_CLASSES, IRA_REG_CLASSES_INTERSECT, and | |
1186 | IRA_REG_CLASSES_INTERSECT_P. For the meaning of the relations, | |
1187 | please see corresponding comments in ira-int.h. */ | |
058e97ec | 1188 | static void |
7db7ed3c | 1189 | setup_reg_class_relations (void) |
058e97ec VM |
1190 | { |
1191 | int i, cl1, cl2, cl3; | |
1192 | HARD_REG_SET intersection_set, union_set, temp_set2; | |
7db7ed3c | 1193 | bool important_class_p[N_REG_CLASSES]; |
058e97ec | 1194 | |
7db7ed3c VM |
1195 | memset (important_class_p, 0, sizeof (important_class_p)); |
1196 | for (i = 0; i < ira_important_classes_num; i++) | |
1197 | important_class_p[ira_important_classes[i]] = true; | |
058e97ec VM |
1198 | for (cl1 = 0; cl1 < N_REG_CLASSES; cl1++) |
1199 | { | |
7db7ed3c | 1200 | ira_reg_class_super_classes[cl1][0] = LIM_REG_CLASSES; |
058e97ec VM |
1201 | for (cl2 = 0; cl2 < N_REG_CLASSES; cl2++) |
1202 | { | |
7db7ed3c | 1203 | ira_reg_classes_intersect_p[cl1][cl2] = false; |
058e97ec | 1204 | ira_reg_class_intersect[cl1][cl2] = NO_REGS; |
55a2c322 | 1205 | ira_reg_class_subset[cl1][cl2] = NO_REGS; |
058e97ec VM |
1206 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl1]); |
1207 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
1208 | COPY_HARD_REG_SET (temp_set2, reg_class_contents[cl2]); | |
1209 | AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs); | |
4f341ea0 RS |
1210 | if (hard_reg_set_empty_p (temp_hard_regset) |
1211 | && hard_reg_set_empty_p (temp_set2)) | |
058e97ec | 1212 | { |
1756cb66 VM |
1213 | /* The both classes have no allocatable hard registers |
1214 | -- take all class hard registers into account and use | |
1215 | reg_class_subunion and reg_class_superunion. */ | |
058e97ec VM |
1216 | for (i = 0;; i++) |
1217 | { | |
1218 | cl3 = reg_class_subclasses[cl1][i]; | |
1219 | if (cl3 == LIM_REG_CLASSES) | |
1220 | break; | |
1221 | if (reg_class_subset_p (ira_reg_class_intersect[cl1][cl2], | |
bbbbb16a ILT |
1222 | (enum reg_class) cl3)) |
1223 | ira_reg_class_intersect[cl1][cl2] = (enum reg_class) cl3; | |
058e97ec | 1224 | } |
1756cb66 VM |
1225 | ira_reg_class_subunion[cl1][cl2] = reg_class_subunion[cl1][cl2]; |
1226 | ira_reg_class_superunion[cl1][cl2] = reg_class_superunion[cl1][cl2]; | |
058e97ec VM |
1227 | continue; |
1228 | } | |
7db7ed3c VM |
1229 | ira_reg_classes_intersect_p[cl1][cl2] |
1230 | = hard_reg_set_intersect_p (temp_hard_regset, temp_set2); | |
1231 | if (important_class_p[cl1] && important_class_p[cl2] | |
1232 | && hard_reg_set_subset_p (temp_hard_regset, temp_set2)) | |
1233 | { | |
1756cb66 VM |
1234 | /* CL1 and CL2 are important classes and CL1 allocatable |
1235 | hard register set is inside of CL2 allocatable hard | |
1236 | registers -- make CL1 a superset of CL2. */ | |
7db7ed3c VM |
1237 | enum reg_class *p; |
1238 | ||
1239 | p = &ira_reg_class_super_classes[cl1][0]; | |
1240 | while (*p != LIM_REG_CLASSES) | |
1241 | p++; | |
1242 | *p++ = (enum reg_class) cl2; | |
1243 | *p = LIM_REG_CLASSES; | |
1244 | } | |
1756cb66 VM |
1245 | ira_reg_class_subunion[cl1][cl2] = NO_REGS; |
1246 | ira_reg_class_superunion[cl1][cl2] = NO_REGS; | |
058e97ec VM |
1247 | COPY_HARD_REG_SET (intersection_set, reg_class_contents[cl1]); |
1248 | AND_HARD_REG_SET (intersection_set, reg_class_contents[cl2]); | |
1249 | AND_COMPL_HARD_REG_SET (intersection_set, no_unit_alloc_regs); | |
1250 | COPY_HARD_REG_SET (union_set, reg_class_contents[cl1]); | |
1251 | IOR_HARD_REG_SET (union_set, reg_class_contents[cl2]); | |
1252 | AND_COMPL_HARD_REG_SET (union_set, no_unit_alloc_regs); | |
55a2c322 | 1253 | for (cl3 = 0; cl3 < N_REG_CLASSES; cl3++) |
058e97ec | 1254 | { |
058e97ec VM |
1255 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl3]); |
1256 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
1257 | if (hard_reg_set_subset_p (temp_hard_regset, intersection_set)) | |
1258 | { | |
1756cb66 VM |
1259 | /* CL3 allocatable hard register set is inside of |
1260 | intersection of allocatable hard register sets | |
1261 | of CL1 and CL2. */ | |
55a2c322 VM |
1262 | if (important_class_p[cl3]) |
1263 | { | |
1264 | COPY_HARD_REG_SET | |
1265 | (temp_set2, | |
1266 | reg_class_contents | |
1267 | [(int) ira_reg_class_intersect[cl1][cl2]]); | |
1268 | AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs); | |
1269 | if (! hard_reg_set_subset_p (temp_hard_regset, temp_set2) | |
1270 | /* If the allocatable hard register sets are | |
1271 | the same, prefer GENERAL_REGS or the | |
1272 | smallest class for debugging | |
1273 | purposes. */ | |
1274 | || (hard_reg_set_equal_p (temp_hard_regset, temp_set2) | |
1275 | && (cl3 == GENERAL_REGS | |
1276 | || ((ira_reg_class_intersect[cl1][cl2] | |
1277 | != GENERAL_REGS) | |
1278 | && hard_reg_set_subset_p | |
1279 | (reg_class_contents[cl3], | |
1280 | reg_class_contents | |
1281 | [(int) | |
1282 | ira_reg_class_intersect[cl1][cl2]]))))) | |
1283 | ira_reg_class_intersect[cl1][cl2] = (enum reg_class) cl3; | |
1284 | } | |
058e97ec VM |
1285 | COPY_HARD_REG_SET |
1286 | (temp_set2, | |
55a2c322 | 1287 | reg_class_contents[(int) ira_reg_class_subset[cl1][cl2]]); |
058e97ec | 1288 | AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs); |
55a2c322 VM |
1289 | if (! hard_reg_set_subset_p (temp_hard_regset, temp_set2) |
1290 | /* Ignore unavailable hard registers and prefer | |
1291 | smallest class for debugging purposes. */ | |
058e97ec | 1292 | || (hard_reg_set_equal_p (temp_hard_regset, temp_set2) |
55a2c322 VM |
1293 | && hard_reg_set_subset_p |
1294 | (reg_class_contents[cl3], | |
1295 | reg_class_contents | |
1296 | [(int) ira_reg_class_subset[cl1][cl2]]))) | |
1297 | ira_reg_class_subset[cl1][cl2] = (enum reg_class) cl3; | |
058e97ec | 1298 | } |
55a2c322 VM |
1299 | if (important_class_p[cl3] |
1300 | && hard_reg_set_subset_p (temp_hard_regset, union_set)) | |
058e97ec | 1301 | { |
1756cb66 VM |
1302 | /* CL3 allocatbale hard register set is inside of |
1303 | union of allocatable hard register sets of CL1 | |
1304 | and CL2. */ | |
058e97ec VM |
1305 | COPY_HARD_REG_SET |
1306 | (temp_set2, | |
1756cb66 | 1307 | reg_class_contents[(int) ira_reg_class_subunion[cl1][cl2]]); |
058e97ec | 1308 | AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs); |
1756cb66 | 1309 | if (ira_reg_class_subunion[cl1][cl2] == NO_REGS |
058e97ec | 1310 | || (hard_reg_set_subset_p (temp_set2, temp_hard_regset) |
1756cb66 VM |
1311 | |
1312 | && (! hard_reg_set_equal_p (temp_set2, | |
1313 | temp_hard_regset) | |
1314 | || cl3 == GENERAL_REGS | |
1315 | /* If the allocatable hard register sets are the | |
1316 | same, prefer GENERAL_REGS or the smallest | |
1317 | class for debugging purposes. */ | |
1318 | || (ira_reg_class_subunion[cl1][cl2] != GENERAL_REGS | |
1319 | && hard_reg_set_subset_p | |
1320 | (reg_class_contents[cl3], | |
1321 | reg_class_contents | |
1322 | [(int) ira_reg_class_subunion[cl1][cl2]]))))) | |
1323 | ira_reg_class_subunion[cl1][cl2] = (enum reg_class) cl3; | |
1324 | } | |
1325 | if (hard_reg_set_subset_p (union_set, temp_hard_regset)) | |
1326 | { | |
1327 | /* CL3 allocatable hard register set contains union | |
1328 | of allocatable hard register sets of CL1 and | |
1329 | CL2. */ | |
1330 | COPY_HARD_REG_SET | |
1331 | (temp_set2, | |
1332 | reg_class_contents[(int) ira_reg_class_superunion[cl1][cl2]]); | |
1333 | AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs); | |
1334 | if (ira_reg_class_superunion[cl1][cl2] == NO_REGS | |
1335 | || (hard_reg_set_subset_p (temp_hard_regset, temp_set2) | |
b8698a0f | 1336 | |
058e97ec VM |
1337 | && (! hard_reg_set_equal_p (temp_set2, |
1338 | temp_hard_regset) | |
1756cb66 VM |
1339 | || cl3 == GENERAL_REGS |
1340 | /* If the allocatable hard register sets are the | |
1341 | same, prefer GENERAL_REGS or the smallest | |
1342 | class for debugging purposes. */ | |
1343 | || (ira_reg_class_superunion[cl1][cl2] != GENERAL_REGS | |
1344 | && hard_reg_set_subset_p | |
1345 | (reg_class_contents[cl3], | |
1346 | reg_class_contents | |
1347 | [(int) ira_reg_class_superunion[cl1][cl2]]))))) | |
1348 | ira_reg_class_superunion[cl1][cl2] = (enum reg_class) cl3; | |
058e97ec VM |
1349 | } |
1350 | } | |
1351 | } | |
1352 | } | |
1353 | } | |
1354 | ||
165f639c VM |
1355 | /* Output all unifrom and important classes into file F. */ |
1356 | static void | |
1357 | print_unform_and_important_classes (FILE *f) | |
1358 | { | |
1359 | static const char *const reg_class_names[] = REG_CLASS_NAMES; | |
1360 | int i, cl; | |
1361 | ||
1362 | fprintf (f, "Uniform classes:\n"); | |
1363 | for (cl = 0; cl < N_REG_CLASSES; cl++) | |
1364 | if (ira_uniform_class_p[cl]) | |
1365 | fprintf (f, " %s", reg_class_names[cl]); | |
1366 | fprintf (f, "\nImportant classes:\n"); | |
1367 | for (i = 0; i < ira_important_classes_num; i++) | |
1368 | fprintf (f, " %s", reg_class_names[ira_important_classes[i]]); | |
1369 | fprintf (f, "\n"); | |
1370 | } | |
1371 | ||
1372 | /* Output all possible allocno or pressure classes and their | |
1373 | translation map into file F. */ | |
058e97ec | 1374 | static void |
165f639c | 1375 | print_translated_classes (FILE *f, bool pressure_p) |
1756cb66 VM |
1376 | { |
1377 | int classes_num = (pressure_p | |
1378 | ? ira_pressure_classes_num : ira_allocno_classes_num); | |
1379 | enum reg_class *classes = (pressure_p | |
1380 | ? ira_pressure_classes : ira_allocno_classes); | |
1381 | enum reg_class *class_translate = (pressure_p | |
1382 | ? ira_pressure_class_translate | |
1383 | : ira_allocno_class_translate); | |
058e97ec VM |
1384 | static const char *const reg_class_names[] = REG_CLASS_NAMES; |
1385 | int i; | |
1386 | ||
1756cb66 VM |
1387 | fprintf (f, "%s classes:\n", pressure_p ? "Pressure" : "Allocno"); |
1388 | for (i = 0; i < classes_num; i++) | |
1389 | fprintf (f, " %s", reg_class_names[classes[i]]); | |
058e97ec VM |
1390 | fprintf (f, "\nClass translation:\n"); |
1391 | for (i = 0; i < N_REG_CLASSES; i++) | |
1392 | fprintf (f, " %s -> %s\n", reg_class_names[i], | |
1756cb66 | 1393 | reg_class_names[class_translate[i]]); |
058e97ec VM |
1394 | } |
1395 | ||
1756cb66 VM |
1396 | /* Output all possible allocno and translation classes and the |
1397 | translation maps into stderr. */ | |
058e97ec | 1398 | void |
1756cb66 | 1399 | ira_debug_allocno_classes (void) |
058e97ec | 1400 | { |
165f639c VM |
1401 | print_unform_and_important_classes (stderr); |
1402 | print_translated_classes (stderr, false); | |
1403 | print_translated_classes (stderr, true); | |
058e97ec VM |
1404 | } |
1405 | ||
1756cb66 | 1406 | /* Set up different arrays concerning class subsets, allocno and |
058e97ec VM |
1407 | important classes. */ |
1408 | static void | |
1756cb66 | 1409 | find_reg_classes (void) |
058e97ec | 1410 | { |
1756cb66 | 1411 | setup_allocno_and_important_classes (); |
7db7ed3c | 1412 | setup_class_translate (); |
db1a8d98 | 1413 | reorder_important_classes (); |
7db7ed3c | 1414 | setup_reg_class_relations (); |
058e97ec VM |
1415 | } |
1416 | ||
1417 | \f | |
1418 | ||
c0683a82 VM |
1419 | /* Set up the array above. */ |
1420 | static void | |
1756cb66 | 1421 | setup_hard_regno_aclass (void) |
c0683a82 | 1422 | { |
7efcf910 | 1423 | int i; |
c0683a82 VM |
1424 | |
1425 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1426 | { | |
1756cb66 VM |
1427 | #if 1 |
1428 | ira_hard_regno_allocno_class[i] | |
7efcf910 CLT |
1429 | = (TEST_HARD_REG_BIT (no_unit_alloc_regs, i) |
1430 | ? NO_REGS | |
1756cb66 VM |
1431 | : ira_allocno_class_translate[REGNO_REG_CLASS (i)]); |
1432 | #else | |
1433 | int j; | |
1434 | enum reg_class cl; | |
1435 | ira_hard_regno_allocno_class[i] = NO_REGS; | |
1436 | for (j = 0; j < ira_allocno_classes_num; j++) | |
1437 | { | |
1438 | cl = ira_allocno_classes[j]; | |
1439 | if (ira_class_hard_reg_index[cl][i] >= 0) | |
1440 | { | |
1441 | ira_hard_regno_allocno_class[i] = cl; | |
1442 | break; | |
1443 | } | |
1444 | } | |
1445 | #endif | |
c0683a82 VM |
1446 | } |
1447 | } | |
1448 | ||
1449 | \f | |
1450 | ||
1756cb66 | 1451 | /* Form IRA_REG_CLASS_MAX_NREGS and IRA_REG_CLASS_MIN_NREGS maps. */ |
058e97ec VM |
1452 | static void |
1453 | setup_reg_class_nregs (void) | |
1454 | { | |
1756cb66 | 1455 | int i, cl, cl2, m; |
058e97ec | 1456 | |
1756cb66 VM |
1457 | for (m = 0; m < MAX_MACHINE_MODE; m++) |
1458 | { | |
1459 | for (cl = 0; cl < N_REG_CLASSES; cl++) | |
1460 | ira_reg_class_max_nregs[cl][m] | |
1461 | = ira_reg_class_min_nregs[cl][m] | |
a8c44c52 | 1462 | = targetm.class_max_nregs ((reg_class_t) cl, (enum machine_mode) m); |
1756cb66 VM |
1463 | for (cl = 0; cl < N_REG_CLASSES; cl++) |
1464 | for (i = 0; | |
1465 | (cl2 = alloc_reg_class_subclasses[cl][i]) != LIM_REG_CLASSES; | |
1466 | i++) | |
1467 | if (ira_reg_class_min_nregs[cl2][m] | |
1468 | < ira_reg_class_min_nregs[cl][m]) | |
1469 | ira_reg_class_min_nregs[cl][m] = ira_reg_class_min_nregs[cl2][m]; | |
1470 | } | |
058e97ec VM |
1471 | } |
1472 | ||
1473 | \f | |
1474 | ||
c9d74da6 RS |
1475 | /* Set up IRA_PROHIBITED_CLASS_MODE_REGS and IRA_CLASS_SINGLETON. |
1476 | This function is called once IRA_CLASS_HARD_REGS has been initialized. */ | |
058e97ec VM |
1477 | static void |
1478 | setup_prohibited_class_mode_regs (void) | |
1479 | { | |
c9d74da6 | 1480 | int j, k, hard_regno, cl, last_hard_regno, count; |
058e97ec | 1481 | |
1756cb66 | 1482 | for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) |
058e97ec | 1483 | { |
c9d74da6 RS |
1484 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); |
1485 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
058e97ec VM |
1486 | for (j = 0; j < NUM_MACHINE_MODES; j++) |
1487 | { | |
c9d74da6 RS |
1488 | count = 0; |
1489 | last_hard_regno = -1; | |
1756cb66 | 1490 | CLEAR_HARD_REG_SET (ira_prohibited_class_mode_regs[cl][j]); |
058e97ec VM |
1491 | for (k = ira_class_hard_regs_num[cl] - 1; k >= 0; k--) |
1492 | { | |
1493 | hard_regno = ira_class_hard_regs[cl][k]; | |
bbbbb16a | 1494 | if (! HARD_REGNO_MODE_OK (hard_regno, (enum machine_mode) j)) |
1756cb66 | 1495 | SET_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j], |
058e97ec | 1496 | hard_regno); |
c9d74da6 RS |
1497 | else if (in_hard_reg_set_p (temp_hard_regset, |
1498 | (enum machine_mode) j, hard_regno)) | |
1499 | { | |
1500 | last_hard_regno = hard_regno; | |
1501 | count++; | |
1502 | } | |
058e97ec | 1503 | } |
c9d74da6 | 1504 | ira_class_singleton[cl][j] = (count == 1 ? last_hard_regno : -1); |
058e97ec VM |
1505 | } |
1506 | } | |
1507 | } | |
1508 | ||
1756cb66 VM |
1509 | /* Clarify IRA_PROHIBITED_CLASS_MODE_REGS by excluding hard registers |
1510 | spanning from one register pressure class to another one. It is | |
1511 | called after defining the pressure classes. */ | |
1512 | static void | |
1513 | clarify_prohibited_class_mode_regs (void) | |
1514 | { | |
1515 | int j, k, hard_regno, cl, pclass, nregs; | |
1516 | ||
1517 | for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) | |
1518 | for (j = 0; j < NUM_MACHINE_MODES; j++) | |
a2c19e93 RS |
1519 | { |
1520 | CLEAR_HARD_REG_SET (ira_useful_class_mode_regs[cl][j]); | |
1521 | for (k = ira_class_hard_regs_num[cl] - 1; k >= 0; k--) | |
1522 | { | |
1523 | hard_regno = ira_class_hard_regs[cl][k]; | |
1524 | if (TEST_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j], hard_regno)) | |
1525 | continue; | |
1526 | nregs = hard_regno_nregs[hard_regno][j]; | |
1527 | if (hard_regno + nregs > FIRST_PSEUDO_REGISTER) | |
1756cb66 VM |
1528 | { |
1529 | SET_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j], | |
1530 | hard_regno); | |
a2c19e93 | 1531 | continue; |
1756cb66 | 1532 | } |
a2c19e93 RS |
1533 | pclass = ira_pressure_class_translate[REGNO_REG_CLASS (hard_regno)]; |
1534 | for (nregs-- ;nregs >= 0; nregs--) | |
1535 | if (((enum reg_class) pclass | |
1536 | != ira_pressure_class_translate[REGNO_REG_CLASS | |
1537 | (hard_regno + nregs)])) | |
1538 | { | |
1539 | SET_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j], | |
1540 | hard_regno); | |
1541 | break; | |
1542 | } | |
1543 | if (!TEST_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j], | |
1544 | hard_regno)) | |
1545 | add_to_hard_reg_set (&ira_useful_class_mode_regs[cl][j], | |
1546 | (enum machine_mode) j, hard_regno); | |
1547 | } | |
1548 | } | |
1756cb66 | 1549 | } |
058e97ec | 1550 | \f |
7cc61ee4 RS |
1551 | /* Allocate and initialize IRA_REGISTER_MOVE_COST, IRA_MAY_MOVE_IN_COST |
1552 | and IRA_MAY_MOVE_OUT_COST for MODE. */ | |
1553 | void | |
1554 | ira_init_register_move_cost (enum machine_mode mode) | |
e80ccebc RS |
1555 | { |
1556 | static unsigned short last_move_cost[N_REG_CLASSES][N_REG_CLASSES]; | |
1557 | bool all_match = true; | |
ed9e2ed0 | 1558 | unsigned int cl1, cl2; |
e80ccebc | 1559 | |
7cc61ee4 RS |
1560 | ira_assert (ira_register_move_cost[mode] == NULL |
1561 | && ira_may_move_in_cost[mode] == NULL | |
1562 | && ira_may_move_out_cost[mode] == NULL); | |
ed9e2ed0 RS |
1563 | ira_assert (have_regs_of_mode[mode]); |
1564 | for (cl1 = 0; cl1 < N_REG_CLASSES; cl1++) | |
1565 | if (contains_reg_of_mode[cl1][mode]) | |
1566 | for (cl2 = 0; cl2 < N_REG_CLASSES; cl2++) | |
e80ccebc RS |
1567 | { |
1568 | int cost; | |
ed9e2ed0 | 1569 | if (!contains_reg_of_mode[cl2][mode]) |
e80ccebc RS |
1570 | cost = 65535; |
1571 | else | |
1572 | { | |
ed9e2ed0 RS |
1573 | cost = register_move_cost (mode, (enum reg_class) cl1, |
1574 | (enum reg_class) cl2); | |
1575 | ira_assert (cost < 65535); | |
e80ccebc | 1576 | } |
ed9e2ed0 RS |
1577 | all_match &= (last_move_cost[cl1][cl2] == cost); |
1578 | last_move_cost[cl1][cl2] = cost; | |
e80ccebc RS |
1579 | } |
1580 | if (all_match && last_mode_for_init_move_cost != -1) | |
1581 | { | |
7cc61ee4 RS |
1582 | ira_register_move_cost[mode] |
1583 | = ira_register_move_cost[last_mode_for_init_move_cost]; | |
1584 | ira_may_move_in_cost[mode] | |
1585 | = ira_may_move_in_cost[last_mode_for_init_move_cost]; | |
1586 | ira_may_move_out_cost[mode] | |
1587 | = ira_may_move_out_cost[last_mode_for_init_move_cost]; | |
e80ccebc RS |
1588 | return; |
1589 | } | |
ed9e2ed0 | 1590 | last_mode_for_init_move_cost = mode; |
7cc61ee4 RS |
1591 | ira_register_move_cost[mode] = XNEWVEC (move_table, N_REG_CLASSES); |
1592 | ira_may_move_in_cost[mode] = XNEWVEC (move_table, N_REG_CLASSES); | |
1593 | ira_may_move_out_cost[mode] = XNEWVEC (move_table, N_REG_CLASSES); | |
ed9e2ed0 RS |
1594 | for (cl1 = 0; cl1 < N_REG_CLASSES; cl1++) |
1595 | if (contains_reg_of_mode[cl1][mode]) | |
1596 | for (cl2 = 0; cl2 < N_REG_CLASSES; cl2++) | |
e80ccebc RS |
1597 | { |
1598 | int cost; | |
1599 | enum reg_class *p1, *p2; | |
1600 | ||
ed9e2ed0 | 1601 | if (last_move_cost[cl1][cl2] == 65535) |
e80ccebc | 1602 | { |
7cc61ee4 RS |
1603 | ira_register_move_cost[mode][cl1][cl2] = 65535; |
1604 | ira_may_move_in_cost[mode][cl1][cl2] = 65535; | |
1605 | ira_may_move_out_cost[mode][cl1][cl2] = 65535; | |
e80ccebc RS |
1606 | } |
1607 | else | |
1608 | { | |
ed9e2ed0 | 1609 | cost = last_move_cost[cl1][cl2]; |
e80ccebc | 1610 | |
ed9e2ed0 | 1611 | for (p2 = ®_class_subclasses[cl2][0]; |
e80ccebc | 1612 | *p2 != LIM_REG_CLASSES; p2++) |
48e3d6e9 RS |
1613 | if (ira_class_hard_regs_num[*p2] > 0 |
1614 | && (ira_reg_class_max_nregs[*p2][mode] | |
1615 | <= ira_class_hard_regs_num[*p2])) | |
7cc61ee4 | 1616 | cost = MAX (cost, ira_register_move_cost[mode][cl1][*p2]); |
e80ccebc | 1617 | |
ed9e2ed0 | 1618 | for (p1 = ®_class_subclasses[cl1][0]; |
e80ccebc | 1619 | *p1 != LIM_REG_CLASSES; p1++) |
48e3d6e9 RS |
1620 | if (ira_class_hard_regs_num[*p1] > 0 |
1621 | && (ira_reg_class_max_nregs[*p1][mode] | |
1622 | <= ira_class_hard_regs_num[*p1])) | |
7cc61ee4 | 1623 | cost = MAX (cost, ira_register_move_cost[mode][*p1][cl2]); |
e80ccebc | 1624 | |
ed9e2ed0 | 1625 | ira_assert (cost <= 65535); |
7cc61ee4 | 1626 | ira_register_move_cost[mode][cl1][cl2] = cost; |
e80ccebc | 1627 | |
48e3d6e9 | 1628 | if (ira_class_subset_p[cl1][cl2]) |
7cc61ee4 | 1629 | ira_may_move_in_cost[mode][cl1][cl2] = 0; |
e80ccebc | 1630 | else |
7cc61ee4 | 1631 | ira_may_move_in_cost[mode][cl1][cl2] = cost; |
e80ccebc | 1632 | |
48e3d6e9 | 1633 | if (ira_class_subset_p[cl2][cl1]) |
7cc61ee4 | 1634 | ira_may_move_out_cost[mode][cl1][cl2] = 0; |
e80ccebc | 1635 | else |
7cc61ee4 | 1636 | ira_may_move_out_cost[mode][cl1][cl2] = cost; |
e80ccebc RS |
1637 | } |
1638 | } | |
1639 | else | |
ed9e2ed0 | 1640 | for (cl2 = 0; cl2 < N_REG_CLASSES; cl2++) |
e80ccebc | 1641 | { |
7cc61ee4 RS |
1642 | ira_register_move_cost[mode][cl1][cl2] = 65535; |
1643 | ira_may_move_in_cost[mode][cl1][cl2] = 65535; | |
1644 | ira_may_move_out_cost[mode][cl1][cl2] = 65535; | |
058e97ec | 1645 | } |
058e97ec | 1646 | } |
058e97ec VM |
1647 | \f |
1648 | ||
058e97ec VM |
1649 | /* This is called once during compiler work. It sets up |
1650 | different arrays whose values don't depend on the compiled | |
1651 | function. */ | |
1652 | void | |
1653 | ira_init_once (void) | |
1654 | { | |
058e97ec | 1655 | ira_init_costs_once (); |
55a2c322 | 1656 | lra_init_once (); |
058e97ec VM |
1657 | } |
1658 | ||
7cc61ee4 RS |
1659 | /* Free ira_max_register_move_cost, ira_may_move_in_cost and |
1660 | ira_may_move_out_cost for each mode. */ | |
058e97ec VM |
1661 | static void |
1662 | free_register_move_costs (void) | |
1663 | { | |
e80ccebc | 1664 | int mode, i; |
058e97ec | 1665 | |
e80ccebc RS |
1666 | /* Reset move_cost and friends, making sure we only free shared |
1667 | table entries once. */ | |
1668 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
7cc61ee4 | 1669 | if (ira_register_move_cost[mode]) |
e80ccebc | 1670 | { |
7cc61ee4 RS |
1671 | for (i = 0; |
1672 | i < mode && (ira_register_move_cost[i] | |
1673 | != ira_register_move_cost[mode]); | |
1674 | i++) | |
e80ccebc RS |
1675 | ; |
1676 | if (i == mode) | |
1677 | { | |
7cc61ee4 RS |
1678 | free (ira_register_move_cost[mode]); |
1679 | free (ira_may_move_in_cost[mode]); | |
1680 | free (ira_may_move_out_cost[mode]); | |
e80ccebc RS |
1681 | } |
1682 | } | |
7cc61ee4 RS |
1683 | memset (ira_register_move_cost, 0, sizeof ira_register_move_cost); |
1684 | memset (ira_may_move_in_cost, 0, sizeof ira_may_move_in_cost); | |
1685 | memset (ira_may_move_out_cost, 0, sizeof ira_may_move_out_cost); | |
e80ccebc | 1686 | last_mode_for_init_move_cost = -1; |
058e97ec VM |
1687 | } |
1688 | ||
1689 | /* This is called every time when register related information is | |
1690 | changed. */ | |
1691 | void | |
1692 | ira_init (void) | |
1693 | { | |
1694 | free_register_move_costs (); | |
1695 | setup_reg_mode_hard_regset (); | |
1696 | setup_alloc_regs (flag_omit_frame_pointer != 0); | |
1697 | setup_class_subset_and_memory_move_costs (); | |
058e97ec VM |
1698 | setup_reg_class_nregs (); |
1699 | setup_prohibited_class_mode_regs (); | |
1756cb66 VM |
1700 | find_reg_classes (); |
1701 | clarify_prohibited_class_mode_regs (); | |
1702 | setup_hard_regno_aclass (); | |
058e97ec | 1703 | ira_init_costs (); |
55a2c322 | 1704 | lra_init (); |
058e97ec VM |
1705 | } |
1706 | ||
1707 | /* Function called once at the end of compiler work. */ | |
1708 | void | |
1709 | ira_finish_once (void) | |
1710 | { | |
1711 | ira_finish_costs_once (); | |
1712 | free_register_move_costs (); | |
55a2c322 | 1713 | lra_finish_once (); |
058e97ec VM |
1714 | } |
1715 | ||
1716 | \f | |
15e7b94f RS |
1717 | #define ira_prohibited_mode_move_regs_initialized_p \ |
1718 | (this_target_ira_int->x_ira_prohibited_mode_move_regs_initialized_p) | |
058e97ec VM |
1719 | |
1720 | /* Set up IRA_PROHIBITED_MODE_MOVE_REGS. */ | |
1721 | static void | |
1722 | setup_prohibited_mode_move_regs (void) | |
1723 | { | |
1724 | int i, j; | |
1725 | rtx test_reg1, test_reg2, move_pat, move_insn; | |
1726 | ||
1727 | if (ira_prohibited_mode_move_regs_initialized_p) | |
1728 | return; | |
1729 | ira_prohibited_mode_move_regs_initialized_p = true; | |
1730 | test_reg1 = gen_rtx_REG (VOIDmode, 0); | |
1731 | test_reg2 = gen_rtx_REG (VOIDmode, 0); | |
1732 | move_pat = gen_rtx_SET (VOIDmode, test_reg1, test_reg2); | |
418e920f | 1733 | move_insn = gen_rtx_INSN (VOIDmode, 0, 0, 0, 0, move_pat, 0, -1, 0); |
058e97ec VM |
1734 | for (i = 0; i < NUM_MACHINE_MODES; i++) |
1735 | { | |
1736 | SET_HARD_REG_SET (ira_prohibited_mode_move_regs[i]); | |
1737 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
1738 | { | |
bbbbb16a | 1739 | if (! HARD_REGNO_MODE_OK (j, (enum machine_mode) i)) |
058e97ec | 1740 | continue; |
5444da31 | 1741 | SET_REGNO_RAW (test_reg1, j); |
32e8bb8e | 1742 | PUT_MODE (test_reg1, (enum machine_mode) i); |
5444da31 | 1743 | SET_REGNO_RAW (test_reg2, j); |
32e8bb8e | 1744 | PUT_MODE (test_reg2, (enum machine_mode) i); |
058e97ec VM |
1745 | INSN_CODE (move_insn) = -1; |
1746 | recog_memoized (move_insn); | |
1747 | if (INSN_CODE (move_insn) < 0) | |
1748 | continue; | |
1749 | extract_insn (move_insn); | |
1750 | if (! constrain_operands (1)) | |
1751 | continue; | |
1752 | CLEAR_HARD_REG_BIT (ira_prohibited_mode_move_regs[i], j); | |
1753 | } | |
1754 | } | |
1755 | } | |
1756 | ||
1757 | \f | |
1758 | ||
0896cc66 JL |
1759 | /* Return nonzero if REGNO is a particularly bad choice for reloading X. */ |
1760 | static bool | |
1761 | ira_bad_reload_regno_1 (int regno, rtx x) | |
1762 | { | |
ac0ab4f7 | 1763 | int x_regno, n, i; |
0896cc66 JL |
1764 | ira_allocno_t a; |
1765 | enum reg_class pref; | |
1766 | ||
1767 | /* We only deal with pseudo regs. */ | |
1768 | if (! x || GET_CODE (x) != REG) | |
1769 | return false; | |
1770 | ||
1771 | x_regno = REGNO (x); | |
1772 | if (x_regno < FIRST_PSEUDO_REGISTER) | |
1773 | return false; | |
1774 | ||
1775 | /* If the pseudo prefers REGNO explicitly, then do not consider | |
1776 | REGNO a bad spill choice. */ | |
1777 | pref = reg_preferred_class (x_regno); | |
1778 | if (reg_class_size[pref] == 1) | |
1779 | return !TEST_HARD_REG_BIT (reg_class_contents[pref], regno); | |
1780 | ||
1781 | /* If the pseudo conflicts with REGNO, then we consider REGNO a | |
1782 | poor choice for a reload regno. */ | |
1783 | a = ira_regno_allocno_map[x_regno]; | |
ac0ab4f7 BS |
1784 | n = ALLOCNO_NUM_OBJECTS (a); |
1785 | for (i = 0; i < n; i++) | |
1786 | { | |
1787 | ira_object_t obj = ALLOCNO_OBJECT (a, i); | |
1788 | if (TEST_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), regno)) | |
1789 | return true; | |
1790 | } | |
0896cc66 JL |
1791 | return false; |
1792 | } | |
1793 | ||
1794 | /* Return nonzero if REGNO is a particularly bad choice for reloading | |
1795 | IN or OUT. */ | |
1796 | bool | |
1797 | ira_bad_reload_regno (int regno, rtx in, rtx out) | |
1798 | { | |
1799 | return (ira_bad_reload_regno_1 (regno, in) | |
1800 | || ira_bad_reload_regno_1 (regno, out)); | |
1801 | } | |
1802 | ||
058e97ec VM |
1803 | /* Return TRUE if *LOC contains an asm. */ |
1804 | static int | |
1805 | insn_contains_asm_1 (rtx *loc, void *data ATTRIBUTE_UNUSED) | |
1806 | { | |
1807 | if ( !*loc) | |
1808 | return FALSE; | |
1809 | if (GET_CODE (*loc) == ASM_OPERANDS) | |
1810 | return TRUE; | |
1811 | return FALSE; | |
1812 | } | |
1813 | ||
1814 | ||
1815 | /* Return TRUE if INSN contains an ASM. */ | |
1816 | static bool | |
1817 | insn_contains_asm (rtx insn) | |
1818 | { | |
1819 | return for_each_rtx (&insn, insn_contains_asm_1, NULL); | |
1820 | } | |
1821 | ||
b748fbd6 | 1822 | /* Add register clobbers from asm statements. */ |
058e97ec | 1823 | static void |
b748fbd6 | 1824 | compute_regs_asm_clobbered (void) |
058e97ec VM |
1825 | { |
1826 | basic_block bb; | |
1827 | ||
058e97ec VM |
1828 | FOR_EACH_BB (bb) |
1829 | { | |
1830 | rtx insn; | |
1831 | FOR_BB_INSNS_REVERSE (bb, insn) | |
1832 | { | |
57512f53 | 1833 | df_ref *def_rec; |
058e97ec VM |
1834 | |
1835 | if (insn_contains_asm (insn)) | |
1836 | for (def_rec = DF_INSN_DEFS (insn); *def_rec; def_rec++) | |
1837 | { | |
57512f53 | 1838 | df_ref def = *def_rec; |
058e97ec | 1839 | unsigned int dregno = DF_REF_REGNO (def); |
d108e679 AS |
1840 | if (HARD_REGISTER_NUM_P (dregno)) |
1841 | add_to_hard_reg_set (&crtl->asm_clobbers, | |
1842 | GET_MODE (DF_REF_REAL_REG (def)), | |
1843 | dregno); | |
058e97ec VM |
1844 | } |
1845 | } | |
1846 | } | |
1847 | } | |
1848 | ||
1849 | ||
55a2c322 VM |
1850 | /* Set up ELIMINABLE_REGSET, IRA_NO_ALLOC_REGS, and REGS_EVER_LIVE. |
1851 | If the function is called from IRA (not from the insn scheduler or | |
1852 | RTL loop invariant motion), FROM_IRA_P is true. */ | |
ce18efcb | 1853 | void |
55a2c322 | 1854 | ira_setup_eliminable_regset (bool from_ira_p) |
058e97ec | 1855 | { |
058e97ec | 1856 | #ifdef ELIMINABLE_REGS |
89ceba31 | 1857 | int i; |
058e97ec VM |
1858 | static const struct {const int from, to; } eliminables[] = ELIMINABLE_REGS; |
1859 | #endif | |
1860 | /* FIXME: If EXIT_IGNORE_STACK is set, we will not save and restore | |
1861 | sp for alloca. So we can't eliminate the frame pointer in that | |
1862 | case. At some point, we should improve this by emitting the | |
1863 | sp-adjusting insns for this case. */ | |
55a2c322 | 1864 | frame_pointer_needed |
058e97ec VM |
1865 | = (! flag_omit_frame_pointer |
1866 | || (cfun->calls_alloca && EXIT_IGNORE_STACK) | |
d809253a EB |
1867 | /* We need the frame pointer to catch stack overflow exceptions |
1868 | if the stack pointer is moving. */ | |
1869 | || (flag_stack_check && STACK_CHECK_MOVING_SP) | |
058e97ec VM |
1870 | || crtl->accesses_prior_frames |
1871 | || crtl->stack_realign_needed | |
b52b1749 | 1872 | || targetm.frame_pointer_required ()); |
058e97ec | 1873 | |
55a2c322 VM |
1874 | if (from_ira_p && ira_use_lra_p) |
1875 | /* It can change FRAME_POINTER_NEEDED. We call it only from IRA | |
1876 | because it is expensive. */ | |
1877 | lra_init_elimination (); | |
058e97ec | 1878 | |
55a2c322 VM |
1879 | if (frame_pointer_needed) |
1880 | df_set_regs_ever_live (HARD_FRAME_POINTER_REGNUM, true); | |
1881 | ||
058e97ec VM |
1882 | COPY_HARD_REG_SET (ira_no_alloc_regs, no_unit_alloc_regs); |
1883 | CLEAR_HARD_REG_SET (eliminable_regset); | |
1884 | ||
b748fbd6 PB |
1885 | compute_regs_asm_clobbered (); |
1886 | ||
058e97ec VM |
1887 | /* Build the regset of all eliminable registers and show we can't |
1888 | use those that we already know won't be eliminated. */ | |
1889 | #ifdef ELIMINABLE_REGS | |
1890 | for (i = 0; i < (int) ARRAY_SIZE (eliminables); i++) | |
1891 | { | |
1892 | bool cannot_elim | |
7b5cbb57 | 1893 | = (! targetm.can_eliminate (eliminables[i].from, eliminables[i].to) |
55a2c322 | 1894 | || (eliminables[i].to == STACK_POINTER_REGNUM && frame_pointer_needed)); |
058e97ec | 1895 | |
b748fbd6 | 1896 | if (!TEST_HARD_REG_BIT (crtl->asm_clobbers, eliminables[i].from)) |
058e97ec VM |
1897 | { |
1898 | SET_HARD_REG_BIT (eliminable_regset, eliminables[i].from); | |
1899 | ||
1900 | if (cannot_elim) | |
1901 | SET_HARD_REG_BIT (ira_no_alloc_regs, eliminables[i].from); | |
1902 | } | |
1903 | else if (cannot_elim) | |
1904 | error ("%s cannot be used in asm here", | |
1905 | reg_names[eliminables[i].from]); | |
1906 | else | |
1907 | df_set_regs_ever_live (eliminables[i].from, true); | |
1908 | } | |
e3339d0f | 1909 | #if !HARD_FRAME_POINTER_IS_FRAME_POINTER |
b748fbd6 | 1910 | if (!TEST_HARD_REG_BIT (crtl->asm_clobbers, HARD_FRAME_POINTER_REGNUM)) |
058e97ec VM |
1911 | { |
1912 | SET_HARD_REG_BIT (eliminable_regset, HARD_FRAME_POINTER_REGNUM); | |
55a2c322 | 1913 | if (frame_pointer_needed) |
058e97ec VM |
1914 | SET_HARD_REG_BIT (ira_no_alloc_regs, HARD_FRAME_POINTER_REGNUM); |
1915 | } | |
55a2c322 | 1916 | else if (frame_pointer_needed) |
058e97ec VM |
1917 | error ("%s cannot be used in asm here", |
1918 | reg_names[HARD_FRAME_POINTER_REGNUM]); | |
1919 | else | |
1920 | df_set_regs_ever_live (HARD_FRAME_POINTER_REGNUM, true); | |
1921 | #endif | |
1922 | ||
1923 | #else | |
b748fbd6 | 1924 | if (!TEST_HARD_REG_BIT (crtl->asm_clobbers, HARD_FRAME_POINTER_REGNUM)) |
058e97ec VM |
1925 | { |
1926 | SET_HARD_REG_BIT (eliminable_regset, FRAME_POINTER_REGNUM); | |
55a2c322 | 1927 | if (frame_pointer_needed) |
058e97ec VM |
1928 | SET_HARD_REG_BIT (ira_no_alloc_regs, FRAME_POINTER_REGNUM); |
1929 | } | |
55a2c322 | 1930 | else if (frame_pointer_needed) |
058e97ec VM |
1931 | error ("%s cannot be used in asm here", reg_names[FRAME_POINTER_REGNUM]); |
1932 | else | |
1933 | df_set_regs_ever_live (FRAME_POINTER_REGNUM, true); | |
1934 | #endif | |
1935 | } | |
1936 | ||
1937 | \f | |
1938 | ||
2af2dbdc VM |
1939 | /* Vector of substitutions of register numbers, |
1940 | used to map pseudo regs into hardware regs. | |
1941 | This is set up as a result of register allocation. | |
1942 | Element N is the hard reg assigned to pseudo reg N, | |
1943 | or is -1 if no hard reg was assigned. | |
1944 | If N is a hard reg number, element N is N. */ | |
1945 | short *reg_renumber; | |
1946 | ||
058e97ec VM |
1947 | /* Set up REG_RENUMBER and CALLER_SAVE_NEEDED (used by reload) from |
1948 | the allocation found by IRA. */ | |
1949 | static void | |
1950 | setup_reg_renumber (void) | |
1951 | { | |
1952 | int regno, hard_regno; | |
1953 | ira_allocno_t a; | |
1954 | ira_allocno_iterator ai; | |
1955 | ||
1956 | caller_save_needed = 0; | |
1957 | FOR_EACH_ALLOCNO (a, ai) | |
1958 | { | |
55a2c322 VM |
1959 | if (ira_use_lra_p && ALLOCNO_CAP_MEMBER (a) != NULL) |
1960 | continue; | |
058e97ec VM |
1961 | /* There are no caps at this point. */ |
1962 | ira_assert (ALLOCNO_CAP_MEMBER (a) == NULL); | |
1963 | if (! ALLOCNO_ASSIGNED_P (a)) | |
1964 | /* It can happen if A is not referenced but partially anticipated | |
1965 | somewhere in a region. */ | |
1966 | ALLOCNO_ASSIGNED_P (a) = true; | |
1967 | ira_free_allocno_updated_costs (a); | |
1968 | hard_regno = ALLOCNO_HARD_REGNO (a); | |
1756cb66 | 1969 | regno = ALLOCNO_REGNO (a); |
058e97ec | 1970 | reg_renumber[regno] = (hard_regno < 0 ? -1 : hard_regno); |
1756cb66 | 1971 | if (hard_regno >= 0) |
058e97ec | 1972 | { |
1756cb66 VM |
1973 | int i, nwords; |
1974 | enum reg_class pclass; | |
1975 | ira_object_t obj; | |
1976 | ||
1977 | pclass = ira_pressure_class_translate[REGNO_REG_CLASS (hard_regno)]; | |
1978 | nwords = ALLOCNO_NUM_OBJECTS (a); | |
1979 | for (i = 0; i < nwords; i++) | |
1980 | { | |
1981 | obj = ALLOCNO_OBJECT (a, i); | |
1982 | IOR_COMPL_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), | |
1983 | reg_class_contents[pclass]); | |
1984 | } | |
1985 | if (ALLOCNO_CALLS_CROSSED_NUM (a) != 0 | |
9181a6e5 VM |
1986 | && ira_hard_reg_set_intersection_p (hard_regno, ALLOCNO_MODE (a), |
1987 | call_used_reg_set)) | |
1756cb66 VM |
1988 | { |
1989 | ira_assert (!optimize || flag_caller_saves | |
e384e6b5 BS |
1990 | || (ALLOCNO_CALLS_CROSSED_NUM (a) |
1991 | == ALLOCNO_CHEAP_CALLS_CROSSED_NUM (a)) | |
55a2c322 | 1992 | || ira_equiv_no_lvalue_p (regno)); |
1756cb66 VM |
1993 | caller_save_needed = 1; |
1994 | } | |
058e97ec VM |
1995 | } |
1996 | } | |
1997 | } | |
1998 | ||
1999 | /* Set up allocno assignment flags for further allocation | |
2000 | improvements. */ | |
2001 | static void | |
2002 | setup_allocno_assignment_flags (void) | |
2003 | { | |
2004 | int hard_regno; | |
2005 | ira_allocno_t a; | |
2006 | ira_allocno_iterator ai; | |
2007 | ||
2008 | FOR_EACH_ALLOCNO (a, ai) | |
2009 | { | |
2010 | if (! ALLOCNO_ASSIGNED_P (a)) | |
2011 | /* It can happen if A is not referenced but partially anticipated | |
2012 | somewhere in a region. */ | |
2013 | ira_free_allocno_updated_costs (a); | |
2014 | hard_regno = ALLOCNO_HARD_REGNO (a); | |
2015 | /* Don't assign hard registers to allocnos which are destination | |
2016 | of removed store at the end of loop. It has no sense to keep | |
2017 | the same value in different hard registers. It is also | |
2018 | impossible to assign hard registers correctly to such | |
2019 | allocnos because the cost info and info about intersected | |
2020 | calls are incorrect for them. */ | |
2021 | ALLOCNO_ASSIGNED_P (a) = (hard_regno >= 0 | |
1756cb66 | 2022 | || ALLOCNO_EMIT_DATA (a)->mem_optimized_dest_p |
058e97ec | 2023 | || (ALLOCNO_MEMORY_COST (a) |
1756cb66 | 2024 | - ALLOCNO_CLASS_COST (a)) < 0); |
9181a6e5 VM |
2025 | ira_assert |
2026 | (hard_regno < 0 | |
2027 | || ira_hard_reg_in_set_p (hard_regno, ALLOCNO_MODE (a), | |
2028 | reg_class_contents[ALLOCNO_CLASS (a)])); | |
058e97ec VM |
2029 | } |
2030 | } | |
2031 | ||
2032 | /* Evaluate overall allocation cost and the costs for using hard | |
2033 | registers and memory for allocnos. */ | |
2034 | static void | |
2035 | calculate_allocation_cost (void) | |
2036 | { | |
2037 | int hard_regno, cost; | |
2038 | ira_allocno_t a; | |
2039 | ira_allocno_iterator ai; | |
2040 | ||
2041 | ira_overall_cost = ira_reg_cost = ira_mem_cost = 0; | |
2042 | FOR_EACH_ALLOCNO (a, ai) | |
2043 | { | |
2044 | hard_regno = ALLOCNO_HARD_REGNO (a); | |
2045 | ira_assert (hard_regno < 0 | |
9181a6e5 VM |
2046 | || (ira_hard_reg_in_set_p |
2047 | (hard_regno, ALLOCNO_MODE (a), | |
2048 | reg_class_contents[ALLOCNO_CLASS (a)]))); | |
058e97ec VM |
2049 | if (hard_regno < 0) |
2050 | { | |
2051 | cost = ALLOCNO_MEMORY_COST (a); | |
2052 | ira_mem_cost += cost; | |
2053 | } | |
2054 | else if (ALLOCNO_HARD_REG_COSTS (a) != NULL) | |
2055 | { | |
2056 | cost = (ALLOCNO_HARD_REG_COSTS (a) | |
2057 | [ira_class_hard_reg_index | |
1756cb66 | 2058 | [ALLOCNO_CLASS (a)][hard_regno]]); |
058e97ec VM |
2059 | ira_reg_cost += cost; |
2060 | } | |
2061 | else | |
2062 | { | |
1756cb66 | 2063 | cost = ALLOCNO_CLASS_COST (a); |
058e97ec VM |
2064 | ira_reg_cost += cost; |
2065 | } | |
2066 | ira_overall_cost += cost; | |
2067 | } | |
2068 | ||
2069 | if (internal_flag_ira_verbose > 0 && ira_dump_file != NULL) | |
2070 | { | |
2071 | fprintf (ira_dump_file, | |
2072 | "+++Costs: overall %d, reg %d, mem %d, ld %d, st %d, move %d\n", | |
2073 | ira_overall_cost, ira_reg_cost, ira_mem_cost, | |
2074 | ira_load_cost, ira_store_cost, ira_shuffle_cost); | |
2075 | fprintf (ira_dump_file, "+++ move loops %d, new jumps %d\n", | |
2076 | ira_move_loops_num, ira_additional_jumps_num); | |
2077 | } | |
2078 | ||
2079 | } | |
2080 | ||
2081 | #ifdef ENABLE_IRA_CHECKING | |
2082 | /* Check the correctness of the allocation. We do need this because | |
2083 | of complicated code to transform more one region internal | |
2084 | representation into one region representation. */ | |
2085 | static void | |
2086 | check_allocation (void) | |
2087 | { | |
fa86d337 | 2088 | ira_allocno_t a; |
ac0ab4f7 | 2089 | int hard_regno, nregs, conflict_nregs; |
058e97ec VM |
2090 | ira_allocno_iterator ai; |
2091 | ||
2092 | FOR_EACH_ALLOCNO (a, ai) | |
2093 | { | |
ac0ab4f7 BS |
2094 | int n = ALLOCNO_NUM_OBJECTS (a); |
2095 | int i; | |
fa86d337 | 2096 | |
058e97ec VM |
2097 | if (ALLOCNO_CAP_MEMBER (a) != NULL |
2098 | || (hard_regno = ALLOCNO_HARD_REGNO (a)) < 0) | |
2099 | continue; | |
2100 | nregs = hard_regno_nregs[hard_regno][ALLOCNO_MODE (a)]; | |
8cfd82bf BS |
2101 | if (nregs == 1) |
2102 | /* We allocated a single hard register. */ | |
2103 | n = 1; | |
2104 | else if (n > 1) | |
2105 | /* We allocated multiple hard registers, and we will test | |
2106 | conflicts in a granularity of single hard regs. */ | |
2107 | nregs = 1; | |
2108 | ||
ac0ab4f7 BS |
2109 | for (i = 0; i < n; i++) |
2110 | { | |
2111 | ira_object_t obj = ALLOCNO_OBJECT (a, i); | |
2112 | ira_object_t conflict_obj; | |
2113 | ira_object_conflict_iterator oci; | |
2114 | int this_regno = hard_regno; | |
2115 | if (n > 1) | |
fa86d337 | 2116 | { |
2805e6c0 | 2117 | if (REG_WORDS_BIG_ENDIAN) |
ac0ab4f7 BS |
2118 | this_regno += n - i - 1; |
2119 | else | |
2120 | this_regno += i; | |
2121 | } | |
2122 | FOR_EACH_OBJECT_CONFLICT (obj, conflict_obj, oci) | |
2123 | { | |
2124 | ira_allocno_t conflict_a = OBJECT_ALLOCNO (conflict_obj); | |
2125 | int conflict_hard_regno = ALLOCNO_HARD_REGNO (conflict_a); | |
2126 | if (conflict_hard_regno < 0) | |
2127 | continue; | |
8cfd82bf BS |
2128 | |
2129 | conflict_nregs | |
2130 | = (hard_regno_nregs | |
2131 | [conflict_hard_regno][ALLOCNO_MODE (conflict_a)]); | |
2132 | ||
2133 | if (ALLOCNO_NUM_OBJECTS (conflict_a) > 1 | |
2134 | && conflict_nregs == ALLOCNO_NUM_OBJECTS (conflict_a)) | |
ac0ab4f7 | 2135 | { |
2805e6c0 | 2136 | if (REG_WORDS_BIG_ENDIAN) |
ac0ab4f7 BS |
2137 | conflict_hard_regno += (ALLOCNO_NUM_OBJECTS (conflict_a) |
2138 | - OBJECT_SUBWORD (conflict_obj) - 1); | |
2139 | else | |
2140 | conflict_hard_regno += OBJECT_SUBWORD (conflict_obj); | |
2141 | conflict_nregs = 1; | |
2142 | } | |
ac0ab4f7 BS |
2143 | |
2144 | if ((conflict_hard_regno <= this_regno | |
2145 | && this_regno < conflict_hard_regno + conflict_nregs) | |
2146 | || (this_regno <= conflict_hard_regno | |
2147 | && conflict_hard_regno < this_regno + nregs)) | |
fa86d337 BS |
2148 | { |
2149 | fprintf (stderr, "bad allocation for %d and %d\n", | |
2150 | ALLOCNO_REGNO (a), ALLOCNO_REGNO (conflict_a)); | |
2151 | gcc_unreachable (); | |
2152 | } | |
2153 | } | |
2154 | } | |
058e97ec VM |
2155 | } |
2156 | } | |
2157 | #endif | |
2158 | ||
55a2c322 VM |
2159 | /* Allocate REG_EQUIV_INIT. Set up it from IRA_REG_EQUIV which should |
2160 | be already calculated. */ | |
2161 | static void | |
2162 | setup_reg_equiv_init (void) | |
2163 | { | |
2164 | int i; | |
2165 | int max_regno = max_reg_num (); | |
2166 | ||
2167 | for (i = 0; i < max_regno; i++) | |
2168 | reg_equiv_init (i) = ira_reg_equiv[i].init_insns; | |
2169 | } | |
2170 | ||
2171 | /* Update equiv regno from movement of FROM_REGNO to TO_REGNO. INSNS | |
2172 | are insns which were generated for such movement. It is assumed | |
2173 | that FROM_REGNO and TO_REGNO always have the same value at the | |
2174 | point of any move containing such registers. This function is used | |
2175 | to update equiv info for register shuffles on the region borders | |
2176 | and for caller save/restore insns. */ | |
2177 | void | |
2178 | ira_update_equiv_info_by_shuffle_insn (int to_regno, int from_regno, rtx insns) | |
2179 | { | |
2180 | rtx insn, x, note; | |
2181 | ||
2182 | if (! ira_reg_equiv[from_regno].defined_p | |
2183 | && (! ira_reg_equiv[to_regno].defined_p | |
2184 | || ((x = ira_reg_equiv[to_regno].memory) != NULL_RTX | |
2185 | && ! MEM_READONLY_P (x)))) | |
2186 | return; | |
2187 | insn = insns; | |
2188 | if (NEXT_INSN (insn) != NULL_RTX) | |
2189 | { | |
2190 | if (! ira_reg_equiv[to_regno].defined_p) | |
2191 | { | |
2192 | ira_assert (ira_reg_equiv[to_regno].init_insns == NULL_RTX); | |
2193 | return; | |
2194 | } | |
2195 | ira_reg_equiv[to_regno].defined_p = false; | |
2196 | ira_reg_equiv[to_regno].memory | |
2197 | = ira_reg_equiv[to_regno].constant | |
2198 | = ira_reg_equiv[to_regno].invariant | |
2199 | = ira_reg_equiv[to_regno].init_insns = NULL_RTX; | |
2200 | if (internal_flag_ira_verbose > 3 && ira_dump_file != NULL) | |
2201 | fprintf (ira_dump_file, | |
2202 | " Invalidating equiv info for reg %d\n", to_regno); | |
2203 | return; | |
2204 | } | |
2205 | /* It is possible that FROM_REGNO still has no equivalence because | |
2206 | in shuffles to_regno<-from_regno and from_regno<-to_regno the 2nd | |
2207 | insn was not processed yet. */ | |
2208 | if (ira_reg_equiv[from_regno].defined_p) | |
2209 | { | |
2210 | ira_reg_equiv[to_regno].defined_p = true; | |
2211 | if ((x = ira_reg_equiv[from_regno].memory) != NULL_RTX) | |
2212 | { | |
2213 | ira_assert (ira_reg_equiv[from_regno].invariant == NULL_RTX | |
2214 | && ira_reg_equiv[from_regno].constant == NULL_RTX); | |
2215 | ira_assert (ira_reg_equiv[to_regno].memory == NULL_RTX | |
2216 | || rtx_equal_p (ira_reg_equiv[to_regno].memory, x)); | |
2217 | ira_reg_equiv[to_regno].memory = x; | |
2218 | if (! MEM_READONLY_P (x)) | |
2219 | /* We don't add the insn to insn init list because memory | |
2220 | equivalence is just to say what memory is better to use | |
2221 | when the pseudo is spilled. */ | |
2222 | return; | |
2223 | } | |
2224 | else if ((x = ira_reg_equiv[from_regno].constant) != NULL_RTX) | |
2225 | { | |
2226 | ira_assert (ira_reg_equiv[from_regno].invariant == NULL_RTX); | |
2227 | ira_assert (ira_reg_equiv[to_regno].constant == NULL_RTX | |
2228 | || rtx_equal_p (ira_reg_equiv[to_regno].constant, x)); | |
2229 | ira_reg_equiv[to_regno].constant = x; | |
2230 | } | |
2231 | else | |
2232 | { | |
2233 | x = ira_reg_equiv[from_regno].invariant; | |
2234 | ira_assert (x != NULL_RTX); | |
2235 | ira_assert (ira_reg_equiv[to_regno].invariant == NULL_RTX | |
2236 | || rtx_equal_p (ira_reg_equiv[to_regno].invariant, x)); | |
2237 | ira_reg_equiv[to_regno].invariant = x; | |
2238 | } | |
2239 | if (find_reg_note (insn, REG_EQUIV, x) == NULL_RTX) | |
2240 | { | |
2241 | note = set_unique_reg_note (insn, REG_EQUIV, x); | |
2242 | gcc_assert (note != NULL_RTX); | |
2243 | if (internal_flag_ira_verbose > 3 && ira_dump_file != NULL) | |
2244 | { | |
2245 | fprintf (ira_dump_file, | |
2246 | " Adding equiv note to insn %u for reg %d ", | |
2247 | INSN_UID (insn), to_regno); | |
2248 | print_value_slim (ira_dump_file, x, 1); | |
2249 | fprintf (ira_dump_file, "\n"); | |
2250 | } | |
2251 | } | |
2252 | } | |
2253 | ira_reg_equiv[to_regno].init_insns | |
2254 | = gen_rtx_INSN_LIST (VOIDmode, insn, | |
2255 | ira_reg_equiv[to_regno].init_insns); | |
2256 | if (internal_flag_ira_verbose > 3 && ira_dump_file != NULL) | |
2257 | fprintf (ira_dump_file, | |
2258 | " Adding equiv init move insn %u to reg %d\n", | |
2259 | INSN_UID (insn), to_regno); | |
2260 | } | |
2261 | ||
058e97ec VM |
2262 | /* Fix values of array REG_EQUIV_INIT after live range splitting done |
2263 | by IRA. */ | |
2264 | static void | |
2265 | fix_reg_equiv_init (void) | |
2266 | { | |
f2034d06 JL |
2267 | unsigned int max_regno = max_reg_num (); |
2268 | int i, new_regno, max; | |
058e97ec | 2269 | rtx x, prev, next, insn, set; |
b8698a0f | 2270 | |
f2034d06 | 2271 | if (VEC_length (reg_equivs_t, reg_equivs) < max_regno) |
058e97ec | 2272 | { |
f2034d06 JL |
2273 | max = VEC_length (reg_equivs_t, reg_equivs); |
2274 | grow_reg_equivs (); | |
2275 | for (i = FIRST_PSEUDO_REGISTER; i < max; i++) | |
2276 | for (prev = NULL_RTX, x = reg_equiv_init (i); | |
2277 | x != NULL_RTX; | |
2278 | x = next) | |
058e97ec VM |
2279 | { |
2280 | next = XEXP (x, 1); | |
2281 | insn = XEXP (x, 0); | |
2282 | set = single_set (insn); | |
2283 | ira_assert (set != NULL_RTX | |
2284 | && (REG_P (SET_DEST (set)) || REG_P (SET_SRC (set)))); | |
2285 | if (REG_P (SET_DEST (set)) | |
2286 | && ((int) REGNO (SET_DEST (set)) == i | |
2287 | || (int) ORIGINAL_REGNO (SET_DEST (set)) == i)) | |
2288 | new_regno = REGNO (SET_DEST (set)); | |
2289 | else if (REG_P (SET_SRC (set)) | |
2290 | && ((int) REGNO (SET_SRC (set)) == i | |
2291 | || (int) ORIGINAL_REGNO (SET_SRC (set)) == i)) | |
2292 | new_regno = REGNO (SET_SRC (set)); | |
2293 | else | |
2294 | gcc_unreachable (); | |
2295 | if (new_regno == i) | |
2296 | prev = x; | |
2297 | else | |
2298 | { | |
55a2c322 | 2299 | /* Remove the wrong list element. */ |
058e97ec | 2300 | if (prev == NULL_RTX) |
f2034d06 | 2301 | reg_equiv_init (i) = next; |
058e97ec VM |
2302 | else |
2303 | XEXP (prev, 1) = next; | |
f2034d06 JL |
2304 | XEXP (x, 1) = reg_equiv_init (new_regno); |
2305 | reg_equiv_init (new_regno) = x; | |
058e97ec VM |
2306 | } |
2307 | } | |
2308 | } | |
2309 | } | |
2310 | ||
2311 | #ifdef ENABLE_IRA_CHECKING | |
2312 | /* Print redundant memory-memory copies. */ | |
2313 | static void | |
2314 | print_redundant_copies (void) | |
2315 | { | |
2316 | int hard_regno; | |
2317 | ira_allocno_t a; | |
2318 | ira_copy_t cp, next_cp; | |
2319 | ira_allocno_iterator ai; | |
b8698a0f | 2320 | |
058e97ec VM |
2321 | FOR_EACH_ALLOCNO (a, ai) |
2322 | { | |
2323 | if (ALLOCNO_CAP_MEMBER (a) != NULL) | |
2324 | /* It is a cap. */ | |
2325 | continue; | |
2326 | hard_regno = ALLOCNO_HARD_REGNO (a); | |
2327 | if (hard_regno >= 0) | |
2328 | continue; | |
2329 | for (cp = ALLOCNO_COPIES (a); cp != NULL; cp = next_cp) | |
2330 | if (cp->first == a) | |
2331 | next_cp = cp->next_first_allocno_copy; | |
2332 | else | |
2333 | { | |
2334 | next_cp = cp->next_second_allocno_copy; | |
2335 | if (internal_flag_ira_verbose > 4 && ira_dump_file != NULL | |
2336 | && cp->insn != NULL_RTX | |
2337 | && ALLOCNO_HARD_REGNO (cp->first) == hard_regno) | |
2338 | fprintf (ira_dump_file, | |
2339 | " Redundant move from %d(freq %d):%d\n", | |
2340 | INSN_UID (cp->insn), cp->freq, hard_regno); | |
2341 | } | |
2342 | } | |
2343 | } | |
2344 | #endif | |
2345 | ||
2346 | /* Setup preferred and alternative classes for new pseudo-registers | |
2347 | created by IRA starting with START. */ | |
2348 | static void | |
2349 | setup_preferred_alternate_classes_for_new_pseudos (int start) | |
2350 | { | |
2351 | int i, old_regno; | |
2352 | int max_regno = max_reg_num (); | |
2353 | ||
2354 | for (i = start; i < max_regno; i++) | |
2355 | { | |
2356 | old_regno = ORIGINAL_REGNO (regno_reg_rtx[i]); | |
b8698a0f | 2357 | ira_assert (i != old_regno); |
058e97ec | 2358 | setup_reg_classes (i, reg_preferred_class (old_regno), |
ce18efcb | 2359 | reg_alternate_class (old_regno), |
1756cb66 | 2360 | reg_allocno_class (old_regno)); |
058e97ec VM |
2361 | if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL) |
2362 | fprintf (ira_dump_file, | |
2363 | " New r%d: setting preferred %s, alternative %s\n", | |
2364 | i, reg_class_names[reg_preferred_class (old_regno)], | |
2365 | reg_class_names[reg_alternate_class (old_regno)]); | |
2366 | } | |
2367 | } | |
2368 | ||
2369 | \f | |
fb99ee9b BS |
2370 | /* The number of entries allocated in teg_info. */ |
2371 | static int allocated_reg_info_size; | |
058e97ec VM |
2372 | |
2373 | /* Regional allocation can create new pseudo-registers. This function | |
2374 | expands some arrays for pseudo-registers. */ | |
2375 | static void | |
fb99ee9b | 2376 | expand_reg_info (void) |
058e97ec VM |
2377 | { |
2378 | int i; | |
2379 | int size = max_reg_num (); | |
2380 | ||
2381 | resize_reg_info (); | |
fb99ee9b | 2382 | for (i = allocated_reg_info_size; i < size; i++) |
ce18efcb | 2383 | setup_reg_classes (i, GENERAL_REGS, ALL_REGS, GENERAL_REGS); |
fb99ee9b BS |
2384 | setup_preferred_alternate_classes_for_new_pseudos (allocated_reg_info_size); |
2385 | allocated_reg_info_size = size; | |
058e97ec VM |
2386 | } |
2387 | ||
3553f0bb VM |
2388 | /* Return TRUE if there is too high register pressure in the function. |
2389 | It is used to decide when stack slot sharing is worth to do. */ | |
2390 | static bool | |
2391 | too_high_register_pressure_p (void) | |
2392 | { | |
2393 | int i; | |
1756cb66 | 2394 | enum reg_class pclass; |
b8698a0f | 2395 | |
1756cb66 | 2396 | for (i = 0; i < ira_pressure_classes_num; i++) |
3553f0bb | 2397 | { |
1756cb66 VM |
2398 | pclass = ira_pressure_classes[i]; |
2399 | if (ira_loop_tree_root->reg_pressure[pclass] > 10000) | |
3553f0bb VM |
2400 | return true; |
2401 | } | |
2402 | return false; | |
2403 | } | |
2404 | ||
058e97ec VM |
2405 | \f |
2406 | ||
2af2dbdc VM |
2407 | /* Indicate that hard register number FROM was eliminated and replaced with |
2408 | an offset from hard register number TO. The status of hard registers live | |
2409 | at the start of a basic block is updated by replacing a use of FROM with | |
2410 | a use of TO. */ | |
2411 | ||
2412 | void | |
2413 | mark_elimination (int from, int to) | |
2414 | { | |
2415 | basic_block bb; | |
bf744527 | 2416 | bitmap r; |
2af2dbdc VM |
2417 | |
2418 | FOR_EACH_BB (bb) | |
2419 | { | |
bf744527 SB |
2420 | r = DF_LR_IN (bb); |
2421 | if (bitmap_bit_p (r, from)) | |
2422 | { | |
2423 | bitmap_clear_bit (r, from); | |
2424 | bitmap_set_bit (r, to); | |
2425 | } | |
2426 | if (! df_live) | |
2427 | continue; | |
2428 | r = DF_LIVE_IN (bb); | |
2429 | if (bitmap_bit_p (r, from)) | |
2af2dbdc | 2430 | { |
bf744527 SB |
2431 | bitmap_clear_bit (r, from); |
2432 | bitmap_set_bit (r, to); | |
2af2dbdc VM |
2433 | } |
2434 | } | |
2435 | } | |
2436 | ||
2437 | \f | |
2438 | ||
55a2c322 VM |
2439 | /* The length of the following array. */ |
2440 | int ira_reg_equiv_len; | |
2441 | ||
2442 | /* Info about equiv. info for each register. */ | |
2443 | struct ira_reg_equiv *ira_reg_equiv; | |
2444 | ||
2445 | /* Expand ira_reg_equiv if necessary. */ | |
2446 | void | |
2447 | ira_expand_reg_equiv (void) | |
2448 | { | |
2449 | int old = ira_reg_equiv_len; | |
2450 | ||
2451 | if (ira_reg_equiv_len > max_reg_num ()) | |
2452 | return; | |
2453 | ira_reg_equiv_len = max_reg_num () * 3 / 2 + 1; | |
2454 | ira_reg_equiv | |
2455 | = (struct ira_reg_equiv *) xrealloc (ira_reg_equiv, | |
2456 | ira_reg_equiv_len | |
2457 | * sizeof (struct ira_reg_equiv)); | |
2458 | gcc_assert (old < ira_reg_equiv_len); | |
2459 | memset (ira_reg_equiv + old, 0, | |
2460 | sizeof (struct ira_reg_equiv) * (ira_reg_equiv_len - old)); | |
2461 | } | |
2462 | ||
2463 | static void | |
2464 | init_reg_equiv (void) | |
2465 | { | |
2466 | ira_reg_equiv_len = 0; | |
2467 | ira_reg_equiv = NULL; | |
2468 | ira_expand_reg_equiv (); | |
2469 | } | |
2470 | ||
2471 | static void | |
2472 | finish_reg_equiv (void) | |
2473 | { | |
2474 | free (ira_reg_equiv); | |
2475 | } | |
2476 | ||
2477 | \f | |
2478 | ||
2af2dbdc VM |
2479 | struct equivalence |
2480 | { | |
2af2dbdc VM |
2481 | /* Set when a REG_EQUIV note is found or created. Use to |
2482 | keep track of what memory accesses might be created later, | |
2483 | e.g. by reload. */ | |
2484 | rtx replacement; | |
2485 | rtx *src_p; | |
8f5929e1 JJ |
2486 | /* The list of each instruction which initializes this register. */ |
2487 | rtx init_insns; | |
2af2dbdc VM |
2488 | /* Loop depth is used to recognize equivalences which appear |
2489 | to be present within the same loop (or in an inner loop). */ | |
2490 | int loop_depth; | |
2af2dbdc VM |
2491 | /* Nonzero if this had a preexisting REG_EQUIV note. */ |
2492 | int is_arg_equivalence; | |
8f5929e1 JJ |
2493 | /* Set when an attempt should be made to replace a register |
2494 | with the associated src_p entry. */ | |
2495 | char replace; | |
2af2dbdc VM |
2496 | }; |
2497 | ||
2498 | /* reg_equiv[N] (where N is a pseudo reg number) is the equivalence | |
2499 | structure for that register. */ | |
2500 | static struct equivalence *reg_equiv; | |
2501 | ||
2502 | /* Used for communication between the following two functions: contains | |
2503 | a MEM that we wish to ensure remains unchanged. */ | |
2504 | static rtx equiv_mem; | |
2505 | ||
2506 | /* Set nonzero if EQUIV_MEM is modified. */ | |
2507 | static int equiv_mem_modified; | |
2508 | ||
2509 | /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified. | |
2510 | Called via note_stores. */ | |
2511 | static void | |
2512 | validate_equiv_mem_from_store (rtx dest, const_rtx set ATTRIBUTE_UNUSED, | |
2513 | void *data ATTRIBUTE_UNUSED) | |
2514 | { | |
2515 | if ((REG_P (dest) | |
2516 | && reg_overlap_mentioned_p (dest, equiv_mem)) | |
2517 | || (MEM_P (dest) | |
53d9622b | 2518 | && true_dependence (dest, VOIDmode, equiv_mem))) |
2af2dbdc VM |
2519 | equiv_mem_modified = 1; |
2520 | } | |
2521 | ||
2522 | /* Verify that no store between START and the death of REG invalidates | |
2523 | MEMREF. MEMREF is invalidated by modifying a register used in MEMREF, | |
2524 | by storing into an overlapping memory location, or with a non-const | |
2525 | CALL_INSN. | |
2526 | ||
2527 | Return 1 if MEMREF remains valid. */ | |
2528 | static int | |
2529 | validate_equiv_mem (rtx start, rtx reg, rtx memref) | |
2530 | { | |
2531 | rtx insn; | |
2532 | rtx note; | |
2533 | ||
2534 | equiv_mem = memref; | |
2535 | equiv_mem_modified = 0; | |
2536 | ||
2537 | /* If the memory reference has side effects or is volatile, it isn't a | |
2538 | valid equivalence. */ | |
2539 | if (side_effects_p (memref)) | |
2540 | return 0; | |
2541 | ||
2542 | for (insn = start; insn && ! equiv_mem_modified; insn = NEXT_INSN (insn)) | |
2543 | { | |
2544 | if (! INSN_P (insn)) | |
2545 | continue; | |
2546 | ||
2547 | if (find_reg_note (insn, REG_DEAD, reg)) | |
2548 | return 1; | |
2549 | ||
a22265a4 JL |
2550 | /* This used to ignore readonly memory and const/pure calls. The problem |
2551 | is the equivalent form may reference a pseudo which gets assigned a | |
2552 | call clobbered hard reg. When we later replace REG with its | |
2553 | equivalent form, the value in the call-clobbered reg has been | |
2554 | changed and all hell breaks loose. */ | |
2555 | if (CALL_P (insn)) | |
2af2dbdc VM |
2556 | return 0; |
2557 | ||
2558 | note_stores (PATTERN (insn), validate_equiv_mem_from_store, NULL); | |
2559 | ||
2560 | /* If a register mentioned in MEMREF is modified via an | |
2561 | auto-increment, we lose the equivalence. Do the same if one | |
2562 | dies; although we could extend the life, it doesn't seem worth | |
2563 | the trouble. */ | |
2564 | ||
2565 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
2566 | if ((REG_NOTE_KIND (note) == REG_INC | |
2567 | || REG_NOTE_KIND (note) == REG_DEAD) | |
2568 | && REG_P (XEXP (note, 0)) | |
2569 | && reg_overlap_mentioned_p (XEXP (note, 0), memref)) | |
2570 | return 0; | |
2571 | } | |
2572 | ||
2573 | return 0; | |
2574 | } | |
2575 | ||
2576 | /* Returns zero if X is known to be invariant. */ | |
2577 | static int | |
2578 | equiv_init_varies_p (rtx x) | |
2579 | { | |
2580 | RTX_CODE code = GET_CODE (x); | |
2581 | int i; | |
2582 | const char *fmt; | |
2583 | ||
2584 | switch (code) | |
2585 | { | |
2586 | case MEM: | |
2587 | return !MEM_READONLY_P (x) || equiv_init_varies_p (XEXP (x, 0)); | |
2588 | ||
2589 | case CONST: | |
d8116890 | 2590 | CASE_CONST_ANY: |
2af2dbdc VM |
2591 | case SYMBOL_REF: |
2592 | case LABEL_REF: | |
2593 | return 0; | |
2594 | ||
2595 | case REG: | |
2596 | return reg_equiv[REGNO (x)].replace == 0 && rtx_varies_p (x, 0); | |
2597 | ||
2598 | case ASM_OPERANDS: | |
2599 | if (MEM_VOLATILE_P (x)) | |
2600 | return 1; | |
2601 | ||
2602 | /* Fall through. */ | |
2603 | ||
2604 | default: | |
2605 | break; | |
2606 | } | |
2607 | ||
2608 | fmt = GET_RTX_FORMAT (code); | |
2609 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2610 | if (fmt[i] == 'e') | |
2611 | { | |
2612 | if (equiv_init_varies_p (XEXP (x, i))) | |
2613 | return 1; | |
2614 | } | |
2615 | else if (fmt[i] == 'E') | |
2616 | { | |
2617 | int j; | |
2618 | for (j = 0; j < XVECLEN (x, i); j++) | |
2619 | if (equiv_init_varies_p (XVECEXP (x, i, j))) | |
2620 | return 1; | |
2621 | } | |
2622 | ||
2623 | return 0; | |
2624 | } | |
2625 | ||
2626 | /* Returns nonzero if X (used to initialize register REGNO) is movable. | |
2627 | X is only movable if the registers it uses have equivalent initializations | |
2628 | which appear to be within the same loop (or in an inner loop) and movable | |
2629 | or if they are not candidates for local_alloc and don't vary. */ | |
2630 | static int | |
2631 | equiv_init_movable_p (rtx x, int regno) | |
2632 | { | |
2633 | int i, j; | |
2634 | const char *fmt; | |
2635 | enum rtx_code code = GET_CODE (x); | |
2636 | ||
2637 | switch (code) | |
2638 | { | |
2639 | case SET: | |
2640 | return equiv_init_movable_p (SET_SRC (x), regno); | |
2641 | ||
2642 | case CC0: | |
2643 | case CLOBBER: | |
2644 | return 0; | |
2645 | ||
2646 | case PRE_INC: | |
2647 | case PRE_DEC: | |
2648 | case POST_INC: | |
2649 | case POST_DEC: | |
2650 | case PRE_MODIFY: | |
2651 | case POST_MODIFY: | |
2652 | return 0; | |
2653 | ||
2654 | case REG: | |
1756cb66 VM |
2655 | return ((reg_equiv[REGNO (x)].loop_depth >= reg_equiv[regno].loop_depth |
2656 | && reg_equiv[REGNO (x)].replace) | |
2657 | || (REG_BASIC_BLOCK (REGNO (x)) < NUM_FIXED_BLOCKS | |
2658 | && ! rtx_varies_p (x, 0))); | |
2af2dbdc VM |
2659 | |
2660 | case UNSPEC_VOLATILE: | |
2661 | return 0; | |
2662 | ||
2663 | case ASM_OPERANDS: | |
2664 | if (MEM_VOLATILE_P (x)) | |
2665 | return 0; | |
2666 | ||
2667 | /* Fall through. */ | |
2668 | ||
2669 | default: | |
2670 | break; | |
2671 | } | |
2672 | ||
2673 | fmt = GET_RTX_FORMAT (code); | |
2674 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2675 | switch (fmt[i]) | |
2676 | { | |
2677 | case 'e': | |
2678 | if (! equiv_init_movable_p (XEXP (x, i), regno)) | |
2679 | return 0; | |
2680 | break; | |
2681 | case 'E': | |
2682 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
2683 | if (! equiv_init_movable_p (XVECEXP (x, i, j), regno)) | |
2684 | return 0; | |
2685 | break; | |
2686 | } | |
2687 | ||
2688 | return 1; | |
2689 | } | |
2690 | ||
1756cb66 VM |
2691 | /* TRUE if X uses any registers for which reg_equiv[REGNO].replace is |
2692 | true. */ | |
2af2dbdc VM |
2693 | static int |
2694 | contains_replace_regs (rtx x) | |
2695 | { | |
2696 | int i, j; | |
2697 | const char *fmt; | |
2698 | enum rtx_code code = GET_CODE (x); | |
2699 | ||
2700 | switch (code) | |
2701 | { | |
2af2dbdc VM |
2702 | case CONST: |
2703 | case LABEL_REF: | |
2704 | case SYMBOL_REF: | |
d8116890 | 2705 | CASE_CONST_ANY: |
2af2dbdc VM |
2706 | case PC: |
2707 | case CC0: | |
2708 | case HIGH: | |
2709 | return 0; | |
2710 | ||
2711 | case REG: | |
2712 | return reg_equiv[REGNO (x)].replace; | |
2713 | ||
2714 | default: | |
2715 | break; | |
2716 | } | |
2717 | ||
2718 | fmt = GET_RTX_FORMAT (code); | |
2719 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2720 | switch (fmt[i]) | |
2721 | { | |
2722 | case 'e': | |
2723 | if (contains_replace_regs (XEXP (x, i))) | |
2724 | return 1; | |
2725 | break; | |
2726 | case 'E': | |
2727 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
2728 | if (contains_replace_regs (XVECEXP (x, i, j))) | |
2729 | return 1; | |
2730 | break; | |
2731 | } | |
2732 | ||
2733 | return 0; | |
2734 | } | |
2735 | ||
2736 | /* TRUE if X references a memory location that would be affected by a store | |
2737 | to MEMREF. */ | |
2738 | static int | |
2739 | memref_referenced_p (rtx memref, rtx x) | |
2740 | { | |
2741 | int i, j; | |
2742 | const char *fmt; | |
2743 | enum rtx_code code = GET_CODE (x); | |
2744 | ||
2745 | switch (code) | |
2746 | { | |
2af2dbdc VM |
2747 | case CONST: |
2748 | case LABEL_REF: | |
2749 | case SYMBOL_REF: | |
d8116890 | 2750 | CASE_CONST_ANY: |
2af2dbdc VM |
2751 | case PC: |
2752 | case CC0: | |
2753 | case HIGH: | |
2754 | case LO_SUM: | |
2755 | return 0; | |
2756 | ||
2757 | case REG: | |
2758 | return (reg_equiv[REGNO (x)].replacement | |
2759 | && memref_referenced_p (memref, | |
2760 | reg_equiv[REGNO (x)].replacement)); | |
2761 | ||
2762 | case MEM: | |
53d9622b | 2763 | if (true_dependence (memref, VOIDmode, x)) |
2af2dbdc VM |
2764 | return 1; |
2765 | break; | |
2766 | ||
2767 | case SET: | |
2768 | /* If we are setting a MEM, it doesn't count (its address does), but any | |
2769 | other SET_DEST that has a MEM in it is referencing the MEM. */ | |
2770 | if (MEM_P (SET_DEST (x))) | |
2771 | { | |
2772 | if (memref_referenced_p (memref, XEXP (SET_DEST (x), 0))) | |
2773 | return 1; | |
2774 | } | |
2775 | else if (memref_referenced_p (memref, SET_DEST (x))) | |
2776 | return 1; | |
2777 | ||
2778 | return memref_referenced_p (memref, SET_SRC (x)); | |
2779 | ||
2780 | default: | |
2781 | break; | |
2782 | } | |
2783 | ||
2784 | fmt = GET_RTX_FORMAT (code); | |
2785 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2786 | switch (fmt[i]) | |
2787 | { | |
2788 | case 'e': | |
2789 | if (memref_referenced_p (memref, XEXP (x, i))) | |
2790 | return 1; | |
2791 | break; | |
2792 | case 'E': | |
2793 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
2794 | if (memref_referenced_p (memref, XVECEXP (x, i, j))) | |
2795 | return 1; | |
2796 | break; | |
2797 | } | |
2798 | ||
2799 | return 0; | |
2800 | } | |
2801 | ||
2802 | /* TRUE if some insn in the range (START, END] references a memory location | |
2803 | that would be affected by a store to MEMREF. */ | |
2804 | static int | |
2805 | memref_used_between_p (rtx memref, rtx start, rtx end) | |
2806 | { | |
2807 | rtx insn; | |
2808 | ||
2809 | for (insn = NEXT_INSN (start); insn != NEXT_INSN (end); | |
2810 | insn = NEXT_INSN (insn)) | |
2811 | { | |
b5b8b0ac | 2812 | if (!NONDEBUG_INSN_P (insn)) |
2af2dbdc | 2813 | continue; |
b8698a0f | 2814 | |
2af2dbdc VM |
2815 | if (memref_referenced_p (memref, PATTERN (insn))) |
2816 | return 1; | |
2817 | ||
2818 | /* Nonconst functions may access memory. */ | |
2819 | if (CALL_P (insn) && (! RTL_CONST_CALL_P (insn))) | |
2820 | return 1; | |
2821 | } | |
2822 | ||
2823 | return 0; | |
2824 | } | |
2825 | ||
2826 | /* Mark REG as having no known equivalence. | |
2827 | Some instructions might have been processed before and furnished | |
2828 | with REG_EQUIV notes for this register; these notes will have to be | |
2829 | removed. | |
2830 | STORE is the piece of RTL that does the non-constant / conflicting | |
2831 | assignment - a SET, CLOBBER or REG_INC note. It is currently not used, | |
2832 | but needs to be there because this function is called from note_stores. */ | |
2833 | static void | |
1756cb66 VM |
2834 | no_equiv (rtx reg, const_rtx store ATTRIBUTE_UNUSED, |
2835 | void *data ATTRIBUTE_UNUSED) | |
2af2dbdc VM |
2836 | { |
2837 | int regno; | |
2838 | rtx list; | |
2839 | ||
2840 | if (!REG_P (reg)) | |
2841 | return; | |
2842 | regno = REGNO (reg); | |
2843 | list = reg_equiv[regno].init_insns; | |
2844 | if (list == const0_rtx) | |
2845 | return; | |
2846 | reg_equiv[regno].init_insns = const0_rtx; | |
2847 | reg_equiv[regno].replacement = NULL_RTX; | |
2848 | /* This doesn't matter for equivalences made for argument registers, we | |
2849 | should keep their initialization insns. */ | |
2850 | if (reg_equiv[regno].is_arg_equivalence) | |
2851 | return; | |
55a2c322 VM |
2852 | ira_reg_equiv[regno].defined_p = false; |
2853 | ira_reg_equiv[regno].init_insns = NULL_RTX; | |
2af2dbdc VM |
2854 | for (; list; list = XEXP (list, 1)) |
2855 | { | |
2856 | rtx insn = XEXP (list, 0); | |
2857 | remove_note (insn, find_reg_note (insn, REG_EQUIV, NULL_RTX)); | |
2858 | } | |
2859 | } | |
2860 | ||
3a6191b1 JJ |
2861 | /* In DEBUG_INSN location adjust REGs from CLEARED_REGS bitmap to the |
2862 | equivalent replacement. */ | |
2863 | ||
2864 | static rtx | |
2865 | adjust_cleared_regs (rtx loc, const_rtx old_rtx ATTRIBUTE_UNUSED, void *data) | |
2866 | { | |
2867 | if (REG_P (loc)) | |
2868 | { | |
2869 | bitmap cleared_regs = (bitmap) data; | |
2870 | if (bitmap_bit_p (cleared_regs, REGNO (loc))) | |
2871 | return simplify_replace_fn_rtx (*reg_equiv[REGNO (loc)].src_p, | |
2872 | NULL_RTX, adjust_cleared_regs, data); | |
2873 | } | |
2874 | return NULL_RTX; | |
2875 | } | |
2876 | ||
2af2dbdc VM |
2877 | /* Nonzero if we recorded an equivalence for a LABEL_REF. */ |
2878 | static int recorded_label_ref; | |
2879 | ||
2880 | /* Find registers that are equivalent to a single value throughout the | |
1756cb66 VM |
2881 | compilation (either because they can be referenced in memory or are |
2882 | set once from a single constant). Lower their priority for a | |
2883 | register. | |
2af2dbdc | 2884 | |
1756cb66 VM |
2885 | If such a register is only referenced once, try substituting its |
2886 | value into the using insn. If it succeeds, we can eliminate the | |
2887 | register completely. | |
2af2dbdc | 2888 | |
55a2c322 | 2889 | Initialize init_insns in ira_reg_equiv array. |
2af2dbdc VM |
2890 | |
2891 | Return non-zero if jump label rebuilding should be done. */ | |
2892 | static int | |
2893 | update_equiv_regs (void) | |
2894 | { | |
2895 | rtx insn; | |
2896 | basic_block bb; | |
2897 | int loop_depth; | |
2898 | bitmap cleared_regs; | |
b8698a0f | 2899 | |
2af2dbdc VM |
2900 | /* We need to keep track of whether or not we recorded a LABEL_REF so |
2901 | that we know if the jump optimizer needs to be rerun. */ | |
2902 | recorded_label_ref = 0; | |
2903 | ||
2904 | reg_equiv = XCNEWVEC (struct equivalence, max_regno); | |
f2034d06 | 2905 | grow_reg_equivs (); |
2af2dbdc VM |
2906 | |
2907 | init_alias_analysis (); | |
2908 | ||
2909 | /* Scan the insns and find which registers have equivalences. Do this | |
2910 | in a separate scan of the insns because (due to -fcse-follow-jumps) | |
2911 | a register can be set below its use. */ | |
2912 | FOR_EACH_BB (bb) | |
2913 | { | |
391886c8 | 2914 | loop_depth = bb_loop_depth (bb); |
2af2dbdc VM |
2915 | |
2916 | for (insn = BB_HEAD (bb); | |
2917 | insn != NEXT_INSN (BB_END (bb)); | |
2918 | insn = NEXT_INSN (insn)) | |
2919 | { | |
2920 | rtx note; | |
2921 | rtx set; | |
2922 | rtx dest, src; | |
2923 | int regno; | |
2924 | ||
2925 | if (! INSN_P (insn)) | |
2926 | continue; | |
2927 | ||
2928 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
2929 | if (REG_NOTE_KIND (note) == REG_INC) | |
2930 | no_equiv (XEXP (note, 0), note, NULL); | |
2931 | ||
2932 | set = single_set (insn); | |
2933 | ||
2934 | /* If this insn contains more (or less) than a single SET, | |
2935 | only mark all destinations as having no known equivalence. */ | |
2936 | if (set == 0) | |
2937 | { | |
2938 | note_stores (PATTERN (insn), no_equiv, NULL); | |
2939 | continue; | |
2940 | } | |
2941 | else if (GET_CODE (PATTERN (insn)) == PARALLEL) | |
2942 | { | |
2943 | int i; | |
2944 | ||
2945 | for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--) | |
2946 | { | |
2947 | rtx part = XVECEXP (PATTERN (insn), 0, i); | |
2948 | if (part != set) | |
2949 | note_stores (part, no_equiv, NULL); | |
2950 | } | |
2951 | } | |
2952 | ||
2953 | dest = SET_DEST (set); | |
2954 | src = SET_SRC (set); | |
2955 | ||
2956 | /* See if this is setting up the equivalence between an argument | |
2957 | register and its stack slot. */ | |
2958 | note = find_reg_note (insn, REG_EQUIV, NULL_RTX); | |
2959 | if (note) | |
2960 | { | |
2961 | gcc_assert (REG_P (dest)); | |
2962 | regno = REGNO (dest); | |
2963 | ||
55a2c322 VM |
2964 | /* Note that we don't want to clear init_insns in |
2965 | ira_reg_equiv even if there are multiple sets of this | |
2966 | register. */ | |
2af2dbdc VM |
2967 | reg_equiv[regno].is_arg_equivalence = 1; |
2968 | ||
2969 | /* Record for reload that this is an equivalencing insn. */ | |
2970 | if (rtx_equal_p (src, XEXP (note, 0))) | |
55a2c322 VM |
2971 | ira_reg_equiv[regno].init_insns |
2972 | = gen_rtx_INSN_LIST (VOIDmode, insn, | |
2973 | ira_reg_equiv[regno].init_insns); | |
2af2dbdc VM |
2974 | |
2975 | /* Continue normally in case this is a candidate for | |
2976 | replacements. */ | |
2977 | } | |
2978 | ||
2979 | if (!optimize) | |
2980 | continue; | |
2981 | ||
2982 | /* We only handle the case of a pseudo register being set | |
2983 | once, or always to the same value. */ | |
1fe28116 VM |
2984 | /* ??? The mn10200 port breaks if we add equivalences for |
2985 | values that need an ADDRESS_REGS register and set them equivalent | |
2986 | to a MEM of a pseudo. The actual problem is in the over-conservative | |
2987 | handling of INPADDR_ADDRESS / INPUT_ADDRESS / INPUT triples in | |
2988 | calculate_needs, but we traditionally work around this problem | |
2989 | here by rejecting equivalences when the destination is in a register | |
2990 | that's likely spilled. This is fragile, of course, since the | |
2991 | preferred class of a pseudo depends on all instructions that set | |
2992 | or use it. */ | |
2993 | ||
2af2dbdc VM |
2994 | if (!REG_P (dest) |
2995 | || (regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER | |
1fe28116 | 2996 | || reg_equiv[regno].init_insns == const0_rtx |
07b8f0a8 | 2997 | || (targetm.class_likely_spilled_p (reg_preferred_class (regno)) |
1fe28116 | 2998 | && MEM_P (src) && ! reg_equiv[regno].is_arg_equivalence)) |
2af2dbdc VM |
2999 | { |
3000 | /* This might be setting a SUBREG of a pseudo, a pseudo that is | |
3001 | also set somewhere else to a constant. */ | |
3002 | note_stores (set, no_equiv, NULL); | |
3003 | continue; | |
3004 | } | |
3005 | ||
3006 | note = find_reg_note (insn, REG_EQUAL, NULL_RTX); | |
3007 | ||
3008 | /* cse sometimes generates function invariants, but doesn't put a | |
3009 | REG_EQUAL note on the insn. Since this note would be redundant, | |
3010 | there's no point creating it earlier than here. */ | |
3011 | if (! note && ! rtx_varies_p (src, 0)) | |
3012 | note = set_unique_reg_note (insn, REG_EQUAL, copy_rtx (src)); | |
3013 | ||
3014 | /* Don't bother considering a REG_EQUAL note containing an EXPR_LIST | |
3015 | since it represents a function call */ | |
3016 | if (note && GET_CODE (XEXP (note, 0)) == EXPR_LIST) | |
3017 | note = NULL_RTX; | |
3018 | ||
3019 | if (DF_REG_DEF_COUNT (regno) != 1 | |
3020 | && (! note | |
3021 | || rtx_varies_p (XEXP (note, 0), 0) | |
3022 | || (reg_equiv[regno].replacement | |
3023 | && ! rtx_equal_p (XEXP (note, 0), | |
3024 | reg_equiv[regno].replacement)))) | |
3025 | { | |
3026 | no_equiv (dest, set, NULL); | |
3027 | continue; | |
3028 | } | |
3029 | /* Record this insn as initializing this register. */ | |
3030 | reg_equiv[regno].init_insns | |
3031 | = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv[regno].init_insns); | |
3032 | ||
3033 | /* If this register is known to be equal to a constant, record that | |
3034 | it is always equivalent to the constant. */ | |
3035 | if (DF_REG_DEF_COUNT (regno) == 1 | |
3036 | && note && ! rtx_varies_p (XEXP (note, 0), 0)) | |
3037 | { | |
3038 | rtx note_value = XEXP (note, 0); | |
3039 | remove_note (insn, note); | |
3040 | set_unique_reg_note (insn, REG_EQUIV, note_value); | |
3041 | } | |
3042 | ||
3043 | /* If this insn introduces a "constant" register, decrease the priority | |
3044 | of that register. Record this insn if the register is only used once | |
3045 | more and the equivalence value is the same as our source. | |
3046 | ||
3047 | The latter condition is checked for two reasons: First, it is an | |
3048 | indication that it may be more efficient to actually emit the insn | |
3049 | as written (if no registers are available, reload will substitute | |
3050 | the equivalence). Secondly, it avoids problems with any registers | |
3051 | dying in this insn whose death notes would be missed. | |
3052 | ||
3053 | If we don't have a REG_EQUIV note, see if this insn is loading | |
3054 | a register used only in one basic block from a MEM. If so, and the | |
3055 | MEM remains unchanged for the life of the register, add a REG_EQUIV | |
3056 | note. */ | |
3057 | ||
3058 | note = find_reg_note (insn, REG_EQUIV, NULL_RTX); | |
3059 | ||
3060 | if (note == 0 && REG_BASIC_BLOCK (regno) >= NUM_FIXED_BLOCKS | |
3061 | && MEM_P (SET_SRC (set)) | |
3062 | && validate_equiv_mem (insn, dest, SET_SRC (set))) | |
3063 | note = set_unique_reg_note (insn, REG_EQUIV, copy_rtx (SET_SRC (set))); | |
3064 | ||
3065 | if (note) | |
3066 | { | |
3067 | int regno = REGNO (dest); | |
3068 | rtx x = XEXP (note, 0); | |
3069 | ||
3070 | /* If we haven't done so, record for reload that this is an | |
3071 | equivalencing insn. */ | |
3072 | if (!reg_equiv[regno].is_arg_equivalence) | |
55a2c322 VM |
3073 | ira_reg_equiv[regno].init_insns |
3074 | = gen_rtx_INSN_LIST (VOIDmode, insn, | |
3075 | ira_reg_equiv[regno].init_insns); | |
2af2dbdc VM |
3076 | |
3077 | /* Record whether or not we created a REG_EQUIV note for a LABEL_REF. | |
3078 | We might end up substituting the LABEL_REF for uses of the | |
3079 | pseudo here or later. That kind of transformation may turn an | |
3080 | indirect jump into a direct jump, in which case we must rerun the | |
3081 | jump optimizer to ensure that the JUMP_LABEL fields are valid. */ | |
3082 | if (GET_CODE (x) == LABEL_REF | |
3083 | || (GET_CODE (x) == CONST | |
3084 | && GET_CODE (XEXP (x, 0)) == PLUS | |
3085 | && (GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF))) | |
3086 | recorded_label_ref = 1; | |
3087 | ||
3088 | reg_equiv[regno].replacement = x; | |
3089 | reg_equiv[regno].src_p = &SET_SRC (set); | |
3090 | reg_equiv[regno].loop_depth = loop_depth; | |
3091 | ||
3092 | /* Don't mess with things live during setjmp. */ | |
3093 | if (REG_LIVE_LENGTH (regno) >= 0 && optimize) | |
3094 | { | |
3095 | /* Note that the statement below does not affect the priority | |
3096 | in local-alloc! */ | |
3097 | REG_LIVE_LENGTH (regno) *= 2; | |
3098 | ||
3099 | /* If the register is referenced exactly twice, meaning it is | |
3100 | set once and used once, indicate that the reference may be | |
3101 | replaced by the equivalence we computed above. Do this | |
3102 | even if the register is only used in one block so that | |
3103 | dependencies can be handled where the last register is | |
3104 | used in a different block (i.e. HIGH / LO_SUM sequences) | |
3105 | and to reduce the number of registers alive across | |
3106 | calls. */ | |
3107 | ||
3108 | if (REG_N_REFS (regno) == 2 | |
3109 | && (rtx_equal_p (x, src) | |
3110 | || ! equiv_init_varies_p (src)) | |
3111 | && NONJUMP_INSN_P (insn) | |
3112 | && equiv_init_movable_p (PATTERN (insn), regno)) | |
3113 | reg_equiv[regno].replace = 1; | |
3114 | } | |
3115 | } | |
3116 | } | |
3117 | } | |
3118 | ||
3119 | if (!optimize) | |
3120 | goto out; | |
3121 | ||
3122 | /* A second pass, to gather additional equivalences with memory. This needs | |
3123 | to be done after we know which registers we are going to replace. */ | |
3124 | ||
3125 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
3126 | { | |
3127 | rtx set, src, dest; | |
3128 | unsigned regno; | |
3129 | ||
3130 | if (! INSN_P (insn)) | |
3131 | continue; | |
3132 | ||
3133 | set = single_set (insn); | |
3134 | if (! set) | |
3135 | continue; | |
3136 | ||
3137 | dest = SET_DEST (set); | |
3138 | src = SET_SRC (set); | |
3139 | ||
3140 | /* If this sets a MEM to the contents of a REG that is only used | |
3141 | in a single basic block, see if the register is always equivalent | |
3142 | to that memory location and if moving the store from INSN to the | |
3143 | insn that set REG is safe. If so, put a REG_EQUIV note on the | |
3144 | initializing insn. | |
3145 | ||
3146 | Don't add a REG_EQUIV note if the insn already has one. The existing | |
3147 | REG_EQUIV is likely more useful than the one we are adding. | |
3148 | ||
3149 | If one of the regs in the address has reg_equiv[REGNO].replace set, | |
3150 | then we can't add this REG_EQUIV note. The reg_equiv[REGNO].replace | |
3151 | optimization may move the set of this register immediately before | |
3152 | insn, which puts it after reg_equiv[REGNO].init_insns, and hence | |
3153 | the mention in the REG_EQUIV note would be to an uninitialized | |
3154 | pseudo. */ | |
3155 | ||
3156 | if (MEM_P (dest) && REG_P (src) | |
3157 | && (regno = REGNO (src)) >= FIRST_PSEUDO_REGISTER | |
3158 | && REG_BASIC_BLOCK (regno) >= NUM_FIXED_BLOCKS | |
3159 | && DF_REG_DEF_COUNT (regno) == 1 | |
3160 | && reg_equiv[regno].init_insns != 0 | |
3161 | && reg_equiv[regno].init_insns != const0_rtx | |
3162 | && ! find_reg_note (XEXP (reg_equiv[regno].init_insns, 0), | |
3163 | REG_EQUIV, NULL_RTX) | |
3164 | && ! contains_replace_regs (XEXP (dest, 0))) | |
3165 | { | |
3166 | rtx init_insn = XEXP (reg_equiv[regno].init_insns, 0); | |
3167 | if (validate_equiv_mem (init_insn, src, dest) | |
3168 | && ! memref_used_between_p (dest, init_insn, insn) | |
3169 | /* Attaching a REG_EQUIV note will fail if INIT_INSN has | |
3170 | multiple sets. */ | |
3171 | && set_unique_reg_note (init_insn, REG_EQUIV, copy_rtx (dest))) | |
3172 | { | |
3173 | /* This insn makes the equivalence, not the one initializing | |
3174 | the register. */ | |
55a2c322 | 3175 | ira_reg_equiv[regno].init_insns |
2af2dbdc VM |
3176 | = gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX); |
3177 | df_notes_rescan (init_insn); | |
3178 | } | |
3179 | } | |
3180 | } | |
3181 | ||
3182 | cleared_regs = BITMAP_ALLOC (NULL); | |
3183 | /* Now scan all regs killed in an insn to see if any of them are | |
3184 | registers only used that once. If so, see if we can replace the | |
3185 | reference with the equivalent form. If we can, delete the | |
3186 | initializing reference and this register will go away. If we | |
3187 | can't replace the reference, and the initializing reference is | |
3188 | within the same loop (or in an inner loop), then move the register | |
3189 | initialization just before the use, so that they are in the same | |
3190 | basic block. */ | |
3191 | FOR_EACH_BB_REVERSE (bb) | |
3192 | { | |
391886c8 | 3193 | loop_depth = bb_loop_depth (bb); |
2af2dbdc VM |
3194 | for (insn = BB_END (bb); |
3195 | insn != PREV_INSN (BB_HEAD (bb)); | |
3196 | insn = PREV_INSN (insn)) | |
3197 | { | |
3198 | rtx link; | |
3199 | ||
3200 | if (! INSN_P (insn)) | |
3201 | continue; | |
3202 | ||
3203 | /* Don't substitute into a non-local goto, this confuses CFG. */ | |
3204 | if (JUMP_P (insn) | |
3205 | && find_reg_note (insn, REG_NON_LOCAL_GOTO, NULL_RTX)) | |
3206 | continue; | |
3207 | ||
3208 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | |
3209 | { | |
3210 | if (REG_NOTE_KIND (link) == REG_DEAD | |
3211 | /* Make sure this insn still refers to the register. */ | |
3212 | && reg_mentioned_p (XEXP (link, 0), PATTERN (insn))) | |
3213 | { | |
3214 | int regno = REGNO (XEXP (link, 0)); | |
3215 | rtx equiv_insn; | |
3216 | ||
3217 | if (! reg_equiv[regno].replace | |
0cad4827 VM |
3218 | || reg_equiv[regno].loop_depth < loop_depth |
3219 | /* There is no sense to move insns if we did | |
3220 | register pressure-sensitive scheduling was | |
3221 | done because it will not improve allocation | |
3222 | but worsen insn schedule with a big | |
3223 | probability. */ | |
3224 | || (flag_sched_pressure && flag_schedule_insns)) | |
2af2dbdc VM |
3225 | continue; |
3226 | ||
3227 | /* reg_equiv[REGNO].replace gets set only when | |
3228 | REG_N_REFS[REGNO] is 2, i.e. the register is set | |
55a2c322 VM |
3229 | once and used once. (If it were only set, but |
3230 | not used, flow would have deleted the setting | |
3231 | insns.) Hence there can only be one insn in | |
3232 | reg_equiv[REGNO].init_insns. */ | |
2af2dbdc VM |
3233 | gcc_assert (reg_equiv[regno].init_insns |
3234 | && !XEXP (reg_equiv[regno].init_insns, 1)); | |
3235 | equiv_insn = XEXP (reg_equiv[regno].init_insns, 0); | |
3236 | ||
3237 | /* We may not move instructions that can throw, since | |
3238 | that changes basic block boundaries and we are not | |
3239 | prepared to adjust the CFG to match. */ | |
3240 | if (can_throw_internal (equiv_insn)) | |
3241 | continue; | |
3242 | ||
3243 | if (asm_noperands (PATTERN (equiv_insn)) < 0 | |
3244 | && validate_replace_rtx (regno_reg_rtx[regno], | |
3245 | *(reg_equiv[regno].src_p), insn)) | |
3246 | { | |
3247 | rtx equiv_link; | |
3248 | rtx last_link; | |
3249 | rtx note; | |
3250 | ||
3251 | /* Find the last note. */ | |
3252 | for (last_link = link; XEXP (last_link, 1); | |
3253 | last_link = XEXP (last_link, 1)) | |
3254 | ; | |
3255 | ||
3256 | /* Append the REG_DEAD notes from equiv_insn. */ | |
3257 | equiv_link = REG_NOTES (equiv_insn); | |
3258 | while (equiv_link) | |
3259 | { | |
3260 | note = equiv_link; | |
3261 | equiv_link = XEXP (equiv_link, 1); | |
3262 | if (REG_NOTE_KIND (note) == REG_DEAD) | |
3263 | { | |
3264 | remove_note (equiv_insn, note); | |
3265 | XEXP (last_link, 1) = note; | |
3266 | XEXP (note, 1) = NULL_RTX; | |
3267 | last_link = note; | |
3268 | } | |
3269 | } | |
3270 | ||
3271 | remove_death (regno, insn); | |
3272 | SET_REG_N_REFS (regno, 0); | |
3273 | REG_FREQ (regno) = 0; | |
3274 | delete_insn (equiv_insn); | |
3275 | ||
3276 | reg_equiv[regno].init_insns | |
3277 | = XEXP (reg_equiv[regno].init_insns, 1); | |
3278 | ||
55a2c322 | 3279 | ira_reg_equiv[regno].init_insns = NULL_RTX; |
2af2dbdc VM |
3280 | bitmap_set_bit (cleared_regs, regno); |
3281 | } | |
3282 | /* Move the initialization of the register to just before | |
3283 | INSN. Update the flow information. */ | |
b5b8b0ac | 3284 | else if (prev_nondebug_insn (insn) != equiv_insn) |
2af2dbdc VM |
3285 | { |
3286 | rtx new_insn; | |
3287 | ||
3288 | new_insn = emit_insn_before (PATTERN (equiv_insn), insn); | |
3289 | REG_NOTES (new_insn) = REG_NOTES (equiv_insn); | |
3290 | REG_NOTES (equiv_insn) = 0; | |
3291 | /* Rescan it to process the notes. */ | |
3292 | df_insn_rescan (new_insn); | |
3293 | ||
3294 | /* Make sure this insn is recognized before | |
3295 | reload begins, otherwise | |
3296 | eliminate_regs_in_insn will die. */ | |
3297 | INSN_CODE (new_insn) = INSN_CODE (equiv_insn); | |
3298 | ||
3299 | delete_insn (equiv_insn); | |
3300 | ||
3301 | XEXP (reg_equiv[regno].init_insns, 0) = new_insn; | |
3302 | ||
3303 | REG_BASIC_BLOCK (regno) = bb->index; | |
3304 | REG_N_CALLS_CROSSED (regno) = 0; | |
3305 | REG_FREQ_CALLS_CROSSED (regno) = 0; | |
3306 | REG_N_THROWING_CALLS_CROSSED (regno) = 0; | |
3307 | REG_LIVE_LENGTH (regno) = 2; | |
3308 | ||
3309 | if (insn == BB_HEAD (bb)) | |
3310 | BB_HEAD (bb) = PREV_INSN (insn); | |
3311 | ||
55a2c322 | 3312 | ira_reg_equiv[regno].init_insns |
2af2dbdc VM |
3313 | = gen_rtx_INSN_LIST (VOIDmode, new_insn, NULL_RTX); |
3314 | bitmap_set_bit (cleared_regs, regno); | |
3315 | } | |
3316 | } | |
3317 | } | |
3318 | } | |
3319 | } | |
3320 | ||
3321 | if (!bitmap_empty_p (cleared_regs)) | |
3a6191b1 JJ |
3322 | { |
3323 | FOR_EACH_BB (bb) | |
3324 | { | |
3a6191b1 JJ |
3325 | bitmap_and_compl_into (DF_LR_IN (bb), cleared_regs); |
3326 | bitmap_and_compl_into (DF_LR_OUT (bb), cleared_regs); | |
bf744527 SB |
3327 | if (! df_live) |
3328 | continue; | |
3329 | bitmap_and_compl_into (DF_LIVE_IN (bb), cleared_regs); | |
3330 | bitmap_and_compl_into (DF_LIVE_OUT (bb), cleared_regs); | |
3a6191b1 JJ |
3331 | } |
3332 | ||
3333 | /* Last pass - adjust debug insns referencing cleared regs. */ | |
3334 | if (MAY_HAVE_DEBUG_INSNS) | |
3335 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
3336 | if (DEBUG_INSN_P (insn)) | |
3337 | { | |
3338 | rtx old_loc = INSN_VAR_LOCATION_LOC (insn); | |
3339 | INSN_VAR_LOCATION_LOC (insn) | |
3340 | = simplify_replace_fn_rtx (old_loc, NULL_RTX, | |
3341 | adjust_cleared_regs, | |
3342 | (void *) cleared_regs); | |
3343 | if (old_loc != INSN_VAR_LOCATION_LOC (insn)) | |
3344 | df_insn_rescan (insn); | |
3345 | } | |
3346 | } | |
2af2dbdc VM |
3347 | |
3348 | BITMAP_FREE (cleared_regs); | |
3349 | ||
3350 | out: | |
3351 | /* Clean up. */ | |
3352 | ||
3353 | end_alias_analysis (); | |
3354 | free (reg_equiv); | |
3355 | return recorded_label_ref; | |
3356 | } | |
3357 | ||
3358 | \f | |
3359 | ||
55a2c322 VM |
3360 | /* Set up fields memory, constant, and invariant from init_insns in |
3361 | the structures of array ira_reg_equiv. */ | |
3362 | static void | |
3363 | setup_reg_equiv (void) | |
3364 | { | |
3365 | int i; | |
3366 | rtx elem, insn, set, x; | |
3367 | ||
3368 | for (i = FIRST_PSEUDO_REGISTER; i < ira_reg_equiv_len; i++) | |
3369 | for (elem = ira_reg_equiv[i].init_insns; elem; elem = XEXP (elem, 1)) | |
3370 | { | |
3371 | insn = XEXP (elem, 0); | |
3372 | set = single_set (insn); | |
3373 | ||
3374 | /* Init insns can set up equivalence when the reg is a destination or | |
3375 | a source (in this case the destination is memory). */ | |
3376 | if (set != 0 && (REG_P (SET_DEST (set)) || REG_P (SET_SRC (set)))) | |
3377 | { | |
3378 | if ((x = find_reg_note (insn, REG_EQUIV, NULL_RTX)) != NULL) | |
3379 | x = XEXP (x, 0); | |
3380 | else if (REG_P (SET_DEST (set)) | |
3381 | && REGNO (SET_DEST (set)) == (unsigned int) i) | |
3382 | x = SET_SRC (set); | |
3383 | else | |
3384 | { | |
3385 | gcc_assert (REG_P (SET_SRC (set)) | |
3386 | && REGNO (SET_SRC (set)) == (unsigned int) i); | |
3387 | x = SET_DEST (set); | |
3388 | } | |
3389 | if (! function_invariant_p (x) | |
3390 | || ! flag_pic | |
3391 | /* A function invariant is often CONSTANT_P but may | |
3392 | include a register. We promise to only pass | |
3393 | CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */ | |
3394 | || (CONSTANT_P (x) && LEGITIMATE_PIC_OPERAND_P (x))) | |
3395 | { | |
3396 | /* It can happen that a REG_EQUIV note contains a MEM | |
3397 | that is not a legitimate memory operand. As later | |
3398 | stages of reload assume that all addresses found in | |
3399 | the lra_regno_equiv_* arrays were originally | |
3400 | legitimate, we ignore such REG_EQUIV notes. */ | |
3401 | if (memory_operand (x, VOIDmode)) | |
3402 | { | |
3403 | ira_reg_equiv[i].defined_p = true; | |
3404 | ira_reg_equiv[i].memory = x; | |
3405 | continue; | |
3406 | } | |
3407 | else if (function_invariant_p (x)) | |
3408 | { | |
3409 | enum machine_mode mode; | |
3410 | ||
3411 | mode = GET_MODE (SET_DEST (set)); | |
3412 | if (GET_CODE (x) == PLUS | |
3413 | || x == frame_pointer_rtx || x == arg_pointer_rtx) | |
3414 | /* This is PLUS of frame pointer and a constant, | |
3415 | or fp, or argp. */ | |
3416 | ira_reg_equiv[i].invariant = x; | |
3417 | else if (targetm.legitimate_constant_p (mode, x)) | |
3418 | ira_reg_equiv[i].constant = x; | |
3419 | else | |
3420 | { | |
3421 | ira_reg_equiv[i].memory = force_const_mem (mode, x); | |
3422 | if (ira_reg_equiv[i].memory == NULL_RTX) | |
3423 | { | |
3424 | ira_reg_equiv[i].defined_p = false; | |
3425 | ira_reg_equiv[i].init_insns = NULL_RTX; | |
3426 | break; | |
3427 | } | |
3428 | } | |
3429 | ira_reg_equiv[i].defined_p = true; | |
3430 | continue; | |
3431 | } | |
3432 | } | |
3433 | } | |
3434 | ira_reg_equiv[i].defined_p = false; | |
3435 | ira_reg_equiv[i].init_insns = NULL_RTX; | |
3436 | break; | |
3437 | } | |
3438 | } | |
3439 | ||
3440 | \f | |
3441 | ||
2af2dbdc VM |
3442 | /* Print chain C to FILE. */ |
3443 | static void | |
3444 | print_insn_chain (FILE *file, struct insn_chain *c) | |
3445 | { | |
3446 | fprintf (file, "insn=%d, ", INSN_UID(c->insn)); | |
3447 | bitmap_print (file, &c->live_throughout, "live_throughout: ", ", "); | |
3448 | bitmap_print (file, &c->dead_or_set, "dead_or_set: ", "\n"); | |
3449 | } | |
3450 | ||
3451 | ||
3452 | /* Print all reload_insn_chains to FILE. */ | |
3453 | static void | |
3454 | print_insn_chains (FILE *file) | |
3455 | { | |
3456 | struct insn_chain *c; | |
3457 | for (c = reload_insn_chain; c ; c = c->next) | |
3458 | print_insn_chain (file, c); | |
3459 | } | |
3460 | ||
3461 | /* Return true if pseudo REGNO should be added to set live_throughout | |
3462 | or dead_or_set of the insn chains for reload consideration. */ | |
3463 | static bool | |
3464 | pseudo_for_reload_consideration_p (int regno) | |
3465 | { | |
3466 | /* Consider spilled pseudos too for IRA because they still have a | |
3467 | chance to get hard-registers in the reload when IRA is used. */ | |
b100151b | 3468 | return (reg_renumber[regno] >= 0 || ira_conflicts_p); |
2af2dbdc VM |
3469 | } |
3470 | ||
3471 | /* Init LIVE_SUBREGS[ALLOCNUM] and LIVE_SUBREGS_USED[ALLOCNUM] using | |
3472 | REG to the number of nregs, and INIT_VALUE to get the | |
3473 | initialization. ALLOCNUM need not be the regno of REG. */ | |
3474 | static void | |
3475 | init_live_subregs (bool init_value, sbitmap *live_subregs, | |
cee784f5 | 3476 | bitmap live_subregs_used, int allocnum, rtx reg) |
2af2dbdc VM |
3477 | { |
3478 | unsigned int regno = REGNO (SUBREG_REG (reg)); | |
3479 | int size = GET_MODE_SIZE (GET_MODE (regno_reg_rtx[regno])); | |
3480 | ||
3481 | gcc_assert (size > 0); | |
3482 | ||
3483 | /* Been there, done that. */ | |
cee784f5 | 3484 | if (bitmap_bit_p (live_subregs_used, allocnum)) |
2af2dbdc VM |
3485 | return; |
3486 | ||
cee784f5 | 3487 | /* Create a new one. */ |
2af2dbdc VM |
3488 | if (live_subregs[allocnum] == NULL) |
3489 | live_subregs[allocnum] = sbitmap_alloc (size); | |
3490 | ||
3491 | /* If the entire reg was live before blasting into subregs, we need | |
3492 | to init all of the subregs to ones else init to 0. */ | |
3493 | if (init_value) | |
3494 | sbitmap_ones (live_subregs[allocnum]); | |
b8698a0f | 3495 | else |
2af2dbdc VM |
3496 | sbitmap_zero (live_subregs[allocnum]); |
3497 | ||
cee784f5 | 3498 | bitmap_set_bit (live_subregs_used, allocnum); |
2af2dbdc VM |
3499 | } |
3500 | ||
3501 | /* Walk the insns of the current function and build reload_insn_chain, | |
3502 | and record register life information. */ | |
3503 | static void | |
3504 | build_insn_chain (void) | |
3505 | { | |
3506 | unsigned int i; | |
3507 | struct insn_chain **p = &reload_insn_chain; | |
3508 | basic_block bb; | |
3509 | struct insn_chain *c = NULL; | |
3510 | struct insn_chain *next = NULL; | |
3511 | bitmap live_relevant_regs = BITMAP_ALLOC (NULL); | |
3512 | bitmap elim_regset = BITMAP_ALLOC (NULL); | |
3513 | /* live_subregs is a vector used to keep accurate information about | |
3514 | which hardregs are live in multiword pseudos. live_subregs and | |
3515 | live_subregs_used are indexed by pseudo number. The live_subreg | |
3516 | entry for a particular pseudo is only used if the corresponding | |
cee784f5 SB |
3517 | element is non zero in live_subregs_used. The sbitmap size of |
3518 | live_subreg[allocno] is number of bytes that the pseudo can | |
2af2dbdc VM |
3519 | occupy. */ |
3520 | sbitmap *live_subregs = XCNEWVEC (sbitmap, max_regno); | |
cee784f5 | 3521 | bitmap live_subregs_used = BITMAP_ALLOC (NULL); |
2af2dbdc VM |
3522 | |
3523 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
3524 | if (TEST_HARD_REG_BIT (eliminable_regset, i)) | |
3525 | bitmap_set_bit (elim_regset, i); | |
3526 | FOR_EACH_BB_REVERSE (bb) | |
3527 | { | |
3528 | bitmap_iterator bi; | |
3529 | rtx insn; | |
b8698a0f | 3530 | |
2af2dbdc | 3531 | CLEAR_REG_SET (live_relevant_regs); |
cee784f5 | 3532 | bitmap_clear (live_subregs_used); |
b8698a0f | 3533 | |
bf744527 | 3534 | EXECUTE_IF_SET_IN_BITMAP (df_get_live_out (bb), 0, i, bi) |
2af2dbdc VM |
3535 | { |
3536 | if (i >= FIRST_PSEUDO_REGISTER) | |
3537 | break; | |
3538 | bitmap_set_bit (live_relevant_regs, i); | |
3539 | } | |
3540 | ||
bf744527 | 3541 | EXECUTE_IF_SET_IN_BITMAP (df_get_live_out (bb), |
2af2dbdc VM |
3542 | FIRST_PSEUDO_REGISTER, i, bi) |
3543 | { | |
3544 | if (pseudo_for_reload_consideration_p (i)) | |
3545 | bitmap_set_bit (live_relevant_regs, i); | |
3546 | } | |
3547 | ||
3548 | FOR_BB_INSNS_REVERSE (bb, insn) | |
3549 | { | |
3550 | if (!NOTE_P (insn) && !BARRIER_P (insn)) | |
3551 | { | |
3552 | unsigned int uid = INSN_UID (insn); | |
3553 | df_ref *def_rec; | |
3554 | df_ref *use_rec; | |
3555 | ||
3556 | c = new_insn_chain (); | |
3557 | c->next = next; | |
3558 | next = c; | |
3559 | *p = c; | |
3560 | p = &c->prev; | |
b8698a0f | 3561 | |
2af2dbdc VM |
3562 | c->insn = insn; |
3563 | c->block = bb->index; | |
3564 | ||
3565 | if (INSN_P (insn)) | |
3566 | for (def_rec = DF_INSN_UID_DEFS (uid); *def_rec; def_rec++) | |
3567 | { | |
3568 | df_ref def = *def_rec; | |
3569 | unsigned int regno = DF_REF_REGNO (def); | |
b8698a0f | 3570 | |
2af2dbdc VM |
3571 | /* Ignore may clobbers because these are generated |
3572 | from calls. However, every other kind of def is | |
3573 | added to dead_or_set. */ | |
3574 | if (!DF_REF_FLAGS_IS_SET (def, DF_REF_MAY_CLOBBER)) | |
3575 | { | |
3576 | if (regno < FIRST_PSEUDO_REGISTER) | |
3577 | { | |
3578 | if (!fixed_regs[regno]) | |
3579 | bitmap_set_bit (&c->dead_or_set, regno); | |
3580 | } | |
3581 | else if (pseudo_for_reload_consideration_p (regno)) | |
3582 | bitmap_set_bit (&c->dead_or_set, regno); | |
3583 | } | |
3584 | ||
3585 | if ((regno < FIRST_PSEUDO_REGISTER | |
3586 | || reg_renumber[regno] >= 0 | |
3587 | || ira_conflicts_p) | |
3588 | && (!DF_REF_FLAGS_IS_SET (def, DF_REF_CONDITIONAL))) | |
3589 | { | |
3590 | rtx reg = DF_REF_REG (def); | |
3591 | ||
3592 | /* We can model subregs, but not if they are | |
3593 | wrapped in ZERO_EXTRACTS. */ | |
3594 | if (GET_CODE (reg) == SUBREG | |
3595 | && !DF_REF_FLAGS_IS_SET (def, DF_REF_ZERO_EXTRACT)) | |
3596 | { | |
3597 | unsigned int start = SUBREG_BYTE (reg); | |
b8698a0f | 3598 | unsigned int last = start |
2af2dbdc VM |
3599 | + GET_MODE_SIZE (GET_MODE (reg)); |
3600 | ||
3601 | init_live_subregs | |
b8698a0f | 3602 | (bitmap_bit_p (live_relevant_regs, regno), |
2af2dbdc VM |
3603 | live_subregs, live_subregs_used, regno, reg); |
3604 | ||
3605 | if (!DF_REF_FLAGS_IS_SET | |
3606 | (def, DF_REF_STRICT_LOW_PART)) | |
3607 | { | |
3608 | /* Expand the range to cover entire words. | |
3609 | Bytes added here are "don't care". */ | |
3610 | start | |
3611 | = start / UNITS_PER_WORD * UNITS_PER_WORD; | |
3612 | last = ((last + UNITS_PER_WORD - 1) | |
3613 | / UNITS_PER_WORD * UNITS_PER_WORD); | |
3614 | } | |
3615 | ||
3616 | /* Ignore the paradoxical bits. */ | |
cee784f5 SB |
3617 | if (last > SBITMAP_SIZE (live_subregs[regno])) |
3618 | last = SBITMAP_SIZE (live_subregs[regno]); | |
2af2dbdc VM |
3619 | |
3620 | while (start < last) | |
3621 | { | |
3622 | RESET_BIT (live_subregs[regno], start); | |
3623 | start++; | |
3624 | } | |
b8698a0f | 3625 | |
2af2dbdc VM |
3626 | if (sbitmap_empty_p (live_subregs[regno])) |
3627 | { | |
cee784f5 | 3628 | bitmap_clear_bit (live_subregs_used, regno); |
2af2dbdc VM |
3629 | bitmap_clear_bit (live_relevant_regs, regno); |
3630 | } | |
3631 | else | |
3632 | /* Set live_relevant_regs here because | |
3633 | that bit has to be true to get us to | |
3634 | look at the live_subregs fields. */ | |
3635 | bitmap_set_bit (live_relevant_regs, regno); | |
3636 | } | |
3637 | else | |
3638 | { | |
3639 | /* DF_REF_PARTIAL is generated for | |
3640 | subregs, STRICT_LOW_PART, and | |
3641 | ZERO_EXTRACT. We handle the subreg | |
3642 | case above so here we have to keep from | |
3643 | modeling the def as a killing def. */ | |
3644 | if (!DF_REF_FLAGS_IS_SET (def, DF_REF_PARTIAL)) | |
3645 | { | |
cee784f5 | 3646 | bitmap_clear_bit (live_subregs_used, regno); |
2af2dbdc | 3647 | bitmap_clear_bit (live_relevant_regs, regno); |
2af2dbdc VM |
3648 | } |
3649 | } | |
3650 | } | |
3651 | } | |
b8698a0f | 3652 | |
2af2dbdc VM |
3653 | bitmap_and_compl_into (live_relevant_regs, elim_regset); |
3654 | bitmap_copy (&c->live_throughout, live_relevant_regs); | |
3655 | ||
3656 | if (INSN_P (insn)) | |
3657 | for (use_rec = DF_INSN_UID_USES (uid); *use_rec; use_rec++) | |
3658 | { | |
3659 | df_ref use = *use_rec; | |
3660 | unsigned int regno = DF_REF_REGNO (use); | |
3661 | rtx reg = DF_REF_REG (use); | |
b8698a0f | 3662 | |
2af2dbdc VM |
3663 | /* DF_REF_READ_WRITE on a use means that this use |
3664 | is fabricated from a def that is a partial set | |
3665 | to a multiword reg. Here, we only model the | |
3666 | subreg case that is not wrapped in ZERO_EXTRACT | |
3667 | precisely so we do not need to look at the | |
3668 | fabricated use. */ | |
b8698a0f L |
3669 | if (DF_REF_FLAGS_IS_SET (use, DF_REF_READ_WRITE) |
3670 | && !DF_REF_FLAGS_IS_SET (use, DF_REF_ZERO_EXTRACT) | |
2af2dbdc VM |
3671 | && DF_REF_FLAGS_IS_SET (use, DF_REF_SUBREG)) |
3672 | continue; | |
b8698a0f | 3673 | |
2af2dbdc VM |
3674 | /* Add the last use of each var to dead_or_set. */ |
3675 | if (!bitmap_bit_p (live_relevant_regs, regno)) | |
3676 | { | |
3677 | if (regno < FIRST_PSEUDO_REGISTER) | |
3678 | { | |
3679 | if (!fixed_regs[regno]) | |
3680 | bitmap_set_bit (&c->dead_or_set, regno); | |
3681 | } | |
3682 | else if (pseudo_for_reload_consideration_p (regno)) | |
3683 | bitmap_set_bit (&c->dead_or_set, regno); | |
3684 | } | |
b8698a0f | 3685 | |
2af2dbdc VM |
3686 | if (regno < FIRST_PSEUDO_REGISTER |
3687 | || pseudo_for_reload_consideration_p (regno)) | |
3688 | { | |
3689 | if (GET_CODE (reg) == SUBREG | |
3690 | && !DF_REF_FLAGS_IS_SET (use, | |
3691 | DF_REF_SIGN_EXTRACT | |
b8698a0f | 3692 | | DF_REF_ZERO_EXTRACT)) |
2af2dbdc VM |
3693 | { |
3694 | unsigned int start = SUBREG_BYTE (reg); | |
b8698a0f | 3695 | unsigned int last = start |
2af2dbdc | 3696 | + GET_MODE_SIZE (GET_MODE (reg)); |
b8698a0f | 3697 | |
2af2dbdc | 3698 | init_live_subregs |
b8698a0f | 3699 | (bitmap_bit_p (live_relevant_regs, regno), |
2af2dbdc | 3700 | live_subregs, live_subregs_used, regno, reg); |
b8698a0f | 3701 | |
2af2dbdc | 3702 | /* Ignore the paradoxical bits. */ |
cee784f5 SB |
3703 | if (last > SBITMAP_SIZE (live_subregs[regno])) |
3704 | last = SBITMAP_SIZE (live_subregs[regno]); | |
2af2dbdc VM |
3705 | |
3706 | while (start < last) | |
3707 | { | |
3708 | SET_BIT (live_subregs[regno], start); | |
3709 | start++; | |
3710 | } | |
3711 | } | |
3712 | else | |
3713 | /* Resetting the live_subregs_used is | |
3714 | effectively saying do not use the subregs | |
3715 | because we are reading the whole | |
3716 | pseudo. */ | |
cee784f5 | 3717 | bitmap_clear_bit (live_subregs_used, regno); |
2af2dbdc VM |
3718 | bitmap_set_bit (live_relevant_regs, regno); |
3719 | } | |
3720 | } | |
3721 | } | |
3722 | } | |
3723 | ||
3724 | /* FIXME!! The following code is a disaster. Reload needs to see the | |
3725 | labels and jump tables that are just hanging out in between | |
3726 | the basic blocks. See pr33676. */ | |
3727 | insn = BB_HEAD (bb); | |
b8698a0f | 3728 | |
2af2dbdc | 3729 | /* Skip over the barriers and cruft. */ |
b8698a0f | 3730 | while (insn && (BARRIER_P (insn) || NOTE_P (insn) |
2af2dbdc VM |
3731 | || BLOCK_FOR_INSN (insn) == bb)) |
3732 | insn = PREV_INSN (insn); | |
b8698a0f | 3733 | |
2af2dbdc VM |
3734 | /* While we add anything except barriers and notes, the focus is |
3735 | to get the labels and jump tables into the | |
3736 | reload_insn_chain. */ | |
3737 | while (insn) | |
3738 | { | |
3739 | if (!NOTE_P (insn) && !BARRIER_P (insn)) | |
3740 | { | |
3741 | if (BLOCK_FOR_INSN (insn)) | |
3742 | break; | |
b8698a0f | 3743 | |
2af2dbdc VM |
3744 | c = new_insn_chain (); |
3745 | c->next = next; | |
3746 | next = c; | |
3747 | *p = c; | |
3748 | p = &c->prev; | |
b8698a0f | 3749 | |
2af2dbdc VM |
3750 | /* The block makes no sense here, but it is what the old |
3751 | code did. */ | |
3752 | c->block = bb->index; | |
3753 | c->insn = insn; | |
3754 | bitmap_copy (&c->live_throughout, live_relevant_regs); | |
b8698a0f | 3755 | } |
2af2dbdc VM |
3756 | insn = PREV_INSN (insn); |
3757 | } | |
3758 | } | |
3759 | ||
2af2dbdc VM |
3760 | reload_insn_chain = c; |
3761 | *p = NULL; | |
3762 | ||
cee784f5 SB |
3763 | for (i = 0; i < (unsigned int) max_regno; i++) |
3764 | if (live_subregs[i] != NULL) | |
3765 | sbitmap_free (live_subregs[i]); | |
2af2dbdc | 3766 | free (live_subregs); |
cee784f5 | 3767 | BITMAP_FREE (live_subregs_used); |
2af2dbdc VM |
3768 | BITMAP_FREE (live_relevant_regs); |
3769 | BITMAP_FREE (elim_regset); | |
3770 | ||
3771 | if (dump_file) | |
3772 | print_insn_chains (dump_file); | |
3773 | } | |
acf41a74 BS |
3774 | \f |
3775 | /* Examine the rtx found in *LOC, which is read or written to as determined | |
3776 | by TYPE. Return false if we find a reason why an insn containing this | |
3777 | rtx should not be moved (such as accesses to non-constant memory), true | |
3778 | otherwise. */ | |
3779 | static bool | |
3780 | rtx_moveable_p (rtx *loc, enum op_type type) | |
3781 | { | |
3782 | const char *fmt; | |
3783 | rtx x = *loc; | |
3784 | enum rtx_code code = GET_CODE (x); | |
3785 | int i, j; | |
3786 | ||
3787 | code = GET_CODE (x); | |
3788 | switch (code) | |
3789 | { | |
3790 | case CONST: | |
d8116890 | 3791 | CASE_CONST_ANY: |
acf41a74 BS |
3792 | case SYMBOL_REF: |
3793 | case LABEL_REF: | |
3794 | return true; | |
3795 | ||
3796 | case PC: | |
3797 | return type == OP_IN; | |
3798 | ||
3799 | case CC0: | |
3800 | return false; | |
3801 | ||
3802 | case REG: | |
3803 | if (x == frame_pointer_rtx) | |
3804 | return true; | |
3805 | if (HARD_REGISTER_P (x)) | |
3806 | return false; | |
3807 | ||
3808 | return true; | |
3809 | ||
3810 | case MEM: | |
3811 | if (type == OP_IN && MEM_READONLY_P (x)) | |
3812 | return rtx_moveable_p (&XEXP (x, 0), OP_IN); | |
3813 | return false; | |
3814 | ||
3815 | case SET: | |
3816 | return (rtx_moveable_p (&SET_SRC (x), OP_IN) | |
3817 | && rtx_moveable_p (&SET_DEST (x), OP_OUT)); | |
3818 | ||
3819 | case STRICT_LOW_PART: | |
3820 | return rtx_moveable_p (&XEXP (x, 0), OP_OUT); | |
3821 | ||
3822 | case ZERO_EXTRACT: | |
3823 | case SIGN_EXTRACT: | |
3824 | return (rtx_moveable_p (&XEXP (x, 0), type) | |
3825 | && rtx_moveable_p (&XEXP (x, 1), OP_IN) | |
3826 | && rtx_moveable_p (&XEXP (x, 2), OP_IN)); | |
3827 | ||
3828 | case CLOBBER: | |
3829 | return rtx_moveable_p (&SET_DEST (x), OP_OUT); | |
3830 | ||
3831 | default: | |
3832 | break; | |
3833 | } | |
3834 | ||
3835 | fmt = GET_RTX_FORMAT (code); | |
3836 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3837 | { | |
3838 | if (fmt[i] == 'e') | |
3839 | { | |
3840 | if (!rtx_moveable_p (&XEXP (x, i), type)) | |
3841 | return false; | |
3842 | } | |
3843 | else if (fmt[i] == 'E') | |
3844 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
3845 | { | |
3846 | if (!rtx_moveable_p (&XVECEXP (x, i, j), type)) | |
3847 | return false; | |
3848 | } | |
3849 | } | |
3850 | return true; | |
3851 | } | |
3852 | ||
3853 | /* A wrapper around dominated_by_p, which uses the information in UID_LUID | |
3854 | to give dominance relationships between two insns I1 and I2. */ | |
3855 | static bool | |
3856 | insn_dominated_by_p (rtx i1, rtx i2, int *uid_luid) | |
3857 | { | |
3858 | basic_block bb1 = BLOCK_FOR_INSN (i1); | |
3859 | basic_block bb2 = BLOCK_FOR_INSN (i2); | |
3860 | ||
3861 | if (bb1 == bb2) | |
3862 | return uid_luid[INSN_UID (i2)] < uid_luid[INSN_UID (i1)]; | |
3863 | return dominated_by_p (CDI_DOMINATORS, bb1, bb2); | |
3864 | } | |
3865 | ||
3866 | /* Record the range of register numbers added by find_moveable_pseudos. */ | |
3867 | int first_moveable_pseudo, last_moveable_pseudo; | |
3868 | ||
3869 | /* These two vectors hold data for every register added by | |
3870 | find_movable_pseudos, with index 0 holding data for the | |
3871 | first_moveable_pseudo. */ | |
3872 | /* The original home register. */ | |
3873 | static VEC (rtx, heap) *pseudo_replaced_reg; | |
acf41a74 BS |
3874 | |
3875 | /* Look for instances where we have an instruction that is known to increase | |
3876 | register pressure, and whose result is not used immediately. If it is | |
3877 | possible to move the instruction downwards to just before its first use, | |
3878 | split its lifetime into two ranges. We create a new pseudo to compute the | |
3879 | value, and emit a move instruction just before the first use. If, after | |
3880 | register allocation, the new pseudo remains unallocated, the function | |
3881 | move_unallocated_pseudos then deletes the move instruction and places | |
3882 | the computation just before the first use. | |
3883 | ||
3884 | Such a move is safe and profitable if all the input registers remain live | |
3885 | and unchanged between the original computation and its first use. In such | |
3886 | a situation, the computation is known to increase register pressure, and | |
3887 | moving it is known to at least not worsen it. | |
3888 | ||
3889 | We restrict moves to only those cases where a register remains unallocated, | |
3890 | in order to avoid interfering too much with the instruction schedule. As | |
3891 | an exception, we may move insns which only modify their input register | |
3892 | (typically induction variables), as this increases the freedom for our | |
3893 | intended transformation, and does not limit the second instruction | |
3894 | scheduler pass. */ | |
3895 | ||
3896 | static void | |
3897 | find_moveable_pseudos (void) | |
3898 | { | |
3899 | unsigned i; | |
3900 | int max_regs = max_reg_num (); | |
3901 | int max_uid = get_max_uid (); | |
3902 | basic_block bb; | |
3903 | int *uid_luid = XNEWVEC (int, max_uid); | |
3904 | rtx *closest_uses = XNEWVEC (rtx, max_regs); | |
3905 | /* A set of registers which are live but not modified throughout a block. */ | |
3906 | bitmap_head *bb_transp_live = XNEWVEC (bitmap_head, last_basic_block); | |
3907 | /* A set of registers which only exist in a given basic block. */ | |
3908 | bitmap_head *bb_local = XNEWVEC (bitmap_head, last_basic_block); | |
3909 | /* A set of registers which are set once, in an instruction that can be | |
3910 | moved freely downwards, but are otherwise transparent to a block. */ | |
3911 | bitmap_head *bb_moveable_reg_sets = XNEWVEC (bitmap_head, last_basic_block); | |
3912 | bitmap_head live, used, set, interesting, unusable_as_input; | |
3913 | bitmap_iterator bi; | |
3914 | bitmap_initialize (&interesting, 0); | |
3915 | ||
3916 | first_moveable_pseudo = max_regs; | |
acf41a74 | 3917 | VEC_free (rtx, heap, pseudo_replaced_reg); |
acf41a74 BS |
3918 | VEC_safe_grow (rtx, heap, pseudo_replaced_reg, max_regs); |
3919 | ||
3920 | df_analyze (); | |
3921 | calculate_dominance_info (CDI_DOMINATORS); | |
3922 | ||
3923 | i = 0; | |
3924 | bitmap_initialize (&live, 0); | |
3925 | bitmap_initialize (&used, 0); | |
3926 | bitmap_initialize (&set, 0); | |
3927 | bitmap_initialize (&unusable_as_input, 0); | |
3928 | FOR_EACH_BB (bb) | |
3929 | { | |
3930 | rtx insn; | |
3931 | bitmap transp = bb_transp_live + bb->index; | |
3932 | bitmap moveable = bb_moveable_reg_sets + bb->index; | |
3933 | bitmap local = bb_local + bb->index; | |
3934 | ||
3935 | bitmap_initialize (local, 0); | |
3936 | bitmap_initialize (transp, 0); | |
3937 | bitmap_initialize (moveable, 0); | |
3938 | bitmap_copy (&live, df_get_live_out (bb)); | |
3939 | bitmap_and_into (&live, df_get_live_in (bb)); | |
3940 | bitmap_copy (transp, &live); | |
3941 | bitmap_clear (moveable); | |
3942 | bitmap_clear (&live); | |
3943 | bitmap_clear (&used); | |
3944 | bitmap_clear (&set); | |
3945 | FOR_BB_INSNS (bb, insn) | |
3946 | if (NONDEBUG_INSN_P (insn)) | |
3947 | { | |
3948 | df_ref *u_rec, *d_rec; | |
3949 | ||
3950 | uid_luid[INSN_UID (insn)] = i++; | |
3951 | ||
3952 | u_rec = DF_INSN_USES (insn); | |
3953 | d_rec = DF_INSN_DEFS (insn); | |
3954 | if (d_rec[0] != NULL && d_rec[1] == NULL | |
3955 | && u_rec[0] != NULL && u_rec[1] == NULL | |
3956 | && DF_REF_REGNO (*u_rec) == DF_REF_REGNO (*d_rec) | |
3957 | && !bitmap_bit_p (&set, DF_REF_REGNO (*u_rec)) | |
3958 | && rtx_moveable_p (&PATTERN (insn), OP_IN)) | |
3959 | { | |
3960 | unsigned regno = DF_REF_REGNO (*u_rec); | |
3961 | bitmap_set_bit (moveable, regno); | |
3962 | bitmap_set_bit (&set, regno); | |
3963 | bitmap_set_bit (&used, regno); | |
3964 | bitmap_clear_bit (transp, regno); | |
3965 | continue; | |
3966 | } | |
3967 | while (*u_rec) | |
3968 | { | |
3969 | unsigned regno = DF_REF_REGNO (*u_rec); | |
3970 | bitmap_set_bit (&used, regno); | |
3971 | if (bitmap_clear_bit (moveable, regno)) | |
3972 | bitmap_clear_bit (transp, regno); | |
3973 | u_rec++; | |
3974 | } | |
3975 | ||
3976 | while (*d_rec) | |
3977 | { | |
3978 | unsigned regno = DF_REF_REGNO (*d_rec); | |
3979 | bitmap_set_bit (&set, regno); | |
3980 | bitmap_clear_bit (transp, regno); | |
3981 | bitmap_clear_bit (moveable, regno); | |
3982 | d_rec++; | |
3983 | } | |
3984 | } | |
3985 | } | |
3986 | ||
3987 | bitmap_clear (&live); | |
3988 | bitmap_clear (&used); | |
3989 | bitmap_clear (&set); | |
3990 | ||
3991 | FOR_EACH_BB (bb) | |
3992 | { | |
3993 | bitmap local = bb_local + bb->index; | |
3994 | rtx insn; | |
3995 | ||
3996 | FOR_BB_INSNS (bb, insn) | |
3997 | if (NONDEBUG_INSN_P (insn)) | |
3998 | { | |
3999 | rtx def_insn, closest_use, note; | |
4000 | df_ref *def_rec, def, use; | |
4001 | unsigned regno; | |
4002 | bool all_dominated, all_local; | |
4003 | enum machine_mode mode; | |
4004 | ||
4005 | def_rec = DF_INSN_DEFS (insn); | |
4006 | /* There must be exactly one def in this insn. */ | |
4007 | def = *def_rec; | |
4008 | if (!def || def_rec[1] || !single_set (insn)) | |
4009 | continue; | |
4010 | /* This must be the only definition of the reg. We also limit | |
4011 | which modes we deal with so that we can assume we can generate | |
4012 | move instructions. */ | |
4013 | regno = DF_REF_REGNO (def); | |
4014 | mode = GET_MODE (DF_REF_REG (def)); | |
4015 | if (DF_REG_DEF_COUNT (regno) != 1 | |
4016 | || !DF_REF_INSN_INFO (def) | |
4017 | || HARD_REGISTER_NUM_P (regno) | |
aa44c80c | 4018 | || DF_REG_EQ_USE_COUNT (regno) > 0 |
acf41a74 BS |
4019 | || (!INTEGRAL_MODE_P (mode) && !FLOAT_MODE_P (mode))) |
4020 | continue; | |
4021 | def_insn = DF_REF_INSN (def); | |
4022 | ||
4023 | for (note = REG_NOTES (def_insn); note; note = XEXP (note, 1)) | |
4024 | if (REG_NOTE_KIND (note) == REG_EQUIV && MEM_P (XEXP (note, 0))) | |
4025 | break; | |
4026 | ||
4027 | if (note) | |
4028 | { | |
4029 | if (dump_file) | |
4030 | fprintf (dump_file, "Ignoring reg %d, has equiv memory\n", | |
4031 | regno); | |
4032 | bitmap_set_bit (&unusable_as_input, regno); | |
4033 | continue; | |
4034 | } | |
4035 | ||
4036 | use = DF_REG_USE_CHAIN (regno); | |
4037 | all_dominated = true; | |
4038 | all_local = true; | |
4039 | closest_use = NULL_RTX; | |
4040 | for (; use; use = DF_REF_NEXT_REG (use)) | |
4041 | { | |
4042 | rtx insn; | |
4043 | if (!DF_REF_INSN_INFO (use)) | |
4044 | { | |
4045 | all_dominated = false; | |
4046 | all_local = false; | |
4047 | break; | |
4048 | } | |
4049 | insn = DF_REF_INSN (use); | |
4050 | if (DEBUG_INSN_P (insn)) | |
4051 | continue; | |
4052 | if (BLOCK_FOR_INSN (insn) != BLOCK_FOR_INSN (def_insn)) | |
4053 | all_local = false; | |
4054 | if (!insn_dominated_by_p (insn, def_insn, uid_luid)) | |
4055 | all_dominated = false; | |
4056 | if (closest_use != insn && closest_use != const0_rtx) | |
4057 | { | |
4058 | if (closest_use == NULL_RTX) | |
4059 | closest_use = insn; | |
4060 | else if (insn_dominated_by_p (closest_use, insn, uid_luid)) | |
4061 | closest_use = insn; | |
4062 | else if (!insn_dominated_by_p (insn, closest_use, uid_luid)) | |
4063 | closest_use = const0_rtx; | |
4064 | } | |
4065 | } | |
4066 | if (!all_dominated) | |
4067 | { | |
4068 | if (dump_file) | |
4069 | fprintf (dump_file, "Reg %d not all uses dominated by set\n", | |
4070 | regno); | |
4071 | continue; | |
4072 | } | |
4073 | if (all_local) | |
4074 | bitmap_set_bit (local, regno); | |
4075 | if (closest_use == const0_rtx || closest_use == NULL | |
4076 | || next_nonnote_nondebug_insn (def_insn) == closest_use) | |
4077 | { | |
4078 | if (dump_file) | |
4079 | fprintf (dump_file, "Reg %d uninteresting%s\n", regno, | |
4080 | closest_use == const0_rtx || closest_use == NULL | |
4081 | ? " (no unique first use)" : ""); | |
4082 | continue; | |
4083 | } | |
4084 | #ifdef HAVE_cc0 | |
4085 | if (reg_referenced_p (cc0_rtx, PATTERN (closest_use))) | |
4086 | { | |
4087 | if (dump_file) | |
4088 | fprintf (dump_file, "Reg %d: closest user uses cc0\n", | |
4089 | regno); | |
4090 | continue; | |
4091 | } | |
4092 | #endif | |
4093 | bitmap_set_bit (&interesting, regno); | |
4094 | closest_uses[regno] = closest_use; | |
4095 | ||
4096 | if (dump_file && (all_local || all_dominated)) | |
4097 | { | |
4098 | fprintf (dump_file, "Reg %u:", regno); | |
4099 | if (all_local) | |
4100 | fprintf (dump_file, " local to bb %d", bb->index); | |
4101 | if (all_dominated) | |
4102 | fprintf (dump_file, " def dominates all uses"); | |
4103 | if (closest_use != const0_rtx) | |
4104 | fprintf (dump_file, " has unique first use"); | |
4105 | fputs ("\n", dump_file); | |
4106 | } | |
4107 | } | |
4108 | } | |
4109 | ||
4110 | EXECUTE_IF_SET_IN_BITMAP (&interesting, 0, i, bi) | |
4111 | { | |
4112 | df_ref def = DF_REG_DEF_CHAIN (i); | |
4113 | rtx def_insn = DF_REF_INSN (def); | |
4114 | basic_block def_block = BLOCK_FOR_INSN (def_insn); | |
4115 | bitmap def_bb_local = bb_local + def_block->index; | |
4116 | bitmap def_bb_moveable = bb_moveable_reg_sets + def_block->index; | |
4117 | bitmap def_bb_transp = bb_transp_live + def_block->index; | |
4118 | bool local_to_bb_p = bitmap_bit_p (def_bb_local, i); | |
4119 | rtx use_insn = closest_uses[i]; | |
4120 | df_ref *def_insn_use_rec = DF_INSN_USES (def_insn); | |
4121 | bool all_ok = true; | |
4122 | bool all_transp = true; | |
4123 | ||
4124 | if (!REG_P (DF_REF_REG (def))) | |
4125 | continue; | |
4126 | ||
4127 | if (!local_to_bb_p) | |
4128 | { | |
4129 | if (dump_file) | |
4130 | fprintf (dump_file, "Reg %u not local to one basic block\n", | |
4131 | i); | |
4132 | continue; | |
4133 | } | |
4134 | if (reg_equiv_init (i) != NULL_RTX) | |
4135 | { | |
4136 | if (dump_file) | |
4137 | fprintf (dump_file, "Ignoring reg %u with equiv init insn\n", | |
4138 | i); | |
4139 | continue; | |
4140 | } | |
4141 | if (!rtx_moveable_p (&PATTERN (def_insn), OP_IN)) | |
4142 | { | |
4143 | if (dump_file) | |
4144 | fprintf (dump_file, "Found def insn %d for %d to be not moveable\n", | |
4145 | INSN_UID (def_insn), i); | |
4146 | continue; | |
4147 | } | |
4148 | if (dump_file) | |
4149 | fprintf (dump_file, "Examining insn %d, def for %d\n", | |
4150 | INSN_UID (def_insn), i); | |
4151 | while (*def_insn_use_rec != NULL) | |
4152 | { | |
4153 | df_ref use = *def_insn_use_rec; | |
4154 | unsigned regno = DF_REF_REGNO (use); | |
4155 | if (bitmap_bit_p (&unusable_as_input, regno)) | |
4156 | { | |
4157 | all_ok = false; | |
4158 | if (dump_file) | |
4159 | fprintf (dump_file, " found unusable input reg %u.\n", regno); | |
4160 | break; | |
4161 | } | |
4162 | if (!bitmap_bit_p (def_bb_transp, regno)) | |
4163 | { | |
4164 | if (bitmap_bit_p (def_bb_moveable, regno) | |
4165 | && !control_flow_insn_p (use_insn) | |
4166 | #ifdef HAVE_cc0 | |
4167 | && !sets_cc0_p (use_insn) | |
4168 | #endif | |
4169 | ) | |
4170 | { | |
4171 | if (modified_between_p (DF_REF_REG (use), def_insn, use_insn)) | |
4172 | { | |
4173 | rtx x = NEXT_INSN (def_insn); | |
4174 | while (!modified_in_p (DF_REF_REG (use), x)) | |
4175 | { | |
4176 | gcc_assert (x != use_insn); | |
4177 | x = NEXT_INSN (x); | |
4178 | } | |
4179 | if (dump_file) | |
4180 | fprintf (dump_file, " input reg %u modified but insn %d moveable\n", | |
4181 | regno, INSN_UID (x)); | |
4182 | emit_insn_after (PATTERN (x), use_insn); | |
4183 | set_insn_deleted (x); | |
4184 | } | |
4185 | else | |
4186 | { | |
4187 | if (dump_file) | |
4188 | fprintf (dump_file, " input reg %u modified between def and use\n", | |
4189 | regno); | |
4190 | all_transp = false; | |
4191 | } | |
4192 | } | |
4193 | else | |
4194 | all_transp = false; | |
4195 | } | |
4196 | ||
4197 | def_insn_use_rec++; | |
4198 | } | |
4199 | if (!all_ok) | |
4200 | continue; | |
4201 | if (!dbg_cnt (ira_move)) | |
4202 | break; | |
4203 | if (dump_file) | |
4204 | fprintf (dump_file, " all ok%s\n", all_transp ? " and transp" : ""); | |
4205 | ||
4206 | if (all_transp) | |
4207 | { | |
4208 | rtx def_reg = DF_REF_REG (def); | |
4209 | rtx newreg = ira_create_new_reg (def_reg); | |
4210 | if (validate_change (def_insn, DF_REF_LOC (def), newreg, 0)) | |
4211 | { | |
4212 | unsigned nregno = REGNO (newreg); | |
a36b2706 | 4213 | emit_insn_before (gen_move_insn (def_reg, newreg), use_insn); |
acf41a74 | 4214 | nregno -= max_regs; |
acf41a74 BS |
4215 | VEC_replace (rtx, pseudo_replaced_reg, nregno, def_reg); |
4216 | } | |
4217 | } | |
4218 | } | |
4219 | ||
4220 | FOR_EACH_BB (bb) | |
4221 | { | |
4222 | bitmap_clear (bb_local + bb->index); | |
4223 | bitmap_clear (bb_transp_live + bb->index); | |
4224 | bitmap_clear (bb_moveable_reg_sets + bb->index); | |
4225 | } | |
4226 | bitmap_clear (&interesting); | |
4227 | bitmap_clear (&unusable_as_input); | |
4228 | free (uid_luid); | |
4229 | free (closest_uses); | |
4230 | free (bb_local); | |
4231 | free (bb_transp_live); | |
4232 | free (bb_moveable_reg_sets); | |
4233 | ||
4234 | last_moveable_pseudo = max_reg_num (); | |
4235 | ||
81c082ec | 4236 | fix_reg_equiv_init (); |
fb99ee9b | 4237 | expand_reg_info (); |
acf41a74 BS |
4238 | regstat_free_n_sets_and_refs (); |
4239 | regstat_free_ri (); | |
4240 | regstat_init_n_sets_and_refs (); | |
4241 | regstat_compute_ri (); | |
4242 | free_dominance_info (CDI_DOMINATORS); | |
4243 | } | |
8ff49c29 | 4244 | |
acf41a74 BS |
4245 | /* Perform the second half of the transformation started in |
4246 | find_moveable_pseudos. We look for instances where the newly introduced | |
4247 | pseudo remains unallocated, and remove it by moving the definition to | |
4248 | just before its use, replacing the move instruction generated by | |
4249 | find_moveable_pseudos. */ | |
4250 | static void | |
4251 | move_unallocated_pseudos (void) | |
4252 | { | |
4253 | int i; | |
4254 | for (i = first_moveable_pseudo; i < last_moveable_pseudo; i++) | |
4255 | if (reg_renumber[i] < 0) | |
4256 | { | |
acf41a74 BS |
4257 | int idx = i - first_moveable_pseudo; |
4258 | rtx other_reg = VEC_index (rtx, pseudo_replaced_reg, idx); | |
a36b2706 RS |
4259 | rtx def_insn = DF_REF_INSN (DF_REG_DEF_CHAIN (i)); |
4260 | /* The use must follow all definitions of OTHER_REG, so we can | |
4261 | insert the new definition immediately after any of them. */ | |
4262 | df_ref other_def = DF_REG_DEF_CHAIN (REGNO (other_reg)); | |
4263 | rtx move_insn = DF_REF_INSN (other_def); | |
acf41a74 | 4264 | rtx newinsn = emit_insn_after (PATTERN (def_insn), move_insn); |
a36b2706 | 4265 | rtx set; |
acf41a74 BS |
4266 | int success; |
4267 | ||
4268 | if (dump_file) | |
4269 | fprintf (dump_file, "moving def of %d (insn %d now) ", | |
4270 | REGNO (other_reg), INSN_UID (def_insn)); | |
4271 | ||
a36b2706 RS |
4272 | delete_insn (move_insn); |
4273 | while ((other_def = DF_REG_DEF_CHAIN (REGNO (other_reg)))) | |
4274 | delete_insn (DF_REF_INSN (other_def)); | |
4275 | delete_insn (def_insn); | |
4276 | ||
acf41a74 BS |
4277 | set = single_set (newinsn); |
4278 | success = validate_change (newinsn, &SET_DEST (set), other_reg, 0); | |
4279 | gcc_assert (success); | |
4280 | if (dump_file) | |
4281 | fprintf (dump_file, " %d) rather than keep unallocated replacement %d\n", | |
4282 | INSN_UID (newinsn), i); | |
acf41a74 BS |
4283 | SET_REG_N_REFS (i, 0); |
4284 | } | |
4285 | } | |
f2034d06 | 4286 | \f |
6399c0ab SB |
4287 | /* If the backend knows where to allocate pseudos for hard |
4288 | register initial values, register these allocations now. */ | |
a932fb89 | 4289 | static void |
6399c0ab SB |
4290 | allocate_initial_values (void) |
4291 | { | |
4292 | if (targetm.allocate_initial_value) | |
4293 | { | |
4294 | rtx hreg, preg, x; | |
4295 | int i, regno; | |
4296 | ||
4297 | for (i = 0; HARD_REGISTER_NUM_P (i); i++) | |
4298 | { | |
4299 | if (! initial_value_entry (i, &hreg, &preg)) | |
4300 | break; | |
4301 | ||
4302 | x = targetm.allocate_initial_value (hreg); | |
4303 | regno = REGNO (preg); | |
4304 | if (x && REG_N_SETS (regno) <= 1) | |
4305 | { | |
4306 | if (MEM_P (x)) | |
4307 | reg_equiv_memory_loc (regno) = x; | |
4308 | else | |
4309 | { | |
4310 | basic_block bb; | |
4311 | int new_regno; | |
4312 | ||
4313 | gcc_assert (REG_P (x)); | |
4314 | new_regno = REGNO (x); | |
4315 | reg_renumber[regno] = new_regno; | |
4316 | /* Poke the regno right into regno_reg_rtx so that even | |
4317 | fixed regs are accepted. */ | |
4318 | SET_REGNO (preg, new_regno); | |
4319 | /* Update global register liveness information. */ | |
4320 | FOR_EACH_BB (bb) | |
4321 | { | |
4322 | if (REGNO_REG_SET_P(df_get_live_in (bb), regno)) | |
4323 | SET_REGNO_REG_SET (df_get_live_in (bb), new_regno); | |
4324 | if (REGNO_REG_SET_P(df_get_live_out (bb), regno)) | |
4325 | SET_REGNO_REG_SET (df_get_live_out (bb), new_regno); | |
4326 | } | |
4327 | } | |
4328 | } | |
4329 | } | |
2af2dbdc | 4330 | |
6399c0ab SB |
4331 | gcc_checking_assert (! initial_value_entry (FIRST_PSEUDO_REGISTER, |
4332 | &hreg, &preg)); | |
4333 | } | |
4334 | } | |
4335 | \f | |
55a2c322 VM |
4336 | |
4337 | /* True when we use LRA instead of reload pass for the current | |
4338 | function. */ | |
4339 | bool ira_use_lra_p; | |
4340 | ||
058e97ec VM |
4341 | /* All natural loops. */ |
4342 | struct loops ira_loops; | |
4343 | ||
311aab06 VM |
4344 | /* True if we have allocno conflicts. It is false for non-optimized |
4345 | mode or when the conflict table is too big. */ | |
4346 | bool ira_conflicts_p; | |
4347 | ||
ae2b9cb6 BS |
4348 | /* Saved between IRA and reload. */ |
4349 | static int saved_flag_ira_share_spill_slots; | |
4350 | ||
058e97ec VM |
4351 | /* This is the main entry of IRA. */ |
4352 | static void | |
4353 | ira (FILE *f) | |
4354 | { | |
058e97ec VM |
4355 | bool loops_p; |
4356 | int max_regno_before_ira, ira_max_point_before_emit; | |
4357 | int rebuild_p; | |
55a2c322 VM |
4358 | bool saved_flag_caller_saves = flag_caller_saves; |
4359 | enum ira_region saved_flag_ira_region = flag_ira_region; | |
4360 | ||
4361 | ira_conflicts_p = optimize > 0; | |
4362 | ||
4363 | ira_use_lra_p = targetm.lra_p (); | |
4364 | /* If there are too many pseudos and/or basic blocks (e.g. 10K | |
4365 | pseudos and 10K blocks or 100K pseudos and 1K blocks), we will | |
4366 | use simplified and faster algorithms in LRA. */ | |
4367 | lra_simple_p | |
4368 | = (ira_use_lra_p && max_reg_num () >= (1 << 26) / last_basic_block); | |
4369 | if (lra_simple_p) | |
4370 | { | |
4371 | /* It permits to skip live range splitting in LRA. */ | |
4372 | flag_caller_saves = false; | |
4373 | /* There is no sense to do regional allocation when we use | |
4374 | simplified LRA. */ | |
4375 | flag_ira_region = IRA_REGION_ONE; | |
4376 | ira_conflicts_p = false; | |
4377 | } | |
4378 | ||
4379 | #ifndef IRA_NO_OBSTACK | |
4380 | gcc_obstack_init (&ira_obstack); | |
4381 | #endif | |
4382 | bitmap_obstack_initialize (&ira_bitmap_obstack); | |
058e97ec | 4383 | |
dc12b70e JZ |
4384 | if (flag_caller_saves) |
4385 | init_caller_save (); | |
4386 | ||
058e97ec VM |
4387 | if (flag_ira_verbose < 10) |
4388 | { | |
4389 | internal_flag_ira_verbose = flag_ira_verbose; | |
4390 | ira_dump_file = f; | |
4391 | } | |
4392 | else | |
4393 | { | |
4394 | internal_flag_ira_verbose = flag_ira_verbose - 10; | |
4395 | ira_dump_file = stderr; | |
4396 | } | |
4397 | ||
4398 | setup_prohibited_mode_move_regs (); | |
4399 | ||
4400 | df_note_add_problem (); | |
058e97ec VM |
4401 | #ifdef ENABLE_CHECKING |
4402 | df->changeable_flags |= DF_VERIFY_SCHEDULED; | |
4403 | #endif | |
4404 | df_analyze (); | |
4405 | df_clear_flags (DF_NO_INSN_RESCAN); | |
4406 | regstat_init_n_sets_and_refs (); | |
4407 | regstat_compute_ri (); | |
4408 | ||
4409 | /* If we are not optimizing, then this is the only place before | |
4410 | register allocation where dataflow is done. And that is needed | |
4411 | to generate these warnings. */ | |
4412 | if (warn_clobbered) | |
4413 | generate_setjmp_warnings (); | |
4414 | ||
ace984c8 RS |
4415 | /* Determine if the current function is a leaf before running IRA |
4416 | since this can impact optimizations done by the prologue and | |
4417 | epilogue thus changing register elimination offsets. */ | |
416ff32e | 4418 | crtl->is_leaf = leaf_function_p (); |
ace984c8 | 4419 | |
1833192f | 4420 | if (resize_reg_info () && flag_ira_loop_pressure) |
b11f0116 | 4421 | ira_set_pseudo_classes (true, ira_dump_file); |
1833192f | 4422 | |
55a2c322 | 4423 | init_reg_equiv (); |
058e97ec | 4424 | rebuild_p = update_equiv_regs (); |
55a2c322 VM |
4425 | setup_reg_equiv (); |
4426 | setup_reg_equiv_init (); | |
058e97ec | 4427 | |
55a2c322 | 4428 | if (optimize && rebuild_p) |
b8698a0f | 4429 | { |
55a2c322 VM |
4430 | timevar_push (TV_JUMP); |
4431 | rebuild_jump_labels (get_insns ()); | |
4432 | if (purge_all_dead_edges ()) | |
4433 | delete_unreachable_blocks (); | |
4434 | timevar_pop (TV_JUMP); | |
058e97ec VM |
4435 | } |
4436 | ||
fb99ee9b | 4437 | allocated_reg_info_size = max_reg_num (); |
e8d7e3e7 | 4438 | |
dbabddf3 JJ |
4439 | if (delete_trivially_dead_insns (get_insns (), max_reg_num ())) |
4440 | df_analyze (); | |
4441 | ||
e8d7e3e7 VM |
4442 | /* It is not worth to do such improvement when we use a simple |
4443 | allocation because of -O0 usage or because the function is too | |
4444 | big. */ | |
4445 | if (ira_conflicts_p) | |
4446 | find_moveable_pseudos (); | |
acf41a74 | 4447 | |
fb99ee9b | 4448 | max_regno_before_ira = max_reg_num (); |
55a2c322 | 4449 | ira_setup_eliminable_regset (true); |
b8698a0f | 4450 | |
058e97ec VM |
4451 | ira_overall_cost = ira_reg_cost = ira_mem_cost = 0; |
4452 | ira_load_cost = ira_store_cost = ira_shuffle_cost = 0; | |
4453 | ira_move_loops_num = ira_additional_jumps_num = 0; | |
b8698a0f | 4454 | |
058e97ec | 4455 | ira_assert (current_loops == NULL); |
2608d841 VM |
4456 | if (flag_ira_region == IRA_REGION_ALL || flag_ira_region == IRA_REGION_MIXED) |
4457 | { | |
4458 | flow_loops_find (&ira_loops); | |
2608d841 | 4459 | current_loops = &ira_loops; |
544e7e78 | 4460 | record_loop_exits (); |
2608d841 | 4461 | } |
b8698a0f | 4462 | |
058e97ec VM |
4463 | if (internal_flag_ira_verbose > 0 && ira_dump_file != NULL) |
4464 | fprintf (ira_dump_file, "Building IRA IR\n"); | |
2608d841 | 4465 | loops_p = ira_build (); |
b8698a0f | 4466 | |
311aab06 | 4467 | ira_assert (ira_conflicts_p || !loops_p); |
3553f0bb VM |
4468 | |
4469 | saved_flag_ira_share_spill_slots = flag_ira_share_spill_slots; | |
de8e52f0 | 4470 | if (too_high_register_pressure_p () || cfun->calls_setjmp) |
3553f0bb | 4471 | /* It is just wasting compiler's time to pack spilled pseudos into |
de8e52f0 VM |
4472 | stack slots in this case -- prohibit it. We also do this if |
4473 | there is setjmp call because a variable not modified between | |
4474 | setjmp and longjmp the compiler is required to preserve its | |
4475 | value and sharing slots does not guarantee it. */ | |
3553f0bb VM |
4476 | flag_ira_share_spill_slots = FALSE; |
4477 | ||
cb1ca6ac | 4478 | ira_color (); |
b8698a0f | 4479 | |
058e97ec | 4480 | ira_max_point_before_emit = ira_max_point; |
b8698a0f | 4481 | |
1756cb66 VM |
4482 | ira_initiate_emit_data (); |
4483 | ||
058e97ec | 4484 | ira_emit (loops_p); |
b8698a0f | 4485 | |
55a2c322 | 4486 | max_regno = max_reg_num (); |
311aab06 | 4487 | if (ira_conflicts_p) |
058e97ec | 4488 | { |
058e97ec | 4489 | if (! loops_p) |
55a2c322 VM |
4490 | { |
4491 | if (! ira_use_lra_p) | |
4492 | ira_initiate_assign (); | |
4493 | } | |
058e97ec VM |
4494 | else |
4495 | { | |
fb99ee9b | 4496 | expand_reg_info (); |
b8698a0f | 4497 | |
55a2c322 VM |
4498 | if (ira_use_lra_p) |
4499 | { | |
4500 | ira_allocno_t a; | |
4501 | ira_allocno_iterator ai; | |
4502 | ||
4503 | FOR_EACH_ALLOCNO (a, ai) | |
4504 | ALLOCNO_REGNO (a) = REGNO (ALLOCNO_EMIT_DATA (a)->reg); | |
4505 | } | |
4506 | else | |
4507 | { | |
4508 | if (internal_flag_ira_verbose > 0 && ira_dump_file != NULL) | |
4509 | fprintf (ira_dump_file, "Flattening IR\n"); | |
4510 | ira_flattening (max_regno_before_ira, ira_max_point_before_emit); | |
4511 | } | |
058e97ec VM |
4512 | /* New insns were generated: add notes and recalculate live |
4513 | info. */ | |
4514 | df_analyze (); | |
b8698a0f | 4515 | |
544e7e78 SB |
4516 | /* ??? Rebuild the loop tree, but why? Does the loop tree |
4517 | change if new insns were generated? Can that be handled | |
4518 | by updating the loop tree incrementally? */ | |
4519 | release_recorded_exits (); | |
4520 | flow_loops_free (&ira_loops); | |
058e97ec VM |
4521 | flow_loops_find (&ira_loops); |
4522 | current_loops = &ira_loops; | |
544e7e78 | 4523 | record_loop_exits (); |
058e97ec | 4524 | |
55a2c322 VM |
4525 | if (! ira_use_lra_p) |
4526 | { | |
4527 | setup_allocno_assignment_flags (); | |
4528 | ira_initiate_assign (); | |
4529 | ira_reassign_conflict_allocnos (max_regno); | |
4530 | } | |
058e97ec VM |
4531 | } |
4532 | } | |
4533 | ||
1756cb66 VM |
4534 | ira_finish_emit_data (); |
4535 | ||
058e97ec | 4536 | setup_reg_renumber (); |
b8698a0f | 4537 | |
058e97ec | 4538 | calculate_allocation_cost (); |
b8698a0f | 4539 | |
058e97ec | 4540 | #ifdef ENABLE_IRA_CHECKING |
311aab06 | 4541 | if (ira_conflicts_p) |
058e97ec VM |
4542 | check_allocation (); |
4543 | #endif | |
b8698a0f | 4544 | |
058e97ec VM |
4545 | if (max_regno != max_regno_before_ira) |
4546 | { | |
4547 | regstat_free_n_sets_and_refs (); | |
4548 | regstat_free_ri (); | |
4549 | regstat_init_n_sets_and_refs (); | |
4550 | regstat_compute_ri (); | |
4551 | } | |
4552 | ||
058e97ec | 4553 | overall_cost_before = ira_overall_cost; |
e5b0e1ca VM |
4554 | if (! ira_conflicts_p) |
4555 | grow_reg_equivs (); | |
4556 | else | |
058e97ec VM |
4557 | { |
4558 | fix_reg_equiv_init (); | |
b8698a0f | 4559 | |
058e97ec VM |
4560 | #ifdef ENABLE_IRA_CHECKING |
4561 | print_redundant_copies (); | |
4562 | #endif | |
4563 | ||
4564 | ira_spilled_reg_stack_slots_num = 0; | |
4565 | ira_spilled_reg_stack_slots | |
4566 | = ((struct ira_spilled_reg_stack_slot *) | |
4567 | ira_allocate (max_regno | |
4568 | * sizeof (struct ira_spilled_reg_stack_slot))); | |
4569 | memset (ira_spilled_reg_stack_slots, 0, | |
4570 | max_regno * sizeof (struct ira_spilled_reg_stack_slot)); | |
4571 | } | |
6399c0ab | 4572 | allocate_initial_values (); |
e8d7e3e7 VM |
4573 | |
4574 | /* See comment for find_moveable_pseudos call. */ | |
4575 | if (ira_conflicts_p) | |
4576 | move_unallocated_pseudos (); | |
55a2c322 VM |
4577 | |
4578 | /* Restore original values. */ | |
4579 | if (lra_simple_p) | |
4580 | { | |
4581 | flag_caller_saves = saved_flag_caller_saves; | |
4582 | flag_ira_region = saved_flag_ira_region; | |
4583 | } | |
ae2b9cb6 | 4584 | } |
b8698a0f | 4585 | |
ae2b9cb6 BS |
4586 | static void |
4587 | do_reload (void) | |
4588 | { | |
4589 | basic_block bb; | |
4590 | bool need_dce; | |
4591 | ||
67463efb | 4592 | if (flag_ira_verbose < 10) |
ae2b9cb6 | 4593 | ira_dump_file = dump_file; |
058e97ec | 4594 | |
55a2c322 VM |
4595 | timevar_push (TV_RELOAD); |
4596 | if (ira_use_lra_p) | |
4597 | { | |
4598 | if (current_loops != NULL) | |
4599 | { | |
4600 | release_recorded_exits (); | |
4601 | flow_loops_free (&ira_loops); | |
4602 | free_dominance_info (CDI_DOMINATORS); | |
4603 | } | |
4604 | FOR_ALL_BB (bb) | |
4605 | bb->loop_father = NULL; | |
4606 | current_loops = NULL; | |
4607 | ||
4608 | if (ira_conflicts_p) | |
4609 | ira_free (ira_spilled_reg_stack_slots); | |
4610 | ||
4611 | ira_destroy (); | |
058e97ec | 4612 | |
55a2c322 VM |
4613 | lra (ira_dump_file); |
4614 | /* ???!!! Move it before lra () when we use ira_reg_equiv in | |
4615 | LRA. */ | |
4616 | VEC_free (reg_equivs_t, gc, reg_equivs); | |
4617 | reg_equivs = NULL; | |
4618 | need_dce = false; | |
4619 | } | |
4620 | else | |
4621 | { | |
4622 | df_set_flags (DF_NO_INSN_RESCAN); | |
4623 | build_insn_chain (); | |
4624 | ||
4625 | need_dce = reload (get_insns (), ira_conflicts_p); | |
4626 | ||
4627 | } | |
4628 | ||
4629 | timevar_pop (TV_RELOAD); | |
058e97ec | 4630 | |
058e97ec VM |
4631 | timevar_push (TV_IRA); |
4632 | ||
55a2c322 | 4633 | if (ira_conflicts_p && ! ira_use_lra_p) |
058e97ec VM |
4634 | { |
4635 | ira_free (ira_spilled_reg_stack_slots); | |
058e97ec | 4636 | ira_finish_assign (); |
b8698a0f | 4637 | } |
55a2c322 | 4638 | |
058e97ec VM |
4639 | if (internal_flag_ira_verbose > 0 && ira_dump_file != NULL |
4640 | && overall_cost_before != ira_overall_cost) | |
4641 | fprintf (ira_dump_file, "+++Overall after reload %d\n", ira_overall_cost); | |
b8698a0f | 4642 | |
3553f0bb VM |
4643 | flag_ira_share_spill_slots = saved_flag_ira_share_spill_slots; |
4644 | ||
55a2c322 | 4645 | if (! ira_use_lra_p) |
2608d841 | 4646 | { |
55a2c322 VM |
4647 | ira_destroy (); |
4648 | if (current_loops != NULL) | |
4649 | { | |
4650 | release_recorded_exits (); | |
4651 | flow_loops_free (&ira_loops); | |
4652 | free_dominance_info (CDI_DOMINATORS); | |
4653 | } | |
4654 | FOR_ALL_BB (bb) | |
4655 | bb->loop_father = NULL; | |
4656 | current_loops = NULL; | |
4657 | ||
4658 | regstat_free_ri (); | |
4659 | regstat_free_n_sets_and_refs (); | |
2608d841 | 4660 | } |
b8698a0f | 4661 | |
058e97ec | 4662 | if (optimize) |
55a2c322 | 4663 | cleanup_cfg (CLEANUP_EXPENSIVE); |
b8698a0f | 4664 | |
55a2c322 | 4665 | finish_reg_equiv (); |
058e97ec VM |
4666 | |
4667 | bitmap_obstack_release (&ira_bitmap_obstack); | |
4668 | #ifndef IRA_NO_OBSTACK | |
4669 | obstack_free (&ira_obstack, NULL); | |
4670 | #endif | |
4671 | ||
4672 | /* The code after the reload has changed so much that at this point | |
b0c11403 | 4673 | we might as well just rescan everything. Note that |
058e97ec VM |
4674 | df_rescan_all_insns is not going to help here because it does not |
4675 | touch the artificial uses and defs. */ | |
4676 | df_finish_pass (true); | |
058e97ec VM |
4677 | df_scan_alloc (NULL); |
4678 | df_scan_blocks (); | |
4679 | ||
4680 | if (optimize) | |
4681 | df_analyze (); | |
4682 | ||
b0c11403 JL |
4683 | if (need_dce && optimize) |
4684 | run_fast_dce (); | |
4685 | ||
058e97ec VM |
4686 | timevar_pop (TV_IRA); |
4687 | } | |
058e97ec | 4688 | \f |
058e97ec VM |
4689 | /* Run the integrated register allocator. */ |
4690 | static unsigned int | |
4691 | rest_of_handle_ira (void) | |
4692 | { | |
4693 | ira (dump_file); | |
4694 | return 0; | |
4695 | } | |
4696 | ||
4697 | struct rtl_opt_pass pass_ira = | |
4698 | { | |
4699 | { | |
4700 | RTL_PASS, | |
4701 | "ira", /* name */ | |
ae2b9cb6 | 4702 | NULL, /* gate */ |
058e97ec VM |
4703 | rest_of_handle_ira, /* execute */ |
4704 | NULL, /* sub */ | |
4705 | NULL, /* next */ | |
4706 | 0, /* static_pass_number */ | |
ae2b9cb6 BS |
4707 | TV_IRA, /* tv_id */ |
4708 | 0, /* properties_required */ | |
4709 | 0, /* properties_provided */ | |
4710 | 0, /* properties_destroyed */ | |
4711 | 0, /* todo_flags_start */ | |
c634f4ba | 4712 | 0, /* todo_flags_finish */ |
ae2b9cb6 BS |
4713 | } |
4714 | }; | |
4715 | ||
4716 | static unsigned int | |
4717 | rest_of_handle_reload (void) | |
4718 | { | |
4719 | do_reload (); | |
4720 | return 0; | |
4721 | } | |
4722 | ||
4723 | struct rtl_opt_pass pass_reload = | |
4724 | { | |
4725 | { | |
4726 | RTL_PASS, | |
4727 | "reload", /* name */ | |
4728 | NULL, /* gate */ | |
4729 | rest_of_handle_reload, /* execute */ | |
4730 | NULL, /* sub */ | |
4731 | NULL, /* next */ | |
4732 | 0, /* static_pass_number */ | |
4733 | TV_RELOAD, /* tv_id */ | |
058e97ec VM |
4734 | 0, /* properties_required */ |
4735 | 0, /* properties_provided */ | |
4736 | 0, /* properties_destroyed */ | |
4737 | 0, /* todo_flags_start */ | |
c634f4ba | 4738 | TODO_ggc_collect /* todo_flags_finish */ |
058e97ec VM |
4739 | } |
4740 | }; |