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058e97ec | 1 | /* Integrated Register Allocator (IRA) entry point. |
530a4800 | 2 | Copyright (C) 2006, 2007, 2008, 2009, 2010, 2011 |
058e97ec VM |
3 | Free Software Foundation, Inc. |
4 | Contributed by Vladimir Makarov <vmakarov@redhat.com>. | |
5 | ||
6 | This file is part of GCC. | |
7 | ||
8 | GCC is free software; you can redistribute it and/or modify it under | |
9 | the terms of the GNU General Public License as published by the Free | |
10 | Software Foundation; either version 3, or (at your option) any later | |
11 | version. | |
12 | ||
13 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
14 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GCC; see the file COPYING3. If not see | |
20 | <http://www.gnu.org/licenses/>. */ | |
21 | ||
22 | /* The integrated register allocator (IRA) is a | |
23 | regional register allocator performing graph coloring on a top-down | |
24 | traversal of nested regions. Graph coloring in a region is based | |
25 | on Chaitin-Briggs algorithm. It is called integrated because | |
26 | register coalescing, register live range splitting, and choosing a | |
27 | better hard register are done on-the-fly during coloring. Register | |
28 | coalescing and choosing a cheaper hard register is done by hard | |
29 | register preferencing during hard register assigning. The live | |
30 | range splitting is a byproduct of the regional register allocation. | |
31 | ||
32 | Major IRA notions are: | |
33 | ||
34 | o *Region* is a part of CFG where graph coloring based on | |
35 | Chaitin-Briggs algorithm is done. IRA can work on any set of | |
36 | nested CFG regions forming a tree. Currently the regions are | |
37 | the entire function for the root region and natural loops for | |
38 | the other regions. Therefore data structure representing a | |
39 | region is called loop_tree_node. | |
40 | ||
1756cb66 VM |
41 | o *Allocno class* is a register class used for allocation of |
42 | given allocno. It means that only hard register of given | |
43 | register class can be assigned to given allocno. In reality, | |
44 | even smaller subset of (*profitable*) hard registers can be | |
45 | assigned. In rare cases, the subset can be even smaller | |
46 | because our modification of Chaitin-Briggs algorithm requires | |
47 | that sets of hard registers can be assigned to allocnos forms a | |
48 | forest, i.e. the sets can be ordered in a way where any | |
49 | previous set is not intersected with given set or is a superset | |
50 | of given set. | |
51 | ||
52 | o *Pressure class* is a register class belonging to a set of | |
53 | register classes containing all of the hard-registers available | |
54 | for register allocation. The set of all pressure classes for a | |
55 | target is defined in the corresponding machine-description file | |
56 | according some criteria. Register pressure is calculated only | |
57 | for pressure classes and it affects some IRA decisions as | |
58 | forming allocation regions. | |
058e97ec VM |
59 | |
60 | o *Allocno* represents the live range of a pseudo-register in a | |
61 | region. Besides the obvious attributes like the corresponding | |
1756cb66 | 62 | pseudo-register number, allocno class, conflicting allocnos and |
058e97ec VM |
63 | conflicting hard-registers, there are a few allocno attributes |
64 | which are important for understanding the allocation algorithm: | |
65 | ||
1756cb66 VM |
66 | - *Live ranges*. This is a list of ranges of *program points* |
67 | where the allocno lives. Program points represent places | |
68 | where a pseudo can be born or become dead (there are | |
058e97ec VM |
69 | approximately two times more program points than the insns) |
70 | and they are represented by integers starting with 0. The | |
1756cb66 VM |
71 | live ranges are used to find conflicts between allocnos. |
72 | They also play very important role for the transformation of | |
73 | the IRA internal representation of several regions into a one | |
74 | region representation. The later is used during the reload | |
75 | pass work because each allocno represents all of the | |
76 | corresponding pseudo-registers. | |
058e97ec VM |
77 | |
78 | - *Hard-register costs*. This is a vector of size equal to the | |
1756cb66 VM |
79 | number of available hard-registers of the allocno class. The |
80 | cost of a callee-clobbered hard-register for an allocno is | |
81 | increased by the cost of save/restore code around the calls | |
82 | through the given allocno's life. If the allocno is a move | |
83 | instruction operand and another operand is a hard-register of | |
84 | the allocno class, the cost of the hard-register is decreased | |
85 | by the move cost. | |
058e97ec VM |
86 | |
87 | When an allocno is assigned, the hard-register with minimal | |
88 | full cost is used. Initially, a hard-register's full cost is | |
89 | the corresponding value from the hard-register's cost vector. | |
90 | If the allocno is connected by a *copy* (see below) to | |
91 | another allocno which has just received a hard-register, the | |
92 | cost of the hard-register is decreased. Before choosing a | |
93 | hard-register for an allocno, the allocno's current costs of | |
94 | the hard-registers are modified by the conflict hard-register | |
95 | costs of all of the conflicting allocnos which are not | |
96 | assigned yet. | |
97 | ||
98 | - *Conflict hard-register costs*. This is a vector of the same | |
99 | size as the hard-register costs vector. To permit an | |
100 | unassigned allocno to get a better hard-register, IRA uses | |
101 | this vector to calculate the final full cost of the | |
102 | available hard-registers. Conflict hard-register costs of an | |
103 | unassigned allocno are also changed with a change of the | |
104 | hard-register cost of the allocno when a copy involving the | |
105 | allocno is processed as described above. This is done to | |
106 | show other unassigned allocnos that a given allocno prefers | |
107 | some hard-registers in order to remove the move instruction | |
108 | corresponding to the copy. | |
109 | ||
110 | o *Cap*. If a pseudo-register does not live in a region but | |
111 | lives in a nested region, IRA creates a special allocno called | |
112 | a cap in the outer region. A region cap is also created for a | |
113 | subregion cap. | |
114 | ||
115 | o *Copy*. Allocnos can be connected by copies. Copies are used | |
116 | to modify hard-register costs for allocnos during coloring. | |
117 | Such modifications reflects a preference to use the same | |
118 | hard-register for the allocnos connected by copies. Usually | |
119 | copies are created for move insns (in this case it results in | |
120 | register coalescing). But IRA also creates copies for operands | |
121 | of an insn which should be assigned to the same hard-register | |
122 | due to constraints in the machine description (it usually | |
123 | results in removing a move generated in reload to satisfy | |
124 | the constraints) and copies referring to the allocno which is | |
125 | the output operand of an instruction and the allocno which is | |
126 | an input operand dying in the instruction (creation of such | |
127 | copies results in less register shuffling). IRA *does not* | |
128 | create copies between the same register allocnos from different | |
129 | regions because we use another technique for propagating | |
130 | hard-register preference on the borders of regions. | |
131 | ||
132 | Allocnos (including caps) for the upper region in the region tree | |
133 | *accumulate* information important for coloring from allocnos with | |
134 | the same pseudo-register from nested regions. This includes | |
135 | hard-register and memory costs, conflicts with hard-registers, | |
136 | allocno conflicts, allocno copies and more. *Thus, attributes for | |
137 | allocnos in a region have the same values as if the region had no | |
138 | subregions*. It means that attributes for allocnos in the | |
139 | outermost region corresponding to the function have the same values | |
140 | as though the allocation used only one region which is the entire | |
141 | function. It also means that we can look at IRA work as if the | |
142 | first IRA did allocation for all function then it improved the | |
143 | allocation for loops then their subloops and so on. | |
144 | ||
145 | IRA major passes are: | |
146 | ||
147 | o Building IRA internal representation which consists of the | |
148 | following subpasses: | |
149 | ||
150 | * First, IRA builds regions and creates allocnos (file | |
151 | ira-build.c) and initializes most of their attributes. | |
152 | ||
1756cb66 VM |
153 | * Then IRA finds an allocno class for each allocno and |
154 | calculates its initial (non-accumulated) cost of memory and | |
155 | each hard-register of its allocno class (file ira-cost.c). | |
058e97ec VM |
156 | |
157 | * IRA creates live ranges of each allocno, calulates register | |
1756cb66 | 158 | pressure for each pressure class in each region, sets up |
058e97ec VM |
159 | conflict hard registers for each allocno and info about calls |
160 | the allocno lives through (file ira-lives.c). | |
161 | ||
162 | * IRA removes low register pressure loops from the regions | |
163 | mostly to speed IRA up (file ira-build.c). | |
164 | ||
165 | * IRA propagates accumulated allocno info from lower region | |
166 | allocnos to corresponding upper region allocnos (file | |
167 | ira-build.c). | |
168 | ||
169 | * IRA creates all caps (file ira-build.c). | |
170 | ||
1756cb66 VM |
171 | * Having live-ranges of allocnos and their classes, IRA creates |
172 | conflicting allocnos for each allocno. Conflicting allocnos | |
173 | are stored as a bit vector or array of pointers to the | |
174 | conflicting allocnos whatever is more profitable (file | |
175 | ira-conflicts.c). At this point IRA creates allocno copies. | |
058e97ec VM |
176 | |
177 | o Coloring. Now IRA has all necessary info to start graph coloring | |
178 | process. It is done in each region on top-down traverse of the | |
179 | region tree (file ira-color.c). There are following subpasses: | |
b8698a0f | 180 | |
1756cb66 VM |
181 | * Finding profitable hard registers of corresponding allocno |
182 | class for each allocno. For example, only callee-saved hard | |
183 | registers are frequently profitable for allocnos living | |
184 | through colors. If the profitable hard register set of | |
185 | allocno does not form a tree based on subset relation, we use | |
186 | some approximation to form the tree. This approximation is | |
187 | used to figure out trivial colorability of allocnos. The | |
188 | approximation is a pretty rare case. | |
189 | ||
058e97ec VM |
190 | * Putting allocnos onto the coloring stack. IRA uses Briggs |
191 | optimistic coloring which is a major improvement over | |
192 | Chaitin's coloring. Therefore IRA does not spill allocnos at | |
193 | this point. There is some freedom in the order of putting | |
194 | allocnos on the stack which can affect the final result of | |
1756cb66 VM |
195 | the allocation. IRA uses some heuristics to improve the |
196 | order. | |
197 | ||
198 | We also use a modification of Chaitin-Briggs algorithm which | |
199 | works for intersected register classes of allocnos. To | |
200 | figure out trivial colorability of allocnos, the mentioned | |
201 | above tree of hard register sets is used. To get an idea how | |
202 | the algorithm works in i386 example, let us consider an | |
203 | allocno to which any general hard register can be assigned. | |
204 | If the allocno conflicts with eight allocnos to which only | |
205 | EAX register can be assigned, given allocno is still | |
206 | trivially colorable because all conflicting allocnos might be | |
207 | assigned only to EAX and all other general hard registers are | |
208 | still free. | |
209 | ||
210 | To get an idea of the used trivial colorability criterion, it | |
211 | is also useful to read article "Graph-Coloring Register | |
212 | Allocation for Irregular Architectures" by Michael D. Smith | |
213 | and Glen Holloway. Major difference between the article | |
214 | approach and approach used in IRA is that Smith's approach | |
215 | takes register classes only from machine description and IRA | |
216 | calculate register classes from intermediate code too | |
217 | (e.g. an explicit usage of hard registers in RTL code for | |
218 | parameter passing can result in creation of additional | |
219 | register classes which contain or exclude the hard | |
220 | registers). That makes IRA approach useful for improving | |
221 | coloring even for architectures with regular register files | |
222 | and in fact some benchmarking shows the improvement for | |
223 | regular class architectures is even bigger than for irregular | |
224 | ones. Another difference is that Smith's approach chooses | |
225 | intersection of classes of all insn operands in which a given | |
226 | pseudo occurs. IRA can use bigger classes if it is still | |
227 | more profitable than memory usage. | |
058e97ec VM |
228 | |
229 | * Popping the allocnos from the stack and assigning them hard | |
230 | registers. If IRA can not assign a hard register to an | |
231 | allocno and the allocno is coalesced, IRA undoes the | |
232 | coalescing and puts the uncoalesced allocnos onto the stack in | |
233 | the hope that some such allocnos will get a hard register | |
234 | separately. If IRA fails to assign hard register or memory | |
235 | is more profitable for it, IRA spills the allocno. IRA | |
236 | assigns the allocno the hard-register with minimal full | |
237 | allocation cost which reflects the cost of usage of the | |
238 | hard-register for the allocno and cost of usage of the | |
239 | hard-register for allocnos conflicting with given allocno. | |
240 | ||
1756cb66 VM |
241 | * Chaitin-Briggs coloring assigns as many pseudos as possible |
242 | to hard registers. After coloringh we try to improve | |
243 | allocation with cost point of view. We improve the | |
244 | allocation by spilling some allocnos and assigning the freed | |
245 | hard registers to other allocnos if it decreases the overall | |
246 | allocation cost. | |
247 | ||
058e97ec VM |
248 | * After allono assigning in the region, IRA modifies the hard |
249 | register and memory costs for the corresponding allocnos in | |
250 | the subregions to reflect the cost of possible loads, stores, | |
251 | or moves on the border of the region and its subregions. | |
252 | When default regional allocation algorithm is used | |
253 | (-fira-algorithm=mixed), IRA just propagates the assignment | |
254 | for allocnos if the register pressure in the region for the | |
1756cb66 VM |
255 | corresponding pressure class is less than number of available |
256 | hard registers for given pressure class. | |
058e97ec VM |
257 | |
258 | o Spill/restore code moving. When IRA performs an allocation | |
259 | by traversing regions in top-down order, it does not know what | |
260 | happens below in the region tree. Therefore, sometimes IRA | |
261 | misses opportunities to perform a better allocation. A simple | |
262 | optimization tries to improve allocation in a region having | |
263 | subregions and containing in another region. If the | |
264 | corresponding allocnos in the subregion are spilled, it spills | |
265 | the region allocno if it is profitable. The optimization | |
266 | implements a simple iterative algorithm performing profitable | |
267 | transformations while they are still possible. It is fast in | |
268 | practice, so there is no real need for a better time complexity | |
269 | algorithm. | |
270 | ||
1756cb66 VM |
271 | o Code change. After coloring, two allocnos representing the |
272 | same pseudo-register outside and inside a region respectively | |
273 | may be assigned to different locations (hard-registers or | |
274 | memory). In this case IRA creates and uses a new | |
275 | pseudo-register inside the region and adds code to move allocno | |
276 | values on the region's borders. This is done during top-down | |
277 | traversal of the regions (file ira-emit.c). In some | |
278 | complicated cases IRA can create a new allocno to move allocno | |
279 | values (e.g. when a swap of values stored in two hard-registers | |
280 | is needed). At this stage, the new allocno is marked as | |
281 | spilled. IRA still creates the pseudo-register and the moves | |
282 | on the region borders even when both allocnos were assigned to | |
283 | the same hard-register. If the reload pass spills a | |
284 | pseudo-register for some reason, the effect will be smaller | |
285 | because another allocno will still be in the hard-register. In | |
286 | most cases, this is better then spilling both allocnos. If | |
287 | reload does not change the allocation for the two | |
288 | pseudo-registers, the trivial move will be removed by | |
289 | post-reload optimizations. IRA does not generate moves for | |
058e97ec VM |
290 | allocnos assigned to the same hard register when the default |
291 | regional allocation algorithm is used and the register pressure | |
1756cb66 VM |
292 | in the region for the corresponding pressure class is less than |
293 | number of available hard registers for given pressure class. | |
058e97ec VM |
294 | IRA also does some optimizations to remove redundant stores and |
295 | to reduce code duplication on the region borders. | |
296 | ||
297 | o Flattening internal representation. After changing code, IRA | |
298 | transforms its internal representation for several regions into | |
299 | one region representation (file ira-build.c). This process is | |
300 | called IR flattening. Such process is more complicated than IR | |
301 | rebuilding would be, but is much faster. | |
302 | ||
303 | o After IR flattening, IRA tries to assign hard registers to all | |
304 | spilled allocnos. This is impelemented by a simple and fast | |
305 | priority coloring algorithm (see function | |
306 | ira_reassign_conflict_allocnos::ira-color.c). Here new allocnos | |
307 | created during the code change pass can be assigned to hard | |
308 | registers. | |
309 | ||
310 | o At the end IRA calls the reload pass. The reload pass | |
311 | communicates with IRA through several functions in file | |
312 | ira-color.c to improve its decisions in | |
313 | ||
314 | * sharing stack slots for the spilled pseudos based on IRA info | |
315 | about pseudo-register conflicts. | |
316 | ||
317 | * reassigning hard-registers to all spilled pseudos at the end | |
318 | of each reload iteration. | |
319 | ||
320 | * choosing a better hard-register to spill based on IRA info | |
321 | about pseudo-register live ranges and the register pressure | |
322 | in places where the pseudo-register lives. | |
323 | ||
324 | IRA uses a lot of data representing the target processors. These | |
325 | data are initilized in file ira.c. | |
326 | ||
327 | If function has no loops (or the loops are ignored when | |
328 | -fira-algorithm=CB is used), we have classic Chaitin-Briggs | |
329 | coloring (only instead of separate pass of coalescing, we use hard | |
330 | register preferencing). In such case, IRA works much faster | |
331 | because many things are not made (like IR flattening, the | |
332 | spill/restore optimization, and the code change). | |
333 | ||
334 | Literature is worth to read for better understanding the code: | |
335 | ||
336 | o Preston Briggs, Keith D. Cooper, Linda Torczon. Improvements to | |
337 | Graph Coloring Register Allocation. | |
338 | ||
339 | o David Callahan, Brian Koblenz. Register allocation via | |
340 | hierarchical graph coloring. | |
341 | ||
342 | o Keith Cooper, Anshuman Dasgupta, Jason Eckhardt. Revisiting Graph | |
343 | Coloring Register Allocation: A Study of the Chaitin-Briggs and | |
344 | Callahan-Koblenz Algorithms. | |
345 | ||
346 | o Guei-Yuan Lueh, Thomas Gross, and Ali-Reza Adl-Tabatabai. Global | |
347 | Register Allocation Based on Graph Fusion. | |
348 | ||
1756cb66 VM |
349 | o Michael D. Smith and Glenn Holloway. Graph-Coloring Register |
350 | Allocation for Irregular Architectures | |
351 | ||
058e97ec VM |
352 | o Vladimir Makarov. The Integrated Register Allocator for GCC. |
353 | ||
354 | o Vladimir Makarov. The top-down register allocator for irregular | |
355 | register file architectures. | |
356 | ||
357 | */ | |
358 | ||
359 | ||
360 | #include "config.h" | |
361 | #include "system.h" | |
362 | #include "coretypes.h" | |
363 | #include "tm.h" | |
364 | #include "regs.h" | |
365 | #include "rtl.h" | |
366 | #include "tm_p.h" | |
367 | #include "target.h" | |
368 | #include "flags.h" | |
369 | #include "obstack.h" | |
370 | #include "bitmap.h" | |
371 | #include "hard-reg-set.h" | |
372 | #include "basic-block.h" | |
7a8cba34 | 373 | #include "df.h" |
058e97ec VM |
374 | #include "expr.h" |
375 | #include "recog.h" | |
376 | #include "params.h" | |
377 | #include "timevar.h" | |
378 | #include "tree-pass.h" | |
379 | #include "output.h" | |
2af2dbdc | 380 | #include "except.h" |
058e97ec | 381 | #include "reload.h" |
718f9c0f | 382 | #include "diagnostic-core.h" |
058e97ec | 383 | #include "integrate.h" |
058e97ec VM |
384 | #include "ggc.h" |
385 | #include "ira-int.h" | |
386 | ||
387 | ||
afcc66c4 RS |
388 | struct target_ira default_target_ira; |
389 | struct target_ira_int default_target_ira_int; | |
390 | #if SWITCHABLE_TARGET | |
391 | struct target_ira *this_target_ira = &default_target_ira; | |
392 | struct target_ira_int *this_target_ira_int = &default_target_ira_int; | |
393 | #endif | |
394 | ||
058e97ec VM |
395 | /* A modified value of flag `-fira-verbose' used internally. */ |
396 | int internal_flag_ira_verbose; | |
397 | ||
398 | /* Dump file of the allocator if it is not NULL. */ | |
399 | FILE *ira_dump_file; | |
400 | ||
058e97ec VM |
401 | /* The number of elements in the following array. */ |
402 | int ira_spilled_reg_stack_slots_num; | |
403 | ||
404 | /* The following array contains info about spilled pseudo-registers | |
405 | stack slots used in current function so far. */ | |
406 | struct ira_spilled_reg_stack_slot *ira_spilled_reg_stack_slots; | |
407 | ||
408 | /* Correspondingly overall cost of the allocation, cost of the | |
409 | allocnos assigned to hard-registers, cost of the allocnos assigned | |
410 | to memory, cost of loads, stores and register move insns generated | |
411 | for pseudo-register live range splitting (see ira-emit.c). */ | |
412 | int ira_overall_cost; | |
413 | int ira_reg_cost, ira_mem_cost; | |
414 | int ira_load_cost, ira_store_cost, ira_shuffle_cost; | |
415 | int ira_move_loops_num, ira_additional_jumps_num; | |
416 | ||
2af2dbdc VM |
417 | /* All registers that can be eliminated. */ |
418 | ||
419 | HARD_REG_SET eliminable_regset; | |
420 | ||
058e97ec VM |
421 | /* Temporary hard reg set used for a different calculation. */ |
422 | static HARD_REG_SET temp_hard_regset; | |
423 | ||
424 | \f | |
425 | ||
426 | /* The function sets up the map IRA_REG_MODE_HARD_REGSET. */ | |
427 | static void | |
428 | setup_reg_mode_hard_regset (void) | |
429 | { | |
430 | int i, m, hard_regno; | |
431 | ||
432 | for (m = 0; m < NUM_MACHINE_MODES; m++) | |
433 | for (hard_regno = 0; hard_regno < FIRST_PSEUDO_REGISTER; hard_regno++) | |
434 | { | |
435 | CLEAR_HARD_REG_SET (ira_reg_mode_hard_regset[hard_regno][m]); | |
436 | for (i = hard_regno_nregs[hard_regno][m] - 1; i >= 0; i--) | |
437 | if (hard_regno + i < FIRST_PSEUDO_REGISTER) | |
438 | SET_HARD_REG_BIT (ira_reg_mode_hard_regset[hard_regno][m], | |
439 | hard_regno + i); | |
440 | } | |
441 | } | |
442 | ||
443 | \f | |
afcc66c4 RS |
444 | #define no_unit_alloc_regs \ |
445 | (this_target_ira_int->x_no_unit_alloc_regs) | |
058e97ec VM |
446 | |
447 | /* The function sets up the three arrays declared above. */ | |
448 | static void | |
449 | setup_class_hard_regs (void) | |
450 | { | |
451 | int cl, i, hard_regno, n; | |
452 | HARD_REG_SET processed_hard_reg_set; | |
453 | ||
454 | ira_assert (SHRT_MAX >= FIRST_PSEUDO_REGISTER); | |
058e97ec VM |
455 | for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) |
456 | { | |
457 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); | |
458 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
459 | CLEAR_HARD_REG_SET (processed_hard_reg_set); | |
7db7ed3c | 460 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
0583835c | 461 | { |
854edfcd VM |
462 | ira_non_ordered_class_hard_regs[cl][i] = -1; |
463 | ira_class_hard_reg_index[cl][i] = -1; | |
0583835c | 464 | } |
058e97ec VM |
465 | for (n = 0, i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
466 | { | |
467 | #ifdef REG_ALLOC_ORDER | |
468 | hard_regno = reg_alloc_order[i]; | |
469 | #else | |
470 | hard_regno = i; | |
b8698a0f | 471 | #endif |
058e97ec VM |
472 | if (TEST_HARD_REG_BIT (processed_hard_reg_set, hard_regno)) |
473 | continue; | |
474 | SET_HARD_REG_BIT (processed_hard_reg_set, hard_regno); | |
475 | if (! TEST_HARD_REG_BIT (temp_hard_regset, hard_regno)) | |
476 | ira_class_hard_reg_index[cl][hard_regno] = -1; | |
477 | else | |
478 | { | |
479 | ira_class_hard_reg_index[cl][hard_regno] = n; | |
480 | ira_class_hard_regs[cl][n++] = hard_regno; | |
481 | } | |
482 | } | |
483 | ira_class_hard_regs_num[cl] = n; | |
0583835c VM |
484 | for (n = 0, i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
485 | if (TEST_HARD_REG_BIT (temp_hard_regset, i)) | |
486 | ira_non_ordered_class_hard_regs[cl][n++] = i; | |
487 | ira_assert (ira_class_hard_regs_num[cl] == n); | |
058e97ec VM |
488 | } |
489 | } | |
490 | ||
058e97ec VM |
491 | /* Set up IRA_AVAILABLE_CLASS_REGS. */ |
492 | static void | |
493 | setup_available_class_regs (void) | |
494 | { | |
495 | int i, j; | |
496 | ||
497 | memset (ira_available_class_regs, 0, sizeof (ira_available_class_regs)); | |
498 | for (i = 0; i < N_REG_CLASSES; i++) | |
499 | { | |
500 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[i]); | |
501 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
502 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
503 | if (TEST_HARD_REG_BIT (temp_hard_regset, j)) | |
504 | ira_available_class_regs[i]++; | |
505 | } | |
506 | } | |
507 | ||
508 | /* Set up global variables defining info about hard registers for the | |
509 | allocation. These depend on USE_HARD_FRAME_P whose TRUE value means | |
510 | that we can use the hard frame pointer for the allocation. */ | |
511 | static void | |
512 | setup_alloc_regs (bool use_hard_frame_p) | |
513 | { | |
5a733826 BS |
514 | #ifdef ADJUST_REG_ALLOC_ORDER |
515 | ADJUST_REG_ALLOC_ORDER; | |
516 | #endif | |
058e97ec VM |
517 | COPY_HARD_REG_SET (no_unit_alloc_regs, fixed_reg_set); |
518 | if (! use_hard_frame_p) | |
519 | SET_HARD_REG_BIT (no_unit_alloc_regs, HARD_FRAME_POINTER_REGNUM); | |
520 | setup_class_hard_regs (); | |
521 | setup_available_class_regs (); | |
522 | } | |
523 | ||
524 | \f | |
525 | ||
1756cb66 VM |
526 | #define alloc_reg_class_subclasses \ |
527 | (this_target_ira_int->x_alloc_reg_class_subclasses) | |
528 | ||
529 | /* Initialize the table of subclasses of each reg class. */ | |
530 | static void | |
531 | setup_reg_subclasses (void) | |
532 | { | |
533 | int i, j; | |
534 | HARD_REG_SET temp_hard_regset2; | |
535 | ||
536 | for (i = 0; i < N_REG_CLASSES; i++) | |
537 | for (j = 0; j < N_REG_CLASSES; j++) | |
538 | alloc_reg_class_subclasses[i][j] = LIM_REG_CLASSES; | |
539 | ||
540 | for (i = 0; i < N_REG_CLASSES; i++) | |
541 | { | |
542 | if (i == (int) NO_REGS) | |
543 | continue; | |
544 | ||
545 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[i]); | |
546 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
547 | if (hard_reg_set_empty_p (temp_hard_regset)) | |
548 | continue; | |
549 | for (j = 0; j < N_REG_CLASSES; j++) | |
550 | if (i != j) | |
551 | { | |
552 | enum reg_class *p; | |
553 | ||
554 | COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[j]); | |
555 | AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs); | |
556 | if (! hard_reg_set_subset_p (temp_hard_regset, | |
557 | temp_hard_regset2)) | |
558 | continue; | |
559 | p = &alloc_reg_class_subclasses[j][0]; | |
560 | while (*p != LIM_REG_CLASSES) p++; | |
561 | *p = (enum reg_class) i; | |
562 | } | |
563 | } | |
564 | } | |
565 | ||
566 | \f | |
567 | ||
568 | /* Set up IRA_MEMORY_MOVE_COST and IRA_MAX_MEMORY_MOVE_COST. */ | |
058e97ec VM |
569 | static void |
570 | setup_class_subset_and_memory_move_costs (void) | |
571 | { | |
1756cb66 | 572 | int cl, cl2, mode, cost; |
058e97ec VM |
573 | HARD_REG_SET temp_hard_regset2; |
574 | ||
575 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
576 | ira_memory_move_cost[mode][NO_REGS][0] | |
577 | = ira_memory_move_cost[mode][NO_REGS][1] = SHRT_MAX; | |
578 | for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) | |
579 | { | |
580 | if (cl != (int) NO_REGS) | |
581 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
582 | { | |
1756cb66 VM |
583 | ira_max_memory_move_cost[mode][cl][0] |
584 | = ira_memory_move_cost[mode][cl][0] | |
585 | = memory_move_cost ((enum machine_mode) mode, | |
586 | (enum reg_class) cl, false); | |
587 | ira_max_memory_move_cost[mode][cl][1] | |
588 | = ira_memory_move_cost[mode][cl][1] | |
589 | = memory_move_cost ((enum machine_mode) mode, | |
590 | (enum reg_class) cl, true); | |
058e97ec VM |
591 | /* Costs for NO_REGS are used in cost calculation on the |
592 | 1st pass when the preferred register classes are not | |
593 | known yet. In this case we take the best scenario. */ | |
594 | if (ira_memory_move_cost[mode][NO_REGS][0] | |
595 | > ira_memory_move_cost[mode][cl][0]) | |
1756cb66 VM |
596 | ira_max_memory_move_cost[mode][NO_REGS][0] |
597 | = ira_memory_move_cost[mode][NO_REGS][0] | |
058e97ec VM |
598 | = ira_memory_move_cost[mode][cl][0]; |
599 | if (ira_memory_move_cost[mode][NO_REGS][1] | |
600 | > ira_memory_move_cost[mode][cl][1]) | |
1756cb66 VM |
601 | ira_max_memory_move_cost[mode][NO_REGS][1] |
602 | = ira_memory_move_cost[mode][NO_REGS][1] | |
058e97ec VM |
603 | = ira_memory_move_cost[mode][cl][1]; |
604 | } | |
058e97ec | 605 | } |
1756cb66 VM |
606 | for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) |
607 | for (cl2 = (int) N_REG_CLASSES - 1; cl2 >= 0; cl2--) | |
608 | { | |
609 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); | |
610 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
611 | COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl2]); | |
612 | AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs); | |
613 | ira_class_subset_p[cl][cl2] | |
614 | = hard_reg_set_subset_p (temp_hard_regset, temp_hard_regset2); | |
615 | if (! hard_reg_set_empty_p (temp_hard_regset2) | |
616 | && hard_reg_set_subset_p (reg_class_contents[cl2], | |
617 | reg_class_contents[cl])) | |
618 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
619 | { | |
620 | cost = ira_memory_move_cost[mode][cl2][0]; | |
621 | if (cost > ira_max_memory_move_cost[mode][cl][0]) | |
622 | ira_max_memory_move_cost[mode][cl][0] = cost; | |
623 | cost = ira_memory_move_cost[mode][cl2][1]; | |
624 | if (cost > ira_max_memory_move_cost[mode][cl][1]) | |
625 | ira_max_memory_move_cost[mode][cl][1] = cost; | |
626 | } | |
627 | } | |
628 | for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) | |
629 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
630 | { | |
631 | ira_memory_move_cost[mode][cl][0] | |
632 | = ira_max_memory_move_cost[mode][cl][0]; | |
633 | ira_memory_move_cost[mode][cl][1] | |
634 | = ira_max_memory_move_cost[mode][cl][1]; | |
635 | } | |
636 | setup_reg_subclasses (); | |
058e97ec VM |
637 | } |
638 | ||
639 | \f | |
640 | ||
641 | /* Define the following macro if allocation through malloc if | |
642 | preferable. */ | |
643 | #define IRA_NO_OBSTACK | |
644 | ||
645 | #ifndef IRA_NO_OBSTACK | |
646 | /* Obstack used for storing all dynamic data (except bitmaps) of the | |
647 | IRA. */ | |
648 | static struct obstack ira_obstack; | |
649 | #endif | |
650 | ||
651 | /* Obstack used for storing all bitmaps of the IRA. */ | |
652 | static struct bitmap_obstack ira_bitmap_obstack; | |
653 | ||
654 | /* Allocate memory of size LEN for IRA data. */ | |
655 | void * | |
656 | ira_allocate (size_t len) | |
657 | { | |
658 | void *res; | |
659 | ||
660 | #ifndef IRA_NO_OBSTACK | |
661 | res = obstack_alloc (&ira_obstack, len); | |
662 | #else | |
663 | res = xmalloc (len); | |
664 | #endif | |
665 | return res; | |
666 | } | |
667 | ||
058e97ec VM |
668 | /* Free memory ADDR allocated for IRA data. */ |
669 | void | |
670 | ira_free (void *addr ATTRIBUTE_UNUSED) | |
671 | { | |
672 | #ifndef IRA_NO_OBSTACK | |
673 | /* do nothing */ | |
674 | #else | |
675 | free (addr); | |
676 | #endif | |
677 | } | |
678 | ||
679 | ||
680 | /* Allocate and returns bitmap for IRA. */ | |
681 | bitmap | |
682 | ira_allocate_bitmap (void) | |
683 | { | |
684 | return BITMAP_ALLOC (&ira_bitmap_obstack); | |
685 | } | |
686 | ||
687 | /* Free bitmap B allocated for IRA. */ | |
688 | void | |
689 | ira_free_bitmap (bitmap b ATTRIBUTE_UNUSED) | |
690 | { | |
691 | /* do nothing */ | |
692 | } | |
693 | ||
694 | \f | |
695 | ||
696 | /* Output information about allocation of all allocnos (except for | |
697 | caps) into file F. */ | |
698 | void | |
699 | ira_print_disposition (FILE *f) | |
700 | { | |
701 | int i, n, max_regno; | |
702 | ira_allocno_t a; | |
703 | basic_block bb; | |
704 | ||
705 | fprintf (f, "Disposition:"); | |
706 | max_regno = max_reg_num (); | |
707 | for (n = 0, i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
708 | for (a = ira_regno_allocno_map[i]; | |
709 | a != NULL; | |
710 | a = ALLOCNO_NEXT_REGNO_ALLOCNO (a)) | |
711 | { | |
712 | if (n % 4 == 0) | |
713 | fprintf (f, "\n"); | |
714 | n++; | |
715 | fprintf (f, " %4d:r%-4d", ALLOCNO_NUM (a), ALLOCNO_REGNO (a)); | |
716 | if ((bb = ALLOCNO_LOOP_TREE_NODE (a)->bb) != NULL) | |
717 | fprintf (f, "b%-3d", bb->index); | |
718 | else | |
719 | fprintf (f, "l%-3d", ALLOCNO_LOOP_TREE_NODE (a)->loop->num); | |
720 | if (ALLOCNO_HARD_REGNO (a) >= 0) | |
721 | fprintf (f, " %3d", ALLOCNO_HARD_REGNO (a)); | |
722 | else | |
723 | fprintf (f, " mem"); | |
724 | } | |
725 | fprintf (f, "\n"); | |
726 | } | |
727 | ||
728 | /* Outputs information about allocation of all allocnos into | |
729 | stderr. */ | |
730 | void | |
731 | ira_debug_disposition (void) | |
732 | { | |
733 | ira_print_disposition (stderr); | |
734 | } | |
735 | ||
736 | \f | |
058e97ec | 737 | |
1756cb66 VM |
738 | /* Set up ira_stack_reg_pressure_class which is the biggest pressure |
739 | register class containing stack registers or NO_REGS if there are | |
740 | no stack registers. To find this class, we iterate through all | |
741 | register pressure classes and choose the first register pressure | |
742 | class containing all the stack registers and having the biggest | |
743 | size. */ | |
fe82cdfb | 744 | static void |
1756cb66 VM |
745 | setup_stack_reg_pressure_class (void) |
746 | { | |
747 | ira_stack_reg_pressure_class = NO_REGS; | |
748 | #ifdef STACK_REGS | |
749 | { | |
750 | int i, best, size; | |
751 | enum reg_class cl; | |
752 | HARD_REG_SET temp_hard_regset2; | |
753 | ||
754 | CLEAR_HARD_REG_SET (temp_hard_regset); | |
755 | for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++) | |
756 | SET_HARD_REG_BIT (temp_hard_regset, i); | |
757 | best = 0; | |
758 | for (i = 0; i < ira_pressure_classes_num; i++) | |
759 | { | |
760 | cl = ira_pressure_classes[i]; | |
761 | COPY_HARD_REG_SET (temp_hard_regset2, temp_hard_regset); | |
762 | AND_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl]); | |
763 | size = hard_reg_set_size (temp_hard_regset2); | |
764 | if (best < size) | |
765 | { | |
766 | best = size; | |
767 | ira_stack_reg_pressure_class = cl; | |
768 | } | |
769 | } | |
770 | } | |
771 | #endif | |
772 | } | |
773 | ||
774 | /* Find pressure classes which are register classes for which we | |
775 | calculate register pressure in IRA, register pressure sensitive | |
776 | insn scheduling, and register pressure sensitive loop invariant | |
777 | motion. | |
778 | ||
779 | To make register pressure calculation easy, we always use | |
780 | non-intersected register pressure classes. A move of hard | |
781 | registers from one register pressure class is not more expensive | |
782 | than load and store of the hard registers. Most likely an allocno | |
783 | class will be a subset of a register pressure class and in many | |
784 | cases a register pressure class. That makes usage of register | |
785 | pressure classes a good approximation to find a high register | |
786 | pressure. */ | |
787 | static void | |
788 | setup_pressure_classes (void) | |
058e97ec | 789 | { |
1756cb66 VM |
790 | int cost, i, n, curr; |
791 | int cl, cl2; | |
792 | enum reg_class pressure_classes[N_REG_CLASSES]; | |
793 | int m; | |
058e97ec | 794 | HARD_REG_SET temp_hard_regset2; |
1756cb66 | 795 | bool insert_p; |
058e97ec | 796 | |
1756cb66 VM |
797 | n = 0; |
798 | for (cl = 0; cl < N_REG_CLASSES; cl++) | |
058e97ec | 799 | { |
1756cb66 | 800 | if (ira_available_class_regs[cl] == 0) |
058e97ec | 801 | continue; |
1756cb66 VM |
802 | /* Check that the moves between any hard registers of the |
803 | current class are not more expensive for a legal mode than | |
804 | load/store of the hard registers of the current class. Such | |
805 | class is a potential candidate to be a register pressure | |
806 | class. */ | |
807 | for (m = 0; m < NUM_MACHINE_MODES; m++) | |
808 | { | |
809 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); | |
810 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
811 | AND_COMPL_HARD_REG_SET (temp_hard_regset, | |
812 | ira_prohibited_class_mode_regs[cl][m]); | |
813 | if (hard_reg_set_empty_p (temp_hard_regset)) | |
814 | continue; | |
815 | ira_init_register_move_cost_if_necessary ((enum machine_mode) m); | |
816 | cost = ira_register_move_cost[m][cl][cl]; | |
817 | if (cost <= ira_max_memory_move_cost[m][cl][1] | |
818 | || cost <= ira_max_memory_move_cost[m][cl][0]) | |
819 | break; | |
820 | } | |
821 | if (m >= NUM_MACHINE_MODES) | |
99710245 | 822 | continue; |
1756cb66 VM |
823 | curr = 0; |
824 | insert_p = true; | |
825 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); | |
826 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
827 | /* Remove so far added pressure classes which are subset of the | |
828 | current candidate class. Prefer GENERAL_REGS as a pressure | |
829 | register class to another class containing the same | |
830 | allocatable hard registers. We do this because machine | |
831 | dependent cost hooks might give wrong costs for the latter | |
832 | class but always give the right cost for the former class | |
833 | (GENERAL_REGS). */ | |
834 | for (i = 0; i < n; i++) | |
835 | { | |
836 | cl2 = pressure_classes[i]; | |
837 | COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl2]); | |
838 | AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs); | |
839 | if (hard_reg_set_subset_p (temp_hard_regset, temp_hard_regset2) | |
840 | && (! hard_reg_set_equal_p (temp_hard_regset, temp_hard_regset2) | |
841 | || cl2 == (int) GENERAL_REGS)) | |
842 | { | |
843 | pressure_classes[curr++] = (enum reg_class) cl2; | |
844 | insert_p = false; | |
058e97ec | 845 | continue; |
1756cb66 VM |
846 | } |
847 | if (hard_reg_set_subset_p (temp_hard_regset2, temp_hard_regset) | |
848 | && (! hard_reg_set_equal_p (temp_hard_regset2, temp_hard_regset) | |
849 | || cl == (int) GENERAL_REGS)) | |
850 | continue; | |
851 | pressure_classes[curr++] = (enum reg_class) cl2; | |
852 | } | |
853 | /* If the current candidate is a subset of a so far added | |
854 | pressure class, don't add it to the list of the pressure | |
855 | classes. */ | |
856 | if (insert_p) | |
857 | pressure_classes[curr++] = (enum reg_class) cl; | |
858 | n = curr; | |
fe82cdfb | 859 | } |
1756cb66 VM |
860 | #ifdef ENABLE_IRA_CHECKING |
861 | /* Check pressure classes correctness: here we check that hard | |
862 | registers from all register pressure classes contains all hard | |
863 | registers available for the allocation. */ | |
864 | CLEAR_HARD_REG_SET (temp_hard_regset); | |
865 | CLEAR_HARD_REG_SET (temp_hard_regset2); | |
866 | for (cl = 0; cl <= LIM_REG_CLASSES; cl++) | |
867 | { | |
868 | for (i = 0; i < n; i++) | |
869 | if ((int) pressure_classes[i] == cl) | |
870 | break; | |
871 | IOR_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl]); | |
872 | if (i >= n) | |
873 | IOR_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); | |
874 | } | |
875 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
876 | AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs); | |
877 | ira_assert (hard_reg_set_subset_p (temp_hard_regset2, temp_hard_regset)); | |
878 | #endif | |
879 | ira_pressure_classes_num = 0; | |
880 | for (i = 0; i < n; i++) | |
881 | { | |
882 | cl = (int) pressure_classes[i]; | |
883 | ira_reg_pressure_class_p[cl] = true; | |
884 | ira_pressure_classes[ira_pressure_classes_num++] = (enum reg_class) cl; | |
885 | } | |
886 | setup_stack_reg_pressure_class (); | |
058e97ec VM |
887 | } |
888 | ||
1756cb66 VM |
889 | /* Set up IRA_ALLOCNO_CLASSES, IRA_ALLOCNO_CLASSES_NUM, |
890 | IRA_IMPORTANT_CLASSES, and IRA_IMPORTANT_CLASSES_NUM. | |
891 | ||
892 | Target may have many subtargets and not all target hard regiters can | |
893 | be used for allocation, e.g. x86 port in 32-bit mode can not use | |
894 | hard registers introduced in x86-64 like r8-r15). Some classes | |
895 | might have the same allocatable hard registers, e.g. INDEX_REGS | |
896 | and GENERAL_REGS in x86 port in 32-bit mode. To decrease different | |
897 | calculations efforts we introduce allocno classes which contain | |
898 | unique non-empty sets of allocatable hard-registers. | |
899 | ||
900 | Pseudo class cost calculation in ira-costs.c is very expensive. | |
901 | Therefore we are trying to decrease number of classes involved in | |
902 | such calculation. Register classes used in the cost calculation | |
903 | are called important classes. They are allocno classes and other | |
904 | non-empty classes whose allocatable hard register sets are inside | |
905 | of an allocno class hard register set. From the first sight, it | |
906 | looks like that they are just allocno classes. It is not true. In | |
907 | example of x86-port in 32-bit mode, allocno classes will contain | |
908 | GENERAL_REGS but not LEGACY_REGS (because allocatable hard | |
909 | registers are the same for the both classes). The important | |
910 | classes will contain GENERAL_REGS and LEGACY_REGS. It is done | |
911 | because a machine description insn constraint may refers for | |
912 | LEGACY_REGS and code in ira-costs.c is mostly base on investigation | |
913 | of the insn constraints. */ | |
058e97ec | 914 | static void |
1756cb66 | 915 | setup_allocno_and_important_classes (void) |
058e97ec | 916 | { |
32e8bb8e | 917 | int i, j, n, cl; |
db1a8d98 | 918 | bool set_p; |
058e97ec | 919 | HARD_REG_SET temp_hard_regset2; |
7db7ed3c VM |
920 | static enum reg_class classes[LIM_REG_CLASSES + 1]; |
921 | ||
1756cb66 VM |
922 | n = 0; |
923 | /* Collect classes which contain unique sets of allocatable hard | |
924 | registers. Prefer GENERAL_REGS to other classes containing the | |
925 | same set of hard registers. */ | |
926 | for (i = 0; i <= LIM_REG_CLASSES; i++) | |
99710245 | 927 | { |
1756cb66 VM |
928 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[i]); |
929 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
930 | for (j = 0; j < n; j++) | |
7db7ed3c | 931 | { |
1756cb66 VM |
932 | cl = classes[j]; |
933 | COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl]); | |
934 | AND_COMPL_HARD_REG_SET (temp_hard_regset2, | |
935 | no_unit_alloc_regs); | |
936 | if (hard_reg_set_equal_p (temp_hard_regset, | |
937 | temp_hard_regset2)) | |
938 | break; | |
7db7ed3c | 939 | } |
1756cb66 VM |
940 | if (j >= n) |
941 | classes[n++] = (enum reg_class) i; | |
942 | else if (i == GENERAL_REGS) | |
943 | /* Prefer general regs. For i386 example, it means that | |
944 | we prefer GENERAL_REGS over INDEX_REGS or LEGACY_REGS | |
945 | (all of them consists of the same available hard | |
946 | registers). */ | |
947 | classes[j] = (enum reg_class) i; | |
7db7ed3c | 948 | } |
1756cb66 | 949 | classes[n] = LIM_REG_CLASSES; |
058e97ec | 950 | |
1756cb66 VM |
951 | /* Set up classes which can be used for allocnos as classes |
952 | conatining non-empty unique sets of allocatable hard | |
953 | registers. */ | |
954 | ira_allocno_classes_num = 0; | |
058e97ec VM |
955 | for (i = 0; (cl = classes[i]) != LIM_REG_CLASSES; i++) |
956 | { | |
058e97ec VM |
957 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); |
958 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
1756cb66 VM |
959 | if (hard_reg_set_empty_p (temp_hard_regset)) |
960 | continue; | |
961 | ira_allocno_classes[ira_allocno_classes_num++] = (enum reg_class) cl; | |
058e97ec VM |
962 | } |
963 | ira_important_classes_num = 0; | |
1756cb66 VM |
964 | /* Add non-allocno classes containing to non-empty set of |
965 | allocatable hard regs. */ | |
058e97ec VM |
966 | for (cl = 0; cl < N_REG_CLASSES; cl++) |
967 | { | |
968 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); | |
969 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
4f341ea0 | 970 | if (! hard_reg_set_empty_p (temp_hard_regset)) |
7db7ed3c | 971 | { |
db1a8d98 | 972 | set_p = false; |
1756cb66 | 973 | for (j = 0; j < ira_allocno_classes_num; j++) |
7db7ed3c | 974 | { |
7db7ed3c | 975 | COPY_HARD_REG_SET (temp_hard_regset2, |
1756cb66 | 976 | reg_class_contents[ira_allocno_classes[j]]); |
7db7ed3c | 977 | AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs); |
1756cb66 | 978 | if ((enum reg_class) cl == ira_allocno_classes[j]) |
db1a8d98 | 979 | break; |
7db7ed3c VM |
980 | else if (hard_reg_set_subset_p (temp_hard_regset, |
981 | temp_hard_regset2)) | |
982 | set_p = true; | |
983 | } | |
1756cb66 | 984 | if (set_p && j >= ira_allocno_classes_num) |
db1a8d98 VM |
985 | ira_important_classes[ira_important_classes_num++] |
986 | = (enum reg_class) cl; | |
7db7ed3c | 987 | } |
058e97ec | 988 | } |
1756cb66 VM |
989 | /* Now add allocno classes to the important classes. */ |
990 | for (j = 0; j < ira_allocno_classes_num; j++) | |
db1a8d98 | 991 | ira_important_classes[ira_important_classes_num++] |
1756cb66 VM |
992 | = ira_allocno_classes[j]; |
993 | for (cl = 0; cl < N_REG_CLASSES; cl++) | |
994 | { | |
995 | ira_reg_allocno_class_p[cl] = false; | |
996 | ira_reg_pressure_class_p[cl] = false; | |
997 | } | |
998 | for (j = 0; j < ira_allocno_classes_num; j++) | |
999 | ira_reg_allocno_class_p[ira_allocno_classes[j]] = true; | |
1000 | setup_pressure_classes (); | |
058e97ec | 1001 | } |
058e97ec | 1002 | |
1756cb66 VM |
1003 | /* Setup translation in CLASS_TRANSLATE of all classes into a class |
1004 | given by array CLASSES of length CLASSES_NUM. The function is used | |
1005 | make translation any reg class to an allocno class or to an | |
1006 | pressure class. This translation is necessary for some | |
1007 | calculations when we can use only allocno or pressure classes and | |
1008 | such translation represents an approximate representation of all | |
1009 | classes. | |
1010 | ||
1011 | The translation in case when allocatable hard register set of a | |
1012 | given class is subset of allocatable hard register set of a class | |
1013 | in CLASSES is pretty simple. We use smallest classes from CLASSES | |
1014 | containing a given class. If allocatable hard register set of a | |
1015 | given class is not a subset of any corresponding set of a class | |
1016 | from CLASSES, we use the cheapest (with load/store point of view) | |
1017 | class from CLASSES whose set intersects with given class set */ | |
058e97ec | 1018 | static void |
1756cb66 VM |
1019 | setup_class_translate_array (enum reg_class *class_translate, |
1020 | int classes_num, enum reg_class *classes) | |
058e97ec | 1021 | { |
32e8bb8e | 1022 | int cl, mode; |
1756cb66 | 1023 | enum reg_class aclass, best_class, *cl_ptr; |
058e97ec VM |
1024 | int i, cost, min_cost, best_cost; |
1025 | ||
1026 | for (cl = 0; cl < N_REG_CLASSES; cl++) | |
1756cb66 | 1027 | class_translate[cl] = NO_REGS; |
b8698a0f | 1028 | |
1756cb66 | 1029 | for (i = 0; i < classes_num; i++) |
058e97ec | 1030 | { |
1756cb66 VM |
1031 | aclass = classes[i]; |
1032 | for (cl_ptr = &alloc_reg_class_subclasses[aclass][0]; | |
1033 | (cl = *cl_ptr) != LIM_REG_CLASSES; | |
1034 | cl_ptr++) | |
1035 | if (class_translate[cl] == NO_REGS) | |
1036 | class_translate[cl] = aclass; | |
1037 | class_translate[aclass] = aclass; | |
058e97ec | 1038 | } |
1756cb66 VM |
1039 | /* For classes which are not fully covered by one of given classes |
1040 | (in other words covered by more one given class), use the | |
1041 | cheapest class. */ | |
058e97ec VM |
1042 | for (cl = 0; cl < N_REG_CLASSES; cl++) |
1043 | { | |
1756cb66 | 1044 | if (cl == NO_REGS || class_translate[cl] != NO_REGS) |
058e97ec VM |
1045 | continue; |
1046 | best_class = NO_REGS; | |
1047 | best_cost = INT_MAX; | |
1756cb66 | 1048 | for (i = 0; i < classes_num; i++) |
058e97ec | 1049 | { |
1756cb66 | 1050 | aclass = classes[i]; |
058e97ec | 1051 | COPY_HARD_REG_SET (temp_hard_regset, |
1756cb66 | 1052 | reg_class_contents[aclass]); |
058e97ec VM |
1053 | AND_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); |
1054 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
4f341ea0 | 1055 | if (! hard_reg_set_empty_p (temp_hard_regset)) |
058e97ec VM |
1056 | { |
1057 | min_cost = INT_MAX; | |
1058 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
1059 | { | |
1060 | cost = (ira_memory_move_cost[mode][cl][0] | |
1061 | + ira_memory_move_cost[mode][cl][1]); | |
1062 | if (min_cost > cost) | |
1063 | min_cost = cost; | |
1064 | } | |
1065 | if (best_class == NO_REGS || best_cost > min_cost) | |
1066 | { | |
1756cb66 | 1067 | best_class = aclass; |
058e97ec VM |
1068 | best_cost = min_cost; |
1069 | } | |
1070 | } | |
1071 | } | |
1756cb66 | 1072 | class_translate[cl] = best_class; |
058e97ec VM |
1073 | } |
1074 | } | |
058e97ec | 1075 | |
1756cb66 VM |
1076 | /* Set up array IRA_ALLOCNO_CLASS_TRANSLATE and |
1077 | IRA_PRESSURE_CLASS_TRANSLATE. */ | |
1078 | static void | |
1079 | setup_class_translate (void) | |
1080 | { | |
1081 | setup_class_translate_array (ira_allocno_class_translate, | |
1082 | ira_allocno_classes_num, ira_allocno_classes); | |
1083 | setup_class_translate_array (ira_pressure_class_translate, | |
1084 | ira_pressure_classes_num, ira_pressure_classes); | |
1085 | } | |
1086 | ||
1087 | /* Order numbers of allocno classes in original target allocno class | |
1088 | array, -1 for non-allocno classes. */ | |
1089 | static int allocno_class_order[N_REG_CLASSES]; | |
db1a8d98 VM |
1090 | |
1091 | /* The function used to sort the important classes. */ | |
1092 | static int | |
1093 | comp_reg_classes_func (const void *v1p, const void *v2p) | |
1094 | { | |
1095 | enum reg_class cl1 = *(const enum reg_class *) v1p; | |
1096 | enum reg_class cl2 = *(const enum reg_class *) v2p; | |
1756cb66 | 1097 | enum reg_class tcl1, tcl2; |
db1a8d98 VM |
1098 | int diff; |
1099 | ||
1756cb66 VM |
1100 | tcl1 = ira_allocno_class_translate[cl1]; |
1101 | tcl2 = ira_allocno_class_translate[cl2]; | |
1102 | if (tcl1 != NO_REGS && tcl2 != NO_REGS | |
1103 | && (diff = allocno_class_order[tcl1] - allocno_class_order[tcl2]) != 0) | |
db1a8d98 VM |
1104 | return diff; |
1105 | return (int) cl1 - (int) cl2; | |
1106 | } | |
1107 | ||
1756cb66 VM |
1108 | /* For correct work of function setup_reg_class_relation we need to |
1109 | reorder important classes according to the order of their allocno | |
1110 | classes. It places important classes containing the same | |
1111 | allocatable hard register set adjacent to each other and allocno | |
1112 | class with the allocatable hard register set right after the other | |
1113 | important classes with the same set. | |
1114 | ||
1115 | In example from comments of function | |
1116 | setup_allocno_and_important_classes, it places LEGACY_REGS and | |
1117 | GENERAL_REGS close to each other and GENERAL_REGS is after | |
1118 | LEGACY_REGS. */ | |
db1a8d98 VM |
1119 | static void |
1120 | reorder_important_classes (void) | |
1121 | { | |
1122 | int i; | |
1123 | ||
1124 | for (i = 0; i < N_REG_CLASSES; i++) | |
1756cb66 VM |
1125 | allocno_class_order[i] = -1; |
1126 | for (i = 0; i < ira_allocno_classes_num; i++) | |
1127 | allocno_class_order[ira_allocno_classes[i]] = i; | |
db1a8d98 VM |
1128 | qsort (ira_important_classes, ira_important_classes_num, |
1129 | sizeof (enum reg_class), comp_reg_classes_func); | |
1756cb66 VM |
1130 | for (i = 0; i < ira_important_classes_num; i++) |
1131 | ira_important_class_nums[ira_important_classes[i]] = i; | |
db1a8d98 VM |
1132 | } |
1133 | ||
1756cb66 VM |
1134 | /* Set up IRA_REG_CLASS_SUBUNION, IRA_REG_CLASS_SUPERUNION, |
1135 | IRA_REG_CLASS_SUPER_CLASSES, IRA_REG_CLASSES_INTERSECT, and | |
1136 | IRA_REG_CLASSES_INTERSECT_P. For the meaning of the relations, | |
1137 | please see corresponding comments in ira-int.h. */ | |
058e97ec | 1138 | static void |
7db7ed3c | 1139 | setup_reg_class_relations (void) |
058e97ec VM |
1140 | { |
1141 | int i, cl1, cl2, cl3; | |
1142 | HARD_REG_SET intersection_set, union_set, temp_set2; | |
7db7ed3c | 1143 | bool important_class_p[N_REG_CLASSES]; |
058e97ec | 1144 | |
7db7ed3c VM |
1145 | memset (important_class_p, 0, sizeof (important_class_p)); |
1146 | for (i = 0; i < ira_important_classes_num; i++) | |
1147 | important_class_p[ira_important_classes[i]] = true; | |
058e97ec VM |
1148 | for (cl1 = 0; cl1 < N_REG_CLASSES; cl1++) |
1149 | { | |
7db7ed3c | 1150 | ira_reg_class_super_classes[cl1][0] = LIM_REG_CLASSES; |
058e97ec VM |
1151 | for (cl2 = 0; cl2 < N_REG_CLASSES; cl2++) |
1152 | { | |
7db7ed3c | 1153 | ira_reg_classes_intersect_p[cl1][cl2] = false; |
058e97ec VM |
1154 | ira_reg_class_intersect[cl1][cl2] = NO_REGS; |
1155 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl1]); | |
1156 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
1157 | COPY_HARD_REG_SET (temp_set2, reg_class_contents[cl2]); | |
1158 | AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs); | |
4f341ea0 RS |
1159 | if (hard_reg_set_empty_p (temp_hard_regset) |
1160 | && hard_reg_set_empty_p (temp_set2)) | |
058e97ec | 1161 | { |
1756cb66 VM |
1162 | /* The both classes have no allocatable hard registers |
1163 | -- take all class hard registers into account and use | |
1164 | reg_class_subunion and reg_class_superunion. */ | |
058e97ec VM |
1165 | for (i = 0;; i++) |
1166 | { | |
1167 | cl3 = reg_class_subclasses[cl1][i]; | |
1168 | if (cl3 == LIM_REG_CLASSES) | |
1169 | break; | |
1170 | if (reg_class_subset_p (ira_reg_class_intersect[cl1][cl2], | |
bbbbb16a ILT |
1171 | (enum reg_class) cl3)) |
1172 | ira_reg_class_intersect[cl1][cl2] = (enum reg_class) cl3; | |
058e97ec | 1173 | } |
1756cb66 VM |
1174 | ira_reg_class_subunion[cl1][cl2] = reg_class_subunion[cl1][cl2]; |
1175 | ira_reg_class_superunion[cl1][cl2] = reg_class_superunion[cl1][cl2]; | |
058e97ec VM |
1176 | continue; |
1177 | } | |
7db7ed3c VM |
1178 | ira_reg_classes_intersect_p[cl1][cl2] |
1179 | = hard_reg_set_intersect_p (temp_hard_regset, temp_set2); | |
1180 | if (important_class_p[cl1] && important_class_p[cl2] | |
1181 | && hard_reg_set_subset_p (temp_hard_regset, temp_set2)) | |
1182 | { | |
1756cb66 VM |
1183 | /* CL1 and CL2 are important classes and CL1 allocatable |
1184 | hard register set is inside of CL2 allocatable hard | |
1185 | registers -- make CL1 a superset of CL2. */ | |
7db7ed3c VM |
1186 | enum reg_class *p; |
1187 | ||
1188 | p = &ira_reg_class_super_classes[cl1][0]; | |
1189 | while (*p != LIM_REG_CLASSES) | |
1190 | p++; | |
1191 | *p++ = (enum reg_class) cl2; | |
1192 | *p = LIM_REG_CLASSES; | |
1193 | } | |
1756cb66 VM |
1194 | ira_reg_class_subunion[cl1][cl2] = NO_REGS; |
1195 | ira_reg_class_superunion[cl1][cl2] = NO_REGS; | |
058e97ec VM |
1196 | COPY_HARD_REG_SET (intersection_set, reg_class_contents[cl1]); |
1197 | AND_HARD_REG_SET (intersection_set, reg_class_contents[cl2]); | |
1198 | AND_COMPL_HARD_REG_SET (intersection_set, no_unit_alloc_regs); | |
1199 | COPY_HARD_REG_SET (union_set, reg_class_contents[cl1]); | |
1200 | IOR_HARD_REG_SET (union_set, reg_class_contents[cl2]); | |
1201 | AND_COMPL_HARD_REG_SET (union_set, no_unit_alloc_regs); | |
1202 | for (i = 0; i < ira_important_classes_num; i++) | |
1203 | { | |
1204 | cl3 = ira_important_classes[i]; | |
1205 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl3]); | |
1206 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
1207 | if (hard_reg_set_subset_p (temp_hard_regset, intersection_set)) | |
1208 | { | |
1756cb66 VM |
1209 | /* CL3 allocatable hard register set is inside of |
1210 | intersection of allocatable hard register sets | |
1211 | of CL1 and CL2. */ | |
058e97ec VM |
1212 | COPY_HARD_REG_SET |
1213 | (temp_set2, | |
1214 | reg_class_contents[(int) | |
1215 | ira_reg_class_intersect[cl1][cl2]]); | |
1216 | AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs); | |
1217 | if (! hard_reg_set_subset_p (temp_hard_regset, temp_set2) | |
1756cb66 VM |
1218 | /* If the allocatable hard register sets are the |
1219 | same, prefer GENERAL_REGS or the smallest | |
1220 | class for debugging purposes. */ | |
058e97ec | 1221 | || (hard_reg_set_equal_p (temp_hard_regset, temp_set2) |
1756cb66 VM |
1222 | && (cl3 == GENERAL_REGS |
1223 | || (ira_reg_class_intersect[cl1][cl2] != GENERAL_REGS | |
1224 | && hard_reg_set_subset_p | |
1225 | (reg_class_contents[cl3], | |
1226 | reg_class_contents | |
1227 | [(int) ira_reg_class_intersect[cl1][cl2]]))))) | |
058e97ec VM |
1228 | ira_reg_class_intersect[cl1][cl2] = (enum reg_class) cl3; |
1229 | } | |
1230 | if (hard_reg_set_subset_p (temp_hard_regset, union_set)) | |
1231 | { | |
1756cb66 VM |
1232 | /* CL3 allocatbale hard register set is inside of |
1233 | union of allocatable hard register sets of CL1 | |
1234 | and CL2. */ | |
058e97ec VM |
1235 | COPY_HARD_REG_SET |
1236 | (temp_set2, | |
1756cb66 | 1237 | reg_class_contents[(int) ira_reg_class_subunion[cl1][cl2]]); |
058e97ec | 1238 | AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs); |
1756cb66 | 1239 | if (ira_reg_class_subunion[cl1][cl2] == NO_REGS |
058e97ec | 1240 | || (hard_reg_set_subset_p (temp_set2, temp_hard_regset) |
1756cb66 VM |
1241 | |
1242 | && (! hard_reg_set_equal_p (temp_set2, | |
1243 | temp_hard_regset) | |
1244 | || cl3 == GENERAL_REGS | |
1245 | /* If the allocatable hard register sets are the | |
1246 | same, prefer GENERAL_REGS or the smallest | |
1247 | class for debugging purposes. */ | |
1248 | || (ira_reg_class_subunion[cl1][cl2] != GENERAL_REGS | |
1249 | && hard_reg_set_subset_p | |
1250 | (reg_class_contents[cl3], | |
1251 | reg_class_contents | |
1252 | [(int) ira_reg_class_subunion[cl1][cl2]]))))) | |
1253 | ira_reg_class_subunion[cl1][cl2] = (enum reg_class) cl3; | |
1254 | } | |
1255 | if (hard_reg_set_subset_p (union_set, temp_hard_regset)) | |
1256 | { | |
1257 | /* CL3 allocatable hard register set contains union | |
1258 | of allocatable hard register sets of CL1 and | |
1259 | CL2. */ | |
1260 | COPY_HARD_REG_SET | |
1261 | (temp_set2, | |
1262 | reg_class_contents[(int) ira_reg_class_superunion[cl1][cl2]]); | |
1263 | AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs); | |
1264 | if (ira_reg_class_superunion[cl1][cl2] == NO_REGS | |
1265 | || (hard_reg_set_subset_p (temp_hard_regset, temp_set2) | |
b8698a0f | 1266 | |
058e97ec VM |
1267 | && (! hard_reg_set_equal_p (temp_set2, |
1268 | temp_hard_regset) | |
1756cb66 VM |
1269 | || cl3 == GENERAL_REGS |
1270 | /* If the allocatable hard register sets are the | |
1271 | same, prefer GENERAL_REGS or the smallest | |
1272 | class for debugging purposes. */ | |
1273 | || (ira_reg_class_superunion[cl1][cl2] != GENERAL_REGS | |
1274 | && hard_reg_set_subset_p | |
1275 | (reg_class_contents[cl3], | |
1276 | reg_class_contents | |
1277 | [(int) ira_reg_class_superunion[cl1][cl2]]))))) | |
1278 | ira_reg_class_superunion[cl1][cl2] = (enum reg_class) cl3; | |
058e97ec VM |
1279 | } |
1280 | } | |
1281 | } | |
1282 | } | |
1283 | } | |
1284 | ||
1756cb66 VM |
1285 | /* Output all possible allocno classes and the translation map into |
1286 | file F. */ | |
058e97ec | 1287 | static void |
1756cb66 VM |
1288 | print_classes (FILE *f, bool pressure_p) |
1289 | { | |
1290 | int classes_num = (pressure_p | |
1291 | ? ira_pressure_classes_num : ira_allocno_classes_num); | |
1292 | enum reg_class *classes = (pressure_p | |
1293 | ? ira_pressure_classes : ira_allocno_classes); | |
1294 | enum reg_class *class_translate = (pressure_p | |
1295 | ? ira_pressure_class_translate | |
1296 | : ira_allocno_class_translate); | |
058e97ec VM |
1297 | static const char *const reg_class_names[] = REG_CLASS_NAMES; |
1298 | int i; | |
1299 | ||
1756cb66 VM |
1300 | fprintf (f, "%s classes:\n", pressure_p ? "Pressure" : "Allocno"); |
1301 | for (i = 0; i < classes_num; i++) | |
1302 | fprintf (f, " %s", reg_class_names[classes[i]]); | |
058e97ec VM |
1303 | fprintf (f, "\nClass translation:\n"); |
1304 | for (i = 0; i < N_REG_CLASSES; i++) | |
1305 | fprintf (f, " %s -> %s\n", reg_class_names[i], | |
1756cb66 | 1306 | reg_class_names[class_translate[i]]); |
058e97ec VM |
1307 | } |
1308 | ||
1756cb66 VM |
1309 | /* Output all possible allocno and translation classes and the |
1310 | translation maps into stderr. */ | |
058e97ec | 1311 | void |
1756cb66 | 1312 | ira_debug_allocno_classes (void) |
058e97ec | 1313 | { |
1756cb66 VM |
1314 | print_classes (stderr, false); |
1315 | print_classes (stderr, true); | |
058e97ec VM |
1316 | } |
1317 | ||
1756cb66 | 1318 | /* Set up different arrays concerning class subsets, allocno and |
058e97ec VM |
1319 | important classes. */ |
1320 | static void | |
1756cb66 | 1321 | find_reg_classes (void) |
058e97ec | 1322 | { |
1756cb66 | 1323 | setup_allocno_and_important_classes (); |
7db7ed3c | 1324 | setup_class_translate (); |
db1a8d98 | 1325 | reorder_important_classes (); |
7db7ed3c | 1326 | setup_reg_class_relations (); |
058e97ec VM |
1327 | } |
1328 | ||
1329 | \f | |
1330 | ||
c0683a82 VM |
1331 | /* Set up the array above. */ |
1332 | static void | |
1756cb66 | 1333 | setup_hard_regno_aclass (void) |
c0683a82 | 1334 | { |
7efcf910 | 1335 | int i; |
c0683a82 VM |
1336 | |
1337 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1338 | { | |
1756cb66 VM |
1339 | #if 1 |
1340 | ira_hard_regno_allocno_class[i] | |
7efcf910 CLT |
1341 | = (TEST_HARD_REG_BIT (no_unit_alloc_regs, i) |
1342 | ? NO_REGS | |
1756cb66 VM |
1343 | : ira_allocno_class_translate[REGNO_REG_CLASS (i)]); |
1344 | #else | |
1345 | int j; | |
1346 | enum reg_class cl; | |
1347 | ira_hard_regno_allocno_class[i] = NO_REGS; | |
1348 | for (j = 0; j < ira_allocno_classes_num; j++) | |
1349 | { | |
1350 | cl = ira_allocno_classes[j]; | |
1351 | if (ira_class_hard_reg_index[cl][i] >= 0) | |
1352 | { | |
1353 | ira_hard_regno_allocno_class[i] = cl; | |
1354 | break; | |
1355 | } | |
1356 | } | |
1357 | #endif | |
c0683a82 VM |
1358 | } |
1359 | } | |
1360 | ||
1361 | \f | |
1362 | ||
1756cb66 | 1363 | /* Form IRA_REG_CLASS_MAX_NREGS and IRA_REG_CLASS_MIN_NREGS maps. */ |
058e97ec VM |
1364 | static void |
1365 | setup_reg_class_nregs (void) | |
1366 | { | |
1756cb66 | 1367 | int i, cl, cl2, m; |
058e97ec | 1368 | |
1756cb66 VM |
1369 | for (m = 0; m < MAX_MACHINE_MODE; m++) |
1370 | { | |
1371 | for (cl = 0; cl < N_REG_CLASSES; cl++) | |
1372 | ira_reg_class_max_nregs[cl][m] | |
1373 | = ira_reg_class_min_nregs[cl][m] | |
1374 | = CLASS_MAX_NREGS ((enum reg_class) cl, (enum machine_mode) m); | |
1375 | for (cl = 0; cl < N_REG_CLASSES; cl++) | |
1376 | for (i = 0; | |
1377 | (cl2 = alloc_reg_class_subclasses[cl][i]) != LIM_REG_CLASSES; | |
1378 | i++) | |
1379 | if (ira_reg_class_min_nregs[cl2][m] | |
1380 | < ira_reg_class_min_nregs[cl][m]) | |
1381 | ira_reg_class_min_nregs[cl][m] = ira_reg_class_min_nregs[cl2][m]; | |
1382 | } | |
058e97ec VM |
1383 | } |
1384 | ||
1385 | \f | |
1386 | ||
1756cb66 | 1387 | /* Set up IRA_PROHIBITED_CLASS_MODE_REGS. */ |
058e97ec VM |
1388 | static void |
1389 | setup_prohibited_class_mode_regs (void) | |
1390 | { | |
1756cb66 | 1391 | int j, k, hard_regno, cl; |
058e97ec | 1392 | |
1756cb66 | 1393 | for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) |
058e97ec | 1394 | { |
058e97ec VM |
1395 | for (j = 0; j < NUM_MACHINE_MODES; j++) |
1396 | { | |
1756cb66 | 1397 | CLEAR_HARD_REG_SET (ira_prohibited_class_mode_regs[cl][j]); |
058e97ec VM |
1398 | for (k = ira_class_hard_regs_num[cl] - 1; k >= 0; k--) |
1399 | { | |
1400 | hard_regno = ira_class_hard_regs[cl][k]; | |
bbbbb16a | 1401 | if (! HARD_REGNO_MODE_OK (hard_regno, (enum machine_mode) j)) |
1756cb66 | 1402 | SET_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j], |
058e97ec VM |
1403 | hard_regno); |
1404 | } | |
1405 | } | |
1406 | } | |
1407 | } | |
1408 | ||
1756cb66 VM |
1409 | /* Clarify IRA_PROHIBITED_CLASS_MODE_REGS by excluding hard registers |
1410 | spanning from one register pressure class to another one. It is | |
1411 | called after defining the pressure classes. */ | |
1412 | static void | |
1413 | clarify_prohibited_class_mode_regs (void) | |
1414 | { | |
1415 | int j, k, hard_regno, cl, pclass, nregs; | |
1416 | ||
1417 | for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) | |
1418 | for (j = 0; j < NUM_MACHINE_MODES; j++) | |
1419 | for (k = ira_class_hard_regs_num[cl] - 1; k >= 0; k--) | |
1420 | { | |
1421 | hard_regno = ira_class_hard_regs[cl][k]; | |
1422 | if (TEST_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j], hard_regno)) | |
1423 | continue; | |
1424 | nregs = hard_regno_nregs[hard_regno][j]; | |
1425 | pclass = ira_pressure_class_translate[REGNO_REG_CLASS (hard_regno)]; | |
1426 | for (nregs-- ;nregs >= 0; nregs--) | |
1427 | if (((enum reg_class) pclass | |
1428 | != ira_pressure_class_translate[REGNO_REG_CLASS | |
1429 | (hard_regno + nregs)])) | |
1430 | { | |
1431 | SET_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j], | |
1432 | hard_regno); | |
1433 | break; | |
1434 | } | |
1435 | } | |
1436 | } | |
1437 | ||
058e97ec VM |
1438 | \f |
1439 | ||
1440 | /* Allocate and initialize IRA_REGISTER_MOVE_COST, | |
1756cb66 VM |
1441 | IRA_MAX_REGISTER_MOVE_COST, IRA_MAY_MOVE_IN_COST, |
1442 | IRA_MAY_MOVE_OUT_COST, IRA_MAX_MAY_MOVE_IN_COST, and | |
1443 | IRA_MAX_MAY_MOVE_OUT_COST for MODE if it is not done yet. */ | |
058e97ec VM |
1444 | void |
1445 | ira_init_register_move_cost (enum machine_mode mode) | |
1446 | { | |
1756cb66 | 1447 | int cl1, cl2, cl3; |
058e97ec VM |
1448 | |
1449 | ira_assert (ira_register_move_cost[mode] == NULL | |
1756cb66 | 1450 | && ira_max_register_move_cost[mode] == NULL |
058e97ec | 1451 | && ira_may_move_in_cost[mode] == NULL |
1756cb66 VM |
1452 | && ira_may_move_out_cost[mode] == NULL |
1453 | && ira_max_may_move_in_cost[mode] == NULL | |
1454 | && ira_max_may_move_out_cost[mode] == NULL); | |
058e97ec VM |
1455 | if (move_cost[mode] == NULL) |
1456 | init_move_cost (mode); | |
1457 | ira_register_move_cost[mode] = move_cost[mode]; | |
1458 | /* Don't use ira_allocate because the tables exist out of scope of a | |
1459 | IRA call. */ | |
1756cb66 VM |
1460 | ira_max_register_move_cost[mode] |
1461 | = (move_table *) xmalloc (sizeof (move_table) * N_REG_CLASSES); | |
1462 | memcpy (ira_max_register_move_cost[mode], ira_register_move_cost[mode], | |
1463 | sizeof (move_table) * N_REG_CLASSES); | |
1464 | for (cl1 = 0; cl1 < N_REG_CLASSES; cl1++) | |
1465 | { | |
1466 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl1]); | |
1467 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
1468 | if (hard_reg_set_empty_p (temp_hard_regset)) | |
1469 | continue; | |
1470 | for (cl2 = 0; cl2 < N_REG_CLASSES; cl2++) | |
1471 | if (hard_reg_set_subset_p (reg_class_contents[cl1], | |
1472 | reg_class_contents[cl2])) | |
1473 | for (cl3 = 0; cl3 < N_REG_CLASSES; cl3++) | |
1474 | { | |
1475 | if (ira_max_register_move_cost[mode][cl2][cl3] | |
1476 | < ira_register_move_cost[mode][cl1][cl3]) | |
1477 | ira_max_register_move_cost[mode][cl2][cl3] | |
1478 | = ira_register_move_cost[mode][cl1][cl3]; | |
1479 | if (ira_max_register_move_cost[mode][cl3][cl2] | |
1480 | < ira_register_move_cost[mode][cl3][cl1]) | |
1481 | ira_max_register_move_cost[mode][cl3][cl2] | |
1482 | = ira_register_move_cost[mode][cl3][cl1]; | |
1483 | } | |
1484 | } | |
058e97ec VM |
1485 | ira_may_move_in_cost[mode] |
1486 | = (move_table *) xmalloc (sizeof (move_table) * N_REG_CLASSES); | |
1487 | memcpy (ira_may_move_in_cost[mode], may_move_in_cost[mode], | |
1488 | sizeof (move_table) * N_REG_CLASSES); | |
1489 | ira_may_move_out_cost[mode] | |
1490 | = (move_table *) xmalloc (sizeof (move_table) * N_REG_CLASSES); | |
1491 | memcpy (ira_may_move_out_cost[mode], may_move_out_cost[mode], | |
1492 | sizeof (move_table) * N_REG_CLASSES); | |
1756cb66 VM |
1493 | ira_max_may_move_in_cost[mode] |
1494 | = (move_table *) xmalloc (sizeof (move_table) * N_REG_CLASSES); | |
1495 | memcpy (ira_max_may_move_in_cost[mode], ira_max_register_move_cost[mode], | |
1496 | sizeof (move_table) * N_REG_CLASSES); | |
1497 | ira_max_may_move_out_cost[mode] | |
1498 | = (move_table *) xmalloc (sizeof (move_table) * N_REG_CLASSES); | |
1499 | memcpy (ira_max_may_move_out_cost[mode], ira_max_register_move_cost[mode], | |
1500 | sizeof (move_table) * N_REG_CLASSES); | |
058e97ec VM |
1501 | for (cl1 = 0; cl1 < N_REG_CLASSES; cl1++) |
1502 | { | |
1503 | for (cl2 = 0; cl2 < N_REG_CLASSES; cl2++) | |
1504 | { | |
1756cb66 VM |
1505 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl2]); |
1506 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
1507 | if (hard_reg_set_empty_p (temp_hard_regset)) | |
1508 | continue; | |
058e97ec VM |
1509 | if (ira_class_subset_p[cl1][cl2]) |
1510 | ira_may_move_in_cost[mode][cl1][cl2] = 0; | |
1511 | if (ira_class_subset_p[cl2][cl1]) | |
1512 | ira_may_move_out_cost[mode][cl1][cl2] = 0; | |
1756cb66 VM |
1513 | if (ira_class_subset_p[cl1][cl2]) |
1514 | ira_max_may_move_in_cost[mode][cl1][cl2] = 0; | |
1515 | if (ira_class_subset_p[cl2][cl1]) | |
1516 | ira_max_may_move_out_cost[mode][cl1][cl2] = 0; | |
1517 | ira_register_move_cost[mode][cl1][cl2] | |
1518 | = ira_max_register_move_cost[mode][cl1][cl2]; | |
1519 | ira_may_move_in_cost[mode][cl1][cl2] | |
1520 | = ira_max_may_move_in_cost[mode][cl1][cl2]; | |
1521 | ira_may_move_out_cost[mode][cl1][cl2] | |
1522 | = ira_max_may_move_out_cost[mode][cl1][cl2]; | |
058e97ec VM |
1523 | } |
1524 | } | |
1525 | } | |
1526 | ||
1527 | \f | |
1528 | ||
058e97ec VM |
1529 | /* This is called once during compiler work. It sets up |
1530 | different arrays whose values don't depend on the compiled | |
1531 | function. */ | |
1532 | void | |
1533 | ira_init_once (void) | |
1534 | { | |
32e8bb8e | 1535 | int mode; |
058e97ec | 1536 | |
058e97ec VM |
1537 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) |
1538 | { | |
1539 | ira_register_move_cost[mode] = NULL; | |
1756cb66 | 1540 | ira_max_register_move_cost[mode] = NULL; |
058e97ec VM |
1541 | ira_may_move_in_cost[mode] = NULL; |
1542 | ira_may_move_out_cost[mode] = NULL; | |
1756cb66 VM |
1543 | ira_max_may_move_in_cost[mode] = NULL; |
1544 | ira_max_may_move_out_cost[mode] = NULL; | |
058e97ec VM |
1545 | } |
1546 | ira_init_costs_once (); | |
1547 | } | |
1548 | ||
1756cb66 VM |
1549 | /* Free ira_max_register_move_cost, ira_may_move_in_cost, |
1550 | ira_may_move_out_cost, ira_max_may_move_in_cost, and | |
1551 | ira_max_may_move_out_cost for each mode. */ | |
058e97ec VM |
1552 | static void |
1553 | free_register_move_costs (void) | |
1554 | { | |
32e8bb8e | 1555 | int mode; |
058e97ec VM |
1556 | |
1557 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
1558 | { | |
1756cb66 VM |
1559 | if (ira_max_register_move_cost[mode] != NULL) |
1560 | free (ira_max_register_move_cost[mode]); | |
058e97ec VM |
1561 | if (ira_may_move_in_cost[mode] != NULL) |
1562 | free (ira_may_move_in_cost[mode]); | |
1563 | if (ira_may_move_out_cost[mode] != NULL) | |
1564 | free (ira_may_move_out_cost[mode]); | |
1756cb66 VM |
1565 | if (ira_max_may_move_in_cost[mode] != NULL) |
1566 | free (ira_max_may_move_in_cost[mode]); | |
1567 | if (ira_max_may_move_out_cost[mode] != NULL) | |
1568 | free (ira_max_may_move_out_cost[mode]); | |
058e97ec | 1569 | ira_register_move_cost[mode] = NULL; |
1756cb66 | 1570 | ira_max_register_move_cost[mode] = NULL; |
058e97ec VM |
1571 | ira_may_move_in_cost[mode] = NULL; |
1572 | ira_may_move_out_cost[mode] = NULL; | |
1756cb66 VM |
1573 | ira_max_may_move_in_cost[mode] = NULL; |
1574 | ira_max_may_move_out_cost[mode] = NULL; | |
058e97ec VM |
1575 | } |
1576 | } | |
1577 | ||
1578 | /* This is called every time when register related information is | |
1579 | changed. */ | |
1580 | void | |
1581 | ira_init (void) | |
1582 | { | |
1583 | free_register_move_costs (); | |
1584 | setup_reg_mode_hard_regset (); | |
1585 | setup_alloc_regs (flag_omit_frame_pointer != 0); | |
1586 | setup_class_subset_and_memory_move_costs (); | |
058e97ec VM |
1587 | setup_reg_class_nregs (); |
1588 | setup_prohibited_class_mode_regs (); | |
1756cb66 VM |
1589 | find_reg_classes (); |
1590 | clarify_prohibited_class_mode_regs (); | |
1591 | setup_hard_regno_aclass (); | |
058e97ec VM |
1592 | ira_init_costs (); |
1593 | } | |
1594 | ||
1595 | /* Function called once at the end of compiler work. */ | |
1596 | void | |
1597 | ira_finish_once (void) | |
1598 | { | |
1599 | ira_finish_costs_once (); | |
1600 | free_register_move_costs (); | |
1601 | } | |
1602 | ||
1603 | \f | |
15e7b94f RS |
1604 | #define ira_prohibited_mode_move_regs_initialized_p \ |
1605 | (this_target_ira_int->x_ira_prohibited_mode_move_regs_initialized_p) | |
058e97ec VM |
1606 | |
1607 | /* Set up IRA_PROHIBITED_MODE_MOVE_REGS. */ | |
1608 | static void | |
1609 | setup_prohibited_mode_move_regs (void) | |
1610 | { | |
1611 | int i, j; | |
1612 | rtx test_reg1, test_reg2, move_pat, move_insn; | |
1613 | ||
1614 | if (ira_prohibited_mode_move_regs_initialized_p) | |
1615 | return; | |
1616 | ira_prohibited_mode_move_regs_initialized_p = true; | |
1617 | test_reg1 = gen_rtx_REG (VOIDmode, 0); | |
1618 | test_reg2 = gen_rtx_REG (VOIDmode, 0); | |
1619 | move_pat = gen_rtx_SET (VOIDmode, test_reg1, test_reg2); | |
418e920f | 1620 | move_insn = gen_rtx_INSN (VOIDmode, 0, 0, 0, 0, move_pat, 0, -1, 0); |
058e97ec VM |
1621 | for (i = 0; i < NUM_MACHINE_MODES; i++) |
1622 | { | |
1623 | SET_HARD_REG_SET (ira_prohibited_mode_move_regs[i]); | |
1624 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
1625 | { | |
bbbbb16a | 1626 | if (! HARD_REGNO_MODE_OK (j, (enum machine_mode) i)) |
058e97ec | 1627 | continue; |
5444da31 | 1628 | SET_REGNO_RAW (test_reg1, j); |
32e8bb8e | 1629 | PUT_MODE (test_reg1, (enum machine_mode) i); |
5444da31 | 1630 | SET_REGNO_RAW (test_reg2, j); |
32e8bb8e | 1631 | PUT_MODE (test_reg2, (enum machine_mode) i); |
058e97ec VM |
1632 | INSN_CODE (move_insn) = -1; |
1633 | recog_memoized (move_insn); | |
1634 | if (INSN_CODE (move_insn) < 0) | |
1635 | continue; | |
1636 | extract_insn (move_insn); | |
1637 | if (! constrain_operands (1)) | |
1638 | continue; | |
1639 | CLEAR_HARD_REG_BIT (ira_prohibited_mode_move_regs[i], j); | |
1640 | } | |
1641 | } | |
1642 | } | |
1643 | ||
1644 | \f | |
1645 | ||
0896cc66 JL |
1646 | /* Return nonzero if REGNO is a particularly bad choice for reloading X. */ |
1647 | static bool | |
1648 | ira_bad_reload_regno_1 (int regno, rtx x) | |
1649 | { | |
ac0ab4f7 | 1650 | int x_regno, n, i; |
0896cc66 JL |
1651 | ira_allocno_t a; |
1652 | enum reg_class pref; | |
1653 | ||
1654 | /* We only deal with pseudo regs. */ | |
1655 | if (! x || GET_CODE (x) != REG) | |
1656 | return false; | |
1657 | ||
1658 | x_regno = REGNO (x); | |
1659 | if (x_regno < FIRST_PSEUDO_REGISTER) | |
1660 | return false; | |
1661 | ||
1662 | /* If the pseudo prefers REGNO explicitly, then do not consider | |
1663 | REGNO a bad spill choice. */ | |
1664 | pref = reg_preferred_class (x_regno); | |
1665 | if (reg_class_size[pref] == 1) | |
1666 | return !TEST_HARD_REG_BIT (reg_class_contents[pref], regno); | |
1667 | ||
1668 | /* If the pseudo conflicts with REGNO, then we consider REGNO a | |
1669 | poor choice for a reload regno. */ | |
1670 | a = ira_regno_allocno_map[x_regno]; | |
ac0ab4f7 BS |
1671 | n = ALLOCNO_NUM_OBJECTS (a); |
1672 | for (i = 0; i < n; i++) | |
1673 | { | |
1674 | ira_object_t obj = ALLOCNO_OBJECT (a, i); | |
1675 | if (TEST_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), regno)) | |
1676 | return true; | |
1677 | } | |
0896cc66 JL |
1678 | return false; |
1679 | } | |
1680 | ||
1681 | /* Return nonzero if REGNO is a particularly bad choice for reloading | |
1682 | IN or OUT. */ | |
1683 | bool | |
1684 | ira_bad_reload_regno (int regno, rtx in, rtx out) | |
1685 | { | |
1686 | return (ira_bad_reload_regno_1 (regno, in) | |
1687 | || ira_bad_reload_regno_1 (regno, out)); | |
1688 | } | |
1689 | ||
058e97ec VM |
1690 | /* Return TRUE if *LOC contains an asm. */ |
1691 | static int | |
1692 | insn_contains_asm_1 (rtx *loc, void *data ATTRIBUTE_UNUSED) | |
1693 | { | |
1694 | if ( !*loc) | |
1695 | return FALSE; | |
1696 | if (GET_CODE (*loc) == ASM_OPERANDS) | |
1697 | return TRUE; | |
1698 | return FALSE; | |
1699 | } | |
1700 | ||
1701 | ||
1702 | /* Return TRUE if INSN contains an ASM. */ | |
1703 | static bool | |
1704 | insn_contains_asm (rtx insn) | |
1705 | { | |
1706 | return for_each_rtx (&insn, insn_contains_asm_1, NULL); | |
1707 | } | |
1708 | ||
b748fbd6 | 1709 | /* Add register clobbers from asm statements. */ |
058e97ec | 1710 | static void |
b748fbd6 | 1711 | compute_regs_asm_clobbered (void) |
058e97ec VM |
1712 | { |
1713 | basic_block bb; | |
1714 | ||
058e97ec VM |
1715 | FOR_EACH_BB (bb) |
1716 | { | |
1717 | rtx insn; | |
1718 | FOR_BB_INSNS_REVERSE (bb, insn) | |
1719 | { | |
57512f53 | 1720 | df_ref *def_rec; |
058e97ec VM |
1721 | |
1722 | if (insn_contains_asm (insn)) | |
1723 | for (def_rec = DF_INSN_DEFS (insn); *def_rec; def_rec++) | |
1724 | { | |
57512f53 | 1725 | df_ref def = *def_rec; |
058e97ec VM |
1726 | unsigned int dregno = DF_REF_REGNO (def); |
1727 | if (dregno < FIRST_PSEUDO_REGISTER) | |
1728 | { | |
1729 | unsigned int i; | |
1730 | enum machine_mode mode = GET_MODE (DF_REF_REAL_REG (def)); | |
b8698a0f | 1731 | unsigned int end = dregno |
058e97ec VM |
1732 | + hard_regno_nregs[dregno][mode] - 1; |
1733 | ||
1734 | for (i = dregno; i <= end; ++i) | |
b748fbd6 | 1735 | SET_HARD_REG_BIT(crtl->asm_clobbers, i); |
058e97ec VM |
1736 | } |
1737 | } | |
1738 | } | |
1739 | } | |
1740 | } | |
1741 | ||
1742 | ||
1743 | /* Set up ELIMINABLE_REGSET, IRA_NO_ALLOC_REGS, and REGS_EVER_LIVE. */ | |
ce18efcb VM |
1744 | void |
1745 | ira_setup_eliminable_regset (void) | |
058e97ec | 1746 | { |
058e97ec | 1747 | #ifdef ELIMINABLE_REGS |
89ceba31 | 1748 | int i; |
058e97ec VM |
1749 | static const struct {const int from, to; } eliminables[] = ELIMINABLE_REGS; |
1750 | #endif | |
1751 | /* FIXME: If EXIT_IGNORE_STACK is set, we will not save and restore | |
1752 | sp for alloca. So we can't eliminate the frame pointer in that | |
1753 | case. At some point, we should improve this by emitting the | |
1754 | sp-adjusting insns for this case. */ | |
1755 | int need_fp | |
1756 | = (! flag_omit_frame_pointer | |
1757 | || (cfun->calls_alloca && EXIT_IGNORE_STACK) | |
d809253a EB |
1758 | /* We need the frame pointer to catch stack overflow exceptions |
1759 | if the stack pointer is moving. */ | |
1760 | || (flag_stack_check && STACK_CHECK_MOVING_SP) | |
058e97ec VM |
1761 | || crtl->accesses_prior_frames |
1762 | || crtl->stack_realign_needed | |
b52b1749 | 1763 | || targetm.frame_pointer_required ()); |
058e97ec VM |
1764 | |
1765 | frame_pointer_needed = need_fp; | |
1766 | ||
1767 | COPY_HARD_REG_SET (ira_no_alloc_regs, no_unit_alloc_regs); | |
1768 | CLEAR_HARD_REG_SET (eliminable_regset); | |
1769 | ||
b748fbd6 PB |
1770 | compute_regs_asm_clobbered (); |
1771 | ||
058e97ec VM |
1772 | /* Build the regset of all eliminable registers and show we can't |
1773 | use those that we already know won't be eliminated. */ | |
1774 | #ifdef ELIMINABLE_REGS | |
1775 | for (i = 0; i < (int) ARRAY_SIZE (eliminables); i++) | |
1776 | { | |
1777 | bool cannot_elim | |
7b5cbb57 | 1778 | = (! targetm.can_eliminate (eliminables[i].from, eliminables[i].to) |
058e97ec VM |
1779 | || (eliminables[i].to == STACK_POINTER_REGNUM && need_fp)); |
1780 | ||
b748fbd6 | 1781 | if (!TEST_HARD_REG_BIT (crtl->asm_clobbers, eliminables[i].from)) |
058e97ec VM |
1782 | { |
1783 | SET_HARD_REG_BIT (eliminable_regset, eliminables[i].from); | |
1784 | ||
1785 | if (cannot_elim) | |
1786 | SET_HARD_REG_BIT (ira_no_alloc_regs, eliminables[i].from); | |
1787 | } | |
1788 | else if (cannot_elim) | |
1789 | error ("%s cannot be used in asm here", | |
1790 | reg_names[eliminables[i].from]); | |
1791 | else | |
1792 | df_set_regs_ever_live (eliminables[i].from, true); | |
1793 | } | |
e3339d0f | 1794 | #if !HARD_FRAME_POINTER_IS_FRAME_POINTER |
b748fbd6 | 1795 | if (!TEST_HARD_REG_BIT (crtl->asm_clobbers, HARD_FRAME_POINTER_REGNUM)) |
058e97ec VM |
1796 | { |
1797 | SET_HARD_REG_BIT (eliminable_regset, HARD_FRAME_POINTER_REGNUM); | |
1798 | if (need_fp) | |
1799 | SET_HARD_REG_BIT (ira_no_alloc_regs, HARD_FRAME_POINTER_REGNUM); | |
1800 | } | |
1801 | else if (need_fp) | |
1802 | error ("%s cannot be used in asm here", | |
1803 | reg_names[HARD_FRAME_POINTER_REGNUM]); | |
1804 | else | |
1805 | df_set_regs_ever_live (HARD_FRAME_POINTER_REGNUM, true); | |
1806 | #endif | |
1807 | ||
1808 | #else | |
b748fbd6 | 1809 | if (!TEST_HARD_REG_BIT (crtl->asm_clobbers, HARD_FRAME_POINTER_REGNUM)) |
058e97ec VM |
1810 | { |
1811 | SET_HARD_REG_BIT (eliminable_regset, FRAME_POINTER_REGNUM); | |
1812 | if (need_fp) | |
1813 | SET_HARD_REG_BIT (ira_no_alloc_regs, FRAME_POINTER_REGNUM); | |
1814 | } | |
1815 | else if (need_fp) | |
1816 | error ("%s cannot be used in asm here", reg_names[FRAME_POINTER_REGNUM]); | |
1817 | else | |
1818 | df_set_regs_ever_live (FRAME_POINTER_REGNUM, true); | |
1819 | #endif | |
1820 | } | |
1821 | ||
1822 | \f | |
1823 | ||
1824 | /* The length of the following two arrays. */ | |
1825 | int ira_reg_equiv_len; | |
1826 | ||
1827 | /* The element value is TRUE if the corresponding regno value is | |
1828 | invariant. */ | |
1829 | bool *ira_reg_equiv_invariant_p; | |
1830 | ||
1831 | /* The element value is equiv constant of given pseudo-register or | |
1832 | NULL_RTX. */ | |
1833 | rtx *ira_reg_equiv_const; | |
1834 | ||
1835 | /* Set up the two arrays declared above. */ | |
1836 | static void | |
1837 | find_reg_equiv_invariant_const (void) | |
1838 | { | |
f2034d06 | 1839 | unsigned int i; |
058e97ec VM |
1840 | bool invariant_p; |
1841 | rtx list, insn, note, constant, x; | |
1842 | ||
f2034d06 | 1843 | for (i = FIRST_PSEUDO_REGISTER; i < VEC_length (reg_equivs_t, reg_equivs); i++) |
058e97ec VM |
1844 | { |
1845 | constant = NULL_RTX; | |
1846 | invariant_p = false; | |
f2034d06 | 1847 | for (list = reg_equiv_init (i); list != NULL_RTX; list = XEXP (list, 1)) |
058e97ec VM |
1848 | { |
1849 | insn = XEXP (list, 0); | |
1850 | note = find_reg_note (insn, REG_EQUIV, NULL_RTX); | |
b8698a0f | 1851 | |
058e97ec VM |
1852 | if (note == NULL_RTX) |
1853 | continue; | |
1854 | ||
1855 | x = XEXP (note, 0); | |
b8698a0f | 1856 | |
60de8907 BS |
1857 | if (! CONSTANT_P (x) |
1858 | || ! flag_pic || LEGITIMATE_PIC_OPERAND_P (x)) | |
058e97ec VM |
1859 | { |
1860 | /* It can happen that a REG_EQUIV note contains a MEM | |
1861 | that is not a legitimate memory operand. As later | |
1862 | stages of the reload assume that all addresses found | |
1863 | in the reg_equiv_* arrays were originally legitimate, | |
1864 | we ignore such REG_EQUIV notes. */ | |
1865 | if (memory_operand (x, VOIDmode)) | |
1866 | invariant_p = MEM_READONLY_P (x); | |
1867 | else if (function_invariant_p (x)) | |
1868 | { | |
1869 | if (GET_CODE (x) == PLUS | |
1870 | || x == frame_pointer_rtx || x == arg_pointer_rtx) | |
1871 | invariant_p = true; | |
1872 | else | |
1873 | constant = x; | |
1874 | } | |
1875 | } | |
1876 | } | |
1877 | ira_reg_equiv_invariant_p[i] = invariant_p; | |
1878 | ira_reg_equiv_const[i] = constant; | |
1879 | } | |
1880 | } | |
1881 | ||
1882 | \f | |
1883 | ||
2af2dbdc VM |
1884 | /* Vector of substitutions of register numbers, |
1885 | used to map pseudo regs into hardware regs. | |
1886 | This is set up as a result of register allocation. | |
1887 | Element N is the hard reg assigned to pseudo reg N, | |
1888 | or is -1 if no hard reg was assigned. | |
1889 | If N is a hard reg number, element N is N. */ | |
1890 | short *reg_renumber; | |
1891 | ||
058e97ec VM |
1892 | /* Set up REG_RENUMBER and CALLER_SAVE_NEEDED (used by reload) from |
1893 | the allocation found by IRA. */ | |
1894 | static void | |
1895 | setup_reg_renumber (void) | |
1896 | { | |
1897 | int regno, hard_regno; | |
1898 | ira_allocno_t a; | |
1899 | ira_allocno_iterator ai; | |
1900 | ||
1901 | caller_save_needed = 0; | |
1902 | FOR_EACH_ALLOCNO (a, ai) | |
1903 | { | |
1904 | /* There are no caps at this point. */ | |
1905 | ira_assert (ALLOCNO_CAP_MEMBER (a) == NULL); | |
1906 | if (! ALLOCNO_ASSIGNED_P (a)) | |
1907 | /* It can happen if A is not referenced but partially anticipated | |
1908 | somewhere in a region. */ | |
1909 | ALLOCNO_ASSIGNED_P (a) = true; | |
1910 | ira_free_allocno_updated_costs (a); | |
1911 | hard_regno = ALLOCNO_HARD_REGNO (a); | |
1756cb66 | 1912 | regno = ALLOCNO_REGNO (a); |
058e97ec | 1913 | reg_renumber[regno] = (hard_regno < 0 ? -1 : hard_regno); |
1756cb66 | 1914 | if (hard_regno >= 0) |
058e97ec | 1915 | { |
1756cb66 VM |
1916 | int i, nwords; |
1917 | enum reg_class pclass; | |
1918 | ira_object_t obj; | |
1919 | ||
1920 | pclass = ira_pressure_class_translate[REGNO_REG_CLASS (hard_regno)]; | |
1921 | nwords = ALLOCNO_NUM_OBJECTS (a); | |
1922 | for (i = 0; i < nwords; i++) | |
1923 | { | |
1924 | obj = ALLOCNO_OBJECT (a, i); | |
1925 | IOR_COMPL_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), | |
1926 | reg_class_contents[pclass]); | |
1927 | } | |
1928 | if (ALLOCNO_CALLS_CROSSED_NUM (a) != 0 | |
1929 | && ! ira_hard_reg_not_in_set_p (hard_regno, ALLOCNO_MODE (a), | |
1930 | call_used_reg_set)) | |
1931 | { | |
1932 | ira_assert (!optimize || flag_caller_saves | |
1933 | || regno >= ira_reg_equiv_len | |
1934 | || ira_reg_equiv_const[regno] | |
1935 | || ira_reg_equiv_invariant_p[regno]); | |
1936 | caller_save_needed = 1; | |
1937 | } | |
058e97ec VM |
1938 | } |
1939 | } | |
1940 | } | |
1941 | ||
1942 | /* Set up allocno assignment flags for further allocation | |
1943 | improvements. */ | |
1944 | static void | |
1945 | setup_allocno_assignment_flags (void) | |
1946 | { | |
1947 | int hard_regno; | |
1948 | ira_allocno_t a; | |
1949 | ira_allocno_iterator ai; | |
1950 | ||
1951 | FOR_EACH_ALLOCNO (a, ai) | |
1952 | { | |
1953 | if (! ALLOCNO_ASSIGNED_P (a)) | |
1954 | /* It can happen if A is not referenced but partially anticipated | |
1955 | somewhere in a region. */ | |
1956 | ira_free_allocno_updated_costs (a); | |
1957 | hard_regno = ALLOCNO_HARD_REGNO (a); | |
1958 | /* Don't assign hard registers to allocnos which are destination | |
1959 | of removed store at the end of loop. It has no sense to keep | |
1960 | the same value in different hard registers. It is also | |
1961 | impossible to assign hard registers correctly to such | |
1962 | allocnos because the cost info and info about intersected | |
1963 | calls are incorrect for them. */ | |
1964 | ALLOCNO_ASSIGNED_P (a) = (hard_regno >= 0 | |
1756cb66 | 1965 | || ALLOCNO_EMIT_DATA (a)->mem_optimized_dest_p |
058e97ec | 1966 | || (ALLOCNO_MEMORY_COST (a) |
1756cb66 | 1967 | - ALLOCNO_CLASS_COST (a)) < 0); |
058e97ec VM |
1968 | ira_assert (hard_regno < 0 |
1969 | || ! ira_hard_reg_not_in_set_p (hard_regno, ALLOCNO_MODE (a), | |
1970 | reg_class_contents | |
1756cb66 | 1971 | [ALLOCNO_CLASS (a)])); |
058e97ec VM |
1972 | } |
1973 | } | |
1974 | ||
1975 | /* Evaluate overall allocation cost and the costs for using hard | |
1976 | registers and memory for allocnos. */ | |
1977 | static void | |
1978 | calculate_allocation_cost (void) | |
1979 | { | |
1980 | int hard_regno, cost; | |
1981 | ira_allocno_t a; | |
1982 | ira_allocno_iterator ai; | |
1983 | ||
1984 | ira_overall_cost = ira_reg_cost = ira_mem_cost = 0; | |
1985 | FOR_EACH_ALLOCNO (a, ai) | |
1986 | { | |
1987 | hard_regno = ALLOCNO_HARD_REGNO (a); | |
1988 | ira_assert (hard_regno < 0 | |
1989 | || ! ira_hard_reg_not_in_set_p | |
1990 | (hard_regno, ALLOCNO_MODE (a), | |
1756cb66 | 1991 | reg_class_contents[ALLOCNO_CLASS (a)])); |
058e97ec VM |
1992 | if (hard_regno < 0) |
1993 | { | |
1994 | cost = ALLOCNO_MEMORY_COST (a); | |
1995 | ira_mem_cost += cost; | |
1996 | } | |
1997 | else if (ALLOCNO_HARD_REG_COSTS (a) != NULL) | |
1998 | { | |
1999 | cost = (ALLOCNO_HARD_REG_COSTS (a) | |
2000 | [ira_class_hard_reg_index | |
1756cb66 | 2001 | [ALLOCNO_CLASS (a)][hard_regno]]); |
058e97ec VM |
2002 | ira_reg_cost += cost; |
2003 | } | |
2004 | else | |
2005 | { | |
1756cb66 | 2006 | cost = ALLOCNO_CLASS_COST (a); |
058e97ec VM |
2007 | ira_reg_cost += cost; |
2008 | } | |
2009 | ira_overall_cost += cost; | |
2010 | } | |
2011 | ||
2012 | if (internal_flag_ira_verbose > 0 && ira_dump_file != NULL) | |
2013 | { | |
2014 | fprintf (ira_dump_file, | |
2015 | "+++Costs: overall %d, reg %d, mem %d, ld %d, st %d, move %d\n", | |
2016 | ira_overall_cost, ira_reg_cost, ira_mem_cost, | |
2017 | ira_load_cost, ira_store_cost, ira_shuffle_cost); | |
2018 | fprintf (ira_dump_file, "+++ move loops %d, new jumps %d\n", | |
2019 | ira_move_loops_num, ira_additional_jumps_num); | |
2020 | } | |
2021 | ||
2022 | } | |
2023 | ||
2024 | #ifdef ENABLE_IRA_CHECKING | |
2025 | /* Check the correctness of the allocation. We do need this because | |
2026 | of complicated code to transform more one region internal | |
2027 | representation into one region representation. */ | |
2028 | static void | |
2029 | check_allocation (void) | |
2030 | { | |
fa86d337 | 2031 | ira_allocno_t a; |
ac0ab4f7 | 2032 | int hard_regno, nregs, conflict_nregs; |
058e97ec VM |
2033 | ira_allocno_iterator ai; |
2034 | ||
2035 | FOR_EACH_ALLOCNO (a, ai) | |
2036 | { | |
ac0ab4f7 BS |
2037 | int n = ALLOCNO_NUM_OBJECTS (a); |
2038 | int i; | |
fa86d337 | 2039 | |
058e97ec VM |
2040 | if (ALLOCNO_CAP_MEMBER (a) != NULL |
2041 | || (hard_regno = ALLOCNO_HARD_REGNO (a)) < 0) | |
2042 | continue; | |
2043 | nregs = hard_regno_nregs[hard_regno][ALLOCNO_MODE (a)]; | |
8cfd82bf BS |
2044 | if (nregs == 1) |
2045 | /* We allocated a single hard register. */ | |
2046 | n = 1; | |
2047 | else if (n > 1) | |
2048 | /* We allocated multiple hard registers, and we will test | |
2049 | conflicts in a granularity of single hard regs. */ | |
2050 | nregs = 1; | |
2051 | ||
ac0ab4f7 BS |
2052 | for (i = 0; i < n; i++) |
2053 | { | |
2054 | ira_object_t obj = ALLOCNO_OBJECT (a, i); | |
2055 | ira_object_t conflict_obj; | |
2056 | ira_object_conflict_iterator oci; | |
2057 | int this_regno = hard_regno; | |
2058 | if (n > 1) | |
fa86d337 | 2059 | { |
ac0ab4f7 BS |
2060 | if (WORDS_BIG_ENDIAN) |
2061 | this_regno += n - i - 1; | |
2062 | else | |
2063 | this_regno += i; | |
2064 | } | |
2065 | FOR_EACH_OBJECT_CONFLICT (obj, conflict_obj, oci) | |
2066 | { | |
2067 | ira_allocno_t conflict_a = OBJECT_ALLOCNO (conflict_obj); | |
2068 | int conflict_hard_regno = ALLOCNO_HARD_REGNO (conflict_a); | |
2069 | if (conflict_hard_regno < 0) | |
2070 | continue; | |
8cfd82bf BS |
2071 | |
2072 | conflict_nregs | |
2073 | = (hard_regno_nregs | |
2074 | [conflict_hard_regno][ALLOCNO_MODE (conflict_a)]); | |
2075 | ||
2076 | if (ALLOCNO_NUM_OBJECTS (conflict_a) > 1 | |
2077 | && conflict_nregs == ALLOCNO_NUM_OBJECTS (conflict_a)) | |
ac0ab4f7 BS |
2078 | { |
2079 | if (WORDS_BIG_ENDIAN) | |
2080 | conflict_hard_regno += (ALLOCNO_NUM_OBJECTS (conflict_a) | |
2081 | - OBJECT_SUBWORD (conflict_obj) - 1); | |
2082 | else | |
2083 | conflict_hard_regno += OBJECT_SUBWORD (conflict_obj); | |
2084 | conflict_nregs = 1; | |
2085 | } | |
ac0ab4f7 BS |
2086 | |
2087 | if ((conflict_hard_regno <= this_regno | |
2088 | && this_regno < conflict_hard_regno + conflict_nregs) | |
2089 | || (this_regno <= conflict_hard_regno | |
2090 | && conflict_hard_regno < this_regno + nregs)) | |
fa86d337 BS |
2091 | { |
2092 | fprintf (stderr, "bad allocation for %d and %d\n", | |
2093 | ALLOCNO_REGNO (a), ALLOCNO_REGNO (conflict_a)); | |
2094 | gcc_unreachable (); | |
2095 | } | |
2096 | } | |
2097 | } | |
058e97ec VM |
2098 | } |
2099 | } | |
2100 | #endif | |
2101 | ||
2102 | /* Fix values of array REG_EQUIV_INIT after live range splitting done | |
2103 | by IRA. */ | |
2104 | static void | |
2105 | fix_reg_equiv_init (void) | |
2106 | { | |
f2034d06 JL |
2107 | unsigned int max_regno = max_reg_num (); |
2108 | int i, new_regno, max; | |
058e97ec | 2109 | rtx x, prev, next, insn, set; |
b8698a0f | 2110 | |
f2034d06 | 2111 | if (VEC_length (reg_equivs_t, reg_equivs) < max_regno) |
058e97ec | 2112 | { |
f2034d06 JL |
2113 | max = VEC_length (reg_equivs_t, reg_equivs); |
2114 | grow_reg_equivs (); | |
2115 | for (i = FIRST_PSEUDO_REGISTER; i < max; i++) | |
2116 | for (prev = NULL_RTX, x = reg_equiv_init (i); | |
2117 | x != NULL_RTX; | |
2118 | x = next) | |
058e97ec VM |
2119 | { |
2120 | next = XEXP (x, 1); | |
2121 | insn = XEXP (x, 0); | |
2122 | set = single_set (insn); | |
2123 | ira_assert (set != NULL_RTX | |
2124 | && (REG_P (SET_DEST (set)) || REG_P (SET_SRC (set)))); | |
2125 | if (REG_P (SET_DEST (set)) | |
2126 | && ((int) REGNO (SET_DEST (set)) == i | |
2127 | || (int) ORIGINAL_REGNO (SET_DEST (set)) == i)) | |
2128 | new_regno = REGNO (SET_DEST (set)); | |
2129 | else if (REG_P (SET_SRC (set)) | |
2130 | && ((int) REGNO (SET_SRC (set)) == i | |
2131 | || (int) ORIGINAL_REGNO (SET_SRC (set)) == i)) | |
2132 | new_regno = REGNO (SET_SRC (set)); | |
2133 | else | |
2134 | gcc_unreachable (); | |
2135 | if (new_regno == i) | |
2136 | prev = x; | |
2137 | else | |
2138 | { | |
2139 | if (prev == NULL_RTX) | |
f2034d06 | 2140 | reg_equiv_init (i) = next; |
058e97ec VM |
2141 | else |
2142 | XEXP (prev, 1) = next; | |
f2034d06 JL |
2143 | XEXP (x, 1) = reg_equiv_init (new_regno); |
2144 | reg_equiv_init (new_regno) = x; | |
058e97ec VM |
2145 | } |
2146 | } | |
2147 | } | |
2148 | } | |
2149 | ||
2150 | #ifdef ENABLE_IRA_CHECKING | |
2151 | /* Print redundant memory-memory copies. */ | |
2152 | static void | |
2153 | print_redundant_copies (void) | |
2154 | { | |
2155 | int hard_regno; | |
2156 | ira_allocno_t a; | |
2157 | ira_copy_t cp, next_cp; | |
2158 | ira_allocno_iterator ai; | |
b8698a0f | 2159 | |
058e97ec VM |
2160 | FOR_EACH_ALLOCNO (a, ai) |
2161 | { | |
2162 | if (ALLOCNO_CAP_MEMBER (a) != NULL) | |
2163 | /* It is a cap. */ | |
2164 | continue; | |
2165 | hard_regno = ALLOCNO_HARD_REGNO (a); | |
2166 | if (hard_regno >= 0) | |
2167 | continue; | |
2168 | for (cp = ALLOCNO_COPIES (a); cp != NULL; cp = next_cp) | |
2169 | if (cp->first == a) | |
2170 | next_cp = cp->next_first_allocno_copy; | |
2171 | else | |
2172 | { | |
2173 | next_cp = cp->next_second_allocno_copy; | |
2174 | if (internal_flag_ira_verbose > 4 && ira_dump_file != NULL | |
2175 | && cp->insn != NULL_RTX | |
2176 | && ALLOCNO_HARD_REGNO (cp->first) == hard_regno) | |
2177 | fprintf (ira_dump_file, | |
2178 | " Redundant move from %d(freq %d):%d\n", | |
2179 | INSN_UID (cp->insn), cp->freq, hard_regno); | |
2180 | } | |
2181 | } | |
2182 | } | |
2183 | #endif | |
2184 | ||
2185 | /* Setup preferred and alternative classes for new pseudo-registers | |
2186 | created by IRA starting with START. */ | |
2187 | static void | |
2188 | setup_preferred_alternate_classes_for_new_pseudos (int start) | |
2189 | { | |
2190 | int i, old_regno; | |
2191 | int max_regno = max_reg_num (); | |
2192 | ||
2193 | for (i = start; i < max_regno; i++) | |
2194 | { | |
2195 | old_regno = ORIGINAL_REGNO (regno_reg_rtx[i]); | |
b8698a0f | 2196 | ira_assert (i != old_regno); |
058e97ec | 2197 | setup_reg_classes (i, reg_preferred_class (old_regno), |
ce18efcb | 2198 | reg_alternate_class (old_regno), |
1756cb66 | 2199 | reg_allocno_class (old_regno)); |
058e97ec VM |
2200 | if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL) |
2201 | fprintf (ira_dump_file, | |
2202 | " New r%d: setting preferred %s, alternative %s\n", | |
2203 | i, reg_class_names[reg_preferred_class (old_regno)], | |
2204 | reg_class_names[reg_alternate_class (old_regno)]); | |
2205 | } | |
2206 | } | |
2207 | ||
2208 | \f | |
2209 | ||
2210 | /* Regional allocation can create new pseudo-registers. This function | |
2211 | expands some arrays for pseudo-registers. */ | |
2212 | static void | |
2213 | expand_reg_info (int old_size) | |
2214 | { | |
2215 | int i; | |
2216 | int size = max_reg_num (); | |
2217 | ||
2218 | resize_reg_info (); | |
2219 | for (i = old_size; i < size; i++) | |
ce18efcb | 2220 | setup_reg_classes (i, GENERAL_REGS, ALL_REGS, GENERAL_REGS); |
058e97ec VM |
2221 | } |
2222 | ||
3553f0bb VM |
2223 | /* Return TRUE if there is too high register pressure in the function. |
2224 | It is used to decide when stack slot sharing is worth to do. */ | |
2225 | static bool | |
2226 | too_high_register_pressure_p (void) | |
2227 | { | |
2228 | int i; | |
1756cb66 | 2229 | enum reg_class pclass; |
b8698a0f | 2230 | |
1756cb66 | 2231 | for (i = 0; i < ira_pressure_classes_num; i++) |
3553f0bb | 2232 | { |
1756cb66 VM |
2233 | pclass = ira_pressure_classes[i]; |
2234 | if (ira_loop_tree_root->reg_pressure[pclass] > 10000) | |
3553f0bb VM |
2235 | return true; |
2236 | } | |
2237 | return false; | |
2238 | } | |
2239 | ||
058e97ec VM |
2240 | \f |
2241 | ||
2af2dbdc VM |
2242 | /* Indicate that hard register number FROM was eliminated and replaced with |
2243 | an offset from hard register number TO. The status of hard registers live | |
2244 | at the start of a basic block is updated by replacing a use of FROM with | |
2245 | a use of TO. */ | |
2246 | ||
2247 | void | |
2248 | mark_elimination (int from, int to) | |
2249 | { | |
2250 | basic_block bb; | |
2251 | ||
2252 | FOR_EACH_BB (bb) | |
2253 | { | |
2254 | /* We don't use LIVE info in IRA. */ | |
7a8cba34 | 2255 | bitmap r = DF_LR_IN (bb); |
2af2dbdc VM |
2256 | |
2257 | if (REGNO_REG_SET_P (r, from)) | |
2258 | { | |
2259 | CLEAR_REGNO_REG_SET (r, from); | |
2260 | SET_REGNO_REG_SET (r, to); | |
2261 | } | |
2262 | } | |
2263 | } | |
2264 | ||
2265 | \f | |
2266 | ||
2267 | struct equivalence | |
2268 | { | |
2af2dbdc VM |
2269 | /* Set when a REG_EQUIV note is found or created. Use to |
2270 | keep track of what memory accesses might be created later, | |
2271 | e.g. by reload. */ | |
2272 | rtx replacement; | |
2273 | rtx *src_p; | |
8f5929e1 JJ |
2274 | /* The list of each instruction which initializes this register. */ |
2275 | rtx init_insns; | |
2af2dbdc VM |
2276 | /* Loop depth is used to recognize equivalences which appear |
2277 | to be present within the same loop (or in an inner loop). */ | |
2278 | int loop_depth; | |
2af2dbdc VM |
2279 | /* Nonzero if this had a preexisting REG_EQUIV note. */ |
2280 | int is_arg_equivalence; | |
8f5929e1 JJ |
2281 | /* Set when an attempt should be made to replace a register |
2282 | with the associated src_p entry. */ | |
2283 | char replace; | |
2af2dbdc VM |
2284 | }; |
2285 | ||
2286 | /* reg_equiv[N] (where N is a pseudo reg number) is the equivalence | |
2287 | structure for that register. */ | |
2288 | static struct equivalence *reg_equiv; | |
2289 | ||
2290 | /* Used for communication between the following two functions: contains | |
2291 | a MEM that we wish to ensure remains unchanged. */ | |
2292 | static rtx equiv_mem; | |
2293 | ||
2294 | /* Set nonzero if EQUIV_MEM is modified. */ | |
2295 | static int equiv_mem_modified; | |
2296 | ||
2297 | /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified. | |
2298 | Called via note_stores. */ | |
2299 | static void | |
2300 | validate_equiv_mem_from_store (rtx dest, const_rtx set ATTRIBUTE_UNUSED, | |
2301 | void *data ATTRIBUTE_UNUSED) | |
2302 | { | |
2303 | if ((REG_P (dest) | |
2304 | && reg_overlap_mentioned_p (dest, equiv_mem)) | |
2305 | || (MEM_P (dest) | |
2306 | && true_dependence (dest, VOIDmode, equiv_mem, rtx_varies_p))) | |
2307 | equiv_mem_modified = 1; | |
2308 | } | |
2309 | ||
2310 | /* Verify that no store between START and the death of REG invalidates | |
2311 | MEMREF. MEMREF is invalidated by modifying a register used in MEMREF, | |
2312 | by storing into an overlapping memory location, or with a non-const | |
2313 | CALL_INSN. | |
2314 | ||
2315 | Return 1 if MEMREF remains valid. */ | |
2316 | static int | |
2317 | validate_equiv_mem (rtx start, rtx reg, rtx memref) | |
2318 | { | |
2319 | rtx insn; | |
2320 | rtx note; | |
2321 | ||
2322 | equiv_mem = memref; | |
2323 | equiv_mem_modified = 0; | |
2324 | ||
2325 | /* If the memory reference has side effects or is volatile, it isn't a | |
2326 | valid equivalence. */ | |
2327 | if (side_effects_p (memref)) | |
2328 | return 0; | |
2329 | ||
2330 | for (insn = start; insn && ! equiv_mem_modified; insn = NEXT_INSN (insn)) | |
2331 | { | |
2332 | if (! INSN_P (insn)) | |
2333 | continue; | |
2334 | ||
2335 | if (find_reg_note (insn, REG_DEAD, reg)) | |
2336 | return 1; | |
2337 | ||
a22265a4 JL |
2338 | /* This used to ignore readonly memory and const/pure calls. The problem |
2339 | is the equivalent form may reference a pseudo which gets assigned a | |
2340 | call clobbered hard reg. When we later replace REG with its | |
2341 | equivalent form, the value in the call-clobbered reg has been | |
2342 | changed and all hell breaks loose. */ | |
2343 | if (CALL_P (insn)) | |
2af2dbdc VM |
2344 | return 0; |
2345 | ||
2346 | note_stores (PATTERN (insn), validate_equiv_mem_from_store, NULL); | |
2347 | ||
2348 | /* If a register mentioned in MEMREF is modified via an | |
2349 | auto-increment, we lose the equivalence. Do the same if one | |
2350 | dies; although we could extend the life, it doesn't seem worth | |
2351 | the trouble. */ | |
2352 | ||
2353 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
2354 | if ((REG_NOTE_KIND (note) == REG_INC | |
2355 | || REG_NOTE_KIND (note) == REG_DEAD) | |
2356 | && REG_P (XEXP (note, 0)) | |
2357 | && reg_overlap_mentioned_p (XEXP (note, 0), memref)) | |
2358 | return 0; | |
2359 | } | |
2360 | ||
2361 | return 0; | |
2362 | } | |
2363 | ||
2364 | /* Returns zero if X is known to be invariant. */ | |
2365 | static int | |
2366 | equiv_init_varies_p (rtx x) | |
2367 | { | |
2368 | RTX_CODE code = GET_CODE (x); | |
2369 | int i; | |
2370 | const char *fmt; | |
2371 | ||
2372 | switch (code) | |
2373 | { | |
2374 | case MEM: | |
2375 | return !MEM_READONLY_P (x) || equiv_init_varies_p (XEXP (x, 0)); | |
2376 | ||
2377 | case CONST: | |
2378 | case CONST_INT: | |
2379 | case CONST_DOUBLE: | |
2380 | case CONST_FIXED: | |
2381 | case CONST_VECTOR: | |
2382 | case SYMBOL_REF: | |
2383 | case LABEL_REF: | |
2384 | return 0; | |
2385 | ||
2386 | case REG: | |
2387 | return reg_equiv[REGNO (x)].replace == 0 && rtx_varies_p (x, 0); | |
2388 | ||
2389 | case ASM_OPERANDS: | |
2390 | if (MEM_VOLATILE_P (x)) | |
2391 | return 1; | |
2392 | ||
2393 | /* Fall through. */ | |
2394 | ||
2395 | default: | |
2396 | break; | |
2397 | } | |
2398 | ||
2399 | fmt = GET_RTX_FORMAT (code); | |
2400 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2401 | if (fmt[i] == 'e') | |
2402 | { | |
2403 | if (equiv_init_varies_p (XEXP (x, i))) | |
2404 | return 1; | |
2405 | } | |
2406 | else if (fmt[i] == 'E') | |
2407 | { | |
2408 | int j; | |
2409 | for (j = 0; j < XVECLEN (x, i); j++) | |
2410 | if (equiv_init_varies_p (XVECEXP (x, i, j))) | |
2411 | return 1; | |
2412 | } | |
2413 | ||
2414 | return 0; | |
2415 | } | |
2416 | ||
2417 | /* Returns nonzero if X (used to initialize register REGNO) is movable. | |
2418 | X is only movable if the registers it uses have equivalent initializations | |
2419 | which appear to be within the same loop (or in an inner loop) and movable | |
2420 | or if they are not candidates for local_alloc and don't vary. */ | |
2421 | static int | |
2422 | equiv_init_movable_p (rtx x, int regno) | |
2423 | { | |
2424 | int i, j; | |
2425 | const char *fmt; | |
2426 | enum rtx_code code = GET_CODE (x); | |
2427 | ||
2428 | switch (code) | |
2429 | { | |
2430 | case SET: | |
2431 | return equiv_init_movable_p (SET_SRC (x), regno); | |
2432 | ||
2433 | case CC0: | |
2434 | case CLOBBER: | |
2435 | return 0; | |
2436 | ||
2437 | case PRE_INC: | |
2438 | case PRE_DEC: | |
2439 | case POST_INC: | |
2440 | case POST_DEC: | |
2441 | case PRE_MODIFY: | |
2442 | case POST_MODIFY: | |
2443 | return 0; | |
2444 | ||
2445 | case REG: | |
1756cb66 VM |
2446 | return ((reg_equiv[REGNO (x)].loop_depth >= reg_equiv[regno].loop_depth |
2447 | && reg_equiv[REGNO (x)].replace) | |
2448 | || (REG_BASIC_BLOCK (REGNO (x)) < NUM_FIXED_BLOCKS | |
2449 | && ! rtx_varies_p (x, 0))); | |
2af2dbdc VM |
2450 | |
2451 | case UNSPEC_VOLATILE: | |
2452 | return 0; | |
2453 | ||
2454 | case ASM_OPERANDS: | |
2455 | if (MEM_VOLATILE_P (x)) | |
2456 | return 0; | |
2457 | ||
2458 | /* Fall through. */ | |
2459 | ||
2460 | default: | |
2461 | break; | |
2462 | } | |
2463 | ||
2464 | fmt = GET_RTX_FORMAT (code); | |
2465 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2466 | switch (fmt[i]) | |
2467 | { | |
2468 | case 'e': | |
2469 | if (! equiv_init_movable_p (XEXP (x, i), regno)) | |
2470 | return 0; | |
2471 | break; | |
2472 | case 'E': | |
2473 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
2474 | if (! equiv_init_movable_p (XVECEXP (x, i, j), regno)) | |
2475 | return 0; | |
2476 | break; | |
2477 | } | |
2478 | ||
2479 | return 1; | |
2480 | } | |
2481 | ||
1756cb66 VM |
2482 | /* TRUE if X uses any registers for which reg_equiv[REGNO].replace is |
2483 | true. */ | |
2af2dbdc VM |
2484 | static int |
2485 | contains_replace_regs (rtx x) | |
2486 | { | |
2487 | int i, j; | |
2488 | const char *fmt; | |
2489 | enum rtx_code code = GET_CODE (x); | |
2490 | ||
2491 | switch (code) | |
2492 | { | |
2493 | case CONST_INT: | |
2494 | case CONST: | |
2495 | case LABEL_REF: | |
2496 | case SYMBOL_REF: | |
2497 | case CONST_DOUBLE: | |
2498 | case CONST_FIXED: | |
2499 | case CONST_VECTOR: | |
2500 | case PC: | |
2501 | case CC0: | |
2502 | case HIGH: | |
2503 | return 0; | |
2504 | ||
2505 | case REG: | |
2506 | return reg_equiv[REGNO (x)].replace; | |
2507 | ||
2508 | default: | |
2509 | break; | |
2510 | } | |
2511 | ||
2512 | fmt = GET_RTX_FORMAT (code); | |
2513 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2514 | switch (fmt[i]) | |
2515 | { | |
2516 | case 'e': | |
2517 | if (contains_replace_regs (XEXP (x, i))) | |
2518 | return 1; | |
2519 | break; | |
2520 | case 'E': | |
2521 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
2522 | if (contains_replace_regs (XVECEXP (x, i, j))) | |
2523 | return 1; | |
2524 | break; | |
2525 | } | |
2526 | ||
2527 | return 0; | |
2528 | } | |
2529 | ||
2530 | /* TRUE if X references a memory location that would be affected by a store | |
2531 | to MEMREF. */ | |
2532 | static int | |
2533 | memref_referenced_p (rtx memref, rtx x) | |
2534 | { | |
2535 | int i, j; | |
2536 | const char *fmt; | |
2537 | enum rtx_code code = GET_CODE (x); | |
2538 | ||
2539 | switch (code) | |
2540 | { | |
2541 | case CONST_INT: | |
2542 | case CONST: | |
2543 | case LABEL_REF: | |
2544 | case SYMBOL_REF: | |
2545 | case CONST_DOUBLE: | |
2546 | case CONST_FIXED: | |
2547 | case CONST_VECTOR: | |
2548 | case PC: | |
2549 | case CC0: | |
2550 | case HIGH: | |
2551 | case LO_SUM: | |
2552 | return 0; | |
2553 | ||
2554 | case REG: | |
2555 | return (reg_equiv[REGNO (x)].replacement | |
2556 | && memref_referenced_p (memref, | |
2557 | reg_equiv[REGNO (x)].replacement)); | |
2558 | ||
2559 | case MEM: | |
2560 | if (true_dependence (memref, VOIDmode, x, rtx_varies_p)) | |
2561 | return 1; | |
2562 | break; | |
2563 | ||
2564 | case SET: | |
2565 | /* If we are setting a MEM, it doesn't count (its address does), but any | |
2566 | other SET_DEST that has a MEM in it is referencing the MEM. */ | |
2567 | if (MEM_P (SET_DEST (x))) | |
2568 | { | |
2569 | if (memref_referenced_p (memref, XEXP (SET_DEST (x), 0))) | |
2570 | return 1; | |
2571 | } | |
2572 | else if (memref_referenced_p (memref, SET_DEST (x))) | |
2573 | return 1; | |
2574 | ||
2575 | return memref_referenced_p (memref, SET_SRC (x)); | |
2576 | ||
2577 | default: | |
2578 | break; | |
2579 | } | |
2580 | ||
2581 | fmt = GET_RTX_FORMAT (code); | |
2582 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2583 | switch (fmt[i]) | |
2584 | { | |
2585 | case 'e': | |
2586 | if (memref_referenced_p (memref, XEXP (x, i))) | |
2587 | return 1; | |
2588 | break; | |
2589 | case 'E': | |
2590 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
2591 | if (memref_referenced_p (memref, XVECEXP (x, i, j))) | |
2592 | return 1; | |
2593 | break; | |
2594 | } | |
2595 | ||
2596 | return 0; | |
2597 | } | |
2598 | ||
2599 | /* TRUE if some insn in the range (START, END] references a memory location | |
2600 | that would be affected by a store to MEMREF. */ | |
2601 | static int | |
2602 | memref_used_between_p (rtx memref, rtx start, rtx end) | |
2603 | { | |
2604 | rtx insn; | |
2605 | ||
2606 | for (insn = NEXT_INSN (start); insn != NEXT_INSN (end); | |
2607 | insn = NEXT_INSN (insn)) | |
2608 | { | |
b5b8b0ac | 2609 | if (!NONDEBUG_INSN_P (insn)) |
2af2dbdc | 2610 | continue; |
b8698a0f | 2611 | |
2af2dbdc VM |
2612 | if (memref_referenced_p (memref, PATTERN (insn))) |
2613 | return 1; | |
2614 | ||
2615 | /* Nonconst functions may access memory. */ | |
2616 | if (CALL_P (insn) && (! RTL_CONST_CALL_P (insn))) | |
2617 | return 1; | |
2618 | } | |
2619 | ||
2620 | return 0; | |
2621 | } | |
2622 | ||
2623 | /* Mark REG as having no known equivalence. | |
2624 | Some instructions might have been processed before and furnished | |
2625 | with REG_EQUIV notes for this register; these notes will have to be | |
2626 | removed. | |
2627 | STORE is the piece of RTL that does the non-constant / conflicting | |
2628 | assignment - a SET, CLOBBER or REG_INC note. It is currently not used, | |
2629 | but needs to be there because this function is called from note_stores. */ | |
2630 | static void | |
1756cb66 VM |
2631 | no_equiv (rtx reg, const_rtx store ATTRIBUTE_UNUSED, |
2632 | void *data ATTRIBUTE_UNUSED) | |
2af2dbdc VM |
2633 | { |
2634 | int regno; | |
2635 | rtx list; | |
2636 | ||
2637 | if (!REG_P (reg)) | |
2638 | return; | |
2639 | regno = REGNO (reg); | |
2640 | list = reg_equiv[regno].init_insns; | |
2641 | if (list == const0_rtx) | |
2642 | return; | |
2643 | reg_equiv[regno].init_insns = const0_rtx; | |
2644 | reg_equiv[regno].replacement = NULL_RTX; | |
2645 | /* This doesn't matter for equivalences made for argument registers, we | |
2646 | should keep their initialization insns. */ | |
2647 | if (reg_equiv[regno].is_arg_equivalence) | |
2648 | return; | |
f2034d06 | 2649 | reg_equiv_init (regno) = NULL_RTX; |
2af2dbdc VM |
2650 | for (; list; list = XEXP (list, 1)) |
2651 | { | |
2652 | rtx insn = XEXP (list, 0); | |
2653 | remove_note (insn, find_reg_note (insn, REG_EQUIV, NULL_RTX)); | |
2654 | } | |
2655 | } | |
2656 | ||
3a6191b1 JJ |
2657 | /* In DEBUG_INSN location adjust REGs from CLEARED_REGS bitmap to the |
2658 | equivalent replacement. */ | |
2659 | ||
2660 | static rtx | |
2661 | adjust_cleared_regs (rtx loc, const_rtx old_rtx ATTRIBUTE_UNUSED, void *data) | |
2662 | { | |
2663 | if (REG_P (loc)) | |
2664 | { | |
2665 | bitmap cleared_regs = (bitmap) data; | |
2666 | if (bitmap_bit_p (cleared_regs, REGNO (loc))) | |
2667 | return simplify_replace_fn_rtx (*reg_equiv[REGNO (loc)].src_p, | |
2668 | NULL_RTX, adjust_cleared_regs, data); | |
2669 | } | |
2670 | return NULL_RTX; | |
2671 | } | |
2672 | ||
2af2dbdc VM |
2673 | /* Nonzero if we recorded an equivalence for a LABEL_REF. */ |
2674 | static int recorded_label_ref; | |
2675 | ||
2676 | /* Find registers that are equivalent to a single value throughout the | |
1756cb66 VM |
2677 | compilation (either because they can be referenced in memory or are |
2678 | set once from a single constant). Lower their priority for a | |
2679 | register. | |
2af2dbdc | 2680 | |
1756cb66 VM |
2681 | If such a register is only referenced once, try substituting its |
2682 | value into the using insn. If it succeeds, we can eliminate the | |
2683 | register completely. | |
2af2dbdc VM |
2684 | |
2685 | Initialize the REG_EQUIV_INIT array of initializing insns. | |
2686 | ||
2687 | Return non-zero if jump label rebuilding should be done. */ | |
2688 | static int | |
2689 | update_equiv_regs (void) | |
2690 | { | |
2691 | rtx insn; | |
2692 | basic_block bb; | |
2693 | int loop_depth; | |
2694 | bitmap cleared_regs; | |
b8698a0f | 2695 | |
2af2dbdc VM |
2696 | /* We need to keep track of whether or not we recorded a LABEL_REF so |
2697 | that we know if the jump optimizer needs to be rerun. */ | |
2698 | recorded_label_ref = 0; | |
2699 | ||
2700 | reg_equiv = XCNEWVEC (struct equivalence, max_regno); | |
f2034d06 | 2701 | grow_reg_equivs (); |
2af2dbdc VM |
2702 | |
2703 | init_alias_analysis (); | |
2704 | ||
2705 | /* Scan the insns and find which registers have equivalences. Do this | |
2706 | in a separate scan of the insns because (due to -fcse-follow-jumps) | |
2707 | a register can be set below its use. */ | |
2708 | FOR_EACH_BB (bb) | |
2709 | { | |
2710 | loop_depth = bb->loop_depth; | |
2711 | ||
2712 | for (insn = BB_HEAD (bb); | |
2713 | insn != NEXT_INSN (BB_END (bb)); | |
2714 | insn = NEXT_INSN (insn)) | |
2715 | { | |
2716 | rtx note; | |
2717 | rtx set; | |
2718 | rtx dest, src; | |
2719 | int regno; | |
2720 | ||
2721 | if (! INSN_P (insn)) | |
2722 | continue; | |
2723 | ||
2724 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
2725 | if (REG_NOTE_KIND (note) == REG_INC) | |
2726 | no_equiv (XEXP (note, 0), note, NULL); | |
2727 | ||
2728 | set = single_set (insn); | |
2729 | ||
2730 | /* If this insn contains more (or less) than a single SET, | |
2731 | only mark all destinations as having no known equivalence. */ | |
2732 | if (set == 0) | |
2733 | { | |
2734 | note_stores (PATTERN (insn), no_equiv, NULL); | |
2735 | continue; | |
2736 | } | |
2737 | else if (GET_CODE (PATTERN (insn)) == PARALLEL) | |
2738 | { | |
2739 | int i; | |
2740 | ||
2741 | for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--) | |
2742 | { | |
2743 | rtx part = XVECEXP (PATTERN (insn), 0, i); | |
2744 | if (part != set) | |
2745 | note_stores (part, no_equiv, NULL); | |
2746 | } | |
2747 | } | |
2748 | ||
2749 | dest = SET_DEST (set); | |
2750 | src = SET_SRC (set); | |
2751 | ||
2752 | /* See if this is setting up the equivalence between an argument | |
2753 | register and its stack slot. */ | |
2754 | note = find_reg_note (insn, REG_EQUIV, NULL_RTX); | |
2755 | if (note) | |
2756 | { | |
2757 | gcc_assert (REG_P (dest)); | |
2758 | regno = REGNO (dest); | |
2759 | ||
2760 | /* Note that we don't want to clear reg_equiv_init even if there | |
2761 | are multiple sets of this register. */ | |
2762 | reg_equiv[regno].is_arg_equivalence = 1; | |
2763 | ||
2764 | /* Record for reload that this is an equivalencing insn. */ | |
2765 | if (rtx_equal_p (src, XEXP (note, 0))) | |
f2034d06 JL |
2766 | reg_equiv_init (regno) |
2767 | = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init (regno)); | |
2af2dbdc VM |
2768 | |
2769 | /* Continue normally in case this is a candidate for | |
2770 | replacements. */ | |
2771 | } | |
2772 | ||
2773 | if (!optimize) | |
2774 | continue; | |
2775 | ||
2776 | /* We only handle the case of a pseudo register being set | |
2777 | once, or always to the same value. */ | |
1fe28116 VM |
2778 | /* ??? The mn10200 port breaks if we add equivalences for |
2779 | values that need an ADDRESS_REGS register and set them equivalent | |
2780 | to a MEM of a pseudo. The actual problem is in the over-conservative | |
2781 | handling of INPADDR_ADDRESS / INPUT_ADDRESS / INPUT triples in | |
2782 | calculate_needs, but we traditionally work around this problem | |
2783 | here by rejecting equivalences when the destination is in a register | |
2784 | that's likely spilled. This is fragile, of course, since the | |
2785 | preferred class of a pseudo depends on all instructions that set | |
2786 | or use it. */ | |
2787 | ||
2af2dbdc VM |
2788 | if (!REG_P (dest) |
2789 | || (regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER | |
1fe28116 | 2790 | || reg_equiv[regno].init_insns == const0_rtx |
07b8f0a8 | 2791 | || (targetm.class_likely_spilled_p (reg_preferred_class (regno)) |
1fe28116 | 2792 | && MEM_P (src) && ! reg_equiv[regno].is_arg_equivalence)) |
2af2dbdc VM |
2793 | { |
2794 | /* This might be setting a SUBREG of a pseudo, a pseudo that is | |
2795 | also set somewhere else to a constant. */ | |
2796 | note_stores (set, no_equiv, NULL); | |
2797 | continue; | |
2798 | } | |
2799 | ||
2800 | note = find_reg_note (insn, REG_EQUAL, NULL_RTX); | |
2801 | ||
2802 | /* cse sometimes generates function invariants, but doesn't put a | |
2803 | REG_EQUAL note on the insn. Since this note would be redundant, | |
2804 | there's no point creating it earlier than here. */ | |
2805 | if (! note && ! rtx_varies_p (src, 0)) | |
2806 | note = set_unique_reg_note (insn, REG_EQUAL, copy_rtx (src)); | |
2807 | ||
2808 | /* Don't bother considering a REG_EQUAL note containing an EXPR_LIST | |
2809 | since it represents a function call */ | |
2810 | if (note && GET_CODE (XEXP (note, 0)) == EXPR_LIST) | |
2811 | note = NULL_RTX; | |
2812 | ||
2813 | if (DF_REG_DEF_COUNT (regno) != 1 | |
2814 | && (! note | |
2815 | || rtx_varies_p (XEXP (note, 0), 0) | |
2816 | || (reg_equiv[regno].replacement | |
2817 | && ! rtx_equal_p (XEXP (note, 0), | |
2818 | reg_equiv[regno].replacement)))) | |
2819 | { | |
2820 | no_equiv (dest, set, NULL); | |
2821 | continue; | |
2822 | } | |
2823 | /* Record this insn as initializing this register. */ | |
2824 | reg_equiv[regno].init_insns | |
2825 | = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv[regno].init_insns); | |
2826 | ||
2827 | /* If this register is known to be equal to a constant, record that | |
2828 | it is always equivalent to the constant. */ | |
2829 | if (DF_REG_DEF_COUNT (regno) == 1 | |
2830 | && note && ! rtx_varies_p (XEXP (note, 0), 0)) | |
2831 | { | |
2832 | rtx note_value = XEXP (note, 0); | |
2833 | remove_note (insn, note); | |
2834 | set_unique_reg_note (insn, REG_EQUIV, note_value); | |
2835 | } | |
2836 | ||
2837 | /* If this insn introduces a "constant" register, decrease the priority | |
2838 | of that register. Record this insn if the register is only used once | |
2839 | more and the equivalence value is the same as our source. | |
2840 | ||
2841 | The latter condition is checked for two reasons: First, it is an | |
2842 | indication that it may be more efficient to actually emit the insn | |
2843 | as written (if no registers are available, reload will substitute | |
2844 | the equivalence). Secondly, it avoids problems with any registers | |
2845 | dying in this insn whose death notes would be missed. | |
2846 | ||
2847 | If we don't have a REG_EQUIV note, see if this insn is loading | |
2848 | a register used only in one basic block from a MEM. If so, and the | |
2849 | MEM remains unchanged for the life of the register, add a REG_EQUIV | |
2850 | note. */ | |
2851 | ||
2852 | note = find_reg_note (insn, REG_EQUIV, NULL_RTX); | |
2853 | ||
2854 | if (note == 0 && REG_BASIC_BLOCK (regno) >= NUM_FIXED_BLOCKS | |
2855 | && MEM_P (SET_SRC (set)) | |
2856 | && validate_equiv_mem (insn, dest, SET_SRC (set))) | |
2857 | note = set_unique_reg_note (insn, REG_EQUIV, copy_rtx (SET_SRC (set))); | |
2858 | ||
2859 | if (note) | |
2860 | { | |
2861 | int regno = REGNO (dest); | |
2862 | rtx x = XEXP (note, 0); | |
2863 | ||
2864 | /* If we haven't done so, record for reload that this is an | |
2865 | equivalencing insn. */ | |
2866 | if (!reg_equiv[regno].is_arg_equivalence) | |
f2034d06 JL |
2867 | reg_equiv_init (regno) |
2868 | = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init (regno)); | |
2af2dbdc VM |
2869 | |
2870 | /* Record whether or not we created a REG_EQUIV note for a LABEL_REF. | |
2871 | We might end up substituting the LABEL_REF for uses of the | |
2872 | pseudo here or later. That kind of transformation may turn an | |
2873 | indirect jump into a direct jump, in which case we must rerun the | |
2874 | jump optimizer to ensure that the JUMP_LABEL fields are valid. */ | |
2875 | if (GET_CODE (x) == LABEL_REF | |
2876 | || (GET_CODE (x) == CONST | |
2877 | && GET_CODE (XEXP (x, 0)) == PLUS | |
2878 | && (GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF))) | |
2879 | recorded_label_ref = 1; | |
2880 | ||
2881 | reg_equiv[regno].replacement = x; | |
2882 | reg_equiv[regno].src_p = &SET_SRC (set); | |
2883 | reg_equiv[regno].loop_depth = loop_depth; | |
2884 | ||
2885 | /* Don't mess with things live during setjmp. */ | |
2886 | if (REG_LIVE_LENGTH (regno) >= 0 && optimize) | |
2887 | { | |
2888 | /* Note that the statement below does not affect the priority | |
2889 | in local-alloc! */ | |
2890 | REG_LIVE_LENGTH (regno) *= 2; | |
2891 | ||
2892 | /* If the register is referenced exactly twice, meaning it is | |
2893 | set once and used once, indicate that the reference may be | |
2894 | replaced by the equivalence we computed above. Do this | |
2895 | even if the register is only used in one block so that | |
2896 | dependencies can be handled where the last register is | |
2897 | used in a different block (i.e. HIGH / LO_SUM sequences) | |
2898 | and to reduce the number of registers alive across | |
2899 | calls. */ | |
2900 | ||
2901 | if (REG_N_REFS (regno) == 2 | |
2902 | && (rtx_equal_p (x, src) | |
2903 | || ! equiv_init_varies_p (src)) | |
2904 | && NONJUMP_INSN_P (insn) | |
2905 | && equiv_init_movable_p (PATTERN (insn), regno)) | |
2906 | reg_equiv[regno].replace = 1; | |
2907 | } | |
2908 | } | |
2909 | } | |
2910 | } | |
2911 | ||
2912 | if (!optimize) | |
2913 | goto out; | |
2914 | ||
2915 | /* A second pass, to gather additional equivalences with memory. This needs | |
2916 | to be done after we know which registers we are going to replace. */ | |
2917 | ||
2918 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
2919 | { | |
2920 | rtx set, src, dest; | |
2921 | unsigned regno; | |
2922 | ||
2923 | if (! INSN_P (insn)) | |
2924 | continue; | |
2925 | ||
2926 | set = single_set (insn); | |
2927 | if (! set) | |
2928 | continue; | |
2929 | ||
2930 | dest = SET_DEST (set); | |
2931 | src = SET_SRC (set); | |
2932 | ||
2933 | /* If this sets a MEM to the contents of a REG that is only used | |
2934 | in a single basic block, see if the register is always equivalent | |
2935 | to that memory location and if moving the store from INSN to the | |
2936 | insn that set REG is safe. If so, put a REG_EQUIV note on the | |
2937 | initializing insn. | |
2938 | ||
2939 | Don't add a REG_EQUIV note if the insn already has one. The existing | |
2940 | REG_EQUIV is likely more useful than the one we are adding. | |
2941 | ||
2942 | If one of the regs in the address has reg_equiv[REGNO].replace set, | |
2943 | then we can't add this REG_EQUIV note. The reg_equiv[REGNO].replace | |
2944 | optimization may move the set of this register immediately before | |
2945 | insn, which puts it after reg_equiv[REGNO].init_insns, and hence | |
2946 | the mention in the REG_EQUIV note would be to an uninitialized | |
2947 | pseudo. */ | |
2948 | ||
2949 | if (MEM_P (dest) && REG_P (src) | |
2950 | && (regno = REGNO (src)) >= FIRST_PSEUDO_REGISTER | |
2951 | && REG_BASIC_BLOCK (regno) >= NUM_FIXED_BLOCKS | |
2952 | && DF_REG_DEF_COUNT (regno) == 1 | |
2953 | && reg_equiv[regno].init_insns != 0 | |
2954 | && reg_equiv[regno].init_insns != const0_rtx | |
2955 | && ! find_reg_note (XEXP (reg_equiv[regno].init_insns, 0), | |
2956 | REG_EQUIV, NULL_RTX) | |
2957 | && ! contains_replace_regs (XEXP (dest, 0))) | |
2958 | { | |
2959 | rtx init_insn = XEXP (reg_equiv[regno].init_insns, 0); | |
2960 | if (validate_equiv_mem (init_insn, src, dest) | |
2961 | && ! memref_used_between_p (dest, init_insn, insn) | |
2962 | /* Attaching a REG_EQUIV note will fail if INIT_INSN has | |
2963 | multiple sets. */ | |
2964 | && set_unique_reg_note (init_insn, REG_EQUIV, copy_rtx (dest))) | |
2965 | { | |
2966 | /* This insn makes the equivalence, not the one initializing | |
2967 | the register. */ | |
f2034d06 | 2968 | reg_equiv_init (regno) |
2af2dbdc VM |
2969 | = gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX); |
2970 | df_notes_rescan (init_insn); | |
2971 | } | |
2972 | } | |
2973 | } | |
2974 | ||
2975 | cleared_regs = BITMAP_ALLOC (NULL); | |
2976 | /* Now scan all regs killed in an insn to see if any of them are | |
2977 | registers only used that once. If so, see if we can replace the | |
2978 | reference with the equivalent form. If we can, delete the | |
2979 | initializing reference and this register will go away. If we | |
2980 | can't replace the reference, and the initializing reference is | |
2981 | within the same loop (or in an inner loop), then move the register | |
2982 | initialization just before the use, so that they are in the same | |
2983 | basic block. */ | |
2984 | FOR_EACH_BB_REVERSE (bb) | |
2985 | { | |
2986 | loop_depth = bb->loop_depth; | |
2987 | for (insn = BB_END (bb); | |
2988 | insn != PREV_INSN (BB_HEAD (bb)); | |
2989 | insn = PREV_INSN (insn)) | |
2990 | { | |
2991 | rtx link; | |
2992 | ||
2993 | if (! INSN_P (insn)) | |
2994 | continue; | |
2995 | ||
2996 | /* Don't substitute into a non-local goto, this confuses CFG. */ | |
2997 | if (JUMP_P (insn) | |
2998 | && find_reg_note (insn, REG_NON_LOCAL_GOTO, NULL_RTX)) | |
2999 | continue; | |
3000 | ||
3001 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | |
3002 | { | |
3003 | if (REG_NOTE_KIND (link) == REG_DEAD | |
3004 | /* Make sure this insn still refers to the register. */ | |
3005 | && reg_mentioned_p (XEXP (link, 0), PATTERN (insn))) | |
3006 | { | |
3007 | int regno = REGNO (XEXP (link, 0)); | |
3008 | rtx equiv_insn; | |
3009 | ||
3010 | if (! reg_equiv[regno].replace | |
0cad4827 VM |
3011 | || reg_equiv[regno].loop_depth < loop_depth |
3012 | /* There is no sense to move insns if we did | |
3013 | register pressure-sensitive scheduling was | |
3014 | done because it will not improve allocation | |
3015 | but worsen insn schedule with a big | |
3016 | probability. */ | |
3017 | || (flag_sched_pressure && flag_schedule_insns)) | |
2af2dbdc VM |
3018 | continue; |
3019 | ||
3020 | /* reg_equiv[REGNO].replace gets set only when | |
3021 | REG_N_REFS[REGNO] is 2, i.e. the register is set | |
3022 | once and used once. (If it were only set, but not used, | |
3023 | flow would have deleted the setting insns.) Hence | |
3024 | there can only be one insn in reg_equiv[REGNO].init_insns. */ | |
3025 | gcc_assert (reg_equiv[regno].init_insns | |
3026 | && !XEXP (reg_equiv[regno].init_insns, 1)); | |
3027 | equiv_insn = XEXP (reg_equiv[regno].init_insns, 0); | |
3028 | ||
3029 | /* We may not move instructions that can throw, since | |
3030 | that changes basic block boundaries and we are not | |
3031 | prepared to adjust the CFG to match. */ | |
3032 | if (can_throw_internal (equiv_insn)) | |
3033 | continue; | |
3034 | ||
3035 | if (asm_noperands (PATTERN (equiv_insn)) < 0 | |
3036 | && validate_replace_rtx (regno_reg_rtx[regno], | |
3037 | *(reg_equiv[regno].src_p), insn)) | |
3038 | { | |
3039 | rtx equiv_link; | |
3040 | rtx last_link; | |
3041 | rtx note; | |
3042 | ||
3043 | /* Find the last note. */ | |
3044 | for (last_link = link; XEXP (last_link, 1); | |
3045 | last_link = XEXP (last_link, 1)) | |
3046 | ; | |
3047 | ||
3048 | /* Append the REG_DEAD notes from equiv_insn. */ | |
3049 | equiv_link = REG_NOTES (equiv_insn); | |
3050 | while (equiv_link) | |
3051 | { | |
3052 | note = equiv_link; | |
3053 | equiv_link = XEXP (equiv_link, 1); | |
3054 | if (REG_NOTE_KIND (note) == REG_DEAD) | |
3055 | { | |
3056 | remove_note (equiv_insn, note); | |
3057 | XEXP (last_link, 1) = note; | |
3058 | XEXP (note, 1) = NULL_RTX; | |
3059 | last_link = note; | |
3060 | } | |
3061 | } | |
3062 | ||
3063 | remove_death (regno, insn); | |
3064 | SET_REG_N_REFS (regno, 0); | |
3065 | REG_FREQ (regno) = 0; | |
3066 | delete_insn (equiv_insn); | |
3067 | ||
3068 | reg_equiv[regno].init_insns | |
3069 | = XEXP (reg_equiv[regno].init_insns, 1); | |
3070 | ||
f2034d06 | 3071 | reg_equiv_init (regno) = NULL_RTX; |
2af2dbdc VM |
3072 | bitmap_set_bit (cleared_regs, regno); |
3073 | } | |
3074 | /* Move the initialization of the register to just before | |
3075 | INSN. Update the flow information. */ | |
b5b8b0ac | 3076 | else if (prev_nondebug_insn (insn) != equiv_insn) |
2af2dbdc VM |
3077 | { |
3078 | rtx new_insn; | |
3079 | ||
3080 | new_insn = emit_insn_before (PATTERN (equiv_insn), insn); | |
3081 | REG_NOTES (new_insn) = REG_NOTES (equiv_insn); | |
3082 | REG_NOTES (equiv_insn) = 0; | |
3083 | /* Rescan it to process the notes. */ | |
3084 | df_insn_rescan (new_insn); | |
3085 | ||
3086 | /* Make sure this insn is recognized before | |
3087 | reload begins, otherwise | |
3088 | eliminate_regs_in_insn will die. */ | |
3089 | INSN_CODE (new_insn) = INSN_CODE (equiv_insn); | |
3090 | ||
3091 | delete_insn (equiv_insn); | |
3092 | ||
3093 | XEXP (reg_equiv[regno].init_insns, 0) = new_insn; | |
3094 | ||
3095 | REG_BASIC_BLOCK (regno) = bb->index; | |
3096 | REG_N_CALLS_CROSSED (regno) = 0; | |
3097 | REG_FREQ_CALLS_CROSSED (regno) = 0; | |
3098 | REG_N_THROWING_CALLS_CROSSED (regno) = 0; | |
3099 | REG_LIVE_LENGTH (regno) = 2; | |
3100 | ||
3101 | if (insn == BB_HEAD (bb)) | |
3102 | BB_HEAD (bb) = PREV_INSN (insn); | |
3103 | ||
f2034d06 | 3104 | reg_equiv_init (regno) |
2af2dbdc VM |
3105 | = gen_rtx_INSN_LIST (VOIDmode, new_insn, NULL_RTX); |
3106 | bitmap_set_bit (cleared_regs, regno); | |
3107 | } | |
3108 | } | |
3109 | } | |
3110 | } | |
3111 | } | |
3112 | ||
3113 | if (!bitmap_empty_p (cleared_regs)) | |
3a6191b1 JJ |
3114 | { |
3115 | FOR_EACH_BB (bb) | |
3116 | { | |
3117 | bitmap_and_compl_into (DF_LIVE_IN (bb), cleared_regs); | |
3118 | bitmap_and_compl_into (DF_LIVE_OUT (bb), cleared_regs); | |
3119 | bitmap_and_compl_into (DF_LR_IN (bb), cleared_regs); | |
3120 | bitmap_and_compl_into (DF_LR_OUT (bb), cleared_regs); | |
3121 | } | |
3122 | ||
3123 | /* Last pass - adjust debug insns referencing cleared regs. */ | |
3124 | if (MAY_HAVE_DEBUG_INSNS) | |
3125 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
3126 | if (DEBUG_INSN_P (insn)) | |
3127 | { | |
3128 | rtx old_loc = INSN_VAR_LOCATION_LOC (insn); | |
3129 | INSN_VAR_LOCATION_LOC (insn) | |
3130 | = simplify_replace_fn_rtx (old_loc, NULL_RTX, | |
3131 | adjust_cleared_regs, | |
3132 | (void *) cleared_regs); | |
3133 | if (old_loc != INSN_VAR_LOCATION_LOC (insn)) | |
3134 | df_insn_rescan (insn); | |
3135 | } | |
3136 | } | |
2af2dbdc VM |
3137 | |
3138 | BITMAP_FREE (cleared_regs); | |
3139 | ||
3140 | out: | |
3141 | /* Clean up. */ | |
3142 | ||
3143 | end_alias_analysis (); | |
3144 | free (reg_equiv); | |
3145 | return recorded_label_ref; | |
3146 | } | |
3147 | ||
3148 | \f | |
3149 | ||
3150 | /* Print chain C to FILE. */ | |
3151 | static void | |
3152 | print_insn_chain (FILE *file, struct insn_chain *c) | |
3153 | { | |
3154 | fprintf (file, "insn=%d, ", INSN_UID(c->insn)); | |
3155 | bitmap_print (file, &c->live_throughout, "live_throughout: ", ", "); | |
3156 | bitmap_print (file, &c->dead_or_set, "dead_or_set: ", "\n"); | |
3157 | } | |
3158 | ||
3159 | ||
3160 | /* Print all reload_insn_chains to FILE. */ | |
3161 | static void | |
3162 | print_insn_chains (FILE *file) | |
3163 | { | |
3164 | struct insn_chain *c; | |
3165 | for (c = reload_insn_chain; c ; c = c->next) | |
3166 | print_insn_chain (file, c); | |
3167 | } | |
3168 | ||
3169 | /* Return true if pseudo REGNO should be added to set live_throughout | |
3170 | or dead_or_set of the insn chains for reload consideration. */ | |
3171 | static bool | |
3172 | pseudo_for_reload_consideration_p (int regno) | |
3173 | { | |
3174 | /* Consider spilled pseudos too for IRA because they still have a | |
3175 | chance to get hard-registers in the reload when IRA is used. */ | |
b100151b | 3176 | return (reg_renumber[regno] >= 0 || ira_conflicts_p); |
2af2dbdc VM |
3177 | } |
3178 | ||
3179 | /* Init LIVE_SUBREGS[ALLOCNUM] and LIVE_SUBREGS_USED[ALLOCNUM] using | |
3180 | REG to the number of nregs, and INIT_VALUE to get the | |
3181 | initialization. ALLOCNUM need not be the regno of REG. */ | |
3182 | static void | |
3183 | init_live_subregs (bool init_value, sbitmap *live_subregs, | |
3184 | int *live_subregs_used, int allocnum, rtx reg) | |
3185 | { | |
3186 | unsigned int regno = REGNO (SUBREG_REG (reg)); | |
3187 | int size = GET_MODE_SIZE (GET_MODE (regno_reg_rtx[regno])); | |
3188 | ||
3189 | gcc_assert (size > 0); | |
3190 | ||
3191 | /* Been there, done that. */ | |
3192 | if (live_subregs_used[allocnum]) | |
3193 | return; | |
3194 | ||
3195 | /* Create a new one with zeros. */ | |
3196 | if (live_subregs[allocnum] == NULL) | |
3197 | live_subregs[allocnum] = sbitmap_alloc (size); | |
3198 | ||
3199 | /* If the entire reg was live before blasting into subregs, we need | |
3200 | to init all of the subregs to ones else init to 0. */ | |
3201 | if (init_value) | |
3202 | sbitmap_ones (live_subregs[allocnum]); | |
b8698a0f | 3203 | else |
2af2dbdc VM |
3204 | sbitmap_zero (live_subregs[allocnum]); |
3205 | ||
3206 | /* Set the number of bits that we really want. */ | |
3207 | live_subregs_used[allocnum] = size; | |
3208 | } | |
3209 | ||
3210 | /* Walk the insns of the current function and build reload_insn_chain, | |
3211 | and record register life information. */ | |
3212 | static void | |
3213 | build_insn_chain (void) | |
3214 | { | |
3215 | unsigned int i; | |
3216 | struct insn_chain **p = &reload_insn_chain; | |
3217 | basic_block bb; | |
3218 | struct insn_chain *c = NULL; | |
3219 | struct insn_chain *next = NULL; | |
3220 | bitmap live_relevant_regs = BITMAP_ALLOC (NULL); | |
3221 | bitmap elim_regset = BITMAP_ALLOC (NULL); | |
3222 | /* live_subregs is a vector used to keep accurate information about | |
3223 | which hardregs are live in multiword pseudos. live_subregs and | |
3224 | live_subregs_used are indexed by pseudo number. The live_subreg | |
3225 | entry for a particular pseudo is only used if the corresponding | |
3226 | element is non zero in live_subregs_used. The value in | |
3227 | live_subregs_used is number of bytes that the pseudo can | |
3228 | occupy. */ | |
3229 | sbitmap *live_subregs = XCNEWVEC (sbitmap, max_regno); | |
3230 | int *live_subregs_used = XNEWVEC (int, max_regno); | |
3231 | ||
3232 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
3233 | if (TEST_HARD_REG_BIT (eliminable_regset, i)) | |
3234 | bitmap_set_bit (elim_regset, i); | |
3235 | FOR_EACH_BB_REVERSE (bb) | |
3236 | { | |
3237 | bitmap_iterator bi; | |
3238 | rtx insn; | |
b8698a0f | 3239 | |
2af2dbdc VM |
3240 | CLEAR_REG_SET (live_relevant_regs); |
3241 | memset (live_subregs_used, 0, max_regno * sizeof (int)); | |
b8698a0f | 3242 | |
54a0ac2d | 3243 | EXECUTE_IF_SET_IN_BITMAP (DF_LR_OUT (bb), 0, i, bi) |
2af2dbdc VM |
3244 | { |
3245 | if (i >= FIRST_PSEUDO_REGISTER) | |
3246 | break; | |
3247 | bitmap_set_bit (live_relevant_regs, i); | |
3248 | } | |
3249 | ||
54a0ac2d | 3250 | EXECUTE_IF_SET_IN_BITMAP (DF_LR_OUT (bb), |
2af2dbdc VM |
3251 | FIRST_PSEUDO_REGISTER, i, bi) |
3252 | { | |
3253 | if (pseudo_for_reload_consideration_p (i)) | |
3254 | bitmap_set_bit (live_relevant_regs, i); | |
3255 | } | |
3256 | ||
3257 | FOR_BB_INSNS_REVERSE (bb, insn) | |
3258 | { | |
3259 | if (!NOTE_P (insn) && !BARRIER_P (insn)) | |
3260 | { | |
3261 | unsigned int uid = INSN_UID (insn); | |
3262 | df_ref *def_rec; | |
3263 | df_ref *use_rec; | |
3264 | ||
3265 | c = new_insn_chain (); | |
3266 | c->next = next; | |
3267 | next = c; | |
3268 | *p = c; | |
3269 | p = &c->prev; | |
b8698a0f | 3270 | |
2af2dbdc VM |
3271 | c->insn = insn; |
3272 | c->block = bb->index; | |
3273 | ||
3274 | if (INSN_P (insn)) | |
3275 | for (def_rec = DF_INSN_UID_DEFS (uid); *def_rec; def_rec++) | |
3276 | { | |
3277 | df_ref def = *def_rec; | |
3278 | unsigned int regno = DF_REF_REGNO (def); | |
b8698a0f | 3279 | |
2af2dbdc VM |
3280 | /* Ignore may clobbers because these are generated |
3281 | from calls. However, every other kind of def is | |
3282 | added to dead_or_set. */ | |
3283 | if (!DF_REF_FLAGS_IS_SET (def, DF_REF_MAY_CLOBBER)) | |
3284 | { | |
3285 | if (regno < FIRST_PSEUDO_REGISTER) | |
3286 | { | |
3287 | if (!fixed_regs[regno]) | |
3288 | bitmap_set_bit (&c->dead_or_set, regno); | |
3289 | } | |
3290 | else if (pseudo_for_reload_consideration_p (regno)) | |
3291 | bitmap_set_bit (&c->dead_or_set, regno); | |
3292 | } | |
3293 | ||
3294 | if ((regno < FIRST_PSEUDO_REGISTER | |
3295 | || reg_renumber[regno] >= 0 | |
3296 | || ira_conflicts_p) | |
3297 | && (!DF_REF_FLAGS_IS_SET (def, DF_REF_CONDITIONAL))) | |
3298 | { | |
3299 | rtx reg = DF_REF_REG (def); | |
3300 | ||
3301 | /* We can model subregs, but not if they are | |
3302 | wrapped in ZERO_EXTRACTS. */ | |
3303 | if (GET_CODE (reg) == SUBREG | |
3304 | && !DF_REF_FLAGS_IS_SET (def, DF_REF_ZERO_EXTRACT)) | |
3305 | { | |
3306 | unsigned int start = SUBREG_BYTE (reg); | |
b8698a0f | 3307 | unsigned int last = start |
2af2dbdc VM |
3308 | + GET_MODE_SIZE (GET_MODE (reg)); |
3309 | ||
3310 | init_live_subregs | |
b8698a0f | 3311 | (bitmap_bit_p (live_relevant_regs, regno), |
2af2dbdc VM |
3312 | live_subregs, live_subregs_used, regno, reg); |
3313 | ||
3314 | if (!DF_REF_FLAGS_IS_SET | |
3315 | (def, DF_REF_STRICT_LOW_PART)) | |
3316 | { | |
3317 | /* Expand the range to cover entire words. | |
3318 | Bytes added here are "don't care". */ | |
3319 | start | |
3320 | = start / UNITS_PER_WORD * UNITS_PER_WORD; | |
3321 | last = ((last + UNITS_PER_WORD - 1) | |
3322 | / UNITS_PER_WORD * UNITS_PER_WORD); | |
3323 | } | |
3324 | ||
3325 | /* Ignore the paradoxical bits. */ | |
3326 | if ((int)last > live_subregs_used[regno]) | |
3327 | last = live_subregs_used[regno]; | |
3328 | ||
3329 | while (start < last) | |
3330 | { | |
3331 | RESET_BIT (live_subregs[regno], start); | |
3332 | start++; | |
3333 | } | |
b8698a0f | 3334 | |
2af2dbdc VM |
3335 | if (sbitmap_empty_p (live_subregs[regno])) |
3336 | { | |
3337 | live_subregs_used[regno] = 0; | |
3338 | bitmap_clear_bit (live_relevant_regs, regno); | |
3339 | } | |
3340 | else | |
3341 | /* Set live_relevant_regs here because | |
3342 | that bit has to be true to get us to | |
3343 | look at the live_subregs fields. */ | |
3344 | bitmap_set_bit (live_relevant_regs, regno); | |
3345 | } | |
3346 | else | |
3347 | { | |
3348 | /* DF_REF_PARTIAL is generated for | |
3349 | subregs, STRICT_LOW_PART, and | |
3350 | ZERO_EXTRACT. We handle the subreg | |
3351 | case above so here we have to keep from | |
3352 | modeling the def as a killing def. */ | |
3353 | if (!DF_REF_FLAGS_IS_SET (def, DF_REF_PARTIAL)) | |
3354 | { | |
3355 | bitmap_clear_bit (live_relevant_regs, regno); | |
3356 | live_subregs_used[regno] = 0; | |
3357 | } | |
3358 | } | |
3359 | } | |
3360 | } | |
b8698a0f | 3361 | |
2af2dbdc VM |
3362 | bitmap_and_compl_into (live_relevant_regs, elim_regset); |
3363 | bitmap_copy (&c->live_throughout, live_relevant_regs); | |
3364 | ||
3365 | if (INSN_P (insn)) | |
3366 | for (use_rec = DF_INSN_UID_USES (uid); *use_rec; use_rec++) | |
3367 | { | |
3368 | df_ref use = *use_rec; | |
3369 | unsigned int regno = DF_REF_REGNO (use); | |
3370 | rtx reg = DF_REF_REG (use); | |
b8698a0f | 3371 | |
2af2dbdc VM |
3372 | /* DF_REF_READ_WRITE on a use means that this use |
3373 | is fabricated from a def that is a partial set | |
3374 | to a multiword reg. Here, we only model the | |
3375 | subreg case that is not wrapped in ZERO_EXTRACT | |
3376 | precisely so we do not need to look at the | |
3377 | fabricated use. */ | |
b8698a0f L |
3378 | if (DF_REF_FLAGS_IS_SET (use, DF_REF_READ_WRITE) |
3379 | && !DF_REF_FLAGS_IS_SET (use, DF_REF_ZERO_EXTRACT) | |
2af2dbdc VM |
3380 | && DF_REF_FLAGS_IS_SET (use, DF_REF_SUBREG)) |
3381 | continue; | |
b8698a0f | 3382 | |
2af2dbdc VM |
3383 | /* Add the last use of each var to dead_or_set. */ |
3384 | if (!bitmap_bit_p (live_relevant_regs, regno)) | |
3385 | { | |
3386 | if (regno < FIRST_PSEUDO_REGISTER) | |
3387 | { | |
3388 | if (!fixed_regs[regno]) | |
3389 | bitmap_set_bit (&c->dead_or_set, regno); | |
3390 | } | |
3391 | else if (pseudo_for_reload_consideration_p (regno)) | |
3392 | bitmap_set_bit (&c->dead_or_set, regno); | |
3393 | } | |
b8698a0f | 3394 | |
2af2dbdc VM |
3395 | if (regno < FIRST_PSEUDO_REGISTER |
3396 | || pseudo_for_reload_consideration_p (regno)) | |
3397 | { | |
3398 | if (GET_CODE (reg) == SUBREG | |
3399 | && !DF_REF_FLAGS_IS_SET (use, | |
3400 | DF_REF_SIGN_EXTRACT | |
b8698a0f | 3401 | | DF_REF_ZERO_EXTRACT)) |
2af2dbdc VM |
3402 | { |
3403 | unsigned int start = SUBREG_BYTE (reg); | |
b8698a0f | 3404 | unsigned int last = start |
2af2dbdc | 3405 | + GET_MODE_SIZE (GET_MODE (reg)); |
b8698a0f | 3406 | |
2af2dbdc | 3407 | init_live_subregs |
b8698a0f | 3408 | (bitmap_bit_p (live_relevant_regs, regno), |
2af2dbdc | 3409 | live_subregs, live_subregs_used, regno, reg); |
b8698a0f | 3410 | |
2af2dbdc VM |
3411 | /* Ignore the paradoxical bits. */ |
3412 | if ((int)last > live_subregs_used[regno]) | |
3413 | last = live_subregs_used[regno]; | |
3414 | ||
3415 | while (start < last) | |
3416 | { | |
3417 | SET_BIT (live_subregs[regno], start); | |
3418 | start++; | |
3419 | } | |
3420 | } | |
3421 | else | |
3422 | /* Resetting the live_subregs_used is | |
3423 | effectively saying do not use the subregs | |
3424 | because we are reading the whole | |
3425 | pseudo. */ | |
3426 | live_subregs_used[regno] = 0; | |
3427 | bitmap_set_bit (live_relevant_regs, regno); | |
3428 | } | |
3429 | } | |
3430 | } | |
3431 | } | |
3432 | ||
3433 | /* FIXME!! The following code is a disaster. Reload needs to see the | |
3434 | labels and jump tables that are just hanging out in between | |
3435 | the basic blocks. See pr33676. */ | |
3436 | insn = BB_HEAD (bb); | |
b8698a0f | 3437 | |
2af2dbdc | 3438 | /* Skip over the barriers and cruft. */ |
b8698a0f | 3439 | while (insn && (BARRIER_P (insn) || NOTE_P (insn) |
2af2dbdc VM |
3440 | || BLOCK_FOR_INSN (insn) == bb)) |
3441 | insn = PREV_INSN (insn); | |
b8698a0f | 3442 | |
2af2dbdc VM |
3443 | /* While we add anything except barriers and notes, the focus is |
3444 | to get the labels and jump tables into the | |
3445 | reload_insn_chain. */ | |
3446 | while (insn) | |
3447 | { | |
3448 | if (!NOTE_P (insn) && !BARRIER_P (insn)) | |
3449 | { | |
3450 | if (BLOCK_FOR_INSN (insn)) | |
3451 | break; | |
b8698a0f | 3452 | |
2af2dbdc VM |
3453 | c = new_insn_chain (); |
3454 | c->next = next; | |
3455 | next = c; | |
3456 | *p = c; | |
3457 | p = &c->prev; | |
b8698a0f | 3458 | |
2af2dbdc VM |
3459 | /* The block makes no sense here, but it is what the old |
3460 | code did. */ | |
3461 | c->block = bb->index; | |
3462 | c->insn = insn; | |
3463 | bitmap_copy (&c->live_throughout, live_relevant_regs); | |
b8698a0f | 3464 | } |
2af2dbdc VM |
3465 | insn = PREV_INSN (insn); |
3466 | } | |
3467 | } | |
3468 | ||
3469 | for (i = 0; i < (unsigned int) max_regno; i++) | |
3470 | if (live_subregs[i]) | |
3471 | free (live_subregs[i]); | |
3472 | ||
3473 | reload_insn_chain = c; | |
3474 | *p = NULL; | |
3475 | ||
3476 | free (live_subregs); | |
3477 | free (live_subregs_used); | |
3478 | BITMAP_FREE (live_relevant_regs); | |
3479 | BITMAP_FREE (elim_regset); | |
3480 | ||
3481 | if (dump_file) | |
3482 | print_insn_chains (dump_file); | |
3483 | } | |
8ff49c29 | 3484 | |
f2034d06 | 3485 | \f |
2af2dbdc | 3486 | |
058e97ec VM |
3487 | /* All natural loops. */ |
3488 | struct loops ira_loops; | |
3489 | ||
311aab06 VM |
3490 | /* True if we have allocno conflicts. It is false for non-optimized |
3491 | mode or when the conflict table is too big. */ | |
3492 | bool ira_conflicts_p; | |
3493 | ||
058e97ec VM |
3494 | /* This is the main entry of IRA. */ |
3495 | static void | |
3496 | ira (FILE *f) | |
3497 | { | |
3498 | int overall_cost_before, allocated_reg_info_size; | |
3499 | bool loops_p; | |
3500 | int max_regno_before_ira, ira_max_point_before_emit; | |
3501 | int rebuild_p; | |
3553f0bb | 3502 | int saved_flag_ira_share_spill_slots; |
058e97ec VM |
3503 | basic_block bb; |
3504 | ||
3505 | timevar_push (TV_IRA); | |
3506 | ||
dc12b70e JZ |
3507 | if (flag_caller_saves) |
3508 | init_caller_save (); | |
3509 | ||
058e97ec VM |
3510 | if (flag_ira_verbose < 10) |
3511 | { | |
3512 | internal_flag_ira_verbose = flag_ira_verbose; | |
3513 | ira_dump_file = f; | |
3514 | } | |
3515 | else | |
3516 | { | |
3517 | internal_flag_ira_verbose = flag_ira_verbose - 10; | |
3518 | ira_dump_file = stderr; | |
3519 | } | |
3520 | ||
311aab06 | 3521 | ira_conflicts_p = optimize > 0; |
058e97ec VM |
3522 | setup_prohibited_mode_move_regs (); |
3523 | ||
3524 | df_note_add_problem (); | |
3525 | ||
3526 | if (optimize == 1) | |
3527 | { | |
3528 | df_live_add_problem (); | |
3529 | df_live_set_all_dirty (); | |
3530 | } | |
3531 | #ifdef ENABLE_CHECKING | |
3532 | df->changeable_flags |= DF_VERIFY_SCHEDULED; | |
3533 | #endif | |
3534 | df_analyze (); | |
3535 | df_clear_flags (DF_NO_INSN_RESCAN); | |
3536 | regstat_init_n_sets_and_refs (); | |
3537 | regstat_compute_ri (); | |
3538 | ||
3539 | /* If we are not optimizing, then this is the only place before | |
3540 | register allocation where dataflow is done. And that is needed | |
3541 | to generate these warnings. */ | |
3542 | if (warn_clobbered) | |
3543 | generate_setjmp_warnings (); | |
3544 | ||
ace984c8 RS |
3545 | /* Determine if the current function is a leaf before running IRA |
3546 | since this can impact optimizations done by the prologue and | |
3547 | epilogue thus changing register elimination offsets. */ | |
3548 | current_function_is_leaf = leaf_function_p (); | |
3549 | ||
1833192f VM |
3550 | if (resize_reg_info () && flag_ira_loop_pressure) |
3551 | ira_set_pseudo_classes (ira_dump_file); | |
3552 | ||
058e97ec VM |
3553 | rebuild_p = update_equiv_regs (); |
3554 | ||
3555 | #ifndef IRA_NO_OBSTACK | |
3556 | gcc_obstack_init (&ira_obstack); | |
3557 | #endif | |
3558 | bitmap_obstack_initialize (&ira_bitmap_obstack); | |
3559 | if (optimize) | |
b8698a0f | 3560 | { |
058e97ec VM |
3561 | max_regno = max_reg_num (); |
3562 | ira_reg_equiv_len = max_regno; | |
3563 | ira_reg_equiv_invariant_p | |
3564 | = (bool *) ira_allocate (max_regno * sizeof (bool)); | |
3565 | memset (ira_reg_equiv_invariant_p, 0, max_regno * sizeof (bool)); | |
3566 | ira_reg_equiv_const = (rtx *) ira_allocate (max_regno * sizeof (rtx)); | |
3567 | memset (ira_reg_equiv_const, 0, max_regno * sizeof (rtx)); | |
3568 | find_reg_equiv_invariant_const (); | |
3569 | if (rebuild_p) | |
3570 | { | |
3571 | timevar_push (TV_JUMP); | |
3572 | rebuild_jump_labels (get_insns ()); | |
59db109a SB |
3573 | if (purge_all_dead_edges ()) |
3574 | delete_unreachable_blocks (); | |
058e97ec VM |
3575 | timevar_pop (TV_JUMP); |
3576 | } | |
3577 | } | |
3578 | ||
3579 | max_regno_before_ira = allocated_reg_info_size = max_reg_num (); | |
ce18efcb | 3580 | ira_setup_eliminable_regset (); |
b8698a0f | 3581 | |
058e97ec VM |
3582 | ira_overall_cost = ira_reg_cost = ira_mem_cost = 0; |
3583 | ira_load_cost = ira_store_cost = ira_shuffle_cost = 0; | |
3584 | ira_move_loops_num = ira_additional_jumps_num = 0; | |
b8698a0f | 3585 | |
058e97ec VM |
3586 | ira_assert (current_loops == NULL); |
3587 | flow_loops_find (&ira_loops); | |
6744a6ab | 3588 | record_loop_exits (); |
058e97ec | 3589 | current_loops = &ira_loops; |
b8698a0f | 3590 | |
058e97ec VM |
3591 | if (internal_flag_ira_verbose > 0 && ira_dump_file != NULL) |
3592 | fprintf (ira_dump_file, "Building IRA IR\n"); | |
3593 | loops_p = ira_build (optimize | |
7db7ed3c VM |
3594 | && (flag_ira_region == IRA_REGION_ALL |
3595 | || flag_ira_region == IRA_REGION_MIXED)); | |
b8698a0f | 3596 | |
311aab06 | 3597 | ira_assert (ira_conflicts_p || !loops_p); |
3553f0bb VM |
3598 | |
3599 | saved_flag_ira_share_spill_slots = flag_ira_share_spill_slots; | |
de8e52f0 | 3600 | if (too_high_register_pressure_p () || cfun->calls_setjmp) |
3553f0bb | 3601 | /* It is just wasting compiler's time to pack spilled pseudos into |
de8e52f0 VM |
3602 | stack slots in this case -- prohibit it. We also do this if |
3603 | there is setjmp call because a variable not modified between | |
3604 | setjmp and longjmp the compiler is required to preserve its | |
3605 | value and sharing slots does not guarantee it. */ | |
3553f0bb VM |
3606 | flag_ira_share_spill_slots = FALSE; |
3607 | ||
cb1ca6ac | 3608 | ira_color (); |
b8698a0f | 3609 | |
058e97ec | 3610 | ira_max_point_before_emit = ira_max_point; |
b8698a0f | 3611 | |
1756cb66 VM |
3612 | ira_initiate_emit_data (); |
3613 | ||
058e97ec | 3614 | ira_emit (loops_p); |
b8698a0f | 3615 | |
311aab06 | 3616 | if (ira_conflicts_p) |
058e97ec VM |
3617 | { |
3618 | max_regno = max_reg_num (); | |
b8698a0f | 3619 | |
058e97ec VM |
3620 | if (! loops_p) |
3621 | ira_initiate_assign (); | |
3622 | else | |
3623 | { | |
3624 | expand_reg_info (allocated_reg_info_size); | |
3625 | setup_preferred_alternate_classes_for_new_pseudos | |
3626 | (allocated_reg_info_size); | |
3627 | allocated_reg_info_size = max_regno; | |
b8698a0f | 3628 | |
058e97ec VM |
3629 | if (internal_flag_ira_verbose > 0 && ira_dump_file != NULL) |
3630 | fprintf (ira_dump_file, "Flattening IR\n"); | |
3631 | ira_flattening (max_regno_before_ira, ira_max_point_before_emit); | |
3632 | /* New insns were generated: add notes and recalculate live | |
3633 | info. */ | |
3634 | df_analyze (); | |
b8698a0f | 3635 | |
058e97ec | 3636 | flow_loops_find (&ira_loops); |
6744a6ab | 3637 | record_loop_exits (); |
058e97ec VM |
3638 | current_loops = &ira_loops; |
3639 | ||
3640 | setup_allocno_assignment_flags (); | |
3641 | ira_initiate_assign (); | |
3642 | ira_reassign_conflict_allocnos (max_regno); | |
3643 | } | |
3644 | } | |
3645 | ||
1756cb66 VM |
3646 | ira_finish_emit_data (); |
3647 | ||
058e97ec | 3648 | setup_reg_renumber (); |
b8698a0f | 3649 | |
058e97ec | 3650 | calculate_allocation_cost (); |
b8698a0f | 3651 | |
058e97ec | 3652 | #ifdef ENABLE_IRA_CHECKING |
311aab06 | 3653 | if (ira_conflicts_p) |
058e97ec VM |
3654 | check_allocation (); |
3655 | #endif | |
b8698a0f | 3656 | |
530a4800 JJ |
3657 | if (delete_trivially_dead_insns (get_insns (), max_reg_num ())) |
3658 | df_analyze (); | |
b8698a0f | 3659 | |
f2034d06 | 3660 | grow_reg_equivs (); |
058e97ec VM |
3661 | |
3662 | if (max_regno != max_regno_before_ira) | |
3663 | { | |
3664 | regstat_free_n_sets_and_refs (); | |
3665 | regstat_free_ri (); | |
3666 | regstat_init_n_sets_and_refs (); | |
3667 | regstat_compute_ri (); | |
3668 | } | |
3669 | ||
f2034d06 | 3670 | allocate_initial_values (reg_equivs); |
058e97ec VM |
3671 | |
3672 | overall_cost_before = ira_overall_cost; | |
311aab06 | 3673 | if (ira_conflicts_p) |
058e97ec VM |
3674 | { |
3675 | fix_reg_equiv_init (); | |
b8698a0f | 3676 | |
058e97ec VM |
3677 | #ifdef ENABLE_IRA_CHECKING |
3678 | print_redundant_copies (); | |
3679 | #endif | |
3680 | ||
3681 | ira_spilled_reg_stack_slots_num = 0; | |
3682 | ira_spilled_reg_stack_slots | |
3683 | = ((struct ira_spilled_reg_stack_slot *) | |
3684 | ira_allocate (max_regno | |
3685 | * sizeof (struct ira_spilled_reg_stack_slot))); | |
3686 | memset (ira_spilled_reg_stack_slots, 0, | |
3687 | max_regno * sizeof (struct ira_spilled_reg_stack_slot)); | |
3688 | } | |
b8698a0f | 3689 | |
058e97ec VM |
3690 | timevar_pop (TV_IRA); |
3691 | ||
3692 | timevar_push (TV_RELOAD); | |
3693 | df_set_flags (DF_NO_INSN_RESCAN); | |
3694 | build_insn_chain (); | |
3695 | ||
311aab06 | 3696 | reload_completed = !reload (get_insns (), ira_conflicts_p); |
058e97ec VM |
3697 | |
3698 | timevar_pop (TV_RELOAD); | |
3699 | ||
3700 | timevar_push (TV_IRA); | |
3701 | ||
311aab06 | 3702 | if (ira_conflicts_p) |
058e97ec VM |
3703 | { |
3704 | ira_free (ira_spilled_reg_stack_slots); | |
b8698a0f | 3705 | |
058e97ec | 3706 | ira_finish_assign (); |
b8698a0f L |
3707 | |
3708 | } | |
058e97ec VM |
3709 | if (internal_flag_ira_verbose > 0 && ira_dump_file != NULL |
3710 | && overall_cost_before != ira_overall_cost) | |
3711 | fprintf (ira_dump_file, "+++Overall after reload %d\n", ira_overall_cost); | |
3712 | ira_destroy (); | |
b8698a0f | 3713 | |
3553f0bb VM |
3714 | flag_ira_share_spill_slots = saved_flag_ira_share_spill_slots; |
3715 | ||
058e97ec VM |
3716 | flow_loops_free (&ira_loops); |
3717 | free_dominance_info (CDI_DOMINATORS); | |
3718 | FOR_ALL_BB (bb) | |
3719 | bb->loop_father = NULL; | |
3720 | current_loops = NULL; | |
3721 | ||
058e97ec VM |
3722 | regstat_free_ri (); |
3723 | regstat_free_n_sets_and_refs (); | |
b8698a0f | 3724 | |
058e97ec VM |
3725 | if (optimize) |
3726 | { | |
3727 | cleanup_cfg (CLEANUP_EXPENSIVE); | |
b8698a0f | 3728 | |
058e97ec VM |
3729 | ira_free (ira_reg_equiv_invariant_p); |
3730 | ira_free (ira_reg_equiv_const); | |
3731 | } | |
3732 | ||
3733 | bitmap_obstack_release (&ira_bitmap_obstack); | |
3734 | #ifndef IRA_NO_OBSTACK | |
3735 | obstack_free (&ira_obstack, NULL); | |
3736 | #endif | |
3737 | ||
3738 | /* The code after the reload has changed so much that at this point | |
3739 | we might as well just rescan everything. Not that | |
3740 | df_rescan_all_insns is not going to help here because it does not | |
3741 | touch the artificial uses and defs. */ | |
3742 | df_finish_pass (true); | |
3743 | if (optimize > 1) | |
3744 | df_live_add_problem (); | |
3745 | df_scan_alloc (NULL); | |
3746 | df_scan_blocks (); | |
3747 | ||
3748 | if (optimize) | |
3749 | df_analyze (); | |
3750 | ||
3751 | timevar_pop (TV_IRA); | |
3752 | } | |
3753 | ||
3754 | \f | |
3755 | ||
3756 | static bool | |
3757 | gate_ira (void) | |
3758 | { | |
2af2dbdc | 3759 | return true; |
058e97ec VM |
3760 | } |
3761 | ||
3762 | /* Run the integrated register allocator. */ | |
3763 | static unsigned int | |
3764 | rest_of_handle_ira (void) | |
3765 | { | |
3766 | ira (dump_file); | |
3767 | return 0; | |
3768 | } | |
3769 | ||
3770 | struct rtl_opt_pass pass_ira = | |
3771 | { | |
3772 | { | |
3773 | RTL_PASS, | |
3774 | "ira", /* name */ | |
3775 | gate_ira, /* gate */ | |
3776 | rest_of_handle_ira, /* execute */ | |
3777 | NULL, /* sub */ | |
3778 | NULL, /* next */ | |
3779 | 0, /* static_pass_number */ | |
7072a650 | 3780 | TV_NONE, /* tv_id */ |
058e97ec VM |
3781 | 0, /* properties_required */ |
3782 | 0, /* properties_provided */ | |
3783 | 0, /* properties_destroyed */ | |
3784 | 0, /* todo_flags_start */ | |
3785 | TODO_dump_func | | |
3786 | TODO_ggc_collect /* todo_flags_finish */ | |
3787 | } | |
3788 | }; |