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058e97ec | 1 | /* Integrated Register Allocator (IRA) entry point. |
cbe34bb5 | 2 | Copyright (C) 2006-2017 Free Software Foundation, Inc. |
058e97ec VM |
3 | Contributed by Vladimir Makarov <vmakarov@redhat.com>. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it under | |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 3, or (at your option) any later | |
10 | version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | /* The integrated register allocator (IRA) is a | |
22 | regional register allocator performing graph coloring on a top-down | |
23 | traversal of nested regions. Graph coloring in a region is based | |
24 | on Chaitin-Briggs algorithm. It is called integrated because | |
25 | register coalescing, register live range splitting, and choosing a | |
26 | better hard register are done on-the-fly during coloring. Register | |
27 | coalescing and choosing a cheaper hard register is done by hard | |
28 | register preferencing during hard register assigning. The live | |
29 | range splitting is a byproduct of the regional register allocation. | |
30 | ||
31 | Major IRA notions are: | |
32 | ||
33 | o *Region* is a part of CFG where graph coloring based on | |
34 | Chaitin-Briggs algorithm is done. IRA can work on any set of | |
35 | nested CFG regions forming a tree. Currently the regions are | |
36 | the entire function for the root region and natural loops for | |
37 | the other regions. Therefore data structure representing a | |
38 | region is called loop_tree_node. | |
39 | ||
1756cb66 VM |
40 | o *Allocno class* is a register class used for allocation of |
41 | given allocno. It means that only hard register of given | |
42 | register class can be assigned to given allocno. In reality, | |
43 | even smaller subset of (*profitable*) hard registers can be | |
44 | assigned. In rare cases, the subset can be even smaller | |
45 | because our modification of Chaitin-Briggs algorithm requires | |
46 | that sets of hard registers can be assigned to allocnos forms a | |
47 | forest, i.e. the sets can be ordered in a way where any | |
48 | previous set is not intersected with given set or is a superset | |
49 | of given set. | |
50 | ||
51 | o *Pressure class* is a register class belonging to a set of | |
52 | register classes containing all of the hard-registers available | |
53 | for register allocation. The set of all pressure classes for a | |
54 | target is defined in the corresponding machine-description file | |
55 | according some criteria. Register pressure is calculated only | |
56 | for pressure classes and it affects some IRA decisions as | |
57 | forming allocation regions. | |
058e97ec VM |
58 | |
59 | o *Allocno* represents the live range of a pseudo-register in a | |
60 | region. Besides the obvious attributes like the corresponding | |
1756cb66 | 61 | pseudo-register number, allocno class, conflicting allocnos and |
058e97ec VM |
62 | conflicting hard-registers, there are a few allocno attributes |
63 | which are important for understanding the allocation algorithm: | |
64 | ||
1756cb66 VM |
65 | - *Live ranges*. This is a list of ranges of *program points* |
66 | where the allocno lives. Program points represent places | |
67 | where a pseudo can be born or become dead (there are | |
058e97ec VM |
68 | approximately two times more program points than the insns) |
69 | and they are represented by integers starting with 0. The | |
1756cb66 VM |
70 | live ranges are used to find conflicts between allocnos. |
71 | They also play very important role for the transformation of | |
72 | the IRA internal representation of several regions into a one | |
73 | region representation. The later is used during the reload | |
74 | pass work because each allocno represents all of the | |
75 | corresponding pseudo-registers. | |
058e97ec VM |
76 | |
77 | - *Hard-register costs*. This is a vector of size equal to the | |
1756cb66 VM |
78 | number of available hard-registers of the allocno class. The |
79 | cost of a callee-clobbered hard-register for an allocno is | |
80 | increased by the cost of save/restore code around the calls | |
81 | through the given allocno's life. If the allocno is a move | |
82 | instruction operand and another operand is a hard-register of | |
83 | the allocno class, the cost of the hard-register is decreased | |
84 | by the move cost. | |
058e97ec VM |
85 | |
86 | When an allocno is assigned, the hard-register with minimal | |
87 | full cost is used. Initially, a hard-register's full cost is | |
88 | the corresponding value from the hard-register's cost vector. | |
89 | If the allocno is connected by a *copy* (see below) to | |
90 | another allocno which has just received a hard-register, the | |
91 | cost of the hard-register is decreased. Before choosing a | |
92 | hard-register for an allocno, the allocno's current costs of | |
93 | the hard-registers are modified by the conflict hard-register | |
94 | costs of all of the conflicting allocnos which are not | |
95 | assigned yet. | |
96 | ||
97 | - *Conflict hard-register costs*. This is a vector of the same | |
98 | size as the hard-register costs vector. To permit an | |
99 | unassigned allocno to get a better hard-register, IRA uses | |
100 | this vector to calculate the final full cost of the | |
101 | available hard-registers. Conflict hard-register costs of an | |
102 | unassigned allocno are also changed with a change of the | |
103 | hard-register cost of the allocno when a copy involving the | |
104 | allocno is processed as described above. This is done to | |
105 | show other unassigned allocnos that a given allocno prefers | |
106 | some hard-registers in order to remove the move instruction | |
107 | corresponding to the copy. | |
108 | ||
109 | o *Cap*. If a pseudo-register does not live in a region but | |
110 | lives in a nested region, IRA creates a special allocno called | |
111 | a cap in the outer region. A region cap is also created for a | |
112 | subregion cap. | |
113 | ||
114 | o *Copy*. Allocnos can be connected by copies. Copies are used | |
115 | to modify hard-register costs for allocnos during coloring. | |
116 | Such modifications reflects a preference to use the same | |
117 | hard-register for the allocnos connected by copies. Usually | |
118 | copies are created for move insns (in this case it results in | |
119 | register coalescing). But IRA also creates copies for operands | |
120 | of an insn which should be assigned to the same hard-register | |
121 | due to constraints in the machine description (it usually | |
122 | results in removing a move generated in reload to satisfy | |
123 | the constraints) and copies referring to the allocno which is | |
124 | the output operand of an instruction and the allocno which is | |
125 | an input operand dying in the instruction (creation of such | |
126 | copies results in less register shuffling). IRA *does not* | |
127 | create copies between the same register allocnos from different | |
128 | regions because we use another technique for propagating | |
129 | hard-register preference on the borders of regions. | |
130 | ||
131 | Allocnos (including caps) for the upper region in the region tree | |
132 | *accumulate* information important for coloring from allocnos with | |
133 | the same pseudo-register from nested regions. This includes | |
134 | hard-register and memory costs, conflicts with hard-registers, | |
135 | allocno conflicts, allocno copies and more. *Thus, attributes for | |
136 | allocnos in a region have the same values as if the region had no | |
137 | subregions*. It means that attributes for allocnos in the | |
138 | outermost region corresponding to the function have the same values | |
139 | as though the allocation used only one region which is the entire | |
140 | function. It also means that we can look at IRA work as if the | |
141 | first IRA did allocation for all function then it improved the | |
142 | allocation for loops then their subloops and so on. | |
143 | ||
144 | IRA major passes are: | |
145 | ||
146 | o Building IRA internal representation which consists of the | |
147 | following subpasses: | |
148 | ||
149 | * First, IRA builds regions and creates allocnos (file | |
150 | ira-build.c) and initializes most of their attributes. | |
151 | ||
1756cb66 VM |
152 | * Then IRA finds an allocno class for each allocno and |
153 | calculates its initial (non-accumulated) cost of memory and | |
154 | each hard-register of its allocno class (file ira-cost.c). | |
058e97ec | 155 | |
df3e3493 | 156 | * IRA creates live ranges of each allocno, calculates register |
1756cb66 | 157 | pressure for each pressure class in each region, sets up |
058e97ec VM |
158 | conflict hard registers for each allocno and info about calls |
159 | the allocno lives through (file ira-lives.c). | |
160 | ||
161 | * IRA removes low register pressure loops from the regions | |
162 | mostly to speed IRA up (file ira-build.c). | |
163 | ||
164 | * IRA propagates accumulated allocno info from lower region | |
165 | allocnos to corresponding upper region allocnos (file | |
166 | ira-build.c). | |
167 | ||
168 | * IRA creates all caps (file ira-build.c). | |
169 | ||
1756cb66 VM |
170 | * Having live-ranges of allocnos and their classes, IRA creates |
171 | conflicting allocnos for each allocno. Conflicting allocnos | |
172 | are stored as a bit vector or array of pointers to the | |
173 | conflicting allocnos whatever is more profitable (file | |
174 | ira-conflicts.c). At this point IRA creates allocno copies. | |
058e97ec VM |
175 | |
176 | o Coloring. Now IRA has all necessary info to start graph coloring | |
177 | process. It is done in each region on top-down traverse of the | |
178 | region tree (file ira-color.c). There are following subpasses: | |
b8698a0f | 179 | |
1756cb66 VM |
180 | * Finding profitable hard registers of corresponding allocno |
181 | class for each allocno. For example, only callee-saved hard | |
182 | registers are frequently profitable for allocnos living | |
183 | through colors. If the profitable hard register set of | |
184 | allocno does not form a tree based on subset relation, we use | |
185 | some approximation to form the tree. This approximation is | |
186 | used to figure out trivial colorability of allocnos. The | |
187 | approximation is a pretty rare case. | |
188 | ||
058e97ec VM |
189 | * Putting allocnos onto the coloring stack. IRA uses Briggs |
190 | optimistic coloring which is a major improvement over | |
191 | Chaitin's coloring. Therefore IRA does not spill allocnos at | |
192 | this point. There is some freedom in the order of putting | |
193 | allocnos on the stack which can affect the final result of | |
1756cb66 | 194 | the allocation. IRA uses some heuristics to improve the |
41808d15 VM |
195 | order. The major one is to form *threads* from colorable |
196 | allocnos and push them on the stack by threads. Thread is a | |
197 | set of non-conflicting colorable allocnos connected by | |
198 | copies. The thread contains allocnos from the colorable | |
199 | bucket or colorable allocnos already pushed onto the coloring | |
200 | stack. Pushing thread allocnos one after another onto the | |
201 | stack increases chances of removing copies when the allocnos | |
202 | get the same hard reg. | |
1756cb66 VM |
203 | |
204 | We also use a modification of Chaitin-Briggs algorithm which | |
205 | works for intersected register classes of allocnos. To | |
206 | figure out trivial colorability of allocnos, the mentioned | |
207 | above tree of hard register sets is used. To get an idea how | |
208 | the algorithm works in i386 example, let us consider an | |
209 | allocno to which any general hard register can be assigned. | |
210 | If the allocno conflicts with eight allocnos to which only | |
211 | EAX register can be assigned, given allocno is still | |
212 | trivially colorable because all conflicting allocnos might be | |
213 | assigned only to EAX and all other general hard registers are | |
214 | still free. | |
215 | ||
216 | To get an idea of the used trivial colorability criterion, it | |
217 | is also useful to read article "Graph-Coloring Register | |
218 | Allocation for Irregular Architectures" by Michael D. Smith | |
219 | and Glen Holloway. Major difference between the article | |
220 | approach and approach used in IRA is that Smith's approach | |
221 | takes register classes only from machine description and IRA | |
222 | calculate register classes from intermediate code too | |
223 | (e.g. an explicit usage of hard registers in RTL code for | |
224 | parameter passing can result in creation of additional | |
225 | register classes which contain or exclude the hard | |
226 | registers). That makes IRA approach useful for improving | |
227 | coloring even for architectures with regular register files | |
228 | and in fact some benchmarking shows the improvement for | |
229 | regular class architectures is even bigger than for irregular | |
230 | ones. Another difference is that Smith's approach chooses | |
231 | intersection of classes of all insn operands in which a given | |
232 | pseudo occurs. IRA can use bigger classes if it is still | |
233 | more profitable than memory usage. | |
058e97ec VM |
234 | |
235 | * Popping the allocnos from the stack and assigning them hard | |
236 | registers. If IRA can not assign a hard register to an | |
237 | allocno and the allocno is coalesced, IRA undoes the | |
238 | coalescing and puts the uncoalesced allocnos onto the stack in | |
239 | the hope that some such allocnos will get a hard register | |
240 | separately. If IRA fails to assign hard register or memory | |
241 | is more profitable for it, IRA spills the allocno. IRA | |
242 | assigns the allocno the hard-register with minimal full | |
243 | allocation cost which reflects the cost of usage of the | |
244 | hard-register for the allocno and cost of usage of the | |
245 | hard-register for allocnos conflicting with given allocno. | |
246 | ||
1756cb66 | 247 | * Chaitin-Briggs coloring assigns as many pseudos as possible |
df3e3493 | 248 | to hard registers. After coloring we try to improve |
1756cb66 VM |
249 | allocation with cost point of view. We improve the |
250 | allocation by spilling some allocnos and assigning the freed | |
251 | hard registers to other allocnos if it decreases the overall | |
252 | allocation cost. | |
253 | ||
3447fefe | 254 | * After allocno assigning in the region, IRA modifies the hard |
058e97ec VM |
255 | register and memory costs for the corresponding allocnos in |
256 | the subregions to reflect the cost of possible loads, stores, | |
257 | or moves on the border of the region and its subregions. | |
258 | When default regional allocation algorithm is used | |
259 | (-fira-algorithm=mixed), IRA just propagates the assignment | |
260 | for allocnos if the register pressure in the region for the | |
1756cb66 VM |
261 | corresponding pressure class is less than number of available |
262 | hard registers for given pressure class. | |
058e97ec VM |
263 | |
264 | o Spill/restore code moving. When IRA performs an allocation | |
265 | by traversing regions in top-down order, it does not know what | |
266 | happens below in the region tree. Therefore, sometimes IRA | |
267 | misses opportunities to perform a better allocation. A simple | |
268 | optimization tries to improve allocation in a region having | |
269 | subregions and containing in another region. If the | |
270 | corresponding allocnos in the subregion are spilled, it spills | |
271 | the region allocno if it is profitable. The optimization | |
272 | implements a simple iterative algorithm performing profitable | |
273 | transformations while they are still possible. It is fast in | |
274 | practice, so there is no real need for a better time complexity | |
275 | algorithm. | |
276 | ||
1756cb66 VM |
277 | o Code change. After coloring, two allocnos representing the |
278 | same pseudo-register outside and inside a region respectively | |
279 | may be assigned to different locations (hard-registers or | |
280 | memory). In this case IRA creates and uses a new | |
281 | pseudo-register inside the region and adds code to move allocno | |
282 | values on the region's borders. This is done during top-down | |
283 | traversal of the regions (file ira-emit.c). In some | |
284 | complicated cases IRA can create a new allocno to move allocno | |
285 | values (e.g. when a swap of values stored in two hard-registers | |
286 | is needed). At this stage, the new allocno is marked as | |
287 | spilled. IRA still creates the pseudo-register and the moves | |
288 | on the region borders even when both allocnos were assigned to | |
289 | the same hard-register. If the reload pass spills a | |
290 | pseudo-register for some reason, the effect will be smaller | |
291 | because another allocno will still be in the hard-register. In | |
292 | most cases, this is better then spilling both allocnos. If | |
293 | reload does not change the allocation for the two | |
294 | pseudo-registers, the trivial move will be removed by | |
295 | post-reload optimizations. IRA does not generate moves for | |
058e97ec VM |
296 | allocnos assigned to the same hard register when the default |
297 | regional allocation algorithm is used and the register pressure | |
1756cb66 VM |
298 | in the region for the corresponding pressure class is less than |
299 | number of available hard registers for given pressure class. | |
058e97ec VM |
300 | IRA also does some optimizations to remove redundant stores and |
301 | to reduce code duplication on the region borders. | |
302 | ||
303 | o Flattening internal representation. After changing code, IRA | |
304 | transforms its internal representation for several regions into | |
305 | one region representation (file ira-build.c). This process is | |
306 | called IR flattening. Such process is more complicated than IR | |
307 | rebuilding would be, but is much faster. | |
308 | ||
309 | o After IR flattening, IRA tries to assign hard registers to all | |
df3e3493 | 310 | spilled allocnos. This is implemented by a simple and fast |
058e97ec VM |
311 | priority coloring algorithm (see function |
312 | ira_reassign_conflict_allocnos::ira-color.c). Here new allocnos | |
313 | created during the code change pass can be assigned to hard | |
314 | registers. | |
315 | ||
316 | o At the end IRA calls the reload pass. The reload pass | |
317 | communicates with IRA through several functions in file | |
318 | ira-color.c to improve its decisions in | |
319 | ||
320 | * sharing stack slots for the spilled pseudos based on IRA info | |
321 | about pseudo-register conflicts. | |
322 | ||
323 | * reassigning hard-registers to all spilled pseudos at the end | |
324 | of each reload iteration. | |
325 | ||
326 | * choosing a better hard-register to spill based on IRA info | |
327 | about pseudo-register live ranges and the register pressure | |
328 | in places where the pseudo-register lives. | |
329 | ||
330 | IRA uses a lot of data representing the target processors. These | |
df3e3493 | 331 | data are initialized in file ira.c. |
058e97ec VM |
332 | |
333 | If function has no loops (or the loops are ignored when | |
334 | -fira-algorithm=CB is used), we have classic Chaitin-Briggs | |
335 | coloring (only instead of separate pass of coalescing, we use hard | |
336 | register preferencing). In such case, IRA works much faster | |
337 | because many things are not made (like IR flattening, the | |
338 | spill/restore optimization, and the code change). | |
339 | ||
340 | Literature is worth to read for better understanding the code: | |
341 | ||
342 | o Preston Briggs, Keith D. Cooper, Linda Torczon. Improvements to | |
343 | Graph Coloring Register Allocation. | |
344 | ||
345 | o David Callahan, Brian Koblenz. Register allocation via | |
346 | hierarchical graph coloring. | |
347 | ||
348 | o Keith Cooper, Anshuman Dasgupta, Jason Eckhardt. Revisiting Graph | |
349 | Coloring Register Allocation: A Study of the Chaitin-Briggs and | |
350 | Callahan-Koblenz Algorithms. | |
351 | ||
352 | o Guei-Yuan Lueh, Thomas Gross, and Ali-Reza Adl-Tabatabai. Global | |
353 | Register Allocation Based on Graph Fusion. | |
354 | ||
1756cb66 VM |
355 | o Michael D. Smith and Glenn Holloway. Graph-Coloring Register |
356 | Allocation for Irregular Architectures | |
357 | ||
058e97ec VM |
358 | o Vladimir Makarov. The Integrated Register Allocator for GCC. |
359 | ||
360 | o Vladimir Makarov. The top-down register allocator for irregular | |
361 | register file architectures. | |
362 | ||
363 | */ | |
364 | ||
365 | ||
366 | #include "config.h" | |
367 | #include "system.h" | |
368 | #include "coretypes.h" | |
c7131fb2 | 369 | #include "backend.h" |
957060b5 | 370 | #include "target.h" |
058e97ec | 371 | #include "rtl.h" |
957060b5 | 372 | #include "tree.h" |
c7131fb2 | 373 | #include "df.h" |
4d0cdd0c | 374 | #include "memmodel.h" |
957060b5 | 375 | #include "tm_p.h" |
957060b5 | 376 | #include "insn-config.h" |
c7131fb2 | 377 | #include "regs.h" |
957060b5 AM |
378 | #include "ira.h" |
379 | #include "ira-int.h" | |
380 | #include "diagnostic-core.h" | |
60393bbc AM |
381 | #include "cfgrtl.h" |
382 | #include "cfgbuild.h" | |
383 | #include "cfgcleanup.h" | |
058e97ec | 384 | #include "expr.h" |
058e97ec VM |
385 | #include "tree-pass.h" |
386 | #include "output.h" | |
387 | #include "reload.h" | |
c7131fb2 | 388 | #include "cfgloop.h" |
55a2c322 | 389 | #include "lra.h" |
b0c11403 | 390 | #include "dce.h" |
acf41a74 | 391 | #include "dbgcnt.h" |
40954ce5 | 392 | #include "rtl-iter.h" |
a5e022d5 | 393 | #include "shrink-wrap.h" |
013a8899 | 394 | #include "print-rtl.h" |
058e97ec | 395 | |
afcc66c4 RS |
396 | struct target_ira default_target_ira; |
397 | struct target_ira_int default_target_ira_int; | |
398 | #if SWITCHABLE_TARGET | |
399 | struct target_ira *this_target_ira = &default_target_ira; | |
400 | struct target_ira_int *this_target_ira_int = &default_target_ira_int; | |
401 | #endif | |
402 | ||
058e97ec VM |
403 | /* A modified value of flag `-fira-verbose' used internally. */ |
404 | int internal_flag_ira_verbose; | |
405 | ||
406 | /* Dump file of the allocator if it is not NULL. */ | |
407 | FILE *ira_dump_file; | |
408 | ||
058e97ec VM |
409 | /* The number of elements in the following array. */ |
410 | int ira_spilled_reg_stack_slots_num; | |
411 | ||
412 | /* The following array contains info about spilled pseudo-registers | |
413 | stack slots used in current function so far. */ | |
414 | struct ira_spilled_reg_stack_slot *ira_spilled_reg_stack_slots; | |
415 | ||
ae2b9cb6 BS |
416 | /* Correspondingly overall cost of the allocation, overall cost before |
417 | reload, cost of the allocnos assigned to hard-registers, cost of | |
418 | the allocnos assigned to memory, cost of loads, stores and register | |
419 | move insns generated for pseudo-register live range splitting (see | |
420 | ira-emit.c). */ | |
2bf7560b VM |
421 | int64_t ira_overall_cost, overall_cost_before; |
422 | int64_t ira_reg_cost, ira_mem_cost; | |
423 | int64_t ira_load_cost, ira_store_cost, ira_shuffle_cost; | |
058e97ec VM |
424 | int ira_move_loops_num, ira_additional_jumps_num; |
425 | ||
2af2dbdc VM |
426 | /* All registers that can be eliminated. */ |
427 | ||
428 | HARD_REG_SET eliminable_regset; | |
429 | ||
70cc3288 VM |
430 | /* Value of max_reg_num () before IRA work start. This value helps |
431 | us to recognize a situation when new pseudos were created during | |
432 | IRA work. */ | |
433 | static int max_regno_before_ira; | |
434 | ||
058e97ec VM |
435 | /* Temporary hard reg set used for a different calculation. */ |
436 | static HARD_REG_SET temp_hard_regset; | |
437 | ||
e80ccebc RS |
438 | #define last_mode_for_init_move_cost \ |
439 | (this_target_ira_int->x_last_mode_for_init_move_cost) | |
058e97ec VM |
440 | \f |
441 | ||
442 | /* The function sets up the map IRA_REG_MODE_HARD_REGSET. */ | |
443 | static void | |
444 | setup_reg_mode_hard_regset (void) | |
445 | { | |
446 | int i, m, hard_regno; | |
447 | ||
448 | for (m = 0; m < NUM_MACHINE_MODES; m++) | |
449 | for (hard_regno = 0; hard_regno < FIRST_PSEUDO_REGISTER; hard_regno++) | |
450 | { | |
451 | CLEAR_HARD_REG_SET (ira_reg_mode_hard_regset[hard_regno][m]); | |
ad474626 RS |
452 | for (i = hard_regno_nregs (hard_regno, (machine_mode) m) - 1; |
453 | i >= 0; i--) | |
058e97ec VM |
454 | if (hard_regno + i < FIRST_PSEUDO_REGISTER) |
455 | SET_HARD_REG_BIT (ira_reg_mode_hard_regset[hard_regno][m], | |
456 | hard_regno + i); | |
457 | } | |
458 | } | |
459 | ||
460 | \f | |
afcc66c4 RS |
461 | #define no_unit_alloc_regs \ |
462 | (this_target_ira_int->x_no_unit_alloc_regs) | |
058e97ec VM |
463 | |
464 | /* The function sets up the three arrays declared above. */ | |
465 | static void | |
466 | setup_class_hard_regs (void) | |
467 | { | |
468 | int cl, i, hard_regno, n; | |
469 | HARD_REG_SET processed_hard_reg_set; | |
470 | ||
471 | ira_assert (SHRT_MAX >= FIRST_PSEUDO_REGISTER); | |
058e97ec VM |
472 | for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) |
473 | { | |
474 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); | |
475 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
476 | CLEAR_HARD_REG_SET (processed_hard_reg_set); | |
7db7ed3c | 477 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
0583835c | 478 | { |
854edfcd VM |
479 | ira_non_ordered_class_hard_regs[cl][i] = -1; |
480 | ira_class_hard_reg_index[cl][i] = -1; | |
0583835c | 481 | } |
058e97ec VM |
482 | for (n = 0, i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
483 | { | |
484 | #ifdef REG_ALLOC_ORDER | |
485 | hard_regno = reg_alloc_order[i]; | |
486 | #else | |
487 | hard_regno = i; | |
b8698a0f | 488 | #endif |
058e97ec VM |
489 | if (TEST_HARD_REG_BIT (processed_hard_reg_set, hard_regno)) |
490 | continue; | |
491 | SET_HARD_REG_BIT (processed_hard_reg_set, hard_regno); | |
492 | if (! TEST_HARD_REG_BIT (temp_hard_regset, hard_regno)) | |
493 | ira_class_hard_reg_index[cl][hard_regno] = -1; | |
494 | else | |
495 | { | |
496 | ira_class_hard_reg_index[cl][hard_regno] = n; | |
497 | ira_class_hard_regs[cl][n++] = hard_regno; | |
498 | } | |
499 | } | |
500 | ira_class_hard_regs_num[cl] = n; | |
0583835c VM |
501 | for (n = 0, i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
502 | if (TEST_HARD_REG_BIT (temp_hard_regset, i)) | |
503 | ira_non_ordered_class_hard_regs[cl][n++] = i; | |
504 | ira_assert (ira_class_hard_regs_num[cl] == n); | |
058e97ec VM |
505 | } |
506 | } | |
507 | ||
058e97ec VM |
508 | /* Set up global variables defining info about hard registers for the |
509 | allocation. These depend on USE_HARD_FRAME_P whose TRUE value means | |
510 | that we can use the hard frame pointer for the allocation. */ | |
511 | static void | |
512 | setup_alloc_regs (bool use_hard_frame_p) | |
513 | { | |
5a733826 BS |
514 | #ifdef ADJUST_REG_ALLOC_ORDER |
515 | ADJUST_REG_ALLOC_ORDER; | |
516 | #endif | |
f80041ef | 517 | COPY_HARD_REG_SET (no_unit_alloc_regs, fixed_nonglobal_reg_set); |
058e97ec VM |
518 | if (! use_hard_frame_p) |
519 | SET_HARD_REG_BIT (no_unit_alloc_regs, HARD_FRAME_POINTER_REGNUM); | |
520 | setup_class_hard_regs (); | |
058e97ec VM |
521 | } |
522 | ||
523 | \f | |
524 | ||
1756cb66 VM |
525 | #define alloc_reg_class_subclasses \ |
526 | (this_target_ira_int->x_alloc_reg_class_subclasses) | |
527 | ||
528 | /* Initialize the table of subclasses of each reg class. */ | |
529 | static void | |
530 | setup_reg_subclasses (void) | |
531 | { | |
532 | int i, j; | |
533 | HARD_REG_SET temp_hard_regset2; | |
534 | ||
535 | for (i = 0; i < N_REG_CLASSES; i++) | |
536 | for (j = 0; j < N_REG_CLASSES; j++) | |
537 | alloc_reg_class_subclasses[i][j] = LIM_REG_CLASSES; | |
538 | ||
539 | for (i = 0; i < N_REG_CLASSES; i++) | |
540 | { | |
541 | if (i == (int) NO_REGS) | |
542 | continue; | |
543 | ||
544 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[i]); | |
545 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
546 | if (hard_reg_set_empty_p (temp_hard_regset)) | |
547 | continue; | |
548 | for (j = 0; j < N_REG_CLASSES; j++) | |
549 | if (i != j) | |
550 | { | |
551 | enum reg_class *p; | |
552 | ||
553 | COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[j]); | |
554 | AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs); | |
555 | if (! hard_reg_set_subset_p (temp_hard_regset, | |
556 | temp_hard_regset2)) | |
557 | continue; | |
558 | p = &alloc_reg_class_subclasses[j][0]; | |
559 | while (*p != LIM_REG_CLASSES) p++; | |
560 | *p = (enum reg_class) i; | |
561 | } | |
562 | } | |
563 | } | |
564 | ||
565 | \f | |
566 | ||
567 | /* Set up IRA_MEMORY_MOVE_COST and IRA_MAX_MEMORY_MOVE_COST. */ | |
058e97ec VM |
568 | static void |
569 | setup_class_subset_and_memory_move_costs (void) | |
570 | { | |
1756cb66 | 571 | int cl, cl2, mode, cost; |
058e97ec VM |
572 | HARD_REG_SET temp_hard_regset2; |
573 | ||
574 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
575 | ira_memory_move_cost[mode][NO_REGS][0] | |
576 | = ira_memory_move_cost[mode][NO_REGS][1] = SHRT_MAX; | |
577 | for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) | |
578 | { | |
579 | if (cl != (int) NO_REGS) | |
580 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
581 | { | |
1756cb66 VM |
582 | ira_max_memory_move_cost[mode][cl][0] |
583 | = ira_memory_move_cost[mode][cl][0] | |
ef4bddc2 | 584 | = memory_move_cost ((machine_mode) mode, |
6f76a878 | 585 | (reg_class_t) cl, false); |
1756cb66 VM |
586 | ira_max_memory_move_cost[mode][cl][1] |
587 | = ira_memory_move_cost[mode][cl][1] | |
ef4bddc2 | 588 | = memory_move_cost ((machine_mode) mode, |
6f76a878 | 589 | (reg_class_t) cl, true); |
058e97ec VM |
590 | /* Costs for NO_REGS are used in cost calculation on the |
591 | 1st pass when the preferred register classes are not | |
592 | known yet. In this case we take the best scenario. */ | |
593 | if (ira_memory_move_cost[mode][NO_REGS][0] | |
594 | > ira_memory_move_cost[mode][cl][0]) | |
1756cb66 VM |
595 | ira_max_memory_move_cost[mode][NO_REGS][0] |
596 | = ira_memory_move_cost[mode][NO_REGS][0] | |
058e97ec VM |
597 | = ira_memory_move_cost[mode][cl][0]; |
598 | if (ira_memory_move_cost[mode][NO_REGS][1] | |
599 | > ira_memory_move_cost[mode][cl][1]) | |
1756cb66 VM |
600 | ira_max_memory_move_cost[mode][NO_REGS][1] |
601 | = ira_memory_move_cost[mode][NO_REGS][1] | |
058e97ec VM |
602 | = ira_memory_move_cost[mode][cl][1]; |
603 | } | |
058e97ec | 604 | } |
1756cb66 VM |
605 | for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) |
606 | for (cl2 = (int) N_REG_CLASSES - 1; cl2 >= 0; cl2--) | |
607 | { | |
608 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); | |
609 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
610 | COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl2]); | |
611 | AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs); | |
612 | ira_class_subset_p[cl][cl2] | |
613 | = hard_reg_set_subset_p (temp_hard_regset, temp_hard_regset2); | |
614 | if (! hard_reg_set_empty_p (temp_hard_regset2) | |
615 | && hard_reg_set_subset_p (reg_class_contents[cl2], | |
616 | reg_class_contents[cl])) | |
617 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
618 | { | |
619 | cost = ira_memory_move_cost[mode][cl2][0]; | |
620 | if (cost > ira_max_memory_move_cost[mode][cl][0]) | |
621 | ira_max_memory_move_cost[mode][cl][0] = cost; | |
622 | cost = ira_memory_move_cost[mode][cl2][1]; | |
623 | if (cost > ira_max_memory_move_cost[mode][cl][1]) | |
624 | ira_max_memory_move_cost[mode][cl][1] = cost; | |
625 | } | |
626 | } | |
627 | for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) | |
628 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
629 | { | |
630 | ira_memory_move_cost[mode][cl][0] | |
631 | = ira_max_memory_move_cost[mode][cl][0]; | |
632 | ira_memory_move_cost[mode][cl][1] | |
633 | = ira_max_memory_move_cost[mode][cl][1]; | |
634 | } | |
635 | setup_reg_subclasses (); | |
058e97ec VM |
636 | } |
637 | ||
638 | \f | |
639 | ||
640 | /* Define the following macro if allocation through malloc if | |
641 | preferable. */ | |
642 | #define IRA_NO_OBSTACK | |
643 | ||
644 | #ifndef IRA_NO_OBSTACK | |
645 | /* Obstack used for storing all dynamic data (except bitmaps) of the | |
646 | IRA. */ | |
647 | static struct obstack ira_obstack; | |
648 | #endif | |
649 | ||
650 | /* Obstack used for storing all bitmaps of the IRA. */ | |
651 | static struct bitmap_obstack ira_bitmap_obstack; | |
652 | ||
653 | /* Allocate memory of size LEN for IRA data. */ | |
654 | void * | |
655 | ira_allocate (size_t len) | |
656 | { | |
657 | void *res; | |
658 | ||
659 | #ifndef IRA_NO_OBSTACK | |
660 | res = obstack_alloc (&ira_obstack, len); | |
661 | #else | |
662 | res = xmalloc (len); | |
663 | #endif | |
664 | return res; | |
665 | } | |
666 | ||
058e97ec VM |
667 | /* Free memory ADDR allocated for IRA data. */ |
668 | void | |
669 | ira_free (void *addr ATTRIBUTE_UNUSED) | |
670 | { | |
671 | #ifndef IRA_NO_OBSTACK | |
672 | /* do nothing */ | |
673 | #else | |
674 | free (addr); | |
675 | #endif | |
676 | } | |
677 | ||
678 | ||
679 | /* Allocate and returns bitmap for IRA. */ | |
680 | bitmap | |
681 | ira_allocate_bitmap (void) | |
682 | { | |
683 | return BITMAP_ALLOC (&ira_bitmap_obstack); | |
684 | } | |
685 | ||
686 | /* Free bitmap B allocated for IRA. */ | |
687 | void | |
688 | ira_free_bitmap (bitmap b ATTRIBUTE_UNUSED) | |
689 | { | |
690 | /* do nothing */ | |
691 | } | |
692 | ||
693 | \f | |
694 | ||
695 | /* Output information about allocation of all allocnos (except for | |
696 | caps) into file F. */ | |
697 | void | |
698 | ira_print_disposition (FILE *f) | |
699 | { | |
700 | int i, n, max_regno; | |
701 | ira_allocno_t a; | |
702 | basic_block bb; | |
703 | ||
704 | fprintf (f, "Disposition:"); | |
705 | max_regno = max_reg_num (); | |
706 | for (n = 0, i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
707 | for (a = ira_regno_allocno_map[i]; | |
708 | a != NULL; | |
709 | a = ALLOCNO_NEXT_REGNO_ALLOCNO (a)) | |
710 | { | |
711 | if (n % 4 == 0) | |
712 | fprintf (f, "\n"); | |
713 | n++; | |
714 | fprintf (f, " %4d:r%-4d", ALLOCNO_NUM (a), ALLOCNO_REGNO (a)); | |
715 | if ((bb = ALLOCNO_LOOP_TREE_NODE (a)->bb) != NULL) | |
716 | fprintf (f, "b%-3d", bb->index); | |
717 | else | |
2608d841 | 718 | fprintf (f, "l%-3d", ALLOCNO_LOOP_TREE_NODE (a)->loop_num); |
058e97ec VM |
719 | if (ALLOCNO_HARD_REGNO (a) >= 0) |
720 | fprintf (f, " %3d", ALLOCNO_HARD_REGNO (a)); | |
721 | else | |
722 | fprintf (f, " mem"); | |
723 | } | |
724 | fprintf (f, "\n"); | |
725 | } | |
726 | ||
727 | /* Outputs information about allocation of all allocnos into | |
728 | stderr. */ | |
729 | void | |
730 | ira_debug_disposition (void) | |
731 | { | |
732 | ira_print_disposition (stderr); | |
733 | } | |
734 | ||
735 | \f | |
058e97ec | 736 | |
1756cb66 VM |
737 | /* Set up ira_stack_reg_pressure_class which is the biggest pressure |
738 | register class containing stack registers or NO_REGS if there are | |
739 | no stack registers. To find this class, we iterate through all | |
740 | register pressure classes and choose the first register pressure | |
741 | class containing all the stack registers and having the biggest | |
742 | size. */ | |
fe82cdfb | 743 | static void |
1756cb66 VM |
744 | setup_stack_reg_pressure_class (void) |
745 | { | |
746 | ira_stack_reg_pressure_class = NO_REGS; | |
747 | #ifdef STACK_REGS | |
748 | { | |
749 | int i, best, size; | |
750 | enum reg_class cl; | |
751 | HARD_REG_SET temp_hard_regset2; | |
752 | ||
753 | CLEAR_HARD_REG_SET (temp_hard_regset); | |
754 | for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++) | |
755 | SET_HARD_REG_BIT (temp_hard_regset, i); | |
756 | best = 0; | |
757 | for (i = 0; i < ira_pressure_classes_num; i++) | |
758 | { | |
759 | cl = ira_pressure_classes[i]; | |
760 | COPY_HARD_REG_SET (temp_hard_regset2, temp_hard_regset); | |
761 | AND_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl]); | |
762 | size = hard_reg_set_size (temp_hard_regset2); | |
763 | if (best < size) | |
764 | { | |
765 | best = size; | |
766 | ira_stack_reg_pressure_class = cl; | |
767 | } | |
768 | } | |
769 | } | |
770 | #endif | |
771 | } | |
772 | ||
773 | /* Find pressure classes which are register classes for which we | |
774 | calculate register pressure in IRA, register pressure sensitive | |
775 | insn scheduling, and register pressure sensitive loop invariant | |
776 | motion. | |
777 | ||
778 | To make register pressure calculation easy, we always use | |
779 | non-intersected register pressure classes. A move of hard | |
780 | registers from one register pressure class is not more expensive | |
781 | than load and store of the hard registers. Most likely an allocno | |
782 | class will be a subset of a register pressure class and in many | |
783 | cases a register pressure class. That makes usage of register | |
784 | pressure classes a good approximation to find a high register | |
785 | pressure. */ | |
786 | static void | |
787 | setup_pressure_classes (void) | |
058e97ec | 788 | { |
1756cb66 VM |
789 | int cost, i, n, curr; |
790 | int cl, cl2; | |
791 | enum reg_class pressure_classes[N_REG_CLASSES]; | |
792 | int m; | |
058e97ec | 793 | HARD_REG_SET temp_hard_regset2; |
1756cb66 | 794 | bool insert_p; |
058e97ec | 795 | |
b4ff394c PH |
796 | if (targetm.compute_pressure_classes) |
797 | n = targetm.compute_pressure_classes (pressure_classes); | |
798 | else | |
799 | { | |
800 | n = 0; | |
801 | for (cl = 0; cl < N_REG_CLASSES; cl++) | |
1756cb66 | 802 | { |
b4ff394c PH |
803 | if (ira_class_hard_regs_num[cl] == 0) |
804 | continue; | |
805 | if (ira_class_hard_regs_num[cl] != 1 | |
806 | /* A register class without subclasses may contain a few | |
807 | hard registers and movement between them is costly | |
808 | (e.g. SPARC FPCC registers). We still should consider it | |
809 | as a candidate for a pressure class. */ | |
810 | && alloc_reg_class_subclasses[cl][0] < cl) | |
113a5be6 | 811 | { |
b4ff394c PH |
812 | /* Check that the moves between any hard registers of the |
813 | current class are not more expensive for a legal mode | |
814 | than load/store of the hard registers of the current | |
815 | class. Such class is a potential candidate to be a | |
816 | register pressure class. */ | |
817 | for (m = 0; m < NUM_MACHINE_MODES; m++) | |
818 | { | |
819 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); | |
820 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
821 | AND_COMPL_HARD_REG_SET (temp_hard_regset, | |
822 | ira_prohibited_class_mode_regs[cl][m]); | |
823 | if (hard_reg_set_empty_p (temp_hard_regset)) | |
824 | continue; | |
825 | ira_init_register_move_cost_if_necessary ((machine_mode) m); | |
826 | cost = ira_register_move_cost[m][cl][cl]; | |
827 | if (cost <= ira_max_memory_move_cost[m][cl][1] | |
828 | || cost <= ira_max_memory_move_cost[m][cl][0]) | |
829 | break; | |
830 | } | |
831 | if (m >= NUM_MACHINE_MODES) | |
113a5be6 | 832 | continue; |
113a5be6 | 833 | } |
b4ff394c PH |
834 | curr = 0; |
835 | insert_p = true; | |
836 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); | |
837 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
838 | /* Remove so far added pressure classes which are subset of the | |
839 | current candidate class. Prefer GENERAL_REGS as a pressure | |
840 | register class to another class containing the same | |
841 | allocatable hard registers. We do this because machine | |
842 | dependent cost hooks might give wrong costs for the latter | |
843 | class but always give the right cost for the former class | |
844 | (GENERAL_REGS). */ | |
845 | for (i = 0; i < n; i++) | |
1756cb66 | 846 | { |
b4ff394c PH |
847 | cl2 = pressure_classes[i]; |
848 | COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl2]); | |
849 | AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs); | |
850 | if (hard_reg_set_subset_p (temp_hard_regset, temp_hard_regset2) | |
851 | && (! hard_reg_set_equal_p (temp_hard_regset, | |
852 | temp_hard_regset2) | |
853 | || cl2 == (int) GENERAL_REGS)) | |
854 | { | |
855 | pressure_classes[curr++] = (enum reg_class) cl2; | |
856 | insert_p = false; | |
857 | continue; | |
858 | } | |
859 | if (hard_reg_set_subset_p (temp_hard_regset2, temp_hard_regset) | |
860 | && (! hard_reg_set_equal_p (temp_hard_regset2, | |
861 | temp_hard_regset) | |
862 | || cl == (int) GENERAL_REGS)) | |
863 | continue; | |
864 | if (hard_reg_set_equal_p (temp_hard_regset2, temp_hard_regset)) | |
865 | insert_p = false; | |
1756cb66 | 866 | pressure_classes[curr++] = (enum reg_class) cl2; |
1756cb66 | 867 | } |
b4ff394c PH |
868 | /* If the current candidate is a subset of a so far added |
869 | pressure class, don't add it to the list of the pressure | |
870 | classes. */ | |
871 | if (insert_p) | |
872 | pressure_classes[curr++] = (enum reg_class) cl; | |
873 | n = curr; | |
1756cb66 | 874 | } |
fe82cdfb | 875 | } |
1756cb66 | 876 | #ifdef ENABLE_IRA_CHECKING |
113a5be6 VM |
877 | { |
878 | HARD_REG_SET ignore_hard_regs; | |
879 | ||
880 | /* Check pressure classes correctness: here we check that hard | |
881 | registers from all register pressure classes contains all hard | |
882 | registers available for the allocation. */ | |
883 | CLEAR_HARD_REG_SET (temp_hard_regset); | |
884 | CLEAR_HARD_REG_SET (temp_hard_regset2); | |
885 | COPY_HARD_REG_SET (ignore_hard_regs, no_unit_alloc_regs); | |
886 | for (cl = 0; cl < LIM_REG_CLASSES; cl++) | |
887 | { | |
888 | /* For some targets (like MIPS with MD_REGS), there are some | |
889 | classes with hard registers available for allocation but | |
890 | not able to hold value of any mode. */ | |
891 | for (m = 0; m < NUM_MACHINE_MODES; m++) | |
892 | if (contains_reg_of_mode[cl][m]) | |
893 | break; | |
894 | if (m >= NUM_MACHINE_MODES) | |
895 | { | |
896 | IOR_HARD_REG_SET (ignore_hard_regs, reg_class_contents[cl]); | |
897 | continue; | |
898 | } | |
899 | for (i = 0; i < n; i++) | |
900 | if ((int) pressure_classes[i] == cl) | |
901 | break; | |
902 | IOR_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl]); | |
903 | if (i < n) | |
904 | IOR_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); | |
905 | } | |
906 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
df3e3493 | 907 | /* Some targets (like SPARC with ICC reg) have allocatable regs |
113a5be6 VM |
908 | for which no reg class is defined. */ |
909 | if (REGNO_REG_CLASS (i) == NO_REGS) | |
910 | SET_HARD_REG_BIT (ignore_hard_regs, i); | |
911 | AND_COMPL_HARD_REG_SET (temp_hard_regset, ignore_hard_regs); | |
912 | AND_COMPL_HARD_REG_SET (temp_hard_regset2, ignore_hard_regs); | |
913 | ira_assert (hard_reg_set_subset_p (temp_hard_regset2, temp_hard_regset)); | |
914 | } | |
1756cb66 VM |
915 | #endif |
916 | ira_pressure_classes_num = 0; | |
917 | for (i = 0; i < n; i++) | |
918 | { | |
919 | cl = (int) pressure_classes[i]; | |
920 | ira_reg_pressure_class_p[cl] = true; | |
921 | ira_pressure_classes[ira_pressure_classes_num++] = (enum reg_class) cl; | |
922 | } | |
923 | setup_stack_reg_pressure_class (); | |
058e97ec VM |
924 | } |
925 | ||
165f639c VM |
926 | /* Set up IRA_UNIFORM_CLASS_P. Uniform class is a register class |
927 | whose register move cost between any registers of the class is the | |
928 | same as for all its subclasses. We use the data to speed up the | |
929 | 2nd pass of calculations of allocno costs. */ | |
930 | static void | |
931 | setup_uniform_class_p (void) | |
932 | { | |
933 | int i, cl, cl2, m; | |
934 | ||
935 | for (cl = 0; cl < N_REG_CLASSES; cl++) | |
936 | { | |
937 | ira_uniform_class_p[cl] = false; | |
938 | if (ira_class_hard_regs_num[cl] == 0) | |
939 | continue; | |
940 | /* We can not use alloc_reg_class_subclasses here because move | |
941 | cost hooks does not take into account that some registers are | |
942 | unavailable for the subtarget. E.g. for i686, INT_SSE_REGS | |
943 | is element of alloc_reg_class_subclasses for GENERAL_REGS | |
944 | because SSE regs are unavailable. */ | |
945 | for (i = 0; (cl2 = reg_class_subclasses[cl][i]) != LIM_REG_CLASSES; i++) | |
946 | { | |
947 | if (ira_class_hard_regs_num[cl2] == 0) | |
948 | continue; | |
949 | for (m = 0; m < NUM_MACHINE_MODES; m++) | |
950 | if (contains_reg_of_mode[cl][m] && contains_reg_of_mode[cl2][m]) | |
951 | { | |
ef4bddc2 | 952 | ira_init_register_move_cost_if_necessary ((machine_mode) m); |
165f639c VM |
953 | if (ira_register_move_cost[m][cl][cl] |
954 | != ira_register_move_cost[m][cl2][cl2]) | |
955 | break; | |
956 | } | |
957 | if (m < NUM_MACHINE_MODES) | |
958 | break; | |
959 | } | |
960 | if (cl2 == LIM_REG_CLASSES) | |
961 | ira_uniform_class_p[cl] = true; | |
962 | } | |
963 | } | |
964 | ||
1756cb66 VM |
965 | /* Set up IRA_ALLOCNO_CLASSES, IRA_ALLOCNO_CLASSES_NUM, |
966 | IRA_IMPORTANT_CLASSES, and IRA_IMPORTANT_CLASSES_NUM. | |
967 | ||
df3e3493 | 968 | Target may have many subtargets and not all target hard registers can |
1756cb66 VM |
969 | be used for allocation, e.g. x86 port in 32-bit mode can not use |
970 | hard registers introduced in x86-64 like r8-r15). Some classes | |
971 | might have the same allocatable hard registers, e.g. INDEX_REGS | |
972 | and GENERAL_REGS in x86 port in 32-bit mode. To decrease different | |
973 | calculations efforts we introduce allocno classes which contain | |
974 | unique non-empty sets of allocatable hard-registers. | |
975 | ||
976 | Pseudo class cost calculation in ira-costs.c is very expensive. | |
977 | Therefore we are trying to decrease number of classes involved in | |
978 | such calculation. Register classes used in the cost calculation | |
979 | are called important classes. They are allocno classes and other | |
980 | non-empty classes whose allocatable hard register sets are inside | |
981 | of an allocno class hard register set. From the first sight, it | |
982 | looks like that they are just allocno classes. It is not true. In | |
983 | example of x86-port in 32-bit mode, allocno classes will contain | |
984 | GENERAL_REGS but not LEGACY_REGS (because allocatable hard | |
985 | registers are the same for the both classes). The important | |
986 | classes will contain GENERAL_REGS and LEGACY_REGS. It is done | |
987 | because a machine description insn constraint may refers for | |
988 | LEGACY_REGS and code in ira-costs.c is mostly base on investigation | |
989 | of the insn constraints. */ | |
058e97ec | 990 | static void |
1756cb66 | 991 | setup_allocno_and_important_classes (void) |
058e97ec | 992 | { |
32e8bb8e | 993 | int i, j, n, cl; |
db1a8d98 | 994 | bool set_p; |
058e97ec | 995 | HARD_REG_SET temp_hard_regset2; |
7db7ed3c VM |
996 | static enum reg_class classes[LIM_REG_CLASSES + 1]; |
997 | ||
1756cb66 VM |
998 | n = 0; |
999 | /* Collect classes which contain unique sets of allocatable hard | |
1000 | registers. Prefer GENERAL_REGS to other classes containing the | |
1001 | same set of hard registers. */ | |
a58dfa49 | 1002 | for (i = 0; i < LIM_REG_CLASSES; i++) |
99710245 | 1003 | { |
1756cb66 VM |
1004 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[i]); |
1005 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
1006 | for (j = 0; j < n; j++) | |
7db7ed3c | 1007 | { |
1756cb66 VM |
1008 | cl = classes[j]; |
1009 | COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl]); | |
1010 | AND_COMPL_HARD_REG_SET (temp_hard_regset2, | |
1011 | no_unit_alloc_regs); | |
1012 | if (hard_reg_set_equal_p (temp_hard_regset, | |
1013 | temp_hard_regset2)) | |
1014 | break; | |
7db7ed3c | 1015 | } |
e93f30a6 | 1016 | if (j >= n || targetm.additional_allocno_class_p (i)) |
1756cb66 VM |
1017 | classes[n++] = (enum reg_class) i; |
1018 | else if (i == GENERAL_REGS) | |
1019 | /* Prefer general regs. For i386 example, it means that | |
1020 | we prefer GENERAL_REGS over INDEX_REGS or LEGACY_REGS | |
1021 | (all of them consists of the same available hard | |
1022 | registers). */ | |
1023 | classes[j] = (enum reg_class) i; | |
7db7ed3c | 1024 | } |
1756cb66 | 1025 | classes[n] = LIM_REG_CLASSES; |
058e97ec | 1026 | |
1756cb66 | 1027 | /* Set up classes which can be used for allocnos as classes |
df3e3493 | 1028 | containing non-empty unique sets of allocatable hard |
1756cb66 VM |
1029 | registers. */ |
1030 | ira_allocno_classes_num = 0; | |
058e97ec | 1031 | for (i = 0; (cl = classes[i]) != LIM_REG_CLASSES; i++) |
3e575fe2 | 1032 | if (ira_class_hard_regs_num[cl] > 0) |
1756cb66 | 1033 | ira_allocno_classes[ira_allocno_classes_num++] = (enum reg_class) cl; |
058e97ec | 1034 | ira_important_classes_num = 0; |
1756cb66 VM |
1035 | /* Add non-allocno classes containing to non-empty set of |
1036 | allocatable hard regs. */ | |
058e97ec | 1037 | for (cl = 0; cl < N_REG_CLASSES; cl++) |
3e575fe2 RS |
1038 | if (ira_class_hard_regs_num[cl] > 0) |
1039 | { | |
1040 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); | |
1041 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
1042 | set_p = false; | |
1043 | for (j = 0; j < ira_allocno_classes_num; j++) | |
1044 | { | |
1045 | COPY_HARD_REG_SET (temp_hard_regset2, | |
1046 | reg_class_contents[ira_allocno_classes[j]]); | |
1047 | AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs); | |
1048 | if ((enum reg_class) cl == ira_allocno_classes[j]) | |
1049 | break; | |
1050 | else if (hard_reg_set_subset_p (temp_hard_regset, | |
1051 | temp_hard_regset2)) | |
1052 | set_p = true; | |
1053 | } | |
1054 | if (set_p && j >= ira_allocno_classes_num) | |
1055 | ira_important_classes[ira_important_classes_num++] | |
1056 | = (enum reg_class) cl; | |
1057 | } | |
1756cb66 VM |
1058 | /* Now add allocno classes to the important classes. */ |
1059 | for (j = 0; j < ira_allocno_classes_num; j++) | |
db1a8d98 | 1060 | ira_important_classes[ira_important_classes_num++] |
1756cb66 VM |
1061 | = ira_allocno_classes[j]; |
1062 | for (cl = 0; cl < N_REG_CLASSES; cl++) | |
1063 | { | |
1064 | ira_reg_allocno_class_p[cl] = false; | |
1065 | ira_reg_pressure_class_p[cl] = false; | |
1066 | } | |
1067 | for (j = 0; j < ira_allocno_classes_num; j++) | |
1068 | ira_reg_allocno_class_p[ira_allocno_classes[j]] = true; | |
1069 | setup_pressure_classes (); | |
165f639c | 1070 | setup_uniform_class_p (); |
058e97ec | 1071 | } |
058e97ec | 1072 | |
1756cb66 VM |
1073 | /* Setup translation in CLASS_TRANSLATE of all classes into a class |
1074 | given by array CLASSES of length CLASSES_NUM. The function is used | |
1075 | make translation any reg class to an allocno class or to an | |
1076 | pressure class. This translation is necessary for some | |
1077 | calculations when we can use only allocno or pressure classes and | |
1078 | such translation represents an approximate representation of all | |
1079 | classes. | |
1080 | ||
1081 | The translation in case when allocatable hard register set of a | |
1082 | given class is subset of allocatable hard register set of a class | |
1083 | in CLASSES is pretty simple. We use smallest classes from CLASSES | |
1084 | containing a given class. If allocatable hard register set of a | |
1085 | given class is not a subset of any corresponding set of a class | |
1086 | from CLASSES, we use the cheapest (with load/store point of view) | |
2b9c63a2 | 1087 | class from CLASSES whose set intersects with given class set. */ |
058e97ec | 1088 | static void |
1756cb66 VM |
1089 | setup_class_translate_array (enum reg_class *class_translate, |
1090 | int classes_num, enum reg_class *classes) | |
058e97ec | 1091 | { |
32e8bb8e | 1092 | int cl, mode; |
1756cb66 | 1093 | enum reg_class aclass, best_class, *cl_ptr; |
058e97ec VM |
1094 | int i, cost, min_cost, best_cost; |
1095 | ||
1096 | for (cl = 0; cl < N_REG_CLASSES; cl++) | |
1756cb66 | 1097 | class_translate[cl] = NO_REGS; |
b8698a0f | 1098 | |
1756cb66 | 1099 | for (i = 0; i < classes_num; i++) |
058e97ec | 1100 | { |
1756cb66 VM |
1101 | aclass = classes[i]; |
1102 | for (cl_ptr = &alloc_reg_class_subclasses[aclass][0]; | |
1103 | (cl = *cl_ptr) != LIM_REG_CLASSES; | |
1104 | cl_ptr++) | |
1105 | if (class_translate[cl] == NO_REGS) | |
1106 | class_translate[cl] = aclass; | |
1107 | class_translate[aclass] = aclass; | |
058e97ec | 1108 | } |
1756cb66 VM |
1109 | /* For classes which are not fully covered by one of given classes |
1110 | (in other words covered by more one given class), use the | |
1111 | cheapest class. */ | |
058e97ec VM |
1112 | for (cl = 0; cl < N_REG_CLASSES; cl++) |
1113 | { | |
1756cb66 | 1114 | if (cl == NO_REGS || class_translate[cl] != NO_REGS) |
058e97ec VM |
1115 | continue; |
1116 | best_class = NO_REGS; | |
1117 | best_cost = INT_MAX; | |
1756cb66 | 1118 | for (i = 0; i < classes_num; i++) |
058e97ec | 1119 | { |
1756cb66 | 1120 | aclass = classes[i]; |
058e97ec | 1121 | COPY_HARD_REG_SET (temp_hard_regset, |
1756cb66 | 1122 | reg_class_contents[aclass]); |
058e97ec VM |
1123 | AND_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); |
1124 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
4f341ea0 | 1125 | if (! hard_reg_set_empty_p (temp_hard_regset)) |
058e97ec VM |
1126 | { |
1127 | min_cost = INT_MAX; | |
1128 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
1129 | { | |
761a8eb7 VM |
1130 | cost = (ira_memory_move_cost[mode][aclass][0] |
1131 | + ira_memory_move_cost[mode][aclass][1]); | |
058e97ec VM |
1132 | if (min_cost > cost) |
1133 | min_cost = cost; | |
1134 | } | |
1135 | if (best_class == NO_REGS || best_cost > min_cost) | |
1136 | { | |
1756cb66 | 1137 | best_class = aclass; |
058e97ec VM |
1138 | best_cost = min_cost; |
1139 | } | |
1140 | } | |
1141 | } | |
1756cb66 | 1142 | class_translate[cl] = best_class; |
058e97ec VM |
1143 | } |
1144 | } | |
058e97ec | 1145 | |
1756cb66 VM |
1146 | /* Set up array IRA_ALLOCNO_CLASS_TRANSLATE and |
1147 | IRA_PRESSURE_CLASS_TRANSLATE. */ | |
1148 | static void | |
1149 | setup_class_translate (void) | |
1150 | { | |
1151 | setup_class_translate_array (ira_allocno_class_translate, | |
1152 | ira_allocno_classes_num, ira_allocno_classes); | |
1153 | setup_class_translate_array (ira_pressure_class_translate, | |
1154 | ira_pressure_classes_num, ira_pressure_classes); | |
1155 | } | |
1156 | ||
1157 | /* Order numbers of allocno classes in original target allocno class | |
1158 | array, -1 for non-allocno classes. */ | |
1159 | static int allocno_class_order[N_REG_CLASSES]; | |
db1a8d98 VM |
1160 | |
1161 | /* The function used to sort the important classes. */ | |
1162 | static int | |
1163 | comp_reg_classes_func (const void *v1p, const void *v2p) | |
1164 | { | |
1165 | enum reg_class cl1 = *(const enum reg_class *) v1p; | |
1166 | enum reg_class cl2 = *(const enum reg_class *) v2p; | |
1756cb66 | 1167 | enum reg_class tcl1, tcl2; |
db1a8d98 VM |
1168 | int diff; |
1169 | ||
1756cb66 VM |
1170 | tcl1 = ira_allocno_class_translate[cl1]; |
1171 | tcl2 = ira_allocno_class_translate[cl2]; | |
1172 | if (tcl1 != NO_REGS && tcl2 != NO_REGS | |
1173 | && (diff = allocno_class_order[tcl1] - allocno_class_order[tcl2]) != 0) | |
db1a8d98 VM |
1174 | return diff; |
1175 | return (int) cl1 - (int) cl2; | |
1176 | } | |
1177 | ||
1756cb66 VM |
1178 | /* For correct work of function setup_reg_class_relation we need to |
1179 | reorder important classes according to the order of their allocno | |
1180 | classes. It places important classes containing the same | |
1181 | allocatable hard register set adjacent to each other and allocno | |
1182 | class with the allocatable hard register set right after the other | |
1183 | important classes with the same set. | |
1184 | ||
1185 | In example from comments of function | |
1186 | setup_allocno_and_important_classes, it places LEGACY_REGS and | |
1187 | GENERAL_REGS close to each other and GENERAL_REGS is after | |
1188 | LEGACY_REGS. */ | |
db1a8d98 VM |
1189 | static void |
1190 | reorder_important_classes (void) | |
1191 | { | |
1192 | int i; | |
1193 | ||
1194 | for (i = 0; i < N_REG_CLASSES; i++) | |
1756cb66 VM |
1195 | allocno_class_order[i] = -1; |
1196 | for (i = 0; i < ira_allocno_classes_num; i++) | |
1197 | allocno_class_order[ira_allocno_classes[i]] = i; | |
db1a8d98 VM |
1198 | qsort (ira_important_classes, ira_important_classes_num, |
1199 | sizeof (enum reg_class), comp_reg_classes_func); | |
1756cb66 VM |
1200 | for (i = 0; i < ira_important_classes_num; i++) |
1201 | ira_important_class_nums[ira_important_classes[i]] = i; | |
db1a8d98 VM |
1202 | } |
1203 | ||
1756cb66 VM |
1204 | /* Set up IRA_REG_CLASS_SUBUNION, IRA_REG_CLASS_SUPERUNION, |
1205 | IRA_REG_CLASS_SUPER_CLASSES, IRA_REG_CLASSES_INTERSECT, and | |
1206 | IRA_REG_CLASSES_INTERSECT_P. For the meaning of the relations, | |
1207 | please see corresponding comments in ira-int.h. */ | |
058e97ec | 1208 | static void |
7db7ed3c | 1209 | setup_reg_class_relations (void) |
058e97ec VM |
1210 | { |
1211 | int i, cl1, cl2, cl3; | |
1212 | HARD_REG_SET intersection_set, union_set, temp_set2; | |
7db7ed3c | 1213 | bool important_class_p[N_REG_CLASSES]; |
058e97ec | 1214 | |
7db7ed3c VM |
1215 | memset (important_class_p, 0, sizeof (important_class_p)); |
1216 | for (i = 0; i < ira_important_classes_num; i++) | |
1217 | important_class_p[ira_important_classes[i]] = true; | |
058e97ec VM |
1218 | for (cl1 = 0; cl1 < N_REG_CLASSES; cl1++) |
1219 | { | |
7db7ed3c | 1220 | ira_reg_class_super_classes[cl1][0] = LIM_REG_CLASSES; |
058e97ec VM |
1221 | for (cl2 = 0; cl2 < N_REG_CLASSES; cl2++) |
1222 | { | |
7db7ed3c | 1223 | ira_reg_classes_intersect_p[cl1][cl2] = false; |
058e97ec | 1224 | ira_reg_class_intersect[cl1][cl2] = NO_REGS; |
55a2c322 | 1225 | ira_reg_class_subset[cl1][cl2] = NO_REGS; |
058e97ec VM |
1226 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl1]); |
1227 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
1228 | COPY_HARD_REG_SET (temp_set2, reg_class_contents[cl2]); | |
1229 | AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs); | |
4f341ea0 RS |
1230 | if (hard_reg_set_empty_p (temp_hard_regset) |
1231 | && hard_reg_set_empty_p (temp_set2)) | |
058e97ec | 1232 | { |
1756cb66 VM |
1233 | /* The both classes have no allocatable hard registers |
1234 | -- take all class hard registers into account and use | |
1235 | reg_class_subunion and reg_class_superunion. */ | |
058e97ec VM |
1236 | for (i = 0;; i++) |
1237 | { | |
1238 | cl3 = reg_class_subclasses[cl1][i]; | |
1239 | if (cl3 == LIM_REG_CLASSES) | |
1240 | break; | |
1241 | if (reg_class_subset_p (ira_reg_class_intersect[cl1][cl2], | |
bbbbb16a ILT |
1242 | (enum reg_class) cl3)) |
1243 | ira_reg_class_intersect[cl1][cl2] = (enum reg_class) cl3; | |
058e97ec | 1244 | } |
1756cb66 VM |
1245 | ira_reg_class_subunion[cl1][cl2] = reg_class_subunion[cl1][cl2]; |
1246 | ira_reg_class_superunion[cl1][cl2] = reg_class_superunion[cl1][cl2]; | |
058e97ec VM |
1247 | continue; |
1248 | } | |
7db7ed3c VM |
1249 | ira_reg_classes_intersect_p[cl1][cl2] |
1250 | = hard_reg_set_intersect_p (temp_hard_regset, temp_set2); | |
1251 | if (important_class_p[cl1] && important_class_p[cl2] | |
1252 | && hard_reg_set_subset_p (temp_hard_regset, temp_set2)) | |
1253 | { | |
1756cb66 VM |
1254 | /* CL1 and CL2 are important classes and CL1 allocatable |
1255 | hard register set is inside of CL2 allocatable hard | |
1256 | registers -- make CL1 a superset of CL2. */ | |
7db7ed3c VM |
1257 | enum reg_class *p; |
1258 | ||
1259 | p = &ira_reg_class_super_classes[cl1][0]; | |
1260 | while (*p != LIM_REG_CLASSES) | |
1261 | p++; | |
1262 | *p++ = (enum reg_class) cl2; | |
1263 | *p = LIM_REG_CLASSES; | |
1264 | } | |
1756cb66 VM |
1265 | ira_reg_class_subunion[cl1][cl2] = NO_REGS; |
1266 | ira_reg_class_superunion[cl1][cl2] = NO_REGS; | |
058e97ec VM |
1267 | COPY_HARD_REG_SET (intersection_set, reg_class_contents[cl1]); |
1268 | AND_HARD_REG_SET (intersection_set, reg_class_contents[cl2]); | |
1269 | AND_COMPL_HARD_REG_SET (intersection_set, no_unit_alloc_regs); | |
1270 | COPY_HARD_REG_SET (union_set, reg_class_contents[cl1]); | |
1271 | IOR_HARD_REG_SET (union_set, reg_class_contents[cl2]); | |
1272 | AND_COMPL_HARD_REG_SET (union_set, no_unit_alloc_regs); | |
55a2c322 | 1273 | for (cl3 = 0; cl3 < N_REG_CLASSES; cl3++) |
058e97ec | 1274 | { |
058e97ec VM |
1275 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl3]); |
1276 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
1277 | if (hard_reg_set_subset_p (temp_hard_regset, intersection_set)) | |
1278 | { | |
1756cb66 VM |
1279 | /* CL3 allocatable hard register set is inside of |
1280 | intersection of allocatable hard register sets | |
1281 | of CL1 and CL2. */ | |
55a2c322 VM |
1282 | if (important_class_p[cl3]) |
1283 | { | |
1284 | COPY_HARD_REG_SET | |
1285 | (temp_set2, | |
1286 | reg_class_contents | |
1287 | [(int) ira_reg_class_intersect[cl1][cl2]]); | |
1288 | AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs); | |
1289 | if (! hard_reg_set_subset_p (temp_hard_regset, temp_set2) | |
1290 | /* If the allocatable hard register sets are | |
1291 | the same, prefer GENERAL_REGS or the | |
1292 | smallest class for debugging | |
1293 | purposes. */ | |
1294 | || (hard_reg_set_equal_p (temp_hard_regset, temp_set2) | |
1295 | && (cl3 == GENERAL_REGS | |
1296 | || ((ira_reg_class_intersect[cl1][cl2] | |
1297 | != GENERAL_REGS) | |
1298 | && hard_reg_set_subset_p | |
1299 | (reg_class_contents[cl3], | |
1300 | reg_class_contents | |
1301 | [(int) | |
1302 | ira_reg_class_intersect[cl1][cl2]]))))) | |
1303 | ira_reg_class_intersect[cl1][cl2] = (enum reg_class) cl3; | |
1304 | } | |
058e97ec VM |
1305 | COPY_HARD_REG_SET |
1306 | (temp_set2, | |
55a2c322 | 1307 | reg_class_contents[(int) ira_reg_class_subset[cl1][cl2]]); |
058e97ec | 1308 | AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs); |
55a2c322 VM |
1309 | if (! hard_reg_set_subset_p (temp_hard_regset, temp_set2) |
1310 | /* Ignore unavailable hard registers and prefer | |
1311 | smallest class for debugging purposes. */ | |
058e97ec | 1312 | || (hard_reg_set_equal_p (temp_hard_regset, temp_set2) |
55a2c322 VM |
1313 | && hard_reg_set_subset_p |
1314 | (reg_class_contents[cl3], | |
1315 | reg_class_contents | |
1316 | [(int) ira_reg_class_subset[cl1][cl2]]))) | |
1317 | ira_reg_class_subset[cl1][cl2] = (enum reg_class) cl3; | |
058e97ec | 1318 | } |
55a2c322 VM |
1319 | if (important_class_p[cl3] |
1320 | && hard_reg_set_subset_p (temp_hard_regset, union_set)) | |
058e97ec | 1321 | { |
df3e3493 | 1322 | /* CL3 allocatable hard register set is inside of |
1756cb66 VM |
1323 | union of allocatable hard register sets of CL1 |
1324 | and CL2. */ | |
058e97ec VM |
1325 | COPY_HARD_REG_SET |
1326 | (temp_set2, | |
1756cb66 | 1327 | reg_class_contents[(int) ira_reg_class_subunion[cl1][cl2]]); |
058e97ec | 1328 | AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs); |
1756cb66 | 1329 | if (ira_reg_class_subunion[cl1][cl2] == NO_REGS |
058e97ec | 1330 | || (hard_reg_set_subset_p (temp_set2, temp_hard_regset) |
1756cb66 VM |
1331 | |
1332 | && (! hard_reg_set_equal_p (temp_set2, | |
1333 | temp_hard_regset) | |
1334 | || cl3 == GENERAL_REGS | |
1335 | /* If the allocatable hard register sets are the | |
1336 | same, prefer GENERAL_REGS or the smallest | |
1337 | class for debugging purposes. */ | |
1338 | || (ira_reg_class_subunion[cl1][cl2] != GENERAL_REGS | |
1339 | && hard_reg_set_subset_p | |
1340 | (reg_class_contents[cl3], | |
1341 | reg_class_contents | |
1342 | [(int) ira_reg_class_subunion[cl1][cl2]]))))) | |
1343 | ira_reg_class_subunion[cl1][cl2] = (enum reg_class) cl3; | |
1344 | } | |
1345 | if (hard_reg_set_subset_p (union_set, temp_hard_regset)) | |
1346 | { | |
1347 | /* CL3 allocatable hard register set contains union | |
1348 | of allocatable hard register sets of CL1 and | |
1349 | CL2. */ | |
1350 | COPY_HARD_REG_SET | |
1351 | (temp_set2, | |
1352 | reg_class_contents[(int) ira_reg_class_superunion[cl1][cl2]]); | |
1353 | AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs); | |
1354 | if (ira_reg_class_superunion[cl1][cl2] == NO_REGS | |
1355 | || (hard_reg_set_subset_p (temp_hard_regset, temp_set2) | |
b8698a0f | 1356 | |
058e97ec VM |
1357 | && (! hard_reg_set_equal_p (temp_set2, |
1358 | temp_hard_regset) | |
1756cb66 VM |
1359 | || cl3 == GENERAL_REGS |
1360 | /* If the allocatable hard register sets are the | |
1361 | same, prefer GENERAL_REGS or the smallest | |
1362 | class for debugging purposes. */ | |
1363 | || (ira_reg_class_superunion[cl1][cl2] != GENERAL_REGS | |
1364 | && hard_reg_set_subset_p | |
1365 | (reg_class_contents[cl3], | |
1366 | reg_class_contents | |
1367 | [(int) ira_reg_class_superunion[cl1][cl2]]))))) | |
1368 | ira_reg_class_superunion[cl1][cl2] = (enum reg_class) cl3; | |
058e97ec VM |
1369 | } |
1370 | } | |
1371 | } | |
1372 | } | |
1373 | } | |
1374 | ||
df3e3493 | 1375 | /* Output all uniform and important classes into file F. */ |
165f639c | 1376 | static void |
89e94470 | 1377 | print_uniform_and_important_classes (FILE *f) |
165f639c | 1378 | { |
165f639c VM |
1379 | int i, cl; |
1380 | ||
1381 | fprintf (f, "Uniform classes:\n"); | |
1382 | for (cl = 0; cl < N_REG_CLASSES; cl++) | |
1383 | if (ira_uniform_class_p[cl]) | |
1384 | fprintf (f, " %s", reg_class_names[cl]); | |
1385 | fprintf (f, "\nImportant classes:\n"); | |
1386 | for (i = 0; i < ira_important_classes_num; i++) | |
1387 | fprintf (f, " %s", reg_class_names[ira_important_classes[i]]); | |
1388 | fprintf (f, "\n"); | |
1389 | } | |
1390 | ||
1391 | /* Output all possible allocno or pressure classes and their | |
1392 | translation map into file F. */ | |
058e97ec | 1393 | static void |
165f639c | 1394 | print_translated_classes (FILE *f, bool pressure_p) |
1756cb66 VM |
1395 | { |
1396 | int classes_num = (pressure_p | |
1397 | ? ira_pressure_classes_num : ira_allocno_classes_num); | |
1398 | enum reg_class *classes = (pressure_p | |
1399 | ? ira_pressure_classes : ira_allocno_classes); | |
1400 | enum reg_class *class_translate = (pressure_p | |
1401 | ? ira_pressure_class_translate | |
1402 | : ira_allocno_class_translate); | |
058e97ec VM |
1403 | int i; |
1404 | ||
1756cb66 VM |
1405 | fprintf (f, "%s classes:\n", pressure_p ? "Pressure" : "Allocno"); |
1406 | for (i = 0; i < classes_num; i++) | |
1407 | fprintf (f, " %s", reg_class_names[classes[i]]); | |
058e97ec VM |
1408 | fprintf (f, "\nClass translation:\n"); |
1409 | for (i = 0; i < N_REG_CLASSES; i++) | |
1410 | fprintf (f, " %s -> %s\n", reg_class_names[i], | |
1756cb66 | 1411 | reg_class_names[class_translate[i]]); |
058e97ec VM |
1412 | } |
1413 | ||
1756cb66 VM |
1414 | /* Output all possible allocno and translation classes and the |
1415 | translation maps into stderr. */ | |
058e97ec | 1416 | void |
1756cb66 | 1417 | ira_debug_allocno_classes (void) |
058e97ec | 1418 | { |
89e94470 | 1419 | print_uniform_and_important_classes (stderr); |
165f639c VM |
1420 | print_translated_classes (stderr, false); |
1421 | print_translated_classes (stderr, true); | |
058e97ec VM |
1422 | } |
1423 | ||
1756cb66 | 1424 | /* Set up different arrays concerning class subsets, allocno and |
058e97ec VM |
1425 | important classes. */ |
1426 | static void | |
1756cb66 | 1427 | find_reg_classes (void) |
058e97ec | 1428 | { |
1756cb66 | 1429 | setup_allocno_and_important_classes (); |
7db7ed3c | 1430 | setup_class_translate (); |
db1a8d98 | 1431 | reorder_important_classes (); |
7db7ed3c | 1432 | setup_reg_class_relations (); |
058e97ec VM |
1433 | } |
1434 | ||
1435 | \f | |
1436 | ||
c0683a82 VM |
1437 | /* Set up the array above. */ |
1438 | static void | |
1756cb66 | 1439 | setup_hard_regno_aclass (void) |
c0683a82 | 1440 | { |
7efcf910 | 1441 | int i; |
c0683a82 VM |
1442 | |
1443 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1444 | { | |
1756cb66 VM |
1445 | #if 1 |
1446 | ira_hard_regno_allocno_class[i] | |
7efcf910 CLT |
1447 | = (TEST_HARD_REG_BIT (no_unit_alloc_regs, i) |
1448 | ? NO_REGS | |
1756cb66 VM |
1449 | : ira_allocno_class_translate[REGNO_REG_CLASS (i)]); |
1450 | #else | |
1451 | int j; | |
1452 | enum reg_class cl; | |
1453 | ira_hard_regno_allocno_class[i] = NO_REGS; | |
1454 | for (j = 0; j < ira_allocno_classes_num; j++) | |
1455 | { | |
1456 | cl = ira_allocno_classes[j]; | |
1457 | if (ira_class_hard_reg_index[cl][i] >= 0) | |
1458 | { | |
1459 | ira_hard_regno_allocno_class[i] = cl; | |
1460 | break; | |
1461 | } | |
1462 | } | |
1463 | #endif | |
c0683a82 VM |
1464 | } |
1465 | } | |
1466 | ||
1467 | \f | |
1468 | ||
1756cb66 | 1469 | /* Form IRA_REG_CLASS_MAX_NREGS and IRA_REG_CLASS_MIN_NREGS maps. */ |
058e97ec VM |
1470 | static void |
1471 | setup_reg_class_nregs (void) | |
1472 | { | |
1756cb66 | 1473 | int i, cl, cl2, m; |
058e97ec | 1474 | |
1756cb66 VM |
1475 | for (m = 0; m < MAX_MACHINE_MODE; m++) |
1476 | { | |
1477 | for (cl = 0; cl < N_REG_CLASSES; cl++) | |
1478 | ira_reg_class_max_nregs[cl][m] | |
1479 | = ira_reg_class_min_nregs[cl][m] | |
ef4bddc2 | 1480 | = targetm.class_max_nregs ((reg_class_t) cl, (machine_mode) m); |
1756cb66 VM |
1481 | for (cl = 0; cl < N_REG_CLASSES; cl++) |
1482 | for (i = 0; | |
1483 | (cl2 = alloc_reg_class_subclasses[cl][i]) != LIM_REG_CLASSES; | |
1484 | i++) | |
1485 | if (ira_reg_class_min_nregs[cl2][m] | |
1486 | < ira_reg_class_min_nregs[cl][m]) | |
1487 | ira_reg_class_min_nregs[cl][m] = ira_reg_class_min_nregs[cl2][m]; | |
1488 | } | |
058e97ec VM |
1489 | } |
1490 | ||
1491 | \f | |
1492 | ||
c9d74da6 RS |
1493 | /* Set up IRA_PROHIBITED_CLASS_MODE_REGS and IRA_CLASS_SINGLETON. |
1494 | This function is called once IRA_CLASS_HARD_REGS has been initialized. */ | |
058e97ec VM |
1495 | static void |
1496 | setup_prohibited_class_mode_regs (void) | |
1497 | { | |
c9d74da6 | 1498 | int j, k, hard_regno, cl, last_hard_regno, count; |
058e97ec | 1499 | |
1756cb66 | 1500 | for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) |
058e97ec | 1501 | { |
c9d74da6 RS |
1502 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); |
1503 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
058e97ec VM |
1504 | for (j = 0; j < NUM_MACHINE_MODES; j++) |
1505 | { | |
c9d74da6 RS |
1506 | count = 0; |
1507 | last_hard_regno = -1; | |
1756cb66 | 1508 | CLEAR_HARD_REG_SET (ira_prohibited_class_mode_regs[cl][j]); |
058e97ec VM |
1509 | for (k = ira_class_hard_regs_num[cl] - 1; k >= 0; k--) |
1510 | { | |
1511 | hard_regno = ira_class_hard_regs[cl][k]; | |
f939c3e6 | 1512 | if (!targetm.hard_regno_mode_ok (hard_regno, (machine_mode) j)) |
1756cb66 | 1513 | SET_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j], |
058e97ec | 1514 | hard_regno); |
c9d74da6 | 1515 | else if (in_hard_reg_set_p (temp_hard_regset, |
ef4bddc2 | 1516 | (machine_mode) j, hard_regno)) |
c9d74da6 RS |
1517 | { |
1518 | last_hard_regno = hard_regno; | |
1519 | count++; | |
1520 | } | |
058e97ec | 1521 | } |
c9d74da6 | 1522 | ira_class_singleton[cl][j] = (count == 1 ? last_hard_regno : -1); |
058e97ec VM |
1523 | } |
1524 | } | |
1525 | } | |
1526 | ||
1756cb66 VM |
1527 | /* Clarify IRA_PROHIBITED_CLASS_MODE_REGS by excluding hard registers |
1528 | spanning from one register pressure class to another one. It is | |
1529 | called after defining the pressure classes. */ | |
1530 | static void | |
1531 | clarify_prohibited_class_mode_regs (void) | |
1532 | { | |
1533 | int j, k, hard_regno, cl, pclass, nregs; | |
1534 | ||
1535 | for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) | |
1536 | for (j = 0; j < NUM_MACHINE_MODES; j++) | |
a2c19e93 RS |
1537 | { |
1538 | CLEAR_HARD_REG_SET (ira_useful_class_mode_regs[cl][j]); | |
1539 | for (k = ira_class_hard_regs_num[cl] - 1; k >= 0; k--) | |
1540 | { | |
1541 | hard_regno = ira_class_hard_regs[cl][k]; | |
1542 | if (TEST_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j], hard_regno)) | |
1543 | continue; | |
ad474626 | 1544 | nregs = hard_regno_nregs (hard_regno, (machine_mode) j); |
a2c19e93 | 1545 | if (hard_regno + nregs > FIRST_PSEUDO_REGISTER) |
1756cb66 VM |
1546 | { |
1547 | SET_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j], | |
1548 | hard_regno); | |
a2c19e93 | 1549 | continue; |
1756cb66 | 1550 | } |
a2c19e93 RS |
1551 | pclass = ira_pressure_class_translate[REGNO_REG_CLASS (hard_regno)]; |
1552 | for (nregs-- ;nregs >= 0; nregs--) | |
1553 | if (((enum reg_class) pclass | |
1554 | != ira_pressure_class_translate[REGNO_REG_CLASS | |
1555 | (hard_regno + nregs)])) | |
1556 | { | |
1557 | SET_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j], | |
1558 | hard_regno); | |
1559 | break; | |
1560 | } | |
1561 | if (!TEST_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j], | |
1562 | hard_regno)) | |
1563 | add_to_hard_reg_set (&ira_useful_class_mode_regs[cl][j], | |
ef4bddc2 | 1564 | (machine_mode) j, hard_regno); |
a2c19e93 RS |
1565 | } |
1566 | } | |
1756cb66 | 1567 | } |
058e97ec | 1568 | \f |
7cc61ee4 RS |
1569 | /* Allocate and initialize IRA_REGISTER_MOVE_COST, IRA_MAY_MOVE_IN_COST |
1570 | and IRA_MAY_MOVE_OUT_COST for MODE. */ | |
1571 | void | |
ef4bddc2 | 1572 | ira_init_register_move_cost (machine_mode mode) |
e80ccebc RS |
1573 | { |
1574 | static unsigned short last_move_cost[N_REG_CLASSES][N_REG_CLASSES]; | |
1575 | bool all_match = true; | |
ed9e2ed0 | 1576 | unsigned int cl1, cl2; |
e80ccebc | 1577 | |
7cc61ee4 RS |
1578 | ira_assert (ira_register_move_cost[mode] == NULL |
1579 | && ira_may_move_in_cost[mode] == NULL | |
1580 | && ira_may_move_out_cost[mode] == NULL); | |
ed9e2ed0 RS |
1581 | ira_assert (have_regs_of_mode[mode]); |
1582 | for (cl1 = 0; cl1 < N_REG_CLASSES; cl1++) | |
fef37404 VM |
1583 | for (cl2 = 0; cl2 < N_REG_CLASSES; cl2++) |
1584 | { | |
1585 | int cost; | |
1586 | if (!contains_reg_of_mode[cl1][mode] | |
1587 | || !contains_reg_of_mode[cl2][mode]) | |
1588 | { | |
1589 | if ((ira_reg_class_max_nregs[cl1][mode] | |
1590 | > ira_class_hard_regs_num[cl1]) | |
1591 | || (ira_reg_class_max_nregs[cl2][mode] | |
1592 | > ira_class_hard_regs_num[cl2])) | |
1593 | cost = 65535; | |
1594 | else | |
1595 | cost = (ira_memory_move_cost[mode][cl1][0] | |
1a788c05 | 1596 | + ira_memory_move_cost[mode][cl2][1]) * 2; |
fef37404 VM |
1597 | } |
1598 | else | |
1599 | { | |
1600 | cost = register_move_cost (mode, (enum reg_class) cl1, | |
1601 | (enum reg_class) cl2); | |
1602 | ira_assert (cost < 65535); | |
1603 | } | |
1604 | all_match &= (last_move_cost[cl1][cl2] == cost); | |
1605 | last_move_cost[cl1][cl2] = cost; | |
1606 | } | |
e80ccebc RS |
1607 | if (all_match && last_mode_for_init_move_cost != -1) |
1608 | { | |
7cc61ee4 RS |
1609 | ira_register_move_cost[mode] |
1610 | = ira_register_move_cost[last_mode_for_init_move_cost]; | |
1611 | ira_may_move_in_cost[mode] | |
1612 | = ira_may_move_in_cost[last_mode_for_init_move_cost]; | |
1613 | ira_may_move_out_cost[mode] | |
1614 | = ira_may_move_out_cost[last_mode_for_init_move_cost]; | |
e80ccebc RS |
1615 | return; |
1616 | } | |
ed9e2ed0 | 1617 | last_mode_for_init_move_cost = mode; |
7cc61ee4 RS |
1618 | ira_register_move_cost[mode] = XNEWVEC (move_table, N_REG_CLASSES); |
1619 | ira_may_move_in_cost[mode] = XNEWVEC (move_table, N_REG_CLASSES); | |
1620 | ira_may_move_out_cost[mode] = XNEWVEC (move_table, N_REG_CLASSES); | |
ed9e2ed0 | 1621 | for (cl1 = 0; cl1 < N_REG_CLASSES; cl1++) |
fef37404 VM |
1622 | for (cl2 = 0; cl2 < N_REG_CLASSES; cl2++) |
1623 | { | |
1624 | int cost; | |
1625 | enum reg_class *p1, *p2; | |
1626 | ||
1627 | if (last_move_cost[cl1][cl2] == 65535) | |
1628 | { | |
1629 | ira_register_move_cost[mode][cl1][cl2] = 65535; | |
1630 | ira_may_move_in_cost[mode][cl1][cl2] = 65535; | |
1631 | ira_may_move_out_cost[mode][cl1][cl2] = 65535; | |
1632 | } | |
1633 | else | |
1634 | { | |
1635 | cost = last_move_cost[cl1][cl2]; | |
1636 | ||
1637 | for (p2 = ®_class_subclasses[cl2][0]; | |
1638 | *p2 != LIM_REG_CLASSES; p2++) | |
1639 | if (ira_class_hard_regs_num[*p2] > 0 | |
1640 | && (ira_reg_class_max_nregs[*p2][mode] | |
1641 | <= ira_class_hard_regs_num[*p2])) | |
1642 | cost = MAX (cost, ira_register_move_cost[mode][cl1][*p2]); | |
1643 | ||
1644 | for (p1 = ®_class_subclasses[cl1][0]; | |
1645 | *p1 != LIM_REG_CLASSES; p1++) | |
1646 | if (ira_class_hard_regs_num[*p1] > 0 | |
1647 | && (ira_reg_class_max_nregs[*p1][mode] | |
1648 | <= ira_class_hard_regs_num[*p1])) | |
1649 | cost = MAX (cost, ira_register_move_cost[mode][*p1][cl2]); | |
1650 | ||
1651 | ira_assert (cost <= 65535); | |
1652 | ira_register_move_cost[mode][cl1][cl2] = cost; | |
1653 | ||
1654 | if (ira_class_subset_p[cl1][cl2]) | |
1655 | ira_may_move_in_cost[mode][cl1][cl2] = 0; | |
1656 | else | |
1657 | ira_may_move_in_cost[mode][cl1][cl2] = cost; | |
1658 | ||
1659 | if (ira_class_subset_p[cl2][cl1]) | |
1660 | ira_may_move_out_cost[mode][cl1][cl2] = 0; | |
1661 | else | |
1662 | ira_may_move_out_cost[mode][cl1][cl2] = cost; | |
1663 | } | |
1664 | } | |
058e97ec | 1665 | } |
fef37404 | 1666 | |
058e97ec VM |
1667 | \f |
1668 | ||
058e97ec VM |
1669 | /* This is called once during compiler work. It sets up |
1670 | different arrays whose values don't depend on the compiled | |
1671 | function. */ | |
1672 | void | |
1673 | ira_init_once (void) | |
1674 | { | |
058e97ec | 1675 | ira_init_costs_once (); |
55a2c322 | 1676 | lra_init_once (); |
23427d51 RL |
1677 | |
1678 | ira_use_lra_p = targetm.lra_p (); | |
058e97ec VM |
1679 | } |
1680 | ||
7cc61ee4 RS |
1681 | /* Free ira_max_register_move_cost, ira_may_move_in_cost and |
1682 | ira_may_move_out_cost for each mode. */ | |
19c708dc RS |
1683 | void |
1684 | target_ira_int::free_register_move_costs (void) | |
058e97ec | 1685 | { |
e80ccebc | 1686 | int mode, i; |
058e97ec | 1687 | |
e80ccebc RS |
1688 | /* Reset move_cost and friends, making sure we only free shared |
1689 | table entries once. */ | |
1690 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
19c708dc | 1691 | if (x_ira_register_move_cost[mode]) |
e80ccebc | 1692 | { |
7cc61ee4 | 1693 | for (i = 0; |
19c708dc RS |
1694 | i < mode && (x_ira_register_move_cost[i] |
1695 | != x_ira_register_move_cost[mode]); | |
7cc61ee4 | 1696 | i++) |
e80ccebc RS |
1697 | ; |
1698 | if (i == mode) | |
1699 | { | |
19c708dc RS |
1700 | free (x_ira_register_move_cost[mode]); |
1701 | free (x_ira_may_move_in_cost[mode]); | |
1702 | free (x_ira_may_move_out_cost[mode]); | |
e80ccebc RS |
1703 | } |
1704 | } | |
19c708dc RS |
1705 | memset (x_ira_register_move_cost, 0, sizeof x_ira_register_move_cost); |
1706 | memset (x_ira_may_move_in_cost, 0, sizeof x_ira_may_move_in_cost); | |
1707 | memset (x_ira_may_move_out_cost, 0, sizeof x_ira_may_move_out_cost); | |
e80ccebc | 1708 | last_mode_for_init_move_cost = -1; |
058e97ec VM |
1709 | } |
1710 | ||
19c708dc RS |
1711 | target_ira_int::~target_ira_int () |
1712 | { | |
1713 | free_ira_costs (); | |
1714 | free_register_move_costs (); | |
1715 | } | |
1716 | ||
058e97ec VM |
1717 | /* This is called every time when register related information is |
1718 | changed. */ | |
1719 | void | |
1720 | ira_init (void) | |
1721 | { | |
19c708dc | 1722 | this_target_ira_int->free_register_move_costs (); |
058e97ec VM |
1723 | setup_reg_mode_hard_regset (); |
1724 | setup_alloc_regs (flag_omit_frame_pointer != 0); | |
1725 | setup_class_subset_and_memory_move_costs (); | |
058e97ec VM |
1726 | setup_reg_class_nregs (); |
1727 | setup_prohibited_class_mode_regs (); | |
1756cb66 VM |
1728 | find_reg_classes (); |
1729 | clarify_prohibited_class_mode_regs (); | |
1730 | setup_hard_regno_aclass (); | |
058e97ec VM |
1731 | ira_init_costs (); |
1732 | } | |
1733 | ||
058e97ec | 1734 | \f |
15e7b94f RS |
1735 | #define ira_prohibited_mode_move_regs_initialized_p \ |
1736 | (this_target_ira_int->x_ira_prohibited_mode_move_regs_initialized_p) | |
058e97ec VM |
1737 | |
1738 | /* Set up IRA_PROHIBITED_MODE_MOVE_REGS. */ | |
1739 | static void | |
1740 | setup_prohibited_mode_move_regs (void) | |
1741 | { | |
1742 | int i, j; | |
647d790d DM |
1743 | rtx test_reg1, test_reg2, move_pat; |
1744 | rtx_insn *move_insn; | |
058e97ec VM |
1745 | |
1746 | if (ira_prohibited_mode_move_regs_initialized_p) | |
1747 | return; | |
1748 | ira_prohibited_mode_move_regs_initialized_p = true; | |
c3dc5e66 RS |
1749 | test_reg1 = gen_rtx_REG (word_mode, LAST_VIRTUAL_REGISTER + 1); |
1750 | test_reg2 = gen_rtx_REG (word_mode, LAST_VIRTUAL_REGISTER + 2); | |
f7df4a84 | 1751 | move_pat = gen_rtx_SET (test_reg1, test_reg2); |
ed8921dc | 1752 | move_insn = gen_rtx_INSN (VOIDmode, 0, 0, 0, move_pat, 0, -1, 0); |
058e97ec VM |
1753 | for (i = 0; i < NUM_MACHINE_MODES; i++) |
1754 | { | |
1755 | SET_HARD_REG_SET (ira_prohibited_mode_move_regs[i]); | |
1756 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
1757 | { | |
f939c3e6 | 1758 | if (!targetm.hard_regno_mode_ok (j, (machine_mode) i)) |
058e97ec | 1759 | continue; |
8deccbb7 RS |
1760 | set_mode_and_regno (test_reg1, (machine_mode) i, j); |
1761 | set_mode_and_regno (test_reg2, (machine_mode) i, j); | |
058e97ec VM |
1762 | INSN_CODE (move_insn) = -1; |
1763 | recog_memoized (move_insn); | |
1764 | if (INSN_CODE (move_insn) < 0) | |
1765 | continue; | |
1766 | extract_insn (move_insn); | |
daca1a96 RS |
1767 | /* We don't know whether the move will be in code that is optimized |
1768 | for size or speed, so consider all enabled alternatives. */ | |
1769 | if (! constrain_operands (1, get_enabled_alternatives (move_insn))) | |
058e97ec VM |
1770 | continue; |
1771 | CLEAR_HARD_REG_BIT (ira_prohibited_mode_move_regs[i], j); | |
1772 | } | |
1773 | } | |
1774 | } | |
1775 | ||
1776 | \f | |
1777 | ||
3b6d1699 VM |
1778 | /* Setup possible alternatives in ALTS for INSN. */ |
1779 | void | |
647d790d | 1780 | ira_setup_alts (rtx_insn *insn, HARD_REG_SET &alts) |
3b6d1699 VM |
1781 | { |
1782 | /* MAP nalt * nop -> start of constraints for given operand and | |
2b9c63a2 | 1783 | alternative. */ |
3b6d1699 VM |
1784 | static vec<const char *> insn_constraints; |
1785 | int nop, nalt; | |
1786 | bool curr_swapped; | |
1787 | const char *p; | |
3b6d1699 VM |
1788 | int commutative = -1; |
1789 | ||
1790 | extract_insn (insn); | |
9840b2fa | 1791 | alternative_mask preferred = get_preferred_alternatives (insn); |
3b6d1699 VM |
1792 | CLEAR_HARD_REG_SET (alts); |
1793 | insn_constraints.release (); | |
1794 | insn_constraints.safe_grow_cleared (recog_data.n_operands | |
1795 | * recog_data.n_alternatives + 1); | |
1796 | /* Check that the hard reg set is enough for holding all | |
1797 | alternatives. It is hard to imagine the situation when the | |
1798 | assertion is wrong. */ | |
1799 | ira_assert (recog_data.n_alternatives | |
1800 | <= (int) MAX (sizeof (HARD_REG_ELT_TYPE) * CHAR_BIT, | |
1801 | FIRST_PSEUDO_REGISTER)); | |
1802 | for (curr_swapped = false;; curr_swapped = true) | |
1803 | { | |
1804 | /* Calculate some data common for all alternatives to speed up the | |
1805 | function. */ | |
1806 | for (nop = 0; nop < recog_data.n_operands; nop++) | |
1807 | { | |
1808 | for (nalt = 0, p = recog_data.constraints[nop]; | |
1809 | nalt < recog_data.n_alternatives; | |
1810 | nalt++) | |
1811 | { | |
1812 | insn_constraints[nop * recog_data.n_alternatives + nalt] = p; | |
1813 | while (*p && *p != ',') | |
3f12f020 AK |
1814 | { |
1815 | /* We only support one commutative marker, the first | |
1816 | one. We already set commutative above. */ | |
1817 | if (*p == '%' && commutative < 0) | |
1818 | commutative = nop; | |
1819 | p++; | |
1820 | } | |
3b6d1699 VM |
1821 | if (*p) |
1822 | p++; | |
1823 | } | |
1824 | } | |
1825 | for (nalt = 0; nalt < recog_data.n_alternatives; nalt++) | |
1826 | { | |
9840b2fa | 1827 | if (!TEST_BIT (preferred, nalt) |
4cc8d9d2 | 1828 | || TEST_HARD_REG_BIT (alts, nalt)) |
3b6d1699 VM |
1829 | continue; |
1830 | ||
1831 | for (nop = 0; nop < recog_data.n_operands; nop++) | |
1832 | { | |
1833 | int c, len; | |
1834 | ||
fab27f52 | 1835 | rtx op = recog_data.operand[nop]; |
3b6d1699 VM |
1836 | p = insn_constraints[nop * recog_data.n_alternatives + nalt]; |
1837 | if (*p == 0 || *p == ',') | |
1838 | continue; | |
1839 | ||
1840 | do | |
1841 | switch (c = *p, len = CONSTRAINT_LEN (c, p), c) | |
1842 | { | |
1843 | case '#': | |
1844 | case ',': | |
1845 | c = '\0'; | |
191816a3 | 1846 | /* FALLTHRU */ |
3b6d1699 VM |
1847 | case '\0': |
1848 | len = 0; | |
1849 | break; | |
1850 | ||
3b6d1699 | 1851 | case '%': |
3f12f020 | 1852 | /* The commutative modifier is handled above. */ |
3b6d1699 VM |
1853 | break; |
1854 | ||
3b6d1699 VM |
1855 | case '0': case '1': case '2': case '3': case '4': |
1856 | case '5': case '6': case '7': case '8': case '9': | |
1857 | goto op_success; | |
1858 | break; | |
1859 | ||
3b6d1699 | 1860 | case 'g': |
3b6d1699 VM |
1861 | goto op_success; |
1862 | break; | |
1863 | ||
1864 | default: | |
1865 | { | |
777e635f RS |
1866 | enum constraint_num cn = lookup_constraint (p); |
1867 | switch (get_constraint_type (cn)) | |
1868 | { | |
1869 | case CT_REGISTER: | |
1870 | if (reg_class_for_constraint (cn) != NO_REGS) | |
1871 | goto op_success; | |
1872 | break; | |
1873 | ||
d9c35eee RS |
1874 | case CT_CONST_INT: |
1875 | if (CONST_INT_P (op) | |
1876 | && (insn_const_int_ok_for_constraint | |
1877 | (INTVAL (op), cn))) | |
1878 | goto op_success; | |
1879 | break; | |
1880 | ||
777e635f RS |
1881 | case CT_ADDRESS: |
1882 | case CT_MEMORY: | |
9eb1ca69 | 1883 | case CT_SPECIAL_MEMORY: |
777e635f RS |
1884 | goto op_success; |
1885 | ||
1886 | case CT_FIXED_FORM: | |
1887 | if (constraint_satisfied_p (op, cn)) | |
1888 | goto op_success; | |
1889 | break; | |
1890 | } | |
3b6d1699 VM |
1891 | break; |
1892 | } | |
1893 | } | |
1894 | while (p += len, c); | |
1895 | break; | |
1896 | op_success: | |
1897 | ; | |
1898 | } | |
1899 | if (nop >= recog_data.n_operands) | |
1900 | SET_HARD_REG_BIT (alts, nalt); | |
1901 | } | |
1902 | if (commutative < 0) | |
1903 | break; | |
43f4a281 | 1904 | /* Swap forth and back to avoid changing recog_data. */ |
fab27f52 MM |
1905 | std::swap (recog_data.operand[commutative], |
1906 | recog_data.operand[commutative + 1]); | |
43f4a281 RB |
1907 | if (curr_swapped) |
1908 | break; | |
3b6d1699 VM |
1909 | } |
1910 | } | |
1911 | ||
1912 | /* Return the number of the output non-early clobber operand which | |
1913 | should be the same in any case as operand with number OP_NUM (or | |
1914 | negative value if there is no such operand). The function takes | |
1915 | only really possible alternatives into consideration. */ | |
1916 | int | |
1917 | ira_get_dup_out_num (int op_num, HARD_REG_SET &alts) | |
1918 | { | |
1919 | int curr_alt, c, original, dup; | |
1920 | bool ignore_p, use_commut_op_p; | |
1921 | const char *str; | |
3b6d1699 VM |
1922 | |
1923 | if (op_num < 0 || recog_data.n_alternatives == 0) | |
1924 | return -1; | |
98f2f031 RS |
1925 | /* We should find duplications only for input operands. */ |
1926 | if (recog_data.operand_type[op_num] != OP_IN) | |
1927 | return -1; | |
3b6d1699 | 1928 | str = recog_data.constraints[op_num]; |
98f2f031 | 1929 | use_commut_op_p = false; |
3b6d1699 VM |
1930 | for (;;) |
1931 | { | |
777e635f | 1932 | rtx op = recog_data.operand[op_num]; |
3b6d1699 | 1933 | |
98f2f031 RS |
1934 | for (curr_alt = 0, ignore_p = !TEST_HARD_REG_BIT (alts, curr_alt), |
1935 | original = -1;;) | |
3b6d1699 VM |
1936 | { |
1937 | c = *str; | |
1938 | if (c == '\0') | |
1939 | break; | |
98f2f031 | 1940 | if (c == '#') |
3b6d1699 VM |
1941 | ignore_p = true; |
1942 | else if (c == ',') | |
1943 | { | |
1944 | curr_alt++; | |
98f2f031 | 1945 | ignore_p = !TEST_HARD_REG_BIT (alts, curr_alt); |
3b6d1699 VM |
1946 | } |
1947 | else if (! ignore_p) | |
1948 | switch (c) | |
1949 | { | |
3b6d1699 VM |
1950 | case 'g': |
1951 | goto fail; | |
8677664e | 1952 | default: |
3b6d1699 | 1953 | { |
777e635f RS |
1954 | enum constraint_num cn = lookup_constraint (str); |
1955 | enum reg_class cl = reg_class_for_constraint (cn); | |
1956 | if (cl != NO_REGS | |
1957 | && !targetm.class_likely_spilled_p (cl)) | |
1958 | goto fail; | |
1959 | if (constraint_satisfied_p (op, cn)) | |
3b6d1699 | 1960 | goto fail; |
3b6d1699 VM |
1961 | break; |
1962 | } | |
1963 | ||
1964 | case '0': case '1': case '2': case '3': case '4': | |
1965 | case '5': case '6': case '7': case '8': case '9': | |
1966 | if (original != -1 && original != c) | |
1967 | goto fail; | |
1968 | original = c; | |
1969 | break; | |
1970 | } | |
1971 | str += CONSTRAINT_LEN (c, str); | |
1972 | } | |
1973 | if (original == -1) | |
1974 | goto fail; | |
1975 | dup = -1; | |
1976 | for (ignore_p = false, str = recog_data.constraints[original - '0']; | |
1977 | *str != 0; | |
1978 | str++) | |
1979 | if (ignore_p) | |
1980 | { | |
1981 | if (*str == ',') | |
1982 | ignore_p = false; | |
1983 | } | |
1984 | else if (*str == '#') | |
1985 | ignore_p = true; | |
1986 | else if (! ignore_p) | |
1987 | { | |
1988 | if (*str == '=') | |
1989 | dup = original - '0'; | |
1990 | /* It is better ignore an alternative with early clobber. */ | |
1991 | else if (*str == '&') | |
1992 | goto fail; | |
1993 | } | |
1994 | if (dup >= 0) | |
1995 | return dup; | |
1996 | fail: | |
1997 | if (use_commut_op_p) | |
1998 | break; | |
1999 | use_commut_op_p = true; | |
73f793e3 | 2000 | if (recog_data.constraints[op_num][0] == '%') |
3b6d1699 | 2001 | str = recog_data.constraints[op_num + 1]; |
73f793e3 | 2002 | else if (op_num > 0 && recog_data.constraints[op_num - 1][0] == '%') |
3b6d1699 VM |
2003 | str = recog_data.constraints[op_num - 1]; |
2004 | else | |
2005 | break; | |
2006 | } | |
2007 | return -1; | |
2008 | } | |
2009 | ||
2010 | \f | |
2011 | ||
2012 | /* Search forward to see if the source register of a copy insn dies | |
2013 | before either it or the destination register is modified, but don't | |
2014 | scan past the end of the basic block. If so, we can replace the | |
2015 | source with the destination and let the source die in the copy | |
2016 | insn. | |
2017 | ||
2018 | This will reduce the number of registers live in that range and may | |
2019 | enable the destination and the source coalescing, thus often saving | |
2020 | one register in addition to a register-register copy. */ | |
2021 | ||
2022 | static void | |
2023 | decrease_live_ranges_number (void) | |
2024 | { | |
2025 | basic_block bb; | |
070a1983 | 2026 | rtx_insn *insn; |
7da26277 TS |
2027 | rtx set, src, dest, dest_death, note; |
2028 | rtx_insn *p, *q; | |
3b6d1699 VM |
2029 | int sregno, dregno; |
2030 | ||
2031 | if (! flag_expensive_optimizations) | |
2032 | return; | |
2033 | ||
2034 | if (ira_dump_file) | |
2035 | fprintf (ira_dump_file, "Starting decreasing number of live ranges...\n"); | |
2036 | ||
11cd3bed | 2037 | FOR_EACH_BB_FN (bb, cfun) |
3b6d1699 VM |
2038 | FOR_BB_INSNS (bb, insn) |
2039 | { | |
2040 | set = single_set (insn); | |
2041 | if (! set) | |
2042 | continue; | |
2043 | src = SET_SRC (set); | |
2044 | dest = SET_DEST (set); | |
2045 | if (! REG_P (src) || ! REG_P (dest) | |
2046 | || find_reg_note (insn, REG_DEAD, src)) | |
2047 | continue; | |
2048 | sregno = REGNO (src); | |
2049 | dregno = REGNO (dest); | |
2050 | ||
2051 | /* We don't want to mess with hard regs if register classes | |
2052 | are small. */ | |
2053 | if (sregno == dregno | |
2054 | || (targetm.small_register_classes_for_mode_p (GET_MODE (src)) | |
2055 | && (sregno < FIRST_PSEUDO_REGISTER | |
2056 | || dregno < FIRST_PSEUDO_REGISTER)) | |
2057 | /* We don't see all updates to SP if they are in an | |
2058 | auto-inc memory reference, so we must disallow this | |
2059 | optimization on them. */ | |
2060 | || sregno == STACK_POINTER_REGNUM | |
2061 | || dregno == STACK_POINTER_REGNUM) | |
2062 | continue; | |
2063 | ||
2064 | dest_death = NULL_RTX; | |
2065 | ||
2066 | for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p)) | |
2067 | { | |
2068 | if (! INSN_P (p)) | |
2069 | continue; | |
2070 | if (BLOCK_FOR_INSN (p) != bb) | |
2071 | break; | |
2072 | ||
2073 | if (reg_set_p (src, p) || reg_set_p (dest, p) | |
2074 | /* If SRC is an asm-declared register, it must not be | |
2075 | replaced in any asm. Unfortunately, the REG_EXPR | |
2076 | tree for the asm variable may be absent in the SRC | |
2077 | rtx, so we can't check the actual register | |
2078 | declaration easily (the asm operand will have it, | |
2079 | though). To avoid complicating the test for a rare | |
2080 | case, we just don't perform register replacement | |
2081 | for a hard reg mentioned in an asm. */ | |
2082 | || (sregno < FIRST_PSEUDO_REGISTER | |
2083 | && asm_noperands (PATTERN (p)) >= 0 | |
2084 | && reg_overlap_mentioned_p (src, PATTERN (p))) | |
2085 | /* Don't change hard registers used by a call. */ | |
2086 | || (CALL_P (p) && sregno < FIRST_PSEUDO_REGISTER | |
2087 | && find_reg_fusage (p, USE, src)) | |
2088 | /* Don't change a USE of a register. */ | |
2089 | || (GET_CODE (PATTERN (p)) == USE | |
2090 | && reg_overlap_mentioned_p (src, XEXP (PATTERN (p), 0)))) | |
2091 | break; | |
2092 | ||
2093 | /* See if all of SRC dies in P. This test is slightly | |
2094 | more conservative than it needs to be. */ | |
2095 | if ((note = find_regno_note (p, REG_DEAD, sregno)) | |
2096 | && GET_MODE (XEXP (note, 0)) == GET_MODE (src)) | |
2097 | { | |
2098 | int failed = 0; | |
2099 | ||
2100 | /* We can do the optimization. Scan forward from INSN | |
2101 | again, replacing regs as we go. Set FAILED if a | |
2102 | replacement can't be done. In that case, we can't | |
2103 | move the death note for SRC. This should be | |
2104 | rare. */ | |
2105 | ||
2106 | /* Set to stop at next insn. */ | |
2107 | for (q = next_real_insn (insn); | |
2108 | q != next_real_insn (p); | |
2109 | q = next_real_insn (q)) | |
2110 | { | |
2111 | if (reg_overlap_mentioned_p (src, PATTERN (q))) | |
2112 | { | |
2113 | /* If SRC is a hard register, we might miss | |
2114 | some overlapping registers with | |
2115 | validate_replace_rtx, so we would have to | |
2116 | undo it. We can't if DEST is present in | |
2117 | the insn, so fail in that combination of | |
2118 | cases. */ | |
2119 | if (sregno < FIRST_PSEUDO_REGISTER | |
2120 | && reg_mentioned_p (dest, PATTERN (q))) | |
2121 | failed = 1; | |
2122 | ||
2123 | /* Attempt to replace all uses. */ | |
2124 | else if (!validate_replace_rtx (src, dest, q)) | |
2125 | failed = 1; | |
2126 | ||
2127 | /* If this succeeded, but some part of the | |
2128 | register is still present, undo the | |
2129 | replacement. */ | |
2130 | else if (sregno < FIRST_PSEUDO_REGISTER | |
2131 | && reg_overlap_mentioned_p (src, PATTERN (q))) | |
2132 | { | |
2133 | validate_replace_rtx (dest, src, q); | |
2134 | failed = 1; | |
2135 | } | |
2136 | } | |
2137 | ||
2138 | /* If DEST dies here, remove the death note and | |
2139 | save it for later. Make sure ALL of DEST dies | |
2140 | here; again, this is overly conservative. */ | |
2141 | if (! dest_death | |
2142 | && (dest_death = find_regno_note (q, REG_DEAD, dregno))) | |
2143 | { | |
2144 | if (GET_MODE (XEXP (dest_death, 0)) == GET_MODE (dest)) | |
2145 | remove_note (q, dest_death); | |
2146 | else | |
2147 | { | |
2148 | failed = 1; | |
2149 | dest_death = 0; | |
2150 | } | |
2151 | } | |
2152 | } | |
2153 | ||
2154 | if (! failed) | |
2155 | { | |
2156 | /* Move death note of SRC from P to INSN. */ | |
2157 | remove_note (p, note); | |
2158 | XEXP (note, 1) = REG_NOTES (insn); | |
2159 | REG_NOTES (insn) = note; | |
2160 | } | |
2161 | ||
2162 | /* DEST is also dead if INSN has a REG_UNUSED note for | |
2163 | DEST. */ | |
2164 | if (! dest_death | |
2165 | && (dest_death | |
2166 | = find_regno_note (insn, REG_UNUSED, dregno))) | |
2167 | { | |
2168 | PUT_REG_NOTE_KIND (dest_death, REG_DEAD); | |
2169 | remove_note (insn, dest_death); | |
2170 | } | |
2171 | ||
2172 | /* Put death note of DEST on P if we saw it die. */ | |
2173 | if (dest_death) | |
2174 | { | |
2175 | XEXP (dest_death, 1) = REG_NOTES (p); | |
2176 | REG_NOTES (p) = dest_death; | |
2177 | } | |
2178 | break; | |
2179 | } | |
2180 | ||
2181 | /* If SRC is a hard register which is set or killed in | |
2182 | some other way, we can't do this optimization. */ | |
2183 | else if (sregno < FIRST_PSEUDO_REGISTER && dead_or_set_p (p, src)) | |
2184 | break; | |
2185 | } | |
2186 | } | |
2187 | } | |
2188 | ||
2189 | \f | |
2190 | ||
0896cc66 JL |
2191 | /* Return nonzero if REGNO is a particularly bad choice for reloading X. */ |
2192 | static bool | |
2193 | ira_bad_reload_regno_1 (int regno, rtx x) | |
2194 | { | |
ac0ab4f7 | 2195 | int x_regno, n, i; |
0896cc66 JL |
2196 | ira_allocno_t a; |
2197 | enum reg_class pref; | |
2198 | ||
2199 | /* We only deal with pseudo regs. */ | |
2200 | if (! x || GET_CODE (x) != REG) | |
2201 | return false; | |
2202 | ||
2203 | x_regno = REGNO (x); | |
2204 | if (x_regno < FIRST_PSEUDO_REGISTER) | |
2205 | return false; | |
2206 | ||
2207 | /* If the pseudo prefers REGNO explicitly, then do not consider | |
2208 | REGNO a bad spill choice. */ | |
2209 | pref = reg_preferred_class (x_regno); | |
2210 | if (reg_class_size[pref] == 1) | |
2211 | return !TEST_HARD_REG_BIT (reg_class_contents[pref], regno); | |
2212 | ||
2213 | /* If the pseudo conflicts with REGNO, then we consider REGNO a | |
2214 | poor choice for a reload regno. */ | |
2215 | a = ira_regno_allocno_map[x_regno]; | |
ac0ab4f7 BS |
2216 | n = ALLOCNO_NUM_OBJECTS (a); |
2217 | for (i = 0; i < n; i++) | |
2218 | { | |
2219 | ira_object_t obj = ALLOCNO_OBJECT (a, i); | |
2220 | if (TEST_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), regno)) | |
2221 | return true; | |
2222 | } | |
0896cc66 JL |
2223 | return false; |
2224 | } | |
2225 | ||
2226 | /* Return nonzero if REGNO is a particularly bad choice for reloading | |
2227 | IN or OUT. */ | |
2228 | bool | |
2229 | ira_bad_reload_regno (int regno, rtx in, rtx out) | |
2230 | { | |
2231 | return (ira_bad_reload_regno_1 (regno, in) | |
2232 | || ira_bad_reload_regno_1 (regno, out)); | |
2233 | } | |
2234 | ||
b748fbd6 | 2235 | /* Add register clobbers from asm statements. */ |
058e97ec | 2236 | static void |
b748fbd6 | 2237 | compute_regs_asm_clobbered (void) |
058e97ec VM |
2238 | { |
2239 | basic_block bb; | |
2240 | ||
11cd3bed | 2241 | FOR_EACH_BB_FN (bb, cfun) |
058e97ec | 2242 | { |
070a1983 | 2243 | rtx_insn *insn; |
058e97ec VM |
2244 | FOR_BB_INSNS_REVERSE (bb, insn) |
2245 | { | |
bfac633a | 2246 | df_ref def; |
058e97ec | 2247 | |
93671519 | 2248 | if (NONDEBUG_INSN_P (insn) && asm_noperands (PATTERN (insn)) >= 0) |
bfac633a | 2249 | FOR_EACH_INSN_DEF (def, insn) |
058e97ec | 2250 | { |
058e97ec | 2251 | unsigned int dregno = DF_REF_REGNO (def); |
d108e679 AS |
2252 | if (HARD_REGISTER_NUM_P (dregno)) |
2253 | add_to_hard_reg_set (&crtl->asm_clobbers, | |
2254 | GET_MODE (DF_REF_REAL_REG (def)), | |
2255 | dregno); | |
058e97ec VM |
2256 | } |
2257 | } | |
2258 | } | |
2259 | } | |
2260 | ||
2261 | ||
8d49e7ef VM |
2262 | /* Set up ELIMINABLE_REGSET, IRA_NO_ALLOC_REGS, and |
2263 | REGS_EVER_LIVE. */ | |
ce18efcb | 2264 | void |
8d49e7ef | 2265 | ira_setup_eliminable_regset (void) |
058e97ec | 2266 | { |
89ceba31 | 2267 | int i; |
058e97ec | 2268 | static const struct {const int from, to; } eliminables[] = ELIMINABLE_REGS; |
53680238 | 2269 | |
0064f49e WD |
2270 | /* Setup is_leaf as frame_pointer_required may use it. This function |
2271 | is called by sched_init before ira if scheduling is enabled. */ | |
2272 | crtl->is_leaf = leaf_function_p (); | |
2273 | ||
058e97ec VM |
2274 | /* FIXME: If EXIT_IGNORE_STACK is set, we will not save and restore |
2275 | sp for alloca. So we can't eliminate the frame pointer in that | |
2276 | case. At some point, we should improve this by emitting the | |
2277 | sp-adjusting insns for this case. */ | |
55a2c322 | 2278 | frame_pointer_needed |
058e97ec VM |
2279 | = (! flag_omit_frame_pointer |
2280 | || (cfun->calls_alloca && EXIT_IGNORE_STACK) | |
7700cd85 EB |
2281 | /* We need the frame pointer to catch stack overflow exceptions if |
2282 | the stack pointer is moving (as for the alloca case just above). */ | |
2283 | || (STACK_CHECK_MOVING_SP | |
2284 | && flag_stack_check | |
2285 | && flag_exceptions | |
2286 | && cfun->can_throw_non_call_exceptions) | |
058e97ec | 2287 | || crtl->accesses_prior_frames |
8d49e7ef | 2288 | || (SUPPORTS_STACK_ALIGNMENT && crtl->stack_realign_needed) |
939b37da BI |
2289 | /* We need a frame pointer for all Cilk Plus functions that use |
2290 | Cilk keywords. */ | |
b72271b9 | 2291 | || (flag_cilkplus && cfun->is_cilk_function) |
b52b1749 | 2292 | || targetm.frame_pointer_required ()); |
058e97ec | 2293 | |
8d49e7ef VM |
2294 | /* The chance that FRAME_POINTER_NEEDED is changed from inspecting |
2295 | RTL is very small. So if we use frame pointer for RA and RTL | |
2296 | actually prevents this, we will spill pseudos assigned to the | |
2297 | frame pointer in LRA. */ | |
058e97ec | 2298 | |
55a2c322 VM |
2299 | if (frame_pointer_needed) |
2300 | df_set_regs_ever_live (HARD_FRAME_POINTER_REGNUM, true); | |
2301 | ||
058e97ec VM |
2302 | COPY_HARD_REG_SET (ira_no_alloc_regs, no_unit_alloc_regs); |
2303 | CLEAR_HARD_REG_SET (eliminable_regset); | |
2304 | ||
b748fbd6 PB |
2305 | compute_regs_asm_clobbered (); |
2306 | ||
058e97ec VM |
2307 | /* Build the regset of all eliminable registers and show we can't |
2308 | use those that we already know won't be eliminated. */ | |
058e97ec VM |
2309 | for (i = 0; i < (int) ARRAY_SIZE (eliminables); i++) |
2310 | { | |
2311 | bool cannot_elim | |
7b5cbb57 | 2312 | = (! targetm.can_eliminate (eliminables[i].from, eliminables[i].to) |
55a2c322 | 2313 | || (eliminables[i].to == STACK_POINTER_REGNUM && frame_pointer_needed)); |
058e97ec | 2314 | |
b748fbd6 | 2315 | if (!TEST_HARD_REG_BIT (crtl->asm_clobbers, eliminables[i].from)) |
058e97ec VM |
2316 | { |
2317 | SET_HARD_REG_BIT (eliminable_regset, eliminables[i].from); | |
2318 | ||
2319 | if (cannot_elim) | |
2320 | SET_HARD_REG_BIT (ira_no_alloc_regs, eliminables[i].from); | |
2321 | } | |
2322 | else if (cannot_elim) | |
2323 | error ("%s cannot be used in asm here", | |
2324 | reg_names[eliminables[i].from]); | |
2325 | else | |
2326 | df_set_regs_ever_live (eliminables[i].from, true); | |
2327 | } | |
c3e08036 | 2328 | if (!HARD_FRAME_POINTER_IS_FRAME_POINTER) |
058e97ec | 2329 | { |
c3e08036 TS |
2330 | if (!TEST_HARD_REG_BIT (crtl->asm_clobbers, HARD_FRAME_POINTER_REGNUM)) |
2331 | { | |
2332 | SET_HARD_REG_BIT (eliminable_regset, HARD_FRAME_POINTER_REGNUM); | |
2333 | if (frame_pointer_needed) | |
2334 | SET_HARD_REG_BIT (ira_no_alloc_regs, HARD_FRAME_POINTER_REGNUM); | |
2335 | } | |
2336 | else if (frame_pointer_needed) | |
2337 | error ("%s cannot be used in asm here", | |
2338 | reg_names[HARD_FRAME_POINTER_REGNUM]); | |
2339 | else | |
2340 | df_set_regs_ever_live (HARD_FRAME_POINTER_REGNUM, true); | |
058e97ec | 2341 | } |
058e97ec VM |
2342 | } |
2343 | ||
2344 | \f | |
2345 | ||
2af2dbdc VM |
2346 | /* Vector of substitutions of register numbers, |
2347 | used to map pseudo regs into hardware regs. | |
2348 | This is set up as a result of register allocation. | |
2349 | Element N is the hard reg assigned to pseudo reg N, | |
2350 | or is -1 if no hard reg was assigned. | |
2351 | If N is a hard reg number, element N is N. */ | |
2352 | short *reg_renumber; | |
2353 | ||
058e97ec VM |
2354 | /* Set up REG_RENUMBER and CALLER_SAVE_NEEDED (used by reload) from |
2355 | the allocation found by IRA. */ | |
2356 | static void | |
2357 | setup_reg_renumber (void) | |
2358 | { | |
2359 | int regno, hard_regno; | |
2360 | ira_allocno_t a; | |
2361 | ira_allocno_iterator ai; | |
2362 | ||
2363 | caller_save_needed = 0; | |
2364 | FOR_EACH_ALLOCNO (a, ai) | |
2365 | { | |
55a2c322 VM |
2366 | if (ira_use_lra_p && ALLOCNO_CAP_MEMBER (a) != NULL) |
2367 | continue; | |
058e97ec VM |
2368 | /* There are no caps at this point. */ |
2369 | ira_assert (ALLOCNO_CAP_MEMBER (a) == NULL); | |
2370 | if (! ALLOCNO_ASSIGNED_P (a)) | |
2371 | /* It can happen if A is not referenced but partially anticipated | |
2372 | somewhere in a region. */ | |
2373 | ALLOCNO_ASSIGNED_P (a) = true; | |
2374 | ira_free_allocno_updated_costs (a); | |
2375 | hard_regno = ALLOCNO_HARD_REGNO (a); | |
1756cb66 | 2376 | regno = ALLOCNO_REGNO (a); |
058e97ec | 2377 | reg_renumber[regno] = (hard_regno < 0 ? -1 : hard_regno); |
1756cb66 | 2378 | if (hard_regno >= 0) |
058e97ec | 2379 | { |
1756cb66 VM |
2380 | int i, nwords; |
2381 | enum reg_class pclass; | |
2382 | ira_object_t obj; | |
2383 | ||
2384 | pclass = ira_pressure_class_translate[REGNO_REG_CLASS (hard_regno)]; | |
2385 | nwords = ALLOCNO_NUM_OBJECTS (a); | |
2386 | for (i = 0; i < nwords; i++) | |
2387 | { | |
2388 | obj = ALLOCNO_OBJECT (a, i); | |
2389 | IOR_COMPL_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), | |
2390 | reg_class_contents[pclass]); | |
2391 | } | |
2392 | if (ALLOCNO_CALLS_CROSSED_NUM (a) != 0 | |
9181a6e5 VM |
2393 | && ira_hard_reg_set_intersection_p (hard_regno, ALLOCNO_MODE (a), |
2394 | call_used_reg_set)) | |
1756cb66 VM |
2395 | { |
2396 | ira_assert (!optimize || flag_caller_saves | |
e384e6b5 BS |
2397 | || (ALLOCNO_CALLS_CROSSED_NUM (a) |
2398 | == ALLOCNO_CHEAP_CALLS_CROSSED_NUM (a)) | |
15652f68 | 2399 | || regno >= ira_reg_equiv_len |
55a2c322 | 2400 | || ira_equiv_no_lvalue_p (regno)); |
1756cb66 VM |
2401 | caller_save_needed = 1; |
2402 | } | |
058e97ec VM |
2403 | } |
2404 | } | |
2405 | } | |
2406 | ||
2407 | /* Set up allocno assignment flags for further allocation | |
2408 | improvements. */ | |
2409 | static void | |
2410 | setup_allocno_assignment_flags (void) | |
2411 | { | |
2412 | int hard_regno; | |
2413 | ira_allocno_t a; | |
2414 | ira_allocno_iterator ai; | |
2415 | ||
2416 | FOR_EACH_ALLOCNO (a, ai) | |
2417 | { | |
2418 | if (! ALLOCNO_ASSIGNED_P (a)) | |
2419 | /* It can happen if A is not referenced but partially anticipated | |
2420 | somewhere in a region. */ | |
2421 | ira_free_allocno_updated_costs (a); | |
2422 | hard_regno = ALLOCNO_HARD_REGNO (a); | |
2423 | /* Don't assign hard registers to allocnos which are destination | |
2424 | of removed store at the end of loop. It has no sense to keep | |
2425 | the same value in different hard registers. It is also | |
2426 | impossible to assign hard registers correctly to such | |
2427 | allocnos because the cost info and info about intersected | |
2428 | calls are incorrect for them. */ | |
2429 | ALLOCNO_ASSIGNED_P (a) = (hard_regno >= 0 | |
1756cb66 | 2430 | || ALLOCNO_EMIT_DATA (a)->mem_optimized_dest_p |
058e97ec | 2431 | || (ALLOCNO_MEMORY_COST (a) |
1756cb66 | 2432 | - ALLOCNO_CLASS_COST (a)) < 0); |
9181a6e5 VM |
2433 | ira_assert |
2434 | (hard_regno < 0 | |
2435 | || ira_hard_reg_in_set_p (hard_regno, ALLOCNO_MODE (a), | |
2436 | reg_class_contents[ALLOCNO_CLASS (a)])); | |
058e97ec VM |
2437 | } |
2438 | } | |
2439 | ||
2440 | /* Evaluate overall allocation cost and the costs for using hard | |
2441 | registers and memory for allocnos. */ | |
2442 | static void | |
2443 | calculate_allocation_cost (void) | |
2444 | { | |
2445 | int hard_regno, cost; | |
2446 | ira_allocno_t a; | |
2447 | ira_allocno_iterator ai; | |
2448 | ||
2449 | ira_overall_cost = ira_reg_cost = ira_mem_cost = 0; | |
2450 | FOR_EACH_ALLOCNO (a, ai) | |
2451 | { | |
2452 | hard_regno = ALLOCNO_HARD_REGNO (a); | |
2453 | ira_assert (hard_regno < 0 | |
9181a6e5 VM |
2454 | || (ira_hard_reg_in_set_p |
2455 | (hard_regno, ALLOCNO_MODE (a), | |
2456 | reg_class_contents[ALLOCNO_CLASS (a)]))); | |
058e97ec VM |
2457 | if (hard_regno < 0) |
2458 | { | |
2459 | cost = ALLOCNO_MEMORY_COST (a); | |
2460 | ira_mem_cost += cost; | |
2461 | } | |
2462 | else if (ALLOCNO_HARD_REG_COSTS (a) != NULL) | |
2463 | { | |
2464 | cost = (ALLOCNO_HARD_REG_COSTS (a) | |
2465 | [ira_class_hard_reg_index | |
1756cb66 | 2466 | [ALLOCNO_CLASS (a)][hard_regno]]); |
058e97ec VM |
2467 | ira_reg_cost += cost; |
2468 | } | |
2469 | else | |
2470 | { | |
1756cb66 | 2471 | cost = ALLOCNO_CLASS_COST (a); |
058e97ec VM |
2472 | ira_reg_cost += cost; |
2473 | } | |
2474 | ira_overall_cost += cost; | |
2475 | } | |
2476 | ||
2477 | if (internal_flag_ira_verbose > 0 && ira_dump_file != NULL) | |
2478 | { | |
2479 | fprintf (ira_dump_file, | |
16998094 JM |
2480 | "+++Costs: overall %" PRId64 |
2481 | ", reg %" PRId64 | |
2482 | ", mem %" PRId64 | |
2483 | ", ld %" PRId64 | |
2484 | ", st %" PRId64 | |
2485 | ", move %" PRId64, | |
058e97ec VM |
2486 | ira_overall_cost, ira_reg_cost, ira_mem_cost, |
2487 | ira_load_cost, ira_store_cost, ira_shuffle_cost); | |
2bf7560b | 2488 | fprintf (ira_dump_file, "\n+++ move loops %d, new jumps %d\n", |
058e97ec VM |
2489 | ira_move_loops_num, ira_additional_jumps_num); |
2490 | } | |
2491 | ||
2492 | } | |
2493 | ||
2494 | #ifdef ENABLE_IRA_CHECKING | |
2495 | /* Check the correctness of the allocation. We do need this because | |
2496 | of complicated code to transform more one region internal | |
2497 | representation into one region representation. */ | |
2498 | static void | |
2499 | check_allocation (void) | |
2500 | { | |
fa86d337 | 2501 | ira_allocno_t a; |
ac0ab4f7 | 2502 | int hard_regno, nregs, conflict_nregs; |
058e97ec VM |
2503 | ira_allocno_iterator ai; |
2504 | ||
2505 | FOR_EACH_ALLOCNO (a, ai) | |
2506 | { | |
ac0ab4f7 BS |
2507 | int n = ALLOCNO_NUM_OBJECTS (a); |
2508 | int i; | |
fa86d337 | 2509 | |
058e97ec VM |
2510 | if (ALLOCNO_CAP_MEMBER (a) != NULL |
2511 | || (hard_regno = ALLOCNO_HARD_REGNO (a)) < 0) | |
2512 | continue; | |
ad474626 | 2513 | nregs = hard_regno_nregs (hard_regno, ALLOCNO_MODE (a)); |
8cfd82bf BS |
2514 | if (nregs == 1) |
2515 | /* We allocated a single hard register. */ | |
2516 | n = 1; | |
2517 | else if (n > 1) | |
2518 | /* We allocated multiple hard registers, and we will test | |
2519 | conflicts in a granularity of single hard regs. */ | |
2520 | nregs = 1; | |
2521 | ||
ac0ab4f7 BS |
2522 | for (i = 0; i < n; i++) |
2523 | { | |
2524 | ira_object_t obj = ALLOCNO_OBJECT (a, i); | |
2525 | ira_object_t conflict_obj; | |
2526 | ira_object_conflict_iterator oci; | |
2527 | int this_regno = hard_regno; | |
2528 | if (n > 1) | |
fa86d337 | 2529 | { |
2805e6c0 | 2530 | if (REG_WORDS_BIG_ENDIAN) |
ac0ab4f7 BS |
2531 | this_regno += n - i - 1; |
2532 | else | |
2533 | this_regno += i; | |
2534 | } | |
2535 | FOR_EACH_OBJECT_CONFLICT (obj, conflict_obj, oci) | |
2536 | { | |
2537 | ira_allocno_t conflict_a = OBJECT_ALLOCNO (conflict_obj); | |
2538 | int conflict_hard_regno = ALLOCNO_HARD_REGNO (conflict_a); | |
2539 | if (conflict_hard_regno < 0) | |
2540 | continue; | |
8cfd82bf | 2541 | |
ad474626 RS |
2542 | conflict_nregs = hard_regno_nregs (conflict_hard_regno, |
2543 | ALLOCNO_MODE (conflict_a)); | |
8cfd82bf BS |
2544 | |
2545 | if (ALLOCNO_NUM_OBJECTS (conflict_a) > 1 | |
2546 | && conflict_nregs == ALLOCNO_NUM_OBJECTS (conflict_a)) | |
ac0ab4f7 | 2547 | { |
2805e6c0 | 2548 | if (REG_WORDS_BIG_ENDIAN) |
ac0ab4f7 BS |
2549 | conflict_hard_regno += (ALLOCNO_NUM_OBJECTS (conflict_a) |
2550 | - OBJECT_SUBWORD (conflict_obj) - 1); | |
2551 | else | |
2552 | conflict_hard_regno += OBJECT_SUBWORD (conflict_obj); | |
2553 | conflict_nregs = 1; | |
2554 | } | |
ac0ab4f7 BS |
2555 | |
2556 | if ((conflict_hard_regno <= this_regno | |
2557 | && this_regno < conflict_hard_regno + conflict_nregs) | |
2558 | || (this_regno <= conflict_hard_regno | |
2559 | && conflict_hard_regno < this_regno + nregs)) | |
fa86d337 BS |
2560 | { |
2561 | fprintf (stderr, "bad allocation for %d and %d\n", | |
2562 | ALLOCNO_REGNO (a), ALLOCNO_REGNO (conflict_a)); | |
2563 | gcc_unreachable (); | |
2564 | } | |
2565 | } | |
2566 | } | |
058e97ec VM |
2567 | } |
2568 | } | |
2569 | #endif | |
2570 | ||
55a2c322 VM |
2571 | /* Allocate REG_EQUIV_INIT. Set up it from IRA_REG_EQUIV which should |
2572 | be already calculated. */ | |
2573 | static void | |
2574 | setup_reg_equiv_init (void) | |
2575 | { | |
2576 | int i; | |
2577 | int max_regno = max_reg_num (); | |
2578 | ||
2579 | for (i = 0; i < max_regno; i++) | |
2580 | reg_equiv_init (i) = ira_reg_equiv[i].init_insns; | |
2581 | } | |
2582 | ||
2583 | /* Update equiv regno from movement of FROM_REGNO to TO_REGNO. INSNS | |
2584 | are insns which were generated for such movement. It is assumed | |
2585 | that FROM_REGNO and TO_REGNO always have the same value at the | |
2586 | point of any move containing such registers. This function is used | |
2587 | to update equiv info for register shuffles on the region borders | |
2588 | and for caller save/restore insns. */ | |
2589 | void | |
b32d5189 | 2590 | ira_update_equiv_info_by_shuffle_insn (int to_regno, int from_regno, rtx_insn *insns) |
55a2c322 | 2591 | { |
b32d5189 DM |
2592 | rtx_insn *insn; |
2593 | rtx x, note; | |
55a2c322 VM |
2594 | |
2595 | if (! ira_reg_equiv[from_regno].defined_p | |
2596 | && (! ira_reg_equiv[to_regno].defined_p | |
2597 | || ((x = ira_reg_equiv[to_regno].memory) != NULL_RTX | |
2598 | && ! MEM_READONLY_P (x)))) | |
5a107a0f | 2599 | return; |
55a2c322 VM |
2600 | insn = insns; |
2601 | if (NEXT_INSN (insn) != NULL_RTX) | |
2602 | { | |
2603 | if (! ira_reg_equiv[to_regno].defined_p) | |
2604 | { | |
2605 | ira_assert (ira_reg_equiv[to_regno].init_insns == NULL_RTX); | |
2606 | return; | |
2607 | } | |
2608 | ira_reg_equiv[to_regno].defined_p = false; | |
2609 | ira_reg_equiv[to_regno].memory | |
2610 | = ira_reg_equiv[to_regno].constant | |
2611 | = ira_reg_equiv[to_regno].invariant | |
0cc97fc5 | 2612 | = ira_reg_equiv[to_regno].init_insns = NULL; |
55a2c322 VM |
2613 | if (internal_flag_ira_verbose > 3 && ira_dump_file != NULL) |
2614 | fprintf (ira_dump_file, | |
2615 | " Invalidating equiv info for reg %d\n", to_regno); | |
2616 | return; | |
2617 | } | |
2618 | /* It is possible that FROM_REGNO still has no equivalence because | |
2619 | in shuffles to_regno<-from_regno and from_regno<-to_regno the 2nd | |
2620 | insn was not processed yet. */ | |
2621 | if (ira_reg_equiv[from_regno].defined_p) | |
2622 | { | |
2623 | ira_reg_equiv[to_regno].defined_p = true; | |
2624 | if ((x = ira_reg_equiv[from_regno].memory) != NULL_RTX) | |
2625 | { | |
2626 | ira_assert (ira_reg_equiv[from_regno].invariant == NULL_RTX | |
2627 | && ira_reg_equiv[from_regno].constant == NULL_RTX); | |
2628 | ira_assert (ira_reg_equiv[to_regno].memory == NULL_RTX | |
2629 | || rtx_equal_p (ira_reg_equiv[to_regno].memory, x)); | |
2630 | ira_reg_equiv[to_regno].memory = x; | |
2631 | if (! MEM_READONLY_P (x)) | |
2632 | /* We don't add the insn to insn init list because memory | |
2633 | equivalence is just to say what memory is better to use | |
2634 | when the pseudo is spilled. */ | |
2635 | return; | |
2636 | } | |
2637 | else if ((x = ira_reg_equiv[from_regno].constant) != NULL_RTX) | |
2638 | { | |
2639 | ira_assert (ira_reg_equiv[from_regno].invariant == NULL_RTX); | |
2640 | ira_assert (ira_reg_equiv[to_regno].constant == NULL_RTX | |
2641 | || rtx_equal_p (ira_reg_equiv[to_regno].constant, x)); | |
2642 | ira_reg_equiv[to_regno].constant = x; | |
2643 | } | |
2644 | else | |
2645 | { | |
2646 | x = ira_reg_equiv[from_regno].invariant; | |
2647 | ira_assert (x != NULL_RTX); | |
2648 | ira_assert (ira_reg_equiv[to_regno].invariant == NULL_RTX | |
2649 | || rtx_equal_p (ira_reg_equiv[to_regno].invariant, x)); | |
2650 | ira_reg_equiv[to_regno].invariant = x; | |
2651 | } | |
2652 | if (find_reg_note (insn, REG_EQUIV, x) == NULL_RTX) | |
2653 | { | |
2c797321 | 2654 | note = set_unique_reg_note (insn, REG_EQUIV, copy_rtx (x)); |
55a2c322 VM |
2655 | gcc_assert (note != NULL_RTX); |
2656 | if (internal_flag_ira_verbose > 3 && ira_dump_file != NULL) | |
2657 | { | |
2658 | fprintf (ira_dump_file, | |
2659 | " Adding equiv note to insn %u for reg %d ", | |
2660 | INSN_UID (insn), to_regno); | |
cfbeaedf | 2661 | dump_value_slim (ira_dump_file, x, 1); |
55a2c322 VM |
2662 | fprintf (ira_dump_file, "\n"); |
2663 | } | |
2664 | } | |
2665 | } | |
2666 | ira_reg_equiv[to_regno].init_insns | |
2667 | = gen_rtx_INSN_LIST (VOIDmode, insn, | |
2668 | ira_reg_equiv[to_regno].init_insns); | |
2669 | if (internal_flag_ira_verbose > 3 && ira_dump_file != NULL) | |
2670 | fprintf (ira_dump_file, | |
2671 | " Adding equiv init move insn %u to reg %d\n", | |
2672 | INSN_UID (insn), to_regno); | |
2673 | } | |
2674 | ||
058e97ec VM |
2675 | /* Fix values of array REG_EQUIV_INIT after live range splitting done |
2676 | by IRA. */ | |
2677 | static void | |
2678 | fix_reg_equiv_init (void) | |
2679 | { | |
70cc3288 | 2680 | int max_regno = max_reg_num (); |
f2034d06 | 2681 | int i, new_regno, max; |
618bccf9 TS |
2682 | rtx set; |
2683 | rtx_insn_list *x, *next, *prev; | |
2684 | rtx_insn *insn; | |
b8698a0f | 2685 | |
70cc3288 | 2686 | if (max_regno_before_ira < max_regno) |
058e97ec | 2687 | { |
9771b263 | 2688 | max = vec_safe_length (reg_equivs); |
f2034d06 JL |
2689 | grow_reg_equivs (); |
2690 | for (i = FIRST_PSEUDO_REGISTER; i < max; i++) | |
618bccf9 | 2691 | for (prev = NULL, x = reg_equiv_init (i); |
f2034d06 JL |
2692 | x != NULL_RTX; |
2693 | x = next) | |
058e97ec | 2694 | { |
618bccf9 TS |
2695 | next = x->next (); |
2696 | insn = x->insn (); | |
2697 | set = single_set (insn); | |
058e97ec VM |
2698 | ira_assert (set != NULL_RTX |
2699 | && (REG_P (SET_DEST (set)) || REG_P (SET_SRC (set)))); | |
2700 | if (REG_P (SET_DEST (set)) | |
2701 | && ((int) REGNO (SET_DEST (set)) == i | |
2702 | || (int) ORIGINAL_REGNO (SET_DEST (set)) == i)) | |
2703 | new_regno = REGNO (SET_DEST (set)); | |
2704 | else if (REG_P (SET_SRC (set)) | |
2705 | && ((int) REGNO (SET_SRC (set)) == i | |
2706 | || (int) ORIGINAL_REGNO (SET_SRC (set)) == i)) | |
2707 | new_regno = REGNO (SET_SRC (set)); | |
2708 | else | |
2709 | gcc_unreachable (); | |
2710 | if (new_regno == i) | |
2711 | prev = x; | |
2712 | else | |
2713 | { | |
55a2c322 | 2714 | /* Remove the wrong list element. */ |
058e97ec | 2715 | if (prev == NULL_RTX) |
f2034d06 | 2716 | reg_equiv_init (i) = next; |
058e97ec VM |
2717 | else |
2718 | XEXP (prev, 1) = next; | |
f2034d06 JL |
2719 | XEXP (x, 1) = reg_equiv_init (new_regno); |
2720 | reg_equiv_init (new_regno) = x; | |
058e97ec VM |
2721 | } |
2722 | } | |
2723 | } | |
2724 | } | |
2725 | ||
2726 | #ifdef ENABLE_IRA_CHECKING | |
2727 | /* Print redundant memory-memory copies. */ | |
2728 | static void | |
2729 | print_redundant_copies (void) | |
2730 | { | |
2731 | int hard_regno; | |
2732 | ira_allocno_t a; | |
2733 | ira_copy_t cp, next_cp; | |
2734 | ira_allocno_iterator ai; | |
b8698a0f | 2735 | |
058e97ec VM |
2736 | FOR_EACH_ALLOCNO (a, ai) |
2737 | { | |
2738 | if (ALLOCNO_CAP_MEMBER (a) != NULL) | |
2b9c63a2 | 2739 | /* It is a cap. */ |
058e97ec VM |
2740 | continue; |
2741 | hard_regno = ALLOCNO_HARD_REGNO (a); | |
2742 | if (hard_regno >= 0) | |
2743 | continue; | |
2744 | for (cp = ALLOCNO_COPIES (a); cp != NULL; cp = next_cp) | |
2745 | if (cp->first == a) | |
2746 | next_cp = cp->next_first_allocno_copy; | |
2747 | else | |
2748 | { | |
2749 | next_cp = cp->next_second_allocno_copy; | |
2750 | if (internal_flag_ira_verbose > 4 && ira_dump_file != NULL | |
2751 | && cp->insn != NULL_RTX | |
2752 | && ALLOCNO_HARD_REGNO (cp->first) == hard_regno) | |
2753 | fprintf (ira_dump_file, | |
2754 | " Redundant move from %d(freq %d):%d\n", | |
2755 | INSN_UID (cp->insn), cp->freq, hard_regno); | |
2756 | } | |
2757 | } | |
2758 | } | |
2759 | #endif | |
2760 | ||
2761 | /* Setup preferred and alternative classes for new pseudo-registers | |
2762 | created by IRA starting with START. */ | |
2763 | static void | |
2764 | setup_preferred_alternate_classes_for_new_pseudos (int start) | |
2765 | { | |
2766 | int i, old_regno; | |
2767 | int max_regno = max_reg_num (); | |
2768 | ||
2769 | for (i = start; i < max_regno; i++) | |
2770 | { | |
2771 | old_regno = ORIGINAL_REGNO (regno_reg_rtx[i]); | |
b8698a0f | 2772 | ira_assert (i != old_regno); |
058e97ec | 2773 | setup_reg_classes (i, reg_preferred_class (old_regno), |
ce18efcb | 2774 | reg_alternate_class (old_regno), |
1756cb66 | 2775 | reg_allocno_class (old_regno)); |
058e97ec VM |
2776 | if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL) |
2777 | fprintf (ira_dump_file, | |
2778 | " New r%d: setting preferred %s, alternative %s\n", | |
2779 | i, reg_class_names[reg_preferred_class (old_regno)], | |
2780 | reg_class_names[reg_alternate_class (old_regno)]); | |
2781 | } | |
2782 | } | |
2783 | ||
2784 | \f | |
df3e3493 | 2785 | /* The number of entries allocated in reg_info. */ |
fb99ee9b | 2786 | static int allocated_reg_info_size; |
058e97ec VM |
2787 | |
2788 | /* Regional allocation can create new pseudo-registers. This function | |
2789 | expands some arrays for pseudo-registers. */ | |
2790 | static void | |
fb99ee9b | 2791 | expand_reg_info (void) |
058e97ec VM |
2792 | { |
2793 | int i; | |
2794 | int size = max_reg_num (); | |
2795 | ||
2796 | resize_reg_info (); | |
fb99ee9b | 2797 | for (i = allocated_reg_info_size; i < size; i++) |
ce18efcb | 2798 | setup_reg_classes (i, GENERAL_REGS, ALL_REGS, GENERAL_REGS); |
fb99ee9b BS |
2799 | setup_preferred_alternate_classes_for_new_pseudos (allocated_reg_info_size); |
2800 | allocated_reg_info_size = size; | |
058e97ec VM |
2801 | } |
2802 | ||
3553f0bb VM |
2803 | /* Return TRUE if there is too high register pressure in the function. |
2804 | It is used to decide when stack slot sharing is worth to do. */ | |
2805 | static bool | |
2806 | too_high_register_pressure_p (void) | |
2807 | { | |
2808 | int i; | |
1756cb66 | 2809 | enum reg_class pclass; |
b8698a0f | 2810 | |
1756cb66 | 2811 | for (i = 0; i < ira_pressure_classes_num; i++) |
3553f0bb | 2812 | { |
1756cb66 VM |
2813 | pclass = ira_pressure_classes[i]; |
2814 | if (ira_loop_tree_root->reg_pressure[pclass] > 10000) | |
3553f0bb VM |
2815 | return true; |
2816 | } | |
2817 | return false; | |
2818 | } | |
2819 | ||
058e97ec VM |
2820 | \f |
2821 | ||
2af2dbdc VM |
2822 | /* Indicate that hard register number FROM was eliminated and replaced with |
2823 | an offset from hard register number TO. The status of hard registers live | |
2824 | at the start of a basic block is updated by replacing a use of FROM with | |
2825 | a use of TO. */ | |
2826 | ||
2827 | void | |
2828 | mark_elimination (int from, int to) | |
2829 | { | |
2830 | basic_block bb; | |
bf744527 | 2831 | bitmap r; |
2af2dbdc | 2832 | |
11cd3bed | 2833 | FOR_EACH_BB_FN (bb, cfun) |
2af2dbdc | 2834 | { |
bf744527 SB |
2835 | r = DF_LR_IN (bb); |
2836 | if (bitmap_bit_p (r, from)) | |
2837 | { | |
2838 | bitmap_clear_bit (r, from); | |
2839 | bitmap_set_bit (r, to); | |
2840 | } | |
2841 | if (! df_live) | |
2842 | continue; | |
2843 | r = DF_LIVE_IN (bb); | |
2844 | if (bitmap_bit_p (r, from)) | |
2af2dbdc | 2845 | { |
bf744527 SB |
2846 | bitmap_clear_bit (r, from); |
2847 | bitmap_set_bit (r, to); | |
2af2dbdc VM |
2848 | } |
2849 | } | |
2850 | } | |
2851 | ||
2852 | \f | |
2853 | ||
55a2c322 VM |
2854 | /* The length of the following array. */ |
2855 | int ira_reg_equiv_len; | |
2856 | ||
2857 | /* Info about equiv. info for each register. */ | |
4c2b2d79 | 2858 | struct ira_reg_equiv_s *ira_reg_equiv; |
55a2c322 VM |
2859 | |
2860 | /* Expand ira_reg_equiv if necessary. */ | |
2861 | void | |
2862 | ira_expand_reg_equiv (void) | |
2863 | { | |
2864 | int old = ira_reg_equiv_len; | |
2865 | ||
2866 | if (ira_reg_equiv_len > max_reg_num ()) | |
2867 | return; | |
2868 | ira_reg_equiv_len = max_reg_num () * 3 / 2 + 1; | |
2869 | ira_reg_equiv | |
4c2b2d79 | 2870 | = (struct ira_reg_equiv_s *) xrealloc (ira_reg_equiv, |
55a2c322 | 2871 | ira_reg_equiv_len |
4c2b2d79 | 2872 | * sizeof (struct ira_reg_equiv_s)); |
55a2c322 VM |
2873 | gcc_assert (old < ira_reg_equiv_len); |
2874 | memset (ira_reg_equiv + old, 0, | |
4c2b2d79 | 2875 | sizeof (struct ira_reg_equiv_s) * (ira_reg_equiv_len - old)); |
55a2c322 VM |
2876 | } |
2877 | ||
2878 | static void | |
2879 | init_reg_equiv (void) | |
2880 | { | |
2881 | ira_reg_equiv_len = 0; | |
2882 | ira_reg_equiv = NULL; | |
2883 | ira_expand_reg_equiv (); | |
2884 | } | |
2885 | ||
2886 | static void | |
2887 | finish_reg_equiv (void) | |
2888 | { | |
2889 | free (ira_reg_equiv); | |
2890 | } | |
2891 | ||
2892 | \f | |
2893 | ||
2af2dbdc VM |
2894 | struct equivalence |
2895 | { | |
2af2dbdc VM |
2896 | /* Set when a REG_EQUIV note is found or created. Use to |
2897 | keep track of what memory accesses might be created later, | |
2898 | e.g. by reload. */ | |
2899 | rtx replacement; | |
2900 | rtx *src_p; | |
fb0ab697 JL |
2901 | |
2902 | /* The list of each instruction which initializes this register. | |
2903 | ||
2904 | NULL indicates we know nothing about this register's equivalence | |
2905 | properties. | |
2906 | ||
2907 | An INSN_LIST with a NULL insn indicates this pseudo is already | |
2908 | known to not have a valid equivalence. */ | |
2909 | rtx_insn_list *init_insns; | |
2910 | ||
2af2dbdc VM |
2911 | /* Loop depth is used to recognize equivalences which appear |
2912 | to be present within the same loop (or in an inner loop). */ | |
5ffa4e6a | 2913 | short loop_depth; |
2af2dbdc | 2914 | /* Nonzero if this had a preexisting REG_EQUIV note. */ |
5ffa4e6a | 2915 | unsigned char is_arg_equivalence : 1; |
8f5929e1 JJ |
2916 | /* Set when an attempt should be made to replace a register |
2917 | with the associated src_p entry. */ | |
5ffa4e6a FY |
2918 | unsigned char replace : 1; |
2919 | /* Set if this register has no known equivalence. */ | |
2920 | unsigned char no_equiv : 1; | |
8c1d8b59 AM |
2921 | /* Set if this register is mentioned in a paradoxical subreg. */ |
2922 | unsigned char pdx_subregs : 1; | |
2af2dbdc VM |
2923 | }; |
2924 | ||
2925 | /* reg_equiv[N] (where N is a pseudo reg number) is the equivalence | |
2926 | structure for that register. */ | |
2927 | static struct equivalence *reg_equiv; | |
2928 | ||
c7a99fc6 AM |
2929 | /* Used for communication between the following two functions. */ |
2930 | struct equiv_mem_data | |
2931 | { | |
2932 | /* A MEM that we wish to ensure remains unchanged. */ | |
2933 | rtx equiv_mem; | |
2af2dbdc | 2934 | |
c7a99fc6 AM |
2935 | /* Set true if EQUIV_MEM is modified. */ |
2936 | bool equiv_mem_modified; | |
2937 | }; | |
2af2dbdc VM |
2938 | |
2939 | /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified. | |
2940 | Called via note_stores. */ | |
2941 | static void | |
2942 | validate_equiv_mem_from_store (rtx dest, const_rtx set ATTRIBUTE_UNUSED, | |
c7a99fc6 | 2943 | void *data) |
2af2dbdc | 2944 | { |
c7a99fc6 AM |
2945 | struct equiv_mem_data *info = (struct equiv_mem_data *) data; |
2946 | ||
2af2dbdc | 2947 | if ((REG_P (dest) |
c7a99fc6 | 2948 | && reg_overlap_mentioned_p (dest, info->equiv_mem)) |
2af2dbdc | 2949 | || (MEM_P (dest) |
c7a99fc6 AM |
2950 | && anti_dependence (info->equiv_mem, dest))) |
2951 | info->equiv_mem_modified = true; | |
2af2dbdc VM |
2952 | } |
2953 | ||
63ce14e0 AM |
2954 | enum valid_equiv { valid_none, valid_combine, valid_reload }; |
2955 | ||
2af2dbdc VM |
2956 | /* Verify that no store between START and the death of REG invalidates |
2957 | MEMREF. MEMREF is invalidated by modifying a register used in MEMREF, | |
2958 | by storing into an overlapping memory location, or with a non-const | |
2959 | CALL_INSN. | |
2960 | ||
63ce14e0 AM |
2961 | Return VALID_RELOAD if MEMREF remains valid for both reload and |
2962 | combine_and_move insns, VALID_COMBINE if only valid for | |
2963 | combine_and_move_insns, and VALID_NONE otherwise. */ | |
2964 | static enum valid_equiv | |
b32d5189 | 2965 | validate_equiv_mem (rtx_insn *start, rtx reg, rtx memref) |
2af2dbdc | 2966 | { |
b32d5189 | 2967 | rtx_insn *insn; |
2af2dbdc | 2968 | rtx note; |
c7a99fc6 | 2969 | struct equiv_mem_data info = { memref, false }; |
63ce14e0 | 2970 | enum valid_equiv ret = valid_reload; |
2af2dbdc VM |
2971 | |
2972 | /* If the memory reference has side effects or is volatile, it isn't a | |
2973 | valid equivalence. */ | |
2974 | if (side_effects_p (memref)) | |
63ce14e0 | 2975 | return valid_none; |
2af2dbdc | 2976 | |
c7a99fc6 | 2977 | for (insn = start; insn; insn = NEXT_INSN (insn)) |
2af2dbdc | 2978 | { |
63ce14e0 | 2979 | if (!INSN_P (insn)) |
2af2dbdc VM |
2980 | continue; |
2981 | ||
2982 | if (find_reg_note (insn, REG_DEAD, reg)) | |
63ce14e0 | 2983 | return ret; |
2af2dbdc | 2984 | |
a22265a4 | 2985 | if (CALL_P (insn)) |
63ce14e0 AM |
2986 | { |
2987 | /* We can combine a reg def from one insn into a reg use in | |
2988 | another over a call if the memory is readonly or the call | |
2989 | const/pure. However, we can't set reg_equiv notes up for | |
2990 | reload over any call. The problem is the equivalent form | |
2991 | may reference a pseudo which gets assigned a call | |
2992 | clobbered hard reg. When we later replace REG with its | |
2993 | equivalent form, the value in the call-clobbered reg has | |
2994 | been changed and all hell breaks loose. */ | |
2995 | ret = valid_combine; | |
2996 | if (!MEM_READONLY_P (memref) | |
2997 | && !RTL_CONST_OR_PURE_CALL_P (insn)) | |
2998 | return valid_none; | |
2999 | } | |
2af2dbdc | 3000 | |
c7a99fc6 AM |
3001 | note_stores (PATTERN (insn), validate_equiv_mem_from_store, &info); |
3002 | if (info.equiv_mem_modified) | |
63ce14e0 | 3003 | return valid_none; |
2af2dbdc VM |
3004 | |
3005 | /* If a register mentioned in MEMREF is modified via an | |
3006 | auto-increment, we lose the equivalence. Do the same if one | |
3007 | dies; although we could extend the life, it doesn't seem worth | |
3008 | the trouble. */ | |
3009 | ||
3010 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
3011 | if ((REG_NOTE_KIND (note) == REG_INC | |
3012 | || REG_NOTE_KIND (note) == REG_DEAD) | |
3013 | && REG_P (XEXP (note, 0)) | |
3014 | && reg_overlap_mentioned_p (XEXP (note, 0), memref)) | |
63ce14e0 | 3015 | return valid_none; |
2af2dbdc VM |
3016 | } |
3017 | ||
63ce14e0 | 3018 | return valid_none; |
2af2dbdc VM |
3019 | } |
3020 | ||
3021 | /* Returns zero if X is known to be invariant. */ | |
3022 | static int | |
3023 | equiv_init_varies_p (rtx x) | |
3024 | { | |
3025 | RTX_CODE code = GET_CODE (x); | |
3026 | int i; | |
3027 | const char *fmt; | |
3028 | ||
3029 | switch (code) | |
3030 | { | |
3031 | case MEM: | |
3032 | return !MEM_READONLY_P (x) || equiv_init_varies_p (XEXP (x, 0)); | |
3033 | ||
3034 | case CONST: | |
d8116890 | 3035 | CASE_CONST_ANY: |
2af2dbdc VM |
3036 | case SYMBOL_REF: |
3037 | case LABEL_REF: | |
3038 | return 0; | |
3039 | ||
3040 | case REG: | |
3041 | return reg_equiv[REGNO (x)].replace == 0 && rtx_varies_p (x, 0); | |
3042 | ||
3043 | case ASM_OPERANDS: | |
3044 | if (MEM_VOLATILE_P (x)) | |
3045 | return 1; | |
3046 | ||
3047 | /* Fall through. */ | |
3048 | ||
3049 | default: | |
3050 | break; | |
3051 | } | |
3052 | ||
3053 | fmt = GET_RTX_FORMAT (code); | |
3054 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3055 | if (fmt[i] == 'e') | |
3056 | { | |
3057 | if (equiv_init_varies_p (XEXP (x, i))) | |
3058 | return 1; | |
3059 | } | |
3060 | else if (fmt[i] == 'E') | |
3061 | { | |
3062 | int j; | |
3063 | for (j = 0; j < XVECLEN (x, i); j++) | |
3064 | if (equiv_init_varies_p (XVECEXP (x, i, j))) | |
3065 | return 1; | |
3066 | } | |
3067 | ||
3068 | return 0; | |
3069 | } | |
3070 | ||
3071 | /* Returns nonzero if X (used to initialize register REGNO) is movable. | |
3072 | X is only movable if the registers it uses have equivalent initializations | |
3073 | which appear to be within the same loop (or in an inner loop) and movable | |
3074 | or if they are not candidates for local_alloc and don't vary. */ | |
3075 | static int | |
3076 | equiv_init_movable_p (rtx x, int regno) | |
3077 | { | |
3078 | int i, j; | |
3079 | const char *fmt; | |
3080 | enum rtx_code code = GET_CODE (x); | |
3081 | ||
3082 | switch (code) | |
3083 | { | |
3084 | case SET: | |
3085 | return equiv_init_movable_p (SET_SRC (x), regno); | |
3086 | ||
3087 | case CC0: | |
3088 | case CLOBBER: | |
3089 | return 0; | |
3090 | ||
3091 | case PRE_INC: | |
3092 | case PRE_DEC: | |
3093 | case POST_INC: | |
3094 | case POST_DEC: | |
3095 | case PRE_MODIFY: | |
3096 | case POST_MODIFY: | |
3097 | return 0; | |
3098 | ||
3099 | case REG: | |
1756cb66 VM |
3100 | return ((reg_equiv[REGNO (x)].loop_depth >= reg_equiv[regno].loop_depth |
3101 | && reg_equiv[REGNO (x)].replace) | |
3102 | || (REG_BASIC_BLOCK (REGNO (x)) < NUM_FIXED_BLOCKS | |
3103 | && ! rtx_varies_p (x, 0))); | |
2af2dbdc VM |
3104 | |
3105 | case UNSPEC_VOLATILE: | |
3106 | return 0; | |
3107 | ||
3108 | case ASM_OPERANDS: | |
3109 | if (MEM_VOLATILE_P (x)) | |
3110 | return 0; | |
3111 | ||
3112 | /* Fall through. */ | |
3113 | ||
3114 | default: | |
3115 | break; | |
3116 | } | |
3117 | ||
3118 | fmt = GET_RTX_FORMAT (code); | |
3119 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3120 | switch (fmt[i]) | |
3121 | { | |
3122 | case 'e': | |
3123 | if (! equiv_init_movable_p (XEXP (x, i), regno)) | |
3124 | return 0; | |
3125 | break; | |
3126 | case 'E': | |
3127 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
3128 | if (! equiv_init_movable_p (XVECEXP (x, i, j), regno)) | |
3129 | return 0; | |
3130 | break; | |
3131 | } | |
3132 | ||
3133 | return 1; | |
3134 | } | |
3135 | ||
2af2dbdc VM |
3136 | /* TRUE if X references a memory location that would be affected by a store |
3137 | to MEMREF. */ | |
3138 | static int | |
3139 | memref_referenced_p (rtx memref, rtx x) | |
3140 | { | |
3141 | int i, j; | |
3142 | const char *fmt; | |
3143 | enum rtx_code code = GET_CODE (x); | |
3144 | ||
3145 | switch (code) | |
3146 | { | |
2af2dbdc VM |
3147 | case CONST: |
3148 | case LABEL_REF: | |
3149 | case SYMBOL_REF: | |
d8116890 | 3150 | CASE_CONST_ANY: |
2af2dbdc VM |
3151 | case PC: |
3152 | case CC0: | |
3153 | case HIGH: | |
3154 | case LO_SUM: | |
3155 | return 0; | |
3156 | ||
3157 | case REG: | |
3158 | return (reg_equiv[REGNO (x)].replacement | |
3159 | && memref_referenced_p (memref, | |
3160 | reg_equiv[REGNO (x)].replacement)); | |
3161 | ||
3162 | case MEM: | |
53d9622b | 3163 | if (true_dependence (memref, VOIDmode, x)) |
2af2dbdc VM |
3164 | return 1; |
3165 | break; | |
3166 | ||
3167 | case SET: | |
3168 | /* If we are setting a MEM, it doesn't count (its address does), but any | |
3169 | other SET_DEST that has a MEM in it is referencing the MEM. */ | |
3170 | if (MEM_P (SET_DEST (x))) | |
3171 | { | |
3172 | if (memref_referenced_p (memref, XEXP (SET_DEST (x), 0))) | |
3173 | return 1; | |
3174 | } | |
3175 | else if (memref_referenced_p (memref, SET_DEST (x))) | |
3176 | return 1; | |
3177 | ||
3178 | return memref_referenced_p (memref, SET_SRC (x)); | |
3179 | ||
3180 | default: | |
3181 | break; | |
3182 | } | |
3183 | ||
3184 | fmt = GET_RTX_FORMAT (code); | |
3185 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3186 | switch (fmt[i]) | |
3187 | { | |
3188 | case 'e': | |
3189 | if (memref_referenced_p (memref, XEXP (x, i))) | |
3190 | return 1; | |
3191 | break; | |
3192 | case 'E': | |
3193 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
3194 | if (memref_referenced_p (memref, XVECEXP (x, i, j))) | |
3195 | return 1; | |
3196 | break; | |
3197 | } | |
3198 | ||
3199 | return 0; | |
3200 | } | |
3201 | ||
3202 | /* TRUE if some insn in the range (START, END] references a memory location | |
14d7d4be JL |
3203 | that would be affected by a store to MEMREF. |
3204 | ||
3205 | Callers should not call this routine if START is after END in the | |
3206 | RTL chain. */ | |
3207 | ||
2af2dbdc | 3208 | static int |
b32d5189 | 3209 | memref_used_between_p (rtx memref, rtx_insn *start, rtx_insn *end) |
2af2dbdc | 3210 | { |
b32d5189 | 3211 | rtx_insn *insn; |
2af2dbdc | 3212 | |
14d7d4be JL |
3213 | for (insn = NEXT_INSN (start); |
3214 | insn && insn != NEXT_INSN (end); | |
2af2dbdc VM |
3215 | insn = NEXT_INSN (insn)) |
3216 | { | |
b5b8b0ac | 3217 | if (!NONDEBUG_INSN_P (insn)) |
2af2dbdc | 3218 | continue; |
b8698a0f | 3219 | |
2af2dbdc VM |
3220 | if (memref_referenced_p (memref, PATTERN (insn))) |
3221 | return 1; | |
3222 | ||
3223 | /* Nonconst functions may access memory. */ | |
3224 | if (CALL_P (insn) && (! RTL_CONST_CALL_P (insn))) | |
3225 | return 1; | |
3226 | } | |
3227 | ||
14d7d4be | 3228 | gcc_assert (insn == NEXT_INSN (end)); |
2af2dbdc VM |
3229 | return 0; |
3230 | } | |
3231 | ||
3232 | /* Mark REG as having no known equivalence. | |
3233 | Some instructions might have been processed before and furnished | |
3234 | with REG_EQUIV notes for this register; these notes will have to be | |
3235 | removed. | |
3236 | STORE is the piece of RTL that does the non-constant / conflicting | |
3237 | assignment - a SET, CLOBBER or REG_INC note. It is currently not used, | |
3238 | but needs to be there because this function is called from note_stores. */ | |
3239 | static void | |
1756cb66 VM |
3240 | no_equiv (rtx reg, const_rtx store ATTRIBUTE_UNUSED, |
3241 | void *data ATTRIBUTE_UNUSED) | |
2af2dbdc VM |
3242 | { |
3243 | int regno; | |
fb0ab697 | 3244 | rtx_insn_list *list; |
2af2dbdc VM |
3245 | |
3246 | if (!REG_P (reg)) | |
3247 | return; | |
3248 | regno = REGNO (reg); | |
5ffa4e6a | 3249 | reg_equiv[regno].no_equiv = 1; |
2af2dbdc | 3250 | list = reg_equiv[regno].init_insns; |
fb0ab697 | 3251 | if (list && list->insn () == NULL) |
2af2dbdc | 3252 | return; |
fb0ab697 | 3253 | reg_equiv[regno].init_insns = gen_rtx_INSN_LIST (VOIDmode, NULL_RTX, NULL); |
2af2dbdc VM |
3254 | reg_equiv[regno].replacement = NULL_RTX; |
3255 | /* This doesn't matter for equivalences made for argument registers, we | |
3256 | should keep their initialization insns. */ | |
3257 | if (reg_equiv[regno].is_arg_equivalence) | |
3258 | return; | |
55a2c322 | 3259 | ira_reg_equiv[regno].defined_p = false; |
0cc97fc5 | 3260 | ira_reg_equiv[regno].init_insns = NULL; |
fb0ab697 | 3261 | for (; list; list = list->next ()) |
2af2dbdc | 3262 | { |
fb0ab697 | 3263 | rtx_insn *insn = list->insn (); |
2af2dbdc VM |
3264 | remove_note (insn, find_reg_note (insn, REG_EQUIV, NULL_RTX)); |
3265 | } | |
3266 | } | |
3267 | ||
e3f9e0ac WM |
3268 | /* Check whether the SUBREG is a paradoxical subreg and set the result |
3269 | in PDX_SUBREGS. */ | |
3270 | ||
40954ce5 | 3271 | static void |
8c1d8b59 | 3272 | set_paradoxical_subreg (rtx_insn *insn) |
e3f9e0ac | 3273 | { |
40954ce5 RS |
3274 | subrtx_iterator::array_type array; |
3275 | FOR_EACH_SUBRTX (iter, array, PATTERN (insn), NONCONST) | |
3276 | { | |
3277 | const_rtx subreg = *iter; | |
3278 | if (GET_CODE (subreg) == SUBREG) | |
3279 | { | |
3280 | const_rtx reg = SUBREG_REG (subreg); | |
3281 | if (REG_P (reg) && paradoxical_subreg_p (subreg)) | |
8c1d8b59 | 3282 | reg_equiv[REGNO (reg)].pdx_subregs = true; |
40954ce5 RS |
3283 | } |
3284 | } | |
e3f9e0ac WM |
3285 | } |
3286 | ||
3a6191b1 JJ |
3287 | /* In DEBUG_INSN location adjust REGs from CLEARED_REGS bitmap to the |
3288 | equivalent replacement. */ | |
3289 | ||
3290 | static rtx | |
3291 | adjust_cleared_regs (rtx loc, const_rtx old_rtx ATTRIBUTE_UNUSED, void *data) | |
3292 | { | |
3293 | if (REG_P (loc)) | |
3294 | { | |
3295 | bitmap cleared_regs = (bitmap) data; | |
3296 | if (bitmap_bit_p (cleared_regs, REGNO (loc))) | |
b8f045e2 | 3297 | return simplify_replace_fn_rtx (copy_rtx (*reg_equiv[REGNO (loc)].src_p), |
3a6191b1 JJ |
3298 | NULL_RTX, adjust_cleared_regs, data); |
3299 | } | |
3300 | return NULL_RTX; | |
3301 | } | |
3302 | ||
a72b242e AM |
3303 | /* Given register REGNO is set only once, return true if the defining |
3304 | insn dominates all uses. */ | |
3305 | ||
3306 | static bool | |
3307 | def_dominates_uses (int regno) | |
3308 | { | |
3309 | df_ref def = DF_REG_DEF_CHAIN (regno); | |
3310 | ||
3311 | struct df_insn_info *def_info = DF_REF_INSN_INFO (def); | |
3312 | /* If this is an artificial def (eh handler regs, hard frame pointer | |
3313 | for non-local goto, regs defined on function entry) then def_info | |
3314 | is NULL and the reg is always live before any use. We might | |
3315 | reasonably return true in that case, but since the only call | |
3316 | of this function is currently here in ira.c when we are looking | |
3317 | at a defining insn we can't have an artificial def as that would | |
3318 | bump DF_REG_DEF_COUNT. */ | |
3319 | gcc_assert (DF_REG_DEF_COUNT (regno) == 1 && def_info != NULL); | |
3320 | ||
3321 | rtx_insn *def_insn = DF_REF_INSN (def); | |
3322 | basic_block def_bb = BLOCK_FOR_INSN (def_insn); | |
3323 | ||
3324 | for (df_ref use = DF_REG_USE_CHAIN (regno); | |
3325 | use; | |
3326 | use = DF_REF_NEXT_REG (use)) | |
3327 | { | |
3328 | struct df_insn_info *use_info = DF_REF_INSN_INFO (use); | |
3329 | /* Only check real uses, not artificial ones. */ | |
3330 | if (use_info) | |
3331 | { | |
3332 | rtx_insn *use_insn = DF_REF_INSN (use); | |
3333 | if (!DEBUG_INSN_P (use_insn)) | |
3334 | { | |
3335 | basic_block use_bb = BLOCK_FOR_INSN (use_insn); | |
3336 | if (use_bb != def_bb | |
3337 | ? !dominated_by_p (CDI_DOMINATORS, use_bb, def_bb) | |
3338 | : DF_INSN_INFO_LUID (use_info) < DF_INSN_INFO_LUID (def_info)) | |
3339 | return false; | |
3340 | } | |
3341 | } | |
3342 | } | |
3343 | return true; | |
3344 | } | |
3345 | ||
2af2dbdc | 3346 | /* Find registers that are equivalent to a single value throughout the |
1756cb66 VM |
3347 | compilation (either because they can be referenced in memory or are |
3348 | set once from a single constant). Lower their priority for a | |
3349 | register. | |
2af2dbdc | 3350 | |
1756cb66 VM |
3351 | If such a register is only referenced once, try substituting its |
3352 | value into the using insn. If it succeeds, we can eliminate the | |
3353 | register completely. | |
2af2dbdc | 3354 | |
ba52669f AM |
3355 | Initialize init_insns in ira_reg_equiv array. */ |
3356 | static void | |
2af2dbdc VM |
3357 | update_equiv_regs (void) |
3358 | { | |
b2908ba6 | 3359 | rtx_insn *insn; |
2af2dbdc | 3360 | basic_block bb; |
2af2dbdc | 3361 | |
8c1d8b59 AM |
3362 | /* Scan insns and set pdx_subregs if the reg is used in a |
3363 | paradoxical subreg. Don't set such reg equivalent to a mem, | |
e3f9e0ac WM |
3364 | because lra will not substitute such equiv memory in order to |
3365 | prevent access beyond allocated memory for paradoxical memory subreg. */ | |
11cd3bed | 3366 | FOR_EACH_BB_FN (bb, cfun) |
e3f9e0ac | 3367 | FOR_BB_INSNS (bb, insn) |
c34c46dd | 3368 | if (NONDEBUG_INSN_P (insn)) |
8c1d8b59 | 3369 | set_paradoxical_subreg (insn); |
e3f9e0ac | 3370 | |
2af2dbdc VM |
3371 | /* Scan the insns and find which registers have equivalences. Do this |
3372 | in a separate scan of the insns because (due to -fcse-follow-jumps) | |
3373 | a register can be set below its use. */ | |
91dabbb2 | 3374 | bitmap setjmp_crosses = regstat_get_setjmp_crosses (); |
11cd3bed | 3375 | FOR_EACH_BB_FN (bb, cfun) |
2af2dbdc | 3376 | { |
91dabbb2 | 3377 | int loop_depth = bb_loop_depth (bb); |
2af2dbdc VM |
3378 | |
3379 | for (insn = BB_HEAD (bb); | |
3380 | insn != NEXT_INSN (BB_END (bb)); | |
3381 | insn = NEXT_INSN (insn)) | |
3382 | { | |
3383 | rtx note; | |
3384 | rtx set; | |
3385 | rtx dest, src; | |
3386 | int regno; | |
3387 | ||
3388 | if (! INSN_P (insn)) | |
3389 | continue; | |
3390 | ||
3391 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
3392 | if (REG_NOTE_KIND (note) == REG_INC) | |
3393 | no_equiv (XEXP (note, 0), note, NULL); | |
3394 | ||
3395 | set = single_set (insn); | |
3396 | ||
3397 | /* If this insn contains more (or less) than a single SET, | |
3398 | only mark all destinations as having no known equivalence. */ | |
07b38331 BS |
3399 | if (set == NULL_RTX |
3400 | || side_effects_p (SET_SRC (set))) | |
2af2dbdc VM |
3401 | { |
3402 | note_stores (PATTERN (insn), no_equiv, NULL); | |
3403 | continue; | |
3404 | } | |
3405 | else if (GET_CODE (PATTERN (insn)) == PARALLEL) | |
3406 | { | |
3407 | int i; | |
3408 | ||
3409 | for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--) | |
3410 | { | |
3411 | rtx part = XVECEXP (PATTERN (insn), 0, i); | |
3412 | if (part != set) | |
3413 | note_stores (part, no_equiv, NULL); | |
3414 | } | |
3415 | } | |
3416 | ||
3417 | dest = SET_DEST (set); | |
3418 | src = SET_SRC (set); | |
3419 | ||
3420 | /* See if this is setting up the equivalence between an argument | |
3421 | register and its stack slot. */ | |
3422 | note = find_reg_note (insn, REG_EQUIV, NULL_RTX); | |
3423 | if (note) | |
3424 | { | |
3425 | gcc_assert (REG_P (dest)); | |
3426 | regno = REGNO (dest); | |
3427 | ||
55a2c322 VM |
3428 | /* Note that we don't want to clear init_insns in |
3429 | ira_reg_equiv even if there are multiple sets of this | |
3430 | register. */ | |
2af2dbdc VM |
3431 | reg_equiv[regno].is_arg_equivalence = 1; |
3432 | ||
5a107a0f VM |
3433 | /* The insn result can have equivalence memory although |
3434 | the equivalence is not set up by the insn. We add | |
3435 | this insn to init insns as it is a flag for now that | |
3436 | regno has an equivalence. We will remove the insn | |
3437 | from init insn list later. */ | |
3438 | if (rtx_equal_p (src, XEXP (note, 0)) || MEM_P (XEXP (note, 0))) | |
55a2c322 VM |
3439 | ira_reg_equiv[regno].init_insns |
3440 | = gen_rtx_INSN_LIST (VOIDmode, insn, | |
3441 | ira_reg_equiv[regno].init_insns); | |
2af2dbdc VM |
3442 | |
3443 | /* Continue normally in case this is a candidate for | |
3444 | replacements. */ | |
3445 | } | |
3446 | ||
3447 | if (!optimize) | |
3448 | continue; | |
3449 | ||
3450 | /* We only handle the case of a pseudo register being set | |
3451 | once, or always to the same value. */ | |
1fe28116 VM |
3452 | /* ??? The mn10200 port breaks if we add equivalences for |
3453 | values that need an ADDRESS_REGS register and set them equivalent | |
3454 | to a MEM of a pseudo. The actual problem is in the over-conservative | |
3455 | handling of INPADDR_ADDRESS / INPUT_ADDRESS / INPUT triples in | |
3456 | calculate_needs, but we traditionally work around this problem | |
3457 | here by rejecting equivalences when the destination is in a register | |
3458 | that's likely spilled. This is fragile, of course, since the | |
3459 | preferred class of a pseudo depends on all instructions that set | |
3460 | or use it. */ | |
3461 | ||
2af2dbdc VM |
3462 | if (!REG_P (dest) |
3463 | || (regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER | |
fb0ab697 JL |
3464 | || (reg_equiv[regno].init_insns |
3465 | && reg_equiv[regno].init_insns->insn () == NULL) | |
07b8f0a8 | 3466 | || (targetm.class_likely_spilled_p (reg_preferred_class (regno)) |
1fe28116 | 3467 | && MEM_P (src) && ! reg_equiv[regno].is_arg_equivalence)) |
2af2dbdc VM |
3468 | { |
3469 | /* This might be setting a SUBREG of a pseudo, a pseudo that is | |
3470 | also set somewhere else to a constant. */ | |
3471 | note_stores (set, no_equiv, NULL); | |
3472 | continue; | |
3473 | } | |
3474 | ||
8c1d8b59 AM |
3475 | /* Don't set reg mentioned in a paradoxical subreg |
3476 | equivalent to a mem. */ | |
3477 | if (MEM_P (src) && reg_equiv[regno].pdx_subregs) | |
e3f9e0ac WM |
3478 | { |
3479 | note_stores (set, no_equiv, NULL); | |
3480 | continue; | |
3481 | } | |
3482 | ||
2af2dbdc VM |
3483 | note = find_reg_note (insn, REG_EQUAL, NULL_RTX); |
3484 | ||
3485 | /* cse sometimes generates function invariants, but doesn't put a | |
3486 | REG_EQUAL note on the insn. Since this note would be redundant, | |
3487 | there's no point creating it earlier than here. */ | |
3488 | if (! note && ! rtx_varies_p (src, 0)) | |
3489 | note = set_unique_reg_note (insn, REG_EQUAL, copy_rtx (src)); | |
3490 | ||
3491 | /* Don't bother considering a REG_EQUAL note containing an EXPR_LIST | |
2b9c63a2 | 3492 | since it represents a function call. */ |
2af2dbdc VM |
3493 | if (note && GET_CODE (XEXP (note, 0)) == EXPR_LIST) |
3494 | note = NULL_RTX; | |
3495 | ||
5ffa4e6a FY |
3496 | if (DF_REG_DEF_COUNT (regno) != 1) |
3497 | { | |
3498 | bool equal_p = true; | |
3499 | rtx_insn_list *list; | |
3500 | ||
3501 | /* If we have already processed this pseudo and determined it | |
3502 | can not have an equivalence, then honor that decision. */ | |
3503 | if (reg_equiv[regno].no_equiv) | |
3504 | continue; | |
3505 | ||
3506 | if (! note | |
2af2dbdc VM |
3507 | || rtx_varies_p (XEXP (note, 0), 0) |
3508 | || (reg_equiv[regno].replacement | |
3509 | && ! rtx_equal_p (XEXP (note, 0), | |
5ffa4e6a FY |
3510 | reg_equiv[regno].replacement))) |
3511 | { | |
3512 | no_equiv (dest, set, NULL); | |
3513 | continue; | |
3514 | } | |
3515 | ||
3516 | list = reg_equiv[regno].init_insns; | |
3517 | for (; list; list = list->next ()) | |
3518 | { | |
3519 | rtx note_tmp; | |
3520 | rtx_insn *insn_tmp; | |
3521 | ||
3522 | insn_tmp = list->insn (); | |
3523 | note_tmp = find_reg_note (insn_tmp, REG_EQUAL, NULL_RTX); | |
3524 | gcc_assert (note_tmp); | |
3525 | if (! rtx_equal_p (XEXP (note, 0), XEXP (note_tmp, 0))) | |
3526 | { | |
3527 | equal_p = false; | |
3528 | break; | |
3529 | } | |
3530 | } | |
3531 | ||
3532 | if (! equal_p) | |
3533 | { | |
3534 | no_equiv (dest, set, NULL); | |
3535 | continue; | |
3536 | } | |
2af2dbdc | 3537 | } |
5ffa4e6a | 3538 | |
2af2dbdc VM |
3539 | /* Record this insn as initializing this register. */ |
3540 | reg_equiv[regno].init_insns | |
3541 | = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv[regno].init_insns); | |
3542 | ||
3543 | /* If this register is known to be equal to a constant, record that | |
a72b242e AM |
3544 | it is always equivalent to the constant. |
3545 | Note that it is possible to have a register use before | |
3546 | the def in loops (see gcc.c-torture/execute/pr79286.c) | |
3547 | where the reg is undefined on first use. If the def insn | |
3548 | won't trap we can use it as an equivalence, effectively | |
3549 | choosing the "undefined" value for the reg to be the | |
3550 | same as the value set by the def. */ | |
2af2dbdc | 3551 | if (DF_REG_DEF_COUNT (regno) == 1 |
a72b242e AM |
3552 | && note |
3553 | && !rtx_varies_p (XEXP (note, 0), 0) | |
08f42414 BE |
3554 | && (!may_trap_or_fault_p (XEXP (note, 0)) |
3555 | || def_dominates_uses (regno))) | |
2af2dbdc VM |
3556 | { |
3557 | rtx note_value = XEXP (note, 0); | |
3558 | remove_note (insn, note); | |
3559 | set_unique_reg_note (insn, REG_EQUIV, note_value); | |
3560 | } | |
3561 | ||
3562 | /* If this insn introduces a "constant" register, decrease the priority | |
3563 | of that register. Record this insn if the register is only used once | |
3564 | more and the equivalence value is the same as our source. | |
3565 | ||
3566 | The latter condition is checked for two reasons: First, it is an | |
3567 | indication that it may be more efficient to actually emit the insn | |
3568 | as written (if no registers are available, reload will substitute | |
3569 | the equivalence). Secondly, it avoids problems with any registers | |
3570 | dying in this insn whose death notes would be missed. | |
3571 | ||
3572 | If we don't have a REG_EQUIV note, see if this insn is loading | |
3573 | a register used only in one basic block from a MEM. If so, and the | |
3574 | MEM remains unchanged for the life of the register, add a REG_EQUIV | |
3575 | note. */ | |
2af2dbdc VM |
3576 | note = find_reg_note (insn, REG_EQUIV, NULL_RTX); |
3577 | ||
63ce14e0 | 3578 | rtx replacement = NULL_RTX; |
2af2dbdc | 3579 | if (note) |
63ce14e0 AM |
3580 | replacement = XEXP (note, 0); |
3581 | else if (REG_BASIC_BLOCK (regno) >= NUM_FIXED_BLOCKS | |
3582 | && MEM_P (SET_SRC (set))) | |
2af2dbdc | 3583 | { |
63ce14e0 AM |
3584 | enum valid_equiv validity; |
3585 | validity = validate_equiv_mem (insn, dest, SET_SRC (set)); | |
3586 | if (validity != valid_none) | |
3587 | { | |
3588 | replacement = copy_rtx (SET_SRC (set)); | |
3589 | if (validity == valid_reload) | |
3590 | note = set_unique_reg_note (insn, REG_EQUIV, replacement); | |
3591 | } | |
3592 | } | |
2af2dbdc | 3593 | |
63ce14e0 AM |
3594 | /* If we haven't done so, record for reload that this is an |
3595 | equivalencing insn. */ | |
3596 | if (note && !reg_equiv[regno].is_arg_equivalence) | |
3597 | ira_reg_equiv[regno].init_insns | |
3598 | = gen_rtx_INSN_LIST (VOIDmode, insn, | |
3599 | ira_reg_equiv[regno].init_insns); | |
2af2dbdc | 3600 | |
63ce14e0 AM |
3601 | if (replacement) |
3602 | { | |
3603 | reg_equiv[regno].replacement = replacement; | |
2af2dbdc | 3604 | reg_equiv[regno].src_p = &SET_SRC (set); |
5ffa4e6a | 3605 | reg_equiv[regno].loop_depth = (short) loop_depth; |
2af2dbdc VM |
3606 | |
3607 | /* Don't mess with things live during setjmp. */ | |
91dabbb2 | 3608 | if (optimize && !bitmap_bit_p (setjmp_crosses, regno)) |
2af2dbdc | 3609 | { |
2af2dbdc VM |
3610 | /* If the register is referenced exactly twice, meaning it is |
3611 | set once and used once, indicate that the reference may be | |
3612 | replaced by the equivalence we computed above. Do this | |
3613 | even if the register is only used in one block so that | |
3614 | dependencies can be handled where the last register is | |
3615 | used in a different block (i.e. HIGH / LO_SUM sequences) | |
3616 | and to reduce the number of registers alive across | |
3617 | calls. */ | |
3618 | ||
3619 | if (REG_N_REFS (regno) == 2 | |
63ce14e0 | 3620 | && (rtx_equal_p (replacement, src) |
2af2dbdc VM |
3621 | || ! equiv_init_varies_p (src)) |
3622 | && NONJUMP_INSN_P (insn) | |
3623 | && equiv_init_movable_p (PATTERN (insn), regno)) | |
3624 | reg_equiv[regno].replace = 1; | |
3625 | } | |
3626 | } | |
3627 | } | |
3628 | } | |
42ae0d7f | 3629 | } |
2af2dbdc | 3630 | |
42ae0d7f AM |
3631 | /* For insns that set a MEM to the contents of a REG that is only used |
3632 | in a single basic block, see if the register is always equivalent | |
3633 | to that memory location and if moving the store from INSN to the | |
3634 | insn that sets REG is safe. If so, put a REG_EQUIV note on the | |
3635 | initializing insn. */ | |
3636 | static void | |
3637 | add_store_equivs (void) | |
3638 | { | |
8f9b31f7 | 3639 | auto_bitmap seen_insns; |
2af2dbdc | 3640 | |
42ae0d7f | 3641 | for (rtx_insn *insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
2af2dbdc VM |
3642 | { |
3643 | rtx set, src, dest; | |
3644 | unsigned regno; | |
42ae0d7f | 3645 | rtx_insn *init_insn; |
2af2dbdc | 3646 | |
8f9b31f7 | 3647 | bitmap_set_bit (seen_insns, INSN_UID (insn)); |
14d7d4be | 3648 | |
2af2dbdc VM |
3649 | if (! INSN_P (insn)) |
3650 | continue; | |
3651 | ||
3652 | set = single_set (insn); | |
3653 | if (! set) | |
3654 | continue; | |
3655 | ||
3656 | dest = SET_DEST (set); | |
3657 | src = SET_SRC (set); | |
3658 | ||
42ae0d7f | 3659 | /* Don't add a REG_EQUIV note if the insn already has one. The existing |
10e04446 | 3660 | REG_EQUIV is likely more useful than the one we are adding. */ |
2af2dbdc VM |
3661 | if (MEM_P (dest) && REG_P (src) |
3662 | && (regno = REGNO (src)) >= FIRST_PSEUDO_REGISTER | |
3663 | && REG_BASIC_BLOCK (regno) >= NUM_FIXED_BLOCKS | |
3664 | && DF_REG_DEF_COUNT (regno) == 1 | |
8c1d8b59 | 3665 | && ! reg_equiv[regno].pdx_subregs |
fb0ab697 | 3666 | && reg_equiv[regno].init_insns != NULL |
42ae0d7f | 3667 | && (init_insn = reg_equiv[regno].init_insns->insn ()) != 0 |
8f9b31f7 | 3668 | && bitmap_bit_p (seen_insns, INSN_UID (init_insn)) |
42ae0d7f | 3669 | && ! find_reg_note (init_insn, REG_EQUIV, NULL_RTX) |
63ce14e0 | 3670 | && validate_equiv_mem (init_insn, src, dest) == valid_reload |
42ae0d7f AM |
3671 | && ! memref_used_between_p (dest, init_insn, insn) |
3672 | /* Attaching a REG_EQUIV note will fail if INIT_INSN has | |
3673 | multiple sets. */ | |
3674 | && set_unique_reg_note (init_insn, REG_EQUIV, copy_rtx (dest))) | |
2af2dbdc | 3675 | { |
42ae0d7f AM |
3676 | /* This insn makes the equivalence, not the one initializing |
3677 | the register. */ | |
3678 | ira_reg_equiv[regno].init_insns | |
3679 | = gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX); | |
3680 | df_notes_rescan (init_insn); | |
3681 | if (dump_file) | |
3682 | fprintf (dump_file, | |
3683 | "Adding REG_EQUIV to insn %d for source of insn %d\n", | |
3684 | INSN_UID (init_insn), | |
3685 | INSN_UID (insn)); | |
2af2dbdc VM |
3686 | } |
3687 | } | |
42ae0d7f AM |
3688 | } |
3689 | ||
3690 | /* Scan all regs killed in an insn to see if any of them are registers | |
3691 | only used that once. If so, see if we can replace the reference | |
3692 | with the equivalent form. If we can, delete the initializing | |
3693 | reference and this register will go away. If we can't replace the | |
3694 | reference, and the initializing reference is within the same loop | |
3695 | (or in an inner loop), then move the register initialization just | |
3696 | before the use, so that they are in the same basic block. */ | |
3697 | static void | |
3698 | combine_and_move_insns (void) | |
3699 | { | |
0e3de1d4 | 3700 | auto_bitmap cleared_regs; |
b00544fa | 3701 | int max = max_reg_num (); |
2af2dbdc | 3702 | |
b00544fa | 3703 | for (int regno = FIRST_PSEUDO_REGISTER; regno < max; regno++) |
2af2dbdc | 3704 | { |
b00544fa AM |
3705 | if (!reg_equiv[regno].replace) |
3706 | continue; | |
2af2dbdc | 3707 | |
b00544fa AM |
3708 | rtx_insn *use_insn = 0; |
3709 | for (df_ref use = DF_REG_USE_CHAIN (regno); | |
3710 | use; | |
3711 | use = DF_REF_NEXT_REG (use)) | |
3712 | if (DF_REF_INSN_INFO (use)) | |
3713 | { | |
3714 | if (DEBUG_INSN_P (DF_REF_INSN (use))) | |
3715 | continue; | |
3716 | gcc_assert (!use_insn); | |
3717 | use_insn = DF_REF_INSN (use); | |
3718 | } | |
3719 | gcc_assert (use_insn); | |
2af2dbdc | 3720 | |
b00544fa AM |
3721 | /* Don't substitute into jumps. indirect_jump_optimize does |
3722 | this for anything we are prepared to handle. */ | |
3723 | if (JUMP_P (use_insn)) | |
3724 | continue; | |
3725 | ||
17a938e8 SB |
3726 | /* Also don't substitute into a conditional trap insn -- it can become |
3727 | an unconditional trap, and that is a flow control insn. */ | |
3728 | if (GET_CODE (PATTERN (use_insn)) == TRAP_IF) | |
3729 | continue; | |
3730 | ||
b00544fa AM |
3731 | df_ref def = DF_REG_DEF_CHAIN (regno); |
3732 | gcc_assert (DF_REG_DEF_COUNT (regno) == 1 && DF_REF_INSN_INFO (def)); | |
3733 | rtx_insn *def_insn = DF_REF_INSN (def); | |
3734 | ||
3735 | /* We may not move instructions that can throw, since that | |
3736 | changes basic block boundaries and we are not prepared to | |
3737 | adjust the CFG to match. */ | |
3738 | if (can_throw_internal (def_insn)) | |
3739 | continue; | |
3740 | ||
3741 | basic_block use_bb = BLOCK_FOR_INSN (use_insn); | |
3742 | basic_block def_bb = BLOCK_FOR_INSN (def_insn); | |
3743 | if (bb_loop_depth (use_bb) > bb_loop_depth (def_bb)) | |
3744 | continue; | |
2af2dbdc | 3745 | |
b00544fa AM |
3746 | if (asm_noperands (PATTERN (def_insn)) < 0 |
3747 | && validate_replace_rtx (regno_reg_rtx[regno], | |
3748 | *reg_equiv[regno].src_p, use_insn)) | |
3749 | { | |
3750 | rtx link; | |
3751 | /* Append the REG_DEAD notes from def_insn. */ | |
3752 | for (rtx *p = ®_NOTES (def_insn); (link = *p) != 0; ) | |
2af2dbdc | 3753 | { |
b00544fa | 3754 | if (REG_NOTE_KIND (XEXP (link, 0)) == REG_DEAD) |
2af2dbdc | 3755 | { |
b00544fa AM |
3756 | *p = XEXP (link, 1); |
3757 | XEXP (link, 1) = REG_NOTES (use_insn); | |
3758 | REG_NOTES (use_insn) = link; | |
3759 | } | |
3760 | else | |
3761 | p = &XEXP (link, 1); | |
3762 | } | |
2af2dbdc | 3763 | |
b00544fa AM |
3764 | remove_death (regno, use_insn); |
3765 | SET_REG_N_REFS (regno, 0); | |
3766 | REG_FREQ (regno) = 0; | |
fba12165 BS |
3767 | df_ref use; |
3768 | FOR_EACH_INSN_USE (use, def_insn) | |
3769 | { | |
3770 | unsigned int use_regno = DF_REF_REGNO (use); | |
3771 | if (!HARD_REGISTER_NUM_P (use_regno)) | |
3772 | reg_equiv[use_regno].replace = 0; | |
3773 | } | |
3774 | ||
b00544fa | 3775 | delete_insn (def_insn); |
2af2dbdc | 3776 | |
b00544fa AM |
3777 | reg_equiv[regno].init_insns = NULL; |
3778 | ira_reg_equiv[regno].init_insns = NULL; | |
3779 | bitmap_set_bit (cleared_regs, regno); | |
3780 | } | |
2af2dbdc | 3781 | |
b00544fa AM |
3782 | /* Move the initialization of the register to just before |
3783 | USE_INSN. Update the flow information. */ | |
3784 | else if (prev_nondebug_insn (use_insn) != def_insn) | |
3785 | { | |
3786 | rtx_insn *new_insn; | |
2af2dbdc | 3787 | |
b00544fa AM |
3788 | new_insn = emit_insn_before (PATTERN (def_insn), use_insn); |
3789 | REG_NOTES (new_insn) = REG_NOTES (def_insn); | |
3790 | REG_NOTES (def_insn) = 0; | |
3791 | /* Rescan it to process the notes. */ | |
3792 | df_insn_rescan (new_insn); | |
2af2dbdc | 3793 | |
b00544fa AM |
3794 | /* Make sure this insn is recognized before reload begins, |
3795 | otherwise eliminate_regs_in_insn will die. */ | |
3796 | INSN_CODE (new_insn) = INSN_CODE (def_insn); | |
2af2dbdc | 3797 | |
b00544fa | 3798 | delete_insn (def_insn); |
2af2dbdc | 3799 | |
b00544fa | 3800 | XEXP (reg_equiv[regno].init_insns, 0) = new_insn; |
2af2dbdc | 3801 | |
b00544fa AM |
3802 | REG_BASIC_BLOCK (regno) = use_bb->index; |
3803 | REG_N_CALLS_CROSSED (regno) = 0; | |
2af2dbdc | 3804 | |
b00544fa AM |
3805 | if (use_insn == BB_HEAD (use_bb)) |
3806 | BB_HEAD (use_bb) = new_insn; | |
2af2dbdc | 3807 | |
fcc861d9 AM |
3808 | /* We know regno dies in use_insn, but inside a loop |
3809 | REG_DEAD notes might be missing when def_insn was in | |
3810 | another basic block. However, when we move def_insn into | |
3811 | this bb we'll definitely get a REG_DEAD note and reload | |
3812 | will see the death. It's possible that update_equiv_regs | |
3813 | set up an equivalence referencing regno for a reg set by | |
3814 | use_insn, when regno was seen as non-local. Now that | |
3815 | regno is local to this block, and dies, such an | |
3816 | equivalence is invalid. */ | |
8972f7e9 | 3817 | if (find_reg_note (use_insn, REG_EQUIV, regno_reg_rtx[regno])) |
fcc861d9 AM |
3818 | { |
3819 | rtx set = single_set (use_insn); | |
3820 | if (set && REG_P (SET_DEST (set))) | |
3821 | no_equiv (SET_DEST (set), set, NULL); | |
3822 | } | |
3823 | ||
b00544fa AM |
3824 | ira_reg_equiv[regno].init_insns |
3825 | = gen_rtx_INSN_LIST (VOIDmode, new_insn, NULL_RTX); | |
3826 | bitmap_set_bit (cleared_regs, regno); | |
2af2dbdc VM |
3827 | } |
3828 | } | |
3829 | ||
3830 | if (!bitmap_empty_p (cleared_regs)) | |
3a6191b1 | 3831 | { |
b00544fa AM |
3832 | basic_block bb; |
3833 | ||
11cd3bed | 3834 | FOR_EACH_BB_FN (bb, cfun) |
3a6191b1 | 3835 | { |
3a6191b1 JJ |
3836 | bitmap_and_compl_into (DF_LR_IN (bb), cleared_regs); |
3837 | bitmap_and_compl_into (DF_LR_OUT (bb), cleared_regs); | |
b00544fa | 3838 | if (!df_live) |
bf744527 SB |
3839 | continue; |
3840 | bitmap_and_compl_into (DF_LIVE_IN (bb), cleared_regs); | |
3841 | bitmap_and_compl_into (DF_LIVE_OUT (bb), cleared_regs); | |
3a6191b1 JJ |
3842 | } |
3843 | ||
3844 | /* Last pass - adjust debug insns referencing cleared regs. */ | |
3845 | if (MAY_HAVE_DEBUG_INSNS) | |
b00544fa | 3846 | for (rtx_insn *insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
3a6191b1 JJ |
3847 | if (DEBUG_INSN_P (insn)) |
3848 | { | |
3849 | rtx old_loc = INSN_VAR_LOCATION_LOC (insn); | |
3850 | INSN_VAR_LOCATION_LOC (insn) | |
3851 | = simplify_replace_fn_rtx (old_loc, NULL_RTX, | |
3852 | adjust_cleared_regs, | |
3853 | (void *) cleared_regs); | |
3854 | if (old_loc != INSN_VAR_LOCATION_LOC (insn)) | |
3855 | df_insn_rescan (insn); | |
3856 | } | |
3857 | } | |
2af2dbdc VM |
3858 | } |
3859 | ||
6585b2e2 AM |
3860 | /* A pass over indirect jumps, converting simple cases to direct jumps. |
3861 | Combine does this optimization too, but only within a basic block. */ | |
ba52669f AM |
3862 | static void |
3863 | indirect_jump_optimize (void) | |
3864 | { | |
3865 | basic_block bb; | |
3866 | bool rebuild_p = false; | |
3867 | ||
3868 | FOR_EACH_BB_REVERSE_FN (bb, cfun) | |
3869 | { | |
3870 | rtx_insn *insn = BB_END (bb); | |
97eb24c4 JJ |
3871 | if (!JUMP_P (insn) |
3872 | || find_reg_note (insn, REG_NON_LOCAL_GOTO, NULL_RTX)) | |
ba52669f AM |
3873 | continue; |
3874 | ||
3875 | rtx x = pc_set (insn); | |
3876 | if (!x || !REG_P (SET_SRC (x))) | |
3877 | continue; | |
3878 | ||
3879 | int regno = REGNO (SET_SRC (x)); | |
3880 | if (DF_REG_DEF_COUNT (regno) == 1) | |
3881 | { | |
6585b2e2 AM |
3882 | df_ref def = DF_REG_DEF_CHAIN (regno); |
3883 | if (!DF_REF_IS_ARTIFICIAL (def)) | |
ba52669f | 3884 | { |
6585b2e2 | 3885 | rtx_insn *def_insn = DF_REF_INSN (def); |
97eb24c4 JJ |
3886 | rtx lab = NULL_RTX; |
3887 | rtx set = single_set (def_insn); | |
3888 | if (set && GET_CODE (SET_SRC (set)) == LABEL_REF) | |
3889 | lab = SET_SRC (set); | |
3890 | else | |
6585b2e2 | 3891 | { |
97eb24c4 JJ |
3892 | rtx eqnote = find_reg_note (def_insn, REG_EQUAL, NULL_RTX); |
3893 | if (eqnote && GET_CODE (XEXP (eqnote, 0)) == LABEL_REF) | |
3894 | lab = XEXP (eqnote, 0); | |
6585b2e2 | 3895 | } |
97eb24c4 JJ |
3896 | if (lab && validate_replace_rtx (SET_SRC (x), lab, insn)) |
3897 | rebuild_p = true; | |
ba52669f AM |
3898 | } |
3899 | } | |
3900 | } | |
2af2dbdc | 3901 | |
ba52669f AM |
3902 | if (rebuild_p) |
3903 | { | |
3904 | timevar_push (TV_JUMP); | |
3905 | rebuild_jump_labels (get_insns ()); | |
3906 | if (purge_all_dead_edges ()) | |
3907 | delete_unreachable_blocks (); | |
3908 | timevar_pop (TV_JUMP); | |
3909 | } | |
3910 | } | |
3911 | \f | |
55a2c322 VM |
3912 | /* Set up fields memory, constant, and invariant from init_insns in |
3913 | the structures of array ira_reg_equiv. */ | |
3914 | static void | |
3915 | setup_reg_equiv (void) | |
3916 | { | |
3917 | int i; | |
0cc97fc5 DM |
3918 | rtx_insn_list *elem, *prev_elem, *next_elem; |
3919 | rtx_insn *insn; | |
3920 | rtx set, x; | |
55a2c322 VM |
3921 | |
3922 | for (i = FIRST_PSEUDO_REGISTER; i < ira_reg_equiv_len; i++) | |
5a107a0f VM |
3923 | for (prev_elem = NULL, elem = ira_reg_equiv[i].init_insns; |
3924 | elem; | |
3925 | prev_elem = elem, elem = next_elem) | |
55a2c322 | 3926 | { |
0cc97fc5 DM |
3927 | next_elem = elem->next (); |
3928 | insn = elem->insn (); | |
55a2c322 VM |
3929 | set = single_set (insn); |
3930 | ||
3931 | /* Init insns can set up equivalence when the reg is a destination or | |
3932 | a source (in this case the destination is memory). */ | |
3933 | if (set != 0 && (REG_P (SET_DEST (set)) || REG_P (SET_SRC (set)))) | |
3934 | { | |
3935 | if ((x = find_reg_note (insn, REG_EQUIV, NULL_RTX)) != NULL) | |
5a107a0f VM |
3936 | { |
3937 | x = XEXP (x, 0); | |
3938 | if (REG_P (SET_DEST (set)) | |
3939 | && REGNO (SET_DEST (set)) == (unsigned int) i | |
3940 | && ! rtx_equal_p (SET_SRC (set), x) && MEM_P (x)) | |
3941 | { | |
3942 | /* This insn reporting the equivalence but | |
3943 | actually not setting it. Remove it from the | |
3944 | list. */ | |
3945 | if (prev_elem == NULL) | |
3946 | ira_reg_equiv[i].init_insns = next_elem; | |
3947 | else | |
3948 | XEXP (prev_elem, 1) = next_elem; | |
3949 | elem = prev_elem; | |
3950 | } | |
3951 | } | |
55a2c322 VM |
3952 | else if (REG_P (SET_DEST (set)) |
3953 | && REGNO (SET_DEST (set)) == (unsigned int) i) | |
3954 | x = SET_SRC (set); | |
3955 | else | |
3956 | { | |
3957 | gcc_assert (REG_P (SET_SRC (set)) | |
3958 | && REGNO (SET_SRC (set)) == (unsigned int) i); | |
3959 | x = SET_DEST (set); | |
3960 | } | |
3961 | if (! function_invariant_p (x) | |
3962 | || ! flag_pic | |
3963 | /* A function invariant is often CONSTANT_P but may | |
3964 | include a register. We promise to only pass | |
3965 | CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */ | |
3966 | || (CONSTANT_P (x) && LEGITIMATE_PIC_OPERAND_P (x))) | |
3967 | { | |
3968 | /* It can happen that a REG_EQUIV note contains a MEM | |
3969 | that is not a legitimate memory operand. As later | |
3970 | stages of reload assume that all addresses found in | |
3971 | the lra_regno_equiv_* arrays were originally | |
3972 | legitimate, we ignore such REG_EQUIV notes. */ | |
3973 | if (memory_operand (x, VOIDmode)) | |
3974 | { | |
3975 | ira_reg_equiv[i].defined_p = true; | |
3976 | ira_reg_equiv[i].memory = x; | |
3977 | continue; | |
3978 | } | |
3979 | else if (function_invariant_p (x)) | |
3980 | { | |
ef4bddc2 | 3981 | machine_mode mode; |
55a2c322 VM |
3982 | |
3983 | mode = GET_MODE (SET_DEST (set)); | |
3984 | if (GET_CODE (x) == PLUS | |
3985 | || x == frame_pointer_rtx || x == arg_pointer_rtx) | |
3986 | /* This is PLUS of frame pointer and a constant, | |
3987 | or fp, or argp. */ | |
3988 | ira_reg_equiv[i].invariant = x; | |
3989 | else if (targetm.legitimate_constant_p (mode, x)) | |
3990 | ira_reg_equiv[i].constant = x; | |
3991 | else | |
3992 | { | |
3993 | ira_reg_equiv[i].memory = force_const_mem (mode, x); | |
3994 | if (ira_reg_equiv[i].memory == NULL_RTX) | |
3995 | { | |
3996 | ira_reg_equiv[i].defined_p = false; | |
0cc97fc5 | 3997 | ira_reg_equiv[i].init_insns = NULL; |
55a2c322 VM |
3998 | break; |
3999 | } | |
4000 | } | |
4001 | ira_reg_equiv[i].defined_p = true; | |
4002 | continue; | |
4003 | } | |
4004 | } | |
4005 | } | |
4006 | ira_reg_equiv[i].defined_p = false; | |
0cc97fc5 | 4007 | ira_reg_equiv[i].init_insns = NULL; |
55a2c322 VM |
4008 | break; |
4009 | } | |
4010 | } | |
4011 | ||
4012 | \f | |
4013 | ||
2af2dbdc VM |
4014 | /* Print chain C to FILE. */ |
4015 | static void | |
4016 | print_insn_chain (FILE *file, struct insn_chain *c) | |
4017 | { | |
c3284718 | 4018 | fprintf (file, "insn=%d, ", INSN_UID (c->insn)); |
2af2dbdc VM |
4019 | bitmap_print (file, &c->live_throughout, "live_throughout: ", ", "); |
4020 | bitmap_print (file, &c->dead_or_set, "dead_or_set: ", "\n"); | |
4021 | } | |
4022 | ||
4023 | ||
4024 | /* Print all reload_insn_chains to FILE. */ | |
4025 | static void | |
4026 | print_insn_chains (FILE *file) | |
4027 | { | |
4028 | struct insn_chain *c; | |
4029 | for (c = reload_insn_chain; c ; c = c->next) | |
4030 | print_insn_chain (file, c); | |
4031 | } | |
4032 | ||
4033 | /* Return true if pseudo REGNO should be added to set live_throughout | |
4034 | or dead_or_set of the insn chains for reload consideration. */ | |
4035 | static bool | |
4036 | pseudo_for_reload_consideration_p (int regno) | |
4037 | { | |
4038 | /* Consider spilled pseudos too for IRA because they still have a | |
4039 | chance to get hard-registers in the reload when IRA is used. */ | |
b100151b | 4040 | return (reg_renumber[regno] >= 0 || ira_conflicts_p); |
2af2dbdc VM |
4041 | } |
4042 | ||
4043 | /* Init LIVE_SUBREGS[ALLOCNUM] and LIVE_SUBREGS_USED[ALLOCNUM] using | |
4044 | REG to the number of nregs, and INIT_VALUE to get the | |
4045 | initialization. ALLOCNUM need not be the regno of REG. */ | |
4046 | static void | |
4047 | init_live_subregs (bool init_value, sbitmap *live_subregs, | |
cee784f5 | 4048 | bitmap live_subregs_used, int allocnum, rtx reg) |
2af2dbdc VM |
4049 | { |
4050 | unsigned int regno = REGNO (SUBREG_REG (reg)); | |
4051 | int size = GET_MODE_SIZE (GET_MODE (regno_reg_rtx[regno])); | |
4052 | ||
4053 | gcc_assert (size > 0); | |
4054 | ||
4055 | /* Been there, done that. */ | |
cee784f5 | 4056 | if (bitmap_bit_p (live_subregs_used, allocnum)) |
2af2dbdc VM |
4057 | return; |
4058 | ||
cee784f5 | 4059 | /* Create a new one. */ |
2af2dbdc VM |
4060 | if (live_subregs[allocnum] == NULL) |
4061 | live_subregs[allocnum] = sbitmap_alloc (size); | |
4062 | ||
4063 | /* If the entire reg was live before blasting into subregs, we need | |
4064 | to init all of the subregs to ones else init to 0. */ | |
4065 | if (init_value) | |
f61e445a | 4066 | bitmap_ones (live_subregs[allocnum]); |
b8698a0f | 4067 | else |
f61e445a | 4068 | bitmap_clear (live_subregs[allocnum]); |
2af2dbdc | 4069 | |
cee784f5 | 4070 | bitmap_set_bit (live_subregs_used, allocnum); |
2af2dbdc VM |
4071 | } |
4072 | ||
4073 | /* Walk the insns of the current function and build reload_insn_chain, | |
4074 | and record register life information. */ | |
4075 | static void | |
4076 | build_insn_chain (void) | |
4077 | { | |
4078 | unsigned int i; | |
4079 | struct insn_chain **p = &reload_insn_chain; | |
4080 | basic_block bb; | |
4081 | struct insn_chain *c = NULL; | |
4082 | struct insn_chain *next = NULL; | |
0e3de1d4 TS |
4083 | auto_bitmap live_relevant_regs; |
4084 | auto_bitmap elim_regset; | |
2af2dbdc VM |
4085 | /* live_subregs is a vector used to keep accurate information about |
4086 | which hardregs are live in multiword pseudos. live_subregs and | |
4087 | live_subregs_used are indexed by pseudo number. The live_subreg | |
4088 | entry for a particular pseudo is only used if the corresponding | |
cee784f5 SB |
4089 | element is non zero in live_subregs_used. The sbitmap size of |
4090 | live_subreg[allocno] is number of bytes that the pseudo can | |
2af2dbdc VM |
4091 | occupy. */ |
4092 | sbitmap *live_subregs = XCNEWVEC (sbitmap, max_regno); | |
0e3de1d4 | 4093 | auto_bitmap live_subregs_used; |
2af2dbdc VM |
4094 | |
4095 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
4096 | if (TEST_HARD_REG_BIT (eliminable_regset, i)) | |
4097 | bitmap_set_bit (elim_regset, i); | |
4f42035e | 4098 | FOR_EACH_BB_REVERSE_FN (bb, cfun) |
2af2dbdc VM |
4099 | { |
4100 | bitmap_iterator bi; | |
070a1983 | 4101 | rtx_insn *insn; |
b8698a0f | 4102 | |
2af2dbdc | 4103 | CLEAR_REG_SET (live_relevant_regs); |
cee784f5 | 4104 | bitmap_clear (live_subregs_used); |
b8698a0f | 4105 | |
bf744527 | 4106 | EXECUTE_IF_SET_IN_BITMAP (df_get_live_out (bb), 0, i, bi) |
2af2dbdc VM |
4107 | { |
4108 | if (i >= FIRST_PSEUDO_REGISTER) | |
4109 | break; | |
4110 | bitmap_set_bit (live_relevant_regs, i); | |
4111 | } | |
4112 | ||
bf744527 | 4113 | EXECUTE_IF_SET_IN_BITMAP (df_get_live_out (bb), |
2af2dbdc VM |
4114 | FIRST_PSEUDO_REGISTER, i, bi) |
4115 | { | |
4116 | if (pseudo_for_reload_consideration_p (i)) | |
4117 | bitmap_set_bit (live_relevant_regs, i); | |
4118 | } | |
4119 | ||
4120 | FOR_BB_INSNS_REVERSE (bb, insn) | |
4121 | { | |
4122 | if (!NOTE_P (insn) && !BARRIER_P (insn)) | |
4123 | { | |
bfac633a RS |
4124 | struct df_insn_info *insn_info = DF_INSN_INFO_GET (insn); |
4125 | df_ref def, use; | |
2af2dbdc VM |
4126 | |
4127 | c = new_insn_chain (); | |
4128 | c->next = next; | |
4129 | next = c; | |
4130 | *p = c; | |
4131 | p = &c->prev; | |
b8698a0f | 4132 | |
2af2dbdc VM |
4133 | c->insn = insn; |
4134 | c->block = bb->index; | |
4135 | ||
4b71920a | 4136 | if (NONDEBUG_INSN_P (insn)) |
bfac633a | 4137 | FOR_EACH_INSN_INFO_DEF (def, insn_info) |
2af2dbdc | 4138 | { |
2af2dbdc | 4139 | unsigned int regno = DF_REF_REGNO (def); |
b8698a0f | 4140 | |
2af2dbdc VM |
4141 | /* Ignore may clobbers because these are generated |
4142 | from calls. However, every other kind of def is | |
4143 | added to dead_or_set. */ | |
4144 | if (!DF_REF_FLAGS_IS_SET (def, DF_REF_MAY_CLOBBER)) | |
4145 | { | |
4146 | if (regno < FIRST_PSEUDO_REGISTER) | |
4147 | { | |
4148 | if (!fixed_regs[regno]) | |
4149 | bitmap_set_bit (&c->dead_or_set, regno); | |
4150 | } | |
4151 | else if (pseudo_for_reload_consideration_p (regno)) | |
4152 | bitmap_set_bit (&c->dead_or_set, regno); | |
4153 | } | |
4154 | ||
4155 | if ((regno < FIRST_PSEUDO_REGISTER | |
4156 | || reg_renumber[regno] >= 0 | |
4157 | || ira_conflicts_p) | |
4158 | && (!DF_REF_FLAGS_IS_SET (def, DF_REF_CONDITIONAL))) | |
4159 | { | |
4160 | rtx reg = DF_REF_REG (def); | |
4161 | ||
4162 | /* We can model subregs, but not if they are | |
4163 | wrapped in ZERO_EXTRACTS. */ | |
4164 | if (GET_CODE (reg) == SUBREG | |
4165 | && !DF_REF_FLAGS_IS_SET (def, DF_REF_ZERO_EXTRACT)) | |
4166 | { | |
4167 | unsigned int start = SUBREG_BYTE (reg); | |
b8698a0f | 4168 | unsigned int last = start |
2af2dbdc VM |
4169 | + GET_MODE_SIZE (GET_MODE (reg)); |
4170 | ||
4171 | init_live_subregs | |
b8698a0f | 4172 | (bitmap_bit_p (live_relevant_regs, regno), |
2af2dbdc VM |
4173 | live_subregs, live_subregs_used, regno, reg); |
4174 | ||
4175 | if (!DF_REF_FLAGS_IS_SET | |
4176 | (def, DF_REF_STRICT_LOW_PART)) | |
4177 | { | |
4178 | /* Expand the range to cover entire words. | |
4179 | Bytes added here are "don't care". */ | |
4180 | start | |
4181 | = start / UNITS_PER_WORD * UNITS_PER_WORD; | |
4182 | last = ((last + UNITS_PER_WORD - 1) | |
4183 | / UNITS_PER_WORD * UNITS_PER_WORD); | |
4184 | } | |
4185 | ||
4186 | /* Ignore the paradoxical bits. */ | |
cee784f5 SB |
4187 | if (last > SBITMAP_SIZE (live_subregs[regno])) |
4188 | last = SBITMAP_SIZE (live_subregs[regno]); | |
2af2dbdc VM |
4189 | |
4190 | while (start < last) | |
4191 | { | |
d7c028c0 | 4192 | bitmap_clear_bit (live_subregs[regno], start); |
2af2dbdc VM |
4193 | start++; |
4194 | } | |
b8698a0f | 4195 | |
f61e445a | 4196 | if (bitmap_empty_p (live_subregs[regno])) |
2af2dbdc | 4197 | { |
cee784f5 | 4198 | bitmap_clear_bit (live_subregs_used, regno); |
2af2dbdc VM |
4199 | bitmap_clear_bit (live_relevant_regs, regno); |
4200 | } | |
4201 | else | |
4202 | /* Set live_relevant_regs here because | |
4203 | that bit has to be true to get us to | |
4204 | look at the live_subregs fields. */ | |
4205 | bitmap_set_bit (live_relevant_regs, regno); | |
4206 | } | |
4207 | else | |
4208 | { | |
4209 | /* DF_REF_PARTIAL is generated for | |
4210 | subregs, STRICT_LOW_PART, and | |
4211 | ZERO_EXTRACT. We handle the subreg | |
4212 | case above so here we have to keep from | |
4213 | modeling the def as a killing def. */ | |
4214 | if (!DF_REF_FLAGS_IS_SET (def, DF_REF_PARTIAL)) | |
4215 | { | |
cee784f5 | 4216 | bitmap_clear_bit (live_subregs_used, regno); |
2af2dbdc | 4217 | bitmap_clear_bit (live_relevant_regs, regno); |
2af2dbdc VM |
4218 | } |
4219 | } | |
4220 | } | |
4221 | } | |
b8698a0f | 4222 | |
2af2dbdc VM |
4223 | bitmap_and_compl_into (live_relevant_regs, elim_regset); |
4224 | bitmap_copy (&c->live_throughout, live_relevant_regs); | |
4225 | ||
4b71920a | 4226 | if (NONDEBUG_INSN_P (insn)) |
bfac633a | 4227 | FOR_EACH_INSN_INFO_USE (use, insn_info) |
2af2dbdc | 4228 | { |
2af2dbdc VM |
4229 | unsigned int regno = DF_REF_REGNO (use); |
4230 | rtx reg = DF_REF_REG (use); | |
b8698a0f | 4231 | |
2af2dbdc VM |
4232 | /* DF_REF_READ_WRITE on a use means that this use |
4233 | is fabricated from a def that is a partial set | |
4234 | to a multiword reg. Here, we only model the | |
4235 | subreg case that is not wrapped in ZERO_EXTRACT | |
4236 | precisely so we do not need to look at the | |
2b9c63a2 | 4237 | fabricated use. */ |
b8698a0f L |
4238 | if (DF_REF_FLAGS_IS_SET (use, DF_REF_READ_WRITE) |
4239 | && !DF_REF_FLAGS_IS_SET (use, DF_REF_ZERO_EXTRACT) | |
2af2dbdc VM |
4240 | && DF_REF_FLAGS_IS_SET (use, DF_REF_SUBREG)) |
4241 | continue; | |
b8698a0f | 4242 | |
2af2dbdc VM |
4243 | /* Add the last use of each var to dead_or_set. */ |
4244 | if (!bitmap_bit_p (live_relevant_regs, regno)) | |
4245 | { | |
4246 | if (regno < FIRST_PSEUDO_REGISTER) | |
4247 | { | |
4248 | if (!fixed_regs[regno]) | |
4249 | bitmap_set_bit (&c->dead_or_set, regno); | |
4250 | } | |
4251 | else if (pseudo_for_reload_consideration_p (regno)) | |
4252 | bitmap_set_bit (&c->dead_or_set, regno); | |
4253 | } | |
b8698a0f | 4254 | |
2af2dbdc VM |
4255 | if (regno < FIRST_PSEUDO_REGISTER |
4256 | || pseudo_for_reload_consideration_p (regno)) | |
4257 | { | |
4258 | if (GET_CODE (reg) == SUBREG | |
4259 | && !DF_REF_FLAGS_IS_SET (use, | |
4260 | DF_REF_SIGN_EXTRACT | |
b8698a0f | 4261 | | DF_REF_ZERO_EXTRACT)) |
2af2dbdc VM |
4262 | { |
4263 | unsigned int start = SUBREG_BYTE (reg); | |
b8698a0f | 4264 | unsigned int last = start |
2af2dbdc | 4265 | + GET_MODE_SIZE (GET_MODE (reg)); |
b8698a0f | 4266 | |
2af2dbdc | 4267 | init_live_subregs |
b8698a0f | 4268 | (bitmap_bit_p (live_relevant_regs, regno), |
2af2dbdc | 4269 | live_subregs, live_subregs_used, regno, reg); |
b8698a0f | 4270 | |
2af2dbdc | 4271 | /* Ignore the paradoxical bits. */ |
cee784f5 SB |
4272 | if (last > SBITMAP_SIZE (live_subregs[regno])) |
4273 | last = SBITMAP_SIZE (live_subregs[regno]); | |
2af2dbdc VM |
4274 | |
4275 | while (start < last) | |
4276 | { | |
d7c028c0 | 4277 | bitmap_set_bit (live_subregs[regno], start); |
2af2dbdc VM |
4278 | start++; |
4279 | } | |
4280 | } | |
4281 | else | |
4282 | /* Resetting the live_subregs_used is | |
4283 | effectively saying do not use the subregs | |
4284 | because we are reading the whole | |
4285 | pseudo. */ | |
cee784f5 | 4286 | bitmap_clear_bit (live_subregs_used, regno); |
2af2dbdc VM |
4287 | bitmap_set_bit (live_relevant_regs, regno); |
4288 | } | |
4289 | } | |
4290 | } | |
4291 | } | |
4292 | ||
4293 | /* FIXME!! The following code is a disaster. Reload needs to see the | |
4294 | labels and jump tables that are just hanging out in between | |
4295 | the basic blocks. See pr33676. */ | |
4296 | insn = BB_HEAD (bb); | |
b8698a0f | 4297 | |
2af2dbdc | 4298 | /* Skip over the barriers and cruft. */ |
b8698a0f | 4299 | while (insn && (BARRIER_P (insn) || NOTE_P (insn) |
2af2dbdc VM |
4300 | || BLOCK_FOR_INSN (insn) == bb)) |
4301 | insn = PREV_INSN (insn); | |
b8698a0f | 4302 | |
2af2dbdc VM |
4303 | /* While we add anything except barriers and notes, the focus is |
4304 | to get the labels and jump tables into the | |
4305 | reload_insn_chain. */ | |
4306 | while (insn) | |
4307 | { | |
4308 | if (!NOTE_P (insn) && !BARRIER_P (insn)) | |
4309 | { | |
4310 | if (BLOCK_FOR_INSN (insn)) | |
4311 | break; | |
b8698a0f | 4312 | |
2af2dbdc VM |
4313 | c = new_insn_chain (); |
4314 | c->next = next; | |
4315 | next = c; | |
4316 | *p = c; | |
4317 | p = &c->prev; | |
b8698a0f | 4318 | |
2af2dbdc VM |
4319 | /* The block makes no sense here, but it is what the old |
4320 | code did. */ | |
4321 | c->block = bb->index; | |
4322 | c->insn = insn; | |
4323 | bitmap_copy (&c->live_throughout, live_relevant_regs); | |
b8698a0f | 4324 | } |
2af2dbdc VM |
4325 | insn = PREV_INSN (insn); |
4326 | } | |
4327 | } | |
4328 | ||
2af2dbdc VM |
4329 | reload_insn_chain = c; |
4330 | *p = NULL; | |
4331 | ||
cee784f5 SB |
4332 | for (i = 0; i < (unsigned int) max_regno; i++) |
4333 | if (live_subregs[i] != NULL) | |
4334 | sbitmap_free (live_subregs[i]); | |
2af2dbdc | 4335 | free (live_subregs); |
2af2dbdc VM |
4336 | |
4337 | if (dump_file) | |
4338 | print_insn_chains (dump_file); | |
4339 | } | |
acf41a74 BS |
4340 | \f |
4341 | /* Examine the rtx found in *LOC, which is read or written to as determined | |
4342 | by TYPE. Return false if we find a reason why an insn containing this | |
4343 | rtx should not be moved (such as accesses to non-constant memory), true | |
4344 | otherwise. */ | |
4345 | static bool | |
4346 | rtx_moveable_p (rtx *loc, enum op_type type) | |
4347 | { | |
4348 | const char *fmt; | |
4349 | rtx x = *loc; | |
4350 | enum rtx_code code = GET_CODE (x); | |
4351 | int i, j; | |
4352 | ||
4353 | code = GET_CODE (x); | |
4354 | switch (code) | |
4355 | { | |
4356 | case CONST: | |
d8116890 | 4357 | CASE_CONST_ANY: |
acf41a74 BS |
4358 | case SYMBOL_REF: |
4359 | case LABEL_REF: | |
4360 | return true; | |
4361 | ||
4362 | case PC: | |
4363 | return type == OP_IN; | |
4364 | ||
4365 | case CC0: | |
4366 | return false; | |
4367 | ||
4368 | case REG: | |
4369 | if (x == frame_pointer_rtx) | |
4370 | return true; | |
4371 | if (HARD_REGISTER_P (x)) | |
4372 | return false; | |
4373 | ||
4374 | return true; | |
4375 | ||
4376 | case MEM: | |
4377 | if (type == OP_IN && MEM_READONLY_P (x)) | |
4378 | return rtx_moveable_p (&XEXP (x, 0), OP_IN); | |
4379 | return false; | |
4380 | ||
4381 | case SET: | |
4382 | return (rtx_moveable_p (&SET_SRC (x), OP_IN) | |
4383 | && rtx_moveable_p (&SET_DEST (x), OP_OUT)); | |
4384 | ||
4385 | case STRICT_LOW_PART: | |
4386 | return rtx_moveable_p (&XEXP (x, 0), OP_OUT); | |
4387 | ||
4388 | case ZERO_EXTRACT: | |
4389 | case SIGN_EXTRACT: | |
4390 | return (rtx_moveable_p (&XEXP (x, 0), type) | |
4391 | && rtx_moveable_p (&XEXP (x, 1), OP_IN) | |
4392 | && rtx_moveable_p (&XEXP (x, 2), OP_IN)); | |
4393 | ||
4394 | case CLOBBER: | |
4395 | return rtx_moveable_p (&SET_DEST (x), OP_OUT); | |
4396 | ||
d8c16744 | 4397 | case UNSPEC_VOLATILE: |
026c3cfd | 4398 | /* It is a bad idea to consider insns with such rtl |
d8c16744 VM |
4399 | as moveable ones. The insn scheduler also considers them as barrier |
4400 | for a reason. */ | |
4401 | return false; | |
4402 | ||
acf41a74 BS |
4403 | default: |
4404 | break; | |
4405 | } | |
4406 | ||
4407 | fmt = GET_RTX_FORMAT (code); | |
4408 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
4409 | { | |
4410 | if (fmt[i] == 'e') | |
4411 | { | |
4412 | if (!rtx_moveable_p (&XEXP (x, i), type)) | |
4413 | return false; | |
4414 | } | |
4415 | else if (fmt[i] == 'E') | |
4416 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
4417 | { | |
4418 | if (!rtx_moveable_p (&XVECEXP (x, i, j), type)) | |
4419 | return false; | |
4420 | } | |
4421 | } | |
4422 | return true; | |
4423 | } | |
4424 | ||
4425 | /* A wrapper around dominated_by_p, which uses the information in UID_LUID | |
4426 | to give dominance relationships between two insns I1 and I2. */ | |
4427 | static bool | |
4428 | insn_dominated_by_p (rtx i1, rtx i2, int *uid_luid) | |
4429 | { | |
4430 | basic_block bb1 = BLOCK_FOR_INSN (i1); | |
4431 | basic_block bb2 = BLOCK_FOR_INSN (i2); | |
4432 | ||
4433 | if (bb1 == bb2) | |
4434 | return uid_luid[INSN_UID (i2)] < uid_luid[INSN_UID (i1)]; | |
4435 | return dominated_by_p (CDI_DOMINATORS, bb1, bb2); | |
4436 | } | |
4437 | ||
4438 | /* Record the range of register numbers added by find_moveable_pseudos. */ | |
4439 | int first_moveable_pseudo, last_moveable_pseudo; | |
4440 | ||
4441 | /* These two vectors hold data for every register added by | |
4442 | find_movable_pseudos, with index 0 holding data for the | |
4443 | first_moveable_pseudo. */ | |
4444 | /* The original home register. */ | |
9771b263 | 4445 | static vec<rtx> pseudo_replaced_reg; |
acf41a74 BS |
4446 | |
4447 | /* Look for instances where we have an instruction that is known to increase | |
4448 | register pressure, and whose result is not used immediately. If it is | |
4449 | possible to move the instruction downwards to just before its first use, | |
4450 | split its lifetime into two ranges. We create a new pseudo to compute the | |
4451 | value, and emit a move instruction just before the first use. If, after | |
4452 | register allocation, the new pseudo remains unallocated, the function | |
4453 | move_unallocated_pseudos then deletes the move instruction and places | |
4454 | the computation just before the first use. | |
4455 | ||
4456 | Such a move is safe and profitable if all the input registers remain live | |
4457 | and unchanged between the original computation and its first use. In such | |
4458 | a situation, the computation is known to increase register pressure, and | |
4459 | moving it is known to at least not worsen it. | |
4460 | ||
4461 | We restrict moves to only those cases where a register remains unallocated, | |
4462 | in order to avoid interfering too much with the instruction schedule. As | |
4463 | an exception, we may move insns which only modify their input register | |
4464 | (typically induction variables), as this increases the freedom for our | |
4465 | intended transformation, and does not limit the second instruction | |
4466 | scheduler pass. */ | |
4467 | ||
4468 | static void | |
4469 | find_moveable_pseudos (void) | |
4470 | { | |
4471 | unsigned i; | |
4472 | int max_regs = max_reg_num (); | |
4473 | int max_uid = get_max_uid (); | |
4474 | basic_block bb; | |
4475 | int *uid_luid = XNEWVEC (int, max_uid); | |
070a1983 | 4476 | rtx_insn **closest_uses = XNEWVEC (rtx_insn *, max_regs); |
acf41a74 | 4477 | /* A set of registers which are live but not modified throughout a block. */ |
8b1c6fd7 DM |
4478 | bitmap_head *bb_transp_live = XNEWVEC (bitmap_head, |
4479 | last_basic_block_for_fn (cfun)); | |
acf41a74 | 4480 | /* A set of registers which only exist in a given basic block. */ |
8b1c6fd7 DM |
4481 | bitmap_head *bb_local = XNEWVEC (bitmap_head, |
4482 | last_basic_block_for_fn (cfun)); | |
acf41a74 BS |
4483 | /* A set of registers which are set once, in an instruction that can be |
4484 | moved freely downwards, but are otherwise transparent to a block. */ | |
8b1c6fd7 DM |
4485 | bitmap_head *bb_moveable_reg_sets = XNEWVEC (bitmap_head, |
4486 | last_basic_block_for_fn (cfun)); | |
8f9b31f7 | 4487 | auto_bitmap live, used, set, interesting, unusable_as_input; |
acf41a74 | 4488 | bitmap_iterator bi; |
acf41a74 BS |
4489 | |
4490 | first_moveable_pseudo = max_regs; | |
9771b263 DN |
4491 | pseudo_replaced_reg.release (); |
4492 | pseudo_replaced_reg.safe_grow_cleared (max_regs); | |
acf41a74 | 4493 | |
2d73cc45 MJ |
4494 | df_analyze (); |
4495 | calculate_dominance_info (CDI_DOMINATORS); | |
4496 | ||
acf41a74 | 4497 | i = 0; |
11cd3bed | 4498 | FOR_EACH_BB_FN (bb, cfun) |
acf41a74 | 4499 | { |
070a1983 | 4500 | rtx_insn *insn; |
acf41a74 BS |
4501 | bitmap transp = bb_transp_live + bb->index; |
4502 | bitmap moveable = bb_moveable_reg_sets + bb->index; | |
4503 | bitmap local = bb_local + bb->index; | |
4504 | ||
4505 | bitmap_initialize (local, 0); | |
4506 | bitmap_initialize (transp, 0); | |
4507 | bitmap_initialize (moveable, 0); | |
8f9b31f7 TS |
4508 | bitmap_copy (live, df_get_live_out (bb)); |
4509 | bitmap_and_into (live, df_get_live_in (bb)); | |
4510 | bitmap_copy (transp, live); | |
acf41a74 | 4511 | bitmap_clear (moveable); |
8f9b31f7 TS |
4512 | bitmap_clear (live); |
4513 | bitmap_clear (used); | |
4514 | bitmap_clear (set); | |
acf41a74 BS |
4515 | FOR_BB_INSNS (bb, insn) |
4516 | if (NONDEBUG_INSN_P (insn)) | |
4517 | { | |
bfac633a | 4518 | df_insn_info *insn_info = DF_INSN_INFO_GET (insn); |
bfac633a | 4519 | df_ref def, use; |
acf41a74 BS |
4520 | |
4521 | uid_luid[INSN_UID (insn)] = i++; | |
4522 | ||
74e59b6c RS |
4523 | def = df_single_def (insn_info); |
4524 | use = df_single_use (insn_info); | |
4525 | if (use | |
4526 | && def | |
4527 | && DF_REF_REGNO (use) == DF_REF_REGNO (def) | |
8f9b31f7 | 4528 | && !bitmap_bit_p (set, DF_REF_REGNO (use)) |
acf41a74 BS |
4529 | && rtx_moveable_p (&PATTERN (insn), OP_IN)) |
4530 | { | |
74e59b6c | 4531 | unsigned regno = DF_REF_REGNO (use); |
acf41a74 | 4532 | bitmap_set_bit (moveable, regno); |
8f9b31f7 TS |
4533 | bitmap_set_bit (set, regno); |
4534 | bitmap_set_bit (used, regno); | |
acf41a74 BS |
4535 | bitmap_clear_bit (transp, regno); |
4536 | continue; | |
4537 | } | |
bfac633a | 4538 | FOR_EACH_INSN_INFO_USE (use, insn_info) |
acf41a74 | 4539 | { |
bfac633a | 4540 | unsigned regno = DF_REF_REGNO (use); |
8f9b31f7 | 4541 | bitmap_set_bit (used, regno); |
acf41a74 BS |
4542 | if (bitmap_clear_bit (moveable, regno)) |
4543 | bitmap_clear_bit (transp, regno); | |
acf41a74 BS |
4544 | } |
4545 | ||
bfac633a | 4546 | FOR_EACH_INSN_INFO_DEF (def, insn_info) |
acf41a74 | 4547 | { |
bfac633a | 4548 | unsigned regno = DF_REF_REGNO (def); |
8f9b31f7 | 4549 | bitmap_set_bit (set, regno); |
acf41a74 BS |
4550 | bitmap_clear_bit (transp, regno); |
4551 | bitmap_clear_bit (moveable, regno); | |
acf41a74 BS |
4552 | } |
4553 | } | |
4554 | } | |
4555 | ||
11cd3bed | 4556 | FOR_EACH_BB_FN (bb, cfun) |
acf41a74 BS |
4557 | { |
4558 | bitmap local = bb_local + bb->index; | |
070a1983 | 4559 | rtx_insn *insn; |
acf41a74 BS |
4560 | |
4561 | FOR_BB_INSNS (bb, insn) | |
4562 | if (NONDEBUG_INSN_P (insn)) | |
4563 | { | |
74e59b6c | 4564 | df_insn_info *insn_info = DF_INSN_INFO_GET (insn); |
070a1983 DM |
4565 | rtx_insn *def_insn; |
4566 | rtx closest_use, note; | |
74e59b6c | 4567 | df_ref def, use; |
acf41a74 BS |
4568 | unsigned regno; |
4569 | bool all_dominated, all_local; | |
ef4bddc2 | 4570 | machine_mode mode; |
acf41a74 | 4571 | |
74e59b6c | 4572 | def = df_single_def (insn_info); |
acf41a74 | 4573 | /* There must be exactly one def in this insn. */ |
74e59b6c | 4574 | if (!def || !single_set (insn)) |
acf41a74 BS |
4575 | continue; |
4576 | /* This must be the only definition of the reg. We also limit | |
4577 | which modes we deal with so that we can assume we can generate | |
4578 | move instructions. */ | |
4579 | regno = DF_REF_REGNO (def); | |
4580 | mode = GET_MODE (DF_REF_REG (def)); | |
4581 | if (DF_REG_DEF_COUNT (regno) != 1 | |
4582 | || !DF_REF_INSN_INFO (def) | |
4583 | || HARD_REGISTER_NUM_P (regno) | |
aa44c80c | 4584 | || DF_REG_EQ_USE_COUNT (regno) > 0 |
acf41a74 BS |
4585 | || (!INTEGRAL_MODE_P (mode) && !FLOAT_MODE_P (mode))) |
4586 | continue; | |
4587 | def_insn = DF_REF_INSN (def); | |
4588 | ||
4589 | for (note = REG_NOTES (def_insn); note; note = XEXP (note, 1)) | |
4590 | if (REG_NOTE_KIND (note) == REG_EQUIV && MEM_P (XEXP (note, 0))) | |
4591 | break; | |
4592 | ||
4593 | if (note) | |
4594 | { | |
4595 | if (dump_file) | |
4596 | fprintf (dump_file, "Ignoring reg %d, has equiv memory\n", | |
4597 | regno); | |
8f9b31f7 | 4598 | bitmap_set_bit (unusable_as_input, regno); |
acf41a74 BS |
4599 | continue; |
4600 | } | |
4601 | ||
4602 | use = DF_REG_USE_CHAIN (regno); | |
4603 | all_dominated = true; | |
4604 | all_local = true; | |
4605 | closest_use = NULL_RTX; | |
4606 | for (; use; use = DF_REF_NEXT_REG (use)) | |
4607 | { | |
070a1983 | 4608 | rtx_insn *insn; |
acf41a74 BS |
4609 | if (!DF_REF_INSN_INFO (use)) |
4610 | { | |
4611 | all_dominated = false; | |
4612 | all_local = false; | |
4613 | break; | |
4614 | } | |
4615 | insn = DF_REF_INSN (use); | |
4616 | if (DEBUG_INSN_P (insn)) | |
4617 | continue; | |
4618 | if (BLOCK_FOR_INSN (insn) != BLOCK_FOR_INSN (def_insn)) | |
4619 | all_local = false; | |
4620 | if (!insn_dominated_by_p (insn, def_insn, uid_luid)) | |
4621 | all_dominated = false; | |
4622 | if (closest_use != insn && closest_use != const0_rtx) | |
4623 | { | |
4624 | if (closest_use == NULL_RTX) | |
4625 | closest_use = insn; | |
4626 | else if (insn_dominated_by_p (closest_use, insn, uid_luid)) | |
4627 | closest_use = insn; | |
4628 | else if (!insn_dominated_by_p (insn, closest_use, uid_luid)) | |
4629 | closest_use = const0_rtx; | |
4630 | } | |
4631 | } | |
4632 | if (!all_dominated) | |
4633 | { | |
4634 | if (dump_file) | |
4635 | fprintf (dump_file, "Reg %d not all uses dominated by set\n", | |
4636 | regno); | |
4637 | continue; | |
4638 | } | |
4639 | if (all_local) | |
4640 | bitmap_set_bit (local, regno); | |
4641 | if (closest_use == const0_rtx || closest_use == NULL | |
4642 | || next_nonnote_nondebug_insn (def_insn) == closest_use) | |
4643 | { | |
4644 | if (dump_file) | |
4645 | fprintf (dump_file, "Reg %d uninteresting%s\n", regno, | |
4646 | closest_use == const0_rtx || closest_use == NULL | |
4647 | ? " (no unique first use)" : ""); | |
4648 | continue; | |
4649 | } | |
058eb3b0 | 4650 | if (HAVE_cc0 && reg_referenced_p (cc0_rtx, PATTERN (closest_use))) |
acf41a74 BS |
4651 | { |
4652 | if (dump_file) | |
4653 | fprintf (dump_file, "Reg %d: closest user uses cc0\n", | |
4654 | regno); | |
4655 | continue; | |
4656 | } | |
058eb3b0 | 4657 | |
8f9b31f7 | 4658 | bitmap_set_bit (interesting, regno); |
070a1983 DM |
4659 | /* If we get here, we know closest_use is a non-NULL insn |
4660 | (as opposed to const_0_rtx). */ | |
4661 | closest_uses[regno] = as_a <rtx_insn *> (closest_use); | |
acf41a74 BS |
4662 | |
4663 | if (dump_file && (all_local || all_dominated)) | |
4664 | { | |
4665 | fprintf (dump_file, "Reg %u:", regno); | |
4666 | if (all_local) | |
4667 | fprintf (dump_file, " local to bb %d", bb->index); | |
4668 | if (all_dominated) | |
4669 | fprintf (dump_file, " def dominates all uses"); | |
4670 | if (closest_use != const0_rtx) | |
4671 | fprintf (dump_file, " has unique first use"); | |
4672 | fputs ("\n", dump_file); | |
4673 | } | |
4674 | } | |
4675 | } | |
4676 | ||
8f9b31f7 | 4677 | EXECUTE_IF_SET_IN_BITMAP (interesting, 0, i, bi) |
acf41a74 BS |
4678 | { |
4679 | df_ref def = DF_REG_DEF_CHAIN (i); | |
070a1983 | 4680 | rtx_insn *def_insn = DF_REF_INSN (def); |
acf41a74 BS |
4681 | basic_block def_block = BLOCK_FOR_INSN (def_insn); |
4682 | bitmap def_bb_local = bb_local + def_block->index; | |
4683 | bitmap def_bb_moveable = bb_moveable_reg_sets + def_block->index; | |
4684 | bitmap def_bb_transp = bb_transp_live + def_block->index; | |
4685 | bool local_to_bb_p = bitmap_bit_p (def_bb_local, i); | |
070a1983 | 4686 | rtx_insn *use_insn = closest_uses[i]; |
bfac633a | 4687 | df_ref use; |
acf41a74 BS |
4688 | bool all_ok = true; |
4689 | bool all_transp = true; | |
4690 | ||
4691 | if (!REG_P (DF_REF_REG (def))) | |
4692 | continue; | |
4693 | ||
4694 | if (!local_to_bb_p) | |
4695 | { | |
4696 | if (dump_file) | |
4697 | fprintf (dump_file, "Reg %u not local to one basic block\n", | |
4698 | i); | |
4699 | continue; | |
4700 | } | |
4701 | if (reg_equiv_init (i) != NULL_RTX) | |
4702 | { | |
4703 | if (dump_file) | |
4704 | fprintf (dump_file, "Ignoring reg %u with equiv init insn\n", | |
4705 | i); | |
4706 | continue; | |
4707 | } | |
4708 | if (!rtx_moveable_p (&PATTERN (def_insn), OP_IN)) | |
4709 | { | |
4710 | if (dump_file) | |
4711 | fprintf (dump_file, "Found def insn %d for %d to be not moveable\n", | |
4712 | INSN_UID (def_insn), i); | |
4713 | continue; | |
4714 | } | |
4715 | if (dump_file) | |
4716 | fprintf (dump_file, "Examining insn %d, def for %d\n", | |
4717 | INSN_UID (def_insn), i); | |
bfac633a | 4718 | FOR_EACH_INSN_USE (use, def_insn) |
acf41a74 | 4719 | { |
acf41a74 | 4720 | unsigned regno = DF_REF_REGNO (use); |
8f9b31f7 | 4721 | if (bitmap_bit_p (unusable_as_input, regno)) |
acf41a74 BS |
4722 | { |
4723 | all_ok = false; | |
4724 | if (dump_file) | |
4725 | fprintf (dump_file, " found unusable input reg %u.\n", regno); | |
4726 | break; | |
4727 | } | |
4728 | if (!bitmap_bit_p (def_bb_transp, regno)) | |
4729 | { | |
4730 | if (bitmap_bit_p (def_bb_moveable, regno) | |
4731 | && !control_flow_insn_p (use_insn) | |
618f4073 | 4732 | && (!HAVE_cc0 || !sets_cc0_p (use_insn))) |
acf41a74 BS |
4733 | { |
4734 | if (modified_between_p (DF_REF_REG (use), def_insn, use_insn)) | |
4735 | { | |
070a1983 | 4736 | rtx_insn *x = NEXT_INSN (def_insn); |
acf41a74 BS |
4737 | while (!modified_in_p (DF_REF_REG (use), x)) |
4738 | { | |
4739 | gcc_assert (x != use_insn); | |
4740 | x = NEXT_INSN (x); | |
4741 | } | |
4742 | if (dump_file) | |
4743 | fprintf (dump_file, " input reg %u modified but insn %d moveable\n", | |
4744 | regno, INSN_UID (x)); | |
4745 | emit_insn_after (PATTERN (x), use_insn); | |
4746 | set_insn_deleted (x); | |
4747 | } | |
4748 | else | |
4749 | { | |
4750 | if (dump_file) | |
4751 | fprintf (dump_file, " input reg %u modified between def and use\n", | |
4752 | regno); | |
4753 | all_transp = false; | |
4754 | } | |
4755 | } | |
4756 | else | |
4757 | all_transp = false; | |
4758 | } | |
acf41a74 BS |
4759 | } |
4760 | if (!all_ok) | |
4761 | continue; | |
4762 | if (!dbg_cnt (ira_move)) | |
4763 | break; | |
4764 | if (dump_file) | |
4765 | fprintf (dump_file, " all ok%s\n", all_transp ? " and transp" : ""); | |
4766 | ||
4767 | if (all_transp) | |
4768 | { | |
4769 | rtx def_reg = DF_REF_REG (def); | |
4770 | rtx newreg = ira_create_new_reg (def_reg); | |
9e3de74c | 4771 | if (validate_change (def_insn, DF_REF_REAL_LOC (def), newreg, 0)) |
acf41a74 BS |
4772 | { |
4773 | unsigned nregno = REGNO (newreg); | |
a36b2706 | 4774 | emit_insn_before (gen_move_insn (def_reg, newreg), use_insn); |
acf41a74 | 4775 | nregno -= max_regs; |
9771b263 | 4776 | pseudo_replaced_reg[nregno] = def_reg; |
acf41a74 BS |
4777 | } |
4778 | } | |
4779 | } | |
4780 | ||
11cd3bed | 4781 | FOR_EACH_BB_FN (bb, cfun) |
acf41a74 BS |
4782 | { |
4783 | bitmap_clear (bb_local + bb->index); | |
4784 | bitmap_clear (bb_transp_live + bb->index); | |
4785 | bitmap_clear (bb_moveable_reg_sets + bb->index); | |
4786 | } | |
acf41a74 BS |
4787 | free (uid_luid); |
4788 | free (closest_uses); | |
4789 | free (bb_local); | |
4790 | free (bb_transp_live); | |
4791 | free (bb_moveable_reg_sets); | |
4792 | ||
4793 | last_moveable_pseudo = max_reg_num (); | |
2d73cc45 MJ |
4794 | |
4795 | fix_reg_equiv_init (); | |
4796 | expand_reg_info (); | |
4797 | regstat_free_n_sets_and_refs (); | |
4798 | regstat_free_ri (); | |
4799 | regstat_init_n_sets_and_refs (); | |
4800 | regstat_compute_ri (); | |
4801 | free_dominance_info (CDI_DOMINATORS); | |
732dad8f | 4802 | } |
acf41a74 | 4803 | |
3e749749 MJ |
4804 | /* If SET pattern SET is an assignment from a hard register to a pseudo which |
4805 | is live at CALL_DOM (if non-NULL, otherwise this check is omitted), return | |
4806 | the destination. Otherwise return NULL. */ | |
732dad8f MJ |
4807 | |
4808 | static rtx | |
3e749749 | 4809 | interesting_dest_for_shprep_1 (rtx set, basic_block call_dom) |
732dad8f | 4810 | { |
732dad8f MJ |
4811 | rtx src = SET_SRC (set); |
4812 | rtx dest = SET_DEST (set); | |
4813 | if (!REG_P (src) || !HARD_REGISTER_P (src) | |
4814 | || !REG_P (dest) || HARD_REGISTER_P (dest) | |
4815 | || (call_dom && !bitmap_bit_p (df_get_live_in (call_dom), REGNO (dest)))) | |
4816 | return NULL; | |
4817 | return dest; | |
4818 | } | |
4819 | ||
df3e3493 | 4820 | /* If insn is interesting for parameter range-splitting shrink-wrapping |
3e749749 MJ |
4821 | preparation, i.e. it is a single set from a hard register to a pseudo, which |
4822 | is live at CALL_DOM (if non-NULL, otherwise this check is omitted), or a | |
4823 | parallel statement with only one such statement, return the destination. | |
4824 | Otherwise return NULL. */ | |
4825 | ||
4826 | static rtx | |
070a1983 | 4827 | interesting_dest_for_shprep (rtx_insn *insn, basic_block call_dom) |
3e749749 MJ |
4828 | { |
4829 | if (!INSN_P (insn)) | |
4830 | return NULL; | |
4831 | rtx pat = PATTERN (insn); | |
4832 | if (GET_CODE (pat) == SET) | |
4833 | return interesting_dest_for_shprep_1 (pat, call_dom); | |
4834 | ||
4835 | if (GET_CODE (pat) != PARALLEL) | |
4836 | return NULL; | |
4837 | rtx ret = NULL; | |
4838 | for (int i = 0; i < XVECLEN (pat, 0); i++) | |
4839 | { | |
4840 | rtx sub = XVECEXP (pat, 0, i); | |
4841 | if (GET_CODE (sub) == USE || GET_CODE (sub) == CLOBBER) | |
4842 | continue; | |
4843 | if (GET_CODE (sub) != SET | |
4844 | || side_effects_p (sub)) | |
4845 | return NULL; | |
4846 | rtx dest = interesting_dest_for_shprep_1 (sub, call_dom); | |
4847 | if (dest && ret) | |
4848 | return NULL; | |
4849 | if (dest) | |
4850 | ret = dest; | |
4851 | } | |
4852 | return ret; | |
4853 | } | |
4854 | ||
732dad8f MJ |
4855 | /* Split live ranges of pseudos that are loaded from hard registers in the |
4856 | first BB in a BB that dominates all non-sibling call if such a BB can be | |
4857 | found and is not in a loop. Return true if the function has made any | |
4858 | changes. */ | |
4859 | ||
4860 | static bool | |
4861 | split_live_ranges_for_shrink_wrap (void) | |
4862 | { | |
4863 | basic_block bb, call_dom = NULL; | |
fefa31b5 | 4864 | basic_block first = single_succ (ENTRY_BLOCK_PTR_FOR_FN (cfun)); |
070a1983 | 4865 | rtx_insn *insn, *last_interesting_insn = NULL; |
8f9b31f7 | 4866 | auto_bitmap need_new, reachable; |
732dad8f MJ |
4867 | vec<basic_block> queue; |
4868 | ||
a5e022d5 | 4869 | if (!SHRINK_WRAPPING_ENABLED) |
732dad8f MJ |
4870 | return false; |
4871 | ||
0cae8d31 | 4872 | queue.create (n_basic_blocks_for_fn (cfun)); |
732dad8f | 4873 | |
11cd3bed | 4874 | FOR_EACH_BB_FN (bb, cfun) |
732dad8f MJ |
4875 | FOR_BB_INSNS (bb, insn) |
4876 | if (CALL_P (insn) && !SIBLING_CALL_P (insn)) | |
4877 | { | |
4878 | if (bb == first) | |
4879 | { | |
732dad8f MJ |
4880 | queue.release (); |
4881 | return false; | |
4882 | } | |
4883 | ||
8f9b31f7 TS |
4884 | bitmap_set_bit (need_new, bb->index); |
4885 | bitmap_set_bit (reachable, bb->index); | |
732dad8f MJ |
4886 | queue.quick_push (bb); |
4887 | break; | |
4888 | } | |
4889 | ||
4890 | if (queue.is_empty ()) | |
4891 | { | |
732dad8f MJ |
4892 | queue.release (); |
4893 | return false; | |
4894 | } | |
4895 | ||
4896 | while (!queue.is_empty ()) | |
4897 | { | |
4898 | edge e; | |
4899 | edge_iterator ei; | |
4900 | ||
4901 | bb = queue.pop (); | |
4902 | FOR_EACH_EDGE (e, ei, bb->succs) | |
fefa31b5 | 4903 | if (e->dest != EXIT_BLOCK_PTR_FOR_FN (cfun) |
8f9b31f7 | 4904 | && bitmap_set_bit (reachable, e->dest->index)) |
732dad8f MJ |
4905 | queue.quick_push (e->dest); |
4906 | } | |
4907 | queue.release (); | |
4908 | ||
4909 | FOR_BB_INSNS (first, insn) | |
4910 | { | |
4911 | rtx dest = interesting_dest_for_shprep (insn, NULL); | |
4912 | if (!dest) | |
4913 | continue; | |
4914 | ||
4915 | if (DF_REG_DEF_COUNT (REGNO (dest)) > 1) | |
8f9b31f7 | 4916 | return false; |
732dad8f MJ |
4917 | |
4918 | for (df_ref use = DF_REG_USE_CHAIN (REGNO(dest)); | |
4919 | use; | |
4920 | use = DF_REF_NEXT_REG (use)) | |
4921 | { | |
732dad8f | 4922 | int ubbi = DF_REF_BB (use)->index; |
8f9b31f7 TS |
4923 | if (bitmap_bit_p (reachable, ubbi)) |
4924 | bitmap_set_bit (need_new, ubbi); | |
732dad8f MJ |
4925 | } |
4926 | last_interesting_insn = insn; | |
4927 | } | |
4928 | ||
732dad8f | 4929 | if (!last_interesting_insn) |
8f9b31f7 | 4930 | return false; |
732dad8f | 4931 | |
8f9b31f7 | 4932 | call_dom = nearest_common_dominator_for_set (CDI_DOMINATORS, need_new); |
732dad8f MJ |
4933 | if (call_dom == first) |
4934 | return false; | |
4935 | ||
4936 | loop_optimizer_init (AVOID_CFG_MODIFICATIONS); | |
4937 | while (bb_loop_depth (call_dom) > 0) | |
4938 | call_dom = get_immediate_dominator (CDI_DOMINATORS, call_dom); | |
4939 | loop_optimizer_finalize (); | |
4940 | ||
4941 | if (call_dom == first) | |
4942 | return false; | |
4943 | ||
4944 | calculate_dominance_info (CDI_POST_DOMINATORS); | |
4945 | if (dominated_by_p (CDI_POST_DOMINATORS, first, call_dom)) | |
4946 | { | |
4947 | free_dominance_info (CDI_POST_DOMINATORS); | |
4948 | return false; | |
4949 | } | |
4950 | free_dominance_info (CDI_POST_DOMINATORS); | |
4951 | ||
4952 | if (dump_file) | |
4953 | fprintf (dump_file, "Will split live ranges of parameters at BB %i\n", | |
4954 | call_dom->index); | |
4955 | ||
4956 | bool ret = false; | |
4957 | FOR_BB_INSNS (first, insn) | |
4958 | { | |
4959 | rtx dest = interesting_dest_for_shprep (insn, call_dom); | |
bcb21886 | 4960 | if (!dest || dest == pic_offset_table_rtx) |
732dad8f MJ |
4961 | continue; |
4962 | ||
fd1ca3fe | 4963 | bool need_newreg = false; |
732dad8f | 4964 | df_ref use, next; |
9e3de74c | 4965 | for (use = DF_REG_USE_CHAIN (REGNO (dest)); use; use = next) |
732dad8f | 4966 | { |
070a1983 | 4967 | rtx_insn *uin = DF_REF_INSN (use); |
732dad8f MJ |
4968 | next = DF_REF_NEXT_REG (use); |
4969 | ||
fd1ca3fe SB |
4970 | if (DEBUG_INSN_P (uin)) |
4971 | continue; | |
4972 | ||
732dad8f MJ |
4973 | basic_block ubb = BLOCK_FOR_INSN (uin); |
4974 | if (ubb == call_dom | |
4975 | || dominated_by_p (CDI_DOMINATORS, ubb, call_dom)) | |
4976 | { | |
fd1ca3fe SB |
4977 | need_newreg = true; |
4978 | break; | |
732dad8f MJ |
4979 | } |
4980 | } | |
4981 | ||
fd1ca3fe | 4982 | if (need_newreg) |
732dad8f | 4983 | { |
fd1ca3fe SB |
4984 | rtx newreg = ira_create_new_reg (dest); |
4985 | ||
4986 | for (use = DF_REG_USE_CHAIN (REGNO (dest)); use; use = next) | |
4987 | { | |
4988 | rtx_insn *uin = DF_REF_INSN (use); | |
4989 | next = DF_REF_NEXT_REG (use); | |
4990 | ||
4991 | basic_block ubb = BLOCK_FOR_INSN (uin); | |
4992 | if (ubb == call_dom | |
4993 | || dominated_by_p (CDI_DOMINATORS, ubb, call_dom)) | |
4994 | validate_change (uin, DF_REF_REAL_LOC (use), newreg, true); | |
4995 | } | |
4996 | ||
1476d1bd | 4997 | rtx_insn *new_move = gen_move_insn (newreg, dest); |
732dad8f MJ |
4998 | emit_insn_after (new_move, bb_note (call_dom)); |
4999 | if (dump_file) | |
5000 | { | |
5001 | fprintf (dump_file, "Split live-range of register "); | |
5002 | print_rtl_single (dump_file, dest); | |
5003 | } | |
5004 | ret = true; | |
5005 | } | |
5006 | ||
5007 | if (insn == last_interesting_insn) | |
5008 | break; | |
5009 | } | |
5010 | apply_change_group (); | |
5011 | return ret; | |
acf41a74 | 5012 | } |
8ff49c29 | 5013 | |
acf41a74 BS |
5014 | /* Perform the second half of the transformation started in |
5015 | find_moveable_pseudos. We look for instances where the newly introduced | |
5016 | pseudo remains unallocated, and remove it by moving the definition to | |
5017 | just before its use, replacing the move instruction generated by | |
5018 | find_moveable_pseudos. */ | |
5019 | static void | |
5020 | move_unallocated_pseudos (void) | |
5021 | { | |
5022 | int i; | |
5023 | for (i = first_moveable_pseudo; i < last_moveable_pseudo; i++) | |
5024 | if (reg_renumber[i] < 0) | |
5025 | { | |
acf41a74 | 5026 | int idx = i - first_moveable_pseudo; |
9771b263 | 5027 | rtx other_reg = pseudo_replaced_reg[idx]; |
070a1983 | 5028 | rtx_insn *def_insn = DF_REF_INSN (DF_REG_DEF_CHAIN (i)); |
a36b2706 RS |
5029 | /* The use must follow all definitions of OTHER_REG, so we can |
5030 | insert the new definition immediately after any of them. */ | |
5031 | df_ref other_def = DF_REG_DEF_CHAIN (REGNO (other_reg)); | |
070a1983 DM |
5032 | rtx_insn *move_insn = DF_REF_INSN (other_def); |
5033 | rtx_insn *newinsn = emit_insn_after (PATTERN (def_insn), move_insn); | |
a36b2706 | 5034 | rtx set; |
acf41a74 BS |
5035 | int success; |
5036 | ||
5037 | if (dump_file) | |
5038 | fprintf (dump_file, "moving def of %d (insn %d now) ", | |
5039 | REGNO (other_reg), INSN_UID (def_insn)); | |
5040 | ||
a36b2706 RS |
5041 | delete_insn (move_insn); |
5042 | while ((other_def = DF_REG_DEF_CHAIN (REGNO (other_reg)))) | |
5043 | delete_insn (DF_REF_INSN (other_def)); | |
5044 | delete_insn (def_insn); | |
5045 | ||
acf41a74 BS |
5046 | set = single_set (newinsn); |
5047 | success = validate_change (newinsn, &SET_DEST (set), other_reg, 0); | |
5048 | gcc_assert (success); | |
5049 | if (dump_file) | |
5050 | fprintf (dump_file, " %d) rather than keep unallocated replacement %d\n", | |
5051 | INSN_UID (newinsn), i); | |
acf41a74 BS |
5052 | SET_REG_N_REFS (i, 0); |
5053 | } | |
5054 | } | |
f2034d06 | 5055 | \f |
6399c0ab SB |
5056 | /* If the backend knows where to allocate pseudos for hard |
5057 | register initial values, register these allocations now. */ | |
a932fb89 | 5058 | static void |
6399c0ab SB |
5059 | allocate_initial_values (void) |
5060 | { | |
5061 | if (targetm.allocate_initial_value) | |
5062 | { | |
5063 | rtx hreg, preg, x; | |
5064 | int i, regno; | |
5065 | ||
5066 | for (i = 0; HARD_REGISTER_NUM_P (i); i++) | |
5067 | { | |
5068 | if (! initial_value_entry (i, &hreg, &preg)) | |
5069 | break; | |
5070 | ||
5071 | x = targetm.allocate_initial_value (hreg); | |
5072 | regno = REGNO (preg); | |
5073 | if (x && REG_N_SETS (regno) <= 1) | |
5074 | { | |
5075 | if (MEM_P (x)) | |
5076 | reg_equiv_memory_loc (regno) = x; | |
5077 | else | |
5078 | { | |
5079 | basic_block bb; | |
5080 | int new_regno; | |
5081 | ||
5082 | gcc_assert (REG_P (x)); | |
5083 | new_regno = REGNO (x); | |
5084 | reg_renumber[regno] = new_regno; | |
5085 | /* Poke the regno right into regno_reg_rtx so that even | |
5086 | fixed regs are accepted. */ | |
5087 | SET_REGNO (preg, new_regno); | |
5088 | /* Update global register liveness information. */ | |
11cd3bed | 5089 | FOR_EACH_BB_FN (bb, cfun) |
6399c0ab | 5090 | { |
c3284718 | 5091 | if (REGNO_REG_SET_P (df_get_live_in (bb), regno)) |
6399c0ab | 5092 | SET_REGNO_REG_SET (df_get_live_in (bb), new_regno); |
c3284718 | 5093 | if (REGNO_REG_SET_P (df_get_live_out (bb), regno)) |
6399c0ab SB |
5094 | SET_REGNO_REG_SET (df_get_live_out (bb), new_regno); |
5095 | } | |
5096 | } | |
5097 | } | |
5098 | } | |
2af2dbdc | 5099 | |
6399c0ab SB |
5100 | gcc_checking_assert (! initial_value_entry (FIRST_PSEUDO_REGISTER, |
5101 | &hreg, &preg)); | |
5102 | } | |
5103 | } | |
5104 | \f | |
55a2c322 VM |
5105 | |
5106 | /* True when we use LRA instead of reload pass for the current | |
5107 | function. */ | |
5108 | bool ira_use_lra_p; | |
5109 | ||
311aab06 VM |
5110 | /* True if we have allocno conflicts. It is false for non-optimized |
5111 | mode or when the conflict table is too big. */ | |
5112 | bool ira_conflicts_p; | |
5113 | ||
ae2b9cb6 BS |
5114 | /* Saved between IRA and reload. */ |
5115 | static int saved_flag_ira_share_spill_slots; | |
5116 | ||
058e97ec VM |
5117 | /* This is the main entry of IRA. */ |
5118 | static void | |
5119 | ira (FILE *f) | |
5120 | { | |
058e97ec | 5121 | bool loops_p; |
70cc3288 | 5122 | int ira_max_point_before_emit; |
55a2c322 VM |
5123 | bool saved_flag_caller_saves = flag_caller_saves; |
5124 | enum ira_region saved_flag_ira_region = flag_ira_region; | |
5125 | ||
62869a1c RB |
5126 | clear_bb_flags (); |
5127 | ||
0064f49e WD |
5128 | /* Determine if the current function is a leaf before running IRA |
5129 | since this can impact optimizations done by the prologue and | |
5130 | epilogue thus changing register elimination offsets. | |
5131 | Other target callbacks may use crtl->is_leaf too, including | |
5132 | SHRINK_WRAPPING_ENABLED, so initialize as early as possible. */ | |
5133 | crtl->is_leaf = leaf_function_p (); | |
5134 | ||
bcb21886 KY |
5135 | /* Perform target specific PIC register initialization. */ |
5136 | targetm.init_pic_reg (); | |
5137 | ||
55a2c322 VM |
5138 | ira_conflicts_p = optimize > 0; |
5139 | ||
55a2c322 VM |
5140 | /* If there are too many pseudos and/or basic blocks (e.g. 10K |
5141 | pseudos and 10K blocks or 100K pseudos and 1K blocks), we will | |
5142 | use simplified and faster algorithms in LRA. */ | |
5143 | lra_simple_p | |
8b1c6fd7 DM |
5144 | = (ira_use_lra_p |
5145 | && max_reg_num () >= (1 << 26) / last_basic_block_for_fn (cfun)); | |
55a2c322 VM |
5146 | if (lra_simple_p) |
5147 | { | |
5148 | /* It permits to skip live range splitting in LRA. */ | |
5149 | flag_caller_saves = false; | |
5150 | /* There is no sense to do regional allocation when we use | |
5151 | simplified LRA. */ | |
5152 | flag_ira_region = IRA_REGION_ONE; | |
5153 | ira_conflicts_p = false; | |
5154 | } | |
5155 | ||
5156 | #ifndef IRA_NO_OBSTACK | |
5157 | gcc_obstack_init (&ira_obstack); | |
5158 | #endif | |
5159 | bitmap_obstack_initialize (&ira_bitmap_obstack); | |
058e97ec | 5160 | |
001010df KC |
5161 | /* LRA uses its own infrastructure to handle caller save registers. */ |
5162 | if (flag_caller_saves && !ira_use_lra_p) | |
dc12b70e JZ |
5163 | init_caller_save (); |
5164 | ||
058e97ec VM |
5165 | if (flag_ira_verbose < 10) |
5166 | { | |
5167 | internal_flag_ira_verbose = flag_ira_verbose; | |
5168 | ira_dump_file = f; | |
5169 | } | |
5170 | else | |
5171 | { | |
5172 | internal_flag_ira_verbose = flag_ira_verbose - 10; | |
5173 | ira_dump_file = stderr; | |
5174 | } | |
5175 | ||
5176 | setup_prohibited_mode_move_regs (); | |
3b6d1699 | 5177 | decrease_live_ranges_number (); |
058e97ec | 5178 | df_note_add_problem (); |
5d517141 SB |
5179 | |
5180 | /* DF_LIVE can't be used in the register allocator, too many other | |
5181 | parts of the compiler depend on using the "classic" liveness | |
5182 | interpretation of the DF_LR problem. See PR38711. | |
5183 | Remove the problem, so that we don't spend time updating it in | |
5184 | any of the df_analyze() calls during IRA/LRA. */ | |
5185 | if (optimize > 1) | |
5186 | df_remove_problem (df_live); | |
5187 | gcc_checking_assert (df_live == NULL); | |
5188 | ||
b2b29377 MM |
5189 | if (flag_checking) |
5190 | df->changeable_flags |= DF_VERIFY_SCHEDULED; | |
5191 | ||
058e97ec | 5192 | df_analyze (); |
3b6d1699 | 5193 | |
2d73cc45 MJ |
5194 | init_reg_equiv (); |
5195 | if (ira_conflicts_p) | |
5196 | { | |
5197 | calculate_dominance_info (CDI_DOMINATORS); | |
5198 | ||
5199 | if (split_live_ranges_for_shrink_wrap ()) | |
5200 | df_analyze (); | |
5201 | ||
5202 | free_dominance_info (CDI_DOMINATORS); | |
5203 | } | |
5204 | ||
058e97ec | 5205 | df_clear_flags (DF_NO_INSN_RESCAN); |
2d73cc45 | 5206 | |
ba52669f AM |
5207 | indirect_jump_optimize (); |
5208 | if (delete_trivially_dead_insns (get_insns (), max_reg_num ())) | |
5209 | df_analyze (); | |
5210 | ||
058e97ec VM |
5211 | regstat_init_n_sets_and_refs (); |
5212 | regstat_compute_ri (); | |
5213 | ||
5214 | /* If we are not optimizing, then this is the only place before | |
5215 | register allocation where dataflow is done. And that is needed | |
5216 | to generate these warnings. */ | |
5217 | if (warn_clobbered) | |
5218 | generate_setjmp_warnings (); | |
5219 | ||
1833192f | 5220 | if (resize_reg_info () && flag_ira_loop_pressure) |
b11f0116 | 5221 | ira_set_pseudo_classes (true, ira_dump_file); |
1833192f | 5222 | |
42ae0d7f | 5223 | init_alias_analysis (); |
c38c11a1 | 5224 | loop_optimizer_init (AVOID_CFG_MODIFICATIONS); |
10e04446 | 5225 | reg_equiv = XCNEWVEC (struct equivalence, max_reg_num ()); |
ba52669f | 5226 | update_equiv_regs (); |
10e04446 AM |
5227 | |
5228 | /* Don't move insns if live range shrinkage or register | |
5229 | pressure-sensitive scheduling were done because it will not | |
5230 | improve allocation but likely worsen insn scheduling. */ | |
5231 | if (optimize | |
5232 | && !flag_live_range_shrinkage | |
5233 | && !(flag_sched_pressure && flag_schedule_insns)) | |
5234 | combine_and_move_insns (); | |
5235 | ||
5236 | /* Gather additional equivalences with memory. */ | |
42ae0d7f | 5237 | if (optimize) |
10e04446 AM |
5238 | add_store_equivs (); |
5239 | ||
c38c11a1 | 5240 | loop_optimizer_finalize (); |
f3c82ff9 | 5241 | free_dominance_info (CDI_DOMINATORS); |
42ae0d7f AM |
5242 | end_alias_analysis (); |
5243 | free (reg_equiv); | |
5244 | ||
55a2c322 | 5245 | setup_reg_equiv (); |
10e04446 | 5246 | grow_reg_equivs (); |
55a2c322 | 5247 | setup_reg_equiv_init (); |
058e97ec | 5248 | |
fb99ee9b | 5249 | allocated_reg_info_size = max_reg_num (); |
e8d7e3e7 VM |
5250 | |
5251 | /* It is not worth to do such improvement when we use a simple | |
5252 | allocation because of -O0 usage or because the function is too | |
5253 | big. */ | |
5254 | if (ira_conflicts_p) | |
2d73cc45 | 5255 | find_moveable_pseudos (); |
acf41a74 | 5256 | |
fb99ee9b | 5257 | max_regno_before_ira = max_reg_num (); |
8d49e7ef | 5258 | ira_setup_eliminable_regset (); |
b8698a0f | 5259 | |
058e97ec VM |
5260 | ira_overall_cost = ira_reg_cost = ira_mem_cost = 0; |
5261 | ira_load_cost = ira_store_cost = ira_shuffle_cost = 0; | |
5262 | ira_move_loops_num = ira_additional_jumps_num = 0; | |
b8698a0f | 5263 | |
058e97ec | 5264 | ira_assert (current_loops == NULL); |
2608d841 | 5265 | if (flag_ira_region == IRA_REGION_ALL || flag_ira_region == IRA_REGION_MIXED) |
661bc682 | 5266 | loop_optimizer_init (AVOID_CFG_MODIFICATIONS | LOOPS_HAVE_RECORDED_EXITS); |
b8698a0f | 5267 | |
058e97ec VM |
5268 | if (internal_flag_ira_verbose > 0 && ira_dump_file != NULL) |
5269 | fprintf (ira_dump_file, "Building IRA IR\n"); | |
2608d841 | 5270 | loops_p = ira_build (); |
b8698a0f | 5271 | |
311aab06 | 5272 | ira_assert (ira_conflicts_p || !loops_p); |
3553f0bb VM |
5273 | |
5274 | saved_flag_ira_share_spill_slots = flag_ira_share_spill_slots; | |
de8e52f0 | 5275 | if (too_high_register_pressure_p () || cfun->calls_setjmp) |
3553f0bb | 5276 | /* It is just wasting compiler's time to pack spilled pseudos into |
de8e52f0 VM |
5277 | stack slots in this case -- prohibit it. We also do this if |
5278 | there is setjmp call because a variable not modified between | |
5279 | setjmp and longjmp the compiler is required to preserve its | |
5280 | value and sharing slots does not guarantee it. */ | |
3553f0bb VM |
5281 | flag_ira_share_spill_slots = FALSE; |
5282 | ||
cb1ca6ac | 5283 | ira_color (); |
b8698a0f | 5284 | |
058e97ec | 5285 | ira_max_point_before_emit = ira_max_point; |
b8698a0f | 5286 | |
1756cb66 VM |
5287 | ira_initiate_emit_data (); |
5288 | ||
058e97ec | 5289 | ira_emit (loops_p); |
b8698a0f | 5290 | |
55a2c322 | 5291 | max_regno = max_reg_num (); |
311aab06 | 5292 | if (ira_conflicts_p) |
058e97ec | 5293 | { |
058e97ec | 5294 | if (! loops_p) |
55a2c322 VM |
5295 | { |
5296 | if (! ira_use_lra_p) | |
5297 | ira_initiate_assign (); | |
5298 | } | |
058e97ec VM |
5299 | else |
5300 | { | |
fb99ee9b | 5301 | expand_reg_info (); |
b8698a0f | 5302 | |
55a2c322 VM |
5303 | if (ira_use_lra_p) |
5304 | { | |
5305 | ira_allocno_t a; | |
5306 | ira_allocno_iterator ai; | |
5307 | ||
5308 | FOR_EACH_ALLOCNO (a, ai) | |
9d6e10c7 RL |
5309 | { |
5310 | int old_regno = ALLOCNO_REGNO (a); | |
5311 | int new_regno = REGNO (ALLOCNO_EMIT_DATA (a)->reg); | |
5312 | ||
5313 | ALLOCNO_REGNO (a) = new_regno; | |
5314 | ||
5315 | if (old_regno != new_regno) | |
5316 | setup_reg_classes (new_regno, reg_preferred_class (old_regno), | |
5317 | reg_alternate_class (old_regno), | |
5318 | reg_allocno_class (old_regno)); | |
5319 | } | |
55a2c322 VM |
5320 | } |
5321 | else | |
5322 | { | |
5323 | if (internal_flag_ira_verbose > 0 && ira_dump_file != NULL) | |
5324 | fprintf (ira_dump_file, "Flattening IR\n"); | |
5325 | ira_flattening (max_regno_before_ira, ira_max_point_before_emit); | |
5326 | } | |
058e97ec VM |
5327 | /* New insns were generated: add notes and recalculate live |
5328 | info. */ | |
5329 | df_analyze (); | |
b8698a0f | 5330 | |
544e7e78 SB |
5331 | /* ??? Rebuild the loop tree, but why? Does the loop tree |
5332 | change if new insns were generated? Can that be handled | |
5333 | by updating the loop tree incrementally? */ | |
661bc682 | 5334 | loop_optimizer_finalize (); |
57548aa2 | 5335 | free_dominance_info (CDI_DOMINATORS); |
661bc682 RB |
5336 | loop_optimizer_init (AVOID_CFG_MODIFICATIONS |
5337 | | LOOPS_HAVE_RECORDED_EXITS); | |
058e97ec | 5338 | |
55a2c322 VM |
5339 | if (! ira_use_lra_p) |
5340 | { | |
5341 | setup_allocno_assignment_flags (); | |
5342 | ira_initiate_assign (); | |
5343 | ira_reassign_conflict_allocnos (max_regno); | |
5344 | } | |
058e97ec VM |
5345 | } |
5346 | } | |
5347 | ||
1756cb66 VM |
5348 | ira_finish_emit_data (); |
5349 | ||
058e97ec | 5350 | setup_reg_renumber (); |
b8698a0f | 5351 | |
058e97ec | 5352 | calculate_allocation_cost (); |
b8698a0f | 5353 | |
058e97ec | 5354 | #ifdef ENABLE_IRA_CHECKING |
e5119fab VM |
5355 | if (ira_conflicts_p && ! ira_use_lra_p) |
5356 | /* Opposite to reload pass, LRA does not use any conflict info | |
5357 | from IRA. We don't rebuild conflict info for LRA (through | |
5358 | ira_flattening call) and can not use the check here. We could | |
5359 | rebuild this info for LRA in the check mode but there is a risk | |
5360 | that code generated with the check and without it will be a bit | |
5361 | different. Calling ira_flattening in any mode would be a | |
5362 | wasting CPU time. So do not check the allocation for LRA. */ | |
058e97ec VM |
5363 | check_allocation (); |
5364 | #endif | |
b8698a0f | 5365 | |
ba52669f | 5366 | if (max_regno != max_regno_before_ira) |
058e97ec VM |
5367 | { |
5368 | regstat_free_n_sets_and_refs (); | |
5369 | regstat_free_ri (); | |
5370 | regstat_init_n_sets_and_refs (); | |
5371 | regstat_compute_ri (); | |
5372 | } | |
5373 | ||
058e97ec | 5374 | overall_cost_before = ira_overall_cost; |
e5b0e1ca VM |
5375 | if (! ira_conflicts_p) |
5376 | grow_reg_equivs (); | |
5377 | else | |
058e97ec VM |
5378 | { |
5379 | fix_reg_equiv_init (); | |
b8698a0f | 5380 | |
058e97ec VM |
5381 | #ifdef ENABLE_IRA_CHECKING |
5382 | print_redundant_copies (); | |
5383 | #endif | |
9994ad20 KC |
5384 | if (! ira_use_lra_p) |
5385 | { | |
5386 | ira_spilled_reg_stack_slots_num = 0; | |
5387 | ira_spilled_reg_stack_slots | |
5388 | = ((struct ira_spilled_reg_stack_slot *) | |
5389 | ira_allocate (max_regno | |
5390 | * sizeof (struct ira_spilled_reg_stack_slot))); | |
5391 | memset (ira_spilled_reg_stack_slots, 0, | |
5392 | max_regno * sizeof (struct ira_spilled_reg_stack_slot)); | |
5393 | } | |
058e97ec | 5394 | } |
6399c0ab | 5395 | allocate_initial_values (); |
e8d7e3e7 VM |
5396 | |
5397 | /* See comment for find_moveable_pseudos call. */ | |
5398 | if (ira_conflicts_p) | |
5399 | move_unallocated_pseudos (); | |
55a2c322 VM |
5400 | |
5401 | /* Restore original values. */ | |
5402 | if (lra_simple_p) | |
5403 | { | |
5404 | flag_caller_saves = saved_flag_caller_saves; | |
5405 | flag_ira_region = saved_flag_ira_region; | |
5406 | } | |
d3afd9aa RB |
5407 | } |
5408 | ||
5409 | static void | |
5410 | do_reload (void) | |
5411 | { | |
5412 | basic_block bb; | |
5413 | bool need_dce; | |
bcb21886 | 5414 | unsigned pic_offset_table_regno = INVALID_REGNUM; |
ae2b9cb6 | 5415 | |
67463efb | 5416 | if (flag_ira_verbose < 10) |
ae2b9cb6 | 5417 | ira_dump_file = dump_file; |
058e97ec | 5418 | |
bcb21886 KY |
5419 | /* If pic_offset_table_rtx is a pseudo register, then keep it so |
5420 | after reload to avoid possible wrong usages of hard reg assigned | |
5421 | to it. */ | |
5422 | if (pic_offset_table_rtx | |
5423 | && REGNO (pic_offset_table_rtx) >= FIRST_PSEUDO_REGISTER) | |
5424 | pic_offset_table_regno = REGNO (pic_offset_table_rtx); | |
5425 | ||
55a2c322 VM |
5426 | timevar_push (TV_RELOAD); |
5427 | if (ira_use_lra_p) | |
5428 | { | |
5429 | if (current_loops != NULL) | |
5430 | { | |
661bc682 | 5431 | loop_optimizer_finalize (); |
55a2c322 VM |
5432 | free_dominance_info (CDI_DOMINATORS); |
5433 | } | |
04a90bec | 5434 | FOR_ALL_BB_FN (bb, cfun) |
55a2c322 VM |
5435 | bb->loop_father = NULL; |
5436 | current_loops = NULL; | |
55a2c322 VM |
5437 | |
5438 | ira_destroy (); | |
058e97ec | 5439 | |
55a2c322 VM |
5440 | lra (ira_dump_file); |
5441 | /* ???!!! Move it before lra () when we use ira_reg_equiv in | |
5442 | LRA. */ | |
9771b263 | 5443 | vec_free (reg_equivs); |
55a2c322 VM |
5444 | reg_equivs = NULL; |
5445 | need_dce = false; | |
5446 | } | |
5447 | else | |
5448 | { | |
5449 | df_set_flags (DF_NO_INSN_RESCAN); | |
5450 | build_insn_chain (); | |
55a2c322 | 5451 | |
355a43a1 | 5452 | need_dce = reload (get_insns (), ira_conflicts_p); |
55a2c322 VM |
5453 | } |
5454 | ||
5455 | timevar_pop (TV_RELOAD); | |
058e97ec | 5456 | |
d3afd9aa RB |
5457 | timevar_push (TV_IRA); |
5458 | ||
55a2c322 | 5459 | if (ira_conflicts_p && ! ira_use_lra_p) |
058e97ec VM |
5460 | { |
5461 | ira_free (ira_spilled_reg_stack_slots); | |
058e97ec | 5462 | ira_finish_assign (); |
b8698a0f | 5463 | } |
55a2c322 | 5464 | |
058e97ec VM |
5465 | if (internal_flag_ira_verbose > 0 && ira_dump_file != NULL |
5466 | && overall_cost_before != ira_overall_cost) | |
16998094 | 5467 | fprintf (ira_dump_file, "+++Overall after reload %" PRId64 "\n", |
2bf7560b | 5468 | ira_overall_cost); |
b8698a0f | 5469 | |
3553f0bb VM |
5470 | flag_ira_share_spill_slots = saved_flag_ira_share_spill_slots; |
5471 | ||
55a2c322 | 5472 | if (! ira_use_lra_p) |
2608d841 | 5473 | { |
55a2c322 VM |
5474 | ira_destroy (); |
5475 | if (current_loops != NULL) | |
5476 | { | |
661bc682 | 5477 | loop_optimizer_finalize (); |
55a2c322 VM |
5478 | free_dominance_info (CDI_DOMINATORS); |
5479 | } | |
04a90bec | 5480 | FOR_ALL_BB_FN (bb, cfun) |
55a2c322 VM |
5481 | bb->loop_father = NULL; |
5482 | current_loops = NULL; | |
5483 | ||
5484 | regstat_free_ri (); | |
5485 | regstat_free_n_sets_and_refs (); | |
2608d841 | 5486 | } |
b8698a0f | 5487 | |
058e97ec | 5488 | if (optimize) |
55a2c322 | 5489 | cleanup_cfg (CLEANUP_EXPENSIVE); |
b8698a0f | 5490 | |
55a2c322 | 5491 | finish_reg_equiv (); |
058e97ec VM |
5492 | |
5493 | bitmap_obstack_release (&ira_bitmap_obstack); | |
5494 | #ifndef IRA_NO_OBSTACK | |
5495 | obstack_free (&ira_obstack, NULL); | |
5496 | #endif | |
5497 | ||
5498 | /* The code after the reload has changed so much that at this point | |
b0c11403 | 5499 | we might as well just rescan everything. Note that |
058e97ec VM |
5500 | df_rescan_all_insns is not going to help here because it does not |
5501 | touch the artificial uses and defs. */ | |
5502 | df_finish_pass (true); | |
058e97ec VM |
5503 | df_scan_alloc (NULL); |
5504 | df_scan_blocks (); | |
5505 | ||
5d517141 SB |
5506 | if (optimize > 1) |
5507 | { | |
5508 | df_live_add_problem (); | |
5509 | df_live_set_all_dirty (); | |
5510 | } | |
5511 | ||
058e97ec VM |
5512 | if (optimize) |
5513 | df_analyze (); | |
5514 | ||
b0c11403 JL |
5515 | if (need_dce && optimize) |
5516 | run_fast_dce (); | |
d3afd9aa | 5517 | |
af6e8467 RH |
5518 | /* Diagnose uses of the hard frame pointer when it is used as a global |
5519 | register. Often we can get away with letting the user appropriate | |
5520 | the frame pointer, but we should let them know when code generation | |
5521 | makes that impossible. */ | |
5522 | if (global_regs[HARD_FRAME_POINTER_REGNUM] && frame_pointer_needed) | |
5523 | { | |
5524 | tree decl = global_regs_decl[HARD_FRAME_POINTER_REGNUM]; | |
5525 | error_at (DECL_SOURCE_LOCATION (current_function_decl), | |
5526 | "frame pointer required, but reserved"); | |
5527 | inform (DECL_SOURCE_LOCATION (decl), "for %qD", decl); | |
5528 | } | |
5529 | ||
355a43a1 EB |
5530 | /* If we are doing generic stack checking, give a warning if this |
5531 | function's frame size is larger than we expect. */ | |
5532 | if (flag_stack_check == GENERIC_STACK_CHECK) | |
5533 | { | |
5534 | HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE; | |
5535 | ||
5536 | for (int i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
5537 | if (df_regs_ever_live_p (i) && !fixed_regs[i] && call_used_regs[i]) | |
5538 | size += UNITS_PER_WORD; | |
5539 | ||
5540 | if (size > STACK_CHECK_MAX_FRAME_SIZE) | |
5541 | warning (0, "frame size too large for reliable stack checking"); | |
5542 | } | |
5543 | ||
bcb21886 KY |
5544 | if (pic_offset_table_regno != INVALID_REGNUM) |
5545 | pic_offset_table_rtx = gen_rtx_REG (Pmode, pic_offset_table_regno); | |
5546 | ||
d3afd9aa | 5547 | timevar_pop (TV_IRA); |
058e97ec | 5548 | } |
058e97ec | 5549 | \f |
058e97ec | 5550 | /* Run the integrated register allocator. */ |
058e97ec | 5551 | |
27a4cd48 DM |
5552 | namespace { |
5553 | ||
5554 | const pass_data pass_data_ira = | |
058e97ec | 5555 | { |
27a4cd48 DM |
5556 | RTL_PASS, /* type */ |
5557 | "ira", /* name */ | |
5558 | OPTGROUP_NONE, /* optinfo_flags */ | |
27a4cd48 DM |
5559 | TV_IRA, /* tv_id */ |
5560 | 0, /* properties_required */ | |
5561 | 0, /* properties_provided */ | |
5562 | 0, /* properties_destroyed */ | |
5563 | 0, /* todo_flags_start */ | |
5564 | TODO_do_not_ggc_collect, /* todo_flags_finish */ | |
d3afd9aa RB |
5565 | }; |
5566 | ||
27a4cd48 DM |
5567 | class pass_ira : public rtl_opt_pass |
5568 | { | |
5569 | public: | |
c3284718 RS |
5570 | pass_ira (gcc::context *ctxt) |
5571 | : rtl_opt_pass (pass_data_ira, ctxt) | |
27a4cd48 DM |
5572 | {} |
5573 | ||
5574 | /* opt_pass methods: */ | |
a50fa76a BS |
5575 | virtual bool gate (function *) |
5576 | { | |
5577 | return !targetm.no_register_allocation; | |
5578 | } | |
be55bfe6 TS |
5579 | virtual unsigned int execute (function *) |
5580 | { | |
5581 | ira (dump_file); | |
5582 | return 0; | |
5583 | } | |
27a4cd48 DM |
5584 | |
5585 | }; // class pass_ira | |
5586 | ||
5587 | } // anon namespace | |
5588 | ||
5589 | rtl_opt_pass * | |
5590 | make_pass_ira (gcc::context *ctxt) | |
5591 | { | |
5592 | return new pass_ira (ctxt); | |
5593 | } | |
5594 | ||
27a4cd48 DM |
5595 | namespace { |
5596 | ||
5597 | const pass_data pass_data_reload = | |
d3afd9aa | 5598 | { |
27a4cd48 DM |
5599 | RTL_PASS, /* type */ |
5600 | "reload", /* name */ | |
5601 | OPTGROUP_NONE, /* optinfo_flags */ | |
27a4cd48 DM |
5602 | TV_RELOAD, /* tv_id */ |
5603 | 0, /* properties_required */ | |
5604 | 0, /* properties_provided */ | |
5605 | 0, /* properties_destroyed */ | |
5606 | 0, /* todo_flags_start */ | |
5607 | 0, /* todo_flags_finish */ | |
058e97ec | 5608 | }; |
27a4cd48 DM |
5609 | |
5610 | class pass_reload : public rtl_opt_pass | |
5611 | { | |
5612 | public: | |
c3284718 RS |
5613 | pass_reload (gcc::context *ctxt) |
5614 | : rtl_opt_pass (pass_data_reload, ctxt) | |
27a4cd48 DM |
5615 | {} |
5616 | ||
5617 | /* opt_pass methods: */ | |
a50fa76a BS |
5618 | virtual bool gate (function *) |
5619 | { | |
5620 | return !targetm.no_register_allocation; | |
5621 | } | |
be55bfe6 TS |
5622 | virtual unsigned int execute (function *) |
5623 | { | |
5624 | do_reload (); | |
5625 | return 0; | |
5626 | } | |
27a4cd48 DM |
5627 | |
5628 | }; // class pass_reload | |
5629 | ||
5630 | } // anon namespace | |
5631 | ||
5632 | rtl_opt_pass * | |
5633 | make_pass_reload (gcc::context *ctxt) | |
5634 | { | |
5635 | return new pass_reload (ctxt); | |
5636 | } |