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058e97ec | 1 | /* Integrated Register Allocator (IRA) entry point. |
66647d44 | 2 | Copyright (C) 2006, 2007, 2008, 2009 |
058e97ec VM |
3 | Free Software Foundation, Inc. |
4 | Contributed by Vladimir Makarov <vmakarov@redhat.com>. | |
5 | ||
6 | This file is part of GCC. | |
7 | ||
8 | GCC is free software; you can redistribute it and/or modify it under | |
9 | the terms of the GNU General Public License as published by the Free | |
10 | Software Foundation; either version 3, or (at your option) any later | |
11 | version. | |
12 | ||
13 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
14 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GCC; see the file COPYING3. If not see | |
20 | <http://www.gnu.org/licenses/>. */ | |
21 | ||
22 | /* The integrated register allocator (IRA) is a | |
23 | regional register allocator performing graph coloring on a top-down | |
24 | traversal of nested regions. Graph coloring in a region is based | |
25 | on Chaitin-Briggs algorithm. It is called integrated because | |
26 | register coalescing, register live range splitting, and choosing a | |
27 | better hard register are done on-the-fly during coloring. Register | |
28 | coalescing and choosing a cheaper hard register is done by hard | |
29 | register preferencing during hard register assigning. The live | |
30 | range splitting is a byproduct of the regional register allocation. | |
31 | ||
32 | Major IRA notions are: | |
33 | ||
34 | o *Region* is a part of CFG where graph coloring based on | |
35 | Chaitin-Briggs algorithm is done. IRA can work on any set of | |
36 | nested CFG regions forming a tree. Currently the regions are | |
37 | the entire function for the root region and natural loops for | |
38 | the other regions. Therefore data structure representing a | |
39 | region is called loop_tree_node. | |
40 | ||
41 | o *Cover class* is a register class belonging to a set of | |
42 | non-intersecting register classes containing all of the | |
43 | hard-registers available for register allocation. The set of | |
44 | all cover classes for a target is defined in the corresponding | |
45 | machine-description file according some criteria. Such notion | |
46 | is needed because Chaitin-Briggs algorithm works on | |
47 | non-intersected register classes. | |
48 | ||
49 | o *Allocno* represents the live range of a pseudo-register in a | |
50 | region. Besides the obvious attributes like the corresponding | |
51 | pseudo-register number, cover class, conflicting allocnos and | |
52 | conflicting hard-registers, there are a few allocno attributes | |
53 | which are important for understanding the allocation algorithm: | |
54 | ||
55 | - *Live ranges*. This is a list of ranges of *program | |
56 | points* where the allocno lives. Program points represent | |
57 | places where a pseudo can be born or become dead (there are | |
58 | approximately two times more program points than the insns) | |
59 | and they are represented by integers starting with 0. The | |
60 | live ranges are used to find conflicts between allocnos of | |
61 | different cover classes. They also play very important role | |
62 | for the transformation of the IRA internal representation of | |
63 | several regions into a one region representation. The later is | |
64 | used during the reload pass work because each allocno | |
65 | represents all of the corresponding pseudo-registers. | |
66 | ||
67 | - *Hard-register costs*. This is a vector of size equal to the | |
68 | number of available hard-registers of the allocno's cover | |
69 | class. The cost of a callee-clobbered hard-register for an | |
70 | allocno is increased by the cost of save/restore code around | |
71 | the calls through the given allocno's life. If the allocno | |
72 | is a move instruction operand and another operand is a | |
73 | hard-register of the allocno's cover class, the cost of the | |
74 | hard-register is decreased by the move cost. | |
75 | ||
76 | When an allocno is assigned, the hard-register with minimal | |
77 | full cost is used. Initially, a hard-register's full cost is | |
78 | the corresponding value from the hard-register's cost vector. | |
79 | If the allocno is connected by a *copy* (see below) to | |
80 | another allocno which has just received a hard-register, the | |
81 | cost of the hard-register is decreased. Before choosing a | |
82 | hard-register for an allocno, the allocno's current costs of | |
83 | the hard-registers are modified by the conflict hard-register | |
84 | costs of all of the conflicting allocnos which are not | |
85 | assigned yet. | |
86 | ||
87 | - *Conflict hard-register costs*. This is a vector of the same | |
88 | size as the hard-register costs vector. To permit an | |
89 | unassigned allocno to get a better hard-register, IRA uses | |
90 | this vector to calculate the final full cost of the | |
91 | available hard-registers. Conflict hard-register costs of an | |
92 | unassigned allocno are also changed with a change of the | |
93 | hard-register cost of the allocno when a copy involving the | |
94 | allocno is processed as described above. This is done to | |
95 | show other unassigned allocnos that a given allocno prefers | |
96 | some hard-registers in order to remove the move instruction | |
97 | corresponding to the copy. | |
98 | ||
99 | o *Cap*. If a pseudo-register does not live in a region but | |
100 | lives in a nested region, IRA creates a special allocno called | |
101 | a cap in the outer region. A region cap is also created for a | |
102 | subregion cap. | |
103 | ||
104 | o *Copy*. Allocnos can be connected by copies. Copies are used | |
105 | to modify hard-register costs for allocnos during coloring. | |
106 | Such modifications reflects a preference to use the same | |
107 | hard-register for the allocnos connected by copies. Usually | |
108 | copies are created for move insns (in this case it results in | |
109 | register coalescing). But IRA also creates copies for operands | |
110 | of an insn which should be assigned to the same hard-register | |
111 | due to constraints in the machine description (it usually | |
112 | results in removing a move generated in reload to satisfy | |
113 | the constraints) and copies referring to the allocno which is | |
114 | the output operand of an instruction and the allocno which is | |
115 | an input operand dying in the instruction (creation of such | |
116 | copies results in less register shuffling). IRA *does not* | |
117 | create copies between the same register allocnos from different | |
118 | regions because we use another technique for propagating | |
119 | hard-register preference on the borders of regions. | |
120 | ||
121 | Allocnos (including caps) for the upper region in the region tree | |
122 | *accumulate* information important for coloring from allocnos with | |
123 | the same pseudo-register from nested regions. This includes | |
124 | hard-register and memory costs, conflicts with hard-registers, | |
125 | allocno conflicts, allocno copies and more. *Thus, attributes for | |
126 | allocnos in a region have the same values as if the region had no | |
127 | subregions*. It means that attributes for allocnos in the | |
128 | outermost region corresponding to the function have the same values | |
129 | as though the allocation used only one region which is the entire | |
130 | function. It also means that we can look at IRA work as if the | |
131 | first IRA did allocation for all function then it improved the | |
132 | allocation for loops then their subloops and so on. | |
133 | ||
134 | IRA major passes are: | |
135 | ||
136 | o Building IRA internal representation which consists of the | |
137 | following subpasses: | |
138 | ||
139 | * First, IRA builds regions and creates allocnos (file | |
140 | ira-build.c) and initializes most of their attributes. | |
141 | ||
142 | * Then IRA finds a cover class for each allocno and calculates | |
143 | its initial (non-accumulated) cost of memory and each | |
144 | hard-register of its cover class (file ira-cost.c). | |
145 | ||
146 | * IRA creates live ranges of each allocno, calulates register | |
147 | pressure for each cover class in each region, sets up | |
148 | conflict hard registers for each allocno and info about calls | |
149 | the allocno lives through (file ira-lives.c). | |
150 | ||
151 | * IRA removes low register pressure loops from the regions | |
152 | mostly to speed IRA up (file ira-build.c). | |
153 | ||
154 | * IRA propagates accumulated allocno info from lower region | |
155 | allocnos to corresponding upper region allocnos (file | |
156 | ira-build.c). | |
157 | ||
158 | * IRA creates all caps (file ira-build.c). | |
159 | ||
160 | * Having live-ranges of allocnos and their cover classes, IRA | |
161 | creates conflicting allocnos of the same cover class for each | |
162 | allocno. Conflicting allocnos are stored as a bit vector or | |
163 | array of pointers to the conflicting allocnos whatever is | |
164 | more profitable (file ira-conflicts.c). At this point IRA | |
165 | creates allocno copies. | |
166 | ||
167 | o Coloring. Now IRA has all necessary info to start graph coloring | |
168 | process. It is done in each region on top-down traverse of the | |
169 | region tree (file ira-color.c). There are following subpasses: | |
170 | ||
171 | * Optional aggressive coalescing of allocnos in the region. | |
172 | ||
173 | * Putting allocnos onto the coloring stack. IRA uses Briggs | |
174 | optimistic coloring which is a major improvement over | |
175 | Chaitin's coloring. Therefore IRA does not spill allocnos at | |
176 | this point. There is some freedom in the order of putting | |
177 | allocnos on the stack which can affect the final result of | |
178 | the allocation. IRA uses some heuristics to improve the order. | |
179 | ||
180 | * Popping the allocnos from the stack and assigning them hard | |
181 | registers. If IRA can not assign a hard register to an | |
182 | allocno and the allocno is coalesced, IRA undoes the | |
183 | coalescing and puts the uncoalesced allocnos onto the stack in | |
184 | the hope that some such allocnos will get a hard register | |
185 | separately. If IRA fails to assign hard register or memory | |
186 | is more profitable for it, IRA spills the allocno. IRA | |
187 | assigns the allocno the hard-register with minimal full | |
188 | allocation cost which reflects the cost of usage of the | |
189 | hard-register for the allocno and cost of usage of the | |
190 | hard-register for allocnos conflicting with given allocno. | |
191 | ||
192 | * After allono assigning in the region, IRA modifies the hard | |
193 | register and memory costs for the corresponding allocnos in | |
194 | the subregions to reflect the cost of possible loads, stores, | |
195 | or moves on the border of the region and its subregions. | |
196 | When default regional allocation algorithm is used | |
197 | (-fira-algorithm=mixed), IRA just propagates the assignment | |
198 | for allocnos if the register pressure in the region for the | |
199 | corresponding cover class is less than number of available | |
200 | hard registers for given cover class. | |
201 | ||
202 | o Spill/restore code moving. When IRA performs an allocation | |
203 | by traversing regions in top-down order, it does not know what | |
204 | happens below in the region tree. Therefore, sometimes IRA | |
205 | misses opportunities to perform a better allocation. A simple | |
206 | optimization tries to improve allocation in a region having | |
207 | subregions and containing in another region. If the | |
208 | corresponding allocnos in the subregion are spilled, it spills | |
209 | the region allocno if it is profitable. The optimization | |
210 | implements a simple iterative algorithm performing profitable | |
211 | transformations while they are still possible. It is fast in | |
212 | practice, so there is no real need for a better time complexity | |
213 | algorithm. | |
214 | ||
215 | o Code change. After coloring, two allocnos representing the same | |
216 | pseudo-register outside and inside a region respectively may be | |
217 | assigned to different locations (hard-registers or memory). In | |
218 | this case IRA creates and uses a new pseudo-register inside the | |
219 | region and adds code to move allocno values on the region's | |
220 | borders. This is done during top-down traversal of the regions | |
221 | (file ira-emit.c). In some complicated cases IRA can create a | |
222 | new allocno to move allocno values (e.g. when a swap of values | |
223 | stored in two hard-registers is needed). At this stage, the | |
224 | new allocno is marked as spilled. IRA still creates the | |
225 | pseudo-register and the moves on the region borders even when | |
226 | both allocnos were assigned to the same hard-register. If the | |
227 | reload pass spills a pseudo-register for some reason, the | |
228 | effect will be smaller because another allocno will still be in | |
229 | the hard-register. In most cases, this is better then spilling | |
230 | both allocnos. If reload does not change the allocation | |
231 | for the two pseudo-registers, the trivial move will be removed | |
232 | by post-reload optimizations. IRA does not generate moves for | |
233 | allocnos assigned to the same hard register when the default | |
234 | regional allocation algorithm is used and the register pressure | |
235 | in the region for the corresponding allocno cover class is less | |
236 | than number of available hard registers for given cover class. | |
237 | IRA also does some optimizations to remove redundant stores and | |
238 | to reduce code duplication on the region borders. | |
239 | ||
240 | o Flattening internal representation. After changing code, IRA | |
241 | transforms its internal representation for several regions into | |
242 | one region representation (file ira-build.c). This process is | |
243 | called IR flattening. Such process is more complicated than IR | |
244 | rebuilding would be, but is much faster. | |
245 | ||
246 | o After IR flattening, IRA tries to assign hard registers to all | |
247 | spilled allocnos. This is impelemented by a simple and fast | |
248 | priority coloring algorithm (see function | |
249 | ira_reassign_conflict_allocnos::ira-color.c). Here new allocnos | |
250 | created during the code change pass can be assigned to hard | |
251 | registers. | |
252 | ||
253 | o At the end IRA calls the reload pass. The reload pass | |
254 | communicates with IRA through several functions in file | |
255 | ira-color.c to improve its decisions in | |
256 | ||
257 | * sharing stack slots for the spilled pseudos based on IRA info | |
258 | about pseudo-register conflicts. | |
259 | ||
260 | * reassigning hard-registers to all spilled pseudos at the end | |
261 | of each reload iteration. | |
262 | ||
263 | * choosing a better hard-register to spill based on IRA info | |
264 | about pseudo-register live ranges and the register pressure | |
265 | in places where the pseudo-register lives. | |
266 | ||
267 | IRA uses a lot of data representing the target processors. These | |
268 | data are initilized in file ira.c. | |
269 | ||
270 | If function has no loops (or the loops are ignored when | |
271 | -fira-algorithm=CB is used), we have classic Chaitin-Briggs | |
272 | coloring (only instead of separate pass of coalescing, we use hard | |
273 | register preferencing). In such case, IRA works much faster | |
274 | because many things are not made (like IR flattening, the | |
275 | spill/restore optimization, and the code change). | |
276 | ||
277 | Literature is worth to read for better understanding the code: | |
278 | ||
279 | o Preston Briggs, Keith D. Cooper, Linda Torczon. Improvements to | |
280 | Graph Coloring Register Allocation. | |
281 | ||
282 | o David Callahan, Brian Koblenz. Register allocation via | |
283 | hierarchical graph coloring. | |
284 | ||
285 | o Keith Cooper, Anshuman Dasgupta, Jason Eckhardt. Revisiting Graph | |
286 | Coloring Register Allocation: A Study of the Chaitin-Briggs and | |
287 | Callahan-Koblenz Algorithms. | |
288 | ||
289 | o Guei-Yuan Lueh, Thomas Gross, and Ali-Reza Adl-Tabatabai. Global | |
290 | Register Allocation Based on Graph Fusion. | |
291 | ||
292 | o Vladimir Makarov. The Integrated Register Allocator for GCC. | |
293 | ||
294 | o Vladimir Makarov. The top-down register allocator for irregular | |
295 | register file architectures. | |
296 | ||
297 | */ | |
298 | ||
299 | ||
300 | #include "config.h" | |
301 | #include "system.h" | |
302 | #include "coretypes.h" | |
303 | #include "tm.h" | |
304 | #include "regs.h" | |
305 | #include "rtl.h" | |
306 | #include "tm_p.h" | |
307 | #include "target.h" | |
308 | #include "flags.h" | |
309 | #include "obstack.h" | |
310 | #include "bitmap.h" | |
311 | #include "hard-reg-set.h" | |
312 | #include "basic-block.h" | |
313 | #include "expr.h" | |
314 | #include "recog.h" | |
315 | #include "params.h" | |
316 | #include "timevar.h" | |
317 | #include "tree-pass.h" | |
318 | #include "output.h" | |
2af2dbdc | 319 | #include "except.h" |
058e97ec VM |
320 | #include "reload.h" |
321 | #include "errors.h" | |
322 | #include "integrate.h" | |
323 | #include "df.h" | |
324 | #include "ggc.h" | |
325 | #include "ira-int.h" | |
326 | ||
327 | ||
328 | /* A modified value of flag `-fira-verbose' used internally. */ | |
329 | int internal_flag_ira_verbose; | |
330 | ||
331 | /* Dump file of the allocator if it is not NULL. */ | |
332 | FILE *ira_dump_file; | |
333 | ||
334 | /* Pools for allocnos, copies, allocno live ranges. */ | |
335 | alloc_pool allocno_pool, copy_pool, allocno_live_range_pool; | |
336 | ||
337 | /* The number of elements in the following array. */ | |
338 | int ira_spilled_reg_stack_slots_num; | |
339 | ||
340 | /* The following array contains info about spilled pseudo-registers | |
341 | stack slots used in current function so far. */ | |
342 | struct ira_spilled_reg_stack_slot *ira_spilled_reg_stack_slots; | |
343 | ||
344 | /* Correspondingly overall cost of the allocation, cost of the | |
345 | allocnos assigned to hard-registers, cost of the allocnos assigned | |
346 | to memory, cost of loads, stores and register move insns generated | |
347 | for pseudo-register live range splitting (see ira-emit.c). */ | |
348 | int ira_overall_cost; | |
349 | int ira_reg_cost, ira_mem_cost; | |
350 | int ira_load_cost, ira_store_cost, ira_shuffle_cost; | |
351 | int ira_move_loops_num, ira_additional_jumps_num; | |
352 | ||
2af2dbdc VM |
353 | /* All registers that can be eliminated. */ |
354 | ||
355 | HARD_REG_SET eliminable_regset; | |
356 | ||
058e97ec VM |
357 | /* Map: hard regs X modes -> set of hard registers for storing value |
358 | of given mode starting with given hard register. */ | |
359 | HARD_REG_SET ira_reg_mode_hard_regset[FIRST_PSEUDO_REGISTER][NUM_MACHINE_MODES]; | |
360 | ||
361 | /* The following two variables are array analogs of the macros | |
362 | MEMORY_MOVE_COST and REGISTER_MOVE_COST. */ | |
363 | short int ira_memory_move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][2]; | |
364 | move_table *ira_register_move_cost[MAX_MACHINE_MODE]; | |
365 | ||
366 | /* Similar to may_move_in_cost but it is calculated in IRA instead of | |
367 | regclass. Another difference is that we take only available hard | |
368 | registers into account to figure out that one register class is a | |
369 | subset of the another one. */ | |
370 | move_table *ira_may_move_in_cost[MAX_MACHINE_MODE]; | |
371 | ||
372 | /* Similar to may_move_out_cost but it is calculated in IRA instead of | |
373 | regclass. Another difference is that we take only available hard | |
374 | registers into account to figure out that one register class is a | |
375 | subset of the another one. */ | |
376 | move_table *ira_may_move_out_cost[MAX_MACHINE_MODE]; | |
377 | ||
378 | /* Register class subset relation: TRUE if the first class is a subset | |
379 | of the second one considering only hard registers available for the | |
380 | allocation. */ | |
381 | int ira_class_subset_p[N_REG_CLASSES][N_REG_CLASSES]; | |
382 | ||
383 | /* Temporary hard reg set used for a different calculation. */ | |
384 | static HARD_REG_SET temp_hard_regset; | |
385 | ||
386 | \f | |
387 | ||
388 | /* The function sets up the map IRA_REG_MODE_HARD_REGSET. */ | |
389 | static void | |
390 | setup_reg_mode_hard_regset (void) | |
391 | { | |
392 | int i, m, hard_regno; | |
393 | ||
394 | for (m = 0; m < NUM_MACHINE_MODES; m++) | |
395 | for (hard_regno = 0; hard_regno < FIRST_PSEUDO_REGISTER; hard_regno++) | |
396 | { | |
397 | CLEAR_HARD_REG_SET (ira_reg_mode_hard_regset[hard_regno][m]); | |
398 | for (i = hard_regno_nregs[hard_regno][m] - 1; i >= 0; i--) | |
399 | if (hard_regno + i < FIRST_PSEUDO_REGISTER) | |
400 | SET_HARD_REG_BIT (ira_reg_mode_hard_regset[hard_regno][m], | |
401 | hard_regno + i); | |
402 | } | |
403 | } | |
404 | ||
405 | \f | |
406 | ||
407 | /* Hard registers that can not be used for the register allocator for | |
408 | all functions of the current compilation unit. */ | |
409 | static HARD_REG_SET no_unit_alloc_regs; | |
410 | ||
411 | /* Array of the number of hard registers of given class which are | |
412 | available for allocation. The order is defined by the | |
413 | allocation order. */ | |
414 | short ira_class_hard_regs[N_REG_CLASSES][FIRST_PSEUDO_REGISTER]; | |
415 | ||
416 | /* The number of elements of the above array for given register | |
417 | class. */ | |
418 | int ira_class_hard_regs_num[N_REG_CLASSES]; | |
419 | ||
420 | /* Index (in ira_class_hard_regs) for given register class and hard | |
421 | register (in general case a hard register can belong to several | |
422 | register classes). The index is negative for hard registers | |
423 | unavailable for the allocation. */ | |
424 | short ira_class_hard_reg_index[N_REG_CLASSES][FIRST_PSEUDO_REGISTER]; | |
425 | ||
426 | /* The function sets up the three arrays declared above. */ | |
427 | static void | |
428 | setup_class_hard_regs (void) | |
429 | { | |
430 | int cl, i, hard_regno, n; | |
431 | HARD_REG_SET processed_hard_reg_set; | |
432 | ||
433 | ira_assert (SHRT_MAX >= FIRST_PSEUDO_REGISTER); | |
434 | /* We could call ORDER_REGS_FOR_LOCAL_ALLOC here (it is usually | |
435 | putting hard callee-used hard registers first). But our | |
436 | heuristics work better. */ | |
437 | for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) | |
438 | { | |
439 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); | |
440 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
441 | CLEAR_HARD_REG_SET (processed_hard_reg_set); | |
7db7ed3c VM |
442 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
443 | ira_class_hard_reg_index[cl][0] = -1; | |
058e97ec VM |
444 | for (n = 0, i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
445 | { | |
446 | #ifdef REG_ALLOC_ORDER | |
447 | hard_regno = reg_alloc_order[i]; | |
448 | #else | |
449 | hard_regno = i; | |
450 | #endif | |
451 | if (TEST_HARD_REG_BIT (processed_hard_reg_set, hard_regno)) | |
452 | continue; | |
453 | SET_HARD_REG_BIT (processed_hard_reg_set, hard_regno); | |
454 | if (! TEST_HARD_REG_BIT (temp_hard_regset, hard_regno)) | |
455 | ira_class_hard_reg_index[cl][hard_regno] = -1; | |
456 | else | |
457 | { | |
458 | ira_class_hard_reg_index[cl][hard_regno] = n; | |
459 | ira_class_hard_regs[cl][n++] = hard_regno; | |
460 | } | |
461 | } | |
462 | ira_class_hard_regs_num[cl] = n; | |
463 | } | |
464 | } | |
465 | ||
466 | /* Number of given class hard registers available for the register | |
467 | allocation for given classes. */ | |
468 | int ira_available_class_regs[N_REG_CLASSES]; | |
469 | ||
470 | /* Set up IRA_AVAILABLE_CLASS_REGS. */ | |
471 | static void | |
472 | setup_available_class_regs (void) | |
473 | { | |
474 | int i, j; | |
475 | ||
476 | memset (ira_available_class_regs, 0, sizeof (ira_available_class_regs)); | |
477 | for (i = 0; i < N_REG_CLASSES; i++) | |
478 | { | |
479 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[i]); | |
480 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
481 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
482 | if (TEST_HARD_REG_BIT (temp_hard_regset, j)) | |
483 | ira_available_class_regs[i]++; | |
484 | } | |
485 | } | |
486 | ||
487 | /* Set up global variables defining info about hard registers for the | |
488 | allocation. These depend on USE_HARD_FRAME_P whose TRUE value means | |
489 | that we can use the hard frame pointer for the allocation. */ | |
490 | static void | |
491 | setup_alloc_regs (bool use_hard_frame_p) | |
492 | { | |
493 | COPY_HARD_REG_SET (no_unit_alloc_regs, fixed_reg_set); | |
494 | if (! use_hard_frame_p) | |
495 | SET_HARD_REG_BIT (no_unit_alloc_regs, HARD_FRAME_POINTER_REGNUM); | |
496 | setup_class_hard_regs (); | |
497 | setup_available_class_regs (); | |
498 | } | |
499 | ||
500 | \f | |
501 | ||
502 | /* Set up IRA_MEMORY_MOVE_COST, IRA_REGISTER_MOVE_COST. */ | |
503 | static void | |
504 | setup_class_subset_and_memory_move_costs (void) | |
505 | { | |
32e8bb8e | 506 | int cl, cl2, mode; |
058e97ec VM |
507 | HARD_REG_SET temp_hard_regset2; |
508 | ||
509 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
510 | ira_memory_move_cost[mode][NO_REGS][0] | |
511 | = ira_memory_move_cost[mode][NO_REGS][1] = SHRT_MAX; | |
512 | for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) | |
513 | { | |
514 | if (cl != (int) NO_REGS) | |
515 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
516 | { | |
bbbbb16a | 517 | ira_memory_move_cost[mode][cl][0] = |
32e8bb8e ILT |
518 | MEMORY_MOVE_COST ((enum machine_mode) mode, |
519 | (enum reg_class) cl, 0); | |
bbbbb16a | 520 | ira_memory_move_cost[mode][cl][1] = |
32e8bb8e ILT |
521 | MEMORY_MOVE_COST ((enum machine_mode) mode, |
522 | (enum reg_class) cl, 1); | |
058e97ec VM |
523 | /* Costs for NO_REGS are used in cost calculation on the |
524 | 1st pass when the preferred register classes are not | |
525 | known yet. In this case we take the best scenario. */ | |
526 | if (ira_memory_move_cost[mode][NO_REGS][0] | |
527 | > ira_memory_move_cost[mode][cl][0]) | |
528 | ira_memory_move_cost[mode][NO_REGS][0] | |
529 | = ira_memory_move_cost[mode][cl][0]; | |
530 | if (ira_memory_move_cost[mode][NO_REGS][1] | |
531 | > ira_memory_move_cost[mode][cl][1]) | |
532 | ira_memory_move_cost[mode][NO_REGS][1] | |
533 | = ira_memory_move_cost[mode][cl][1]; | |
534 | } | |
535 | for (cl2 = (int) N_REG_CLASSES - 1; cl2 >= 0; cl2--) | |
536 | { | |
537 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); | |
538 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
539 | COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl2]); | |
540 | AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs); | |
541 | ira_class_subset_p[cl][cl2] | |
542 | = hard_reg_set_subset_p (temp_hard_regset, temp_hard_regset2); | |
543 | } | |
544 | } | |
545 | } | |
546 | ||
547 | \f | |
548 | ||
549 | /* Define the following macro if allocation through malloc if | |
550 | preferable. */ | |
551 | #define IRA_NO_OBSTACK | |
552 | ||
553 | #ifndef IRA_NO_OBSTACK | |
554 | /* Obstack used for storing all dynamic data (except bitmaps) of the | |
555 | IRA. */ | |
556 | static struct obstack ira_obstack; | |
557 | #endif | |
558 | ||
559 | /* Obstack used for storing all bitmaps of the IRA. */ | |
560 | static struct bitmap_obstack ira_bitmap_obstack; | |
561 | ||
562 | /* Allocate memory of size LEN for IRA data. */ | |
563 | void * | |
564 | ira_allocate (size_t len) | |
565 | { | |
566 | void *res; | |
567 | ||
568 | #ifndef IRA_NO_OBSTACK | |
569 | res = obstack_alloc (&ira_obstack, len); | |
570 | #else | |
571 | res = xmalloc (len); | |
572 | #endif | |
573 | return res; | |
574 | } | |
575 | ||
576 | /* Reallocate memory PTR of size LEN for IRA data. */ | |
577 | void * | |
578 | ira_reallocate (void *ptr, size_t len) | |
579 | { | |
580 | void *res; | |
581 | ||
582 | #ifndef IRA_NO_OBSTACK | |
583 | res = obstack_alloc (&ira_obstack, len); | |
584 | #else | |
585 | res = xrealloc (ptr, len); | |
586 | #endif | |
587 | return res; | |
588 | } | |
589 | ||
590 | /* Free memory ADDR allocated for IRA data. */ | |
591 | void | |
592 | ira_free (void *addr ATTRIBUTE_UNUSED) | |
593 | { | |
594 | #ifndef IRA_NO_OBSTACK | |
595 | /* do nothing */ | |
596 | #else | |
597 | free (addr); | |
598 | #endif | |
599 | } | |
600 | ||
601 | ||
602 | /* Allocate and returns bitmap for IRA. */ | |
603 | bitmap | |
604 | ira_allocate_bitmap (void) | |
605 | { | |
606 | return BITMAP_ALLOC (&ira_bitmap_obstack); | |
607 | } | |
608 | ||
609 | /* Free bitmap B allocated for IRA. */ | |
610 | void | |
611 | ira_free_bitmap (bitmap b ATTRIBUTE_UNUSED) | |
612 | { | |
613 | /* do nothing */ | |
614 | } | |
615 | ||
616 | \f | |
617 | ||
618 | /* Output information about allocation of all allocnos (except for | |
619 | caps) into file F. */ | |
620 | void | |
621 | ira_print_disposition (FILE *f) | |
622 | { | |
623 | int i, n, max_regno; | |
624 | ira_allocno_t a; | |
625 | basic_block bb; | |
626 | ||
627 | fprintf (f, "Disposition:"); | |
628 | max_regno = max_reg_num (); | |
629 | for (n = 0, i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
630 | for (a = ira_regno_allocno_map[i]; | |
631 | a != NULL; | |
632 | a = ALLOCNO_NEXT_REGNO_ALLOCNO (a)) | |
633 | { | |
634 | if (n % 4 == 0) | |
635 | fprintf (f, "\n"); | |
636 | n++; | |
637 | fprintf (f, " %4d:r%-4d", ALLOCNO_NUM (a), ALLOCNO_REGNO (a)); | |
638 | if ((bb = ALLOCNO_LOOP_TREE_NODE (a)->bb) != NULL) | |
639 | fprintf (f, "b%-3d", bb->index); | |
640 | else | |
641 | fprintf (f, "l%-3d", ALLOCNO_LOOP_TREE_NODE (a)->loop->num); | |
642 | if (ALLOCNO_HARD_REGNO (a) >= 0) | |
643 | fprintf (f, " %3d", ALLOCNO_HARD_REGNO (a)); | |
644 | else | |
645 | fprintf (f, " mem"); | |
646 | } | |
647 | fprintf (f, "\n"); | |
648 | } | |
649 | ||
650 | /* Outputs information about allocation of all allocnos into | |
651 | stderr. */ | |
652 | void | |
653 | ira_debug_disposition (void) | |
654 | { | |
655 | ira_print_disposition (stderr); | |
656 | } | |
657 | ||
658 | \f | |
659 | ||
660 | /* For each reg class, table listing all the classes contained in it | |
661 | (excluding the class itself. Non-allocatable registers are | |
662 | excluded from the consideration). */ | |
663 | static enum reg_class alloc_reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES]; | |
664 | ||
665 | /* Initialize the table of subclasses of each reg class. */ | |
666 | static void | |
667 | setup_reg_subclasses (void) | |
668 | { | |
669 | int i, j; | |
670 | HARD_REG_SET temp_hard_regset2; | |
671 | ||
672 | for (i = 0; i < N_REG_CLASSES; i++) | |
673 | for (j = 0; j < N_REG_CLASSES; j++) | |
674 | alloc_reg_class_subclasses[i][j] = LIM_REG_CLASSES; | |
675 | ||
676 | for (i = 0; i < N_REG_CLASSES; i++) | |
677 | { | |
678 | if (i == (int) NO_REGS) | |
679 | continue; | |
680 | ||
681 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[i]); | |
682 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
4f341ea0 | 683 | if (hard_reg_set_empty_p (temp_hard_regset)) |
058e97ec VM |
684 | continue; |
685 | for (j = 0; j < N_REG_CLASSES; j++) | |
686 | if (i != j) | |
687 | { | |
688 | enum reg_class *p; | |
689 | ||
690 | COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[j]); | |
691 | AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs); | |
692 | if (! hard_reg_set_subset_p (temp_hard_regset, | |
693 | temp_hard_regset2)) | |
694 | continue; | |
695 | p = &alloc_reg_class_subclasses[j][0]; | |
696 | while (*p != LIM_REG_CLASSES) p++; | |
697 | *p = (enum reg_class) i; | |
698 | } | |
699 | } | |
700 | } | |
701 | ||
702 | \f | |
703 | ||
704 | /* Number of cover classes. Cover classes is non-intersected register | |
705 | classes containing all hard-registers available for the | |
706 | allocation. */ | |
707 | int ira_reg_class_cover_size; | |
708 | ||
709 | /* The array containing cover classes (see also comments for macro | |
710 | IRA_COVER_CLASSES). Only first IRA_REG_CLASS_COVER_SIZE elements are | |
711 | used for this. */ | |
712 | enum reg_class ira_reg_class_cover[N_REG_CLASSES]; | |
713 | ||
714 | /* The number of elements in the subsequent array. */ | |
715 | int ira_important_classes_num; | |
716 | ||
717 | /* The array containing non-empty classes (including non-empty cover | |
718 | classes) which are subclasses of cover classes. Such classes is | |
719 | important for calculation of the hard register usage costs. */ | |
720 | enum reg_class ira_important_classes[N_REG_CLASSES]; | |
721 | ||
722 | /* The array containing indexes of important classes in the previous | |
723 | array. The array elements are defined only for important | |
724 | classes. */ | |
725 | int ira_important_class_nums[N_REG_CLASSES]; | |
726 | ||
7db7ed3c | 727 | /* Set the four global variables defined above. */ |
058e97ec VM |
728 | static void |
729 | setup_cover_and_important_classes (void) | |
730 | { | |
32e8bb8e | 731 | int i, j, n, cl; |
db1a8d98 | 732 | bool set_p; |
7db7ed3c | 733 | const enum reg_class *cover_classes; |
058e97ec | 734 | HARD_REG_SET temp_hard_regset2; |
7db7ed3c VM |
735 | static enum reg_class classes[LIM_REG_CLASSES + 1]; |
736 | ||
737 | if (targetm.ira_cover_classes == NULL) | |
738 | cover_classes = NULL; | |
739 | else | |
740 | cover_classes = targetm.ira_cover_classes (); | |
741 | if (cover_classes == NULL) | |
742 | ira_assert (flag_ira_algorithm == IRA_ALGORITHM_PRIORITY); | |
743 | else | |
744 | { | |
745 | for (i = 0; (cl = cover_classes[i]) != LIM_REG_CLASSES; i++) | |
32e8bb8e | 746 | classes[i] = (enum reg_class) cl; |
7db7ed3c VM |
747 | classes[i] = LIM_REG_CLASSES; |
748 | } | |
749 | ||
750 | if (flag_ira_algorithm == IRA_ALGORITHM_PRIORITY) | |
751 | { | |
752 | n = 0; | |
753 | for (i = 0; i <= LIM_REG_CLASSES; i++) | |
754 | { | |
755 | if (i == NO_REGS) | |
756 | continue; | |
ff3cb468 | 757 | #ifdef CONSTRAINT_NUM_DEFINED_P |
7db7ed3c | 758 | for (j = 0; j < CONSTRAINT__LIMIT; j++) |
b65d6744 | 759 | if ((int) REG_CLASS_FOR_CONSTRAINT ((enum constraint_num) j) == i) |
7db7ed3c VM |
760 | break; |
761 | if (j < CONSTRAINT__LIMIT) | |
762 | { | |
569c72fc | 763 | classes[n++] = (enum reg_class) i; |
7db7ed3c VM |
764 | continue; |
765 | } | |
766 | #endif | |
767 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[i]); | |
768 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
769 | for (j = 0; j < LIM_REG_CLASSES; j++) | |
770 | { | |
771 | if (i == j) | |
772 | continue; | |
773 | COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[j]); | |
774 | AND_COMPL_HARD_REG_SET (temp_hard_regset2, | |
775 | no_unit_alloc_regs); | |
776 | if (hard_reg_set_equal_p (temp_hard_regset, | |
777 | temp_hard_regset2)) | |
778 | break; | |
779 | } | |
780 | if (j >= i) | |
32e8bb8e | 781 | classes[n++] = (enum reg_class) i; |
7db7ed3c VM |
782 | } |
783 | classes[n] = LIM_REG_CLASSES; | |
784 | } | |
058e97ec VM |
785 | |
786 | ira_reg_class_cover_size = 0; | |
787 | for (i = 0; (cl = classes[i]) != LIM_REG_CLASSES; i++) | |
788 | { | |
789 | for (j = 0; j < i; j++) | |
7db7ed3c | 790 | if (flag_ira_algorithm != IRA_ALGORITHM_PRIORITY |
32e8bb8e | 791 | && reg_classes_intersect_p ((enum reg_class) cl, classes[j])) |
058e97ec VM |
792 | gcc_unreachable (); |
793 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); | |
794 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
4f341ea0 | 795 | if (! hard_reg_set_empty_p (temp_hard_regset)) |
32e8bb8e | 796 | ira_reg_class_cover[ira_reg_class_cover_size++] = (enum reg_class) cl; |
058e97ec VM |
797 | } |
798 | ira_important_classes_num = 0; | |
799 | for (cl = 0; cl < N_REG_CLASSES; cl++) | |
800 | { | |
801 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); | |
802 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
4f341ea0 | 803 | if (! hard_reg_set_empty_p (temp_hard_regset)) |
7db7ed3c | 804 | { |
db1a8d98 | 805 | set_p = false; |
7db7ed3c VM |
806 | for (j = 0; j < ira_reg_class_cover_size; j++) |
807 | { | |
808 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); | |
809 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
810 | COPY_HARD_REG_SET (temp_hard_regset2, | |
811 | reg_class_contents[ira_reg_class_cover[j]]); | |
812 | AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs); | |
db1a8d98 VM |
813 | if ((enum reg_class) cl == ira_reg_class_cover[j] |
814 | || hard_reg_set_equal_p (temp_hard_regset, | |
815 | temp_hard_regset2)) | |
816 | break; | |
7db7ed3c VM |
817 | else if (hard_reg_set_subset_p (temp_hard_regset, |
818 | temp_hard_regset2)) | |
819 | set_p = true; | |
820 | } | |
db1a8d98 VM |
821 | if (set_p && j >= ira_reg_class_cover_size) |
822 | ira_important_classes[ira_important_classes_num++] | |
823 | = (enum reg_class) cl; | |
7db7ed3c | 824 | } |
058e97ec | 825 | } |
db1a8d98 VM |
826 | for (j = 0; j < ira_reg_class_cover_size; j++) |
827 | ira_important_classes[ira_important_classes_num++] | |
828 | = ira_reg_class_cover[j]; | |
058e97ec | 829 | } |
058e97ec VM |
830 | |
831 | /* Map of all register classes to corresponding cover class containing | |
832 | the given class. If given class is not a subset of a cover class, | |
833 | we translate it into the cheapest cover class. */ | |
834 | enum reg_class ira_class_translate[N_REG_CLASSES]; | |
835 | ||
058e97ec VM |
836 | /* Set up array IRA_CLASS_TRANSLATE. */ |
837 | static void | |
838 | setup_class_translate (void) | |
839 | { | |
32e8bb8e ILT |
840 | int cl, mode; |
841 | enum reg_class cover_class, best_class, *cl_ptr; | |
058e97ec VM |
842 | int i, cost, min_cost, best_cost; |
843 | ||
844 | for (cl = 0; cl < N_REG_CLASSES; cl++) | |
845 | ira_class_translate[cl] = NO_REGS; | |
7db7ed3c VM |
846 | |
847 | if (flag_ira_algorithm == IRA_ALGORITHM_PRIORITY) | |
848 | for (cl = 0; cl < LIM_REG_CLASSES; cl++) | |
849 | { | |
850 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); | |
851 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
852 | for (i = 0; i < ira_reg_class_cover_size; i++) | |
853 | { | |
854 | HARD_REG_SET temp_hard_regset2; | |
855 | ||
856 | cover_class = ira_reg_class_cover[i]; | |
857 | COPY_HARD_REG_SET (temp_hard_regset2, | |
858 | reg_class_contents[cover_class]); | |
859 | AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs); | |
860 | if (hard_reg_set_equal_p (temp_hard_regset, temp_hard_regset2)) | |
861 | ira_class_translate[cl] = cover_class; | |
862 | } | |
863 | } | |
058e97ec VM |
864 | for (i = 0; i < ira_reg_class_cover_size; i++) |
865 | { | |
866 | cover_class = ira_reg_class_cover[i]; | |
7db7ed3c VM |
867 | if (flag_ira_algorithm != IRA_ALGORITHM_PRIORITY) |
868 | for (cl_ptr = &alloc_reg_class_subclasses[cover_class][0]; | |
869 | (cl = *cl_ptr) != LIM_REG_CLASSES; | |
870 | cl_ptr++) | |
871 | { | |
872 | if (ira_class_translate[cl] == NO_REGS) | |
873 | ira_class_translate[cl] = cover_class; | |
058e97ec | 874 | #ifdef ENABLE_IRA_CHECKING |
7db7ed3c VM |
875 | else |
876 | { | |
877 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); | |
878 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
879 | if (! hard_reg_set_empty_p (temp_hard_regset)) | |
880 | gcc_unreachable (); | |
881 | } | |
058e97ec | 882 | #endif |
7db7ed3c | 883 | } |
058e97ec VM |
884 | ira_class_translate[cover_class] = cover_class; |
885 | } | |
886 | /* For classes which are not fully covered by a cover class (in | |
887 | other words covered by more one cover class), use the cheapest | |
888 | cover class. */ | |
889 | for (cl = 0; cl < N_REG_CLASSES; cl++) | |
890 | { | |
891 | if (cl == NO_REGS || ira_class_translate[cl] != NO_REGS) | |
892 | continue; | |
893 | best_class = NO_REGS; | |
894 | best_cost = INT_MAX; | |
895 | for (i = 0; i < ira_reg_class_cover_size; i++) | |
896 | { | |
897 | cover_class = ira_reg_class_cover[i]; | |
898 | COPY_HARD_REG_SET (temp_hard_regset, | |
899 | reg_class_contents[cover_class]); | |
900 | AND_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); | |
901 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
4f341ea0 | 902 | if (! hard_reg_set_empty_p (temp_hard_regset)) |
058e97ec VM |
903 | { |
904 | min_cost = INT_MAX; | |
905 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
906 | { | |
907 | cost = (ira_memory_move_cost[mode][cl][0] | |
908 | + ira_memory_move_cost[mode][cl][1]); | |
909 | if (min_cost > cost) | |
910 | min_cost = cost; | |
911 | } | |
912 | if (best_class == NO_REGS || best_cost > min_cost) | |
913 | { | |
914 | best_class = cover_class; | |
915 | best_cost = min_cost; | |
916 | } | |
917 | } | |
918 | } | |
919 | ira_class_translate[cl] = best_class; | |
920 | } | |
921 | } | |
058e97ec | 922 | |
db1a8d98 VM |
923 | /* Order numbers of cover classes in original target cover class |
924 | array, -1 for non-cover classes. */ | |
925 | static int cover_class_order[N_REG_CLASSES]; | |
926 | ||
927 | /* The function used to sort the important classes. */ | |
928 | static int | |
929 | comp_reg_classes_func (const void *v1p, const void *v2p) | |
930 | { | |
931 | enum reg_class cl1 = *(const enum reg_class *) v1p; | |
932 | enum reg_class cl2 = *(const enum reg_class *) v2p; | |
933 | int diff; | |
934 | ||
935 | cl1 = ira_class_translate[cl1]; | |
936 | cl2 = ira_class_translate[cl2]; | |
937 | if (cl1 != NO_REGS && cl2 != NO_REGS | |
938 | && (diff = cover_class_order[cl1] - cover_class_order[cl2]) != 0) | |
939 | return diff; | |
940 | return (int) cl1 - (int) cl2; | |
941 | } | |
942 | ||
943 | /* Reorder important classes according to the order of their cover | |
944 | classes. Set up array ira_important_class_nums too. */ | |
945 | static void | |
946 | reorder_important_classes (void) | |
947 | { | |
948 | int i; | |
949 | ||
950 | for (i = 0; i < N_REG_CLASSES; i++) | |
951 | cover_class_order[i] = -1; | |
952 | for (i = 0; i < ira_reg_class_cover_size; i++) | |
953 | cover_class_order[ira_reg_class_cover[i]] = i; | |
954 | qsort (ira_important_classes, ira_important_classes_num, | |
955 | sizeof (enum reg_class), comp_reg_classes_func); | |
956 | for (i = 0; i < ira_important_classes_num; i++) | |
957 | ira_important_class_nums[ira_important_classes[i]] = i; | |
958 | } | |
959 | ||
058e97ec VM |
960 | /* The biggest important reg_class inside of intersection of the two |
961 | reg_classes (that is calculated taking only hard registers | |
962 | available for allocation into account). If the both reg_classes | |
963 | contain no hard registers available for allocation, the value is | |
964 | calculated by taking all hard-registers including fixed ones into | |
965 | account. */ | |
966 | enum reg_class ira_reg_class_intersect[N_REG_CLASSES][N_REG_CLASSES]; | |
967 | ||
7db7ed3c VM |
968 | /* True if the two classes (that is calculated taking only hard |
969 | registers available for allocation into account) are | |
970 | intersected. */ | |
971 | bool ira_reg_classes_intersect_p[N_REG_CLASSES][N_REG_CLASSES]; | |
972 | ||
973 | /* Important classes with end marker LIM_REG_CLASSES which are | |
974 | supersets with given important class (the first index). That | |
975 | includes given class itself. This is calculated taking only hard | |
976 | registers available for allocation into account. */ | |
977 | enum reg_class ira_reg_class_super_classes[N_REG_CLASSES][N_REG_CLASSES]; | |
978 | ||
058e97ec VM |
979 | /* The biggest important reg_class inside of union of the two |
980 | reg_classes (that is calculated taking only hard registers | |
981 | available for allocation into account). If the both reg_classes | |
982 | contain no hard registers available for allocation, the value is | |
983 | calculated by taking all hard-registers including fixed ones into | |
984 | account. In other words, the value is the corresponding | |
985 | reg_class_subunion value. */ | |
986 | enum reg_class ira_reg_class_union[N_REG_CLASSES][N_REG_CLASSES]; | |
987 | ||
7db7ed3c | 988 | /* Set up the above reg class relations. */ |
058e97ec | 989 | static void |
7db7ed3c | 990 | setup_reg_class_relations (void) |
058e97ec VM |
991 | { |
992 | int i, cl1, cl2, cl3; | |
993 | HARD_REG_SET intersection_set, union_set, temp_set2; | |
7db7ed3c | 994 | bool important_class_p[N_REG_CLASSES]; |
058e97ec | 995 | |
7db7ed3c VM |
996 | memset (important_class_p, 0, sizeof (important_class_p)); |
997 | for (i = 0; i < ira_important_classes_num; i++) | |
998 | important_class_p[ira_important_classes[i]] = true; | |
058e97ec VM |
999 | for (cl1 = 0; cl1 < N_REG_CLASSES; cl1++) |
1000 | { | |
7db7ed3c | 1001 | ira_reg_class_super_classes[cl1][0] = LIM_REG_CLASSES; |
058e97ec VM |
1002 | for (cl2 = 0; cl2 < N_REG_CLASSES; cl2++) |
1003 | { | |
7db7ed3c | 1004 | ira_reg_classes_intersect_p[cl1][cl2] = false; |
058e97ec VM |
1005 | ira_reg_class_intersect[cl1][cl2] = NO_REGS; |
1006 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl1]); | |
1007 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
1008 | COPY_HARD_REG_SET (temp_set2, reg_class_contents[cl2]); | |
1009 | AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs); | |
4f341ea0 RS |
1010 | if (hard_reg_set_empty_p (temp_hard_regset) |
1011 | && hard_reg_set_empty_p (temp_set2)) | |
058e97ec VM |
1012 | { |
1013 | for (i = 0;; i++) | |
1014 | { | |
1015 | cl3 = reg_class_subclasses[cl1][i]; | |
1016 | if (cl3 == LIM_REG_CLASSES) | |
1017 | break; | |
1018 | if (reg_class_subset_p (ira_reg_class_intersect[cl1][cl2], | |
bbbbb16a ILT |
1019 | (enum reg_class) cl3)) |
1020 | ira_reg_class_intersect[cl1][cl2] = (enum reg_class) cl3; | |
058e97ec VM |
1021 | } |
1022 | ira_reg_class_union[cl1][cl2] = reg_class_subunion[cl1][cl2]; | |
1023 | continue; | |
1024 | } | |
7db7ed3c VM |
1025 | ira_reg_classes_intersect_p[cl1][cl2] |
1026 | = hard_reg_set_intersect_p (temp_hard_regset, temp_set2); | |
1027 | if (important_class_p[cl1] && important_class_p[cl2] | |
1028 | && hard_reg_set_subset_p (temp_hard_regset, temp_set2)) | |
1029 | { | |
1030 | enum reg_class *p; | |
1031 | ||
1032 | p = &ira_reg_class_super_classes[cl1][0]; | |
1033 | while (*p != LIM_REG_CLASSES) | |
1034 | p++; | |
1035 | *p++ = (enum reg_class) cl2; | |
1036 | *p = LIM_REG_CLASSES; | |
1037 | } | |
058e97ec VM |
1038 | ira_reg_class_union[cl1][cl2] = NO_REGS; |
1039 | COPY_HARD_REG_SET (intersection_set, reg_class_contents[cl1]); | |
1040 | AND_HARD_REG_SET (intersection_set, reg_class_contents[cl2]); | |
1041 | AND_COMPL_HARD_REG_SET (intersection_set, no_unit_alloc_regs); | |
1042 | COPY_HARD_REG_SET (union_set, reg_class_contents[cl1]); | |
1043 | IOR_HARD_REG_SET (union_set, reg_class_contents[cl2]); | |
1044 | AND_COMPL_HARD_REG_SET (union_set, no_unit_alloc_regs); | |
1045 | for (i = 0; i < ira_important_classes_num; i++) | |
1046 | { | |
1047 | cl3 = ira_important_classes[i]; | |
1048 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl3]); | |
1049 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
1050 | if (hard_reg_set_subset_p (temp_hard_regset, intersection_set)) | |
1051 | { | |
1052 | COPY_HARD_REG_SET | |
1053 | (temp_set2, | |
1054 | reg_class_contents[(int) | |
1055 | ira_reg_class_intersect[cl1][cl2]]); | |
1056 | AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs); | |
1057 | if (! hard_reg_set_subset_p (temp_hard_regset, temp_set2) | |
1058 | /* Ignore unavailable hard registers and prefer | |
1059 | smallest class for debugging purposes. */ | |
1060 | || (hard_reg_set_equal_p (temp_hard_regset, temp_set2) | |
1061 | && hard_reg_set_subset_p | |
1062 | (reg_class_contents[cl3], | |
1063 | reg_class_contents | |
1064 | [(int) ira_reg_class_intersect[cl1][cl2]]))) | |
1065 | ira_reg_class_intersect[cl1][cl2] = (enum reg_class) cl3; | |
1066 | } | |
1067 | if (hard_reg_set_subset_p (temp_hard_regset, union_set)) | |
1068 | { | |
1069 | COPY_HARD_REG_SET | |
1070 | (temp_set2, | |
1071 | reg_class_contents[(int) ira_reg_class_union[cl1][cl2]]); | |
1072 | AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs); | |
1073 | if (ira_reg_class_union[cl1][cl2] == NO_REGS | |
1074 | || (hard_reg_set_subset_p (temp_set2, temp_hard_regset) | |
1075 | ||
1076 | && (! hard_reg_set_equal_p (temp_set2, | |
1077 | temp_hard_regset) | |
1078 | /* Ignore unavailable hard registers and | |
1079 | prefer smallest class for debugging | |
1080 | purposes. */ | |
1081 | || hard_reg_set_subset_p | |
1082 | (reg_class_contents[cl3], | |
1083 | reg_class_contents | |
1084 | [(int) ira_reg_class_union[cl1][cl2]])))) | |
1085 | ira_reg_class_union[cl1][cl2] = (enum reg_class) cl3; | |
1086 | } | |
1087 | } | |
1088 | } | |
1089 | } | |
1090 | } | |
1091 | ||
058e97ec VM |
1092 | /* Output all cover classes and the translation map into file F. */ |
1093 | static void | |
1094 | print_class_cover (FILE *f) | |
1095 | { | |
1096 | static const char *const reg_class_names[] = REG_CLASS_NAMES; | |
1097 | int i; | |
1098 | ||
1099 | fprintf (f, "Class cover:\n"); | |
1100 | for (i = 0; i < ira_reg_class_cover_size; i++) | |
1101 | fprintf (f, " %s", reg_class_names[ira_reg_class_cover[i]]); | |
1102 | fprintf (f, "\nClass translation:\n"); | |
1103 | for (i = 0; i < N_REG_CLASSES; i++) | |
1104 | fprintf (f, " %s -> %s\n", reg_class_names[i], | |
1105 | reg_class_names[ira_class_translate[i]]); | |
1106 | } | |
1107 | ||
1108 | /* Output all cover classes and the translation map into | |
1109 | stderr. */ | |
1110 | void | |
1111 | ira_debug_class_cover (void) | |
1112 | { | |
1113 | print_class_cover (stderr); | |
1114 | } | |
1115 | ||
1116 | /* Set up different arrays concerning class subsets, cover and | |
1117 | important classes. */ | |
1118 | static void | |
1119 | find_reg_class_closure (void) | |
1120 | { | |
1121 | setup_reg_subclasses (); | |
7db7ed3c VM |
1122 | setup_cover_and_important_classes (); |
1123 | setup_class_translate (); | |
db1a8d98 | 1124 | reorder_important_classes (); |
7db7ed3c | 1125 | setup_reg_class_relations (); |
058e97ec VM |
1126 | } |
1127 | ||
1128 | \f | |
1129 | ||
c0683a82 VM |
1130 | /* Map: hard register number -> cover class it belongs to. If the |
1131 | corresponding class is NO_REGS, the hard register is not available | |
1132 | for allocation. */ | |
1133 | enum reg_class ira_hard_regno_cover_class[FIRST_PSEUDO_REGISTER]; | |
1134 | ||
1135 | /* Set up the array above. */ | |
1136 | static void | |
1137 | setup_hard_regno_cover_class (void) | |
1138 | { | |
1139 | int i, j; | |
1140 | enum reg_class cl; | |
1141 | ||
1142 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1143 | { | |
1144 | ira_hard_regno_cover_class[i] = NO_REGS; | |
1145 | for (j = 0; j < ira_reg_class_cover_size; j++) | |
1146 | { | |
1147 | cl = ira_reg_class_cover[j]; | |
1148 | if (ira_class_hard_reg_index[cl][i] >= 0) | |
1149 | { | |
1150 | ira_hard_regno_cover_class[i] = cl; | |
1151 | break; | |
1152 | } | |
1153 | } | |
1154 | ||
1155 | } | |
1156 | } | |
1157 | ||
1158 | \f | |
1159 | ||
058e97ec VM |
1160 | /* Map: register class x machine mode -> number of hard registers of |
1161 | given class needed to store value of given mode. If the number is | |
1162 | different, the size will be negative. */ | |
1163 | int ira_reg_class_nregs[N_REG_CLASSES][MAX_MACHINE_MODE]; | |
1164 | ||
1165 | /* Maximal value of the previous array elements. */ | |
1166 | int ira_max_nregs; | |
1167 | ||
1168 | /* Form IRA_REG_CLASS_NREGS map. */ | |
1169 | static void | |
1170 | setup_reg_class_nregs (void) | |
1171 | { | |
bbbbb16a | 1172 | int cl, m; |
058e97ec VM |
1173 | |
1174 | ira_max_nregs = -1; | |
1175 | for (cl = 0; cl < N_REG_CLASSES; cl++) | |
1176 | for (m = 0; m < MAX_MACHINE_MODE; m++) | |
1177 | { | |
bbbbb16a ILT |
1178 | ira_reg_class_nregs[cl][m] = CLASS_MAX_NREGS ((enum reg_class) cl, |
1179 | (enum machine_mode) m); | |
058e97ec VM |
1180 | if (ira_max_nregs < ira_reg_class_nregs[cl][m]) |
1181 | ira_max_nregs = ira_reg_class_nregs[cl][m]; | |
1182 | } | |
1183 | } | |
1184 | ||
1185 | \f | |
1186 | ||
1187 | /* Array whose values are hard regset of hard registers available for | |
1188 | the allocation of given register class whose HARD_REGNO_MODE_OK | |
1189 | values for given mode are zero. */ | |
1190 | HARD_REG_SET prohibited_class_mode_regs[N_REG_CLASSES][NUM_MACHINE_MODES]; | |
1191 | ||
1192 | /* Set up PROHIBITED_CLASS_MODE_REGS. */ | |
1193 | static void | |
1194 | setup_prohibited_class_mode_regs (void) | |
1195 | { | |
1196 | int i, j, k, hard_regno; | |
1197 | enum reg_class cl; | |
1198 | ||
1199 | for (i = 0; i < ira_reg_class_cover_size; i++) | |
1200 | { | |
1201 | cl = ira_reg_class_cover[i]; | |
1202 | for (j = 0; j < NUM_MACHINE_MODES; j++) | |
1203 | { | |
1204 | CLEAR_HARD_REG_SET (prohibited_class_mode_regs[cl][j]); | |
1205 | for (k = ira_class_hard_regs_num[cl] - 1; k >= 0; k--) | |
1206 | { | |
1207 | hard_regno = ira_class_hard_regs[cl][k]; | |
bbbbb16a | 1208 | if (! HARD_REGNO_MODE_OK (hard_regno, (enum machine_mode) j)) |
058e97ec VM |
1209 | SET_HARD_REG_BIT (prohibited_class_mode_regs[cl][j], |
1210 | hard_regno); | |
1211 | } | |
1212 | } | |
1213 | } | |
1214 | } | |
1215 | ||
1216 | \f | |
1217 | ||
1218 | /* Allocate and initialize IRA_REGISTER_MOVE_COST, | |
1219 | IRA_MAY_MOVE_IN_COST, and IRA_MAY_MOVE_OUT_COST for MODE if it is | |
1220 | not done yet. */ | |
1221 | void | |
1222 | ira_init_register_move_cost (enum machine_mode mode) | |
1223 | { | |
1224 | int cl1, cl2; | |
1225 | ||
1226 | ira_assert (ira_register_move_cost[mode] == NULL | |
1227 | && ira_may_move_in_cost[mode] == NULL | |
1228 | && ira_may_move_out_cost[mode] == NULL); | |
1229 | if (move_cost[mode] == NULL) | |
1230 | init_move_cost (mode); | |
1231 | ira_register_move_cost[mode] = move_cost[mode]; | |
1232 | /* Don't use ira_allocate because the tables exist out of scope of a | |
1233 | IRA call. */ | |
1234 | ira_may_move_in_cost[mode] | |
1235 | = (move_table *) xmalloc (sizeof (move_table) * N_REG_CLASSES); | |
1236 | memcpy (ira_may_move_in_cost[mode], may_move_in_cost[mode], | |
1237 | sizeof (move_table) * N_REG_CLASSES); | |
1238 | ira_may_move_out_cost[mode] | |
1239 | = (move_table *) xmalloc (sizeof (move_table) * N_REG_CLASSES); | |
1240 | memcpy (ira_may_move_out_cost[mode], may_move_out_cost[mode], | |
1241 | sizeof (move_table) * N_REG_CLASSES); | |
1242 | for (cl1 = 0; cl1 < N_REG_CLASSES; cl1++) | |
1243 | { | |
1244 | for (cl2 = 0; cl2 < N_REG_CLASSES; cl2++) | |
1245 | { | |
1246 | if (ira_class_subset_p[cl1][cl2]) | |
1247 | ira_may_move_in_cost[mode][cl1][cl2] = 0; | |
1248 | if (ira_class_subset_p[cl2][cl1]) | |
1249 | ira_may_move_out_cost[mode][cl1][cl2] = 0; | |
1250 | } | |
1251 | } | |
1252 | } | |
1253 | ||
1254 | \f | |
1255 | ||
058e97ec VM |
1256 | /* This is called once during compiler work. It sets up |
1257 | different arrays whose values don't depend on the compiled | |
1258 | function. */ | |
1259 | void | |
1260 | ira_init_once (void) | |
1261 | { | |
32e8bb8e | 1262 | int mode; |
058e97ec | 1263 | |
058e97ec VM |
1264 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) |
1265 | { | |
1266 | ira_register_move_cost[mode] = NULL; | |
1267 | ira_may_move_in_cost[mode] = NULL; | |
1268 | ira_may_move_out_cost[mode] = NULL; | |
1269 | } | |
1270 | ira_init_costs_once (); | |
1271 | } | |
1272 | ||
1273 | /* Free ira_register_move_cost, ira_may_move_in_cost, and | |
1274 | ira_may_move_out_cost for each mode. */ | |
1275 | static void | |
1276 | free_register_move_costs (void) | |
1277 | { | |
32e8bb8e | 1278 | int mode; |
058e97ec VM |
1279 | |
1280 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
1281 | { | |
1282 | if (ira_may_move_in_cost[mode] != NULL) | |
1283 | free (ira_may_move_in_cost[mode]); | |
1284 | if (ira_may_move_out_cost[mode] != NULL) | |
1285 | free (ira_may_move_out_cost[mode]); | |
1286 | ira_register_move_cost[mode] = NULL; | |
1287 | ira_may_move_in_cost[mode] = NULL; | |
1288 | ira_may_move_out_cost[mode] = NULL; | |
1289 | } | |
1290 | } | |
1291 | ||
1292 | /* This is called every time when register related information is | |
1293 | changed. */ | |
1294 | void | |
1295 | ira_init (void) | |
1296 | { | |
1297 | free_register_move_costs (); | |
1298 | setup_reg_mode_hard_regset (); | |
1299 | setup_alloc_regs (flag_omit_frame_pointer != 0); | |
1300 | setup_class_subset_and_memory_move_costs (); | |
1301 | find_reg_class_closure (); | |
c0683a82 | 1302 | setup_hard_regno_cover_class (); |
058e97ec VM |
1303 | setup_reg_class_nregs (); |
1304 | setup_prohibited_class_mode_regs (); | |
1305 | ira_init_costs (); | |
1306 | } | |
1307 | ||
1308 | /* Function called once at the end of compiler work. */ | |
1309 | void | |
1310 | ira_finish_once (void) | |
1311 | { | |
1312 | ira_finish_costs_once (); | |
1313 | free_register_move_costs (); | |
1314 | } | |
1315 | ||
1316 | \f | |
1317 | ||
1318 | /* Array whose values are hard regset of hard registers for which | |
1319 | move of the hard register in given mode into itself is | |
1320 | prohibited. */ | |
1321 | HARD_REG_SET ira_prohibited_mode_move_regs[NUM_MACHINE_MODES]; | |
1322 | ||
1323 | /* Flag of that the above array has been initialized. */ | |
1324 | static bool ira_prohibited_mode_move_regs_initialized_p = false; | |
1325 | ||
1326 | /* Set up IRA_PROHIBITED_MODE_MOVE_REGS. */ | |
1327 | static void | |
1328 | setup_prohibited_mode_move_regs (void) | |
1329 | { | |
1330 | int i, j; | |
1331 | rtx test_reg1, test_reg2, move_pat, move_insn; | |
1332 | ||
1333 | if (ira_prohibited_mode_move_regs_initialized_p) | |
1334 | return; | |
1335 | ira_prohibited_mode_move_regs_initialized_p = true; | |
1336 | test_reg1 = gen_rtx_REG (VOIDmode, 0); | |
1337 | test_reg2 = gen_rtx_REG (VOIDmode, 0); | |
1338 | move_pat = gen_rtx_SET (VOIDmode, test_reg1, test_reg2); | |
1339 | move_insn = gen_rtx_INSN (VOIDmode, 0, 0, 0, 0, 0, move_pat, -1, 0); | |
1340 | for (i = 0; i < NUM_MACHINE_MODES; i++) | |
1341 | { | |
1342 | SET_HARD_REG_SET (ira_prohibited_mode_move_regs[i]); | |
1343 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
1344 | { | |
bbbbb16a | 1345 | if (! HARD_REGNO_MODE_OK (j, (enum machine_mode) i)) |
058e97ec VM |
1346 | continue; |
1347 | SET_REGNO (test_reg1, j); | |
32e8bb8e | 1348 | PUT_MODE (test_reg1, (enum machine_mode) i); |
058e97ec | 1349 | SET_REGNO (test_reg2, j); |
32e8bb8e | 1350 | PUT_MODE (test_reg2, (enum machine_mode) i); |
058e97ec VM |
1351 | INSN_CODE (move_insn) = -1; |
1352 | recog_memoized (move_insn); | |
1353 | if (INSN_CODE (move_insn) < 0) | |
1354 | continue; | |
1355 | extract_insn (move_insn); | |
1356 | if (! constrain_operands (1)) | |
1357 | continue; | |
1358 | CLEAR_HARD_REG_BIT (ira_prohibited_mode_move_regs[i], j); | |
1359 | } | |
1360 | } | |
1361 | } | |
1362 | ||
1363 | \f | |
1364 | ||
1365 | /* Function specific hard registers that can not be used for the | |
1366 | register allocation. */ | |
1367 | HARD_REG_SET ira_no_alloc_regs; | |
1368 | ||
1369 | /* Return TRUE if *LOC contains an asm. */ | |
1370 | static int | |
1371 | insn_contains_asm_1 (rtx *loc, void *data ATTRIBUTE_UNUSED) | |
1372 | { | |
1373 | if ( !*loc) | |
1374 | return FALSE; | |
1375 | if (GET_CODE (*loc) == ASM_OPERANDS) | |
1376 | return TRUE; | |
1377 | return FALSE; | |
1378 | } | |
1379 | ||
1380 | ||
1381 | /* Return TRUE if INSN contains an ASM. */ | |
1382 | static bool | |
1383 | insn_contains_asm (rtx insn) | |
1384 | { | |
1385 | return for_each_rtx (&insn, insn_contains_asm_1, NULL); | |
1386 | } | |
1387 | ||
1388 | /* Set up regs_asm_clobbered. */ | |
1389 | static void | |
1390 | compute_regs_asm_clobbered (char *regs_asm_clobbered) | |
1391 | { | |
1392 | basic_block bb; | |
1393 | ||
1394 | memset (regs_asm_clobbered, 0, sizeof (char) * FIRST_PSEUDO_REGISTER); | |
1395 | ||
1396 | FOR_EACH_BB (bb) | |
1397 | { | |
1398 | rtx insn; | |
1399 | FOR_BB_INSNS_REVERSE (bb, insn) | |
1400 | { | |
57512f53 | 1401 | df_ref *def_rec; |
058e97ec VM |
1402 | |
1403 | if (insn_contains_asm (insn)) | |
1404 | for (def_rec = DF_INSN_DEFS (insn); *def_rec; def_rec++) | |
1405 | { | |
57512f53 | 1406 | df_ref def = *def_rec; |
058e97ec VM |
1407 | unsigned int dregno = DF_REF_REGNO (def); |
1408 | if (dregno < FIRST_PSEUDO_REGISTER) | |
1409 | { | |
1410 | unsigned int i; | |
1411 | enum machine_mode mode = GET_MODE (DF_REF_REAL_REG (def)); | |
1412 | unsigned int end = dregno | |
1413 | + hard_regno_nregs[dregno][mode] - 1; | |
1414 | ||
1415 | for (i = dregno; i <= end; ++i) | |
1416 | regs_asm_clobbered[i] = 1; | |
1417 | } | |
1418 | } | |
1419 | } | |
1420 | } | |
1421 | } | |
1422 | ||
1423 | ||
1424 | /* Set up ELIMINABLE_REGSET, IRA_NO_ALLOC_REGS, and REGS_EVER_LIVE. */ | |
1425 | static void | |
1426 | setup_eliminable_regset (void) | |
1427 | { | |
058e97ec VM |
1428 | /* Like regs_ever_live, but 1 if a reg is set or clobbered from an |
1429 | asm. Unlike regs_ever_live, elements of this array corresponding | |
1430 | to eliminable regs (like the frame pointer) are set if an asm | |
1431 | sets them. */ | |
1432 | char *regs_asm_clobbered | |
1433 | = (char *) alloca (FIRST_PSEUDO_REGISTER * sizeof (char)); | |
1434 | #ifdef ELIMINABLE_REGS | |
89ceba31 | 1435 | int i; |
058e97ec VM |
1436 | static const struct {const int from, to; } eliminables[] = ELIMINABLE_REGS; |
1437 | #endif | |
1438 | /* FIXME: If EXIT_IGNORE_STACK is set, we will not save and restore | |
1439 | sp for alloca. So we can't eliminate the frame pointer in that | |
1440 | case. At some point, we should improve this by emitting the | |
1441 | sp-adjusting insns for this case. */ | |
1442 | int need_fp | |
1443 | = (! flag_omit_frame_pointer | |
1444 | || (cfun->calls_alloca && EXIT_IGNORE_STACK) | |
1445 | || crtl->accesses_prior_frames | |
1446 | || crtl->stack_realign_needed | |
b52b1749 | 1447 | || targetm.frame_pointer_required ()); |
058e97ec VM |
1448 | |
1449 | frame_pointer_needed = need_fp; | |
1450 | ||
1451 | COPY_HARD_REG_SET (ira_no_alloc_regs, no_unit_alloc_regs); | |
1452 | CLEAR_HARD_REG_SET (eliminable_regset); | |
1453 | ||
1454 | compute_regs_asm_clobbered (regs_asm_clobbered); | |
1455 | /* Build the regset of all eliminable registers and show we can't | |
1456 | use those that we already know won't be eliminated. */ | |
1457 | #ifdef ELIMINABLE_REGS | |
1458 | for (i = 0; i < (int) ARRAY_SIZE (eliminables); i++) | |
1459 | { | |
1460 | bool cannot_elim | |
7b5cbb57 | 1461 | = (! targetm.can_eliminate (eliminables[i].from, eliminables[i].to) |
058e97ec VM |
1462 | || (eliminables[i].to == STACK_POINTER_REGNUM && need_fp)); |
1463 | ||
1464 | if (! regs_asm_clobbered[eliminables[i].from]) | |
1465 | { | |
1466 | SET_HARD_REG_BIT (eliminable_regset, eliminables[i].from); | |
1467 | ||
1468 | if (cannot_elim) | |
1469 | SET_HARD_REG_BIT (ira_no_alloc_regs, eliminables[i].from); | |
1470 | } | |
1471 | else if (cannot_elim) | |
1472 | error ("%s cannot be used in asm here", | |
1473 | reg_names[eliminables[i].from]); | |
1474 | else | |
1475 | df_set_regs_ever_live (eliminables[i].from, true); | |
1476 | } | |
1477 | #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM | |
1478 | if (! regs_asm_clobbered[HARD_FRAME_POINTER_REGNUM]) | |
1479 | { | |
1480 | SET_HARD_REG_BIT (eliminable_regset, HARD_FRAME_POINTER_REGNUM); | |
1481 | if (need_fp) | |
1482 | SET_HARD_REG_BIT (ira_no_alloc_regs, HARD_FRAME_POINTER_REGNUM); | |
1483 | } | |
1484 | else if (need_fp) | |
1485 | error ("%s cannot be used in asm here", | |
1486 | reg_names[HARD_FRAME_POINTER_REGNUM]); | |
1487 | else | |
1488 | df_set_regs_ever_live (HARD_FRAME_POINTER_REGNUM, true); | |
1489 | #endif | |
1490 | ||
1491 | #else | |
1492 | if (! regs_asm_clobbered[FRAME_POINTER_REGNUM]) | |
1493 | { | |
1494 | SET_HARD_REG_BIT (eliminable_regset, FRAME_POINTER_REGNUM); | |
1495 | if (need_fp) | |
1496 | SET_HARD_REG_BIT (ira_no_alloc_regs, FRAME_POINTER_REGNUM); | |
1497 | } | |
1498 | else if (need_fp) | |
1499 | error ("%s cannot be used in asm here", reg_names[FRAME_POINTER_REGNUM]); | |
1500 | else | |
1501 | df_set_regs_ever_live (FRAME_POINTER_REGNUM, true); | |
1502 | #endif | |
1503 | } | |
1504 | ||
1505 | \f | |
1506 | ||
1507 | /* The length of the following two arrays. */ | |
1508 | int ira_reg_equiv_len; | |
1509 | ||
1510 | /* The element value is TRUE if the corresponding regno value is | |
1511 | invariant. */ | |
1512 | bool *ira_reg_equiv_invariant_p; | |
1513 | ||
1514 | /* The element value is equiv constant of given pseudo-register or | |
1515 | NULL_RTX. */ | |
1516 | rtx *ira_reg_equiv_const; | |
1517 | ||
1518 | /* Set up the two arrays declared above. */ | |
1519 | static void | |
1520 | find_reg_equiv_invariant_const (void) | |
1521 | { | |
1522 | int i; | |
1523 | bool invariant_p; | |
1524 | rtx list, insn, note, constant, x; | |
1525 | ||
1526 | for (i = FIRST_PSEUDO_REGISTER; i < reg_equiv_init_size; i++) | |
1527 | { | |
1528 | constant = NULL_RTX; | |
1529 | invariant_p = false; | |
1530 | for (list = reg_equiv_init[i]; list != NULL_RTX; list = XEXP (list, 1)) | |
1531 | { | |
1532 | insn = XEXP (list, 0); | |
1533 | note = find_reg_note (insn, REG_EQUIV, NULL_RTX); | |
1534 | ||
1535 | if (note == NULL_RTX) | |
1536 | continue; | |
1537 | ||
1538 | x = XEXP (note, 0); | |
1539 | ||
1540 | if (! function_invariant_p (x) | |
1541 | || ! flag_pic | |
1542 | /* A function invariant is often CONSTANT_P but may | |
1543 | include a register. We promise to only pass CONSTANT_P | |
1544 | objects to LEGITIMATE_PIC_OPERAND_P. */ | |
1545 | || (CONSTANT_P (x) && LEGITIMATE_PIC_OPERAND_P (x))) | |
1546 | { | |
1547 | /* It can happen that a REG_EQUIV note contains a MEM | |
1548 | that is not a legitimate memory operand. As later | |
1549 | stages of the reload assume that all addresses found | |
1550 | in the reg_equiv_* arrays were originally legitimate, | |
1551 | we ignore such REG_EQUIV notes. */ | |
1552 | if (memory_operand (x, VOIDmode)) | |
1553 | invariant_p = MEM_READONLY_P (x); | |
1554 | else if (function_invariant_p (x)) | |
1555 | { | |
1556 | if (GET_CODE (x) == PLUS | |
1557 | || x == frame_pointer_rtx || x == arg_pointer_rtx) | |
1558 | invariant_p = true; | |
1559 | else | |
1560 | constant = x; | |
1561 | } | |
1562 | } | |
1563 | } | |
1564 | ira_reg_equiv_invariant_p[i] = invariant_p; | |
1565 | ira_reg_equiv_const[i] = constant; | |
1566 | } | |
1567 | } | |
1568 | ||
1569 | \f | |
1570 | ||
2af2dbdc VM |
1571 | /* Vector of substitutions of register numbers, |
1572 | used to map pseudo regs into hardware regs. | |
1573 | This is set up as a result of register allocation. | |
1574 | Element N is the hard reg assigned to pseudo reg N, | |
1575 | or is -1 if no hard reg was assigned. | |
1576 | If N is a hard reg number, element N is N. */ | |
1577 | short *reg_renumber; | |
1578 | ||
058e97ec VM |
1579 | /* Set up REG_RENUMBER and CALLER_SAVE_NEEDED (used by reload) from |
1580 | the allocation found by IRA. */ | |
1581 | static void | |
1582 | setup_reg_renumber (void) | |
1583 | { | |
1584 | int regno, hard_regno; | |
1585 | ira_allocno_t a; | |
1586 | ira_allocno_iterator ai; | |
1587 | ||
1588 | caller_save_needed = 0; | |
1589 | FOR_EACH_ALLOCNO (a, ai) | |
1590 | { | |
1591 | /* There are no caps at this point. */ | |
1592 | ira_assert (ALLOCNO_CAP_MEMBER (a) == NULL); | |
1593 | if (! ALLOCNO_ASSIGNED_P (a)) | |
1594 | /* It can happen if A is not referenced but partially anticipated | |
1595 | somewhere in a region. */ | |
1596 | ALLOCNO_ASSIGNED_P (a) = true; | |
1597 | ira_free_allocno_updated_costs (a); | |
1598 | hard_regno = ALLOCNO_HARD_REGNO (a); | |
1599 | regno = (int) REGNO (ALLOCNO_REG (a)); | |
1600 | reg_renumber[regno] = (hard_regno < 0 ? -1 : hard_regno); | |
1601 | if (hard_regno >= 0 && ALLOCNO_CALLS_CROSSED_NUM (a) != 0 | |
1602 | && ! ira_hard_reg_not_in_set_p (hard_regno, ALLOCNO_MODE (a), | |
1603 | call_used_reg_set)) | |
1604 | { | |
1605 | ira_assert (!optimize || flag_caller_saves | |
1606 | || regno >= ira_reg_equiv_len | |
1607 | || ira_reg_equiv_const[regno] | |
1608 | || ira_reg_equiv_invariant_p[regno]); | |
1609 | caller_save_needed = 1; | |
1610 | } | |
1611 | } | |
1612 | } | |
1613 | ||
1614 | /* Set up allocno assignment flags for further allocation | |
1615 | improvements. */ | |
1616 | static void | |
1617 | setup_allocno_assignment_flags (void) | |
1618 | { | |
1619 | int hard_regno; | |
1620 | ira_allocno_t a; | |
1621 | ira_allocno_iterator ai; | |
1622 | ||
1623 | FOR_EACH_ALLOCNO (a, ai) | |
1624 | { | |
1625 | if (! ALLOCNO_ASSIGNED_P (a)) | |
1626 | /* It can happen if A is not referenced but partially anticipated | |
1627 | somewhere in a region. */ | |
1628 | ira_free_allocno_updated_costs (a); | |
1629 | hard_regno = ALLOCNO_HARD_REGNO (a); | |
1630 | /* Don't assign hard registers to allocnos which are destination | |
1631 | of removed store at the end of loop. It has no sense to keep | |
1632 | the same value in different hard registers. It is also | |
1633 | impossible to assign hard registers correctly to such | |
1634 | allocnos because the cost info and info about intersected | |
1635 | calls are incorrect for them. */ | |
1636 | ALLOCNO_ASSIGNED_P (a) = (hard_regno >= 0 | |
1637 | || ALLOCNO_MEM_OPTIMIZED_DEST_P (a) | |
1638 | || (ALLOCNO_MEMORY_COST (a) | |
1639 | - ALLOCNO_COVER_CLASS_COST (a)) < 0); | |
1640 | ira_assert (hard_regno < 0 | |
1641 | || ! ira_hard_reg_not_in_set_p (hard_regno, ALLOCNO_MODE (a), | |
1642 | reg_class_contents | |
1643 | [ALLOCNO_COVER_CLASS (a)])); | |
1644 | } | |
1645 | } | |
1646 | ||
1647 | /* Evaluate overall allocation cost and the costs for using hard | |
1648 | registers and memory for allocnos. */ | |
1649 | static void | |
1650 | calculate_allocation_cost (void) | |
1651 | { | |
1652 | int hard_regno, cost; | |
1653 | ira_allocno_t a; | |
1654 | ira_allocno_iterator ai; | |
1655 | ||
1656 | ira_overall_cost = ira_reg_cost = ira_mem_cost = 0; | |
1657 | FOR_EACH_ALLOCNO (a, ai) | |
1658 | { | |
1659 | hard_regno = ALLOCNO_HARD_REGNO (a); | |
1660 | ira_assert (hard_regno < 0 | |
1661 | || ! ira_hard_reg_not_in_set_p | |
1662 | (hard_regno, ALLOCNO_MODE (a), | |
1663 | reg_class_contents[ALLOCNO_COVER_CLASS (a)])); | |
1664 | if (hard_regno < 0) | |
1665 | { | |
1666 | cost = ALLOCNO_MEMORY_COST (a); | |
1667 | ira_mem_cost += cost; | |
1668 | } | |
1669 | else if (ALLOCNO_HARD_REG_COSTS (a) != NULL) | |
1670 | { | |
1671 | cost = (ALLOCNO_HARD_REG_COSTS (a) | |
1672 | [ira_class_hard_reg_index | |
1673 | [ALLOCNO_COVER_CLASS (a)][hard_regno]]); | |
1674 | ira_reg_cost += cost; | |
1675 | } | |
1676 | else | |
1677 | { | |
1678 | cost = ALLOCNO_COVER_CLASS_COST (a); | |
1679 | ira_reg_cost += cost; | |
1680 | } | |
1681 | ira_overall_cost += cost; | |
1682 | } | |
1683 | ||
1684 | if (internal_flag_ira_verbose > 0 && ira_dump_file != NULL) | |
1685 | { | |
1686 | fprintf (ira_dump_file, | |
1687 | "+++Costs: overall %d, reg %d, mem %d, ld %d, st %d, move %d\n", | |
1688 | ira_overall_cost, ira_reg_cost, ira_mem_cost, | |
1689 | ira_load_cost, ira_store_cost, ira_shuffle_cost); | |
1690 | fprintf (ira_dump_file, "+++ move loops %d, new jumps %d\n", | |
1691 | ira_move_loops_num, ira_additional_jumps_num); | |
1692 | } | |
1693 | ||
1694 | } | |
1695 | ||
1696 | #ifdef ENABLE_IRA_CHECKING | |
1697 | /* Check the correctness of the allocation. We do need this because | |
1698 | of complicated code to transform more one region internal | |
1699 | representation into one region representation. */ | |
1700 | static void | |
1701 | check_allocation (void) | |
1702 | { | |
1703 | ira_allocno_t a, conflict_a; | |
1704 | int hard_regno, conflict_hard_regno, nregs, conflict_nregs; | |
1705 | ira_allocno_conflict_iterator aci; | |
1706 | ira_allocno_iterator ai; | |
1707 | ||
1708 | FOR_EACH_ALLOCNO (a, ai) | |
1709 | { | |
1710 | if (ALLOCNO_CAP_MEMBER (a) != NULL | |
1711 | || (hard_regno = ALLOCNO_HARD_REGNO (a)) < 0) | |
1712 | continue; | |
1713 | nregs = hard_regno_nregs[hard_regno][ALLOCNO_MODE (a)]; | |
1714 | FOR_EACH_ALLOCNO_CONFLICT (a, conflict_a, aci) | |
1715 | if ((conflict_hard_regno = ALLOCNO_HARD_REGNO (conflict_a)) >= 0) | |
1716 | { | |
1717 | conflict_nregs | |
1718 | = (hard_regno_nregs | |
1719 | [conflict_hard_regno][ALLOCNO_MODE (conflict_a)]); | |
1720 | if ((conflict_hard_regno <= hard_regno | |
1721 | && hard_regno < conflict_hard_regno + conflict_nregs) | |
1722 | || (hard_regno <= conflict_hard_regno | |
1723 | && conflict_hard_regno < hard_regno + nregs)) | |
1724 | { | |
1725 | fprintf (stderr, "bad allocation for %d and %d\n", | |
1726 | ALLOCNO_REGNO (a), ALLOCNO_REGNO (conflict_a)); | |
1727 | gcc_unreachable (); | |
1728 | } | |
1729 | } | |
1730 | } | |
1731 | } | |
1732 | #endif | |
1733 | ||
1734 | /* Fix values of array REG_EQUIV_INIT after live range splitting done | |
1735 | by IRA. */ | |
1736 | static void | |
1737 | fix_reg_equiv_init (void) | |
1738 | { | |
1739 | int max_regno = max_reg_num (); | |
1740 | int i, new_regno; | |
1741 | rtx x, prev, next, insn, set; | |
1742 | ||
1743 | if (reg_equiv_init_size < max_regno) | |
1744 | { | |
1745 | reg_equiv_init | |
1746 | = (rtx *) ggc_realloc (reg_equiv_init, max_regno * sizeof (rtx)); | |
1747 | while (reg_equiv_init_size < max_regno) | |
1748 | reg_equiv_init[reg_equiv_init_size++] = NULL_RTX; | |
1749 | for (i = FIRST_PSEUDO_REGISTER; i < reg_equiv_init_size; i++) | |
1750 | for (prev = NULL_RTX, x = reg_equiv_init[i]; x != NULL_RTX; x = next) | |
1751 | { | |
1752 | next = XEXP (x, 1); | |
1753 | insn = XEXP (x, 0); | |
1754 | set = single_set (insn); | |
1755 | ira_assert (set != NULL_RTX | |
1756 | && (REG_P (SET_DEST (set)) || REG_P (SET_SRC (set)))); | |
1757 | if (REG_P (SET_DEST (set)) | |
1758 | && ((int) REGNO (SET_DEST (set)) == i | |
1759 | || (int) ORIGINAL_REGNO (SET_DEST (set)) == i)) | |
1760 | new_regno = REGNO (SET_DEST (set)); | |
1761 | else if (REG_P (SET_SRC (set)) | |
1762 | && ((int) REGNO (SET_SRC (set)) == i | |
1763 | || (int) ORIGINAL_REGNO (SET_SRC (set)) == i)) | |
1764 | new_regno = REGNO (SET_SRC (set)); | |
1765 | else | |
1766 | gcc_unreachable (); | |
1767 | if (new_regno == i) | |
1768 | prev = x; | |
1769 | else | |
1770 | { | |
1771 | if (prev == NULL_RTX) | |
1772 | reg_equiv_init[i] = next; | |
1773 | else | |
1774 | XEXP (prev, 1) = next; | |
1775 | XEXP (x, 1) = reg_equiv_init[new_regno]; | |
1776 | reg_equiv_init[new_regno] = x; | |
1777 | } | |
1778 | } | |
1779 | } | |
1780 | } | |
1781 | ||
1782 | #ifdef ENABLE_IRA_CHECKING | |
1783 | /* Print redundant memory-memory copies. */ | |
1784 | static void | |
1785 | print_redundant_copies (void) | |
1786 | { | |
1787 | int hard_regno; | |
1788 | ira_allocno_t a; | |
1789 | ira_copy_t cp, next_cp; | |
1790 | ira_allocno_iterator ai; | |
1791 | ||
1792 | FOR_EACH_ALLOCNO (a, ai) | |
1793 | { | |
1794 | if (ALLOCNO_CAP_MEMBER (a) != NULL) | |
1795 | /* It is a cap. */ | |
1796 | continue; | |
1797 | hard_regno = ALLOCNO_HARD_REGNO (a); | |
1798 | if (hard_regno >= 0) | |
1799 | continue; | |
1800 | for (cp = ALLOCNO_COPIES (a); cp != NULL; cp = next_cp) | |
1801 | if (cp->first == a) | |
1802 | next_cp = cp->next_first_allocno_copy; | |
1803 | else | |
1804 | { | |
1805 | next_cp = cp->next_second_allocno_copy; | |
1806 | if (internal_flag_ira_verbose > 4 && ira_dump_file != NULL | |
1807 | && cp->insn != NULL_RTX | |
1808 | && ALLOCNO_HARD_REGNO (cp->first) == hard_regno) | |
1809 | fprintf (ira_dump_file, | |
1810 | " Redundant move from %d(freq %d):%d\n", | |
1811 | INSN_UID (cp->insn), cp->freq, hard_regno); | |
1812 | } | |
1813 | } | |
1814 | } | |
1815 | #endif | |
1816 | ||
1817 | /* Setup preferred and alternative classes for new pseudo-registers | |
1818 | created by IRA starting with START. */ | |
1819 | static void | |
1820 | setup_preferred_alternate_classes_for_new_pseudos (int start) | |
1821 | { | |
1822 | int i, old_regno; | |
1823 | int max_regno = max_reg_num (); | |
1824 | ||
1825 | for (i = start; i < max_regno; i++) | |
1826 | { | |
1827 | old_regno = ORIGINAL_REGNO (regno_reg_rtx[i]); | |
1828 | ira_assert (i != old_regno); | |
1829 | setup_reg_classes (i, reg_preferred_class (old_regno), | |
1830 | reg_alternate_class (old_regno)); | |
1831 | if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL) | |
1832 | fprintf (ira_dump_file, | |
1833 | " New r%d: setting preferred %s, alternative %s\n", | |
1834 | i, reg_class_names[reg_preferred_class (old_regno)], | |
1835 | reg_class_names[reg_alternate_class (old_regno)]); | |
1836 | } | |
1837 | } | |
1838 | ||
1839 | \f | |
1840 | ||
1841 | /* Regional allocation can create new pseudo-registers. This function | |
1842 | expands some arrays for pseudo-registers. */ | |
1843 | static void | |
1844 | expand_reg_info (int old_size) | |
1845 | { | |
1846 | int i; | |
1847 | int size = max_reg_num (); | |
1848 | ||
1849 | resize_reg_info (); | |
1850 | for (i = old_size; i < size; i++) | |
1851 | { | |
1852 | reg_renumber[i] = -1; | |
1853 | setup_reg_classes (i, GENERAL_REGS, ALL_REGS); | |
1854 | } | |
1855 | } | |
1856 | ||
3553f0bb VM |
1857 | /* Return TRUE if there is too high register pressure in the function. |
1858 | It is used to decide when stack slot sharing is worth to do. */ | |
1859 | static bool | |
1860 | too_high_register_pressure_p (void) | |
1861 | { | |
1862 | int i; | |
1863 | enum reg_class cover_class; | |
1864 | ||
1865 | for (i = 0; i < ira_reg_class_cover_size; i++) | |
1866 | { | |
1867 | cover_class = ira_reg_class_cover[i]; | |
1868 | if (ira_loop_tree_root->reg_pressure[cover_class] > 10000) | |
1869 | return true; | |
1870 | } | |
1871 | return false; | |
1872 | } | |
1873 | ||
058e97ec VM |
1874 | \f |
1875 | ||
2af2dbdc VM |
1876 | /* Indicate that hard register number FROM was eliminated and replaced with |
1877 | an offset from hard register number TO. The status of hard registers live | |
1878 | at the start of a basic block is updated by replacing a use of FROM with | |
1879 | a use of TO. */ | |
1880 | ||
1881 | void | |
1882 | mark_elimination (int from, int to) | |
1883 | { | |
1884 | basic_block bb; | |
1885 | ||
1886 | FOR_EACH_BB (bb) | |
1887 | { | |
1888 | /* We don't use LIVE info in IRA. */ | |
1889 | regset r = DF_LR_IN (bb); | |
1890 | ||
1891 | if (REGNO_REG_SET_P (r, from)) | |
1892 | { | |
1893 | CLEAR_REGNO_REG_SET (r, from); | |
1894 | SET_REGNO_REG_SET (r, to); | |
1895 | } | |
1896 | } | |
1897 | } | |
1898 | ||
1899 | \f | |
1900 | ||
1901 | struct equivalence | |
1902 | { | |
2af2dbdc VM |
1903 | /* Set when a REG_EQUIV note is found or created. Use to |
1904 | keep track of what memory accesses might be created later, | |
1905 | e.g. by reload. */ | |
1906 | rtx replacement; | |
1907 | rtx *src_p; | |
8f5929e1 JJ |
1908 | /* The list of each instruction which initializes this register. */ |
1909 | rtx init_insns; | |
2af2dbdc VM |
1910 | /* Loop depth is used to recognize equivalences which appear |
1911 | to be present within the same loop (or in an inner loop). */ | |
1912 | int loop_depth; | |
2af2dbdc VM |
1913 | /* Nonzero if this had a preexisting REG_EQUIV note. */ |
1914 | int is_arg_equivalence; | |
8f5929e1 JJ |
1915 | /* Set when an attempt should be made to replace a register |
1916 | with the associated src_p entry. */ | |
1917 | char replace; | |
2af2dbdc VM |
1918 | }; |
1919 | ||
1920 | /* reg_equiv[N] (where N is a pseudo reg number) is the equivalence | |
1921 | structure for that register. */ | |
1922 | static struct equivalence *reg_equiv; | |
1923 | ||
1924 | /* Used for communication between the following two functions: contains | |
1925 | a MEM that we wish to ensure remains unchanged. */ | |
1926 | static rtx equiv_mem; | |
1927 | ||
1928 | /* Set nonzero if EQUIV_MEM is modified. */ | |
1929 | static int equiv_mem_modified; | |
1930 | ||
1931 | /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified. | |
1932 | Called via note_stores. */ | |
1933 | static void | |
1934 | validate_equiv_mem_from_store (rtx dest, const_rtx set ATTRIBUTE_UNUSED, | |
1935 | void *data ATTRIBUTE_UNUSED) | |
1936 | { | |
1937 | if ((REG_P (dest) | |
1938 | && reg_overlap_mentioned_p (dest, equiv_mem)) | |
1939 | || (MEM_P (dest) | |
1940 | && true_dependence (dest, VOIDmode, equiv_mem, rtx_varies_p))) | |
1941 | equiv_mem_modified = 1; | |
1942 | } | |
1943 | ||
1944 | /* Verify that no store between START and the death of REG invalidates | |
1945 | MEMREF. MEMREF is invalidated by modifying a register used in MEMREF, | |
1946 | by storing into an overlapping memory location, or with a non-const | |
1947 | CALL_INSN. | |
1948 | ||
1949 | Return 1 if MEMREF remains valid. */ | |
1950 | static int | |
1951 | validate_equiv_mem (rtx start, rtx reg, rtx memref) | |
1952 | { | |
1953 | rtx insn; | |
1954 | rtx note; | |
1955 | ||
1956 | equiv_mem = memref; | |
1957 | equiv_mem_modified = 0; | |
1958 | ||
1959 | /* If the memory reference has side effects or is volatile, it isn't a | |
1960 | valid equivalence. */ | |
1961 | if (side_effects_p (memref)) | |
1962 | return 0; | |
1963 | ||
1964 | for (insn = start; insn && ! equiv_mem_modified; insn = NEXT_INSN (insn)) | |
1965 | { | |
1966 | if (! INSN_P (insn)) | |
1967 | continue; | |
1968 | ||
1969 | if (find_reg_note (insn, REG_DEAD, reg)) | |
1970 | return 1; | |
1971 | ||
1972 | if (CALL_P (insn) && ! MEM_READONLY_P (memref) | |
1973 | && ! RTL_CONST_OR_PURE_CALL_P (insn)) | |
1974 | return 0; | |
1975 | ||
1976 | note_stores (PATTERN (insn), validate_equiv_mem_from_store, NULL); | |
1977 | ||
1978 | /* If a register mentioned in MEMREF is modified via an | |
1979 | auto-increment, we lose the equivalence. Do the same if one | |
1980 | dies; although we could extend the life, it doesn't seem worth | |
1981 | the trouble. */ | |
1982 | ||
1983 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
1984 | if ((REG_NOTE_KIND (note) == REG_INC | |
1985 | || REG_NOTE_KIND (note) == REG_DEAD) | |
1986 | && REG_P (XEXP (note, 0)) | |
1987 | && reg_overlap_mentioned_p (XEXP (note, 0), memref)) | |
1988 | return 0; | |
1989 | } | |
1990 | ||
1991 | return 0; | |
1992 | } | |
1993 | ||
1994 | /* Returns zero if X is known to be invariant. */ | |
1995 | static int | |
1996 | equiv_init_varies_p (rtx x) | |
1997 | { | |
1998 | RTX_CODE code = GET_CODE (x); | |
1999 | int i; | |
2000 | const char *fmt; | |
2001 | ||
2002 | switch (code) | |
2003 | { | |
2004 | case MEM: | |
2005 | return !MEM_READONLY_P (x) || equiv_init_varies_p (XEXP (x, 0)); | |
2006 | ||
2007 | case CONST: | |
2008 | case CONST_INT: | |
2009 | case CONST_DOUBLE: | |
2010 | case CONST_FIXED: | |
2011 | case CONST_VECTOR: | |
2012 | case SYMBOL_REF: | |
2013 | case LABEL_REF: | |
2014 | return 0; | |
2015 | ||
2016 | case REG: | |
2017 | return reg_equiv[REGNO (x)].replace == 0 && rtx_varies_p (x, 0); | |
2018 | ||
2019 | case ASM_OPERANDS: | |
2020 | if (MEM_VOLATILE_P (x)) | |
2021 | return 1; | |
2022 | ||
2023 | /* Fall through. */ | |
2024 | ||
2025 | default: | |
2026 | break; | |
2027 | } | |
2028 | ||
2029 | fmt = GET_RTX_FORMAT (code); | |
2030 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2031 | if (fmt[i] == 'e') | |
2032 | { | |
2033 | if (equiv_init_varies_p (XEXP (x, i))) | |
2034 | return 1; | |
2035 | } | |
2036 | else if (fmt[i] == 'E') | |
2037 | { | |
2038 | int j; | |
2039 | for (j = 0; j < XVECLEN (x, i); j++) | |
2040 | if (equiv_init_varies_p (XVECEXP (x, i, j))) | |
2041 | return 1; | |
2042 | } | |
2043 | ||
2044 | return 0; | |
2045 | } | |
2046 | ||
2047 | /* Returns nonzero if X (used to initialize register REGNO) is movable. | |
2048 | X is only movable if the registers it uses have equivalent initializations | |
2049 | which appear to be within the same loop (or in an inner loop) and movable | |
2050 | or if they are not candidates for local_alloc and don't vary. */ | |
2051 | static int | |
2052 | equiv_init_movable_p (rtx x, int regno) | |
2053 | { | |
2054 | int i, j; | |
2055 | const char *fmt; | |
2056 | enum rtx_code code = GET_CODE (x); | |
2057 | ||
2058 | switch (code) | |
2059 | { | |
2060 | case SET: | |
2061 | return equiv_init_movable_p (SET_SRC (x), regno); | |
2062 | ||
2063 | case CC0: | |
2064 | case CLOBBER: | |
2065 | return 0; | |
2066 | ||
2067 | case PRE_INC: | |
2068 | case PRE_DEC: | |
2069 | case POST_INC: | |
2070 | case POST_DEC: | |
2071 | case PRE_MODIFY: | |
2072 | case POST_MODIFY: | |
2073 | return 0; | |
2074 | ||
2075 | case REG: | |
2076 | return (reg_equiv[REGNO (x)].loop_depth >= reg_equiv[regno].loop_depth | |
2077 | && reg_equiv[REGNO (x)].replace) | |
2078 | || (REG_BASIC_BLOCK (REGNO (x)) < NUM_FIXED_BLOCKS && ! rtx_varies_p (x, 0)); | |
2079 | ||
2080 | case UNSPEC_VOLATILE: | |
2081 | return 0; | |
2082 | ||
2083 | case ASM_OPERANDS: | |
2084 | if (MEM_VOLATILE_P (x)) | |
2085 | return 0; | |
2086 | ||
2087 | /* Fall through. */ | |
2088 | ||
2089 | default: | |
2090 | break; | |
2091 | } | |
2092 | ||
2093 | fmt = GET_RTX_FORMAT (code); | |
2094 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2095 | switch (fmt[i]) | |
2096 | { | |
2097 | case 'e': | |
2098 | if (! equiv_init_movable_p (XEXP (x, i), regno)) | |
2099 | return 0; | |
2100 | break; | |
2101 | case 'E': | |
2102 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
2103 | if (! equiv_init_movable_p (XVECEXP (x, i, j), regno)) | |
2104 | return 0; | |
2105 | break; | |
2106 | } | |
2107 | ||
2108 | return 1; | |
2109 | } | |
2110 | ||
2111 | /* TRUE if X uses any registers for which reg_equiv[REGNO].replace is true. */ | |
2112 | static int | |
2113 | contains_replace_regs (rtx x) | |
2114 | { | |
2115 | int i, j; | |
2116 | const char *fmt; | |
2117 | enum rtx_code code = GET_CODE (x); | |
2118 | ||
2119 | switch (code) | |
2120 | { | |
2121 | case CONST_INT: | |
2122 | case CONST: | |
2123 | case LABEL_REF: | |
2124 | case SYMBOL_REF: | |
2125 | case CONST_DOUBLE: | |
2126 | case CONST_FIXED: | |
2127 | case CONST_VECTOR: | |
2128 | case PC: | |
2129 | case CC0: | |
2130 | case HIGH: | |
2131 | return 0; | |
2132 | ||
2133 | case REG: | |
2134 | return reg_equiv[REGNO (x)].replace; | |
2135 | ||
2136 | default: | |
2137 | break; | |
2138 | } | |
2139 | ||
2140 | fmt = GET_RTX_FORMAT (code); | |
2141 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2142 | switch (fmt[i]) | |
2143 | { | |
2144 | case 'e': | |
2145 | if (contains_replace_regs (XEXP (x, i))) | |
2146 | return 1; | |
2147 | break; | |
2148 | case 'E': | |
2149 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
2150 | if (contains_replace_regs (XVECEXP (x, i, j))) | |
2151 | return 1; | |
2152 | break; | |
2153 | } | |
2154 | ||
2155 | return 0; | |
2156 | } | |
2157 | ||
2158 | /* TRUE if X references a memory location that would be affected by a store | |
2159 | to MEMREF. */ | |
2160 | static int | |
2161 | memref_referenced_p (rtx memref, rtx x) | |
2162 | { | |
2163 | int i, j; | |
2164 | const char *fmt; | |
2165 | enum rtx_code code = GET_CODE (x); | |
2166 | ||
2167 | switch (code) | |
2168 | { | |
2169 | case CONST_INT: | |
2170 | case CONST: | |
2171 | case LABEL_REF: | |
2172 | case SYMBOL_REF: | |
2173 | case CONST_DOUBLE: | |
2174 | case CONST_FIXED: | |
2175 | case CONST_VECTOR: | |
2176 | case PC: | |
2177 | case CC0: | |
2178 | case HIGH: | |
2179 | case LO_SUM: | |
2180 | return 0; | |
2181 | ||
2182 | case REG: | |
2183 | return (reg_equiv[REGNO (x)].replacement | |
2184 | && memref_referenced_p (memref, | |
2185 | reg_equiv[REGNO (x)].replacement)); | |
2186 | ||
2187 | case MEM: | |
2188 | if (true_dependence (memref, VOIDmode, x, rtx_varies_p)) | |
2189 | return 1; | |
2190 | break; | |
2191 | ||
2192 | case SET: | |
2193 | /* If we are setting a MEM, it doesn't count (its address does), but any | |
2194 | other SET_DEST that has a MEM in it is referencing the MEM. */ | |
2195 | if (MEM_P (SET_DEST (x))) | |
2196 | { | |
2197 | if (memref_referenced_p (memref, XEXP (SET_DEST (x), 0))) | |
2198 | return 1; | |
2199 | } | |
2200 | else if (memref_referenced_p (memref, SET_DEST (x))) | |
2201 | return 1; | |
2202 | ||
2203 | return memref_referenced_p (memref, SET_SRC (x)); | |
2204 | ||
2205 | default: | |
2206 | break; | |
2207 | } | |
2208 | ||
2209 | fmt = GET_RTX_FORMAT (code); | |
2210 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2211 | switch (fmt[i]) | |
2212 | { | |
2213 | case 'e': | |
2214 | if (memref_referenced_p (memref, XEXP (x, i))) | |
2215 | return 1; | |
2216 | break; | |
2217 | case 'E': | |
2218 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
2219 | if (memref_referenced_p (memref, XVECEXP (x, i, j))) | |
2220 | return 1; | |
2221 | break; | |
2222 | } | |
2223 | ||
2224 | return 0; | |
2225 | } | |
2226 | ||
2227 | /* TRUE if some insn in the range (START, END] references a memory location | |
2228 | that would be affected by a store to MEMREF. */ | |
2229 | static int | |
2230 | memref_used_between_p (rtx memref, rtx start, rtx end) | |
2231 | { | |
2232 | rtx insn; | |
2233 | ||
2234 | for (insn = NEXT_INSN (start); insn != NEXT_INSN (end); | |
2235 | insn = NEXT_INSN (insn)) | |
2236 | { | |
b5b8b0ac | 2237 | if (!NONDEBUG_INSN_P (insn)) |
2af2dbdc VM |
2238 | continue; |
2239 | ||
2240 | if (memref_referenced_p (memref, PATTERN (insn))) | |
2241 | return 1; | |
2242 | ||
2243 | /* Nonconst functions may access memory. */ | |
2244 | if (CALL_P (insn) && (! RTL_CONST_CALL_P (insn))) | |
2245 | return 1; | |
2246 | } | |
2247 | ||
2248 | return 0; | |
2249 | } | |
2250 | ||
2251 | /* Mark REG as having no known equivalence. | |
2252 | Some instructions might have been processed before and furnished | |
2253 | with REG_EQUIV notes for this register; these notes will have to be | |
2254 | removed. | |
2255 | STORE is the piece of RTL that does the non-constant / conflicting | |
2256 | assignment - a SET, CLOBBER or REG_INC note. It is currently not used, | |
2257 | but needs to be there because this function is called from note_stores. */ | |
2258 | static void | |
2259 | no_equiv (rtx reg, const_rtx store ATTRIBUTE_UNUSED, void *data ATTRIBUTE_UNUSED) | |
2260 | { | |
2261 | int regno; | |
2262 | rtx list; | |
2263 | ||
2264 | if (!REG_P (reg)) | |
2265 | return; | |
2266 | regno = REGNO (reg); | |
2267 | list = reg_equiv[regno].init_insns; | |
2268 | if (list == const0_rtx) | |
2269 | return; | |
2270 | reg_equiv[regno].init_insns = const0_rtx; | |
2271 | reg_equiv[regno].replacement = NULL_RTX; | |
2272 | /* This doesn't matter for equivalences made for argument registers, we | |
2273 | should keep their initialization insns. */ | |
2274 | if (reg_equiv[regno].is_arg_equivalence) | |
2275 | return; | |
2276 | reg_equiv_init[regno] = NULL_RTX; | |
2277 | for (; list; list = XEXP (list, 1)) | |
2278 | { | |
2279 | rtx insn = XEXP (list, 0); | |
2280 | remove_note (insn, find_reg_note (insn, REG_EQUIV, NULL_RTX)); | |
2281 | } | |
2282 | } | |
2283 | ||
2284 | /* Nonzero if we recorded an equivalence for a LABEL_REF. */ | |
2285 | static int recorded_label_ref; | |
2286 | ||
2287 | /* Find registers that are equivalent to a single value throughout the | |
2288 | compilation (either because they can be referenced in memory or are set once | |
2289 | from a single constant). Lower their priority for a register. | |
2290 | ||
2291 | If such a register is only referenced once, try substituting its value | |
2292 | into the using insn. If it succeeds, we can eliminate the register | |
2293 | completely. | |
2294 | ||
2295 | Initialize the REG_EQUIV_INIT array of initializing insns. | |
2296 | ||
2297 | Return non-zero if jump label rebuilding should be done. */ | |
2298 | static int | |
2299 | update_equiv_regs (void) | |
2300 | { | |
2301 | rtx insn; | |
2302 | basic_block bb; | |
2303 | int loop_depth; | |
2304 | bitmap cleared_regs; | |
2305 | ||
2306 | /* We need to keep track of whether or not we recorded a LABEL_REF so | |
2307 | that we know if the jump optimizer needs to be rerun. */ | |
2308 | recorded_label_ref = 0; | |
2309 | ||
2310 | reg_equiv = XCNEWVEC (struct equivalence, max_regno); | |
2311 | reg_equiv_init = GGC_CNEWVEC (rtx, max_regno); | |
2312 | reg_equiv_init_size = max_regno; | |
2313 | ||
2314 | init_alias_analysis (); | |
2315 | ||
2316 | /* Scan the insns and find which registers have equivalences. Do this | |
2317 | in a separate scan of the insns because (due to -fcse-follow-jumps) | |
2318 | a register can be set below its use. */ | |
2319 | FOR_EACH_BB (bb) | |
2320 | { | |
2321 | loop_depth = bb->loop_depth; | |
2322 | ||
2323 | for (insn = BB_HEAD (bb); | |
2324 | insn != NEXT_INSN (BB_END (bb)); | |
2325 | insn = NEXT_INSN (insn)) | |
2326 | { | |
2327 | rtx note; | |
2328 | rtx set; | |
2329 | rtx dest, src; | |
2330 | int regno; | |
2331 | ||
2332 | if (! INSN_P (insn)) | |
2333 | continue; | |
2334 | ||
2335 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
2336 | if (REG_NOTE_KIND (note) == REG_INC) | |
2337 | no_equiv (XEXP (note, 0), note, NULL); | |
2338 | ||
2339 | set = single_set (insn); | |
2340 | ||
2341 | /* If this insn contains more (or less) than a single SET, | |
2342 | only mark all destinations as having no known equivalence. */ | |
2343 | if (set == 0) | |
2344 | { | |
2345 | note_stores (PATTERN (insn), no_equiv, NULL); | |
2346 | continue; | |
2347 | } | |
2348 | else if (GET_CODE (PATTERN (insn)) == PARALLEL) | |
2349 | { | |
2350 | int i; | |
2351 | ||
2352 | for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--) | |
2353 | { | |
2354 | rtx part = XVECEXP (PATTERN (insn), 0, i); | |
2355 | if (part != set) | |
2356 | note_stores (part, no_equiv, NULL); | |
2357 | } | |
2358 | } | |
2359 | ||
2360 | dest = SET_DEST (set); | |
2361 | src = SET_SRC (set); | |
2362 | ||
2363 | /* See if this is setting up the equivalence between an argument | |
2364 | register and its stack slot. */ | |
2365 | note = find_reg_note (insn, REG_EQUIV, NULL_RTX); | |
2366 | if (note) | |
2367 | { | |
2368 | gcc_assert (REG_P (dest)); | |
2369 | regno = REGNO (dest); | |
2370 | ||
2371 | /* Note that we don't want to clear reg_equiv_init even if there | |
2372 | are multiple sets of this register. */ | |
2373 | reg_equiv[regno].is_arg_equivalence = 1; | |
2374 | ||
2375 | /* Record for reload that this is an equivalencing insn. */ | |
2376 | if (rtx_equal_p (src, XEXP (note, 0))) | |
2377 | reg_equiv_init[regno] | |
2378 | = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[regno]); | |
2379 | ||
2380 | /* Continue normally in case this is a candidate for | |
2381 | replacements. */ | |
2382 | } | |
2383 | ||
2384 | if (!optimize) | |
2385 | continue; | |
2386 | ||
2387 | /* We only handle the case of a pseudo register being set | |
2388 | once, or always to the same value. */ | |
2389 | /* ??? The mn10200 port breaks if we add equivalences for | |
2390 | values that need an ADDRESS_REGS register and set them equivalent | |
2391 | to a MEM of a pseudo. The actual problem is in the over-conservative | |
2392 | handling of INPADDR_ADDRESS / INPUT_ADDRESS / INPUT triples in | |
2393 | calculate_needs, but we traditionally work around this problem | |
2394 | here by rejecting equivalences when the destination is in a register | |
2395 | that's likely spilled. This is fragile, of course, since the | |
2396 | preferred class of a pseudo depends on all instructions that set | |
2397 | or use it. */ | |
2398 | ||
2399 | if (!REG_P (dest) | |
2400 | || (regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER | |
2401 | || reg_equiv[regno].init_insns == const0_rtx | |
2402 | || (CLASS_LIKELY_SPILLED_P (reg_preferred_class (regno)) | |
2403 | && MEM_P (src) && ! reg_equiv[regno].is_arg_equivalence)) | |
2404 | { | |
2405 | /* This might be setting a SUBREG of a pseudo, a pseudo that is | |
2406 | also set somewhere else to a constant. */ | |
2407 | note_stores (set, no_equiv, NULL); | |
2408 | continue; | |
2409 | } | |
2410 | ||
2411 | note = find_reg_note (insn, REG_EQUAL, NULL_RTX); | |
2412 | ||
2413 | /* cse sometimes generates function invariants, but doesn't put a | |
2414 | REG_EQUAL note on the insn. Since this note would be redundant, | |
2415 | there's no point creating it earlier than here. */ | |
2416 | if (! note && ! rtx_varies_p (src, 0)) | |
2417 | note = set_unique_reg_note (insn, REG_EQUAL, copy_rtx (src)); | |
2418 | ||
2419 | /* Don't bother considering a REG_EQUAL note containing an EXPR_LIST | |
2420 | since it represents a function call */ | |
2421 | if (note && GET_CODE (XEXP (note, 0)) == EXPR_LIST) | |
2422 | note = NULL_RTX; | |
2423 | ||
2424 | if (DF_REG_DEF_COUNT (regno) != 1 | |
2425 | && (! note | |
2426 | || rtx_varies_p (XEXP (note, 0), 0) | |
2427 | || (reg_equiv[regno].replacement | |
2428 | && ! rtx_equal_p (XEXP (note, 0), | |
2429 | reg_equiv[regno].replacement)))) | |
2430 | { | |
2431 | no_equiv (dest, set, NULL); | |
2432 | continue; | |
2433 | } | |
2434 | /* Record this insn as initializing this register. */ | |
2435 | reg_equiv[regno].init_insns | |
2436 | = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv[regno].init_insns); | |
2437 | ||
2438 | /* If this register is known to be equal to a constant, record that | |
2439 | it is always equivalent to the constant. */ | |
2440 | if (DF_REG_DEF_COUNT (regno) == 1 | |
2441 | && note && ! rtx_varies_p (XEXP (note, 0), 0)) | |
2442 | { | |
2443 | rtx note_value = XEXP (note, 0); | |
2444 | remove_note (insn, note); | |
2445 | set_unique_reg_note (insn, REG_EQUIV, note_value); | |
2446 | } | |
2447 | ||
2448 | /* If this insn introduces a "constant" register, decrease the priority | |
2449 | of that register. Record this insn if the register is only used once | |
2450 | more and the equivalence value is the same as our source. | |
2451 | ||
2452 | The latter condition is checked for two reasons: First, it is an | |
2453 | indication that it may be more efficient to actually emit the insn | |
2454 | as written (if no registers are available, reload will substitute | |
2455 | the equivalence). Secondly, it avoids problems with any registers | |
2456 | dying in this insn whose death notes would be missed. | |
2457 | ||
2458 | If we don't have a REG_EQUIV note, see if this insn is loading | |
2459 | a register used only in one basic block from a MEM. If so, and the | |
2460 | MEM remains unchanged for the life of the register, add a REG_EQUIV | |
2461 | note. */ | |
2462 | ||
2463 | note = find_reg_note (insn, REG_EQUIV, NULL_RTX); | |
2464 | ||
2465 | if (note == 0 && REG_BASIC_BLOCK (regno) >= NUM_FIXED_BLOCKS | |
2466 | && MEM_P (SET_SRC (set)) | |
2467 | && validate_equiv_mem (insn, dest, SET_SRC (set))) | |
2468 | note = set_unique_reg_note (insn, REG_EQUIV, copy_rtx (SET_SRC (set))); | |
2469 | ||
2470 | if (note) | |
2471 | { | |
2472 | int regno = REGNO (dest); | |
2473 | rtx x = XEXP (note, 0); | |
2474 | ||
2475 | /* If we haven't done so, record for reload that this is an | |
2476 | equivalencing insn. */ | |
2477 | if (!reg_equiv[regno].is_arg_equivalence) | |
2478 | reg_equiv_init[regno] | |
2479 | = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[regno]); | |
2480 | ||
2481 | /* Record whether or not we created a REG_EQUIV note for a LABEL_REF. | |
2482 | We might end up substituting the LABEL_REF for uses of the | |
2483 | pseudo here or later. That kind of transformation may turn an | |
2484 | indirect jump into a direct jump, in which case we must rerun the | |
2485 | jump optimizer to ensure that the JUMP_LABEL fields are valid. */ | |
2486 | if (GET_CODE (x) == LABEL_REF | |
2487 | || (GET_CODE (x) == CONST | |
2488 | && GET_CODE (XEXP (x, 0)) == PLUS | |
2489 | && (GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF))) | |
2490 | recorded_label_ref = 1; | |
2491 | ||
2492 | reg_equiv[regno].replacement = x; | |
2493 | reg_equiv[regno].src_p = &SET_SRC (set); | |
2494 | reg_equiv[regno].loop_depth = loop_depth; | |
2495 | ||
2496 | /* Don't mess with things live during setjmp. */ | |
2497 | if (REG_LIVE_LENGTH (regno) >= 0 && optimize) | |
2498 | { | |
2499 | /* Note that the statement below does not affect the priority | |
2500 | in local-alloc! */ | |
2501 | REG_LIVE_LENGTH (regno) *= 2; | |
2502 | ||
2503 | /* If the register is referenced exactly twice, meaning it is | |
2504 | set once and used once, indicate that the reference may be | |
2505 | replaced by the equivalence we computed above. Do this | |
2506 | even if the register is only used in one block so that | |
2507 | dependencies can be handled where the last register is | |
2508 | used in a different block (i.e. HIGH / LO_SUM sequences) | |
2509 | and to reduce the number of registers alive across | |
2510 | calls. */ | |
2511 | ||
2512 | if (REG_N_REFS (regno) == 2 | |
2513 | && (rtx_equal_p (x, src) | |
2514 | || ! equiv_init_varies_p (src)) | |
2515 | && NONJUMP_INSN_P (insn) | |
2516 | && equiv_init_movable_p (PATTERN (insn), regno)) | |
2517 | reg_equiv[regno].replace = 1; | |
2518 | } | |
2519 | } | |
2520 | } | |
2521 | } | |
2522 | ||
2523 | if (!optimize) | |
2524 | goto out; | |
2525 | ||
2526 | /* A second pass, to gather additional equivalences with memory. This needs | |
2527 | to be done after we know which registers we are going to replace. */ | |
2528 | ||
2529 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
2530 | { | |
2531 | rtx set, src, dest; | |
2532 | unsigned regno; | |
2533 | ||
2534 | if (! INSN_P (insn)) | |
2535 | continue; | |
2536 | ||
2537 | set = single_set (insn); | |
2538 | if (! set) | |
2539 | continue; | |
2540 | ||
2541 | dest = SET_DEST (set); | |
2542 | src = SET_SRC (set); | |
2543 | ||
2544 | /* If this sets a MEM to the contents of a REG that is only used | |
2545 | in a single basic block, see if the register is always equivalent | |
2546 | to that memory location and if moving the store from INSN to the | |
2547 | insn that set REG is safe. If so, put a REG_EQUIV note on the | |
2548 | initializing insn. | |
2549 | ||
2550 | Don't add a REG_EQUIV note if the insn already has one. The existing | |
2551 | REG_EQUIV is likely more useful than the one we are adding. | |
2552 | ||
2553 | If one of the regs in the address has reg_equiv[REGNO].replace set, | |
2554 | then we can't add this REG_EQUIV note. The reg_equiv[REGNO].replace | |
2555 | optimization may move the set of this register immediately before | |
2556 | insn, which puts it after reg_equiv[REGNO].init_insns, and hence | |
2557 | the mention in the REG_EQUIV note would be to an uninitialized | |
2558 | pseudo. */ | |
2559 | ||
2560 | if (MEM_P (dest) && REG_P (src) | |
2561 | && (regno = REGNO (src)) >= FIRST_PSEUDO_REGISTER | |
2562 | && REG_BASIC_BLOCK (regno) >= NUM_FIXED_BLOCKS | |
2563 | && DF_REG_DEF_COUNT (regno) == 1 | |
2564 | && reg_equiv[regno].init_insns != 0 | |
2565 | && reg_equiv[regno].init_insns != const0_rtx | |
2566 | && ! find_reg_note (XEXP (reg_equiv[regno].init_insns, 0), | |
2567 | REG_EQUIV, NULL_RTX) | |
2568 | && ! contains_replace_regs (XEXP (dest, 0))) | |
2569 | { | |
2570 | rtx init_insn = XEXP (reg_equiv[regno].init_insns, 0); | |
2571 | if (validate_equiv_mem (init_insn, src, dest) | |
2572 | && ! memref_used_between_p (dest, init_insn, insn) | |
2573 | /* Attaching a REG_EQUIV note will fail if INIT_INSN has | |
2574 | multiple sets. */ | |
2575 | && set_unique_reg_note (init_insn, REG_EQUIV, copy_rtx (dest))) | |
2576 | { | |
2577 | /* This insn makes the equivalence, not the one initializing | |
2578 | the register. */ | |
2579 | reg_equiv_init[regno] | |
2580 | = gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX); | |
2581 | df_notes_rescan (init_insn); | |
2582 | } | |
2583 | } | |
2584 | } | |
2585 | ||
2586 | cleared_regs = BITMAP_ALLOC (NULL); | |
2587 | /* Now scan all regs killed in an insn to see if any of them are | |
2588 | registers only used that once. If so, see if we can replace the | |
2589 | reference with the equivalent form. If we can, delete the | |
2590 | initializing reference and this register will go away. If we | |
2591 | can't replace the reference, and the initializing reference is | |
2592 | within the same loop (or in an inner loop), then move the register | |
2593 | initialization just before the use, so that they are in the same | |
2594 | basic block. */ | |
2595 | FOR_EACH_BB_REVERSE (bb) | |
2596 | { | |
2597 | loop_depth = bb->loop_depth; | |
2598 | for (insn = BB_END (bb); | |
2599 | insn != PREV_INSN (BB_HEAD (bb)); | |
2600 | insn = PREV_INSN (insn)) | |
2601 | { | |
2602 | rtx link; | |
2603 | ||
2604 | if (! INSN_P (insn)) | |
2605 | continue; | |
2606 | ||
2607 | /* Don't substitute into a non-local goto, this confuses CFG. */ | |
2608 | if (JUMP_P (insn) | |
2609 | && find_reg_note (insn, REG_NON_LOCAL_GOTO, NULL_RTX)) | |
2610 | continue; | |
2611 | ||
2612 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | |
2613 | { | |
2614 | if (REG_NOTE_KIND (link) == REG_DEAD | |
2615 | /* Make sure this insn still refers to the register. */ | |
2616 | && reg_mentioned_p (XEXP (link, 0), PATTERN (insn))) | |
2617 | { | |
2618 | int regno = REGNO (XEXP (link, 0)); | |
2619 | rtx equiv_insn; | |
2620 | ||
2621 | if (! reg_equiv[regno].replace | |
2622 | || reg_equiv[regno].loop_depth < loop_depth) | |
2623 | continue; | |
2624 | ||
2625 | /* reg_equiv[REGNO].replace gets set only when | |
2626 | REG_N_REFS[REGNO] is 2, i.e. the register is set | |
2627 | once and used once. (If it were only set, but not used, | |
2628 | flow would have deleted the setting insns.) Hence | |
2629 | there can only be one insn in reg_equiv[REGNO].init_insns. */ | |
2630 | gcc_assert (reg_equiv[regno].init_insns | |
2631 | && !XEXP (reg_equiv[regno].init_insns, 1)); | |
2632 | equiv_insn = XEXP (reg_equiv[regno].init_insns, 0); | |
2633 | ||
2634 | /* We may not move instructions that can throw, since | |
2635 | that changes basic block boundaries and we are not | |
2636 | prepared to adjust the CFG to match. */ | |
2637 | if (can_throw_internal (equiv_insn)) | |
2638 | continue; | |
2639 | ||
2640 | if (asm_noperands (PATTERN (equiv_insn)) < 0 | |
2641 | && validate_replace_rtx (regno_reg_rtx[regno], | |
2642 | *(reg_equiv[regno].src_p), insn)) | |
2643 | { | |
2644 | rtx equiv_link; | |
2645 | rtx last_link; | |
2646 | rtx note; | |
2647 | ||
2648 | /* Find the last note. */ | |
2649 | for (last_link = link; XEXP (last_link, 1); | |
2650 | last_link = XEXP (last_link, 1)) | |
2651 | ; | |
2652 | ||
2653 | /* Append the REG_DEAD notes from equiv_insn. */ | |
2654 | equiv_link = REG_NOTES (equiv_insn); | |
2655 | while (equiv_link) | |
2656 | { | |
2657 | note = equiv_link; | |
2658 | equiv_link = XEXP (equiv_link, 1); | |
2659 | if (REG_NOTE_KIND (note) == REG_DEAD) | |
2660 | { | |
2661 | remove_note (equiv_insn, note); | |
2662 | XEXP (last_link, 1) = note; | |
2663 | XEXP (note, 1) = NULL_RTX; | |
2664 | last_link = note; | |
2665 | } | |
2666 | } | |
2667 | ||
2668 | remove_death (regno, insn); | |
2669 | SET_REG_N_REFS (regno, 0); | |
2670 | REG_FREQ (regno) = 0; | |
2671 | delete_insn (equiv_insn); | |
2672 | ||
2673 | reg_equiv[regno].init_insns | |
2674 | = XEXP (reg_equiv[regno].init_insns, 1); | |
2675 | ||
2676 | reg_equiv_init[regno] = NULL_RTX; | |
2677 | bitmap_set_bit (cleared_regs, regno); | |
2678 | } | |
2679 | /* Move the initialization of the register to just before | |
2680 | INSN. Update the flow information. */ | |
b5b8b0ac | 2681 | else if (prev_nondebug_insn (insn) != equiv_insn) |
2af2dbdc VM |
2682 | { |
2683 | rtx new_insn; | |
2684 | ||
2685 | new_insn = emit_insn_before (PATTERN (equiv_insn), insn); | |
2686 | REG_NOTES (new_insn) = REG_NOTES (equiv_insn); | |
2687 | REG_NOTES (equiv_insn) = 0; | |
2688 | /* Rescan it to process the notes. */ | |
2689 | df_insn_rescan (new_insn); | |
2690 | ||
2691 | /* Make sure this insn is recognized before | |
2692 | reload begins, otherwise | |
2693 | eliminate_regs_in_insn will die. */ | |
2694 | INSN_CODE (new_insn) = INSN_CODE (equiv_insn); | |
2695 | ||
2696 | delete_insn (equiv_insn); | |
2697 | ||
2698 | XEXP (reg_equiv[regno].init_insns, 0) = new_insn; | |
2699 | ||
2700 | REG_BASIC_BLOCK (regno) = bb->index; | |
2701 | REG_N_CALLS_CROSSED (regno) = 0; | |
2702 | REG_FREQ_CALLS_CROSSED (regno) = 0; | |
2703 | REG_N_THROWING_CALLS_CROSSED (regno) = 0; | |
2704 | REG_LIVE_LENGTH (regno) = 2; | |
2705 | ||
2706 | if (insn == BB_HEAD (bb)) | |
2707 | BB_HEAD (bb) = PREV_INSN (insn); | |
2708 | ||
2709 | reg_equiv_init[regno] | |
2710 | = gen_rtx_INSN_LIST (VOIDmode, new_insn, NULL_RTX); | |
2711 | bitmap_set_bit (cleared_regs, regno); | |
2712 | } | |
2713 | } | |
2714 | } | |
2715 | } | |
2716 | } | |
2717 | ||
2718 | if (!bitmap_empty_p (cleared_regs)) | |
2719 | FOR_EACH_BB (bb) | |
2720 | { | |
2721 | bitmap_and_compl_into (DF_LIVE_IN (bb), cleared_regs); | |
2722 | bitmap_and_compl_into (DF_LIVE_OUT (bb), cleared_regs); | |
2723 | bitmap_and_compl_into (DF_LR_IN (bb), cleared_regs); | |
2724 | bitmap_and_compl_into (DF_LR_OUT (bb), cleared_regs); | |
2725 | } | |
2726 | ||
2727 | BITMAP_FREE (cleared_regs); | |
2728 | ||
2729 | out: | |
2730 | /* Clean up. */ | |
2731 | ||
2732 | end_alias_analysis (); | |
2733 | free (reg_equiv); | |
2734 | return recorded_label_ref; | |
2735 | } | |
2736 | ||
2737 | \f | |
2738 | ||
2739 | /* Print chain C to FILE. */ | |
2740 | static void | |
2741 | print_insn_chain (FILE *file, struct insn_chain *c) | |
2742 | { | |
2743 | fprintf (file, "insn=%d, ", INSN_UID(c->insn)); | |
2744 | bitmap_print (file, &c->live_throughout, "live_throughout: ", ", "); | |
2745 | bitmap_print (file, &c->dead_or_set, "dead_or_set: ", "\n"); | |
2746 | } | |
2747 | ||
2748 | ||
2749 | /* Print all reload_insn_chains to FILE. */ | |
2750 | static void | |
2751 | print_insn_chains (FILE *file) | |
2752 | { | |
2753 | struct insn_chain *c; | |
2754 | for (c = reload_insn_chain; c ; c = c->next) | |
2755 | print_insn_chain (file, c); | |
2756 | } | |
2757 | ||
2758 | /* Return true if pseudo REGNO should be added to set live_throughout | |
2759 | or dead_or_set of the insn chains for reload consideration. */ | |
2760 | static bool | |
2761 | pseudo_for_reload_consideration_p (int regno) | |
2762 | { | |
2763 | /* Consider spilled pseudos too for IRA because they still have a | |
2764 | chance to get hard-registers in the reload when IRA is used. */ | |
2765 | return (reg_renumber[regno] >= 0 | |
2766 | || (ira_conflicts_p && flag_ira_share_spill_slots)); | |
2767 | } | |
2768 | ||
2769 | /* Init LIVE_SUBREGS[ALLOCNUM] and LIVE_SUBREGS_USED[ALLOCNUM] using | |
2770 | REG to the number of nregs, and INIT_VALUE to get the | |
2771 | initialization. ALLOCNUM need not be the regno of REG. */ | |
2772 | static void | |
2773 | init_live_subregs (bool init_value, sbitmap *live_subregs, | |
2774 | int *live_subregs_used, int allocnum, rtx reg) | |
2775 | { | |
2776 | unsigned int regno = REGNO (SUBREG_REG (reg)); | |
2777 | int size = GET_MODE_SIZE (GET_MODE (regno_reg_rtx[regno])); | |
2778 | ||
2779 | gcc_assert (size > 0); | |
2780 | ||
2781 | /* Been there, done that. */ | |
2782 | if (live_subregs_used[allocnum]) | |
2783 | return; | |
2784 | ||
2785 | /* Create a new one with zeros. */ | |
2786 | if (live_subregs[allocnum] == NULL) | |
2787 | live_subregs[allocnum] = sbitmap_alloc (size); | |
2788 | ||
2789 | /* If the entire reg was live before blasting into subregs, we need | |
2790 | to init all of the subregs to ones else init to 0. */ | |
2791 | if (init_value) | |
2792 | sbitmap_ones (live_subregs[allocnum]); | |
2793 | else | |
2794 | sbitmap_zero (live_subregs[allocnum]); | |
2795 | ||
2796 | /* Set the number of bits that we really want. */ | |
2797 | live_subregs_used[allocnum] = size; | |
2798 | } | |
2799 | ||
2800 | /* Walk the insns of the current function and build reload_insn_chain, | |
2801 | and record register life information. */ | |
2802 | static void | |
2803 | build_insn_chain (void) | |
2804 | { | |
2805 | unsigned int i; | |
2806 | struct insn_chain **p = &reload_insn_chain; | |
2807 | basic_block bb; | |
2808 | struct insn_chain *c = NULL; | |
2809 | struct insn_chain *next = NULL; | |
2810 | bitmap live_relevant_regs = BITMAP_ALLOC (NULL); | |
2811 | bitmap elim_regset = BITMAP_ALLOC (NULL); | |
2812 | /* live_subregs is a vector used to keep accurate information about | |
2813 | which hardregs are live in multiword pseudos. live_subregs and | |
2814 | live_subregs_used are indexed by pseudo number. The live_subreg | |
2815 | entry for a particular pseudo is only used if the corresponding | |
2816 | element is non zero in live_subregs_used. The value in | |
2817 | live_subregs_used is number of bytes that the pseudo can | |
2818 | occupy. */ | |
2819 | sbitmap *live_subregs = XCNEWVEC (sbitmap, max_regno); | |
2820 | int *live_subregs_used = XNEWVEC (int, max_regno); | |
2821 | ||
2822 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
2823 | if (TEST_HARD_REG_BIT (eliminable_regset, i)) | |
2824 | bitmap_set_bit (elim_regset, i); | |
2825 | FOR_EACH_BB_REVERSE (bb) | |
2826 | { | |
2827 | bitmap_iterator bi; | |
2828 | rtx insn; | |
2829 | ||
2830 | CLEAR_REG_SET (live_relevant_regs); | |
2831 | memset (live_subregs_used, 0, max_regno * sizeof (int)); | |
2832 | ||
54a0ac2d | 2833 | EXECUTE_IF_SET_IN_BITMAP (DF_LR_OUT (bb), 0, i, bi) |
2af2dbdc VM |
2834 | { |
2835 | if (i >= FIRST_PSEUDO_REGISTER) | |
2836 | break; | |
2837 | bitmap_set_bit (live_relevant_regs, i); | |
2838 | } | |
2839 | ||
54a0ac2d | 2840 | EXECUTE_IF_SET_IN_BITMAP (DF_LR_OUT (bb), |
2af2dbdc VM |
2841 | FIRST_PSEUDO_REGISTER, i, bi) |
2842 | { | |
2843 | if (pseudo_for_reload_consideration_p (i)) | |
2844 | bitmap_set_bit (live_relevant_regs, i); | |
2845 | } | |
2846 | ||
2847 | FOR_BB_INSNS_REVERSE (bb, insn) | |
2848 | { | |
2849 | if (!NOTE_P (insn) && !BARRIER_P (insn)) | |
2850 | { | |
2851 | unsigned int uid = INSN_UID (insn); | |
2852 | df_ref *def_rec; | |
2853 | df_ref *use_rec; | |
2854 | ||
2855 | c = new_insn_chain (); | |
2856 | c->next = next; | |
2857 | next = c; | |
2858 | *p = c; | |
2859 | p = &c->prev; | |
2860 | ||
2861 | c->insn = insn; | |
2862 | c->block = bb->index; | |
2863 | ||
2864 | if (INSN_P (insn)) | |
2865 | for (def_rec = DF_INSN_UID_DEFS (uid); *def_rec; def_rec++) | |
2866 | { | |
2867 | df_ref def = *def_rec; | |
2868 | unsigned int regno = DF_REF_REGNO (def); | |
2869 | ||
2870 | /* Ignore may clobbers because these are generated | |
2871 | from calls. However, every other kind of def is | |
2872 | added to dead_or_set. */ | |
2873 | if (!DF_REF_FLAGS_IS_SET (def, DF_REF_MAY_CLOBBER)) | |
2874 | { | |
2875 | if (regno < FIRST_PSEUDO_REGISTER) | |
2876 | { | |
2877 | if (!fixed_regs[regno]) | |
2878 | bitmap_set_bit (&c->dead_or_set, regno); | |
2879 | } | |
2880 | else if (pseudo_for_reload_consideration_p (regno)) | |
2881 | bitmap_set_bit (&c->dead_or_set, regno); | |
2882 | } | |
2883 | ||
2884 | if ((regno < FIRST_PSEUDO_REGISTER | |
2885 | || reg_renumber[regno] >= 0 | |
2886 | || ira_conflicts_p) | |
2887 | && (!DF_REF_FLAGS_IS_SET (def, DF_REF_CONDITIONAL))) | |
2888 | { | |
2889 | rtx reg = DF_REF_REG (def); | |
2890 | ||
2891 | /* We can model subregs, but not if they are | |
2892 | wrapped in ZERO_EXTRACTS. */ | |
2893 | if (GET_CODE (reg) == SUBREG | |
2894 | && !DF_REF_FLAGS_IS_SET (def, DF_REF_ZERO_EXTRACT)) | |
2895 | { | |
2896 | unsigned int start = SUBREG_BYTE (reg); | |
2897 | unsigned int last = start | |
2898 | + GET_MODE_SIZE (GET_MODE (reg)); | |
2899 | ||
2900 | init_live_subregs | |
2901 | (bitmap_bit_p (live_relevant_regs, regno), | |
2902 | live_subregs, live_subregs_used, regno, reg); | |
2903 | ||
2904 | if (!DF_REF_FLAGS_IS_SET | |
2905 | (def, DF_REF_STRICT_LOW_PART)) | |
2906 | { | |
2907 | /* Expand the range to cover entire words. | |
2908 | Bytes added here are "don't care". */ | |
2909 | start | |
2910 | = start / UNITS_PER_WORD * UNITS_PER_WORD; | |
2911 | last = ((last + UNITS_PER_WORD - 1) | |
2912 | / UNITS_PER_WORD * UNITS_PER_WORD); | |
2913 | } | |
2914 | ||
2915 | /* Ignore the paradoxical bits. */ | |
2916 | if ((int)last > live_subregs_used[regno]) | |
2917 | last = live_subregs_used[regno]; | |
2918 | ||
2919 | while (start < last) | |
2920 | { | |
2921 | RESET_BIT (live_subregs[regno], start); | |
2922 | start++; | |
2923 | } | |
2924 | ||
2925 | if (sbitmap_empty_p (live_subregs[regno])) | |
2926 | { | |
2927 | live_subregs_used[regno] = 0; | |
2928 | bitmap_clear_bit (live_relevant_regs, regno); | |
2929 | } | |
2930 | else | |
2931 | /* Set live_relevant_regs here because | |
2932 | that bit has to be true to get us to | |
2933 | look at the live_subregs fields. */ | |
2934 | bitmap_set_bit (live_relevant_regs, regno); | |
2935 | } | |
2936 | else | |
2937 | { | |
2938 | /* DF_REF_PARTIAL is generated for | |
2939 | subregs, STRICT_LOW_PART, and | |
2940 | ZERO_EXTRACT. We handle the subreg | |
2941 | case above so here we have to keep from | |
2942 | modeling the def as a killing def. */ | |
2943 | if (!DF_REF_FLAGS_IS_SET (def, DF_REF_PARTIAL)) | |
2944 | { | |
2945 | bitmap_clear_bit (live_relevant_regs, regno); | |
2946 | live_subregs_used[regno] = 0; | |
2947 | } | |
2948 | } | |
2949 | } | |
2950 | } | |
2951 | ||
2952 | bitmap_and_compl_into (live_relevant_regs, elim_regset); | |
2953 | bitmap_copy (&c->live_throughout, live_relevant_regs); | |
2954 | ||
2955 | if (INSN_P (insn)) | |
2956 | for (use_rec = DF_INSN_UID_USES (uid); *use_rec; use_rec++) | |
2957 | { | |
2958 | df_ref use = *use_rec; | |
2959 | unsigned int regno = DF_REF_REGNO (use); | |
2960 | rtx reg = DF_REF_REG (use); | |
2961 | ||
2962 | /* DF_REF_READ_WRITE on a use means that this use | |
2963 | is fabricated from a def that is a partial set | |
2964 | to a multiword reg. Here, we only model the | |
2965 | subreg case that is not wrapped in ZERO_EXTRACT | |
2966 | precisely so we do not need to look at the | |
2967 | fabricated use. */ | |
2968 | if (DF_REF_FLAGS_IS_SET (use, DF_REF_READ_WRITE) | |
2969 | && !DF_REF_FLAGS_IS_SET (use, DF_REF_ZERO_EXTRACT) | |
2970 | && DF_REF_FLAGS_IS_SET (use, DF_REF_SUBREG)) | |
2971 | continue; | |
2972 | ||
2973 | /* Add the last use of each var to dead_or_set. */ | |
2974 | if (!bitmap_bit_p (live_relevant_regs, regno)) | |
2975 | { | |
2976 | if (regno < FIRST_PSEUDO_REGISTER) | |
2977 | { | |
2978 | if (!fixed_regs[regno]) | |
2979 | bitmap_set_bit (&c->dead_or_set, regno); | |
2980 | } | |
2981 | else if (pseudo_for_reload_consideration_p (regno)) | |
2982 | bitmap_set_bit (&c->dead_or_set, regno); | |
2983 | } | |
2984 | ||
2985 | if (regno < FIRST_PSEUDO_REGISTER | |
2986 | || pseudo_for_reload_consideration_p (regno)) | |
2987 | { | |
2988 | if (GET_CODE (reg) == SUBREG | |
2989 | && !DF_REF_FLAGS_IS_SET (use, | |
2990 | DF_REF_SIGN_EXTRACT | |
2991 | | DF_REF_ZERO_EXTRACT)) | |
2992 | { | |
2993 | unsigned int start = SUBREG_BYTE (reg); | |
2994 | unsigned int last = start | |
2995 | + GET_MODE_SIZE (GET_MODE (reg)); | |
2996 | ||
2997 | init_live_subregs | |
2998 | (bitmap_bit_p (live_relevant_regs, regno), | |
2999 | live_subregs, live_subregs_used, regno, reg); | |
3000 | ||
3001 | /* Ignore the paradoxical bits. */ | |
3002 | if ((int)last > live_subregs_used[regno]) | |
3003 | last = live_subregs_used[regno]; | |
3004 | ||
3005 | while (start < last) | |
3006 | { | |
3007 | SET_BIT (live_subregs[regno], start); | |
3008 | start++; | |
3009 | } | |
3010 | } | |
3011 | else | |
3012 | /* Resetting the live_subregs_used is | |
3013 | effectively saying do not use the subregs | |
3014 | because we are reading the whole | |
3015 | pseudo. */ | |
3016 | live_subregs_used[regno] = 0; | |
3017 | bitmap_set_bit (live_relevant_regs, regno); | |
3018 | } | |
3019 | } | |
3020 | } | |
3021 | } | |
3022 | ||
3023 | /* FIXME!! The following code is a disaster. Reload needs to see the | |
3024 | labels and jump tables that are just hanging out in between | |
3025 | the basic blocks. See pr33676. */ | |
3026 | insn = BB_HEAD (bb); | |
3027 | ||
3028 | /* Skip over the barriers and cruft. */ | |
3029 | while (insn && (BARRIER_P (insn) || NOTE_P (insn) | |
3030 | || BLOCK_FOR_INSN (insn) == bb)) | |
3031 | insn = PREV_INSN (insn); | |
3032 | ||
3033 | /* While we add anything except barriers and notes, the focus is | |
3034 | to get the labels and jump tables into the | |
3035 | reload_insn_chain. */ | |
3036 | while (insn) | |
3037 | { | |
3038 | if (!NOTE_P (insn) && !BARRIER_P (insn)) | |
3039 | { | |
3040 | if (BLOCK_FOR_INSN (insn)) | |
3041 | break; | |
3042 | ||
3043 | c = new_insn_chain (); | |
3044 | c->next = next; | |
3045 | next = c; | |
3046 | *p = c; | |
3047 | p = &c->prev; | |
3048 | ||
3049 | /* The block makes no sense here, but it is what the old | |
3050 | code did. */ | |
3051 | c->block = bb->index; | |
3052 | c->insn = insn; | |
3053 | bitmap_copy (&c->live_throughout, live_relevant_regs); | |
3054 | } | |
3055 | insn = PREV_INSN (insn); | |
3056 | } | |
3057 | } | |
3058 | ||
3059 | for (i = 0; i < (unsigned int) max_regno; i++) | |
3060 | if (live_subregs[i]) | |
3061 | free (live_subregs[i]); | |
3062 | ||
3063 | reload_insn_chain = c; | |
3064 | *p = NULL; | |
3065 | ||
3066 | free (live_subregs); | |
3067 | free (live_subregs_used); | |
3068 | BITMAP_FREE (live_relevant_regs); | |
3069 | BITMAP_FREE (elim_regset); | |
3070 | ||
3071 | if (dump_file) | |
3072 | print_insn_chains (dump_file); | |
3073 | } | |
3074 | ||
3075 | \f | |
3076 | ||
058e97ec VM |
3077 | /* All natural loops. */ |
3078 | struct loops ira_loops; | |
3079 | ||
311aab06 VM |
3080 | /* True if we have allocno conflicts. It is false for non-optimized |
3081 | mode or when the conflict table is too big. */ | |
3082 | bool ira_conflicts_p; | |
3083 | ||
058e97ec VM |
3084 | /* This is the main entry of IRA. */ |
3085 | static void | |
3086 | ira (FILE *f) | |
3087 | { | |
3088 | int overall_cost_before, allocated_reg_info_size; | |
3089 | bool loops_p; | |
3090 | int max_regno_before_ira, ira_max_point_before_emit; | |
3091 | int rebuild_p; | |
3553f0bb | 3092 | int saved_flag_ira_share_spill_slots; |
058e97ec VM |
3093 | basic_block bb; |
3094 | ||
3095 | timevar_push (TV_IRA); | |
3096 | ||
3097 | if (flag_ira_verbose < 10) | |
3098 | { | |
3099 | internal_flag_ira_verbose = flag_ira_verbose; | |
3100 | ira_dump_file = f; | |
3101 | } | |
3102 | else | |
3103 | { | |
3104 | internal_flag_ira_verbose = flag_ira_verbose - 10; | |
3105 | ira_dump_file = stderr; | |
3106 | } | |
3107 | ||
311aab06 | 3108 | ira_conflicts_p = optimize > 0; |
058e97ec VM |
3109 | setup_prohibited_mode_move_regs (); |
3110 | ||
3111 | df_note_add_problem (); | |
3112 | ||
3113 | if (optimize == 1) | |
3114 | { | |
3115 | df_live_add_problem (); | |
3116 | df_live_set_all_dirty (); | |
3117 | } | |
3118 | #ifdef ENABLE_CHECKING | |
3119 | df->changeable_flags |= DF_VERIFY_SCHEDULED; | |
3120 | #endif | |
3121 | df_analyze (); | |
3122 | df_clear_flags (DF_NO_INSN_RESCAN); | |
3123 | regstat_init_n_sets_and_refs (); | |
3124 | regstat_compute_ri (); | |
3125 | ||
3126 | /* If we are not optimizing, then this is the only place before | |
3127 | register allocation where dataflow is done. And that is needed | |
3128 | to generate these warnings. */ | |
3129 | if (warn_clobbered) | |
3130 | generate_setjmp_warnings (); | |
3131 | ||
ace984c8 RS |
3132 | /* Determine if the current function is a leaf before running IRA |
3133 | since this can impact optimizations done by the prologue and | |
3134 | epilogue thus changing register elimination offsets. */ | |
3135 | current_function_is_leaf = leaf_function_p (); | |
3136 | ||
058e97ec VM |
3137 | rebuild_p = update_equiv_regs (); |
3138 | ||
3139 | #ifndef IRA_NO_OBSTACK | |
3140 | gcc_obstack_init (&ira_obstack); | |
3141 | #endif | |
3142 | bitmap_obstack_initialize (&ira_bitmap_obstack); | |
3143 | if (optimize) | |
3144 | { | |
3145 | max_regno = max_reg_num (); | |
3146 | ira_reg_equiv_len = max_regno; | |
3147 | ira_reg_equiv_invariant_p | |
3148 | = (bool *) ira_allocate (max_regno * sizeof (bool)); | |
3149 | memset (ira_reg_equiv_invariant_p, 0, max_regno * sizeof (bool)); | |
3150 | ira_reg_equiv_const = (rtx *) ira_allocate (max_regno * sizeof (rtx)); | |
3151 | memset (ira_reg_equiv_const, 0, max_regno * sizeof (rtx)); | |
3152 | find_reg_equiv_invariant_const (); | |
3153 | if (rebuild_p) | |
3154 | { | |
3155 | timevar_push (TV_JUMP); | |
3156 | rebuild_jump_labels (get_insns ()); | |
3157 | purge_all_dead_edges (); | |
3158 | timevar_pop (TV_JUMP); | |
3159 | } | |
3160 | } | |
3161 | ||
3162 | max_regno_before_ira = allocated_reg_info_size = max_reg_num (); | |
3163 | allocate_reg_info (); | |
3164 | setup_eliminable_regset (); | |
3165 | ||
3166 | ira_overall_cost = ira_reg_cost = ira_mem_cost = 0; | |
3167 | ira_load_cost = ira_store_cost = ira_shuffle_cost = 0; | |
3168 | ira_move_loops_num = ira_additional_jumps_num = 0; | |
3169 | ||
3170 | ira_assert (current_loops == NULL); | |
3171 | flow_loops_find (&ira_loops); | |
3172 | current_loops = &ira_loops; | |
058e97ec VM |
3173 | |
3174 | if (internal_flag_ira_verbose > 0 && ira_dump_file != NULL) | |
3175 | fprintf (ira_dump_file, "Building IRA IR\n"); | |
3176 | loops_p = ira_build (optimize | |
7db7ed3c VM |
3177 | && (flag_ira_region == IRA_REGION_ALL |
3178 | || flag_ira_region == IRA_REGION_MIXED)); | |
311aab06 VM |
3179 | |
3180 | ira_assert (ira_conflicts_p || !loops_p); | |
3553f0bb VM |
3181 | |
3182 | saved_flag_ira_share_spill_slots = flag_ira_share_spill_slots; | |
3183 | if (too_high_register_pressure_p ()) | |
3184 | /* It is just wasting compiler's time to pack spilled pseudos into | |
3185 | stack slots in this case -- prohibit it. */ | |
3186 | flag_ira_share_spill_slots = FALSE; | |
3187 | ||
cb1ca6ac | 3188 | ira_color (); |
058e97ec VM |
3189 | |
3190 | ira_max_point_before_emit = ira_max_point; | |
3191 | ||
3192 | ira_emit (loops_p); | |
3193 | ||
311aab06 | 3194 | if (ira_conflicts_p) |
058e97ec VM |
3195 | { |
3196 | max_regno = max_reg_num (); | |
3197 | ||
3198 | if (! loops_p) | |
3199 | ira_initiate_assign (); | |
3200 | else | |
3201 | { | |
3202 | expand_reg_info (allocated_reg_info_size); | |
3203 | setup_preferred_alternate_classes_for_new_pseudos | |
3204 | (allocated_reg_info_size); | |
3205 | allocated_reg_info_size = max_regno; | |
3206 | ||
3207 | if (internal_flag_ira_verbose > 0 && ira_dump_file != NULL) | |
3208 | fprintf (ira_dump_file, "Flattening IR\n"); | |
3209 | ira_flattening (max_regno_before_ira, ira_max_point_before_emit); | |
3210 | /* New insns were generated: add notes and recalculate live | |
3211 | info. */ | |
3212 | df_analyze (); | |
3213 | ||
3214 | flow_loops_find (&ira_loops); | |
3215 | current_loops = &ira_loops; | |
3216 | ||
3217 | setup_allocno_assignment_flags (); | |
3218 | ira_initiate_assign (); | |
3219 | ira_reassign_conflict_allocnos (max_regno); | |
3220 | } | |
3221 | } | |
3222 | ||
3223 | setup_reg_renumber (); | |
3224 | ||
3225 | calculate_allocation_cost (); | |
3226 | ||
3227 | #ifdef ENABLE_IRA_CHECKING | |
311aab06 | 3228 | if (ira_conflicts_p) |
058e97ec VM |
3229 | check_allocation (); |
3230 | #endif | |
3231 | ||
3232 | delete_trivially_dead_insns (get_insns (), max_reg_num ()); | |
3233 | max_regno = max_reg_num (); | |
3234 | ||
058e97ec VM |
3235 | /* And the reg_equiv_memory_loc array. */ |
3236 | VEC_safe_grow (rtx, gc, reg_equiv_memory_loc_vec, max_regno); | |
3237 | memset (VEC_address (rtx, reg_equiv_memory_loc_vec), 0, | |
3238 | sizeof (rtx) * max_regno); | |
3239 | reg_equiv_memory_loc = VEC_address (rtx, reg_equiv_memory_loc_vec); | |
3240 | ||
3241 | if (max_regno != max_regno_before_ira) | |
3242 | { | |
3243 | regstat_free_n_sets_and_refs (); | |
3244 | regstat_free_ri (); | |
3245 | regstat_init_n_sets_and_refs (); | |
3246 | regstat_compute_ri (); | |
3247 | } | |
3248 | ||
3249 | allocate_initial_values (reg_equiv_memory_loc); | |
3250 | ||
3251 | overall_cost_before = ira_overall_cost; | |
311aab06 | 3252 | if (ira_conflicts_p) |
058e97ec VM |
3253 | { |
3254 | fix_reg_equiv_init (); | |
3255 | ||
3256 | #ifdef ENABLE_IRA_CHECKING | |
3257 | print_redundant_copies (); | |
3258 | #endif | |
3259 | ||
3260 | ira_spilled_reg_stack_slots_num = 0; | |
3261 | ira_spilled_reg_stack_slots | |
3262 | = ((struct ira_spilled_reg_stack_slot *) | |
3263 | ira_allocate (max_regno | |
3264 | * sizeof (struct ira_spilled_reg_stack_slot))); | |
3265 | memset (ira_spilled_reg_stack_slots, 0, | |
3266 | max_regno * sizeof (struct ira_spilled_reg_stack_slot)); | |
3267 | } | |
3268 | ||
3269 | timevar_pop (TV_IRA); | |
3270 | ||
3271 | timevar_push (TV_RELOAD); | |
3272 | df_set_flags (DF_NO_INSN_RESCAN); | |
3273 | build_insn_chain (); | |
3274 | ||
311aab06 | 3275 | reload_completed = !reload (get_insns (), ira_conflicts_p); |
058e97ec VM |
3276 | |
3277 | timevar_pop (TV_RELOAD); | |
3278 | ||
3279 | timevar_push (TV_IRA); | |
3280 | ||
311aab06 | 3281 | if (ira_conflicts_p) |
058e97ec VM |
3282 | { |
3283 | ira_free (ira_spilled_reg_stack_slots); | |
3284 | ||
3285 | ira_finish_assign (); | |
3286 | ||
3287 | } | |
3288 | if (internal_flag_ira_verbose > 0 && ira_dump_file != NULL | |
3289 | && overall_cost_before != ira_overall_cost) | |
3290 | fprintf (ira_dump_file, "+++Overall after reload %d\n", ira_overall_cost); | |
3291 | ira_destroy (); | |
3292 | ||
3553f0bb VM |
3293 | flag_ira_share_spill_slots = saved_flag_ira_share_spill_slots; |
3294 | ||
058e97ec VM |
3295 | flow_loops_free (&ira_loops); |
3296 | free_dominance_info (CDI_DOMINATORS); | |
3297 | FOR_ALL_BB (bb) | |
3298 | bb->loop_father = NULL; | |
3299 | current_loops = NULL; | |
3300 | ||
058e97ec VM |
3301 | regstat_free_ri (); |
3302 | regstat_free_n_sets_and_refs (); | |
3303 | ||
3304 | if (optimize) | |
3305 | { | |
3306 | cleanup_cfg (CLEANUP_EXPENSIVE); | |
3307 | ||
3308 | ira_free (ira_reg_equiv_invariant_p); | |
3309 | ira_free (ira_reg_equiv_const); | |
3310 | } | |
3311 | ||
3312 | bitmap_obstack_release (&ira_bitmap_obstack); | |
3313 | #ifndef IRA_NO_OBSTACK | |
3314 | obstack_free (&ira_obstack, NULL); | |
3315 | #endif | |
3316 | ||
3317 | /* The code after the reload has changed so much that at this point | |
3318 | we might as well just rescan everything. Not that | |
3319 | df_rescan_all_insns is not going to help here because it does not | |
3320 | touch the artificial uses and defs. */ | |
3321 | df_finish_pass (true); | |
3322 | if (optimize > 1) | |
3323 | df_live_add_problem (); | |
3324 | df_scan_alloc (NULL); | |
3325 | df_scan_blocks (); | |
3326 | ||
3327 | if (optimize) | |
3328 | df_analyze (); | |
3329 | ||
3330 | timevar_pop (TV_IRA); | |
3331 | } | |
3332 | ||
3333 | \f | |
3334 | ||
3335 | static bool | |
3336 | gate_ira (void) | |
3337 | { | |
2af2dbdc | 3338 | return true; |
058e97ec VM |
3339 | } |
3340 | ||
3341 | /* Run the integrated register allocator. */ | |
3342 | static unsigned int | |
3343 | rest_of_handle_ira (void) | |
3344 | { | |
3345 | ira (dump_file); | |
3346 | return 0; | |
3347 | } | |
3348 | ||
3349 | struct rtl_opt_pass pass_ira = | |
3350 | { | |
3351 | { | |
3352 | RTL_PASS, | |
3353 | "ira", /* name */ | |
3354 | gate_ira, /* gate */ | |
3355 | rest_of_handle_ira, /* execute */ | |
3356 | NULL, /* sub */ | |
3357 | NULL, /* next */ | |
3358 | 0, /* static_pass_number */ | |
7072a650 | 3359 | TV_NONE, /* tv_id */ |
058e97ec VM |
3360 | 0, /* properties_required */ |
3361 | 0, /* properties_provided */ | |
3362 | 0, /* properties_destroyed */ | |
3363 | 0, /* todo_flags_start */ | |
3364 | TODO_dump_func | | |
3365 | TODO_ggc_collect /* todo_flags_finish */ | |
3366 | } | |
3367 | }; |