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058e97ec | 1 | /* Integrated Register Allocator (IRA) entry point. |
2805e6c0 | 2 | Copyright (C) 2006, 2007, 2008, 2009, 2010, 2011, 2012 |
058e97ec VM |
3 | Free Software Foundation, Inc. |
4 | Contributed by Vladimir Makarov <vmakarov@redhat.com>. | |
5 | ||
6 | This file is part of GCC. | |
7 | ||
8 | GCC is free software; you can redistribute it and/or modify it under | |
9 | the terms of the GNU General Public License as published by the Free | |
10 | Software Foundation; either version 3, or (at your option) any later | |
11 | version. | |
12 | ||
13 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
14 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GCC; see the file COPYING3. If not see | |
20 | <http://www.gnu.org/licenses/>. */ | |
21 | ||
22 | /* The integrated register allocator (IRA) is a | |
23 | regional register allocator performing graph coloring on a top-down | |
24 | traversal of nested regions. Graph coloring in a region is based | |
25 | on Chaitin-Briggs algorithm. It is called integrated because | |
26 | register coalescing, register live range splitting, and choosing a | |
27 | better hard register are done on-the-fly during coloring. Register | |
28 | coalescing and choosing a cheaper hard register is done by hard | |
29 | register preferencing during hard register assigning. The live | |
30 | range splitting is a byproduct of the regional register allocation. | |
31 | ||
32 | Major IRA notions are: | |
33 | ||
34 | o *Region* is a part of CFG where graph coloring based on | |
35 | Chaitin-Briggs algorithm is done. IRA can work on any set of | |
36 | nested CFG regions forming a tree. Currently the regions are | |
37 | the entire function for the root region and natural loops for | |
38 | the other regions. Therefore data structure representing a | |
39 | region is called loop_tree_node. | |
40 | ||
1756cb66 VM |
41 | o *Allocno class* is a register class used for allocation of |
42 | given allocno. It means that only hard register of given | |
43 | register class can be assigned to given allocno. In reality, | |
44 | even smaller subset of (*profitable*) hard registers can be | |
45 | assigned. In rare cases, the subset can be even smaller | |
46 | because our modification of Chaitin-Briggs algorithm requires | |
47 | that sets of hard registers can be assigned to allocnos forms a | |
48 | forest, i.e. the sets can be ordered in a way where any | |
49 | previous set is not intersected with given set or is a superset | |
50 | of given set. | |
51 | ||
52 | o *Pressure class* is a register class belonging to a set of | |
53 | register classes containing all of the hard-registers available | |
54 | for register allocation. The set of all pressure classes for a | |
55 | target is defined in the corresponding machine-description file | |
56 | according some criteria. Register pressure is calculated only | |
57 | for pressure classes and it affects some IRA decisions as | |
58 | forming allocation regions. | |
058e97ec VM |
59 | |
60 | o *Allocno* represents the live range of a pseudo-register in a | |
61 | region. Besides the obvious attributes like the corresponding | |
1756cb66 | 62 | pseudo-register number, allocno class, conflicting allocnos and |
058e97ec VM |
63 | conflicting hard-registers, there are a few allocno attributes |
64 | which are important for understanding the allocation algorithm: | |
65 | ||
1756cb66 VM |
66 | - *Live ranges*. This is a list of ranges of *program points* |
67 | where the allocno lives. Program points represent places | |
68 | where a pseudo can be born or become dead (there are | |
058e97ec VM |
69 | approximately two times more program points than the insns) |
70 | and they are represented by integers starting with 0. The | |
1756cb66 VM |
71 | live ranges are used to find conflicts between allocnos. |
72 | They also play very important role for the transformation of | |
73 | the IRA internal representation of several regions into a one | |
74 | region representation. The later is used during the reload | |
75 | pass work because each allocno represents all of the | |
76 | corresponding pseudo-registers. | |
058e97ec VM |
77 | |
78 | - *Hard-register costs*. This is a vector of size equal to the | |
1756cb66 VM |
79 | number of available hard-registers of the allocno class. The |
80 | cost of a callee-clobbered hard-register for an allocno is | |
81 | increased by the cost of save/restore code around the calls | |
82 | through the given allocno's life. If the allocno is a move | |
83 | instruction operand and another operand is a hard-register of | |
84 | the allocno class, the cost of the hard-register is decreased | |
85 | by the move cost. | |
058e97ec VM |
86 | |
87 | When an allocno is assigned, the hard-register with minimal | |
88 | full cost is used. Initially, a hard-register's full cost is | |
89 | the corresponding value from the hard-register's cost vector. | |
90 | If the allocno is connected by a *copy* (see below) to | |
91 | another allocno which has just received a hard-register, the | |
92 | cost of the hard-register is decreased. Before choosing a | |
93 | hard-register for an allocno, the allocno's current costs of | |
94 | the hard-registers are modified by the conflict hard-register | |
95 | costs of all of the conflicting allocnos which are not | |
96 | assigned yet. | |
97 | ||
98 | - *Conflict hard-register costs*. This is a vector of the same | |
99 | size as the hard-register costs vector. To permit an | |
100 | unassigned allocno to get a better hard-register, IRA uses | |
101 | this vector to calculate the final full cost of the | |
102 | available hard-registers. Conflict hard-register costs of an | |
103 | unassigned allocno are also changed with a change of the | |
104 | hard-register cost of the allocno when a copy involving the | |
105 | allocno is processed as described above. This is done to | |
106 | show other unassigned allocnos that a given allocno prefers | |
107 | some hard-registers in order to remove the move instruction | |
108 | corresponding to the copy. | |
109 | ||
110 | o *Cap*. If a pseudo-register does not live in a region but | |
111 | lives in a nested region, IRA creates a special allocno called | |
112 | a cap in the outer region. A region cap is also created for a | |
113 | subregion cap. | |
114 | ||
115 | o *Copy*. Allocnos can be connected by copies. Copies are used | |
116 | to modify hard-register costs for allocnos during coloring. | |
117 | Such modifications reflects a preference to use the same | |
118 | hard-register for the allocnos connected by copies. Usually | |
119 | copies are created for move insns (in this case it results in | |
120 | register coalescing). But IRA also creates copies for operands | |
121 | of an insn which should be assigned to the same hard-register | |
122 | due to constraints in the machine description (it usually | |
123 | results in removing a move generated in reload to satisfy | |
124 | the constraints) and copies referring to the allocno which is | |
125 | the output operand of an instruction and the allocno which is | |
126 | an input operand dying in the instruction (creation of such | |
127 | copies results in less register shuffling). IRA *does not* | |
128 | create copies between the same register allocnos from different | |
129 | regions because we use another technique for propagating | |
130 | hard-register preference on the borders of regions. | |
131 | ||
132 | Allocnos (including caps) for the upper region in the region tree | |
133 | *accumulate* information important for coloring from allocnos with | |
134 | the same pseudo-register from nested regions. This includes | |
135 | hard-register and memory costs, conflicts with hard-registers, | |
136 | allocno conflicts, allocno copies and more. *Thus, attributes for | |
137 | allocnos in a region have the same values as if the region had no | |
138 | subregions*. It means that attributes for allocnos in the | |
139 | outermost region corresponding to the function have the same values | |
140 | as though the allocation used only one region which is the entire | |
141 | function. It also means that we can look at IRA work as if the | |
142 | first IRA did allocation for all function then it improved the | |
143 | allocation for loops then their subloops and so on. | |
144 | ||
145 | IRA major passes are: | |
146 | ||
147 | o Building IRA internal representation which consists of the | |
148 | following subpasses: | |
149 | ||
150 | * First, IRA builds regions and creates allocnos (file | |
151 | ira-build.c) and initializes most of their attributes. | |
152 | ||
1756cb66 VM |
153 | * Then IRA finds an allocno class for each allocno and |
154 | calculates its initial (non-accumulated) cost of memory and | |
155 | each hard-register of its allocno class (file ira-cost.c). | |
058e97ec VM |
156 | |
157 | * IRA creates live ranges of each allocno, calulates register | |
1756cb66 | 158 | pressure for each pressure class in each region, sets up |
058e97ec VM |
159 | conflict hard registers for each allocno and info about calls |
160 | the allocno lives through (file ira-lives.c). | |
161 | ||
162 | * IRA removes low register pressure loops from the regions | |
163 | mostly to speed IRA up (file ira-build.c). | |
164 | ||
165 | * IRA propagates accumulated allocno info from lower region | |
166 | allocnos to corresponding upper region allocnos (file | |
167 | ira-build.c). | |
168 | ||
169 | * IRA creates all caps (file ira-build.c). | |
170 | ||
1756cb66 VM |
171 | * Having live-ranges of allocnos and their classes, IRA creates |
172 | conflicting allocnos for each allocno. Conflicting allocnos | |
173 | are stored as a bit vector or array of pointers to the | |
174 | conflicting allocnos whatever is more profitable (file | |
175 | ira-conflicts.c). At this point IRA creates allocno copies. | |
058e97ec VM |
176 | |
177 | o Coloring. Now IRA has all necessary info to start graph coloring | |
178 | process. It is done in each region on top-down traverse of the | |
179 | region tree (file ira-color.c). There are following subpasses: | |
b8698a0f | 180 | |
1756cb66 VM |
181 | * Finding profitable hard registers of corresponding allocno |
182 | class for each allocno. For example, only callee-saved hard | |
183 | registers are frequently profitable for allocnos living | |
184 | through colors. If the profitable hard register set of | |
185 | allocno does not form a tree based on subset relation, we use | |
186 | some approximation to form the tree. This approximation is | |
187 | used to figure out trivial colorability of allocnos. The | |
188 | approximation is a pretty rare case. | |
189 | ||
058e97ec VM |
190 | * Putting allocnos onto the coloring stack. IRA uses Briggs |
191 | optimistic coloring which is a major improvement over | |
192 | Chaitin's coloring. Therefore IRA does not spill allocnos at | |
193 | this point. There is some freedom in the order of putting | |
194 | allocnos on the stack which can affect the final result of | |
1756cb66 VM |
195 | the allocation. IRA uses some heuristics to improve the |
196 | order. | |
197 | ||
198 | We also use a modification of Chaitin-Briggs algorithm which | |
199 | works for intersected register classes of allocnos. To | |
200 | figure out trivial colorability of allocnos, the mentioned | |
201 | above tree of hard register sets is used. To get an idea how | |
202 | the algorithm works in i386 example, let us consider an | |
203 | allocno to which any general hard register can be assigned. | |
204 | If the allocno conflicts with eight allocnos to which only | |
205 | EAX register can be assigned, given allocno is still | |
206 | trivially colorable because all conflicting allocnos might be | |
207 | assigned only to EAX and all other general hard registers are | |
208 | still free. | |
209 | ||
210 | To get an idea of the used trivial colorability criterion, it | |
211 | is also useful to read article "Graph-Coloring Register | |
212 | Allocation for Irregular Architectures" by Michael D. Smith | |
213 | and Glen Holloway. Major difference between the article | |
214 | approach and approach used in IRA is that Smith's approach | |
215 | takes register classes only from machine description and IRA | |
216 | calculate register classes from intermediate code too | |
217 | (e.g. an explicit usage of hard registers in RTL code for | |
218 | parameter passing can result in creation of additional | |
219 | register classes which contain or exclude the hard | |
220 | registers). That makes IRA approach useful for improving | |
221 | coloring even for architectures with regular register files | |
222 | and in fact some benchmarking shows the improvement for | |
223 | regular class architectures is even bigger than for irregular | |
224 | ones. Another difference is that Smith's approach chooses | |
225 | intersection of classes of all insn operands in which a given | |
226 | pseudo occurs. IRA can use bigger classes if it is still | |
227 | more profitable than memory usage. | |
058e97ec VM |
228 | |
229 | * Popping the allocnos from the stack and assigning them hard | |
230 | registers. If IRA can not assign a hard register to an | |
231 | allocno and the allocno is coalesced, IRA undoes the | |
232 | coalescing and puts the uncoalesced allocnos onto the stack in | |
233 | the hope that some such allocnos will get a hard register | |
234 | separately. If IRA fails to assign hard register or memory | |
235 | is more profitable for it, IRA spills the allocno. IRA | |
236 | assigns the allocno the hard-register with minimal full | |
237 | allocation cost which reflects the cost of usage of the | |
238 | hard-register for the allocno and cost of usage of the | |
239 | hard-register for allocnos conflicting with given allocno. | |
240 | ||
1756cb66 VM |
241 | * Chaitin-Briggs coloring assigns as many pseudos as possible |
242 | to hard registers. After coloringh we try to improve | |
243 | allocation with cost point of view. We improve the | |
244 | allocation by spilling some allocnos and assigning the freed | |
245 | hard registers to other allocnos if it decreases the overall | |
246 | allocation cost. | |
247 | ||
058e97ec VM |
248 | * After allono assigning in the region, IRA modifies the hard |
249 | register and memory costs for the corresponding allocnos in | |
250 | the subregions to reflect the cost of possible loads, stores, | |
251 | or moves on the border of the region and its subregions. | |
252 | When default regional allocation algorithm is used | |
253 | (-fira-algorithm=mixed), IRA just propagates the assignment | |
254 | for allocnos if the register pressure in the region for the | |
1756cb66 VM |
255 | corresponding pressure class is less than number of available |
256 | hard registers for given pressure class. | |
058e97ec VM |
257 | |
258 | o Spill/restore code moving. When IRA performs an allocation | |
259 | by traversing regions in top-down order, it does not know what | |
260 | happens below in the region tree. Therefore, sometimes IRA | |
261 | misses opportunities to perform a better allocation. A simple | |
262 | optimization tries to improve allocation in a region having | |
263 | subregions and containing in another region. If the | |
264 | corresponding allocnos in the subregion are spilled, it spills | |
265 | the region allocno if it is profitable. The optimization | |
266 | implements a simple iterative algorithm performing profitable | |
267 | transformations while they are still possible. It is fast in | |
268 | practice, so there is no real need for a better time complexity | |
269 | algorithm. | |
270 | ||
1756cb66 VM |
271 | o Code change. After coloring, two allocnos representing the |
272 | same pseudo-register outside and inside a region respectively | |
273 | may be assigned to different locations (hard-registers or | |
274 | memory). In this case IRA creates and uses a new | |
275 | pseudo-register inside the region and adds code to move allocno | |
276 | values on the region's borders. This is done during top-down | |
277 | traversal of the regions (file ira-emit.c). In some | |
278 | complicated cases IRA can create a new allocno to move allocno | |
279 | values (e.g. when a swap of values stored in two hard-registers | |
280 | is needed). At this stage, the new allocno is marked as | |
281 | spilled. IRA still creates the pseudo-register and the moves | |
282 | on the region borders even when both allocnos were assigned to | |
283 | the same hard-register. If the reload pass spills a | |
284 | pseudo-register for some reason, the effect will be smaller | |
285 | because another allocno will still be in the hard-register. In | |
286 | most cases, this is better then spilling both allocnos. If | |
287 | reload does not change the allocation for the two | |
288 | pseudo-registers, the trivial move will be removed by | |
289 | post-reload optimizations. IRA does not generate moves for | |
058e97ec VM |
290 | allocnos assigned to the same hard register when the default |
291 | regional allocation algorithm is used and the register pressure | |
1756cb66 VM |
292 | in the region for the corresponding pressure class is less than |
293 | number of available hard registers for given pressure class. | |
058e97ec VM |
294 | IRA also does some optimizations to remove redundant stores and |
295 | to reduce code duplication on the region borders. | |
296 | ||
297 | o Flattening internal representation. After changing code, IRA | |
298 | transforms its internal representation for several regions into | |
299 | one region representation (file ira-build.c). This process is | |
300 | called IR flattening. Such process is more complicated than IR | |
301 | rebuilding would be, but is much faster. | |
302 | ||
303 | o After IR flattening, IRA tries to assign hard registers to all | |
304 | spilled allocnos. This is impelemented by a simple and fast | |
305 | priority coloring algorithm (see function | |
306 | ira_reassign_conflict_allocnos::ira-color.c). Here new allocnos | |
307 | created during the code change pass can be assigned to hard | |
308 | registers. | |
309 | ||
310 | o At the end IRA calls the reload pass. The reload pass | |
311 | communicates with IRA through several functions in file | |
312 | ira-color.c to improve its decisions in | |
313 | ||
314 | * sharing stack slots for the spilled pseudos based on IRA info | |
315 | about pseudo-register conflicts. | |
316 | ||
317 | * reassigning hard-registers to all spilled pseudos at the end | |
318 | of each reload iteration. | |
319 | ||
320 | * choosing a better hard-register to spill based on IRA info | |
321 | about pseudo-register live ranges and the register pressure | |
322 | in places where the pseudo-register lives. | |
323 | ||
324 | IRA uses a lot of data representing the target processors. These | |
325 | data are initilized in file ira.c. | |
326 | ||
327 | If function has no loops (or the loops are ignored when | |
328 | -fira-algorithm=CB is used), we have classic Chaitin-Briggs | |
329 | coloring (only instead of separate pass of coalescing, we use hard | |
330 | register preferencing). In such case, IRA works much faster | |
331 | because many things are not made (like IR flattening, the | |
332 | spill/restore optimization, and the code change). | |
333 | ||
334 | Literature is worth to read for better understanding the code: | |
335 | ||
336 | o Preston Briggs, Keith D. Cooper, Linda Torczon. Improvements to | |
337 | Graph Coloring Register Allocation. | |
338 | ||
339 | o David Callahan, Brian Koblenz. Register allocation via | |
340 | hierarchical graph coloring. | |
341 | ||
342 | o Keith Cooper, Anshuman Dasgupta, Jason Eckhardt. Revisiting Graph | |
343 | Coloring Register Allocation: A Study of the Chaitin-Briggs and | |
344 | Callahan-Koblenz Algorithms. | |
345 | ||
346 | o Guei-Yuan Lueh, Thomas Gross, and Ali-Reza Adl-Tabatabai. Global | |
347 | Register Allocation Based on Graph Fusion. | |
348 | ||
1756cb66 VM |
349 | o Michael D. Smith and Glenn Holloway. Graph-Coloring Register |
350 | Allocation for Irregular Architectures | |
351 | ||
058e97ec VM |
352 | o Vladimir Makarov. The Integrated Register Allocator for GCC. |
353 | ||
354 | o Vladimir Makarov. The top-down register allocator for irregular | |
355 | register file architectures. | |
356 | ||
357 | */ | |
358 | ||
359 | ||
360 | #include "config.h" | |
361 | #include "system.h" | |
362 | #include "coretypes.h" | |
363 | #include "tm.h" | |
364 | #include "regs.h" | |
365 | #include "rtl.h" | |
366 | #include "tm_p.h" | |
367 | #include "target.h" | |
368 | #include "flags.h" | |
369 | #include "obstack.h" | |
370 | #include "bitmap.h" | |
371 | #include "hard-reg-set.h" | |
372 | #include "basic-block.h" | |
7a8cba34 | 373 | #include "df.h" |
058e97ec VM |
374 | #include "expr.h" |
375 | #include "recog.h" | |
376 | #include "params.h" | |
377 | #include "timevar.h" | |
378 | #include "tree-pass.h" | |
379 | #include "output.h" | |
2af2dbdc | 380 | #include "except.h" |
058e97ec | 381 | #include "reload.h" |
718f9c0f | 382 | #include "diagnostic-core.h" |
6399c0ab | 383 | #include "function.h" |
058e97ec VM |
384 | #include "ggc.h" |
385 | #include "ira-int.h" | |
b0c11403 | 386 | #include "dce.h" |
acf41a74 | 387 | #include "dbgcnt.h" |
058e97ec | 388 | |
afcc66c4 RS |
389 | struct target_ira default_target_ira; |
390 | struct target_ira_int default_target_ira_int; | |
391 | #if SWITCHABLE_TARGET | |
392 | struct target_ira *this_target_ira = &default_target_ira; | |
393 | struct target_ira_int *this_target_ira_int = &default_target_ira_int; | |
394 | #endif | |
395 | ||
058e97ec VM |
396 | /* A modified value of flag `-fira-verbose' used internally. */ |
397 | int internal_flag_ira_verbose; | |
398 | ||
399 | /* Dump file of the allocator if it is not NULL. */ | |
400 | FILE *ira_dump_file; | |
401 | ||
058e97ec VM |
402 | /* The number of elements in the following array. */ |
403 | int ira_spilled_reg_stack_slots_num; | |
404 | ||
405 | /* The following array contains info about spilled pseudo-registers | |
406 | stack slots used in current function so far. */ | |
407 | struct ira_spilled_reg_stack_slot *ira_spilled_reg_stack_slots; | |
408 | ||
ae2b9cb6 BS |
409 | /* Correspondingly overall cost of the allocation, overall cost before |
410 | reload, cost of the allocnos assigned to hard-registers, cost of | |
411 | the allocnos assigned to memory, cost of loads, stores and register | |
412 | move insns generated for pseudo-register live range splitting (see | |
413 | ira-emit.c). */ | |
414 | int ira_overall_cost, overall_cost_before; | |
058e97ec VM |
415 | int ira_reg_cost, ira_mem_cost; |
416 | int ira_load_cost, ira_store_cost, ira_shuffle_cost; | |
417 | int ira_move_loops_num, ira_additional_jumps_num; | |
418 | ||
2af2dbdc VM |
419 | /* All registers that can be eliminated. */ |
420 | ||
421 | HARD_REG_SET eliminable_regset; | |
422 | ||
058e97ec VM |
423 | /* Temporary hard reg set used for a different calculation. */ |
424 | static HARD_REG_SET temp_hard_regset; | |
425 | ||
426 | \f | |
427 | ||
428 | /* The function sets up the map IRA_REG_MODE_HARD_REGSET. */ | |
429 | static void | |
430 | setup_reg_mode_hard_regset (void) | |
431 | { | |
432 | int i, m, hard_regno; | |
433 | ||
434 | for (m = 0; m < NUM_MACHINE_MODES; m++) | |
435 | for (hard_regno = 0; hard_regno < FIRST_PSEUDO_REGISTER; hard_regno++) | |
436 | { | |
437 | CLEAR_HARD_REG_SET (ira_reg_mode_hard_regset[hard_regno][m]); | |
438 | for (i = hard_regno_nregs[hard_regno][m] - 1; i >= 0; i--) | |
439 | if (hard_regno + i < FIRST_PSEUDO_REGISTER) | |
440 | SET_HARD_REG_BIT (ira_reg_mode_hard_regset[hard_regno][m], | |
441 | hard_regno + i); | |
442 | } | |
443 | } | |
444 | ||
445 | \f | |
afcc66c4 RS |
446 | #define no_unit_alloc_regs \ |
447 | (this_target_ira_int->x_no_unit_alloc_regs) | |
058e97ec VM |
448 | |
449 | /* The function sets up the three arrays declared above. */ | |
450 | static void | |
451 | setup_class_hard_regs (void) | |
452 | { | |
453 | int cl, i, hard_regno, n; | |
454 | HARD_REG_SET processed_hard_reg_set; | |
455 | ||
456 | ira_assert (SHRT_MAX >= FIRST_PSEUDO_REGISTER); | |
058e97ec VM |
457 | for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) |
458 | { | |
459 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); | |
460 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
461 | CLEAR_HARD_REG_SET (processed_hard_reg_set); | |
7db7ed3c | 462 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
0583835c | 463 | { |
854edfcd VM |
464 | ira_non_ordered_class_hard_regs[cl][i] = -1; |
465 | ira_class_hard_reg_index[cl][i] = -1; | |
0583835c | 466 | } |
058e97ec VM |
467 | for (n = 0, i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
468 | { | |
469 | #ifdef REG_ALLOC_ORDER | |
470 | hard_regno = reg_alloc_order[i]; | |
471 | #else | |
472 | hard_regno = i; | |
b8698a0f | 473 | #endif |
058e97ec VM |
474 | if (TEST_HARD_REG_BIT (processed_hard_reg_set, hard_regno)) |
475 | continue; | |
476 | SET_HARD_REG_BIT (processed_hard_reg_set, hard_regno); | |
477 | if (! TEST_HARD_REG_BIT (temp_hard_regset, hard_regno)) | |
478 | ira_class_hard_reg_index[cl][hard_regno] = -1; | |
479 | else | |
480 | { | |
481 | ira_class_hard_reg_index[cl][hard_regno] = n; | |
482 | ira_class_hard_regs[cl][n++] = hard_regno; | |
483 | } | |
484 | } | |
485 | ira_class_hard_regs_num[cl] = n; | |
0583835c VM |
486 | for (n = 0, i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
487 | if (TEST_HARD_REG_BIT (temp_hard_regset, i)) | |
488 | ira_non_ordered_class_hard_regs[cl][n++] = i; | |
489 | ira_assert (ira_class_hard_regs_num[cl] == n); | |
058e97ec VM |
490 | } |
491 | } | |
492 | ||
058e97ec VM |
493 | /* Set up global variables defining info about hard registers for the |
494 | allocation. These depend on USE_HARD_FRAME_P whose TRUE value means | |
495 | that we can use the hard frame pointer for the allocation. */ | |
496 | static void | |
497 | setup_alloc_regs (bool use_hard_frame_p) | |
498 | { | |
5a733826 BS |
499 | #ifdef ADJUST_REG_ALLOC_ORDER |
500 | ADJUST_REG_ALLOC_ORDER; | |
501 | #endif | |
058e97ec VM |
502 | COPY_HARD_REG_SET (no_unit_alloc_regs, fixed_reg_set); |
503 | if (! use_hard_frame_p) | |
504 | SET_HARD_REG_BIT (no_unit_alloc_regs, HARD_FRAME_POINTER_REGNUM); | |
505 | setup_class_hard_regs (); | |
058e97ec VM |
506 | } |
507 | ||
508 | \f | |
509 | ||
1756cb66 VM |
510 | #define alloc_reg_class_subclasses \ |
511 | (this_target_ira_int->x_alloc_reg_class_subclasses) | |
512 | ||
513 | /* Initialize the table of subclasses of each reg class. */ | |
514 | static void | |
515 | setup_reg_subclasses (void) | |
516 | { | |
517 | int i, j; | |
518 | HARD_REG_SET temp_hard_regset2; | |
519 | ||
520 | for (i = 0; i < N_REG_CLASSES; i++) | |
521 | for (j = 0; j < N_REG_CLASSES; j++) | |
522 | alloc_reg_class_subclasses[i][j] = LIM_REG_CLASSES; | |
523 | ||
524 | for (i = 0; i < N_REG_CLASSES; i++) | |
525 | { | |
526 | if (i == (int) NO_REGS) | |
527 | continue; | |
528 | ||
529 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[i]); | |
530 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
531 | if (hard_reg_set_empty_p (temp_hard_regset)) | |
532 | continue; | |
533 | for (j = 0; j < N_REG_CLASSES; j++) | |
534 | if (i != j) | |
535 | { | |
536 | enum reg_class *p; | |
537 | ||
538 | COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[j]); | |
539 | AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs); | |
540 | if (! hard_reg_set_subset_p (temp_hard_regset, | |
541 | temp_hard_regset2)) | |
542 | continue; | |
543 | p = &alloc_reg_class_subclasses[j][0]; | |
544 | while (*p != LIM_REG_CLASSES) p++; | |
545 | *p = (enum reg_class) i; | |
546 | } | |
547 | } | |
548 | } | |
549 | ||
550 | \f | |
551 | ||
552 | /* Set up IRA_MEMORY_MOVE_COST and IRA_MAX_MEMORY_MOVE_COST. */ | |
058e97ec VM |
553 | static void |
554 | setup_class_subset_and_memory_move_costs (void) | |
555 | { | |
1756cb66 | 556 | int cl, cl2, mode, cost; |
058e97ec VM |
557 | HARD_REG_SET temp_hard_regset2; |
558 | ||
559 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
560 | ira_memory_move_cost[mode][NO_REGS][0] | |
561 | = ira_memory_move_cost[mode][NO_REGS][1] = SHRT_MAX; | |
562 | for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) | |
563 | { | |
564 | if (cl != (int) NO_REGS) | |
565 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
566 | { | |
1756cb66 VM |
567 | ira_max_memory_move_cost[mode][cl][0] |
568 | = ira_memory_move_cost[mode][cl][0] | |
569 | = memory_move_cost ((enum machine_mode) mode, | |
6f76a878 | 570 | (reg_class_t) cl, false); |
1756cb66 VM |
571 | ira_max_memory_move_cost[mode][cl][1] |
572 | = ira_memory_move_cost[mode][cl][1] | |
573 | = memory_move_cost ((enum machine_mode) mode, | |
6f76a878 | 574 | (reg_class_t) cl, true); |
058e97ec VM |
575 | /* Costs for NO_REGS are used in cost calculation on the |
576 | 1st pass when the preferred register classes are not | |
577 | known yet. In this case we take the best scenario. */ | |
578 | if (ira_memory_move_cost[mode][NO_REGS][0] | |
579 | > ira_memory_move_cost[mode][cl][0]) | |
1756cb66 VM |
580 | ira_max_memory_move_cost[mode][NO_REGS][0] |
581 | = ira_memory_move_cost[mode][NO_REGS][0] | |
058e97ec VM |
582 | = ira_memory_move_cost[mode][cl][0]; |
583 | if (ira_memory_move_cost[mode][NO_REGS][1] | |
584 | > ira_memory_move_cost[mode][cl][1]) | |
1756cb66 VM |
585 | ira_max_memory_move_cost[mode][NO_REGS][1] |
586 | = ira_memory_move_cost[mode][NO_REGS][1] | |
058e97ec VM |
587 | = ira_memory_move_cost[mode][cl][1]; |
588 | } | |
058e97ec | 589 | } |
1756cb66 VM |
590 | for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) |
591 | for (cl2 = (int) N_REG_CLASSES - 1; cl2 >= 0; cl2--) | |
592 | { | |
593 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); | |
594 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
595 | COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl2]); | |
596 | AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs); | |
597 | ira_class_subset_p[cl][cl2] | |
598 | = hard_reg_set_subset_p (temp_hard_regset, temp_hard_regset2); | |
599 | if (! hard_reg_set_empty_p (temp_hard_regset2) | |
600 | && hard_reg_set_subset_p (reg_class_contents[cl2], | |
601 | reg_class_contents[cl])) | |
602 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
603 | { | |
604 | cost = ira_memory_move_cost[mode][cl2][0]; | |
605 | if (cost > ira_max_memory_move_cost[mode][cl][0]) | |
606 | ira_max_memory_move_cost[mode][cl][0] = cost; | |
607 | cost = ira_memory_move_cost[mode][cl2][1]; | |
608 | if (cost > ira_max_memory_move_cost[mode][cl][1]) | |
609 | ira_max_memory_move_cost[mode][cl][1] = cost; | |
610 | } | |
611 | } | |
612 | for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) | |
613 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
614 | { | |
615 | ira_memory_move_cost[mode][cl][0] | |
616 | = ira_max_memory_move_cost[mode][cl][0]; | |
617 | ira_memory_move_cost[mode][cl][1] | |
618 | = ira_max_memory_move_cost[mode][cl][1]; | |
619 | } | |
620 | setup_reg_subclasses (); | |
058e97ec VM |
621 | } |
622 | ||
623 | \f | |
624 | ||
625 | /* Define the following macro if allocation through malloc if | |
626 | preferable. */ | |
627 | #define IRA_NO_OBSTACK | |
628 | ||
629 | #ifndef IRA_NO_OBSTACK | |
630 | /* Obstack used for storing all dynamic data (except bitmaps) of the | |
631 | IRA. */ | |
632 | static struct obstack ira_obstack; | |
633 | #endif | |
634 | ||
635 | /* Obstack used for storing all bitmaps of the IRA. */ | |
636 | static struct bitmap_obstack ira_bitmap_obstack; | |
637 | ||
638 | /* Allocate memory of size LEN for IRA data. */ | |
639 | void * | |
640 | ira_allocate (size_t len) | |
641 | { | |
642 | void *res; | |
643 | ||
644 | #ifndef IRA_NO_OBSTACK | |
645 | res = obstack_alloc (&ira_obstack, len); | |
646 | #else | |
647 | res = xmalloc (len); | |
648 | #endif | |
649 | return res; | |
650 | } | |
651 | ||
058e97ec VM |
652 | /* Free memory ADDR allocated for IRA data. */ |
653 | void | |
654 | ira_free (void *addr ATTRIBUTE_UNUSED) | |
655 | { | |
656 | #ifndef IRA_NO_OBSTACK | |
657 | /* do nothing */ | |
658 | #else | |
659 | free (addr); | |
660 | #endif | |
661 | } | |
662 | ||
663 | ||
664 | /* Allocate and returns bitmap for IRA. */ | |
665 | bitmap | |
666 | ira_allocate_bitmap (void) | |
667 | { | |
668 | return BITMAP_ALLOC (&ira_bitmap_obstack); | |
669 | } | |
670 | ||
671 | /* Free bitmap B allocated for IRA. */ | |
672 | void | |
673 | ira_free_bitmap (bitmap b ATTRIBUTE_UNUSED) | |
674 | { | |
675 | /* do nothing */ | |
676 | } | |
677 | ||
678 | \f | |
679 | ||
680 | /* Output information about allocation of all allocnos (except for | |
681 | caps) into file F. */ | |
682 | void | |
683 | ira_print_disposition (FILE *f) | |
684 | { | |
685 | int i, n, max_regno; | |
686 | ira_allocno_t a; | |
687 | basic_block bb; | |
688 | ||
689 | fprintf (f, "Disposition:"); | |
690 | max_regno = max_reg_num (); | |
691 | for (n = 0, i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
692 | for (a = ira_regno_allocno_map[i]; | |
693 | a != NULL; | |
694 | a = ALLOCNO_NEXT_REGNO_ALLOCNO (a)) | |
695 | { | |
696 | if (n % 4 == 0) | |
697 | fprintf (f, "\n"); | |
698 | n++; | |
699 | fprintf (f, " %4d:r%-4d", ALLOCNO_NUM (a), ALLOCNO_REGNO (a)); | |
700 | if ((bb = ALLOCNO_LOOP_TREE_NODE (a)->bb) != NULL) | |
701 | fprintf (f, "b%-3d", bb->index); | |
702 | else | |
2608d841 | 703 | fprintf (f, "l%-3d", ALLOCNO_LOOP_TREE_NODE (a)->loop_num); |
058e97ec VM |
704 | if (ALLOCNO_HARD_REGNO (a) >= 0) |
705 | fprintf (f, " %3d", ALLOCNO_HARD_REGNO (a)); | |
706 | else | |
707 | fprintf (f, " mem"); | |
708 | } | |
709 | fprintf (f, "\n"); | |
710 | } | |
711 | ||
712 | /* Outputs information about allocation of all allocnos into | |
713 | stderr. */ | |
714 | void | |
715 | ira_debug_disposition (void) | |
716 | { | |
717 | ira_print_disposition (stderr); | |
718 | } | |
719 | ||
720 | \f | |
058e97ec | 721 | |
1756cb66 VM |
722 | /* Set up ira_stack_reg_pressure_class which is the biggest pressure |
723 | register class containing stack registers or NO_REGS if there are | |
724 | no stack registers. To find this class, we iterate through all | |
725 | register pressure classes and choose the first register pressure | |
726 | class containing all the stack registers and having the biggest | |
727 | size. */ | |
fe82cdfb | 728 | static void |
1756cb66 VM |
729 | setup_stack_reg_pressure_class (void) |
730 | { | |
731 | ira_stack_reg_pressure_class = NO_REGS; | |
732 | #ifdef STACK_REGS | |
733 | { | |
734 | int i, best, size; | |
735 | enum reg_class cl; | |
736 | HARD_REG_SET temp_hard_regset2; | |
737 | ||
738 | CLEAR_HARD_REG_SET (temp_hard_regset); | |
739 | for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++) | |
740 | SET_HARD_REG_BIT (temp_hard_regset, i); | |
741 | best = 0; | |
742 | for (i = 0; i < ira_pressure_classes_num; i++) | |
743 | { | |
744 | cl = ira_pressure_classes[i]; | |
745 | COPY_HARD_REG_SET (temp_hard_regset2, temp_hard_regset); | |
746 | AND_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl]); | |
747 | size = hard_reg_set_size (temp_hard_regset2); | |
748 | if (best < size) | |
749 | { | |
750 | best = size; | |
751 | ira_stack_reg_pressure_class = cl; | |
752 | } | |
753 | } | |
754 | } | |
755 | #endif | |
756 | } | |
757 | ||
758 | /* Find pressure classes which are register classes for which we | |
759 | calculate register pressure in IRA, register pressure sensitive | |
760 | insn scheduling, and register pressure sensitive loop invariant | |
761 | motion. | |
762 | ||
763 | To make register pressure calculation easy, we always use | |
764 | non-intersected register pressure classes. A move of hard | |
765 | registers from one register pressure class is not more expensive | |
766 | than load and store of the hard registers. Most likely an allocno | |
767 | class will be a subset of a register pressure class and in many | |
768 | cases a register pressure class. That makes usage of register | |
769 | pressure classes a good approximation to find a high register | |
770 | pressure. */ | |
771 | static void | |
772 | setup_pressure_classes (void) | |
058e97ec | 773 | { |
1756cb66 VM |
774 | int cost, i, n, curr; |
775 | int cl, cl2; | |
776 | enum reg_class pressure_classes[N_REG_CLASSES]; | |
777 | int m; | |
058e97ec | 778 | HARD_REG_SET temp_hard_regset2; |
1756cb66 | 779 | bool insert_p; |
058e97ec | 780 | |
1756cb66 VM |
781 | n = 0; |
782 | for (cl = 0; cl < N_REG_CLASSES; cl++) | |
058e97ec | 783 | { |
f508f827 | 784 | if (ira_class_hard_regs_num[cl] == 0) |
058e97ec | 785 | continue; |
f508f827 | 786 | if (ira_class_hard_regs_num[cl] != 1 |
574e418a VM |
787 | /* A register class without subclasses may contain a few |
788 | hard registers and movement between them is costly | |
789 | (e.g. SPARC FPCC registers). We still should consider it | |
790 | as a candidate for a pressure class. */ | |
791 | && alloc_reg_class_subclasses[cl][0] != LIM_REG_CLASSES) | |
1756cb66 | 792 | { |
113a5be6 VM |
793 | /* Check that the moves between any hard registers of the |
794 | current class are not more expensive for a legal mode | |
795 | than load/store of the hard registers of the current | |
796 | class. Such class is a potential candidate to be a | |
797 | register pressure class. */ | |
798 | for (m = 0; m < NUM_MACHINE_MODES; m++) | |
799 | { | |
800 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); | |
801 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
802 | AND_COMPL_HARD_REG_SET (temp_hard_regset, | |
803 | ira_prohibited_class_mode_regs[cl][m]); | |
804 | if (hard_reg_set_empty_p (temp_hard_regset)) | |
805 | continue; | |
806 | ira_init_register_move_cost_if_necessary ((enum machine_mode) m); | |
807 | cost = ira_register_move_cost[m][cl][cl]; | |
808 | if (cost <= ira_max_memory_move_cost[m][cl][1] | |
809 | || cost <= ira_max_memory_move_cost[m][cl][0]) | |
810 | break; | |
811 | } | |
812 | if (m >= NUM_MACHINE_MODES) | |
1756cb66 | 813 | continue; |
1756cb66 | 814 | } |
1756cb66 VM |
815 | curr = 0; |
816 | insert_p = true; | |
817 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); | |
818 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
819 | /* Remove so far added pressure classes which are subset of the | |
820 | current candidate class. Prefer GENERAL_REGS as a pressure | |
821 | register class to another class containing the same | |
822 | allocatable hard registers. We do this because machine | |
823 | dependent cost hooks might give wrong costs for the latter | |
824 | class but always give the right cost for the former class | |
825 | (GENERAL_REGS). */ | |
826 | for (i = 0; i < n; i++) | |
827 | { | |
828 | cl2 = pressure_classes[i]; | |
829 | COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl2]); | |
830 | AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs); | |
831 | if (hard_reg_set_subset_p (temp_hard_regset, temp_hard_regset2) | |
832 | && (! hard_reg_set_equal_p (temp_hard_regset, temp_hard_regset2) | |
833 | || cl2 == (int) GENERAL_REGS)) | |
834 | { | |
835 | pressure_classes[curr++] = (enum reg_class) cl2; | |
836 | insert_p = false; | |
058e97ec | 837 | continue; |
1756cb66 VM |
838 | } |
839 | if (hard_reg_set_subset_p (temp_hard_regset2, temp_hard_regset) | |
840 | && (! hard_reg_set_equal_p (temp_hard_regset2, temp_hard_regset) | |
841 | || cl == (int) GENERAL_REGS)) | |
842 | continue; | |
113a5be6 VM |
843 | if (hard_reg_set_equal_p (temp_hard_regset2, temp_hard_regset)) |
844 | insert_p = false; | |
1756cb66 VM |
845 | pressure_classes[curr++] = (enum reg_class) cl2; |
846 | } | |
847 | /* If the current candidate is a subset of a so far added | |
848 | pressure class, don't add it to the list of the pressure | |
849 | classes. */ | |
850 | if (insert_p) | |
851 | pressure_classes[curr++] = (enum reg_class) cl; | |
852 | n = curr; | |
fe82cdfb | 853 | } |
1756cb66 | 854 | #ifdef ENABLE_IRA_CHECKING |
113a5be6 VM |
855 | { |
856 | HARD_REG_SET ignore_hard_regs; | |
857 | ||
858 | /* Check pressure classes correctness: here we check that hard | |
859 | registers from all register pressure classes contains all hard | |
860 | registers available for the allocation. */ | |
861 | CLEAR_HARD_REG_SET (temp_hard_regset); | |
862 | CLEAR_HARD_REG_SET (temp_hard_regset2); | |
863 | COPY_HARD_REG_SET (ignore_hard_regs, no_unit_alloc_regs); | |
864 | for (cl = 0; cl < LIM_REG_CLASSES; cl++) | |
865 | { | |
866 | /* For some targets (like MIPS with MD_REGS), there are some | |
867 | classes with hard registers available for allocation but | |
868 | not able to hold value of any mode. */ | |
869 | for (m = 0; m < NUM_MACHINE_MODES; m++) | |
870 | if (contains_reg_of_mode[cl][m]) | |
871 | break; | |
872 | if (m >= NUM_MACHINE_MODES) | |
873 | { | |
874 | IOR_HARD_REG_SET (ignore_hard_regs, reg_class_contents[cl]); | |
875 | continue; | |
876 | } | |
877 | for (i = 0; i < n; i++) | |
878 | if ((int) pressure_classes[i] == cl) | |
879 | break; | |
880 | IOR_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl]); | |
881 | if (i < n) | |
882 | IOR_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); | |
883 | } | |
884 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
885 | /* Some targets (like SPARC with ICC reg) have alocatable regs | |
886 | for which no reg class is defined. */ | |
887 | if (REGNO_REG_CLASS (i) == NO_REGS) | |
888 | SET_HARD_REG_BIT (ignore_hard_regs, i); | |
889 | AND_COMPL_HARD_REG_SET (temp_hard_regset, ignore_hard_regs); | |
890 | AND_COMPL_HARD_REG_SET (temp_hard_regset2, ignore_hard_regs); | |
891 | ira_assert (hard_reg_set_subset_p (temp_hard_regset2, temp_hard_regset)); | |
892 | } | |
1756cb66 VM |
893 | #endif |
894 | ira_pressure_classes_num = 0; | |
895 | for (i = 0; i < n; i++) | |
896 | { | |
897 | cl = (int) pressure_classes[i]; | |
898 | ira_reg_pressure_class_p[cl] = true; | |
899 | ira_pressure_classes[ira_pressure_classes_num++] = (enum reg_class) cl; | |
900 | } | |
901 | setup_stack_reg_pressure_class (); | |
058e97ec VM |
902 | } |
903 | ||
1756cb66 VM |
904 | /* Set up IRA_ALLOCNO_CLASSES, IRA_ALLOCNO_CLASSES_NUM, |
905 | IRA_IMPORTANT_CLASSES, and IRA_IMPORTANT_CLASSES_NUM. | |
906 | ||
907 | Target may have many subtargets and not all target hard regiters can | |
908 | be used for allocation, e.g. x86 port in 32-bit mode can not use | |
909 | hard registers introduced in x86-64 like r8-r15). Some classes | |
910 | might have the same allocatable hard registers, e.g. INDEX_REGS | |
911 | and GENERAL_REGS in x86 port in 32-bit mode. To decrease different | |
912 | calculations efforts we introduce allocno classes which contain | |
913 | unique non-empty sets of allocatable hard-registers. | |
914 | ||
915 | Pseudo class cost calculation in ira-costs.c is very expensive. | |
916 | Therefore we are trying to decrease number of classes involved in | |
917 | such calculation. Register classes used in the cost calculation | |
918 | are called important classes. They are allocno classes and other | |
919 | non-empty classes whose allocatable hard register sets are inside | |
920 | of an allocno class hard register set. From the first sight, it | |
921 | looks like that they are just allocno classes. It is not true. In | |
922 | example of x86-port in 32-bit mode, allocno classes will contain | |
923 | GENERAL_REGS but not LEGACY_REGS (because allocatable hard | |
924 | registers are the same for the both classes). The important | |
925 | classes will contain GENERAL_REGS and LEGACY_REGS. It is done | |
926 | because a machine description insn constraint may refers for | |
927 | LEGACY_REGS and code in ira-costs.c is mostly base on investigation | |
928 | of the insn constraints. */ | |
058e97ec | 929 | static void |
1756cb66 | 930 | setup_allocno_and_important_classes (void) |
058e97ec | 931 | { |
32e8bb8e | 932 | int i, j, n, cl; |
db1a8d98 | 933 | bool set_p; |
058e97ec | 934 | HARD_REG_SET temp_hard_regset2; |
7db7ed3c VM |
935 | static enum reg_class classes[LIM_REG_CLASSES + 1]; |
936 | ||
1756cb66 VM |
937 | n = 0; |
938 | /* Collect classes which contain unique sets of allocatable hard | |
939 | registers. Prefer GENERAL_REGS to other classes containing the | |
940 | same set of hard registers. */ | |
a58dfa49 | 941 | for (i = 0; i < LIM_REG_CLASSES; i++) |
99710245 | 942 | { |
1756cb66 VM |
943 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[i]); |
944 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
945 | for (j = 0; j < n; j++) | |
7db7ed3c | 946 | { |
1756cb66 VM |
947 | cl = classes[j]; |
948 | COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl]); | |
949 | AND_COMPL_HARD_REG_SET (temp_hard_regset2, | |
950 | no_unit_alloc_regs); | |
951 | if (hard_reg_set_equal_p (temp_hard_regset, | |
952 | temp_hard_regset2)) | |
953 | break; | |
7db7ed3c | 954 | } |
1756cb66 VM |
955 | if (j >= n) |
956 | classes[n++] = (enum reg_class) i; | |
957 | else if (i == GENERAL_REGS) | |
958 | /* Prefer general regs. For i386 example, it means that | |
959 | we prefer GENERAL_REGS over INDEX_REGS or LEGACY_REGS | |
960 | (all of them consists of the same available hard | |
961 | registers). */ | |
962 | classes[j] = (enum reg_class) i; | |
7db7ed3c | 963 | } |
1756cb66 | 964 | classes[n] = LIM_REG_CLASSES; |
058e97ec | 965 | |
1756cb66 VM |
966 | /* Set up classes which can be used for allocnos as classes |
967 | conatining non-empty unique sets of allocatable hard | |
968 | registers. */ | |
969 | ira_allocno_classes_num = 0; | |
058e97ec VM |
970 | for (i = 0; (cl = classes[i]) != LIM_REG_CLASSES; i++) |
971 | { | |
058e97ec VM |
972 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); |
973 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
1756cb66 VM |
974 | if (hard_reg_set_empty_p (temp_hard_regset)) |
975 | continue; | |
976 | ira_allocno_classes[ira_allocno_classes_num++] = (enum reg_class) cl; | |
058e97ec VM |
977 | } |
978 | ira_important_classes_num = 0; | |
1756cb66 VM |
979 | /* Add non-allocno classes containing to non-empty set of |
980 | allocatable hard regs. */ | |
058e97ec VM |
981 | for (cl = 0; cl < N_REG_CLASSES; cl++) |
982 | { | |
983 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); | |
984 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
4f341ea0 | 985 | if (! hard_reg_set_empty_p (temp_hard_regset)) |
7db7ed3c | 986 | { |
db1a8d98 | 987 | set_p = false; |
1756cb66 | 988 | for (j = 0; j < ira_allocno_classes_num; j++) |
7db7ed3c | 989 | { |
7db7ed3c | 990 | COPY_HARD_REG_SET (temp_hard_regset2, |
1756cb66 | 991 | reg_class_contents[ira_allocno_classes[j]]); |
7db7ed3c | 992 | AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs); |
1756cb66 | 993 | if ((enum reg_class) cl == ira_allocno_classes[j]) |
db1a8d98 | 994 | break; |
7db7ed3c VM |
995 | else if (hard_reg_set_subset_p (temp_hard_regset, |
996 | temp_hard_regset2)) | |
997 | set_p = true; | |
998 | } | |
1756cb66 | 999 | if (set_p && j >= ira_allocno_classes_num) |
db1a8d98 VM |
1000 | ira_important_classes[ira_important_classes_num++] |
1001 | = (enum reg_class) cl; | |
7db7ed3c | 1002 | } |
058e97ec | 1003 | } |
1756cb66 VM |
1004 | /* Now add allocno classes to the important classes. */ |
1005 | for (j = 0; j < ira_allocno_classes_num; j++) | |
db1a8d98 | 1006 | ira_important_classes[ira_important_classes_num++] |
1756cb66 VM |
1007 | = ira_allocno_classes[j]; |
1008 | for (cl = 0; cl < N_REG_CLASSES; cl++) | |
1009 | { | |
1010 | ira_reg_allocno_class_p[cl] = false; | |
1011 | ira_reg_pressure_class_p[cl] = false; | |
1012 | } | |
1013 | for (j = 0; j < ira_allocno_classes_num; j++) | |
1014 | ira_reg_allocno_class_p[ira_allocno_classes[j]] = true; | |
1015 | setup_pressure_classes (); | |
058e97ec | 1016 | } |
058e97ec | 1017 | |
1756cb66 VM |
1018 | /* Setup translation in CLASS_TRANSLATE of all classes into a class |
1019 | given by array CLASSES of length CLASSES_NUM. The function is used | |
1020 | make translation any reg class to an allocno class or to an | |
1021 | pressure class. This translation is necessary for some | |
1022 | calculations when we can use only allocno or pressure classes and | |
1023 | such translation represents an approximate representation of all | |
1024 | classes. | |
1025 | ||
1026 | The translation in case when allocatable hard register set of a | |
1027 | given class is subset of allocatable hard register set of a class | |
1028 | in CLASSES is pretty simple. We use smallest classes from CLASSES | |
1029 | containing a given class. If allocatable hard register set of a | |
1030 | given class is not a subset of any corresponding set of a class | |
1031 | from CLASSES, we use the cheapest (with load/store point of view) | |
1032 | class from CLASSES whose set intersects with given class set */ | |
058e97ec | 1033 | static void |
1756cb66 VM |
1034 | setup_class_translate_array (enum reg_class *class_translate, |
1035 | int classes_num, enum reg_class *classes) | |
058e97ec | 1036 | { |
32e8bb8e | 1037 | int cl, mode; |
1756cb66 | 1038 | enum reg_class aclass, best_class, *cl_ptr; |
058e97ec VM |
1039 | int i, cost, min_cost, best_cost; |
1040 | ||
1041 | for (cl = 0; cl < N_REG_CLASSES; cl++) | |
1756cb66 | 1042 | class_translate[cl] = NO_REGS; |
b8698a0f | 1043 | |
1756cb66 | 1044 | for (i = 0; i < classes_num; i++) |
058e97ec | 1045 | { |
1756cb66 VM |
1046 | aclass = classes[i]; |
1047 | for (cl_ptr = &alloc_reg_class_subclasses[aclass][0]; | |
1048 | (cl = *cl_ptr) != LIM_REG_CLASSES; | |
1049 | cl_ptr++) | |
1050 | if (class_translate[cl] == NO_REGS) | |
1051 | class_translate[cl] = aclass; | |
1052 | class_translate[aclass] = aclass; | |
058e97ec | 1053 | } |
1756cb66 VM |
1054 | /* For classes which are not fully covered by one of given classes |
1055 | (in other words covered by more one given class), use the | |
1056 | cheapest class. */ | |
058e97ec VM |
1057 | for (cl = 0; cl < N_REG_CLASSES; cl++) |
1058 | { | |
1756cb66 | 1059 | if (cl == NO_REGS || class_translate[cl] != NO_REGS) |
058e97ec VM |
1060 | continue; |
1061 | best_class = NO_REGS; | |
1062 | best_cost = INT_MAX; | |
1756cb66 | 1063 | for (i = 0; i < classes_num; i++) |
058e97ec | 1064 | { |
1756cb66 | 1065 | aclass = classes[i]; |
058e97ec | 1066 | COPY_HARD_REG_SET (temp_hard_regset, |
1756cb66 | 1067 | reg_class_contents[aclass]); |
058e97ec VM |
1068 | AND_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); |
1069 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
4f341ea0 | 1070 | if (! hard_reg_set_empty_p (temp_hard_regset)) |
058e97ec VM |
1071 | { |
1072 | min_cost = INT_MAX; | |
1073 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
1074 | { | |
1075 | cost = (ira_memory_move_cost[mode][cl][0] | |
1076 | + ira_memory_move_cost[mode][cl][1]); | |
1077 | if (min_cost > cost) | |
1078 | min_cost = cost; | |
1079 | } | |
1080 | if (best_class == NO_REGS || best_cost > min_cost) | |
1081 | { | |
1756cb66 | 1082 | best_class = aclass; |
058e97ec VM |
1083 | best_cost = min_cost; |
1084 | } | |
1085 | } | |
1086 | } | |
1756cb66 | 1087 | class_translate[cl] = best_class; |
058e97ec VM |
1088 | } |
1089 | } | |
058e97ec | 1090 | |
1756cb66 VM |
1091 | /* Set up array IRA_ALLOCNO_CLASS_TRANSLATE and |
1092 | IRA_PRESSURE_CLASS_TRANSLATE. */ | |
1093 | static void | |
1094 | setup_class_translate (void) | |
1095 | { | |
1096 | setup_class_translate_array (ira_allocno_class_translate, | |
1097 | ira_allocno_classes_num, ira_allocno_classes); | |
1098 | setup_class_translate_array (ira_pressure_class_translate, | |
1099 | ira_pressure_classes_num, ira_pressure_classes); | |
1100 | } | |
1101 | ||
1102 | /* Order numbers of allocno classes in original target allocno class | |
1103 | array, -1 for non-allocno classes. */ | |
1104 | static int allocno_class_order[N_REG_CLASSES]; | |
db1a8d98 VM |
1105 | |
1106 | /* The function used to sort the important classes. */ | |
1107 | static int | |
1108 | comp_reg_classes_func (const void *v1p, const void *v2p) | |
1109 | { | |
1110 | enum reg_class cl1 = *(const enum reg_class *) v1p; | |
1111 | enum reg_class cl2 = *(const enum reg_class *) v2p; | |
1756cb66 | 1112 | enum reg_class tcl1, tcl2; |
db1a8d98 VM |
1113 | int diff; |
1114 | ||
1756cb66 VM |
1115 | tcl1 = ira_allocno_class_translate[cl1]; |
1116 | tcl2 = ira_allocno_class_translate[cl2]; | |
1117 | if (tcl1 != NO_REGS && tcl2 != NO_REGS | |
1118 | && (diff = allocno_class_order[tcl1] - allocno_class_order[tcl2]) != 0) | |
db1a8d98 VM |
1119 | return diff; |
1120 | return (int) cl1 - (int) cl2; | |
1121 | } | |
1122 | ||
1756cb66 VM |
1123 | /* For correct work of function setup_reg_class_relation we need to |
1124 | reorder important classes according to the order of their allocno | |
1125 | classes. It places important classes containing the same | |
1126 | allocatable hard register set adjacent to each other and allocno | |
1127 | class with the allocatable hard register set right after the other | |
1128 | important classes with the same set. | |
1129 | ||
1130 | In example from comments of function | |
1131 | setup_allocno_and_important_classes, it places LEGACY_REGS and | |
1132 | GENERAL_REGS close to each other and GENERAL_REGS is after | |
1133 | LEGACY_REGS. */ | |
db1a8d98 VM |
1134 | static void |
1135 | reorder_important_classes (void) | |
1136 | { | |
1137 | int i; | |
1138 | ||
1139 | for (i = 0; i < N_REG_CLASSES; i++) | |
1756cb66 VM |
1140 | allocno_class_order[i] = -1; |
1141 | for (i = 0; i < ira_allocno_classes_num; i++) | |
1142 | allocno_class_order[ira_allocno_classes[i]] = i; | |
db1a8d98 VM |
1143 | qsort (ira_important_classes, ira_important_classes_num, |
1144 | sizeof (enum reg_class), comp_reg_classes_func); | |
1756cb66 VM |
1145 | for (i = 0; i < ira_important_classes_num; i++) |
1146 | ira_important_class_nums[ira_important_classes[i]] = i; | |
db1a8d98 VM |
1147 | } |
1148 | ||
1756cb66 VM |
1149 | /* Set up IRA_REG_CLASS_SUBUNION, IRA_REG_CLASS_SUPERUNION, |
1150 | IRA_REG_CLASS_SUPER_CLASSES, IRA_REG_CLASSES_INTERSECT, and | |
1151 | IRA_REG_CLASSES_INTERSECT_P. For the meaning of the relations, | |
1152 | please see corresponding comments in ira-int.h. */ | |
058e97ec | 1153 | static void |
7db7ed3c | 1154 | setup_reg_class_relations (void) |
058e97ec VM |
1155 | { |
1156 | int i, cl1, cl2, cl3; | |
1157 | HARD_REG_SET intersection_set, union_set, temp_set2; | |
7db7ed3c | 1158 | bool important_class_p[N_REG_CLASSES]; |
058e97ec | 1159 | |
7db7ed3c VM |
1160 | memset (important_class_p, 0, sizeof (important_class_p)); |
1161 | for (i = 0; i < ira_important_classes_num; i++) | |
1162 | important_class_p[ira_important_classes[i]] = true; | |
058e97ec VM |
1163 | for (cl1 = 0; cl1 < N_REG_CLASSES; cl1++) |
1164 | { | |
7db7ed3c | 1165 | ira_reg_class_super_classes[cl1][0] = LIM_REG_CLASSES; |
058e97ec VM |
1166 | for (cl2 = 0; cl2 < N_REG_CLASSES; cl2++) |
1167 | { | |
7db7ed3c | 1168 | ira_reg_classes_intersect_p[cl1][cl2] = false; |
058e97ec VM |
1169 | ira_reg_class_intersect[cl1][cl2] = NO_REGS; |
1170 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl1]); | |
1171 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
1172 | COPY_HARD_REG_SET (temp_set2, reg_class_contents[cl2]); | |
1173 | AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs); | |
4f341ea0 RS |
1174 | if (hard_reg_set_empty_p (temp_hard_regset) |
1175 | && hard_reg_set_empty_p (temp_set2)) | |
058e97ec | 1176 | { |
1756cb66 VM |
1177 | /* The both classes have no allocatable hard registers |
1178 | -- take all class hard registers into account and use | |
1179 | reg_class_subunion and reg_class_superunion. */ | |
058e97ec VM |
1180 | for (i = 0;; i++) |
1181 | { | |
1182 | cl3 = reg_class_subclasses[cl1][i]; | |
1183 | if (cl3 == LIM_REG_CLASSES) | |
1184 | break; | |
1185 | if (reg_class_subset_p (ira_reg_class_intersect[cl1][cl2], | |
bbbbb16a ILT |
1186 | (enum reg_class) cl3)) |
1187 | ira_reg_class_intersect[cl1][cl2] = (enum reg_class) cl3; | |
058e97ec | 1188 | } |
1756cb66 VM |
1189 | ira_reg_class_subunion[cl1][cl2] = reg_class_subunion[cl1][cl2]; |
1190 | ira_reg_class_superunion[cl1][cl2] = reg_class_superunion[cl1][cl2]; | |
058e97ec VM |
1191 | continue; |
1192 | } | |
7db7ed3c VM |
1193 | ira_reg_classes_intersect_p[cl1][cl2] |
1194 | = hard_reg_set_intersect_p (temp_hard_regset, temp_set2); | |
1195 | if (important_class_p[cl1] && important_class_p[cl2] | |
1196 | && hard_reg_set_subset_p (temp_hard_regset, temp_set2)) | |
1197 | { | |
1756cb66 VM |
1198 | /* CL1 and CL2 are important classes and CL1 allocatable |
1199 | hard register set is inside of CL2 allocatable hard | |
1200 | registers -- make CL1 a superset of CL2. */ | |
7db7ed3c VM |
1201 | enum reg_class *p; |
1202 | ||
1203 | p = &ira_reg_class_super_classes[cl1][0]; | |
1204 | while (*p != LIM_REG_CLASSES) | |
1205 | p++; | |
1206 | *p++ = (enum reg_class) cl2; | |
1207 | *p = LIM_REG_CLASSES; | |
1208 | } | |
1756cb66 VM |
1209 | ira_reg_class_subunion[cl1][cl2] = NO_REGS; |
1210 | ira_reg_class_superunion[cl1][cl2] = NO_REGS; | |
058e97ec VM |
1211 | COPY_HARD_REG_SET (intersection_set, reg_class_contents[cl1]); |
1212 | AND_HARD_REG_SET (intersection_set, reg_class_contents[cl2]); | |
1213 | AND_COMPL_HARD_REG_SET (intersection_set, no_unit_alloc_regs); | |
1214 | COPY_HARD_REG_SET (union_set, reg_class_contents[cl1]); | |
1215 | IOR_HARD_REG_SET (union_set, reg_class_contents[cl2]); | |
1216 | AND_COMPL_HARD_REG_SET (union_set, no_unit_alloc_regs); | |
1217 | for (i = 0; i < ira_important_classes_num; i++) | |
1218 | { | |
1219 | cl3 = ira_important_classes[i]; | |
1220 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl3]); | |
1221 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
1222 | if (hard_reg_set_subset_p (temp_hard_regset, intersection_set)) | |
1223 | { | |
1756cb66 VM |
1224 | /* CL3 allocatable hard register set is inside of |
1225 | intersection of allocatable hard register sets | |
1226 | of CL1 and CL2. */ | |
058e97ec VM |
1227 | COPY_HARD_REG_SET |
1228 | (temp_set2, | |
1229 | reg_class_contents[(int) | |
1230 | ira_reg_class_intersect[cl1][cl2]]); | |
1231 | AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs); | |
1232 | if (! hard_reg_set_subset_p (temp_hard_regset, temp_set2) | |
1756cb66 VM |
1233 | /* If the allocatable hard register sets are the |
1234 | same, prefer GENERAL_REGS or the smallest | |
1235 | class for debugging purposes. */ | |
058e97ec | 1236 | || (hard_reg_set_equal_p (temp_hard_regset, temp_set2) |
1756cb66 VM |
1237 | && (cl3 == GENERAL_REGS |
1238 | || (ira_reg_class_intersect[cl1][cl2] != GENERAL_REGS | |
1239 | && hard_reg_set_subset_p | |
1240 | (reg_class_contents[cl3], | |
1241 | reg_class_contents | |
1242 | [(int) ira_reg_class_intersect[cl1][cl2]]))))) | |
058e97ec VM |
1243 | ira_reg_class_intersect[cl1][cl2] = (enum reg_class) cl3; |
1244 | } | |
1245 | if (hard_reg_set_subset_p (temp_hard_regset, union_set)) | |
1246 | { | |
1756cb66 VM |
1247 | /* CL3 allocatbale hard register set is inside of |
1248 | union of allocatable hard register sets of CL1 | |
1249 | and CL2. */ | |
058e97ec VM |
1250 | COPY_HARD_REG_SET |
1251 | (temp_set2, | |
1756cb66 | 1252 | reg_class_contents[(int) ira_reg_class_subunion[cl1][cl2]]); |
058e97ec | 1253 | AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs); |
1756cb66 | 1254 | if (ira_reg_class_subunion[cl1][cl2] == NO_REGS |
058e97ec | 1255 | || (hard_reg_set_subset_p (temp_set2, temp_hard_regset) |
1756cb66 VM |
1256 | |
1257 | && (! hard_reg_set_equal_p (temp_set2, | |
1258 | temp_hard_regset) | |
1259 | || cl3 == GENERAL_REGS | |
1260 | /* If the allocatable hard register sets are the | |
1261 | same, prefer GENERAL_REGS or the smallest | |
1262 | class for debugging purposes. */ | |
1263 | || (ira_reg_class_subunion[cl1][cl2] != GENERAL_REGS | |
1264 | && hard_reg_set_subset_p | |
1265 | (reg_class_contents[cl3], | |
1266 | reg_class_contents | |
1267 | [(int) ira_reg_class_subunion[cl1][cl2]]))))) | |
1268 | ira_reg_class_subunion[cl1][cl2] = (enum reg_class) cl3; | |
1269 | } | |
1270 | if (hard_reg_set_subset_p (union_set, temp_hard_regset)) | |
1271 | { | |
1272 | /* CL3 allocatable hard register set contains union | |
1273 | of allocatable hard register sets of CL1 and | |
1274 | CL2. */ | |
1275 | COPY_HARD_REG_SET | |
1276 | (temp_set2, | |
1277 | reg_class_contents[(int) ira_reg_class_superunion[cl1][cl2]]); | |
1278 | AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs); | |
1279 | if (ira_reg_class_superunion[cl1][cl2] == NO_REGS | |
1280 | || (hard_reg_set_subset_p (temp_hard_regset, temp_set2) | |
b8698a0f | 1281 | |
058e97ec VM |
1282 | && (! hard_reg_set_equal_p (temp_set2, |
1283 | temp_hard_regset) | |
1756cb66 VM |
1284 | || cl3 == GENERAL_REGS |
1285 | /* If the allocatable hard register sets are the | |
1286 | same, prefer GENERAL_REGS or the smallest | |
1287 | class for debugging purposes. */ | |
1288 | || (ira_reg_class_superunion[cl1][cl2] != GENERAL_REGS | |
1289 | && hard_reg_set_subset_p | |
1290 | (reg_class_contents[cl3], | |
1291 | reg_class_contents | |
1292 | [(int) ira_reg_class_superunion[cl1][cl2]]))))) | |
1293 | ira_reg_class_superunion[cl1][cl2] = (enum reg_class) cl3; | |
058e97ec VM |
1294 | } |
1295 | } | |
1296 | } | |
1297 | } | |
1298 | } | |
1299 | ||
1756cb66 VM |
1300 | /* Output all possible allocno classes and the translation map into |
1301 | file F. */ | |
058e97ec | 1302 | static void |
1756cb66 VM |
1303 | print_classes (FILE *f, bool pressure_p) |
1304 | { | |
1305 | int classes_num = (pressure_p | |
1306 | ? ira_pressure_classes_num : ira_allocno_classes_num); | |
1307 | enum reg_class *classes = (pressure_p | |
1308 | ? ira_pressure_classes : ira_allocno_classes); | |
1309 | enum reg_class *class_translate = (pressure_p | |
1310 | ? ira_pressure_class_translate | |
1311 | : ira_allocno_class_translate); | |
058e97ec VM |
1312 | static const char *const reg_class_names[] = REG_CLASS_NAMES; |
1313 | int i; | |
1314 | ||
1756cb66 VM |
1315 | fprintf (f, "%s classes:\n", pressure_p ? "Pressure" : "Allocno"); |
1316 | for (i = 0; i < classes_num; i++) | |
1317 | fprintf (f, " %s", reg_class_names[classes[i]]); | |
058e97ec VM |
1318 | fprintf (f, "\nClass translation:\n"); |
1319 | for (i = 0; i < N_REG_CLASSES; i++) | |
1320 | fprintf (f, " %s -> %s\n", reg_class_names[i], | |
1756cb66 | 1321 | reg_class_names[class_translate[i]]); |
058e97ec VM |
1322 | } |
1323 | ||
1756cb66 VM |
1324 | /* Output all possible allocno and translation classes and the |
1325 | translation maps into stderr. */ | |
058e97ec | 1326 | void |
1756cb66 | 1327 | ira_debug_allocno_classes (void) |
058e97ec | 1328 | { |
1756cb66 VM |
1329 | print_classes (stderr, false); |
1330 | print_classes (stderr, true); | |
058e97ec VM |
1331 | } |
1332 | ||
1756cb66 | 1333 | /* Set up different arrays concerning class subsets, allocno and |
058e97ec VM |
1334 | important classes. */ |
1335 | static void | |
1756cb66 | 1336 | find_reg_classes (void) |
058e97ec | 1337 | { |
1756cb66 | 1338 | setup_allocno_and_important_classes (); |
7db7ed3c | 1339 | setup_class_translate (); |
db1a8d98 | 1340 | reorder_important_classes (); |
7db7ed3c | 1341 | setup_reg_class_relations (); |
058e97ec VM |
1342 | } |
1343 | ||
1344 | \f | |
1345 | ||
c0683a82 VM |
1346 | /* Set up the array above. */ |
1347 | static void | |
1756cb66 | 1348 | setup_hard_regno_aclass (void) |
c0683a82 | 1349 | { |
7efcf910 | 1350 | int i; |
c0683a82 VM |
1351 | |
1352 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1353 | { | |
1756cb66 VM |
1354 | #if 1 |
1355 | ira_hard_regno_allocno_class[i] | |
7efcf910 CLT |
1356 | = (TEST_HARD_REG_BIT (no_unit_alloc_regs, i) |
1357 | ? NO_REGS | |
1756cb66 VM |
1358 | : ira_allocno_class_translate[REGNO_REG_CLASS (i)]); |
1359 | #else | |
1360 | int j; | |
1361 | enum reg_class cl; | |
1362 | ira_hard_regno_allocno_class[i] = NO_REGS; | |
1363 | for (j = 0; j < ira_allocno_classes_num; j++) | |
1364 | { | |
1365 | cl = ira_allocno_classes[j]; | |
1366 | if (ira_class_hard_reg_index[cl][i] >= 0) | |
1367 | { | |
1368 | ira_hard_regno_allocno_class[i] = cl; | |
1369 | break; | |
1370 | } | |
1371 | } | |
1372 | #endif | |
c0683a82 VM |
1373 | } |
1374 | } | |
1375 | ||
1376 | \f | |
1377 | ||
1756cb66 | 1378 | /* Form IRA_REG_CLASS_MAX_NREGS and IRA_REG_CLASS_MIN_NREGS maps. */ |
058e97ec VM |
1379 | static void |
1380 | setup_reg_class_nregs (void) | |
1381 | { | |
1756cb66 | 1382 | int i, cl, cl2, m; |
058e97ec | 1383 | |
1756cb66 VM |
1384 | for (m = 0; m < MAX_MACHINE_MODE; m++) |
1385 | { | |
1386 | for (cl = 0; cl < N_REG_CLASSES; cl++) | |
1387 | ira_reg_class_max_nregs[cl][m] | |
1388 | = ira_reg_class_min_nregs[cl][m] | |
a8c44c52 | 1389 | = targetm.class_max_nregs ((reg_class_t) cl, (enum machine_mode) m); |
1756cb66 VM |
1390 | for (cl = 0; cl < N_REG_CLASSES; cl++) |
1391 | for (i = 0; | |
1392 | (cl2 = alloc_reg_class_subclasses[cl][i]) != LIM_REG_CLASSES; | |
1393 | i++) | |
1394 | if (ira_reg_class_min_nregs[cl2][m] | |
1395 | < ira_reg_class_min_nregs[cl][m]) | |
1396 | ira_reg_class_min_nregs[cl][m] = ira_reg_class_min_nregs[cl2][m]; | |
1397 | } | |
058e97ec VM |
1398 | } |
1399 | ||
1400 | \f | |
1401 | ||
1756cb66 | 1402 | /* Set up IRA_PROHIBITED_CLASS_MODE_REGS. */ |
058e97ec VM |
1403 | static void |
1404 | setup_prohibited_class_mode_regs (void) | |
1405 | { | |
1756cb66 | 1406 | int j, k, hard_regno, cl; |
058e97ec | 1407 | |
1756cb66 | 1408 | for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) |
058e97ec | 1409 | { |
058e97ec VM |
1410 | for (j = 0; j < NUM_MACHINE_MODES; j++) |
1411 | { | |
1756cb66 | 1412 | CLEAR_HARD_REG_SET (ira_prohibited_class_mode_regs[cl][j]); |
058e97ec VM |
1413 | for (k = ira_class_hard_regs_num[cl] - 1; k >= 0; k--) |
1414 | { | |
1415 | hard_regno = ira_class_hard_regs[cl][k]; | |
bbbbb16a | 1416 | if (! HARD_REGNO_MODE_OK (hard_regno, (enum machine_mode) j)) |
1756cb66 | 1417 | SET_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j], |
058e97ec VM |
1418 | hard_regno); |
1419 | } | |
1420 | } | |
1421 | } | |
1422 | } | |
1423 | ||
1756cb66 VM |
1424 | /* Clarify IRA_PROHIBITED_CLASS_MODE_REGS by excluding hard registers |
1425 | spanning from one register pressure class to another one. It is | |
1426 | called after defining the pressure classes. */ | |
1427 | static void | |
1428 | clarify_prohibited_class_mode_regs (void) | |
1429 | { | |
1430 | int j, k, hard_regno, cl, pclass, nregs; | |
1431 | ||
1432 | for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) | |
1433 | for (j = 0; j < NUM_MACHINE_MODES; j++) | |
1434 | for (k = ira_class_hard_regs_num[cl] - 1; k >= 0; k--) | |
1435 | { | |
1436 | hard_regno = ira_class_hard_regs[cl][k]; | |
1437 | if (TEST_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j], hard_regno)) | |
1438 | continue; | |
1439 | nregs = hard_regno_nregs[hard_regno][j]; | |
b27981e0 HS |
1440 | if (hard_regno + nregs > FIRST_PSEUDO_REGISTER) |
1441 | { | |
1442 | SET_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j], | |
1443 | hard_regno); | |
1444 | continue; | |
1445 | } | |
1756cb66 VM |
1446 | pclass = ira_pressure_class_translate[REGNO_REG_CLASS (hard_regno)]; |
1447 | for (nregs-- ;nregs >= 0; nregs--) | |
1448 | if (((enum reg_class) pclass | |
1449 | != ira_pressure_class_translate[REGNO_REG_CLASS | |
1450 | (hard_regno + nregs)])) | |
1451 | { | |
1452 | SET_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j], | |
1453 | hard_regno); | |
1454 | break; | |
1455 | } | |
1456 | } | |
1457 | } | |
1458 | ||
058e97ec VM |
1459 | \f |
1460 | ||
1461 | /* Allocate and initialize IRA_REGISTER_MOVE_COST, | |
1756cb66 VM |
1462 | IRA_MAX_REGISTER_MOVE_COST, IRA_MAY_MOVE_IN_COST, |
1463 | IRA_MAY_MOVE_OUT_COST, IRA_MAX_MAY_MOVE_IN_COST, and | |
1464 | IRA_MAX_MAY_MOVE_OUT_COST for MODE if it is not done yet. */ | |
058e97ec VM |
1465 | void |
1466 | ira_init_register_move_cost (enum machine_mode mode) | |
1467 | { | |
1756cb66 | 1468 | int cl1, cl2, cl3; |
058e97ec VM |
1469 | |
1470 | ira_assert (ira_register_move_cost[mode] == NULL | |
1756cb66 | 1471 | && ira_max_register_move_cost[mode] == NULL |
058e97ec | 1472 | && ira_may_move_in_cost[mode] == NULL |
1756cb66 VM |
1473 | && ira_may_move_out_cost[mode] == NULL |
1474 | && ira_max_may_move_in_cost[mode] == NULL | |
1475 | && ira_max_may_move_out_cost[mode] == NULL); | |
058e97ec VM |
1476 | if (move_cost[mode] == NULL) |
1477 | init_move_cost (mode); | |
1478 | ira_register_move_cost[mode] = move_cost[mode]; | |
1479 | /* Don't use ira_allocate because the tables exist out of scope of a | |
1480 | IRA call. */ | |
1756cb66 VM |
1481 | ira_max_register_move_cost[mode] |
1482 | = (move_table *) xmalloc (sizeof (move_table) * N_REG_CLASSES); | |
1483 | memcpy (ira_max_register_move_cost[mode], ira_register_move_cost[mode], | |
1484 | sizeof (move_table) * N_REG_CLASSES); | |
1485 | for (cl1 = 0; cl1 < N_REG_CLASSES; cl1++) | |
1486 | { | |
3bb19a90 VM |
1487 | /* Some subclasses are to small to have enough registers to hold |
1488 | a value of MODE. Just ignore them. */ | |
f508f827 | 1489 | if (ira_reg_class_max_nregs[cl1][mode] > ira_class_hard_regs_num[cl1]) |
3bb19a90 | 1490 | continue; |
1756cb66 VM |
1491 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl1]); |
1492 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
1493 | if (hard_reg_set_empty_p (temp_hard_regset)) | |
1494 | continue; | |
1495 | for (cl2 = 0; cl2 < N_REG_CLASSES; cl2++) | |
1496 | if (hard_reg_set_subset_p (reg_class_contents[cl1], | |
1497 | reg_class_contents[cl2])) | |
1498 | for (cl3 = 0; cl3 < N_REG_CLASSES; cl3++) | |
1499 | { | |
1500 | if (ira_max_register_move_cost[mode][cl2][cl3] | |
1501 | < ira_register_move_cost[mode][cl1][cl3]) | |
1502 | ira_max_register_move_cost[mode][cl2][cl3] | |
1503 | = ira_register_move_cost[mode][cl1][cl3]; | |
1504 | if (ira_max_register_move_cost[mode][cl3][cl2] | |
1505 | < ira_register_move_cost[mode][cl3][cl1]) | |
1506 | ira_max_register_move_cost[mode][cl3][cl2] | |
1507 | = ira_register_move_cost[mode][cl3][cl1]; | |
1508 | } | |
1509 | } | |
058e97ec VM |
1510 | ira_may_move_in_cost[mode] |
1511 | = (move_table *) xmalloc (sizeof (move_table) * N_REG_CLASSES); | |
1512 | memcpy (ira_may_move_in_cost[mode], may_move_in_cost[mode], | |
1513 | sizeof (move_table) * N_REG_CLASSES); | |
1514 | ira_may_move_out_cost[mode] | |
1515 | = (move_table *) xmalloc (sizeof (move_table) * N_REG_CLASSES); | |
1516 | memcpy (ira_may_move_out_cost[mode], may_move_out_cost[mode], | |
1517 | sizeof (move_table) * N_REG_CLASSES); | |
1756cb66 VM |
1518 | ira_max_may_move_in_cost[mode] |
1519 | = (move_table *) xmalloc (sizeof (move_table) * N_REG_CLASSES); | |
1520 | memcpy (ira_max_may_move_in_cost[mode], ira_max_register_move_cost[mode], | |
1521 | sizeof (move_table) * N_REG_CLASSES); | |
1522 | ira_max_may_move_out_cost[mode] | |
1523 | = (move_table *) xmalloc (sizeof (move_table) * N_REG_CLASSES); | |
1524 | memcpy (ira_max_may_move_out_cost[mode], ira_max_register_move_cost[mode], | |
1525 | sizeof (move_table) * N_REG_CLASSES); | |
058e97ec VM |
1526 | for (cl1 = 0; cl1 < N_REG_CLASSES; cl1++) |
1527 | { | |
1528 | for (cl2 = 0; cl2 < N_REG_CLASSES; cl2++) | |
1529 | { | |
1756cb66 VM |
1530 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl2]); |
1531 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
1532 | if (hard_reg_set_empty_p (temp_hard_regset)) | |
1533 | continue; | |
058e97ec VM |
1534 | if (ira_class_subset_p[cl1][cl2]) |
1535 | ira_may_move_in_cost[mode][cl1][cl2] = 0; | |
1536 | if (ira_class_subset_p[cl2][cl1]) | |
1537 | ira_may_move_out_cost[mode][cl1][cl2] = 0; | |
1756cb66 VM |
1538 | if (ira_class_subset_p[cl1][cl2]) |
1539 | ira_max_may_move_in_cost[mode][cl1][cl2] = 0; | |
1540 | if (ira_class_subset_p[cl2][cl1]) | |
1541 | ira_max_may_move_out_cost[mode][cl1][cl2] = 0; | |
1542 | ira_register_move_cost[mode][cl1][cl2] | |
1543 | = ira_max_register_move_cost[mode][cl1][cl2]; | |
1544 | ira_may_move_in_cost[mode][cl1][cl2] | |
1545 | = ira_max_may_move_in_cost[mode][cl1][cl2]; | |
1546 | ira_may_move_out_cost[mode][cl1][cl2] | |
1547 | = ira_max_may_move_out_cost[mode][cl1][cl2]; | |
058e97ec VM |
1548 | } |
1549 | } | |
1550 | } | |
1551 | ||
1552 | \f | |
1553 | ||
058e97ec VM |
1554 | /* This is called once during compiler work. It sets up |
1555 | different arrays whose values don't depend on the compiled | |
1556 | function. */ | |
1557 | void | |
1558 | ira_init_once (void) | |
1559 | { | |
32e8bb8e | 1560 | int mode; |
058e97ec | 1561 | |
058e97ec VM |
1562 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) |
1563 | { | |
1564 | ira_register_move_cost[mode] = NULL; | |
1756cb66 | 1565 | ira_max_register_move_cost[mode] = NULL; |
058e97ec VM |
1566 | ira_may_move_in_cost[mode] = NULL; |
1567 | ira_may_move_out_cost[mode] = NULL; | |
1756cb66 VM |
1568 | ira_max_may_move_in_cost[mode] = NULL; |
1569 | ira_max_may_move_out_cost[mode] = NULL; | |
058e97ec VM |
1570 | } |
1571 | ira_init_costs_once (); | |
1572 | } | |
1573 | ||
1756cb66 VM |
1574 | /* Free ira_max_register_move_cost, ira_may_move_in_cost, |
1575 | ira_may_move_out_cost, ira_max_may_move_in_cost, and | |
1576 | ira_max_may_move_out_cost for each mode. */ | |
058e97ec VM |
1577 | static void |
1578 | free_register_move_costs (void) | |
1579 | { | |
32e8bb8e | 1580 | int mode; |
058e97ec VM |
1581 | |
1582 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
1583 | { | |
04695783 JM |
1584 | free (ira_max_register_move_cost[mode]); |
1585 | free (ira_may_move_in_cost[mode]); | |
1586 | free (ira_may_move_out_cost[mode]); | |
1587 | free (ira_max_may_move_in_cost[mode]); | |
1588 | free (ira_max_may_move_out_cost[mode]); | |
058e97ec | 1589 | ira_register_move_cost[mode] = NULL; |
1756cb66 | 1590 | ira_max_register_move_cost[mode] = NULL; |
058e97ec VM |
1591 | ira_may_move_in_cost[mode] = NULL; |
1592 | ira_may_move_out_cost[mode] = NULL; | |
1756cb66 VM |
1593 | ira_max_may_move_in_cost[mode] = NULL; |
1594 | ira_max_may_move_out_cost[mode] = NULL; | |
058e97ec VM |
1595 | } |
1596 | } | |
1597 | ||
1598 | /* This is called every time when register related information is | |
1599 | changed. */ | |
1600 | void | |
1601 | ira_init (void) | |
1602 | { | |
1603 | free_register_move_costs (); | |
1604 | setup_reg_mode_hard_regset (); | |
1605 | setup_alloc_regs (flag_omit_frame_pointer != 0); | |
1606 | setup_class_subset_and_memory_move_costs (); | |
058e97ec VM |
1607 | setup_reg_class_nregs (); |
1608 | setup_prohibited_class_mode_regs (); | |
1756cb66 VM |
1609 | find_reg_classes (); |
1610 | clarify_prohibited_class_mode_regs (); | |
1611 | setup_hard_regno_aclass (); | |
058e97ec VM |
1612 | ira_init_costs (); |
1613 | } | |
1614 | ||
1615 | /* Function called once at the end of compiler work. */ | |
1616 | void | |
1617 | ira_finish_once (void) | |
1618 | { | |
1619 | ira_finish_costs_once (); | |
1620 | free_register_move_costs (); | |
1621 | } | |
1622 | ||
1623 | \f | |
15e7b94f RS |
1624 | #define ira_prohibited_mode_move_regs_initialized_p \ |
1625 | (this_target_ira_int->x_ira_prohibited_mode_move_regs_initialized_p) | |
058e97ec VM |
1626 | |
1627 | /* Set up IRA_PROHIBITED_MODE_MOVE_REGS. */ | |
1628 | static void | |
1629 | setup_prohibited_mode_move_regs (void) | |
1630 | { | |
1631 | int i, j; | |
1632 | rtx test_reg1, test_reg2, move_pat, move_insn; | |
1633 | ||
1634 | if (ira_prohibited_mode_move_regs_initialized_p) | |
1635 | return; | |
1636 | ira_prohibited_mode_move_regs_initialized_p = true; | |
1637 | test_reg1 = gen_rtx_REG (VOIDmode, 0); | |
1638 | test_reg2 = gen_rtx_REG (VOIDmode, 0); | |
1639 | move_pat = gen_rtx_SET (VOIDmode, test_reg1, test_reg2); | |
418e920f | 1640 | move_insn = gen_rtx_INSN (VOIDmode, 0, 0, 0, 0, move_pat, 0, -1, 0); |
058e97ec VM |
1641 | for (i = 0; i < NUM_MACHINE_MODES; i++) |
1642 | { | |
1643 | SET_HARD_REG_SET (ira_prohibited_mode_move_regs[i]); | |
1644 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
1645 | { | |
bbbbb16a | 1646 | if (! HARD_REGNO_MODE_OK (j, (enum machine_mode) i)) |
058e97ec | 1647 | continue; |
5444da31 | 1648 | SET_REGNO_RAW (test_reg1, j); |
32e8bb8e | 1649 | PUT_MODE (test_reg1, (enum machine_mode) i); |
5444da31 | 1650 | SET_REGNO_RAW (test_reg2, j); |
32e8bb8e | 1651 | PUT_MODE (test_reg2, (enum machine_mode) i); |
058e97ec VM |
1652 | INSN_CODE (move_insn) = -1; |
1653 | recog_memoized (move_insn); | |
1654 | if (INSN_CODE (move_insn) < 0) | |
1655 | continue; | |
1656 | extract_insn (move_insn); | |
1657 | if (! constrain_operands (1)) | |
1658 | continue; | |
1659 | CLEAR_HARD_REG_BIT (ira_prohibited_mode_move_regs[i], j); | |
1660 | } | |
1661 | } | |
1662 | } | |
1663 | ||
1664 | \f | |
1665 | ||
0896cc66 JL |
1666 | /* Return nonzero if REGNO is a particularly bad choice for reloading X. */ |
1667 | static bool | |
1668 | ira_bad_reload_regno_1 (int regno, rtx x) | |
1669 | { | |
ac0ab4f7 | 1670 | int x_regno, n, i; |
0896cc66 JL |
1671 | ira_allocno_t a; |
1672 | enum reg_class pref; | |
1673 | ||
1674 | /* We only deal with pseudo regs. */ | |
1675 | if (! x || GET_CODE (x) != REG) | |
1676 | return false; | |
1677 | ||
1678 | x_regno = REGNO (x); | |
1679 | if (x_regno < FIRST_PSEUDO_REGISTER) | |
1680 | return false; | |
1681 | ||
1682 | /* If the pseudo prefers REGNO explicitly, then do not consider | |
1683 | REGNO a bad spill choice. */ | |
1684 | pref = reg_preferred_class (x_regno); | |
1685 | if (reg_class_size[pref] == 1) | |
1686 | return !TEST_HARD_REG_BIT (reg_class_contents[pref], regno); | |
1687 | ||
1688 | /* If the pseudo conflicts with REGNO, then we consider REGNO a | |
1689 | poor choice for a reload regno. */ | |
1690 | a = ira_regno_allocno_map[x_regno]; | |
ac0ab4f7 BS |
1691 | n = ALLOCNO_NUM_OBJECTS (a); |
1692 | for (i = 0; i < n; i++) | |
1693 | { | |
1694 | ira_object_t obj = ALLOCNO_OBJECT (a, i); | |
1695 | if (TEST_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), regno)) | |
1696 | return true; | |
1697 | } | |
0896cc66 JL |
1698 | return false; |
1699 | } | |
1700 | ||
1701 | /* Return nonzero if REGNO is a particularly bad choice for reloading | |
1702 | IN or OUT. */ | |
1703 | bool | |
1704 | ira_bad_reload_regno (int regno, rtx in, rtx out) | |
1705 | { | |
1706 | return (ira_bad_reload_regno_1 (regno, in) | |
1707 | || ira_bad_reload_regno_1 (regno, out)); | |
1708 | } | |
1709 | ||
058e97ec VM |
1710 | /* Return TRUE if *LOC contains an asm. */ |
1711 | static int | |
1712 | insn_contains_asm_1 (rtx *loc, void *data ATTRIBUTE_UNUSED) | |
1713 | { | |
1714 | if ( !*loc) | |
1715 | return FALSE; | |
1716 | if (GET_CODE (*loc) == ASM_OPERANDS) | |
1717 | return TRUE; | |
1718 | return FALSE; | |
1719 | } | |
1720 | ||
1721 | ||
1722 | /* Return TRUE if INSN contains an ASM. */ | |
1723 | static bool | |
1724 | insn_contains_asm (rtx insn) | |
1725 | { | |
1726 | return for_each_rtx (&insn, insn_contains_asm_1, NULL); | |
1727 | } | |
1728 | ||
b748fbd6 | 1729 | /* Add register clobbers from asm statements. */ |
058e97ec | 1730 | static void |
b748fbd6 | 1731 | compute_regs_asm_clobbered (void) |
058e97ec VM |
1732 | { |
1733 | basic_block bb; | |
1734 | ||
058e97ec VM |
1735 | FOR_EACH_BB (bb) |
1736 | { | |
1737 | rtx insn; | |
1738 | FOR_BB_INSNS_REVERSE (bb, insn) | |
1739 | { | |
57512f53 | 1740 | df_ref *def_rec; |
058e97ec VM |
1741 | |
1742 | if (insn_contains_asm (insn)) | |
1743 | for (def_rec = DF_INSN_DEFS (insn); *def_rec; def_rec++) | |
1744 | { | |
57512f53 | 1745 | df_ref def = *def_rec; |
058e97ec | 1746 | unsigned int dregno = DF_REF_REGNO (def); |
d108e679 AS |
1747 | if (HARD_REGISTER_NUM_P (dregno)) |
1748 | add_to_hard_reg_set (&crtl->asm_clobbers, | |
1749 | GET_MODE (DF_REF_REAL_REG (def)), | |
1750 | dregno); | |
058e97ec VM |
1751 | } |
1752 | } | |
1753 | } | |
1754 | } | |
1755 | ||
1756 | ||
1757 | /* Set up ELIMINABLE_REGSET, IRA_NO_ALLOC_REGS, and REGS_EVER_LIVE. */ | |
ce18efcb VM |
1758 | void |
1759 | ira_setup_eliminable_regset (void) | |
058e97ec | 1760 | { |
058e97ec | 1761 | #ifdef ELIMINABLE_REGS |
89ceba31 | 1762 | int i; |
058e97ec VM |
1763 | static const struct {const int from, to; } eliminables[] = ELIMINABLE_REGS; |
1764 | #endif | |
1765 | /* FIXME: If EXIT_IGNORE_STACK is set, we will not save and restore | |
1766 | sp for alloca. So we can't eliminate the frame pointer in that | |
1767 | case. At some point, we should improve this by emitting the | |
1768 | sp-adjusting insns for this case. */ | |
1769 | int need_fp | |
1770 | = (! flag_omit_frame_pointer | |
1771 | || (cfun->calls_alloca && EXIT_IGNORE_STACK) | |
d809253a EB |
1772 | /* We need the frame pointer to catch stack overflow exceptions |
1773 | if the stack pointer is moving. */ | |
1774 | || (flag_stack_check && STACK_CHECK_MOVING_SP) | |
058e97ec VM |
1775 | || crtl->accesses_prior_frames |
1776 | || crtl->stack_realign_needed | |
b52b1749 | 1777 | || targetm.frame_pointer_required ()); |
058e97ec VM |
1778 | |
1779 | frame_pointer_needed = need_fp; | |
1780 | ||
1781 | COPY_HARD_REG_SET (ira_no_alloc_regs, no_unit_alloc_regs); | |
1782 | CLEAR_HARD_REG_SET (eliminable_regset); | |
1783 | ||
b748fbd6 PB |
1784 | compute_regs_asm_clobbered (); |
1785 | ||
058e97ec VM |
1786 | /* Build the regset of all eliminable registers and show we can't |
1787 | use those that we already know won't be eliminated. */ | |
1788 | #ifdef ELIMINABLE_REGS | |
1789 | for (i = 0; i < (int) ARRAY_SIZE (eliminables); i++) | |
1790 | { | |
1791 | bool cannot_elim | |
7b5cbb57 | 1792 | = (! targetm.can_eliminate (eliminables[i].from, eliminables[i].to) |
058e97ec VM |
1793 | || (eliminables[i].to == STACK_POINTER_REGNUM && need_fp)); |
1794 | ||
b748fbd6 | 1795 | if (!TEST_HARD_REG_BIT (crtl->asm_clobbers, eliminables[i].from)) |
058e97ec VM |
1796 | { |
1797 | SET_HARD_REG_BIT (eliminable_regset, eliminables[i].from); | |
1798 | ||
1799 | if (cannot_elim) | |
1800 | SET_HARD_REG_BIT (ira_no_alloc_regs, eliminables[i].from); | |
1801 | } | |
1802 | else if (cannot_elim) | |
1803 | error ("%s cannot be used in asm here", | |
1804 | reg_names[eliminables[i].from]); | |
1805 | else | |
1806 | df_set_regs_ever_live (eliminables[i].from, true); | |
1807 | } | |
e3339d0f | 1808 | #if !HARD_FRAME_POINTER_IS_FRAME_POINTER |
b748fbd6 | 1809 | if (!TEST_HARD_REG_BIT (crtl->asm_clobbers, HARD_FRAME_POINTER_REGNUM)) |
058e97ec VM |
1810 | { |
1811 | SET_HARD_REG_BIT (eliminable_regset, HARD_FRAME_POINTER_REGNUM); | |
1812 | if (need_fp) | |
1813 | SET_HARD_REG_BIT (ira_no_alloc_regs, HARD_FRAME_POINTER_REGNUM); | |
1814 | } | |
1815 | else if (need_fp) | |
1816 | error ("%s cannot be used in asm here", | |
1817 | reg_names[HARD_FRAME_POINTER_REGNUM]); | |
1818 | else | |
1819 | df_set_regs_ever_live (HARD_FRAME_POINTER_REGNUM, true); | |
1820 | #endif | |
1821 | ||
1822 | #else | |
b748fbd6 | 1823 | if (!TEST_HARD_REG_BIT (crtl->asm_clobbers, HARD_FRAME_POINTER_REGNUM)) |
058e97ec VM |
1824 | { |
1825 | SET_HARD_REG_BIT (eliminable_regset, FRAME_POINTER_REGNUM); | |
1826 | if (need_fp) | |
1827 | SET_HARD_REG_BIT (ira_no_alloc_regs, FRAME_POINTER_REGNUM); | |
1828 | } | |
1829 | else if (need_fp) | |
1830 | error ("%s cannot be used in asm here", reg_names[FRAME_POINTER_REGNUM]); | |
1831 | else | |
1832 | df_set_regs_ever_live (FRAME_POINTER_REGNUM, true); | |
1833 | #endif | |
1834 | } | |
1835 | ||
1836 | \f | |
1837 | ||
1838 | /* The length of the following two arrays. */ | |
1839 | int ira_reg_equiv_len; | |
1840 | ||
1841 | /* The element value is TRUE if the corresponding regno value is | |
1842 | invariant. */ | |
1843 | bool *ira_reg_equiv_invariant_p; | |
1844 | ||
1845 | /* The element value is equiv constant of given pseudo-register or | |
1846 | NULL_RTX. */ | |
1847 | rtx *ira_reg_equiv_const; | |
1848 | ||
1849 | /* Set up the two arrays declared above. */ | |
1850 | static void | |
1851 | find_reg_equiv_invariant_const (void) | |
1852 | { | |
f2034d06 | 1853 | unsigned int i; |
058e97ec VM |
1854 | bool invariant_p; |
1855 | rtx list, insn, note, constant, x; | |
1856 | ||
f2034d06 | 1857 | for (i = FIRST_PSEUDO_REGISTER; i < VEC_length (reg_equivs_t, reg_equivs); i++) |
058e97ec VM |
1858 | { |
1859 | constant = NULL_RTX; | |
1860 | invariant_p = false; | |
f2034d06 | 1861 | for (list = reg_equiv_init (i); list != NULL_RTX; list = XEXP (list, 1)) |
058e97ec VM |
1862 | { |
1863 | insn = XEXP (list, 0); | |
1864 | note = find_reg_note (insn, REG_EQUIV, NULL_RTX); | |
b8698a0f | 1865 | |
058e97ec VM |
1866 | if (note == NULL_RTX) |
1867 | continue; | |
1868 | ||
1869 | x = XEXP (note, 0); | |
b8698a0f | 1870 | |
60de8907 BS |
1871 | if (! CONSTANT_P (x) |
1872 | || ! flag_pic || LEGITIMATE_PIC_OPERAND_P (x)) | |
058e97ec VM |
1873 | { |
1874 | /* It can happen that a REG_EQUIV note contains a MEM | |
1875 | that is not a legitimate memory operand. As later | |
1876 | stages of the reload assume that all addresses found | |
1877 | in the reg_equiv_* arrays were originally legitimate, | |
1878 | we ignore such REG_EQUIV notes. */ | |
1879 | if (memory_operand (x, VOIDmode)) | |
1880 | invariant_p = MEM_READONLY_P (x); | |
1881 | else if (function_invariant_p (x)) | |
1882 | { | |
1883 | if (GET_CODE (x) == PLUS | |
1884 | || x == frame_pointer_rtx || x == arg_pointer_rtx) | |
1885 | invariant_p = true; | |
1886 | else | |
1887 | constant = x; | |
1888 | } | |
1889 | } | |
1890 | } | |
1891 | ira_reg_equiv_invariant_p[i] = invariant_p; | |
1892 | ira_reg_equiv_const[i] = constant; | |
1893 | } | |
1894 | } | |
1895 | ||
1896 | \f | |
1897 | ||
2af2dbdc VM |
1898 | /* Vector of substitutions of register numbers, |
1899 | used to map pseudo regs into hardware regs. | |
1900 | This is set up as a result of register allocation. | |
1901 | Element N is the hard reg assigned to pseudo reg N, | |
1902 | or is -1 if no hard reg was assigned. | |
1903 | If N is a hard reg number, element N is N. */ | |
1904 | short *reg_renumber; | |
1905 | ||
058e97ec VM |
1906 | /* Set up REG_RENUMBER and CALLER_SAVE_NEEDED (used by reload) from |
1907 | the allocation found by IRA. */ | |
1908 | static void | |
1909 | setup_reg_renumber (void) | |
1910 | { | |
1911 | int regno, hard_regno; | |
1912 | ira_allocno_t a; | |
1913 | ira_allocno_iterator ai; | |
1914 | ||
1915 | caller_save_needed = 0; | |
1916 | FOR_EACH_ALLOCNO (a, ai) | |
1917 | { | |
1918 | /* There are no caps at this point. */ | |
1919 | ira_assert (ALLOCNO_CAP_MEMBER (a) == NULL); | |
1920 | if (! ALLOCNO_ASSIGNED_P (a)) | |
1921 | /* It can happen if A is not referenced but partially anticipated | |
1922 | somewhere in a region. */ | |
1923 | ALLOCNO_ASSIGNED_P (a) = true; | |
1924 | ira_free_allocno_updated_costs (a); | |
1925 | hard_regno = ALLOCNO_HARD_REGNO (a); | |
1756cb66 | 1926 | regno = ALLOCNO_REGNO (a); |
058e97ec | 1927 | reg_renumber[regno] = (hard_regno < 0 ? -1 : hard_regno); |
1756cb66 | 1928 | if (hard_regno >= 0) |
058e97ec | 1929 | { |
1756cb66 VM |
1930 | int i, nwords; |
1931 | enum reg_class pclass; | |
1932 | ira_object_t obj; | |
1933 | ||
1934 | pclass = ira_pressure_class_translate[REGNO_REG_CLASS (hard_regno)]; | |
1935 | nwords = ALLOCNO_NUM_OBJECTS (a); | |
1936 | for (i = 0; i < nwords; i++) | |
1937 | { | |
1938 | obj = ALLOCNO_OBJECT (a, i); | |
1939 | IOR_COMPL_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), | |
1940 | reg_class_contents[pclass]); | |
1941 | } | |
1942 | if (ALLOCNO_CALLS_CROSSED_NUM (a) != 0 | |
9181a6e5 VM |
1943 | && ira_hard_reg_set_intersection_p (hard_regno, ALLOCNO_MODE (a), |
1944 | call_used_reg_set)) | |
1756cb66 VM |
1945 | { |
1946 | ira_assert (!optimize || flag_caller_saves | |
e384e6b5 BS |
1947 | || (ALLOCNO_CALLS_CROSSED_NUM (a) |
1948 | == ALLOCNO_CHEAP_CALLS_CROSSED_NUM (a)) | |
1756cb66 VM |
1949 | || regno >= ira_reg_equiv_len |
1950 | || ira_reg_equiv_const[regno] | |
1951 | || ira_reg_equiv_invariant_p[regno]); | |
1952 | caller_save_needed = 1; | |
1953 | } | |
058e97ec VM |
1954 | } |
1955 | } | |
1956 | } | |
1957 | ||
1958 | /* Set up allocno assignment flags for further allocation | |
1959 | improvements. */ | |
1960 | static void | |
1961 | setup_allocno_assignment_flags (void) | |
1962 | { | |
1963 | int hard_regno; | |
1964 | ira_allocno_t a; | |
1965 | ira_allocno_iterator ai; | |
1966 | ||
1967 | FOR_EACH_ALLOCNO (a, ai) | |
1968 | { | |
1969 | if (! ALLOCNO_ASSIGNED_P (a)) | |
1970 | /* It can happen if A is not referenced but partially anticipated | |
1971 | somewhere in a region. */ | |
1972 | ira_free_allocno_updated_costs (a); | |
1973 | hard_regno = ALLOCNO_HARD_REGNO (a); | |
1974 | /* Don't assign hard registers to allocnos which are destination | |
1975 | of removed store at the end of loop. It has no sense to keep | |
1976 | the same value in different hard registers. It is also | |
1977 | impossible to assign hard registers correctly to such | |
1978 | allocnos because the cost info and info about intersected | |
1979 | calls are incorrect for them. */ | |
1980 | ALLOCNO_ASSIGNED_P (a) = (hard_regno >= 0 | |
1756cb66 | 1981 | || ALLOCNO_EMIT_DATA (a)->mem_optimized_dest_p |
058e97ec | 1982 | || (ALLOCNO_MEMORY_COST (a) |
1756cb66 | 1983 | - ALLOCNO_CLASS_COST (a)) < 0); |
9181a6e5 VM |
1984 | ira_assert |
1985 | (hard_regno < 0 | |
1986 | || ira_hard_reg_in_set_p (hard_regno, ALLOCNO_MODE (a), | |
1987 | reg_class_contents[ALLOCNO_CLASS (a)])); | |
058e97ec VM |
1988 | } |
1989 | } | |
1990 | ||
1991 | /* Evaluate overall allocation cost and the costs for using hard | |
1992 | registers and memory for allocnos. */ | |
1993 | static void | |
1994 | calculate_allocation_cost (void) | |
1995 | { | |
1996 | int hard_regno, cost; | |
1997 | ira_allocno_t a; | |
1998 | ira_allocno_iterator ai; | |
1999 | ||
2000 | ira_overall_cost = ira_reg_cost = ira_mem_cost = 0; | |
2001 | FOR_EACH_ALLOCNO (a, ai) | |
2002 | { | |
2003 | hard_regno = ALLOCNO_HARD_REGNO (a); | |
2004 | ira_assert (hard_regno < 0 | |
9181a6e5 VM |
2005 | || (ira_hard_reg_in_set_p |
2006 | (hard_regno, ALLOCNO_MODE (a), | |
2007 | reg_class_contents[ALLOCNO_CLASS (a)]))); | |
058e97ec VM |
2008 | if (hard_regno < 0) |
2009 | { | |
2010 | cost = ALLOCNO_MEMORY_COST (a); | |
2011 | ira_mem_cost += cost; | |
2012 | } | |
2013 | else if (ALLOCNO_HARD_REG_COSTS (a) != NULL) | |
2014 | { | |
2015 | cost = (ALLOCNO_HARD_REG_COSTS (a) | |
2016 | [ira_class_hard_reg_index | |
1756cb66 | 2017 | [ALLOCNO_CLASS (a)][hard_regno]]); |
058e97ec VM |
2018 | ira_reg_cost += cost; |
2019 | } | |
2020 | else | |
2021 | { | |
1756cb66 | 2022 | cost = ALLOCNO_CLASS_COST (a); |
058e97ec VM |
2023 | ira_reg_cost += cost; |
2024 | } | |
2025 | ira_overall_cost += cost; | |
2026 | } | |
2027 | ||
2028 | if (internal_flag_ira_verbose > 0 && ira_dump_file != NULL) | |
2029 | { | |
2030 | fprintf (ira_dump_file, | |
2031 | "+++Costs: overall %d, reg %d, mem %d, ld %d, st %d, move %d\n", | |
2032 | ira_overall_cost, ira_reg_cost, ira_mem_cost, | |
2033 | ira_load_cost, ira_store_cost, ira_shuffle_cost); | |
2034 | fprintf (ira_dump_file, "+++ move loops %d, new jumps %d\n", | |
2035 | ira_move_loops_num, ira_additional_jumps_num); | |
2036 | } | |
2037 | ||
2038 | } | |
2039 | ||
2040 | #ifdef ENABLE_IRA_CHECKING | |
2041 | /* Check the correctness of the allocation. We do need this because | |
2042 | of complicated code to transform more one region internal | |
2043 | representation into one region representation. */ | |
2044 | static void | |
2045 | check_allocation (void) | |
2046 | { | |
fa86d337 | 2047 | ira_allocno_t a; |
ac0ab4f7 | 2048 | int hard_regno, nregs, conflict_nregs; |
058e97ec VM |
2049 | ira_allocno_iterator ai; |
2050 | ||
2051 | FOR_EACH_ALLOCNO (a, ai) | |
2052 | { | |
ac0ab4f7 BS |
2053 | int n = ALLOCNO_NUM_OBJECTS (a); |
2054 | int i; | |
fa86d337 | 2055 | |
058e97ec VM |
2056 | if (ALLOCNO_CAP_MEMBER (a) != NULL |
2057 | || (hard_regno = ALLOCNO_HARD_REGNO (a)) < 0) | |
2058 | continue; | |
2059 | nregs = hard_regno_nregs[hard_regno][ALLOCNO_MODE (a)]; | |
8cfd82bf BS |
2060 | if (nregs == 1) |
2061 | /* We allocated a single hard register. */ | |
2062 | n = 1; | |
2063 | else if (n > 1) | |
2064 | /* We allocated multiple hard registers, and we will test | |
2065 | conflicts in a granularity of single hard regs. */ | |
2066 | nregs = 1; | |
2067 | ||
ac0ab4f7 BS |
2068 | for (i = 0; i < n; i++) |
2069 | { | |
2070 | ira_object_t obj = ALLOCNO_OBJECT (a, i); | |
2071 | ira_object_t conflict_obj; | |
2072 | ira_object_conflict_iterator oci; | |
2073 | int this_regno = hard_regno; | |
2074 | if (n > 1) | |
fa86d337 | 2075 | { |
2805e6c0 | 2076 | if (REG_WORDS_BIG_ENDIAN) |
ac0ab4f7 BS |
2077 | this_regno += n - i - 1; |
2078 | else | |
2079 | this_regno += i; | |
2080 | } | |
2081 | FOR_EACH_OBJECT_CONFLICT (obj, conflict_obj, oci) | |
2082 | { | |
2083 | ira_allocno_t conflict_a = OBJECT_ALLOCNO (conflict_obj); | |
2084 | int conflict_hard_regno = ALLOCNO_HARD_REGNO (conflict_a); | |
2085 | if (conflict_hard_regno < 0) | |
2086 | continue; | |
8cfd82bf BS |
2087 | |
2088 | conflict_nregs | |
2089 | = (hard_regno_nregs | |
2090 | [conflict_hard_regno][ALLOCNO_MODE (conflict_a)]); | |
2091 | ||
2092 | if (ALLOCNO_NUM_OBJECTS (conflict_a) > 1 | |
2093 | && conflict_nregs == ALLOCNO_NUM_OBJECTS (conflict_a)) | |
ac0ab4f7 | 2094 | { |
2805e6c0 | 2095 | if (REG_WORDS_BIG_ENDIAN) |
ac0ab4f7 BS |
2096 | conflict_hard_regno += (ALLOCNO_NUM_OBJECTS (conflict_a) |
2097 | - OBJECT_SUBWORD (conflict_obj) - 1); | |
2098 | else | |
2099 | conflict_hard_regno += OBJECT_SUBWORD (conflict_obj); | |
2100 | conflict_nregs = 1; | |
2101 | } | |
ac0ab4f7 BS |
2102 | |
2103 | if ((conflict_hard_regno <= this_regno | |
2104 | && this_regno < conflict_hard_regno + conflict_nregs) | |
2105 | || (this_regno <= conflict_hard_regno | |
2106 | && conflict_hard_regno < this_regno + nregs)) | |
fa86d337 BS |
2107 | { |
2108 | fprintf (stderr, "bad allocation for %d and %d\n", | |
2109 | ALLOCNO_REGNO (a), ALLOCNO_REGNO (conflict_a)); | |
2110 | gcc_unreachable (); | |
2111 | } | |
2112 | } | |
2113 | } | |
058e97ec VM |
2114 | } |
2115 | } | |
2116 | #endif | |
2117 | ||
2118 | /* Fix values of array REG_EQUIV_INIT after live range splitting done | |
2119 | by IRA. */ | |
2120 | static void | |
2121 | fix_reg_equiv_init (void) | |
2122 | { | |
f2034d06 JL |
2123 | unsigned int max_regno = max_reg_num (); |
2124 | int i, new_regno, max; | |
058e97ec | 2125 | rtx x, prev, next, insn, set; |
b8698a0f | 2126 | |
f2034d06 | 2127 | if (VEC_length (reg_equivs_t, reg_equivs) < max_regno) |
058e97ec | 2128 | { |
f2034d06 JL |
2129 | max = VEC_length (reg_equivs_t, reg_equivs); |
2130 | grow_reg_equivs (); | |
2131 | for (i = FIRST_PSEUDO_REGISTER; i < max; i++) | |
2132 | for (prev = NULL_RTX, x = reg_equiv_init (i); | |
2133 | x != NULL_RTX; | |
2134 | x = next) | |
058e97ec VM |
2135 | { |
2136 | next = XEXP (x, 1); | |
2137 | insn = XEXP (x, 0); | |
2138 | set = single_set (insn); | |
2139 | ira_assert (set != NULL_RTX | |
2140 | && (REG_P (SET_DEST (set)) || REG_P (SET_SRC (set)))); | |
2141 | if (REG_P (SET_DEST (set)) | |
2142 | && ((int) REGNO (SET_DEST (set)) == i | |
2143 | || (int) ORIGINAL_REGNO (SET_DEST (set)) == i)) | |
2144 | new_regno = REGNO (SET_DEST (set)); | |
2145 | else if (REG_P (SET_SRC (set)) | |
2146 | && ((int) REGNO (SET_SRC (set)) == i | |
2147 | || (int) ORIGINAL_REGNO (SET_SRC (set)) == i)) | |
2148 | new_regno = REGNO (SET_SRC (set)); | |
2149 | else | |
2150 | gcc_unreachable (); | |
2151 | if (new_regno == i) | |
2152 | prev = x; | |
2153 | else | |
2154 | { | |
2155 | if (prev == NULL_RTX) | |
f2034d06 | 2156 | reg_equiv_init (i) = next; |
058e97ec VM |
2157 | else |
2158 | XEXP (prev, 1) = next; | |
f2034d06 JL |
2159 | XEXP (x, 1) = reg_equiv_init (new_regno); |
2160 | reg_equiv_init (new_regno) = x; | |
058e97ec VM |
2161 | } |
2162 | } | |
2163 | } | |
2164 | } | |
2165 | ||
2166 | #ifdef ENABLE_IRA_CHECKING | |
2167 | /* Print redundant memory-memory copies. */ | |
2168 | static void | |
2169 | print_redundant_copies (void) | |
2170 | { | |
2171 | int hard_regno; | |
2172 | ira_allocno_t a; | |
2173 | ira_copy_t cp, next_cp; | |
2174 | ira_allocno_iterator ai; | |
b8698a0f | 2175 | |
058e97ec VM |
2176 | FOR_EACH_ALLOCNO (a, ai) |
2177 | { | |
2178 | if (ALLOCNO_CAP_MEMBER (a) != NULL) | |
2179 | /* It is a cap. */ | |
2180 | continue; | |
2181 | hard_regno = ALLOCNO_HARD_REGNO (a); | |
2182 | if (hard_regno >= 0) | |
2183 | continue; | |
2184 | for (cp = ALLOCNO_COPIES (a); cp != NULL; cp = next_cp) | |
2185 | if (cp->first == a) | |
2186 | next_cp = cp->next_first_allocno_copy; | |
2187 | else | |
2188 | { | |
2189 | next_cp = cp->next_second_allocno_copy; | |
2190 | if (internal_flag_ira_verbose > 4 && ira_dump_file != NULL | |
2191 | && cp->insn != NULL_RTX | |
2192 | && ALLOCNO_HARD_REGNO (cp->first) == hard_regno) | |
2193 | fprintf (ira_dump_file, | |
2194 | " Redundant move from %d(freq %d):%d\n", | |
2195 | INSN_UID (cp->insn), cp->freq, hard_regno); | |
2196 | } | |
2197 | } | |
2198 | } | |
2199 | #endif | |
2200 | ||
2201 | /* Setup preferred and alternative classes for new pseudo-registers | |
2202 | created by IRA starting with START. */ | |
2203 | static void | |
2204 | setup_preferred_alternate_classes_for_new_pseudos (int start) | |
2205 | { | |
2206 | int i, old_regno; | |
2207 | int max_regno = max_reg_num (); | |
2208 | ||
2209 | for (i = start; i < max_regno; i++) | |
2210 | { | |
2211 | old_regno = ORIGINAL_REGNO (regno_reg_rtx[i]); | |
b8698a0f | 2212 | ira_assert (i != old_regno); |
058e97ec | 2213 | setup_reg_classes (i, reg_preferred_class (old_regno), |
ce18efcb | 2214 | reg_alternate_class (old_regno), |
1756cb66 | 2215 | reg_allocno_class (old_regno)); |
058e97ec VM |
2216 | if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL) |
2217 | fprintf (ira_dump_file, | |
2218 | " New r%d: setting preferred %s, alternative %s\n", | |
2219 | i, reg_class_names[reg_preferred_class (old_regno)], | |
2220 | reg_class_names[reg_alternate_class (old_regno)]); | |
2221 | } | |
2222 | } | |
2223 | ||
2224 | \f | |
fb99ee9b BS |
2225 | /* The number of entries allocated in teg_info. */ |
2226 | static int allocated_reg_info_size; | |
058e97ec VM |
2227 | |
2228 | /* Regional allocation can create new pseudo-registers. This function | |
2229 | expands some arrays for pseudo-registers. */ | |
2230 | static void | |
fb99ee9b | 2231 | expand_reg_info (void) |
058e97ec VM |
2232 | { |
2233 | int i; | |
2234 | int size = max_reg_num (); | |
2235 | ||
2236 | resize_reg_info (); | |
fb99ee9b | 2237 | for (i = allocated_reg_info_size; i < size; i++) |
ce18efcb | 2238 | setup_reg_classes (i, GENERAL_REGS, ALL_REGS, GENERAL_REGS); |
fb99ee9b BS |
2239 | setup_preferred_alternate_classes_for_new_pseudos (allocated_reg_info_size); |
2240 | allocated_reg_info_size = size; | |
058e97ec VM |
2241 | } |
2242 | ||
3553f0bb VM |
2243 | /* Return TRUE if there is too high register pressure in the function. |
2244 | It is used to decide when stack slot sharing is worth to do. */ | |
2245 | static bool | |
2246 | too_high_register_pressure_p (void) | |
2247 | { | |
2248 | int i; | |
1756cb66 | 2249 | enum reg_class pclass; |
b8698a0f | 2250 | |
1756cb66 | 2251 | for (i = 0; i < ira_pressure_classes_num; i++) |
3553f0bb | 2252 | { |
1756cb66 VM |
2253 | pclass = ira_pressure_classes[i]; |
2254 | if (ira_loop_tree_root->reg_pressure[pclass] > 10000) | |
3553f0bb VM |
2255 | return true; |
2256 | } | |
2257 | return false; | |
2258 | } | |
2259 | ||
058e97ec VM |
2260 | \f |
2261 | ||
2af2dbdc VM |
2262 | /* Indicate that hard register number FROM was eliminated and replaced with |
2263 | an offset from hard register number TO. The status of hard registers live | |
2264 | at the start of a basic block is updated by replacing a use of FROM with | |
2265 | a use of TO. */ | |
2266 | ||
2267 | void | |
2268 | mark_elimination (int from, int to) | |
2269 | { | |
2270 | basic_block bb; | |
2271 | ||
2272 | FOR_EACH_BB (bb) | |
2273 | { | |
2274 | /* We don't use LIVE info in IRA. */ | |
7a8cba34 | 2275 | bitmap r = DF_LR_IN (bb); |
2af2dbdc VM |
2276 | |
2277 | if (REGNO_REG_SET_P (r, from)) | |
2278 | { | |
2279 | CLEAR_REGNO_REG_SET (r, from); | |
2280 | SET_REGNO_REG_SET (r, to); | |
2281 | } | |
2282 | } | |
2283 | } | |
2284 | ||
2285 | \f | |
2286 | ||
2287 | struct equivalence | |
2288 | { | |
2af2dbdc VM |
2289 | /* Set when a REG_EQUIV note is found or created. Use to |
2290 | keep track of what memory accesses might be created later, | |
2291 | e.g. by reload. */ | |
2292 | rtx replacement; | |
2293 | rtx *src_p; | |
8f5929e1 JJ |
2294 | /* The list of each instruction which initializes this register. */ |
2295 | rtx init_insns; | |
2af2dbdc VM |
2296 | /* Loop depth is used to recognize equivalences which appear |
2297 | to be present within the same loop (or in an inner loop). */ | |
2298 | int loop_depth; | |
2af2dbdc VM |
2299 | /* Nonzero if this had a preexisting REG_EQUIV note. */ |
2300 | int is_arg_equivalence; | |
8f5929e1 JJ |
2301 | /* Set when an attempt should be made to replace a register |
2302 | with the associated src_p entry. */ | |
2303 | char replace; | |
2af2dbdc VM |
2304 | }; |
2305 | ||
2306 | /* reg_equiv[N] (where N is a pseudo reg number) is the equivalence | |
2307 | structure for that register. */ | |
2308 | static struct equivalence *reg_equiv; | |
2309 | ||
2310 | /* Used for communication between the following two functions: contains | |
2311 | a MEM that we wish to ensure remains unchanged. */ | |
2312 | static rtx equiv_mem; | |
2313 | ||
2314 | /* Set nonzero if EQUIV_MEM is modified. */ | |
2315 | static int equiv_mem_modified; | |
2316 | ||
2317 | /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified. | |
2318 | Called via note_stores. */ | |
2319 | static void | |
2320 | validate_equiv_mem_from_store (rtx dest, const_rtx set ATTRIBUTE_UNUSED, | |
2321 | void *data ATTRIBUTE_UNUSED) | |
2322 | { | |
2323 | if ((REG_P (dest) | |
2324 | && reg_overlap_mentioned_p (dest, equiv_mem)) | |
2325 | || (MEM_P (dest) | |
53d9622b | 2326 | && true_dependence (dest, VOIDmode, equiv_mem))) |
2af2dbdc VM |
2327 | equiv_mem_modified = 1; |
2328 | } | |
2329 | ||
2330 | /* Verify that no store between START and the death of REG invalidates | |
2331 | MEMREF. MEMREF is invalidated by modifying a register used in MEMREF, | |
2332 | by storing into an overlapping memory location, or with a non-const | |
2333 | CALL_INSN. | |
2334 | ||
2335 | Return 1 if MEMREF remains valid. */ | |
2336 | static int | |
2337 | validate_equiv_mem (rtx start, rtx reg, rtx memref) | |
2338 | { | |
2339 | rtx insn; | |
2340 | rtx note; | |
2341 | ||
2342 | equiv_mem = memref; | |
2343 | equiv_mem_modified = 0; | |
2344 | ||
2345 | /* If the memory reference has side effects or is volatile, it isn't a | |
2346 | valid equivalence. */ | |
2347 | if (side_effects_p (memref)) | |
2348 | return 0; | |
2349 | ||
2350 | for (insn = start; insn && ! equiv_mem_modified; insn = NEXT_INSN (insn)) | |
2351 | { | |
2352 | if (! INSN_P (insn)) | |
2353 | continue; | |
2354 | ||
2355 | if (find_reg_note (insn, REG_DEAD, reg)) | |
2356 | return 1; | |
2357 | ||
a22265a4 JL |
2358 | /* This used to ignore readonly memory and const/pure calls. The problem |
2359 | is the equivalent form may reference a pseudo which gets assigned a | |
2360 | call clobbered hard reg. When we later replace REG with its | |
2361 | equivalent form, the value in the call-clobbered reg has been | |
2362 | changed and all hell breaks loose. */ | |
2363 | if (CALL_P (insn)) | |
2af2dbdc VM |
2364 | return 0; |
2365 | ||
2366 | note_stores (PATTERN (insn), validate_equiv_mem_from_store, NULL); | |
2367 | ||
2368 | /* If a register mentioned in MEMREF is modified via an | |
2369 | auto-increment, we lose the equivalence. Do the same if one | |
2370 | dies; although we could extend the life, it doesn't seem worth | |
2371 | the trouble. */ | |
2372 | ||
2373 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
2374 | if ((REG_NOTE_KIND (note) == REG_INC | |
2375 | || REG_NOTE_KIND (note) == REG_DEAD) | |
2376 | && REG_P (XEXP (note, 0)) | |
2377 | && reg_overlap_mentioned_p (XEXP (note, 0), memref)) | |
2378 | return 0; | |
2379 | } | |
2380 | ||
2381 | return 0; | |
2382 | } | |
2383 | ||
2384 | /* Returns zero if X is known to be invariant. */ | |
2385 | static int | |
2386 | equiv_init_varies_p (rtx x) | |
2387 | { | |
2388 | RTX_CODE code = GET_CODE (x); | |
2389 | int i; | |
2390 | const char *fmt; | |
2391 | ||
2392 | switch (code) | |
2393 | { | |
2394 | case MEM: | |
2395 | return !MEM_READONLY_P (x) || equiv_init_varies_p (XEXP (x, 0)); | |
2396 | ||
2397 | case CONST: | |
2398 | case CONST_INT: | |
2399 | case CONST_DOUBLE: | |
2400 | case CONST_FIXED: | |
2401 | case CONST_VECTOR: | |
2402 | case SYMBOL_REF: | |
2403 | case LABEL_REF: | |
2404 | return 0; | |
2405 | ||
2406 | case REG: | |
2407 | return reg_equiv[REGNO (x)].replace == 0 && rtx_varies_p (x, 0); | |
2408 | ||
2409 | case ASM_OPERANDS: | |
2410 | if (MEM_VOLATILE_P (x)) | |
2411 | return 1; | |
2412 | ||
2413 | /* Fall through. */ | |
2414 | ||
2415 | default: | |
2416 | break; | |
2417 | } | |
2418 | ||
2419 | fmt = GET_RTX_FORMAT (code); | |
2420 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2421 | if (fmt[i] == 'e') | |
2422 | { | |
2423 | if (equiv_init_varies_p (XEXP (x, i))) | |
2424 | return 1; | |
2425 | } | |
2426 | else if (fmt[i] == 'E') | |
2427 | { | |
2428 | int j; | |
2429 | for (j = 0; j < XVECLEN (x, i); j++) | |
2430 | if (equiv_init_varies_p (XVECEXP (x, i, j))) | |
2431 | return 1; | |
2432 | } | |
2433 | ||
2434 | return 0; | |
2435 | } | |
2436 | ||
2437 | /* Returns nonzero if X (used to initialize register REGNO) is movable. | |
2438 | X is only movable if the registers it uses have equivalent initializations | |
2439 | which appear to be within the same loop (or in an inner loop) and movable | |
2440 | or if they are not candidates for local_alloc and don't vary. */ | |
2441 | static int | |
2442 | equiv_init_movable_p (rtx x, int regno) | |
2443 | { | |
2444 | int i, j; | |
2445 | const char *fmt; | |
2446 | enum rtx_code code = GET_CODE (x); | |
2447 | ||
2448 | switch (code) | |
2449 | { | |
2450 | case SET: | |
2451 | return equiv_init_movable_p (SET_SRC (x), regno); | |
2452 | ||
2453 | case CC0: | |
2454 | case CLOBBER: | |
2455 | return 0; | |
2456 | ||
2457 | case PRE_INC: | |
2458 | case PRE_DEC: | |
2459 | case POST_INC: | |
2460 | case POST_DEC: | |
2461 | case PRE_MODIFY: | |
2462 | case POST_MODIFY: | |
2463 | return 0; | |
2464 | ||
2465 | case REG: | |
1756cb66 VM |
2466 | return ((reg_equiv[REGNO (x)].loop_depth >= reg_equiv[regno].loop_depth |
2467 | && reg_equiv[REGNO (x)].replace) | |
2468 | || (REG_BASIC_BLOCK (REGNO (x)) < NUM_FIXED_BLOCKS | |
2469 | && ! rtx_varies_p (x, 0))); | |
2af2dbdc VM |
2470 | |
2471 | case UNSPEC_VOLATILE: | |
2472 | return 0; | |
2473 | ||
2474 | case ASM_OPERANDS: | |
2475 | if (MEM_VOLATILE_P (x)) | |
2476 | return 0; | |
2477 | ||
2478 | /* Fall through. */ | |
2479 | ||
2480 | default: | |
2481 | break; | |
2482 | } | |
2483 | ||
2484 | fmt = GET_RTX_FORMAT (code); | |
2485 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2486 | switch (fmt[i]) | |
2487 | { | |
2488 | case 'e': | |
2489 | if (! equiv_init_movable_p (XEXP (x, i), regno)) | |
2490 | return 0; | |
2491 | break; | |
2492 | case 'E': | |
2493 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
2494 | if (! equiv_init_movable_p (XVECEXP (x, i, j), regno)) | |
2495 | return 0; | |
2496 | break; | |
2497 | } | |
2498 | ||
2499 | return 1; | |
2500 | } | |
2501 | ||
1756cb66 VM |
2502 | /* TRUE if X uses any registers for which reg_equiv[REGNO].replace is |
2503 | true. */ | |
2af2dbdc VM |
2504 | static int |
2505 | contains_replace_regs (rtx x) | |
2506 | { | |
2507 | int i, j; | |
2508 | const char *fmt; | |
2509 | enum rtx_code code = GET_CODE (x); | |
2510 | ||
2511 | switch (code) | |
2512 | { | |
2513 | case CONST_INT: | |
2514 | case CONST: | |
2515 | case LABEL_REF: | |
2516 | case SYMBOL_REF: | |
2517 | case CONST_DOUBLE: | |
2518 | case CONST_FIXED: | |
2519 | case CONST_VECTOR: | |
2520 | case PC: | |
2521 | case CC0: | |
2522 | case HIGH: | |
2523 | return 0; | |
2524 | ||
2525 | case REG: | |
2526 | return reg_equiv[REGNO (x)].replace; | |
2527 | ||
2528 | default: | |
2529 | break; | |
2530 | } | |
2531 | ||
2532 | fmt = GET_RTX_FORMAT (code); | |
2533 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2534 | switch (fmt[i]) | |
2535 | { | |
2536 | case 'e': | |
2537 | if (contains_replace_regs (XEXP (x, i))) | |
2538 | return 1; | |
2539 | break; | |
2540 | case 'E': | |
2541 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
2542 | if (contains_replace_regs (XVECEXP (x, i, j))) | |
2543 | return 1; | |
2544 | break; | |
2545 | } | |
2546 | ||
2547 | return 0; | |
2548 | } | |
2549 | ||
2550 | /* TRUE if X references a memory location that would be affected by a store | |
2551 | to MEMREF. */ | |
2552 | static int | |
2553 | memref_referenced_p (rtx memref, rtx x) | |
2554 | { | |
2555 | int i, j; | |
2556 | const char *fmt; | |
2557 | enum rtx_code code = GET_CODE (x); | |
2558 | ||
2559 | switch (code) | |
2560 | { | |
2561 | case CONST_INT: | |
2562 | case CONST: | |
2563 | case LABEL_REF: | |
2564 | case SYMBOL_REF: | |
2565 | case CONST_DOUBLE: | |
2566 | case CONST_FIXED: | |
2567 | case CONST_VECTOR: | |
2568 | case PC: | |
2569 | case CC0: | |
2570 | case HIGH: | |
2571 | case LO_SUM: | |
2572 | return 0; | |
2573 | ||
2574 | case REG: | |
2575 | return (reg_equiv[REGNO (x)].replacement | |
2576 | && memref_referenced_p (memref, | |
2577 | reg_equiv[REGNO (x)].replacement)); | |
2578 | ||
2579 | case MEM: | |
53d9622b | 2580 | if (true_dependence (memref, VOIDmode, x)) |
2af2dbdc VM |
2581 | return 1; |
2582 | break; | |
2583 | ||
2584 | case SET: | |
2585 | /* If we are setting a MEM, it doesn't count (its address does), but any | |
2586 | other SET_DEST that has a MEM in it is referencing the MEM. */ | |
2587 | if (MEM_P (SET_DEST (x))) | |
2588 | { | |
2589 | if (memref_referenced_p (memref, XEXP (SET_DEST (x), 0))) | |
2590 | return 1; | |
2591 | } | |
2592 | else if (memref_referenced_p (memref, SET_DEST (x))) | |
2593 | return 1; | |
2594 | ||
2595 | return memref_referenced_p (memref, SET_SRC (x)); | |
2596 | ||
2597 | default: | |
2598 | break; | |
2599 | } | |
2600 | ||
2601 | fmt = GET_RTX_FORMAT (code); | |
2602 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2603 | switch (fmt[i]) | |
2604 | { | |
2605 | case 'e': | |
2606 | if (memref_referenced_p (memref, XEXP (x, i))) | |
2607 | return 1; | |
2608 | break; | |
2609 | case 'E': | |
2610 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
2611 | if (memref_referenced_p (memref, XVECEXP (x, i, j))) | |
2612 | return 1; | |
2613 | break; | |
2614 | } | |
2615 | ||
2616 | return 0; | |
2617 | } | |
2618 | ||
2619 | /* TRUE if some insn in the range (START, END] references a memory location | |
2620 | that would be affected by a store to MEMREF. */ | |
2621 | static int | |
2622 | memref_used_between_p (rtx memref, rtx start, rtx end) | |
2623 | { | |
2624 | rtx insn; | |
2625 | ||
2626 | for (insn = NEXT_INSN (start); insn != NEXT_INSN (end); | |
2627 | insn = NEXT_INSN (insn)) | |
2628 | { | |
b5b8b0ac | 2629 | if (!NONDEBUG_INSN_P (insn)) |
2af2dbdc | 2630 | continue; |
b8698a0f | 2631 | |
2af2dbdc VM |
2632 | if (memref_referenced_p (memref, PATTERN (insn))) |
2633 | return 1; | |
2634 | ||
2635 | /* Nonconst functions may access memory. */ | |
2636 | if (CALL_P (insn) && (! RTL_CONST_CALL_P (insn))) | |
2637 | return 1; | |
2638 | } | |
2639 | ||
2640 | return 0; | |
2641 | } | |
2642 | ||
2643 | /* Mark REG as having no known equivalence. | |
2644 | Some instructions might have been processed before and furnished | |
2645 | with REG_EQUIV notes for this register; these notes will have to be | |
2646 | removed. | |
2647 | STORE is the piece of RTL that does the non-constant / conflicting | |
2648 | assignment - a SET, CLOBBER or REG_INC note. It is currently not used, | |
2649 | but needs to be there because this function is called from note_stores. */ | |
2650 | static void | |
1756cb66 VM |
2651 | no_equiv (rtx reg, const_rtx store ATTRIBUTE_UNUSED, |
2652 | void *data ATTRIBUTE_UNUSED) | |
2af2dbdc VM |
2653 | { |
2654 | int regno; | |
2655 | rtx list; | |
2656 | ||
2657 | if (!REG_P (reg)) | |
2658 | return; | |
2659 | regno = REGNO (reg); | |
2660 | list = reg_equiv[regno].init_insns; | |
2661 | if (list == const0_rtx) | |
2662 | return; | |
2663 | reg_equiv[regno].init_insns = const0_rtx; | |
2664 | reg_equiv[regno].replacement = NULL_RTX; | |
2665 | /* This doesn't matter for equivalences made for argument registers, we | |
2666 | should keep their initialization insns. */ | |
2667 | if (reg_equiv[regno].is_arg_equivalence) | |
2668 | return; | |
f2034d06 | 2669 | reg_equiv_init (regno) = NULL_RTX; |
2af2dbdc VM |
2670 | for (; list; list = XEXP (list, 1)) |
2671 | { | |
2672 | rtx insn = XEXP (list, 0); | |
2673 | remove_note (insn, find_reg_note (insn, REG_EQUIV, NULL_RTX)); | |
2674 | } | |
2675 | } | |
2676 | ||
3a6191b1 JJ |
2677 | /* In DEBUG_INSN location adjust REGs from CLEARED_REGS bitmap to the |
2678 | equivalent replacement. */ | |
2679 | ||
2680 | static rtx | |
2681 | adjust_cleared_regs (rtx loc, const_rtx old_rtx ATTRIBUTE_UNUSED, void *data) | |
2682 | { | |
2683 | if (REG_P (loc)) | |
2684 | { | |
2685 | bitmap cleared_regs = (bitmap) data; | |
2686 | if (bitmap_bit_p (cleared_regs, REGNO (loc))) | |
2687 | return simplify_replace_fn_rtx (*reg_equiv[REGNO (loc)].src_p, | |
2688 | NULL_RTX, adjust_cleared_regs, data); | |
2689 | } | |
2690 | return NULL_RTX; | |
2691 | } | |
2692 | ||
2af2dbdc VM |
2693 | /* Nonzero if we recorded an equivalence for a LABEL_REF. */ |
2694 | static int recorded_label_ref; | |
2695 | ||
2696 | /* Find registers that are equivalent to a single value throughout the | |
1756cb66 VM |
2697 | compilation (either because they can be referenced in memory or are |
2698 | set once from a single constant). Lower their priority for a | |
2699 | register. | |
2af2dbdc | 2700 | |
1756cb66 VM |
2701 | If such a register is only referenced once, try substituting its |
2702 | value into the using insn. If it succeeds, we can eliminate the | |
2703 | register completely. | |
2af2dbdc VM |
2704 | |
2705 | Initialize the REG_EQUIV_INIT array of initializing insns. | |
2706 | ||
2707 | Return non-zero if jump label rebuilding should be done. */ | |
2708 | static int | |
2709 | update_equiv_regs (void) | |
2710 | { | |
2711 | rtx insn; | |
2712 | basic_block bb; | |
2713 | int loop_depth; | |
2714 | bitmap cleared_regs; | |
b8698a0f | 2715 | |
2af2dbdc VM |
2716 | /* We need to keep track of whether or not we recorded a LABEL_REF so |
2717 | that we know if the jump optimizer needs to be rerun. */ | |
2718 | recorded_label_ref = 0; | |
2719 | ||
2720 | reg_equiv = XCNEWVEC (struct equivalence, max_regno); | |
f2034d06 | 2721 | grow_reg_equivs (); |
2af2dbdc VM |
2722 | |
2723 | init_alias_analysis (); | |
2724 | ||
2725 | /* Scan the insns and find which registers have equivalences. Do this | |
2726 | in a separate scan of the insns because (due to -fcse-follow-jumps) | |
2727 | a register can be set below its use. */ | |
2728 | FOR_EACH_BB (bb) | |
2729 | { | |
2730 | loop_depth = bb->loop_depth; | |
2731 | ||
2732 | for (insn = BB_HEAD (bb); | |
2733 | insn != NEXT_INSN (BB_END (bb)); | |
2734 | insn = NEXT_INSN (insn)) | |
2735 | { | |
2736 | rtx note; | |
2737 | rtx set; | |
2738 | rtx dest, src; | |
2739 | int regno; | |
2740 | ||
2741 | if (! INSN_P (insn)) | |
2742 | continue; | |
2743 | ||
2744 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
2745 | if (REG_NOTE_KIND (note) == REG_INC) | |
2746 | no_equiv (XEXP (note, 0), note, NULL); | |
2747 | ||
2748 | set = single_set (insn); | |
2749 | ||
2750 | /* If this insn contains more (or less) than a single SET, | |
2751 | only mark all destinations as having no known equivalence. */ | |
2752 | if (set == 0) | |
2753 | { | |
2754 | note_stores (PATTERN (insn), no_equiv, NULL); | |
2755 | continue; | |
2756 | } | |
2757 | else if (GET_CODE (PATTERN (insn)) == PARALLEL) | |
2758 | { | |
2759 | int i; | |
2760 | ||
2761 | for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--) | |
2762 | { | |
2763 | rtx part = XVECEXP (PATTERN (insn), 0, i); | |
2764 | if (part != set) | |
2765 | note_stores (part, no_equiv, NULL); | |
2766 | } | |
2767 | } | |
2768 | ||
2769 | dest = SET_DEST (set); | |
2770 | src = SET_SRC (set); | |
2771 | ||
2772 | /* See if this is setting up the equivalence between an argument | |
2773 | register and its stack slot. */ | |
2774 | note = find_reg_note (insn, REG_EQUIV, NULL_RTX); | |
2775 | if (note) | |
2776 | { | |
2777 | gcc_assert (REG_P (dest)); | |
2778 | regno = REGNO (dest); | |
2779 | ||
2780 | /* Note that we don't want to clear reg_equiv_init even if there | |
2781 | are multiple sets of this register. */ | |
2782 | reg_equiv[regno].is_arg_equivalence = 1; | |
2783 | ||
2784 | /* Record for reload that this is an equivalencing insn. */ | |
2785 | if (rtx_equal_p (src, XEXP (note, 0))) | |
f2034d06 JL |
2786 | reg_equiv_init (regno) |
2787 | = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init (regno)); | |
2af2dbdc VM |
2788 | |
2789 | /* Continue normally in case this is a candidate for | |
2790 | replacements. */ | |
2791 | } | |
2792 | ||
2793 | if (!optimize) | |
2794 | continue; | |
2795 | ||
2796 | /* We only handle the case of a pseudo register being set | |
2797 | once, or always to the same value. */ | |
1fe28116 VM |
2798 | /* ??? The mn10200 port breaks if we add equivalences for |
2799 | values that need an ADDRESS_REGS register and set them equivalent | |
2800 | to a MEM of a pseudo. The actual problem is in the over-conservative | |
2801 | handling of INPADDR_ADDRESS / INPUT_ADDRESS / INPUT triples in | |
2802 | calculate_needs, but we traditionally work around this problem | |
2803 | here by rejecting equivalences when the destination is in a register | |
2804 | that's likely spilled. This is fragile, of course, since the | |
2805 | preferred class of a pseudo depends on all instructions that set | |
2806 | or use it. */ | |
2807 | ||
2af2dbdc VM |
2808 | if (!REG_P (dest) |
2809 | || (regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER | |
1fe28116 | 2810 | || reg_equiv[regno].init_insns == const0_rtx |
07b8f0a8 | 2811 | || (targetm.class_likely_spilled_p (reg_preferred_class (regno)) |
1fe28116 | 2812 | && MEM_P (src) && ! reg_equiv[regno].is_arg_equivalence)) |
2af2dbdc VM |
2813 | { |
2814 | /* This might be setting a SUBREG of a pseudo, a pseudo that is | |
2815 | also set somewhere else to a constant. */ | |
2816 | note_stores (set, no_equiv, NULL); | |
2817 | continue; | |
2818 | } | |
2819 | ||
2820 | note = find_reg_note (insn, REG_EQUAL, NULL_RTX); | |
2821 | ||
2822 | /* cse sometimes generates function invariants, but doesn't put a | |
2823 | REG_EQUAL note on the insn. Since this note would be redundant, | |
2824 | there's no point creating it earlier than here. */ | |
2825 | if (! note && ! rtx_varies_p (src, 0)) | |
2826 | note = set_unique_reg_note (insn, REG_EQUAL, copy_rtx (src)); | |
2827 | ||
2828 | /* Don't bother considering a REG_EQUAL note containing an EXPR_LIST | |
2829 | since it represents a function call */ | |
2830 | if (note && GET_CODE (XEXP (note, 0)) == EXPR_LIST) | |
2831 | note = NULL_RTX; | |
2832 | ||
2833 | if (DF_REG_DEF_COUNT (regno) != 1 | |
2834 | && (! note | |
2835 | || rtx_varies_p (XEXP (note, 0), 0) | |
2836 | || (reg_equiv[regno].replacement | |
2837 | && ! rtx_equal_p (XEXP (note, 0), | |
2838 | reg_equiv[regno].replacement)))) | |
2839 | { | |
2840 | no_equiv (dest, set, NULL); | |
2841 | continue; | |
2842 | } | |
2843 | /* Record this insn as initializing this register. */ | |
2844 | reg_equiv[regno].init_insns | |
2845 | = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv[regno].init_insns); | |
2846 | ||
2847 | /* If this register is known to be equal to a constant, record that | |
2848 | it is always equivalent to the constant. */ | |
2849 | if (DF_REG_DEF_COUNT (regno) == 1 | |
2850 | && note && ! rtx_varies_p (XEXP (note, 0), 0)) | |
2851 | { | |
2852 | rtx note_value = XEXP (note, 0); | |
2853 | remove_note (insn, note); | |
2854 | set_unique_reg_note (insn, REG_EQUIV, note_value); | |
2855 | } | |
2856 | ||
2857 | /* If this insn introduces a "constant" register, decrease the priority | |
2858 | of that register. Record this insn if the register is only used once | |
2859 | more and the equivalence value is the same as our source. | |
2860 | ||
2861 | The latter condition is checked for two reasons: First, it is an | |
2862 | indication that it may be more efficient to actually emit the insn | |
2863 | as written (if no registers are available, reload will substitute | |
2864 | the equivalence). Secondly, it avoids problems with any registers | |
2865 | dying in this insn whose death notes would be missed. | |
2866 | ||
2867 | If we don't have a REG_EQUIV note, see if this insn is loading | |
2868 | a register used only in one basic block from a MEM. If so, and the | |
2869 | MEM remains unchanged for the life of the register, add a REG_EQUIV | |
2870 | note. */ | |
2871 | ||
2872 | note = find_reg_note (insn, REG_EQUIV, NULL_RTX); | |
2873 | ||
2874 | if (note == 0 && REG_BASIC_BLOCK (regno) >= NUM_FIXED_BLOCKS | |
2875 | && MEM_P (SET_SRC (set)) | |
2876 | && validate_equiv_mem (insn, dest, SET_SRC (set))) | |
2877 | note = set_unique_reg_note (insn, REG_EQUIV, copy_rtx (SET_SRC (set))); | |
2878 | ||
2879 | if (note) | |
2880 | { | |
2881 | int regno = REGNO (dest); | |
2882 | rtx x = XEXP (note, 0); | |
2883 | ||
2884 | /* If we haven't done so, record for reload that this is an | |
2885 | equivalencing insn. */ | |
2886 | if (!reg_equiv[regno].is_arg_equivalence) | |
f2034d06 JL |
2887 | reg_equiv_init (regno) |
2888 | = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init (regno)); | |
2af2dbdc VM |
2889 | |
2890 | /* Record whether or not we created a REG_EQUIV note for a LABEL_REF. | |
2891 | We might end up substituting the LABEL_REF for uses of the | |
2892 | pseudo here or later. That kind of transformation may turn an | |
2893 | indirect jump into a direct jump, in which case we must rerun the | |
2894 | jump optimizer to ensure that the JUMP_LABEL fields are valid. */ | |
2895 | if (GET_CODE (x) == LABEL_REF | |
2896 | || (GET_CODE (x) == CONST | |
2897 | && GET_CODE (XEXP (x, 0)) == PLUS | |
2898 | && (GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF))) | |
2899 | recorded_label_ref = 1; | |
2900 | ||
2901 | reg_equiv[regno].replacement = x; | |
2902 | reg_equiv[regno].src_p = &SET_SRC (set); | |
2903 | reg_equiv[regno].loop_depth = loop_depth; | |
2904 | ||
2905 | /* Don't mess with things live during setjmp. */ | |
2906 | if (REG_LIVE_LENGTH (regno) >= 0 && optimize) | |
2907 | { | |
2908 | /* Note that the statement below does not affect the priority | |
2909 | in local-alloc! */ | |
2910 | REG_LIVE_LENGTH (regno) *= 2; | |
2911 | ||
2912 | /* If the register is referenced exactly twice, meaning it is | |
2913 | set once and used once, indicate that the reference may be | |
2914 | replaced by the equivalence we computed above. Do this | |
2915 | even if the register is only used in one block so that | |
2916 | dependencies can be handled where the last register is | |
2917 | used in a different block (i.e. HIGH / LO_SUM sequences) | |
2918 | and to reduce the number of registers alive across | |
2919 | calls. */ | |
2920 | ||
2921 | if (REG_N_REFS (regno) == 2 | |
2922 | && (rtx_equal_p (x, src) | |
2923 | || ! equiv_init_varies_p (src)) | |
2924 | && NONJUMP_INSN_P (insn) | |
2925 | && equiv_init_movable_p (PATTERN (insn), regno)) | |
2926 | reg_equiv[regno].replace = 1; | |
2927 | } | |
2928 | } | |
2929 | } | |
2930 | } | |
2931 | ||
2932 | if (!optimize) | |
2933 | goto out; | |
2934 | ||
2935 | /* A second pass, to gather additional equivalences with memory. This needs | |
2936 | to be done after we know which registers we are going to replace. */ | |
2937 | ||
2938 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
2939 | { | |
2940 | rtx set, src, dest; | |
2941 | unsigned regno; | |
2942 | ||
2943 | if (! INSN_P (insn)) | |
2944 | continue; | |
2945 | ||
2946 | set = single_set (insn); | |
2947 | if (! set) | |
2948 | continue; | |
2949 | ||
2950 | dest = SET_DEST (set); | |
2951 | src = SET_SRC (set); | |
2952 | ||
2953 | /* If this sets a MEM to the contents of a REG that is only used | |
2954 | in a single basic block, see if the register is always equivalent | |
2955 | to that memory location and if moving the store from INSN to the | |
2956 | insn that set REG is safe. If so, put a REG_EQUIV note on the | |
2957 | initializing insn. | |
2958 | ||
2959 | Don't add a REG_EQUIV note if the insn already has one. The existing | |
2960 | REG_EQUIV is likely more useful than the one we are adding. | |
2961 | ||
2962 | If one of the regs in the address has reg_equiv[REGNO].replace set, | |
2963 | then we can't add this REG_EQUIV note. The reg_equiv[REGNO].replace | |
2964 | optimization may move the set of this register immediately before | |
2965 | insn, which puts it after reg_equiv[REGNO].init_insns, and hence | |
2966 | the mention in the REG_EQUIV note would be to an uninitialized | |
2967 | pseudo. */ | |
2968 | ||
2969 | if (MEM_P (dest) && REG_P (src) | |
2970 | && (regno = REGNO (src)) >= FIRST_PSEUDO_REGISTER | |
2971 | && REG_BASIC_BLOCK (regno) >= NUM_FIXED_BLOCKS | |
2972 | && DF_REG_DEF_COUNT (regno) == 1 | |
2973 | && reg_equiv[regno].init_insns != 0 | |
2974 | && reg_equiv[regno].init_insns != const0_rtx | |
2975 | && ! find_reg_note (XEXP (reg_equiv[regno].init_insns, 0), | |
2976 | REG_EQUIV, NULL_RTX) | |
2977 | && ! contains_replace_regs (XEXP (dest, 0))) | |
2978 | { | |
2979 | rtx init_insn = XEXP (reg_equiv[regno].init_insns, 0); | |
2980 | if (validate_equiv_mem (init_insn, src, dest) | |
2981 | && ! memref_used_between_p (dest, init_insn, insn) | |
2982 | /* Attaching a REG_EQUIV note will fail if INIT_INSN has | |
2983 | multiple sets. */ | |
2984 | && set_unique_reg_note (init_insn, REG_EQUIV, copy_rtx (dest))) | |
2985 | { | |
2986 | /* This insn makes the equivalence, not the one initializing | |
2987 | the register. */ | |
f2034d06 | 2988 | reg_equiv_init (regno) |
2af2dbdc VM |
2989 | = gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX); |
2990 | df_notes_rescan (init_insn); | |
2991 | } | |
2992 | } | |
2993 | } | |
2994 | ||
2995 | cleared_regs = BITMAP_ALLOC (NULL); | |
2996 | /* Now scan all regs killed in an insn to see if any of them are | |
2997 | registers only used that once. If so, see if we can replace the | |
2998 | reference with the equivalent form. If we can, delete the | |
2999 | initializing reference and this register will go away. If we | |
3000 | can't replace the reference, and the initializing reference is | |
3001 | within the same loop (or in an inner loop), then move the register | |
3002 | initialization just before the use, so that they are in the same | |
3003 | basic block. */ | |
3004 | FOR_EACH_BB_REVERSE (bb) | |
3005 | { | |
3006 | loop_depth = bb->loop_depth; | |
3007 | for (insn = BB_END (bb); | |
3008 | insn != PREV_INSN (BB_HEAD (bb)); | |
3009 | insn = PREV_INSN (insn)) | |
3010 | { | |
3011 | rtx link; | |
3012 | ||
3013 | if (! INSN_P (insn)) | |
3014 | continue; | |
3015 | ||
3016 | /* Don't substitute into a non-local goto, this confuses CFG. */ | |
3017 | if (JUMP_P (insn) | |
3018 | && find_reg_note (insn, REG_NON_LOCAL_GOTO, NULL_RTX)) | |
3019 | continue; | |
3020 | ||
3021 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | |
3022 | { | |
3023 | if (REG_NOTE_KIND (link) == REG_DEAD | |
3024 | /* Make sure this insn still refers to the register. */ | |
3025 | && reg_mentioned_p (XEXP (link, 0), PATTERN (insn))) | |
3026 | { | |
3027 | int regno = REGNO (XEXP (link, 0)); | |
3028 | rtx equiv_insn; | |
3029 | ||
3030 | if (! reg_equiv[regno].replace | |
0cad4827 VM |
3031 | || reg_equiv[regno].loop_depth < loop_depth |
3032 | /* There is no sense to move insns if we did | |
3033 | register pressure-sensitive scheduling was | |
3034 | done because it will not improve allocation | |
3035 | but worsen insn schedule with a big | |
3036 | probability. */ | |
3037 | || (flag_sched_pressure && flag_schedule_insns)) | |
2af2dbdc VM |
3038 | continue; |
3039 | ||
3040 | /* reg_equiv[REGNO].replace gets set only when | |
3041 | REG_N_REFS[REGNO] is 2, i.e. the register is set | |
3042 | once and used once. (If it were only set, but not used, | |
3043 | flow would have deleted the setting insns.) Hence | |
3044 | there can only be one insn in reg_equiv[REGNO].init_insns. */ | |
3045 | gcc_assert (reg_equiv[regno].init_insns | |
3046 | && !XEXP (reg_equiv[regno].init_insns, 1)); | |
3047 | equiv_insn = XEXP (reg_equiv[regno].init_insns, 0); | |
3048 | ||
3049 | /* We may not move instructions that can throw, since | |
3050 | that changes basic block boundaries and we are not | |
3051 | prepared to adjust the CFG to match. */ | |
3052 | if (can_throw_internal (equiv_insn)) | |
3053 | continue; | |
3054 | ||
3055 | if (asm_noperands (PATTERN (equiv_insn)) < 0 | |
3056 | && validate_replace_rtx (regno_reg_rtx[regno], | |
3057 | *(reg_equiv[regno].src_p), insn)) | |
3058 | { | |
3059 | rtx equiv_link; | |
3060 | rtx last_link; | |
3061 | rtx note; | |
3062 | ||
3063 | /* Find the last note. */ | |
3064 | for (last_link = link; XEXP (last_link, 1); | |
3065 | last_link = XEXP (last_link, 1)) | |
3066 | ; | |
3067 | ||
3068 | /* Append the REG_DEAD notes from equiv_insn. */ | |
3069 | equiv_link = REG_NOTES (equiv_insn); | |
3070 | while (equiv_link) | |
3071 | { | |
3072 | note = equiv_link; | |
3073 | equiv_link = XEXP (equiv_link, 1); | |
3074 | if (REG_NOTE_KIND (note) == REG_DEAD) | |
3075 | { | |
3076 | remove_note (equiv_insn, note); | |
3077 | XEXP (last_link, 1) = note; | |
3078 | XEXP (note, 1) = NULL_RTX; | |
3079 | last_link = note; | |
3080 | } | |
3081 | } | |
3082 | ||
3083 | remove_death (regno, insn); | |
3084 | SET_REG_N_REFS (regno, 0); | |
3085 | REG_FREQ (regno) = 0; | |
3086 | delete_insn (equiv_insn); | |
3087 | ||
3088 | reg_equiv[regno].init_insns | |
3089 | = XEXP (reg_equiv[regno].init_insns, 1); | |
3090 | ||
f2034d06 | 3091 | reg_equiv_init (regno) = NULL_RTX; |
2af2dbdc VM |
3092 | bitmap_set_bit (cleared_regs, regno); |
3093 | } | |
3094 | /* Move the initialization of the register to just before | |
3095 | INSN. Update the flow information. */ | |
b5b8b0ac | 3096 | else if (prev_nondebug_insn (insn) != equiv_insn) |
2af2dbdc VM |
3097 | { |
3098 | rtx new_insn; | |
3099 | ||
3100 | new_insn = emit_insn_before (PATTERN (equiv_insn), insn); | |
3101 | REG_NOTES (new_insn) = REG_NOTES (equiv_insn); | |
3102 | REG_NOTES (equiv_insn) = 0; | |
3103 | /* Rescan it to process the notes. */ | |
3104 | df_insn_rescan (new_insn); | |
3105 | ||
3106 | /* Make sure this insn is recognized before | |
3107 | reload begins, otherwise | |
3108 | eliminate_regs_in_insn will die. */ | |
3109 | INSN_CODE (new_insn) = INSN_CODE (equiv_insn); | |
3110 | ||
3111 | delete_insn (equiv_insn); | |
3112 | ||
3113 | XEXP (reg_equiv[regno].init_insns, 0) = new_insn; | |
3114 | ||
3115 | REG_BASIC_BLOCK (regno) = bb->index; | |
3116 | REG_N_CALLS_CROSSED (regno) = 0; | |
3117 | REG_FREQ_CALLS_CROSSED (regno) = 0; | |
3118 | REG_N_THROWING_CALLS_CROSSED (regno) = 0; | |
3119 | REG_LIVE_LENGTH (regno) = 2; | |
3120 | ||
3121 | if (insn == BB_HEAD (bb)) | |
3122 | BB_HEAD (bb) = PREV_INSN (insn); | |
3123 | ||
f2034d06 | 3124 | reg_equiv_init (regno) |
2af2dbdc VM |
3125 | = gen_rtx_INSN_LIST (VOIDmode, new_insn, NULL_RTX); |
3126 | bitmap_set_bit (cleared_regs, regno); | |
3127 | } | |
3128 | } | |
3129 | } | |
3130 | } | |
3131 | } | |
3132 | ||
3133 | if (!bitmap_empty_p (cleared_regs)) | |
3a6191b1 JJ |
3134 | { |
3135 | FOR_EACH_BB (bb) | |
3136 | { | |
3137 | bitmap_and_compl_into (DF_LIVE_IN (bb), cleared_regs); | |
3138 | bitmap_and_compl_into (DF_LIVE_OUT (bb), cleared_regs); | |
3139 | bitmap_and_compl_into (DF_LR_IN (bb), cleared_regs); | |
3140 | bitmap_and_compl_into (DF_LR_OUT (bb), cleared_regs); | |
3141 | } | |
3142 | ||
3143 | /* Last pass - adjust debug insns referencing cleared regs. */ | |
3144 | if (MAY_HAVE_DEBUG_INSNS) | |
3145 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
3146 | if (DEBUG_INSN_P (insn)) | |
3147 | { | |
3148 | rtx old_loc = INSN_VAR_LOCATION_LOC (insn); | |
3149 | INSN_VAR_LOCATION_LOC (insn) | |
3150 | = simplify_replace_fn_rtx (old_loc, NULL_RTX, | |
3151 | adjust_cleared_regs, | |
3152 | (void *) cleared_regs); | |
3153 | if (old_loc != INSN_VAR_LOCATION_LOC (insn)) | |
3154 | df_insn_rescan (insn); | |
3155 | } | |
3156 | } | |
2af2dbdc VM |
3157 | |
3158 | BITMAP_FREE (cleared_regs); | |
3159 | ||
3160 | out: | |
3161 | /* Clean up. */ | |
3162 | ||
3163 | end_alias_analysis (); | |
3164 | free (reg_equiv); | |
3165 | return recorded_label_ref; | |
3166 | } | |
3167 | ||
3168 | \f | |
3169 | ||
3170 | /* Print chain C to FILE. */ | |
3171 | static void | |
3172 | print_insn_chain (FILE *file, struct insn_chain *c) | |
3173 | { | |
3174 | fprintf (file, "insn=%d, ", INSN_UID(c->insn)); | |
3175 | bitmap_print (file, &c->live_throughout, "live_throughout: ", ", "); | |
3176 | bitmap_print (file, &c->dead_or_set, "dead_or_set: ", "\n"); | |
3177 | } | |
3178 | ||
3179 | ||
3180 | /* Print all reload_insn_chains to FILE. */ | |
3181 | static void | |
3182 | print_insn_chains (FILE *file) | |
3183 | { | |
3184 | struct insn_chain *c; | |
3185 | for (c = reload_insn_chain; c ; c = c->next) | |
3186 | print_insn_chain (file, c); | |
3187 | } | |
3188 | ||
3189 | /* Return true if pseudo REGNO should be added to set live_throughout | |
3190 | or dead_or_set of the insn chains for reload consideration. */ | |
3191 | static bool | |
3192 | pseudo_for_reload_consideration_p (int regno) | |
3193 | { | |
3194 | /* Consider spilled pseudos too for IRA because they still have a | |
3195 | chance to get hard-registers in the reload when IRA is used. */ | |
b100151b | 3196 | return (reg_renumber[regno] >= 0 || ira_conflicts_p); |
2af2dbdc VM |
3197 | } |
3198 | ||
3199 | /* Init LIVE_SUBREGS[ALLOCNUM] and LIVE_SUBREGS_USED[ALLOCNUM] using | |
3200 | REG to the number of nregs, and INIT_VALUE to get the | |
3201 | initialization. ALLOCNUM need not be the regno of REG. */ | |
3202 | static void | |
3203 | init_live_subregs (bool init_value, sbitmap *live_subregs, | |
3204 | int *live_subregs_used, int allocnum, rtx reg) | |
3205 | { | |
3206 | unsigned int regno = REGNO (SUBREG_REG (reg)); | |
3207 | int size = GET_MODE_SIZE (GET_MODE (regno_reg_rtx[regno])); | |
3208 | ||
3209 | gcc_assert (size > 0); | |
3210 | ||
3211 | /* Been there, done that. */ | |
3212 | if (live_subregs_used[allocnum]) | |
3213 | return; | |
3214 | ||
3215 | /* Create a new one with zeros. */ | |
3216 | if (live_subregs[allocnum] == NULL) | |
3217 | live_subregs[allocnum] = sbitmap_alloc (size); | |
3218 | ||
3219 | /* If the entire reg was live before blasting into subregs, we need | |
3220 | to init all of the subregs to ones else init to 0. */ | |
3221 | if (init_value) | |
3222 | sbitmap_ones (live_subregs[allocnum]); | |
b8698a0f | 3223 | else |
2af2dbdc VM |
3224 | sbitmap_zero (live_subregs[allocnum]); |
3225 | ||
3226 | /* Set the number of bits that we really want. */ | |
3227 | live_subregs_used[allocnum] = size; | |
3228 | } | |
3229 | ||
3230 | /* Walk the insns of the current function and build reload_insn_chain, | |
3231 | and record register life information. */ | |
3232 | static void | |
3233 | build_insn_chain (void) | |
3234 | { | |
3235 | unsigned int i; | |
3236 | struct insn_chain **p = &reload_insn_chain; | |
3237 | basic_block bb; | |
3238 | struct insn_chain *c = NULL; | |
3239 | struct insn_chain *next = NULL; | |
3240 | bitmap live_relevant_regs = BITMAP_ALLOC (NULL); | |
3241 | bitmap elim_regset = BITMAP_ALLOC (NULL); | |
3242 | /* live_subregs is a vector used to keep accurate information about | |
3243 | which hardregs are live in multiword pseudos. live_subregs and | |
3244 | live_subregs_used are indexed by pseudo number. The live_subreg | |
3245 | entry for a particular pseudo is only used if the corresponding | |
3246 | element is non zero in live_subregs_used. The value in | |
3247 | live_subregs_used is number of bytes that the pseudo can | |
3248 | occupy. */ | |
3249 | sbitmap *live_subregs = XCNEWVEC (sbitmap, max_regno); | |
3250 | int *live_subregs_used = XNEWVEC (int, max_regno); | |
3251 | ||
3252 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
3253 | if (TEST_HARD_REG_BIT (eliminable_regset, i)) | |
3254 | bitmap_set_bit (elim_regset, i); | |
3255 | FOR_EACH_BB_REVERSE (bb) | |
3256 | { | |
3257 | bitmap_iterator bi; | |
3258 | rtx insn; | |
b8698a0f | 3259 | |
2af2dbdc VM |
3260 | CLEAR_REG_SET (live_relevant_regs); |
3261 | memset (live_subregs_used, 0, max_regno * sizeof (int)); | |
b8698a0f | 3262 | |
54a0ac2d | 3263 | EXECUTE_IF_SET_IN_BITMAP (DF_LR_OUT (bb), 0, i, bi) |
2af2dbdc VM |
3264 | { |
3265 | if (i >= FIRST_PSEUDO_REGISTER) | |
3266 | break; | |
3267 | bitmap_set_bit (live_relevant_regs, i); | |
3268 | } | |
3269 | ||
54a0ac2d | 3270 | EXECUTE_IF_SET_IN_BITMAP (DF_LR_OUT (bb), |
2af2dbdc VM |
3271 | FIRST_PSEUDO_REGISTER, i, bi) |
3272 | { | |
3273 | if (pseudo_for_reload_consideration_p (i)) | |
3274 | bitmap_set_bit (live_relevant_regs, i); | |
3275 | } | |
3276 | ||
3277 | FOR_BB_INSNS_REVERSE (bb, insn) | |
3278 | { | |
3279 | if (!NOTE_P (insn) && !BARRIER_P (insn)) | |
3280 | { | |
3281 | unsigned int uid = INSN_UID (insn); | |
3282 | df_ref *def_rec; | |
3283 | df_ref *use_rec; | |
3284 | ||
3285 | c = new_insn_chain (); | |
3286 | c->next = next; | |
3287 | next = c; | |
3288 | *p = c; | |
3289 | p = &c->prev; | |
b8698a0f | 3290 | |
2af2dbdc VM |
3291 | c->insn = insn; |
3292 | c->block = bb->index; | |
3293 | ||
3294 | if (INSN_P (insn)) | |
3295 | for (def_rec = DF_INSN_UID_DEFS (uid); *def_rec; def_rec++) | |
3296 | { | |
3297 | df_ref def = *def_rec; | |
3298 | unsigned int regno = DF_REF_REGNO (def); | |
b8698a0f | 3299 | |
2af2dbdc VM |
3300 | /* Ignore may clobbers because these are generated |
3301 | from calls. However, every other kind of def is | |
3302 | added to dead_or_set. */ | |
3303 | if (!DF_REF_FLAGS_IS_SET (def, DF_REF_MAY_CLOBBER)) | |
3304 | { | |
3305 | if (regno < FIRST_PSEUDO_REGISTER) | |
3306 | { | |
3307 | if (!fixed_regs[regno]) | |
3308 | bitmap_set_bit (&c->dead_or_set, regno); | |
3309 | } | |
3310 | else if (pseudo_for_reload_consideration_p (regno)) | |
3311 | bitmap_set_bit (&c->dead_or_set, regno); | |
3312 | } | |
3313 | ||
3314 | if ((regno < FIRST_PSEUDO_REGISTER | |
3315 | || reg_renumber[regno] >= 0 | |
3316 | || ira_conflicts_p) | |
3317 | && (!DF_REF_FLAGS_IS_SET (def, DF_REF_CONDITIONAL))) | |
3318 | { | |
3319 | rtx reg = DF_REF_REG (def); | |
3320 | ||
3321 | /* We can model subregs, but not if they are | |
3322 | wrapped in ZERO_EXTRACTS. */ | |
3323 | if (GET_CODE (reg) == SUBREG | |
3324 | && !DF_REF_FLAGS_IS_SET (def, DF_REF_ZERO_EXTRACT)) | |
3325 | { | |
3326 | unsigned int start = SUBREG_BYTE (reg); | |
b8698a0f | 3327 | unsigned int last = start |
2af2dbdc VM |
3328 | + GET_MODE_SIZE (GET_MODE (reg)); |
3329 | ||
3330 | init_live_subregs | |
b8698a0f | 3331 | (bitmap_bit_p (live_relevant_regs, regno), |
2af2dbdc VM |
3332 | live_subregs, live_subregs_used, regno, reg); |
3333 | ||
3334 | if (!DF_REF_FLAGS_IS_SET | |
3335 | (def, DF_REF_STRICT_LOW_PART)) | |
3336 | { | |
3337 | /* Expand the range to cover entire words. | |
3338 | Bytes added here are "don't care". */ | |
3339 | start | |
3340 | = start / UNITS_PER_WORD * UNITS_PER_WORD; | |
3341 | last = ((last + UNITS_PER_WORD - 1) | |
3342 | / UNITS_PER_WORD * UNITS_PER_WORD); | |
3343 | } | |
3344 | ||
3345 | /* Ignore the paradoxical bits. */ | |
3346 | if ((int)last > live_subregs_used[regno]) | |
3347 | last = live_subregs_used[regno]; | |
3348 | ||
3349 | while (start < last) | |
3350 | { | |
3351 | RESET_BIT (live_subregs[regno], start); | |
3352 | start++; | |
3353 | } | |
b8698a0f | 3354 | |
2af2dbdc VM |
3355 | if (sbitmap_empty_p (live_subregs[regno])) |
3356 | { | |
3357 | live_subregs_used[regno] = 0; | |
3358 | bitmap_clear_bit (live_relevant_regs, regno); | |
3359 | } | |
3360 | else | |
3361 | /* Set live_relevant_regs here because | |
3362 | that bit has to be true to get us to | |
3363 | look at the live_subregs fields. */ | |
3364 | bitmap_set_bit (live_relevant_regs, regno); | |
3365 | } | |
3366 | else | |
3367 | { | |
3368 | /* DF_REF_PARTIAL is generated for | |
3369 | subregs, STRICT_LOW_PART, and | |
3370 | ZERO_EXTRACT. We handle the subreg | |
3371 | case above so here we have to keep from | |
3372 | modeling the def as a killing def. */ | |
3373 | if (!DF_REF_FLAGS_IS_SET (def, DF_REF_PARTIAL)) | |
3374 | { | |
3375 | bitmap_clear_bit (live_relevant_regs, regno); | |
3376 | live_subregs_used[regno] = 0; | |
3377 | } | |
3378 | } | |
3379 | } | |
3380 | } | |
b8698a0f | 3381 | |
2af2dbdc VM |
3382 | bitmap_and_compl_into (live_relevant_regs, elim_regset); |
3383 | bitmap_copy (&c->live_throughout, live_relevant_regs); | |
3384 | ||
3385 | if (INSN_P (insn)) | |
3386 | for (use_rec = DF_INSN_UID_USES (uid); *use_rec; use_rec++) | |
3387 | { | |
3388 | df_ref use = *use_rec; | |
3389 | unsigned int regno = DF_REF_REGNO (use); | |
3390 | rtx reg = DF_REF_REG (use); | |
b8698a0f | 3391 | |
2af2dbdc VM |
3392 | /* DF_REF_READ_WRITE on a use means that this use |
3393 | is fabricated from a def that is a partial set | |
3394 | to a multiword reg. Here, we only model the | |
3395 | subreg case that is not wrapped in ZERO_EXTRACT | |
3396 | precisely so we do not need to look at the | |
3397 | fabricated use. */ | |
b8698a0f L |
3398 | if (DF_REF_FLAGS_IS_SET (use, DF_REF_READ_WRITE) |
3399 | && !DF_REF_FLAGS_IS_SET (use, DF_REF_ZERO_EXTRACT) | |
2af2dbdc VM |
3400 | && DF_REF_FLAGS_IS_SET (use, DF_REF_SUBREG)) |
3401 | continue; | |
b8698a0f | 3402 | |
2af2dbdc VM |
3403 | /* Add the last use of each var to dead_or_set. */ |
3404 | if (!bitmap_bit_p (live_relevant_regs, regno)) | |
3405 | { | |
3406 | if (regno < FIRST_PSEUDO_REGISTER) | |
3407 | { | |
3408 | if (!fixed_regs[regno]) | |
3409 | bitmap_set_bit (&c->dead_or_set, regno); | |
3410 | } | |
3411 | else if (pseudo_for_reload_consideration_p (regno)) | |
3412 | bitmap_set_bit (&c->dead_or_set, regno); | |
3413 | } | |
b8698a0f | 3414 | |
2af2dbdc VM |
3415 | if (regno < FIRST_PSEUDO_REGISTER |
3416 | || pseudo_for_reload_consideration_p (regno)) | |
3417 | { | |
3418 | if (GET_CODE (reg) == SUBREG | |
3419 | && !DF_REF_FLAGS_IS_SET (use, | |
3420 | DF_REF_SIGN_EXTRACT | |
b8698a0f | 3421 | | DF_REF_ZERO_EXTRACT)) |
2af2dbdc VM |
3422 | { |
3423 | unsigned int start = SUBREG_BYTE (reg); | |
b8698a0f | 3424 | unsigned int last = start |
2af2dbdc | 3425 | + GET_MODE_SIZE (GET_MODE (reg)); |
b8698a0f | 3426 | |
2af2dbdc | 3427 | init_live_subregs |
b8698a0f | 3428 | (bitmap_bit_p (live_relevant_regs, regno), |
2af2dbdc | 3429 | live_subregs, live_subregs_used, regno, reg); |
b8698a0f | 3430 | |
2af2dbdc VM |
3431 | /* Ignore the paradoxical bits. */ |
3432 | if ((int)last > live_subregs_used[regno]) | |
3433 | last = live_subregs_used[regno]; | |
3434 | ||
3435 | while (start < last) | |
3436 | { | |
3437 | SET_BIT (live_subregs[regno], start); | |
3438 | start++; | |
3439 | } | |
3440 | } | |
3441 | else | |
3442 | /* Resetting the live_subregs_used is | |
3443 | effectively saying do not use the subregs | |
3444 | because we are reading the whole | |
3445 | pseudo. */ | |
3446 | live_subregs_used[regno] = 0; | |
3447 | bitmap_set_bit (live_relevant_regs, regno); | |
3448 | } | |
3449 | } | |
3450 | } | |
3451 | } | |
3452 | ||
3453 | /* FIXME!! The following code is a disaster. Reload needs to see the | |
3454 | labels and jump tables that are just hanging out in between | |
3455 | the basic blocks. See pr33676. */ | |
3456 | insn = BB_HEAD (bb); | |
b8698a0f | 3457 | |
2af2dbdc | 3458 | /* Skip over the barriers and cruft. */ |
b8698a0f | 3459 | while (insn && (BARRIER_P (insn) || NOTE_P (insn) |
2af2dbdc VM |
3460 | || BLOCK_FOR_INSN (insn) == bb)) |
3461 | insn = PREV_INSN (insn); | |
b8698a0f | 3462 | |
2af2dbdc VM |
3463 | /* While we add anything except barriers and notes, the focus is |
3464 | to get the labels and jump tables into the | |
3465 | reload_insn_chain. */ | |
3466 | while (insn) | |
3467 | { | |
3468 | if (!NOTE_P (insn) && !BARRIER_P (insn)) | |
3469 | { | |
3470 | if (BLOCK_FOR_INSN (insn)) | |
3471 | break; | |
b8698a0f | 3472 | |
2af2dbdc VM |
3473 | c = new_insn_chain (); |
3474 | c->next = next; | |
3475 | next = c; | |
3476 | *p = c; | |
3477 | p = &c->prev; | |
b8698a0f | 3478 | |
2af2dbdc VM |
3479 | /* The block makes no sense here, but it is what the old |
3480 | code did. */ | |
3481 | c->block = bb->index; | |
3482 | c->insn = insn; | |
3483 | bitmap_copy (&c->live_throughout, live_relevant_regs); | |
b8698a0f | 3484 | } |
2af2dbdc VM |
3485 | insn = PREV_INSN (insn); |
3486 | } | |
3487 | } | |
3488 | ||
3489 | for (i = 0; i < (unsigned int) max_regno; i++) | |
04695783 | 3490 | free (live_subregs[i]); |
2af2dbdc VM |
3491 | |
3492 | reload_insn_chain = c; | |
3493 | *p = NULL; | |
3494 | ||
3495 | free (live_subregs); | |
3496 | free (live_subregs_used); | |
3497 | BITMAP_FREE (live_relevant_regs); | |
3498 | BITMAP_FREE (elim_regset); | |
3499 | ||
3500 | if (dump_file) | |
3501 | print_insn_chains (dump_file); | |
3502 | } | |
acf41a74 BS |
3503 | \f |
3504 | /* Examine the rtx found in *LOC, which is read or written to as determined | |
3505 | by TYPE. Return false if we find a reason why an insn containing this | |
3506 | rtx should not be moved (such as accesses to non-constant memory), true | |
3507 | otherwise. */ | |
3508 | static bool | |
3509 | rtx_moveable_p (rtx *loc, enum op_type type) | |
3510 | { | |
3511 | const char *fmt; | |
3512 | rtx x = *loc; | |
3513 | enum rtx_code code = GET_CODE (x); | |
3514 | int i, j; | |
3515 | ||
3516 | code = GET_CODE (x); | |
3517 | switch (code) | |
3518 | { | |
3519 | case CONST: | |
3520 | case CONST_INT: | |
3521 | case CONST_DOUBLE: | |
3522 | case CONST_FIXED: | |
3523 | case CONST_VECTOR: | |
3524 | case SYMBOL_REF: | |
3525 | case LABEL_REF: | |
3526 | return true; | |
3527 | ||
3528 | case PC: | |
3529 | return type == OP_IN; | |
3530 | ||
3531 | case CC0: | |
3532 | return false; | |
3533 | ||
3534 | case REG: | |
3535 | if (x == frame_pointer_rtx) | |
3536 | return true; | |
3537 | if (HARD_REGISTER_P (x)) | |
3538 | return false; | |
3539 | ||
3540 | return true; | |
3541 | ||
3542 | case MEM: | |
3543 | if (type == OP_IN && MEM_READONLY_P (x)) | |
3544 | return rtx_moveable_p (&XEXP (x, 0), OP_IN); | |
3545 | return false; | |
3546 | ||
3547 | case SET: | |
3548 | return (rtx_moveable_p (&SET_SRC (x), OP_IN) | |
3549 | && rtx_moveable_p (&SET_DEST (x), OP_OUT)); | |
3550 | ||
3551 | case STRICT_LOW_PART: | |
3552 | return rtx_moveable_p (&XEXP (x, 0), OP_OUT); | |
3553 | ||
3554 | case ZERO_EXTRACT: | |
3555 | case SIGN_EXTRACT: | |
3556 | return (rtx_moveable_p (&XEXP (x, 0), type) | |
3557 | && rtx_moveable_p (&XEXP (x, 1), OP_IN) | |
3558 | && rtx_moveable_p (&XEXP (x, 2), OP_IN)); | |
3559 | ||
3560 | case CLOBBER: | |
3561 | return rtx_moveable_p (&SET_DEST (x), OP_OUT); | |
3562 | ||
3563 | default: | |
3564 | break; | |
3565 | } | |
3566 | ||
3567 | fmt = GET_RTX_FORMAT (code); | |
3568 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3569 | { | |
3570 | if (fmt[i] == 'e') | |
3571 | { | |
3572 | if (!rtx_moveable_p (&XEXP (x, i), type)) | |
3573 | return false; | |
3574 | } | |
3575 | else if (fmt[i] == 'E') | |
3576 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
3577 | { | |
3578 | if (!rtx_moveable_p (&XVECEXP (x, i, j), type)) | |
3579 | return false; | |
3580 | } | |
3581 | } | |
3582 | return true; | |
3583 | } | |
3584 | ||
3585 | /* A wrapper around dominated_by_p, which uses the information in UID_LUID | |
3586 | to give dominance relationships between two insns I1 and I2. */ | |
3587 | static bool | |
3588 | insn_dominated_by_p (rtx i1, rtx i2, int *uid_luid) | |
3589 | { | |
3590 | basic_block bb1 = BLOCK_FOR_INSN (i1); | |
3591 | basic_block bb2 = BLOCK_FOR_INSN (i2); | |
3592 | ||
3593 | if (bb1 == bb2) | |
3594 | return uid_luid[INSN_UID (i2)] < uid_luid[INSN_UID (i1)]; | |
3595 | return dominated_by_p (CDI_DOMINATORS, bb1, bb2); | |
3596 | } | |
3597 | ||
3598 | /* Record the range of register numbers added by find_moveable_pseudos. */ | |
3599 | int first_moveable_pseudo, last_moveable_pseudo; | |
3600 | ||
3601 | /* These two vectors hold data for every register added by | |
3602 | find_movable_pseudos, with index 0 holding data for the | |
3603 | first_moveable_pseudo. */ | |
3604 | /* The original home register. */ | |
3605 | static VEC (rtx, heap) *pseudo_replaced_reg; | |
acf41a74 BS |
3606 | |
3607 | /* Look for instances where we have an instruction that is known to increase | |
3608 | register pressure, and whose result is not used immediately. If it is | |
3609 | possible to move the instruction downwards to just before its first use, | |
3610 | split its lifetime into two ranges. We create a new pseudo to compute the | |
3611 | value, and emit a move instruction just before the first use. If, after | |
3612 | register allocation, the new pseudo remains unallocated, the function | |
3613 | move_unallocated_pseudos then deletes the move instruction and places | |
3614 | the computation just before the first use. | |
3615 | ||
3616 | Such a move is safe and profitable if all the input registers remain live | |
3617 | and unchanged between the original computation and its first use. In such | |
3618 | a situation, the computation is known to increase register pressure, and | |
3619 | moving it is known to at least not worsen it. | |
3620 | ||
3621 | We restrict moves to only those cases where a register remains unallocated, | |
3622 | in order to avoid interfering too much with the instruction schedule. As | |
3623 | an exception, we may move insns which only modify their input register | |
3624 | (typically induction variables), as this increases the freedom for our | |
3625 | intended transformation, and does not limit the second instruction | |
3626 | scheduler pass. */ | |
3627 | ||
3628 | static void | |
3629 | find_moveable_pseudos (void) | |
3630 | { | |
3631 | unsigned i; | |
3632 | int max_regs = max_reg_num (); | |
3633 | int max_uid = get_max_uid (); | |
3634 | basic_block bb; | |
3635 | int *uid_luid = XNEWVEC (int, max_uid); | |
3636 | rtx *closest_uses = XNEWVEC (rtx, max_regs); | |
3637 | /* A set of registers which are live but not modified throughout a block. */ | |
3638 | bitmap_head *bb_transp_live = XNEWVEC (bitmap_head, last_basic_block); | |
3639 | /* A set of registers which only exist in a given basic block. */ | |
3640 | bitmap_head *bb_local = XNEWVEC (bitmap_head, last_basic_block); | |
3641 | /* A set of registers which are set once, in an instruction that can be | |
3642 | moved freely downwards, but are otherwise transparent to a block. */ | |
3643 | bitmap_head *bb_moveable_reg_sets = XNEWVEC (bitmap_head, last_basic_block); | |
3644 | bitmap_head live, used, set, interesting, unusable_as_input; | |
3645 | bitmap_iterator bi; | |
3646 | bitmap_initialize (&interesting, 0); | |
3647 | ||
3648 | first_moveable_pseudo = max_regs; | |
acf41a74 | 3649 | VEC_free (rtx, heap, pseudo_replaced_reg); |
acf41a74 BS |
3650 | VEC_safe_grow (rtx, heap, pseudo_replaced_reg, max_regs); |
3651 | ||
3652 | df_analyze (); | |
3653 | calculate_dominance_info (CDI_DOMINATORS); | |
3654 | ||
3655 | i = 0; | |
3656 | bitmap_initialize (&live, 0); | |
3657 | bitmap_initialize (&used, 0); | |
3658 | bitmap_initialize (&set, 0); | |
3659 | bitmap_initialize (&unusable_as_input, 0); | |
3660 | FOR_EACH_BB (bb) | |
3661 | { | |
3662 | rtx insn; | |
3663 | bitmap transp = bb_transp_live + bb->index; | |
3664 | bitmap moveable = bb_moveable_reg_sets + bb->index; | |
3665 | bitmap local = bb_local + bb->index; | |
3666 | ||
3667 | bitmap_initialize (local, 0); | |
3668 | bitmap_initialize (transp, 0); | |
3669 | bitmap_initialize (moveable, 0); | |
3670 | bitmap_copy (&live, df_get_live_out (bb)); | |
3671 | bitmap_and_into (&live, df_get_live_in (bb)); | |
3672 | bitmap_copy (transp, &live); | |
3673 | bitmap_clear (moveable); | |
3674 | bitmap_clear (&live); | |
3675 | bitmap_clear (&used); | |
3676 | bitmap_clear (&set); | |
3677 | FOR_BB_INSNS (bb, insn) | |
3678 | if (NONDEBUG_INSN_P (insn)) | |
3679 | { | |
3680 | df_ref *u_rec, *d_rec; | |
3681 | ||
3682 | uid_luid[INSN_UID (insn)] = i++; | |
3683 | ||
3684 | u_rec = DF_INSN_USES (insn); | |
3685 | d_rec = DF_INSN_DEFS (insn); | |
3686 | if (d_rec[0] != NULL && d_rec[1] == NULL | |
3687 | && u_rec[0] != NULL && u_rec[1] == NULL | |
3688 | && DF_REF_REGNO (*u_rec) == DF_REF_REGNO (*d_rec) | |
3689 | && !bitmap_bit_p (&set, DF_REF_REGNO (*u_rec)) | |
3690 | && rtx_moveable_p (&PATTERN (insn), OP_IN)) | |
3691 | { | |
3692 | unsigned regno = DF_REF_REGNO (*u_rec); | |
3693 | bitmap_set_bit (moveable, regno); | |
3694 | bitmap_set_bit (&set, regno); | |
3695 | bitmap_set_bit (&used, regno); | |
3696 | bitmap_clear_bit (transp, regno); | |
3697 | continue; | |
3698 | } | |
3699 | while (*u_rec) | |
3700 | { | |
3701 | unsigned regno = DF_REF_REGNO (*u_rec); | |
3702 | bitmap_set_bit (&used, regno); | |
3703 | if (bitmap_clear_bit (moveable, regno)) | |
3704 | bitmap_clear_bit (transp, regno); | |
3705 | u_rec++; | |
3706 | } | |
3707 | ||
3708 | while (*d_rec) | |
3709 | { | |
3710 | unsigned regno = DF_REF_REGNO (*d_rec); | |
3711 | bitmap_set_bit (&set, regno); | |
3712 | bitmap_clear_bit (transp, regno); | |
3713 | bitmap_clear_bit (moveable, regno); | |
3714 | d_rec++; | |
3715 | } | |
3716 | } | |
3717 | } | |
3718 | ||
3719 | bitmap_clear (&live); | |
3720 | bitmap_clear (&used); | |
3721 | bitmap_clear (&set); | |
3722 | ||
3723 | FOR_EACH_BB (bb) | |
3724 | { | |
3725 | bitmap local = bb_local + bb->index; | |
3726 | rtx insn; | |
3727 | ||
3728 | FOR_BB_INSNS (bb, insn) | |
3729 | if (NONDEBUG_INSN_P (insn)) | |
3730 | { | |
3731 | rtx def_insn, closest_use, note; | |
3732 | df_ref *def_rec, def, use; | |
3733 | unsigned regno; | |
3734 | bool all_dominated, all_local; | |
3735 | enum machine_mode mode; | |
3736 | ||
3737 | def_rec = DF_INSN_DEFS (insn); | |
3738 | /* There must be exactly one def in this insn. */ | |
3739 | def = *def_rec; | |
3740 | if (!def || def_rec[1] || !single_set (insn)) | |
3741 | continue; | |
3742 | /* This must be the only definition of the reg. We also limit | |
3743 | which modes we deal with so that we can assume we can generate | |
3744 | move instructions. */ | |
3745 | regno = DF_REF_REGNO (def); | |
3746 | mode = GET_MODE (DF_REF_REG (def)); | |
3747 | if (DF_REG_DEF_COUNT (regno) != 1 | |
3748 | || !DF_REF_INSN_INFO (def) | |
3749 | || HARD_REGISTER_NUM_P (regno) | |
aa44c80c | 3750 | || DF_REG_EQ_USE_COUNT (regno) > 0 |
acf41a74 BS |
3751 | || (!INTEGRAL_MODE_P (mode) && !FLOAT_MODE_P (mode))) |
3752 | continue; | |
3753 | def_insn = DF_REF_INSN (def); | |
3754 | ||
3755 | for (note = REG_NOTES (def_insn); note; note = XEXP (note, 1)) | |
3756 | if (REG_NOTE_KIND (note) == REG_EQUIV && MEM_P (XEXP (note, 0))) | |
3757 | break; | |
3758 | ||
3759 | if (note) | |
3760 | { | |
3761 | if (dump_file) | |
3762 | fprintf (dump_file, "Ignoring reg %d, has equiv memory\n", | |
3763 | regno); | |
3764 | bitmap_set_bit (&unusable_as_input, regno); | |
3765 | continue; | |
3766 | } | |
3767 | ||
3768 | use = DF_REG_USE_CHAIN (regno); | |
3769 | all_dominated = true; | |
3770 | all_local = true; | |
3771 | closest_use = NULL_RTX; | |
3772 | for (; use; use = DF_REF_NEXT_REG (use)) | |
3773 | { | |
3774 | rtx insn; | |
3775 | if (!DF_REF_INSN_INFO (use)) | |
3776 | { | |
3777 | all_dominated = false; | |
3778 | all_local = false; | |
3779 | break; | |
3780 | } | |
3781 | insn = DF_REF_INSN (use); | |
3782 | if (DEBUG_INSN_P (insn)) | |
3783 | continue; | |
3784 | if (BLOCK_FOR_INSN (insn) != BLOCK_FOR_INSN (def_insn)) | |
3785 | all_local = false; | |
3786 | if (!insn_dominated_by_p (insn, def_insn, uid_luid)) | |
3787 | all_dominated = false; | |
3788 | if (closest_use != insn && closest_use != const0_rtx) | |
3789 | { | |
3790 | if (closest_use == NULL_RTX) | |
3791 | closest_use = insn; | |
3792 | else if (insn_dominated_by_p (closest_use, insn, uid_luid)) | |
3793 | closest_use = insn; | |
3794 | else if (!insn_dominated_by_p (insn, closest_use, uid_luid)) | |
3795 | closest_use = const0_rtx; | |
3796 | } | |
3797 | } | |
3798 | if (!all_dominated) | |
3799 | { | |
3800 | if (dump_file) | |
3801 | fprintf (dump_file, "Reg %d not all uses dominated by set\n", | |
3802 | regno); | |
3803 | continue; | |
3804 | } | |
3805 | if (all_local) | |
3806 | bitmap_set_bit (local, regno); | |
3807 | if (closest_use == const0_rtx || closest_use == NULL | |
3808 | || next_nonnote_nondebug_insn (def_insn) == closest_use) | |
3809 | { | |
3810 | if (dump_file) | |
3811 | fprintf (dump_file, "Reg %d uninteresting%s\n", regno, | |
3812 | closest_use == const0_rtx || closest_use == NULL | |
3813 | ? " (no unique first use)" : ""); | |
3814 | continue; | |
3815 | } | |
3816 | #ifdef HAVE_cc0 | |
3817 | if (reg_referenced_p (cc0_rtx, PATTERN (closest_use))) | |
3818 | { | |
3819 | if (dump_file) | |
3820 | fprintf (dump_file, "Reg %d: closest user uses cc0\n", | |
3821 | regno); | |
3822 | continue; | |
3823 | } | |
3824 | #endif | |
3825 | bitmap_set_bit (&interesting, regno); | |
3826 | closest_uses[regno] = closest_use; | |
3827 | ||
3828 | if (dump_file && (all_local || all_dominated)) | |
3829 | { | |
3830 | fprintf (dump_file, "Reg %u:", regno); | |
3831 | if (all_local) | |
3832 | fprintf (dump_file, " local to bb %d", bb->index); | |
3833 | if (all_dominated) | |
3834 | fprintf (dump_file, " def dominates all uses"); | |
3835 | if (closest_use != const0_rtx) | |
3836 | fprintf (dump_file, " has unique first use"); | |
3837 | fputs ("\n", dump_file); | |
3838 | } | |
3839 | } | |
3840 | } | |
3841 | ||
3842 | EXECUTE_IF_SET_IN_BITMAP (&interesting, 0, i, bi) | |
3843 | { | |
3844 | df_ref def = DF_REG_DEF_CHAIN (i); | |
3845 | rtx def_insn = DF_REF_INSN (def); | |
3846 | basic_block def_block = BLOCK_FOR_INSN (def_insn); | |
3847 | bitmap def_bb_local = bb_local + def_block->index; | |
3848 | bitmap def_bb_moveable = bb_moveable_reg_sets + def_block->index; | |
3849 | bitmap def_bb_transp = bb_transp_live + def_block->index; | |
3850 | bool local_to_bb_p = bitmap_bit_p (def_bb_local, i); | |
3851 | rtx use_insn = closest_uses[i]; | |
3852 | df_ref *def_insn_use_rec = DF_INSN_USES (def_insn); | |
3853 | bool all_ok = true; | |
3854 | bool all_transp = true; | |
3855 | ||
3856 | if (!REG_P (DF_REF_REG (def))) | |
3857 | continue; | |
3858 | ||
3859 | if (!local_to_bb_p) | |
3860 | { | |
3861 | if (dump_file) | |
3862 | fprintf (dump_file, "Reg %u not local to one basic block\n", | |
3863 | i); | |
3864 | continue; | |
3865 | } | |
3866 | if (reg_equiv_init (i) != NULL_RTX) | |
3867 | { | |
3868 | if (dump_file) | |
3869 | fprintf (dump_file, "Ignoring reg %u with equiv init insn\n", | |
3870 | i); | |
3871 | continue; | |
3872 | } | |
3873 | if (!rtx_moveable_p (&PATTERN (def_insn), OP_IN)) | |
3874 | { | |
3875 | if (dump_file) | |
3876 | fprintf (dump_file, "Found def insn %d for %d to be not moveable\n", | |
3877 | INSN_UID (def_insn), i); | |
3878 | continue; | |
3879 | } | |
3880 | if (dump_file) | |
3881 | fprintf (dump_file, "Examining insn %d, def for %d\n", | |
3882 | INSN_UID (def_insn), i); | |
3883 | while (*def_insn_use_rec != NULL) | |
3884 | { | |
3885 | df_ref use = *def_insn_use_rec; | |
3886 | unsigned regno = DF_REF_REGNO (use); | |
3887 | if (bitmap_bit_p (&unusable_as_input, regno)) | |
3888 | { | |
3889 | all_ok = false; | |
3890 | if (dump_file) | |
3891 | fprintf (dump_file, " found unusable input reg %u.\n", regno); | |
3892 | break; | |
3893 | } | |
3894 | if (!bitmap_bit_p (def_bb_transp, regno)) | |
3895 | { | |
3896 | if (bitmap_bit_p (def_bb_moveable, regno) | |
3897 | && !control_flow_insn_p (use_insn) | |
3898 | #ifdef HAVE_cc0 | |
3899 | && !sets_cc0_p (use_insn) | |
3900 | #endif | |
3901 | ) | |
3902 | { | |
3903 | if (modified_between_p (DF_REF_REG (use), def_insn, use_insn)) | |
3904 | { | |
3905 | rtx x = NEXT_INSN (def_insn); | |
3906 | while (!modified_in_p (DF_REF_REG (use), x)) | |
3907 | { | |
3908 | gcc_assert (x != use_insn); | |
3909 | x = NEXT_INSN (x); | |
3910 | } | |
3911 | if (dump_file) | |
3912 | fprintf (dump_file, " input reg %u modified but insn %d moveable\n", | |
3913 | regno, INSN_UID (x)); | |
3914 | emit_insn_after (PATTERN (x), use_insn); | |
3915 | set_insn_deleted (x); | |
3916 | } | |
3917 | else | |
3918 | { | |
3919 | if (dump_file) | |
3920 | fprintf (dump_file, " input reg %u modified between def and use\n", | |
3921 | regno); | |
3922 | all_transp = false; | |
3923 | } | |
3924 | } | |
3925 | else | |
3926 | all_transp = false; | |
3927 | } | |
3928 | ||
3929 | def_insn_use_rec++; | |
3930 | } | |
3931 | if (!all_ok) | |
3932 | continue; | |
3933 | if (!dbg_cnt (ira_move)) | |
3934 | break; | |
3935 | if (dump_file) | |
3936 | fprintf (dump_file, " all ok%s\n", all_transp ? " and transp" : ""); | |
3937 | ||
3938 | if (all_transp) | |
3939 | { | |
3940 | rtx def_reg = DF_REF_REG (def); | |
3941 | rtx newreg = ira_create_new_reg (def_reg); | |
3942 | if (validate_change (def_insn, DF_REF_LOC (def), newreg, 0)) | |
3943 | { | |
3944 | unsigned nregno = REGNO (newreg); | |
a36b2706 | 3945 | emit_insn_before (gen_move_insn (def_reg, newreg), use_insn); |
acf41a74 | 3946 | nregno -= max_regs; |
acf41a74 BS |
3947 | VEC_replace (rtx, pseudo_replaced_reg, nregno, def_reg); |
3948 | } | |
3949 | } | |
3950 | } | |
3951 | ||
3952 | FOR_EACH_BB (bb) | |
3953 | { | |
3954 | bitmap_clear (bb_local + bb->index); | |
3955 | bitmap_clear (bb_transp_live + bb->index); | |
3956 | bitmap_clear (bb_moveable_reg_sets + bb->index); | |
3957 | } | |
3958 | bitmap_clear (&interesting); | |
3959 | bitmap_clear (&unusable_as_input); | |
3960 | free (uid_luid); | |
3961 | free (closest_uses); | |
3962 | free (bb_local); | |
3963 | free (bb_transp_live); | |
3964 | free (bb_moveable_reg_sets); | |
3965 | ||
3966 | last_moveable_pseudo = max_reg_num (); | |
3967 | ||
81c082ec | 3968 | fix_reg_equiv_init (); |
fb99ee9b | 3969 | expand_reg_info (); |
acf41a74 BS |
3970 | regstat_free_n_sets_and_refs (); |
3971 | regstat_free_ri (); | |
3972 | regstat_init_n_sets_and_refs (); | |
3973 | regstat_compute_ri (); | |
3974 | free_dominance_info (CDI_DOMINATORS); | |
3975 | } | |
8ff49c29 | 3976 | |
acf41a74 BS |
3977 | /* Perform the second half of the transformation started in |
3978 | find_moveable_pseudos. We look for instances where the newly introduced | |
3979 | pseudo remains unallocated, and remove it by moving the definition to | |
3980 | just before its use, replacing the move instruction generated by | |
3981 | find_moveable_pseudos. */ | |
3982 | static void | |
3983 | move_unallocated_pseudos (void) | |
3984 | { | |
3985 | int i; | |
3986 | for (i = first_moveable_pseudo; i < last_moveable_pseudo; i++) | |
3987 | if (reg_renumber[i] < 0) | |
3988 | { | |
acf41a74 BS |
3989 | int idx = i - first_moveable_pseudo; |
3990 | rtx other_reg = VEC_index (rtx, pseudo_replaced_reg, idx); | |
a36b2706 RS |
3991 | rtx def_insn = DF_REF_INSN (DF_REG_DEF_CHAIN (i)); |
3992 | /* The use must follow all definitions of OTHER_REG, so we can | |
3993 | insert the new definition immediately after any of them. */ | |
3994 | df_ref other_def = DF_REG_DEF_CHAIN (REGNO (other_reg)); | |
3995 | rtx move_insn = DF_REF_INSN (other_def); | |
acf41a74 | 3996 | rtx newinsn = emit_insn_after (PATTERN (def_insn), move_insn); |
a36b2706 | 3997 | rtx set; |
acf41a74 BS |
3998 | int success; |
3999 | ||
4000 | if (dump_file) | |
4001 | fprintf (dump_file, "moving def of %d (insn %d now) ", | |
4002 | REGNO (other_reg), INSN_UID (def_insn)); | |
4003 | ||
a36b2706 RS |
4004 | delete_insn (move_insn); |
4005 | while ((other_def = DF_REG_DEF_CHAIN (REGNO (other_reg)))) | |
4006 | delete_insn (DF_REF_INSN (other_def)); | |
4007 | delete_insn (def_insn); | |
4008 | ||
acf41a74 BS |
4009 | set = single_set (newinsn); |
4010 | success = validate_change (newinsn, &SET_DEST (set), other_reg, 0); | |
4011 | gcc_assert (success); | |
4012 | if (dump_file) | |
4013 | fprintf (dump_file, " %d) rather than keep unallocated replacement %d\n", | |
4014 | INSN_UID (newinsn), i); | |
acf41a74 BS |
4015 | SET_REG_N_REFS (i, 0); |
4016 | } | |
4017 | } | |
f2034d06 | 4018 | \f |
6399c0ab SB |
4019 | /* If the backend knows where to allocate pseudos for hard |
4020 | register initial values, register these allocations now. */ | |
a932fb89 | 4021 | static void |
6399c0ab SB |
4022 | allocate_initial_values (void) |
4023 | { | |
4024 | if (targetm.allocate_initial_value) | |
4025 | { | |
4026 | rtx hreg, preg, x; | |
4027 | int i, regno; | |
4028 | ||
4029 | for (i = 0; HARD_REGISTER_NUM_P (i); i++) | |
4030 | { | |
4031 | if (! initial_value_entry (i, &hreg, &preg)) | |
4032 | break; | |
4033 | ||
4034 | x = targetm.allocate_initial_value (hreg); | |
4035 | regno = REGNO (preg); | |
4036 | if (x && REG_N_SETS (regno) <= 1) | |
4037 | { | |
4038 | if (MEM_P (x)) | |
4039 | reg_equiv_memory_loc (regno) = x; | |
4040 | else | |
4041 | { | |
4042 | basic_block bb; | |
4043 | int new_regno; | |
4044 | ||
4045 | gcc_assert (REG_P (x)); | |
4046 | new_regno = REGNO (x); | |
4047 | reg_renumber[regno] = new_regno; | |
4048 | /* Poke the regno right into regno_reg_rtx so that even | |
4049 | fixed regs are accepted. */ | |
4050 | SET_REGNO (preg, new_regno); | |
4051 | /* Update global register liveness information. */ | |
4052 | FOR_EACH_BB (bb) | |
4053 | { | |
4054 | if (REGNO_REG_SET_P(df_get_live_in (bb), regno)) | |
4055 | SET_REGNO_REG_SET (df_get_live_in (bb), new_regno); | |
4056 | if (REGNO_REG_SET_P(df_get_live_out (bb), regno)) | |
4057 | SET_REGNO_REG_SET (df_get_live_out (bb), new_regno); | |
4058 | } | |
4059 | } | |
4060 | } | |
4061 | } | |
2af2dbdc | 4062 | |
6399c0ab SB |
4063 | gcc_checking_assert (! initial_value_entry (FIRST_PSEUDO_REGISTER, |
4064 | &hreg, &preg)); | |
4065 | } | |
4066 | } | |
4067 | \f | |
058e97ec VM |
4068 | /* All natural loops. */ |
4069 | struct loops ira_loops; | |
4070 | ||
311aab06 VM |
4071 | /* True if we have allocno conflicts. It is false for non-optimized |
4072 | mode or when the conflict table is too big. */ | |
4073 | bool ira_conflicts_p; | |
4074 | ||
ae2b9cb6 BS |
4075 | /* Saved between IRA and reload. */ |
4076 | static int saved_flag_ira_share_spill_slots; | |
4077 | ||
058e97ec VM |
4078 | /* This is the main entry of IRA. */ |
4079 | static void | |
4080 | ira (FILE *f) | |
4081 | { | |
058e97ec VM |
4082 | bool loops_p; |
4083 | int max_regno_before_ira, ira_max_point_before_emit; | |
4084 | int rebuild_p; | |
058e97ec | 4085 | |
dc12b70e JZ |
4086 | if (flag_caller_saves) |
4087 | init_caller_save (); | |
4088 | ||
058e97ec VM |
4089 | if (flag_ira_verbose < 10) |
4090 | { | |
4091 | internal_flag_ira_verbose = flag_ira_verbose; | |
4092 | ira_dump_file = f; | |
4093 | } | |
4094 | else | |
4095 | { | |
4096 | internal_flag_ira_verbose = flag_ira_verbose - 10; | |
4097 | ira_dump_file = stderr; | |
4098 | } | |
4099 | ||
311aab06 | 4100 | ira_conflicts_p = optimize > 0; |
058e97ec VM |
4101 | setup_prohibited_mode_move_regs (); |
4102 | ||
4103 | df_note_add_problem (); | |
4104 | ||
4105 | if (optimize == 1) | |
4106 | { | |
4107 | df_live_add_problem (); | |
4108 | df_live_set_all_dirty (); | |
4109 | } | |
4110 | #ifdef ENABLE_CHECKING | |
4111 | df->changeable_flags |= DF_VERIFY_SCHEDULED; | |
4112 | #endif | |
4113 | df_analyze (); | |
4114 | df_clear_flags (DF_NO_INSN_RESCAN); | |
4115 | regstat_init_n_sets_and_refs (); | |
4116 | regstat_compute_ri (); | |
4117 | ||
4118 | /* If we are not optimizing, then this is the only place before | |
4119 | register allocation where dataflow is done. And that is needed | |
4120 | to generate these warnings. */ | |
4121 | if (warn_clobbered) | |
4122 | generate_setjmp_warnings (); | |
4123 | ||
ace984c8 RS |
4124 | /* Determine if the current function is a leaf before running IRA |
4125 | since this can impact optimizations done by the prologue and | |
4126 | epilogue thus changing register elimination offsets. */ | |
4127 | current_function_is_leaf = leaf_function_p (); | |
4128 | ||
1833192f VM |
4129 | if (resize_reg_info () && flag_ira_loop_pressure) |
4130 | ira_set_pseudo_classes (ira_dump_file); | |
4131 | ||
058e97ec VM |
4132 | rebuild_p = update_equiv_regs (); |
4133 | ||
4134 | #ifndef IRA_NO_OBSTACK | |
4135 | gcc_obstack_init (&ira_obstack); | |
4136 | #endif | |
4137 | bitmap_obstack_initialize (&ira_bitmap_obstack); | |
4138 | if (optimize) | |
b8698a0f | 4139 | { |
058e97ec VM |
4140 | max_regno = max_reg_num (); |
4141 | ira_reg_equiv_len = max_regno; | |
4142 | ira_reg_equiv_invariant_p | |
4143 | = (bool *) ira_allocate (max_regno * sizeof (bool)); | |
4144 | memset (ira_reg_equiv_invariant_p, 0, max_regno * sizeof (bool)); | |
4145 | ira_reg_equiv_const = (rtx *) ira_allocate (max_regno * sizeof (rtx)); | |
4146 | memset (ira_reg_equiv_const, 0, max_regno * sizeof (rtx)); | |
4147 | find_reg_equiv_invariant_const (); | |
4148 | if (rebuild_p) | |
4149 | { | |
4150 | timevar_push (TV_JUMP); | |
4151 | rebuild_jump_labels (get_insns ()); | |
59db109a SB |
4152 | if (purge_all_dead_edges ()) |
4153 | delete_unreachable_blocks (); | |
058e97ec VM |
4154 | timevar_pop (TV_JUMP); |
4155 | } | |
4156 | } | |
4157 | ||
fb99ee9b | 4158 | allocated_reg_info_size = max_reg_num (); |
e8d7e3e7 VM |
4159 | |
4160 | /* It is not worth to do such improvement when we use a simple | |
4161 | allocation because of -O0 usage or because the function is too | |
4162 | big. */ | |
4163 | if (ira_conflicts_p) | |
4164 | find_moveable_pseudos (); | |
acf41a74 | 4165 | |
fb99ee9b | 4166 | max_regno_before_ira = max_reg_num (); |
ce18efcb | 4167 | ira_setup_eliminable_regset (); |
b8698a0f | 4168 | |
058e97ec VM |
4169 | ira_overall_cost = ira_reg_cost = ira_mem_cost = 0; |
4170 | ira_load_cost = ira_store_cost = ira_shuffle_cost = 0; | |
4171 | ira_move_loops_num = ira_additional_jumps_num = 0; | |
b8698a0f | 4172 | |
058e97ec | 4173 | ira_assert (current_loops == NULL); |
2608d841 VM |
4174 | if (flag_ira_region == IRA_REGION_ALL || flag_ira_region == IRA_REGION_MIXED) |
4175 | { | |
4176 | flow_loops_find (&ira_loops); | |
4177 | record_loop_exits (); | |
4178 | current_loops = &ira_loops; | |
4179 | } | |
b8698a0f | 4180 | |
058e97ec VM |
4181 | if (internal_flag_ira_verbose > 0 && ira_dump_file != NULL) |
4182 | fprintf (ira_dump_file, "Building IRA IR\n"); | |
2608d841 | 4183 | loops_p = ira_build (); |
b8698a0f | 4184 | |
311aab06 | 4185 | ira_assert (ira_conflicts_p || !loops_p); |
3553f0bb VM |
4186 | |
4187 | saved_flag_ira_share_spill_slots = flag_ira_share_spill_slots; | |
de8e52f0 | 4188 | if (too_high_register_pressure_p () || cfun->calls_setjmp) |
3553f0bb | 4189 | /* It is just wasting compiler's time to pack spilled pseudos into |
de8e52f0 VM |
4190 | stack slots in this case -- prohibit it. We also do this if |
4191 | there is setjmp call because a variable not modified between | |
4192 | setjmp and longjmp the compiler is required to preserve its | |
4193 | value and sharing slots does not guarantee it. */ | |
3553f0bb VM |
4194 | flag_ira_share_spill_slots = FALSE; |
4195 | ||
cb1ca6ac | 4196 | ira_color (); |
b8698a0f | 4197 | |
058e97ec | 4198 | ira_max_point_before_emit = ira_max_point; |
b8698a0f | 4199 | |
1756cb66 VM |
4200 | ira_initiate_emit_data (); |
4201 | ||
058e97ec | 4202 | ira_emit (loops_p); |
b8698a0f | 4203 | |
311aab06 | 4204 | if (ira_conflicts_p) |
058e97ec VM |
4205 | { |
4206 | max_regno = max_reg_num (); | |
b8698a0f | 4207 | |
058e97ec VM |
4208 | if (! loops_p) |
4209 | ira_initiate_assign (); | |
4210 | else | |
4211 | { | |
fb99ee9b | 4212 | expand_reg_info (); |
b8698a0f | 4213 | |
058e97ec VM |
4214 | if (internal_flag_ira_verbose > 0 && ira_dump_file != NULL) |
4215 | fprintf (ira_dump_file, "Flattening IR\n"); | |
4216 | ira_flattening (max_regno_before_ira, ira_max_point_before_emit); | |
4217 | /* New insns were generated: add notes and recalculate live | |
4218 | info. */ | |
4219 | df_analyze (); | |
b8698a0f | 4220 | |
058e97ec | 4221 | flow_loops_find (&ira_loops); |
6744a6ab | 4222 | record_loop_exits (); |
058e97ec VM |
4223 | current_loops = &ira_loops; |
4224 | ||
4225 | setup_allocno_assignment_flags (); | |
4226 | ira_initiate_assign (); | |
4227 | ira_reassign_conflict_allocnos (max_regno); | |
4228 | } | |
4229 | } | |
4230 | ||
1756cb66 VM |
4231 | ira_finish_emit_data (); |
4232 | ||
058e97ec | 4233 | setup_reg_renumber (); |
b8698a0f | 4234 | |
058e97ec | 4235 | calculate_allocation_cost (); |
b8698a0f | 4236 | |
058e97ec | 4237 | #ifdef ENABLE_IRA_CHECKING |
311aab06 | 4238 | if (ira_conflicts_p) |
058e97ec VM |
4239 | check_allocation (); |
4240 | #endif | |
b8698a0f | 4241 | |
530a4800 JJ |
4242 | if (delete_trivially_dead_insns (get_insns (), max_reg_num ())) |
4243 | df_analyze (); | |
b8698a0f | 4244 | |
058e97ec VM |
4245 | if (max_regno != max_regno_before_ira) |
4246 | { | |
4247 | regstat_free_n_sets_and_refs (); | |
4248 | regstat_free_ri (); | |
4249 | regstat_init_n_sets_and_refs (); | |
4250 | regstat_compute_ri (); | |
4251 | } | |
4252 | ||
058e97ec | 4253 | overall_cost_before = ira_overall_cost; |
e5b0e1ca VM |
4254 | if (! ira_conflicts_p) |
4255 | grow_reg_equivs (); | |
4256 | else | |
058e97ec VM |
4257 | { |
4258 | fix_reg_equiv_init (); | |
b8698a0f | 4259 | |
058e97ec VM |
4260 | #ifdef ENABLE_IRA_CHECKING |
4261 | print_redundant_copies (); | |
4262 | #endif | |
4263 | ||
4264 | ira_spilled_reg_stack_slots_num = 0; | |
4265 | ira_spilled_reg_stack_slots | |
4266 | = ((struct ira_spilled_reg_stack_slot *) | |
4267 | ira_allocate (max_regno | |
4268 | * sizeof (struct ira_spilled_reg_stack_slot))); | |
4269 | memset (ira_spilled_reg_stack_slots, 0, | |
4270 | max_regno * sizeof (struct ira_spilled_reg_stack_slot)); | |
4271 | } | |
6399c0ab | 4272 | allocate_initial_values (); |
e8d7e3e7 VM |
4273 | |
4274 | /* See comment for find_moveable_pseudos call. */ | |
4275 | if (ira_conflicts_p) | |
4276 | move_unallocated_pseudos (); | |
ae2b9cb6 | 4277 | } |
b8698a0f | 4278 | |
ae2b9cb6 BS |
4279 | static void |
4280 | do_reload (void) | |
4281 | { | |
4282 | basic_block bb; | |
4283 | bool need_dce; | |
4284 | ||
67463efb | 4285 | if (flag_ira_verbose < 10) |
ae2b9cb6 | 4286 | ira_dump_file = dump_file; |
058e97ec | 4287 | |
058e97ec VM |
4288 | df_set_flags (DF_NO_INSN_RESCAN); |
4289 | build_insn_chain (); | |
4290 | ||
b0c11403 | 4291 | need_dce = reload (get_insns (), ira_conflicts_p); |
058e97ec | 4292 | |
058e97ec VM |
4293 | timevar_push (TV_IRA); |
4294 | ||
311aab06 | 4295 | if (ira_conflicts_p) |
058e97ec VM |
4296 | { |
4297 | ira_free (ira_spilled_reg_stack_slots); | |
b8698a0f | 4298 | |
058e97ec | 4299 | ira_finish_assign (); |
b8698a0f | 4300 | } |
058e97ec VM |
4301 | if (internal_flag_ira_verbose > 0 && ira_dump_file != NULL |
4302 | && overall_cost_before != ira_overall_cost) | |
4303 | fprintf (ira_dump_file, "+++Overall after reload %d\n", ira_overall_cost); | |
4304 | ira_destroy (); | |
b8698a0f | 4305 | |
3553f0bb VM |
4306 | flag_ira_share_spill_slots = saved_flag_ira_share_spill_slots; |
4307 | ||
2608d841 VM |
4308 | if (current_loops != NULL) |
4309 | { | |
4310 | flow_loops_free (&ira_loops); | |
4311 | free_dominance_info (CDI_DOMINATORS); | |
4312 | } | |
058e97ec VM |
4313 | FOR_ALL_BB (bb) |
4314 | bb->loop_father = NULL; | |
4315 | current_loops = NULL; | |
4316 | ||
058e97ec VM |
4317 | regstat_free_ri (); |
4318 | regstat_free_n_sets_and_refs (); | |
b8698a0f | 4319 | |
058e97ec VM |
4320 | if (optimize) |
4321 | { | |
4322 | cleanup_cfg (CLEANUP_EXPENSIVE); | |
b8698a0f | 4323 | |
058e97ec VM |
4324 | ira_free (ira_reg_equiv_invariant_p); |
4325 | ira_free (ira_reg_equiv_const); | |
4326 | } | |
4327 | ||
4328 | bitmap_obstack_release (&ira_bitmap_obstack); | |
4329 | #ifndef IRA_NO_OBSTACK | |
4330 | obstack_free (&ira_obstack, NULL); | |
4331 | #endif | |
4332 | ||
4333 | /* The code after the reload has changed so much that at this point | |
b0c11403 | 4334 | we might as well just rescan everything. Note that |
058e97ec VM |
4335 | df_rescan_all_insns is not going to help here because it does not |
4336 | touch the artificial uses and defs. */ | |
4337 | df_finish_pass (true); | |
4338 | if (optimize > 1) | |
4339 | df_live_add_problem (); | |
4340 | df_scan_alloc (NULL); | |
4341 | df_scan_blocks (); | |
4342 | ||
4343 | if (optimize) | |
4344 | df_analyze (); | |
4345 | ||
b0c11403 JL |
4346 | if (need_dce && optimize) |
4347 | run_fast_dce (); | |
4348 | ||
058e97ec VM |
4349 | timevar_pop (TV_IRA); |
4350 | } | |
058e97ec | 4351 | \f |
058e97ec VM |
4352 | /* Run the integrated register allocator. */ |
4353 | static unsigned int | |
4354 | rest_of_handle_ira (void) | |
4355 | { | |
4356 | ira (dump_file); | |
4357 | return 0; | |
4358 | } | |
4359 | ||
4360 | struct rtl_opt_pass pass_ira = | |
4361 | { | |
4362 | { | |
4363 | RTL_PASS, | |
4364 | "ira", /* name */ | |
ae2b9cb6 | 4365 | NULL, /* gate */ |
058e97ec VM |
4366 | rest_of_handle_ira, /* execute */ |
4367 | NULL, /* sub */ | |
4368 | NULL, /* next */ | |
4369 | 0, /* static_pass_number */ | |
ae2b9cb6 BS |
4370 | TV_IRA, /* tv_id */ |
4371 | 0, /* properties_required */ | |
4372 | 0, /* properties_provided */ | |
4373 | 0, /* properties_destroyed */ | |
4374 | 0, /* todo_flags_start */ | |
c634f4ba | 4375 | 0, /* todo_flags_finish */ |
ae2b9cb6 BS |
4376 | } |
4377 | }; | |
4378 | ||
4379 | static unsigned int | |
4380 | rest_of_handle_reload (void) | |
4381 | { | |
4382 | do_reload (); | |
4383 | return 0; | |
4384 | } | |
4385 | ||
4386 | struct rtl_opt_pass pass_reload = | |
4387 | { | |
4388 | { | |
4389 | RTL_PASS, | |
4390 | "reload", /* name */ | |
4391 | NULL, /* gate */ | |
4392 | rest_of_handle_reload, /* execute */ | |
4393 | NULL, /* sub */ | |
4394 | NULL, /* next */ | |
4395 | 0, /* static_pass_number */ | |
4396 | TV_RELOAD, /* tv_id */ | |
058e97ec VM |
4397 | 0, /* properties_required */ |
4398 | 0, /* properties_provided */ | |
4399 | 0, /* properties_destroyed */ | |
4400 | 0, /* todo_flags_start */ | |
c634f4ba | 4401 | TODO_ggc_collect /* todo_flags_finish */ |
058e97ec VM |
4402 | } |
4403 | }; |