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058e97ec | 1 | /* Integrated Register Allocator (IRA) entry point. |
5624e564 | 2 | Copyright (C) 2006-2015 Free Software Foundation, Inc. |
058e97ec VM |
3 | Contributed by Vladimir Makarov <vmakarov@redhat.com>. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it under | |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 3, or (at your option) any later | |
10 | version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | /* The integrated register allocator (IRA) is a | |
22 | regional register allocator performing graph coloring on a top-down | |
23 | traversal of nested regions. Graph coloring in a region is based | |
24 | on Chaitin-Briggs algorithm. It is called integrated because | |
25 | register coalescing, register live range splitting, and choosing a | |
26 | better hard register are done on-the-fly during coloring. Register | |
27 | coalescing and choosing a cheaper hard register is done by hard | |
28 | register preferencing during hard register assigning. The live | |
29 | range splitting is a byproduct of the regional register allocation. | |
30 | ||
31 | Major IRA notions are: | |
32 | ||
33 | o *Region* is a part of CFG where graph coloring based on | |
34 | Chaitin-Briggs algorithm is done. IRA can work on any set of | |
35 | nested CFG regions forming a tree. Currently the regions are | |
36 | the entire function for the root region and natural loops for | |
37 | the other regions. Therefore data structure representing a | |
38 | region is called loop_tree_node. | |
39 | ||
1756cb66 VM |
40 | o *Allocno class* is a register class used for allocation of |
41 | given allocno. It means that only hard register of given | |
42 | register class can be assigned to given allocno. In reality, | |
43 | even smaller subset of (*profitable*) hard registers can be | |
44 | assigned. In rare cases, the subset can be even smaller | |
45 | because our modification of Chaitin-Briggs algorithm requires | |
46 | that sets of hard registers can be assigned to allocnos forms a | |
47 | forest, i.e. the sets can be ordered in a way where any | |
48 | previous set is not intersected with given set or is a superset | |
49 | of given set. | |
50 | ||
51 | o *Pressure class* is a register class belonging to a set of | |
52 | register classes containing all of the hard-registers available | |
53 | for register allocation. The set of all pressure classes for a | |
54 | target is defined in the corresponding machine-description file | |
55 | according some criteria. Register pressure is calculated only | |
56 | for pressure classes and it affects some IRA decisions as | |
57 | forming allocation regions. | |
058e97ec VM |
58 | |
59 | o *Allocno* represents the live range of a pseudo-register in a | |
60 | region. Besides the obvious attributes like the corresponding | |
1756cb66 | 61 | pseudo-register number, allocno class, conflicting allocnos and |
058e97ec VM |
62 | conflicting hard-registers, there are a few allocno attributes |
63 | which are important for understanding the allocation algorithm: | |
64 | ||
1756cb66 VM |
65 | - *Live ranges*. This is a list of ranges of *program points* |
66 | where the allocno lives. Program points represent places | |
67 | where a pseudo can be born or become dead (there are | |
058e97ec VM |
68 | approximately two times more program points than the insns) |
69 | and they are represented by integers starting with 0. The | |
1756cb66 VM |
70 | live ranges are used to find conflicts between allocnos. |
71 | They also play very important role for the transformation of | |
72 | the IRA internal representation of several regions into a one | |
73 | region representation. The later is used during the reload | |
74 | pass work because each allocno represents all of the | |
75 | corresponding pseudo-registers. | |
058e97ec VM |
76 | |
77 | - *Hard-register costs*. This is a vector of size equal to the | |
1756cb66 VM |
78 | number of available hard-registers of the allocno class. The |
79 | cost of a callee-clobbered hard-register for an allocno is | |
80 | increased by the cost of save/restore code around the calls | |
81 | through the given allocno's life. If the allocno is a move | |
82 | instruction operand and another operand is a hard-register of | |
83 | the allocno class, the cost of the hard-register is decreased | |
84 | by the move cost. | |
058e97ec VM |
85 | |
86 | When an allocno is assigned, the hard-register with minimal | |
87 | full cost is used. Initially, a hard-register's full cost is | |
88 | the corresponding value from the hard-register's cost vector. | |
89 | If the allocno is connected by a *copy* (see below) to | |
90 | another allocno which has just received a hard-register, the | |
91 | cost of the hard-register is decreased. Before choosing a | |
92 | hard-register for an allocno, the allocno's current costs of | |
93 | the hard-registers are modified by the conflict hard-register | |
94 | costs of all of the conflicting allocnos which are not | |
95 | assigned yet. | |
96 | ||
97 | - *Conflict hard-register costs*. This is a vector of the same | |
98 | size as the hard-register costs vector. To permit an | |
99 | unassigned allocno to get a better hard-register, IRA uses | |
100 | this vector to calculate the final full cost of the | |
101 | available hard-registers. Conflict hard-register costs of an | |
102 | unassigned allocno are also changed with a change of the | |
103 | hard-register cost of the allocno when a copy involving the | |
104 | allocno is processed as described above. This is done to | |
105 | show other unassigned allocnos that a given allocno prefers | |
106 | some hard-registers in order to remove the move instruction | |
107 | corresponding to the copy. | |
108 | ||
109 | o *Cap*. If a pseudo-register does not live in a region but | |
110 | lives in a nested region, IRA creates a special allocno called | |
111 | a cap in the outer region. A region cap is also created for a | |
112 | subregion cap. | |
113 | ||
114 | o *Copy*. Allocnos can be connected by copies. Copies are used | |
115 | to modify hard-register costs for allocnos during coloring. | |
116 | Such modifications reflects a preference to use the same | |
117 | hard-register for the allocnos connected by copies. Usually | |
118 | copies are created for move insns (in this case it results in | |
119 | register coalescing). But IRA also creates copies for operands | |
120 | of an insn which should be assigned to the same hard-register | |
121 | due to constraints in the machine description (it usually | |
122 | results in removing a move generated in reload to satisfy | |
123 | the constraints) and copies referring to the allocno which is | |
124 | the output operand of an instruction and the allocno which is | |
125 | an input operand dying in the instruction (creation of such | |
126 | copies results in less register shuffling). IRA *does not* | |
127 | create copies between the same register allocnos from different | |
128 | regions because we use another technique for propagating | |
129 | hard-register preference on the borders of regions. | |
130 | ||
131 | Allocnos (including caps) for the upper region in the region tree | |
132 | *accumulate* information important for coloring from allocnos with | |
133 | the same pseudo-register from nested regions. This includes | |
134 | hard-register and memory costs, conflicts with hard-registers, | |
135 | allocno conflicts, allocno copies and more. *Thus, attributes for | |
136 | allocnos in a region have the same values as if the region had no | |
137 | subregions*. It means that attributes for allocnos in the | |
138 | outermost region corresponding to the function have the same values | |
139 | as though the allocation used only one region which is the entire | |
140 | function. It also means that we can look at IRA work as if the | |
141 | first IRA did allocation for all function then it improved the | |
142 | allocation for loops then their subloops and so on. | |
143 | ||
144 | IRA major passes are: | |
145 | ||
146 | o Building IRA internal representation which consists of the | |
147 | following subpasses: | |
148 | ||
149 | * First, IRA builds regions and creates allocnos (file | |
150 | ira-build.c) and initializes most of their attributes. | |
151 | ||
1756cb66 VM |
152 | * Then IRA finds an allocno class for each allocno and |
153 | calculates its initial (non-accumulated) cost of memory and | |
154 | each hard-register of its allocno class (file ira-cost.c). | |
058e97ec | 155 | |
df3e3493 | 156 | * IRA creates live ranges of each allocno, calculates register |
1756cb66 | 157 | pressure for each pressure class in each region, sets up |
058e97ec VM |
158 | conflict hard registers for each allocno and info about calls |
159 | the allocno lives through (file ira-lives.c). | |
160 | ||
161 | * IRA removes low register pressure loops from the regions | |
162 | mostly to speed IRA up (file ira-build.c). | |
163 | ||
164 | * IRA propagates accumulated allocno info from lower region | |
165 | allocnos to corresponding upper region allocnos (file | |
166 | ira-build.c). | |
167 | ||
168 | * IRA creates all caps (file ira-build.c). | |
169 | ||
1756cb66 VM |
170 | * Having live-ranges of allocnos and their classes, IRA creates |
171 | conflicting allocnos for each allocno. Conflicting allocnos | |
172 | are stored as a bit vector or array of pointers to the | |
173 | conflicting allocnos whatever is more profitable (file | |
174 | ira-conflicts.c). At this point IRA creates allocno copies. | |
058e97ec VM |
175 | |
176 | o Coloring. Now IRA has all necessary info to start graph coloring | |
177 | process. It is done in each region on top-down traverse of the | |
178 | region tree (file ira-color.c). There are following subpasses: | |
b8698a0f | 179 | |
1756cb66 VM |
180 | * Finding profitable hard registers of corresponding allocno |
181 | class for each allocno. For example, only callee-saved hard | |
182 | registers are frequently profitable for allocnos living | |
183 | through colors. If the profitable hard register set of | |
184 | allocno does not form a tree based on subset relation, we use | |
185 | some approximation to form the tree. This approximation is | |
186 | used to figure out trivial colorability of allocnos. The | |
187 | approximation is a pretty rare case. | |
188 | ||
058e97ec VM |
189 | * Putting allocnos onto the coloring stack. IRA uses Briggs |
190 | optimistic coloring which is a major improvement over | |
191 | Chaitin's coloring. Therefore IRA does not spill allocnos at | |
192 | this point. There is some freedom in the order of putting | |
193 | allocnos on the stack which can affect the final result of | |
1756cb66 | 194 | the allocation. IRA uses some heuristics to improve the |
41808d15 VM |
195 | order. The major one is to form *threads* from colorable |
196 | allocnos and push them on the stack by threads. Thread is a | |
197 | set of non-conflicting colorable allocnos connected by | |
198 | copies. The thread contains allocnos from the colorable | |
199 | bucket or colorable allocnos already pushed onto the coloring | |
200 | stack. Pushing thread allocnos one after another onto the | |
201 | stack increases chances of removing copies when the allocnos | |
202 | get the same hard reg. | |
1756cb66 VM |
203 | |
204 | We also use a modification of Chaitin-Briggs algorithm which | |
205 | works for intersected register classes of allocnos. To | |
206 | figure out trivial colorability of allocnos, the mentioned | |
207 | above tree of hard register sets is used. To get an idea how | |
208 | the algorithm works in i386 example, let us consider an | |
209 | allocno to which any general hard register can be assigned. | |
210 | If the allocno conflicts with eight allocnos to which only | |
211 | EAX register can be assigned, given allocno is still | |
212 | trivially colorable because all conflicting allocnos might be | |
213 | assigned only to EAX and all other general hard registers are | |
214 | still free. | |
215 | ||
216 | To get an idea of the used trivial colorability criterion, it | |
217 | is also useful to read article "Graph-Coloring Register | |
218 | Allocation for Irregular Architectures" by Michael D. Smith | |
219 | and Glen Holloway. Major difference between the article | |
220 | approach and approach used in IRA is that Smith's approach | |
221 | takes register classes only from machine description and IRA | |
222 | calculate register classes from intermediate code too | |
223 | (e.g. an explicit usage of hard registers in RTL code for | |
224 | parameter passing can result in creation of additional | |
225 | register classes which contain or exclude the hard | |
226 | registers). That makes IRA approach useful for improving | |
227 | coloring even for architectures with regular register files | |
228 | and in fact some benchmarking shows the improvement for | |
229 | regular class architectures is even bigger than for irregular | |
230 | ones. Another difference is that Smith's approach chooses | |
231 | intersection of classes of all insn operands in which a given | |
232 | pseudo occurs. IRA can use bigger classes if it is still | |
233 | more profitable than memory usage. | |
058e97ec VM |
234 | |
235 | * Popping the allocnos from the stack and assigning them hard | |
236 | registers. If IRA can not assign a hard register to an | |
237 | allocno and the allocno is coalesced, IRA undoes the | |
238 | coalescing and puts the uncoalesced allocnos onto the stack in | |
239 | the hope that some such allocnos will get a hard register | |
240 | separately. If IRA fails to assign hard register or memory | |
241 | is more profitable for it, IRA spills the allocno. IRA | |
242 | assigns the allocno the hard-register with minimal full | |
243 | allocation cost which reflects the cost of usage of the | |
244 | hard-register for the allocno and cost of usage of the | |
245 | hard-register for allocnos conflicting with given allocno. | |
246 | ||
1756cb66 | 247 | * Chaitin-Briggs coloring assigns as many pseudos as possible |
df3e3493 | 248 | to hard registers. After coloring we try to improve |
1756cb66 VM |
249 | allocation with cost point of view. We improve the |
250 | allocation by spilling some allocnos and assigning the freed | |
251 | hard registers to other allocnos if it decreases the overall | |
252 | allocation cost. | |
253 | ||
3447fefe | 254 | * After allocno assigning in the region, IRA modifies the hard |
058e97ec VM |
255 | register and memory costs for the corresponding allocnos in |
256 | the subregions to reflect the cost of possible loads, stores, | |
257 | or moves on the border of the region and its subregions. | |
258 | When default regional allocation algorithm is used | |
259 | (-fira-algorithm=mixed), IRA just propagates the assignment | |
260 | for allocnos if the register pressure in the region for the | |
1756cb66 VM |
261 | corresponding pressure class is less than number of available |
262 | hard registers for given pressure class. | |
058e97ec VM |
263 | |
264 | o Spill/restore code moving. When IRA performs an allocation | |
265 | by traversing regions in top-down order, it does not know what | |
266 | happens below in the region tree. Therefore, sometimes IRA | |
267 | misses opportunities to perform a better allocation. A simple | |
268 | optimization tries to improve allocation in a region having | |
269 | subregions and containing in another region. If the | |
270 | corresponding allocnos in the subregion are spilled, it spills | |
271 | the region allocno if it is profitable. The optimization | |
272 | implements a simple iterative algorithm performing profitable | |
273 | transformations while they are still possible. It is fast in | |
274 | practice, so there is no real need for a better time complexity | |
275 | algorithm. | |
276 | ||
1756cb66 VM |
277 | o Code change. After coloring, two allocnos representing the |
278 | same pseudo-register outside and inside a region respectively | |
279 | may be assigned to different locations (hard-registers or | |
280 | memory). In this case IRA creates and uses a new | |
281 | pseudo-register inside the region and adds code to move allocno | |
282 | values on the region's borders. This is done during top-down | |
283 | traversal of the regions (file ira-emit.c). In some | |
284 | complicated cases IRA can create a new allocno to move allocno | |
285 | values (e.g. when a swap of values stored in two hard-registers | |
286 | is needed). At this stage, the new allocno is marked as | |
287 | spilled. IRA still creates the pseudo-register and the moves | |
288 | on the region borders even when both allocnos were assigned to | |
289 | the same hard-register. If the reload pass spills a | |
290 | pseudo-register for some reason, the effect will be smaller | |
291 | because another allocno will still be in the hard-register. In | |
292 | most cases, this is better then spilling both allocnos. If | |
293 | reload does not change the allocation for the two | |
294 | pseudo-registers, the trivial move will be removed by | |
295 | post-reload optimizations. IRA does not generate moves for | |
058e97ec VM |
296 | allocnos assigned to the same hard register when the default |
297 | regional allocation algorithm is used and the register pressure | |
1756cb66 VM |
298 | in the region for the corresponding pressure class is less than |
299 | number of available hard registers for given pressure class. | |
058e97ec VM |
300 | IRA also does some optimizations to remove redundant stores and |
301 | to reduce code duplication on the region borders. | |
302 | ||
303 | o Flattening internal representation. After changing code, IRA | |
304 | transforms its internal representation for several regions into | |
305 | one region representation (file ira-build.c). This process is | |
306 | called IR flattening. Such process is more complicated than IR | |
307 | rebuilding would be, but is much faster. | |
308 | ||
309 | o After IR flattening, IRA tries to assign hard registers to all | |
df3e3493 | 310 | spilled allocnos. This is implemented by a simple and fast |
058e97ec VM |
311 | priority coloring algorithm (see function |
312 | ira_reassign_conflict_allocnos::ira-color.c). Here new allocnos | |
313 | created during the code change pass can be assigned to hard | |
314 | registers. | |
315 | ||
316 | o At the end IRA calls the reload pass. The reload pass | |
317 | communicates with IRA through several functions in file | |
318 | ira-color.c to improve its decisions in | |
319 | ||
320 | * sharing stack slots for the spilled pseudos based on IRA info | |
321 | about pseudo-register conflicts. | |
322 | ||
323 | * reassigning hard-registers to all spilled pseudos at the end | |
324 | of each reload iteration. | |
325 | ||
326 | * choosing a better hard-register to spill based on IRA info | |
327 | about pseudo-register live ranges and the register pressure | |
328 | in places where the pseudo-register lives. | |
329 | ||
330 | IRA uses a lot of data representing the target processors. These | |
df3e3493 | 331 | data are initialized in file ira.c. |
058e97ec VM |
332 | |
333 | If function has no loops (or the loops are ignored when | |
334 | -fira-algorithm=CB is used), we have classic Chaitin-Briggs | |
335 | coloring (only instead of separate pass of coalescing, we use hard | |
336 | register preferencing). In such case, IRA works much faster | |
337 | because many things are not made (like IR flattening, the | |
338 | spill/restore optimization, and the code change). | |
339 | ||
340 | Literature is worth to read for better understanding the code: | |
341 | ||
342 | o Preston Briggs, Keith D. Cooper, Linda Torczon. Improvements to | |
343 | Graph Coloring Register Allocation. | |
344 | ||
345 | o David Callahan, Brian Koblenz. Register allocation via | |
346 | hierarchical graph coloring. | |
347 | ||
348 | o Keith Cooper, Anshuman Dasgupta, Jason Eckhardt. Revisiting Graph | |
349 | Coloring Register Allocation: A Study of the Chaitin-Briggs and | |
350 | Callahan-Koblenz Algorithms. | |
351 | ||
352 | o Guei-Yuan Lueh, Thomas Gross, and Ali-Reza Adl-Tabatabai. Global | |
353 | Register Allocation Based on Graph Fusion. | |
354 | ||
1756cb66 VM |
355 | o Michael D. Smith and Glenn Holloway. Graph-Coloring Register |
356 | Allocation for Irregular Architectures | |
357 | ||
058e97ec VM |
358 | o Vladimir Makarov. The Integrated Register Allocator for GCC. |
359 | ||
360 | o Vladimir Makarov. The top-down register allocator for irregular | |
361 | register file architectures. | |
362 | ||
363 | */ | |
364 | ||
365 | ||
366 | #include "config.h" | |
367 | #include "system.h" | |
368 | #include "coretypes.h" | |
c7131fb2 | 369 | #include "backend.h" |
4d648807 | 370 | #include "tree.h" |
058e97ec | 371 | #include "rtl.h" |
c7131fb2 AM |
372 | #include "df.h" |
373 | #include "regs.h" | |
374 | #include "alias.h" | |
058e97ec VM |
375 | #include "tm_p.h" |
376 | #include "target.h" | |
377 | #include "flags.h" | |
378 | #include "obstack.h" | |
60393bbc AM |
379 | #include "cfgrtl.h" |
380 | #include "cfgbuild.h" | |
381 | #include "cfgcleanup.h" | |
36566b39 PK |
382 | #include "insn-config.h" |
383 | #include "expmed.h" | |
384 | #include "dojump.h" | |
385 | #include "explow.h" | |
386 | #include "calls.h" | |
387 | #include "emit-rtl.h" | |
388 | #include "varasm.h" | |
389 | #include "stmt.h" | |
058e97ec VM |
390 | #include "expr.h" |
391 | #include "recog.h" | |
392 | #include "params.h" | |
058e97ec VM |
393 | #include "tree-pass.h" |
394 | #include "output.h" | |
2af2dbdc | 395 | #include "except.h" |
058e97ec | 396 | #include "reload.h" |
718f9c0f | 397 | #include "diagnostic-core.h" |
c7131fb2 AM |
398 | #include "cfgloop.h" |
399 | #include "ira.h" | |
400 | #include "alloc-pool.h" | |
058e97ec | 401 | #include "ira-int.h" |
55a2c322 | 402 | #include "lra.h" |
b0c11403 | 403 | #include "dce.h" |
acf41a74 | 404 | #include "dbgcnt.h" |
40954ce5 | 405 | #include "rtl-iter.h" |
a5e022d5 | 406 | #include "shrink-wrap.h" |
058e97ec | 407 | |
afcc66c4 RS |
408 | struct target_ira default_target_ira; |
409 | struct target_ira_int default_target_ira_int; | |
410 | #if SWITCHABLE_TARGET | |
411 | struct target_ira *this_target_ira = &default_target_ira; | |
412 | struct target_ira_int *this_target_ira_int = &default_target_ira_int; | |
413 | #endif | |
414 | ||
058e97ec VM |
415 | /* A modified value of flag `-fira-verbose' used internally. */ |
416 | int internal_flag_ira_verbose; | |
417 | ||
418 | /* Dump file of the allocator if it is not NULL. */ | |
419 | FILE *ira_dump_file; | |
420 | ||
058e97ec VM |
421 | /* The number of elements in the following array. */ |
422 | int ira_spilled_reg_stack_slots_num; | |
423 | ||
424 | /* The following array contains info about spilled pseudo-registers | |
425 | stack slots used in current function so far. */ | |
426 | struct ira_spilled_reg_stack_slot *ira_spilled_reg_stack_slots; | |
427 | ||
ae2b9cb6 BS |
428 | /* Correspondingly overall cost of the allocation, overall cost before |
429 | reload, cost of the allocnos assigned to hard-registers, cost of | |
430 | the allocnos assigned to memory, cost of loads, stores and register | |
431 | move insns generated for pseudo-register live range splitting (see | |
432 | ira-emit.c). */ | |
2bf7560b VM |
433 | int64_t ira_overall_cost, overall_cost_before; |
434 | int64_t ira_reg_cost, ira_mem_cost; | |
435 | int64_t ira_load_cost, ira_store_cost, ira_shuffle_cost; | |
058e97ec VM |
436 | int ira_move_loops_num, ira_additional_jumps_num; |
437 | ||
2af2dbdc VM |
438 | /* All registers that can be eliminated. */ |
439 | ||
440 | HARD_REG_SET eliminable_regset; | |
441 | ||
70cc3288 VM |
442 | /* Value of max_reg_num () before IRA work start. This value helps |
443 | us to recognize a situation when new pseudos were created during | |
444 | IRA work. */ | |
445 | static int max_regno_before_ira; | |
446 | ||
058e97ec VM |
447 | /* Temporary hard reg set used for a different calculation. */ |
448 | static HARD_REG_SET temp_hard_regset; | |
449 | ||
e80ccebc RS |
450 | #define last_mode_for_init_move_cost \ |
451 | (this_target_ira_int->x_last_mode_for_init_move_cost) | |
058e97ec VM |
452 | \f |
453 | ||
454 | /* The function sets up the map IRA_REG_MODE_HARD_REGSET. */ | |
455 | static void | |
456 | setup_reg_mode_hard_regset (void) | |
457 | { | |
458 | int i, m, hard_regno; | |
459 | ||
460 | for (m = 0; m < NUM_MACHINE_MODES; m++) | |
461 | for (hard_regno = 0; hard_regno < FIRST_PSEUDO_REGISTER; hard_regno++) | |
462 | { | |
463 | CLEAR_HARD_REG_SET (ira_reg_mode_hard_regset[hard_regno][m]); | |
464 | for (i = hard_regno_nregs[hard_regno][m] - 1; i >= 0; i--) | |
465 | if (hard_regno + i < FIRST_PSEUDO_REGISTER) | |
466 | SET_HARD_REG_BIT (ira_reg_mode_hard_regset[hard_regno][m], | |
467 | hard_regno + i); | |
468 | } | |
469 | } | |
470 | ||
471 | \f | |
afcc66c4 RS |
472 | #define no_unit_alloc_regs \ |
473 | (this_target_ira_int->x_no_unit_alloc_regs) | |
058e97ec VM |
474 | |
475 | /* The function sets up the three arrays declared above. */ | |
476 | static void | |
477 | setup_class_hard_regs (void) | |
478 | { | |
479 | int cl, i, hard_regno, n; | |
480 | HARD_REG_SET processed_hard_reg_set; | |
481 | ||
482 | ira_assert (SHRT_MAX >= FIRST_PSEUDO_REGISTER); | |
058e97ec VM |
483 | for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) |
484 | { | |
485 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); | |
486 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
487 | CLEAR_HARD_REG_SET (processed_hard_reg_set); | |
7db7ed3c | 488 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
0583835c | 489 | { |
854edfcd VM |
490 | ira_non_ordered_class_hard_regs[cl][i] = -1; |
491 | ira_class_hard_reg_index[cl][i] = -1; | |
0583835c | 492 | } |
058e97ec VM |
493 | for (n = 0, i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
494 | { | |
495 | #ifdef REG_ALLOC_ORDER | |
496 | hard_regno = reg_alloc_order[i]; | |
497 | #else | |
498 | hard_regno = i; | |
b8698a0f | 499 | #endif |
058e97ec VM |
500 | if (TEST_HARD_REG_BIT (processed_hard_reg_set, hard_regno)) |
501 | continue; | |
502 | SET_HARD_REG_BIT (processed_hard_reg_set, hard_regno); | |
503 | if (! TEST_HARD_REG_BIT (temp_hard_regset, hard_regno)) | |
504 | ira_class_hard_reg_index[cl][hard_regno] = -1; | |
505 | else | |
506 | { | |
507 | ira_class_hard_reg_index[cl][hard_regno] = n; | |
508 | ira_class_hard_regs[cl][n++] = hard_regno; | |
509 | } | |
510 | } | |
511 | ira_class_hard_regs_num[cl] = n; | |
0583835c VM |
512 | for (n = 0, i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
513 | if (TEST_HARD_REG_BIT (temp_hard_regset, i)) | |
514 | ira_non_ordered_class_hard_regs[cl][n++] = i; | |
515 | ira_assert (ira_class_hard_regs_num[cl] == n); | |
058e97ec VM |
516 | } |
517 | } | |
518 | ||
058e97ec VM |
519 | /* Set up global variables defining info about hard registers for the |
520 | allocation. These depend on USE_HARD_FRAME_P whose TRUE value means | |
521 | that we can use the hard frame pointer for the allocation. */ | |
522 | static void | |
523 | setup_alloc_regs (bool use_hard_frame_p) | |
524 | { | |
5a733826 BS |
525 | #ifdef ADJUST_REG_ALLOC_ORDER |
526 | ADJUST_REG_ALLOC_ORDER; | |
527 | #endif | |
058e97ec VM |
528 | COPY_HARD_REG_SET (no_unit_alloc_regs, fixed_reg_set); |
529 | if (! use_hard_frame_p) | |
530 | SET_HARD_REG_BIT (no_unit_alloc_regs, HARD_FRAME_POINTER_REGNUM); | |
531 | setup_class_hard_regs (); | |
058e97ec VM |
532 | } |
533 | ||
534 | \f | |
535 | ||
1756cb66 VM |
536 | #define alloc_reg_class_subclasses \ |
537 | (this_target_ira_int->x_alloc_reg_class_subclasses) | |
538 | ||
539 | /* Initialize the table of subclasses of each reg class. */ | |
540 | static void | |
541 | setup_reg_subclasses (void) | |
542 | { | |
543 | int i, j; | |
544 | HARD_REG_SET temp_hard_regset2; | |
545 | ||
546 | for (i = 0; i < N_REG_CLASSES; i++) | |
547 | for (j = 0; j < N_REG_CLASSES; j++) | |
548 | alloc_reg_class_subclasses[i][j] = LIM_REG_CLASSES; | |
549 | ||
550 | for (i = 0; i < N_REG_CLASSES; i++) | |
551 | { | |
552 | if (i == (int) NO_REGS) | |
553 | continue; | |
554 | ||
555 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[i]); | |
556 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
557 | if (hard_reg_set_empty_p (temp_hard_regset)) | |
558 | continue; | |
559 | for (j = 0; j < N_REG_CLASSES; j++) | |
560 | if (i != j) | |
561 | { | |
562 | enum reg_class *p; | |
563 | ||
564 | COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[j]); | |
565 | AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs); | |
566 | if (! hard_reg_set_subset_p (temp_hard_regset, | |
567 | temp_hard_regset2)) | |
568 | continue; | |
569 | p = &alloc_reg_class_subclasses[j][0]; | |
570 | while (*p != LIM_REG_CLASSES) p++; | |
571 | *p = (enum reg_class) i; | |
572 | } | |
573 | } | |
574 | } | |
575 | ||
576 | \f | |
577 | ||
578 | /* Set up IRA_MEMORY_MOVE_COST and IRA_MAX_MEMORY_MOVE_COST. */ | |
058e97ec VM |
579 | static void |
580 | setup_class_subset_and_memory_move_costs (void) | |
581 | { | |
1756cb66 | 582 | int cl, cl2, mode, cost; |
058e97ec VM |
583 | HARD_REG_SET temp_hard_regset2; |
584 | ||
585 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
586 | ira_memory_move_cost[mode][NO_REGS][0] | |
587 | = ira_memory_move_cost[mode][NO_REGS][1] = SHRT_MAX; | |
588 | for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) | |
589 | { | |
590 | if (cl != (int) NO_REGS) | |
591 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
592 | { | |
1756cb66 VM |
593 | ira_max_memory_move_cost[mode][cl][0] |
594 | = ira_memory_move_cost[mode][cl][0] | |
ef4bddc2 | 595 | = memory_move_cost ((machine_mode) mode, |
6f76a878 | 596 | (reg_class_t) cl, false); |
1756cb66 VM |
597 | ira_max_memory_move_cost[mode][cl][1] |
598 | = ira_memory_move_cost[mode][cl][1] | |
ef4bddc2 | 599 | = memory_move_cost ((machine_mode) mode, |
6f76a878 | 600 | (reg_class_t) cl, true); |
058e97ec VM |
601 | /* Costs for NO_REGS are used in cost calculation on the |
602 | 1st pass when the preferred register classes are not | |
603 | known yet. In this case we take the best scenario. */ | |
604 | if (ira_memory_move_cost[mode][NO_REGS][0] | |
605 | > ira_memory_move_cost[mode][cl][0]) | |
1756cb66 VM |
606 | ira_max_memory_move_cost[mode][NO_REGS][0] |
607 | = ira_memory_move_cost[mode][NO_REGS][0] | |
058e97ec VM |
608 | = ira_memory_move_cost[mode][cl][0]; |
609 | if (ira_memory_move_cost[mode][NO_REGS][1] | |
610 | > ira_memory_move_cost[mode][cl][1]) | |
1756cb66 VM |
611 | ira_max_memory_move_cost[mode][NO_REGS][1] |
612 | = ira_memory_move_cost[mode][NO_REGS][1] | |
058e97ec VM |
613 | = ira_memory_move_cost[mode][cl][1]; |
614 | } | |
058e97ec | 615 | } |
1756cb66 VM |
616 | for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) |
617 | for (cl2 = (int) N_REG_CLASSES - 1; cl2 >= 0; cl2--) | |
618 | { | |
619 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); | |
620 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
621 | COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl2]); | |
622 | AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs); | |
623 | ira_class_subset_p[cl][cl2] | |
624 | = hard_reg_set_subset_p (temp_hard_regset, temp_hard_regset2); | |
625 | if (! hard_reg_set_empty_p (temp_hard_regset2) | |
626 | && hard_reg_set_subset_p (reg_class_contents[cl2], | |
627 | reg_class_contents[cl])) | |
628 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
629 | { | |
630 | cost = ira_memory_move_cost[mode][cl2][0]; | |
631 | if (cost > ira_max_memory_move_cost[mode][cl][0]) | |
632 | ira_max_memory_move_cost[mode][cl][0] = cost; | |
633 | cost = ira_memory_move_cost[mode][cl2][1]; | |
634 | if (cost > ira_max_memory_move_cost[mode][cl][1]) | |
635 | ira_max_memory_move_cost[mode][cl][1] = cost; | |
636 | } | |
637 | } | |
638 | for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) | |
639 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
640 | { | |
641 | ira_memory_move_cost[mode][cl][0] | |
642 | = ira_max_memory_move_cost[mode][cl][0]; | |
643 | ira_memory_move_cost[mode][cl][1] | |
644 | = ira_max_memory_move_cost[mode][cl][1]; | |
645 | } | |
646 | setup_reg_subclasses (); | |
058e97ec VM |
647 | } |
648 | ||
649 | \f | |
650 | ||
651 | /* Define the following macro if allocation through malloc if | |
652 | preferable. */ | |
653 | #define IRA_NO_OBSTACK | |
654 | ||
655 | #ifndef IRA_NO_OBSTACK | |
656 | /* Obstack used for storing all dynamic data (except bitmaps) of the | |
657 | IRA. */ | |
658 | static struct obstack ira_obstack; | |
659 | #endif | |
660 | ||
661 | /* Obstack used for storing all bitmaps of the IRA. */ | |
662 | static struct bitmap_obstack ira_bitmap_obstack; | |
663 | ||
664 | /* Allocate memory of size LEN for IRA data. */ | |
665 | void * | |
666 | ira_allocate (size_t len) | |
667 | { | |
668 | void *res; | |
669 | ||
670 | #ifndef IRA_NO_OBSTACK | |
671 | res = obstack_alloc (&ira_obstack, len); | |
672 | #else | |
673 | res = xmalloc (len); | |
674 | #endif | |
675 | return res; | |
676 | } | |
677 | ||
058e97ec VM |
678 | /* Free memory ADDR allocated for IRA data. */ |
679 | void | |
680 | ira_free (void *addr ATTRIBUTE_UNUSED) | |
681 | { | |
682 | #ifndef IRA_NO_OBSTACK | |
683 | /* do nothing */ | |
684 | #else | |
685 | free (addr); | |
686 | #endif | |
687 | } | |
688 | ||
689 | ||
690 | /* Allocate and returns bitmap for IRA. */ | |
691 | bitmap | |
692 | ira_allocate_bitmap (void) | |
693 | { | |
694 | return BITMAP_ALLOC (&ira_bitmap_obstack); | |
695 | } | |
696 | ||
697 | /* Free bitmap B allocated for IRA. */ | |
698 | void | |
699 | ira_free_bitmap (bitmap b ATTRIBUTE_UNUSED) | |
700 | { | |
701 | /* do nothing */ | |
702 | } | |
703 | ||
704 | \f | |
705 | ||
706 | /* Output information about allocation of all allocnos (except for | |
707 | caps) into file F. */ | |
708 | void | |
709 | ira_print_disposition (FILE *f) | |
710 | { | |
711 | int i, n, max_regno; | |
712 | ira_allocno_t a; | |
713 | basic_block bb; | |
714 | ||
715 | fprintf (f, "Disposition:"); | |
716 | max_regno = max_reg_num (); | |
717 | for (n = 0, i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
718 | for (a = ira_regno_allocno_map[i]; | |
719 | a != NULL; | |
720 | a = ALLOCNO_NEXT_REGNO_ALLOCNO (a)) | |
721 | { | |
722 | if (n % 4 == 0) | |
723 | fprintf (f, "\n"); | |
724 | n++; | |
725 | fprintf (f, " %4d:r%-4d", ALLOCNO_NUM (a), ALLOCNO_REGNO (a)); | |
726 | if ((bb = ALLOCNO_LOOP_TREE_NODE (a)->bb) != NULL) | |
727 | fprintf (f, "b%-3d", bb->index); | |
728 | else | |
2608d841 | 729 | fprintf (f, "l%-3d", ALLOCNO_LOOP_TREE_NODE (a)->loop_num); |
058e97ec VM |
730 | if (ALLOCNO_HARD_REGNO (a) >= 0) |
731 | fprintf (f, " %3d", ALLOCNO_HARD_REGNO (a)); | |
732 | else | |
733 | fprintf (f, " mem"); | |
734 | } | |
735 | fprintf (f, "\n"); | |
736 | } | |
737 | ||
738 | /* Outputs information about allocation of all allocnos into | |
739 | stderr. */ | |
740 | void | |
741 | ira_debug_disposition (void) | |
742 | { | |
743 | ira_print_disposition (stderr); | |
744 | } | |
745 | ||
746 | \f | |
058e97ec | 747 | |
1756cb66 VM |
748 | /* Set up ira_stack_reg_pressure_class which is the biggest pressure |
749 | register class containing stack registers or NO_REGS if there are | |
750 | no stack registers. To find this class, we iterate through all | |
751 | register pressure classes and choose the first register pressure | |
752 | class containing all the stack registers and having the biggest | |
753 | size. */ | |
fe82cdfb | 754 | static void |
1756cb66 VM |
755 | setup_stack_reg_pressure_class (void) |
756 | { | |
757 | ira_stack_reg_pressure_class = NO_REGS; | |
758 | #ifdef STACK_REGS | |
759 | { | |
760 | int i, best, size; | |
761 | enum reg_class cl; | |
762 | HARD_REG_SET temp_hard_regset2; | |
763 | ||
764 | CLEAR_HARD_REG_SET (temp_hard_regset); | |
765 | for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++) | |
766 | SET_HARD_REG_BIT (temp_hard_regset, i); | |
767 | best = 0; | |
768 | for (i = 0; i < ira_pressure_classes_num; i++) | |
769 | { | |
770 | cl = ira_pressure_classes[i]; | |
771 | COPY_HARD_REG_SET (temp_hard_regset2, temp_hard_regset); | |
772 | AND_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl]); | |
773 | size = hard_reg_set_size (temp_hard_regset2); | |
774 | if (best < size) | |
775 | { | |
776 | best = size; | |
777 | ira_stack_reg_pressure_class = cl; | |
778 | } | |
779 | } | |
780 | } | |
781 | #endif | |
782 | } | |
783 | ||
784 | /* Find pressure classes which are register classes for which we | |
785 | calculate register pressure in IRA, register pressure sensitive | |
786 | insn scheduling, and register pressure sensitive loop invariant | |
787 | motion. | |
788 | ||
789 | To make register pressure calculation easy, we always use | |
790 | non-intersected register pressure classes. A move of hard | |
791 | registers from one register pressure class is not more expensive | |
792 | than load and store of the hard registers. Most likely an allocno | |
793 | class will be a subset of a register pressure class and in many | |
794 | cases a register pressure class. That makes usage of register | |
795 | pressure classes a good approximation to find a high register | |
796 | pressure. */ | |
797 | static void | |
798 | setup_pressure_classes (void) | |
058e97ec | 799 | { |
1756cb66 VM |
800 | int cost, i, n, curr; |
801 | int cl, cl2; | |
802 | enum reg_class pressure_classes[N_REG_CLASSES]; | |
803 | int m; | |
058e97ec | 804 | HARD_REG_SET temp_hard_regset2; |
1756cb66 | 805 | bool insert_p; |
058e97ec | 806 | |
1756cb66 VM |
807 | n = 0; |
808 | for (cl = 0; cl < N_REG_CLASSES; cl++) | |
058e97ec | 809 | { |
f508f827 | 810 | if (ira_class_hard_regs_num[cl] == 0) |
058e97ec | 811 | continue; |
f508f827 | 812 | if (ira_class_hard_regs_num[cl] != 1 |
574e418a VM |
813 | /* A register class without subclasses may contain a few |
814 | hard registers and movement between them is costly | |
815 | (e.g. SPARC FPCC registers). We still should consider it | |
816 | as a candidate for a pressure class. */ | |
af2b97c4 | 817 | && alloc_reg_class_subclasses[cl][0] < cl) |
1756cb66 | 818 | { |
113a5be6 VM |
819 | /* Check that the moves between any hard registers of the |
820 | current class are not more expensive for a legal mode | |
821 | than load/store of the hard registers of the current | |
822 | class. Such class is a potential candidate to be a | |
823 | register pressure class. */ | |
824 | for (m = 0; m < NUM_MACHINE_MODES; m++) | |
825 | { | |
826 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); | |
827 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
828 | AND_COMPL_HARD_REG_SET (temp_hard_regset, | |
829 | ira_prohibited_class_mode_regs[cl][m]); | |
830 | if (hard_reg_set_empty_p (temp_hard_regset)) | |
831 | continue; | |
ef4bddc2 | 832 | ira_init_register_move_cost_if_necessary ((machine_mode) m); |
113a5be6 VM |
833 | cost = ira_register_move_cost[m][cl][cl]; |
834 | if (cost <= ira_max_memory_move_cost[m][cl][1] | |
835 | || cost <= ira_max_memory_move_cost[m][cl][0]) | |
836 | break; | |
837 | } | |
838 | if (m >= NUM_MACHINE_MODES) | |
1756cb66 | 839 | continue; |
1756cb66 | 840 | } |
1756cb66 VM |
841 | curr = 0; |
842 | insert_p = true; | |
843 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); | |
844 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
845 | /* Remove so far added pressure classes which are subset of the | |
846 | current candidate class. Prefer GENERAL_REGS as a pressure | |
847 | register class to another class containing the same | |
848 | allocatable hard registers. We do this because machine | |
849 | dependent cost hooks might give wrong costs for the latter | |
850 | class but always give the right cost for the former class | |
851 | (GENERAL_REGS). */ | |
852 | for (i = 0; i < n; i++) | |
853 | { | |
854 | cl2 = pressure_classes[i]; | |
855 | COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl2]); | |
856 | AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs); | |
857 | if (hard_reg_set_subset_p (temp_hard_regset, temp_hard_regset2) | |
858 | && (! hard_reg_set_equal_p (temp_hard_regset, temp_hard_regset2) | |
859 | || cl2 == (int) GENERAL_REGS)) | |
860 | { | |
861 | pressure_classes[curr++] = (enum reg_class) cl2; | |
862 | insert_p = false; | |
058e97ec | 863 | continue; |
1756cb66 VM |
864 | } |
865 | if (hard_reg_set_subset_p (temp_hard_regset2, temp_hard_regset) | |
866 | && (! hard_reg_set_equal_p (temp_hard_regset2, temp_hard_regset) | |
867 | || cl == (int) GENERAL_REGS)) | |
868 | continue; | |
113a5be6 VM |
869 | if (hard_reg_set_equal_p (temp_hard_regset2, temp_hard_regset)) |
870 | insert_p = false; | |
1756cb66 VM |
871 | pressure_classes[curr++] = (enum reg_class) cl2; |
872 | } | |
873 | /* If the current candidate is a subset of a so far added | |
874 | pressure class, don't add it to the list of the pressure | |
875 | classes. */ | |
876 | if (insert_p) | |
877 | pressure_classes[curr++] = (enum reg_class) cl; | |
878 | n = curr; | |
fe82cdfb | 879 | } |
1756cb66 | 880 | #ifdef ENABLE_IRA_CHECKING |
113a5be6 VM |
881 | { |
882 | HARD_REG_SET ignore_hard_regs; | |
883 | ||
884 | /* Check pressure classes correctness: here we check that hard | |
885 | registers from all register pressure classes contains all hard | |
886 | registers available for the allocation. */ | |
887 | CLEAR_HARD_REG_SET (temp_hard_regset); | |
888 | CLEAR_HARD_REG_SET (temp_hard_regset2); | |
889 | COPY_HARD_REG_SET (ignore_hard_regs, no_unit_alloc_regs); | |
890 | for (cl = 0; cl < LIM_REG_CLASSES; cl++) | |
891 | { | |
892 | /* For some targets (like MIPS with MD_REGS), there are some | |
893 | classes with hard registers available for allocation but | |
894 | not able to hold value of any mode. */ | |
895 | for (m = 0; m < NUM_MACHINE_MODES; m++) | |
896 | if (contains_reg_of_mode[cl][m]) | |
897 | break; | |
898 | if (m >= NUM_MACHINE_MODES) | |
899 | { | |
900 | IOR_HARD_REG_SET (ignore_hard_regs, reg_class_contents[cl]); | |
901 | continue; | |
902 | } | |
903 | for (i = 0; i < n; i++) | |
904 | if ((int) pressure_classes[i] == cl) | |
905 | break; | |
906 | IOR_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl]); | |
907 | if (i < n) | |
908 | IOR_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); | |
909 | } | |
910 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
df3e3493 | 911 | /* Some targets (like SPARC with ICC reg) have allocatable regs |
113a5be6 VM |
912 | for which no reg class is defined. */ |
913 | if (REGNO_REG_CLASS (i) == NO_REGS) | |
914 | SET_HARD_REG_BIT (ignore_hard_regs, i); | |
915 | AND_COMPL_HARD_REG_SET (temp_hard_regset, ignore_hard_regs); | |
916 | AND_COMPL_HARD_REG_SET (temp_hard_regset2, ignore_hard_regs); | |
917 | ira_assert (hard_reg_set_subset_p (temp_hard_regset2, temp_hard_regset)); | |
918 | } | |
1756cb66 VM |
919 | #endif |
920 | ira_pressure_classes_num = 0; | |
921 | for (i = 0; i < n; i++) | |
922 | { | |
923 | cl = (int) pressure_classes[i]; | |
924 | ira_reg_pressure_class_p[cl] = true; | |
925 | ira_pressure_classes[ira_pressure_classes_num++] = (enum reg_class) cl; | |
926 | } | |
927 | setup_stack_reg_pressure_class (); | |
058e97ec VM |
928 | } |
929 | ||
165f639c VM |
930 | /* Set up IRA_UNIFORM_CLASS_P. Uniform class is a register class |
931 | whose register move cost between any registers of the class is the | |
932 | same as for all its subclasses. We use the data to speed up the | |
933 | 2nd pass of calculations of allocno costs. */ | |
934 | static void | |
935 | setup_uniform_class_p (void) | |
936 | { | |
937 | int i, cl, cl2, m; | |
938 | ||
939 | for (cl = 0; cl < N_REG_CLASSES; cl++) | |
940 | { | |
941 | ira_uniform_class_p[cl] = false; | |
942 | if (ira_class_hard_regs_num[cl] == 0) | |
943 | continue; | |
944 | /* We can not use alloc_reg_class_subclasses here because move | |
945 | cost hooks does not take into account that some registers are | |
946 | unavailable for the subtarget. E.g. for i686, INT_SSE_REGS | |
947 | is element of alloc_reg_class_subclasses for GENERAL_REGS | |
948 | because SSE regs are unavailable. */ | |
949 | for (i = 0; (cl2 = reg_class_subclasses[cl][i]) != LIM_REG_CLASSES; i++) | |
950 | { | |
951 | if (ira_class_hard_regs_num[cl2] == 0) | |
952 | continue; | |
953 | for (m = 0; m < NUM_MACHINE_MODES; m++) | |
954 | if (contains_reg_of_mode[cl][m] && contains_reg_of_mode[cl2][m]) | |
955 | { | |
ef4bddc2 | 956 | ira_init_register_move_cost_if_necessary ((machine_mode) m); |
165f639c VM |
957 | if (ira_register_move_cost[m][cl][cl] |
958 | != ira_register_move_cost[m][cl2][cl2]) | |
959 | break; | |
960 | } | |
961 | if (m < NUM_MACHINE_MODES) | |
962 | break; | |
963 | } | |
964 | if (cl2 == LIM_REG_CLASSES) | |
965 | ira_uniform_class_p[cl] = true; | |
966 | } | |
967 | } | |
968 | ||
1756cb66 VM |
969 | /* Set up IRA_ALLOCNO_CLASSES, IRA_ALLOCNO_CLASSES_NUM, |
970 | IRA_IMPORTANT_CLASSES, and IRA_IMPORTANT_CLASSES_NUM. | |
971 | ||
df3e3493 | 972 | Target may have many subtargets and not all target hard registers can |
1756cb66 VM |
973 | be used for allocation, e.g. x86 port in 32-bit mode can not use |
974 | hard registers introduced in x86-64 like r8-r15). Some classes | |
975 | might have the same allocatable hard registers, e.g. INDEX_REGS | |
976 | and GENERAL_REGS in x86 port in 32-bit mode. To decrease different | |
977 | calculations efforts we introduce allocno classes which contain | |
978 | unique non-empty sets of allocatable hard-registers. | |
979 | ||
980 | Pseudo class cost calculation in ira-costs.c is very expensive. | |
981 | Therefore we are trying to decrease number of classes involved in | |
982 | such calculation. Register classes used in the cost calculation | |
983 | are called important classes. They are allocno classes and other | |
984 | non-empty classes whose allocatable hard register sets are inside | |
985 | of an allocno class hard register set. From the first sight, it | |
986 | looks like that they are just allocno classes. It is not true. In | |
987 | example of x86-port in 32-bit mode, allocno classes will contain | |
988 | GENERAL_REGS but not LEGACY_REGS (because allocatable hard | |
989 | registers are the same for the both classes). The important | |
990 | classes will contain GENERAL_REGS and LEGACY_REGS. It is done | |
991 | because a machine description insn constraint may refers for | |
992 | LEGACY_REGS and code in ira-costs.c is mostly base on investigation | |
993 | of the insn constraints. */ | |
058e97ec | 994 | static void |
1756cb66 | 995 | setup_allocno_and_important_classes (void) |
058e97ec | 996 | { |
32e8bb8e | 997 | int i, j, n, cl; |
db1a8d98 | 998 | bool set_p; |
058e97ec | 999 | HARD_REG_SET temp_hard_regset2; |
7db7ed3c VM |
1000 | static enum reg_class classes[LIM_REG_CLASSES + 1]; |
1001 | ||
1756cb66 VM |
1002 | n = 0; |
1003 | /* Collect classes which contain unique sets of allocatable hard | |
1004 | registers. Prefer GENERAL_REGS to other classes containing the | |
1005 | same set of hard registers. */ | |
a58dfa49 | 1006 | for (i = 0; i < LIM_REG_CLASSES; i++) |
99710245 | 1007 | { |
1756cb66 VM |
1008 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[i]); |
1009 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
1010 | for (j = 0; j < n; j++) | |
7db7ed3c | 1011 | { |
1756cb66 VM |
1012 | cl = classes[j]; |
1013 | COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl]); | |
1014 | AND_COMPL_HARD_REG_SET (temp_hard_regset2, | |
1015 | no_unit_alloc_regs); | |
1016 | if (hard_reg_set_equal_p (temp_hard_regset, | |
1017 | temp_hard_regset2)) | |
1018 | break; | |
7db7ed3c | 1019 | } |
1756cb66 VM |
1020 | if (j >= n) |
1021 | classes[n++] = (enum reg_class) i; | |
1022 | else if (i == GENERAL_REGS) | |
1023 | /* Prefer general regs. For i386 example, it means that | |
1024 | we prefer GENERAL_REGS over INDEX_REGS or LEGACY_REGS | |
1025 | (all of them consists of the same available hard | |
1026 | registers). */ | |
1027 | classes[j] = (enum reg_class) i; | |
7db7ed3c | 1028 | } |
1756cb66 | 1029 | classes[n] = LIM_REG_CLASSES; |
058e97ec | 1030 | |
1756cb66 | 1031 | /* Set up classes which can be used for allocnos as classes |
df3e3493 | 1032 | containing non-empty unique sets of allocatable hard |
1756cb66 VM |
1033 | registers. */ |
1034 | ira_allocno_classes_num = 0; | |
058e97ec | 1035 | for (i = 0; (cl = classes[i]) != LIM_REG_CLASSES; i++) |
3e575fe2 | 1036 | if (ira_class_hard_regs_num[cl] > 0) |
1756cb66 | 1037 | ira_allocno_classes[ira_allocno_classes_num++] = (enum reg_class) cl; |
058e97ec | 1038 | ira_important_classes_num = 0; |
1756cb66 VM |
1039 | /* Add non-allocno classes containing to non-empty set of |
1040 | allocatable hard regs. */ | |
058e97ec | 1041 | for (cl = 0; cl < N_REG_CLASSES; cl++) |
3e575fe2 RS |
1042 | if (ira_class_hard_regs_num[cl] > 0) |
1043 | { | |
1044 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); | |
1045 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
1046 | set_p = false; | |
1047 | for (j = 0; j < ira_allocno_classes_num; j++) | |
1048 | { | |
1049 | COPY_HARD_REG_SET (temp_hard_regset2, | |
1050 | reg_class_contents[ira_allocno_classes[j]]); | |
1051 | AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs); | |
1052 | if ((enum reg_class) cl == ira_allocno_classes[j]) | |
1053 | break; | |
1054 | else if (hard_reg_set_subset_p (temp_hard_regset, | |
1055 | temp_hard_regset2)) | |
1056 | set_p = true; | |
1057 | } | |
1058 | if (set_p && j >= ira_allocno_classes_num) | |
1059 | ira_important_classes[ira_important_classes_num++] | |
1060 | = (enum reg_class) cl; | |
1061 | } | |
1756cb66 VM |
1062 | /* Now add allocno classes to the important classes. */ |
1063 | for (j = 0; j < ira_allocno_classes_num; j++) | |
db1a8d98 | 1064 | ira_important_classes[ira_important_classes_num++] |
1756cb66 VM |
1065 | = ira_allocno_classes[j]; |
1066 | for (cl = 0; cl < N_REG_CLASSES; cl++) | |
1067 | { | |
1068 | ira_reg_allocno_class_p[cl] = false; | |
1069 | ira_reg_pressure_class_p[cl] = false; | |
1070 | } | |
1071 | for (j = 0; j < ira_allocno_classes_num; j++) | |
1072 | ira_reg_allocno_class_p[ira_allocno_classes[j]] = true; | |
1073 | setup_pressure_classes (); | |
165f639c | 1074 | setup_uniform_class_p (); |
058e97ec | 1075 | } |
058e97ec | 1076 | |
1756cb66 VM |
1077 | /* Setup translation in CLASS_TRANSLATE of all classes into a class |
1078 | given by array CLASSES of length CLASSES_NUM. The function is used | |
1079 | make translation any reg class to an allocno class or to an | |
1080 | pressure class. This translation is necessary for some | |
1081 | calculations when we can use only allocno or pressure classes and | |
1082 | such translation represents an approximate representation of all | |
1083 | classes. | |
1084 | ||
1085 | The translation in case when allocatable hard register set of a | |
1086 | given class is subset of allocatable hard register set of a class | |
1087 | in CLASSES is pretty simple. We use smallest classes from CLASSES | |
1088 | containing a given class. If allocatable hard register set of a | |
1089 | given class is not a subset of any corresponding set of a class | |
1090 | from CLASSES, we use the cheapest (with load/store point of view) | |
2b9c63a2 | 1091 | class from CLASSES whose set intersects with given class set. */ |
058e97ec | 1092 | static void |
1756cb66 VM |
1093 | setup_class_translate_array (enum reg_class *class_translate, |
1094 | int classes_num, enum reg_class *classes) | |
058e97ec | 1095 | { |
32e8bb8e | 1096 | int cl, mode; |
1756cb66 | 1097 | enum reg_class aclass, best_class, *cl_ptr; |
058e97ec VM |
1098 | int i, cost, min_cost, best_cost; |
1099 | ||
1100 | for (cl = 0; cl < N_REG_CLASSES; cl++) | |
1756cb66 | 1101 | class_translate[cl] = NO_REGS; |
b8698a0f | 1102 | |
1756cb66 | 1103 | for (i = 0; i < classes_num; i++) |
058e97ec | 1104 | { |
1756cb66 VM |
1105 | aclass = classes[i]; |
1106 | for (cl_ptr = &alloc_reg_class_subclasses[aclass][0]; | |
1107 | (cl = *cl_ptr) != LIM_REG_CLASSES; | |
1108 | cl_ptr++) | |
1109 | if (class_translate[cl] == NO_REGS) | |
1110 | class_translate[cl] = aclass; | |
1111 | class_translate[aclass] = aclass; | |
058e97ec | 1112 | } |
1756cb66 VM |
1113 | /* For classes which are not fully covered by one of given classes |
1114 | (in other words covered by more one given class), use the | |
1115 | cheapest class. */ | |
058e97ec VM |
1116 | for (cl = 0; cl < N_REG_CLASSES; cl++) |
1117 | { | |
1756cb66 | 1118 | if (cl == NO_REGS || class_translate[cl] != NO_REGS) |
058e97ec VM |
1119 | continue; |
1120 | best_class = NO_REGS; | |
1121 | best_cost = INT_MAX; | |
1756cb66 | 1122 | for (i = 0; i < classes_num; i++) |
058e97ec | 1123 | { |
1756cb66 | 1124 | aclass = classes[i]; |
058e97ec | 1125 | COPY_HARD_REG_SET (temp_hard_regset, |
1756cb66 | 1126 | reg_class_contents[aclass]); |
058e97ec VM |
1127 | AND_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); |
1128 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
4f341ea0 | 1129 | if (! hard_reg_set_empty_p (temp_hard_regset)) |
058e97ec VM |
1130 | { |
1131 | min_cost = INT_MAX; | |
1132 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
1133 | { | |
761a8eb7 VM |
1134 | cost = (ira_memory_move_cost[mode][aclass][0] |
1135 | + ira_memory_move_cost[mode][aclass][1]); | |
058e97ec VM |
1136 | if (min_cost > cost) |
1137 | min_cost = cost; | |
1138 | } | |
1139 | if (best_class == NO_REGS || best_cost > min_cost) | |
1140 | { | |
1756cb66 | 1141 | best_class = aclass; |
058e97ec VM |
1142 | best_cost = min_cost; |
1143 | } | |
1144 | } | |
1145 | } | |
1756cb66 | 1146 | class_translate[cl] = best_class; |
058e97ec VM |
1147 | } |
1148 | } | |
058e97ec | 1149 | |
1756cb66 VM |
1150 | /* Set up array IRA_ALLOCNO_CLASS_TRANSLATE and |
1151 | IRA_PRESSURE_CLASS_TRANSLATE. */ | |
1152 | static void | |
1153 | setup_class_translate (void) | |
1154 | { | |
1155 | setup_class_translate_array (ira_allocno_class_translate, | |
1156 | ira_allocno_classes_num, ira_allocno_classes); | |
1157 | setup_class_translate_array (ira_pressure_class_translate, | |
1158 | ira_pressure_classes_num, ira_pressure_classes); | |
1159 | } | |
1160 | ||
1161 | /* Order numbers of allocno classes in original target allocno class | |
1162 | array, -1 for non-allocno classes. */ | |
1163 | static int allocno_class_order[N_REG_CLASSES]; | |
db1a8d98 VM |
1164 | |
1165 | /* The function used to sort the important classes. */ | |
1166 | static int | |
1167 | comp_reg_classes_func (const void *v1p, const void *v2p) | |
1168 | { | |
1169 | enum reg_class cl1 = *(const enum reg_class *) v1p; | |
1170 | enum reg_class cl2 = *(const enum reg_class *) v2p; | |
1756cb66 | 1171 | enum reg_class tcl1, tcl2; |
db1a8d98 VM |
1172 | int diff; |
1173 | ||
1756cb66 VM |
1174 | tcl1 = ira_allocno_class_translate[cl1]; |
1175 | tcl2 = ira_allocno_class_translate[cl2]; | |
1176 | if (tcl1 != NO_REGS && tcl2 != NO_REGS | |
1177 | && (diff = allocno_class_order[tcl1] - allocno_class_order[tcl2]) != 0) | |
db1a8d98 VM |
1178 | return diff; |
1179 | return (int) cl1 - (int) cl2; | |
1180 | } | |
1181 | ||
1756cb66 VM |
1182 | /* For correct work of function setup_reg_class_relation we need to |
1183 | reorder important classes according to the order of their allocno | |
1184 | classes. It places important classes containing the same | |
1185 | allocatable hard register set adjacent to each other and allocno | |
1186 | class with the allocatable hard register set right after the other | |
1187 | important classes with the same set. | |
1188 | ||
1189 | In example from comments of function | |
1190 | setup_allocno_and_important_classes, it places LEGACY_REGS and | |
1191 | GENERAL_REGS close to each other and GENERAL_REGS is after | |
1192 | LEGACY_REGS. */ | |
db1a8d98 VM |
1193 | static void |
1194 | reorder_important_classes (void) | |
1195 | { | |
1196 | int i; | |
1197 | ||
1198 | for (i = 0; i < N_REG_CLASSES; i++) | |
1756cb66 VM |
1199 | allocno_class_order[i] = -1; |
1200 | for (i = 0; i < ira_allocno_classes_num; i++) | |
1201 | allocno_class_order[ira_allocno_classes[i]] = i; | |
db1a8d98 VM |
1202 | qsort (ira_important_classes, ira_important_classes_num, |
1203 | sizeof (enum reg_class), comp_reg_classes_func); | |
1756cb66 VM |
1204 | for (i = 0; i < ira_important_classes_num; i++) |
1205 | ira_important_class_nums[ira_important_classes[i]] = i; | |
db1a8d98 VM |
1206 | } |
1207 | ||
1756cb66 VM |
1208 | /* Set up IRA_REG_CLASS_SUBUNION, IRA_REG_CLASS_SUPERUNION, |
1209 | IRA_REG_CLASS_SUPER_CLASSES, IRA_REG_CLASSES_INTERSECT, and | |
1210 | IRA_REG_CLASSES_INTERSECT_P. For the meaning of the relations, | |
1211 | please see corresponding comments in ira-int.h. */ | |
058e97ec | 1212 | static void |
7db7ed3c | 1213 | setup_reg_class_relations (void) |
058e97ec VM |
1214 | { |
1215 | int i, cl1, cl2, cl3; | |
1216 | HARD_REG_SET intersection_set, union_set, temp_set2; | |
7db7ed3c | 1217 | bool important_class_p[N_REG_CLASSES]; |
058e97ec | 1218 | |
7db7ed3c VM |
1219 | memset (important_class_p, 0, sizeof (important_class_p)); |
1220 | for (i = 0; i < ira_important_classes_num; i++) | |
1221 | important_class_p[ira_important_classes[i]] = true; | |
058e97ec VM |
1222 | for (cl1 = 0; cl1 < N_REG_CLASSES; cl1++) |
1223 | { | |
7db7ed3c | 1224 | ira_reg_class_super_classes[cl1][0] = LIM_REG_CLASSES; |
058e97ec VM |
1225 | for (cl2 = 0; cl2 < N_REG_CLASSES; cl2++) |
1226 | { | |
7db7ed3c | 1227 | ira_reg_classes_intersect_p[cl1][cl2] = false; |
058e97ec | 1228 | ira_reg_class_intersect[cl1][cl2] = NO_REGS; |
55a2c322 | 1229 | ira_reg_class_subset[cl1][cl2] = NO_REGS; |
058e97ec VM |
1230 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl1]); |
1231 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
1232 | COPY_HARD_REG_SET (temp_set2, reg_class_contents[cl2]); | |
1233 | AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs); | |
4f341ea0 RS |
1234 | if (hard_reg_set_empty_p (temp_hard_regset) |
1235 | && hard_reg_set_empty_p (temp_set2)) | |
058e97ec | 1236 | { |
1756cb66 VM |
1237 | /* The both classes have no allocatable hard registers |
1238 | -- take all class hard registers into account and use | |
1239 | reg_class_subunion and reg_class_superunion. */ | |
058e97ec VM |
1240 | for (i = 0;; i++) |
1241 | { | |
1242 | cl3 = reg_class_subclasses[cl1][i]; | |
1243 | if (cl3 == LIM_REG_CLASSES) | |
1244 | break; | |
1245 | if (reg_class_subset_p (ira_reg_class_intersect[cl1][cl2], | |
bbbbb16a ILT |
1246 | (enum reg_class) cl3)) |
1247 | ira_reg_class_intersect[cl1][cl2] = (enum reg_class) cl3; | |
058e97ec | 1248 | } |
1756cb66 VM |
1249 | ira_reg_class_subunion[cl1][cl2] = reg_class_subunion[cl1][cl2]; |
1250 | ira_reg_class_superunion[cl1][cl2] = reg_class_superunion[cl1][cl2]; | |
058e97ec VM |
1251 | continue; |
1252 | } | |
7db7ed3c VM |
1253 | ira_reg_classes_intersect_p[cl1][cl2] |
1254 | = hard_reg_set_intersect_p (temp_hard_regset, temp_set2); | |
1255 | if (important_class_p[cl1] && important_class_p[cl2] | |
1256 | && hard_reg_set_subset_p (temp_hard_regset, temp_set2)) | |
1257 | { | |
1756cb66 VM |
1258 | /* CL1 and CL2 are important classes and CL1 allocatable |
1259 | hard register set is inside of CL2 allocatable hard | |
1260 | registers -- make CL1 a superset of CL2. */ | |
7db7ed3c VM |
1261 | enum reg_class *p; |
1262 | ||
1263 | p = &ira_reg_class_super_classes[cl1][0]; | |
1264 | while (*p != LIM_REG_CLASSES) | |
1265 | p++; | |
1266 | *p++ = (enum reg_class) cl2; | |
1267 | *p = LIM_REG_CLASSES; | |
1268 | } | |
1756cb66 VM |
1269 | ira_reg_class_subunion[cl1][cl2] = NO_REGS; |
1270 | ira_reg_class_superunion[cl1][cl2] = NO_REGS; | |
058e97ec VM |
1271 | COPY_HARD_REG_SET (intersection_set, reg_class_contents[cl1]); |
1272 | AND_HARD_REG_SET (intersection_set, reg_class_contents[cl2]); | |
1273 | AND_COMPL_HARD_REG_SET (intersection_set, no_unit_alloc_regs); | |
1274 | COPY_HARD_REG_SET (union_set, reg_class_contents[cl1]); | |
1275 | IOR_HARD_REG_SET (union_set, reg_class_contents[cl2]); | |
1276 | AND_COMPL_HARD_REG_SET (union_set, no_unit_alloc_regs); | |
55a2c322 | 1277 | for (cl3 = 0; cl3 < N_REG_CLASSES; cl3++) |
058e97ec | 1278 | { |
058e97ec VM |
1279 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl3]); |
1280 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
1281 | if (hard_reg_set_subset_p (temp_hard_regset, intersection_set)) | |
1282 | { | |
1756cb66 VM |
1283 | /* CL3 allocatable hard register set is inside of |
1284 | intersection of allocatable hard register sets | |
1285 | of CL1 and CL2. */ | |
55a2c322 VM |
1286 | if (important_class_p[cl3]) |
1287 | { | |
1288 | COPY_HARD_REG_SET | |
1289 | (temp_set2, | |
1290 | reg_class_contents | |
1291 | [(int) ira_reg_class_intersect[cl1][cl2]]); | |
1292 | AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs); | |
1293 | if (! hard_reg_set_subset_p (temp_hard_regset, temp_set2) | |
1294 | /* If the allocatable hard register sets are | |
1295 | the same, prefer GENERAL_REGS or the | |
1296 | smallest class for debugging | |
1297 | purposes. */ | |
1298 | || (hard_reg_set_equal_p (temp_hard_regset, temp_set2) | |
1299 | && (cl3 == GENERAL_REGS | |
1300 | || ((ira_reg_class_intersect[cl1][cl2] | |
1301 | != GENERAL_REGS) | |
1302 | && hard_reg_set_subset_p | |
1303 | (reg_class_contents[cl3], | |
1304 | reg_class_contents | |
1305 | [(int) | |
1306 | ira_reg_class_intersect[cl1][cl2]]))))) | |
1307 | ira_reg_class_intersect[cl1][cl2] = (enum reg_class) cl3; | |
1308 | } | |
058e97ec VM |
1309 | COPY_HARD_REG_SET |
1310 | (temp_set2, | |
55a2c322 | 1311 | reg_class_contents[(int) ira_reg_class_subset[cl1][cl2]]); |
058e97ec | 1312 | AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs); |
55a2c322 VM |
1313 | if (! hard_reg_set_subset_p (temp_hard_regset, temp_set2) |
1314 | /* Ignore unavailable hard registers and prefer | |
1315 | smallest class for debugging purposes. */ | |
058e97ec | 1316 | || (hard_reg_set_equal_p (temp_hard_regset, temp_set2) |
55a2c322 VM |
1317 | && hard_reg_set_subset_p |
1318 | (reg_class_contents[cl3], | |
1319 | reg_class_contents | |
1320 | [(int) ira_reg_class_subset[cl1][cl2]]))) | |
1321 | ira_reg_class_subset[cl1][cl2] = (enum reg_class) cl3; | |
058e97ec | 1322 | } |
55a2c322 VM |
1323 | if (important_class_p[cl3] |
1324 | && hard_reg_set_subset_p (temp_hard_regset, union_set)) | |
058e97ec | 1325 | { |
df3e3493 | 1326 | /* CL3 allocatable hard register set is inside of |
1756cb66 VM |
1327 | union of allocatable hard register sets of CL1 |
1328 | and CL2. */ | |
058e97ec VM |
1329 | COPY_HARD_REG_SET |
1330 | (temp_set2, | |
1756cb66 | 1331 | reg_class_contents[(int) ira_reg_class_subunion[cl1][cl2]]); |
058e97ec | 1332 | AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs); |
1756cb66 | 1333 | if (ira_reg_class_subunion[cl1][cl2] == NO_REGS |
058e97ec | 1334 | || (hard_reg_set_subset_p (temp_set2, temp_hard_regset) |
1756cb66 VM |
1335 | |
1336 | && (! hard_reg_set_equal_p (temp_set2, | |
1337 | temp_hard_regset) | |
1338 | || cl3 == GENERAL_REGS | |
1339 | /* If the allocatable hard register sets are the | |
1340 | same, prefer GENERAL_REGS or the smallest | |
1341 | class for debugging purposes. */ | |
1342 | || (ira_reg_class_subunion[cl1][cl2] != GENERAL_REGS | |
1343 | && hard_reg_set_subset_p | |
1344 | (reg_class_contents[cl3], | |
1345 | reg_class_contents | |
1346 | [(int) ira_reg_class_subunion[cl1][cl2]]))))) | |
1347 | ira_reg_class_subunion[cl1][cl2] = (enum reg_class) cl3; | |
1348 | } | |
1349 | if (hard_reg_set_subset_p (union_set, temp_hard_regset)) | |
1350 | { | |
1351 | /* CL3 allocatable hard register set contains union | |
1352 | of allocatable hard register sets of CL1 and | |
1353 | CL2. */ | |
1354 | COPY_HARD_REG_SET | |
1355 | (temp_set2, | |
1356 | reg_class_contents[(int) ira_reg_class_superunion[cl1][cl2]]); | |
1357 | AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs); | |
1358 | if (ira_reg_class_superunion[cl1][cl2] == NO_REGS | |
1359 | || (hard_reg_set_subset_p (temp_hard_regset, temp_set2) | |
b8698a0f | 1360 | |
058e97ec VM |
1361 | && (! hard_reg_set_equal_p (temp_set2, |
1362 | temp_hard_regset) | |
1756cb66 VM |
1363 | || cl3 == GENERAL_REGS |
1364 | /* If the allocatable hard register sets are the | |
1365 | same, prefer GENERAL_REGS or the smallest | |
1366 | class for debugging purposes. */ | |
1367 | || (ira_reg_class_superunion[cl1][cl2] != GENERAL_REGS | |
1368 | && hard_reg_set_subset_p | |
1369 | (reg_class_contents[cl3], | |
1370 | reg_class_contents | |
1371 | [(int) ira_reg_class_superunion[cl1][cl2]]))))) | |
1372 | ira_reg_class_superunion[cl1][cl2] = (enum reg_class) cl3; | |
058e97ec VM |
1373 | } |
1374 | } | |
1375 | } | |
1376 | } | |
1377 | } | |
1378 | ||
df3e3493 | 1379 | /* Output all uniform and important classes into file F. */ |
165f639c VM |
1380 | static void |
1381 | print_unform_and_important_classes (FILE *f) | |
1382 | { | |
1383 | static const char *const reg_class_names[] = REG_CLASS_NAMES; | |
1384 | int i, cl; | |
1385 | ||
1386 | fprintf (f, "Uniform classes:\n"); | |
1387 | for (cl = 0; cl < N_REG_CLASSES; cl++) | |
1388 | if (ira_uniform_class_p[cl]) | |
1389 | fprintf (f, " %s", reg_class_names[cl]); | |
1390 | fprintf (f, "\nImportant classes:\n"); | |
1391 | for (i = 0; i < ira_important_classes_num; i++) | |
1392 | fprintf (f, " %s", reg_class_names[ira_important_classes[i]]); | |
1393 | fprintf (f, "\n"); | |
1394 | } | |
1395 | ||
1396 | /* Output all possible allocno or pressure classes and their | |
1397 | translation map into file F. */ | |
058e97ec | 1398 | static void |
165f639c | 1399 | print_translated_classes (FILE *f, bool pressure_p) |
1756cb66 VM |
1400 | { |
1401 | int classes_num = (pressure_p | |
1402 | ? ira_pressure_classes_num : ira_allocno_classes_num); | |
1403 | enum reg_class *classes = (pressure_p | |
1404 | ? ira_pressure_classes : ira_allocno_classes); | |
1405 | enum reg_class *class_translate = (pressure_p | |
1406 | ? ira_pressure_class_translate | |
1407 | : ira_allocno_class_translate); | |
058e97ec VM |
1408 | static const char *const reg_class_names[] = REG_CLASS_NAMES; |
1409 | int i; | |
1410 | ||
1756cb66 VM |
1411 | fprintf (f, "%s classes:\n", pressure_p ? "Pressure" : "Allocno"); |
1412 | for (i = 0; i < classes_num; i++) | |
1413 | fprintf (f, " %s", reg_class_names[classes[i]]); | |
058e97ec VM |
1414 | fprintf (f, "\nClass translation:\n"); |
1415 | for (i = 0; i < N_REG_CLASSES; i++) | |
1416 | fprintf (f, " %s -> %s\n", reg_class_names[i], | |
1756cb66 | 1417 | reg_class_names[class_translate[i]]); |
058e97ec VM |
1418 | } |
1419 | ||
1756cb66 VM |
1420 | /* Output all possible allocno and translation classes and the |
1421 | translation maps into stderr. */ | |
058e97ec | 1422 | void |
1756cb66 | 1423 | ira_debug_allocno_classes (void) |
058e97ec | 1424 | { |
165f639c VM |
1425 | print_unform_and_important_classes (stderr); |
1426 | print_translated_classes (stderr, false); | |
1427 | print_translated_classes (stderr, true); | |
058e97ec VM |
1428 | } |
1429 | ||
1756cb66 | 1430 | /* Set up different arrays concerning class subsets, allocno and |
058e97ec VM |
1431 | important classes. */ |
1432 | static void | |
1756cb66 | 1433 | find_reg_classes (void) |
058e97ec | 1434 | { |
1756cb66 | 1435 | setup_allocno_and_important_classes (); |
7db7ed3c | 1436 | setup_class_translate (); |
db1a8d98 | 1437 | reorder_important_classes (); |
7db7ed3c | 1438 | setup_reg_class_relations (); |
058e97ec VM |
1439 | } |
1440 | ||
1441 | \f | |
1442 | ||
c0683a82 VM |
1443 | /* Set up the array above. */ |
1444 | static void | |
1756cb66 | 1445 | setup_hard_regno_aclass (void) |
c0683a82 | 1446 | { |
7efcf910 | 1447 | int i; |
c0683a82 VM |
1448 | |
1449 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1450 | { | |
1756cb66 VM |
1451 | #if 1 |
1452 | ira_hard_regno_allocno_class[i] | |
7efcf910 CLT |
1453 | = (TEST_HARD_REG_BIT (no_unit_alloc_regs, i) |
1454 | ? NO_REGS | |
1756cb66 VM |
1455 | : ira_allocno_class_translate[REGNO_REG_CLASS (i)]); |
1456 | #else | |
1457 | int j; | |
1458 | enum reg_class cl; | |
1459 | ira_hard_regno_allocno_class[i] = NO_REGS; | |
1460 | for (j = 0; j < ira_allocno_classes_num; j++) | |
1461 | { | |
1462 | cl = ira_allocno_classes[j]; | |
1463 | if (ira_class_hard_reg_index[cl][i] >= 0) | |
1464 | { | |
1465 | ira_hard_regno_allocno_class[i] = cl; | |
1466 | break; | |
1467 | } | |
1468 | } | |
1469 | #endif | |
c0683a82 VM |
1470 | } |
1471 | } | |
1472 | ||
1473 | \f | |
1474 | ||
1756cb66 | 1475 | /* Form IRA_REG_CLASS_MAX_NREGS and IRA_REG_CLASS_MIN_NREGS maps. */ |
058e97ec VM |
1476 | static void |
1477 | setup_reg_class_nregs (void) | |
1478 | { | |
1756cb66 | 1479 | int i, cl, cl2, m; |
058e97ec | 1480 | |
1756cb66 VM |
1481 | for (m = 0; m < MAX_MACHINE_MODE; m++) |
1482 | { | |
1483 | for (cl = 0; cl < N_REG_CLASSES; cl++) | |
1484 | ira_reg_class_max_nregs[cl][m] | |
1485 | = ira_reg_class_min_nregs[cl][m] | |
ef4bddc2 | 1486 | = targetm.class_max_nregs ((reg_class_t) cl, (machine_mode) m); |
1756cb66 VM |
1487 | for (cl = 0; cl < N_REG_CLASSES; cl++) |
1488 | for (i = 0; | |
1489 | (cl2 = alloc_reg_class_subclasses[cl][i]) != LIM_REG_CLASSES; | |
1490 | i++) | |
1491 | if (ira_reg_class_min_nregs[cl2][m] | |
1492 | < ira_reg_class_min_nregs[cl][m]) | |
1493 | ira_reg_class_min_nregs[cl][m] = ira_reg_class_min_nregs[cl2][m]; | |
1494 | } | |
058e97ec VM |
1495 | } |
1496 | ||
1497 | \f | |
1498 | ||
c9d74da6 RS |
1499 | /* Set up IRA_PROHIBITED_CLASS_MODE_REGS and IRA_CLASS_SINGLETON. |
1500 | This function is called once IRA_CLASS_HARD_REGS has been initialized. */ | |
058e97ec VM |
1501 | static void |
1502 | setup_prohibited_class_mode_regs (void) | |
1503 | { | |
c9d74da6 | 1504 | int j, k, hard_regno, cl, last_hard_regno, count; |
058e97ec | 1505 | |
1756cb66 | 1506 | for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) |
058e97ec | 1507 | { |
c9d74da6 RS |
1508 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); |
1509 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
058e97ec VM |
1510 | for (j = 0; j < NUM_MACHINE_MODES; j++) |
1511 | { | |
c9d74da6 RS |
1512 | count = 0; |
1513 | last_hard_regno = -1; | |
1756cb66 | 1514 | CLEAR_HARD_REG_SET (ira_prohibited_class_mode_regs[cl][j]); |
058e97ec VM |
1515 | for (k = ira_class_hard_regs_num[cl] - 1; k >= 0; k--) |
1516 | { | |
1517 | hard_regno = ira_class_hard_regs[cl][k]; | |
ef4bddc2 | 1518 | if (! HARD_REGNO_MODE_OK (hard_regno, (machine_mode) j)) |
1756cb66 | 1519 | SET_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j], |
058e97ec | 1520 | hard_regno); |
c9d74da6 | 1521 | else if (in_hard_reg_set_p (temp_hard_regset, |
ef4bddc2 | 1522 | (machine_mode) j, hard_regno)) |
c9d74da6 RS |
1523 | { |
1524 | last_hard_regno = hard_regno; | |
1525 | count++; | |
1526 | } | |
058e97ec | 1527 | } |
c9d74da6 | 1528 | ira_class_singleton[cl][j] = (count == 1 ? last_hard_regno : -1); |
058e97ec VM |
1529 | } |
1530 | } | |
1531 | } | |
1532 | ||
1756cb66 VM |
1533 | /* Clarify IRA_PROHIBITED_CLASS_MODE_REGS by excluding hard registers |
1534 | spanning from one register pressure class to another one. It is | |
1535 | called after defining the pressure classes. */ | |
1536 | static void | |
1537 | clarify_prohibited_class_mode_regs (void) | |
1538 | { | |
1539 | int j, k, hard_regno, cl, pclass, nregs; | |
1540 | ||
1541 | for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) | |
1542 | for (j = 0; j < NUM_MACHINE_MODES; j++) | |
a2c19e93 RS |
1543 | { |
1544 | CLEAR_HARD_REG_SET (ira_useful_class_mode_regs[cl][j]); | |
1545 | for (k = ira_class_hard_regs_num[cl] - 1; k >= 0; k--) | |
1546 | { | |
1547 | hard_regno = ira_class_hard_regs[cl][k]; | |
1548 | if (TEST_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j], hard_regno)) | |
1549 | continue; | |
1550 | nregs = hard_regno_nregs[hard_regno][j]; | |
1551 | if (hard_regno + nregs > FIRST_PSEUDO_REGISTER) | |
1756cb66 VM |
1552 | { |
1553 | SET_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j], | |
1554 | hard_regno); | |
a2c19e93 | 1555 | continue; |
1756cb66 | 1556 | } |
a2c19e93 RS |
1557 | pclass = ira_pressure_class_translate[REGNO_REG_CLASS (hard_regno)]; |
1558 | for (nregs-- ;nregs >= 0; nregs--) | |
1559 | if (((enum reg_class) pclass | |
1560 | != ira_pressure_class_translate[REGNO_REG_CLASS | |
1561 | (hard_regno + nregs)])) | |
1562 | { | |
1563 | SET_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j], | |
1564 | hard_regno); | |
1565 | break; | |
1566 | } | |
1567 | if (!TEST_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j], | |
1568 | hard_regno)) | |
1569 | add_to_hard_reg_set (&ira_useful_class_mode_regs[cl][j], | |
ef4bddc2 | 1570 | (machine_mode) j, hard_regno); |
a2c19e93 RS |
1571 | } |
1572 | } | |
1756cb66 | 1573 | } |
058e97ec | 1574 | \f |
7cc61ee4 RS |
1575 | /* Allocate and initialize IRA_REGISTER_MOVE_COST, IRA_MAY_MOVE_IN_COST |
1576 | and IRA_MAY_MOVE_OUT_COST for MODE. */ | |
1577 | void | |
ef4bddc2 | 1578 | ira_init_register_move_cost (machine_mode mode) |
e80ccebc RS |
1579 | { |
1580 | static unsigned short last_move_cost[N_REG_CLASSES][N_REG_CLASSES]; | |
1581 | bool all_match = true; | |
ed9e2ed0 | 1582 | unsigned int cl1, cl2; |
e80ccebc | 1583 | |
7cc61ee4 RS |
1584 | ira_assert (ira_register_move_cost[mode] == NULL |
1585 | && ira_may_move_in_cost[mode] == NULL | |
1586 | && ira_may_move_out_cost[mode] == NULL); | |
ed9e2ed0 RS |
1587 | ira_assert (have_regs_of_mode[mode]); |
1588 | for (cl1 = 0; cl1 < N_REG_CLASSES; cl1++) | |
fef37404 VM |
1589 | for (cl2 = 0; cl2 < N_REG_CLASSES; cl2++) |
1590 | { | |
1591 | int cost; | |
1592 | if (!contains_reg_of_mode[cl1][mode] | |
1593 | || !contains_reg_of_mode[cl2][mode]) | |
1594 | { | |
1595 | if ((ira_reg_class_max_nregs[cl1][mode] | |
1596 | > ira_class_hard_regs_num[cl1]) | |
1597 | || (ira_reg_class_max_nregs[cl2][mode] | |
1598 | > ira_class_hard_regs_num[cl2])) | |
1599 | cost = 65535; | |
1600 | else | |
1601 | cost = (ira_memory_move_cost[mode][cl1][0] | |
1a788c05 | 1602 | + ira_memory_move_cost[mode][cl2][1]) * 2; |
fef37404 VM |
1603 | } |
1604 | else | |
1605 | { | |
1606 | cost = register_move_cost (mode, (enum reg_class) cl1, | |
1607 | (enum reg_class) cl2); | |
1608 | ira_assert (cost < 65535); | |
1609 | } | |
1610 | all_match &= (last_move_cost[cl1][cl2] == cost); | |
1611 | last_move_cost[cl1][cl2] = cost; | |
1612 | } | |
e80ccebc RS |
1613 | if (all_match && last_mode_for_init_move_cost != -1) |
1614 | { | |
7cc61ee4 RS |
1615 | ira_register_move_cost[mode] |
1616 | = ira_register_move_cost[last_mode_for_init_move_cost]; | |
1617 | ira_may_move_in_cost[mode] | |
1618 | = ira_may_move_in_cost[last_mode_for_init_move_cost]; | |
1619 | ira_may_move_out_cost[mode] | |
1620 | = ira_may_move_out_cost[last_mode_for_init_move_cost]; | |
e80ccebc RS |
1621 | return; |
1622 | } | |
ed9e2ed0 | 1623 | last_mode_for_init_move_cost = mode; |
7cc61ee4 RS |
1624 | ira_register_move_cost[mode] = XNEWVEC (move_table, N_REG_CLASSES); |
1625 | ira_may_move_in_cost[mode] = XNEWVEC (move_table, N_REG_CLASSES); | |
1626 | ira_may_move_out_cost[mode] = XNEWVEC (move_table, N_REG_CLASSES); | |
ed9e2ed0 | 1627 | for (cl1 = 0; cl1 < N_REG_CLASSES; cl1++) |
fef37404 VM |
1628 | for (cl2 = 0; cl2 < N_REG_CLASSES; cl2++) |
1629 | { | |
1630 | int cost; | |
1631 | enum reg_class *p1, *p2; | |
1632 | ||
1633 | if (last_move_cost[cl1][cl2] == 65535) | |
1634 | { | |
1635 | ira_register_move_cost[mode][cl1][cl2] = 65535; | |
1636 | ira_may_move_in_cost[mode][cl1][cl2] = 65535; | |
1637 | ira_may_move_out_cost[mode][cl1][cl2] = 65535; | |
1638 | } | |
1639 | else | |
1640 | { | |
1641 | cost = last_move_cost[cl1][cl2]; | |
1642 | ||
1643 | for (p2 = ®_class_subclasses[cl2][0]; | |
1644 | *p2 != LIM_REG_CLASSES; p2++) | |
1645 | if (ira_class_hard_regs_num[*p2] > 0 | |
1646 | && (ira_reg_class_max_nregs[*p2][mode] | |
1647 | <= ira_class_hard_regs_num[*p2])) | |
1648 | cost = MAX (cost, ira_register_move_cost[mode][cl1][*p2]); | |
1649 | ||
1650 | for (p1 = ®_class_subclasses[cl1][0]; | |
1651 | *p1 != LIM_REG_CLASSES; p1++) | |
1652 | if (ira_class_hard_regs_num[*p1] > 0 | |
1653 | && (ira_reg_class_max_nregs[*p1][mode] | |
1654 | <= ira_class_hard_regs_num[*p1])) | |
1655 | cost = MAX (cost, ira_register_move_cost[mode][*p1][cl2]); | |
1656 | ||
1657 | ira_assert (cost <= 65535); | |
1658 | ira_register_move_cost[mode][cl1][cl2] = cost; | |
1659 | ||
1660 | if (ira_class_subset_p[cl1][cl2]) | |
1661 | ira_may_move_in_cost[mode][cl1][cl2] = 0; | |
1662 | else | |
1663 | ira_may_move_in_cost[mode][cl1][cl2] = cost; | |
1664 | ||
1665 | if (ira_class_subset_p[cl2][cl1]) | |
1666 | ira_may_move_out_cost[mode][cl1][cl2] = 0; | |
1667 | else | |
1668 | ira_may_move_out_cost[mode][cl1][cl2] = cost; | |
1669 | } | |
1670 | } | |
058e97ec | 1671 | } |
fef37404 | 1672 | |
058e97ec VM |
1673 | \f |
1674 | ||
058e97ec VM |
1675 | /* This is called once during compiler work. It sets up |
1676 | different arrays whose values don't depend on the compiled | |
1677 | function. */ | |
1678 | void | |
1679 | ira_init_once (void) | |
1680 | { | |
058e97ec | 1681 | ira_init_costs_once (); |
55a2c322 | 1682 | lra_init_once (); |
058e97ec VM |
1683 | } |
1684 | ||
7cc61ee4 RS |
1685 | /* Free ira_max_register_move_cost, ira_may_move_in_cost and |
1686 | ira_may_move_out_cost for each mode. */ | |
19c708dc RS |
1687 | void |
1688 | target_ira_int::free_register_move_costs (void) | |
058e97ec | 1689 | { |
e80ccebc | 1690 | int mode, i; |
058e97ec | 1691 | |
e80ccebc RS |
1692 | /* Reset move_cost and friends, making sure we only free shared |
1693 | table entries once. */ | |
1694 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
19c708dc | 1695 | if (x_ira_register_move_cost[mode]) |
e80ccebc | 1696 | { |
7cc61ee4 | 1697 | for (i = 0; |
19c708dc RS |
1698 | i < mode && (x_ira_register_move_cost[i] |
1699 | != x_ira_register_move_cost[mode]); | |
7cc61ee4 | 1700 | i++) |
e80ccebc RS |
1701 | ; |
1702 | if (i == mode) | |
1703 | { | |
19c708dc RS |
1704 | free (x_ira_register_move_cost[mode]); |
1705 | free (x_ira_may_move_in_cost[mode]); | |
1706 | free (x_ira_may_move_out_cost[mode]); | |
e80ccebc RS |
1707 | } |
1708 | } | |
19c708dc RS |
1709 | memset (x_ira_register_move_cost, 0, sizeof x_ira_register_move_cost); |
1710 | memset (x_ira_may_move_in_cost, 0, sizeof x_ira_may_move_in_cost); | |
1711 | memset (x_ira_may_move_out_cost, 0, sizeof x_ira_may_move_out_cost); | |
e80ccebc | 1712 | last_mode_for_init_move_cost = -1; |
058e97ec VM |
1713 | } |
1714 | ||
19c708dc RS |
1715 | target_ira_int::~target_ira_int () |
1716 | { | |
1717 | free_ira_costs (); | |
1718 | free_register_move_costs (); | |
1719 | } | |
1720 | ||
058e97ec VM |
1721 | /* This is called every time when register related information is |
1722 | changed. */ | |
1723 | void | |
1724 | ira_init (void) | |
1725 | { | |
19c708dc | 1726 | this_target_ira_int->free_register_move_costs (); |
058e97ec VM |
1727 | setup_reg_mode_hard_regset (); |
1728 | setup_alloc_regs (flag_omit_frame_pointer != 0); | |
1729 | setup_class_subset_and_memory_move_costs (); | |
058e97ec VM |
1730 | setup_reg_class_nregs (); |
1731 | setup_prohibited_class_mode_regs (); | |
1756cb66 VM |
1732 | find_reg_classes (); |
1733 | clarify_prohibited_class_mode_regs (); | |
1734 | setup_hard_regno_aclass (); | |
058e97ec VM |
1735 | ira_init_costs (); |
1736 | } | |
1737 | ||
058e97ec | 1738 | \f |
15e7b94f RS |
1739 | #define ira_prohibited_mode_move_regs_initialized_p \ |
1740 | (this_target_ira_int->x_ira_prohibited_mode_move_regs_initialized_p) | |
058e97ec VM |
1741 | |
1742 | /* Set up IRA_PROHIBITED_MODE_MOVE_REGS. */ | |
1743 | static void | |
1744 | setup_prohibited_mode_move_regs (void) | |
1745 | { | |
1746 | int i, j; | |
647d790d DM |
1747 | rtx test_reg1, test_reg2, move_pat; |
1748 | rtx_insn *move_insn; | |
058e97ec VM |
1749 | |
1750 | if (ira_prohibited_mode_move_regs_initialized_p) | |
1751 | return; | |
1752 | ira_prohibited_mode_move_regs_initialized_p = true; | |
c3dc5e66 RS |
1753 | test_reg1 = gen_rtx_REG (word_mode, LAST_VIRTUAL_REGISTER + 1); |
1754 | test_reg2 = gen_rtx_REG (word_mode, LAST_VIRTUAL_REGISTER + 2); | |
f7df4a84 | 1755 | move_pat = gen_rtx_SET (test_reg1, test_reg2); |
ed8921dc | 1756 | move_insn = gen_rtx_INSN (VOIDmode, 0, 0, 0, move_pat, 0, -1, 0); |
058e97ec VM |
1757 | for (i = 0; i < NUM_MACHINE_MODES; i++) |
1758 | { | |
1759 | SET_HARD_REG_SET (ira_prohibited_mode_move_regs[i]); | |
1760 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
1761 | { | |
ef4bddc2 | 1762 | if (! HARD_REGNO_MODE_OK (j, (machine_mode) i)) |
058e97ec | 1763 | continue; |
8deccbb7 RS |
1764 | set_mode_and_regno (test_reg1, (machine_mode) i, j); |
1765 | set_mode_and_regno (test_reg2, (machine_mode) i, j); | |
058e97ec VM |
1766 | INSN_CODE (move_insn) = -1; |
1767 | recog_memoized (move_insn); | |
1768 | if (INSN_CODE (move_insn) < 0) | |
1769 | continue; | |
1770 | extract_insn (move_insn); | |
daca1a96 RS |
1771 | /* We don't know whether the move will be in code that is optimized |
1772 | for size or speed, so consider all enabled alternatives. */ | |
1773 | if (! constrain_operands (1, get_enabled_alternatives (move_insn))) | |
058e97ec VM |
1774 | continue; |
1775 | CLEAR_HARD_REG_BIT (ira_prohibited_mode_move_regs[i], j); | |
1776 | } | |
1777 | } | |
1778 | } | |
1779 | ||
1780 | \f | |
1781 | ||
3b6d1699 VM |
1782 | /* Setup possible alternatives in ALTS for INSN. */ |
1783 | void | |
647d790d | 1784 | ira_setup_alts (rtx_insn *insn, HARD_REG_SET &alts) |
3b6d1699 VM |
1785 | { |
1786 | /* MAP nalt * nop -> start of constraints for given operand and | |
2b9c63a2 | 1787 | alternative. */ |
3b6d1699 VM |
1788 | static vec<const char *> insn_constraints; |
1789 | int nop, nalt; | |
1790 | bool curr_swapped; | |
1791 | const char *p; | |
3b6d1699 VM |
1792 | int commutative = -1; |
1793 | ||
1794 | extract_insn (insn); | |
9840b2fa | 1795 | alternative_mask preferred = get_preferred_alternatives (insn); |
3b6d1699 VM |
1796 | CLEAR_HARD_REG_SET (alts); |
1797 | insn_constraints.release (); | |
1798 | insn_constraints.safe_grow_cleared (recog_data.n_operands | |
1799 | * recog_data.n_alternatives + 1); | |
1800 | /* Check that the hard reg set is enough for holding all | |
1801 | alternatives. It is hard to imagine the situation when the | |
1802 | assertion is wrong. */ | |
1803 | ira_assert (recog_data.n_alternatives | |
1804 | <= (int) MAX (sizeof (HARD_REG_ELT_TYPE) * CHAR_BIT, | |
1805 | FIRST_PSEUDO_REGISTER)); | |
1806 | for (curr_swapped = false;; curr_swapped = true) | |
1807 | { | |
1808 | /* Calculate some data common for all alternatives to speed up the | |
1809 | function. */ | |
1810 | for (nop = 0; nop < recog_data.n_operands; nop++) | |
1811 | { | |
1812 | for (nalt = 0, p = recog_data.constraints[nop]; | |
1813 | nalt < recog_data.n_alternatives; | |
1814 | nalt++) | |
1815 | { | |
1816 | insn_constraints[nop * recog_data.n_alternatives + nalt] = p; | |
1817 | while (*p && *p != ',') | |
1818 | p++; | |
1819 | if (*p) | |
1820 | p++; | |
1821 | } | |
1822 | } | |
1823 | for (nalt = 0; nalt < recog_data.n_alternatives; nalt++) | |
1824 | { | |
9840b2fa | 1825 | if (!TEST_BIT (preferred, nalt) |
4cc8d9d2 | 1826 | || TEST_HARD_REG_BIT (alts, nalt)) |
3b6d1699 VM |
1827 | continue; |
1828 | ||
1829 | for (nop = 0; nop < recog_data.n_operands; nop++) | |
1830 | { | |
1831 | int c, len; | |
1832 | ||
fab27f52 | 1833 | rtx op = recog_data.operand[nop]; |
3b6d1699 VM |
1834 | p = insn_constraints[nop * recog_data.n_alternatives + nalt]; |
1835 | if (*p == 0 || *p == ',') | |
1836 | continue; | |
1837 | ||
1838 | do | |
1839 | switch (c = *p, len = CONSTRAINT_LEN (c, p), c) | |
1840 | { | |
1841 | case '#': | |
1842 | case ',': | |
1843 | c = '\0'; | |
1844 | case '\0': | |
1845 | len = 0; | |
1846 | break; | |
1847 | ||
3b6d1699 VM |
1848 | case '%': |
1849 | /* We only support one commutative marker, the | |
1850 | first one. We already set commutative | |
1851 | above. */ | |
1852 | if (commutative < 0) | |
1853 | commutative = nop; | |
1854 | break; | |
1855 | ||
3b6d1699 VM |
1856 | case '0': case '1': case '2': case '3': case '4': |
1857 | case '5': case '6': case '7': case '8': case '9': | |
1858 | goto op_success; | |
1859 | break; | |
1860 | ||
3b6d1699 | 1861 | case 'g': |
3b6d1699 VM |
1862 | goto op_success; |
1863 | break; | |
1864 | ||
1865 | default: | |
1866 | { | |
777e635f RS |
1867 | enum constraint_num cn = lookup_constraint (p); |
1868 | switch (get_constraint_type (cn)) | |
1869 | { | |
1870 | case CT_REGISTER: | |
1871 | if (reg_class_for_constraint (cn) != NO_REGS) | |
1872 | goto op_success; | |
1873 | break; | |
1874 | ||
d9c35eee RS |
1875 | case CT_CONST_INT: |
1876 | if (CONST_INT_P (op) | |
1877 | && (insn_const_int_ok_for_constraint | |
1878 | (INTVAL (op), cn))) | |
1879 | goto op_success; | |
1880 | break; | |
1881 | ||
777e635f RS |
1882 | case CT_ADDRESS: |
1883 | case CT_MEMORY: | |
1884 | goto op_success; | |
1885 | ||
1886 | case CT_FIXED_FORM: | |
1887 | if (constraint_satisfied_p (op, cn)) | |
1888 | goto op_success; | |
1889 | break; | |
1890 | } | |
3b6d1699 VM |
1891 | break; |
1892 | } | |
1893 | } | |
1894 | while (p += len, c); | |
1895 | break; | |
1896 | op_success: | |
1897 | ; | |
1898 | } | |
1899 | if (nop >= recog_data.n_operands) | |
1900 | SET_HARD_REG_BIT (alts, nalt); | |
1901 | } | |
1902 | if (commutative < 0) | |
1903 | break; | |
1904 | if (curr_swapped) | |
1905 | break; | |
fab27f52 MM |
1906 | std::swap (recog_data.operand[commutative], |
1907 | recog_data.operand[commutative + 1]); | |
3b6d1699 VM |
1908 | } |
1909 | } | |
1910 | ||
1911 | /* Return the number of the output non-early clobber operand which | |
1912 | should be the same in any case as operand with number OP_NUM (or | |
1913 | negative value if there is no such operand). The function takes | |
1914 | only really possible alternatives into consideration. */ | |
1915 | int | |
1916 | ira_get_dup_out_num (int op_num, HARD_REG_SET &alts) | |
1917 | { | |
1918 | int curr_alt, c, original, dup; | |
1919 | bool ignore_p, use_commut_op_p; | |
1920 | const char *str; | |
3b6d1699 VM |
1921 | |
1922 | if (op_num < 0 || recog_data.n_alternatives == 0) | |
1923 | return -1; | |
98f2f031 RS |
1924 | /* We should find duplications only for input operands. */ |
1925 | if (recog_data.operand_type[op_num] != OP_IN) | |
1926 | return -1; | |
3b6d1699 | 1927 | str = recog_data.constraints[op_num]; |
98f2f031 | 1928 | use_commut_op_p = false; |
3b6d1699 VM |
1929 | for (;;) |
1930 | { | |
777e635f | 1931 | rtx op = recog_data.operand[op_num]; |
3b6d1699 | 1932 | |
98f2f031 RS |
1933 | for (curr_alt = 0, ignore_p = !TEST_HARD_REG_BIT (alts, curr_alt), |
1934 | original = -1;;) | |
3b6d1699 VM |
1935 | { |
1936 | c = *str; | |
1937 | if (c == '\0') | |
1938 | break; | |
98f2f031 | 1939 | if (c == '#') |
3b6d1699 VM |
1940 | ignore_p = true; |
1941 | else if (c == ',') | |
1942 | { | |
1943 | curr_alt++; | |
98f2f031 | 1944 | ignore_p = !TEST_HARD_REG_BIT (alts, curr_alt); |
3b6d1699 VM |
1945 | } |
1946 | else if (! ignore_p) | |
1947 | switch (c) | |
1948 | { | |
3b6d1699 VM |
1949 | case 'g': |
1950 | goto fail; | |
8677664e | 1951 | default: |
3b6d1699 | 1952 | { |
777e635f RS |
1953 | enum constraint_num cn = lookup_constraint (str); |
1954 | enum reg_class cl = reg_class_for_constraint (cn); | |
1955 | if (cl != NO_REGS | |
1956 | && !targetm.class_likely_spilled_p (cl)) | |
1957 | goto fail; | |
1958 | if (constraint_satisfied_p (op, cn)) | |
3b6d1699 | 1959 | goto fail; |
3b6d1699 VM |
1960 | break; |
1961 | } | |
1962 | ||
1963 | case '0': case '1': case '2': case '3': case '4': | |
1964 | case '5': case '6': case '7': case '8': case '9': | |
1965 | if (original != -1 && original != c) | |
1966 | goto fail; | |
1967 | original = c; | |
1968 | break; | |
1969 | } | |
1970 | str += CONSTRAINT_LEN (c, str); | |
1971 | } | |
1972 | if (original == -1) | |
1973 | goto fail; | |
1974 | dup = -1; | |
1975 | for (ignore_p = false, str = recog_data.constraints[original - '0']; | |
1976 | *str != 0; | |
1977 | str++) | |
1978 | if (ignore_p) | |
1979 | { | |
1980 | if (*str == ',') | |
1981 | ignore_p = false; | |
1982 | } | |
1983 | else if (*str == '#') | |
1984 | ignore_p = true; | |
1985 | else if (! ignore_p) | |
1986 | { | |
1987 | if (*str == '=') | |
1988 | dup = original - '0'; | |
1989 | /* It is better ignore an alternative with early clobber. */ | |
1990 | else if (*str == '&') | |
1991 | goto fail; | |
1992 | } | |
1993 | if (dup >= 0) | |
1994 | return dup; | |
1995 | fail: | |
1996 | if (use_commut_op_p) | |
1997 | break; | |
1998 | use_commut_op_p = true; | |
73f793e3 | 1999 | if (recog_data.constraints[op_num][0] == '%') |
3b6d1699 | 2000 | str = recog_data.constraints[op_num + 1]; |
73f793e3 | 2001 | else if (op_num > 0 && recog_data.constraints[op_num - 1][0] == '%') |
3b6d1699 VM |
2002 | str = recog_data.constraints[op_num - 1]; |
2003 | else | |
2004 | break; | |
2005 | } | |
2006 | return -1; | |
2007 | } | |
2008 | ||
2009 | \f | |
2010 | ||
2011 | /* Search forward to see if the source register of a copy insn dies | |
2012 | before either it or the destination register is modified, but don't | |
2013 | scan past the end of the basic block. If so, we can replace the | |
2014 | source with the destination and let the source die in the copy | |
2015 | insn. | |
2016 | ||
2017 | This will reduce the number of registers live in that range and may | |
2018 | enable the destination and the source coalescing, thus often saving | |
2019 | one register in addition to a register-register copy. */ | |
2020 | ||
2021 | static void | |
2022 | decrease_live_ranges_number (void) | |
2023 | { | |
2024 | basic_block bb; | |
070a1983 | 2025 | rtx_insn *insn; |
7da26277 TS |
2026 | rtx set, src, dest, dest_death, note; |
2027 | rtx_insn *p, *q; | |
3b6d1699 VM |
2028 | int sregno, dregno; |
2029 | ||
2030 | if (! flag_expensive_optimizations) | |
2031 | return; | |
2032 | ||
2033 | if (ira_dump_file) | |
2034 | fprintf (ira_dump_file, "Starting decreasing number of live ranges...\n"); | |
2035 | ||
11cd3bed | 2036 | FOR_EACH_BB_FN (bb, cfun) |
3b6d1699 VM |
2037 | FOR_BB_INSNS (bb, insn) |
2038 | { | |
2039 | set = single_set (insn); | |
2040 | if (! set) | |
2041 | continue; | |
2042 | src = SET_SRC (set); | |
2043 | dest = SET_DEST (set); | |
2044 | if (! REG_P (src) || ! REG_P (dest) | |
2045 | || find_reg_note (insn, REG_DEAD, src)) | |
2046 | continue; | |
2047 | sregno = REGNO (src); | |
2048 | dregno = REGNO (dest); | |
2049 | ||
2050 | /* We don't want to mess with hard regs if register classes | |
2051 | are small. */ | |
2052 | if (sregno == dregno | |
2053 | || (targetm.small_register_classes_for_mode_p (GET_MODE (src)) | |
2054 | && (sregno < FIRST_PSEUDO_REGISTER | |
2055 | || dregno < FIRST_PSEUDO_REGISTER)) | |
2056 | /* We don't see all updates to SP if they are in an | |
2057 | auto-inc memory reference, so we must disallow this | |
2058 | optimization on them. */ | |
2059 | || sregno == STACK_POINTER_REGNUM | |
2060 | || dregno == STACK_POINTER_REGNUM) | |
2061 | continue; | |
2062 | ||
2063 | dest_death = NULL_RTX; | |
2064 | ||
2065 | for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p)) | |
2066 | { | |
2067 | if (! INSN_P (p)) | |
2068 | continue; | |
2069 | if (BLOCK_FOR_INSN (p) != bb) | |
2070 | break; | |
2071 | ||
2072 | if (reg_set_p (src, p) || reg_set_p (dest, p) | |
2073 | /* If SRC is an asm-declared register, it must not be | |
2074 | replaced in any asm. Unfortunately, the REG_EXPR | |
2075 | tree for the asm variable may be absent in the SRC | |
2076 | rtx, so we can't check the actual register | |
2077 | declaration easily (the asm operand will have it, | |
2078 | though). To avoid complicating the test for a rare | |
2079 | case, we just don't perform register replacement | |
2080 | for a hard reg mentioned in an asm. */ | |
2081 | || (sregno < FIRST_PSEUDO_REGISTER | |
2082 | && asm_noperands (PATTERN (p)) >= 0 | |
2083 | && reg_overlap_mentioned_p (src, PATTERN (p))) | |
2084 | /* Don't change hard registers used by a call. */ | |
2085 | || (CALL_P (p) && sregno < FIRST_PSEUDO_REGISTER | |
2086 | && find_reg_fusage (p, USE, src)) | |
2087 | /* Don't change a USE of a register. */ | |
2088 | || (GET_CODE (PATTERN (p)) == USE | |
2089 | && reg_overlap_mentioned_p (src, XEXP (PATTERN (p), 0)))) | |
2090 | break; | |
2091 | ||
2092 | /* See if all of SRC dies in P. This test is slightly | |
2093 | more conservative than it needs to be. */ | |
2094 | if ((note = find_regno_note (p, REG_DEAD, sregno)) | |
2095 | && GET_MODE (XEXP (note, 0)) == GET_MODE (src)) | |
2096 | { | |
2097 | int failed = 0; | |
2098 | ||
2099 | /* We can do the optimization. Scan forward from INSN | |
2100 | again, replacing regs as we go. Set FAILED if a | |
2101 | replacement can't be done. In that case, we can't | |
2102 | move the death note for SRC. This should be | |
2103 | rare. */ | |
2104 | ||
2105 | /* Set to stop at next insn. */ | |
2106 | for (q = next_real_insn (insn); | |
2107 | q != next_real_insn (p); | |
2108 | q = next_real_insn (q)) | |
2109 | { | |
2110 | if (reg_overlap_mentioned_p (src, PATTERN (q))) | |
2111 | { | |
2112 | /* If SRC is a hard register, we might miss | |
2113 | some overlapping registers with | |
2114 | validate_replace_rtx, so we would have to | |
2115 | undo it. We can't if DEST is present in | |
2116 | the insn, so fail in that combination of | |
2117 | cases. */ | |
2118 | if (sregno < FIRST_PSEUDO_REGISTER | |
2119 | && reg_mentioned_p (dest, PATTERN (q))) | |
2120 | failed = 1; | |
2121 | ||
2122 | /* Attempt to replace all uses. */ | |
2123 | else if (!validate_replace_rtx (src, dest, q)) | |
2124 | failed = 1; | |
2125 | ||
2126 | /* If this succeeded, but some part of the | |
2127 | register is still present, undo the | |
2128 | replacement. */ | |
2129 | else if (sregno < FIRST_PSEUDO_REGISTER | |
2130 | && reg_overlap_mentioned_p (src, PATTERN (q))) | |
2131 | { | |
2132 | validate_replace_rtx (dest, src, q); | |
2133 | failed = 1; | |
2134 | } | |
2135 | } | |
2136 | ||
2137 | /* If DEST dies here, remove the death note and | |
2138 | save it for later. Make sure ALL of DEST dies | |
2139 | here; again, this is overly conservative. */ | |
2140 | if (! dest_death | |
2141 | && (dest_death = find_regno_note (q, REG_DEAD, dregno))) | |
2142 | { | |
2143 | if (GET_MODE (XEXP (dest_death, 0)) == GET_MODE (dest)) | |
2144 | remove_note (q, dest_death); | |
2145 | else | |
2146 | { | |
2147 | failed = 1; | |
2148 | dest_death = 0; | |
2149 | } | |
2150 | } | |
2151 | } | |
2152 | ||
2153 | if (! failed) | |
2154 | { | |
2155 | /* Move death note of SRC from P to INSN. */ | |
2156 | remove_note (p, note); | |
2157 | XEXP (note, 1) = REG_NOTES (insn); | |
2158 | REG_NOTES (insn) = note; | |
2159 | } | |
2160 | ||
2161 | /* DEST is also dead if INSN has a REG_UNUSED note for | |
2162 | DEST. */ | |
2163 | if (! dest_death | |
2164 | && (dest_death | |
2165 | = find_regno_note (insn, REG_UNUSED, dregno))) | |
2166 | { | |
2167 | PUT_REG_NOTE_KIND (dest_death, REG_DEAD); | |
2168 | remove_note (insn, dest_death); | |
2169 | } | |
2170 | ||
2171 | /* Put death note of DEST on P if we saw it die. */ | |
2172 | if (dest_death) | |
2173 | { | |
2174 | XEXP (dest_death, 1) = REG_NOTES (p); | |
2175 | REG_NOTES (p) = dest_death; | |
2176 | } | |
2177 | break; | |
2178 | } | |
2179 | ||
2180 | /* If SRC is a hard register which is set or killed in | |
2181 | some other way, we can't do this optimization. */ | |
2182 | else if (sregno < FIRST_PSEUDO_REGISTER && dead_or_set_p (p, src)) | |
2183 | break; | |
2184 | } | |
2185 | } | |
2186 | } | |
2187 | ||
2188 | \f | |
2189 | ||
0896cc66 JL |
2190 | /* Return nonzero if REGNO is a particularly bad choice for reloading X. */ |
2191 | static bool | |
2192 | ira_bad_reload_regno_1 (int regno, rtx x) | |
2193 | { | |
ac0ab4f7 | 2194 | int x_regno, n, i; |
0896cc66 JL |
2195 | ira_allocno_t a; |
2196 | enum reg_class pref; | |
2197 | ||
2198 | /* We only deal with pseudo regs. */ | |
2199 | if (! x || GET_CODE (x) != REG) | |
2200 | return false; | |
2201 | ||
2202 | x_regno = REGNO (x); | |
2203 | if (x_regno < FIRST_PSEUDO_REGISTER) | |
2204 | return false; | |
2205 | ||
2206 | /* If the pseudo prefers REGNO explicitly, then do not consider | |
2207 | REGNO a bad spill choice. */ | |
2208 | pref = reg_preferred_class (x_regno); | |
2209 | if (reg_class_size[pref] == 1) | |
2210 | return !TEST_HARD_REG_BIT (reg_class_contents[pref], regno); | |
2211 | ||
2212 | /* If the pseudo conflicts with REGNO, then we consider REGNO a | |
2213 | poor choice for a reload regno. */ | |
2214 | a = ira_regno_allocno_map[x_regno]; | |
ac0ab4f7 BS |
2215 | n = ALLOCNO_NUM_OBJECTS (a); |
2216 | for (i = 0; i < n; i++) | |
2217 | { | |
2218 | ira_object_t obj = ALLOCNO_OBJECT (a, i); | |
2219 | if (TEST_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), regno)) | |
2220 | return true; | |
2221 | } | |
0896cc66 JL |
2222 | return false; |
2223 | } | |
2224 | ||
2225 | /* Return nonzero if REGNO is a particularly bad choice for reloading | |
2226 | IN or OUT. */ | |
2227 | bool | |
2228 | ira_bad_reload_regno (int regno, rtx in, rtx out) | |
2229 | { | |
2230 | return (ira_bad_reload_regno_1 (regno, in) | |
2231 | || ira_bad_reload_regno_1 (regno, out)); | |
2232 | } | |
2233 | ||
b748fbd6 | 2234 | /* Add register clobbers from asm statements. */ |
058e97ec | 2235 | static void |
b748fbd6 | 2236 | compute_regs_asm_clobbered (void) |
058e97ec VM |
2237 | { |
2238 | basic_block bb; | |
2239 | ||
11cd3bed | 2240 | FOR_EACH_BB_FN (bb, cfun) |
058e97ec | 2241 | { |
070a1983 | 2242 | rtx_insn *insn; |
058e97ec VM |
2243 | FOR_BB_INSNS_REVERSE (bb, insn) |
2244 | { | |
bfac633a | 2245 | df_ref def; |
058e97ec | 2246 | |
f33a8d10 | 2247 | if (NONDEBUG_INSN_P (insn) && extract_asm_operands (PATTERN (insn))) |
bfac633a | 2248 | FOR_EACH_INSN_DEF (def, insn) |
058e97ec | 2249 | { |
058e97ec | 2250 | unsigned int dregno = DF_REF_REGNO (def); |
d108e679 AS |
2251 | if (HARD_REGISTER_NUM_P (dregno)) |
2252 | add_to_hard_reg_set (&crtl->asm_clobbers, | |
2253 | GET_MODE (DF_REF_REAL_REG (def)), | |
2254 | dregno); | |
058e97ec VM |
2255 | } |
2256 | } | |
2257 | } | |
2258 | } | |
2259 | ||
2260 | ||
8d49e7ef VM |
2261 | /* Set up ELIMINABLE_REGSET, IRA_NO_ALLOC_REGS, and |
2262 | REGS_EVER_LIVE. */ | |
ce18efcb | 2263 | void |
8d49e7ef | 2264 | ira_setup_eliminable_regset (void) |
058e97ec | 2265 | { |
058e97ec | 2266 | #ifdef ELIMINABLE_REGS |
89ceba31 | 2267 | int i; |
058e97ec VM |
2268 | static const struct {const int from, to; } eliminables[] = ELIMINABLE_REGS; |
2269 | #endif | |
2270 | /* FIXME: If EXIT_IGNORE_STACK is set, we will not save and restore | |
2271 | sp for alloca. So we can't eliminate the frame pointer in that | |
2272 | case. At some point, we should improve this by emitting the | |
2273 | sp-adjusting insns for this case. */ | |
55a2c322 | 2274 | frame_pointer_needed |
058e97ec VM |
2275 | = (! flag_omit_frame_pointer |
2276 | || (cfun->calls_alloca && EXIT_IGNORE_STACK) | |
d809253a EB |
2277 | /* We need the frame pointer to catch stack overflow exceptions |
2278 | if the stack pointer is moving. */ | |
2279 | || (flag_stack_check && STACK_CHECK_MOVING_SP) | |
058e97ec | 2280 | || crtl->accesses_prior_frames |
8d49e7ef | 2281 | || (SUPPORTS_STACK_ALIGNMENT && crtl->stack_realign_needed) |
939b37da BI |
2282 | /* We need a frame pointer for all Cilk Plus functions that use |
2283 | Cilk keywords. */ | |
b72271b9 | 2284 | || (flag_cilkplus && cfun->is_cilk_function) |
b52b1749 | 2285 | || targetm.frame_pointer_required ()); |
058e97ec | 2286 | |
8d49e7ef VM |
2287 | /* The chance that FRAME_POINTER_NEEDED is changed from inspecting |
2288 | RTL is very small. So if we use frame pointer for RA and RTL | |
2289 | actually prevents this, we will spill pseudos assigned to the | |
2290 | frame pointer in LRA. */ | |
058e97ec | 2291 | |
55a2c322 VM |
2292 | if (frame_pointer_needed) |
2293 | df_set_regs_ever_live (HARD_FRAME_POINTER_REGNUM, true); | |
2294 | ||
058e97ec VM |
2295 | COPY_HARD_REG_SET (ira_no_alloc_regs, no_unit_alloc_regs); |
2296 | CLEAR_HARD_REG_SET (eliminable_regset); | |
2297 | ||
b748fbd6 PB |
2298 | compute_regs_asm_clobbered (); |
2299 | ||
058e97ec VM |
2300 | /* Build the regset of all eliminable registers and show we can't |
2301 | use those that we already know won't be eliminated. */ | |
2302 | #ifdef ELIMINABLE_REGS | |
2303 | for (i = 0; i < (int) ARRAY_SIZE (eliminables); i++) | |
2304 | { | |
2305 | bool cannot_elim | |
7b5cbb57 | 2306 | = (! targetm.can_eliminate (eliminables[i].from, eliminables[i].to) |
55a2c322 | 2307 | || (eliminables[i].to == STACK_POINTER_REGNUM && frame_pointer_needed)); |
058e97ec | 2308 | |
b748fbd6 | 2309 | if (!TEST_HARD_REG_BIT (crtl->asm_clobbers, eliminables[i].from)) |
058e97ec VM |
2310 | { |
2311 | SET_HARD_REG_BIT (eliminable_regset, eliminables[i].from); | |
2312 | ||
2313 | if (cannot_elim) | |
2314 | SET_HARD_REG_BIT (ira_no_alloc_regs, eliminables[i].from); | |
2315 | } | |
2316 | else if (cannot_elim) | |
2317 | error ("%s cannot be used in asm here", | |
2318 | reg_names[eliminables[i].from]); | |
2319 | else | |
2320 | df_set_regs_ever_live (eliminables[i].from, true); | |
2321 | } | |
c3e08036 | 2322 | if (!HARD_FRAME_POINTER_IS_FRAME_POINTER) |
058e97ec | 2323 | { |
c3e08036 TS |
2324 | if (!TEST_HARD_REG_BIT (crtl->asm_clobbers, HARD_FRAME_POINTER_REGNUM)) |
2325 | { | |
2326 | SET_HARD_REG_BIT (eliminable_regset, HARD_FRAME_POINTER_REGNUM); | |
2327 | if (frame_pointer_needed) | |
2328 | SET_HARD_REG_BIT (ira_no_alloc_regs, HARD_FRAME_POINTER_REGNUM); | |
2329 | } | |
2330 | else if (frame_pointer_needed) | |
2331 | error ("%s cannot be used in asm here", | |
2332 | reg_names[HARD_FRAME_POINTER_REGNUM]); | |
2333 | else | |
2334 | df_set_regs_ever_live (HARD_FRAME_POINTER_REGNUM, true); | |
058e97ec | 2335 | } |
058e97ec VM |
2336 | |
2337 | #else | |
b748fbd6 | 2338 | if (!TEST_HARD_REG_BIT (crtl->asm_clobbers, HARD_FRAME_POINTER_REGNUM)) |
058e97ec VM |
2339 | { |
2340 | SET_HARD_REG_BIT (eliminable_regset, FRAME_POINTER_REGNUM); | |
55a2c322 | 2341 | if (frame_pointer_needed) |
058e97ec VM |
2342 | SET_HARD_REG_BIT (ira_no_alloc_regs, FRAME_POINTER_REGNUM); |
2343 | } | |
55a2c322 | 2344 | else if (frame_pointer_needed) |
058e97ec VM |
2345 | error ("%s cannot be used in asm here", reg_names[FRAME_POINTER_REGNUM]); |
2346 | else | |
2347 | df_set_regs_ever_live (FRAME_POINTER_REGNUM, true); | |
2348 | #endif | |
2349 | } | |
2350 | ||
2351 | \f | |
2352 | ||
2af2dbdc VM |
2353 | /* Vector of substitutions of register numbers, |
2354 | used to map pseudo regs into hardware regs. | |
2355 | This is set up as a result of register allocation. | |
2356 | Element N is the hard reg assigned to pseudo reg N, | |
2357 | or is -1 if no hard reg was assigned. | |
2358 | If N is a hard reg number, element N is N. */ | |
2359 | short *reg_renumber; | |
2360 | ||
058e97ec VM |
2361 | /* Set up REG_RENUMBER and CALLER_SAVE_NEEDED (used by reload) from |
2362 | the allocation found by IRA. */ | |
2363 | static void | |
2364 | setup_reg_renumber (void) | |
2365 | { | |
2366 | int regno, hard_regno; | |
2367 | ira_allocno_t a; | |
2368 | ira_allocno_iterator ai; | |
2369 | ||
2370 | caller_save_needed = 0; | |
2371 | FOR_EACH_ALLOCNO (a, ai) | |
2372 | { | |
55a2c322 VM |
2373 | if (ira_use_lra_p && ALLOCNO_CAP_MEMBER (a) != NULL) |
2374 | continue; | |
058e97ec VM |
2375 | /* There are no caps at this point. */ |
2376 | ira_assert (ALLOCNO_CAP_MEMBER (a) == NULL); | |
2377 | if (! ALLOCNO_ASSIGNED_P (a)) | |
2378 | /* It can happen if A is not referenced but partially anticipated | |
2379 | somewhere in a region. */ | |
2380 | ALLOCNO_ASSIGNED_P (a) = true; | |
2381 | ira_free_allocno_updated_costs (a); | |
2382 | hard_regno = ALLOCNO_HARD_REGNO (a); | |
1756cb66 | 2383 | regno = ALLOCNO_REGNO (a); |
058e97ec | 2384 | reg_renumber[regno] = (hard_regno < 0 ? -1 : hard_regno); |
1756cb66 | 2385 | if (hard_regno >= 0) |
058e97ec | 2386 | { |
1756cb66 VM |
2387 | int i, nwords; |
2388 | enum reg_class pclass; | |
2389 | ira_object_t obj; | |
2390 | ||
2391 | pclass = ira_pressure_class_translate[REGNO_REG_CLASS (hard_regno)]; | |
2392 | nwords = ALLOCNO_NUM_OBJECTS (a); | |
2393 | for (i = 0; i < nwords; i++) | |
2394 | { | |
2395 | obj = ALLOCNO_OBJECT (a, i); | |
2396 | IOR_COMPL_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), | |
2397 | reg_class_contents[pclass]); | |
2398 | } | |
2399 | if (ALLOCNO_CALLS_CROSSED_NUM (a) != 0 | |
9181a6e5 VM |
2400 | && ira_hard_reg_set_intersection_p (hard_regno, ALLOCNO_MODE (a), |
2401 | call_used_reg_set)) | |
1756cb66 VM |
2402 | { |
2403 | ira_assert (!optimize || flag_caller_saves | |
e384e6b5 BS |
2404 | || (ALLOCNO_CALLS_CROSSED_NUM (a) |
2405 | == ALLOCNO_CHEAP_CALLS_CROSSED_NUM (a)) | |
15652f68 | 2406 | || regno >= ira_reg_equiv_len |
55a2c322 | 2407 | || ira_equiv_no_lvalue_p (regno)); |
1756cb66 VM |
2408 | caller_save_needed = 1; |
2409 | } | |
058e97ec VM |
2410 | } |
2411 | } | |
2412 | } | |
2413 | ||
2414 | /* Set up allocno assignment flags for further allocation | |
2415 | improvements. */ | |
2416 | static void | |
2417 | setup_allocno_assignment_flags (void) | |
2418 | { | |
2419 | int hard_regno; | |
2420 | ira_allocno_t a; | |
2421 | ira_allocno_iterator ai; | |
2422 | ||
2423 | FOR_EACH_ALLOCNO (a, ai) | |
2424 | { | |
2425 | if (! ALLOCNO_ASSIGNED_P (a)) | |
2426 | /* It can happen if A is not referenced but partially anticipated | |
2427 | somewhere in a region. */ | |
2428 | ira_free_allocno_updated_costs (a); | |
2429 | hard_regno = ALLOCNO_HARD_REGNO (a); | |
2430 | /* Don't assign hard registers to allocnos which are destination | |
2431 | of removed store at the end of loop. It has no sense to keep | |
2432 | the same value in different hard registers. It is also | |
2433 | impossible to assign hard registers correctly to such | |
2434 | allocnos because the cost info and info about intersected | |
2435 | calls are incorrect for them. */ | |
2436 | ALLOCNO_ASSIGNED_P (a) = (hard_regno >= 0 | |
1756cb66 | 2437 | || ALLOCNO_EMIT_DATA (a)->mem_optimized_dest_p |
058e97ec | 2438 | || (ALLOCNO_MEMORY_COST (a) |
1756cb66 | 2439 | - ALLOCNO_CLASS_COST (a)) < 0); |
9181a6e5 VM |
2440 | ira_assert |
2441 | (hard_regno < 0 | |
2442 | || ira_hard_reg_in_set_p (hard_regno, ALLOCNO_MODE (a), | |
2443 | reg_class_contents[ALLOCNO_CLASS (a)])); | |
058e97ec VM |
2444 | } |
2445 | } | |
2446 | ||
2447 | /* Evaluate overall allocation cost and the costs for using hard | |
2448 | registers and memory for allocnos. */ | |
2449 | static void | |
2450 | calculate_allocation_cost (void) | |
2451 | { | |
2452 | int hard_regno, cost; | |
2453 | ira_allocno_t a; | |
2454 | ira_allocno_iterator ai; | |
2455 | ||
2456 | ira_overall_cost = ira_reg_cost = ira_mem_cost = 0; | |
2457 | FOR_EACH_ALLOCNO (a, ai) | |
2458 | { | |
2459 | hard_regno = ALLOCNO_HARD_REGNO (a); | |
2460 | ira_assert (hard_regno < 0 | |
9181a6e5 VM |
2461 | || (ira_hard_reg_in_set_p |
2462 | (hard_regno, ALLOCNO_MODE (a), | |
2463 | reg_class_contents[ALLOCNO_CLASS (a)]))); | |
058e97ec VM |
2464 | if (hard_regno < 0) |
2465 | { | |
2466 | cost = ALLOCNO_MEMORY_COST (a); | |
2467 | ira_mem_cost += cost; | |
2468 | } | |
2469 | else if (ALLOCNO_HARD_REG_COSTS (a) != NULL) | |
2470 | { | |
2471 | cost = (ALLOCNO_HARD_REG_COSTS (a) | |
2472 | [ira_class_hard_reg_index | |
1756cb66 | 2473 | [ALLOCNO_CLASS (a)][hard_regno]]); |
058e97ec VM |
2474 | ira_reg_cost += cost; |
2475 | } | |
2476 | else | |
2477 | { | |
1756cb66 | 2478 | cost = ALLOCNO_CLASS_COST (a); |
058e97ec VM |
2479 | ira_reg_cost += cost; |
2480 | } | |
2481 | ira_overall_cost += cost; | |
2482 | } | |
2483 | ||
2484 | if (internal_flag_ira_verbose > 0 && ira_dump_file != NULL) | |
2485 | { | |
2486 | fprintf (ira_dump_file, | |
16998094 JM |
2487 | "+++Costs: overall %" PRId64 |
2488 | ", reg %" PRId64 | |
2489 | ", mem %" PRId64 | |
2490 | ", ld %" PRId64 | |
2491 | ", st %" PRId64 | |
2492 | ", move %" PRId64, | |
058e97ec VM |
2493 | ira_overall_cost, ira_reg_cost, ira_mem_cost, |
2494 | ira_load_cost, ira_store_cost, ira_shuffle_cost); | |
2bf7560b | 2495 | fprintf (ira_dump_file, "\n+++ move loops %d, new jumps %d\n", |
058e97ec VM |
2496 | ira_move_loops_num, ira_additional_jumps_num); |
2497 | } | |
2498 | ||
2499 | } | |
2500 | ||
2501 | #ifdef ENABLE_IRA_CHECKING | |
2502 | /* Check the correctness of the allocation. We do need this because | |
2503 | of complicated code to transform more one region internal | |
2504 | representation into one region representation. */ | |
2505 | static void | |
2506 | check_allocation (void) | |
2507 | { | |
fa86d337 | 2508 | ira_allocno_t a; |
ac0ab4f7 | 2509 | int hard_regno, nregs, conflict_nregs; |
058e97ec VM |
2510 | ira_allocno_iterator ai; |
2511 | ||
2512 | FOR_EACH_ALLOCNO (a, ai) | |
2513 | { | |
ac0ab4f7 BS |
2514 | int n = ALLOCNO_NUM_OBJECTS (a); |
2515 | int i; | |
fa86d337 | 2516 | |
058e97ec VM |
2517 | if (ALLOCNO_CAP_MEMBER (a) != NULL |
2518 | || (hard_regno = ALLOCNO_HARD_REGNO (a)) < 0) | |
2519 | continue; | |
2520 | nregs = hard_regno_nregs[hard_regno][ALLOCNO_MODE (a)]; | |
8cfd82bf BS |
2521 | if (nregs == 1) |
2522 | /* We allocated a single hard register. */ | |
2523 | n = 1; | |
2524 | else if (n > 1) | |
2525 | /* We allocated multiple hard registers, and we will test | |
2526 | conflicts in a granularity of single hard regs. */ | |
2527 | nregs = 1; | |
2528 | ||
ac0ab4f7 BS |
2529 | for (i = 0; i < n; i++) |
2530 | { | |
2531 | ira_object_t obj = ALLOCNO_OBJECT (a, i); | |
2532 | ira_object_t conflict_obj; | |
2533 | ira_object_conflict_iterator oci; | |
2534 | int this_regno = hard_regno; | |
2535 | if (n > 1) | |
fa86d337 | 2536 | { |
2805e6c0 | 2537 | if (REG_WORDS_BIG_ENDIAN) |
ac0ab4f7 BS |
2538 | this_regno += n - i - 1; |
2539 | else | |
2540 | this_regno += i; | |
2541 | } | |
2542 | FOR_EACH_OBJECT_CONFLICT (obj, conflict_obj, oci) | |
2543 | { | |
2544 | ira_allocno_t conflict_a = OBJECT_ALLOCNO (conflict_obj); | |
2545 | int conflict_hard_regno = ALLOCNO_HARD_REGNO (conflict_a); | |
2546 | if (conflict_hard_regno < 0) | |
2547 | continue; | |
8cfd82bf BS |
2548 | |
2549 | conflict_nregs | |
2550 | = (hard_regno_nregs | |
2551 | [conflict_hard_regno][ALLOCNO_MODE (conflict_a)]); | |
2552 | ||
2553 | if (ALLOCNO_NUM_OBJECTS (conflict_a) > 1 | |
2554 | && conflict_nregs == ALLOCNO_NUM_OBJECTS (conflict_a)) | |
ac0ab4f7 | 2555 | { |
2805e6c0 | 2556 | if (REG_WORDS_BIG_ENDIAN) |
ac0ab4f7 BS |
2557 | conflict_hard_regno += (ALLOCNO_NUM_OBJECTS (conflict_a) |
2558 | - OBJECT_SUBWORD (conflict_obj) - 1); | |
2559 | else | |
2560 | conflict_hard_regno += OBJECT_SUBWORD (conflict_obj); | |
2561 | conflict_nregs = 1; | |
2562 | } | |
ac0ab4f7 BS |
2563 | |
2564 | if ((conflict_hard_regno <= this_regno | |
2565 | && this_regno < conflict_hard_regno + conflict_nregs) | |
2566 | || (this_regno <= conflict_hard_regno | |
2567 | && conflict_hard_regno < this_regno + nregs)) | |
fa86d337 BS |
2568 | { |
2569 | fprintf (stderr, "bad allocation for %d and %d\n", | |
2570 | ALLOCNO_REGNO (a), ALLOCNO_REGNO (conflict_a)); | |
2571 | gcc_unreachable (); | |
2572 | } | |
2573 | } | |
2574 | } | |
058e97ec VM |
2575 | } |
2576 | } | |
2577 | #endif | |
2578 | ||
55a2c322 VM |
2579 | /* Allocate REG_EQUIV_INIT. Set up it from IRA_REG_EQUIV which should |
2580 | be already calculated. */ | |
2581 | static void | |
2582 | setup_reg_equiv_init (void) | |
2583 | { | |
2584 | int i; | |
2585 | int max_regno = max_reg_num (); | |
2586 | ||
2587 | for (i = 0; i < max_regno; i++) | |
2588 | reg_equiv_init (i) = ira_reg_equiv[i].init_insns; | |
2589 | } | |
2590 | ||
2591 | /* Update equiv regno from movement of FROM_REGNO to TO_REGNO. INSNS | |
2592 | are insns which were generated for such movement. It is assumed | |
2593 | that FROM_REGNO and TO_REGNO always have the same value at the | |
2594 | point of any move containing such registers. This function is used | |
2595 | to update equiv info for register shuffles on the region borders | |
2596 | and for caller save/restore insns. */ | |
2597 | void | |
b32d5189 | 2598 | ira_update_equiv_info_by_shuffle_insn (int to_regno, int from_regno, rtx_insn *insns) |
55a2c322 | 2599 | { |
b32d5189 DM |
2600 | rtx_insn *insn; |
2601 | rtx x, note; | |
55a2c322 VM |
2602 | |
2603 | if (! ira_reg_equiv[from_regno].defined_p | |
2604 | && (! ira_reg_equiv[to_regno].defined_p | |
2605 | || ((x = ira_reg_equiv[to_regno].memory) != NULL_RTX | |
2606 | && ! MEM_READONLY_P (x)))) | |
5a107a0f | 2607 | return; |
55a2c322 VM |
2608 | insn = insns; |
2609 | if (NEXT_INSN (insn) != NULL_RTX) | |
2610 | { | |
2611 | if (! ira_reg_equiv[to_regno].defined_p) | |
2612 | { | |
2613 | ira_assert (ira_reg_equiv[to_regno].init_insns == NULL_RTX); | |
2614 | return; | |
2615 | } | |
2616 | ira_reg_equiv[to_regno].defined_p = false; | |
2617 | ira_reg_equiv[to_regno].memory | |
2618 | = ira_reg_equiv[to_regno].constant | |
2619 | = ira_reg_equiv[to_regno].invariant | |
0cc97fc5 | 2620 | = ira_reg_equiv[to_regno].init_insns = NULL; |
55a2c322 VM |
2621 | if (internal_flag_ira_verbose > 3 && ira_dump_file != NULL) |
2622 | fprintf (ira_dump_file, | |
2623 | " Invalidating equiv info for reg %d\n", to_regno); | |
2624 | return; | |
2625 | } | |
2626 | /* It is possible that FROM_REGNO still has no equivalence because | |
2627 | in shuffles to_regno<-from_regno and from_regno<-to_regno the 2nd | |
2628 | insn was not processed yet. */ | |
2629 | if (ira_reg_equiv[from_regno].defined_p) | |
2630 | { | |
2631 | ira_reg_equiv[to_regno].defined_p = true; | |
2632 | if ((x = ira_reg_equiv[from_regno].memory) != NULL_RTX) | |
2633 | { | |
2634 | ira_assert (ira_reg_equiv[from_regno].invariant == NULL_RTX | |
2635 | && ira_reg_equiv[from_regno].constant == NULL_RTX); | |
2636 | ira_assert (ira_reg_equiv[to_regno].memory == NULL_RTX | |
2637 | || rtx_equal_p (ira_reg_equiv[to_regno].memory, x)); | |
2638 | ira_reg_equiv[to_regno].memory = x; | |
2639 | if (! MEM_READONLY_P (x)) | |
2640 | /* We don't add the insn to insn init list because memory | |
2641 | equivalence is just to say what memory is better to use | |
2642 | when the pseudo is spilled. */ | |
2643 | return; | |
2644 | } | |
2645 | else if ((x = ira_reg_equiv[from_regno].constant) != NULL_RTX) | |
2646 | { | |
2647 | ira_assert (ira_reg_equiv[from_regno].invariant == NULL_RTX); | |
2648 | ira_assert (ira_reg_equiv[to_regno].constant == NULL_RTX | |
2649 | || rtx_equal_p (ira_reg_equiv[to_regno].constant, x)); | |
2650 | ira_reg_equiv[to_regno].constant = x; | |
2651 | } | |
2652 | else | |
2653 | { | |
2654 | x = ira_reg_equiv[from_regno].invariant; | |
2655 | ira_assert (x != NULL_RTX); | |
2656 | ira_assert (ira_reg_equiv[to_regno].invariant == NULL_RTX | |
2657 | || rtx_equal_p (ira_reg_equiv[to_regno].invariant, x)); | |
2658 | ira_reg_equiv[to_regno].invariant = x; | |
2659 | } | |
2660 | if (find_reg_note (insn, REG_EQUIV, x) == NULL_RTX) | |
2661 | { | |
2662 | note = set_unique_reg_note (insn, REG_EQUIV, x); | |
2663 | gcc_assert (note != NULL_RTX); | |
2664 | if (internal_flag_ira_verbose > 3 && ira_dump_file != NULL) | |
2665 | { | |
2666 | fprintf (ira_dump_file, | |
2667 | " Adding equiv note to insn %u for reg %d ", | |
2668 | INSN_UID (insn), to_regno); | |
cfbeaedf | 2669 | dump_value_slim (ira_dump_file, x, 1); |
55a2c322 VM |
2670 | fprintf (ira_dump_file, "\n"); |
2671 | } | |
2672 | } | |
2673 | } | |
2674 | ira_reg_equiv[to_regno].init_insns | |
2675 | = gen_rtx_INSN_LIST (VOIDmode, insn, | |
2676 | ira_reg_equiv[to_regno].init_insns); | |
2677 | if (internal_flag_ira_verbose > 3 && ira_dump_file != NULL) | |
2678 | fprintf (ira_dump_file, | |
2679 | " Adding equiv init move insn %u to reg %d\n", | |
2680 | INSN_UID (insn), to_regno); | |
2681 | } | |
2682 | ||
058e97ec VM |
2683 | /* Fix values of array REG_EQUIV_INIT after live range splitting done |
2684 | by IRA. */ | |
2685 | static void | |
2686 | fix_reg_equiv_init (void) | |
2687 | { | |
70cc3288 | 2688 | int max_regno = max_reg_num (); |
f2034d06 | 2689 | int i, new_regno, max; |
618bccf9 TS |
2690 | rtx set; |
2691 | rtx_insn_list *x, *next, *prev; | |
2692 | rtx_insn *insn; | |
b8698a0f | 2693 | |
70cc3288 | 2694 | if (max_regno_before_ira < max_regno) |
058e97ec | 2695 | { |
9771b263 | 2696 | max = vec_safe_length (reg_equivs); |
f2034d06 JL |
2697 | grow_reg_equivs (); |
2698 | for (i = FIRST_PSEUDO_REGISTER; i < max; i++) | |
618bccf9 | 2699 | for (prev = NULL, x = reg_equiv_init (i); |
f2034d06 JL |
2700 | x != NULL_RTX; |
2701 | x = next) | |
058e97ec | 2702 | { |
618bccf9 TS |
2703 | next = x->next (); |
2704 | insn = x->insn (); | |
2705 | set = single_set (insn); | |
058e97ec VM |
2706 | ira_assert (set != NULL_RTX |
2707 | && (REG_P (SET_DEST (set)) || REG_P (SET_SRC (set)))); | |
2708 | if (REG_P (SET_DEST (set)) | |
2709 | && ((int) REGNO (SET_DEST (set)) == i | |
2710 | || (int) ORIGINAL_REGNO (SET_DEST (set)) == i)) | |
2711 | new_regno = REGNO (SET_DEST (set)); | |
2712 | else if (REG_P (SET_SRC (set)) | |
2713 | && ((int) REGNO (SET_SRC (set)) == i | |
2714 | || (int) ORIGINAL_REGNO (SET_SRC (set)) == i)) | |
2715 | new_regno = REGNO (SET_SRC (set)); | |
2716 | else | |
2717 | gcc_unreachable (); | |
2718 | if (new_regno == i) | |
2719 | prev = x; | |
2720 | else | |
2721 | { | |
55a2c322 | 2722 | /* Remove the wrong list element. */ |
058e97ec | 2723 | if (prev == NULL_RTX) |
f2034d06 | 2724 | reg_equiv_init (i) = next; |
058e97ec VM |
2725 | else |
2726 | XEXP (prev, 1) = next; | |
f2034d06 JL |
2727 | XEXP (x, 1) = reg_equiv_init (new_regno); |
2728 | reg_equiv_init (new_regno) = x; | |
058e97ec VM |
2729 | } |
2730 | } | |
2731 | } | |
2732 | } | |
2733 | ||
2734 | #ifdef ENABLE_IRA_CHECKING | |
2735 | /* Print redundant memory-memory copies. */ | |
2736 | static void | |
2737 | print_redundant_copies (void) | |
2738 | { | |
2739 | int hard_regno; | |
2740 | ira_allocno_t a; | |
2741 | ira_copy_t cp, next_cp; | |
2742 | ira_allocno_iterator ai; | |
b8698a0f | 2743 | |
058e97ec VM |
2744 | FOR_EACH_ALLOCNO (a, ai) |
2745 | { | |
2746 | if (ALLOCNO_CAP_MEMBER (a) != NULL) | |
2b9c63a2 | 2747 | /* It is a cap. */ |
058e97ec VM |
2748 | continue; |
2749 | hard_regno = ALLOCNO_HARD_REGNO (a); | |
2750 | if (hard_regno >= 0) | |
2751 | continue; | |
2752 | for (cp = ALLOCNO_COPIES (a); cp != NULL; cp = next_cp) | |
2753 | if (cp->first == a) | |
2754 | next_cp = cp->next_first_allocno_copy; | |
2755 | else | |
2756 | { | |
2757 | next_cp = cp->next_second_allocno_copy; | |
2758 | if (internal_flag_ira_verbose > 4 && ira_dump_file != NULL | |
2759 | && cp->insn != NULL_RTX | |
2760 | && ALLOCNO_HARD_REGNO (cp->first) == hard_regno) | |
2761 | fprintf (ira_dump_file, | |
2762 | " Redundant move from %d(freq %d):%d\n", | |
2763 | INSN_UID (cp->insn), cp->freq, hard_regno); | |
2764 | } | |
2765 | } | |
2766 | } | |
2767 | #endif | |
2768 | ||
2769 | /* Setup preferred and alternative classes for new pseudo-registers | |
2770 | created by IRA starting with START. */ | |
2771 | static void | |
2772 | setup_preferred_alternate_classes_for_new_pseudos (int start) | |
2773 | { | |
2774 | int i, old_regno; | |
2775 | int max_regno = max_reg_num (); | |
2776 | ||
2777 | for (i = start; i < max_regno; i++) | |
2778 | { | |
2779 | old_regno = ORIGINAL_REGNO (regno_reg_rtx[i]); | |
b8698a0f | 2780 | ira_assert (i != old_regno); |
058e97ec | 2781 | setup_reg_classes (i, reg_preferred_class (old_regno), |
ce18efcb | 2782 | reg_alternate_class (old_regno), |
1756cb66 | 2783 | reg_allocno_class (old_regno)); |
058e97ec VM |
2784 | if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL) |
2785 | fprintf (ira_dump_file, | |
2786 | " New r%d: setting preferred %s, alternative %s\n", | |
2787 | i, reg_class_names[reg_preferred_class (old_regno)], | |
2788 | reg_class_names[reg_alternate_class (old_regno)]); | |
2789 | } | |
2790 | } | |
2791 | ||
2792 | \f | |
df3e3493 | 2793 | /* The number of entries allocated in reg_info. */ |
fb99ee9b | 2794 | static int allocated_reg_info_size; |
058e97ec VM |
2795 | |
2796 | /* Regional allocation can create new pseudo-registers. This function | |
2797 | expands some arrays for pseudo-registers. */ | |
2798 | static void | |
fb99ee9b | 2799 | expand_reg_info (void) |
058e97ec VM |
2800 | { |
2801 | int i; | |
2802 | int size = max_reg_num (); | |
2803 | ||
2804 | resize_reg_info (); | |
fb99ee9b | 2805 | for (i = allocated_reg_info_size; i < size; i++) |
ce18efcb | 2806 | setup_reg_classes (i, GENERAL_REGS, ALL_REGS, GENERAL_REGS); |
fb99ee9b BS |
2807 | setup_preferred_alternate_classes_for_new_pseudos (allocated_reg_info_size); |
2808 | allocated_reg_info_size = size; | |
058e97ec VM |
2809 | } |
2810 | ||
3553f0bb VM |
2811 | /* Return TRUE if there is too high register pressure in the function. |
2812 | It is used to decide when stack slot sharing is worth to do. */ | |
2813 | static bool | |
2814 | too_high_register_pressure_p (void) | |
2815 | { | |
2816 | int i; | |
1756cb66 | 2817 | enum reg_class pclass; |
b8698a0f | 2818 | |
1756cb66 | 2819 | for (i = 0; i < ira_pressure_classes_num; i++) |
3553f0bb | 2820 | { |
1756cb66 VM |
2821 | pclass = ira_pressure_classes[i]; |
2822 | if (ira_loop_tree_root->reg_pressure[pclass] > 10000) | |
3553f0bb VM |
2823 | return true; |
2824 | } | |
2825 | return false; | |
2826 | } | |
2827 | ||
058e97ec VM |
2828 | \f |
2829 | ||
2af2dbdc VM |
2830 | /* Indicate that hard register number FROM was eliminated and replaced with |
2831 | an offset from hard register number TO. The status of hard registers live | |
2832 | at the start of a basic block is updated by replacing a use of FROM with | |
2833 | a use of TO. */ | |
2834 | ||
2835 | void | |
2836 | mark_elimination (int from, int to) | |
2837 | { | |
2838 | basic_block bb; | |
bf744527 | 2839 | bitmap r; |
2af2dbdc | 2840 | |
11cd3bed | 2841 | FOR_EACH_BB_FN (bb, cfun) |
2af2dbdc | 2842 | { |
bf744527 SB |
2843 | r = DF_LR_IN (bb); |
2844 | if (bitmap_bit_p (r, from)) | |
2845 | { | |
2846 | bitmap_clear_bit (r, from); | |
2847 | bitmap_set_bit (r, to); | |
2848 | } | |
2849 | if (! df_live) | |
2850 | continue; | |
2851 | r = DF_LIVE_IN (bb); | |
2852 | if (bitmap_bit_p (r, from)) | |
2af2dbdc | 2853 | { |
bf744527 SB |
2854 | bitmap_clear_bit (r, from); |
2855 | bitmap_set_bit (r, to); | |
2af2dbdc VM |
2856 | } |
2857 | } | |
2858 | } | |
2859 | ||
2860 | \f | |
2861 | ||
55a2c322 VM |
2862 | /* The length of the following array. */ |
2863 | int ira_reg_equiv_len; | |
2864 | ||
2865 | /* Info about equiv. info for each register. */ | |
4c2b2d79 | 2866 | struct ira_reg_equiv_s *ira_reg_equiv; |
55a2c322 VM |
2867 | |
2868 | /* Expand ira_reg_equiv if necessary. */ | |
2869 | void | |
2870 | ira_expand_reg_equiv (void) | |
2871 | { | |
2872 | int old = ira_reg_equiv_len; | |
2873 | ||
2874 | if (ira_reg_equiv_len > max_reg_num ()) | |
2875 | return; | |
2876 | ira_reg_equiv_len = max_reg_num () * 3 / 2 + 1; | |
2877 | ira_reg_equiv | |
4c2b2d79 | 2878 | = (struct ira_reg_equiv_s *) xrealloc (ira_reg_equiv, |
55a2c322 | 2879 | ira_reg_equiv_len |
4c2b2d79 | 2880 | * sizeof (struct ira_reg_equiv_s)); |
55a2c322 VM |
2881 | gcc_assert (old < ira_reg_equiv_len); |
2882 | memset (ira_reg_equiv + old, 0, | |
4c2b2d79 | 2883 | sizeof (struct ira_reg_equiv_s) * (ira_reg_equiv_len - old)); |
55a2c322 VM |
2884 | } |
2885 | ||
2886 | static void | |
2887 | init_reg_equiv (void) | |
2888 | { | |
2889 | ira_reg_equiv_len = 0; | |
2890 | ira_reg_equiv = NULL; | |
2891 | ira_expand_reg_equiv (); | |
2892 | } | |
2893 | ||
2894 | static void | |
2895 | finish_reg_equiv (void) | |
2896 | { | |
2897 | free (ira_reg_equiv); | |
2898 | } | |
2899 | ||
2900 | \f | |
2901 | ||
2af2dbdc VM |
2902 | struct equivalence |
2903 | { | |
2af2dbdc VM |
2904 | /* Set when a REG_EQUIV note is found or created. Use to |
2905 | keep track of what memory accesses might be created later, | |
2906 | e.g. by reload. */ | |
2907 | rtx replacement; | |
2908 | rtx *src_p; | |
fb0ab697 JL |
2909 | |
2910 | /* The list of each instruction which initializes this register. | |
2911 | ||
2912 | NULL indicates we know nothing about this register's equivalence | |
2913 | properties. | |
2914 | ||
2915 | An INSN_LIST with a NULL insn indicates this pseudo is already | |
2916 | known to not have a valid equivalence. */ | |
2917 | rtx_insn_list *init_insns; | |
2918 | ||
2af2dbdc VM |
2919 | /* Loop depth is used to recognize equivalences which appear |
2920 | to be present within the same loop (or in an inner loop). */ | |
5ffa4e6a | 2921 | short loop_depth; |
2af2dbdc | 2922 | /* Nonzero if this had a preexisting REG_EQUIV note. */ |
5ffa4e6a | 2923 | unsigned char is_arg_equivalence : 1; |
8f5929e1 JJ |
2924 | /* Set when an attempt should be made to replace a register |
2925 | with the associated src_p entry. */ | |
5ffa4e6a FY |
2926 | unsigned char replace : 1; |
2927 | /* Set if this register has no known equivalence. */ | |
2928 | unsigned char no_equiv : 1; | |
2af2dbdc VM |
2929 | }; |
2930 | ||
2931 | /* reg_equiv[N] (where N is a pseudo reg number) is the equivalence | |
2932 | structure for that register. */ | |
2933 | static struct equivalence *reg_equiv; | |
2934 | ||
2935 | /* Used for communication between the following two functions: contains | |
2936 | a MEM that we wish to ensure remains unchanged. */ | |
2937 | static rtx equiv_mem; | |
2938 | ||
2939 | /* Set nonzero if EQUIV_MEM is modified. */ | |
2940 | static int equiv_mem_modified; | |
2941 | ||
2942 | /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified. | |
2943 | Called via note_stores. */ | |
2944 | static void | |
2945 | validate_equiv_mem_from_store (rtx dest, const_rtx set ATTRIBUTE_UNUSED, | |
2946 | void *data ATTRIBUTE_UNUSED) | |
2947 | { | |
2948 | if ((REG_P (dest) | |
2949 | && reg_overlap_mentioned_p (dest, equiv_mem)) | |
2950 | || (MEM_P (dest) | |
a55757ea | 2951 | && anti_dependence (equiv_mem, dest))) |
2af2dbdc VM |
2952 | equiv_mem_modified = 1; |
2953 | } | |
2954 | ||
2955 | /* Verify that no store between START and the death of REG invalidates | |
2956 | MEMREF. MEMREF is invalidated by modifying a register used in MEMREF, | |
2957 | by storing into an overlapping memory location, or with a non-const | |
2958 | CALL_INSN. | |
2959 | ||
2960 | Return 1 if MEMREF remains valid. */ | |
2961 | static int | |
b32d5189 | 2962 | validate_equiv_mem (rtx_insn *start, rtx reg, rtx memref) |
2af2dbdc | 2963 | { |
b32d5189 | 2964 | rtx_insn *insn; |
2af2dbdc VM |
2965 | rtx note; |
2966 | ||
2967 | equiv_mem = memref; | |
2968 | equiv_mem_modified = 0; | |
2969 | ||
2970 | /* If the memory reference has side effects or is volatile, it isn't a | |
2971 | valid equivalence. */ | |
2972 | if (side_effects_p (memref)) | |
2973 | return 0; | |
2974 | ||
2975 | for (insn = start; insn && ! equiv_mem_modified; insn = NEXT_INSN (insn)) | |
2976 | { | |
2977 | if (! INSN_P (insn)) | |
2978 | continue; | |
2979 | ||
2980 | if (find_reg_note (insn, REG_DEAD, reg)) | |
2981 | return 1; | |
2982 | ||
a22265a4 JL |
2983 | /* This used to ignore readonly memory and const/pure calls. The problem |
2984 | is the equivalent form may reference a pseudo which gets assigned a | |
2985 | call clobbered hard reg. When we later replace REG with its | |
2986 | equivalent form, the value in the call-clobbered reg has been | |
2987 | changed and all hell breaks loose. */ | |
2988 | if (CALL_P (insn)) | |
2af2dbdc VM |
2989 | return 0; |
2990 | ||
2991 | note_stores (PATTERN (insn), validate_equiv_mem_from_store, NULL); | |
2992 | ||
2993 | /* If a register mentioned in MEMREF is modified via an | |
2994 | auto-increment, we lose the equivalence. Do the same if one | |
2995 | dies; although we could extend the life, it doesn't seem worth | |
2996 | the trouble. */ | |
2997 | ||
2998 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
2999 | if ((REG_NOTE_KIND (note) == REG_INC | |
3000 | || REG_NOTE_KIND (note) == REG_DEAD) | |
3001 | && REG_P (XEXP (note, 0)) | |
3002 | && reg_overlap_mentioned_p (XEXP (note, 0), memref)) | |
3003 | return 0; | |
3004 | } | |
3005 | ||
3006 | return 0; | |
3007 | } | |
3008 | ||
3009 | /* Returns zero if X is known to be invariant. */ | |
3010 | static int | |
3011 | equiv_init_varies_p (rtx x) | |
3012 | { | |
3013 | RTX_CODE code = GET_CODE (x); | |
3014 | int i; | |
3015 | const char *fmt; | |
3016 | ||
3017 | switch (code) | |
3018 | { | |
3019 | case MEM: | |
3020 | return !MEM_READONLY_P (x) || equiv_init_varies_p (XEXP (x, 0)); | |
3021 | ||
3022 | case CONST: | |
d8116890 | 3023 | CASE_CONST_ANY: |
2af2dbdc VM |
3024 | case SYMBOL_REF: |
3025 | case LABEL_REF: | |
3026 | return 0; | |
3027 | ||
3028 | case REG: | |
3029 | return reg_equiv[REGNO (x)].replace == 0 && rtx_varies_p (x, 0); | |
3030 | ||
3031 | case ASM_OPERANDS: | |
3032 | if (MEM_VOLATILE_P (x)) | |
3033 | return 1; | |
3034 | ||
3035 | /* Fall through. */ | |
3036 | ||
3037 | default: | |
3038 | break; | |
3039 | } | |
3040 | ||
3041 | fmt = GET_RTX_FORMAT (code); | |
3042 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3043 | if (fmt[i] == 'e') | |
3044 | { | |
3045 | if (equiv_init_varies_p (XEXP (x, i))) | |
3046 | return 1; | |
3047 | } | |
3048 | else if (fmt[i] == 'E') | |
3049 | { | |
3050 | int j; | |
3051 | for (j = 0; j < XVECLEN (x, i); j++) | |
3052 | if (equiv_init_varies_p (XVECEXP (x, i, j))) | |
3053 | return 1; | |
3054 | } | |
3055 | ||
3056 | return 0; | |
3057 | } | |
3058 | ||
3059 | /* Returns nonzero if X (used to initialize register REGNO) is movable. | |
3060 | X is only movable if the registers it uses have equivalent initializations | |
3061 | which appear to be within the same loop (or in an inner loop) and movable | |
3062 | or if they are not candidates for local_alloc and don't vary. */ | |
3063 | static int | |
3064 | equiv_init_movable_p (rtx x, int regno) | |
3065 | { | |
3066 | int i, j; | |
3067 | const char *fmt; | |
3068 | enum rtx_code code = GET_CODE (x); | |
3069 | ||
3070 | switch (code) | |
3071 | { | |
3072 | case SET: | |
3073 | return equiv_init_movable_p (SET_SRC (x), regno); | |
3074 | ||
3075 | case CC0: | |
3076 | case CLOBBER: | |
3077 | return 0; | |
3078 | ||
3079 | case PRE_INC: | |
3080 | case PRE_DEC: | |
3081 | case POST_INC: | |
3082 | case POST_DEC: | |
3083 | case PRE_MODIFY: | |
3084 | case POST_MODIFY: | |
3085 | return 0; | |
3086 | ||
3087 | case REG: | |
1756cb66 VM |
3088 | return ((reg_equiv[REGNO (x)].loop_depth >= reg_equiv[regno].loop_depth |
3089 | && reg_equiv[REGNO (x)].replace) | |
3090 | || (REG_BASIC_BLOCK (REGNO (x)) < NUM_FIXED_BLOCKS | |
3091 | && ! rtx_varies_p (x, 0))); | |
2af2dbdc VM |
3092 | |
3093 | case UNSPEC_VOLATILE: | |
3094 | return 0; | |
3095 | ||
3096 | case ASM_OPERANDS: | |
3097 | if (MEM_VOLATILE_P (x)) | |
3098 | return 0; | |
3099 | ||
3100 | /* Fall through. */ | |
3101 | ||
3102 | default: | |
3103 | break; | |
3104 | } | |
3105 | ||
3106 | fmt = GET_RTX_FORMAT (code); | |
3107 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3108 | switch (fmt[i]) | |
3109 | { | |
3110 | case 'e': | |
3111 | if (! equiv_init_movable_p (XEXP (x, i), regno)) | |
3112 | return 0; | |
3113 | break; | |
3114 | case 'E': | |
3115 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
3116 | if (! equiv_init_movable_p (XVECEXP (x, i, j), regno)) | |
3117 | return 0; | |
3118 | break; | |
3119 | } | |
3120 | ||
3121 | return 1; | |
3122 | } | |
3123 | ||
1756cb66 VM |
3124 | /* TRUE if X uses any registers for which reg_equiv[REGNO].replace is |
3125 | true. */ | |
2af2dbdc VM |
3126 | static int |
3127 | contains_replace_regs (rtx x) | |
3128 | { | |
3129 | int i, j; | |
3130 | const char *fmt; | |
3131 | enum rtx_code code = GET_CODE (x); | |
3132 | ||
3133 | switch (code) | |
3134 | { | |
2af2dbdc VM |
3135 | case CONST: |
3136 | case LABEL_REF: | |
3137 | case SYMBOL_REF: | |
d8116890 | 3138 | CASE_CONST_ANY: |
2af2dbdc VM |
3139 | case PC: |
3140 | case CC0: | |
3141 | case HIGH: | |
3142 | return 0; | |
3143 | ||
3144 | case REG: | |
3145 | return reg_equiv[REGNO (x)].replace; | |
3146 | ||
3147 | default: | |
3148 | break; | |
3149 | } | |
3150 | ||
3151 | fmt = GET_RTX_FORMAT (code); | |
3152 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3153 | switch (fmt[i]) | |
3154 | { | |
3155 | case 'e': | |
3156 | if (contains_replace_regs (XEXP (x, i))) | |
3157 | return 1; | |
3158 | break; | |
3159 | case 'E': | |
3160 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
3161 | if (contains_replace_regs (XVECEXP (x, i, j))) | |
3162 | return 1; | |
3163 | break; | |
3164 | } | |
3165 | ||
3166 | return 0; | |
3167 | } | |
3168 | ||
3169 | /* TRUE if X references a memory location that would be affected by a store | |
3170 | to MEMREF. */ | |
3171 | static int | |
3172 | memref_referenced_p (rtx memref, rtx x) | |
3173 | { | |
3174 | int i, j; | |
3175 | const char *fmt; | |
3176 | enum rtx_code code = GET_CODE (x); | |
3177 | ||
3178 | switch (code) | |
3179 | { | |
2af2dbdc VM |
3180 | case CONST: |
3181 | case LABEL_REF: | |
3182 | case SYMBOL_REF: | |
d8116890 | 3183 | CASE_CONST_ANY: |
2af2dbdc VM |
3184 | case PC: |
3185 | case CC0: | |
3186 | case HIGH: | |
3187 | case LO_SUM: | |
3188 | return 0; | |
3189 | ||
3190 | case REG: | |
3191 | return (reg_equiv[REGNO (x)].replacement | |
3192 | && memref_referenced_p (memref, | |
3193 | reg_equiv[REGNO (x)].replacement)); | |
3194 | ||
3195 | case MEM: | |
53d9622b | 3196 | if (true_dependence (memref, VOIDmode, x)) |
2af2dbdc VM |
3197 | return 1; |
3198 | break; | |
3199 | ||
3200 | case SET: | |
3201 | /* If we are setting a MEM, it doesn't count (its address does), but any | |
3202 | other SET_DEST that has a MEM in it is referencing the MEM. */ | |
3203 | if (MEM_P (SET_DEST (x))) | |
3204 | { | |
3205 | if (memref_referenced_p (memref, XEXP (SET_DEST (x), 0))) | |
3206 | return 1; | |
3207 | } | |
3208 | else if (memref_referenced_p (memref, SET_DEST (x))) | |
3209 | return 1; | |
3210 | ||
3211 | return memref_referenced_p (memref, SET_SRC (x)); | |
3212 | ||
3213 | default: | |
3214 | break; | |
3215 | } | |
3216 | ||
3217 | fmt = GET_RTX_FORMAT (code); | |
3218 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3219 | switch (fmt[i]) | |
3220 | { | |
3221 | case 'e': | |
3222 | if (memref_referenced_p (memref, XEXP (x, i))) | |
3223 | return 1; | |
3224 | break; | |
3225 | case 'E': | |
3226 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
3227 | if (memref_referenced_p (memref, XVECEXP (x, i, j))) | |
3228 | return 1; | |
3229 | break; | |
3230 | } | |
3231 | ||
3232 | return 0; | |
3233 | } | |
3234 | ||
3235 | /* TRUE if some insn in the range (START, END] references a memory location | |
3236 | that would be affected by a store to MEMREF. */ | |
3237 | static int | |
b32d5189 | 3238 | memref_used_between_p (rtx memref, rtx_insn *start, rtx_insn *end) |
2af2dbdc | 3239 | { |
b32d5189 | 3240 | rtx_insn *insn; |
2af2dbdc VM |
3241 | |
3242 | for (insn = NEXT_INSN (start); insn != NEXT_INSN (end); | |
3243 | insn = NEXT_INSN (insn)) | |
3244 | { | |
b5b8b0ac | 3245 | if (!NONDEBUG_INSN_P (insn)) |
2af2dbdc | 3246 | continue; |
b8698a0f | 3247 | |
2af2dbdc VM |
3248 | if (memref_referenced_p (memref, PATTERN (insn))) |
3249 | return 1; | |
3250 | ||
3251 | /* Nonconst functions may access memory. */ | |
3252 | if (CALL_P (insn) && (! RTL_CONST_CALL_P (insn))) | |
3253 | return 1; | |
3254 | } | |
3255 | ||
3256 | return 0; | |
3257 | } | |
3258 | ||
3259 | /* Mark REG as having no known equivalence. | |
3260 | Some instructions might have been processed before and furnished | |
3261 | with REG_EQUIV notes for this register; these notes will have to be | |
3262 | removed. | |
3263 | STORE is the piece of RTL that does the non-constant / conflicting | |
3264 | assignment - a SET, CLOBBER or REG_INC note. It is currently not used, | |
3265 | but needs to be there because this function is called from note_stores. */ | |
3266 | static void | |
1756cb66 VM |
3267 | no_equiv (rtx reg, const_rtx store ATTRIBUTE_UNUSED, |
3268 | void *data ATTRIBUTE_UNUSED) | |
2af2dbdc VM |
3269 | { |
3270 | int regno; | |
fb0ab697 | 3271 | rtx_insn_list *list; |
2af2dbdc VM |
3272 | |
3273 | if (!REG_P (reg)) | |
3274 | return; | |
3275 | regno = REGNO (reg); | |
5ffa4e6a | 3276 | reg_equiv[regno].no_equiv = 1; |
2af2dbdc | 3277 | list = reg_equiv[regno].init_insns; |
fb0ab697 | 3278 | if (list && list->insn () == NULL) |
2af2dbdc | 3279 | return; |
fb0ab697 | 3280 | reg_equiv[regno].init_insns = gen_rtx_INSN_LIST (VOIDmode, NULL_RTX, NULL); |
2af2dbdc VM |
3281 | reg_equiv[regno].replacement = NULL_RTX; |
3282 | /* This doesn't matter for equivalences made for argument registers, we | |
3283 | should keep their initialization insns. */ | |
3284 | if (reg_equiv[regno].is_arg_equivalence) | |
3285 | return; | |
55a2c322 | 3286 | ira_reg_equiv[regno].defined_p = false; |
0cc97fc5 | 3287 | ira_reg_equiv[regno].init_insns = NULL; |
fb0ab697 | 3288 | for (; list; list = list->next ()) |
2af2dbdc | 3289 | { |
fb0ab697 | 3290 | rtx_insn *insn = list->insn (); |
2af2dbdc VM |
3291 | remove_note (insn, find_reg_note (insn, REG_EQUIV, NULL_RTX)); |
3292 | } | |
3293 | } | |
3294 | ||
e3f9e0ac WM |
3295 | /* Check whether the SUBREG is a paradoxical subreg and set the result |
3296 | in PDX_SUBREGS. */ | |
3297 | ||
40954ce5 RS |
3298 | static void |
3299 | set_paradoxical_subreg (rtx_insn *insn, bool *pdx_subregs) | |
e3f9e0ac | 3300 | { |
40954ce5 RS |
3301 | subrtx_iterator::array_type array; |
3302 | FOR_EACH_SUBRTX (iter, array, PATTERN (insn), NONCONST) | |
3303 | { | |
3304 | const_rtx subreg = *iter; | |
3305 | if (GET_CODE (subreg) == SUBREG) | |
3306 | { | |
3307 | const_rtx reg = SUBREG_REG (subreg); | |
3308 | if (REG_P (reg) && paradoxical_subreg_p (subreg)) | |
3309 | pdx_subregs[REGNO (reg)] = true; | |
3310 | } | |
3311 | } | |
e3f9e0ac WM |
3312 | } |
3313 | ||
3a6191b1 JJ |
3314 | /* In DEBUG_INSN location adjust REGs from CLEARED_REGS bitmap to the |
3315 | equivalent replacement. */ | |
3316 | ||
3317 | static rtx | |
3318 | adjust_cleared_regs (rtx loc, const_rtx old_rtx ATTRIBUTE_UNUSED, void *data) | |
3319 | { | |
3320 | if (REG_P (loc)) | |
3321 | { | |
3322 | bitmap cleared_regs = (bitmap) data; | |
3323 | if (bitmap_bit_p (cleared_regs, REGNO (loc))) | |
b8f045e2 | 3324 | return simplify_replace_fn_rtx (copy_rtx (*reg_equiv[REGNO (loc)].src_p), |
3a6191b1 JJ |
3325 | NULL_RTX, adjust_cleared_regs, data); |
3326 | } | |
3327 | return NULL_RTX; | |
3328 | } | |
3329 | ||
2af2dbdc VM |
3330 | /* Nonzero if we recorded an equivalence for a LABEL_REF. */ |
3331 | static int recorded_label_ref; | |
3332 | ||
3333 | /* Find registers that are equivalent to a single value throughout the | |
1756cb66 VM |
3334 | compilation (either because they can be referenced in memory or are |
3335 | set once from a single constant). Lower their priority for a | |
3336 | register. | |
2af2dbdc | 3337 | |
1756cb66 VM |
3338 | If such a register is only referenced once, try substituting its |
3339 | value into the using insn. If it succeeds, we can eliminate the | |
3340 | register completely. | |
2af2dbdc | 3341 | |
55a2c322 | 3342 | Initialize init_insns in ira_reg_equiv array. |
2af2dbdc VM |
3343 | |
3344 | Return non-zero if jump label rebuilding should be done. */ | |
3345 | static int | |
3346 | update_equiv_regs (void) | |
3347 | { | |
b2908ba6 | 3348 | rtx_insn *insn; |
2af2dbdc VM |
3349 | basic_block bb; |
3350 | int loop_depth; | |
3351 | bitmap cleared_regs; | |
e3f9e0ac | 3352 | bool *pdx_subregs; |
b8698a0f | 3353 | |
2af2dbdc VM |
3354 | /* We need to keep track of whether or not we recorded a LABEL_REF so |
3355 | that we know if the jump optimizer needs to be rerun. */ | |
3356 | recorded_label_ref = 0; | |
3357 | ||
e3f9e0ac WM |
3358 | /* Use pdx_subregs to show whether a reg is used in a paradoxical |
3359 | subreg. */ | |
3360 | pdx_subregs = XCNEWVEC (bool, max_regno); | |
3361 | ||
2af2dbdc | 3362 | reg_equiv = XCNEWVEC (struct equivalence, max_regno); |
f2034d06 | 3363 | grow_reg_equivs (); |
2af2dbdc VM |
3364 | |
3365 | init_alias_analysis (); | |
3366 | ||
e3f9e0ac | 3367 | /* Scan insns and set pdx_subregs[regno] if the reg is used in a |
df3e3493 | 3368 | paradoxical subreg. Don't set such reg equivalent to a mem, |
e3f9e0ac WM |
3369 | because lra will not substitute such equiv memory in order to |
3370 | prevent access beyond allocated memory for paradoxical memory subreg. */ | |
11cd3bed | 3371 | FOR_EACH_BB_FN (bb, cfun) |
e3f9e0ac | 3372 | FOR_BB_INSNS (bb, insn) |
c34c46dd | 3373 | if (NONDEBUG_INSN_P (insn)) |
40954ce5 | 3374 | set_paradoxical_subreg (insn, pdx_subregs); |
e3f9e0ac | 3375 | |
2af2dbdc VM |
3376 | /* Scan the insns and find which registers have equivalences. Do this |
3377 | in a separate scan of the insns because (due to -fcse-follow-jumps) | |
3378 | a register can be set below its use. */ | |
11cd3bed | 3379 | FOR_EACH_BB_FN (bb, cfun) |
2af2dbdc | 3380 | { |
391886c8 | 3381 | loop_depth = bb_loop_depth (bb); |
2af2dbdc VM |
3382 | |
3383 | for (insn = BB_HEAD (bb); | |
3384 | insn != NEXT_INSN (BB_END (bb)); | |
3385 | insn = NEXT_INSN (insn)) | |
3386 | { | |
3387 | rtx note; | |
3388 | rtx set; | |
3389 | rtx dest, src; | |
3390 | int regno; | |
3391 | ||
3392 | if (! INSN_P (insn)) | |
3393 | continue; | |
3394 | ||
3395 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
3396 | if (REG_NOTE_KIND (note) == REG_INC) | |
3397 | no_equiv (XEXP (note, 0), note, NULL); | |
3398 | ||
3399 | set = single_set (insn); | |
3400 | ||
3401 | /* If this insn contains more (or less) than a single SET, | |
3402 | only mark all destinations as having no known equivalence. */ | |
5ffa4e6a | 3403 | if (set == NULL_RTX) |
2af2dbdc VM |
3404 | { |
3405 | note_stores (PATTERN (insn), no_equiv, NULL); | |
3406 | continue; | |
3407 | } | |
3408 | else if (GET_CODE (PATTERN (insn)) == PARALLEL) | |
3409 | { | |
3410 | int i; | |
3411 | ||
3412 | for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--) | |
3413 | { | |
3414 | rtx part = XVECEXP (PATTERN (insn), 0, i); | |
3415 | if (part != set) | |
3416 | note_stores (part, no_equiv, NULL); | |
3417 | } | |
3418 | } | |
3419 | ||
3420 | dest = SET_DEST (set); | |
3421 | src = SET_SRC (set); | |
3422 | ||
3423 | /* See if this is setting up the equivalence between an argument | |
3424 | register and its stack slot. */ | |
3425 | note = find_reg_note (insn, REG_EQUIV, NULL_RTX); | |
3426 | if (note) | |
3427 | { | |
3428 | gcc_assert (REG_P (dest)); | |
3429 | regno = REGNO (dest); | |
3430 | ||
55a2c322 VM |
3431 | /* Note that we don't want to clear init_insns in |
3432 | ira_reg_equiv even if there are multiple sets of this | |
3433 | register. */ | |
2af2dbdc VM |
3434 | reg_equiv[regno].is_arg_equivalence = 1; |
3435 | ||
5a107a0f VM |
3436 | /* The insn result can have equivalence memory although |
3437 | the equivalence is not set up by the insn. We add | |
3438 | this insn to init insns as it is a flag for now that | |
3439 | regno has an equivalence. We will remove the insn | |
3440 | from init insn list later. */ | |
3441 | if (rtx_equal_p (src, XEXP (note, 0)) || MEM_P (XEXP (note, 0))) | |
55a2c322 VM |
3442 | ira_reg_equiv[regno].init_insns |
3443 | = gen_rtx_INSN_LIST (VOIDmode, insn, | |
3444 | ira_reg_equiv[regno].init_insns); | |
2af2dbdc VM |
3445 | |
3446 | /* Continue normally in case this is a candidate for | |
3447 | replacements. */ | |
3448 | } | |
3449 | ||
3450 | if (!optimize) | |
3451 | continue; | |
3452 | ||
3453 | /* We only handle the case of a pseudo register being set | |
3454 | once, or always to the same value. */ | |
1fe28116 VM |
3455 | /* ??? The mn10200 port breaks if we add equivalences for |
3456 | values that need an ADDRESS_REGS register and set them equivalent | |
3457 | to a MEM of a pseudo. The actual problem is in the over-conservative | |
3458 | handling of INPADDR_ADDRESS / INPUT_ADDRESS / INPUT triples in | |
3459 | calculate_needs, but we traditionally work around this problem | |
3460 | here by rejecting equivalences when the destination is in a register | |
3461 | that's likely spilled. This is fragile, of course, since the | |
3462 | preferred class of a pseudo depends on all instructions that set | |
3463 | or use it. */ | |
3464 | ||
2af2dbdc VM |
3465 | if (!REG_P (dest) |
3466 | || (regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER | |
fb0ab697 JL |
3467 | || (reg_equiv[regno].init_insns |
3468 | && reg_equiv[regno].init_insns->insn () == NULL) | |
07b8f0a8 | 3469 | || (targetm.class_likely_spilled_p (reg_preferred_class (regno)) |
1fe28116 | 3470 | && MEM_P (src) && ! reg_equiv[regno].is_arg_equivalence)) |
2af2dbdc VM |
3471 | { |
3472 | /* This might be setting a SUBREG of a pseudo, a pseudo that is | |
3473 | also set somewhere else to a constant. */ | |
3474 | note_stores (set, no_equiv, NULL); | |
3475 | continue; | |
3476 | } | |
3477 | ||
e3f9e0ac WM |
3478 | /* Don't set reg (if pdx_subregs[regno] == true) equivalent to a mem. */ |
3479 | if (MEM_P (src) && pdx_subregs[regno]) | |
3480 | { | |
3481 | note_stores (set, no_equiv, NULL); | |
3482 | continue; | |
3483 | } | |
3484 | ||
2af2dbdc VM |
3485 | note = find_reg_note (insn, REG_EQUAL, NULL_RTX); |
3486 | ||
3487 | /* cse sometimes generates function invariants, but doesn't put a | |
3488 | REG_EQUAL note on the insn. Since this note would be redundant, | |
3489 | there's no point creating it earlier than here. */ | |
3490 | if (! note && ! rtx_varies_p (src, 0)) | |
3491 | note = set_unique_reg_note (insn, REG_EQUAL, copy_rtx (src)); | |
3492 | ||
3493 | /* Don't bother considering a REG_EQUAL note containing an EXPR_LIST | |
2b9c63a2 | 3494 | since it represents a function call. */ |
2af2dbdc VM |
3495 | if (note && GET_CODE (XEXP (note, 0)) == EXPR_LIST) |
3496 | note = NULL_RTX; | |
3497 | ||
5ffa4e6a FY |
3498 | if (DF_REG_DEF_COUNT (regno) != 1) |
3499 | { | |
3500 | bool equal_p = true; | |
3501 | rtx_insn_list *list; | |
3502 | ||
3503 | /* If we have already processed this pseudo and determined it | |
3504 | can not have an equivalence, then honor that decision. */ | |
3505 | if (reg_equiv[regno].no_equiv) | |
3506 | continue; | |
3507 | ||
3508 | if (! note | |
2af2dbdc VM |
3509 | || rtx_varies_p (XEXP (note, 0), 0) |
3510 | || (reg_equiv[regno].replacement | |
3511 | && ! rtx_equal_p (XEXP (note, 0), | |
5ffa4e6a FY |
3512 | reg_equiv[regno].replacement))) |
3513 | { | |
3514 | no_equiv (dest, set, NULL); | |
3515 | continue; | |
3516 | } | |
3517 | ||
3518 | list = reg_equiv[regno].init_insns; | |
3519 | for (; list; list = list->next ()) | |
3520 | { | |
3521 | rtx note_tmp; | |
3522 | rtx_insn *insn_tmp; | |
3523 | ||
3524 | insn_tmp = list->insn (); | |
3525 | note_tmp = find_reg_note (insn_tmp, REG_EQUAL, NULL_RTX); | |
3526 | gcc_assert (note_tmp); | |
3527 | if (! rtx_equal_p (XEXP (note, 0), XEXP (note_tmp, 0))) | |
3528 | { | |
3529 | equal_p = false; | |
3530 | break; | |
3531 | } | |
3532 | } | |
3533 | ||
3534 | if (! equal_p) | |
3535 | { | |
3536 | no_equiv (dest, set, NULL); | |
3537 | continue; | |
3538 | } | |
2af2dbdc | 3539 | } |
5ffa4e6a | 3540 | |
2af2dbdc VM |
3541 | /* Record this insn as initializing this register. */ |
3542 | reg_equiv[regno].init_insns | |
3543 | = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv[regno].init_insns); | |
3544 | ||
3545 | /* If this register is known to be equal to a constant, record that | |
3546 | it is always equivalent to the constant. */ | |
3547 | if (DF_REG_DEF_COUNT (regno) == 1 | |
3548 | && note && ! rtx_varies_p (XEXP (note, 0), 0)) | |
3549 | { | |
3550 | rtx note_value = XEXP (note, 0); | |
3551 | remove_note (insn, note); | |
3552 | set_unique_reg_note (insn, REG_EQUIV, note_value); | |
3553 | } | |
3554 | ||
3555 | /* If this insn introduces a "constant" register, decrease the priority | |
3556 | of that register. Record this insn if the register is only used once | |
3557 | more and the equivalence value is the same as our source. | |
3558 | ||
3559 | The latter condition is checked for two reasons: First, it is an | |
3560 | indication that it may be more efficient to actually emit the insn | |
3561 | as written (if no registers are available, reload will substitute | |
3562 | the equivalence). Secondly, it avoids problems with any registers | |
3563 | dying in this insn whose death notes would be missed. | |
3564 | ||
3565 | If we don't have a REG_EQUIV note, see if this insn is loading | |
3566 | a register used only in one basic block from a MEM. If so, and the | |
3567 | MEM remains unchanged for the life of the register, add a REG_EQUIV | |
3568 | note. */ | |
2af2dbdc VM |
3569 | note = find_reg_note (insn, REG_EQUIV, NULL_RTX); |
3570 | ||
5ffa4e6a | 3571 | if (note == NULL_RTX && REG_BASIC_BLOCK (regno) >= NUM_FIXED_BLOCKS |
2af2dbdc VM |
3572 | && MEM_P (SET_SRC (set)) |
3573 | && validate_equiv_mem (insn, dest, SET_SRC (set))) | |
3574 | note = set_unique_reg_note (insn, REG_EQUIV, copy_rtx (SET_SRC (set))); | |
3575 | ||
3576 | if (note) | |
3577 | { | |
3578 | int regno = REGNO (dest); | |
3579 | rtx x = XEXP (note, 0); | |
3580 | ||
3581 | /* If we haven't done so, record for reload that this is an | |
3582 | equivalencing insn. */ | |
3583 | if (!reg_equiv[regno].is_arg_equivalence) | |
55a2c322 VM |
3584 | ira_reg_equiv[regno].init_insns |
3585 | = gen_rtx_INSN_LIST (VOIDmode, insn, | |
3586 | ira_reg_equiv[regno].init_insns); | |
2af2dbdc VM |
3587 | |
3588 | /* Record whether or not we created a REG_EQUIV note for a LABEL_REF. | |
3589 | We might end up substituting the LABEL_REF for uses of the | |
3590 | pseudo here or later. That kind of transformation may turn an | |
3591 | indirect jump into a direct jump, in which case we must rerun the | |
3592 | jump optimizer to ensure that the JUMP_LABEL fields are valid. */ | |
3593 | if (GET_CODE (x) == LABEL_REF | |
3594 | || (GET_CODE (x) == CONST | |
3595 | && GET_CODE (XEXP (x, 0)) == PLUS | |
3596 | && (GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF))) | |
3597 | recorded_label_ref = 1; | |
3598 | ||
3599 | reg_equiv[regno].replacement = x; | |
3600 | reg_equiv[regno].src_p = &SET_SRC (set); | |
5ffa4e6a | 3601 | reg_equiv[regno].loop_depth = (short) loop_depth; |
2af2dbdc VM |
3602 | |
3603 | /* Don't mess with things live during setjmp. */ | |
3604 | if (REG_LIVE_LENGTH (regno) >= 0 && optimize) | |
3605 | { | |
3606 | /* Note that the statement below does not affect the priority | |
3607 | in local-alloc! */ | |
3608 | REG_LIVE_LENGTH (regno) *= 2; | |
3609 | ||
3610 | /* If the register is referenced exactly twice, meaning it is | |
3611 | set once and used once, indicate that the reference may be | |
3612 | replaced by the equivalence we computed above. Do this | |
3613 | even if the register is only used in one block so that | |
3614 | dependencies can be handled where the last register is | |
3615 | used in a different block (i.e. HIGH / LO_SUM sequences) | |
3616 | and to reduce the number of registers alive across | |
3617 | calls. */ | |
3618 | ||
3619 | if (REG_N_REFS (regno) == 2 | |
3620 | && (rtx_equal_p (x, src) | |
3621 | || ! equiv_init_varies_p (src)) | |
3622 | && NONJUMP_INSN_P (insn) | |
3623 | && equiv_init_movable_p (PATTERN (insn), regno)) | |
3624 | reg_equiv[regno].replace = 1; | |
3625 | } | |
3626 | } | |
3627 | } | |
3628 | } | |
3629 | ||
3630 | if (!optimize) | |
3631 | goto out; | |
3632 | ||
3633 | /* A second pass, to gather additional equivalences with memory. This needs | |
3634 | to be done after we know which registers we are going to replace. */ | |
3635 | ||
3636 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
3637 | { | |
3638 | rtx set, src, dest; | |
3639 | unsigned regno; | |
3640 | ||
3641 | if (! INSN_P (insn)) | |
3642 | continue; | |
3643 | ||
3644 | set = single_set (insn); | |
3645 | if (! set) | |
3646 | continue; | |
3647 | ||
3648 | dest = SET_DEST (set); | |
3649 | src = SET_SRC (set); | |
3650 | ||
3651 | /* If this sets a MEM to the contents of a REG that is only used | |
3652 | in a single basic block, see if the register is always equivalent | |
3653 | to that memory location and if moving the store from INSN to the | |
3654 | insn that set REG is safe. If so, put a REG_EQUIV note on the | |
3655 | initializing insn. | |
3656 | ||
3657 | Don't add a REG_EQUIV note if the insn already has one. The existing | |
3658 | REG_EQUIV is likely more useful than the one we are adding. | |
3659 | ||
3660 | If one of the regs in the address has reg_equiv[REGNO].replace set, | |
3661 | then we can't add this REG_EQUIV note. The reg_equiv[REGNO].replace | |
3662 | optimization may move the set of this register immediately before | |
3663 | insn, which puts it after reg_equiv[REGNO].init_insns, and hence | |
3664 | the mention in the REG_EQUIV note would be to an uninitialized | |
3665 | pseudo. */ | |
3666 | ||
3667 | if (MEM_P (dest) && REG_P (src) | |
3668 | && (regno = REGNO (src)) >= FIRST_PSEUDO_REGISTER | |
3669 | && REG_BASIC_BLOCK (regno) >= NUM_FIXED_BLOCKS | |
3670 | && DF_REG_DEF_COUNT (regno) == 1 | |
fb0ab697 JL |
3671 | && reg_equiv[regno].init_insns != NULL |
3672 | && reg_equiv[regno].init_insns->insn () != NULL | |
2af2dbdc VM |
3673 | && ! find_reg_note (XEXP (reg_equiv[regno].init_insns, 0), |
3674 | REG_EQUIV, NULL_RTX) | |
e3f9e0ac WM |
3675 | && ! contains_replace_regs (XEXP (dest, 0)) |
3676 | && ! pdx_subregs[regno]) | |
2af2dbdc | 3677 | { |
b2908ba6 DM |
3678 | rtx_insn *init_insn = |
3679 | as_a <rtx_insn *> (XEXP (reg_equiv[regno].init_insns, 0)); | |
2af2dbdc VM |
3680 | if (validate_equiv_mem (init_insn, src, dest) |
3681 | && ! memref_used_between_p (dest, init_insn, insn) | |
3682 | /* Attaching a REG_EQUIV note will fail if INIT_INSN has | |
3683 | multiple sets. */ | |
3684 | && set_unique_reg_note (init_insn, REG_EQUIV, copy_rtx (dest))) | |
3685 | { | |
3686 | /* This insn makes the equivalence, not the one initializing | |
3687 | the register. */ | |
55a2c322 | 3688 | ira_reg_equiv[regno].init_insns |
2af2dbdc VM |
3689 | = gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX); |
3690 | df_notes_rescan (init_insn); | |
3691 | } | |
3692 | } | |
3693 | } | |
3694 | ||
3695 | cleared_regs = BITMAP_ALLOC (NULL); | |
3696 | /* Now scan all regs killed in an insn to see if any of them are | |
3697 | registers only used that once. If so, see if we can replace the | |
3698 | reference with the equivalent form. If we can, delete the | |
3699 | initializing reference and this register will go away. If we | |
3700 | can't replace the reference, and the initializing reference is | |
3701 | within the same loop (or in an inner loop), then move the register | |
3702 | initialization just before the use, so that they are in the same | |
3703 | basic block. */ | |
4f42035e | 3704 | FOR_EACH_BB_REVERSE_FN (bb, cfun) |
2af2dbdc | 3705 | { |
391886c8 | 3706 | loop_depth = bb_loop_depth (bb); |
2af2dbdc VM |
3707 | for (insn = BB_END (bb); |
3708 | insn != PREV_INSN (BB_HEAD (bb)); | |
3709 | insn = PREV_INSN (insn)) | |
3710 | { | |
3711 | rtx link; | |
3712 | ||
3713 | if (! INSN_P (insn)) | |
3714 | continue; | |
3715 | ||
3716 | /* Don't substitute into a non-local goto, this confuses CFG. */ | |
3717 | if (JUMP_P (insn) | |
3718 | && find_reg_note (insn, REG_NON_LOCAL_GOTO, NULL_RTX)) | |
3719 | continue; | |
3720 | ||
3721 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | |
3722 | { | |
3723 | if (REG_NOTE_KIND (link) == REG_DEAD | |
3724 | /* Make sure this insn still refers to the register. */ | |
3725 | && reg_mentioned_p (XEXP (link, 0), PATTERN (insn))) | |
3726 | { | |
3727 | int regno = REGNO (XEXP (link, 0)); | |
3728 | rtx equiv_insn; | |
3729 | ||
3730 | if (! reg_equiv[regno].replace | |
5ffa4e6a | 3731 | || reg_equiv[regno].loop_depth < (short) loop_depth |
f20f2613 VM |
3732 | /* There is no sense to move insns if live range |
3733 | shrinkage or register pressure-sensitive | |
3734 | scheduling were done because it will not | |
3735 | improve allocation but worsen insn schedule | |
3736 | with a big probability. */ | |
3737 | || flag_live_range_shrinkage | |
0cad4827 | 3738 | || (flag_sched_pressure && flag_schedule_insns)) |
2af2dbdc VM |
3739 | continue; |
3740 | ||
3741 | /* reg_equiv[REGNO].replace gets set only when | |
3742 | REG_N_REFS[REGNO] is 2, i.e. the register is set | |
55a2c322 VM |
3743 | once and used once. (If it were only set, but |
3744 | not used, flow would have deleted the setting | |
3745 | insns.) Hence there can only be one insn in | |
3746 | reg_equiv[REGNO].init_insns. */ | |
2af2dbdc VM |
3747 | gcc_assert (reg_equiv[regno].init_insns |
3748 | && !XEXP (reg_equiv[regno].init_insns, 1)); | |
3749 | equiv_insn = XEXP (reg_equiv[regno].init_insns, 0); | |
3750 | ||
3751 | /* We may not move instructions that can throw, since | |
3752 | that changes basic block boundaries and we are not | |
3753 | prepared to adjust the CFG to match. */ | |
3754 | if (can_throw_internal (equiv_insn)) | |
3755 | continue; | |
3756 | ||
3757 | if (asm_noperands (PATTERN (equiv_insn)) < 0 | |
3758 | && validate_replace_rtx (regno_reg_rtx[regno], | |
3759 | *(reg_equiv[regno].src_p), insn)) | |
3760 | { | |
3761 | rtx equiv_link; | |
3762 | rtx last_link; | |
3763 | rtx note; | |
3764 | ||
3765 | /* Find the last note. */ | |
3766 | for (last_link = link; XEXP (last_link, 1); | |
3767 | last_link = XEXP (last_link, 1)) | |
3768 | ; | |
3769 | ||
3770 | /* Append the REG_DEAD notes from equiv_insn. */ | |
3771 | equiv_link = REG_NOTES (equiv_insn); | |
3772 | while (equiv_link) | |
3773 | { | |
3774 | note = equiv_link; | |
3775 | equiv_link = XEXP (equiv_link, 1); | |
3776 | if (REG_NOTE_KIND (note) == REG_DEAD) | |
3777 | { | |
3778 | remove_note (equiv_insn, note); | |
3779 | XEXP (last_link, 1) = note; | |
3780 | XEXP (note, 1) = NULL_RTX; | |
3781 | last_link = note; | |
3782 | } | |
3783 | } | |
3784 | ||
3785 | remove_death (regno, insn); | |
3786 | SET_REG_N_REFS (regno, 0); | |
3787 | REG_FREQ (regno) = 0; | |
3788 | delete_insn (equiv_insn); | |
3789 | ||
3790 | reg_equiv[regno].init_insns | |
fb0ab697 | 3791 | = reg_equiv[regno].init_insns->next (); |
2af2dbdc | 3792 | |
0cc97fc5 | 3793 | ira_reg_equiv[regno].init_insns = NULL; |
2af2dbdc VM |
3794 | bitmap_set_bit (cleared_regs, regno); |
3795 | } | |
3796 | /* Move the initialization of the register to just before | |
3797 | INSN. Update the flow information. */ | |
b5b8b0ac | 3798 | else if (prev_nondebug_insn (insn) != equiv_insn) |
2af2dbdc | 3799 | { |
b2908ba6 | 3800 | rtx_insn *new_insn; |
2af2dbdc VM |
3801 | |
3802 | new_insn = emit_insn_before (PATTERN (equiv_insn), insn); | |
3803 | REG_NOTES (new_insn) = REG_NOTES (equiv_insn); | |
3804 | REG_NOTES (equiv_insn) = 0; | |
3805 | /* Rescan it to process the notes. */ | |
3806 | df_insn_rescan (new_insn); | |
3807 | ||
3808 | /* Make sure this insn is recognized before | |
3809 | reload begins, otherwise | |
3810 | eliminate_regs_in_insn will die. */ | |
3811 | INSN_CODE (new_insn) = INSN_CODE (equiv_insn); | |
3812 | ||
3813 | delete_insn (equiv_insn); | |
3814 | ||
3815 | XEXP (reg_equiv[regno].init_insns, 0) = new_insn; | |
3816 | ||
3817 | REG_BASIC_BLOCK (regno) = bb->index; | |
3818 | REG_N_CALLS_CROSSED (regno) = 0; | |
3819 | REG_FREQ_CALLS_CROSSED (regno) = 0; | |
3820 | REG_N_THROWING_CALLS_CROSSED (regno) = 0; | |
3821 | REG_LIVE_LENGTH (regno) = 2; | |
3822 | ||
3823 | if (insn == BB_HEAD (bb)) | |
1130d5e3 | 3824 | BB_HEAD (bb) = PREV_INSN (insn); |
2af2dbdc | 3825 | |
55a2c322 | 3826 | ira_reg_equiv[regno].init_insns |
2af2dbdc VM |
3827 | = gen_rtx_INSN_LIST (VOIDmode, new_insn, NULL_RTX); |
3828 | bitmap_set_bit (cleared_regs, regno); | |
3829 | } | |
3830 | } | |
3831 | } | |
3832 | } | |
3833 | } | |
3834 | ||
3835 | if (!bitmap_empty_p (cleared_regs)) | |
3a6191b1 | 3836 | { |
11cd3bed | 3837 | FOR_EACH_BB_FN (bb, cfun) |
3a6191b1 | 3838 | { |
3a6191b1 JJ |
3839 | bitmap_and_compl_into (DF_LR_IN (bb), cleared_regs); |
3840 | bitmap_and_compl_into (DF_LR_OUT (bb), cleared_regs); | |
bf744527 SB |
3841 | if (! df_live) |
3842 | continue; | |
3843 | bitmap_and_compl_into (DF_LIVE_IN (bb), cleared_regs); | |
3844 | bitmap_and_compl_into (DF_LIVE_OUT (bb), cleared_regs); | |
3a6191b1 JJ |
3845 | } |
3846 | ||
3847 | /* Last pass - adjust debug insns referencing cleared regs. */ | |
3848 | if (MAY_HAVE_DEBUG_INSNS) | |
3849 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
3850 | if (DEBUG_INSN_P (insn)) | |
3851 | { | |
3852 | rtx old_loc = INSN_VAR_LOCATION_LOC (insn); | |
3853 | INSN_VAR_LOCATION_LOC (insn) | |
3854 | = simplify_replace_fn_rtx (old_loc, NULL_RTX, | |
3855 | adjust_cleared_regs, | |
3856 | (void *) cleared_regs); | |
3857 | if (old_loc != INSN_VAR_LOCATION_LOC (insn)) | |
3858 | df_insn_rescan (insn); | |
3859 | } | |
3860 | } | |
2af2dbdc VM |
3861 | |
3862 | BITMAP_FREE (cleared_regs); | |
3863 | ||
3864 | out: | |
3865 | /* Clean up. */ | |
3866 | ||
3867 | end_alias_analysis (); | |
3868 | free (reg_equiv); | |
e3f9e0ac | 3869 | free (pdx_subregs); |
2af2dbdc VM |
3870 | return recorded_label_ref; |
3871 | } | |
3872 | ||
3873 | \f | |
3874 | ||
55a2c322 VM |
3875 | /* Set up fields memory, constant, and invariant from init_insns in |
3876 | the structures of array ira_reg_equiv. */ | |
3877 | static void | |
3878 | setup_reg_equiv (void) | |
3879 | { | |
3880 | int i; | |
0cc97fc5 DM |
3881 | rtx_insn_list *elem, *prev_elem, *next_elem; |
3882 | rtx_insn *insn; | |
3883 | rtx set, x; | |
55a2c322 VM |
3884 | |
3885 | for (i = FIRST_PSEUDO_REGISTER; i < ira_reg_equiv_len; i++) | |
5a107a0f VM |
3886 | for (prev_elem = NULL, elem = ira_reg_equiv[i].init_insns; |
3887 | elem; | |
3888 | prev_elem = elem, elem = next_elem) | |
55a2c322 | 3889 | { |
0cc97fc5 DM |
3890 | next_elem = elem->next (); |
3891 | insn = elem->insn (); | |
55a2c322 VM |
3892 | set = single_set (insn); |
3893 | ||
3894 | /* Init insns can set up equivalence when the reg is a destination or | |
3895 | a source (in this case the destination is memory). */ | |
3896 | if (set != 0 && (REG_P (SET_DEST (set)) || REG_P (SET_SRC (set)))) | |
3897 | { | |
3898 | if ((x = find_reg_note (insn, REG_EQUIV, NULL_RTX)) != NULL) | |
5a107a0f VM |
3899 | { |
3900 | x = XEXP (x, 0); | |
3901 | if (REG_P (SET_DEST (set)) | |
3902 | && REGNO (SET_DEST (set)) == (unsigned int) i | |
3903 | && ! rtx_equal_p (SET_SRC (set), x) && MEM_P (x)) | |
3904 | { | |
3905 | /* This insn reporting the equivalence but | |
3906 | actually not setting it. Remove it from the | |
3907 | list. */ | |
3908 | if (prev_elem == NULL) | |
3909 | ira_reg_equiv[i].init_insns = next_elem; | |
3910 | else | |
3911 | XEXP (prev_elem, 1) = next_elem; | |
3912 | elem = prev_elem; | |
3913 | } | |
3914 | } | |
55a2c322 VM |
3915 | else if (REG_P (SET_DEST (set)) |
3916 | && REGNO (SET_DEST (set)) == (unsigned int) i) | |
3917 | x = SET_SRC (set); | |
3918 | else | |
3919 | { | |
3920 | gcc_assert (REG_P (SET_SRC (set)) | |
3921 | && REGNO (SET_SRC (set)) == (unsigned int) i); | |
3922 | x = SET_DEST (set); | |
3923 | } | |
3924 | if (! function_invariant_p (x) | |
3925 | || ! flag_pic | |
3926 | /* A function invariant is often CONSTANT_P but may | |
3927 | include a register. We promise to only pass | |
3928 | CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */ | |
3929 | || (CONSTANT_P (x) && LEGITIMATE_PIC_OPERAND_P (x))) | |
3930 | { | |
3931 | /* It can happen that a REG_EQUIV note contains a MEM | |
3932 | that is not a legitimate memory operand. As later | |
3933 | stages of reload assume that all addresses found in | |
3934 | the lra_regno_equiv_* arrays were originally | |
3935 | legitimate, we ignore such REG_EQUIV notes. */ | |
3936 | if (memory_operand (x, VOIDmode)) | |
3937 | { | |
3938 | ira_reg_equiv[i].defined_p = true; | |
3939 | ira_reg_equiv[i].memory = x; | |
3940 | continue; | |
3941 | } | |
3942 | else if (function_invariant_p (x)) | |
3943 | { | |
ef4bddc2 | 3944 | machine_mode mode; |
55a2c322 VM |
3945 | |
3946 | mode = GET_MODE (SET_DEST (set)); | |
3947 | if (GET_CODE (x) == PLUS | |
3948 | || x == frame_pointer_rtx || x == arg_pointer_rtx) | |
3949 | /* This is PLUS of frame pointer and a constant, | |
3950 | or fp, or argp. */ | |
3951 | ira_reg_equiv[i].invariant = x; | |
3952 | else if (targetm.legitimate_constant_p (mode, x)) | |
3953 | ira_reg_equiv[i].constant = x; | |
3954 | else | |
3955 | { | |
3956 | ira_reg_equiv[i].memory = force_const_mem (mode, x); | |
3957 | if (ira_reg_equiv[i].memory == NULL_RTX) | |
3958 | { | |
3959 | ira_reg_equiv[i].defined_p = false; | |
0cc97fc5 | 3960 | ira_reg_equiv[i].init_insns = NULL; |
55a2c322 VM |
3961 | break; |
3962 | } | |
3963 | } | |
3964 | ira_reg_equiv[i].defined_p = true; | |
3965 | continue; | |
3966 | } | |
3967 | } | |
3968 | } | |
3969 | ira_reg_equiv[i].defined_p = false; | |
0cc97fc5 | 3970 | ira_reg_equiv[i].init_insns = NULL; |
55a2c322 VM |
3971 | break; |
3972 | } | |
3973 | } | |
3974 | ||
3975 | \f | |
3976 | ||
2af2dbdc VM |
3977 | /* Print chain C to FILE. */ |
3978 | static void | |
3979 | print_insn_chain (FILE *file, struct insn_chain *c) | |
3980 | { | |
c3284718 | 3981 | fprintf (file, "insn=%d, ", INSN_UID (c->insn)); |
2af2dbdc VM |
3982 | bitmap_print (file, &c->live_throughout, "live_throughout: ", ", "); |
3983 | bitmap_print (file, &c->dead_or_set, "dead_or_set: ", "\n"); | |
3984 | } | |
3985 | ||
3986 | ||
3987 | /* Print all reload_insn_chains to FILE. */ | |
3988 | static void | |
3989 | print_insn_chains (FILE *file) | |
3990 | { | |
3991 | struct insn_chain *c; | |
3992 | for (c = reload_insn_chain; c ; c = c->next) | |
3993 | print_insn_chain (file, c); | |
3994 | } | |
3995 | ||
3996 | /* Return true if pseudo REGNO should be added to set live_throughout | |
3997 | or dead_or_set of the insn chains for reload consideration. */ | |
3998 | static bool | |
3999 | pseudo_for_reload_consideration_p (int regno) | |
4000 | { | |
4001 | /* Consider spilled pseudos too for IRA because they still have a | |
4002 | chance to get hard-registers in the reload when IRA is used. */ | |
b100151b | 4003 | return (reg_renumber[regno] >= 0 || ira_conflicts_p); |
2af2dbdc VM |
4004 | } |
4005 | ||
4006 | /* Init LIVE_SUBREGS[ALLOCNUM] and LIVE_SUBREGS_USED[ALLOCNUM] using | |
4007 | REG to the number of nregs, and INIT_VALUE to get the | |
4008 | initialization. ALLOCNUM need not be the regno of REG. */ | |
4009 | static void | |
4010 | init_live_subregs (bool init_value, sbitmap *live_subregs, | |
cee784f5 | 4011 | bitmap live_subregs_used, int allocnum, rtx reg) |
2af2dbdc VM |
4012 | { |
4013 | unsigned int regno = REGNO (SUBREG_REG (reg)); | |
4014 | int size = GET_MODE_SIZE (GET_MODE (regno_reg_rtx[regno])); | |
4015 | ||
4016 | gcc_assert (size > 0); | |
4017 | ||
4018 | /* Been there, done that. */ | |
cee784f5 | 4019 | if (bitmap_bit_p (live_subregs_used, allocnum)) |
2af2dbdc VM |
4020 | return; |
4021 | ||
cee784f5 | 4022 | /* Create a new one. */ |
2af2dbdc VM |
4023 | if (live_subregs[allocnum] == NULL) |
4024 | live_subregs[allocnum] = sbitmap_alloc (size); | |
4025 | ||
4026 | /* If the entire reg was live before blasting into subregs, we need | |
4027 | to init all of the subregs to ones else init to 0. */ | |
4028 | if (init_value) | |
f61e445a | 4029 | bitmap_ones (live_subregs[allocnum]); |
b8698a0f | 4030 | else |
f61e445a | 4031 | bitmap_clear (live_subregs[allocnum]); |
2af2dbdc | 4032 | |
cee784f5 | 4033 | bitmap_set_bit (live_subregs_used, allocnum); |
2af2dbdc VM |
4034 | } |
4035 | ||
4036 | /* Walk the insns of the current function and build reload_insn_chain, | |
4037 | and record register life information. */ | |
4038 | static void | |
4039 | build_insn_chain (void) | |
4040 | { | |
4041 | unsigned int i; | |
4042 | struct insn_chain **p = &reload_insn_chain; | |
4043 | basic_block bb; | |
4044 | struct insn_chain *c = NULL; | |
4045 | struct insn_chain *next = NULL; | |
4046 | bitmap live_relevant_regs = BITMAP_ALLOC (NULL); | |
4047 | bitmap elim_regset = BITMAP_ALLOC (NULL); | |
4048 | /* live_subregs is a vector used to keep accurate information about | |
4049 | which hardregs are live in multiword pseudos. live_subregs and | |
4050 | live_subregs_used are indexed by pseudo number. The live_subreg | |
4051 | entry for a particular pseudo is only used if the corresponding | |
cee784f5 SB |
4052 | element is non zero in live_subregs_used. The sbitmap size of |
4053 | live_subreg[allocno] is number of bytes that the pseudo can | |
2af2dbdc VM |
4054 | occupy. */ |
4055 | sbitmap *live_subregs = XCNEWVEC (sbitmap, max_regno); | |
cee784f5 | 4056 | bitmap live_subregs_used = BITMAP_ALLOC (NULL); |
2af2dbdc VM |
4057 | |
4058 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
4059 | if (TEST_HARD_REG_BIT (eliminable_regset, i)) | |
4060 | bitmap_set_bit (elim_regset, i); | |
4f42035e | 4061 | FOR_EACH_BB_REVERSE_FN (bb, cfun) |
2af2dbdc VM |
4062 | { |
4063 | bitmap_iterator bi; | |
070a1983 | 4064 | rtx_insn *insn; |
b8698a0f | 4065 | |
2af2dbdc | 4066 | CLEAR_REG_SET (live_relevant_regs); |
cee784f5 | 4067 | bitmap_clear (live_subregs_used); |
b8698a0f | 4068 | |
bf744527 | 4069 | EXECUTE_IF_SET_IN_BITMAP (df_get_live_out (bb), 0, i, bi) |
2af2dbdc VM |
4070 | { |
4071 | if (i >= FIRST_PSEUDO_REGISTER) | |
4072 | break; | |
4073 | bitmap_set_bit (live_relevant_regs, i); | |
4074 | } | |
4075 | ||
bf744527 | 4076 | EXECUTE_IF_SET_IN_BITMAP (df_get_live_out (bb), |
2af2dbdc VM |
4077 | FIRST_PSEUDO_REGISTER, i, bi) |
4078 | { | |
4079 | if (pseudo_for_reload_consideration_p (i)) | |
4080 | bitmap_set_bit (live_relevant_regs, i); | |
4081 | } | |
4082 | ||
4083 | FOR_BB_INSNS_REVERSE (bb, insn) | |
4084 | { | |
4085 | if (!NOTE_P (insn) && !BARRIER_P (insn)) | |
4086 | { | |
bfac633a RS |
4087 | struct df_insn_info *insn_info = DF_INSN_INFO_GET (insn); |
4088 | df_ref def, use; | |
2af2dbdc VM |
4089 | |
4090 | c = new_insn_chain (); | |
4091 | c->next = next; | |
4092 | next = c; | |
4093 | *p = c; | |
4094 | p = &c->prev; | |
b8698a0f | 4095 | |
2af2dbdc VM |
4096 | c->insn = insn; |
4097 | c->block = bb->index; | |
4098 | ||
4b71920a | 4099 | if (NONDEBUG_INSN_P (insn)) |
bfac633a | 4100 | FOR_EACH_INSN_INFO_DEF (def, insn_info) |
2af2dbdc | 4101 | { |
2af2dbdc | 4102 | unsigned int regno = DF_REF_REGNO (def); |
b8698a0f | 4103 | |
2af2dbdc VM |
4104 | /* Ignore may clobbers because these are generated |
4105 | from calls. However, every other kind of def is | |
4106 | added to dead_or_set. */ | |
4107 | if (!DF_REF_FLAGS_IS_SET (def, DF_REF_MAY_CLOBBER)) | |
4108 | { | |
4109 | if (regno < FIRST_PSEUDO_REGISTER) | |
4110 | { | |
4111 | if (!fixed_regs[regno]) | |
4112 | bitmap_set_bit (&c->dead_or_set, regno); | |
4113 | } | |
4114 | else if (pseudo_for_reload_consideration_p (regno)) | |
4115 | bitmap_set_bit (&c->dead_or_set, regno); | |
4116 | } | |
4117 | ||
4118 | if ((regno < FIRST_PSEUDO_REGISTER | |
4119 | || reg_renumber[regno] >= 0 | |
4120 | || ira_conflicts_p) | |
4121 | && (!DF_REF_FLAGS_IS_SET (def, DF_REF_CONDITIONAL))) | |
4122 | { | |
4123 | rtx reg = DF_REF_REG (def); | |
4124 | ||
4125 | /* We can model subregs, but not if they are | |
4126 | wrapped in ZERO_EXTRACTS. */ | |
4127 | if (GET_CODE (reg) == SUBREG | |
4128 | && !DF_REF_FLAGS_IS_SET (def, DF_REF_ZERO_EXTRACT)) | |
4129 | { | |
4130 | unsigned int start = SUBREG_BYTE (reg); | |
b8698a0f | 4131 | unsigned int last = start |
2af2dbdc VM |
4132 | + GET_MODE_SIZE (GET_MODE (reg)); |
4133 | ||
4134 | init_live_subregs | |
b8698a0f | 4135 | (bitmap_bit_p (live_relevant_regs, regno), |
2af2dbdc VM |
4136 | live_subregs, live_subregs_used, regno, reg); |
4137 | ||
4138 | if (!DF_REF_FLAGS_IS_SET | |
4139 | (def, DF_REF_STRICT_LOW_PART)) | |
4140 | { | |
4141 | /* Expand the range to cover entire words. | |
4142 | Bytes added here are "don't care". */ | |
4143 | start | |
4144 | = start / UNITS_PER_WORD * UNITS_PER_WORD; | |
4145 | last = ((last + UNITS_PER_WORD - 1) | |
4146 | / UNITS_PER_WORD * UNITS_PER_WORD); | |
4147 | } | |
4148 | ||
4149 | /* Ignore the paradoxical bits. */ | |
cee784f5 SB |
4150 | if (last > SBITMAP_SIZE (live_subregs[regno])) |
4151 | last = SBITMAP_SIZE (live_subregs[regno]); | |
2af2dbdc VM |
4152 | |
4153 | while (start < last) | |
4154 | { | |
d7c028c0 | 4155 | bitmap_clear_bit (live_subregs[regno], start); |
2af2dbdc VM |
4156 | start++; |
4157 | } | |
b8698a0f | 4158 | |
f61e445a | 4159 | if (bitmap_empty_p (live_subregs[regno])) |
2af2dbdc | 4160 | { |
cee784f5 | 4161 | bitmap_clear_bit (live_subregs_used, regno); |
2af2dbdc VM |
4162 | bitmap_clear_bit (live_relevant_regs, regno); |
4163 | } | |
4164 | else | |
4165 | /* Set live_relevant_regs here because | |
4166 | that bit has to be true to get us to | |
4167 | look at the live_subregs fields. */ | |
4168 | bitmap_set_bit (live_relevant_regs, regno); | |
4169 | } | |
4170 | else | |
4171 | { | |
4172 | /* DF_REF_PARTIAL is generated for | |
4173 | subregs, STRICT_LOW_PART, and | |
4174 | ZERO_EXTRACT. We handle the subreg | |
4175 | case above so here we have to keep from | |
4176 | modeling the def as a killing def. */ | |
4177 | if (!DF_REF_FLAGS_IS_SET (def, DF_REF_PARTIAL)) | |
4178 | { | |
cee784f5 | 4179 | bitmap_clear_bit (live_subregs_used, regno); |
2af2dbdc | 4180 | bitmap_clear_bit (live_relevant_regs, regno); |
2af2dbdc VM |
4181 | } |
4182 | } | |
4183 | } | |
4184 | } | |
b8698a0f | 4185 | |
2af2dbdc VM |
4186 | bitmap_and_compl_into (live_relevant_regs, elim_regset); |
4187 | bitmap_copy (&c->live_throughout, live_relevant_regs); | |
4188 | ||
4b71920a | 4189 | if (NONDEBUG_INSN_P (insn)) |
bfac633a | 4190 | FOR_EACH_INSN_INFO_USE (use, insn_info) |
2af2dbdc | 4191 | { |
2af2dbdc VM |
4192 | unsigned int regno = DF_REF_REGNO (use); |
4193 | rtx reg = DF_REF_REG (use); | |
b8698a0f | 4194 | |
2af2dbdc VM |
4195 | /* DF_REF_READ_WRITE on a use means that this use |
4196 | is fabricated from a def that is a partial set | |
4197 | to a multiword reg. Here, we only model the | |
4198 | subreg case that is not wrapped in ZERO_EXTRACT | |
4199 | precisely so we do not need to look at the | |
2b9c63a2 | 4200 | fabricated use. */ |
b8698a0f L |
4201 | if (DF_REF_FLAGS_IS_SET (use, DF_REF_READ_WRITE) |
4202 | && !DF_REF_FLAGS_IS_SET (use, DF_REF_ZERO_EXTRACT) | |
2af2dbdc VM |
4203 | && DF_REF_FLAGS_IS_SET (use, DF_REF_SUBREG)) |
4204 | continue; | |
b8698a0f | 4205 | |
2af2dbdc VM |
4206 | /* Add the last use of each var to dead_or_set. */ |
4207 | if (!bitmap_bit_p (live_relevant_regs, regno)) | |
4208 | { | |
4209 | if (regno < FIRST_PSEUDO_REGISTER) | |
4210 | { | |
4211 | if (!fixed_regs[regno]) | |
4212 | bitmap_set_bit (&c->dead_or_set, regno); | |
4213 | } | |
4214 | else if (pseudo_for_reload_consideration_p (regno)) | |
4215 | bitmap_set_bit (&c->dead_or_set, regno); | |
4216 | } | |
b8698a0f | 4217 | |
2af2dbdc VM |
4218 | if (regno < FIRST_PSEUDO_REGISTER |
4219 | || pseudo_for_reload_consideration_p (regno)) | |
4220 | { | |
4221 | if (GET_CODE (reg) == SUBREG | |
4222 | && !DF_REF_FLAGS_IS_SET (use, | |
4223 | DF_REF_SIGN_EXTRACT | |
b8698a0f | 4224 | | DF_REF_ZERO_EXTRACT)) |
2af2dbdc VM |
4225 | { |
4226 | unsigned int start = SUBREG_BYTE (reg); | |
b8698a0f | 4227 | unsigned int last = start |
2af2dbdc | 4228 | + GET_MODE_SIZE (GET_MODE (reg)); |
b8698a0f | 4229 | |
2af2dbdc | 4230 | init_live_subregs |
b8698a0f | 4231 | (bitmap_bit_p (live_relevant_regs, regno), |
2af2dbdc | 4232 | live_subregs, live_subregs_used, regno, reg); |
b8698a0f | 4233 | |
2af2dbdc | 4234 | /* Ignore the paradoxical bits. */ |
cee784f5 SB |
4235 | if (last > SBITMAP_SIZE (live_subregs[regno])) |
4236 | last = SBITMAP_SIZE (live_subregs[regno]); | |
2af2dbdc VM |
4237 | |
4238 | while (start < last) | |
4239 | { | |
d7c028c0 | 4240 | bitmap_set_bit (live_subregs[regno], start); |
2af2dbdc VM |
4241 | start++; |
4242 | } | |
4243 | } | |
4244 | else | |
4245 | /* Resetting the live_subregs_used is | |
4246 | effectively saying do not use the subregs | |
4247 | because we are reading the whole | |
4248 | pseudo. */ | |
cee784f5 | 4249 | bitmap_clear_bit (live_subregs_used, regno); |
2af2dbdc VM |
4250 | bitmap_set_bit (live_relevant_regs, regno); |
4251 | } | |
4252 | } | |
4253 | } | |
4254 | } | |
4255 | ||
4256 | /* FIXME!! The following code is a disaster. Reload needs to see the | |
4257 | labels and jump tables that are just hanging out in between | |
4258 | the basic blocks. See pr33676. */ | |
4259 | insn = BB_HEAD (bb); | |
b8698a0f | 4260 | |
2af2dbdc | 4261 | /* Skip over the barriers and cruft. */ |
b8698a0f | 4262 | while (insn && (BARRIER_P (insn) || NOTE_P (insn) |
2af2dbdc VM |
4263 | || BLOCK_FOR_INSN (insn) == bb)) |
4264 | insn = PREV_INSN (insn); | |
b8698a0f | 4265 | |
2af2dbdc VM |
4266 | /* While we add anything except barriers and notes, the focus is |
4267 | to get the labels and jump tables into the | |
4268 | reload_insn_chain. */ | |
4269 | while (insn) | |
4270 | { | |
4271 | if (!NOTE_P (insn) && !BARRIER_P (insn)) | |
4272 | { | |
4273 | if (BLOCK_FOR_INSN (insn)) | |
4274 | break; | |
b8698a0f | 4275 | |
2af2dbdc VM |
4276 | c = new_insn_chain (); |
4277 | c->next = next; | |
4278 | next = c; | |
4279 | *p = c; | |
4280 | p = &c->prev; | |
b8698a0f | 4281 | |
2af2dbdc VM |
4282 | /* The block makes no sense here, but it is what the old |
4283 | code did. */ | |
4284 | c->block = bb->index; | |
4285 | c->insn = insn; | |
4286 | bitmap_copy (&c->live_throughout, live_relevant_regs); | |
b8698a0f | 4287 | } |
2af2dbdc VM |
4288 | insn = PREV_INSN (insn); |
4289 | } | |
4290 | } | |
4291 | ||
2af2dbdc VM |
4292 | reload_insn_chain = c; |
4293 | *p = NULL; | |
4294 | ||
cee784f5 SB |
4295 | for (i = 0; i < (unsigned int) max_regno; i++) |
4296 | if (live_subregs[i] != NULL) | |
4297 | sbitmap_free (live_subregs[i]); | |
2af2dbdc | 4298 | free (live_subregs); |
cee784f5 | 4299 | BITMAP_FREE (live_subregs_used); |
2af2dbdc VM |
4300 | BITMAP_FREE (live_relevant_regs); |
4301 | BITMAP_FREE (elim_regset); | |
4302 | ||
4303 | if (dump_file) | |
4304 | print_insn_chains (dump_file); | |
4305 | } | |
acf41a74 BS |
4306 | \f |
4307 | /* Examine the rtx found in *LOC, which is read or written to as determined | |
4308 | by TYPE. Return false if we find a reason why an insn containing this | |
4309 | rtx should not be moved (such as accesses to non-constant memory), true | |
4310 | otherwise. */ | |
4311 | static bool | |
4312 | rtx_moveable_p (rtx *loc, enum op_type type) | |
4313 | { | |
4314 | const char *fmt; | |
4315 | rtx x = *loc; | |
4316 | enum rtx_code code = GET_CODE (x); | |
4317 | int i, j; | |
4318 | ||
4319 | code = GET_CODE (x); | |
4320 | switch (code) | |
4321 | { | |
4322 | case CONST: | |
d8116890 | 4323 | CASE_CONST_ANY: |
acf41a74 BS |
4324 | case SYMBOL_REF: |
4325 | case LABEL_REF: | |
4326 | return true; | |
4327 | ||
4328 | case PC: | |
4329 | return type == OP_IN; | |
4330 | ||
4331 | case CC0: | |
4332 | return false; | |
4333 | ||
4334 | case REG: | |
4335 | if (x == frame_pointer_rtx) | |
4336 | return true; | |
4337 | if (HARD_REGISTER_P (x)) | |
4338 | return false; | |
4339 | ||
4340 | return true; | |
4341 | ||
4342 | case MEM: | |
4343 | if (type == OP_IN && MEM_READONLY_P (x)) | |
4344 | return rtx_moveable_p (&XEXP (x, 0), OP_IN); | |
4345 | return false; | |
4346 | ||
4347 | case SET: | |
4348 | return (rtx_moveable_p (&SET_SRC (x), OP_IN) | |
4349 | && rtx_moveable_p (&SET_DEST (x), OP_OUT)); | |
4350 | ||
4351 | case STRICT_LOW_PART: | |
4352 | return rtx_moveable_p (&XEXP (x, 0), OP_OUT); | |
4353 | ||
4354 | case ZERO_EXTRACT: | |
4355 | case SIGN_EXTRACT: | |
4356 | return (rtx_moveable_p (&XEXP (x, 0), type) | |
4357 | && rtx_moveable_p (&XEXP (x, 1), OP_IN) | |
4358 | && rtx_moveable_p (&XEXP (x, 2), OP_IN)); | |
4359 | ||
4360 | case CLOBBER: | |
4361 | return rtx_moveable_p (&SET_DEST (x), OP_OUT); | |
4362 | ||
d8c16744 VM |
4363 | case UNSPEC_VOLATILE: |
4364 | /* It is a bad idea to consider insns with with such rtl | |
4365 | as moveable ones. The insn scheduler also considers them as barrier | |
4366 | for a reason. */ | |
4367 | return false; | |
4368 | ||
acf41a74 BS |
4369 | default: |
4370 | break; | |
4371 | } | |
4372 | ||
4373 | fmt = GET_RTX_FORMAT (code); | |
4374 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
4375 | { | |
4376 | if (fmt[i] == 'e') | |
4377 | { | |
4378 | if (!rtx_moveable_p (&XEXP (x, i), type)) | |
4379 | return false; | |
4380 | } | |
4381 | else if (fmt[i] == 'E') | |
4382 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
4383 | { | |
4384 | if (!rtx_moveable_p (&XVECEXP (x, i, j), type)) | |
4385 | return false; | |
4386 | } | |
4387 | } | |
4388 | return true; | |
4389 | } | |
4390 | ||
4391 | /* A wrapper around dominated_by_p, which uses the information in UID_LUID | |
4392 | to give dominance relationships between two insns I1 and I2. */ | |
4393 | static bool | |
4394 | insn_dominated_by_p (rtx i1, rtx i2, int *uid_luid) | |
4395 | { | |
4396 | basic_block bb1 = BLOCK_FOR_INSN (i1); | |
4397 | basic_block bb2 = BLOCK_FOR_INSN (i2); | |
4398 | ||
4399 | if (bb1 == bb2) | |
4400 | return uid_luid[INSN_UID (i2)] < uid_luid[INSN_UID (i1)]; | |
4401 | return dominated_by_p (CDI_DOMINATORS, bb1, bb2); | |
4402 | } | |
4403 | ||
4404 | /* Record the range of register numbers added by find_moveable_pseudos. */ | |
4405 | int first_moveable_pseudo, last_moveable_pseudo; | |
4406 | ||
4407 | /* These two vectors hold data for every register added by | |
4408 | find_movable_pseudos, with index 0 holding data for the | |
4409 | first_moveable_pseudo. */ | |
4410 | /* The original home register. */ | |
9771b263 | 4411 | static vec<rtx> pseudo_replaced_reg; |
acf41a74 BS |
4412 | |
4413 | /* Look for instances where we have an instruction that is known to increase | |
4414 | register pressure, and whose result is not used immediately. If it is | |
4415 | possible to move the instruction downwards to just before its first use, | |
4416 | split its lifetime into two ranges. We create a new pseudo to compute the | |
4417 | value, and emit a move instruction just before the first use. If, after | |
4418 | register allocation, the new pseudo remains unallocated, the function | |
4419 | move_unallocated_pseudos then deletes the move instruction and places | |
4420 | the computation just before the first use. | |
4421 | ||
4422 | Such a move is safe and profitable if all the input registers remain live | |
4423 | and unchanged between the original computation and its first use. In such | |
4424 | a situation, the computation is known to increase register pressure, and | |
4425 | moving it is known to at least not worsen it. | |
4426 | ||
4427 | We restrict moves to only those cases where a register remains unallocated, | |
4428 | in order to avoid interfering too much with the instruction schedule. As | |
4429 | an exception, we may move insns which only modify their input register | |
4430 | (typically induction variables), as this increases the freedom for our | |
4431 | intended transformation, and does not limit the second instruction | |
4432 | scheduler pass. */ | |
4433 | ||
4434 | static void | |
4435 | find_moveable_pseudos (void) | |
4436 | { | |
4437 | unsigned i; | |
4438 | int max_regs = max_reg_num (); | |
4439 | int max_uid = get_max_uid (); | |
4440 | basic_block bb; | |
4441 | int *uid_luid = XNEWVEC (int, max_uid); | |
070a1983 | 4442 | rtx_insn **closest_uses = XNEWVEC (rtx_insn *, max_regs); |
acf41a74 | 4443 | /* A set of registers which are live but not modified throughout a block. */ |
8b1c6fd7 DM |
4444 | bitmap_head *bb_transp_live = XNEWVEC (bitmap_head, |
4445 | last_basic_block_for_fn (cfun)); | |
acf41a74 | 4446 | /* A set of registers which only exist in a given basic block. */ |
8b1c6fd7 DM |
4447 | bitmap_head *bb_local = XNEWVEC (bitmap_head, |
4448 | last_basic_block_for_fn (cfun)); | |
acf41a74 BS |
4449 | /* A set of registers which are set once, in an instruction that can be |
4450 | moved freely downwards, but are otherwise transparent to a block. */ | |
8b1c6fd7 DM |
4451 | bitmap_head *bb_moveable_reg_sets = XNEWVEC (bitmap_head, |
4452 | last_basic_block_for_fn (cfun)); | |
acf41a74 BS |
4453 | bitmap_head live, used, set, interesting, unusable_as_input; |
4454 | bitmap_iterator bi; | |
4455 | bitmap_initialize (&interesting, 0); | |
4456 | ||
4457 | first_moveable_pseudo = max_regs; | |
9771b263 DN |
4458 | pseudo_replaced_reg.release (); |
4459 | pseudo_replaced_reg.safe_grow_cleared (max_regs); | |
acf41a74 | 4460 | |
2d73cc45 MJ |
4461 | df_analyze (); |
4462 | calculate_dominance_info (CDI_DOMINATORS); | |
4463 | ||
acf41a74 BS |
4464 | i = 0; |
4465 | bitmap_initialize (&live, 0); | |
4466 | bitmap_initialize (&used, 0); | |
4467 | bitmap_initialize (&set, 0); | |
4468 | bitmap_initialize (&unusable_as_input, 0); | |
11cd3bed | 4469 | FOR_EACH_BB_FN (bb, cfun) |
acf41a74 | 4470 | { |
070a1983 | 4471 | rtx_insn *insn; |
acf41a74 BS |
4472 | bitmap transp = bb_transp_live + bb->index; |
4473 | bitmap moveable = bb_moveable_reg_sets + bb->index; | |
4474 | bitmap local = bb_local + bb->index; | |
4475 | ||
4476 | bitmap_initialize (local, 0); | |
4477 | bitmap_initialize (transp, 0); | |
4478 | bitmap_initialize (moveable, 0); | |
4479 | bitmap_copy (&live, df_get_live_out (bb)); | |
4480 | bitmap_and_into (&live, df_get_live_in (bb)); | |
4481 | bitmap_copy (transp, &live); | |
4482 | bitmap_clear (moveable); | |
4483 | bitmap_clear (&live); | |
4484 | bitmap_clear (&used); | |
4485 | bitmap_clear (&set); | |
4486 | FOR_BB_INSNS (bb, insn) | |
4487 | if (NONDEBUG_INSN_P (insn)) | |
4488 | { | |
bfac633a | 4489 | df_insn_info *insn_info = DF_INSN_INFO_GET (insn); |
bfac633a | 4490 | df_ref def, use; |
acf41a74 BS |
4491 | |
4492 | uid_luid[INSN_UID (insn)] = i++; | |
4493 | ||
74e59b6c RS |
4494 | def = df_single_def (insn_info); |
4495 | use = df_single_use (insn_info); | |
4496 | if (use | |
4497 | && def | |
4498 | && DF_REF_REGNO (use) == DF_REF_REGNO (def) | |
4499 | && !bitmap_bit_p (&set, DF_REF_REGNO (use)) | |
acf41a74 BS |
4500 | && rtx_moveable_p (&PATTERN (insn), OP_IN)) |
4501 | { | |
74e59b6c | 4502 | unsigned regno = DF_REF_REGNO (use); |
acf41a74 BS |
4503 | bitmap_set_bit (moveable, regno); |
4504 | bitmap_set_bit (&set, regno); | |
4505 | bitmap_set_bit (&used, regno); | |
4506 | bitmap_clear_bit (transp, regno); | |
4507 | continue; | |
4508 | } | |
bfac633a | 4509 | FOR_EACH_INSN_INFO_USE (use, insn_info) |
acf41a74 | 4510 | { |
bfac633a | 4511 | unsigned regno = DF_REF_REGNO (use); |
acf41a74 BS |
4512 | bitmap_set_bit (&used, regno); |
4513 | if (bitmap_clear_bit (moveable, regno)) | |
4514 | bitmap_clear_bit (transp, regno); | |
acf41a74 BS |
4515 | } |
4516 | ||
bfac633a | 4517 | FOR_EACH_INSN_INFO_DEF (def, insn_info) |
acf41a74 | 4518 | { |
bfac633a | 4519 | unsigned regno = DF_REF_REGNO (def); |
acf41a74 BS |
4520 | bitmap_set_bit (&set, regno); |
4521 | bitmap_clear_bit (transp, regno); | |
4522 | bitmap_clear_bit (moveable, regno); | |
acf41a74 BS |
4523 | } |
4524 | } | |
4525 | } | |
4526 | ||
4527 | bitmap_clear (&live); | |
4528 | bitmap_clear (&used); | |
4529 | bitmap_clear (&set); | |
4530 | ||
11cd3bed | 4531 | FOR_EACH_BB_FN (bb, cfun) |
acf41a74 BS |
4532 | { |
4533 | bitmap local = bb_local + bb->index; | |
070a1983 | 4534 | rtx_insn *insn; |
acf41a74 BS |
4535 | |
4536 | FOR_BB_INSNS (bb, insn) | |
4537 | if (NONDEBUG_INSN_P (insn)) | |
4538 | { | |
74e59b6c | 4539 | df_insn_info *insn_info = DF_INSN_INFO_GET (insn); |
070a1983 DM |
4540 | rtx_insn *def_insn; |
4541 | rtx closest_use, note; | |
74e59b6c | 4542 | df_ref def, use; |
acf41a74 BS |
4543 | unsigned regno; |
4544 | bool all_dominated, all_local; | |
ef4bddc2 | 4545 | machine_mode mode; |
acf41a74 | 4546 | |
74e59b6c | 4547 | def = df_single_def (insn_info); |
acf41a74 | 4548 | /* There must be exactly one def in this insn. */ |
74e59b6c | 4549 | if (!def || !single_set (insn)) |
acf41a74 BS |
4550 | continue; |
4551 | /* This must be the only definition of the reg. We also limit | |
4552 | which modes we deal with so that we can assume we can generate | |
4553 | move instructions. */ | |
4554 | regno = DF_REF_REGNO (def); | |
4555 | mode = GET_MODE (DF_REF_REG (def)); | |
4556 | if (DF_REG_DEF_COUNT (regno) != 1 | |
4557 | || !DF_REF_INSN_INFO (def) | |
4558 | || HARD_REGISTER_NUM_P (regno) | |
aa44c80c | 4559 | || DF_REG_EQ_USE_COUNT (regno) > 0 |
acf41a74 BS |
4560 | || (!INTEGRAL_MODE_P (mode) && !FLOAT_MODE_P (mode))) |
4561 | continue; | |
4562 | def_insn = DF_REF_INSN (def); | |
4563 | ||
4564 | for (note = REG_NOTES (def_insn); note; note = XEXP (note, 1)) | |
4565 | if (REG_NOTE_KIND (note) == REG_EQUIV && MEM_P (XEXP (note, 0))) | |
4566 | break; | |
4567 | ||
4568 | if (note) | |
4569 | { | |
4570 | if (dump_file) | |
4571 | fprintf (dump_file, "Ignoring reg %d, has equiv memory\n", | |
4572 | regno); | |
4573 | bitmap_set_bit (&unusable_as_input, regno); | |
4574 | continue; | |
4575 | } | |
4576 | ||
4577 | use = DF_REG_USE_CHAIN (regno); | |
4578 | all_dominated = true; | |
4579 | all_local = true; | |
4580 | closest_use = NULL_RTX; | |
4581 | for (; use; use = DF_REF_NEXT_REG (use)) | |
4582 | { | |
070a1983 | 4583 | rtx_insn *insn; |
acf41a74 BS |
4584 | if (!DF_REF_INSN_INFO (use)) |
4585 | { | |
4586 | all_dominated = false; | |
4587 | all_local = false; | |
4588 | break; | |
4589 | } | |
4590 | insn = DF_REF_INSN (use); | |
4591 | if (DEBUG_INSN_P (insn)) | |
4592 | continue; | |
4593 | if (BLOCK_FOR_INSN (insn) != BLOCK_FOR_INSN (def_insn)) | |
4594 | all_local = false; | |
4595 | if (!insn_dominated_by_p (insn, def_insn, uid_luid)) | |
4596 | all_dominated = false; | |
4597 | if (closest_use != insn && closest_use != const0_rtx) | |
4598 | { | |
4599 | if (closest_use == NULL_RTX) | |
4600 | closest_use = insn; | |
4601 | else if (insn_dominated_by_p (closest_use, insn, uid_luid)) | |
4602 | closest_use = insn; | |
4603 | else if (!insn_dominated_by_p (insn, closest_use, uid_luid)) | |
4604 | closest_use = const0_rtx; | |
4605 | } | |
4606 | } | |
4607 | if (!all_dominated) | |
4608 | { | |
4609 | if (dump_file) | |
4610 | fprintf (dump_file, "Reg %d not all uses dominated by set\n", | |
4611 | regno); | |
4612 | continue; | |
4613 | } | |
4614 | if (all_local) | |
4615 | bitmap_set_bit (local, regno); | |
4616 | if (closest_use == const0_rtx || closest_use == NULL | |
4617 | || next_nonnote_nondebug_insn (def_insn) == closest_use) | |
4618 | { | |
4619 | if (dump_file) | |
4620 | fprintf (dump_file, "Reg %d uninteresting%s\n", regno, | |
4621 | closest_use == const0_rtx || closest_use == NULL | |
4622 | ? " (no unique first use)" : ""); | |
4623 | continue; | |
4624 | } | |
058eb3b0 | 4625 | if (HAVE_cc0 && reg_referenced_p (cc0_rtx, PATTERN (closest_use))) |
acf41a74 BS |
4626 | { |
4627 | if (dump_file) | |
4628 | fprintf (dump_file, "Reg %d: closest user uses cc0\n", | |
4629 | regno); | |
4630 | continue; | |
4631 | } | |
058eb3b0 | 4632 | |
acf41a74 | 4633 | bitmap_set_bit (&interesting, regno); |
070a1983 DM |
4634 | /* If we get here, we know closest_use is a non-NULL insn |
4635 | (as opposed to const_0_rtx). */ | |
4636 | closest_uses[regno] = as_a <rtx_insn *> (closest_use); | |
acf41a74 BS |
4637 | |
4638 | if (dump_file && (all_local || all_dominated)) | |
4639 | { | |
4640 | fprintf (dump_file, "Reg %u:", regno); | |
4641 | if (all_local) | |
4642 | fprintf (dump_file, " local to bb %d", bb->index); | |
4643 | if (all_dominated) | |
4644 | fprintf (dump_file, " def dominates all uses"); | |
4645 | if (closest_use != const0_rtx) | |
4646 | fprintf (dump_file, " has unique first use"); | |
4647 | fputs ("\n", dump_file); | |
4648 | } | |
4649 | } | |
4650 | } | |
4651 | ||
4652 | EXECUTE_IF_SET_IN_BITMAP (&interesting, 0, i, bi) | |
4653 | { | |
4654 | df_ref def = DF_REG_DEF_CHAIN (i); | |
070a1983 | 4655 | rtx_insn *def_insn = DF_REF_INSN (def); |
acf41a74 BS |
4656 | basic_block def_block = BLOCK_FOR_INSN (def_insn); |
4657 | bitmap def_bb_local = bb_local + def_block->index; | |
4658 | bitmap def_bb_moveable = bb_moveable_reg_sets + def_block->index; | |
4659 | bitmap def_bb_transp = bb_transp_live + def_block->index; | |
4660 | bool local_to_bb_p = bitmap_bit_p (def_bb_local, i); | |
070a1983 | 4661 | rtx_insn *use_insn = closest_uses[i]; |
bfac633a | 4662 | df_ref use; |
acf41a74 BS |
4663 | bool all_ok = true; |
4664 | bool all_transp = true; | |
4665 | ||
4666 | if (!REG_P (DF_REF_REG (def))) | |
4667 | continue; | |
4668 | ||
4669 | if (!local_to_bb_p) | |
4670 | { | |
4671 | if (dump_file) | |
4672 | fprintf (dump_file, "Reg %u not local to one basic block\n", | |
4673 | i); | |
4674 | continue; | |
4675 | } | |
4676 | if (reg_equiv_init (i) != NULL_RTX) | |
4677 | { | |
4678 | if (dump_file) | |
4679 | fprintf (dump_file, "Ignoring reg %u with equiv init insn\n", | |
4680 | i); | |
4681 | continue; | |
4682 | } | |
4683 | if (!rtx_moveable_p (&PATTERN (def_insn), OP_IN)) | |
4684 | { | |
4685 | if (dump_file) | |
4686 | fprintf (dump_file, "Found def insn %d for %d to be not moveable\n", | |
4687 | INSN_UID (def_insn), i); | |
4688 | continue; | |
4689 | } | |
4690 | if (dump_file) | |
4691 | fprintf (dump_file, "Examining insn %d, def for %d\n", | |
4692 | INSN_UID (def_insn), i); | |
bfac633a | 4693 | FOR_EACH_INSN_USE (use, def_insn) |
acf41a74 | 4694 | { |
acf41a74 BS |
4695 | unsigned regno = DF_REF_REGNO (use); |
4696 | if (bitmap_bit_p (&unusable_as_input, regno)) | |
4697 | { | |
4698 | all_ok = false; | |
4699 | if (dump_file) | |
4700 | fprintf (dump_file, " found unusable input reg %u.\n", regno); | |
4701 | break; | |
4702 | } | |
4703 | if (!bitmap_bit_p (def_bb_transp, regno)) | |
4704 | { | |
4705 | if (bitmap_bit_p (def_bb_moveable, regno) | |
4706 | && !control_flow_insn_p (use_insn) | |
618f4073 | 4707 | && (!HAVE_cc0 || !sets_cc0_p (use_insn))) |
acf41a74 BS |
4708 | { |
4709 | if (modified_between_p (DF_REF_REG (use), def_insn, use_insn)) | |
4710 | { | |
070a1983 | 4711 | rtx_insn *x = NEXT_INSN (def_insn); |
acf41a74 BS |
4712 | while (!modified_in_p (DF_REF_REG (use), x)) |
4713 | { | |
4714 | gcc_assert (x != use_insn); | |
4715 | x = NEXT_INSN (x); | |
4716 | } | |
4717 | if (dump_file) | |
4718 | fprintf (dump_file, " input reg %u modified but insn %d moveable\n", | |
4719 | regno, INSN_UID (x)); | |
4720 | emit_insn_after (PATTERN (x), use_insn); | |
4721 | set_insn_deleted (x); | |
4722 | } | |
4723 | else | |
4724 | { | |
4725 | if (dump_file) | |
4726 | fprintf (dump_file, " input reg %u modified between def and use\n", | |
4727 | regno); | |
4728 | all_transp = false; | |
4729 | } | |
4730 | } | |
4731 | else | |
4732 | all_transp = false; | |
4733 | } | |
acf41a74 BS |
4734 | } |
4735 | if (!all_ok) | |
4736 | continue; | |
4737 | if (!dbg_cnt (ira_move)) | |
4738 | break; | |
4739 | if (dump_file) | |
4740 | fprintf (dump_file, " all ok%s\n", all_transp ? " and transp" : ""); | |
4741 | ||
4742 | if (all_transp) | |
4743 | { | |
4744 | rtx def_reg = DF_REF_REG (def); | |
4745 | rtx newreg = ira_create_new_reg (def_reg); | |
9e3de74c | 4746 | if (validate_change (def_insn, DF_REF_REAL_LOC (def), newreg, 0)) |
acf41a74 BS |
4747 | { |
4748 | unsigned nregno = REGNO (newreg); | |
a36b2706 | 4749 | emit_insn_before (gen_move_insn (def_reg, newreg), use_insn); |
acf41a74 | 4750 | nregno -= max_regs; |
9771b263 | 4751 | pseudo_replaced_reg[nregno] = def_reg; |
acf41a74 BS |
4752 | } |
4753 | } | |
4754 | } | |
4755 | ||
11cd3bed | 4756 | FOR_EACH_BB_FN (bb, cfun) |
acf41a74 BS |
4757 | { |
4758 | bitmap_clear (bb_local + bb->index); | |
4759 | bitmap_clear (bb_transp_live + bb->index); | |
4760 | bitmap_clear (bb_moveable_reg_sets + bb->index); | |
4761 | } | |
4762 | bitmap_clear (&interesting); | |
4763 | bitmap_clear (&unusable_as_input); | |
4764 | free (uid_luid); | |
4765 | free (closest_uses); | |
4766 | free (bb_local); | |
4767 | free (bb_transp_live); | |
4768 | free (bb_moveable_reg_sets); | |
4769 | ||
4770 | last_moveable_pseudo = max_reg_num (); | |
2d73cc45 MJ |
4771 | |
4772 | fix_reg_equiv_init (); | |
4773 | expand_reg_info (); | |
4774 | regstat_free_n_sets_and_refs (); | |
4775 | regstat_free_ri (); | |
4776 | regstat_init_n_sets_and_refs (); | |
4777 | regstat_compute_ri (); | |
4778 | free_dominance_info (CDI_DOMINATORS); | |
732dad8f | 4779 | } |
acf41a74 | 4780 | |
3e749749 MJ |
4781 | /* If SET pattern SET is an assignment from a hard register to a pseudo which |
4782 | is live at CALL_DOM (if non-NULL, otherwise this check is omitted), return | |
4783 | the destination. Otherwise return NULL. */ | |
732dad8f MJ |
4784 | |
4785 | static rtx | |
3e749749 | 4786 | interesting_dest_for_shprep_1 (rtx set, basic_block call_dom) |
732dad8f | 4787 | { |
732dad8f MJ |
4788 | rtx src = SET_SRC (set); |
4789 | rtx dest = SET_DEST (set); | |
4790 | if (!REG_P (src) || !HARD_REGISTER_P (src) | |
4791 | || !REG_P (dest) || HARD_REGISTER_P (dest) | |
4792 | || (call_dom && !bitmap_bit_p (df_get_live_in (call_dom), REGNO (dest)))) | |
4793 | return NULL; | |
4794 | return dest; | |
4795 | } | |
4796 | ||
df3e3493 | 4797 | /* If insn is interesting for parameter range-splitting shrink-wrapping |
3e749749 MJ |
4798 | preparation, i.e. it is a single set from a hard register to a pseudo, which |
4799 | is live at CALL_DOM (if non-NULL, otherwise this check is omitted), or a | |
4800 | parallel statement with only one such statement, return the destination. | |
4801 | Otherwise return NULL. */ | |
4802 | ||
4803 | static rtx | |
070a1983 | 4804 | interesting_dest_for_shprep (rtx_insn *insn, basic_block call_dom) |
3e749749 MJ |
4805 | { |
4806 | if (!INSN_P (insn)) | |
4807 | return NULL; | |
4808 | rtx pat = PATTERN (insn); | |
4809 | if (GET_CODE (pat) == SET) | |
4810 | return interesting_dest_for_shprep_1 (pat, call_dom); | |
4811 | ||
4812 | if (GET_CODE (pat) != PARALLEL) | |
4813 | return NULL; | |
4814 | rtx ret = NULL; | |
4815 | for (int i = 0; i < XVECLEN (pat, 0); i++) | |
4816 | { | |
4817 | rtx sub = XVECEXP (pat, 0, i); | |
4818 | if (GET_CODE (sub) == USE || GET_CODE (sub) == CLOBBER) | |
4819 | continue; | |
4820 | if (GET_CODE (sub) != SET | |
4821 | || side_effects_p (sub)) | |
4822 | return NULL; | |
4823 | rtx dest = interesting_dest_for_shprep_1 (sub, call_dom); | |
4824 | if (dest && ret) | |
4825 | return NULL; | |
4826 | if (dest) | |
4827 | ret = dest; | |
4828 | } | |
4829 | return ret; | |
4830 | } | |
4831 | ||
732dad8f MJ |
4832 | /* Split live ranges of pseudos that are loaded from hard registers in the |
4833 | first BB in a BB that dominates all non-sibling call if such a BB can be | |
4834 | found and is not in a loop. Return true if the function has made any | |
4835 | changes. */ | |
4836 | ||
4837 | static bool | |
4838 | split_live_ranges_for_shrink_wrap (void) | |
4839 | { | |
4840 | basic_block bb, call_dom = NULL; | |
fefa31b5 | 4841 | basic_block first = single_succ (ENTRY_BLOCK_PTR_FOR_FN (cfun)); |
070a1983 | 4842 | rtx_insn *insn, *last_interesting_insn = NULL; |
732dad8f MJ |
4843 | bitmap_head need_new, reachable; |
4844 | vec<basic_block> queue; | |
4845 | ||
a5e022d5 | 4846 | if (!SHRINK_WRAPPING_ENABLED) |
732dad8f MJ |
4847 | return false; |
4848 | ||
4849 | bitmap_initialize (&need_new, 0); | |
4850 | bitmap_initialize (&reachable, 0); | |
0cae8d31 | 4851 | queue.create (n_basic_blocks_for_fn (cfun)); |
732dad8f | 4852 | |
11cd3bed | 4853 | FOR_EACH_BB_FN (bb, cfun) |
732dad8f MJ |
4854 | FOR_BB_INSNS (bb, insn) |
4855 | if (CALL_P (insn) && !SIBLING_CALL_P (insn)) | |
4856 | { | |
4857 | if (bb == first) | |
4858 | { | |
4859 | bitmap_clear (&need_new); | |
4860 | bitmap_clear (&reachable); | |
4861 | queue.release (); | |
4862 | return false; | |
4863 | } | |
4864 | ||
4865 | bitmap_set_bit (&need_new, bb->index); | |
4866 | bitmap_set_bit (&reachable, bb->index); | |
4867 | queue.quick_push (bb); | |
4868 | break; | |
4869 | } | |
4870 | ||
4871 | if (queue.is_empty ()) | |
4872 | { | |
4873 | bitmap_clear (&need_new); | |
4874 | bitmap_clear (&reachable); | |
4875 | queue.release (); | |
4876 | return false; | |
4877 | } | |
4878 | ||
4879 | while (!queue.is_empty ()) | |
4880 | { | |
4881 | edge e; | |
4882 | edge_iterator ei; | |
4883 | ||
4884 | bb = queue.pop (); | |
4885 | FOR_EACH_EDGE (e, ei, bb->succs) | |
fefa31b5 | 4886 | if (e->dest != EXIT_BLOCK_PTR_FOR_FN (cfun) |
732dad8f MJ |
4887 | && bitmap_set_bit (&reachable, e->dest->index)) |
4888 | queue.quick_push (e->dest); | |
4889 | } | |
4890 | queue.release (); | |
4891 | ||
4892 | FOR_BB_INSNS (first, insn) | |
4893 | { | |
4894 | rtx dest = interesting_dest_for_shprep (insn, NULL); | |
4895 | if (!dest) | |
4896 | continue; | |
4897 | ||
4898 | if (DF_REG_DEF_COUNT (REGNO (dest)) > 1) | |
4899 | { | |
4900 | bitmap_clear (&need_new); | |
4901 | bitmap_clear (&reachable); | |
4902 | return false; | |
4903 | } | |
4904 | ||
4905 | for (df_ref use = DF_REG_USE_CHAIN (REGNO(dest)); | |
4906 | use; | |
4907 | use = DF_REF_NEXT_REG (use)) | |
4908 | { | |
732dad8f MJ |
4909 | int ubbi = DF_REF_BB (use)->index; |
4910 | if (bitmap_bit_p (&reachable, ubbi)) | |
4911 | bitmap_set_bit (&need_new, ubbi); | |
4912 | } | |
4913 | last_interesting_insn = insn; | |
4914 | } | |
4915 | ||
4916 | bitmap_clear (&reachable); | |
4917 | if (!last_interesting_insn) | |
4918 | { | |
4919 | bitmap_clear (&need_new); | |
4920 | return false; | |
4921 | } | |
4922 | ||
4923 | call_dom = nearest_common_dominator_for_set (CDI_DOMINATORS, &need_new); | |
4924 | bitmap_clear (&need_new); | |
4925 | if (call_dom == first) | |
4926 | return false; | |
4927 | ||
4928 | loop_optimizer_init (AVOID_CFG_MODIFICATIONS); | |
4929 | while (bb_loop_depth (call_dom) > 0) | |
4930 | call_dom = get_immediate_dominator (CDI_DOMINATORS, call_dom); | |
4931 | loop_optimizer_finalize (); | |
4932 | ||
4933 | if (call_dom == first) | |
4934 | return false; | |
4935 | ||
4936 | calculate_dominance_info (CDI_POST_DOMINATORS); | |
4937 | if (dominated_by_p (CDI_POST_DOMINATORS, first, call_dom)) | |
4938 | { | |
4939 | free_dominance_info (CDI_POST_DOMINATORS); | |
4940 | return false; | |
4941 | } | |
4942 | free_dominance_info (CDI_POST_DOMINATORS); | |
4943 | ||
4944 | if (dump_file) | |
4945 | fprintf (dump_file, "Will split live ranges of parameters at BB %i\n", | |
4946 | call_dom->index); | |
4947 | ||
4948 | bool ret = false; | |
4949 | FOR_BB_INSNS (first, insn) | |
4950 | { | |
4951 | rtx dest = interesting_dest_for_shprep (insn, call_dom); | |
bcb21886 | 4952 | if (!dest || dest == pic_offset_table_rtx) |
732dad8f MJ |
4953 | continue; |
4954 | ||
4955 | rtx newreg = NULL_RTX; | |
4956 | df_ref use, next; | |
9e3de74c | 4957 | for (use = DF_REG_USE_CHAIN (REGNO (dest)); use; use = next) |
732dad8f | 4958 | { |
070a1983 | 4959 | rtx_insn *uin = DF_REF_INSN (use); |
732dad8f MJ |
4960 | next = DF_REF_NEXT_REG (use); |
4961 | ||
4962 | basic_block ubb = BLOCK_FOR_INSN (uin); | |
4963 | if (ubb == call_dom | |
4964 | || dominated_by_p (CDI_DOMINATORS, ubb, call_dom)) | |
4965 | { | |
4966 | if (!newreg) | |
4967 | newreg = ira_create_new_reg (dest); | |
9e3de74c | 4968 | validate_change (uin, DF_REF_REAL_LOC (use), newreg, true); |
732dad8f MJ |
4969 | } |
4970 | } | |
4971 | ||
4972 | if (newreg) | |
4973 | { | |
1476d1bd | 4974 | rtx_insn *new_move = gen_move_insn (newreg, dest); |
732dad8f MJ |
4975 | emit_insn_after (new_move, bb_note (call_dom)); |
4976 | if (dump_file) | |
4977 | { | |
4978 | fprintf (dump_file, "Split live-range of register "); | |
4979 | print_rtl_single (dump_file, dest); | |
4980 | } | |
4981 | ret = true; | |
4982 | } | |
4983 | ||
4984 | if (insn == last_interesting_insn) | |
4985 | break; | |
4986 | } | |
4987 | apply_change_group (); | |
4988 | return ret; | |
acf41a74 | 4989 | } |
8ff49c29 | 4990 | |
acf41a74 BS |
4991 | /* Perform the second half of the transformation started in |
4992 | find_moveable_pseudos. We look for instances where the newly introduced | |
4993 | pseudo remains unallocated, and remove it by moving the definition to | |
4994 | just before its use, replacing the move instruction generated by | |
4995 | find_moveable_pseudos. */ | |
4996 | static void | |
4997 | move_unallocated_pseudos (void) | |
4998 | { | |
4999 | int i; | |
5000 | for (i = first_moveable_pseudo; i < last_moveable_pseudo; i++) | |
5001 | if (reg_renumber[i] < 0) | |
5002 | { | |
acf41a74 | 5003 | int idx = i - first_moveable_pseudo; |
9771b263 | 5004 | rtx other_reg = pseudo_replaced_reg[idx]; |
070a1983 | 5005 | rtx_insn *def_insn = DF_REF_INSN (DF_REG_DEF_CHAIN (i)); |
a36b2706 RS |
5006 | /* The use must follow all definitions of OTHER_REG, so we can |
5007 | insert the new definition immediately after any of them. */ | |
5008 | df_ref other_def = DF_REG_DEF_CHAIN (REGNO (other_reg)); | |
070a1983 DM |
5009 | rtx_insn *move_insn = DF_REF_INSN (other_def); |
5010 | rtx_insn *newinsn = emit_insn_after (PATTERN (def_insn), move_insn); | |
a36b2706 | 5011 | rtx set; |
acf41a74 BS |
5012 | int success; |
5013 | ||
5014 | if (dump_file) | |
5015 | fprintf (dump_file, "moving def of %d (insn %d now) ", | |
5016 | REGNO (other_reg), INSN_UID (def_insn)); | |
5017 | ||
a36b2706 RS |
5018 | delete_insn (move_insn); |
5019 | while ((other_def = DF_REG_DEF_CHAIN (REGNO (other_reg)))) | |
5020 | delete_insn (DF_REF_INSN (other_def)); | |
5021 | delete_insn (def_insn); | |
5022 | ||
acf41a74 BS |
5023 | set = single_set (newinsn); |
5024 | success = validate_change (newinsn, &SET_DEST (set), other_reg, 0); | |
5025 | gcc_assert (success); | |
5026 | if (dump_file) | |
5027 | fprintf (dump_file, " %d) rather than keep unallocated replacement %d\n", | |
5028 | INSN_UID (newinsn), i); | |
acf41a74 BS |
5029 | SET_REG_N_REFS (i, 0); |
5030 | } | |
5031 | } | |
f2034d06 | 5032 | \f |
6399c0ab SB |
5033 | /* If the backend knows where to allocate pseudos for hard |
5034 | register initial values, register these allocations now. */ | |
a932fb89 | 5035 | static void |
6399c0ab SB |
5036 | allocate_initial_values (void) |
5037 | { | |
5038 | if (targetm.allocate_initial_value) | |
5039 | { | |
5040 | rtx hreg, preg, x; | |
5041 | int i, regno; | |
5042 | ||
5043 | for (i = 0; HARD_REGISTER_NUM_P (i); i++) | |
5044 | { | |
5045 | if (! initial_value_entry (i, &hreg, &preg)) | |
5046 | break; | |
5047 | ||
5048 | x = targetm.allocate_initial_value (hreg); | |
5049 | regno = REGNO (preg); | |
5050 | if (x && REG_N_SETS (regno) <= 1) | |
5051 | { | |
5052 | if (MEM_P (x)) | |
5053 | reg_equiv_memory_loc (regno) = x; | |
5054 | else | |
5055 | { | |
5056 | basic_block bb; | |
5057 | int new_regno; | |
5058 | ||
5059 | gcc_assert (REG_P (x)); | |
5060 | new_regno = REGNO (x); | |
5061 | reg_renumber[regno] = new_regno; | |
5062 | /* Poke the regno right into regno_reg_rtx so that even | |
5063 | fixed regs are accepted. */ | |
5064 | SET_REGNO (preg, new_regno); | |
5065 | /* Update global register liveness information. */ | |
11cd3bed | 5066 | FOR_EACH_BB_FN (bb, cfun) |
6399c0ab | 5067 | { |
c3284718 | 5068 | if (REGNO_REG_SET_P (df_get_live_in (bb), regno)) |
6399c0ab | 5069 | SET_REGNO_REG_SET (df_get_live_in (bb), new_regno); |
c3284718 | 5070 | if (REGNO_REG_SET_P (df_get_live_out (bb), regno)) |
6399c0ab SB |
5071 | SET_REGNO_REG_SET (df_get_live_out (bb), new_regno); |
5072 | } | |
5073 | } | |
5074 | } | |
5075 | } | |
2af2dbdc | 5076 | |
6399c0ab SB |
5077 | gcc_checking_assert (! initial_value_entry (FIRST_PSEUDO_REGISTER, |
5078 | &hreg, &preg)); | |
5079 | } | |
5080 | } | |
5081 | \f | |
55a2c322 VM |
5082 | |
5083 | /* True when we use LRA instead of reload pass for the current | |
5084 | function. */ | |
5085 | bool ira_use_lra_p; | |
5086 | ||
311aab06 VM |
5087 | /* True if we have allocno conflicts. It is false for non-optimized |
5088 | mode or when the conflict table is too big. */ | |
5089 | bool ira_conflicts_p; | |
5090 | ||
ae2b9cb6 BS |
5091 | /* Saved between IRA and reload. */ |
5092 | static int saved_flag_ira_share_spill_slots; | |
5093 | ||
058e97ec VM |
5094 | /* This is the main entry of IRA. */ |
5095 | static void | |
5096 | ira (FILE *f) | |
5097 | { | |
058e97ec | 5098 | bool loops_p; |
70cc3288 | 5099 | int ira_max_point_before_emit; |
058e97ec | 5100 | int rebuild_p; |
55a2c322 VM |
5101 | bool saved_flag_caller_saves = flag_caller_saves; |
5102 | enum ira_region saved_flag_ira_region = flag_ira_region; | |
5103 | ||
bcb21886 KY |
5104 | /* Perform target specific PIC register initialization. */ |
5105 | targetm.init_pic_reg (); | |
5106 | ||
55a2c322 VM |
5107 | ira_conflicts_p = optimize > 0; |
5108 | ||
5109 | ira_use_lra_p = targetm.lra_p (); | |
5110 | /* If there are too many pseudos and/or basic blocks (e.g. 10K | |
5111 | pseudos and 10K blocks or 100K pseudos and 1K blocks), we will | |
5112 | use simplified and faster algorithms in LRA. */ | |
5113 | lra_simple_p | |
8b1c6fd7 DM |
5114 | = (ira_use_lra_p |
5115 | && max_reg_num () >= (1 << 26) / last_basic_block_for_fn (cfun)); | |
55a2c322 VM |
5116 | if (lra_simple_p) |
5117 | { | |
5118 | /* It permits to skip live range splitting in LRA. */ | |
5119 | flag_caller_saves = false; | |
5120 | /* There is no sense to do regional allocation when we use | |
5121 | simplified LRA. */ | |
5122 | flag_ira_region = IRA_REGION_ONE; | |
5123 | ira_conflicts_p = false; | |
5124 | } | |
5125 | ||
5126 | #ifndef IRA_NO_OBSTACK | |
5127 | gcc_obstack_init (&ira_obstack); | |
5128 | #endif | |
5129 | bitmap_obstack_initialize (&ira_bitmap_obstack); | |
058e97ec | 5130 | |
001010df KC |
5131 | /* LRA uses its own infrastructure to handle caller save registers. */ |
5132 | if (flag_caller_saves && !ira_use_lra_p) | |
dc12b70e JZ |
5133 | init_caller_save (); |
5134 | ||
058e97ec VM |
5135 | if (flag_ira_verbose < 10) |
5136 | { | |
5137 | internal_flag_ira_verbose = flag_ira_verbose; | |
5138 | ira_dump_file = f; | |
5139 | } | |
5140 | else | |
5141 | { | |
5142 | internal_flag_ira_verbose = flag_ira_verbose - 10; | |
5143 | ira_dump_file = stderr; | |
5144 | } | |
5145 | ||
5146 | setup_prohibited_mode_move_regs (); | |
3b6d1699 | 5147 | decrease_live_ranges_number (); |
058e97ec | 5148 | df_note_add_problem (); |
5d517141 SB |
5149 | |
5150 | /* DF_LIVE can't be used in the register allocator, too many other | |
5151 | parts of the compiler depend on using the "classic" liveness | |
5152 | interpretation of the DF_LR problem. See PR38711. | |
5153 | Remove the problem, so that we don't spend time updating it in | |
5154 | any of the df_analyze() calls during IRA/LRA. */ | |
5155 | if (optimize > 1) | |
5156 | df_remove_problem (df_live); | |
5157 | gcc_checking_assert (df_live == NULL); | |
5158 | ||
058e97ec VM |
5159 | #ifdef ENABLE_CHECKING |
5160 | df->changeable_flags |= DF_VERIFY_SCHEDULED; | |
5161 | #endif | |
5162 | df_analyze (); | |
3b6d1699 | 5163 | |
2d73cc45 MJ |
5164 | init_reg_equiv (); |
5165 | if (ira_conflicts_p) | |
5166 | { | |
5167 | calculate_dominance_info (CDI_DOMINATORS); | |
5168 | ||
5169 | if (split_live_ranges_for_shrink_wrap ()) | |
5170 | df_analyze (); | |
5171 | ||
5172 | free_dominance_info (CDI_DOMINATORS); | |
5173 | } | |
5174 | ||
058e97ec | 5175 | df_clear_flags (DF_NO_INSN_RESCAN); |
2d73cc45 | 5176 | |
058e97ec VM |
5177 | regstat_init_n_sets_and_refs (); |
5178 | regstat_compute_ri (); | |
5179 | ||
5180 | /* If we are not optimizing, then this is the only place before | |
5181 | register allocation where dataflow is done. And that is needed | |
5182 | to generate these warnings. */ | |
5183 | if (warn_clobbered) | |
5184 | generate_setjmp_warnings (); | |
5185 | ||
ace984c8 RS |
5186 | /* Determine if the current function is a leaf before running IRA |
5187 | since this can impact optimizations done by the prologue and | |
5188 | epilogue thus changing register elimination offsets. */ | |
416ff32e | 5189 | crtl->is_leaf = leaf_function_p (); |
ace984c8 | 5190 | |
1833192f | 5191 | if (resize_reg_info () && flag_ira_loop_pressure) |
b11f0116 | 5192 | ira_set_pseudo_classes (true, ira_dump_file); |
1833192f | 5193 | |
058e97ec | 5194 | rebuild_p = update_equiv_regs (); |
55a2c322 VM |
5195 | setup_reg_equiv (); |
5196 | setup_reg_equiv_init (); | |
058e97ec | 5197 | |
55a2c322 | 5198 | if (optimize && rebuild_p) |
b8698a0f | 5199 | { |
55a2c322 | 5200 | timevar_push (TV_JUMP); |
29f3fd5b | 5201 | rebuild_jump_labels (get_insns ()); |
55a2c322 VM |
5202 | if (purge_all_dead_edges ()) |
5203 | delete_unreachable_blocks (); | |
5204 | timevar_pop (TV_JUMP); | |
058e97ec VM |
5205 | } |
5206 | ||
fb99ee9b | 5207 | allocated_reg_info_size = max_reg_num (); |
e8d7e3e7 | 5208 | |
dbabddf3 JJ |
5209 | if (delete_trivially_dead_insns (get_insns (), max_reg_num ())) |
5210 | df_analyze (); | |
5211 | ||
e8d7e3e7 VM |
5212 | /* It is not worth to do such improvement when we use a simple |
5213 | allocation because of -O0 usage or because the function is too | |
5214 | big. */ | |
5215 | if (ira_conflicts_p) | |
2d73cc45 | 5216 | find_moveable_pseudos (); |
acf41a74 | 5217 | |
fb99ee9b | 5218 | max_regno_before_ira = max_reg_num (); |
8d49e7ef | 5219 | ira_setup_eliminable_regset (); |
b8698a0f | 5220 | |
058e97ec VM |
5221 | ira_overall_cost = ira_reg_cost = ira_mem_cost = 0; |
5222 | ira_load_cost = ira_store_cost = ira_shuffle_cost = 0; | |
5223 | ira_move_loops_num = ira_additional_jumps_num = 0; | |
b8698a0f | 5224 | |
058e97ec | 5225 | ira_assert (current_loops == NULL); |
2608d841 | 5226 | if (flag_ira_region == IRA_REGION_ALL || flag_ira_region == IRA_REGION_MIXED) |
661bc682 | 5227 | loop_optimizer_init (AVOID_CFG_MODIFICATIONS | LOOPS_HAVE_RECORDED_EXITS); |
b8698a0f | 5228 | |
058e97ec VM |
5229 | if (internal_flag_ira_verbose > 0 && ira_dump_file != NULL) |
5230 | fprintf (ira_dump_file, "Building IRA IR\n"); | |
2608d841 | 5231 | loops_p = ira_build (); |
b8698a0f | 5232 | |
311aab06 | 5233 | ira_assert (ira_conflicts_p || !loops_p); |
3553f0bb VM |
5234 | |
5235 | saved_flag_ira_share_spill_slots = flag_ira_share_spill_slots; | |
de8e52f0 | 5236 | if (too_high_register_pressure_p () || cfun->calls_setjmp) |
3553f0bb | 5237 | /* It is just wasting compiler's time to pack spilled pseudos into |
de8e52f0 VM |
5238 | stack slots in this case -- prohibit it. We also do this if |
5239 | there is setjmp call because a variable not modified between | |
5240 | setjmp and longjmp the compiler is required to preserve its | |
5241 | value and sharing slots does not guarantee it. */ | |
3553f0bb VM |
5242 | flag_ira_share_spill_slots = FALSE; |
5243 | ||
cb1ca6ac | 5244 | ira_color (); |
b8698a0f | 5245 | |
058e97ec | 5246 | ira_max_point_before_emit = ira_max_point; |
b8698a0f | 5247 | |
1756cb66 VM |
5248 | ira_initiate_emit_data (); |
5249 | ||
058e97ec | 5250 | ira_emit (loops_p); |
b8698a0f | 5251 | |
55a2c322 | 5252 | max_regno = max_reg_num (); |
311aab06 | 5253 | if (ira_conflicts_p) |
058e97ec | 5254 | { |
058e97ec | 5255 | if (! loops_p) |
55a2c322 VM |
5256 | { |
5257 | if (! ira_use_lra_p) | |
5258 | ira_initiate_assign (); | |
5259 | } | |
058e97ec VM |
5260 | else |
5261 | { | |
fb99ee9b | 5262 | expand_reg_info (); |
b8698a0f | 5263 | |
55a2c322 VM |
5264 | if (ira_use_lra_p) |
5265 | { | |
5266 | ira_allocno_t a; | |
5267 | ira_allocno_iterator ai; | |
5268 | ||
5269 | FOR_EACH_ALLOCNO (a, ai) | |
9d6e10c7 RL |
5270 | { |
5271 | int old_regno = ALLOCNO_REGNO (a); | |
5272 | int new_regno = REGNO (ALLOCNO_EMIT_DATA (a)->reg); | |
5273 | ||
5274 | ALLOCNO_REGNO (a) = new_regno; | |
5275 | ||
5276 | if (old_regno != new_regno) | |
5277 | setup_reg_classes (new_regno, reg_preferred_class (old_regno), | |
5278 | reg_alternate_class (old_regno), | |
5279 | reg_allocno_class (old_regno)); | |
5280 | } | |
5281 | ||
55a2c322 VM |
5282 | } |
5283 | else | |
5284 | { | |
5285 | if (internal_flag_ira_verbose > 0 && ira_dump_file != NULL) | |
5286 | fprintf (ira_dump_file, "Flattening IR\n"); | |
5287 | ira_flattening (max_regno_before_ira, ira_max_point_before_emit); | |
5288 | } | |
058e97ec VM |
5289 | /* New insns were generated: add notes and recalculate live |
5290 | info. */ | |
5291 | df_analyze (); | |
b8698a0f | 5292 | |
544e7e78 SB |
5293 | /* ??? Rebuild the loop tree, but why? Does the loop tree |
5294 | change if new insns were generated? Can that be handled | |
5295 | by updating the loop tree incrementally? */ | |
661bc682 | 5296 | loop_optimizer_finalize (); |
57548aa2 | 5297 | free_dominance_info (CDI_DOMINATORS); |
661bc682 RB |
5298 | loop_optimizer_init (AVOID_CFG_MODIFICATIONS |
5299 | | LOOPS_HAVE_RECORDED_EXITS); | |
058e97ec | 5300 | |
55a2c322 VM |
5301 | if (! ira_use_lra_p) |
5302 | { | |
5303 | setup_allocno_assignment_flags (); | |
5304 | ira_initiate_assign (); | |
5305 | ira_reassign_conflict_allocnos (max_regno); | |
5306 | } | |
058e97ec VM |
5307 | } |
5308 | } | |
5309 | ||
1756cb66 VM |
5310 | ira_finish_emit_data (); |
5311 | ||
058e97ec | 5312 | setup_reg_renumber (); |
b8698a0f | 5313 | |
058e97ec | 5314 | calculate_allocation_cost (); |
b8698a0f | 5315 | |
058e97ec | 5316 | #ifdef ENABLE_IRA_CHECKING |
311aab06 | 5317 | if (ira_conflicts_p) |
058e97ec VM |
5318 | check_allocation (); |
5319 | #endif | |
b8698a0f | 5320 | |
058e97ec VM |
5321 | if (max_regno != max_regno_before_ira) |
5322 | { | |
5323 | regstat_free_n_sets_and_refs (); | |
5324 | regstat_free_ri (); | |
5325 | regstat_init_n_sets_and_refs (); | |
5326 | regstat_compute_ri (); | |
5327 | } | |
5328 | ||
058e97ec | 5329 | overall_cost_before = ira_overall_cost; |
e5b0e1ca VM |
5330 | if (! ira_conflicts_p) |
5331 | grow_reg_equivs (); | |
5332 | else | |
058e97ec VM |
5333 | { |
5334 | fix_reg_equiv_init (); | |
b8698a0f | 5335 | |
058e97ec VM |
5336 | #ifdef ENABLE_IRA_CHECKING |
5337 | print_redundant_copies (); | |
5338 | #endif | |
9994ad20 KC |
5339 | if (! ira_use_lra_p) |
5340 | { | |
5341 | ira_spilled_reg_stack_slots_num = 0; | |
5342 | ira_spilled_reg_stack_slots | |
5343 | = ((struct ira_spilled_reg_stack_slot *) | |
5344 | ira_allocate (max_regno | |
5345 | * sizeof (struct ira_spilled_reg_stack_slot))); | |
5346 | memset (ira_spilled_reg_stack_slots, 0, | |
5347 | max_regno * sizeof (struct ira_spilled_reg_stack_slot)); | |
5348 | } | |
058e97ec | 5349 | } |
6399c0ab | 5350 | allocate_initial_values (); |
e8d7e3e7 VM |
5351 | |
5352 | /* See comment for find_moveable_pseudos call. */ | |
5353 | if (ira_conflicts_p) | |
5354 | move_unallocated_pseudos (); | |
55a2c322 VM |
5355 | |
5356 | /* Restore original values. */ | |
5357 | if (lra_simple_p) | |
5358 | { | |
5359 | flag_caller_saves = saved_flag_caller_saves; | |
5360 | flag_ira_region = saved_flag_ira_region; | |
5361 | } | |
d3afd9aa RB |
5362 | } |
5363 | ||
5364 | static void | |
5365 | do_reload (void) | |
5366 | { | |
5367 | basic_block bb; | |
5368 | bool need_dce; | |
bcb21886 | 5369 | unsigned pic_offset_table_regno = INVALID_REGNUM; |
ae2b9cb6 | 5370 | |
67463efb | 5371 | if (flag_ira_verbose < 10) |
ae2b9cb6 | 5372 | ira_dump_file = dump_file; |
058e97ec | 5373 | |
bcb21886 KY |
5374 | /* If pic_offset_table_rtx is a pseudo register, then keep it so |
5375 | after reload to avoid possible wrong usages of hard reg assigned | |
5376 | to it. */ | |
5377 | if (pic_offset_table_rtx | |
5378 | && REGNO (pic_offset_table_rtx) >= FIRST_PSEUDO_REGISTER) | |
5379 | pic_offset_table_regno = REGNO (pic_offset_table_rtx); | |
5380 | ||
55a2c322 VM |
5381 | timevar_push (TV_RELOAD); |
5382 | if (ira_use_lra_p) | |
5383 | { | |
5384 | if (current_loops != NULL) | |
5385 | { | |
661bc682 | 5386 | loop_optimizer_finalize (); |
55a2c322 VM |
5387 | free_dominance_info (CDI_DOMINATORS); |
5388 | } | |
04a90bec | 5389 | FOR_ALL_BB_FN (bb, cfun) |
55a2c322 VM |
5390 | bb->loop_father = NULL; |
5391 | current_loops = NULL; | |
55a2c322 VM |
5392 | |
5393 | ira_destroy (); | |
058e97ec | 5394 | |
55a2c322 VM |
5395 | lra (ira_dump_file); |
5396 | /* ???!!! Move it before lra () when we use ira_reg_equiv in | |
5397 | LRA. */ | |
9771b263 | 5398 | vec_free (reg_equivs); |
55a2c322 VM |
5399 | reg_equivs = NULL; |
5400 | need_dce = false; | |
5401 | } | |
5402 | else | |
5403 | { | |
5404 | df_set_flags (DF_NO_INSN_RESCAN); | |
5405 | build_insn_chain (); | |
5406 | ||
5407 | need_dce = reload (get_insns (), ira_conflicts_p); | |
5408 | ||
5409 | } | |
5410 | ||
5411 | timevar_pop (TV_RELOAD); | |
058e97ec | 5412 | |
d3afd9aa RB |
5413 | timevar_push (TV_IRA); |
5414 | ||
55a2c322 | 5415 | if (ira_conflicts_p && ! ira_use_lra_p) |
058e97ec VM |
5416 | { |
5417 | ira_free (ira_spilled_reg_stack_slots); | |
058e97ec | 5418 | ira_finish_assign (); |
b8698a0f | 5419 | } |
55a2c322 | 5420 | |
058e97ec VM |
5421 | if (internal_flag_ira_verbose > 0 && ira_dump_file != NULL |
5422 | && overall_cost_before != ira_overall_cost) | |
16998094 | 5423 | fprintf (ira_dump_file, "+++Overall after reload %" PRId64 "\n", |
2bf7560b | 5424 | ira_overall_cost); |
b8698a0f | 5425 | |
3553f0bb VM |
5426 | flag_ira_share_spill_slots = saved_flag_ira_share_spill_slots; |
5427 | ||
55a2c322 | 5428 | if (! ira_use_lra_p) |
2608d841 | 5429 | { |
55a2c322 VM |
5430 | ira_destroy (); |
5431 | if (current_loops != NULL) | |
5432 | { | |
661bc682 | 5433 | loop_optimizer_finalize (); |
55a2c322 VM |
5434 | free_dominance_info (CDI_DOMINATORS); |
5435 | } | |
04a90bec | 5436 | FOR_ALL_BB_FN (bb, cfun) |
55a2c322 VM |
5437 | bb->loop_father = NULL; |
5438 | current_loops = NULL; | |
5439 | ||
5440 | regstat_free_ri (); | |
5441 | regstat_free_n_sets_and_refs (); | |
2608d841 | 5442 | } |
b8698a0f | 5443 | |
058e97ec | 5444 | if (optimize) |
55a2c322 | 5445 | cleanup_cfg (CLEANUP_EXPENSIVE); |
b8698a0f | 5446 | |
55a2c322 | 5447 | finish_reg_equiv (); |
058e97ec VM |
5448 | |
5449 | bitmap_obstack_release (&ira_bitmap_obstack); | |
5450 | #ifndef IRA_NO_OBSTACK | |
5451 | obstack_free (&ira_obstack, NULL); | |
5452 | #endif | |
5453 | ||
5454 | /* The code after the reload has changed so much that at this point | |
b0c11403 | 5455 | we might as well just rescan everything. Note that |
058e97ec VM |
5456 | df_rescan_all_insns is not going to help here because it does not |
5457 | touch the artificial uses and defs. */ | |
5458 | df_finish_pass (true); | |
058e97ec VM |
5459 | df_scan_alloc (NULL); |
5460 | df_scan_blocks (); | |
5461 | ||
5d517141 SB |
5462 | if (optimize > 1) |
5463 | { | |
5464 | df_live_add_problem (); | |
5465 | df_live_set_all_dirty (); | |
5466 | } | |
5467 | ||
058e97ec VM |
5468 | if (optimize) |
5469 | df_analyze (); | |
5470 | ||
b0c11403 JL |
5471 | if (need_dce && optimize) |
5472 | run_fast_dce (); | |
d3afd9aa | 5473 | |
af6e8467 RH |
5474 | /* Diagnose uses of the hard frame pointer when it is used as a global |
5475 | register. Often we can get away with letting the user appropriate | |
5476 | the frame pointer, but we should let them know when code generation | |
5477 | makes that impossible. */ | |
5478 | if (global_regs[HARD_FRAME_POINTER_REGNUM] && frame_pointer_needed) | |
5479 | { | |
5480 | tree decl = global_regs_decl[HARD_FRAME_POINTER_REGNUM]; | |
5481 | error_at (DECL_SOURCE_LOCATION (current_function_decl), | |
5482 | "frame pointer required, but reserved"); | |
5483 | inform (DECL_SOURCE_LOCATION (decl), "for %qD", decl); | |
5484 | } | |
5485 | ||
bcb21886 KY |
5486 | if (pic_offset_table_regno != INVALID_REGNUM) |
5487 | pic_offset_table_rtx = gen_rtx_REG (Pmode, pic_offset_table_regno); | |
5488 | ||
d3afd9aa | 5489 | timevar_pop (TV_IRA); |
058e97ec | 5490 | } |
058e97ec | 5491 | \f |
058e97ec | 5492 | /* Run the integrated register allocator. */ |
058e97ec | 5493 | |
27a4cd48 DM |
5494 | namespace { |
5495 | ||
5496 | const pass_data pass_data_ira = | |
058e97ec | 5497 | { |
27a4cd48 DM |
5498 | RTL_PASS, /* type */ |
5499 | "ira", /* name */ | |
5500 | OPTGROUP_NONE, /* optinfo_flags */ | |
27a4cd48 DM |
5501 | TV_IRA, /* tv_id */ |
5502 | 0, /* properties_required */ | |
5503 | 0, /* properties_provided */ | |
5504 | 0, /* properties_destroyed */ | |
5505 | 0, /* todo_flags_start */ | |
5506 | TODO_do_not_ggc_collect, /* todo_flags_finish */ | |
d3afd9aa RB |
5507 | }; |
5508 | ||
27a4cd48 DM |
5509 | class pass_ira : public rtl_opt_pass |
5510 | { | |
5511 | public: | |
c3284718 RS |
5512 | pass_ira (gcc::context *ctxt) |
5513 | : rtl_opt_pass (pass_data_ira, ctxt) | |
27a4cd48 DM |
5514 | {} |
5515 | ||
5516 | /* opt_pass methods: */ | |
a50fa76a BS |
5517 | virtual bool gate (function *) |
5518 | { | |
5519 | return !targetm.no_register_allocation; | |
5520 | } | |
be55bfe6 TS |
5521 | virtual unsigned int execute (function *) |
5522 | { | |
5523 | ira (dump_file); | |
5524 | return 0; | |
5525 | } | |
27a4cd48 DM |
5526 | |
5527 | }; // class pass_ira | |
5528 | ||
5529 | } // anon namespace | |
5530 | ||
5531 | rtl_opt_pass * | |
5532 | make_pass_ira (gcc::context *ctxt) | |
5533 | { | |
5534 | return new pass_ira (ctxt); | |
5535 | } | |
5536 | ||
27a4cd48 DM |
5537 | namespace { |
5538 | ||
5539 | const pass_data pass_data_reload = | |
d3afd9aa | 5540 | { |
27a4cd48 DM |
5541 | RTL_PASS, /* type */ |
5542 | "reload", /* name */ | |
5543 | OPTGROUP_NONE, /* optinfo_flags */ | |
27a4cd48 DM |
5544 | TV_RELOAD, /* tv_id */ |
5545 | 0, /* properties_required */ | |
5546 | 0, /* properties_provided */ | |
5547 | 0, /* properties_destroyed */ | |
5548 | 0, /* todo_flags_start */ | |
5549 | 0, /* todo_flags_finish */ | |
058e97ec | 5550 | }; |
27a4cd48 DM |
5551 | |
5552 | class pass_reload : public rtl_opt_pass | |
5553 | { | |
5554 | public: | |
c3284718 RS |
5555 | pass_reload (gcc::context *ctxt) |
5556 | : rtl_opt_pass (pass_data_reload, ctxt) | |
27a4cd48 DM |
5557 | {} |
5558 | ||
5559 | /* opt_pass methods: */ | |
a50fa76a BS |
5560 | virtual bool gate (function *) |
5561 | { | |
5562 | return !targetm.no_register_allocation; | |
5563 | } | |
be55bfe6 TS |
5564 | virtual unsigned int execute (function *) |
5565 | { | |
5566 | do_reload (); | |
5567 | return 0; | |
5568 | } | |
27a4cd48 DM |
5569 | |
5570 | }; // class pass_reload | |
5571 | ||
5572 | } // anon namespace | |
5573 | ||
5574 | rtl_opt_pass * | |
5575 | make_pass_reload (gcc::context *ctxt) | |
5576 | { | |
5577 | return new pass_reload (ctxt); | |
5578 | } |