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058e97ec | 1 | /* Integrated Register Allocator (IRA) entry point. |
8d9254fc | 2 | Copyright (C) 2006-2020 Free Software Foundation, Inc. |
058e97ec VM |
3 | Contributed by Vladimir Makarov <vmakarov@redhat.com>. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it under | |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 3, or (at your option) any later | |
10 | version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | /* The integrated register allocator (IRA) is a | |
22 | regional register allocator performing graph coloring on a top-down | |
23 | traversal of nested regions. Graph coloring in a region is based | |
24 | on Chaitin-Briggs algorithm. It is called integrated because | |
25 | register coalescing, register live range splitting, and choosing a | |
26 | better hard register are done on-the-fly during coloring. Register | |
27 | coalescing and choosing a cheaper hard register is done by hard | |
28 | register preferencing during hard register assigning. The live | |
29 | range splitting is a byproduct of the regional register allocation. | |
30 | ||
31 | Major IRA notions are: | |
32 | ||
33 | o *Region* is a part of CFG where graph coloring based on | |
34 | Chaitin-Briggs algorithm is done. IRA can work on any set of | |
35 | nested CFG regions forming a tree. Currently the regions are | |
36 | the entire function for the root region and natural loops for | |
37 | the other regions. Therefore data structure representing a | |
38 | region is called loop_tree_node. | |
39 | ||
1756cb66 VM |
40 | o *Allocno class* is a register class used for allocation of |
41 | given allocno. It means that only hard register of given | |
42 | register class can be assigned to given allocno. In reality, | |
43 | even smaller subset of (*profitable*) hard registers can be | |
44 | assigned. In rare cases, the subset can be even smaller | |
45 | because our modification of Chaitin-Briggs algorithm requires | |
46 | that sets of hard registers can be assigned to allocnos forms a | |
47 | forest, i.e. the sets can be ordered in a way where any | |
48 | previous set is not intersected with given set or is a superset | |
49 | of given set. | |
50 | ||
51 | o *Pressure class* is a register class belonging to a set of | |
52 | register classes containing all of the hard-registers available | |
53 | for register allocation. The set of all pressure classes for a | |
54 | target is defined in the corresponding machine-description file | |
55 | according some criteria. Register pressure is calculated only | |
56 | for pressure classes and it affects some IRA decisions as | |
57 | forming allocation regions. | |
058e97ec VM |
58 | |
59 | o *Allocno* represents the live range of a pseudo-register in a | |
60 | region. Besides the obvious attributes like the corresponding | |
1756cb66 | 61 | pseudo-register number, allocno class, conflicting allocnos and |
058e97ec VM |
62 | conflicting hard-registers, there are a few allocno attributes |
63 | which are important for understanding the allocation algorithm: | |
64 | ||
1756cb66 VM |
65 | - *Live ranges*. This is a list of ranges of *program points* |
66 | where the allocno lives. Program points represent places | |
67 | where a pseudo can be born or become dead (there are | |
058e97ec VM |
68 | approximately two times more program points than the insns) |
69 | and they are represented by integers starting with 0. The | |
1756cb66 VM |
70 | live ranges are used to find conflicts between allocnos. |
71 | They also play very important role for the transformation of | |
72 | the IRA internal representation of several regions into a one | |
73 | region representation. The later is used during the reload | |
74 | pass work because each allocno represents all of the | |
75 | corresponding pseudo-registers. | |
058e97ec VM |
76 | |
77 | - *Hard-register costs*. This is a vector of size equal to the | |
1756cb66 VM |
78 | number of available hard-registers of the allocno class. The |
79 | cost of a callee-clobbered hard-register for an allocno is | |
80 | increased by the cost of save/restore code around the calls | |
81 | through the given allocno's life. If the allocno is a move | |
82 | instruction operand and another operand is a hard-register of | |
83 | the allocno class, the cost of the hard-register is decreased | |
84 | by the move cost. | |
058e97ec VM |
85 | |
86 | When an allocno is assigned, the hard-register with minimal | |
87 | full cost is used. Initially, a hard-register's full cost is | |
88 | the corresponding value from the hard-register's cost vector. | |
89 | If the allocno is connected by a *copy* (see below) to | |
90 | another allocno which has just received a hard-register, the | |
91 | cost of the hard-register is decreased. Before choosing a | |
92 | hard-register for an allocno, the allocno's current costs of | |
93 | the hard-registers are modified by the conflict hard-register | |
94 | costs of all of the conflicting allocnos which are not | |
95 | assigned yet. | |
96 | ||
97 | - *Conflict hard-register costs*. This is a vector of the same | |
98 | size as the hard-register costs vector. To permit an | |
99 | unassigned allocno to get a better hard-register, IRA uses | |
100 | this vector to calculate the final full cost of the | |
101 | available hard-registers. Conflict hard-register costs of an | |
102 | unassigned allocno are also changed with a change of the | |
103 | hard-register cost of the allocno when a copy involving the | |
104 | allocno is processed as described above. This is done to | |
105 | show other unassigned allocnos that a given allocno prefers | |
106 | some hard-registers in order to remove the move instruction | |
107 | corresponding to the copy. | |
108 | ||
109 | o *Cap*. If a pseudo-register does not live in a region but | |
110 | lives in a nested region, IRA creates a special allocno called | |
111 | a cap in the outer region. A region cap is also created for a | |
112 | subregion cap. | |
113 | ||
114 | o *Copy*. Allocnos can be connected by copies. Copies are used | |
115 | to modify hard-register costs for allocnos during coloring. | |
116 | Such modifications reflects a preference to use the same | |
117 | hard-register for the allocnos connected by copies. Usually | |
118 | copies are created for move insns (in this case it results in | |
119 | register coalescing). But IRA also creates copies for operands | |
120 | of an insn which should be assigned to the same hard-register | |
121 | due to constraints in the machine description (it usually | |
122 | results in removing a move generated in reload to satisfy | |
123 | the constraints) and copies referring to the allocno which is | |
124 | the output operand of an instruction and the allocno which is | |
125 | an input operand dying in the instruction (creation of such | |
126 | copies results in less register shuffling). IRA *does not* | |
127 | create copies between the same register allocnos from different | |
128 | regions because we use another technique for propagating | |
129 | hard-register preference on the borders of regions. | |
130 | ||
131 | Allocnos (including caps) for the upper region in the region tree | |
132 | *accumulate* information important for coloring from allocnos with | |
133 | the same pseudo-register from nested regions. This includes | |
134 | hard-register and memory costs, conflicts with hard-registers, | |
135 | allocno conflicts, allocno copies and more. *Thus, attributes for | |
136 | allocnos in a region have the same values as if the region had no | |
137 | subregions*. It means that attributes for allocnos in the | |
138 | outermost region corresponding to the function have the same values | |
139 | as though the allocation used only one region which is the entire | |
140 | function. It also means that we can look at IRA work as if the | |
141 | first IRA did allocation for all function then it improved the | |
142 | allocation for loops then their subloops and so on. | |
143 | ||
144 | IRA major passes are: | |
145 | ||
146 | o Building IRA internal representation which consists of the | |
147 | following subpasses: | |
148 | ||
149 | * First, IRA builds regions and creates allocnos (file | |
150 | ira-build.c) and initializes most of their attributes. | |
151 | ||
1756cb66 VM |
152 | * Then IRA finds an allocno class for each allocno and |
153 | calculates its initial (non-accumulated) cost of memory and | |
154 | each hard-register of its allocno class (file ira-cost.c). | |
058e97ec | 155 | |
df3e3493 | 156 | * IRA creates live ranges of each allocno, calculates register |
1756cb66 | 157 | pressure for each pressure class in each region, sets up |
058e97ec VM |
158 | conflict hard registers for each allocno and info about calls |
159 | the allocno lives through (file ira-lives.c). | |
160 | ||
161 | * IRA removes low register pressure loops from the regions | |
162 | mostly to speed IRA up (file ira-build.c). | |
163 | ||
164 | * IRA propagates accumulated allocno info from lower region | |
165 | allocnos to corresponding upper region allocnos (file | |
166 | ira-build.c). | |
167 | ||
168 | * IRA creates all caps (file ira-build.c). | |
169 | ||
1756cb66 VM |
170 | * Having live-ranges of allocnos and their classes, IRA creates |
171 | conflicting allocnos for each allocno. Conflicting allocnos | |
172 | are stored as a bit vector or array of pointers to the | |
173 | conflicting allocnos whatever is more profitable (file | |
174 | ira-conflicts.c). At this point IRA creates allocno copies. | |
058e97ec VM |
175 | |
176 | o Coloring. Now IRA has all necessary info to start graph coloring | |
177 | process. It is done in each region on top-down traverse of the | |
178 | region tree (file ira-color.c). There are following subpasses: | |
b8698a0f | 179 | |
1756cb66 VM |
180 | * Finding profitable hard registers of corresponding allocno |
181 | class for each allocno. For example, only callee-saved hard | |
182 | registers are frequently profitable for allocnos living | |
183 | through colors. If the profitable hard register set of | |
184 | allocno does not form a tree based on subset relation, we use | |
185 | some approximation to form the tree. This approximation is | |
186 | used to figure out trivial colorability of allocnos. The | |
187 | approximation is a pretty rare case. | |
188 | ||
058e97ec VM |
189 | * Putting allocnos onto the coloring stack. IRA uses Briggs |
190 | optimistic coloring which is a major improvement over | |
191 | Chaitin's coloring. Therefore IRA does not spill allocnos at | |
192 | this point. There is some freedom in the order of putting | |
193 | allocnos on the stack which can affect the final result of | |
1756cb66 | 194 | the allocation. IRA uses some heuristics to improve the |
41808d15 VM |
195 | order. The major one is to form *threads* from colorable |
196 | allocnos and push them on the stack by threads. Thread is a | |
197 | set of non-conflicting colorable allocnos connected by | |
198 | copies. The thread contains allocnos from the colorable | |
199 | bucket or colorable allocnos already pushed onto the coloring | |
200 | stack. Pushing thread allocnos one after another onto the | |
201 | stack increases chances of removing copies when the allocnos | |
202 | get the same hard reg. | |
1756cb66 VM |
203 | |
204 | We also use a modification of Chaitin-Briggs algorithm which | |
205 | works for intersected register classes of allocnos. To | |
206 | figure out trivial colorability of allocnos, the mentioned | |
207 | above tree of hard register sets is used. To get an idea how | |
208 | the algorithm works in i386 example, let us consider an | |
209 | allocno to which any general hard register can be assigned. | |
210 | If the allocno conflicts with eight allocnos to which only | |
211 | EAX register can be assigned, given allocno is still | |
212 | trivially colorable because all conflicting allocnos might be | |
213 | assigned only to EAX and all other general hard registers are | |
214 | still free. | |
215 | ||
216 | To get an idea of the used trivial colorability criterion, it | |
217 | is also useful to read article "Graph-Coloring Register | |
218 | Allocation for Irregular Architectures" by Michael D. Smith | |
219 | and Glen Holloway. Major difference between the article | |
220 | approach and approach used in IRA is that Smith's approach | |
221 | takes register classes only from machine description and IRA | |
222 | calculate register classes from intermediate code too | |
223 | (e.g. an explicit usage of hard registers in RTL code for | |
224 | parameter passing can result in creation of additional | |
225 | register classes which contain or exclude the hard | |
226 | registers). That makes IRA approach useful for improving | |
227 | coloring even for architectures with regular register files | |
228 | and in fact some benchmarking shows the improvement for | |
229 | regular class architectures is even bigger than for irregular | |
230 | ones. Another difference is that Smith's approach chooses | |
231 | intersection of classes of all insn operands in which a given | |
232 | pseudo occurs. IRA can use bigger classes if it is still | |
233 | more profitable than memory usage. | |
058e97ec VM |
234 | |
235 | * Popping the allocnos from the stack and assigning them hard | |
67914693 | 236 | registers. If IRA cannot assign a hard register to an |
058e97ec VM |
237 | allocno and the allocno is coalesced, IRA undoes the |
238 | coalescing and puts the uncoalesced allocnos onto the stack in | |
239 | the hope that some such allocnos will get a hard register | |
240 | separately. If IRA fails to assign hard register or memory | |
241 | is more profitable for it, IRA spills the allocno. IRA | |
242 | assigns the allocno the hard-register with minimal full | |
243 | allocation cost which reflects the cost of usage of the | |
244 | hard-register for the allocno and cost of usage of the | |
245 | hard-register for allocnos conflicting with given allocno. | |
246 | ||
1756cb66 | 247 | * Chaitin-Briggs coloring assigns as many pseudos as possible |
df3e3493 | 248 | to hard registers. After coloring we try to improve |
1756cb66 VM |
249 | allocation with cost point of view. We improve the |
250 | allocation by spilling some allocnos and assigning the freed | |
251 | hard registers to other allocnos if it decreases the overall | |
252 | allocation cost. | |
253 | ||
3447fefe | 254 | * After allocno assigning in the region, IRA modifies the hard |
058e97ec VM |
255 | register and memory costs for the corresponding allocnos in |
256 | the subregions to reflect the cost of possible loads, stores, | |
257 | or moves on the border of the region and its subregions. | |
258 | When default regional allocation algorithm is used | |
259 | (-fira-algorithm=mixed), IRA just propagates the assignment | |
260 | for allocnos if the register pressure in the region for the | |
1756cb66 VM |
261 | corresponding pressure class is less than number of available |
262 | hard registers for given pressure class. | |
058e97ec VM |
263 | |
264 | o Spill/restore code moving. When IRA performs an allocation | |
265 | by traversing regions in top-down order, it does not know what | |
266 | happens below in the region tree. Therefore, sometimes IRA | |
267 | misses opportunities to perform a better allocation. A simple | |
268 | optimization tries to improve allocation in a region having | |
269 | subregions and containing in another region. If the | |
270 | corresponding allocnos in the subregion are spilled, it spills | |
271 | the region allocno if it is profitable. The optimization | |
272 | implements a simple iterative algorithm performing profitable | |
273 | transformations while they are still possible. It is fast in | |
274 | practice, so there is no real need for a better time complexity | |
275 | algorithm. | |
276 | ||
1756cb66 VM |
277 | o Code change. After coloring, two allocnos representing the |
278 | same pseudo-register outside and inside a region respectively | |
279 | may be assigned to different locations (hard-registers or | |
280 | memory). In this case IRA creates and uses a new | |
281 | pseudo-register inside the region and adds code to move allocno | |
282 | values on the region's borders. This is done during top-down | |
283 | traversal of the regions (file ira-emit.c). In some | |
284 | complicated cases IRA can create a new allocno to move allocno | |
285 | values (e.g. when a swap of values stored in two hard-registers | |
286 | is needed). At this stage, the new allocno is marked as | |
287 | spilled. IRA still creates the pseudo-register and the moves | |
288 | on the region borders even when both allocnos were assigned to | |
289 | the same hard-register. If the reload pass spills a | |
290 | pseudo-register for some reason, the effect will be smaller | |
291 | because another allocno will still be in the hard-register. In | |
292 | most cases, this is better then spilling both allocnos. If | |
293 | reload does not change the allocation for the two | |
294 | pseudo-registers, the trivial move will be removed by | |
295 | post-reload optimizations. IRA does not generate moves for | |
058e97ec VM |
296 | allocnos assigned to the same hard register when the default |
297 | regional allocation algorithm is used and the register pressure | |
1756cb66 VM |
298 | in the region for the corresponding pressure class is less than |
299 | number of available hard registers for given pressure class. | |
058e97ec VM |
300 | IRA also does some optimizations to remove redundant stores and |
301 | to reduce code duplication on the region borders. | |
302 | ||
303 | o Flattening internal representation. After changing code, IRA | |
304 | transforms its internal representation for several regions into | |
305 | one region representation (file ira-build.c). This process is | |
306 | called IR flattening. Such process is more complicated than IR | |
307 | rebuilding would be, but is much faster. | |
308 | ||
309 | o After IR flattening, IRA tries to assign hard registers to all | |
df3e3493 | 310 | spilled allocnos. This is implemented by a simple and fast |
058e97ec VM |
311 | priority coloring algorithm (see function |
312 | ira_reassign_conflict_allocnos::ira-color.c). Here new allocnos | |
313 | created during the code change pass can be assigned to hard | |
314 | registers. | |
315 | ||
316 | o At the end IRA calls the reload pass. The reload pass | |
317 | communicates with IRA through several functions in file | |
318 | ira-color.c to improve its decisions in | |
319 | ||
320 | * sharing stack slots for the spilled pseudos based on IRA info | |
321 | about pseudo-register conflicts. | |
322 | ||
323 | * reassigning hard-registers to all spilled pseudos at the end | |
324 | of each reload iteration. | |
325 | ||
326 | * choosing a better hard-register to spill based on IRA info | |
327 | about pseudo-register live ranges and the register pressure | |
328 | in places where the pseudo-register lives. | |
329 | ||
330 | IRA uses a lot of data representing the target processors. These | |
df3e3493 | 331 | data are initialized in file ira.c. |
058e97ec VM |
332 | |
333 | If function has no loops (or the loops are ignored when | |
334 | -fira-algorithm=CB is used), we have classic Chaitin-Briggs | |
335 | coloring (only instead of separate pass of coalescing, we use hard | |
336 | register preferencing). In such case, IRA works much faster | |
337 | because many things are not made (like IR flattening, the | |
338 | spill/restore optimization, and the code change). | |
339 | ||
340 | Literature is worth to read for better understanding the code: | |
341 | ||
342 | o Preston Briggs, Keith D. Cooper, Linda Torczon. Improvements to | |
343 | Graph Coloring Register Allocation. | |
344 | ||
345 | o David Callahan, Brian Koblenz. Register allocation via | |
346 | hierarchical graph coloring. | |
347 | ||
348 | o Keith Cooper, Anshuman Dasgupta, Jason Eckhardt. Revisiting Graph | |
349 | Coloring Register Allocation: A Study of the Chaitin-Briggs and | |
350 | Callahan-Koblenz Algorithms. | |
351 | ||
352 | o Guei-Yuan Lueh, Thomas Gross, and Ali-Reza Adl-Tabatabai. Global | |
353 | Register Allocation Based on Graph Fusion. | |
354 | ||
1756cb66 VM |
355 | o Michael D. Smith and Glenn Holloway. Graph-Coloring Register |
356 | Allocation for Irregular Architectures | |
357 | ||
058e97ec VM |
358 | o Vladimir Makarov. The Integrated Register Allocator for GCC. |
359 | ||
360 | o Vladimir Makarov. The top-down register allocator for irregular | |
361 | register file architectures. | |
362 | ||
363 | */ | |
364 | ||
365 | ||
366 | #include "config.h" | |
367 | #include "system.h" | |
368 | #include "coretypes.h" | |
c7131fb2 | 369 | #include "backend.h" |
957060b5 | 370 | #include "target.h" |
058e97ec | 371 | #include "rtl.h" |
957060b5 | 372 | #include "tree.h" |
c7131fb2 | 373 | #include "df.h" |
4d0cdd0c | 374 | #include "memmodel.h" |
957060b5 | 375 | #include "tm_p.h" |
957060b5 | 376 | #include "insn-config.h" |
c7131fb2 | 377 | #include "regs.h" |
957060b5 AM |
378 | #include "ira.h" |
379 | #include "ira-int.h" | |
380 | #include "diagnostic-core.h" | |
60393bbc AM |
381 | #include "cfgrtl.h" |
382 | #include "cfgbuild.h" | |
383 | #include "cfgcleanup.h" | |
058e97ec | 384 | #include "expr.h" |
058e97ec VM |
385 | #include "tree-pass.h" |
386 | #include "output.h" | |
387 | #include "reload.h" | |
c7131fb2 | 388 | #include "cfgloop.h" |
55a2c322 | 389 | #include "lra.h" |
b0c11403 | 390 | #include "dce.h" |
acf41a74 | 391 | #include "dbgcnt.h" |
40954ce5 | 392 | #include "rtl-iter.h" |
a5e022d5 | 393 | #include "shrink-wrap.h" |
013a8899 | 394 | #include "print-rtl.h" |
058e97ec | 395 | |
afcc66c4 | 396 | struct target_ira default_target_ira; |
99b1c316 | 397 | class target_ira_int default_target_ira_int; |
afcc66c4 RS |
398 | #if SWITCHABLE_TARGET |
399 | struct target_ira *this_target_ira = &default_target_ira; | |
99b1c316 | 400 | class target_ira_int *this_target_ira_int = &default_target_ira_int; |
afcc66c4 RS |
401 | #endif |
402 | ||
058e97ec VM |
403 | /* A modified value of flag `-fira-verbose' used internally. */ |
404 | int internal_flag_ira_verbose; | |
405 | ||
406 | /* Dump file of the allocator if it is not NULL. */ | |
407 | FILE *ira_dump_file; | |
408 | ||
058e97ec VM |
409 | /* The number of elements in the following array. */ |
410 | int ira_spilled_reg_stack_slots_num; | |
411 | ||
412 | /* The following array contains info about spilled pseudo-registers | |
413 | stack slots used in current function so far. */ | |
99b1c316 | 414 | class ira_spilled_reg_stack_slot *ira_spilled_reg_stack_slots; |
058e97ec | 415 | |
ae2b9cb6 BS |
416 | /* Correspondingly overall cost of the allocation, overall cost before |
417 | reload, cost of the allocnos assigned to hard-registers, cost of | |
418 | the allocnos assigned to memory, cost of loads, stores and register | |
419 | move insns generated for pseudo-register live range splitting (see | |
420 | ira-emit.c). */ | |
2bf7560b VM |
421 | int64_t ira_overall_cost, overall_cost_before; |
422 | int64_t ira_reg_cost, ira_mem_cost; | |
423 | int64_t ira_load_cost, ira_store_cost, ira_shuffle_cost; | |
058e97ec VM |
424 | int ira_move_loops_num, ira_additional_jumps_num; |
425 | ||
2af2dbdc VM |
426 | /* All registers that can be eliminated. */ |
427 | ||
428 | HARD_REG_SET eliminable_regset; | |
429 | ||
70cc3288 VM |
430 | /* Value of max_reg_num () before IRA work start. This value helps |
431 | us to recognize a situation when new pseudos were created during | |
432 | IRA work. */ | |
433 | static int max_regno_before_ira; | |
434 | ||
058e97ec VM |
435 | /* Temporary hard reg set used for a different calculation. */ |
436 | static HARD_REG_SET temp_hard_regset; | |
437 | ||
e80ccebc RS |
438 | #define last_mode_for_init_move_cost \ |
439 | (this_target_ira_int->x_last_mode_for_init_move_cost) | |
058e97ec VM |
440 | \f |
441 | ||
442 | /* The function sets up the map IRA_REG_MODE_HARD_REGSET. */ | |
443 | static void | |
444 | setup_reg_mode_hard_regset (void) | |
445 | { | |
446 | int i, m, hard_regno; | |
447 | ||
448 | for (m = 0; m < NUM_MACHINE_MODES; m++) | |
449 | for (hard_regno = 0; hard_regno < FIRST_PSEUDO_REGISTER; hard_regno++) | |
450 | { | |
451 | CLEAR_HARD_REG_SET (ira_reg_mode_hard_regset[hard_regno][m]); | |
ad474626 RS |
452 | for (i = hard_regno_nregs (hard_regno, (machine_mode) m) - 1; |
453 | i >= 0; i--) | |
058e97ec VM |
454 | if (hard_regno + i < FIRST_PSEUDO_REGISTER) |
455 | SET_HARD_REG_BIT (ira_reg_mode_hard_regset[hard_regno][m], | |
456 | hard_regno + i); | |
457 | } | |
458 | } | |
459 | ||
460 | \f | |
afcc66c4 RS |
461 | #define no_unit_alloc_regs \ |
462 | (this_target_ira_int->x_no_unit_alloc_regs) | |
058e97ec VM |
463 | |
464 | /* The function sets up the three arrays declared above. */ | |
465 | static void | |
466 | setup_class_hard_regs (void) | |
467 | { | |
468 | int cl, i, hard_regno, n; | |
469 | HARD_REG_SET processed_hard_reg_set; | |
470 | ||
471 | ira_assert (SHRT_MAX >= FIRST_PSEUDO_REGISTER); | |
058e97ec VM |
472 | for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) |
473 | { | |
d15e5131 | 474 | temp_hard_regset = reg_class_contents[cl] & ~no_unit_alloc_regs; |
058e97ec | 475 | CLEAR_HARD_REG_SET (processed_hard_reg_set); |
7db7ed3c | 476 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
0583835c | 477 | { |
854edfcd VM |
478 | ira_non_ordered_class_hard_regs[cl][i] = -1; |
479 | ira_class_hard_reg_index[cl][i] = -1; | |
0583835c | 480 | } |
058e97ec VM |
481 | for (n = 0, i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
482 | { | |
483 | #ifdef REG_ALLOC_ORDER | |
484 | hard_regno = reg_alloc_order[i]; | |
485 | #else | |
486 | hard_regno = i; | |
b8698a0f | 487 | #endif |
058e97ec VM |
488 | if (TEST_HARD_REG_BIT (processed_hard_reg_set, hard_regno)) |
489 | continue; | |
490 | SET_HARD_REG_BIT (processed_hard_reg_set, hard_regno); | |
491 | if (! TEST_HARD_REG_BIT (temp_hard_regset, hard_regno)) | |
492 | ira_class_hard_reg_index[cl][hard_regno] = -1; | |
493 | else | |
494 | { | |
495 | ira_class_hard_reg_index[cl][hard_regno] = n; | |
496 | ira_class_hard_regs[cl][n++] = hard_regno; | |
497 | } | |
498 | } | |
499 | ira_class_hard_regs_num[cl] = n; | |
0583835c VM |
500 | for (n = 0, i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
501 | if (TEST_HARD_REG_BIT (temp_hard_regset, i)) | |
502 | ira_non_ordered_class_hard_regs[cl][n++] = i; | |
503 | ira_assert (ira_class_hard_regs_num[cl] == n); | |
058e97ec VM |
504 | } |
505 | } | |
506 | ||
058e97ec VM |
507 | /* Set up global variables defining info about hard registers for the |
508 | allocation. These depend on USE_HARD_FRAME_P whose TRUE value means | |
509 | that we can use the hard frame pointer for the allocation. */ | |
510 | static void | |
511 | setup_alloc_regs (bool use_hard_frame_p) | |
512 | { | |
5a733826 BS |
513 | #ifdef ADJUST_REG_ALLOC_ORDER |
514 | ADJUST_REG_ALLOC_ORDER; | |
515 | #endif | |
6576d245 | 516 | no_unit_alloc_regs = fixed_nonglobal_reg_set; |
058e97ec | 517 | if (! use_hard_frame_p) |
ff33d187 KCY |
518 | add_to_hard_reg_set (&no_unit_alloc_regs, Pmode, |
519 | HARD_FRAME_POINTER_REGNUM); | |
058e97ec | 520 | setup_class_hard_regs (); |
058e97ec VM |
521 | } |
522 | ||
523 | \f | |
524 | ||
1756cb66 VM |
525 | #define alloc_reg_class_subclasses \ |
526 | (this_target_ira_int->x_alloc_reg_class_subclasses) | |
527 | ||
528 | /* Initialize the table of subclasses of each reg class. */ | |
529 | static void | |
530 | setup_reg_subclasses (void) | |
531 | { | |
532 | int i, j; | |
533 | HARD_REG_SET temp_hard_regset2; | |
534 | ||
535 | for (i = 0; i < N_REG_CLASSES; i++) | |
536 | for (j = 0; j < N_REG_CLASSES; j++) | |
537 | alloc_reg_class_subclasses[i][j] = LIM_REG_CLASSES; | |
538 | ||
539 | for (i = 0; i < N_REG_CLASSES; i++) | |
540 | { | |
541 | if (i == (int) NO_REGS) | |
542 | continue; | |
543 | ||
d15e5131 | 544 | temp_hard_regset = reg_class_contents[i] & ~no_unit_alloc_regs; |
1756cb66 VM |
545 | if (hard_reg_set_empty_p (temp_hard_regset)) |
546 | continue; | |
547 | for (j = 0; j < N_REG_CLASSES; j++) | |
548 | if (i != j) | |
549 | { | |
550 | enum reg_class *p; | |
551 | ||
d15e5131 | 552 | temp_hard_regset2 = reg_class_contents[j] & ~no_unit_alloc_regs; |
1756cb66 VM |
553 | if (! hard_reg_set_subset_p (temp_hard_regset, |
554 | temp_hard_regset2)) | |
555 | continue; | |
556 | p = &alloc_reg_class_subclasses[j][0]; | |
557 | while (*p != LIM_REG_CLASSES) p++; | |
558 | *p = (enum reg_class) i; | |
559 | } | |
560 | } | |
561 | } | |
562 | ||
563 | \f | |
564 | ||
565 | /* Set up IRA_MEMORY_MOVE_COST and IRA_MAX_MEMORY_MOVE_COST. */ | |
058e97ec VM |
566 | static void |
567 | setup_class_subset_and_memory_move_costs (void) | |
568 | { | |
1756cb66 | 569 | int cl, cl2, mode, cost; |
058e97ec VM |
570 | HARD_REG_SET temp_hard_regset2; |
571 | ||
572 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
573 | ira_memory_move_cost[mode][NO_REGS][0] | |
574 | = ira_memory_move_cost[mode][NO_REGS][1] = SHRT_MAX; | |
575 | for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) | |
576 | { | |
577 | if (cl != (int) NO_REGS) | |
578 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
579 | { | |
1756cb66 VM |
580 | ira_max_memory_move_cost[mode][cl][0] |
581 | = ira_memory_move_cost[mode][cl][0] | |
ef4bddc2 | 582 | = memory_move_cost ((machine_mode) mode, |
6f76a878 | 583 | (reg_class_t) cl, false); |
1756cb66 VM |
584 | ira_max_memory_move_cost[mode][cl][1] |
585 | = ira_memory_move_cost[mode][cl][1] | |
ef4bddc2 | 586 | = memory_move_cost ((machine_mode) mode, |
6f76a878 | 587 | (reg_class_t) cl, true); |
058e97ec VM |
588 | /* Costs for NO_REGS are used in cost calculation on the |
589 | 1st pass when the preferred register classes are not | |
590 | known yet. In this case we take the best scenario. */ | |
591 | if (ira_memory_move_cost[mode][NO_REGS][0] | |
592 | > ira_memory_move_cost[mode][cl][0]) | |
1756cb66 VM |
593 | ira_max_memory_move_cost[mode][NO_REGS][0] |
594 | = ira_memory_move_cost[mode][NO_REGS][0] | |
058e97ec VM |
595 | = ira_memory_move_cost[mode][cl][0]; |
596 | if (ira_memory_move_cost[mode][NO_REGS][1] | |
597 | > ira_memory_move_cost[mode][cl][1]) | |
1756cb66 VM |
598 | ira_max_memory_move_cost[mode][NO_REGS][1] |
599 | = ira_memory_move_cost[mode][NO_REGS][1] | |
058e97ec VM |
600 | = ira_memory_move_cost[mode][cl][1]; |
601 | } | |
058e97ec | 602 | } |
1756cb66 VM |
603 | for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) |
604 | for (cl2 = (int) N_REG_CLASSES - 1; cl2 >= 0; cl2--) | |
605 | { | |
d15e5131 RS |
606 | temp_hard_regset = reg_class_contents[cl] & ~no_unit_alloc_regs; |
607 | temp_hard_regset2 = reg_class_contents[cl2] & ~no_unit_alloc_regs; | |
1756cb66 VM |
608 | ira_class_subset_p[cl][cl2] |
609 | = hard_reg_set_subset_p (temp_hard_regset, temp_hard_regset2); | |
610 | if (! hard_reg_set_empty_p (temp_hard_regset2) | |
611 | && hard_reg_set_subset_p (reg_class_contents[cl2], | |
612 | reg_class_contents[cl])) | |
613 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
614 | { | |
615 | cost = ira_memory_move_cost[mode][cl2][0]; | |
616 | if (cost > ira_max_memory_move_cost[mode][cl][0]) | |
617 | ira_max_memory_move_cost[mode][cl][0] = cost; | |
618 | cost = ira_memory_move_cost[mode][cl2][1]; | |
619 | if (cost > ira_max_memory_move_cost[mode][cl][1]) | |
620 | ira_max_memory_move_cost[mode][cl][1] = cost; | |
621 | } | |
622 | } | |
623 | for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) | |
624 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
625 | { | |
626 | ira_memory_move_cost[mode][cl][0] | |
627 | = ira_max_memory_move_cost[mode][cl][0]; | |
628 | ira_memory_move_cost[mode][cl][1] | |
629 | = ira_max_memory_move_cost[mode][cl][1]; | |
630 | } | |
631 | setup_reg_subclasses (); | |
058e97ec VM |
632 | } |
633 | ||
634 | \f | |
635 | ||
636 | /* Define the following macro if allocation through malloc if | |
637 | preferable. */ | |
638 | #define IRA_NO_OBSTACK | |
639 | ||
640 | #ifndef IRA_NO_OBSTACK | |
641 | /* Obstack used for storing all dynamic data (except bitmaps) of the | |
642 | IRA. */ | |
643 | static struct obstack ira_obstack; | |
644 | #endif | |
645 | ||
646 | /* Obstack used for storing all bitmaps of the IRA. */ | |
647 | static struct bitmap_obstack ira_bitmap_obstack; | |
648 | ||
649 | /* Allocate memory of size LEN for IRA data. */ | |
650 | void * | |
651 | ira_allocate (size_t len) | |
652 | { | |
653 | void *res; | |
654 | ||
655 | #ifndef IRA_NO_OBSTACK | |
656 | res = obstack_alloc (&ira_obstack, len); | |
657 | #else | |
658 | res = xmalloc (len); | |
659 | #endif | |
660 | return res; | |
661 | } | |
662 | ||
058e97ec VM |
663 | /* Free memory ADDR allocated for IRA data. */ |
664 | void | |
665 | ira_free (void *addr ATTRIBUTE_UNUSED) | |
666 | { | |
667 | #ifndef IRA_NO_OBSTACK | |
668 | /* do nothing */ | |
669 | #else | |
670 | free (addr); | |
671 | #endif | |
672 | } | |
673 | ||
674 | ||
675 | /* Allocate and returns bitmap for IRA. */ | |
676 | bitmap | |
677 | ira_allocate_bitmap (void) | |
678 | { | |
679 | return BITMAP_ALLOC (&ira_bitmap_obstack); | |
680 | } | |
681 | ||
682 | /* Free bitmap B allocated for IRA. */ | |
683 | void | |
684 | ira_free_bitmap (bitmap b ATTRIBUTE_UNUSED) | |
685 | { | |
686 | /* do nothing */ | |
687 | } | |
688 | ||
689 | \f | |
690 | ||
691 | /* Output information about allocation of all allocnos (except for | |
692 | caps) into file F. */ | |
693 | void | |
694 | ira_print_disposition (FILE *f) | |
695 | { | |
696 | int i, n, max_regno; | |
697 | ira_allocno_t a; | |
698 | basic_block bb; | |
699 | ||
700 | fprintf (f, "Disposition:"); | |
701 | max_regno = max_reg_num (); | |
702 | for (n = 0, i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
703 | for (a = ira_regno_allocno_map[i]; | |
704 | a != NULL; | |
705 | a = ALLOCNO_NEXT_REGNO_ALLOCNO (a)) | |
706 | { | |
707 | if (n % 4 == 0) | |
708 | fprintf (f, "\n"); | |
709 | n++; | |
710 | fprintf (f, " %4d:r%-4d", ALLOCNO_NUM (a), ALLOCNO_REGNO (a)); | |
711 | if ((bb = ALLOCNO_LOOP_TREE_NODE (a)->bb) != NULL) | |
712 | fprintf (f, "b%-3d", bb->index); | |
713 | else | |
2608d841 | 714 | fprintf (f, "l%-3d", ALLOCNO_LOOP_TREE_NODE (a)->loop_num); |
058e97ec VM |
715 | if (ALLOCNO_HARD_REGNO (a) >= 0) |
716 | fprintf (f, " %3d", ALLOCNO_HARD_REGNO (a)); | |
717 | else | |
718 | fprintf (f, " mem"); | |
719 | } | |
720 | fprintf (f, "\n"); | |
721 | } | |
722 | ||
723 | /* Outputs information about allocation of all allocnos into | |
724 | stderr. */ | |
725 | void | |
726 | ira_debug_disposition (void) | |
727 | { | |
728 | ira_print_disposition (stderr); | |
729 | } | |
730 | ||
731 | \f | |
058e97ec | 732 | |
1756cb66 VM |
733 | /* Set up ira_stack_reg_pressure_class which is the biggest pressure |
734 | register class containing stack registers or NO_REGS if there are | |
735 | no stack registers. To find this class, we iterate through all | |
736 | register pressure classes and choose the first register pressure | |
737 | class containing all the stack registers and having the biggest | |
738 | size. */ | |
fe82cdfb | 739 | static void |
1756cb66 VM |
740 | setup_stack_reg_pressure_class (void) |
741 | { | |
742 | ira_stack_reg_pressure_class = NO_REGS; | |
743 | #ifdef STACK_REGS | |
744 | { | |
745 | int i, best, size; | |
746 | enum reg_class cl; | |
747 | HARD_REG_SET temp_hard_regset2; | |
748 | ||
749 | CLEAR_HARD_REG_SET (temp_hard_regset); | |
750 | for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++) | |
751 | SET_HARD_REG_BIT (temp_hard_regset, i); | |
752 | best = 0; | |
753 | for (i = 0; i < ira_pressure_classes_num; i++) | |
754 | { | |
755 | cl = ira_pressure_classes[i]; | |
dc333d8f | 756 | temp_hard_regset2 = temp_hard_regset & reg_class_contents[cl]; |
1756cb66 VM |
757 | size = hard_reg_set_size (temp_hard_regset2); |
758 | if (best < size) | |
759 | { | |
760 | best = size; | |
761 | ira_stack_reg_pressure_class = cl; | |
762 | } | |
763 | } | |
764 | } | |
765 | #endif | |
766 | } | |
767 | ||
768 | /* Find pressure classes which are register classes for which we | |
769 | calculate register pressure in IRA, register pressure sensitive | |
770 | insn scheduling, and register pressure sensitive loop invariant | |
771 | motion. | |
772 | ||
773 | To make register pressure calculation easy, we always use | |
774 | non-intersected register pressure classes. A move of hard | |
775 | registers from one register pressure class is not more expensive | |
776 | than load and store of the hard registers. Most likely an allocno | |
777 | class will be a subset of a register pressure class and in many | |
778 | cases a register pressure class. That makes usage of register | |
779 | pressure classes a good approximation to find a high register | |
780 | pressure. */ | |
781 | static void | |
782 | setup_pressure_classes (void) | |
058e97ec | 783 | { |
1756cb66 VM |
784 | int cost, i, n, curr; |
785 | int cl, cl2; | |
786 | enum reg_class pressure_classes[N_REG_CLASSES]; | |
787 | int m; | |
058e97ec | 788 | HARD_REG_SET temp_hard_regset2; |
1756cb66 | 789 | bool insert_p; |
058e97ec | 790 | |
b4ff394c PH |
791 | if (targetm.compute_pressure_classes) |
792 | n = targetm.compute_pressure_classes (pressure_classes); | |
793 | else | |
794 | { | |
795 | n = 0; | |
796 | for (cl = 0; cl < N_REG_CLASSES; cl++) | |
1756cb66 | 797 | { |
b4ff394c PH |
798 | if (ira_class_hard_regs_num[cl] == 0) |
799 | continue; | |
800 | if (ira_class_hard_regs_num[cl] != 1 | |
801 | /* A register class without subclasses may contain a few | |
802 | hard registers and movement between them is costly | |
803 | (e.g. SPARC FPCC registers). We still should consider it | |
804 | as a candidate for a pressure class. */ | |
805 | && alloc_reg_class_subclasses[cl][0] < cl) | |
113a5be6 | 806 | { |
b4ff394c PH |
807 | /* Check that the moves between any hard registers of the |
808 | current class are not more expensive for a legal mode | |
809 | than load/store of the hard registers of the current | |
810 | class. Such class is a potential candidate to be a | |
811 | register pressure class. */ | |
812 | for (m = 0; m < NUM_MACHINE_MODES; m++) | |
813 | { | |
d15e5131 RS |
814 | temp_hard_regset |
815 | = (reg_class_contents[cl] | |
816 | & ~(no_unit_alloc_regs | |
817 | | ira_prohibited_class_mode_regs[cl][m])); | |
b4ff394c PH |
818 | if (hard_reg_set_empty_p (temp_hard_regset)) |
819 | continue; | |
820 | ira_init_register_move_cost_if_necessary ((machine_mode) m); | |
821 | cost = ira_register_move_cost[m][cl][cl]; | |
822 | if (cost <= ira_max_memory_move_cost[m][cl][1] | |
823 | || cost <= ira_max_memory_move_cost[m][cl][0]) | |
824 | break; | |
825 | } | |
826 | if (m >= NUM_MACHINE_MODES) | |
113a5be6 | 827 | continue; |
113a5be6 | 828 | } |
b4ff394c PH |
829 | curr = 0; |
830 | insert_p = true; | |
d15e5131 | 831 | temp_hard_regset = reg_class_contents[cl] & ~no_unit_alloc_regs; |
b4ff394c PH |
832 | /* Remove so far added pressure classes which are subset of the |
833 | current candidate class. Prefer GENERAL_REGS as a pressure | |
834 | register class to another class containing the same | |
835 | allocatable hard registers. We do this because machine | |
836 | dependent cost hooks might give wrong costs for the latter | |
837 | class but always give the right cost for the former class | |
838 | (GENERAL_REGS). */ | |
839 | for (i = 0; i < n; i++) | |
1756cb66 | 840 | { |
b4ff394c | 841 | cl2 = pressure_classes[i]; |
d15e5131 RS |
842 | temp_hard_regset2 = (reg_class_contents[cl2] |
843 | & ~no_unit_alloc_regs); | |
b4ff394c | 844 | if (hard_reg_set_subset_p (temp_hard_regset, temp_hard_regset2) |
a8579651 | 845 | && (temp_hard_regset != temp_hard_regset2 |
b4ff394c PH |
846 | || cl2 == (int) GENERAL_REGS)) |
847 | { | |
848 | pressure_classes[curr++] = (enum reg_class) cl2; | |
849 | insert_p = false; | |
850 | continue; | |
851 | } | |
852 | if (hard_reg_set_subset_p (temp_hard_regset2, temp_hard_regset) | |
a8579651 | 853 | && (temp_hard_regset2 != temp_hard_regset |
b4ff394c PH |
854 | || cl == (int) GENERAL_REGS)) |
855 | continue; | |
a8579651 | 856 | if (temp_hard_regset2 == temp_hard_regset) |
b4ff394c | 857 | insert_p = false; |
1756cb66 | 858 | pressure_classes[curr++] = (enum reg_class) cl2; |
1756cb66 | 859 | } |
b4ff394c PH |
860 | /* If the current candidate is a subset of a so far added |
861 | pressure class, don't add it to the list of the pressure | |
862 | classes. */ | |
863 | if (insert_p) | |
864 | pressure_classes[curr++] = (enum reg_class) cl; | |
865 | n = curr; | |
1756cb66 | 866 | } |
fe82cdfb | 867 | } |
1756cb66 | 868 | #ifdef ENABLE_IRA_CHECKING |
113a5be6 VM |
869 | { |
870 | HARD_REG_SET ignore_hard_regs; | |
871 | ||
872 | /* Check pressure classes correctness: here we check that hard | |
873 | registers from all register pressure classes contains all hard | |
874 | registers available for the allocation. */ | |
875 | CLEAR_HARD_REG_SET (temp_hard_regset); | |
876 | CLEAR_HARD_REG_SET (temp_hard_regset2); | |
6576d245 | 877 | ignore_hard_regs = no_unit_alloc_regs; |
113a5be6 VM |
878 | for (cl = 0; cl < LIM_REG_CLASSES; cl++) |
879 | { | |
880 | /* For some targets (like MIPS with MD_REGS), there are some | |
881 | classes with hard registers available for allocation but | |
882 | not able to hold value of any mode. */ | |
883 | for (m = 0; m < NUM_MACHINE_MODES; m++) | |
884 | if (contains_reg_of_mode[cl][m]) | |
885 | break; | |
886 | if (m >= NUM_MACHINE_MODES) | |
887 | { | |
44942965 | 888 | ignore_hard_regs |= reg_class_contents[cl]; |
113a5be6 VM |
889 | continue; |
890 | } | |
891 | for (i = 0; i < n; i++) | |
892 | if ((int) pressure_classes[i] == cl) | |
893 | break; | |
44942965 | 894 | temp_hard_regset2 |= reg_class_contents[cl]; |
113a5be6 | 895 | if (i < n) |
44942965 | 896 | temp_hard_regset |= reg_class_contents[cl]; |
113a5be6 VM |
897 | } |
898 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
df3e3493 | 899 | /* Some targets (like SPARC with ICC reg) have allocatable regs |
113a5be6 VM |
900 | for which no reg class is defined. */ |
901 | if (REGNO_REG_CLASS (i) == NO_REGS) | |
902 | SET_HARD_REG_BIT (ignore_hard_regs, i); | |
d15e5131 RS |
903 | temp_hard_regset &= ~ignore_hard_regs; |
904 | temp_hard_regset2 &= ~ignore_hard_regs; | |
113a5be6 VM |
905 | ira_assert (hard_reg_set_subset_p (temp_hard_regset2, temp_hard_regset)); |
906 | } | |
1756cb66 VM |
907 | #endif |
908 | ira_pressure_classes_num = 0; | |
909 | for (i = 0; i < n; i++) | |
910 | { | |
911 | cl = (int) pressure_classes[i]; | |
912 | ira_reg_pressure_class_p[cl] = true; | |
913 | ira_pressure_classes[ira_pressure_classes_num++] = (enum reg_class) cl; | |
914 | } | |
915 | setup_stack_reg_pressure_class (); | |
058e97ec VM |
916 | } |
917 | ||
165f639c VM |
918 | /* Set up IRA_UNIFORM_CLASS_P. Uniform class is a register class |
919 | whose register move cost between any registers of the class is the | |
920 | same as for all its subclasses. We use the data to speed up the | |
921 | 2nd pass of calculations of allocno costs. */ | |
922 | static void | |
923 | setup_uniform_class_p (void) | |
924 | { | |
925 | int i, cl, cl2, m; | |
926 | ||
927 | for (cl = 0; cl < N_REG_CLASSES; cl++) | |
928 | { | |
929 | ira_uniform_class_p[cl] = false; | |
930 | if (ira_class_hard_regs_num[cl] == 0) | |
931 | continue; | |
67914693 | 932 | /* We cannot use alloc_reg_class_subclasses here because move |
165f639c VM |
933 | cost hooks does not take into account that some registers are |
934 | unavailable for the subtarget. E.g. for i686, INT_SSE_REGS | |
935 | is element of alloc_reg_class_subclasses for GENERAL_REGS | |
936 | because SSE regs are unavailable. */ | |
937 | for (i = 0; (cl2 = reg_class_subclasses[cl][i]) != LIM_REG_CLASSES; i++) | |
938 | { | |
939 | if (ira_class_hard_regs_num[cl2] == 0) | |
940 | continue; | |
941 | for (m = 0; m < NUM_MACHINE_MODES; m++) | |
942 | if (contains_reg_of_mode[cl][m] && contains_reg_of_mode[cl2][m]) | |
943 | { | |
ef4bddc2 | 944 | ira_init_register_move_cost_if_necessary ((machine_mode) m); |
165f639c VM |
945 | if (ira_register_move_cost[m][cl][cl] |
946 | != ira_register_move_cost[m][cl2][cl2]) | |
947 | break; | |
948 | } | |
949 | if (m < NUM_MACHINE_MODES) | |
950 | break; | |
951 | } | |
952 | if (cl2 == LIM_REG_CLASSES) | |
953 | ira_uniform_class_p[cl] = true; | |
954 | } | |
955 | } | |
956 | ||
1756cb66 VM |
957 | /* Set up IRA_ALLOCNO_CLASSES, IRA_ALLOCNO_CLASSES_NUM, |
958 | IRA_IMPORTANT_CLASSES, and IRA_IMPORTANT_CLASSES_NUM. | |
959 | ||
df3e3493 | 960 | Target may have many subtargets and not all target hard registers can |
67914693 | 961 | be used for allocation, e.g. x86 port in 32-bit mode cannot use |
1756cb66 VM |
962 | hard registers introduced in x86-64 like r8-r15). Some classes |
963 | might have the same allocatable hard registers, e.g. INDEX_REGS | |
964 | and GENERAL_REGS in x86 port in 32-bit mode. To decrease different | |
965 | calculations efforts we introduce allocno classes which contain | |
966 | unique non-empty sets of allocatable hard-registers. | |
967 | ||
968 | Pseudo class cost calculation in ira-costs.c is very expensive. | |
969 | Therefore we are trying to decrease number of classes involved in | |
970 | such calculation. Register classes used in the cost calculation | |
971 | are called important classes. They are allocno classes and other | |
972 | non-empty classes whose allocatable hard register sets are inside | |
973 | of an allocno class hard register set. From the first sight, it | |
974 | looks like that they are just allocno classes. It is not true. In | |
975 | example of x86-port in 32-bit mode, allocno classes will contain | |
976 | GENERAL_REGS but not LEGACY_REGS (because allocatable hard | |
977 | registers are the same for the both classes). The important | |
978 | classes will contain GENERAL_REGS and LEGACY_REGS. It is done | |
979 | because a machine description insn constraint may refers for | |
980 | LEGACY_REGS and code in ira-costs.c is mostly base on investigation | |
981 | of the insn constraints. */ | |
058e97ec | 982 | static void |
1756cb66 | 983 | setup_allocno_and_important_classes (void) |
058e97ec | 984 | { |
32e8bb8e | 985 | int i, j, n, cl; |
db1a8d98 | 986 | bool set_p; |
058e97ec | 987 | HARD_REG_SET temp_hard_regset2; |
7db7ed3c VM |
988 | static enum reg_class classes[LIM_REG_CLASSES + 1]; |
989 | ||
1756cb66 VM |
990 | n = 0; |
991 | /* Collect classes which contain unique sets of allocatable hard | |
992 | registers. Prefer GENERAL_REGS to other classes containing the | |
993 | same set of hard registers. */ | |
a58dfa49 | 994 | for (i = 0; i < LIM_REG_CLASSES; i++) |
99710245 | 995 | { |
d15e5131 | 996 | temp_hard_regset = reg_class_contents[i] & ~no_unit_alloc_regs; |
1756cb66 | 997 | for (j = 0; j < n; j++) |
7db7ed3c | 998 | { |
1756cb66 | 999 | cl = classes[j]; |
d15e5131 | 1000 | temp_hard_regset2 = reg_class_contents[cl] & ~no_unit_alloc_regs; |
a8579651 | 1001 | if (temp_hard_regset == temp_hard_regset2) |
1756cb66 | 1002 | break; |
7db7ed3c | 1003 | } |
e93f30a6 | 1004 | if (j >= n || targetm.additional_allocno_class_p (i)) |
1756cb66 VM |
1005 | classes[n++] = (enum reg_class) i; |
1006 | else if (i == GENERAL_REGS) | |
1007 | /* Prefer general regs. For i386 example, it means that | |
1008 | we prefer GENERAL_REGS over INDEX_REGS or LEGACY_REGS | |
1009 | (all of them consists of the same available hard | |
1010 | registers). */ | |
1011 | classes[j] = (enum reg_class) i; | |
7db7ed3c | 1012 | } |
1756cb66 | 1013 | classes[n] = LIM_REG_CLASSES; |
058e97ec | 1014 | |
1756cb66 | 1015 | /* Set up classes which can be used for allocnos as classes |
df3e3493 | 1016 | containing non-empty unique sets of allocatable hard |
1756cb66 VM |
1017 | registers. */ |
1018 | ira_allocno_classes_num = 0; | |
058e97ec | 1019 | for (i = 0; (cl = classes[i]) != LIM_REG_CLASSES; i++) |
3e575fe2 | 1020 | if (ira_class_hard_regs_num[cl] > 0) |
1756cb66 | 1021 | ira_allocno_classes[ira_allocno_classes_num++] = (enum reg_class) cl; |
058e97ec | 1022 | ira_important_classes_num = 0; |
1756cb66 VM |
1023 | /* Add non-allocno classes containing to non-empty set of |
1024 | allocatable hard regs. */ | |
058e97ec | 1025 | for (cl = 0; cl < N_REG_CLASSES; cl++) |
3e575fe2 RS |
1026 | if (ira_class_hard_regs_num[cl] > 0) |
1027 | { | |
d15e5131 | 1028 | temp_hard_regset = reg_class_contents[cl] & ~no_unit_alloc_regs; |
3e575fe2 RS |
1029 | set_p = false; |
1030 | for (j = 0; j < ira_allocno_classes_num; j++) | |
1031 | { | |
d15e5131 RS |
1032 | temp_hard_regset2 = (reg_class_contents[ira_allocno_classes[j]] |
1033 | & ~no_unit_alloc_regs); | |
3e575fe2 RS |
1034 | if ((enum reg_class) cl == ira_allocno_classes[j]) |
1035 | break; | |
1036 | else if (hard_reg_set_subset_p (temp_hard_regset, | |
1037 | temp_hard_regset2)) | |
1038 | set_p = true; | |
1039 | } | |
1040 | if (set_p && j >= ira_allocno_classes_num) | |
1041 | ira_important_classes[ira_important_classes_num++] | |
1042 | = (enum reg_class) cl; | |
1043 | } | |
1756cb66 VM |
1044 | /* Now add allocno classes to the important classes. */ |
1045 | for (j = 0; j < ira_allocno_classes_num; j++) | |
db1a8d98 | 1046 | ira_important_classes[ira_important_classes_num++] |
1756cb66 VM |
1047 | = ira_allocno_classes[j]; |
1048 | for (cl = 0; cl < N_REG_CLASSES; cl++) | |
1049 | { | |
1050 | ira_reg_allocno_class_p[cl] = false; | |
1051 | ira_reg_pressure_class_p[cl] = false; | |
1052 | } | |
1053 | for (j = 0; j < ira_allocno_classes_num; j++) | |
1054 | ira_reg_allocno_class_p[ira_allocno_classes[j]] = true; | |
1055 | setup_pressure_classes (); | |
165f639c | 1056 | setup_uniform_class_p (); |
058e97ec | 1057 | } |
058e97ec | 1058 | |
1756cb66 VM |
1059 | /* Setup translation in CLASS_TRANSLATE of all classes into a class |
1060 | given by array CLASSES of length CLASSES_NUM. The function is used | |
1061 | make translation any reg class to an allocno class or to an | |
1062 | pressure class. This translation is necessary for some | |
1063 | calculations when we can use only allocno or pressure classes and | |
1064 | such translation represents an approximate representation of all | |
1065 | classes. | |
1066 | ||
1067 | The translation in case when allocatable hard register set of a | |
1068 | given class is subset of allocatable hard register set of a class | |
1069 | in CLASSES is pretty simple. We use smallest classes from CLASSES | |
1070 | containing a given class. If allocatable hard register set of a | |
1071 | given class is not a subset of any corresponding set of a class | |
1072 | from CLASSES, we use the cheapest (with load/store point of view) | |
2b9c63a2 | 1073 | class from CLASSES whose set intersects with given class set. */ |
058e97ec | 1074 | static void |
1756cb66 VM |
1075 | setup_class_translate_array (enum reg_class *class_translate, |
1076 | int classes_num, enum reg_class *classes) | |
058e97ec | 1077 | { |
32e8bb8e | 1078 | int cl, mode; |
1756cb66 | 1079 | enum reg_class aclass, best_class, *cl_ptr; |
058e97ec VM |
1080 | int i, cost, min_cost, best_cost; |
1081 | ||
1082 | for (cl = 0; cl < N_REG_CLASSES; cl++) | |
1756cb66 | 1083 | class_translate[cl] = NO_REGS; |
b8698a0f | 1084 | |
1756cb66 | 1085 | for (i = 0; i < classes_num; i++) |
058e97ec | 1086 | { |
1756cb66 VM |
1087 | aclass = classes[i]; |
1088 | for (cl_ptr = &alloc_reg_class_subclasses[aclass][0]; | |
1089 | (cl = *cl_ptr) != LIM_REG_CLASSES; | |
1090 | cl_ptr++) | |
1091 | if (class_translate[cl] == NO_REGS) | |
1092 | class_translate[cl] = aclass; | |
1093 | class_translate[aclass] = aclass; | |
058e97ec | 1094 | } |
1756cb66 VM |
1095 | /* For classes which are not fully covered by one of given classes |
1096 | (in other words covered by more one given class), use the | |
1097 | cheapest class. */ | |
058e97ec VM |
1098 | for (cl = 0; cl < N_REG_CLASSES; cl++) |
1099 | { | |
1756cb66 | 1100 | if (cl == NO_REGS || class_translate[cl] != NO_REGS) |
058e97ec VM |
1101 | continue; |
1102 | best_class = NO_REGS; | |
1103 | best_cost = INT_MAX; | |
1756cb66 | 1104 | for (i = 0; i < classes_num; i++) |
058e97ec | 1105 | { |
1756cb66 | 1106 | aclass = classes[i]; |
dc333d8f | 1107 | temp_hard_regset = (reg_class_contents[aclass] |
d15e5131 RS |
1108 | & reg_class_contents[cl] |
1109 | & ~no_unit_alloc_regs); | |
4f341ea0 | 1110 | if (! hard_reg_set_empty_p (temp_hard_regset)) |
058e97ec VM |
1111 | { |
1112 | min_cost = INT_MAX; | |
1113 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
1114 | { | |
761a8eb7 VM |
1115 | cost = (ira_memory_move_cost[mode][aclass][0] |
1116 | + ira_memory_move_cost[mode][aclass][1]); | |
058e97ec VM |
1117 | if (min_cost > cost) |
1118 | min_cost = cost; | |
1119 | } | |
1120 | if (best_class == NO_REGS || best_cost > min_cost) | |
1121 | { | |
1756cb66 | 1122 | best_class = aclass; |
058e97ec VM |
1123 | best_cost = min_cost; |
1124 | } | |
1125 | } | |
1126 | } | |
1756cb66 | 1127 | class_translate[cl] = best_class; |
058e97ec VM |
1128 | } |
1129 | } | |
058e97ec | 1130 | |
1756cb66 VM |
1131 | /* Set up array IRA_ALLOCNO_CLASS_TRANSLATE and |
1132 | IRA_PRESSURE_CLASS_TRANSLATE. */ | |
1133 | static void | |
1134 | setup_class_translate (void) | |
1135 | { | |
1136 | setup_class_translate_array (ira_allocno_class_translate, | |
1137 | ira_allocno_classes_num, ira_allocno_classes); | |
1138 | setup_class_translate_array (ira_pressure_class_translate, | |
1139 | ira_pressure_classes_num, ira_pressure_classes); | |
1140 | } | |
1141 | ||
1142 | /* Order numbers of allocno classes in original target allocno class | |
1143 | array, -1 for non-allocno classes. */ | |
1144 | static int allocno_class_order[N_REG_CLASSES]; | |
db1a8d98 VM |
1145 | |
1146 | /* The function used to sort the important classes. */ | |
1147 | static int | |
1148 | comp_reg_classes_func (const void *v1p, const void *v2p) | |
1149 | { | |
1150 | enum reg_class cl1 = *(const enum reg_class *) v1p; | |
1151 | enum reg_class cl2 = *(const enum reg_class *) v2p; | |
1756cb66 | 1152 | enum reg_class tcl1, tcl2; |
db1a8d98 VM |
1153 | int diff; |
1154 | ||
1756cb66 VM |
1155 | tcl1 = ira_allocno_class_translate[cl1]; |
1156 | tcl2 = ira_allocno_class_translate[cl2]; | |
1157 | if (tcl1 != NO_REGS && tcl2 != NO_REGS | |
1158 | && (diff = allocno_class_order[tcl1] - allocno_class_order[tcl2]) != 0) | |
db1a8d98 VM |
1159 | return diff; |
1160 | return (int) cl1 - (int) cl2; | |
1161 | } | |
1162 | ||
1756cb66 VM |
1163 | /* For correct work of function setup_reg_class_relation we need to |
1164 | reorder important classes according to the order of their allocno | |
1165 | classes. It places important classes containing the same | |
1166 | allocatable hard register set adjacent to each other and allocno | |
1167 | class with the allocatable hard register set right after the other | |
1168 | important classes with the same set. | |
1169 | ||
1170 | In example from comments of function | |
1171 | setup_allocno_and_important_classes, it places LEGACY_REGS and | |
1172 | GENERAL_REGS close to each other and GENERAL_REGS is after | |
1173 | LEGACY_REGS. */ | |
db1a8d98 VM |
1174 | static void |
1175 | reorder_important_classes (void) | |
1176 | { | |
1177 | int i; | |
1178 | ||
1179 | for (i = 0; i < N_REG_CLASSES; i++) | |
1756cb66 VM |
1180 | allocno_class_order[i] = -1; |
1181 | for (i = 0; i < ira_allocno_classes_num; i++) | |
1182 | allocno_class_order[ira_allocno_classes[i]] = i; | |
db1a8d98 VM |
1183 | qsort (ira_important_classes, ira_important_classes_num, |
1184 | sizeof (enum reg_class), comp_reg_classes_func); | |
1756cb66 VM |
1185 | for (i = 0; i < ira_important_classes_num; i++) |
1186 | ira_important_class_nums[ira_important_classes[i]] = i; | |
db1a8d98 VM |
1187 | } |
1188 | ||
1756cb66 VM |
1189 | /* Set up IRA_REG_CLASS_SUBUNION, IRA_REG_CLASS_SUPERUNION, |
1190 | IRA_REG_CLASS_SUPER_CLASSES, IRA_REG_CLASSES_INTERSECT, and | |
1191 | IRA_REG_CLASSES_INTERSECT_P. For the meaning of the relations, | |
1192 | please see corresponding comments in ira-int.h. */ | |
058e97ec | 1193 | static void |
7db7ed3c | 1194 | setup_reg_class_relations (void) |
058e97ec VM |
1195 | { |
1196 | int i, cl1, cl2, cl3; | |
1197 | HARD_REG_SET intersection_set, union_set, temp_set2; | |
7db7ed3c | 1198 | bool important_class_p[N_REG_CLASSES]; |
058e97ec | 1199 | |
7db7ed3c VM |
1200 | memset (important_class_p, 0, sizeof (important_class_p)); |
1201 | for (i = 0; i < ira_important_classes_num; i++) | |
1202 | important_class_p[ira_important_classes[i]] = true; | |
058e97ec VM |
1203 | for (cl1 = 0; cl1 < N_REG_CLASSES; cl1++) |
1204 | { | |
7db7ed3c | 1205 | ira_reg_class_super_classes[cl1][0] = LIM_REG_CLASSES; |
058e97ec VM |
1206 | for (cl2 = 0; cl2 < N_REG_CLASSES; cl2++) |
1207 | { | |
7db7ed3c | 1208 | ira_reg_classes_intersect_p[cl1][cl2] = false; |
058e97ec | 1209 | ira_reg_class_intersect[cl1][cl2] = NO_REGS; |
55a2c322 | 1210 | ira_reg_class_subset[cl1][cl2] = NO_REGS; |
d15e5131 RS |
1211 | temp_hard_regset = reg_class_contents[cl1] & ~no_unit_alloc_regs; |
1212 | temp_set2 = reg_class_contents[cl2] & ~no_unit_alloc_regs; | |
4f341ea0 RS |
1213 | if (hard_reg_set_empty_p (temp_hard_regset) |
1214 | && hard_reg_set_empty_p (temp_set2)) | |
058e97ec | 1215 | { |
1756cb66 VM |
1216 | /* The both classes have no allocatable hard registers |
1217 | -- take all class hard registers into account and use | |
1218 | reg_class_subunion and reg_class_superunion. */ | |
058e97ec VM |
1219 | for (i = 0;; i++) |
1220 | { | |
1221 | cl3 = reg_class_subclasses[cl1][i]; | |
1222 | if (cl3 == LIM_REG_CLASSES) | |
1223 | break; | |
1224 | if (reg_class_subset_p (ira_reg_class_intersect[cl1][cl2], | |
bbbbb16a ILT |
1225 | (enum reg_class) cl3)) |
1226 | ira_reg_class_intersect[cl1][cl2] = (enum reg_class) cl3; | |
058e97ec | 1227 | } |
1756cb66 VM |
1228 | ira_reg_class_subunion[cl1][cl2] = reg_class_subunion[cl1][cl2]; |
1229 | ira_reg_class_superunion[cl1][cl2] = reg_class_superunion[cl1][cl2]; | |
058e97ec VM |
1230 | continue; |
1231 | } | |
7db7ed3c VM |
1232 | ira_reg_classes_intersect_p[cl1][cl2] |
1233 | = hard_reg_set_intersect_p (temp_hard_regset, temp_set2); | |
1234 | if (important_class_p[cl1] && important_class_p[cl2] | |
1235 | && hard_reg_set_subset_p (temp_hard_regset, temp_set2)) | |
1236 | { | |
1756cb66 VM |
1237 | /* CL1 and CL2 are important classes and CL1 allocatable |
1238 | hard register set is inside of CL2 allocatable hard | |
1239 | registers -- make CL1 a superset of CL2. */ | |
7db7ed3c VM |
1240 | enum reg_class *p; |
1241 | ||
1242 | p = &ira_reg_class_super_classes[cl1][0]; | |
1243 | while (*p != LIM_REG_CLASSES) | |
1244 | p++; | |
1245 | *p++ = (enum reg_class) cl2; | |
1246 | *p = LIM_REG_CLASSES; | |
1247 | } | |
1756cb66 VM |
1248 | ira_reg_class_subunion[cl1][cl2] = NO_REGS; |
1249 | ira_reg_class_superunion[cl1][cl2] = NO_REGS; | |
dc333d8f | 1250 | intersection_set = (reg_class_contents[cl1] |
d15e5131 RS |
1251 | & reg_class_contents[cl2] |
1252 | & ~no_unit_alloc_regs); | |
1253 | union_set = ((reg_class_contents[cl1] | reg_class_contents[cl2]) | |
1254 | & ~no_unit_alloc_regs); | |
55a2c322 | 1255 | for (cl3 = 0; cl3 < N_REG_CLASSES; cl3++) |
058e97ec | 1256 | { |
d15e5131 | 1257 | temp_hard_regset = reg_class_contents[cl3] & ~no_unit_alloc_regs; |
058e97ec VM |
1258 | if (hard_reg_set_subset_p (temp_hard_regset, intersection_set)) |
1259 | { | |
1756cb66 VM |
1260 | /* CL3 allocatable hard register set is inside of |
1261 | intersection of allocatable hard register sets | |
1262 | of CL1 and CL2. */ | |
55a2c322 VM |
1263 | if (important_class_p[cl3]) |
1264 | { | |
6576d245 RS |
1265 | temp_set2 |
1266 | = (reg_class_contents | |
1267 | [ira_reg_class_intersect[cl1][cl2]]); | |
d15e5131 | 1268 | temp_set2 &= ~no_unit_alloc_regs; |
55a2c322 VM |
1269 | if (! hard_reg_set_subset_p (temp_hard_regset, temp_set2) |
1270 | /* If the allocatable hard register sets are | |
1271 | the same, prefer GENERAL_REGS or the | |
1272 | smallest class for debugging | |
1273 | purposes. */ | |
a8579651 | 1274 | || (temp_hard_regset == temp_set2 |
55a2c322 VM |
1275 | && (cl3 == GENERAL_REGS |
1276 | || ((ira_reg_class_intersect[cl1][cl2] | |
1277 | != GENERAL_REGS) | |
1278 | && hard_reg_set_subset_p | |
1279 | (reg_class_contents[cl3], | |
1280 | reg_class_contents | |
1281 | [(int) | |
1282 | ira_reg_class_intersect[cl1][cl2]]))))) | |
1283 | ira_reg_class_intersect[cl1][cl2] = (enum reg_class) cl3; | |
1284 | } | |
6576d245 | 1285 | temp_set2 |
d15e5131 RS |
1286 | = (reg_class_contents[ira_reg_class_subset[cl1][cl2]] |
1287 | & ~no_unit_alloc_regs); | |
55a2c322 VM |
1288 | if (! hard_reg_set_subset_p (temp_hard_regset, temp_set2) |
1289 | /* Ignore unavailable hard registers and prefer | |
1290 | smallest class for debugging purposes. */ | |
a8579651 | 1291 | || (temp_hard_regset == temp_set2 |
55a2c322 VM |
1292 | && hard_reg_set_subset_p |
1293 | (reg_class_contents[cl3], | |
1294 | reg_class_contents | |
1295 | [(int) ira_reg_class_subset[cl1][cl2]]))) | |
1296 | ira_reg_class_subset[cl1][cl2] = (enum reg_class) cl3; | |
058e97ec | 1297 | } |
55a2c322 VM |
1298 | if (important_class_p[cl3] |
1299 | && hard_reg_set_subset_p (temp_hard_regset, union_set)) | |
058e97ec | 1300 | { |
df3e3493 | 1301 | /* CL3 allocatable hard register set is inside of |
1756cb66 VM |
1302 | union of allocatable hard register sets of CL1 |
1303 | and CL2. */ | |
6576d245 | 1304 | temp_set2 |
d15e5131 RS |
1305 | = (reg_class_contents[ira_reg_class_subunion[cl1][cl2]] |
1306 | & ~no_unit_alloc_regs); | |
1756cb66 | 1307 | if (ira_reg_class_subunion[cl1][cl2] == NO_REGS |
058e97ec | 1308 | || (hard_reg_set_subset_p (temp_set2, temp_hard_regset) |
1756cb66 | 1309 | |
a8579651 | 1310 | && (temp_set2 != temp_hard_regset |
1756cb66 VM |
1311 | || cl3 == GENERAL_REGS |
1312 | /* If the allocatable hard register sets are the | |
1313 | same, prefer GENERAL_REGS or the smallest | |
1314 | class for debugging purposes. */ | |
1315 | || (ira_reg_class_subunion[cl1][cl2] != GENERAL_REGS | |
1316 | && hard_reg_set_subset_p | |
1317 | (reg_class_contents[cl3], | |
1318 | reg_class_contents | |
1319 | [(int) ira_reg_class_subunion[cl1][cl2]]))))) | |
1320 | ira_reg_class_subunion[cl1][cl2] = (enum reg_class) cl3; | |
1321 | } | |
1322 | if (hard_reg_set_subset_p (union_set, temp_hard_regset)) | |
1323 | { | |
1324 | /* CL3 allocatable hard register set contains union | |
1325 | of allocatable hard register sets of CL1 and | |
1326 | CL2. */ | |
6576d245 | 1327 | temp_set2 |
d15e5131 RS |
1328 | = (reg_class_contents[ira_reg_class_superunion[cl1][cl2]] |
1329 | & ~no_unit_alloc_regs); | |
1756cb66 VM |
1330 | if (ira_reg_class_superunion[cl1][cl2] == NO_REGS |
1331 | || (hard_reg_set_subset_p (temp_hard_regset, temp_set2) | |
b8698a0f | 1332 | |
a8579651 | 1333 | && (temp_set2 != temp_hard_regset |
1756cb66 VM |
1334 | || cl3 == GENERAL_REGS |
1335 | /* If the allocatable hard register sets are the | |
1336 | same, prefer GENERAL_REGS or the smallest | |
1337 | class for debugging purposes. */ | |
1338 | || (ira_reg_class_superunion[cl1][cl2] != GENERAL_REGS | |
1339 | && hard_reg_set_subset_p | |
1340 | (reg_class_contents[cl3], | |
1341 | reg_class_contents | |
1342 | [(int) ira_reg_class_superunion[cl1][cl2]]))))) | |
1343 | ira_reg_class_superunion[cl1][cl2] = (enum reg_class) cl3; | |
058e97ec VM |
1344 | } |
1345 | } | |
1346 | } | |
1347 | } | |
1348 | } | |
1349 | ||
df3e3493 | 1350 | /* Output all uniform and important classes into file F. */ |
165f639c | 1351 | static void |
89e94470 | 1352 | print_uniform_and_important_classes (FILE *f) |
165f639c | 1353 | { |
165f639c VM |
1354 | int i, cl; |
1355 | ||
1356 | fprintf (f, "Uniform classes:\n"); | |
1357 | for (cl = 0; cl < N_REG_CLASSES; cl++) | |
1358 | if (ira_uniform_class_p[cl]) | |
1359 | fprintf (f, " %s", reg_class_names[cl]); | |
1360 | fprintf (f, "\nImportant classes:\n"); | |
1361 | for (i = 0; i < ira_important_classes_num; i++) | |
1362 | fprintf (f, " %s", reg_class_names[ira_important_classes[i]]); | |
1363 | fprintf (f, "\n"); | |
1364 | } | |
1365 | ||
1366 | /* Output all possible allocno or pressure classes and their | |
1367 | translation map into file F. */ | |
058e97ec | 1368 | static void |
165f639c | 1369 | print_translated_classes (FILE *f, bool pressure_p) |
1756cb66 VM |
1370 | { |
1371 | int classes_num = (pressure_p | |
1372 | ? ira_pressure_classes_num : ira_allocno_classes_num); | |
1373 | enum reg_class *classes = (pressure_p | |
1374 | ? ira_pressure_classes : ira_allocno_classes); | |
1375 | enum reg_class *class_translate = (pressure_p | |
1376 | ? ira_pressure_class_translate | |
1377 | : ira_allocno_class_translate); | |
058e97ec VM |
1378 | int i; |
1379 | ||
1756cb66 VM |
1380 | fprintf (f, "%s classes:\n", pressure_p ? "Pressure" : "Allocno"); |
1381 | for (i = 0; i < classes_num; i++) | |
1382 | fprintf (f, " %s", reg_class_names[classes[i]]); | |
058e97ec VM |
1383 | fprintf (f, "\nClass translation:\n"); |
1384 | for (i = 0; i < N_REG_CLASSES; i++) | |
1385 | fprintf (f, " %s -> %s\n", reg_class_names[i], | |
1756cb66 | 1386 | reg_class_names[class_translate[i]]); |
058e97ec VM |
1387 | } |
1388 | ||
1756cb66 VM |
1389 | /* Output all possible allocno and translation classes and the |
1390 | translation maps into stderr. */ | |
058e97ec | 1391 | void |
1756cb66 | 1392 | ira_debug_allocno_classes (void) |
058e97ec | 1393 | { |
89e94470 | 1394 | print_uniform_and_important_classes (stderr); |
165f639c VM |
1395 | print_translated_classes (stderr, false); |
1396 | print_translated_classes (stderr, true); | |
058e97ec VM |
1397 | } |
1398 | ||
1756cb66 | 1399 | /* Set up different arrays concerning class subsets, allocno and |
058e97ec VM |
1400 | important classes. */ |
1401 | static void | |
1756cb66 | 1402 | find_reg_classes (void) |
058e97ec | 1403 | { |
1756cb66 | 1404 | setup_allocno_and_important_classes (); |
7db7ed3c | 1405 | setup_class_translate (); |
db1a8d98 | 1406 | reorder_important_classes (); |
7db7ed3c | 1407 | setup_reg_class_relations (); |
058e97ec VM |
1408 | } |
1409 | ||
1410 | \f | |
1411 | ||
c0683a82 VM |
1412 | /* Set up the array above. */ |
1413 | static void | |
1756cb66 | 1414 | setup_hard_regno_aclass (void) |
c0683a82 | 1415 | { |
7efcf910 | 1416 | int i; |
c0683a82 VM |
1417 | |
1418 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1419 | { | |
1756cb66 VM |
1420 | #if 1 |
1421 | ira_hard_regno_allocno_class[i] | |
7efcf910 CLT |
1422 | = (TEST_HARD_REG_BIT (no_unit_alloc_regs, i) |
1423 | ? NO_REGS | |
1756cb66 VM |
1424 | : ira_allocno_class_translate[REGNO_REG_CLASS (i)]); |
1425 | #else | |
1426 | int j; | |
1427 | enum reg_class cl; | |
1428 | ira_hard_regno_allocno_class[i] = NO_REGS; | |
1429 | for (j = 0; j < ira_allocno_classes_num; j++) | |
1430 | { | |
1431 | cl = ira_allocno_classes[j]; | |
1432 | if (ira_class_hard_reg_index[cl][i] >= 0) | |
1433 | { | |
1434 | ira_hard_regno_allocno_class[i] = cl; | |
1435 | break; | |
1436 | } | |
1437 | } | |
1438 | #endif | |
c0683a82 VM |
1439 | } |
1440 | } | |
1441 | ||
1442 | \f | |
1443 | ||
1756cb66 | 1444 | /* Form IRA_REG_CLASS_MAX_NREGS and IRA_REG_CLASS_MIN_NREGS maps. */ |
058e97ec VM |
1445 | static void |
1446 | setup_reg_class_nregs (void) | |
1447 | { | |
1756cb66 | 1448 | int i, cl, cl2, m; |
058e97ec | 1449 | |
1756cb66 VM |
1450 | for (m = 0; m < MAX_MACHINE_MODE; m++) |
1451 | { | |
1452 | for (cl = 0; cl < N_REG_CLASSES; cl++) | |
1453 | ira_reg_class_max_nregs[cl][m] | |
1454 | = ira_reg_class_min_nregs[cl][m] | |
ef4bddc2 | 1455 | = targetm.class_max_nregs ((reg_class_t) cl, (machine_mode) m); |
1756cb66 VM |
1456 | for (cl = 0; cl < N_REG_CLASSES; cl++) |
1457 | for (i = 0; | |
1458 | (cl2 = alloc_reg_class_subclasses[cl][i]) != LIM_REG_CLASSES; | |
1459 | i++) | |
1460 | if (ira_reg_class_min_nregs[cl2][m] | |
1461 | < ira_reg_class_min_nregs[cl][m]) | |
1462 | ira_reg_class_min_nregs[cl][m] = ira_reg_class_min_nregs[cl2][m]; | |
1463 | } | |
058e97ec VM |
1464 | } |
1465 | ||
1466 | \f | |
1467 | ||
c9d74da6 RS |
1468 | /* Set up IRA_PROHIBITED_CLASS_MODE_REGS and IRA_CLASS_SINGLETON. |
1469 | This function is called once IRA_CLASS_HARD_REGS has been initialized. */ | |
058e97ec VM |
1470 | static void |
1471 | setup_prohibited_class_mode_regs (void) | |
1472 | { | |
c9d74da6 | 1473 | int j, k, hard_regno, cl, last_hard_regno, count; |
058e97ec | 1474 | |
1756cb66 | 1475 | for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) |
058e97ec | 1476 | { |
d15e5131 | 1477 | temp_hard_regset = reg_class_contents[cl] & ~no_unit_alloc_regs; |
058e97ec VM |
1478 | for (j = 0; j < NUM_MACHINE_MODES; j++) |
1479 | { | |
c9d74da6 RS |
1480 | count = 0; |
1481 | last_hard_regno = -1; | |
1756cb66 | 1482 | CLEAR_HARD_REG_SET (ira_prohibited_class_mode_regs[cl][j]); |
058e97ec VM |
1483 | for (k = ira_class_hard_regs_num[cl] - 1; k >= 0; k--) |
1484 | { | |
1485 | hard_regno = ira_class_hard_regs[cl][k]; | |
f939c3e6 | 1486 | if (!targetm.hard_regno_mode_ok (hard_regno, (machine_mode) j)) |
1756cb66 | 1487 | SET_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j], |
058e97ec | 1488 | hard_regno); |
c9d74da6 | 1489 | else if (in_hard_reg_set_p (temp_hard_regset, |
ef4bddc2 | 1490 | (machine_mode) j, hard_regno)) |
c9d74da6 RS |
1491 | { |
1492 | last_hard_regno = hard_regno; | |
1493 | count++; | |
1494 | } | |
058e97ec | 1495 | } |
c9d74da6 | 1496 | ira_class_singleton[cl][j] = (count == 1 ? last_hard_regno : -1); |
058e97ec VM |
1497 | } |
1498 | } | |
1499 | } | |
1500 | ||
1756cb66 VM |
1501 | /* Clarify IRA_PROHIBITED_CLASS_MODE_REGS by excluding hard registers |
1502 | spanning from one register pressure class to another one. It is | |
1503 | called after defining the pressure classes. */ | |
1504 | static void | |
1505 | clarify_prohibited_class_mode_regs (void) | |
1506 | { | |
1507 | int j, k, hard_regno, cl, pclass, nregs; | |
1508 | ||
1509 | for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) | |
1510 | for (j = 0; j < NUM_MACHINE_MODES; j++) | |
a2c19e93 RS |
1511 | { |
1512 | CLEAR_HARD_REG_SET (ira_useful_class_mode_regs[cl][j]); | |
1513 | for (k = ira_class_hard_regs_num[cl] - 1; k >= 0; k--) | |
1514 | { | |
1515 | hard_regno = ira_class_hard_regs[cl][k]; | |
1516 | if (TEST_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j], hard_regno)) | |
1517 | continue; | |
ad474626 | 1518 | nregs = hard_regno_nregs (hard_regno, (machine_mode) j); |
a2c19e93 | 1519 | if (hard_regno + nregs > FIRST_PSEUDO_REGISTER) |
1756cb66 VM |
1520 | { |
1521 | SET_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j], | |
1522 | hard_regno); | |
a2c19e93 | 1523 | continue; |
1756cb66 | 1524 | } |
a2c19e93 RS |
1525 | pclass = ira_pressure_class_translate[REGNO_REG_CLASS (hard_regno)]; |
1526 | for (nregs-- ;nregs >= 0; nregs--) | |
1527 | if (((enum reg_class) pclass | |
1528 | != ira_pressure_class_translate[REGNO_REG_CLASS | |
1529 | (hard_regno + nregs)])) | |
1530 | { | |
1531 | SET_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j], | |
1532 | hard_regno); | |
1533 | break; | |
1534 | } | |
1535 | if (!TEST_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j], | |
1536 | hard_regno)) | |
1537 | add_to_hard_reg_set (&ira_useful_class_mode_regs[cl][j], | |
ef4bddc2 | 1538 | (machine_mode) j, hard_regno); |
a2c19e93 RS |
1539 | } |
1540 | } | |
1756cb66 | 1541 | } |
058e97ec | 1542 | \f |
7cc61ee4 RS |
1543 | /* Allocate and initialize IRA_REGISTER_MOVE_COST, IRA_MAY_MOVE_IN_COST |
1544 | and IRA_MAY_MOVE_OUT_COST for MODE. */ | |
1545 | void | |
ef4bddc2 | 1546 | ira_init_register_move_cost (machine_mode mode) |
e80ccebc RS |
1547 | { |
1548 | static unsigned short last_move_cost[N_REG_CLASSES][N_REG_CLASSES]; | |
1549 | bool all_match = true; | |
e384094a VM |
1550 | unsigned int i, cl1, cl2; |
1551 | HARD_REG_SET ok_regs; | |
e80ccebc | 1552 | |
7cc61ee4 RS |
1553 | ira_assert (ira_register_move_cost[mode] == NULL |
1554 | && ira_may_move_in_cost[mode] == NULL | |
1555 | && ira_may_move_out_cost[mode] == NULL); | |
e384094a VM |
1556 | CLEAR_HARD_REG_SET (ok_regs); |
1557 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1558 | if (targetm.hard_regno_mode_ok (i, mode)) | |
1559 | SET_HARD_REG_BIT (ok_regs, i); | |
1560 | ||
87e176df RS |
1561 | /* Note that we might be asked about the move costs of modes that |
1562 | cannot be stored in any hard register, for example if an inline | |
1563 | asm tries to create a register operand with an impossible mode. | |
1564 | We therefore can't assert have_regs_of_mode[mode] here. */ | |
ed9e2ed0 | 1565 | for (cl1 = 0; cl1 < N_REG_CLASSES; cl1++) |
fef37404 VM |
1566 | for (cl2 = 0; cl2 < N_REG_CLASSES; cl2++) |
1567 | { | |
1568 | int cost; | |
e384094a VM |
1569 | if (!hard_reg_set_intersect_p (ok_regs, reg_class_contents[cl1]) |
1570 | || !hard_reg_set_intersect_p (ok_regs, reg_class_contents[cl2])) | |
fef37404 VM |
1571 | { |
1572 | if ((ira_reg_class_max_nregs[cl1][mode] | |
1573 | > ira_class_hard_regs_num[cl1]) | |
1574 | || (ira_reg_class_max_nregs[cl2][mode] | |
1575 | > ira_class_hard_regs_num[cl2])) | |
1576 | cost = 65535; | |
1577 | else | |
1578 | cost = (ira_memory_move_cost[mode][cl1][0] | |
1a788c05 | 1579 | + ira_memory_move_cost[mode][cl2][1]) * 2; |
fef37404 VM |
1580 | } |
1581 | else | |
1582 | { | |
1583 | cost = register_move_cost (mode, (enum reg_class) cl1, | |
1584 | (enum reg_class) cl2); | |
1585 | ira_assert (cost < 65535); | |
1586 | } | |
1587 | all_match &= (last_move_cost[cl1][cl2] == cost); | |
1588 | last_move_cost[cl1][cl2] = cost; | |
1589 | } | |
e80ccebc RS |
1590 | if (all_match && last_mode_for_init_move_cost != -1) |
1591 | { | |
7cc61ee4 RS |
1592 | ira_register_move_cost[mode] |
1593 | = ira_register_move_cost[last_mode_for_init_move_cost]; | |
1594 | ira_may_move_in_cost[mode] | |
1595 | = ira_may_move_in_cost[last_mode_for_init_move_cost]; | |
1596 | ira_may_move_out_cost[mode] | |
1597 | = ira_may_move_out_cost[last_mode_for_init_move_cost]; | |
e80ccebc RS |
1598 | return; |
1599 | } | |
ed9e2ed0 | 1600 | last_mode_for_init_move_cost = mode; |
7cc61ee4 RS |
1601 | ira_register_move_cost[mode] = XNEWVEC (move_table, N_REG_CLASSES); |
1602 | ira_may_move_in_cost[mode] = XNEWVEC (move_table, N_REG_CLASSES); | |
1603 | ira_may_move_out_cost[mode] = XNEWVEC (move_table, N_REG_CLASSES); | |
ed9e2ed0 | 1604 | for (cl1 = 0; cl1 < N_REG_CLASSES; cl1++) |
fef37404 VM |
1605 | for (cl2 = 0; cl2 < N_REG_CLASSES; cl2++) |
1606 | { | |
1607 | int cost; | |
1608 | enum reg_class *p1, *p2; | |
1609 | ||
1610 | if (last_move_cost[cl1][cl2] == 65535) | |
1611 | { | |
1612 | ira_register_move_cost[mode][cl1][cl2] = 65535; | |
1613 | ira_may_move_in_cost[mode][cl1][cl2] = 65535; | |
1614 | ira_may_move_out_cost[mode][cl1][cl2] = 65535; | |
1615 | } | |
1616 | else | |
1617 | { | |
1618 | cost = last_move_cost[cl1][cl2]; | |
1619 | ||
1620 | for (p2 = ®_class_subclasses[cl2][0]; | |
1621 | *p2 != LIM_REG_CLASSES; p2++) | |
1622 | if (ira_class_hard_regs_num[*p2] > 0 | |
1623 | && (ira_reg_class_max_nregs[*p2][mode] | |
1624 | <= ira_class_hard_regs_num[*p2])) | |
1625 | cost = MAX (cost, ira_register_move_cost[mode][cl1][*p2]); | |
1626 | ||
1627 | for (p1 = ®_class_subclasses[cl1][0]; | |
1628 | *p1 != LIM_REG_CLASSES; p1++) | |
1629 | if (ira_class_hard_regs_num[*p1] > 0 | |
1630 | && (ira_reg_class_max_nregs[*p1][mode] | |
1631 | <= ira_class_hard_regs_num[*p1])) | |
1632 | cost = MAX (cost, ira_register_move_cost[mode][*p1][cl2]); | |
1633 | ||
1634 | ira_assert (cost <= 65535); | |
1635 | ira_register_move_cost[mode][cl1][cl2] = cost; | |
1636 | ||
1637 | if (ira_class_subset_p[cl1][cl2]) | |
1638 | ira_may_move_in_cost[mode][cl1][cl2] = 0; | |
1639 | else | |
1640 | ira_may_move_in_cost[mode][cl1][cl2] = cost; | |
1641 | ||
1642 | if (ira_class_subset_p[cl2][cl1]) | |
1643 | ira_may_move_out_cost[mode][cl1][cl2] = 0; | |
1644 | else | |
1645 | ira_may_move_out_cost[mode][cl1][cl2] = cost; | |
1646 | } | |
1647 | } | |
058e97ec | 1648 | } |
fef37404 | 1649 | |
058e97ec VM |
1650 | \f |
1651 | ||
058e97ec VM |
1652 | /* This is called once during compiler work. It sets up |
1653 | different arrays whose values don't depend on the compiled | |
1654 | function. */ | |
1655 | void | |
1656 | ira_init_once (void) | |
1657 | { | |
058e97ec | 1658 | ira_init_costs_once (); |
55a2c322 | 1659 | lra_init_once (); |
23427d51 RL |
1660 | |
1661 | ira_use_lra_p = targetm.lra_p (); | |
058e97ec VM |
1662 | } |
1663 | ||
7cc61ee4 RS |
1664 | /* Free ira_max_register_move_cost, ira_may_move_in_cost and |
1665 | ira_may_move_out_cost for each mode. */ | |
19c708dc RS |
1666 | void |
1667 | target_ira_int::free_register_move_costs (void) | |
058e97ec | 1668 | { |
e80ccebc | 1669 | int mode, i; |
058e97ec | 1670 | |
e80ccebc RS |
1671 | /* Reset move_cost and friends, making sure we only free shared |
1672 | table entries once. */ | |
1673 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
19c708dc | 1674 | if (x_ira_register_move_cost[mode]) |
e80ccebc | 1675 | { |
7cc61ee4 | 1676 | for (i = 0; |
19c708dc RS |
1677 | i < mode && (x_ira_register_move_cost[i] |
1678 | != x_ira_register_move_cost[mode]); | |
7cc61ee4 | 1679 | i++) |
e80ccebc RS |
1680 | ; |
1681 | if (i == mode) | |
1682 | { | |
19c708dc RS |
1683 | free (x_ira_register_move_cost[mode]); |
1684 | free (x_ira_may_move_in_cost[mode]); | |
1685 | free (x_ira_may_move_out_cost[mode]); | |
e80ccebc RS |
1686 | } |
1687 | } | |
19c708dc RS |
1688 | memset (x_ira_register_move_cost, 0, sizeof x_ira_register_move_cost); |
1689 | memset (x_ira_may_move_in_cost, 0, sizeof x_ira_may_move_in_cost); | |
1690 | memset (x_ira_may_move_out_cost, 0, sizeof x_ira_may_move_out_cost); | |
e80ccebc | 1691 | last_mode_for_init_move_cost = -1; |
058e97ec VM |
1692 | } |
1693 | ||
19c708dc RS |
1694 | target_ira_int::~target_ira_int () |
1695 | { | |
1696 | free_ira_costs (); | |
1697 | free_register_move_costs (); | |
1698 | } | |
1699 | ||
058e97ec VM |
1700 | /* This is called every time when register related information is |
1701 | changed. */ | |
1702 | void | |
1703 | ira_init (void) | |
1704 | { | |
19c708dc | 1705 | this_target_ira_int->free_register_move_costs (); |
058e97ec VM |
1706 | setup_reg_mode_hard_regset (); |
1707 | setup_alloc_regs (flag_omit_frame_pointer != 0); | |
1708 | setup_class_subset_and_memory_move_costs (); | |
058e97ec VM |
1709 | setup_reg_class_nregs (); |
1710 | setup_prohibited_class_mode_regs (); | |
1756cb66 VM |
1711 | find_reg_classes (); |
1712 | clarify_prohibited_class_mode_regs (); | |
1713 | setup_hard_regno_aclass (); | |
058e97ec VM |
1714 | ira_init_costs (); |
1715 | } | |
1716 | ||
058e97ec | 1717 | \f |
15e7b94f RS |
1718 | #define ira_prohibited_mode_move_regs_initialized_p \ |
1719 | (this_target_ira_int->x_ira_prohibited_mode_move_regs_initialized_p) | |
058e97ec VM |
1720 | |
1721 | /* Set up IRA_PROHIBITED_MODE_MOVE_REGS. */ | |
1722 | static void | |
1723 | setup_prohibited_mode_move_regs (void) | |
1724 | { | |
1725 | int i, j; | |
647d790d DM |
1726 | rtx test_reg1, test_reg2, move_pat; |
1727 | rtx_insn *move_insn; | |
058e97ec VM |
1728 | |
1729 | if (ira_prohibited_mode_move_regs_initialized_p) | |
1730 | return; | |
1731 | ira_prohibited_mode_move_regs_initialized_p = true; | |
c3dc5e66 RS |
1732 | test_reg1 = gen_rtx_REG (word_mode, LAST_VIRTUAL_REGISTER + 1); |
1733 | test_reg2 = gen_rtx_REG (word_mode, LAST_VIRTUAL_REGISTER + 2); | |
f7df4a84 | 1734 | move_pat = gen_rtx_SET (test_reg1, test_reg2); |
ed8921dc | 1735 | move_insn = gen_rtx_INSN (VOIDmode, 0, 0, 0, move_pat, 0, -1, 0); |
058e97ec VM |
1736 | for (i = 0; i < NUM_MACHINE_MODES; i++) |
1737 | { | |
1738 | SET_HARD_REG_SET (ira_prohibited_mode_move_regs[i]); | |
1739 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
1740 | { | |
f939c3e6 | 1741 | if (!targetm.hard_regno_mode_ok (j, (machine_mode) i)) |
058e97ec | 1742 | continue; |
8deccbb7 RS |
1743 | set_mode_and_regno (test_reg1, (machine_mode) i, j); |
1744 | set_mode_and_regno (test_reg2, (machine_mode) i, j); | |
058e97ec VM |
1745 | INSN_CODE (move_insn) = -1; |
1746 | recog_memoized (move_insn); | |
1747 | if (INSN_CODE (move_insn) < 0) | |
1748 | continue; | |
1749 | extract_insn (move_insn); | |
daca1a96 RS |
1750 | /* We don't know whether the move will be in code that is optimized |
1751 | for size or speed, so consider all enabled alternatives. */ | |
1752 | if (! constrain_operands (1, get_enabled_alternatives (move_insn))) | |
058e97ec VM |
1753 | continue; |
1754 | CLEAR_HARD_REG_BIT (ira_prohibited_mode_move_regs[i], j); | |
1755 | } | |
1756 | } | |
1757 | } | |
1758 | ||
1759 | \f | |
1760 | ||
73bb8fe9 RS |
1761 | /* Extract INSN and return the set of alternatives that we should consider. |
1762 | This excludes any alternatives whose constraints are obviously impossible | |
1763 | to meet (e.g. because the constraint requires a constant and the operand | |
ed680e2c RS |
1764 | is nonconstant). It also excludes alternatives that are bound to need |
1765 | a spill or reload, as long as we have other alternatives that match | |
1766 | exactly. */ | |
73bb8fe9 RS |
1767 | alternative_mask |
1768 | ira_setup_alts (rtx_insn *insn) | |
3b6d1699 | 1769 | { |
3b6d1699 VM |
1770 | int nop, nalt; |
1771 | bool curr_swapped; | |
1772 | const char *p; | |
3b6d1699 VM |
1773 | int commutative = -1; |
1774 | ||
1775 | extract_insn (insn); | |
06a65e80 | 1776 | preprocess_constraints (insn); |
9840b2fa | 1777 | alternative_mask preferred = get_preferred_alternatives (insn); |
73bb8fe9 | 1778 | alternative_mask alts = 0; |
ed680e2c | 1779 | alternative_mask exact_alts = 0; |
3b6d1699 VM |
1780 | /* Check that the hard reg set is enough for holding all |
1781 | alternatives. It is hard to imagine the situation when the | |
1782 | assertion is wrong. */ | |
1783 | ira_assert (recog_data.n_alternatives | |
1784 | <= (int) MAX (sizeof (HARD_REG_ELT_TYPE) * CHAR_BIT, | |
1785 | FIRST_PSEUDO_REGISTER)); | |
06a65e80 RS |
1786 | for (nop = 0; nop < recog_data.n_operands; nop++) |
1787 | if (recog_data.constraints[nop][0] == '%') | |
1788 | { | |
1789 | commutative = nop; | |
1790 | break; | |
1791 | } | |
3b6d1699 VM |
1792 | for (curr_swapped = false;; curr_swapped = true) |
1793 | { | |
3b6d1699 VM |
1794 | for (nalt = 0; nalt < recog_data.n_alternatives; nalt++) |
1795 | { | |
ed680e2c | 1796 | if (!TEST_BIT (preferred, nalt) || TEST_BIT (exact_alts, nalt)) |
3b6d1699 VM |
1797 | continue; |
1798 | ||
06a65e80 RS |
1799 | const operand_alternative *op_alt |
1800 | = &recog_op_alt[nalt * recog_data.n_operands]; | |
ed680e2c | 1801 | int this_reject = 0; |
3b6d1699 VM |
1802 | for (nop = 0; nop < recog_data.n_operands; nop++) |
1803 | { | |
1804 | int c, len; | |
1805 | ||
ed680e2c RS |
1806 | this_reject += op_alt[nop].reject; |
1807 | ||
fab27f52 | 1808 | rtx op = recog_data.operand[nop]; |
06a65e80 | 1809 | p = op_alt[nop].constraint; |
3b6d1699 VM |
1810 | if (*p == 0 || *p == ',') |
1811 | continue; | |
ed680e2c RS |
1812 | |
1813 | bool win_p = false; | |
3b6d1699 VM |
1814 | do |
1815 | switch (c = *p, len = CONSTRAINT_LEN (c, p), c) | |
1816 | { | |
1817 | case '#': | |
1818 | case ',': | |
1819 | c = '\0'; | |
191816a3 | 1820 | /* FALLTHRU */ |
3b6d1699 VM |
1821 | case '\0': |
1822 | len = 0; | |
1823 | break; | |
1824 | ||
3b6d1699 | 1825 | case '%': |
3f12f020 | 1826 | /* The commutative modifier is handled above. */ |
3b6d1699 VM |
1827 | break; |
1828 | ||
3b6d1699 VM |
1829 | case '0': case '1': case '2': case '3': case '4': |
1830 | case '5': case '6': case '7': case '8': case '9': | |
ed680e2c RS |
1831 | { |
1832 | rtx other = recog_data.operand[c - '0']; | |
1833 | if (MEM_P (other) | |
1834 | ? rtx_equal_p (other, op) | |
1835 | : REG_P (op) || SUBREG_P (op)) | |
1836 | goto op_success; | |
1837 | win_p = true; | |
1838 | } | |
3b6d1699 VM |
1839 | break; |
1840 | ||
3b6d1699 | 1841 | case 'g': |
3b6d1699 VM |
1842 | goto op_success; |
1843 | break; | |
1844 | ||
1845 | default: | |
1846 | { | |
777e635f RS |
1847 | enum constraint_num cn = lookup_constraint (p); |
1848 | switch (get_constraint_type (cn)) | |
1849 | { | |
1850 | case CT_REGISTER: | |
1851 | if (reg_class_for_constraint (cn) != NO_REGS) | |
ed680e2c RS |
1852 | { |
1853 | if (REG_P (op) || SUBREG_P (op)) | |
1854 | goto op_success; | |
1855 | win_p = true; | |
1856 | } | |
777e635f RS |
1857 | break; |
1858 | ||
d9c35eee RS |
1859 | case CT_CONST_INT: |
1860 | if (CONST_INT_P (op) | |
1861 | && (insn_const_int_ok_for_constraint | |
1862 | (INTVAL (op), cn))) | |
1863 | goto op_success; | |
1864 | break; | |
1865 | ||
777e635f | 1866 | case CT_ADDRESS: |
ed680e2c RS |
1867 | goto op_success; |
1868 | ||
777e635f | 1869 | case CT_MEMORY: |
9eb1ca69 | 1870 | case CT_SPECIAL_MEMORY: |
ed680e2c RS |
1871 | if (MEM_P (op)) |
1872 | goto op_success; | |
1873 | win_p = true; | |
1874 | break; | |
777e635f RS |
1875 | |
1876 | case CT_FIXED_FORM: | |
1877 | if (constraint_satisfied_p (op, cn)) | |
1878 | goto op_success; | |
1879 | break; | |
1880 | } | |
3b6d1699 VM |
1881 | break; |
1882 | } | |
1883 | } | |
1884 | while (p += len, c); | |
ed680e2c RS |
1885 | if (!win_p) |
1886 | break; | |
1887 | /* We can make the alternative match by spilling a register | |
1888 | to memory or loading something into a register. Count a | |
1889 | cost of one reload (the equivalent of the '?' constraint). */ | |
1890 | this_reject += 6; | |
3b6d1699 VM |
1891 | op_success: |
1892 | ; | |
1893 | } | |
ed680e2c | 1894 | |
3b6d1699 | 1895 | if (nop >= recog_data.n_operands) |
ed680e2c RS |
1896 | { |
1897 | alts |= ALTERNATIVE_BIT (nalt); | |
1898 | if (this_reject == 0) | |
1899 | exact_alts |= ALTERNATIVE_BIT (nalt); | |
1900 | } | |
3b6d1699 VM |
1901 | } |
1902 | if (commutative < 0) | |
1903 | break; | |
43f4a281 | 1904 | /* Swap forth and back to avoid changing recog_data. */ |
fab27f52 MM |
1905 | std::swap (recog_data.operand[commutative], |
1906 | recog_data.operand[commutative + 1]); | |
43f4a281 RB |
1907 | if (curr_swapped) |
1908 | break; | |
3b6d1699 | 1909 | } |
ed680e2c | 1910 | return exact_alts ? exact_alts : alts; |
3b6d1699 VM |
1911 | } |
1912 | ||
1913 | /* Return the number of the output non-early clobber operand which | |
1914 | should be the same in any case as operand with number OP_NUM (or | |
ed680e2c RS |
1915 | negative value if there is no such operand). ALTS is the mask |
1916 | of alternatives that we should consider. */ | |
3b6d1699 | 1917 | int |
73bb8fe9 | 1918 | ira_get_dup_out_num (int op_num, alternative_mask alts) |
3b6d1699 VM |
1919 | { |
1920 | int curr_alt, c, original, dup; | |
1921 | bool ignore_p, use_commut_op_p; | |
1922 | const char *str; | |
3b6d1699 VM |
1923 | |
1924 | if (op_num < 0 || recog_data.n_alternatives == 0) | |
1925 | return -1; | |
98f2f031 RS |
1926 | /* We should find duplications only for input operands. */ |
1927 | if (recog_data.operand_type[op_num] != OP_IN) | |
1928 | return -1; | |
3b6d1699 | 1929 | str = recog_data.constraints[op_num]; |
98f2f031 | 1930 | use_commut_op_p = false; |
3b6d1699 VM |
1931 | for (;;) |
1932 | { | |
777e635f | 1933 | rtx op = recog_data.operand[op_num]; |
3b6d1699 | 1934 | |
73bb8fe9 | 1935 | for (curr_alt = 0, ignore_p = !TEST_BIT (alts, curr_alt), |
98f2f031 | 1936 | original = -1;;) |
3b6d1699 VM |
1937 | { |
1938 | c = *str; | |
1939 | if (c == '\0') | |
1940 | break; | |
98f2f031 | 1941 | if (c == '#') |
3b6d1699 VM |
1942 | ignore_p = true; |
1943 | else if (c == ',') | |
1944 | { | |
1945 | curr_alt++; | |
73bb8fe9 | 1946 | ignore_p = !TEST_BIT (alts, curr_alt); |
3b6d1699 VM |
1947 | } |
1948 | else if (! ignore_p) | |
1949 | switch (c) | |
1950 | { | |
3b6d1699 VM |
1951 | case 'g': |
1952 | goto fail; | |
8677664e | 1953 | default: |
3b6d1699 | 1954 | { |
777e635f RS |
1955 | enum constraint_num cn = lookup_constraint (str); |
1956 | enum reg_class cl = reg_class_for_constraint (cn); | |
1957 | if (cl != NO_REGS | |
1958 | && !targetm.class_likely_spilled_p (cl)) | |
1959 | goto fail; | |
1960 | if (constraint_satisfied_p (op, cn)) | |
3b6d1699 | 1961 | goto fail; |
3b6d1699 VM |
1962 | break; |
1963 | } | |
1964 | ||
1965 | case '0': case '1': case '2': case '3': case '4': | |
1966 | case '5': case '6': case '7': case '8': case '9': | |
1967 | if (original != -1 && original != c) | |
1968 | goto fail; | |
1969 | original = c; | |
1970 | break; | |
1971 | } | |
1972 | str += CONSTRAINT_LEN (c, str); | |
1973 | } | |
1974 | if (original == -1) | |
1975 | goto fail; | |
ae5569fa RS |
1976 | dup = original - '0'; |
1977 | if (recog_data.operand_type[dup] == OP_OUT) | |
3b6d1699 VM |
1978 | return dup; |
1979 | fail: | |
1980 | if (use_commut_op_p) | |
1981 | break; | |
1982 | use_commut_op_p = true; | |
73f793e3 | 1983 | if (recog_data.constraints[op_num][0] == '%') |
3b6d1699 | 1984 | str = recog_data.constraints[op_num + 1]; |
73f793e3 | 1985 | else if (op_num > 0 && recog_data.constraints[op_num - 1][0] == '%') |
3b6d1699 VM |
1986 | str = recog_data.constraints[op_num - 1]; |
1987 | else | |
1988 | break; | |
1989 | } | |
1990 | return -1; | |
1991 | } | |
1992 | ||
1993 | \f | |
1994 | ||
1995 | /* Search forward to see if the source register of a copy insn dies | |
1996 | before either it or the destination register is modified, but don't | |
1997 | scan past the end of the basic block. If so, we can replace the | |
1998 | source with the destination and let the source die in the copy | |
1999 | insn. | |
2000 | ||
2001 | This will reduce the number of registers live in that range and may | |
2002 | enable the destination and the source coalescing, thus often saving | |
2003 | one register in addition to a register-register copy. */ | |
2004 | ||
2005 | static void | |
2006 | decrease_live_ranges_number (void) | |
2007 | { | |
2008 | basic_block bb; | |
070a1983 | 2009 | rtx_insn *insn; |
7da26277 TS |
2010 | rtx set, src, dest, dest_death, note; |
2011 | rtx_insn *p, *q; | |
3b6d1699 VM |
2012 | int sregno, dregno; |
2013 | ||
2014 | if (! flag_expensive_optimizations) | |
2015 | return; | |
2016 | ||
2017 | if (ira_dump_file) | |
2018 | fprintf (ira_dump_file, "Starting decreasing number of live ranges...\n"); | |
2019 | ||
11cd3bed | 2020 | FOR_EACH_BB_FN (bb, cfun) |
3b6d1699 VM |
2021 | FOR_BB_INSNS (bb, insn) |
2022 | { | |
2023 | set = single_set (insn); | |
2024 | if (! set) | |
2025 | continue; | |
2026 | src = SET_SRC (set); | |
2027 | dest = SET_DEST (set); | |
2028 | if (! REG_P (src) || ! REG_P (dest) | |
2029 | || find_reg_note (insn, REG_DEAD, src)) | |
2030 | continue; | |
2031 | sregno = REGNO (src); | |
2032 | dregno = REGNO (dest); | |
2033 | ||
2034 | /* We don't want to mess with hard regs if register classes | |
2035 | are small. */ | |
2036 | if (sregno == dregno | |
2037 | || (targetm.small_register_classes_for_mode_p (GET_MODE (src)) | |
2038 | && (sregno < FIRST_PSEUDO_REGISTER | |
2039 | || dregno < FIRST_PSEUDO_REGISTER)) | |
2040 | /* We don't see all updates to SP if they are in an | |
2041 | auto-inc memory reference, so we must disallow this | |
2042 | optimization on them. */ | |
2043 | || sregno == STACK_POINTER_REGNUM | |
2044 | || dregno == STACK_POINTER_REGNUM) | |
2045 | continue; | |
2046 | ||
2047 | dest_death = NULL_RTX; | |
2048 | ||
2049 | for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p)) | |
2050 | { | |
2051 | if (! INSN_P (p)) | |
2052 | continue; | |
2053 | if (BLOCK_FOR_INSN (p) != bb) | |
2054 | break; | |
2055 | ||
2056 | if (reg_set_p (src, p) || reg_set_p (dest, p) | |
2057 | /* If SRC is an asm-declared register, it must not be | |
2058 | replaced in any asm. Unfortunately, the REG_EXPR | |
2059 | tree for the asm variable may be absent in the SRC | |
2060 | rtx, so we can't check the actual register | |
2061 | declaration easily (the asm operand will have it, | |
2062 | though). To avoid complicating the test for a rare | |
2063 | case, we just don't perform register replacement | |
2064 | for a hard reg mentioned in an asm. */ | |
2065 | || (sregno < FIRST_PSEUDO_REGISTER | |
2066 | && asm_noperands (PATTERN (p)) >= 0 | |
2067 | && reg_overlap_mentioned_p (src, PATTERN (p))) | |
2068 | /* Don't change hard registers used by a call. */ | |
2069 | || (CALL_P (p) && sregno < FIRST_PSEUDO_REGISTER | |
2070 | && find_reg_fusage (p, USE, src)) | |
2071 | /* Don't change a USE of a register. */ | |
2072 | || (GET_CODE (PATTERN (p)) == USE | |
2073 | && reg_overlap_mentioned_p (src, XEXP (PATTERN (p), 0)))) | |
2074 | break; | |
2075 | ||
2076 | /* See if all of SRC dies in P. This test is slightly | |
2077 | more conservative than it needs to be. */ | |
2078 | if ((note = find_regno_note (p, REG_DEAD, sregno)) | |
2079 | && GET_MODE (XEXP (note, 0)) == GET_MODE (src)) | |
2080 | { | |
2081 | int failed = 0; | |
2082 | ||
2083 | /* We can do the optimization. Scan forward from INSN | |
2084 | again, replacing regs as we go. Set FAILED if a | |
2085 | replacement can't be done. In that case, we can't | |
2086 | move the death note for SRC. This should be | |
2087 | rare. */ | |
2088 | ||
2089 | /* Set to stop at next insn. */ | |
2090 | for (q = next_real_insn (insn); | |
2091 | q != next_real_insn (p); | |
2092 | q = next_real_insn (q)) | |
2093 | { | |
2094 | if (reg_overlap_mentioned_p (src, PATTERN (q))) | |
2095 | { | |
2096 | /* If SRC is a hard register, we might miss | |
2097 | some overlapping registers with | |
2098 | validate_replace_rtx, so we would have to | |
2099 | undo it. We can't if DEST is present in | |
2100 | the insn, so fail in that combination of | |
2101 | cases. */ | |
2102 | if (sregno < FIRST_PSEUDO_REGISTER | |
2103 | && reg_mentioned_p (dest, PATTERN (q))) | |
2104 | failed = 1; | |
2105 | ||
2106 | /* Attempt to replace all uses. */ | |
2107 | else if (!validate_replace_rtx (src, dest, q)) | |
2108 | failed = 1; | |
2109 | ||
2110 | /* If this succeeded, but some part of the | |
2111 | register is still present, undo the | |
2112 | replacement. */ | |
2113 | else if (sregno < FIRST_PSEUDO_REGISTER | |
2114 | && reg_overlap_mentioned_p (src, PATTERN (q))) | |
2115 | { | |
2116 | validate_replace_rtx (dest, src, q); | |
2117 | failed = 1; | |
2118 | } | |
2119 | } | |
2120 | ||
2121 | /* If DEST dies here, remove the death note and | |
2122 | save it for later. Make sure ALL of DEST dies | |
2123 | here; again, this is overly conservative. */ | |
2124 | if (! dest_death | |
2125 | && (dest_death = find_regno_note (q, REG_DEAD, dregno))) | |
2126 | { | |
2127 | if (GET_MODE (XEXP (dest_death, 0)) == GET_MODE (dest)) | |
2128 | remove_note (q, dest_death); | |
2129 | else | |
2130 | { | |
2131 | failed = 1; | |
2132 | dest_death = 0; | |
2133 | } | |
2134 | } | |
2135 | } | |
2136 | ||
2137 | if (! failed) | |
2138 | { | |
2139 | /* Move death note of SRC from P to INSN. */ | |
2140 | remove_note (p, note); | |
2141 | XEXP (note, 1) = REG_NOTES (insn); | |
2142 | REG_NOTES (insn) = note; | |
2143 | } | |
2144 | ||
2145 | /* DEST is also dead if INSN has a REG_UNUSED note for | |
2146 | DEST. */ | |
2147 | if (! dest_death | |
2148 | && (dest_death | |
2149 | = find_regno_note (insn, REG_UNUSED, dregno))) | |
2150 | { | |
2151 | PUT_REG_NOTE_KIND (dest_death, REG_DEAD); | |
2152 | remove_note (insn, dest_death); | |
2153 | } | |
2154 | ||
2155 | /* Put death note of DEST on P if we saw it die. */ | |
2156 | if (dest_death) | |
2157 | { | |
2158 | XEXP (dest_death, 1) = REG_NOTES (p); | |
2159 | REG_NOTES (p) = dest_death; | |
2160 | } | |
2161 | break; | |
2162 | } | |
2163 | ||
2164 | /* If SRC is a hard register which is set or killed in | |
2165 | some other way, we can't do this optimization. */ | |
2166 | else if (sregno < FIRST_PSEUDO_REGISTER && dead_or_set_p (p, src)) | |
2167 | break; | |
2168 | } | |
2169 | } | |
2170 | } | |
2171 | ||
2172 | \f | |
2173 | ||
0896cc66 JL |
2174 | /* Return nonzero if REGNO is a particularly bad choice for reloading X. */ |
2175 | static bool | |
2176 | ira_bad_reload_regno_1 (int regno, rtx x) | |
2177 | { | |
ac0ab4f7 | 2178 | int x_regno, n, i; |
0896cc66 JL |
2179 | ira_allocno_t a; |
2180 | enum reg_class pref; | |
2181 | ||
2182 | /* We only deal with pseudo regs. */ | |
2183 | if (! x || GET_CODE (x) != REG) | |
2184 | return false; | |
2185 | ||
2186 | x_regno = REGNO (x); | |
2187 | if (x_regno < FIRST_PSEUDO_REGISTER) | |
2188 | return false; | |
2189 | ||
2190 | /* If the pseudo prefers REGNO explicitly, then do not consider | |
2191 | REGNO a bad spill choice. */ | |
2192 | pref = reg_preferred_class (x_regno); | |
2193 | if (reg_class_size[pref] == 1) | |
2194 | return !TEST_HARD_REG_BIT (reg_class_contents[pref], regno); | |
2195 | ||
2196 | /* If the pseudo conflicts with REGNO, then we consider REGNO a | |
2197 | poor choice for a reload regno. */ | |
2198 | a = ira_regno_allocno_map[x_regno]; | |
ac0ab4f7 BS |
2199 | n = ALLOCNO_NUM_OBJECTS (a); |
2200 | for (i = 0; i < n; i++) | |
2201 | { | |
2202 | ira_object_t obj = ALLOCNO_OBJECT (a, i); | |
2203 | if (TEST_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), regno)) | |
2204 | return true; | |
2205 | } | |
0896cc66 JL |
2206 | return false; |
2207 | } | |
2208 | ||
2209 | /* Return nonzero if REGNO is a particularly bad choice for reloading | |
2210 | IN or OUT. */ | |
2211 | bool | |
2212 | ira_bad_reload_regno (int regno, rtx in, rtx out) | |
2213 | { | |
2214 | return (ira_bad_reload_regno_1 (regno, in) | |
2215 | || ira_bad_reload_regno_1 (regno, out)); | |
2216 | } | |
2217 | ||
b748fbd6 | 2218 | /* Add register clobbers from asm statements. */ |
058e97ec | 2219 | static void |
b748fbd6 | 2220 | compute_regs_asm_clobbered (void) |
058e97ec VM |
2221 | { |
2222 | basic_block bb; | |
2223 | ||
11cd3bed | 2224 | FOR_EACH_BB_FN (bb, cfun) |
058e97ec | 2225 | { |
070a1983 | 2226 | rtx_insn *insn; |
058e97ec VM |
2227 | FOR_BB_INSNS_REVERSE (bb, insn) |
2228 | { | |
bfac633a | 2229 | df_ref def; |
058e97ec | 2230 | |
93671519 | 2231 | if (NONDEBUG_INSN_P (insn) && asm_noperands (PATTERN (insn)) >= 0) |
bfac633a | 2232 | FOR_EACH_INSN_DEF (def, insn) |
058e97ec | 2233 | { |
058e97ec | 2234 | unsigned int dregno = DF_REF_REGNO (def); |
d108e679 AS |
2235 | if (HARD_REGISTER_NUM_P (dregno)) |
2236 | add_to_hard_reg_set (&crtl->asm_clobbers, | |
2237 | GET_MODE (DF_REF_REAL_REG (def)), | |
2238 | dregno); | |
058e97ec VM |
2239 | } |
2240 | } | |
2241 | } | |
2242 | } | |
2243 | ||
2244 | ||
8d49e7ef VM |
2245 | /* Set up ELIMINABLE_REGSET, IRA_NO_ALLOC_REGS, and |
2246 | REGS_EVER_LIVE. */ | |
ce18efcb | 2247 | void |
8d49e7ef | 2248 | ira_setup_eliminable_regset (void) |
058e97ec | 2249 | { |
89ceba31 | 2250 | int i; |
058e97ec | 2251 | static const struct {const int from, to; } eliminables[] = ELIMINABLE_REGS; |
ff33d187 | 2252 | int fp_reg_count = hard_regno_nregs (HARD_FRAME_POINTER_REGNUM, Pmode); |
53680238 | 2253 | |
0064f49e WD |
2254 | /* Setup is_leaf as frame_pointer_required may use it. This function |
2255 | is called by sched_init before ira if scheduling is enabled. */ | |
2256 | crtl->is_leaf = leaf_function_p (); | |
2257 | ||
058e97ec VM |
2258 | /* FIXME: If EXIT_IGNORE_STACK is set, we will not save and restore |
2259 | sp for alloca. So we can't eliminate the frame pointer in that | |
2260 | case. At some point, we should improve this by emitting the | |
2261 | sp-adjusting insns for this case. */ | |
55a2c322 | 2262 | frame_pointer_needed |
058e97ec VM |
2263 | = (! flag_omit_frame_pointer |
2264 | || (cfun->calls_alloca && EXIT_IGNORE_STACK) | |
7700cd85 EB |
2265 | /* We need the frame pointer to catch stack overflow exceptions if |
2266 | the stack pointer is moving (as for the alloca case just above). */ | |
2267 | || (STACK_CHECK_MOVING_SP | |
2268 | && flag_stack_check | |
2269 | && flag_exceptions | |
2270 | && cfun->can_throw_non_call_exceptions) | |
058e97ec | 2271 | || crtl->accesses_prior_frames |
8d49e7ef | 2272 | || (SUPPORTS_STACK_ALIGNMENT && crtl->stack_realign_needed) |
b52b1749 | 2273 | || targetm.frame_pointer_required ()); |
058e97ec | 2274 | |
8d49e7ef VM |
2275 | /* The chance that FRAME_POINTER_NEEDED is changed from inspecting |
2276 | RTL is very small. So if we use frame pointer for RA and RTL | |
2277 | actually prevents this, we will spill pseudos assigned to the | |
2278 | frame pointer in LRA. */ | |
058e97ec | 2279 | |
55a2c322 | 2280 | if (frame_pointer_needed) |
ff33d187 KCY |
2281 | for (i = 0; i < fp_reg_count; i++) |
2282 | df_set_regs_ever_live (HARD_FRAME_POINTER_REGNUM + i, true); | |
55a2c322 | 2283 | |
6576d245 | 2284 | ira_no_alloc_regs = no_unit_alloc_regs; |
058e97ec VM |
2285 | CLEAR_HARD_REG_SET (eliminable_regset); |
2286 | ||
b748fbd6 PB |
2287 | compute_regs_asm_clobbered (); |
2288 | ||
058e97ec VM |
2289 | /* Build the regset of all eliminable registers and show we can't |
2290 | use those that we already know won't be eliminated. */ | |
058e97ec VM |
2291 | for (i = 0; i < (int) ARRAY_SIZE (eliminables); i++) |
2292 | { | |
2293 | bool cannot_elim | |
7b5cbb57 | 2294 | = (! targetm.can_eliminate (eliminables[i].from, eliminables[i].to) |
55a2c322 | 2295 | || (eliminables[i].to == STACK_POINTER_REGNUM && frame_pointer_needed)); |
058e97ec | 2296 | |
b748fbd6 | 2297 | if (!TEST_HARD_REG_BIT (crtl->asm_clobbers, eliminables[i].from)) |
058e97ec VM |
2298 | { |
2299 | SET_HARD_REG_BIT (eliminable_regset, eliminables[i].from); | |
2300 | ||
2301 | if (cannot_elim) | |
2302 | SET_HARD_REG_BIT (ira_no_alloc_regs, eliminables[i].from); | |
2303 | } | |
2304 | else if (cannot_elim) | |
a9c697b8 | 2305 | error ("%s cannot be used in %<asm%> here", |
058e97ec VM |
2306 | reg_names[eliminables[i].from]); |
2307 | else | |
2308 | df_set_regs_ever_live (eliminables[i].from, true); | |
2309 | } | |
c3e08036 | 2310 | if (!HARD_FRAME_POINTER_IS_FRAME_POINTER) |
058e97ec | 2311 | { |
ff33d187 KCY |
2312 | for (i = 0; i < fp_reg_count; i++) |
2313 | if (!TEST_HARD_REG_BIT (crtl->asm_clobbers, | |
2314 | HARD_FRAME_POINTER_REGNUM + i)) | |
2315 | { | |
2316 | SET_HARD_REG_BIT (eliminable_regset, | |
2317 | HARD_FRAME_POINTER_REGNUM + i); | |
2318 | if (frame_pointer_needed) | |
2319 | SET_HARD_REG_BIT (ira_no_alloc_regs, | |
2320 | HARD_FRAME_POINTER_REGNUM + i); | |
2321 | } | |
2322 | else if (frame_pointer_needed) | |
2323 | error ("%s cannot be used in %<asm%> here", | |
2324 | reg_names[HARD_FRAME_POINTER_REGNUM + i]); | |
2325 | else | |
2326 | df_set_regs_ever_live (HARD_FRAME_POINTER_REGNUM + i, true); | |
058e97ec | 2327 | } |
058e97ec VM |
2328 | } |
2329 | ||
2330 | \f | |
2331 | ||
2af2dbdc VM |
2332 | /* Vector of substitutions of register numbers, |
2333 | used to map pseudo regs into hardware regs. | |
2334 | This is set up as a result of register allocation. | |
2335 | Element N is the hard reg assigned to pseudo reg N, | |
2336 | or is -1 if no hard reg was assigned. | |
2337 | If N is a hard reg number, element N is N. */ | |
2338 | short *reg_renumber; | |
2339 | ||
058e97ec VM |
2340 | /* Set up REG_RENUMBER and CALLER_SAVE_NEEDED (used by reload) from |
2341 | the allocation found by IRA. */ | |
2342 | static void | |
2343 | setup_reg_renumber (void) | |
2344 | { | |
2345 | int regno, hard_regno; | |
2346 | ira_allocno_t a; | |
2347 | ira_allocno_iterator ai; | |
2348 | ||
2349 | caller_save_needed = 0; | |
2350 | FOR_EACH_ALLOCNO (a, ai) | |
2351 | { | |
55a2c322 VM |
2352 | if (ira_use_lra_p && ALLOCNO_CAP_MEMBER (a) != NULL) |
2353 | continue; | |
058e97ec VM |
2354 | /* There are no caps at this point. */ |
2355 | ira_assert (ALLOCNO_CAP_MEMBER (a) == NULL); | |
2356 | if (! ALLOCNO_ASSIGNED_P (a)) | |
2357 | /* It can happen if A is not referenced but partially anticipated | |
2358 | somewhere in a region. */ | |
2359 | ALLOCNO_ASSIGNED_P (a) = true; | |
2360 | ira_free_allocno_updated_costs (a); | |
2361 | hard_regno = ALLOCNO_HARD_REGNO (a); | |
1756cb66 | 2362 | regno = ALLOCNO_REGNO (a); |
058e97ec | 2363 | reg_renumber[regno] = (hard_regno < 0 ? -1 : hard_regno); |
1756cb66 | 2364 | if (hard_regno >= 0) |
058e97ec | 2365 | { |
1756cb66 VM |
2366 | int i, nwords; |
2367 | enum reg_class pclass; | |
2368 | ira_object_t obj; | |
2369 | ||
2370 | pclass = ira_pressure_class_translate[REGNO_REG_CLASS (hard_regno)]; | |
2371 | nwords = ALLOCNO_NUM_OBJECTS (a); | |
2372 | for (i = 0; i < nwords; i++) | |
2373 | { | |
2374 | obj = ALLOCNO_OBJECT (a, i); | |
4897c5aa RS |
2375 | OBJECT_TOTAL_CONFLICT_HARD_REGS (obj) |
2376 | |= ~reg_class_contents[pclass]; | |
1756cb66 | 2377 | } |
6c476222 | 2378 | if (ira_need_caller_save_p (a, hard_regno)) |
1756cb66 VM |
2379 | { |
2380 | ira_assert (!optimize || flag_caller_saves | |
e384e6b5 BS |
2381 | || (ALLOCNO_CALLS_CROSSED_NUM (a) |
2382 | == ALLOCNO_CHEAP_CALLS_CROSSED_NUM (a)) | |
15652f68 | 2383 | || regno >= ira_reg_equiv_len |
55a2c322 | 2384 | || ira_equiv_no_lvalue_p (regno)); |
1756cb66 VM |
2385 | caller_save_needed = 1; |
2386 | } | |
058e97ec VM |
2387 | } |
2388 | } | |
2389 | } | |
2390 | ||
2391 | /* Set up allocno assignment flags for further allocation | |
2392 | improvements. */ | |
2393 | static void | |
2394 | setup_allocno_assignment_flags (void) | |
2395 | { | |
2396 | int hard_regno; | |
2397 | ira_allocno_t a; | |
2398 | ira_allocno_iterator ai; | |
2399 | ||
2400 | FOR_EACH_ALLOCNO (a, ai) | |
2401 | { | |
2402 | if (! ALLOCNO_ASSIGNED_P (a)) | |
2403 | /* It can happen if A is not referenced but partially anticipated | |
2404 | somewhere in a region. */ | |
2405 | ira_free_allocno_updated_costs (a); | |
2406 | hard_regno = ALLOCNO_HARD_REGNO (a); | |
2407 | /* Don't assign hard registers to allocnos which are destination | |
2408 | of removed store at the end of loop. It has no sense to keep | |
2409 | the same value in different hard registers. It is also | |
2410 | impossible to assign hard registers correctly to such | |
2411 | allocnos because the cost info and info about intersected | |
2412 | calls are incorrect for them. */ | |
2413 | ALLOCNO_ASSIGNED_P (a) = (hard_regno >= 0 | |
1756cb66 | 2414 | || ALLOCNO_EMIT_DATA (a)->mem_optimized_dest_p |
058e97ec | 2415 | || (ALLOCNO_MEMORY_COST (a) |
1756cb66 | 2416 | - ALLOCNO_CLASS_COST (a)) < 0); |
9181a6e5 VM |
2417 | ira_assert |
2418 | (hard_regno < 0 | |
2419 | || ira_hard_reg_in_set_p (hard_regno, ALLOCNO_MODE (a), | |
2420 | reg_class_contents[ALLOCNO_CLASS (a)])); | |
058e97ec VM |
2421 | } |
2422 | } | |
2423 | ||
2424 | /* Evaluate overall allocation cost and the costs for using hard | |
2425 | registers and memory for allocnos. */ | |
2426 | static void | |
2427 | calculate_allocation_cost (void) | |
2428 | { | |
2429 | int hard_regno, cost; | |
2430 | ira_allocno_t a; | |
2431 | ira_allocno_iterator ai; | |
2432 | ||
2433 | ira_overall_cost = ira_reg_cost = ira_mem_cost = 0; | |
2434 | FOR_EACH_ALLOCNO (a, ai) | |
2435 | { | |
2436 | hard_regno = ALLOCNO_HARD_REGNO (a); | |
2437 | ira_assert (hard_regno < 0 | |
9181a6e5 VM |
2438 | || (ira_hard_reg_in_set_p |
2439 | (hard_regno, ALLOCNO_MODE (a), | |
2440 | reg_class_contents[ALLOCNO_CLASS (a)]))); | |
058e97ec VM |
2441 | if (hard_regno < 0) |
2442 | { | |
2443 | cost = ALLOCNO_MEMORY_COST (a); | |
2444 | ira_mem_cost += cost; | |
2445 | } | |
2446 | else if (ALLOCNO_HARD_REG_COSTS (a) != NULL) | |
2447 | { | |
2448 | cost = (ALLOCNO_HARD_REG_COSTS (a) | |
2449 | [ira_class_hard_reg_index | |
1756cb66 | 2450 | [ALLOCNO_CLASS (a)][hard_regno]]); |
058e97ec VM |
2451 | ira_reg_cost += cost; |
2452 | } | |
2453 | else | |
2454 | { | |
1756cb66 | 2455 | cost = ALLOCNO_CLASS_COST (a); |
058e97ec VM |
2456 | ira_reg_cost += cost; |
2457 | } | |
2458 | ira_overall_cost += cost; | |
2459 | } | |
2460 | ||
2461 | if (internal_flag_ira_verbose > 0 && ira_dump_file != NULL) | |
2462 | { | |
2463 | fprintf (ira_dump_file, | |
16998094 JM |
2464 | "+++Costs: overall %" PRId64 |
2465 | ", reg %" PRId64 | |
2466 | ", mem %" PRId64 | |
2467 | ", ld %" PRId64 | |
2468 | ", st %" PRId64 | |
2469 | ", move %" PRId64, | |
058e97ec VM |
2470 | ira_overall_cost, ira_reg_cost, ira_mem_cost, |
2471 | ira_load_cost, ira_store_cost, ira_shuffle_cost); | |
2bf7560b | 2472 | fprintf (ira_dump_file, "\n+++ move loops %d, new jumps %d\n", |
058e97ec VM |
2473 | ira_move_loops_num, ira_additional_jumps_num); |
2474 | } | |
2475 | ||
2476 | } | |
2477 | ||
2478 | #ifdef ENABLE_IRA_CHECKING | |
2479 | /* Check the correctness of the allocation. We do need this because | |
2480 | of complicated code to transform more one region internal | |
2481 | representation into one region representation. */ | |
2482 | static void | |
2483 | check_allocation (void) | |
2484 | { | |
fa86d337 | 2485 | ira_allocno_t a; |
ac0ab4f7 | 2486 | int hard_regno, nregs, conflict_nregs; |
058e97ec VM |
2487 | ira_allocno_iterator ai; |
2488 | ||
2489 | FOR_EACH_ALLOCNO (a, ai) | |
2490 | { | |
ac0ab4f7 BS |
2491 | int n = ALLOCNO_NUM_OBJECTS (a); |
2492 | int i; | |
fa86d337 | 2493 | |
058e97ec VM |
2494 | if (ALLOCNO_CAP_MEMBER (a) != NULL |
2495 | || (hard_regno = ALLOCNO_HARD_REGNO (a)) < 0) | |
2496 | continue; | |
ad474626 | 2497 | nregs = hard_regno_nregs (hard_regno, ALLOCNO_MODE (a)); |
8cfd82bf BS |
2498 | if (nregs == 1) |
2499 | /* We allocated a single hard register. */ | |
2500 | n = 1; | |
2501 | else if (n > 1) | |
2502 | /* We allocated multiple hard registers, and we will test | |
2503 | conflicts in a granularity of single hard regs. */ | |
2504 | nregs = 1; | |
2505 | ||
ac0ab4f7 BS |
2506 | for (i = 0; i < n; i++) |
2507 | { | |
2508 | ira_object_t obj = ALLOCNO_OBJECT (a, i); | |
2509 | ira_object_t conflict_obj; | |
2510 | ira_object_conflict_iterator oci; | |
2511 | int this_regno = hard_regno; | |
2512 | if (n > 1) | |
fa86d337 | 2513 | { |
2805e6c0 | 2514 | if (REG_WORDS_BIG_ENDIAN) |
ac0ab4f7 BS |
2515 | this_regno += n - i - 1; |
2516 | else | |
2517 | this_regno += i; | |
2518 | } | |
2519 | FOR_EACH_OBJECT_CONFLICT (obj, conflict_obj, oci) | |
2520 | { | |
2521 | ira_allocno_t conflict_a = OBJECT_ALLOCNO (conflict_obj); | |
2522 | int conflict_hard_regno = ALLOCNO_HARD_REGNO (conflict_a); | |
2523 | if (conflict_hard_regno < 0) | |
2524 | continue; | |
8cfd82bf | 2525 | |
ad474626 RS |
2526 | conflict_nregs = hard_regno_nregs (conflict_hard_regno, |
2527 | ALLOCNO_MODE (conflict_a)); | |
8cfd82bf BS |
2528 | |
2529 | if (ALLOCNO_NUM_OBJECTS (conflict_a) > 1 | |
2530 | && conflict_nregs == ALLOCNO_NUM_OBJECTS (conflict_a)) | |
ac0ab4f7 | 2531 | { |
2805e6c0 | 2532 | if (REG_WORDS_BIG_ENDIAN) |
ac0ab4f7 BS |
2533 | conflict_hard_regno += (ALLOCNO_NUM_OBJECTS (conflict_a) |
2534 | - OBJECT_SUBWORD (conflict_obj) - 1); | |
2535 | else | |
2536 | conflict_hard_regno += OBJECT_SUBWORD (conflict_obj); | |
2537 | conflict_nregs = 1; | |
2538 | } | |
ac0ab4f7 BS |
2539 | |
2540 | if ((conflict_hard_regno <= this_regno | |
2541 | && this_regno < conflict_hard_regno + conflict_nregs) | |
2542 | || (this_regno <= conflict_hard_regno | |
2543 | && conflict_hard_regno < this_regno + nregs)) | |
fa86d337 BS |
2544 | { |
2545 | fprintf (stderr, "bad allocation for %d and %d\n", | |
2546 | ALLOCNO_REGNO (a), ALLOCNO_REGNO (conflict_a)); | |
2547 | gcc_unreachable (); | |
2548 | } | |
2549 | } | |
2550 | } | |
058e97ec VM |
2551 | } |
2552 | } | |
2553 | #endif | |
2554 | ||
55a2c322 VM |
2555 | /* Allocate REG_EQUIV_INIT. Set up it from IRA_REG_EQUIV which should |
2556 | be already calculated. */ | |
2557 | static void | |
2558 | setup_reg_equiv_init (void) | |
2559 | { | |
2560 | int i; | |
2561 | int max_regno = max_reg_num (); | |
2562 | ||
2563 | for (i = 0; i < max_regno; i++) | |
2564 | reg_equiv_init (i) = ira_reg_equiv[i].init_insns; | |
2565 | } | |
2566 | ||
2567 | /* Update equiv regno from movement of FROM_REGNO to TO_REGNO. INSNS | |
2568 | are insns which were generated for such movement. It is assumed | |
2569 | that FROM_REGNO and TO_REGNO always have the same value at the | |
2570 | point of any move containing such registers. This function is used | |
2571 | to update equiv info for register shuffles on the region borders | |
2572 | and for caller save/restore insns. */ | |
2573 | void | |
b32d5189 | 2574 | ira_update_equiv_info_by_shuffle_insn (int to_regno, int from_regno, rtx_insn *insns) |
55a2c322 | 2575 | { |
b32d5189 DM |
2576 | rtx_insn *insn; |
2577 | rtx x, note; | |
55a2c322 VM |
2578 | |
2579 | if (! ira_reg_equiv[from_regno].defined_p | |
2580 | && (! ira_reg_equiv[to_regno].defined_p | |
2581 | || ((x = ira_reg_equiv[to_regno].memory) != NULL_RTX | |
2582 | && ! MEM_READONLY_P (x)))) | |
5a107a0f | 2583 | return; |
55a2c322 VM |
2584 | insn = insns; |
2585 | if (NEXT_INSN (insn) != NULL_RTX) | |
2586 | { | |
2587 | if (! ira_reg_equiv[to_regno].defined_p) | |
2588 | { | |
2589 | ira_assert (ira_reg_equiv[to_regno].init_insns == NULL_RTX); | |
2590 | return; | |
2591 | } | |
2592 | ira_reg_equiv[to_regno].defined_p = false; | |
2593 | ira_reg_equiv[to_regno].memory | |
2594 | = ira_reg_equiv[to_regno].constant | |
2595 | = ira_reg_equiv[to_regno].invariant | |
0cc97fc5 | 2596 | = ira_reg_equiv[to_regno].init_insns = NULL; |
55a2c322 VM |
2597 | if (internal_flag_ira_verbose > 3 && ira_dump_file != NULL) |
2598 | fprintf (ira_dump_file, | |
2599 | " Invalidating equiv info for reg %d\n", to_regno); | |
2600 | return; | |
2601 | } | |
2602 | /* It is possible that FROM_REGNO still has no equivalence because | |
2603 | in shuffles to_regno<-from_regno and from_regno<-to_regno the 2nd | |
2604 | insn was not processed yet. */ | |
2605 | if (ira_reg_equiv[from_regno].defined_p) | |
2606 | { | |
2607 | ira_reg_equiv[to_regno].defined_p = true; | |
2608 | if ((x = ira_reg_equiv[from_regno].memory) != NULL_RTX) | |
2609 | { | |
2610 | ira_assert (ira_reg_equiv[from_regno].invariant == NULL_RTX | |
2611 | && ira_reg_equiv[from_regno].constant == NULL_RTX); | |
2612 | ira_assert (ira_reg_equiv[to_regno].memory == NULL_RTX | |
2613 | || rtx_equal_p (ira_reg_equiv[to_regno].memory, x)); | |
2614 | ira_reg_equiv[to_regno].memory = x; | |
2615 | if (! MEM_READONLY_P (x)) | |
2616 | /* We don't add the insn to insn init list because memory | |
2617 | equivalence is just to say what memory is better to use | |
2618 | when the pseudo is spilled. */ | |
2619 | return; | |
2620 | } | |
2621 | else if ((x = ira_reg_equiv[from_regno].constant) != NULL_RTX) | |
2622 | { | |
2623 | ira_assert (ira_reg_equiv[from_regno].invariant == NULL_RTX); | |
2624 | ira_assert (ira_reg_equiv[to_regno].constant == NULL_RTX | |
2625 | || rtx_equal_p (ira_reg_equiv[to_regno].constant, x)); | |
2626 | ira_reg_equiv[to_regno].constant = x; | |
2627 | } | |
2628 | else | |
2629 | { | |
2630 | x = ira_reg_equiv[from_regno].invariant; | |
2631 | ira_assert (x != NULL_RTX); | |
2632 | ira_assert (ira_reg_equiv[to_regno].invariant == NULL_RTX | |
2633 | || rtx_equal_p (ira_reg_equiv[to_regno].invariant, x)); | |
2634 | ira_reg_equiv[to_regno].invariant = x; | |
2635 | } | |
2636 | if (find_reg_note (insn, REG_EQUIV, x) == NULL_RTX) | |
2637 | { | |
2c797321 | 2638 | note = set_unique_reg_note (insn, REG_EQUIV, copy_rtx (x)); |
55a2c322 VM |
2639 | gcc_assert (note != NULL_RTX); |
2640 | if (internal_flag_ira_verbose > 3 && ira_dump_file != NULL) | |
2641 | { | |
2642 | fprintf (ira_dump_file, | |
2643 | " Adding equiv note to insn %u for reg %d ", | |
2644 | INSN_UID (insn), to_regno); | |
cfbeaedf | 2645 | dump_value_slim (ira_dump_file, x, 1); |
55a2c322 VM |
2646 | fprintf (ira_dump_file, "\n"); |
2647 | } | |
2648 | } | |
2649 | } | |
2650 | ira_reg_equiv[to_regno].init_insns | |
2651 | = gen_rtx_INSN_LIST (VOIDmode, insn, | |
2652 | ira_reg_equiv[to_regno].init_insns); | |
2653 | if (internal_flag_ira_verbose > 3 && ira_dump_file != NULL) | |
2654 | fprintf (ira_dump_file, | |
2655 | " Adding equiv init move insn %u to reg %d\n", | |
2656 | INSN_UID (insn), to_regno); | |
2657 | } | |
2658 | ||
058e97ec VM |
2659 | /* Fix values of array REG_EQUIV_INIT after live range splitting done |
2660 | by IRA. */ | |
2661 | static void | |
2662 | fix_reg_equiv_init (void) | |
2663 | { | |
70cc3288 | 2664 | int max_regno = max_reg_num (); |
f2034d06 | 2665 | int i, new_regno, max; |
618bccf9 TS |
2666 | rtx set; |
2667 | rtx_insn_list *x, *next, *prev; | |
2668 | rtx_insn *insn; | |
b8698a0f | 2669 | |
70cc3288 | 2670 | if (max_regno_before_ira < max_regno) |
058e97ec | 2671 | { |
9771b263 | 2672 | max = vec_safe_length (reg_equivs); |
f2034d06 JL |
2673 | grow_reg_equivs (); |
2674 | for (i = FIRST_PSEUDO_REGISTER; i < max; i++) | |
618bccf9 | 2675 | for (prev = NULL, x = reg_equiv_init (i); |
f2034d06 JL |
2676 | x != NULL_RTX; |
2677 | x = next) | |
058e97ec | 2678 | { |
618bccf9 TS |
2679 | next = x->next (); |
2680 | insn = x->insn (); | |
2681 | set = single_set (insn); | |
058e97ec VM |
2682 | ira_assert (set != NULL_RTX |
2683 | && (REG_P (SET_DEST (set)) || REG_P (SET_SRC (set)))); | |
2684 | if (REG_P (SET_DEST (set)) | |
2685 | && ((int) REGNO (SET_DEST (set)) == i | |
2686 | || (int) ORIGINAL_REGNO (SET_DEST (set)) == i)) | |
2687 | new_regno = REGNO (SET_DEST (set)); | |
2688 | else if (REG_P (SET_SRC (set)) | |
2689 | && ((int) REGNO (SET_SRC (set)) == i | |
2690 | || (int) ORIGINAL_REGNO (SET_SRC (set)) == i)) | |
2691 | new_regno = REGNO (SET_SRC (set)); | |
2692 | else | |
2693 | gcc_unreachable (); | |
2694 | if (new_regno == i) | |
2695 | prev = x; | |
2696 | else | |
2697 | { | |
55a2c322 | 2698 | /* Remove the wrong list element. */ |
058e97ec | 2699 | if (prev == NULL_RTX) |
f2034d06 | 2700 | reg_equiv_init (i) = next; |
058e97ec VM |
2701 | else |
2702 | XEXP (prev, 1) = next; | |
f2034d06 JL |
2703 | XEXP (x, 1) = reg_equiv_init (new_regno); |
2704 | reg_equiv_init (new_regno) = x; | |
058e97ec VM |
2705 | } |
2706 | } | |
2707 | } | |
2708 | } | |
2709 | ||
2710 | #ifdef ENABLE_IRA_CHECKING | |
2711 | /* Print redundant memory-memory copies. */ | |
2712 | static void | |
2713 | print_redundant_copies (void) | |
2714 | { | |
2715 | int hard_regno; | |
2716 | ira_allocno_t a; | |
2717 | ira_copy_t cp, next_cp; | |
2718 | ira_allocno_iterator ai; | |
b8698a0f | 2719 | |
058e97ec VM |
2720 | FOR_EACH_ALLOCNO (a, ai) |
2721 | { | |
2722 | if (ALLOCNO_CAP_MEMBER (a) != NULL) | |
2b9c63a2 | 2723 | /* It is a cap. */ |
058e97ec VM |
2724 | continue; |
2725 | hard_regno = ALLOCNO_HARD_REGNO (a); | |
2726 | if (hard_regno >= 0) | |
2727 | continue; | |
2728 | for (cp = ALLOCNO_COPIES (a); cp != NULL; cp = next_cp) | |
2729 | if (cp->first == a) | |
2730 | next_cp = cp->next_first_allocno_copy; | |
2731 | else | |
2732 | { | |
2733 | next_cp = cp->next_second_allocno_copy; | |
2734 | if (internal_flag_ira_verbose > 4 && ira_dump_file != NULL | |
2735 | && cp->insn != NULL_RTX | |
2736 | && ALLOCNO_HARD_REGNO (cp->first) == hard_regno) | |
2737 | fprintf (ira_dump_file, | |
2738 | " Redundant move from %d(freq %d):%d\n", | |
2739 | INSN_UID (cp->insn), cp->freq, hard_regno); | |
2740 | } | |
2741 | } | |
2742 | } | |
2743 | #endif | |
2744 | ||
2745 | /* Setup preferred and alternative classes for new pseudo-registers | |
2746 | created by IRA starting with START. */ | |
2747 | static void | |
2748 | setup_preferred_alternate_classes_for_new_pseudos (int start) | |
2749 | { | |
2750 | int i, old_regno; | |
2751 | int max_regno = max_reg_num (); | |
2752 | ||
2753 | for (i = start; i < max_regno; i++) | |
2754 | { | |
2755 | old_regno = ORIGINAL_REGNO (regno_reg_rtx[i]); | |
b8698a0f | 2756 | ira_assert (i != old_regno); |
058e97ec | 2757 | setup_reg_classes (i, reg_preferred_class (old_regno), |
ce18efcb | 2758 | reg_alternate_class (old_regno), |
1756cb66 | 2759 | reg_allocno_class (old_regno)); |
058e97ec VM |
2760 | if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL) |
2761 | fprintf (ira_dump_file, | |
2762 | " New r%d: setting preferred %s, alternative %s\n", | |
2763 | i, reg_class_names[reg_preferred_class (old_regno)], | |
2764 | reg_class_names[reg_alternate_class (old_regno)]); | |
2765 | } | |
2766 | } | |
2767 | ||
2768 | \f | |
df3e3493 | 2769 | /* The number of entries allocated in reg_info. */ |
fb99ee9b | 2770 | static int allocated_reg_info_size; |
058e97ec VM |
2771 | |
2772 | /* Regional allocation can create new pseudo-registers. This function | |
2773 | expands some arrays for pseudo-registers. */ | |
2774 | static void | |
fb99ee9b | 2775 | expand_reg_info (void) |
058e97ec VM |
2776 | { |
2777 | int i; | |
2778 | int size = max_reg_num (); | |
2779 | ||
2780 | resize_reg_info (); | |
fb99ee9b | 2781 | for (i = allocated_reg_info_size; i < size; i++) |
ce18efcb | 2782 | setup_reg_classes (i, GENERAL_REGS, ALL_REGS, GENERAL_REGS); |
fb99ee9b BS |
2783 | setup_preferred_alternate_classes_for_new_pseudos (allocated_reg_info_size); |
2784 | allocated_reg_info_size = size; | |
058e97ec VM |
2785 | } |
2786 | ||
3553f0bb VM |
2787 | /* Return TRUE if there is too high register pressure in the function. |
2788 | It is used to decide when stack slot sharing is worth to do. */ | |
2789 | static bool | |
2790 | too_high_register_pressure_p (void) | |
2791 | { | |
2792 | int i; | |
1756cb66 | 2793 | enum reg_class pclass; |
b8698a0f | 2794 | |
1756cb66 | 2795 | for (i = 0; i < ira_pressure_classes_num; i++) |
3553f0bb | 2796 | { |
1756cb66 VM |
2797 | pclass = ira_pressure_classes[i]; |
2798 | if (ira_loop_tree_root->reg_pressure[pclass] > 10000) | |
3553f0bb VM |
2799 | return true; |
2800 | } | |
2801 | return false; | |
2802 | } | |
2803 | ||
058e97ec VM |
2804 | \f |
2805 | ||
2af2dbdc VM |
2806 | /* Indicate that hard register number FROM was eliminated and replaced with |
2807 | an offset from hard register number TO. The status of hard registers live | |
2808 | at the start of a basic block is updated by replacing a use of FROM with | |
2809 | a use of TO. */ | |
2810 | ||
2811 | void | |
2812 | mark_elimination (int from, int to) | |
2813 | { | |
2814 | basic_block bb; | |
bf744527 | 2815 | bitmap r; |
2af2dbdc | 2816 | |
11cd3bed | 2817 | FOR_EACH_BB_FN (bb, cfun) |
2af2dbdc | 2818 | { |
bf744527 SB |
2819 | r = DF_LR_IN (bb); |
2820 | if (bitmap_bit_p (r, from)) | |
2821 | { | |
2822 | bitmap_clear_bit (r, from); | |
2823 | bitmap_set_bit (r, to); | |
2824 | } | |
2825 | if (! df_live) | |
2826 | continue; | |
2827 | r = DF_LIVE_IN (bb); | |
2828 | if (bitmap_bit_p (r, from)) | |
2af2dbdc | 2829 | { |
bf744527 SB |
2830 | bitmap_clear_bit (r, from); |
2831 | bitmap_set_bit (r, to); | |
2af2dbdc VM |
2832 | } |
2833 | } | |
2834 | } | |
2835 | ||
2836 | \f | |
2837 | ||
55a2c322 VM |
2838 | /* The length of the following array. */ |
2839 | int ira_reg_equiv_len; | |
2840 | ||
2841 | /* Info about equiv. info for each register. */ | |
4c2b2d79 | 2842 | struct ira_reg_equiv_s *ira_reg_equiv; |
55a2c322 VM |
2843 | |
2844 | /* Expand ira_reg_equiv if necessary. */ | |
2845 | void | |
2846 | ira_expand_reg_equiv (void) | |
2847 | { | |
2848 | int old = ira_reg_equiv_len; | |
2849 | ||
2850 | if (ira_reg_equiv_len > max_reg_num ()) | |
2851 | return; | |
2852 | ira_reg_equiv_len = max_reg_num () * 3 / 2 + 1; | |
2853 | ira_reg_equiv | |
4c2b2d79 | 2854 | = (struct ira_reg_equiv_s *) xrealloc (ira_reg_equiv, |
55a2c322 | 2855 | ira_reg_equiv_len |
4c2b2d79 | 2856 | * sizeof (struct ira_reg_equiv_s)); |
55a2c322 VM |
2857 | gcc_assert (old < ira_reg_equiv_len); |
2858 | memset (ira_reg_equiv + old, 0, | |
4c2b2d79 | 2859 | sizeof (struct ira_reg_equiv_s) * (ira_reg_equiv_len - old)); |
55a2c322 VM |
2860 | } |
2861 | ||
2862 | static void | |
2863 | init_reg_equiv (void) | |
2864 | { | |
2865 | ira_reg_equiv_len = 0; | |
2866 | ira_reg_equiv = NULL; | |
2867 | ira_expand_reg_equiv (); | |
2868 | } | |
2869 | ||
2870 | static void | |
2871 | finish_reg_equiv (void) | |
2872 | { | |
2873 | free (ira_reg_equiv); | |
2874 | } | |
2875 | ||
2876 | \f | |
2877 | ||
2af2dbdc VM |
2878 | struct equivalence |
2879 | { | |
2af2dbdc VM |
2880 | /* Set when a REG_EQUIV note is found or created. Use to |
2881 | keep track of what memory accesses might be created later, | |
2882 | e.g. by reload. */ | |
2883 | rtx replacement; | |
2884 | rtx *src_p; | |
fb0ab697 JL |
2885 | |
2886 | /* The list of each instruction which initializes this register. | |
2887 | ||
2888 | NULL indicates we know nothing about this register's equivalence | |
2889 | properties. | |
2890 | ||
2891 | An INSN_LIST with a NULL insn indicates this pseudo is already | |
2892 | known to not have a valid equivalence. */ | |
2893 | rtx_insn_list *init_insns; | |
2894 | ||
2af2dbdc VM |
2895 | /* Loop depth is used to recognize equivalences which appear |
2896 | to be present within the same loop (or in an inner loop). */ | |
5ffa4e6a | 2897 | short loop_depth; |
2af2dbdc | 2898 | /* Nonzero if this had a preexisting REG_EQUIV note. */ |
5ffa4e6a | 2899 | unsigned char is_arg_equivalence : 1; |
8f5929e1 JJ |
2900 | /* Set when an attempt should be made to replace a register |
2901 | with the associated src_p entry. */ | |
5ffa4e6a FY |
2902 | unsigned char replace : 1; |
2903 | /* Set if this register has no known equivalence. */ | |
2904 | unsigned char no_equiv : 1; | |
8c1d8b59 AM |
2905 | /* Set if this register is mentioned in a paradoxical subreg. */ |
2906 | unsigned char pdx_subregs : 1; | |
2af2dbdc VM |
2907 | }; |
2908 | ||
2909 | /* reg_equiv[N] (where N is a pseudo reg number) is the equivalence | |
2910 | structure for that register. */ | |
2911 | static struct equivalence *reg_equiv; | |
2912 | ||
c7a99fc6 AM |
2913 | /* Used for communication between the following two functions. */ |
2914 | struct equiv_mem_data | |
2915 | { | |
2916 | /* A MEM that we wish to ensure remains unchanged. */ | |
2917 | rtx equiv_mem; | |
2af2dbdc | 2918 | |
c7a99fc6 AM |
2919 | /* Set true if EQUIV_MEM is modified. */ |
2920 | bool equiv_mem_modified; | |
2921 | }; | |
2af2dbdc VM |
2922 | |
2923 | /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified. | |
2924 | Called via note_stores. */ | |
2925 | static void | |
2926 | validate_equiv_mem_from_store (rtx dest, const_rtx set ATTRIBUTE_UNUSED, | |
c7a99fc6 | 2927 | void *data) |
2af2dbdc | 2928 | { |
c7a99fc6 AM |
2929 | struct equiv_mem_data *info = (struct equiv_mem_data *) data; |
2930 | ||
2af2dbdc | 2931 | if ((REG_P (dest) |
c7a99fc6 | 2932 | && reg_overlap_mentioned_p (dest, info->equiv_mem)) |
2af2dbdc | 2933 | || (MEM_P (dest) |
c7a99fc6 AM |
2934 | && anti_dependence (info->equiv_mem, dest))) |
2935 | info->equiv_mem_modified = true; | |
2af2dbdc VM |
2936 | } |
2937 | ||
63ce14e0 AM |
2938 | enum valid_equiv { valid_none, valid_combine, valid_reload }; |
2939 | ||
2af2dbdc VM |
2940 | /* Verify that no store between START and the death of REG invalidates |
2941 | MEMREF. MEMREF is invalidated by modifying a register used in MEMREF, | |
2942 | by storing into an overlapping memory location, or with a non-const | |
2943 | CALL_INSN. | |
2944 | ||
63ce14e0 AM |
2945 | Return VALID_RELOAD if MEMREF remains valid for both reload and |
2946 | combine_and_move insns, VALID_COMBINE if only valid for | |
2947 | combine_and_move_insns, and VALID_NONE otherwise. */ | |
2948 | static enum valid_equiv | |
b32d5189 | 2949 | validate_equiv_mem (rtx_insn *start, rtx reg, rtx memref) |
2af2dbdc | 2950 | { |
b32d5189 | 2951 | rtx_insn *insn; |
2af2dbdc | 2952 | rtx note; |
c7a99fc6 | 2953 | struct equiv_mem_data info = { memref, false }; |
63ce14e0 | 2954 | enum valid_equiv ret = valid_reload; |
2af2dbdc VM |
2955 | |
2956 | /* If the memory reference has side effects or is volatile, it isn't a | |
2957 | valid equivalence. */ | |
2958 | if (side_effects_p (memref)) | |
63ce14e0 | 2959 | return valid_none; |
2af2dbdc | 2960 | |
c7a99fc6 | 2961 | for (insn = start; insn; insn = NEXT_INSN (insn)) |
2af2dbdc | 2962 | { |
63ce14e0 | 2963 | if (!INSN_P (insn)) |
2af2dbdc VM |
2964 | continue; |
2965 | ||
2966 | if (find_reg_note (insn, REG_DEAD, reg)) | |
63ce14e0 | 2967 | return ret; |
2af2dbdc | 2968 | |
a22265a4 | 2969 | if (CALL_P (insn)) |
63ce14e0 AM |
2970 | { |
2971 | /* We can combine a reg def from one insn into a reg use in | |
2972 | another over a call if the memory is readonly or the call | |
2973 | const/pure. However, we can't set reg_equiv notes up for | |
2974 | reload over any call. The problem is the equivalent form | |
2975 | may reference a pseudo which gets assigned a call | |
2976 | clobbered hard reg. When we later replace REG with its | |
2977 | equivalent form, the value in the call-clobbered reg has | |
2978 | been changed and all hell breaks loose. */ | |
2979 | ret = valid_combine; | |
2980 | if (!MEM_READONLY_P (memref) | |
2981 | && !RTL_CONST_OR_PURE_CALL_P (insn)) | |
2982 | return valid_none; | |
2983 | } | |
2af2dbdc | 2984 | |
e8448ba5 | 2985 | note_stores (insn, validate_equiv_mem_from_store, &info); |
c7a99fc6 | 2986 | if (info.equiv_mem_modified) |
63ce14e0 | 2987 | return valid_none; |
2af2dbdc VM |
2988 | |
2989 | /* If a register mentioned in MEMREF is modified via an | |
2990 | auto-increment, we lose the equivalence. Do the same if one | |
2991 | dies; although we could extend the life, it doesn't seem worth | |
2992 | the trouble. */ | |
2993 | ||
2994 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
2995 | if ((REG_NOTE_KIND (note) == REG_INC | |
2996 | || REG_NOTE_KIND (note) == REG_DEAD) | |
2997 | && REG_P (XEXP (note, 0)) | |
2998 | && reg_overlap_mentioned_p (XEXP (note, 0), memref)) | |
63ce14e0 | 2999 | return valid_none; |
2af2dbdc VM |
3000 | } |
3001 | ||
63ce14e0 | 3002 | return valid_none; |
2af2dbdc VM |
3003 | } |
3004 | ||
3005 | /* Returns zero if X is known to be invariant. */ | |
3006 | static int | |
3007 | equiv_init_varies_p (rtx x) | |
3008 | { | |
3009 | RTX_CODE code = GET_CODE (x); | |
3010 | int i; | |
3011 | const char *fmt; | |
3012 | ||
3013 | switch (code) | |
3014 | { | |
3015 | case MEM: | |
3016 | return !MEM_READONLY_P (x) || equiv_init_varies_p (XEXP (x, 0)); | |
3017 | ||
3018 | case CONST: | |
d8116890 | 3019 | CASE_CONST_ANY: |
2af2dbdc VM |
3020 | case SYMBOL_REF: |
3021 | case LABEL_REF: | |
3022 | return 0; | |
3023 | ||
3024 | case REG: | |
3025 | return reg_equiv[REGNO (x)].replace == 0 && rtx_varies_p (x, 0); | |
3026 | ||
3027 | case ASM_OPERANDS: | |
3028 | if (MEM_VOLATILE_P (x)) | |
3029 | return 1; | |
3030 | ||
3031 | /* Fall through. */ | |
3032 | ||
3033 | default: | |
3034 | break; | |
3035 | } | |
3036 | ||
3037 | fmt = GET_RTX_FORMAT (code); | |
3038 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3039 | if (fmt[i] == 'e') | |
3040 | { | |
3041 | if (equiv_init_varies_p (XEXP (x, i))) | |
3042 | return 1; | |
3043 | } | |
3044 | else if (fmt[i] == 'E') | |
3045 | { | |
3046 | int j; | |
3047 | for (j = 0; j < XVECLEN (x, i); j++) | |
3048 | if (equiv_init_varies_p (XVECEXP (x, i, j))) | |
3049 | return 1; | |
3050 | } | |
3051 | ||
3052 | return 0; | |
3053 | } | |
3054 | ||
3055 | /* Returns nonzero if X (used to initialize register REGNO) is movable. | |
3056 | X is only movable if the registers it uses have equivalent initializations | |
3057 | which appear to be within the same loop (or in an inner loop) and movable | |
3058 | or if they are not candidates for local_alloc and don't vary. */ | |
3059 | static int | |
3060 | equiv_init_movable_p (rtx x, int regno) | |
3061 | { | |
3062 | int i, j; | |
3063 | const char *fmt; | |
3064 | enum rtx_code code = GET_CODE (x); | |
3065 | ||
3066 | switch (code) | |
3067 | { | |
3068 | case SET: | |
3069 | return equiv_init_movable_p (SET_SRC (x), regno); | |
3070 | ||
3071 | case CC0: | |
3072 | case CLOBBER: | |
3073 | return 0; | |
3074 | ||
3075 | case PRE_INC: | |
3076 | case PRE_DEC: | |
3077 | case POST_INC: | |
3078 | case POST_DEC: | |
3079 | case PRE_MODIFY: | |
3080 | case POST_MODIFY: | |
3081 | return 0; | |
3082 | ||
3083 | case REG: | |
1756cb66 VM |
3084 | return ((reg_equiv[REGNO (x)].loop_depth >= reg_equiv[regno].loop_depth |
3085 | && reg_equiv[REGNO (x)].replace) | |
3086 | || (REG_BASIC_BLOCK (REGNO (x)) < NUM_FIXED_BLOCKS | |
3087 | && ! rtx_varies_p (x, 0))); | |
2af2dbdc VM |
3088 | |
3089 | case UNSPEC_VOLATILE: | |
3090 | return 0; | |
3091 | ||
3092 | case ASM_OPERANDS: | |
3093 | if (MEM_VOLATILE_P (x)) | |
3094 | return 0; | |
3095 | ||
3096 | /* Fall through. */ | |
3097 | ||
3098 | default: | |
3099 | break; | |
3100 | } | |
3101 | ||
3102 | fmt = GET_RTX_FORMAT (code); | |
3103 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3104 | switch (fmt[i]) | |
3105 | { | |
3106 | case 'e': | |
3107 | if (! equiv_init_movable_p (XEXP (x, i), regno)) | |
3108 | return 0; | |
3109 | break; | |
3110 | case 'E': | |
3111 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
3112 | if (! equiv_init_movable_p (XVECEXP (x, i, j), regno)) | |
3113 | return 0; | |
3114 | break; | |
3115 | } | |
3116 | ||
3117 | return 1; | |
3118 | } | |
3119 | ||
cc30d932 VM |
3120 | static bool memref_referenced_p (rtx memref, rtx x, bool read_p); |
3121 | ||
3122 | /* Auxiliary function for memref_referenced_p. Process setting X for | |
3123 | MEMREF store. */ | |
3124 | static bool | |
3125 | process_set_for_memref_referenced_p (rtx memref, rtx x) | |
3126 | { | |
3127 | /* If we are setting a MEM, it doesn't count (its address does), but any | |
3128 | other SET_DEST that has a MEM in it is referencing the MEM. */ | |
3129 | if (MEM_P (x)) | |
3130 | { | |
3131 | if (memref_referenced_p (memref, XEXP (x, 0), true)) | |
3132 | return true; | |
3133 | } | |
3134 | else if (memref_referenced_p (memref, x, false)) | |
3135 | return true; | |
3136 | ||
3137 | return false; | |
3138 | } | |
3139 | ||
3140 | /* TRUE if X references a memory location (as a read if READ_P) that | |
3141 | would be affected by a store to MEMREF. */ | |
3142 | static bool | |
3143 | memref_referenced_p (rtx memref, rtx x, bool read_p) | |
2af2dbdc VM |
3144 | { |
3145 | int i, j; | |
3146 | const char *fmt; | |
3147 | enum rtx_code code = GET_CODE (x); | |
3148 | ||
3149 | switch (code) | |
3150 | { | |
2af2dbdc VM |
3151 | case CONST: |
3152 | case LABEL_REF: | |
3153 | case SYMBOL_REF: | |
d8116890 | 3154 | CASE_CONST_ANY: |
2af2dbdc VM |
3155 | case PC: |
3156 | case CC0: | |
3157 | case HIGH: | |
3158 | case LO_SUM: | |
cc30d932 | 3159 | return false; |
2af2dbdc VM |
3160 | |
3161 | case REG: | |
3162 | return (reg_equiv[REGNO (x)].replacement | |
3163 | && memref_referenced_p (memref, | |
cc30d932 | 3164 | reg_equiv[REGNO (x)].replacement, read_p)); |
2af2dbdc VM |
3165 | |
3166 | case MEM: | |
cc30d932 VM |
3167 | /* Memory X might have another effective type than MEMREF. */ |
3168 | if (read_p || true_dependence (memref, VOIDmode, x)) | |
3169 | return true; | |
2af2dbdc VM |
3170 | break; |
3171 | ||
3172 | case SET: | |
cc30d932 VM |
3173 | if (process_set_for_memref_referenced_p (memref, SET_DEST (x))) |
3174 | return true; | |
3175 | ||
3176 | return memref_referenced_p (memref, SET_SRC (x), true); | |
3177 | ||
3178 | case CLOBBER: | |
cc30d932 VM |
3179 | if (process_set_for_memref_referenced_p (memref, XEXP (x, 0))) |
3180 | return true; | |
2af2dbdc | 3181 | |
cc30d932 VM |
3182 | return false; |
3183 | ||
3184 | case PRE_DEC: | |
3185 | case POST_DEC: | |
3186 | case PRE_INC: | |
3187 | case POST_INC: | |
3188 | if (process_set_for_memref_referenced_p (memref, XEXP (x, 0))) | |
3189 | return true; | |
3190 | ||
3191 | return memref_referenced_p (memref, XEXP (x, 0), true); | |
3192 | ||
3193 | case POST_MODIFY: | |
3194 | case PRE_MODIFY: | |
3195 | /* op0 = op0 + op1 */ | |
3196 | if (process_set_for_memref_referenced_p (memref, XEXP (x, 0))) | |
3197 | return true; | |
3198 | ||
3199 | if (memref_referenced_p (memref, XEXP (x, 0), true)) | |
3200 | return true; | |
3201 | ||
3202 | return memref_referenced_p (memref, XEXP (x, 1), true); | |
2af2dbdc VM |
3203 | |
3204 | default: | |
3205 | break; | |
3206 | } | |
3207 | ||
3208 | fmt = GET_RTX_FORMAT (code); | |
3209 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3210 | switch (fmt[i]) | |
3211 | { | |
3212 | case 'e': | |
cc30d932 VM |
3213 | if (memref_referenced_p (memref, XEXP (x, i), read_p)) |
3214 | return true; | |
2af2dbdc VM |
3215 | break; |
3216 | case 'E': | |
3217 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
cc30d932 VM |
3218 | if (memref_referenced_p (memref, XVECEXP (x, i, j), read_p)) |
3219 | return true; | |
2af2dbdc VM |
3220 | break; |
3221 | } | |
3222 | ||
cc30d932 | 3223 | return false; |
2af2dbdc VM |
3224 | } |
3225 | ||
3226 | /* TRUE if some insn in the range (START, END] references a memory location | |
14d7d4be JL |
3227 | that would be affected by a store to MEMREF. |
3228 | ||
3229 | Callers should not call this routine if START is after END in the | |
3230 | RTL chain. */ | |
3231 | ||
2af2dbdc | 3232 | static int |
b32d5189 | 3233 | memref_used_between_p (rtx memref, rtx_insn *start, rtx_insn *end) |
2af2dbdc | 3234 | { |
b32d5189 | 3235 | rtx_insn *insn; |
2af2dbdc | 3236 | |
14d7d4be JL |
3237 | for (insn = NEXT_INSN (start); |
3238 | insn && insn != NEXT_INSN (end); | |
2af2dbdc VM |
3239 | insn = NEXT_INSN (insn)) |
3240 | { | |
b5b8b0ac | 3241 | if (!NONDEBUG_INSN_P (insn)) |
2af2dbdc | 3242 | continue; |
b8698a0f | 3243 | |
cc30d932 | 3244 | if (memref_referenced_p (memref, PATTERN (insn), false)) |
2af2dbdc VM |
3245 | return 1; |
3246 | ||
3247 | /* Nonconst functions may access memory. */ | |
3248 | if (CALL_P (insn) && (! RTL_CONST_CALL_P (insn))) | |
3249 | return 1; | |
3250 | } | |
3251 | ||
14d7d4be | 3252 | gcc_assert (insn == NEXT_INSN (end)); |
2af2dbdc VM |
3253 | return 0; |
3254 | } | |
3255 | ||
3256 | /* Mark REG as having no known equivalence. | |
3257 | Some instructions might have been processed before and furnished | |
3258 | with REG_EQUIV notes for this register; these notes will have to be | |
3259 | removed. | |
3260 | STORE is the piece of RTL that does the non-constant / conflicting | |
3261 | assignment - a SET, CLOBBER or REG_INC note. It is currently not used, | |
3262 | but needs to be there because this function is called from note_stores. */ | |
3263 | static void | |
1756cb66 VM |
3264 | no_equiv (rtx reg, const_rtx store ATTRIBUTE_UNUSED, |
3265 | void *data ATTRIBUTE_UNUSED) | |
2af2dbdc VM |
3266 | { |
3267 | int regno; | |
fb0ab697 | 3268 | rtx_insn_list *list; |
2af2dbdc VM |
3269 | |
3270 | if (!REG_P (reg)) | |
3271 | return; | |
3272 | regno = REGNO (reg); | |
5ffa4e6a | 3273 | reg_equiv[regno].no_equiv = 1; |
2af2dbdc | 3274 | list = reg_equiv[regno].init_insns; |
fb0ab697 | 3275 | if (list && list->insn () == NULL) |
2af2dbdc | 3276 | return; |
fb0ab697 | 3277 | reg_equiv[regno].init_insns = gen_rtx_INSN_LIST (VOIDmode, NULL_RTX, NULL); |
2af2dbdc VM |
3278 | reg_equiv[regno].replacement = NULL_RTX; |
3279 | /* This doesn't matter for equivalences made for argument registers, we | |
3280 | should keep their initialization insns. */ | |
3281 | if (reg_equiv[regno].is_arg_equivalence) | |
3282 | return; | |
55a2c322 | 3283 | ira_reg_equiv[regno].defined_p = false; |
0cc97fc5 | 3284 | ira_reg_equiv[regno].init_insns = NULL; |
fb0ab697 | 3285 | for (; list; list = list->next ()) |
2af2dbdc | 3286 | { |
fb0ab697 | 3287 | rtx_insn *insn = list->insn (); |
2af2dbdc VM |
3288 | remove_note (insn, find_reg_note (insn, REG_EQUIV, NULL_RTX)); |
3289 | } | |
3290 | } | |
3291 | ||
e3f9e0ac WM |
3292 | /* Check whether the SUBREG is a paradoxical subreg and set the result |
3293 | in PDX_SUBREGS. */ | |
3294 | ||
40954ce5 | 3295 | static void |
8c1d8b59 | 3296 | set_paradoxical_subreg (rtx_insn *insn) |
e3f9e0ac | 3297 | { |
40954ce5 RS |
3298 | subrtx_iterator::array_type array; |
3299 | FOR_EACH_SUBRTX (iter, array, PATTERN (insn), NONCONST) | |
3300 | { | |
3301 | const_rtx subreg = *iter; | |
3302 | if (GET_CODE (subreg) == SUBREG) | |
3303 | { | |
3304 | const_rtx reg = SUBREG_REG (subreg); | |
3305 | if (REG_P (reg) && paradoxical_subreg_p (subreg)) | |
8c1d8b59 | 3306 | reg_equiv[REGNO (reg)].pdx_subregs = true; |
40954ce5 RS |
3307 | } |
3308 | } | |
e3f9e0ac WM |
3309 | } |
3310 | ||
3a6191b1 JJ |
3311 | /* In DEBUG_INSN location adjust REGs from CLEARED_REGS bitmap to the |
3312 | equivalent replacement. */ | |
3313 | ||
3314 | static rtx | |
3315 | adjust_cleared_regs (rtx loc, const_rtx old_rtx ATTRIBUTE_UNUSED, void *data) | |
3316 | { | |
3317 | if (REG_P (loc)) | |
3318 | { | |
3319 | bitmap cleared_regs = (bitmap) data; | |
3320 | if (bitmap_bit_p (cleared_regs, REGNO (loc))) | |
b8f045e2 | 3321 | return simplify_replace_fn_rtx (copy_rtx (*reg_equiv[REGNO (loc)].src_p), |
3a6191b1 JJ |
3322 | NULL_RTX, adjust_cleared_regs, data); |
3323 | } | |
3324 | return NULL_RTX; | |
3325 | } | |
3326 | ||
a72b242e AM |
3327 | /* Given register REGNO is set only once, return true if the defining |
3328 | insn dominates all uses. */ | |
3329 | ||
3330 | static bool | |
3331 | def_dominates_uses (int regno) | |
3332 | { | |
3333 | df_ref def = DF_REG_DEF_CHAIN (regno); | |
3334 | ||
3335 | struct df_insn_info *def_info = DF_REF_INSN_INFO (def); | |
3336 | /* If this is an artificial def (eh handler regs, hard frame pointer | |
3337 | for non-local goto, regs defined on function entry) then def_info | |
3338 | is NULL and the reg is always live before any use. We might | |
3339 | reasonably return true in that case, but since the only call | |
3340 | of this function is currently here in ira.c when we are looking | |
3341 | at a defining insn we can't have an artificial def as that would | |
3342 | bump DF_REG_DEF_COUNT. */ | |
3343 | gcc_assert (DF_REG_DEF_COUNT (regno) == 1 && def_info != NULL); | |
3344 | ||
3345 | rtx_insn *def_insn = DF_REF_INSN (def); | |
3346 | basic_block def_bb = BLOCK_FOR_INSN (def_insn); | |
3347 | ||
3348 | for (df_ref use = DF_REG_USE_CHAIN (regno); | |
3349 | use; | |
3350 | use = DF_REF_NEXT_REG (use)) | |
3351 | { | |
3352 | struct df_insn_info *use_info = DF_REF_INSN_INFO (use); | |
3353 | /* Only check real uses, not artificial ones. */ | |
3354 | if (use_info) | |
3355 | { | |
3356 | rtx_insn *use_insn = DF_REF_INSN (use); | |
3357 | if (!DEBUG_INSN_P (use_insn)) | |
3358 | { | |
3359 | basic_block use_bb = BLOCK_FOR_INSN (use_insn); | |
3360 | if (use_bb != def_bb | |
3361 | ? !dominated_by_p (CDI_DOMINATORS, use_bb, def_bb) | |
3362 | : DF_INSN_INFO_LUID (use_info) < DF_INSN_INFO_LUID (def_info)) | |
3363 | return false; | |
3364 | } | |
3365 | } | |
3366 | } | |
3367 | return true; | |
3368 | } | |
3369 | ||
6d1e98df RS |
3370 | /* Scan the instructions before update_equiv_regs. Record which registers |
3371 | are referenced as paradoxical subregs. Also check for cases in which | |
3372 | the current function needs to save a register that one of its call | |
3373 | instructions clobbers. | |
3374 | ||
3375 | These things are logically unrelated, but it's more efficient to do | |
3376 | them together. */ | |
3377 | ||
3378 | static void | |
3379 | update_equiv_regs_prescan (void) | |
3380 | { | |
3381 | basic_block bb; | |
3382 | rtx_insn *insn; | |
3383 | function_abi_aggregator callee_abis; | |
3384 | ||
3385 | FOR_EACH_BB_FN (bb, cfun) | |
3386 | FOR_BB_INSNS (bb, insn) | |
3387 | if (NONDEBUG_INSN_P (insn)) | |
3388 | { | |
3389 | set_paradoxical_subreg (insn); | |
3390 | if (CALL_P (insn)) | |
3391 | callee_abis.note_callee_abi (insn_callee_abi (insn)); | |
3392 | } | |
3393 | ||
3394 | HARD_REG_SET extra_caller_saves = callee_abis.caller_save_regs (*crtl->abi); | |
3395 | if (!hard_reg_set_empty_p (extra_caller_saves)) | |
3396 | for (unsigned int regno = 0; regno < FIRST_PSEUDO_REGISTER; ++regno) | |
3397 | if (TEST_HARD_REG_BIT (extra_caller_saves, regno)) | |
3398 | df_set_regs_ever_live (regno, true); | |
3399 | } | |
3400 | ||
2af2dbdc | 3401 | /* Find registers that are equivalent to a single value throughout the |
1756cb66 VM |
3402 | compilation (either because they can be referenced in memory or are |
3403 | set once from a single constant). Lower their priority for a | |
3404 | register. | |
2af2dbdc | 3405 | |
1756cb66 VM |
3406 | If such a register is only referenced once, try substituting its |
3407 | value into the using insn. If it succeeds, we can eliminate the | |
3408 | register completely. | |
2af2dbdc | 3409 | |
ba52669f AM |
3410 | Initialize init_insns in ira_reg_equiv array. */ |
3411 | static void | |
2af2dbdc VM |
3412 | update_equiv_regs (void) |
3413 | { | |
b2908ba6 | 3414 | rtx_insn *insn; |
2af2dbdc | 3415 | basic_block bb; |
2af2dbdc VM |
3416 | |
3417 | /* Scan the insns and find which registers have equivalences. Do this | |
3418 | in a separate scan of the insns because (due to -fcse-follow-jumps) | |
3419 | a register can be set below its use. */ | |
91dabbb2 | 3420 | bitmap setjmp_crosses = regstat_get_setjmp_crosses (); |
11cd3bed | 3421 | FOR_EACH_BB_FN (bb, cfun) |
2af2dbdc | 3422 | { |
91dabbb2 | 3423 | int loop_depth = bb_loop_depth (bb); |
2af2dbdc VM |
3424 | |
3425 | for (insn = BB_HEAD (bb); | |
3426 | insn != NEXT_INSN (BB_END (bb)); | |
3427 | insn = NEXT_INSN (insn)) | |
3428 | { | |
3429 | rtx note; | |
3430 | rtx set; | |
3431 | rtx dest, src; | |
3432 | int regno; | |
3433 | ||
3434 | if (! INSN_P (insn)) | |
3435 | continue; | |
3436 | ||
3437 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
3438 | if (REG_NOTE_KIND (note) == REG_INC) | |
3439 | no_equiv (XEXP (note, 0), note, NULL); | |
3440 | ||
3441 | set = single_set (insn); | |
3442 | ||
3443 | /* If this insn contains more (or less) than a single SET, | |
3444 | only mark all destinations as having no known equivalence. */ | |
07b38331 BS |
3445 | if (set == NULL_RTX |
3446 | || side_effects_p (SET_SRC (set))) | |
2af2dbdc | 3447 | { |
e8448ba5 | 3448 | note_pattern_stores (PATTERN (insn), no_equiv, NULL); |
2af2dbdc VM |
3449 | continue; |
3450 | } | |
3451 | else if (GET_CODE (PATTERN (insn)) == PARALLEL) | |
3452 | { | |
3453 | int i; | |
3454 | ||
3455 | for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--) | |
3456 | { | |
3457 | rtx part = XVECEXP (PATTERN (insn), 0, i); | |
3458 | if (part != set) | |
e8448ba5 | 3459 | note_pattern_stores (part, no_equiv, NULL); |
2af2dbdc VM |
3460 | } |
3461 | } | |
3462 | ||
3463 | dest = SET_DEST (set); | |
3464 | src = SET_SRC (set); | |
3465 | ||
3466 | /* See if this is setting up the equivalence between an argument | |
3467 | register and its stack slot. */ | |
3468 | note = find_reg_note (insn, REG_EQUIV, NULL_RTX); | |
3469 | if (note) | |
3470 | { | |
3471 | gcc_assert (REG_P (dest)); | |
3472 | regno = REGNO (dest); | |
3473 | ||
55a2c322 VM |
3474 | /* Note that we don't want to clear init_insns in |
3475 | ira_reg_equiv even if there are multiple sets of this | |
3476 | register. */ | |
2af2dbdc VM |
3477 | reg_equiv[regno].is_arg_equivalence = 1; |
3478 | ||
5a107a0f VM |
3479 | /* The insn result can have equivalence memory although |
3480 | the equivalence is not set up by the insn. We add | |
3481 | this insn to init insns as it is a flag for now that | |
3482 | regno has an equivalence. We will remove the insn | |
3483 | from init insn list later. */ | |
3484 | if (rtx_equal_p (src, XEXP (note, 0)) || MEM_P (XEXP (note, 0))) | |
55a2c322 VM |
3485 | ira_reg_equiv[regno].init_insns |
3486 | = gen_rtx_INSN_LIST (VOIDmode, insn, | |
3487 | ira_reg_equiv[regno].init_insns); | |
2af2dbdc VM |
3488 | |
3489 | /* Continue normally in case this is a candidate for | |
3490 | replacements. */ | |
3491 | } | |
3492 | ||
3493 | if (!optimize) | |
3494 | continue; | |
3495 | ||
3496 | /* We only handle the case of a pseudo register being set | |
3497 | once, or always to the same value. */ | |
1fe28116 VM |
3498 | /* ??? The mn10200 port breaks if we add equivalences for |
3499 | values that need an ADDRESS_REGS register and set them equivalent | |
3500 | to a MEM of a pseudo. The actual problem is in the over-conservative | |
3501 | handling of INPADDR_ADDRESS / INPUT_ADDRESS / INPUT triples in | |
3502 | calculate_needs, but we traditionally work around this problem | |
3503 | here by rejecting equivalences when the destination is in a register | |
3504 | that's likely spilled. This is fragile, of course, since the | |
3505 | preferred class of a pseudo depends on all instructions that set | |
3506 | or use it. */ | |
3507 | ||
2af2dbdc VM |
3508 | if (!REG_P (dest) |
3509 | || (regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER | |
fb0ab697 JL |
3510 | || (reg_equiv[regno].init_insns |
3511 | && reg_equiv[regno].init_insns->insn () == NULL) | |
07b8f0a8 | 3512 | || (targetm.class_likely_spilled_p (reg_preferred_class (regno)) |
1fe28116 | 3513 | && MEM_P (src) && ! reg_equiv[regno].is_arg_equivalence)) |
2af2dbdc VM |
3514 | { |
3515 | /* This might be setting a SUBREG of a pseudo, a pseudo that is | |
3516 | also set somewhere else to a constant. */ | |
e8448ba5 | 3517 | note_pattern_stores (set, no_equiv, NULL); |
2af2dbdc VM |
3518 | continue; |
3519 | } | |
3520 | ||
8c1d8b59 AM |
3521 | /* Don't set reg mentioned in a paradoxical subreg |
3522 | equivalent to a mem. */ | |
3523 | if (MEM_P (src) && reg_equiv[regno].pdx_subregs) | |
e3f9e0ac | 3524 | { |
e8448ba5 | 3525 | note_pattern_stores (set, no_equiv, NULL); |
e3f9e0ac WM |
3526 | continue; |
3527 | } | |
3528 | ||
2af2dbdc VM |
3529 | note = find_reg_note (insn, REG_EQUAL, NULL_RTX); |
3530 | ||
3531 | /* cse sometimes generates function invariants, but doesn't put a | |
3532 | REG_EQUAL note on the insn. Since this note would be redundant, | |
3533 | there's no point creating it earlier than here. */ | |
3534 | if (! note && ! rtx_varies_p (src, 0)) | |
3535 | note = set_unique_reg_note (insn, REG_EQUAL, copy_rtx (src)); | |
3536 | ||
3537 | /* Don't bother considering a REG_EQUAL note containing an EXPR_LIST | |
2b9c63a2 | 3538 | since it represents a function call. */ |
2af2dbdc VM |
3539 | if (note && GET_CODE (XEXP (note, 0)) == EXPR_LIST) |
3540 | note = NULL_RTX; | |
3541 | ||
5ffa4e6a FY |
3542 | if (DF_REG_DEF_COUNT (regno) != 1) |
3543 | { | |
3544 | bool equal_p = true; | |
3545 | rtx_insn_list *list; | |
3546 | ||
3547 | /* If we have already processed this pseudo and determined it | |
67914693 | 3548 | cannot have an equivalence, then honor that decision. */ |
5ffa4e6a FY |
3549 | if (reg_equiv[regno].no_equiv) |
3550 | continue; | |
3551 | ||
3552 | if (! note | |
2af2dbdc VM |
3553 | || rtx_varies_p (XEXP (note, 0), 0) |
3554 | || (reg_equiv[regno].replacement | |
3555 | && ! rtx_equal_p (XEXP (note, 0), | |
5ffa4e6a FY |
3556 | reg_equiv[regno].replacement))) |
3557 | { | |
3558 | no_equiv (dest, set, NULL); | |
3559 | continue; | |
3560 | } | |
3561 | ||
3562 | list = reg_equiv[regno].init_insns; | |
3563 | for (; list; list = list->next ()) | |
3564 | { | |
3565 | rtx note_tmp; | |
3566 | rtx_insn *insn_tmp; | |
3567 | ||
3568 | insn_tmp = list->insn (); | |
3569 | note_tmp = find_reg_note (insn_tmp, REG_EQUAL, NULL_RTX); | |
3570 | gcc_assert (note_tmp); | |
3571 | if (! rtx_equal_p (XEXP (note, 0), XEXP (note_tmp, 0))) | |
3572 | { | |
3573 | equal_p = false; | |
3574 | break; | |
3575 | } | |
3576 | } | |
3577 | ||
3578 | if (! equal_p) | |
3579 | { | |
3580 | no_equiv (dest, set, NULL); | |
3581 | continue; | |
3582 | } | |
2af2dbdc | 3583 | } |
5ffa4e6a | 3584 | |
2af2dbdc VM |
3585 | /* Record this insn as initializing this register. */ |
3586 | reg_equiv[regno].init_insns | |
3587 | = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv[regno].init_insns); | |
3588 | ||
3589 | /* If this register is known to be equal to a constant, record that | |
a72b242e AM |
3590 | it is always equivalent to the constant. |
3591 | Note that it is possible to have a register use before | |
3592 | the def in loops (see gcc.c-torture/execute/pr79286.c) | |
3593 | where the reg is undefined on first use. If the def insn | |
3594 | won't trap we can use it as an equivalence, effectively | |
3595 | choosing the "undefined" value for the reg to be the | |
3596 | same as the value set by the def. */ | |
2af2dbdc | 3597 | if (DF_REG_DEF_COUNT (regno) == 1 |
a72b242e AM |
3598 | && note |
3599 | && !rtx_varies_p (XEXP (note, 0), 0) | |
08f42414 BE |
3600 | && (!may_trap_or_fault_p (XEXP (note, 0)) |
3601 | || def_dominates_uses (regno))) | |
2af2dbdc VM |
3602 | { |
3603 | rtx note_value = XEXP (note, 0); | |
3604 | remove_note (insn, note); | |
3605 | set_unique_reg_note (insn, REG_EQUIV, note_value); | |
3606 | } | |
3607 | ||
3608 | /* If this insn introduces a "constant" register, decrease the priority | |
3609 | of that register. Record this insn if the register is only used once | |
3610 | more and the equivalence value is the same as our source. | |
3611 | ||
3612 | The latter condition is checked for two reasons: First, it is an | |
3613 | indication that it may be more efficient to actually emit the insn | |
3614 | as written (if no registers are available, reload will substitute | |
3615 | the equivalence). Secondly, it avoids problems with any registers | |
3616 | dying in this insn whose death notes would be missed. | |
3617 | ||
3618 | If we don't have a REG_EQUIV note, see if this insn is loading | |
3619 | a register used only in one basic block from a MEM. If so, and the | |
3620 | MEM remains unchanged for the life of the register, add a REG_EQUIV | |
3621 | note. */ | |
2af2dbdc VM |
3622 | note = find_reg_note (insn, REG_EQUIV, NULL_RTX); |
3623 | ||
63ce14e0 | 3624 | rtx replacement = NULL_RTX; |
2af2dbdc | 3625 | if (note) |
63ce14e0 AM |
3626 | replacement = XEXP (note, 0); |
3627 | else if (REG_BASIC_BLOCK (regno) >= NUM_FIXED_BLOCKS | |
3628 | && MEM_P (SET_SRC (set))) | |
2af2dbdc | 3629 | { |
63ce14e0 AM |
3630 | enum valid_equiv validity; |
3631 | validity = validate_equiv_mem (insn, dest, SET_SRC (set)); | |
3632 | if (validity != valid_none) | |
3633 | { | |
3634 | replacement = copy_rtx (SET_SRC (set)); | |
3635 | if (validity == valid_reload) | |
3636 | note = set_unique_reg_note (insn, REG_EQUIV, replacement); | |
3637 | } | |
3638 | } | |
2af2dbdc | 3639 | |
63ce14e0 AM |
3640 | /* If we haven't done so, record for reload that this is an |
3641 | equivalencing insn. */ | |
3642 | if (note && !reg_equiv[regno].is_arg_equivalence) | |
3643 | ira_reg_equiv[regno].init_insns | |
3644 | = gen_rtx_INSN_LIST (VOIDmode, insn, | |
3645 | ira_reg_equiv[regno].init_insns); | |
2af2dbdc | 3646 | |
63ce14e0 AM |
3647 | if (replacement) |
3648 | { | |
3649 | reg_equiv[regno].replacement = replacement; | |
2af2dbdc | 3650 | reg_equiv[regno].src_p = &SET_SRC (set); |
5ffa4e6a | 3651 | reg_equiv[regno].loop_depth = (short) loop_depth; |
2af2dbdc VM |
3652 | |
3653 | /* Don't mess with things live during setjmp. */ | |
91dabbb2 | 3654 | if (optimize && !bitmap_bit_p (setjmp_crosses, regno)) |
2af2dbdc | 3655 | { |
2af2dbdc VM |
3656 | /* If the register is referenced exactly twice, meaning it is |
3657 | set once and used once, indicate that the reference may be | |
3658 | replaced by the equivalence we computed above. Do this | |
3659 | even if the register is only used in one block so that | |
3660 | dependencies can be handled where the last register is | |
3661 | used in a different block (i.e. HIGH / LO_SUM sequences) | |
3662 | and to reduce the number of registers alive across | |
3663 | calls. */ | |
3664 | ||
3665 | if (REG_N_REFS (regno) == 2 | |
63ce14e0 | 3666 | && (rtx_equal_p (replacement, src) |
2af2dbdc VM |
3667 | || ! equiv_init_varies_p (src)) |
3668 | && NONJUMP_INSN_P (insn) | |
3669 | && equiv_init_movable_p (PATTERN (insn), regno)) | |
3670 | reg_equiv[regno].replace = 1; | |
3671 | } | |
3672 | } | |
3673 | } | |
3674 | } | |
42ae0d7f | 3675 | } |
2af2dbdc | 3676 | |
42ae0d7f AM |
3677 | /* For insns that set a MEM to the contents of a REG that is only used |
3678 | in a single basic block, see if the register is always equivalent | |
3679 | to that memory location and if moving the store from INSN to the | |
3680 | insn that sets REG is safe. If so, put a REG_EQUIV note on the | |
3681 | initializing insn. */ | |
3682 | static void | |
3683 | add_store_equivs (void) | |
3684 | { | |
8f9b31f7 | 3685 | auto_bitmap seen_insns; |
2af2dbdc | 3686 | |
42ae0d7f | 3687 | for (rtx_insn *insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
2af2dbdc VM |
3688 | { |
3689 | rtx set, src, dest; | |
3690 | unsigned regno; | |
42ae0d7f | 3691 | rtx_insn *init_insn; |
2af2dbdc | 3692 | |
8f9b31f7 | 3693 | bitmap_set_bit (seen_insns, INSN_UID (insn)); |
14d7d4be | 3694 | |
2af2dbdc VM |
3695 | if (! INSN_P (insn)) |
3696 | continue; | |
3697 | ||
3698 | set = single_set (insn); | |
3699 | if (! set) | |
3700 | continue; | |
3701 | ||
3702 | dest = SET_DEST (set); | |
3703 | src = SET_SRC (set); | |
3704 | ||
42ae0d7f | 3705 | /* Don't add a REG_EQUIV note if the insn already has one. The existing |
10e04446 | 3706 | REG_EQUIV is likely more useful than the one we are adding. */ |
2af2dbdc VM |
3707 | if (MEM_P (dest) && REG_P (src) |
3708 | && (regno = REGNO (src)) >= FIRST_PSEUDO_REGISTER | |
3709 | && REG_BASIC_BLOCK (regno) >= NUM_FIXED_BLOCKS | |
3710 | && DF_REG_DEF_COUNT (regno) == 1 | |
8c1d8b59 | 3711 | && ! reg_equiv[regno].pdx_subregs |
fb0ab697 | 3712 | && reg_equiv[regno].init_insns != NULL |
42ae0d7f | 3713 | && (init_insn = reg_equiv[regno].init_insns->insn ()) != 0 |
8f9b31f7 | 3714 | && bitmap_bit_p (seen_insns, INSN_UID (init_insn)) |
42ae0d7f | 3715 | && ! find_reg_note (init_insn, REG_EQUIV, NULL_RTX) |
63ce14e0 | 3716 | && validate_equiv_mem (init_insn, src, dest) == valid_reload |
42ae0d7f AM |
3717 | && ! memref_used_between_p (dest, init_insn, insn) |
3718 | /* Attaching a REG_EQUIV note will fail if INIT_INSN has | |
3719 | multiple sets. */ | |
3720 | && set_unique_reg_note (init_insn, REG_EQUIV, copy_rtx (dest))) | |
2af2dbdc | 3721 | { |
42ae0d7f AM |
3722 | /* This insn makes the equivalence, not the one initializing |
3723 | the register. */ | |
3724 | ira_reg_equiv[regno].init_insns | |
3725 | = gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX); | |
3726 | df_notes_rescan (init_insn); | |
3727 | if (dump_file) | |
3728 | fprintf (dump_file, | |
3729 | "Adding REG_EQUIV to insn %d for source of insn %d\n", | |
3730 | INSN_UID (init_insn), | |
3731 | INSN_UID (insn)); | |
2af2dbdc VM |
3732 | } |
3733 | } | |
42ae0d7f AM |
3734 | } |
3735 | ||
3736 | /* Scan all regs killed in an insn to see if any of them are registers | |
3737 | only used that once. If so, see if we can replace the reference | |
3738 | with the equivalent form. If we can, delete the initializing | |
3739 | reference and this register will go away. If we can't replace the | |
3740 | reference, and the initializing reference is within the same loop | |
3741 | (or in an inner loop), then move the register initialization just | |
3742 | before the use, so that they are in the same basic block. */ | |
3743 | static void | |
3744 | combine_and_move_insns (void) | |
3745 | { | |
0e3de1d4 | 3746 | auto_bitmap cleared_regs; |
b00544fa | 3747 | int max = max_reg_num (); |
2af2dbdc | 3748 | |
b00544fa | 3749 | for (int regno = FIRST_PSEUDO_REGISTER; regno < max; regno++) |
2af2dbdc | 3750 | { |
b00544fa AM |
3751 | if (!reg_equiv[regno].replace) |
3752 | continue; | |
2af2dbdc | 3753 | |
b00544fa AM |
3754 | rtx_insn *use_insn = 0; |
3755 | for (df_ref use = DF_REG_USE_CHAIN (regno); | |
3756 | use; | |
3757 | use = DF_REF_NEXT_REG (use)) | |
3758 | if (DF_REF_INSN_INFO (use)) | |
3759 | { | |
3760 | if (DEBUG_INSN_P (DF_REF_INSN (use))) | |
3761 | continue; | |
3762 | gcc_assert (!use_insn); | |
3763 | use_insn = DF_REF_INSN (use); | |
3764 | } | |
3765 | gcc_assert (use_insn); | |
2af2dbdc | 3766 | |
b00544fa AM |
3767 | /* Don't substitute into jumps. indirect_jump_optimize does |
3768 | this for anything we are prepared to handle. */ | |
3769 | if (JUMP_P (use_insn)) | |
3770 | continue; | |
3771 | ||
17a938e8 SB |
3772 | /* Also don't substitute into a conditional trap insn -- it can become |
3773 | an unconditional trap, and that is a flow control insn. */ | |
3774 | if (GET_CODE (PATTERN (use_insn)) == TRAP_IF) | |
3775 | continue; | |
3776 | ||
b00544fa AM |
3777 | df_ref def = DF_REG_DEF_CHAIN (regno); |
3778 | gcc_assert (DF_REG_DEF_COUNT (regno) == 1 && DF_REF_INSN_INFO (def)); | |
3779 | rtx_insn *def_insn = DF_REF_INSN (def); | |
3780 | ||
3781 | /* We may not move instructions that can throw, since that | |
3782 | changes basic block boundaries and we are not prepared to | |
3783 | adjust the CFG to match. */ | |
3784 | if (can_throw_internal (def_insn)) | |
3785 | continue; | |
3786 | ||
3787 | basic_block use_bb = BLOCK_FOR_INSN (use_insn); | |
3788 | basic_block def_bb = BLOCK_FOR_INSN (def_insn); | |
3789 | if (bb_loop_depth (use_bb) > bb_loop_depth (def_bb)) | |
3790 | continue; | |
2af2dbdc | 3791 | |
b00544fa AM |
3792 | if (asm_noperands (PATTERN (def_insn)) < 0 |
3793 | && validate_replace_rtx (regno_reg_rtx[regno], | |
3794 | *reg_equiv[regno].src_p, use_insn)) | |
3795 | { | |
3796 | rtx link; | |
3797 | /* Append the REG_DEAD notes from def_insn. */ | |
3798 | for (rtx *p = ®_NOTES (def_insn); (link = *p) != 0; ) | |
2af2dbdc | 3799 | { |
b00544fa | 3800 | if (REG_NOTE_KIND (XEXP (link, 0)) == REG_DEAD) |
2af2dbdc | 3801 | { |
b00544fa AM |
3802 | *p = XEXP (link, 1); |
3803 | XEXP (link, 1) = REG_NOTES (use_insn); | |
3804 | REG_NOTES (use_insn) = link; | |
3805 | } | |
3806 | else | |
3807 | p = &XEXP (link, 1); | |
3808 | } | |
2af2dbdc | 3809 | |
b00544fa AM |
3810 | remove_death (regno, use_insn); |
3811 | SET_REG_N_REFS (regno, 0); | |
3812 | REG_FREQ (regno) = 0; | |
fba12165 BS |
3813 | df_ref use; |
3814 | FOR_EACH_INSN_USE (use, def_insn) | |
3815 | { | |
3816 | unsigned int use_regno = DF_REF_REGNO (use); | |
3817 | if (!HARD_REGISTER_NUM_P (use_regno)) | |
3818 | reg_equiv[use_regno].replace = 0; | |
3819 | } | |
3820 | ||
b00544fa | 3821 | delete_insn (def_insn); |
2af2dbdc | 3822 | |
b00544fa AM |
3823 | reg_equiv[regno].init_insns = NULL; |
3824 | ira_reg_equiv[regno].init_insns = NULL; | |
3825 | bitmap_set_bit (cleared_regs, regno); | |
3826 | } | |
2af2dbdc | 3827 | |
b00544fa AM |
3828 | /* Move the initialization of the register to just before |
3829 | USE_INSN. Update the flow information. */ | |
3830 | else if (prev_nondebug_insn (use_insn) != def_insn) | |
3831 | { | |
3832 | rtx_insn *new_insn; | |
2af2dbdc | 3833 | |
b00544fa AM |
3834 | new_insn = emit_insn_before (PATTERN (def_insn), use_insn); |
3835 | REG_NOTES (new_insn) = REG_NOTES (def_insn); | |
3836 | REG_NOTES (def_insn) = 0; | |
3837 | /* Rescan it to process the notes. */ | |
3838 | df_insn_rescan (new_insn); | |
2af2dbdc | 3839 | |
b00544fa AM |
3840 | /* Make sure this insn is recognized before reload begins, |
3841 | otherwise eliminate_regs_in_insn will die. */ | |
3842 | INSN_CODE (new_insn) = INSN_CODE (def_insn); | |
2af2dbdc | 3843 | |
b00544fa | 3844 | delete_insn (def_insn); |
2af2dbdc | 3845 | |
b00544fa | 3846 | XEXP (reg_equiv[regno].init_insns, 0) = new_insn; |
2af2dbdc | 3847 | |
b00544fa AM |
3848 | REG_BASIC_BLOCK (regno) = use_bb->index; |
3849 | REG_N_CALLS_CROSSED (regno) = 0; | |
2af2dbdc | 3850 | |
b00544fa AM |
3851 | if (use_insn == BB_HEAD (use_bb)) |
3852 | BB_HEAD (use_bb) = new_insn; | |
2af2dbdc | 3853 | |
fcc861d9 AM |
3854 | /* We know regno dies in use_insn, but inside a loop |
3855 | REG_DEAD notes might be missing when def_insn was in | |
3856 | another basic block. However, when we move def_insn into | |
3857 | this bb we'll definitely get a REG_DEAD note and reload | |
3858 | will see the death. It's possible that update_equiv_regs | |
3859 | set up an equivalence referencing regno for a reg set by | |
3860 | use_insn, when regno was seen as non-local. Now that | |
3861 | regno is local to this block, and dies, such an | |
3862 | equivalence is invalid. */ | |
8972f7e9 | 3863 | if (find_reg_note (use_insn, REG_EQUIV, regno_reg_rtx[regno])) |
fcc861d9 AM |
3864 | { |
3865 | rtx set = single_set (use_insn); | |
3866 | if (set && REG_P (SET_DEST (set))) | |
3867 | no_equiv (SET_DEST (set), set, NULL); | |
3868 | } | |
3869 | ||
b00544fa AM |
3870 | ira_reg_equiv[regno].init_insns |
3871 | = gen_rtx_INSN_LIST (VOIDmode, new_insn, NULL_RTX); | |
3872 | bitmap_set_bit (cleared_regs, regno); | |
2af2dbdc VM |
3873 | } |
3874 | } | |
3875 | ||
3876 | if (!bitmap_empty_p (cleared_regs)) | |
3a6191b1 | 3877 | { |
b00544fa AM |
3878 | basic_block bb; |
3879 | ||
11cd3bed | 3880 | FOR_EACH_BB_FN (bb, cfun) |
3a6191b1 | 3881 | { |
3a6191b1 JJ |
3882 | bitmap_and_compl_into (DF_LR_IN (bb), cleared_regs); |
3883 | bitmap_and_compl_into (DF_LR_OUT (bb), cleared_regs); | |
b00544fa | 3884 | if (!df_live) |
bf744527 SB |
3885 | continue; |
3886 | bitmap_and_compl_into (DF_LIVE_IN (bb), cleared_regs); | |
3887 | bitmap_and_compl_into (DF_LIVE_OUT (bb), cleared_regs); | |
3a6191b1 JJ |
3888 | } |
3889 | ||
3890 | /* Last pass - adjust debug insns referencing cleared regs. */ | |
36f52e8f | 3891 | if (MAY_HAVE_DEBUG_BIND_INSNS) |
b00544fa | 3892 | for (rtx_insn *insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
36f52e8f | 3893 | if (DEBUG_BIND_INSN_P (insn)) |
3a6191b1 JJ |
3894 | { |
3895 | rtx old_loc = INSN_VAR_LOCATION_LOC (insn); | |
3896 | INSN_VAR_LOCATION_LOC (insn) | |
3897 | = simplify_replace_fn_rtx (old_loc, NULL_RTX, | |
3898 | adjust_cleared_regs, | |
3899 | (void *) cleared_regs); | |
3900 | if (old_loc != INSN_VAR_LOCATION_LOC (insn)) | |
3901 | df_insn_rescan (insn); | |
3902 | } | |
3903 | } | |
2af2dbdc VM |
3904 | } |
3905 | ||
6585b2e2 AM |
3906 | /* A pass over indirect jumps, converting simple cases to direct jumps. |
3907 | Combine does this optimization too, but only within a basic block. */ | |
ba52669f AM |
3908 | static void |
3909 | indirect_jump_optimize (void) | |
3910 | { | |
3911 | basic_block bb; | |
3912 | bool rebuild_p = false; | |
3913 | ||
3914 | FOR_EACH_BB_REVERSE_FN (bb, cfun) | |
3915 | { | |
3916 | rtx_insn *insn = BB_END (bb); | |
97eb24c4 JJ |
3917 | if (!JUMP_P (insn) |
3918 | || find_reg_note (insn, REG_NON_LOCAL_GOTO, NULL_RTX)) | |
ba52669f AM |
3919 | continue; |
3920 | ||
3921 | rtx x = pc_set (insn); | |
3922 | if (!x || !REG_P (SET_SRC (x))) | |
3923 | continue; | |
3924 | ||
3925 | int regno = REGNO (SET_SRC (x)); | |
3926 | if (DF_REG_DEF_COUNT (regno) == 1) | |
3927 | { | |
6585b2e2 AM |
3928 | df_ref def = DF_REG_DEF_CHAIN (regno); |
3929 | if (!DF_REF_IS_ARTIFICIAL (def)) | |
ba52669f | 3930 | { |
6585b2e2 | 3931 | rtx_insn *def_insn = DF_REF_INSN (def); |
97eb24c4 JJ |
3932 | rtx lab = NULL_RTX; |
3933 | rtx set = single_set (def_insn); | |
3934 | if (set && GET_CODE (SET_SRC (set)) == LABEL_REF) | |
3935 | lab = SET_SRC (set); | |
3936 | else | |
6585b2e2 | 3937 | { |
97eb24c4 JJ |
3938 | rtx eqnote = find_reg_note (def_insn, REG_EQUAL, NULL_RTX); |
3939 | if (eqnote && GET_CODE (XEXP (eqnote, 0)) == LABEL_REF) | |
3940 | lab = XEXP (eqnote, 0); | |
6585b2e2 | 3941 | } |
97eb24c4 JJ |
3942 | if (lab && validate_replace_rtx (SET_SRC (x), lab, insn)) |
3943 | rebuild_p = true; | |
ba52669f AM |
3944 | } |
3945 | } | |
3946 | } | |
2af2dbdc | 3947 | |
ba52669f AM |
3948 | if (rebuild_p) |
3949 | { | |
3950 | timevar_push (TV_JUMP); | |
3951 | rebuild_jump_labels (get_insns ()); | |
3952 | if (purge_all_dead_edges ()) | |
3953 | delete_unreachable_blocks (); | |
3954 | timevar_pop (TV_JUMP); | |
3955 | } | |
3956 | } | |
3957 | \f | |
55a2c322 VM |
3958 | /* Set up fields memory, constant, and invariant from init_insns in |
3959 | the structures of array ira_reg_equiv. */ | |
3960 | static void | |
3961 | setup_reg_equiv (void) | |
3962 | { | |
3963 | int i; | |
0cc97fc5 DM |
3964 | rtx_insn_list *elem, *prev_elem, *next_elem; |
3965 | rtx_insn *insn; | |
3966 | rtx set, x; | |
55a2c322 VM |
3967 | |
3968 | for (i = FIRST_PSEUDO_REGISTER; i < ira_reg_equiv_len; i++) | |
5a107a0f VM |
3969 | for (prev_elem = NULL, elem = ira_reg_equiv[i].init_insns; |
3970 | elem; | |
3971 | prev_elem = elem, elem = next_elem) | |
55a2c322 | 3972 | { |
0cc97fc5 DM |
3973 | next_elem = elem->next (); |
3974 | insn = elem->insn (); | |
55a2c322 VM |
3975 | set = single_set (insn); |
3976 | ||
3977 | /* Init insns can set up equivalence when the reg is a destination or | |
3978 | a source (in this case the destination is memory). */ | |
3979 | if (set != 0 && (REG_P (SET_DEST (set)) || REG_P (SET_SRC (set)))) | |
3980 | { | |
3981 | if ((x = find_reg_note (insn, REG_EQUIV, NULL_RTX)) != NULL) | |
5a107a0f VM |
3982 | { |
3983 | x = XEXP (x, 0); | |
3984 | if (REG_P (SET_DEST (set)) | |
3985 | && REGNO (SET_DEST (set)) == (unsigned int) i | |
3986 | && ! rtx_equal_p (SET_SRC (set), x) && MEM_P (x)) | |
3987 | { | |
3988 | /* This insn reporting the equivalence but | |
3989 | actually not setting it. Remove it from the | |
3990 | list. */ | |
3991 | if (prev_elem == NULL) | |
3992 | ira_reg_equiv[i].init_insns = next_elem; | |
3993 | else | |
3994 | XEXP (prev_elem, 1) = next_elem; | |
3995 | elem = prev_elem; | |
3996 | } | |
3997 | } | |
55a2c322 VM |
3998 | else if (REG_P (SET_DEST (set)) |
3999 | && REGNO (SET_DEST (set)) == (unsigned int) i) | |
4000 | x = SET_SRC (set); | |
4001 | else | |
4002 | { | |
4003 | gcc_assert (REG_P (SET_SRC (set)) | |
4004 | && REGNO (SET_SRC (set)) == (unsigned int) i); | |
4005 | x = SET_DEST (set); | |
4006 | } | |
4007 | if (! function_invariant_p (x) | |
4008 | || ! flag_pic | |
4009 | /* A function invariant is often CONSTANT_P but may | |
4010 | include a register. We promise to only pass | |
4011 | CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */ | |
4012 | || (CONSTANT_P (x) && LEGITIMATE_PIC_OPERAND_P (x))) | |
4013 | { | |
4014 | /* It can happen that a REG_EQUIV note contains a MEM | |
4015 | that is not a legitimate memory operand. As later | |
4016 | stages of reload assume that all addresses found in | |
4017 | the lra_regno_equiv_* arrays were originally | |
4018 | legitimate, we ignore such REG_EQUIV notes. */ | |
4019 | if (memory_operand (x, VOIDmode)) | |
4020 | { | |
4021 | ira_reg_equiv[i].defined_p = true; | |
4022 | ira_reg_equiv[i].memory = x; | |
4023 | continue; | |
4024 | } | |
4025 | else if (function_invariant_p (x)) | |
4026 | { | |
ef4bddc2 | 4027 | machine_mode mode; |
55a2c322 VM |
4028 | |
4029 | mode = GET_MODE (SET_DEST (set)); | |
4030 | if (GET_CODE (x) == PLUS | |
4031 | || x == frame_pointer_rtx || x == arg_pointer_rtx) | |
4032 | /* This is PLUS of frame pointer and a constant, | |
4033 | or fp, or argp. */ | |
4034 | ira_reg_equiv[i].invariant = x; | |
4035 | else if (targetm.legitimate_constant_p (mode, x)) | |
4036 | ira_reg_equiv[i].constant = x; | |
4037 | else | |
4038 | { | |
4039 | ira_reg_equiv[i].memory = force_const_mem (mode, x); | |
4040 | if (ira_reg_equiv[i].memory == NULL_RTX) | |
4041 | { | |
4042 | ira_reg_equiv[i].defined_p = false; | |
0cc97fc5 | 4043 | ira_reg_equiv[i].init_insns = NULL; |
55a2c322 VM |
4044 | break; |
4045 | } | |
4046 | } | |
4047 | ira_reg_equiv[i].defined_p = true; | |
4048 | continue; | |
4049 | } | |
4050 | } | |
4051 | } | |
4052 | ira_reg_equiv[i].defined_p = false; | |
0cc97fc5 | 4053 | ira_reg_equiv[i].init_insns = NULL; |
55a2c322 VM |
4054 | break; |
4055 | } | |
4056 | } | |
4057 | ||
4058 | \f | |
4059 | ||
2af2dbdc VM |
4060 | /* Print chain C to FILE. */ |
4061 | static void | |
99b1c316 | 4062 | print_insn_chain (FILE *file, class insn_chain *c) |
2af2dbdc | 4063 | { |
c3284718 | 4064 | fprintf (file, "insn=%d, ", INSN_UID (c->insn)); |
2af2dbdc VM |
4065 | bitmap_print (file, &c->live_throughout, "live_throughout: ", ", "); |
4066 | bitmap_print (file, &c->dead_or_set, "dead_or_set: ", "\n"); | |
4067 | } | |
4068 | ||
4069 | ||
4070 | /* Print all reload_insn_chains to FILE. */ | |
4071 | static void | |
4072 | print_insn_chains (FILE *file) | |
4073 | { | |
99b1c316 | 4074 | class insn_chain *c; |
2af2dbdc VM |
4075 | for (c = reload_insn_chain; c ; c = c->next) |
4076 | print_insn_chain (file, c); | |
4077 | } | |
4078 | ||
4079 | /* Return true if pseudo REGNO should be added to set live_throughout | |
4080 | or dead_or_set of the insn chains for reload consideration. */ | |
4081 | static bool | |
4082 | pseudo_for_reload_consideration_p (int regno) | |
4083 | { | |
4084 | /* Consider spilled pseudos too for IRA because they still have a | |
4085 | chance to get hard-registers in the reload when IRA is used. */ | |
b100151b | 4086 | return (reg_renumber[regno] >= 0 || ira_conflicts_p); |
2af2dbdc VM |
4087 | } |
4088 | ||
9dcf1f86 RS |
4089 | /* Return true if we can track the individual bytes of subreg X. |
4090 | When returning true, set *OUTER_SIZE to the number of bytes in | |
4091 | X itself, *INNER_SIZE to the number of bytes in the inner register | |
4092 | and *START to the offset of the first byte. */ | |
4093 | static bool | |
4094 | get_subreg_tracking_sizes (rtx x, HOST_WIDE_INT *outer_size, | |
4095 | HOST_WIDE_INT *inner_size, HOST_WIDE_INT *start) | |
4096 | { | |
4097 | rtx reg = regno_reg_rtx[REGNO (SUBREG_REG (x))]; | |
cf098191 RS |
4098 | return (GET_MODE_SIZE (GET_MODE (x)).is_constant (outer_size) |
4099 | && GET_MODE_SIZE (GET_MODE (reg)).is_constant (inner_size) | |
4100 | && SUBREG_BYTE (x).is_constant (start)); | |
9dcf1f86 RS |
4101 | } |
4102 | ||
4103 | /* Init LIVE_SUBREGS[ALLOCNUM] and LIVE_SUBREGS_USED[ALLOCNUM] for | |
4104 | a register with SIZE bytes, making the register live if INIT_VALUE. */ | |
2af2dbdc VM |
4105 | static void |
4106 | init_live_subregs (bool init_value, sbitmap *live_subregs, | |
9dcf1f86 | 4107 | bitmap live_subregs_used, int allocnum, int size) |
2af2dbdc | 4108 | { |
2af2dbdc VM |
4109 | gcc_assert (size > 0); |
4110 | ||
4111 | /* Been there, done that. */ | |
cee784f5 | 4112 | if (bitmap_bit_p (live_subregs_used, allocnum)) |
2af2dbdc VM |
4113 | return; |
4114 | ||
cee784f5 | 4115 | /* Create a new one. */ |
2af2dbdc VM |
4116 | if (live_subregs[allocnum] == NULL) |
4117 | live_subregs[allocnum] = sbitmap_alloc (size); | |
4118 | ||
4119 | /* If the entire reg was live before blasting into subregs, we need | |
4120 | to init all of the subregs to ones else init to 0. */ | |
4121 | if (init_value) | |
f61e445a | 4122 | bitmap_ones (live_subregs[allocnum]); |
b8698a0f | 4123 | else |
f61e445a | 4124 | bitmap_clear (live_subregs[allocnum]); |
2af2dbdc | 4125 | |
cee784f5 | 4126 | bitmap_set_bit (live_subregs_used, allocnum); |
2af2dbdc VM |
4127 | } |
4128 | ||
4129 | /* Walk the insns of the current function and build reload_insn_chain, | |
4130 | and record register life information. */ | |
4131 | static void | |
4132 | build_insn_chain (void) | |
4133 | { | |
4134 | unsigned int i; | |
99b1c316 | 4135 | class insn_chain **p = &reload_insn_chain; |
2af2dbdc | 4136 | basic_block bb; |
99b1c316 MS |
4137 | class insn_chain *c = NULL; |
4138 | class insn_chain *next = NULL; | |
0e3de1d4 TS |
4139 | auto_bitmap live_relevant_regs; |
4140 | auto_bitmap elim_regset; | |
2af2dbdc VM |
4141 | /* live_subregs is a vector used to keep accurate information about |
4142 | which hardregs are live in multiword pseudos. live_subregs and | |
4143 | live_subregs_used are indexed by pseudo number. The live_subreg | |
4144 | entry for a particular pseudo is only used if the corresponding | |
cee784f5 SB |
4145 | element is non zero in live_subregs_used. The sbitmap size of |
4146 | live_subreg[allocno] is number of bytes that the pseudo can | |
2af2dbdc VM |
4147 | occupy. */ |
4148 | sbitmap *live_subregs = XCNEWVEC (sbitmap, max_regno); | |
0e3de1d4 | 4149 | auto_bitmap live_subregs_used; |
2af2dbdc VM |
4150 | |
4151 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
4152 | if (TEST_HARD_REG_BIT (eliminable_regset, i)) | |
4153 | bitmap_set_bit (elim_regset, i); | |
4f42035e | 4154 | FOR_EACH_BB_REVERSE_FN (bb, cfun) |
2af2dbdc VM |
4155 | { |
4156 | bitmap_iterator bi; | |
070a1983 | 4157 | rtx_insn *insn; |
b8698a0f | 4158 | |
2af2dbdc | 4159 | CLEAR_REG_SET (live_relevant_regs); |
cee784f5 | 4160 | bitmap_clear (live_subregs_used); |
b8698a0f | 4161 | |
bf744527 | 4162 | EXECUTE_IF_SET_IN_BITMAP (df_get_live_out (bb), 0, i, bi) |
2af2dbdc VM |
4163 | { |
4164 | if (i >= FIRST_PSEUDO_REGISTER) | |
4165 | break; | |
4166 | bitmap_set_bit (live_relevant_regs, i); | |
4167 | } | |
4168 | ||
bf744527 | 4169 | EXECUTE_IF_SET_IN_BITMAP (df_get_live_out (bb), |
2af2dbdc VM |
4170 | FIRST_PSEUDO_REGISTER, i, bi) |
4171 | { | |
4172 | if (pseudo_for_reload_consideration_p (i)) | |
4173 | bitmap_set_bit (live_relevant_regs, i); | |
4174 | } | |
4175 | ||
4176 | FOR_BB_INSNS_REVERSE (bb, insn) | |
4177 | { | |
4178 | if (!NOTE_P (insn) && !BARRIER_P (insn)) | |
4179 | { | |
bfac633a RS |
4180 | struct df_insn_info *insn_info = DF_INSN_INFO_GET (insn); |
4181 | df_ref def, use; | |
2af2dbdc VM |
4182 | |
4183 | c = new_insn_chain (); | |
4184 | c->next = next; | |
4185 | next = c; | |
4186 | *p = c; | |
4187 | p = &c->prev; | |
b8698a0f | 4188 | |
2af2dbdc VM |
4189 | c->insn = insn; |
4190 | c->block = bb->index; | |
4191 | ||
4b71920a | 4192 | if (NONDEBUG_INSN_P (insn)) |
bfac633a | 4193 | FOR_EACH_INSN_INFO_DEF (def, insn_info) |
2af2dbdc | 4194 | { |
2af2dbdc | 4195 | unsigned int regno = DF_REF_REGNO (def); |
b8698a0f | 4196 | |
2af2dbdc VM |
4197 | /* Ignore may clobbers because these are generated |
4198 | from calls. However, every other kind of def is | |
4199 | added to dead_or_set. */ | |
4200 | if (!DF_REF_FLAGS_IS_SET (def, DF_REF_MAY_CLOBBER)) | |
4201 | { | |
4202 | if (regno < FIRST_PSEUDO_REGISTER) | |
4203 | { | |
4204 | if (!fixed_regs[regno]) | |
4205 | bitmap_set_bit (&c->dead_or_set, regno); | |
4206 | } | |
4207 | else if (pseudo_for_reload_consideration_p (regno)) | |
4208 | bitmap_set_bit (&c->dead_or_set, regno); | |
4209 | } | |
4210 | ||
4211 | if ((regno < FIRST_PSEUDO_REGISTER | |
4212 | || reg_renumber[regno] >= 0 | |
4213 | || ira_conflicts_p) | |
4214 | && (!DF_REF_FLAGS_IS_SET (def, DF_REF_CONDITIONAL))) | |
4215 | { | |
4216 | rtx reg = DF_REF_REG (def); | |
9dcf1f86 RS |
4217 | HOST_WIDE_INT outer_size, inner_size, start; |
4218 | ||
4219 | /* We can usually track the liveness of individual | |
4220 | bytes within a subreg. The only exceptions are | |
4221 | subregs wrapped in ZERO_EXTRACTs and subregs whose | |
4222 | size is not known; in those cases we need to be | |
4223 | conservative and treat the definition as a partial | |
4224 | definition of the full register rather than a full | |
4225 | definition of a specific part of the register. */ | |
2af2dbdc | 4226 | if (GET_CODE (reg) == SUBREG |
9dcf1f86 RS |
4227 | && !DF_REF_FLAGS_IS_SET (def, DF_REF_ZERO_EXTRACT) |
4228 | && get_subreg_tracking_sizes (reg, &outer_size, | |
4229 | &inner_size, &start)) | |
2af2dbdc | 4230 | { |
9dcf1f86 | 4231 | HOST_WIDE_INT last = start + outer_size; |
2af2dbdc VM |
4232 | |
4233 | init_live_subregs | |
b8698a0f | 4234 | (bitmap_bit_p (live_relevant_regs, regno), |
9dcf1f86 RS |
4235 | live_subregs, live_subregs_used, regno, |
4236 | inner_size); | |
2af2dbdc VM |
4237 | |
4238 | if (!DF_REF_FLAGS_IS_SET | |
4239 | (def, DF_REF_STRICT_LOW_PART)) | |
4240 | { | |
4241 | /* Expand the range to cover entire words. | |
4242 | Bytes added here are "don't care". */ | |
4243 | start | |
4244 | = start / UNITS_PER_WORD * UNITS_PER_WORD; | |
4245 | last = ((last + UNITS_PER_WORD - 1) | |
4246 | / UNITS_PER_WORD * UNITS_PER_WORD); | |
4247 | } | |
4248 | ||
4249 | /* Ignore the paradoxical bits. */ | |
cee784f5 SB |
4250 | if (last > SBITMAP_SIZE (live_subregs[regno])) |
4251 | last = SBITMAP_SIZE (live_subregs[regno]); | |
2af2dbdc VM |
4252 | |
4253 | while (start < last) | |
4254 | { | |
d7c028c0 | 4255 | bitmap_clear_bit (live_subregs[regno], start); |
2af2dbdc VM |
4256 | start++; |
4257 | } | |
b8698a0f | 4258 | |
f61e445a | 4259 | if (bitmap_empty_p (live_subregs[regno])) |
2af2dbdc | 4260 | { |
cee784f5 | 4261 | bitmap_clear_bit (live_subregs_used, regno); |
2af2dbdc VM |
4262 | bitmap_clear_bit (live_relevant_regs, regno); |
4263 | } | |
4264 | else | |
4265 | /* Set live_relevant_regs here because | |
4266 | that bit has to be true to get us to | |
4267 | look at the live_subregs fields. */ | |
4268 | bitmap_set_bit (live_relevant_regs, regno); | |
4269 | } | |
4270 | else | |
4271 | { | |
4272 | /* DF_REF_PARTIAL is generated for | |
4273 | subregs, STRICT_LOW_PART, and | |
4274 | ZERO_EXTRACT. We handle the subreg | |
4275 | case above so here we have to keep from | |
4276 | modeling the def as a killing def. */ | |
4277 | if (!DF_REF_FLAGS_IS_SET (def, DF_REF_PARTIAL)) | |
4278 | { | |
cee784f5 | 4279 | bitmap_clear_bit (live_subregs_used, regno); |
2af2dbdc | 4280 | bitmap_clear_bit (live_relevant_regs, regno); |
2af2dbdc VM |
4281 | } |
4282 | } | |
4283 | } | |
4284 | } | |
b8698a0f | 4285 | |
2af2dbdc VM |
4286 | bitmap_and_compl_into (live_relevant_regs, elim_regset); |
4287 | bitmap_copy (&c->live_throughout, live_relevant_regs); | |
4288 | ||
4b71920a | 4289 | if (NONDEBUG_INSN_P (insn)) |
bfac633a | 4290 | FOR_EACH_INSN_INFO_USE (use, insn_info) |
2af2dbdc | 4291 | { |
2af2dbdc VM |
4292 | unsigned int regno = DF_REF_REGNO (use); |
4293 | rtx reg = DF_REF_REG (use); | |
b8698a0f | 4294 | |
2af2dbdc VM |
4295 | /* DF_REF_READ_WRITE on a use means that this use |
4296 | is fabricated from a def that is a partial set | |
4297 | to a multiword reg. Here, we only model the | |
4298 | subreg case that is not wrapped in ZERO_EXTRACT | |
4299 | precisely so we do not need to look at the | |
2b9c63a2 | 4300 | fabricated use. */ |
b8698a0f L |
4301 | if (DF_REF_FLAGS_IS_SET (use, DF_REF_READ_WRITE) |
4302 | && !DF_REF_FLAGS_IS_SET (use, DF_REF_ZERO_EXTRACT) | |
2af2dbdc VM |
4303 | && DF_REF_FLAGS_IS_SET (use, DF_REF_SUBREG)) |
4304 | continue; | |
b8698a0f | 4305 | |
2af2dbdc VM |
4306 | /* Add the last use of each var to dead_or_set. */ |
4307 | if (!bitmap_bit_p (live_relevant_regs, regno)) | |
4308 | { | |
4309 | if (regno < FIRST_PSEUDO_REGISTER) | |
4310 | { | |
4311 | if (!fixed_regs[regno]) | |
4312 | bitmap_set_bit (&c->dead_or_set, regno); | |
4313 | } | |
4314 | else if (pseudo_for_reload_consideration_p (regno)) | |
4315 | bitmap_set_bit (&c->dead_or_set, regno); | |
4316 | } | |
b8698a0f | 4317 | |
2af2dbdc VM |
4318 | if (regno < FIRST_PSEUDO_REGISTER |
4319 | || pseudo_for_reload_consideration_p (regno)) | |
4320 | { | |
9dcf1f86 | 4321 | HOST_WIDE_INT outer_size, inner_size, start; |
2af2dbdc VM |
4322 | if (GET_CODE (reg) == SUBREG |
4323 | && !DF_REF_FLAGS_IS_SET (use, | |
4324 | DF_REF_SIGN_EXTRACT | |
9dcf1f86 RS |
4325 | | DF_REF_ZERO_EXTRACT) |
4326 | && get_subreg_tracking_sizes (reg, &outer_size, | |
4327 | &inner_size, &start)) | |
2af2dbdc | 4328 | { |
9dcf1f86 | 4329 | HOST_WIDE_INT last = start + outer_size; |
b8698a0f | 4330 | |
2af2dbdc | 4331 | init_live_subregs |
b8698a0f | 4332 | (bitmap_bit_p (live_relevant_regs, regno), |
9dcf1f86 RS |
4333 | live_subregs, live_subregs_used, regno, |
4334 | inner_size); | |
b8698a0f | 4335 | |
2af2dbdc | 4336 | /* Ignore the paradoxical bits. */ |
cee784f5 SB |
4337 | if (last > SBITMAP_SIZE (live_subregs[regno])) |
4338 | last = SBITMAP_SIZE (live_subregs[regno]); | |
2af2dbdc VM |
4339 | |
4340 | while (start < last) | |
4341 | { | |
d7c028c0 | 4342 | bitmap_set_bit (live_subregs[regno], start); |
2af2dbdc VM |
4343 | start++; |
4344 | } | |
4345 | } | |
4346 | else | |
4347 | /* Resetting the live_subregs_used is | |
4348 | effectively saying do not use the subregs | |
4349 | because we are reading the whole | |
4350 | pseudo. */ | |
cee784f5 | 4351 | bitmap_clear_bit (live_subregs_used, regno); |
2af2dbdc VM |
4352 | bitmap_set_bit (live_relevant_regs, regno); |
4353 | } | |
4354 | } | |
4355 | } | |
4356 | } | |
4357 | ||
4358 | /* FIXME!! The following code is a disaster. Reload needs to see the | |
4359 | labels and jump tables that are just hanging out in between | |
4360 | the basic blocks. See pr33676. */ | |
4361 | insn = BB_HEAD (bb); | |
b8698a0f | 4362 | |
2af2dbdc | 4363 | /* Skip over the barriers and cruft. */ |
b8698a0f | 4364 | while (insn && (BARRIER_P (insn) || NOTE_P (insn) |
2af2dbdc VM |
4365 | || BLOCK_FOR_INSN (insn) == bb)) |
4366 | insn = PREV_INSN (insn); | |
b8698a0f | 4367 | |
2af2dbdc VM |
4368 | /* While we add anything except barriers and notes, the focus is |
4369 | to get the labels and jump tables into the | |
4370 | reload_insn_chain. */ | |
4371 | while (insn) | |
4372 | { | |
4373 | if (!NOTE_P (insn) && !BARRIER_P (insn)) | |
4374 | { | |
4375 | if (BLOCK_FOR_INSN (insn)) | |
4376 | break; | |
b8698a0f | 4377 | |
2af2dbdc VM |
4378 | c = new_insn_chain (); |
4379 | c->next = next; | |
4380 | next = c; | |
4381 | *p = c; | |
4382 | p = &c->prev; | |
b8698a0f | 4383 | |
2af2dbdc VM |
4384 | /* The block makes no sense here, but it is what the old |
4385 | code did. */ | |
4386 | c->block = bb->index; | |
4387 | c->insn = insn; | |
4388 | bitmap_copy (&c->live_throughout, live_relevant_regs); | |
b8698a0f | 4389 | } |
2af2dbdc VM |
4390 | insn = PREV_INSN (insn); |
4391 | } | |
4392 | } | |
4393 | ||
2af2dbdc VM |
4394 | reload_insn_chain = c; |
4395 | *p = NULL; | |
4396 | ||
cee784f5 SB |
4397 | for (i = 0; i < (unsigned int) max_regno; i++) |
4398 | if (live_subregs[i] != NULL) | |
4399 | sbitmap_free (live_subregs[i]); | |
2af2dbdc | 4400 | free (live_subregs); |
2af2dbdc VM |
4401 | |
4402 | if (dump_file) | |
4403 | print_insn_chains (dump_file); | |
4404 | } | |
acf41a74 BS |
4405 | \f |
4406 | /* Examine the rtx found in *LOC, which is read or written to as determined | |
4407 | by TYPE. Return false if we find a reason why an insn containing this | |
4408 | rtx should not be moved (such as accesses to non-constant memory), true | |
4409 | otherwise. */ | |
4410 | static bool | |
4411 | rtx_moveable_p (rtx *loc, enum op_type type) | |
4412 | { | |
4413 | const char *fmt; | |
4414 | rtx x = *loc; | |
acf41a74 BS |
4415 | int i, j; |
4416 | ||
45309d28 | 4417 | enum rtx_code code = GET_CODE (x); |
acf41a74 BS |
4418 | switch (code) |
4419 | { | |
4420 | case CONST: | |
d8116890 | 4421 | CASE_CONST_ANY: |
acf41a74 BS |
4422 | case SYMBOL_REF: |
4423 | case LABEL_REF: | |
4424 | return true; | |
4425 | ||
4426 | case PC: | |
4427 | return type == OP_IN; | |
4428 | ||
4429 | case CC0: | |
4430 | return false; | |
4431 | ||
4432 | case REG: | |
4433 | if (x == frame_pointer_rtx) | |
4434 | return true; | |
4435 | if (HARD_REGISTER_P (x)) | |
4436 | return false; | |
4437 | ||
4438 | return true; | |
4439 | ||
4440 | case MEM: | |
4441 | if (type == OP_IN && MEM_READONLY_P (x)) | |
4442 | return rtx_moveable_p (&XEXP (x, 0), OP_IN); | |
4443 | return false; | |
4444 | ||
4445 | case SET: | |
4446 | return (rtx_moveable_p (&SET_SRC (x), OP_IN) | |
4447 | && rtx_moveable_p (&SET_DEST (x), OP_OUT)); | |
4448 | ||
4449 | case STRICT_LOW_PART: | |
4450 | return rtx_moveable_p (&XEXP (x, 0), OP_OUT); | |
4451 | ||
4452 | case ZERO_EXTRACT: | |
4453 | case SIGN_EXTRACT: | |
4454 | return (rtx_moveable_p (&XEXP (x, 0), type) | |
4455 | && rtx_moveable_p (&XEXP (x, 1), OP_IN) | |
4456 | && rtx_moveable_p (&XEXP (x, 2), OP_IN)); | |
4457 | ||
4458 | case CLOBBER: | |
4459 | return rtx_moveable_p (&SET_DEST (x), OP_OUT); | |
4460 | ||
d8c16744 | 4461 | case UNSPEC_VOLATILE: |
026c3cfd | 4462 | /* It is a bad idea to consider insns with such rtl |
d8c16744 VM |
4463 | as moveable ones. The insn scheduler also considers them as barrier |
4464 | for a reason. */ | |
4465 | return false; | |
4466 | ||
9d0d0a5a SB |
4467 | case ASM_OPERANDS: |
4468 | /* The same is true for volatile asm: it has unknown side effects, it | |
4469 | cannot be moved at will. */ | |
4470 | if (MEM_VOLATILE_P (x)) | |
4471 | return false; | |
4472 | ||
acf41a74 BS |
4473 | default: |
4474 | break; | |
4475 | } | |
4476 | ||
4477 | fmt = GET_RTX_FORMAT (code); | |
4478 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
4479 | { | |
4480 | if (fmt[i] == 'e') | |
4481 | { | |
4482 | if (!rtx_moveable_p (&XEXP (x, i), type)) | |
4483 | return false; | |
4484 | } | |
4485 | else if (fmt[i] == 'E') | |
4486 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
4487 | { | |
4488 | if (!rtx_moveable_p (&XVECEXP (x, i, j), type)) | |
4489 | return false; | |
4490 | } | |
4491 | } | |
4492 | return true; | |
4493 | } | |
4494 | ||
4495 | /* A wrapper around dominated_by_p, which uses the information in UID_LUID | |
4496 | to give dominance relationships between two insns I1 and I2. */ | |
4497 | static bool | |
4498 | insn_dominated_by_p (rtx i1, rtx i2, int *uid_luid) | |
4499 | { | |
4500 | basic_block bb1 = BLOCK_FOR_INSN (i1); | |
4501 | basic_block bb2 = BLOCK_FOR_INSN (i2); | |
4502 | ||
4503 | if (bb1 == bb2) | |
4504 | return uid_luid[INSN_UID (i2)] < uid_luid[INSN_UID (i1)]; | |
4505 | return dominated_by_p (CDI_DOMINATORS, bb1, bb2); | |
4506 | } | |
4507 | ||
4508 | /* Record the range of register numbers added by find_moveable_pseudos. */ | |
4509 | int first_moveable_pseudo, last_moveable_pseudo; | |
4510 | ||
4511 | /* These two vectors hold data for every register added by | |
4512 | find_movable_pseudos, with index 0 holding data for the | |
4513 | first_moveable_pseudo. */ | |
4514 | /* The original home register. */ | |
9771b263 | 4515 | static vec<rtx> pseudo_replaced_reg; |
acf41a74 BS |
4516 | |
4517 | /* Look for instances where we have an instruction that is known to increase | |
4518 | register pressure, and whose result is not used immediately. If it is | |
4519 | possible to move the instruction downwards to just before its first use, | |
4520 | split its lifetime into two ranges. We create a new pseudo to compute the | |
4521 | value, and emit a move instruction just before the first use. If, after | |
4522 | register allocation, the new pseudo remains unallocated, the function | |
4523 | move_unallocated_pseudos then deletes the move instruction and places | |
4524 | the computation just before the first use. | |
4525 | ||
4526 | Such a move is safe and profitable if all the input registers remain live | |
4527 | and unchanged between the original computation and its first use. In such | |
4528 | a situation, the computation is known to increase register pressure, and | |
4529 | moving it is known to at least not worsen it. | |
4530 | ||
4531 | We restrict moves to only those cases where a register remains unallocated, | |
4532 | in order to avoid interfering too much with the instruction schedule. As | |
4533 | an exception, we may move insns which only modify their input register | |
4534 | (typically induction variables), as this increases the freedom for our | |
4535 | intended transformation, and does not limit the second instruction | |
4536 | scheduler pass. */ | |
4537 | ||
4538 | static void | |
4539 | find_moveable_pseudos (void) | |
4540 | { | |
4541 | unsigned i; | |
4542 | int max_regs = max_reg_num (); | |
4543 | int max_uid = get_max_uid (); | |
4544 | basic_block bb; | |
4545 | int *uid_luid = XNEWVEC (int, max_uid); | |
070a1983 | 4546 | rtx_insn **closest_uses = XNEWVEC (rtx_insn *, max_regs); |
acf41a74 | 4547 | /* A set of registers which are live but not modified throughout a block. */ |
8b1c6fd7 DM |
4548 | bitmap_head *bb_transp_live = XNEWVEC (bitmap_head, |
4549 | last_basic_block_for_fn (cfun)); | |
acf41a74 | 4550 | /* A set of registers which only exist in a given basic block. */ |
8b1c6fd7 DM |
4551 | bitmap_head *bb_local = XNEWVEC (bitmap_head, |
4552 | last_basic_block_for_fn (cfun)); | |
acf41a74 BS |
4553 | /* A set of registers which are set once, in an instruction that can be |
4554 | moved freely downwards, but are otherwise transparent to a block. */ | |
8b1c6fd7 DM |
4555 | bitmap_head *bb_moveable_reg_sets = XNEWVEC (bitmap_head, |
4556 | last_basic_block_for_fn (cfun)); | |
8f9b31f7 | 4557 | auto_bitmap live, used, set, interesting, unusable_as_input; |
acf41a74 | 4558 | bitmap_iterator bi; |
acf41a74 BS |
4559 | |
4560 | first_moveable_pseudo = max_regs; | |
9771b263 DN |
4561 | pseudo_replaced_reg.release (); |
4562 | pseudo_replaced_reg.safe_grow_cleared (max_regs); | |
acf41a74 | 4563 | |
2d73cc45 MJ |
4564 | df_analyze (); |
4565 | calculate_dominance_info (CDI_DOMINATORS); | |
4566 | ||
acf41a74 | 4567 | i = 0; |
11cd3bed | 4568 | FOR_EACH_BB_FN (bb, cfun) |
acf41a74 | 4569 | { |
070a1983 | 4570 | rtx_insn *insn; |
acf41a74 BS |
4571 | bitmap transp = bb_transp_live + bb->index; |
4572 | bitmap moveable = bb_moveable_reg_sets + bb->index; | |
4573 | bitmap local = bb_local + bb->index; | |
4574 | ||
4575 | bitmap_initialize (local, 0); | |
4576 | bitmap_initialize (transp, 0); | |
4577 | bitmap_initialize (moveable, 0); | |
8f9b31f7 TS |
4578 | bitmap_copy (live, df_get_live_out (bb)); |
4579 | bitmap_and_into (live, df_get_live_in (bb)); | |
4580 | bitmap_copy (transp, live); | |
acf41a74 | 4581 | bitmap_clear (moveable); |
8f9b31f7 TS |
4582 | bitmap_clear (live); |
4583 | bitmap_clear (used); | |
4584 | bitmap_clear (set); | |
acf41a74 BS |
4585 | FOR_BB_INSNS (bb, insn) |
4586 | if (NONDEBUG_INSN_P (insn)) | |
4587 | { | |
bfac633a | 4588 | df_insn_info *insn_info = DF_INSN_INFO_GET (insn); |
bfac633a | 4589 | df_ref def, use; |
acf41a74 BS |
4590 | |
4591 | uid_luid[INSN_UID (insn)] = i++; | |
4592 | ||
74e59b6c RS |
4593 | def = df_single_def (insn_info); |
4594 | use = df_single_use (insn_info); | |
4595 | if (use | |
4596 | && def | |
4597 | && DF_REF_REGNO (use) == DF_REF_REGNO (def) | |
8f9b31f7 | 4598 | && !bitmap_bit_p (set, DF_REF_REGNO (use)) |
acf41a74 BS |
4599 | && rtx_moveable_p (&PATTERN (insn), OP_IN)) |
4600 | { | |
74e59b6c | 4601 | unsigned regno = DF_REF_REGNO (use); |
acf41a74 | 4602 | bitmap_set_bit (moveable, regno); |
8f9b31f7 TS |
4603 | bitmap_set_bit (set, regno); |
4604 | bitmap_set_bit (used, regno); | |
acf41a74 BS |
4605 | bitmap_clear_bit (transp, regno); |
4606 | continue; | |
4607 | } | |
bfac633a | 4608 | FOR_EACH_INSN_INFO_USE (use, insn_info) |
acf41a74 | 4609 | { |
bfac633a | 4610 | unsigned regno = DF_REF_REGNO (use); |
8f9b31f7 | 4611 | bitmap_set_bit (used, regno); |
acf41a74 BS |
4612 | if (bitmap_clear_bit (moveable, regno)) |
4613 | bitmap_clear_bit (transp, regno); | |
acf41a74 BS |
4614 | } |
4615 | ||
bfac633a | 4616 | FOR_EACH_INSN_INFO_DEF (def, insn_info) |
acf41a74 | 4617 | { |
bfac633a | 4618 | unsigned regno = DF_REF_REGNO (def); |
8f9b31f7 | 4619 | bitmap_set_bit (set, regno); |
acf41a74 BS |
4620 | bitmap_clear_bit (transp, regno); |
4621 | bitmap_clear_bit (moveable, regno); | |
acf41a74 BS |
4622 | } |
4623 | } | |
4624 | } | |
4625 | ||
11cd3bed | 4626 | FOR_EACH_BB_FN (bb, cfun) |
acf41a74 BS |
4627 | { |
4628 | bitmap local = bb_local + bb->index; | |
070a1983 | 4629 | rtx_insn *insn; |
acf41a74 BS |
4630 | |
4631 | FOR_BB_INSNS (bb, insn) | |
4632 | if (NONDEBUG_INSN_P (insn)) | |
4633 | { | |
74e59b6c | 4634 | df_insn_info *insn_info = DF_INSN_INFO_GET (insn); |
070a1983 DM |
4635 | rtx_insn *def_insn; |
4636 | rtx closest_use, note; | |
74e59b6c | 4637 | df_ref def, use; |
acf41a74 BS |
4638 | unsigned regno; |
4639 | bool all_dominated, all_local; | |
ef4bddc2 | 4640 | machine_mode mode; |
acf41a74 | 4641 | |
74e59b6c | 4642 | def = df_single_def (insn_info); |
acf41a74 | 4643 | /* There must be exactly one def in this insn. */ |
74e59b6c | 4644 | if (!def || !single_set (insn)) |
acf41a74 BS |
4645 | continue; |
4646 | /* This must be the only definition of the reg. We also limit | |
4647 | which modes we deal with so that we can assume we can generate | |
4648 | move instructions. */ | |
4649 | regno = DF_REF_REGNO (def); | |
4650 | mode = GET_MODE (DF_REF_REG (def)); | |
4651 | if (DF_REG_DEF_COUNT (regno) != 1 | |
4652 | || !DF_REF_INSN_INFO (def) | |
4653 | || HARD_REGISTER_NUM_P (regno) | |
aa44c80c | 4654 | || DF_REG_EQ_USE_COUNT (regno) > 0 |
acf41a74 BS |
4655 | || (!INTEGRAL_MODE_P (mode) && !FLOAT_MODE_P (mode))) |
4656 | continue; | |
4657 | def_insn = DF_REF_INSN (def); | |
4658 | ||
4659 | for (note = REG_NOTES (def_insn); note; note = XEXP (note, 1)) | |
4660 | if (REG_NOTE_KIND (note) == REG_EQUIV && MEM_P (XEXP (note, 0))) | |
4661 | break; | |
4662 | ||
4663 | if (note) | |
4664 | { | |
4665 | if (dump_file) | |
4666 | fprintf (dump_file, "Ignoring reg %d, has equiv memory\n", | |
4667 | regno); | |
8f9b31f7 | 4668 | bitmap_set_bit (unusable_as_input, regno); |
acf41a74 BS |
4669 | continue; |
4670 | } | |
4671 | ||
4672 | use = DF_REG_USE_CHAIN (regno); | |
4673 | all_dominated = true; | |
4674 | all_local = true; | |
4675 | closest_use = NULL_RTX; | |
4676 | for (; use; use = DF_REF_NEXT_REG (use)) | |
4677 | { | |
070a1983 | 4678 | rtx_insn *insn; |
acf41a74 BS |
4679 | if (!DF_REF_INSN_INFO (use)) |
4680 | { | |
4681 | all_dominated = false; | |
4682 | all_local = false; | |
4683 | break; | |
4684 | } | |
4685 | insn = DF_REF_INSN (use); | |
4686 | if (DEBUG_INSN_P (insn)) | |
4687 | continue; | |
4688 | if (BLOCK_FOR_INSN (insn) != BLOCK_FOR_INSN (def_insn)) | |
4689 | all_local = false; | |
4690 | if (!insn_dominated_by_p (insn, def_insn, uid_luid)) | |
4691 | all_dominated = false; | |
4692 | if (closest_use != insn && closest_use != const0_rtx) | |
4693 | { | |
4694 | if (closest_use == NULL_RTX) | |
4695 | closest_use = insn; | |
4696 | else if (insn_dominated_by_p (closest_use, insn, uid_luid)) | |
4697 | closest_use = insn; | |
4698 | else if (!insn_dominated_by_p (insn, closest_use, uid_luid)) | |
4699 | closest_use = const0_rtx; | |
4700 | } | |
4701 | } | |
4702 | if (!all_dominated) | |
4703 | { | |
4704 | if (dump_file) | |
4705 | fprintf (dump_file, "Reg %d not all uses dominated by set\n", | |
4706 | regno); | |
4707 | continue; | |
4708 | } | |
4709 | if (all_local) | |
4710 | bitmap_set_bit (local, regno); | |
4711 | if (closest_use == const0_rtx || closest_use == NULL | |
4712 | || next_nonnote_nondebug_insn (def_insn) == closest_use) | |
4713 | { | |
4714 | if (dump_file) | |
4715 | fprintf (dump_file, "Reg %d uninteresting%s\n", regno, | |
4716 | closest_use == const0_rtx || closest_use == NULL | |
4717 | ? " (no unique first use)" : ""); | |
4718 | continue; | |
4719 | } | |
058eb3b0 | 4720 | if (HAVE_cc0 && reg_referenced_p (cc0_rtx, PATTERN (closest_use))) |
acf41a74 BS |
4721 | { |
4722 | if (dump_file) | |
4723 | fprintf (dump_file, "Reg %d: closest user uses cc0\n", | |
4724 | regno); | |
4725 | continue; | |
4726 | } | |
058eb3b0 | 4727 | |
8f9b31f7 | 4728 | bitmap_set_bit (interesting, regno); |
070a1983 DM |
4729 | /* If we get here, we know closest_use is a non-NULL insn |
4730 | (as opposed to const_0_rtx). */ | |
4731 | closest_uses[regno] = as_a <rtx_insn *> (closest_use); | |
acf41a74 BS |
4732 | |
4733 | if (dump_file && (all_local || all_dominated)) | |
4734 | { | |
4735 | fprintf (dump_file, "Reg %u:", regno); | |
4736 | if (all_local) | |
4737 | fprintf (dump_file, " local to bb %d", bb->index); | |
4738 | if (all_dominated) | |
4739 | fprintf (dump_file, " def dominates all uses"); | |
4740 | if (closest_use != const0_rtx) | |
4741 | fprintf (dump_file, " has unique first use"); | |
4742 | fputs ("\n", dump_file); | |
4743 | } | |
4744 | } | |
4745 | } | |
4746 | ||
8f9b31f7 | 4747 | EXECUTE_IF_SET_IN_BITMAP (interesting, 0, i, bi) |
acf41a74 BS |
4748 | { |
4749 | df_ref def = DF_REG_DEF_CHAIN (i); | |
070a1983 | 4750 | rtx_insn *def_insn = DF_REF_INSN (def); |
acf41a74 BS |
4751 | basic_block def_block = BLOCK_FOR_INSN (def_insn); |
4752 | bitmap def_bb_local = bb_local + def_block->index; | |
4753 | bitmap def_bb_moveable = bb_moveable_reg_sets + def_block->index; | |
4754 | bitmap def_bb_transp = bb_transp_live + def_block->index; | |
4755 | bool local_to_bb_p = bitmap_bit_p (def_bb_local, i); | |
070a1983 | 4756 | rtx_insn *use_insn = closest_uses[i]; |
bfac633a | 4757 | df_ref use; |
acf41a74 BS |
4758 | bool all_ok = true; |
4759 | bool all_transp = true; | |
4760 | ||
4761 | if (!REG_P (DF_REF_REG (def))) | |
4762 | continue; | |
4763 | ||
4764 | if (!local_to_bb_p) | |
4765 | { | |
4766 | if (dump_file) | |
4767 | fprintf (dump_file, "Reg %u not local to one basic block\n", | |
4768 | i); | |
4769 | continue; | |
4770 | } | |
4771 | if (reg_equiv_init (i) != NULL_RTX) | |
4772 | { | |
4773 | if (dump_file) | |
4774 | fprintf (dump_file, "Ignoring reg %u with equiv init insn\n", | |
4775 | i); | |
4776 | continue; | |
4777 | } | |
4778 | if (!rtx_moveable_p (&PATTERN (def_insn), OP_IN)) | |
4779 | { | |
4780 | if (dump_file) | |
4781 | fprintf (dump_file, "Found def insn %d for %d to be not moveable\n", | |
4782 | INSN_UID (def_insn), i); | |
4783 | continue; | |
4784 | } | |
4785 | if (dump_file) | |
4786 | fprintf (dump_file, "Examining insn %d, def for %d\n", | |
4787 | INSN_UID (def_insn), i); | |
bfac633a | 4788 | FOR_EACH_INSN_USE (use, def_insn) |
acf41a74 | 4789 | { |
acf41a74 | 4790 | unsigned regno = DF_REF_REGNO (use); |
8f9b31f7 | 4791 | if (bitmap_bit_p (unusable_as_input, regno)) |
acf41a74 BS |
4792 | { |
4793 | all_ok = false; | |
4794 | if (dump_file) | |
4795 | fprintf (dump_file, " found unusable input reg %u.\n", regno); | |
4796 | break; | |
4797 | } | |
4798 | if (!bitmap_bit_p (def_bb_transp, regno)) | |
4799 | { | |
4800 | if (bitmap_bit_p (def_bb_moveable, regno) | |
4801 | && !control_flow_insn_p (use_insn) | |
618f4073 | 4802 | && (!HAVE_cc0 || !sets_cc0_p (use_insn))) |
acf41a74 BS |
4803 | { |
4804 | if (modified_between_p (DF_REF_REG (use), def_insn, use_insn)) | |
4805 | { | |
070a1983 | 4806 | rtx_insn *x = NEXT_INSN (def_insn); |
acf41a74 BS |
4807 | while (!modified_in_p (DF_REF_REG (use), x)) |
4808 | { | |
4809 | gcc_assert (x != use_insn); | |
4810 | x = NEXT_INSN (x); | |
4811 | } | |
4812 | if (dump_file) | |
4813 | fprintf (dump_file, " input reg %u modified but insn %d moveable\n", | |
4814 | regno, INSN_UID (x)); | |
4815 | emit_insn_after (PATTERN (x), use_insn); | |
4816 | set_insn_deleted (x); | |
4817 | } | |
4818 | else | |
4819 | { | |
4820 | if (dump_file) | |
4821 | fprintf (dump_file, " input reg %u modified between def and use\n", | |
4822 | regno); | |
4823 | all_transp = false; | |
4824 | } | |
4825 | } | |
4826 | else | |
4827 | all_transp = false; | |
4828 | } | |
acf41a74 BS |
4829 | } |
4830 | if (!all_ok) | |
4831 | continue; | |
4832 | if (!dbg_cnt (ira_move)) | |
4833 | break; | |
4834 | if (dump_file) | |
4835 | fprintf (dump_file, " all ok%s\n", all_transp ? " and transp" : ""); | |
4836 | ||
4837 | if (all_transp) | |
4838 | { | |
4839 | rtx def_reg = DF_REF_REG (def); | |
4840 | rtx newreg = ira_create_new_reg (def_reg); | |
9e3de74c | 4841 | if (validate_change (def_insn, DF_REF_REAL_LOC (def), newreg, 0)) |
acf41a74 BS |
4842 | { |
4843 | unsigned nregno = REGNO (newreg); | |
a36b2706 | 4844 | emit_insn_before (gen_move_insn (def_reg, newreg), use_insn); |
acf41a74 | 4845 | nregno -= max_regs; |
9771b263 | 4846 | pseudo_replaced_reg[nregno] = def_reg; |
acf41a74 BS |
4847 | } |
4848 | } | |
4849 | } | |
4850 | ||
11cd3bed | 4851 | FOR_EACH_BB_FN (bb, cfun) |
acf41a74 BS |
4852 | { |
4853 | bitmap_clear (bb_local + bb->index); | |
4854 | bitmap_clear (bb_transp_live + bb->index); | |
4855 | bitmap_clear (bb_moveable_reg_sets + bb->index); | |
4856 | } | |
acf41a74 BS |
4857 | free (uid_luid); |
4858 | free (closest_uses); | |
4859 | free (bb_local); | |
4860 | free (bb_transp_live); | |
4861 | free (bb_moveable_reg_sets); | |
4862 | ||
4863 | last_moveable_pseudo = max_reg_num (); | |
2d73cc45 MJ |
4864 | |
4865 | fix_reg_equiv_init (); | |
4866 | expand_reg_info (); | |
4867 | regstat_free_n_sets_and_refs (); | |
4868 | regstat_free_ri (); | |
4869 | regstat_init_n_sets_and_refs (); | |
4870 | regstat_compute_ri (); | |
4871 | free_dominance_info (CDI_DOMINATORS); | |
732dad8f | 4872 | } |
acf41a74 | 4873 | |
3e749749 MJ |
4874 | /* If SET pattern SET is an assignment from a hard register to a pseudo which |
4875 | is live at CALL_DOM (if non-NULL, otherwise this check is omitted), return | |
4876 | the destination. Otherwise return NULL. */ | |
732dad8f MJ |
4877 | |
4878 | static rtx | |
3e749749 | 4879 | interesting_dest_for_shprep_1 (rtx set, basic_block call_dom) |
732dad8f | 4880 | { |
732dad8f MJ |
4881 | rtx src = SET_SRC (set); |
4882 | rtx dest = SET_DEST (set); | |
4883 | if (!REG_P (src) || !HARD_REGISTER_P (src) | |
4884 | || !REG_P (dest) || HARD_REGISTER_P (dest) | |
4885 | || (call_dom && !bitmap_bit_p (df_get_live_in (call_dom), REGNO (dest)))) | |
4886 | return NULL; | |
4887 | return dest; | |
4888 | } | |
4889 | ||
df3e3493 | 4890 | /* If insn is interesting for parameter range-splitting shrink-wrapping |
3e749749 MJ |
4891 | preparation, i.e. it is a single set from a hard register to a pseudo, which |
4892 | is live at CALL_DOM (if non-NULL, otherwise this check is omitted), or a | |
4893 | parallel statement with only one such statement, return the destination. | |
4894 | Otherwise return NULL. */ | |
4895 | ||
4896 | static rtx | |
070a1983 | 4897 | interesting_dest_for_shprep (rtx_insn *insn, basic_block call_dom) |
3e749749 MJ |
4898 | { |
4899 | if (!INSN_P (insn)) | |
4900 | return NULL; | |
4901 | rtx pat = PATTERN (insn); | |
4902 | if (GET_CODE (pat) == SET) | |
4903 | return interesting_dest_for_shprep_1 (pat, call_dom); | |
4904 | ||
4905 | if (GET_CODE (pat) != PARALLEL) | |
4906 | return NULL; | |
4907 | rtx ret = NULL; | |
4908 | for (int i = 0; i < XVECLEN (pat, 0); i++) | |
4909 | { | |
4910 | rtx sub = XVECEXP (pat, 0, i); | |
17d184e5 | 4911 | if (GET_CODE (sub) == USE || GET_CODE (sub) == CLOBBER) |
3e749749 MJ |
4912 | continue; |
4913 | if (GET_CODE (sub) != SET | |
4914 | || side_effects_p (sub)) | |
4915 | return NULL; | |
4916 | rtx dest = interesting_dest_for_shprep_1 (sub, call_dom); | |
4917 | if (dest && ret) | |
4918 | return NULL; | |
4919 | if (dest) | |
4920 | ret = dest; | |
4921 | } | |
4922 | return ret; | |
4923 | } | |
4924 | ||
732dad8f MJ |
4925 | /* Split live ranges of pseudos that are loaded from hard registers in the |
4926 | first BB in a BB that dominates all non-sibling call if such a BB can be | |
4927 | found and is not in a loop. Return true if the function has made any | |
4928 | changes. */ | |
4929 | ||
4930 | static bool | |
4931 | split_live_ranges_for_shrink_wrap (void) | |
4932 | { | |
4933 | basic_block bb, call_dom = NULL; | |
fefa31b5 | 4934 | basic_block first = single_succ (ENTRY_BLOCK_PTR_FOR_FN (cfun)); |
070a1983 | 4935 | rtx_insn *insn, *last_interesting_insn = NULL; |
8f9b31f7 | 4936 | auto_bitmap need_new, reachable; |
732dad8f MJ |
4937 | vec<basic_block> queue; |
4938 | ||
a5e022d5 | 4939 | if (!SHRINK_WRAPPING_ENABLED) |
732dad8f MJ |
4940 | return false; |
4941 | ||
0cae8d31 | 4942 | queue.create (n_basic_blocks_for_fn (cfun)); |
732dad8f | 4943 | |
11cd3bed | 4944 | FOR_EACH_BB_FN (bb, cfun) |
732dad8f MJ |
4945 | FOR_BB_INSNS (bb, insn) |
4946 | if (CALL_P (insn) && !SIBLING_CALL_P (insn)) | |
4947 | { | |
4948 | if (bb == first) | |
4949 | { | |
732dad8f MJ |
4950 | queue.release (); |
4951 | return false; | |
4952 | } | |
4953 | ||
8f9b31f7 TS |
4954 | bitmap_set_bit (need_new, bb->index); |
4955 | bitmap_set_bit (reachable, bb->index); | |
732dad8f MJ |
4956 | queue.quick_push (bb); |
4957 | break; | |
4958 | } | |
4959 | ||
4960 | if (queue.is_empty ()) | |
4961 | { | |
732dad8f MJ |
4962 | queue.release (); |
4963 | return false; | |
4964 | } | |
4965 | ||
4966 | while (!queue.is_empty ()) | |
4967 | { | |
4968 | edge e; | |
4969 | edge_iterator ei; | |
4970 | ||
4971 | bb = queue.pop (); | |
4972 | FOR_EACH_EDGE (e, ei, bb->succs) | |
fefa31b5 | 4973 | if (e->dest != EXIT_BLOCK_PTR_FOR_FN (cfun) |
8f9b31f7 | 4974 | && bitmap_set_bit (reachable, e->dest->index)) |
732dad8f MJ |
4975 | queue.quick_push (e->dest); |
4976 | } | |
4977 | queue.release (); | |
4978 | ||
4979 | FOR_BB_INSNS (first, insn) | |
4980 | { | |
4981 | rtx dest = interesting_dest_for_shprep (insn, NULL); | |
4982 | if (!dest) | |
4983 | continue; | |
4984 | ||
4985 | if (DF_REG_DEF_COUNT (REGNO (dest)) > 1) | |
8f9b31f7 | 4986 | return false; |
732dad8f MJ |
4987 | |
4988 | for (df_ref use = DF_REG_USE_CHAIN (REGNO(dest)); | |
4989 | use; | |
4990 | use = DF_REF_NEXT_REG (use)) | |
4991 | { | |
732dad8f | 4992 | int ubbi = DF_REF_BB (use)->index; |
8f9b31f7 TS |
4993 | if (bitmap_bit_p (reachable, ubbi)) |
4994 | bitmap_set_bit (need_new, ubbi); | |
732dad8f MJ |
4995 | } |
4996 | last_interesting_insn = insn; | |
4997 | } | |
4998 | ||
732dad8f | 4999 | if (!last_interesting_insn) |
8f9b31f7 | 5000 | return false; |
732dad8f | 5001 | |
8f9b31f7 | 5002 | call_dom = nearest_common_dominator_for_set (CDI_DOMINATORS, need_new); |
732dad8f MJ |
5003 | if (call_dom == first) |
5004 | return false; | |
5005 | ||
5006 | loop_optimizer_init (AVOID_CFG_MODIFICATIONS); | |
5007 | while (bb_loop_depth (call_dom) > 0) | |
5008 | call_dom = get_immediate_dominator (CDI_DOMINATORS, call_dom); | |
5009 | loop_optimizer_finalize (); | |
5010 | ||
5011 | if (call_dom == first) | |
5012 | return false; | |
5013 | ||
5014 | calculate_dominance_info (CDI_POST_DOMINATORS); | |
5015 | if (dominated_by_p (CDI_POST_DOMINATORS, first, call_dom)) | |
5016 | { | |
5017 | free_dominance_info (CDI_POST_DOMINATORS); | |
5018 | return false; | |
5019 | } | |
5020 | free_dominance_info (CDI_POST_DOMINATORS); | |
5021 | ||
5022 | if (dump_file) | |
5023 | fprintf (dump_file, "Will split live ranges of parameters at BB %i\n", | |
5024 | call_dom->index); | |
5025 | ||
5026 | bool ret = false; | |
5027 | FOR_BB_INSNS (first, insn) | |
5028 | { | |
5029 | rtx dest = interesting_dest_for_shprep (insn, call_dom); | |
bcb21886 | 5030 | if (!dest || dest == pic_offset_table_rtx) |
732dad8f MJ |
5031 | continue; |
5032 | ||
fd1ca3fe | 5033 | bool need_newreg = false; |
732dad8f | 5034 | df_ref use, next; |
9e3de74c | 5035 | for (use = DF_REG_USE_CHAIN (REGNO (dest)); use; use = next) |
732dad8f | 5036 | { |
070a1983 | 5037 | rtx_insn *uin = DF_REF_INSN (use); |
732dad8f MJ |
5038 | next = DF_REF_NEXT_REG (use); |
5039 | ||
fd1ca3fe SB |
5040 | if (DEBUG_INSN_P (uin)) |
5041 | continue; | |
5042 | ||
732dad8f MJ |
5043 | basic_block ubb = BLOCK_FOR_INSN (uin); |
5044 | if (ubb == call_dom | |
5045 | || dominated_by_p (CDI_DOMINATORS, ubb, call_dom)) | |
5046 | { | |
fd1ca3fe SB |
5047 | need_newreg = true; |
5048 | break; | |
732dad8f MJ |
5049 | } |
5050 | } | |
5051 | ||
fd1ca3fe | 5052 | if (need_newreg) |
732dad8f | 5053 | { |
fd1ca3fe SB |
5054 | rtx newreg = ira_create_new_reg (dest); |
5055 | ||
5056 | for (use = DF_REG_USE_CHAIN (REGNO (dest)); use; use = next) | |
5057 | { | |
5058 | rtx_insn *uin = DF_REF_INSN (use); | |
5059 | next = DF_REF_NEXT_REG (use); | |
5060 | ||
5061 | basic_block ubb = BLOCK_FOR_INSN (uin); | |
5062 | if (ubb == call_dom | |
5063 | || dominated_by_p (CDI_DOMINATORS, ubb, call_dom)) | |
5064 | validate_change (uin, DF_REF_REAL_LOC (use), newreg, true); | |
5065 | } | |
5066 | ||
1476d1bd | 5067 | rtx_insn *new_move = gen_move_insn (newreg, dest); |
732dad8f MJ |
5068 | emit_insn_after (new_move, bb_note (call_dom)); |
5069 | if (dump_file) | |
5070 | { | |
5071 | fprintf (dump_file, "Split live-range of register "); | |
5072 | print_rtl_single (dump_file, dest); | |
5073 | } | |
5074 | ret = true; | |
5075 | } | |
5076 | ||
5077 | if (insn == last_interesting_insn) | |
5078 | break; | |
5079 | } | |
5080 | apply_change_group (); | |
5081 | return ret; | |
acf41a74 | 5082 | } |
8ff49c29 | 5083 | |
acf41a74 BS |
5084 | /* Perform the second half of the transformation started in |
5085 | find_moveable_pseudos. We look for instances where the newly introduced | |
5086 | pseudo remains unallocated, and remove it by moving the definition to | |
5087 | just before its use, replacing the move instruction generated by | |
5088 | find_moveable_pseudos. */ | |
5089 | static void | |
5090 | move_unallocated_pseudos (void) | |
5091 | { | |
5092 | int i; | |
5093 | for (i = first_moveable_pseudo; i < last_moveable_pseudo; i++) | |
5094 | if (reg_renumber[i] < 0) | |
5095 | { | |
acf41a74 | 5096 | int idx = i - first_moveable_pseudo; |
9771b263 | 5097 | rtx other_reg = pseudo_replaced_reg[idx]; |
070a1983 | 5098 | rtx_insn *def_insn = DF_REF_INSN (DF_REG_DEF_CHAIN (i)); |
a36b2706 RS |
5099 | /* The use must follow all definitions of OTHER_REG, so we can |
5100 | insert the new definition immediately after any of them. */ | |
5101 | df_ref other_def = DF_REG_DEF_CHAIN (REGNO (other_reg)); | |
070a1983 DM |
5102 | rtx_insn *move_insn = DF_REF_INSN (other_def); |
5103 | rtx_insn *newinsn = emit_insn_after (PATTERN (def_insn), move_insn); | |
a36b2706 | 5104 | rtx set; |
acf41a74 BS |
5105 | int success; |
5106 | ||
5107 | if (dump_file) | |
5108 | fprintf (dump_file, "moving def of %d (insn %d now) ", | |
5109 | REGNO (other_reg), INSN_UID (def_insn)); | |
5110 | ||
a36b2706 RS |
5111 | delete_insn (move_insn); |
5112 | while ((other_def = DF_REG_DEF_CHAIN (REGNO (other_reg)))) | |
5113 | delete_insn (DF_REF_INSN (other_def)); | |
5114 | delete_insn (def_insn); | |
5115 | ||
acf41a74 BS |
5116 | set = single_set (newinsn); |
5117 | success = validate_change (newinsn, &SET_DEST (set), other_reg, 0); | |
5118 | gcc_assert (success); | |
5119 | if (dump_file) | |
5120 | fprintf (dump_file, " %d) rather than keep unallocated replacement %d\n", | |
5121 | INSN_UID (newinsn), i); | |
acf41a74 BS |
5122 | SET_REG_N_REFS (i, 0); |
5123 | } | |
5124 | } | |
f2034d06 | 5125 | \f |
6399c0ab SB |
5126 | /* If the backend knows where to allocate pseudos for hard |
5127 | register initial values, register these allocations now. */ | |
a932fb89 | 5128 | static void |
6399c0ab SB |
5129 | allocate_initial_values (void) |
5130 | { | |
5131 | if (targetm.allocate_initial_value) | |
5132 | { | |
5133 | rtx hreg, preg, x; | |
5134 | int i, regno; | |
5135 | ||
5136 | for (i = 0; HARD_REGISTER_NUM_P (i); i++) | |
5137 | { | |
5138 | if (! initial_value_entry (i, &hreg, &preg)) | |
5139 | break; | |
5140 | ||
5141 | x = targetm.allocate_initial_value (hreg); | |
5142 | regno = REGNO (preg); | |
5143 | if (x && REG_N_SETS (regno) <= 1) | |
5144 | { | |
5145 | if (MEM_P (x)) | |
5146 | reg_equiv_memory_loc (regno) = x; | |
5147 | else | |
5148 | { | |
5149 | basic_block bb; | |
5150 | int new_regno; | |
5151 | ||
5152 | gcc_assert (REG_P (x)); | |
5153 | new_regno = REGNO (x); | |
5154 | reg_renumber[regno] = new_regno; | |
5155 | /* Poke the regno right into regno_reg_rtx so that even | |
5156 | fixed regs are accepted. */ | |
5157 | SET_REGNO (preg, new_regno); | |
5158 | /* Update global register liveness information. */ | |
11cd3bed | 5159 | FOR_EACH_BB_FN (bb, cfun) |
6399c0ab | 5160 | { |
c3284718 | 5161 | if (REGNO_REG_SET_P (df_get_live_in (bb), regno)) |
6399c0ab | 5162 | SET_REGNO_REG_SET (df_get_live_in (bb), new_regno); |
c3284718 | 5163 | if (REGNO_REG_SET_P (df_get_live_out (bb), regno)) |
6399c0ab SB |
5164 | SET_REGNO_REG_SET (df_get_live_out (bb), new_regno); |
5165 | } | |
5166 | } | |
5167 | } | |
5168 | } | |
2af2dbdc | 5169 | |
6399c0ab SB |
5170 | gcc_checking_assert (! initial_value_entry (FIRST_PSEUDO_REGISTER, |
5171 | &hreg, &preg)); | |
5172 | } | |
5173 | } | |
5174 | \f | |
55a2c322 VM |
5175 | |
5176 | /* True when we use LRA instead of reload pass for the current | |
5177 | function. */ | |
5178 | bool ira_use_lra_p; | |
5179 | ||
311aab06 VM |
5180 | /* True if we have allocno conflicts. It is false for non-optimized |
5181 | mode or when the conflict table is too big. */ | |
5182 | bool ira_conflicts_p; | |
5183 | ||
ae2b9cb6 BS |
5184 | /* Saved between IRA and reload. */ |
5185 | static int saved_flag_ira_share_spill_slots; | |
5186 | ||
058e97ec VM |
5187 | /* This is the main entry of IRA. */ |
5188 | static void | |
5189 | ira (FILE *f) | |
5190 | { | |
058e97ec | 5191 | bool loops_p; |
70cc3288 | 5192 | int ira_max_point_before_emit; |
55a2c322 VM |
5193 | bool saved_flag_caller_saves = flag_caller_saves; |
5194 | enum ira_region saved_flag_ira_region = flag_ira_region; | |
5195 | ||
62869a1c RB |
5196 | clear_bb_flags (); |
5197 | ||
0064f49e WD |
5198 | /* Determine if the current function is a leaf before running IRA |
5199 | since this can impact optimizations done by the prologue and | |
5200 | epilogue thus changing register elimination offsets. | |
5201 | Other target callbacks may use crtl->is_leaf too, including | |
5202 | SHRINK_WRAPPING_ENABLED, so initialize as early as possible. */ | |
5203 | crtl->is_leaf = leaf_function_p (); | |
5204 | ||
bcb21886 KY |
5205 | /* Perform target specific PIC register initialization. */ |
5206 | targetm.init_pic_reg (); | |
5207 | ||
11b8091f EB |
5208 | if (optimize) |
5209 | { | |
5210 | ira_conflicts_p = true; | |
5211 | ||
5212 | /* Determine the number of pseudos actually requiring coloring. */ | |
5213 | unsigned int num_used_regs = 0; | |
5214 | for (unsigned int i = FIRST_PSEUDO_REGISTER; i < DF_REG_SIZE (df); i++) | |
5215 | if (DF_REG_DEF_COUNT (i) || DF_REG_USE_COUNT (i)) | |
5216 | num_used_regs++; | |
5217 | ||
5218 | /* If there are too many pseudos and/or basic blocks (e.g. 10K | |
5219 | pseudos and 10K blocks or 100K pseudos and 1K blocks), we will | |
5220 | use simplified and faster algorithms in LRA. */ | |
5221 | lra_simple_p | |
5222 | = ira_use_lra_p | |
5223 | && num_used_regs >= (1U << 26) / last_basic_block_for_fn (cfun); | |
5224 | } | |
5225 | else | |
5226 | { | |
5227 | ira_conflicts_p = false; | |
5228 | lra_simple_p = ira_use_lra_p; | |
5229 | } | |
891f31f9 | 5230 | |
55a2c322 VM |
5231 | if (lra_simple_p) |
5232 | { | |
5233 | /* It permits to skip live range splitting in LRA. */ | |
5234 | flag_caller_saves = false; | |
5235 | /* There is no sense to do regional allocation when we use | |
5236 | simplified LRA. */ | |
5237 | flag_ira_region = IRA_REGION_ONE; | |
5238 | ira_conflicts_p = false; | |
5239 | } | |
5240 | ||
5241 | #ifndef IRA_NO_OBSTACK | |
5242 | gcc_obstack_init (&ira_obstack); | |
5243 | #endif | |
5244 | bitmap_obstack_initialize (&ira_bitmap_obstack); | |
058e97ec | 5245 | |
001010df KC |
5246 | /* LRA uses its own infrastructure to handle caller save registers. */ |
5247 | if (flag_caller_saves && !ira_use_lra_p) | |
dc12b70e JZ |
5248 | init_caller_save (); |
5249 | ||
058e97ec VM |
5250 | if (flag_ira_verbose < 10) |
5251 | { | |
5252 | internal_flag_ira_verbose = flag_ira_verbose; | |
5253 | ira_dump_file = f; | |
5254 | } | |
5255 | else | |
5256 | { | |
5257 | internal_flag_ira_verbose = flag_ira_verbose - 10; | |
5258 | ira_dump_file = stderr; | |
5259 | } | |
5260 | ||
5261 | setup_prohibited_mode_move_regs (); | |
3b6d1699 | 5262 | decrease_live_ranges_number (); |
058e97ec | 5263 | df_note_add_problem (); |
5d517141 SB |
5264 | |
5265 | /* DF_LIVE can't be used in the register allocator, too many other | |
5266 | parts of the compiler depend on using the "classic" liveness | |
5267 | interpretation of the DF_LR problem. See PR38711. | |
5268 | Remove the problem, so that we don't spend time updating it in | |
5269 | any of the df_analyze() calls during IRA/LRA. */ | |
5270 | if (optimize > 1) | |
5271 | df_remove_problem (df_live); | |
5272 | gcc_checking_assert (df_live == NULL); | |
5273 | ||
b2b29377 MM |
5274 | if (flag_checking) |
5275 | df->changeable_flags |= DF_VERIFY_SCHEDULED; | |
5276 | ||
058e97ec | 5277 | df_analyze (); |
3b6d1699 | 5278 | |
2d73cc45 MJ |
5279 | init_reg_equiv (); |
5280 | if (ira_conflicts_p) | |
5281 | { | |
5282 | calculate_dominance_info (CDI_DOMINATORS); | |
5283 | ||
5284 | if (split_live_ranges_for_shrink_wrap ()) | |
5285 | df_analyze (); | |
5286 | ||
5287 | free_dominance_info (CDI_DOMINATORS); | |
5288 | } | |
5289 | ||
058e97ec | 5290 | df_clear_flags (DF_NO_INSN_RESCAN); |
2d73cc45 | 5291 | |
ba52669f AM |
5292 | indirect_jump_optimize (); |
5293 | if (delete_trivially_dead_insns (get_insns (), max_reg_num ())) | |
5294 | df_analyze (); | |
5295 | ||
058e97ec VM |
5296 | regstat_init_n_sets_and_refs (); |
5297 | regstat_compute_ri (); | |
5298 | ||
5299 | /* If we are not optimizing, then this is the only place before | |
5300 | register allocation where dataflow is done. And that is needed | |
5301 | to generate these warnings. */ | |
5302 | if (warn_clobbered) | |
5303 | generate_setjmp_warnings (); | |
5304 | ||
1833192f | 5305 | if (resize_reg_info () && flag_ira_loop_pressure) |
b11f0116 | 5306 | ira_set_pseudo_classes (true, ira_dump_file); |
1833192f | 5307 | |
42ae0d7f | 5308 | init_alias_analysis (); |
c38c11a1 | 5309 | loop_optimizer_init (AVOID_CFG_MODIFICATIONS); |
10e04446 | 5310 | reg_equiv = XCNEWVEC (struct equivalence, max_reg_num ()); |
6d1e98df | 5311 | update_equiv_regs_prescan (); |
ba52669f | 5312 | update_equiv_regs (); |
10e04446 AM |
5313 | |
5314 | /* Don't move insns if live range shrinkage or register | |
5315 | pressure-sensitive scheduling were done because it will not | |
5316 | improve allocation but likely worsen insn scheduling. */ | |
5317 | if (optimize | |
5318 | && !flag_live_range_shrinkage | |
5319 | && !(flag_sched_pressure && flag_schedule_insns)) | |
5320 | combine_and_move_insns (); | |
5321 | ||
5322 | /* Gather additional equivalences with memory. */ | |
42ae0d7f | 5323 | if (optimize) |
10e04446 AM |
5324 | add_store_equivs (); |
5325 | ||
c38c11a1 | 5326 | loop_optimizer_finalize (); |
f3c82ff9 | 5327 | free_dominance_info (CDI_DOMINATORS); |
42ae0d7f AM |
5328 | end_alias_analysis (); |
5329 | free (reg_equiv); | |
5330 | ||
55a2c322 | 5331 | setup_reg_equiv (); |
10e04446 | 5332 | grow_reg_equivs (); |
55a2c322 | 5333 | setup_reg_equiv_init (); |
058e97ec | 5334 | |
fb99ee9b | 5335 | allocated_reg_info_size = max_reg_num (); |
e8d7e3e7 VM |
5336 | |
5337 | /* It is not worth to do such improvement when we use a simple | |
5338 | allocation because of -O0 usage or because the function is too | |
5339 | big. */ | |
5340 | if (ira_conflicts_p) | |
2d73cc45 | 5341 | find_moveable_pseudos (); |
acf41a74 | 5342 | |
fb99ee9b | 5343 | max_regno_before_ira = max_reg_num (); |
8d49e7ef | 5344 | ira_setup_eliminable_regset (); |
b8698a0f | 5345 | |
058e97ec VM |
5346 | ira_overall_cost = ira_reg_cost = ira_mem_cost = 0; |
5347 | ira_load_cost = ira_store_cost = ira_shuffle_cost = 0; | |
5348 | ira_move_loops_num = ira_additional_jumps_num = 0; | |
b8698a0f | 5349 | |
058e97ec | 5350 | ira_assert (current_loops == NULL); |
2608d841 | 5351 | if (flag_ira_region == IRA_REGION_ALL || flag_ira_region == IRA_REGION_MIXED) |
661bc682 | 5352 | loop_optimizer_init (AVOID_CFG_MODIFICATIONS | LOOPS_HAVE_RECORDED_EXITS); |
b8698a0f | 5353 | |
058e97ec VM |
5354 | if (internal_flag_ira_verbose > 0 && ira_dump_file != NULL) |
5355 | fprintf (ira_dump_file, "Building IRA IR\n"); | |
2608d841 | 5356 | loops_p = ira_build (); |
b8698a0f | 5357 | |
311aab06 | 5358 | ira_assert (ira_conflicts_p || !loops_p); |
3553f0bb VM |
5359 | |
5360 | saved_flag_ira_share_spill_slots = flag_ira_share_spill_slots; | |
de8e52f0 | 5361 | if (too_high_register_pressure_p () || cfun->calls_setjmp) |
3553f0bb | 5362 | /* It is just wasting compiler's time to pack spilled pseudos into |
de8e52f0 VM |
5363 | stack slots in this case -- prohibit it. We also do this if |
5364 | there is setjmp call because a variable not modified between | |
5365 | setjmp and longjmp the compiler is required to preserve its | |
5366 | value and sharing slots does not guarantee it. */ | |
3553f0bb VM |
5367 | flag_ira_share_spill_slots = FALSE; |
5368 | ||
cb1ca6ac | 5369 | ira_color (); |
b8698a0f | 5370 | |
058e97ec | 5371 | ira_max_point_before_emit = ira_max_point; |
b8698a0f | 5372 | |
1756cb66 VM |
5373 | ira_initiate_emit_data (); |
5374 | ||
058e97ec | 5375 | ira_emit (loops_p); |
b8698a0f | 5376 | |
55a2c322 | 5377 | max_regno = max_reg_num (); |
311aab06 | 5378 | if (ira_conflicts_p) |
058e97ec | 5379 | { |
058e97ec | 5380 | if (! loops_p) |
55a2c322 VM |
5381 | { |
5382 | if (! ira_use_lra_p) | |
5383 | ira_initiate_assign (); | |
5384 | } | |
058e97ec VM |
5385 | else |
5386 | { | |
fb99ee9b | 5387 | expand_reg_info (); |
b8698a0f | 5388 | |
55a2c322 VM |
5389 | if (ira_use_lra_p) |
5390 | { | |
5391 | ira_allocno_t a; | |
5392 | ira_allocno_iterator ai; | |
5393 | ||
5394 | FOR_EACH_ALLOCNO (a, ai) | |
9d6e10c7 RL |
5395 | { |
5396 | int old_regno = ALLOCNO_REGNO (a); | |
5397 | int new_regno = REGNO (ALLOCNO_EMIT_DATA (a)->reg); | |
5398 | ||
5399 | ALLOCNO_REGNO (a) = new_regno; | |
5400 | ||
5401 | if (old_regno != new_regno) | |
5402 | setup_reg_classes (new_regno, reg_preferred_class (old_regno), | |
5403 | reg_alternate_class (old_regno), | |
5404 | reg_allocno_class (old_regno)); | |
5405 | } | |
55a2c322 VM |
5406 | } |
5407 | else | |
5408 | { | |
5409 | if (internal_flag_ira_verbose > 0 && ira_dump_file != NULL) | |
5410 | fprintf (ira_dump_file, "Flattening IR\n"); | |
5411 | ira_flattening (max_regno_before_ira, ira_max_point_before_emit); | |
5412 | } | |
058e97ec VM |
5413 | /* New insns were generated: add notes and recalculate live |
5414 | info. */ | |
5415 | df_analyze (); | |
b8698a0f | 5416 | |
544e7e78 SB |
5417 | /* ??? Rebuild the loop tree, but why? Does the loop tree |
5418 | change if new insns were generated? Can that be handled | |
5419 | by updating the loop tree incrementally? */ | |
661bc682 | 5420 | loop_optimizer_finalize (); |
57548aa2 | 5421 | free_dominance_info (CDI_DOMINATORS); |
661bc682 RB |
5422 | loop_optimizer_init (AVOID_CFG_MODIFICATIONS |
5423 | | LOOPS_HAVE_RECORDED_EXITS); | |
058e97ec | 5424 | |
55a2c322 VM |
5425 | if (! ira_use_lra_p) |
5426 | { | |
5427 | setup_allocno_assignment_flags (); | |
5428 | ira_initiate_assign (); | |
5429 | ira_reassign_conflict_allocnos (max_regno); | |
5430 | } | |
058e97ec VM |
5431 | } |
5432 | } | |
5433 | ||
1756cb66 VM |
5434 | ira_finish_emit_data (); |
5435 | ||
058e97ec | 5436 | setup_reg_renumber (); |
b8698a0f | 5437 | |
058e97ec | 5438 | calculate_allocation_cost (); |
b8698a0f | 5439 | |
058e97ec | 5440 | #ifdef ENABLE_IRA_CHECKING |
e5119fab VM |
5441 | if (ira_conflicts_p && ! ira_use_lra_p) |
5442 | /* Opposite to reload pass, LRA does not use any conflict info | |
5443 | from IRA. We don't rebuild conflict info for LRA (through | |
67914693 | 5444 | ira_flattening call) and cannot use the check here. We could |
e5119fab VM |
5445 | rebuild this info for LRA in the check mode but there is a risk |
5446 | that code generated with the check and without it will be a bit | |
5447 | different. Calling ira_flattening in any mode would be a | |
5448 | wasting CPU time. So do not check the allocation for LRA. */ | |
058e97ec VM |
5449 | check_allocation (); |
5450 | #endif | |
b8698a0f | 5451 | |
ba52669f | 5452 | if (max_regno != max_regno_before_ira) |
058e97ec VM |
5453 | { |
5454 | regstat_free_n_sets_and_refs (); | |
5455 | regstat_free_ri (); | |
5456 | regstat_init_n_sets_and_refs (); | |
5457 | regstat_compute_ri (); | |
5458 | } | |
5459 | ||
058e97ec | 5460 | overall_cost_before = ira_overall_cost; |
e5b0e1ca VM |
5461 | if (! ira_conflicts_p) |
5462 | grow_reg_equivs (); | |
5463 | else | |
058e97ec VM |
5464 | { |
5465 | fix_reg_equiv_init (); | |
b8698a0f | 5466 | |
058e97ec VM |
5467 | #ifdef ENABLE_IRA_CHECKING |
5468 | print_redundant_copies (); | |
5469 | #endif | |
9994ad20 KC |
5470 | if (! ira_use_lra_p) |
5471 | { | |
5472 | ira_spilled_reg_stack_slots_num = 0; | |
5473 | ira_spilled_reg_stack_slots | |
99b1c316 | 5474 | = ((class ira_spilled_reg_stack_slot *) |
9994ad20 | 5475 | ira_allocate (max_regno |
99b1c316 | 5476 | * sizeof (class ira_spilled_reg_stack_slot))); |
1c252ef3 | 5477 | memset ((void *)ira_spilled_reg_stack_slots, 0, |
99b1c316 | 5478 | max_regno * sizeof (class ira_spilled_reg_stack_slot)); |
9994ad20 | 5479 | } |
058e97ec | 5480 | } |
6399c0ab | 5481 | allocate_initial_values (); |
e8d7e3e7 VM |
5482 | |
5483 | /* See comment for find_moveable_pseudos call. */ | |
5484 | if (ira_conflicts_p) | |
5485 | move_unallocated_pseudos (); | |
55a2c322 VM |
5486 | |
5487 | /* Restore original values. */ | |
5488 | if (lra_simple_p) | |
5489 | { | |
5490 | flag_caller_saves = saved_flag_caller_saves; | |
5491 | flag_ira_region = saved_flag_ira_region; | |
5492 | } | |
d3afd9aa RB |
5493 | } |
5494 | ||
5495 | static void | |
5496 | do_reload (void) | |
5497 | { | |
5498 | basic_block bb; | |
5499 | bool need_dce; | |
bcb21886 | 5500 | unsigned pic_offset_table_regno = INVALID_REGNUM; |
ae2b9cb6 | 5501 | |
67463efb | 5502 | if (flag_ira_verbose < 10) |
ae2b9cb6 | 5503 | ira_dump_file = dump_file; |
058e97ec | 5504 | |
bcb21886 KY |
5505 | /* If pic_offset_table_rtx is a pseudo register, then keep it so |
5506 | after reload to avoid possible wrong usages of hard reg assigned | |
5507 | to it. */ | |
5508 | if (pic_offset_table_rtx | |
5509 | && REGNO (pic_offset_table_rtx) >= FIRST_PSEUDO_REGISTER) | |
5510 | pic_offset_table_regno = REGNO (pic_offset_table_rtx); | |
5511 | ||
55a2c322 VM |
5512 | timevar_push (TV_RELOAD); |
5513 | if (ira_use_lra_p) | |
5514 | { | |
5515 | if (current_loops != NULL) | |
5516 | { | |
661bc682 | 5517 | loop_optimizer_finalize (); |
55a2c322 VM |
5518 | free_dominance_info (CDI_DOMINATORS); |
5519 | } | |
04a90bec | 5520 | FOR_ALL_BB_FN (bb, cfun) |
55a2c322 VM |
5521 | bb->loop_father = NULL; |
5522 | current_loops = NULL; | |
55a2c322 VM |
5523 | |
5524 | ira_destroy (); | |
058e97ec | 5525 | |
55a2c322 VM |
5526 | lra (ira_dump_file); |
5527 | /* ???!!! Move it before lra () when we use ira_reg_equiv in | |
5528 | LRA. */ | |
9771b263 | 5529 | vec_free (reg_equivs); |
55a2c322 VM |
5530 | reg_equivs = NULL; |
5531 | need_dce = false; | |
5532 | } | |
5533 | else | |
5534 | { | |
5535 | df_set_flags (DF_NO_INSN_RESCAN); | |
5536 | build_insn_chain (); | |
55a2c322 | 5537 | |
355a43a1 | 5538 | need_dce = reload (get_insns (), ira_conflicts_p); |
55a2c322 VM |
5539 | } |
5540 | ||
5541 | timevar_pop (TV_RELOAD); | |
058e97ec | 5542 | |
d3afd9aa RB |
5543 | timevar_push (TV_IRA); |
5544 | ||
55a2c322 | 5545 | if (ira_conflicts_p && ! ira_use_lra_p) |
058e97ec VM |
5546 | { |
5547 | ira_free (ira_spilled_reg_stack_slots); | |
058e97ec | 5548 | ira_finish_assign (); |
b8698a0f | 5549 | } |
55a2c322 | 5550 | |
058e97ec VM |
5551 | if (internal_flag_ira_verbose > 0 && ira_dump_file != NULL |
5552 | && overall_cost_before != ira_overall_cost) | |
16998094 | 5553 | fprintf (ira_dump_file, "+++Overall after reload %" PRId64 "\n", |
2bf7560b | 5554 | ira_overall_cost); |
b8698a0f | 5555 | |
3553f0bb VM |
5556 | flag_ira_share_spill_slots = saved_flag_ira_share_spill_slots; |
5557 | ||
55a2c322 | 5558 | if (! ira_use_lra_p) |
2608d841 | 5559 | { |
55a2c322 VM |
5560 | ira_destroy (); |
5561 | if (current_loops != NULL) | |
5562 | { | |
661bc682 | 5563 | loop_optimizer_finalize (); |
55a2c322 VM |
5564 | free_dominance_info (CDI_DOMINATORS); |
5565 | } | |
04a90bec | 5566 | FOR_ALL_BB_FN (bb, cfun) |
55a2c322 VM |
5567 | bb->loop_father = NULL; |
5568 | current_loops = NULL; | |
5569 | ||
5570 | regstat_free_ri (); | |
5571 | regstat_free_n_sets_and_refs (); | |
2608d841 | 5572 | } |
b8698a0f | 5573 | |
058e97ec | 5574 | if (optimize) |
55a2c322 | 5575 | cleanup_cfg (CLEANUP_EXPENSIVE); |
b8698a0f | 5576 | |
55a2c322 | 5577 | finish_reg_equiv (); |
058e97ec VM |
5578 | |
5579 | bitmap_obstack_release (&ira_bitmap_obstack); | |
5580 | #ifndef IRA_NO_OBSTACK | |
5581 | obstack_free (&ira_obstack, NULL); | |
5582 | #endif | |
5583 | ||
5584 | /* The code after the reload has changed so much that at this point | |
b0c11403 | 5585 | we might as well just rescan everything. Note that |
058e97ec VM |
5586 | df_rescan_all_insns is not going to help here because it does not |
5587 | touch the artificial uses and defs. */ | |
5588 | df_finish_pass (true); | |
058e97ec VM |
5589 | df_scan_alloc (NULL); |
5590 | df_scan_blocks (); | |
5591 | ||
5d517141 SB |
5592 | if (optimize > 1) |
5593 | { | |
5594 | df_live_add_problem (); | |
5595 | df_live_set_all_dirty (); | |
5596 | } | |
5597 | ||
058e97ec VM |
5598 | if (optimize) |
5599 | df_analyze (); | |
5600 | ||
b0c11403 JL |
5601 | if (need_dce && optimize) |
5602 | run_fast_dce (); | |
d3afd9aa | 5603 | |
af6e8467 RH |
5604 | /* Diagnose uses of the hard frame pointer when it is used as a global |
5605 | register. Often we can get away with letting the user appropriate | |
5606 | the frame pointer, but we should let them know when code generation | |
5607 | makes that impossible. */ | |
5608 | if (global_regs[HARD_FRAME_POINTER_REGNUM] && frame_pointer_needed) | |
5609 | { | |
5610 | tree decl = global_regs_decl[HARD_FRAME_POINTER_REGNUM]; | |
5611 | error_at (DECL_SOURCE_LOCATION (current_function_decl), | |
5612 | "frame pointer required, but reserved"); | |
5613 | inform (DECL_SOURCE_LOCATION (decl), "for %qD", decl); | |
5614 | } | |
5615 | ||
355a43a1 EB |
5616 | /* If we are doing generic stack checking, give a warning if this |
5617 | function's frame size is larger than we expect. */ | |
5618 | if (flag_stack_check == GENERIC_STACK_CHECK) | |
5619 | { | |
f075bd95 | 5620 | poly_int64 size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE; |
355a43a1 EB |
5621 | |
5622 | for (int i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
a365fa06 RS |
5623 | if (df_regs_ever_live_p (i) |
5624 | && !fixed_regs[i] | |
6c476222 | 5625 | && !crtl->abi->clobbers_full_reg_p (i)) |
355a43a1 EB |
5626 | size += UNITS_PER_WORD; |
5627 | ||
f075bd95 | 5628 | if (constant_lower_bound (size) > STACK_CHECK_MAX_FRAME_SIZE) |
355a43a1 EB |
5629 | warning (0, "frame size too large for reliable stack checking"); |
5630 | } | |
5631 | ||
bcb21886 KY |
5632 | if (pic_offset_table_regno != INVALID_REGNUM) |
5633 | pic_offset_table_rtx = gen_rtx_REG (Pmode, pic_offset_table_regno); | |
5634 | ||
d3afd9aa | 5635 | timevar_pop (TV_IRA); |
058e97ec | 5636 | } |
058e97ec | 5637 | \f |
058e97ec | 5638 | /* Run the integrated register allocator. */ |
058e97ec | 5639 | |
27a4cd48 DM |
5640 | namespace { |
5641 | ||
5642 | const pass_data pass_data_ira = | |
058e97ec | 5643 | { |
27a4cd48 DM |
5644 | RTL_PASS, /* type */ |
5645 | "ira", /* name */ | |
5646 | OPTGROUP_NONE, /* optinfo_flags */ | |
27a4cd48 DM |
5647 | TV_IRA, /* tv_id */ |
5648 | 0, /* properties_required */ | |
5649 | 0, /* properties_provided */ | |
5650 | 0, /* properties_destroyed */ | |
5651 | 0, /* todo_flags_start */ | |
5652 | TODO_do_not_ggc_collect, /* todo_flags_finish */ | |
d3afd9aa RB |
5653 | }; |
5654 | ||
27a4cd48 DM |
5655 | class pass_ira : public rtl_opt_pass |
5656 | { | |
5657 | public: | |
c3284718 RS |
5658 | pass_ira (gcc::context *ctxt) |
5659 | : rtl_opt_pass (pass_data_ira, ctxt) | |
27a4cd48 DM |
5660 | {} |
5661 | ||
5662 | /* opt_pass methods: */ | |
a50fa76a BS |
5663 | virtual bool gate (function *) |
5664 | { | |
5665 | return !targetm.no_register_allocation; | |
5666 | } | |
be55bfe6 TS |
5667 | virtual unsigned int execute (function *) |
5668 | { | |
5669 | ira (dump_file); | |
5670 | return 0; | |
5671 | } | |
27a4cd48 DM |
5672 | |
5673 | }; // class pass_ira | |
5674 | ||
5675 | } // anon namespace | |
5676 | ||
5677 | rtl_opt_pass * | |
5678 | make_pass_ira (gcc::context *ctxt) | |
5679 | { | |
5680 | return new pass_ira (ctxt); | |
5681 | } | |
5682 | ||
27a4cd48 DM |
5683 | namespace { |
5684 | ||
5685 | const pass_data pass_data_reload = | |
d3afd9aa | 5686 | { |
27a4cd48 DM |
5687 | RTL_PASS, /* type */ |
5688 | "reload", /* name */ | |
5689 | OPTGROUP_NONE, /* optinfo_flags */ | |
27a4cd48 DM |
5690 | TV_RELOAD, /* tv_id */ |
5691 | 0, /* properties_required */ | |
5692 | 0, /* properties_provided */ | |
5693 | 0, /* properties_destroyed */ | |
5694 | 0, /* todo_flags_start */ | |
5695 | 0, /* todo_flags_finish */ | |
058e97ec | 5696 | }; |
27a4cd48 DM |
5697 | |
5698 | class pass_reload : public rtl_opt_pass | |
5699 | { | |
5700 | public: | |
c3284718 RS |
5701 | pass_reload (gcc::context *ctxt) |
5702 | : rtl_opt_pass (pass_data_reload, ctxt) | |
27a4cd48 DM |
5703 | {} |
5704 | ||
5705 | /* opt_pass methods: */ | |
a50fa76a BS |
5706 | virtual bool gate (function *) |
5707 | { | |
5708 | return !targetm.no_register_allocation; | |
5709 | } | |
be55bfe6 TS |
5710 | virtual unsigned int execute (function *) |
5711 | { | |
5712 | do_reload (); | |
5713 | return 0; | |
5714 | } | |
27a4cd48 DM |
5715 | |
5716 | }; // class pass_reload | |
5717 | ||
5718 | } // anon namespace | |
5719 | ||
5720 | rtl_opt_pass * | |
5721 | make_pass_reload (gcc::context *ctxt) | |
5722 | { | |
5723 | return new pass_reload (ctxt); | |
5724 | } |