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47dd2e78 | 1 | /* Communication between the Integrated Register Allocator (IRA) and |
2 | the rest of the compiler. | |
d91f7526 | 3 | Copyright (C) 2006, 2007, 2008, 2009, 2010 |
47dd2e78 | 4 | Free Software Foundation, Inc. |
5 | Contributed by Vladimir Makarov <vmakarov@redhat.com>. | |
6 | ||
7 | This file is part of GCC. | |
8 | ||
9 | GCC is free software; you can redistribute it and/or modify it under | |
10 | the terms of the GNU General Public License as published by the Free | |
11 | Software Foundation; either version 3, or (at your option) any later | |
12 | version. | |
13 | ||
14 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
15 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
17 | for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with GCC; see the file COPYING3. If not see | |
21 | <http://www.gnu.org/licenses/>. */ | |
22 | ||
95c83f01 | 23 | /* True if we have allocno conflicts. It is false for non-optimized |
24 | mode or when the conflict table is too big. */ | |
25 | extern bool ira_conflicts_p; | |
26 | ||
a1e0509e | 27 | struct target_ira { |
28 | /* Number of given class hard registers available for the register | |
29 | allocation for given classes. */ | |
30 | int x_ira_available_class_regs[N_REG_CLASSES]; | |
31 | ||
66d9a7b9 | 32 | /* Map: hard register number -> allocno class it belongs to. If the |
a1e0509e | 33 | corresponding class is NO_REGS, the hard register is not available |
34 | for allocation. */ | |
66d9a7b9 | 35 | enum reg_class x_ira_hard_regno_allocno_class[FIRST_PSEUDO_REGISTER]; |
a1e0509e | 36 | |
66d9a7b9 | 37 | /* Number of allocno classes. Allocno classes are register classes |
38 | which can be used for allocations of allocnos. */ | |
39 | int x_ira_allocno_classes_num; | |
40 | ||
41 | /* The array containing allocno classes. Only first | |
42 | IRA_ALLOCNO_CLASSES_NUM elements are used for this. */ | |
43 | enum reg_class x_ira_allocno_classes[N_REG_CLASSES]; | |
28491485 | 44 | |
66d9a7b9 | 45 | /* Map of all register classes to corresponding allocno classes |
46 | containing the given class. If given class is not a subset of an | |
47 | allocno class, we translate it into the cheapest allocno class. */ | |
48 | enum reg_class x_ira_allocno_class_translate[N_REG_CLASSES]; | |
28491485 | 49 | |
66d9a7b9 | 50 | /* Number of pressure classes. Pressure classes are register |
51 | classes for which we calculate register pressure. */ | |
52 | int x_ira_pressure_classes_num; | |
28491485 | 53 | |
66d9a7b9 | 54 | /* The array containing pressure classes. Only first |
55 | IRA_PRESSURE_CLASSES_NUM elements are used for this. */ | |
56 | enum reg_class x_ira_pressure_classes[N_REG_CLASSES]; | |
57 | ||
58 | /* Map of all register classes to corresponding pressure classes | |
59 | containing the given class. If given class is not a subset of an | |
60 | pressure class, we translate it into the cheapest pressure | |
61 | class. */ | |
62 | enum reg_class x_ira_pressure_class_translate[N_REG_CLASSES]; | |
63 | ||
64 | /* Bigest pressure register class containing stack registers. | |
65 | NO_REGS if there are no stack registers. */ | |
66 | enum reg_class x_ira_stack_reg_pressure_class; | |
67 | ||
68 | /* Maps: register class x machine mode -> maximal/minimal number of | |
69 | hard registers of given class needed to store value of given | |
70 | mode. */ | |
71 | int x_ira_reg_class_max_nregs[N_REG_CLASSES][MAX_MACHINE_MODE]; | |
72 | int x_ira_reg_class_min_nregs[N_REG_CLASSES][MAX_MACHINE_MODE]; | |
a1e0509e | 73 | |
74 | /* Array analogous to target hook TARGET_MEMORY_MOVE_COST. */ | |
75 | short x_ira_memory_move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][2]; | |
76 | ||
77 | /* Array of number of hard registers of given class which are | |
78 | available for the allocation. The order is defined by the | |
79 | allocation order. */ | |
80 | short x_ira_class_hard_regs[N_REG_CLASSES][FIRST_PSEUDO_REGISTER]; | |
81 | ||
82 | /* The number of elements of the above array for given register | |
83 | class. */ | |
84 | int x_ira_class_hard_regs_num[N_REG_CLASSES]; | |
66d9a7b9 | 85 | |
86 | /* Function specific hard registers can not be used for the register | |
87 | allocation. */ | |
88 | HARD_REG_SET x_ira_no_alloc_regs; | |
a1e0509e | 89 | }; |
90 | ||
91 | extern struct target_ira default_target_ira; | |
92 | #if SWITCHABLE_TARGET | |
93 | extern struct target_ira *this_target_ira; | |
94 | #else | |
95 | #define this_target_ira (&default_target_ira) | |
96 | #endif | |
97 | ||
98 | #define ira_available_class_regs \ | |
99 | (this_target_ira->x_ira_available_class_regs) | |
66d9a7b9 | 100 | #define ira_hard_regno_allocno_class \ |
101 | (this_target_ira->x_ira_hard_regno_allocno_class) | |
102 | #define ira_allocno_classes_num \ | |
103 | (this_target_ira->x_ira_allocno_classes_num) | |
104 | #define ira_allocno_classes \ | |
105 | (this_target_ira->x_ira_allocno_classes) | |
106 | #define ira_allocno_class_translate \ | |
107 | (this_target_ira->x_ira_allocno_class_translate) | |
108 | #define ira_pressure_classes_num \ | |
109 | (this_target_ira->x_ira_pressure_classes_num) | |
110 | #define ira_pressure_classes \ | |
111 | (this_target_ira->x_ira_pressure_classes) | |
112 | #define ira_pressure_class_translate \ | |
113 | (this_target_ira->x_ira_pressure_class_translate) | |
114 | #define ira_stack_reg_pressure_class \ | |
115 | (this_target_ira->x_ira_stack_reg_pressure_class) | |
116 | #define ira_reg_class_max_nregs \ | |
117 | (this_target_ira->x_ira_reg_class_max_nregs) | |
118 | #define ira_reg_class_min_nregs \ | |
119 | (this_target_ira->x_ira_reg_class_min_nregs) | |
a1e0509e | 120 | #define ira_memory_move_cost \ |
121 | (this_target_ira->x_ira_memory_move_cost) | |
122 | #define ira_class_hard_regs \ | |
123 | (this_target_ira->x_ira_class_hard_regs) | |
124 | #define ira_class_hard_regs_num \ | |
125 | (this_target_ira->x_ira_class_hard_regs_num) | |
66d9a7b9 | 126 | #define ira_no_alloc_regs \ |
127 | (this_target_ira->x_ira_no_alloc_regs) | |
a7dcf969 | 128 | |
47dd2e78 | 129 | extern void ira_init_once (void); |
130 | extern void ira_init (void); | |
131 | extern void ira_finish_once (void); | |
a7dcf969 | 132 | extern void ira_setup_eliminable_regset (void); |
47dd2e78 | 133 | extern rtx ira_eliminate_regs (rtx, enum machine_mode); |
a7dcf969 | 134 | extern void ira_set_pseudo_classes (FILE *); |
135 | extern void ira_implicitly_set_insn_hard_regs (HARD_REG_SET *); | |
47dd2e78 | 136 | |
137 | extern void ira_sort_regnos_for_alter_reg (int *, int, unsigned int *); | |
138 | extern void ira_mark_allocation_change (int); | |
139 | extern void ira_mark_memory_move_deletion (int, int); | |
140 | extern bool ira_reassign_pseudos (int *, int, HARD_REG_SET, HARD_REG_SET *, | |
141 | HARD_REG_SET *, bitmap); | |
142 | extern rtx ira_reuse_stack_slot (int, unsigned int, unsigned int); | |
143 | extern void ira_mark_new_stack_slot (rtx, int, unsigned int); | |
144 | extern bool ira_better_spill_reload_regno_p (int *, int *, rtx, rtx, rtx); | |
732f3fd8 | 145 | extern bool ira_bad_reload_regno (int, rtx, rtx); |
47dd2e78 | 146 | |
4164ad58 | 147 | extern void ira_adjust_equiv_reg_cost (unsigned, int); |