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058e97ec VM |
1 | /* Communication between the Integrated Register Allocator (IRA) and |
2 | the rest of the compiler. | |
23a5b65a | 3 | Copyright (C) 2006-2014 Free Software Foundation, Inc. |
058e97ec VM |
4 | Contributed by Vladimir Makarov <vmakarov@redhat.com>. |
5 | ||
6 | This file is part of GCC. | |
7 | ||
8 | GCC is free software; you can redistribute it and/or modify it under | |
9 | the terms of the GNU General Public License as published by the Free | |
10 | Software Foundation; either version 3, or (at your option) any later | |
11 | version. | |
12 | ||
13 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
14 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GCC; see the file COPYING3. If not see | |
20 | <http://www.gnu.org/licenses/>. */ | |
21 | ||
55a2c322 VM |
22 | /* True when we use LRA instead of reload pass for the current |
23 | function. */ | |
24 | extern bool ira_use_lra_p; | |
25 | ||
311aab06 VM |
26 | /* True if we have allocno conflicts. It is false for non-optimized |
27 | mode or when the conflict table is too big. */ | |
28 | extern bool ira_conflicts_p; | |
29 | ||
55a2c322 VM |
30 | struct target_ira |
31 | { | |
1756cb66 | 32 | /* Map: hard register number -> allocno class it belongs to. If the |
afcc66c4 RS |
33 | corresponding class is NO_REGS, the hard register is not available |
34 | for allocation. */ | |
1756cb66 | 35 | enum reg_class x_ira_hard_regno_allocno_class[FIRST_PSEUDO_REGISTER]; |
afcc66c4 | 36 | |
1756cb66 VM |
37 | /* Number of allocno classes. Allocno classes are register classes |
38 | which can be used for allocations of allocnos. */ | |
39 | int x_ira_allocno_classes_num; | |
40 | ||
41 | /* The array containing allocno classes. Only first | |
42 | IRA_ALLOCNO_CLASSES_NUM elements are used for this. */ | |
43 | enum reg_class x_ira_allocno_classes[N_REG_CLASSES]; | |
fe82cdfb | 44 | |
1756cb66 VM |
45 | /* Map of all register classes to corresponding allocno classes |
46 | containing the given class. If given class is not a subset of an | |
47 | allocno class, we translate it into the cheapest allocno class. */ | |
48 | enum reg_class x_ira_allocno_class_translate[N_REG_CLASSES]; | |
fe82cdfb | 49 | |
1756cb66 VM |
50 | /* Number of pressure classes. Pressure classes are register |
51 | classes for which we calculate register pressure. */ | |
52 | int x_ira_pressure_classes_num; | |
fe82cdfb | 53 | |
1756cb66 VM |
54 | /* The array containing pressure classes. Only first |
55 | IRA_PRESSURE_CLASSES_NUM elements are used for this. */ | |
56 | enum reg_class x_ira_pressure_classes[N_REG_CLASSES]; | |
57 | ||
58 | /* Map of all register classes to corresponding pressure classes | |
59 | containing the given class. If given class is not a subset of an | |
60 | pressure class, we translate it into the cheapest pressure | |
61 | class. */ | |
62 | enum reg_class x_ira_pressure_class_translate[N_REG_CLASSES]; | |
63 | ||
64 | /* Bigest pressure register class containing stack registers. | |
65 | NO_REGS if there are no stack registers. */ | |
66 | enum reg_class x_ira_stack_reg_pressure_class; | |
67 | ||
68 | /* Maps: register class x machine mode -> maximal/minimal number of | |
69 | hard registers of given class needed to store value of given | |
70 | mode. */ | |
a8c44c52 AS |
71 | unsigned char x_ira_reg_class_max_nregs[N_REG_CLASSES][MAX_MACHINE_MODE]; |
72 | unsigned char x_ira_reg_class_min_nregs[N_REG_CLASSES][MAX_MACHINE_MODE]; | |
afcc66c4 RS |
73 | |
74 | /* Array analogous to target hook TARGET_MEMORY_MOVE_COST. */ | |
75 | short x_ira_memory_move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][2]; | |
76 | ||
77 | /* Array of number of hard registers of given class which are | |
78 | available for the allocation. The order is defined by the | |
79 | allocation order. */ | |
80 | short x_ira_class_hard_regs[N_REG_CLASSES][FIRST_PSEUDO_REGISTER]; | |
81 | ||
82 | /* The number of elements of the above array for given register | |
83 | class. */ | |
84 | int x_ira_class_hard_regs_num[N_REG_CLASSES]; | |
1756cb66 | 85 | |
55a2c322 VM |
86 | /* Register class subset relation: TRUE if the first class is a subset |
87 | of the second one considering only hard registers available for the | |
88 | allocation. */ | |
89 | int x_ira_class_subset_p[N_REG_CLASSES][N_REG_CLASSES]; | |
90 | ||
91 | /* The biggest class inside of intersection of the two classes (that | |
92 | is calculated taking only hard registers available for allocation | |
93 | into account. If the both classes contain no hard registers | |
94 | available for allocation, the value is calculated with taking all | |
95 | hard-registers including fixed ones into account. */ | |
96 | enum reg_class x_ira_reg_class_subset[N_REG_CLASSES][N_REG_CLASSES]; | |
97 | ||
98 | /* True if the two classes (that is calculated taking only hard | |
99 | registers available for allocation into account; are | |
100 | intersected. */ | |
101 | bool x_ira_reg_classes_intersect_p[N_REG_CLASSES][N_REG_CLASSES]; | |
102 | ||
c9d74da6 RS |
103 | /* If class CL has a single allocatable register of mode M, |
104 | index [CL][M] gives the number of that register, otherwise it is -1. */ | |
105 | short x_ira_class_singleton[N_REG_CLASSES][MAX_MACHINE_MODE]; | |
106 | ||
1756cb66 VM |
107 | /* Function specific hard registers can not be used for the register |
108 | allocation. */ | |
109 | HARD_REG_SET x_ira_no_alloc_regs; | |
afcc66c4 RS |
110 | }; |
111 | ||
112 | extern struct target_ira default_target_ira; | |
113 | #if SWITCHABLE_TARGET | |
114 | extern struct target_ira *this_target_ira; | |
115 | #else | |
116 | #define this_target_ira (&default_target_ira) | |
117 | #endif | |
118 | ||
1756cb66 VM |
119 | #define ira_hard_regno_allocno_class \ |
120 | (this_target_ira->x_ira_hard_regno_allocno_class) | |
121 | #define ira_allocno_classes_num \ | |
122 | (this_target_ira->x_ira_allocno_classes_num) | |
123 | #define ira_allocno_classes \ | |
124 | (this_target_ira->x_ira_allocno_classes) | |
125 | #define ira_allocno_class_translate \ | |
126 | (this_target_ira->x_ira_allocno_class_translate) | |
127 | #define ira_pressure_classes_num \ | |
128 | (this_target_ira->x_ira_pressure_classes_num) | |
129 | #define ira_pressure_classes \ | |
130 | (this_target_ira->x_ira_pressure_classes) | |
131 | #define ira_pressure_class_translate \ | |
132 | (this_target_ira->x_ira_pressure_class_translate) | |
133 | #define ira_stack_reg_pressure_class \ | |
134 | (this_target_ira->x_ira_stack_reg_pressure_class) | |
135 | #define ira_reg_class_max_nregs \ | |
136 | (this_target_ira->x_ira_reg_class_max_nregs) | |
137 | #define ira_reg_class_min_nregs \ | |
138 | (this_target_ira->x_ira_reg_class_min_nregs) | |
afcc66c4 RS |
139 | #define ira_memory_move_cost \ |
140 | (this_target_ira->x_ira_memory_move_cost) | |
141 | #define ira_class_hard_regs \ | |
142 | (this_target_ira->x_ira_class_hard_regs) | |
143 | #define ira_class_hard_regs_num \ | |
144 | (this_target_ira->x_ira_class_hard_regs_num) | |
55a2c322 VM |
145 | #define ira_class_subset_p \ |
146 | (this_target_ira->x_ira_class_subset_p) | |
147 | #define ira_reg_class_subset \ | |
148 | (this_target_ira->x_ira_reg_class_subset) | |
149 | #define ira_reg_classes_intersect_p \ | |
150 | (this_target_ira->x_ira_reg_classes_intersect_p) | |
c9d74da6 RS |
151 | #define ira_class_singleton \ |
152 | (this_target_ira->x_ira_class_singleton) | |
1756cb66 VM |
153 | #define ira_no_alloc_regs \ |
154 | (this_target_ira->x_ira_no_alloc_regs) | |
ce18efcb | 155 | |
55a2c322 | 156 | /* Major structure describing equivalence info for a pseudo. */ |
4c2b2d79 | 157 | struct ira_reg_equiv_s |
55a2c322 VM |
158 | { |
159 | /* True if we can use this equivalence. */ | |
160 | bool defined_p; | |
161 | /* True if the usage of the equivalence is profitable. */ | |
162 | bool profitable_p; | |
163 | /* Equiv. memory, constant, invariant, and initializing insns of | |
164 | given pseudo-register or NULL_RTX. */ | |
165 | rtx memory; | |
166 | rtx constant; | |
167 | rtx invariant; | |
168 | /* Always NULL_RTX if defined_p is false. */ | |
169 | rtx init_insns; | |
170 | }; | |
171 | ||
172 | /* The length of the following array. */ | |
173 | extern int ira_reg_equiv_len; | |
174 | ||
175 | /* Info about equiv. info for each register. */ | |
4c2b2d79 | 176 | extern struct ira_reg_equiv_s *ira_reg_equiv; |
55a2c322 | 177 | |
058e97ec VM |
178 | extern void ira_init_once (void); |
179 | extern void ira_init (void); | |
180 | extern void ira_finish_once (void); | |
8d49e7ef | 181 | extern void ira_setup_eliminable_regset (void); |
058e97ec | 182 | extern rtx ira_eliminate_regs (rtx, enum machine_mode); |
b11f0116 | 183 | extern void ira_set_pseudo_classes (bool, FILE *); |
ce18efcb | 184 | extern void ira_implicitly_set_insn_hard_regs (HARD_REG_SET *); |
55a2c322 | 185 | extern void ira_expand_reg_equiv (void); |
b32d5189 | 186 | extern void ira_update_equiv_info_by_shuffle_insn (int, int, rtx_insn *); |
058e97ec VM |
187 | |
188 | extern void ira_sort_regnos_for_alter_reg (int *, int, unsigned int *); | |
189 | extern void ira_mark_allocation_change (int); | |
190 | extern void ira_mark_memory_move_deletion (int, int); | |
191 | extern bool ira_reassign_pseudos (int *, int, HARD_REG_SET, HARD_REG_SET *, | |
192 | HARD_REG_SET *, bitmap); | |
193 | extern rtx ira_reuse_stack_slot (int, unsigned int, unsigned int); | |
194 | extern void ira_mark_new_stack_slot (rtx, int, unsigned int); | |
195 | extern bool ira_better_spill_reload_regno_p (int *, int *, rtx, rtx, rtx); | |
0896cc66 | 196 | extern bool ira_bad_reload_regno (int, rtx, rtx); |
058e97ec | 197 | |
8ff49c29 | 198 | extern void ira_adjust_equiv_reg_cost (unsigned, int); |