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2bbd3819 | 1 | /* Allocate registers within a basic block, for GNU compiler. |
d050d723 | 2 | Copyright (C) 1987, 1988, 1991, 1993, 1994, 1995, 1996, 1997, 1998, |
a4d3961a | 3 | 1999, 2000, 2001 Free Software Foundation, Inc. |
2bbd3819 | 4 | |
1322177d | 5 | This file is part of GCC. |
2bbd3819 | 6 | |
1322177d LB |
7 | GCC is free software; you can redistribute it and/or modify it under |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 2, or (at your option) any later | |
10 | version. | |
2bbd3819 | 11 | |
1322177d LB |
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
2bbd3819 RS |
16 | |
17 | You should have received a copy of the GNU General Public License | |
1322177d LB |
18 | along with GCC; see the file COPYING. If not, write to the Free |
19 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
20 | 02111-1307, USA. */ | |
2bbd3819 | 21 | |
2bbd3819 RS |
22 | /* Allocation of hard register numbers to pseudo registers is done in |
23 | two passes. In this pass we consider only regs that are born and | |
24 | die once within one basic block. We do this one basic block at a | |
25 | time. Then the next pass allocates the registers that remain. | |
26 | Two passes are used because this pass uses methods that work only | |
27 | on linear code, but that do a better job than the general methods | |
28 | used in global_alloc, and more quickly too. | |
29 | ||
30 | The assignments made are recorded in the vector reg_renumber | |
31 | whose space is allocated here. The rtl code itself is not altered. | |
32 | ||
33 | We assign each instruction in the basic block a number | |
34 | which is its order from the beginning of the block. | |
35 | Then we can represent the lifetime of a pseudo register with | |
36 | a pair of numbers, and check for conflicts easily. | |
37 | We can record the availability of hard registers with a | |
38 | HARD_REG_SET for each instruction. The HARD_REG_SET | |
39 | contains 0 or 1 for each hard reg. | |
40 | ||
41 | To avoid register shuffling, we tie registers together when one | |
42 | dies by being copied into another, or dies in an instruction that | |
43 | does arithmetic to produce another. The tied registers are | |
44 | allocated as one. Registers with different reg class preferences | |
45 | can never be tied unless the class preferred by one is a subclass | |
46 | of the one preferred by the other. | |
47 | ||
48 | Tying is represented with "quantity numbers". | |
49 | A non-tied register is given a new quantity number. | |
50 | Tied registers have the same quantity number. | |
64e3a413 | 51 | |
2bbd3819 RS |
52 | We have provision to exempt registers, even when they are contained |
53 | within the block, that can be tied to others that are not contained in it. | |
54 | This is so that global_alloc could process them both and tie them then. | |
55 | But this is currently disabled since tying in global_alloc is not | |
56 | yet implemented. */ | |
57 | ||
a300b8d9 JW |
58 | /* Pseudos allocated here can be reallocated by global.c if the hard register |
59 | is used as a spill register. Currently we don't allocate such pseudos | |
6cad67d2 JL |
60 | here if their preferred class is likely to be used by spills. */ |
61 | ||
2bbd3819 | 62 | #include "config.h" |
670ee920 | 63 | #include "system.h" |
2bbd3819 | 64 | #include "rtl.h" |
6baf1cc8 | 65 | #include "tm_p.h" |
2bbd3819 | 66 | #include "flags.h" |
efc9bd41 | 67 | #include "hard-reg-set.h" |
2bbd3819 RS |
68 | #include "basic-block.h" |
69 | #include "regs.h" | |
49ad7cfa | 70 | #include "function.h" |
2bbd3819 | 71 | #include "insn-config.h" |
624a8b3a | 72 | #include "insn-attr.h" |
2bbd3819 RS |
73 | #include "recog.h" |
74 | #include "output.h" | |
2e107e9e | 75 | #include "toplev.h" |
a4d3961a | 76 | #include "except.h" |
2bbd3819 RS |
77 | \f |
78 | /* Next quantity number available for allocation. */ | |
79 | ||
80 | static int next_qty; | |
81 | ||
a1ed7bdb JH |
82 | /* Information we maitain about each quantity. */ |
83 | struct qty | |
84 | { | |
85 | /* The number of refs to quantity Q. */ | |
2bbd3819 | 86 | |
a1ed7bdb | 87 | int n_refs; |
2bbd3819 | 88 | |
b2aec5c0 JH |
89 | /* The frequency of uses of quantity Q. */ |
90 | ||
91 | int freq; | |
92 | ||
a1ed7bdb JH |
93 | /* Insn number (counting from head of basic block) |
94 | where quantity Q was born. -1 if birth has not been recorded. */ | |
2bbd3819 | 95 | |
a1ed7bdb | 96 | int birth; |
2bbd3819 | 97 | |
a1ed7bdb JH |
98 | /* Insn number (counting from head of basic block) |
99 | where given quantity died. Due to the way tying is done, | |
100 | and the fact that we consider in this pass only regs that die but once, | |
101 | a quantity can die only once. Each quantity's life span | |
102 | is a set of consecutive insns. -1 if death has not been recorded. */ | |
2bbd3819 | 103 | |
a1ed7bdb | 104 | int death; |
2bbd3819 | 105 | |
a1ed7bdb JH |
106 | /* Number of words needed to hold the data in given quantity. |
107 | This depends on its machine mode. It is used for these purposes: | |
108 | 1. It is used in computing the relative importances of qtys, | |
109 | which determines the order in which we look for regs for them. | |
110 | 2. It is used in rules that prevent tying several registers of | |
111 | different sizes in a way that is geometrically impossible | |
112 | (see combine_regs). */ | |
2bbd3819 | 113 | |
a1ed7bdb | 114 | int size; |
2bbd3819 | 115 | |
a1ed7bdb | 116 | /* Number of times a reg tied to given qty lives across a CALL_INSN. */ |
2bbd3819 | 117 | |
a1ed7bdb | 118 | int n_calls_crossed; |
2bbd3819 | 119 | |
a1ed7bdb JH |
120 | /* The register number of one pseudo register whose reg_qty value is Q. |
121 | This register should be the head of the chain | |
122 | maintained in reg_next_in_qty. */ | |
2bbd3819 | 123 | |
a1ed7bdb | 124 | int first_reg; |
2bbd3819 | 125 | |
a1ed7bdb JH |
126 | /* Reg class contained in (smaller than) the preferred classes of all |
127 | the pseudo regs that are tied in given quantity. | |
128 | This is the preferred class for allocating that quantity. */ | |
129 | ||
130 | enum reg_class min_class; | |
2bbd3819 | 131 | |
a1ed7bdb JH |
132 | /* Register class within which we allocate given qty if we can't get |
133 | its preferred class. */ | |
2bbd3819 | 134 | |
a1ed7bdb | 135 | enum reg_class alternate_class; |
2bbd3819 | 136 | |
a1ed7bdb JH |
137 | /* This holds the mode of the registers that are tied to given qty, |
138 | or VOIDmode if registers with differing modes are tied together. */ | |
2bbd3819 | 139 | |
a1ed7bdb | 140 | enum machine_mode mode; |
2bbd3819 | 141 | |
a1ed7bdb JH |
142 | /* the hard reg number chosen for given quantity, |
143 | or -1 if none was found. */ | |
2bbd3819 | 144 | |
a1ed7bdb | 145 | short phys_reg; |
2bbd3819 | 146 | |
02188693 RH |
147 | /* Nonzero if this quantity has been used in a SUBREG in some |
148 | way that is illegal. */ | |
2bbd3819 | 149 | |
02188693 | 150 | char changes_mode; |
2bbd3819 | 151 | |
a1ed7bdb | 152 | }; |
2bbd3819 | 153 | |
a1ed7bdb | 154 | static struct qty *qty; |
2bbd3819 | 155 | |
a1ed7bdb | 156 | /* These fields are kept separately to speedup their clearing. */ |
2bbd3819 | 157 | |
a1ed7bdb JH |
158 | /* We maintain two hard register sets that indicate suggested hard registers |
159 | for each quantity. The first, phys_copy_sugg, contains hard registers | |
160 | that are tied to the quantity by a simple copy. The second contains all | |
161 | hard registers that are tied to the quantity via an arithmetic operation. | |
2bbd3819 | 162 | |
a1ed7bdb JH |
163 | The former register set is given priority for allocation. This tends to |
164 | eliminate copy insns. */ | |
2bbd3819 | 165 | |
a1ed7bdb JH |
166 | /* Element Q is a set of hard registers that are suggested for quantity Q by |
167 | copy insns. */ | |
2bbd3819 | 168 | |
a1ed7bdb | 169 | static HARD_REG_SET *qty_phys_copy_sugg; |
2bbd3819 | 170 | |
a1ed7bdb JH |
171 | /* Element Q is a set of hard registers that are suggested for quantity Q by |
172 | arithmetic insns. */ | |
173 | ||
174 | static HARD_REG_SET *qty_phys_sugg; | |
175 | ||
176 | /* Element Q is the number of suggested registers in qty_phys_copy_sugg. */ | |
2bbd3819 | 177 | |
a1ed7bdb | 178 | static short *qty_phys_num_copy_sugg; |
0f64b8f6 | 179 | |
a1ed7bdb | 180 | /* Element Q is the number of suggested registers in qty_phys_sugg. */ |
0f64b8f6 | 181 | |
a1ed7bdb | 182 | static short *qty_phys_num_sugg; |
2bbd3819 | 183 | |
2bbd3819 RS |
184 | /* If (REG N) has been assigned a quantity number, is a register number |
185 | of another register assigned the same quantity number, or -1 for the | |
a1ed7bdb | 186 | end of the chain. qty->first_reg point to the head of this chain. */ |
2bbd3819 | 187 | |
aabf56ce | 188 | static int *reg_next_in_qty; |
2bbd3819 RS |
189 | |
190 | /* reg_qty[N] (where N is a pseudo reg number) is the qty number of that reg | |
191 | if it is >= 0, | |
192 | of -1 if this register cannot be allocated by local-alloc, | |
193 | or -2 if not known yet. | |
194 | ||
195 | Note that if we see a use or death of pseudo register N with | |
196 | reg_qty[N] == -2, register N must be local to the current block. If | |
197 | it were used in more than one block, we would have reg_qty[N] == -1. | |
198 | This relies on the fact that if reg_basic_block[N] is >= 0, register N | |
199 | will not appear in any other block. We save a considerable number of | |
200 | tests by exploiting this. | |
201 | ||
202 | If N is < FIRST_PSEUDO_REGISTER, reg_qty[N] is undefined and should not | |
203 | be referenced. */ | |
204 | ||
205 | static int *reg_qty; | |
206 | ||
207 | /* The offset (in words) of register N within its quantity. | |
208 | This can be nonzero if register N is SImode, and has been tied | |
209 | to a subreg of a DImode register. */ | |
210 | ||
211 | static char *reg_offset; | |
212 | ||
213 | /* Vector of substitutions of register numbers, | |
214 | used to map pseudo regs into hardware regs. | |
215 | This is set up as a result of register allocation. | |
216 | Element N is the hard reg assigned to pseudo reg N, | |
217 | or is -1 if no hard reg was assigned. | |
218 | If N is a hard reg number, element N is N. */ | |
219 | ||
220 | short *reg_renumber; | |
221 | ||
222 | /* Set of hard registers live at the current point in the scan | |
223 | of the instructions in a basic block. */ | |
224 | ||
225 | static HARD_REG_SET regs_live; | |
226 | ||
227 | /* Each set of hard registers indicates registers live at a particular | |
228 | point in the basic block. For N even, regs_live_at[N] says which | |
229 | hard registers are needed *after* insn N/2 (i.e., they may not | |
230 | conflict with the outputs of insn N/2 or the inputs of insn N/2 + 1. | |
231 | ||
232 | If an object is to conflict with the inputs of insn J but not the | |
233 | outputs of insn J + 1, we say it is born at index J*2 - 1. Similarly, | |
234 | if it is to conflict with the outputs of insn J but not the inputs of | |
235 | insn J + 1, it is said to die at index J*2 + 1. */ | |
236 | ||
237 | static HARD_REG_SET *regs_live_at; | |
238 | ||
239 | /* Communicate local vars `insn_number' and `insn' | |
240 | from `block_alloc' to `reg_is_set', `wipe_dead_reg', and `alloc_qty'. */ | |
241 | static int this_insn_number; | |
242 | static rtx this_insn; | |
243 | ||
bf6d9fd7 JW |
244 | struct equivalence |
245 | { | |
246 | /* Set when an attempt should be made to replace a register | |
247 | with the associated src entry. */ | |
248 | ||
249 | char replace; | |
250 | ||
251 | /* Set when a REG_EQUIV note is found or created. Use to | |
252 | keep track of what memory accesses might be created later, | |
253 | e.g. by reload. */ | |
254 | ||
255 | rtx replacement; | |
68342d36 | 256 | |
bf6d9fd7 | 257 | rtx src; |
c25a4c25 | 258 | |
bf6d9fd7 JW |
259 | /* Loop depth is used to recognize equivalences which appear |
260 | to be present within the same loop (or in an inner loop). */ | |
261 | ||
262 | int loop_depth; | |
263 | ||
264 | /* The list of each instruction which initializes this register. */ | |
265 | ||
266 | rtx init_insns; | |
267 | }; | |
268 | ||
269 | /* reg_equiv[N] (where N is a pseudo reg number) is the equivalence | |
270 | structure for that register. */ | |
271 | ||
272 | static struct equivalence *reg_equiv; | |
135eb61c | 273 | |
3f1b9b1b JL |
274 | /* Nonzero if we recorded an equivalence for a LABEL_REF. */ |
275 | static int recorded_label_ref; | |
276 | ||
3fe41456 KG |
277 | static void alloc_qty PARAMS ((int, enum machine_mode, int, int)); |
278 | static void validate_equiv_mem_from_store PARAMS ((rtx, rtx, void *)); | |
279 | static int validate_equiv_mem PARAMS ((rtx, rtx, rtx)); | |
bf6d9fd7 JW |
280 | static int equiv_init_varies_p PARAMS ((rtx)); |
281 | static int equiv_init_movable_p PARAMS ((rtx, int)); | |
282 | static int contains_replace_regs PARAMS ((rtx)); | |
3fe41456 KG |
283 | static int memref_referenced_p PARAMS ((rtx, rtx)); |
284 | static int memref_used_between_p PARAMS ((rtx, rtx, rtx)); | |
285 | static void update_equiv_regs PARAMS ((void)); | |
286 | static void no_equiv PARAMS ((rtx, rtx, void *)); | |
287 | static void block_alloc PARAMS ((int)); | |
288 | static int qty_sugg_compare PARAMS ((int, int)); | |
289 | static int qty_sugg_compare_1 PARAMS ((const PTR, const PTR)); | |
290 | static int qty_compare PARAMS ((int, int)); | |
291 | static int qty_compare_1 PARAMS ((const PTR, const PTR)); | |
292 | static int combine_regs PARAMS ((rtx, rtx, int, int, rtx, int)); | |
293 | static int reg_meets_class_p PARAMS ((int, enum reg_class)); | |
294 | static void update_qty_class PARAMS ((int, int)); | |
295 | static void reg_is_set PARAMS ((rtx, rtx, void *)); | |
296 | static void reg_is_born PARAMS ((rtx, int)); | |
297 | static void wipe_dead_reg PARAMS ((rtx, int)); | |
298 | static int find_free_reg PARAMS ((enum reg_class, enum machine_mode, | |
82c68a78 | 299 | int, int, int, int, int)); |
3fe41456 KG |
300 | static void mark_life PARAMS ((int, enum machine_mode, int)); |
301 | static void post_mark_life PARAMS ((int, enum machine_mode, int, int, int)); | |
302 | static int no_conflict_p PARAMS ((rtx, rtx, rtx)); | |
303 | static int requires_inout PARAMS ((const char *)); | |
2bbd3819 RS |
304 | \f |
305 | /* Allocate a new quantity (new within current basic block) | |
306 | for register number REGNO which is born at index BIRTH | |
307 | within the block. MODE and SIZE are info on reg REGNO. */ | |
308 | ||
309 | static void | |
310 | alloc_qty (regno, mode, size, birth) | |
311 | int regno; | |
312 | enum machine_mode mode; | |
313 | int size, birth; | |
314 | { | |
a1ed7bdb | 315 | register int qtyno = next_qty++; |
2bbd3819 | 316 | |
a1ed7bdb | 317 | reg_qty[regno] = qtyno; |
2bbd3819 RS |
318 | reg_offset[regno] = 0; |
319 | reg_next_in_qty[regno] = -1; | |
320 | ||
a1ed7bdb JH |
321 | qty[qtyno].first_reg = regno; |
322 | qty[qtyno].size = size; | |
323 | qty[qtyno].mode = mode; | |
324 | qty[qtyno].birth = birth; | |
325 | qty[qtyno].n_calls_crossed = REG_N_CALLS_CROSSED (regno); | |
326 | qty[qtyno].min_class = reg_preferred_class (regno); | |
327 | qty[qtyno].alternate_class = reg_alternate_class (regno); | |
328 | qty[qtyno].n_refs = REG_N_REFS (regno); | |
b2aec5c0 | 329 | qty[qtyno].freq = REG_FREQ (regno); |
02188693 | 330 | qty[qtyno].changes_mode = REG_CHANGES_MODE (regno); |
2bbd3819 RS |
331 | } |
332 | \f | |
2bbd3819 RS |
333 | /* Main entry point of this file. */ |
334 | ||
3f1b9b1b | 335 | int |
2bbd3819 RS |
336 | local_alloc () |
337 | { | |
338 | register int b, i; | |
339 | int max_qty; | |
340 | ||
3f1b9b1b JL |
341 | /* We need to keep track of whether or not we recorded a LABEL_REF so |
342 | that we know if the jump optimizer needs to be rerun. */ | |
343 | recorded_label_ref = 0; | |
344 | ||
2bbd3819 RS |
345 | /* Leaf functions and non-leaf functions have different needs. |
346 | If defined, let the machine say what kind of ordering we | |
347 | should use. */ | |
348 | #ifdef ORDER_REGS_FOR_LOCAL_ALLOC | |
349 | ORDER_REGS_FOR_LOCAL_ALLOC; | |
350 | #endif | |
351 | ||
352 | /* Promote REG_EQUAL notes to REG_EQUIV notes and adjust status of affected | |
353 | registers. */ | |
354 | update_equiv_regs (); | |
355 | ||
356 | /* This sets the maximum number of quantities we can have. Quantity | |
34f89b5f BS |
357 | numbers start at zero and we can have one for each pseudo. */ |
358 | max_qty = (max_regno - FIRST_PSEUDO_REGISTER); | |
2bbd3819 RS |
359 | |
360 | /* Allocate vectors of temporary data. | |
361 | See the declarations of these variables, above, | |
362 | for what they mean. */ | |
363 | ||
a1ed7bdb | 364 | qty = (struct qty *) xmalloc (max_qty * sizeof (struct qty)); |
4c9a05bc | 365 | qty_phys_copy_sugg |
75c6bd46 RH |
366 | = (HARD_REG_SET *) xmalloc (max_qty * sizeof (HARD_REG_SET)); |
367 | qty_phys_num_copy_sugg = (short *) xmalloc (max_qty * sizeof (short)); | |
368 | qty_phys_sugg = (HARD_REG_SET *) xmalloc (max_qty * sizeof (HARD_REG_SET)); | |
369 | qty_phys_num_sugg = (short *) xmalloc (max_qty * sizeof (short)); | |
2bbd3819 | 370 | |
83cbe7e4 RH |
371 | reg_qty = (int *) xmalloc (max_regno * sizeof (int)); |
372 | reg_offset = (char *) xmalloc (max_regno * sizeof (char)); | |
64e3a413 | 373 | reg_next_in_qty = (int *) xmalloc (max_regno * sizeof (int)); |
2bbd3819 | 374 | |
64e3a413 | 375 | /* Allocate the reg_renumber array. */ |
39379e67 | 376 | allocate_reg_info (max_regno, FALSE, TRUE); |
2bbd3819 RS |
377 | |
378 | /* Determine which pseudo-registers can be allocated by local-alloc. | |
379 | In general, these are the registers used only in a single block and | |
611bbf2a | 380 | which only die once. |
2bbd3819 RS |
381 | |
382 | We need not be concerned with which block actually uses the register | |
383 | since we will never see it outside that block. */ | |
384 | ||
385 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
386 | { | |
611bbf2a | 387 | if (REG_BASIC_BLOCK (i) >= 0 && REG_N_DEATHS (i) == 1) |
2bbd3819 RS |
388 | reg_qty[i] = -2; |
389 | else | |
390 | reg_qty[i] = -1; | |
391 | } | |
392 | ||
393 | /* Force loop below to initialize entire quantity array. */ | |
394 | next_qty = max_qty; | |
395 | ||
396 | /* Allocate each block's local registers, block by block. */ | |
397 | ||
398 | for (b = 0; b < n_basic_blocks; b++) | |
399 | { | |
400 | /* NEXT_QTY indicates which elements of the `qty_...' | |
401 | vectors might need to be initialized because they were used | |
402 | for the previous block; it is set to the entire array before | |
403 | block 0. Initialize those, with explicit loop if there are few, | |
404 | else with bzero and bcopy. Do not initialize vectors that are | |
405 | explicit set by `alloc_qty'. */ | |
406 | ||
407 | if (next_qty < 6) | |
408 | { | |
409 | for (i = 0; i < next_qty; i++) | |
410 | { | |
2bbd3819 | 411 | CLEAR_HARD_REG_SET (qty_phys_copy_sugg[i]); |
51b86d8b | 412 | qty_phys_num_copy_sugg[i] = 0; |
2bbd3819 | 413 | CLEAR_HARD_REG_SET (qty_phys_sugg[i]); |
51b86d8b | 414 | qty_phys_num_sugg[i] = 0; |
2bbd3819 RS |
415 | } |
416 | } | |
417 | else | |
418 | { | |
419 | #define CLEAR(vector) \ | |
961192e1 | 420 | memset ((char *) (vector), 0, (sizeof (*(vector))) * next_qty); |
2bbd3819 | 421 | |
2bbd3819 | 422 | CLEAR (qty_phys_copy_sugg); |
51b86d8b | 423 | CLEAR (qty_phys_num_copy_sugg); |
2bbd3819 | 424 | CLEAR (qty_phys_sugg); |
51b86d8b | 425 | CLEAR (qty_phys_num_sugg); |
2bbd3819 RS |
426 | } |
427 | ||
428 | next_qty = 0; | |
429 | ||
430 | block_alloc (b); | |
2bbd3819 | 431 | } |
83cbe7e4 | 432 | |
a1ed7bdb | 433 | free (qty); |
75c6bd46 RH |
434 | free (qty_phys_copy_sugg); |
435 | free (qty_phys_num_copy_sugg); | |
436 | free (qty_phys_sugg); | |
e7749837 | 437 | free (qty_phys_num_sugg); |
75c6bd46 | 438 | |
83cbe7e4 RH |
439 | free (reg_qty); |
440 | free (reg_offset); | |
441 | free (reg_next_in_qty); | |
75c6bd46 | 442 | |
3f1b9b1b | 443 | return recorded_label_ref; |
2bbd3819 RS |
444 | } |
445 | \f | |
2bbd3819 RS |
446 | /* Used for communication between the following two functions: contains |
447 | a MEM that we wish to ensure remains unchanged. */ | |
448 | static rtx equiv_mem; | |
449 | ||
450 | /* Set nonzero if EQUIV_MEM is modified. */ | |
451 | static int equiv_mem_modified; | |
452 | ||
453 | /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified. | |
454 | Called via note_stores. */ | |
455 | ||
456 | static void | |
84832317 | 457 | validate_equiv_mem_from_store (dest, set, data) |
2bbd3819 | 458 | rtx dest; |
e51712db | 459 | rtx set ATTRIBUTE_UNUSED; |
84832317 | 460 | void *data ATTRIBUTE_UNUSED; |
2bbd3819 RS |
461 | { |
462 | if ((GET_CODE (dest) == REG | |
463 | && reg_overlap_mentioned_p (dest, equiv_mem)) | |
464 | || (GET_CODE (dest) == MEM | |
9ae8ffe7 | 465 | && true_dependence (dest, VOIDmode, equiv_mem, rtx_varies_p))) |
2bbd3819 RS |
466 | equiv_mem_modified = 1; |
467 | } | |
468 | ||
469 | /* Verify that no store between START and the death of REG invalidates | |
470 | MEMREF. MEMREF is invalidated by modifying a register used in MEMREF, | |
471 | by storing into an overlapping memory location, or with a non-const | |
472 | CALL_INSN. | |
473 | ||
474 | Return 1 if MEMREF remains valid. */ | |
475 | ||
476 | static int | |
477 | validate_equiv_mem (start, reg, memref) | |
478 | rtx start; | |
479 | rtx reg; | |
480 | rtx memref; | |
481 | { | |
482 | rtx insn; | |
483 | rtx note; | |
484 | ||
485 | equiv_mem = memref; | |
486 | equiv_mem_modified = 0; | |
487 | ||
488 | /* If the memory reference has side effects or is volatile, it isn't a | |
489 | valid equivalence. */ | |
490 | if (side_effects_p (memref)) | |
491 | return 0; | |
492 | ||
493 | for (insn = start; insn && ! equiv_mem_modified; insn = NEXT_INSN (insn)) | |
494 | { | |
2c3c49de | 495 | if (! INSN_P (insn)) |
2bbd3819 RS |
496 | continue; |
497 | ||
498 | if (find_reg_note (insn, REG_DEAD, reg)) | |
499 | return 1; | |
500 | ||
501 | if (GET_CODE (insn) == CALL_INSN && ! RTX_UNCHANGING_P (memref) | |
24a28584 | 502 | && ! CONST_OR_PURE_CALL_P (insn)) |
2bbd3819 RS |
503 | return 0; |
504 | ||
84832317 | 505 | note_stores (PATTERN (insn), validate_equiv_mem_from_store, NULL); |
2bbd3819 RS |
506 | |
507 | /* If a register mentioned in MEMREF is modified via an | |
508 | auto-increment, we lose the equivalence. Do the same if one | |
509 | dies; although we could extend the life, it doesn't seem worth | |
510 | the trouble. */ | |
511 | ||
512 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
513 | if ((REG_NOTE_KIND (note) == REG_INC | |
514 | || REG_NOTE_KIND (note) == REG_DEAD) | |
515 | && GET_CODE (XEXP (note, 0)) == REG | |
516 | && reg_overlap_mentioned_p (XEXP (note, 0), memref)) | |
517 | return 0; | |
518 | } | |
519 | ||
520 | return 0; | |
521 | } | |
a1729519 | 522 | |
bf6d9fd7 JW |
523 | /* Returns zero if X is known to be invariant. */ |
524 | ||
525 | static int | |
526 | equiv_init_varies_p (x) | |
527 | rtx x; | |
528 | { | |
529 | register RTX_CODE code = GET_CODE (x); | |
530 | register int i; | |
531 | register const char *fmt; | |
532 | ||
533 | switch (code) | |
534 | { | |
535 | case MEM: | |
536 | return ! RTX_UNCHANGING_P (x) || equiv_init_varies_p (XEXP (x, 0)); | |
537 | ||
538 | case QUEUED: | |
539 | return 1; | |
540 | ||
541 | case CONST: | |
542 | case CONST_INT: | |
543 | case CONST_DOUBLE: | |
544 | case SYMBOL_REF: | |
545 | case LABEL_REF: | |
546 | return 0; | |
547 | ||
548 | case REG: | |
e38fe8e0 | 549 | return reg_equiv[REGNO (x)].replace == 0 && rtx_varies_p (x, 0); |
bf6d9fd7 JW |
550 | |
551 | case ASM_OPERANDS: | |
552 | if (MEM_VOLATILE_P (x)) | |
553 | return 1; | |
554 | ||
555 | /* FALLTHROUGH */ | |
556 | ||
557 | default: | |
558 | break; | |
559 | } | |
560 | ||
561 | fmt = GET_RTX_FORMAT (code); | |
562 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
563 | if (fmt[i] == 'e') | |
564 | { | |
565 | if (equiv_init_varies_p (XEXP (x, i))) | |
566 | return 1; | |
567 | } | |
568 | else if (fmt[i] == 'E') | |
569 | { | |
570 | int j; | |
571 | for (j = 0; j < XVECLEN (x, i); j++) | |
572 | if (equiv_init_varies_p (XVECEXP (x, i, j))) | |
573 | return 1; | |
574 | } | |
575 | ||
576 | return 0; | |
577 | } | |
578 | ||
579 | /* Returns non-zero if X (used to initialize register REGNO) is movable. | |
580 | X is only movable if the registers it uses have equivalent initializations | |
581 | which appear to be within the same loop (or in an inner loop) and movable | |
582 | or if they are not candidates for local_alloc and don't vary. */ | |
a1729519 JW |
583 | |
584 | static int | |
bf6d9fd7 JW |
585 | equiv_init_movable_p (x, regno) |
586 | rtx x; | |
587 | int regno; | |
588 | { | |
589 | int i, j; | |
590 | const char *fmt; | |
591 | enum rtx_code code = GET_CODE (x); | |
592 | ||
593 | switch (code) | |
594 | { | |
595 | case SET: | |
596 | return equiv_init_movable_p (SET_SRC (x), regno); | |
597 | ||
d9068c61 | 598 | case CC0: |
bf6d9fd7 JW |
599 | case CLOBBER: |
600 | return 0; | |
601 | ||
602 | case PRE_INC: | |
603 | case PRE_DEC: | |
604 | case POST_INC: | |
605 | case POST_DEC: | |
606 | case PRE_MODIFY: | |
607 | case POST_MODIFY: | |
608 | return 0; | |
609 | ||
610 | case REG: | |
611 | return (reg_equiv[REGNO (x)].loop_depth >= reg_equiv[regno].loop_depth | |
612 | && reg_equiv[REGNO (x)].replace) | |
e38fe8e0 | 613 | || (REG_BASIC_BLOCK (REGNO (x)) < 0 && ! rtx_varies_p (x, 0)); |
bf6d9fd7 JW |
614 | |
615 | case UNSPEC_VOLATILE: | |
616 | return 0; | |
617 | ||
618 | case ASM_OPERANDS: | |
619 | if (MEM_VOLATILE_P (x)) | |
620 | return 0; | |
621 | ||
622 | /* FALLTHROUGH */ | |
623 | ||
624 | default: | |
625 | break; | |
626 | } | |
627 | ||
628 | fmt = GET_RTX_FORMAT (code); | |
629 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
630 | switch (fmt[i]) | |
631 | { | |
632 | case 'e': | |
633 | if (! equiv_init_movable_p (XEXP (x, i), regno)) | |
634 | return 0; | |
635 | break; | |
636 | case 'E': | |
637 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
638 | if (! equiv_init_movable_p (XVECEXP (x, i, j), regno)) | |
639 | return 0; | |
640 | break; | |
641 | } | |
642 | ||
643 | return 1; | |
644 | } | |
645 | ||
646 | /* TRUE if X uses any registers for which reg_equiv[REGNO].replace is true. */ | |
647 | ||
648 | static int | |
649 | contains_replace_regs (x) | |
a1729519 | 650 | rtx x; |
a1729519 JW |
651 | { |
652 | int i, j; | |
6f7d635c | 653 | const char *fmt; |
a1729519 JW |
654 | enum rtx_code code = GET_CODE (x); |
655 | ||
656 | switch (code) | |
657 | { | |
658 | case CONST_INT: | |
659 | case CONST: | |
660 | case LABEL_REF: | |
661 | case SYMBOL_REF: | |
662 | case CONST_DOUBLE: | |
663 | case PC: | |
664 | case CC0: | |
665 | case HIGH: | |
666 | case LO_SUM: | |
667 | return 0; | |
668 | ||
669 | case REG: | |
bf6d9fd7 | 670 | return reg_equiv[REGNO (x)].replace; |
1d300e19 KG |
671 | |
672 | default: | |
673 | break; | |
a1729519 JW |
674 | } |
675 | ||
676 | fmt = GET_RTX_FORMAT (code); | |
677 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
678 | switch (fmt[i]) | |
679 | { | |
680 | case 'e': | |
bf6d9fd7 | 681 | if (contains_replace_regs (XEXP (x, i))) |
a1729519 JW |
682 | return 1; |
683 | break; | |
684 | case 'E': | |
685 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
bf6d9fd7 | 686 | if (contains_replace_regs (XVECEXP (x, i, j))) |
a1729519 JW |
687 | return 1; |
688 | break; | |
689 | } | |
690 | ||
691 | return 0; | |
692 | } | |
2bbd3819 RS |
693 | \f |
694 | /* TRUE if X references a memory location that would be affected by a store | |
695 | to MEMREF. */ | |
696 | ||
697 | static int | |
698 | memref_referenced_p (memref, x) | |
699 | rtx x; | |
700 | rtx memref; | |
701 | { | |
702 | int i, j; | |
6f7d635c | 703 | const char *fmt; |
2bbd3819 RS |
704 | enum rtx_code code = GET_CODE (x); |
705 | ||
706 | switch (code) | |
707 | { | |
2bbd3819 RS |
708 | case CONST_INT: |
709 | case CONST: | |
710 | case LABEL_REF: | |
711 | case SYMBOL_REF: | |
712 | case CONST_DOUBLE: | |
713 | case PC: | |
714 | case CC0: | |
715 | case HIGH: | |
716 | case LO_SUM: | |
717 | return 0; | |
718 | ||
c25a4c25 | 719 | case REG: |
bf6d9fd7 | 720 | return (reg_equiv[REGNO (x)].replacement |
3298a1b1 | 721 | && memref_referenced_p (memref, |
bf6d9fd7 | 722 | reg_equiv[REGNO (x)].replacement)); |
c25a4c25 | 723 | |
2bbd3819 | 724 | case MEM: |
9ae8ffe7 | 725 | if (true_dependence (memref, VOIDmode, x, rtx_varies_p)) |
2bbd3819 RS |
726 | return 1; |
727 | break; | |
728 | ||
729 | case SET: | |
730 | /* If we are setting a MEM, it doesn't count (its address does), but any | |
731 | other SET_DEST that has a MEM in it is referencing the MEM. */ | |
732 | if (GET_CODE (SET_DEST (x)) == MEM) | |
733 | { | |
734 | if (memref_referenced_p (memref, XEXP (SET_DEST (x), 0))) | |
735 | return 1; | |
736 | } | |
737 | else if (memref_referenced_p (memref, SET_DEST (x))) | |
738 | return 1; | |
739 | ||
740 | return memref_referenced_p (memref, SET_SRC (x)); | |
64e3a413 | 741 | |
e9a25f70 JL |
742 | default: |
743 | break; | |
2bbd3819 RS |
744 | } |
745 | ||
746 | fmt = GET_RTX_FORMAT (code); | |
747 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
748 | switch (fmt[i]) | |
749 | { | |
750 | case 'e': | |
751 | if (memref_referenced_p (memref, XEXP (x, i))) | |
752 | return 1; | |
753 | break; | |
754 | case 'E': | |
755 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
756 | if (memref_referenced_p (memref, XVECEXP (x, i, j))) | |
757 | return 1; | |
758 | break; | |
759 | } | |
760 | ||
761 | return 0; | |
762 | } | |
763 | ||
764 | /* TRUE if some insn in the range (START, END] references a memory location | |
765 | that would be affected by a store to MEMREF. */ | |
766 | ||
767 | static int | |
768 | memref_used_between_p (memref, start, end) | |
769 | rtx memref; | |
770 | rtx start; | |
771 | rtx end; | |
772 | { | |
773 | rtx insn; | |
774 | ||
775 | for (insn = NEXT_INSN (start); insn != NEXT_INSN (end); | |
776 | insn = NEXT_INSN (insn)) | |
2c3c49de | 777 | if (INSN_P (insn) && memref_referenced_p (memref, PATTERN (insn))) |
2bbd3819 RS |
778 | return 1; |
779 | ||
780 | return 0; | |
781 | } | |
782 | \f | |
2b49ee39 R |
783 | /* Return nonzero if the rtx X is invariant over the current function. */ |
784 | int | |
785 | function_invariant_p (x) | |
786 | rtx x; | |
787 | { | |
788 | if (CONSTANT_P (x)) | |
789 | return 1; | |
790 | if (x == frame_pointer_rtx || x == arg_pointer_rtx) | |
791 | return 1; | |
792 | if (GET_CODE (x) == PLUS | |
793 | && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx) | |
794 | && CONSTANT_P (XEXP (x, 1))) | |
795 | return 1; | |
796 | return 0; | |
797 | } | |
798 | ||
2bbd3819 RS |
799 | /* Find registers that are equivalent to a single value throughout the |
800 | compilation (either because they can be referenced in memory or are set once | |
801 | from a single constant). Lower their priority for a register. | |
802 | ||
803 | If such a register is only referenced once, try substituting its value | |
804 | into the using insn. If it succeeds, we can eliminate the register | |
805 | completely. */ | |
806 | ||
807 | static void | |
808 | update_equiv_regs () | |
809 | { | |
2bbd3819 | 810 | rtx insn; |
bf6d9fd7 JW |
811 | int block; |
812 | int loop_depth; | |
25e4379f MM |
813 | regset_head cleared_regs; |
814 | int clear_regnos = 0; | |
2bbd3819 | 815 | |
bf6d9fd7 | 816 | reg_equiv = (struct equivalence *) xcalloc (max_regno, sizeof *reg_equiv); |
25e4379f | 817 | INIT_REG_SET (&cleared_regs); |
2bbd3819 RS |
818 | |
819 | init_alias_analysis (); | |
820 | ||
2bbd3819 RS |
821 | /* Scan the insns and find which registers have equivalences. Do this |
822 | in a separate scan of the insns because (due to -fcse-follow-jumps) | |
823 | a register can be set below its use. */ | |
bf6d9fd7 | 824 | loop_depth = 0; |
2bbd3819 RS |
825 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
826 | { | |
827 | rtx note; | |
135eb61c | 828 | rtx set; |
49ddab16 | 829 | rtx dest, src; |
2bbd3819 RS |
830 | int regno; |
831 | ||
832 | if (GET_CODE (insn) == NOTE) | |
833 | { | |
834 | if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG) | |
bf6d9fd7 | 835 | ++loop_depth; |
2bbd3819 | 836 | else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END) |
bf6d9fd7 JW |
837 | { |
838 | if (! loop_depth) | |
839 | abort (); | |
840 | --loop_depth; | |
841 | } | |
2bbd3819 RS |
842 | } |
843 | ||
2c3c49de | 844 | if (! INSN_P (insn)) |
2bbd3819 RS |
845 | continue; |
846 | ||
135eb61c R |
847 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) |
848 | if (REG_NOTE_KIND (note) == REG_INC) | |
84832317 | 849 | no_equiv (XEXP (note, 0), note, NULL); |
135eb61c R |
850 | |
851 | set = single_set (insn); | |
852 | ||
853 | /* If this insn contains more (or less) than a single SET, | |
854 | only mark all destinations as having no known equivalence. */ | |
855 | if (set == 0) | |
856 | { | |
84832317 | 857 | note_stores (PATTERN (insn), no_equiv, NULL); |
135eb61c R |
858 | continue; |
859 | } | |
860 | else if (GET_CODE (PATTERN (insn)) == PARALLEL) | |
861 | { | |
862 | int i; | |
863 | ||
864 | for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--) | |
865 | { | |
866 | rtx part = XVECEXP (PATTERN (insn), 0, i); | |
867 | if (part != set) | |
84832317 | 868 | note_stores (part, no_equiv, NULL); |
135eb61c R |
869 | } |
870 | } | |
871 | ||
2bbd3819 | 872 | dest = SET_DEST (set); |
49ddab16 | 873 | src = SET_SRC (set); |
2bbd3819 RS |
874 | |
875 | /* If this sets a MEM to the contents of a REG that is only used | |
876 | in a single basic block, see if the register is always equivalent | |
877 | to that memory location and if moving the store from INSN to the | |
878 | insn that set REG is safe. If so, put a REG_EQUIV note on the | |
a1729519 JW |
879 | initializing insn. |
880 | ||
881 | Don't add a REG_EQUIV note if the insn already has one. The existing | |
882 | REG_EQUIV is likely more useful than the one we are adding. | |
883 | ||
bf6d9fd7 JW |
884 | If one of the regs in the address has reg_equiv[REGNO].replace set, |
885 | then we can't add this REG_EQUIV note. The reg_equiv[REGNO].replace | |
a1729519 | 886 | optimization may move the set of this register immediately before |
bf6d9fd7 | 887 | insn, which puts it after reg_equiv[REGNO].init_insns, and hence |
a1729519 JW |
888 | the mention in the REG_EQUIV note would be to an uninitialized |
889 | pseudo. */ | |
135eb61c R |
890 | /* ????? This test isn't good enough; we might see a MEM with a use of |
891 | a pseudo register before we see its setting insn that will cause | |
bf6d9fd7 | 892 | reg_equiv[].replace for that pseudo to be set. |
135eb61c | 893 | Equivalences to MEMs should be made in another pass, after the |
bf6d9fd7 | 894 | reg_equiv[].replace information has been gathered. */ |
135eb61c R |
895 | |
896 | if (GET_CODE (dest) == MEM && GET_CODE (src) == REG | |
897 | && (regno = REGNO (src)) >= FIRST_PSEUDO_REGISTER | |
b1f21e0a | 898 | && REG_BASIC_BLOCK (regno) >= 0 |
135eb61c | 899 | && REG_N_SETS (regno) == 1 |
bf6d9fd7 JW |
900 | && reg_equiv[regno].init_insns != 0 |
901 | && reg_equiv[regno].init_insns != const0_rtx | |
902 | && ! find_reg_note (XEXP (reg_equiv[regno].init_insns, 0), | |
b768aa38 | 903 | REG_EQUIV, NULL_RTX) |
bf6d9fd7 | 904 | && ! contains_replace_regs (XEXP (dest, 0))) |
135eb61c | 905 | { |
bf6d9fd7 | 906 | rtx init_insn = XEXP (reg_equiv[regno].init_insns, 0); |
135eb61c R |
907 | if (validate_equiv_mem (init_insn, src, dest) |
908 | && ! memref_used_between_p (dest, init_insn, insn)) | |
909 | REG_NOTES (init_insn) | |
910 | = gen_rtx_EXPR_LIST (REG_EQUIV, dest, REG_NOTES (init_insn)); | |
911 | } | |
2bbd3819 | 912 | |
1230327b | 913 | /* We only handle the case of a pseudo register being set |
135eb61c R |
914 | once, or always to the same value. */ |
915 | /* ??? The mn10200 port breaks if we add equivalences for | |
916 | values that need an ADDRESS_REGS register and set them equivalent | |
917 | to a MEM of a pseudo. The actual problem is in the over-conservative | |
918 | handling of INPADDR_ADDRESS / INPUT_ADDRESS / INPUT triples in | |
919 | calculate_needs, but we traditionally work around this problem | |
920 | here by rejecting equivalences when the destination is in a register | |
921 | that's likely spilled. This is fragile, of course, since the | |
8585f8f1 | 922 | preferred class of a pseudo depends on all instructions that set |
135eb61c R |
923 | or use it. */ |
924 | ||
2bbd3819 RS |
925 | if (GET_CODE (dest) != REG |
926 | || (regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER | |
bf6d9fd7 | 927 | || reg_equiv[regno].init_insns == const0_rtx |
135eb61c R |
928 | || (CLASS_LIKELY_SPILLED_P (reg_preferred_class (regno)) |
929 | && GET_CODE (src) == MEM)) | |
930 | { | |
931 | /* This might be seting a SUBREG of a pseudo, a pseudo that is | |
932 | also set somewhere else to a constant. */ | |
84832317 | 933 | note_stores (set, no_equiv, NULL); |
135eb61c R |
934 | continue; |
935 | } | |
2bbd3819 | 936 | |
b1ec3c92 | 937 | note = find_reg_note (insn, REG_EQUAL, NULL_RTX); |
2bbd3819 | 938 | |
2f93c5c3 BS |
939 | /* cse sometimes generates function invariants, but doesn't put a |
940 | REG_EQUAL note on the insn. Since this note would be redundant, | |
941 | there's no point creating it earlier than here. */ | |
e38fe8e0 | 942 | if (! note && ! rtx_varies_p (src, 0)) |
2f93c5c3 BS |
943 | REG_NOTES (insn) |
944 | = note = gen_rtx_EXPR_LIST (REG_EQUAL, src, REG_NOTES (insn)); | |
945 | ||
bf6d9fd7 JW |
946 | /* Don't bother considering a REG_EQUAL note containing an EXPR_LIST |
947 | since it represents a function call */ | |
948 | if (note && GET_CODE (XEXP (note, 0)) == EXPR_LIST) | |
949 | note = NULL_RTX; | |
950 | ||
135eb61c R |
951 | if (REG_N_SETS (regno) != 1 |
952 | && (! note | |
e38fe8e0 | 953 | || rtx_varies_p (XEXP (note, 0), 0) |
bf6d9fd7 | 954 | || (reg_equiv[regno].replacement |
135eb61c | 955 | && ! rtx_equal_p (XEXP (note, 0), |
bf6d9fd7 | 956 | reg_equiv[regno].replacement)))) |
135eb61c | 957 | { |
84832317 | 958 | no_equiv (dest, set, NULL); |
135eb61c R |
959 | continue; |
960 | } | |
2bbd3819 | 961 | /* Record this insn as initializing this register. */ |
bf6d9fd7 JW |
962 | reg_equiv[regno].init_insns |
963 | = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv[regno].init_insns); | |
2bbd3819 RS |
964 | |
965 | /* If this register is known to be equal to a constant, record that | |
966 | it is always equivalent to the constant. */ | |
e38fe8e0 | 967 | if (note && ! rtx_varies_p (XEXP (note, 0), 0)) |
2bbd3819 RS |
968 | PUT_MODE (note, (enum machine_mode) REG_EQUIV); |
969 | ||
970 | /* If this insn introduces a "constant" register, decrease the priority | |
971 | of that register. Record this insn if the register is only used once | |
972 | more and the equivalence value is the same as our source. | |
973 | ||
974 | The latter condition is checked for two reasons: First, it is an | |
975 | indication that it may be more efficient to actually emit the insn | |
976 | as written (if no registers are available, reload will substitute | |
977 | the equivalence). Secondly, it avoids problems with any registers | |
978 | dying in this insn whose death notes would be missed. | |
979 | ||
980 | If we don't have a REG_EQUIV note, see if this insn is loading | |
981 | a register used only in one basic block from a MEM. If so, and the | |
982 | MEM remains unchanged for the life of the register, add a REG_EQUIV | |
983 | note. */ | |
64e3a413 | 984 | |
b1ec3c92 | 985 | note = find_reg_note (insn, REG_EQUIV, NULL_RTX); |
2bbd3819 | 986 | |
b1f21e0a | 987 | if (note == 0 && REG_BASIC_BLOCK (regno) >= 0 |
2bbd3819 RS |
988 | && GET_CODE (SET_SRC (set)) == MEM |
989 | && validate_equiv_mem (insn, dest, SET_SRC (set))) | |
38a448ca RH |
990 | REG_NOTES (insn) = note = gen_rtx_EXPR_LIST (REG_EQUIV, SET_SRC (set), |
991 | REG_NOTES (insn)); | |
2bbd3819 | 992 | |
68342d36 | 993 | if (note) |
2bbd3819 RS |
994 | { |
995 | int regno = REGNO (dest); | |
996 | ||
3f1b9b1b JL |
997 | /* Record whether or not we created a REG_EQUIV note for a LABEL_REF. |
998 | We might end up substituting the LABEL_REF for uses of the | |
999 | pseudo here or later. That kind of transformation may turn an | |
1000 | indirect jump into a direct jump, in which case we must rerun the | |
1001 | jump optimizer to ensure that the JUMP_LABEL fields are valid. */ | |
1002 | if (GET_CODE (XEXP (note, 0)) == LABEL_REF | |
1003 | || (GET_CODE (XEXP (note, 0)) == CONST | |
1004 | && GET_CODE (XEXP (XEXP (note, 0), 0)) == PLUS | |
1005 | && (GET_CODE (XEXP (XEXP (XEXP (note, 0), 0), 0)) | |
1006 | == LABEL_REF))) | |
1007 | recorded_label_ref = 1; | |
64e3a413 | 1008 | |
bf6d9fd7 JW |
1009 | reg_equiv[regno].replacement = XEXP (note, 0); |
1010 | reg_equiv[regno].src = src; | |
1011 | reg_equiv[regno].loop_depth = loop_depth; | |
68342d36 RK |
1012 | |
1013 | /* Don't mess with things live during setjmp. */ | |
49a18670 | 1014 | if (REG_LIVE_LENGTH (regno) >= 0 && optimize) |
68342d36 RK |
1015 | { |
1016 | /* Note that the statement below does not affect the priority | |
1017 | in local-alloc! */ | |
b1f21e0a | 1018 | REG_LIVE_LENGTH (regno) *= 2; |
2bbd3819 | 1019 | |
2bbd3819 | 1020 | |
68342d36 RK |
1021 | /* If the register is referenced exactly twice, meaning it is |
1022 | set once and used once, indicate that the reference may be | |
bf6d9fd7 JW |
1023 | replaced by the equivalence we computed above. Do this |
1024 | even if the register is only used in one block so that | |
1025 | dependencies can be handled where the last register is | |
1026 | used in a different block (i.e. HIGH / LO_SUM sequences) | |
1027 | and to reduce the number of registers alive across calls. | |
2bbd3819 | 1028 | |
68342d36 RK |
1029 | It would be nice to use "loop_depth * 2" in the compare |
1030 | below. Unfortunately, LOOP_DEPTH need not be constant within | |
1031 | a basic block so this would be too complicated. | |
2bbd3819 | 1032 | |
68342d36 RK |
1033 | This case normally occurs when a parameter is read from |
1034 | memory and then used exactly once, not in a loop. */ | |
1035 | ||
b1f21e0a | 1036 | if (REG_N_REFS (regno) == 2 |
bf6d9fd7 JW |
1037 | && (rtx_equal_p (XEXP (note, 0), src) |
1038 | || ! equiv_init_varies_p (src)) | |
1039 | && GET_CODE (insn) == INSN | |
1040 | && equiv_init_movable_p (PATTERN (insn), regno)) | |
1041 | reg_equiv[regno].replace = 1; | |
68342d36 | 1042 | } |
2bbd3819 RS |
1043 | } |
1044 | } | |
1045 | ||
2e1253f3 ILT |
1046 | /* Now scan all regs killed in an insn to see if any of them are |
1047 | registers only used that once. If so, see if we can replace the | |
1048 | reference with the equivalent from. If we can, delete the | |
1049 | initializing reference and this register will go away. If we | |
bf6d9fd7 JW |
1050 | can't replace the reference, and the initialzing reference is |
1051 | within the same loop (or in an inner loop), then move the register | |
1052 | initialization just before the use, so that they are in the same | |
1053 | basic block. | |
1054 | ||
1055 | Skip this optimization if loop_depth isn't initially zero since | |
1056 | that indicates a mismatch between loop begin and loop end notes | |
1057 | (i.e. gcc.dg/noncompile/920721-2.c). */ | |
1058 | block = n_basic_blocks - 1; | |
1059 | for (insn = (loop_depth == 0) ? get_last_insn () : NULL_RTX; | |
1060 | insn; insn = PREV_INSN (insn)) | |
2bbd3819 RS |
1061 | { |
1062 | rtx link; | |
1063 | ||
2c3c49de | 1064 | if (! INSN_P (insn)) |
2e1253f3 ILT |
1065 | { |
1066 | if (GET_CODE (insn) == NOTE) | |
1067 | { | |
bf6d9fd7 JW |
1068 | if (NOTE_INSN_BASIC_BLOCK_P (insn)) |
1069 | block = NOTE_BASIC_BLOCK (insn)->index - 1; | |
1070 | else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG) | |
2e1253f3 | 1071 | { |
bf6d9fd7 | 1072 | if (! loop_depth) |
2e1253f3 | 1073 | abort (); |
bf6d9fd7 | 1074 | --loop_depth; |
2e1253f3 | 1075 | } |
bf6d9fd7 JW |
1076 | else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END) |
1077 | ++loop_depth; | |
2e1253f3 ILT |
1078 | } |
1079 | ||
1080 | continue; | |
1081 | } | |
1082 | ||
2bbd3819 | 1083 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) |
2e1253f3 ILT |
1084 | { |
1085 | if (REG_NOTE_KIND (link) == REG_DEAD | |
1086 | /* Make sure this insn still refers to the register. */ | |
1087 | && reg_mentioned_p (XEXP (link, 0), PATTERN (insn))) | |
1088 | { | |
1089 | int regno = REGNO (XEXP (link, 0)); | |
1090 | rtx equiv_insn; | |
2bbd3819 | 1091 | |
bf6d9fd7 JW |
1092 | if (! reg_equiv[regno].replace |
1093 | || reg_equiv[regno].loop_depth < loop_depth) | |
2e1253f3 ILT |
1094 | continue; |
1095 | ||
bf6d9fd7 | 1096 | /* reg_equiv[REGNO].replace gets set only when |
135eb61c R |
1097 | REG_N_REFS[REGNO] is 2, i.e. the register is set |
1098 | once and used once. (If it were only set, but not used, | |
64e3a413 | 1099 | flow would have deleted the setting insns.) Hence |
bf6d9fd7 | 1100 | there can only be one insn in reg_equiv[REGNO].init_insns. */ |
96af667a GK |
1101 | if (reg_equiv[regno].init_insns == NULL_RTX |
1102 | || XEXP (reg_equiv[regno].init_insns, 1) != NULL_RTX) | |
1103 | abort (); | |
bf6d9fd7 | 1104 | equiv_insn = XEXP (reg_equiv[regno].init_insns, 0); |
2e1253f3 | 1105 | |
78d56e8b RH |
1106 | /* We may not move instructions that can throw, since |
1107 | that changes basic block boundaries and we are not | |
1108 | prepared to adjust the CFG to match. */ | |
1109 | if (can_throw_internal (equiv_insn)) | |
1110 | continue; | |
1111 | ||
bf6d9fd7 JW |
1112 | if (asm_noperands (PATTERN (equiv_insn)) < 0 |
1113 | && validate_replace_rtx (regno_reg_rtx[regno], | |
1114 | reg_equiv[regno].src, insn)) | |
2e1253f3 | 1115 | { |
bf6d9fd7 JW |
1116 | rtx equiv_link; |
1117 | rtx last_link; | |
1118 | rtx note; | |
1119 | ||
1120 | /* Find the last note. */ | |
1121 | for (last_link = link; XEXP (last_link, 1); | |
1122 | last_link = XEXP (last_link, 1)) | |
1123 | ; | |
1124 | ||
1125 | /* Append the REG_DEAD notes from equiv_insn. */ | |
1126 | equiv_link = REG_NOTES (equiv_insn); | |
1127 | while (equiv_link) | |
1128 | { | |
1129 | note = equiv_link; | |
1130 | equiv_link = XEXP (equiv_link, 1); | |
1131 | if (REG_NOTE_KIND (note) == REG_DEAD) | |
1132 | { | |
1133 | remove_note (equiv_insn, note); | |
1134 | XEXP (last_link, 1) = note; | |
1135 | XEXP (note, 1) = NULL_RTX; | |
1136 | last_link = note; | |
1137 | } | |
1138 | } | |
1139 | ||
2e1253f3 | 1140 | remove_death (regno, insn); |
b1f21e0a | 1141 | REG_N_REFS (regno) = 0; |
b2aec5c0 | 1142 | REG_FREQ (regno) = 0; |
2e1253f3 ILT |
1143 | PUT_CODE (equiv_insn, NOTE); |
1144 | NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED; | |
1145 | NOTE_SOURCE_FILE (equiv_insn) = 0; | |
96af667a | 1146 | |
c2fd66f4 RK |
1147 | reg_equiv[regno].init_insns |
1148 | = XEXP (reg_equiv[regno].init_insns, 1); | |
2e1253f3 | 1149 | } |
bf6d9fd7 JW |
1150 | /* Move the initialization of the register to just before |
1151 | INSN. Update the flow information. */ | |
1152 | else if (PREV_INSN (insn) != equiv_insn) | |
2e1253f3 | 1153 | { |
96af667a | 1154 | rtx new_insn; |
2e1253f3 | 1155 | |
c2fd66f4 | 1156 | new_insn = emit_insn_before (PATTERN (equiv_insn), insn); |
cad33336 | 1157 | REG_NOTES (new_insn) = REG_NOTES (equiv_insn); |
ef178af3 | 1158 | REG_NOTES (equiv_insn) = 0; |
2e1253f3 | 1159 | |
cad33336 RH |
1160 | /* Make sure this insn is recognized before reload begins, |
1161 | otherwise eliminate_regs_in_insn will abort. */ | |
1162 | INSN_CODE (new_insn) = INSN_CODE (equiv_insn); | |
1163 | ||
2e1253f3 ILT |
1164 | PUT_CODE (equiv_insn, NOTE); |
1165 | NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED; | |
1166 | NOTE_SOURCE_FILE (equiv_insn) = 0; | |
2e1253f3 | 1167 | |
96af667a GK |
1168 | XEXP (reg_equiv[regno].init_insns, 0) = new_insn; |
1169 | ||
bf6d9fd7 | 1170 | REG_BASIC_BLOCK (regno) = block >= 0 ? block : 0; |
b1f21e0a MM |
1171 | REG_N_CALLS_CROSSED (regno) = 0; |
1172 | REG_LIVE_LENGTH (regno) = 2; | |
2e1253f3 | 1173 | |
3b413743 RH |
1174 | if (block >= 0 && insn == BLOCK_HEAD (block)) |
1175 | BLOCK_HEAD (block) = PREV_INSN (insn); | |
2e1253f3 | 1176 | |
25e4379f MM |
1177 | /* Remember to clear REGNO from all basic block's live |
1178 | info. */ | |
1179 | SET_REGNO_REG_SET (&cleared_regs, regno); | |
1180 | clear_regnos++; | |
2e1253f3 ILT |
1181 | } |
1182 | } | |
1183 | } | |
2bbd3819 | 1184 | } |
e05e2395 | 1185 | |
25e4379f MM |
1186 | /* Clear all dead REGNOs from all basic block's live info. */ |
1187 | if (clear_regnos) | |
1188 | { | |
1189 | int j, l; | |
1190 | if (clear_regnos > 8) | |
1191 | { | |
1192 | for (l = 0; l < n_basic_blocks; l++) | |
1193 | { | |
1194 | AND_COMPL_REG_SET (BASIC_BLOCK (l)->global_live_at_start, | |
1195 | &cleared_regs); | |
1196 | AND_COMPL_REG_SET (BASIC_BLOCK (l)->global_live_at_end, | |
1197 | &cleared_regs); | |
1198 | } | |
1199 | } | |
1200 | else | |
1201 | EXECUTE_IF_SET_IN_REG_SET (&cleared_regs, 0, j, | |
1202 | { | |
1203 | for (l = 0; l < n_basic_blocks; l++) | |
1204 | { | |
1205 | CLEAR_REGNO_REG_SET (BASIC_BLOCK (l)->global_live_at_start, j); | |
1206 | CLEAR_REGNO_REG_SET (BASIC_BLOCK (l)->global_live_at_end, j); | |
1207 | } | |
1208 | }); | |
1209 | } | |
1210 | ||
e05e2395 MM |
1211 | /* Clean up. */ |
1212 | end_alias_analysis (); | |
25e4379f | 1213 | CLEAR_REG_SET (&cleared_regs); |
bf6d9fd7 | 1214 | free (reg_equiv); |
2bbd3819 | 1215 | } |
135eb61c R |
1216 | |
1217 | /* Mark REG as having no known equivalence. | |
1218 | Some instructions might have been proceessed before and furnished | |
1219 | with REG_EQUIV notes for this register; these notes will have to be | |
1220 | removed. | |
1221 | STORE is the piece of RTL that does the non-constant / conflicting | |
1222 | assignment - a SET, CLOBBER or REG_INC note. It is currently not used, | |
1223 | but needs to be there because this function is called from note_stores. */ | |
1224 | static void | |
84832317 | 1225 | no_equiv (reg, store, data) |
54ea1de9 | 1226 | rtx reg, store ATTRIBUTE_UNUSED; |
84832317 | 1227 | void *data ATTRIBUTE_UNUSED; |
135eb61c R |
1228 | { |
1229 | int regno; | |
1230 | rtx list; | |
1231 | ||
1232 | if (GET_CODE (reg) != REG) | |
1233 | return; | |
1234 | regno = REGNO (reg); | |
bf6d9fd7 | 1235 | list = reg_equiv[regno].init_insns; |
135eb61c R |
1236 | if (list == const0_rtx) |
1237 | return; | |
1238 | for (; list; list = XEXP (list, 1)) | |
1239 | { | |
1240 | rtx insn = XEXP (list, 0); | |
1241 | remove_note (insn, find_reg_note (insn, REG_EQUIV, NULL_RTX)); | |
1242 | } | |
bf6d9fd7 JW |
1243 | reg_equiv[regno].init_insns = const0_rtx; |
1244 | reg_equiv[regno].replacement = NULL_RTX; | |
135eb61c | 1245 | } |
2bbd3819 RS |
1246 | \f |
1247 | /* Allocate hard regs to the pseudo regs used only within block number B. | |
1248 | Only the pseudos that die but once can be handled. */ | |
1249 | ||
1250 | static void | |
1251 | block_alloc (b) | |
1252 | int b; | |
1253 | { | |
1254 | register int i, q; | |
1255 | register rtx insn; | |
1256 | rtx note; | |
1257 | int insn_number = 0; | |
1258 | int insn_count = 0; | |
1259 | int max_uid = get_max_uid (); | |
aabf56ce | 1260 | int *qty_order; |
2bbd3819 RS |
1261 | int no_conflict_combined_regno = -1; |
1262 | ||
1263 | /* Count the instructions in the basic block. */ | |
1264 | ||
3b413743 | 1265 | insn = BLOCK_END (b); |
2bbd3819 RS |
1266 | while (1) |
1267 | { | |
1268 | if (GET_CODE (insn) != NOTE) | |
1269 | if (++insn_count > max_uid) | |
1270 | abort (); | |
3b413743 | 1271 | if (insn == BLOCK_HEAD (b)) |
2bbd3819 RS |
1272 | break; |
1273 | insn = PREV_INSN (insn); | |
1274 | } | |
1275 | ||
1276 | /* +2 to leave room for a post_mark_life at the last insn and for | |
1277 | the birth of a CLOBBER in the first insn. */ | |
ff154f78 MM |
1278 | regs_live_at = (HARD_REG_SET *) xcalloc ((2 * insn_count + 2), |
1279 | sizeof (HARD_REG_SET)); | |
2bbd3819 RS |
1280 | |
1281 | /* Initialize table of hardware registers currently live. */ | |
1282 | ||
e881bb1b | 1283 | REG_SET_TO_HARD_REG_SET (regs_live, BASIC_BLOCK (b)->global_live_at_start); |
2bbd3819 RS |
1284 | |
1285 | /* This loop scans the instructions of the basic block | |
1286 | and assigns quantities to registers. | |
1287 | It computes which registers to tie. */ | |
1288 | ||
3b413743 | 1289 | insn = BLOCK_HEAD (b); |
2bbd3819 RS |
1290 | while (1) |
1291 | { | |
2bbd3819 RS |
1292 | if (GET_CODE (insn) != NOTE) |
1293 | insn_number++; | |
1294 | ||
2c3c49de | 1295 | if (INSN_P (insn)) |
2bbd3819 RS |
1296 | { |
1297 | register rtx link, set; | |
1298 | register int win = 0; | |
a544cfd2 | 1299 | register rtx r0, r1 = NULL_RTX; |
2bbd3819 RS |
1300 | int combined_regno = -1; |
1301 | int i; | |
2bbd3819 RS |
1302 | |
1303 | this_insn_number = insn_number; | |
1304 | this_insn = insn; | |
1305 | ||
0a578fee | 1306 | extract_insn (insn); |
2bbd3819 RS |
1307 | which_alternative = -1; |
1308 | ||
1309 | /* Is this insn suitable for tying two registers? | |
1310 | If so, try doing that. | |
1311 | Suitable insns are those with at least two operands and where | |
1312 | operand 0 is an output that is a register that is not | |
1313 | earlyclobber. | |
7aba0f0b RK |
1314 | |
1315 | We can tie operand 0 with some operand that dies in this insn. | |
1316 | First look for operands that are required to be in the same | |
1317 | register as operand 0. If we find such, only try tying that | |
1318 | operand or one that can be put into that operand if the | |
1319 | operation is commutative. If we don't find an operand | |
1320 | that is required to be in the same register as operand 0, | |
1321 | we can tie with any operand. | |
1322 | ||
2bbd3819 RS |
1323 | Subregs in place of regs are also ok. |
1324 | ||
1325 | If tying is done, WIN is set nonzero. */ | |
1326 | ||
d29c259b RH |
1327 | if (optimize |
1328 | && recog_data.n_operands > 1 | |
1ccbefce | 1329 | && recog_data.constraints[0][0] == '=' |
19af6455 | 1330 | && recog_data.constraints[0][1] != '&') |
2bbd3819 | 1331 | { |
3061cc54 | 1332 | /* If non-negative, is an operand that must match operand 0. */ |
7aba0f0b | 1333 | int must_match_0 = -1; |
3061cc54 RK |
1334 | /* Counts number of alternatives that require a match with |
1335 | operand 0. */ | |
1336 | int n_matching_alts = 0; | |
7aba0f0b | 1337 | |
1ccbefce | 1338 | for (i = 1; i < recog_data.n_operands; i++) |
3061cc54 | 1339 | { |
1ccbefce | 1340 | const char *p = recog_data.constraints[i]; |
3061cc54 RK |
1341 | int this_match = (requires_inout (p)); |
1342 | ||
1343 | n_matching_alts += this_match; | |
1ccbefce | 1344 | if (this_match == recog_data.n_alternatives) |
3061cc54 RK |
1345 | must_match_0 = i; |
1346 | } | |
2bbd3819 | 1347 | |
1ccbefce RH |
1348 | r0 = recog_data.operand[0]; |
1349 | for (i = 1; i < recog_data.n_operands; i++) | |
2bbd3819 | 1350 | { |
7aba0f0b RK |
1351 | /* Skip this operand if we found an operand that |
1352 | must match operand 0 and this operand isn't it | |
1353 | and can't be made to be it by commutativity. */ | |
1354 | ||
1355 | if (must_match_0 >= 0 && i != must_match_0 | |
1356 | && ! (i == must_match_0 + 1 | |
1ccbefce | 1357 | && recog_data.constraints[i-1][0] == '%') |
7aba0f0b | 1358 | && ! (i == must_match_0 - 1 |
1ccbefce | 1359 | && recog_data.constraints[i][0] == '%')) |
7aba0f0b | 1360 | continue; |
3061cc54 RK |
1361 | |
1362 | /* Likewise if each alternative has some operand that | |
64e3a413 | 1363 | must match operand zero. In that case, skip any |
3061cc54 RK |
1364 | operand that doesn't list operand 0 since we know that |
1365 | the operand always conflicts with operand 0. We | |
1366 | ignore commutatity in this case to keep things simple. */ | |
1ccbefce RH |
1367 | if (n_matching_alts == recog_data.n_alternatives |
1368 | && 0 == requires_inout (recog_data.constraints[i])) | |
3061cc54 | 1369 | continue; |
2bbd3819 | 1370 | |
1ccbefce | 1371 | r1 = recog_data.operand[i]; |
2bbd3819 | 1372 | |
7aba0f0b RK |
1373 | /* If the operand is an address, find a register in it. |
1374 | There may be more than one register, but we only try one | |
1375 | of them. */ | |
19af6455 | 1376 | if (recog_data.constraints[i][0] == 'p') |
7aba0f0b RK |
1377 | while (GET_CODE (r1) == PLUS || GET_CODE (r1) == MULT) |
1378 | r1 = XEXP (r1, 0); | |
1379 | ||
1380 | if (GET_CODE (r0) == REG || GET_CODE (r0) == SUBREG) | |
1381 | { | |
1382 | /* We have two priorities for hard register preferences. | |
1383 | If we have a move insn or an insn whose first input | |
1384 | can only be in the same register as the output, give | |
1385 | priority to an equivalence found from that insn. */ | |
1386 | int may_save_copy | |
1ccbefce | 1387 | = (r1 == recog_data.operand[i] && must_match_0 >= 0); |
64e3a413 | 1388 | |
7aba0f0b RK |
1389 | if (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG) |
1390 | win = combine_regs (r1, r0, may_save_copy, | |
1391 | insn_number, insn, 0); | |
1392 | } | |
662347c5 JL |
1393 | if (win) |
1394 | break; | |
2bbd3819 RS |
1395 | } |
1396 | } | |
1397 | ||
1398 | /* Recognize an insn sequence with an ultimate result | |
1399 | which can safely overlap one of the inputs. | |
1400 | The sequence begins with a CLOBBER of its result, | |
1401 | and ends with an insn that copies the result to itself | |
1402 | and has a REG_EQUAL note for an equivalent formula. | |
1403 | That note indicates what the inputs are. | |
1404 | The result and the input can overlap if each insn in | |
1405 | the sequence either doesn't mention the input | |
1406 | or has a REG_NO_CONFLICT note to inhibit the conflict. | |
1407 | ||
1408 | We do the combining test at the CLOBBER so that the | |
1409 | destination register won't have had a quantity number | |
1410 | assigned, since that would prevent combining. */ | |
1411 | ||
d29c259b RH |
1412 | if (optimize |
1413 | && GET_CODE (PATTERN (insn)) == CLOBBER | |
2bbd3819 RS |
1414 | && (r0 = XEXP (PATTERN (insn), 0), |
1415 | GET_CODE (r0) == REG) | |
b1ec3c92 | 1416 | && (link = find_reg_note (insn, REG_LIBCALL, NULL_RTX)) != 0 |
a6665f8c | 1417 | && XEXP (link, 0) != 0 |
2bbd3819 RS |
1418 | && GET_CODE (XEXP (link, 0)) == INSN |
1419 | && (set = single_set (XEXP (link, 0))) != 0 | |
1420 | && SET_DEST (set) == r0 && SET_SRC (set) == r0 | |
b1ec3c92 CH |
1421 | && (note = find_reg_note (XEXP (link, 0), REG_EQUAL, |
1422 | NULL_RTX)) != 0) | |
2bbd3819 RS |
1423 | { |
1424 | if (r1 = XEXP (note, 0), GET_CODE (r1) == REG | |
1425 | /* Check that we have such a sequence. */ | |
1426 | && no_conflict_p (insn, r0, r1)) | |
1427 | win = combine_regs (r1, r0, 1, insn_number, insn, 1); | |
1428 | else if (GET_RTX_FORMAT (GET_CODE (XEXP (note, 0)))[0] == 'e' | |
1429 | && (r1 = XEXP (XEXP (note, 0), 0), | |
1430 | GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG) | |
1431 | && no_conflict_p (insn, r0, r1)) | |
1432 | win = combine_regs (r1, r0, 0, insn_number, insn, 1); | |
1433 | ||
1434 | /* Here we care if the operation to be computed is | |
1435 | commutative. */ | |
1436 | else if ((GET_CODE (XEXP (note, 0)) == EQ | |
1437 | || GET_CODE (XEXP (note, 0)) == NE | |
1438 | || GET_RTX_CLASS (GET_CODE (XEXP (note, 0))) == 'c') | |
1439 | && (r1 = XEXP (XEXP (note, 0), 1), | |
1440 | (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)) | |
1441 | && no_conflict_p (insn, r0, r1)) | |
1442 | win = combine_regs (r1, r0, 0, insn_number, insn, 1); | |
1443 | ||
1444 | /* If we did combine something, show the register number | |
1445 | in question so that we know to ignore its death. */ | |
1446 | if (win) | |
1447 | no_conflict_combined_regno = REGNO (r1); | |
1448 | } | |
1449 | ||
1450 | /* If registers were just tied, set COMBINED_REGNO | |
1451 | to the number of the register used in this insn | |
1452 | that was tied to the register set in this insn. | |
1453 | This register's qty should not be "killed". */ | |
1454 | ||
1455 | if (win) | |
1456 | { | |
1457 | while (GET_CODE (r1) == SUBREG) | |
1458 | r1 = SUBREG_REG (r1); | |
1459 | combined_regno = REGNO (r1); | |
1460 | } | |
1461 | ||
1462 | /* Mark the death of everything that dies in this instruction, | |
1463 | except for anything that was just combined. */ | |
1464 | ||
1465 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | |
1466 | if (REG_NOTE_KIND (link) == REG_DEAD | |
1467 | && GET_CODE (XEXP (link, 0)) == REG | |
770ae6cc RK |
1468 | && combined_regno != (int) REGNO (XEXP (link, 0)) |
1469 | && (no_conflict_combined_regno != (int) REGNO (XEXP (link, 0)) | |
1470 | || ! find_reg_note (insn, REG_NO_CONFLICT, | |
1471 | XEXP (link, 0)))) | |
2bbd3819 RS |
1472 | wipe_dead_reg (XEXP (link, 0), 0); |
1473 | ||
1474 | /* Allocate qty numbers for all registers local to this block | |
1475 | that are born (set) in this instruction. | |
1476 | A pseudo that already has a qty is not changed. */ | |
1477 | ||
84832317 | 1478 | note_stores (PATTERN (insn), reg_is_set, NULL); |
2bbd3819 RS |
1479 | |
1480 | /* If anything is set in this insn and then unused, mark it as dying | |
1481 | after this insn, so it will conflict with our outputs. This | |
1482 | can't match with something that combined, and it doesn't matter | |
1483 | if it did. Do this after the calls to reg_is_set since these | |
1484 | die after, not during, the current insn. */ | |
1485 | ||
1486 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | |
1487 | if (REG_NOTE_KIND (link) == REG_UNUSED | |
1488 | && GET_CODE (XEXP (link, 0)) == REG) | |
1489 | wipe_dead_reg (XEXP (link, 0), 1); | |
1490 | ||
64e3a413 | 1491 | /* If this is an insn that has a REG_RETVAL note pointing at a |
2bbd3819 RS |
1492 | CLOBBER insn, we have reached the end of a REG_NO_CONFLICT |
1493 | block, so clear any register number that combined within it. */ | |
b1ec3c92 | 1494 | if ((note = find_reg_note (insn, REG_RETVAL, NULL_RTX)) != 0 |
2bbd3819 RS |
1495 | && GET_CODE (XEXP (note, 0)) == INSN |
1496 | && GET_CODE (PATTERN (XEXP (note, 0))) == CLOBBER) | |
1497 | no_conflict_combined_regno = -1; | |
1498 | } | |
1499 | ||
1500 | /* Set the registers live after INSN_NUMBER. Note that we never | |
1501 | record the registers live before the block's first insn, since no | |
1502 | pseudos we care about are live before that insn. */ | |
1503 | ||
1504 | IOR_HARD_REG_SET (regs_live_at[2 * insn_number], regs_live); | |
1505 | IOR_HARD_REG_SET (regs_live_at[2 * insn_number + 1], regs_live); | |
1506 | ||
3b413743 | 1507 | if (insn == BLOCK_END (b)) |
2bbd3819 RS |
1508 | break; |
1509 | ||
1510 | insn = NEXT_INSN (insn); | |
1511 | } | |
1512 | ||
1513 | /* Now every register that is local to this basic block | |
1514 | should have been given a quantity, or else -1 meaning ignore it. | |
64e3a413 | 1515 | Every quantity should have a known birth and death. |
2bbd3819 | 1516 | |
51b86d8b RK |
1517 | Order the qtys so we assign them registers in order of the |
1518 | number of suggested registers they need so we allocate those with | |
1519 | the most restrictive needs first. */ | |
2bbd3819 | 1520 | |
ff154f78 | 1521 | qty_order = (int *) xmalloc (next_qty * sizeof (int)); |
2bbd3819 RS |
1522 | for (i = 0; i < next_qty; i++) |
1523 | qty_order[i] = i; | |
1524 | ||
1525 | #define EXCHANGE(I1, I2) \ | |
1526 | { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; } | |
1527 | ||
1528 | switch (next_qty) | |
1529 | { | |
1530 | case 3: | |
1531 | /* Make qty_order[2] be the one to allocate last. */ | |
51b86d8b | 1532 | if (qty_sugg_compare (0, 1) > 0) |
2bbd3819 | 1533 | EXCHANGE (0, 1); |
51b86d8b | 1534 | if (qty_sugg_compare (1, 2) > 0) |
2bbd3819 RS |
1535 | EXCHANGE (2, 1); |
1536 | ||
0f41302f | 1537 | /* ... Fall through ... */ |
2bbd3819 RS |
1538 | case 2: |
1539 | /* Put the best one to allocate in qty_order[0]. */ | |
51b86d8b | 1540 | if (qty_sugg_compare (0, 1) > 0) |
2bbd3819 RS |
1541 | EXCHANGE (0, 1); |
1542 | ||
0f41302f | 1543 | /* ... Fall through ... */ |
2bbd3819 RS |
1544 | |
1545 | case 1: | |
1546 | case 0: | |
1547 | /* Nothing to do here. */ | |
1548 | break; | |
1549 | ||
1550 | default: | |
51b86d8b | 1551 | qsort (qty_order, next_qty, sizeof (int), qty_sugg_compare_1); |
2bbd3819 RS |
1552 | } |
1553 | ||
1554 | /* Try to put each quantity in a suggested physical register, if it has one. | |
1555 | This may cause registers to be allocated that otherwise wouldn't be, but | |
1556 | this seems acceptable in local allocation (unlike global allocation). */ | |
1557 | for (i = 0; i < next_qty; i++) | |
1558 | { | |
1559 | q = qty_order[i]; | |
51b86d8b | 1560 | if (qty_phys_num_sugg[q] != 0 || qty_phys_num_copy_sugg[q] != 0) |
a1ed7bdb JH |
1561 | qty[q].phys_reg = find_free_reg (qty[q].min_class, qty[q].mode, q, |
1562 | 0, 1, qty[q].birth, qty[q].death); | |
2bbd3819 | 1563 | else |
a1ed7bdb | 1564 | qty[q].phys_reg = -1; |
2bbd3819 RS |
1565 | } |
1566 | ||
64e3a413 KH |
1567 | /* Order the qtys so we assign them registers in order of |
1568 | decreasing length of life. Normally call qsort, but if we | |
51b86d8b RK |
1569 | have only a very small number of quantities, sort them ourselves. */ |
1570 | ||
1571 | for (i = 0; i < next_qty; i++) | |
1572 | qty_order[i] = i; | |
1573 | ||
1574 | #define EXCHANGE(I1, I2) \ | |
1575 | { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; } | |
1576 | ||
1577 | switch (next_qty) | |
1578 | { | |
1579 | case 3: | |
1580 | /* Make qty_order[2] be the one to allocate last. */ | |
1581 | if (qty_compare (0, 1) > 0) | |
1582 | EXCHANGE (0, 1); | |
1583 | if (qty_compare (1, 2) > 0) | |
1584 | EXCHANGE (2, 1); | |
1585 | ||
0f41302f | 1586 | /* ... Fall through ... */ |
51b86d8b RK |
1587 | case 2: |
1588 | /* Put the best one to allocate in qty_order[0]. */ | |
1589 | if (qty_compare (0, 1) > 0) | |
1590 | EXCHANGE (0, 1); | |
1591 | ||
0f41302f | 1592 | /* ... Fall through ... */ |
51b86d8b RK |
1593 | |
1594 | case 1: | |
1595 | case 0: | |
1596 | /* Nothing to do here. */ | |
1597 | break; | |
1598 | ||
1599 | default: | |
1600 | qsort (qty_order, next_qty, sizeof (int), qty_compare_1); | |
1601 | } | |
1602 | ||
2bbd3819 RS |
1603 | /* Now for each qty that is not a hardware register, |
1604 | look for a hardware register to put it in. | |
1605 | First try the register class that is cheapest for this qty, | |
1606 | if there is more than one class. */ | |
1607 | ||
1608 | for (i = 0; i < next_qty; i++) | |
1609 | { | |
1610 | q = qty_order[i]; | |
a1ed7bdb | 1611 | if (qty[q].phys_reg < 0) |
2bbd3819 | 1612 | { |
624a8b3a JL |
1613 | #ifdef INSN_SCHEDULING |
1614 | /* These values represent the adjusted lifetime of a qty so | |
1615 | that it conflicts with qtys which appear near the start/end | |
1616 | of this qty's lifetime. | |
1617 | ||
1618 | The purpose behind extending the lifetime of this qty is to | |
1619 | discourage the register allocator from creating false | |
1620 | dependencies. | |
64e3a413 | 1621 | |
996e9683 JL |
1622 | The adjustment value is choosen to indicate that this qty |
1623 | conflicts with all the qtys in the instructions immediately | |
624a8b3a JL |
1624 | before and after the lifetime of this qty. |
1625 | ||
1626 | Experiments have shown that higher values tend to hurt | |
1627 | overall code performance. | |
1628 | ||
1629 | If allocation using the extended lifetime fails we will try | |
1630 | again with the qty's unadjusted lifetime. */ | |
a1ed7bdb | 1631 | int fake_birth = MAX (0, qty[q].birth - 2 + qty[q].birth % 2); |
996e9683 | 1632 | int fake_death = MIN (insn_number * 2 + 1, |
a1ed7bdb | 1633 | qty[q].death + 2 - qty[q].death % 2); |
624a8b3a JL |
1634 | #endif |
1635 | ||
2bbd3819 RS |
1636 | if (N_REG_CLASSES > 1) |
1637 | { | |
624a8b3a JL |
1638 | #ifdef INSN_SCHEDULING |
1639 | /* We try to avoid using hard registers allocated to qtys which | |
1640 | are born immediately after this qty or die immediately before | |
1641 | this qty. | |
1642 | ||
1643 | This optimization is only appropriate when we will run | |
1644 | a scheduling pass after reload and we are not optimizing | |
1645 | for code size. */ | |
c358412f JL |
1646 | if (flag_schedule_insns_after_reload |
1647 | && !optimize_size | |
1648 | && !SMALL_REGISTER_CLASSES) | |
624a8b3a | 1649 | { |
64e3a413 | 1650 | qty[q].phys_reg = find_free_reg (qty[q].min_class, |
a1ed7bdb | 1651 | qty[q].mode, q, 0, 0, |
624a8b3a | 1652 | fake_birth, fake_death); |
a1ed7bdb | 1653 | if (qty[q].phys_reg >= 0) |
624a8b3a JL |
1654 | continue; |
1655 | } | |
1656 | #endif | |
64e3a413 | 1657 | qty[q].phys_reg = find_free_reg (qty[q].min_class, |
a1ed7bdb JH |
1658 | qty[q].mode, q, 0, 0, |
1659 | qty[q].birth, qty[q].death); | |
1660 | if (qty[q].phys_reg >= 0) | |
2bbd3819 RS |
1661 | continue; |
1662 | } | |
1663 | ||
624a8b3a JL |
1664 | #ifdef INSN_SCHEDULING |
1665 | /* Similarly, avoid false dependencies. */ | |
c358412f JL |
1666 | if (flag_schedule_insns_after_reload |
1667 | && !optimize_size | |
1668 | && !SMALL_REGISTER_CLASSES | |
a1ed7bdb JH |
1669 | && qty[q].alternate_class != NO_REGS) |
1670 | qty[q].phys_reg = find_free_reg (qty[q].alternate_class, | |
1671 | qty[q].mode, q, 0, 0, | |
624a8b3a JL |
1672 | fake_birth, fake_death); |
1673 | #endif | |
a1ed7bdb JH |
1674 | if (qty[q].alternate_class != NO_REGS) |
1675 | qty[q].phys_reg = find_free_reg (qty[q].alternate_class, | |
1676 | qty[q].mode, q, 0, 0, | |
1677 | qty[q].birth, qty[q].death); | |
2bbd3819 RS |
1678 | } |
1679 | } | |
1680 | ||
1681 | /* Now propagate the register assignments | |
1682 | to the pseudo regs belonging to the qtys. */ | |
1683 | ||
1684 | for (q = 0; q < next_qty; q++) | |
a1ed7bdb | 1685 | if (qty[q].phys_reg >= 0) |
2bbd3819 | 1686 | { |
a1ed7bdb JH |
1687 | for (i = qty[q].first_reg; i >= 0; i = reg_next_in_qty[i]) |
1688 | reg_renumber[i] = qty[q].phys_reg + reg_offset[i]; | |
2bbd3819 | 1689 | } |
ff154f78 MM |
1690 | |
1691 | /* Clean up. */ | |
1692 | free (regs_live_at); | |
1693 | free (qty_order); | |
2bbd3819 RS |
1694 | } |
1695 | \f | |
1696 | /* Compare two quantities' priority for getting real registers. | |
1697 | We give shorter-lived quantities higher priority. | |
6dc42e49 RS |
1698 | Quantities with more references are also preferred, as are quantities that |
1699 | require multiple registers. This is the identical prioritization as | |
2bbd3819 RS |
1700 | done by global-alloc. |
1701 | ||
1702 | We used to give preference to registers with *longer* lives, but using | |
1703 | the same algorithm in both local- and global-alloc can speed up execution | |
1704 | of some programs by as much as a factor of three! */ | |
1705 | ||
2f23fcc9 RK |
1706 | /* Note that the quotient will never be bigger than |
1707 | the value of floor_log2 times the maximum number of | |
a08b2604 JH |
1708 | times a register can occur in one insn (surely less than 100) |
1709 | weighted by frequency (max REG_FREQ_MAX). | |
1710 | Multiplying this by 10000/REG_FREQ_MAX can't overflow. | |
2f23fcc9 RK |
1711 | QTY_CMP_PRI is also used by qty_sugg_compare. */ |
1712 | ||
1713 | #define QTY_CMP_PRI(q) \ | |
b2aec5c0 | 1714 | ((int) (((double) (floor_log2 (qty[q].n_refs) * qty[q].freq * qty[q].size) \ |
a08b2604 | 1715 | / (qty[q].death - qty[q].birth)) * (10000 / REG_FREQ_MAX))) |
2f23fcc9 | 1716 | |
2bbd3819 RS |
1717 | static int |
1718 | qty_compare (q1, q2) | |
1719 | int q1, q2; | |
1720 | { | |
2f23fcc9 | 1721 | return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1); |
2bbd3819 RS |
1722 | } |
1723 | ||
1724 | static int | |
2f23fcc9 | 1725 | qty_compare_1 (q1p, q2p) |
e1b6684c KG |
1726 | const PTR q1p; |
1727 | const PTR q2p; | |
2bbd3819 | 1728 | { |
64e3a413 | 1729 | register int q1 = *(const int *) q1p, q2 = *(const int *) q2p; |
2f23fcc9 RK |
1730 | register int tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1); |
1731 | ||
1732 | if (tem != 0) | |
1733 | return tem; | |
1734 | ||
2bbd3819 RS |
1735 | /* If qtys are equally good, sort by qty number, |
1736 | so that the results of qsort leave nothing to chance. */ | |
2f23fcc9 | 1737 | return q1 - q2; |
2bbd3819 RS |
1738 | } |
1739 | \f | |
51b86d8b RK |
1740 | /* Compare two quantities' priority for getting real registers. This version |
1741 | is called for quantities that have suggested hard registers. First priority | |
1742 | goes to quantities that have copy preferences, then to those that have | |
1743 | normal preferences. Within those groups, quantities with the lower | |
9faa82d8 | 1744 | number of preferences have the highest priority. Of those, we use the same |
51b86d8b RK |
1745 | algorithm as above. */ |
1746 | ||
2f23fcc9 RK |
1747 | #define QTY_CMP_SUGG(q) \ |
1748 | (qty_phys_num_copy_sugg[q] \ | |
1749 | ? qty_phys_num_copy_sugg[q] \ | |
1750 | : qty_phys_num_sugg[q] * FIRST_PSEUDO_REGISTER) | |
1751 | ||
51b86d8b RK |
1752 | static int |
1753 | qty_sugg_compare (q1, q2) | |
1754 | int q1, q2; | |
1755 | { | |
2f23fcc9 RK |
1756 | register int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2); |
1757 | ||
1758 | if (tem != 0) | |
1759 | return tem; | |
64e3a413 | 1760 | |
2f23fcc9 | 1761 | return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1); |
51b86d8b RK |
1762 | } |
1763 | ||
1764 | static int | |
2f23fcc9 | 1765 | qty_sugg_compare_1 (q1p, q2p) |
e1b6684c KG |
1766 | const PTR q1p; |
1767 | const PTR q2p; | |
51b86d8b | 1768 | { |
64e3a413 | 1769 | register int q1 = *(const int *) q1p, q2 = *(const int *) q2p; |
2f23fcc9 RK |
1770 | register int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2); |
1771 | ||
1772 | if (tem != 0) | |
1773 | return tem; | |
1774 | ||
1775 | tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1); | |
1776 | if (tem != 0) | |
1777 | return tem; | |
51b86d8b RK |
1778 | |
1779 | /* If qtys are equally good, sort by qty number, | |
1780 | so that the results of qsort leave nothing to chance. */ | |
2f23fcc9 | 1781 | return q1 - q2; |
51b86d8b | 1782 | } |
2f23fcc9 RK |
1783 | |
1784 | #undef QTY_CMP_SUGG | |
1785 | #undef QTY_CMP_PRI | |
51b86d8b | 1786 | \f |
2bbd3819 RS |
1787 | /* Attempt to combine the two registers (rtx's) USEDREG and SETREG. |
1788 | Returns 1 if have done so, or 0 if cannot. | |
1789 | ||
1790 | Combining registers means marking them as having the same quantity | |
1791 | and adjusting the offsets within the quantity if either of | |
1792 | them is a SUBREG). | |
1793 | ||
1794 | We don't actually combine a hard reg with a pseudo; instead | |
1795 | we just record the hard reg as the suggestion for the pseudo's quantity. | |
1796 | If we really combined them, we could lose if the pseudo lives | |
1797 | across an insn that clobbers the hard reg (eg, movstr). | |
1798 | ||
1799 | ALREADY_DEAD is non-zero if USEDREG is known to be dead even though | |
1800 | there is no REG_DEAD note on INSN. This occurs during the processing | |
1801 | of REG_NO_CONFLICT blocks. | |
1802 | ||
1803 | MAY_SAVE_COPYCOPY is non-zero if this insn is simply copying USEDREG to | |
1804 | SETREG or if the input and output must share a register. | |
1805 | In that case, we record a hard reg suggestion in QTY_PHYS_COPY_SUGG. | |
64e3a413 | 1806 | |
2bbd3819 RS |
1807 | There are elaborate checks for the validity of combining. */ |
1808 | ||
2bbd3819 RS |
1809 | static int |
1810 | combine_regs (usedreg, setreg, may_save_copy, insn_number, insn, already_dead) | |
1811 | rtx usedreg, setreg; | |
1812 | int may_save_copy; | |
1813 | int insn_number; | |
1814 | rtx insn; | |
1815 | int already_dead; | |
1816 | { | |
1817 | register int ureg, sreg; | |
1818 | register int offset = 0; | |
1819 | int usize, ssize; | |
1820 | register int sqty; | |
1821 | ||
1822 | /* Determine the numbers and sizes of registers being used. If a subreg | |
6dc42e49 | 1823 | is present that does not change the entire register, don't consider |
2bbd3819 RS |
1824 | this a copy insn. */ |
1825 | ||
1826 | while (GET_CODE (usedreg) == SUBREG) | |
1827 | { | |
1828 | if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (usedreg))) > UNITS_PER_WORD) | |
1829 | may_save_copy = 0; | |
ddef6bc7 JJ |
1830 | if (REGNO (SUBREG_REG (usedreg)) < FIRST_PSEUDO_REGISTER) |
1831 | offset += subreg_regno_offset (REGNO (SUBREG_REG (usedreg)), | |
1832 | GET_MODE (SUBREG_REG (usedreg)), | |
1833 | SUBREG_BYTE (usedreg), | |
1834 | GET_MODE (usedreg)); | |
1835 | else | |
1836 | offset += (SUBREG_BYTE (usedreg) | |
1837 | / REGMODE_NATURAL_SIZE (GET_MODE (usedreg))); | |
2bbd3819 RS |
1838 | usedreg = SUBREG_REG (usedreg); |
1839 | } | |
1840 | if (GET_CODE (usedreg) != REG) | |
1841 | return 0; | |
1842 | ureg = REGNO (usedreg); | |
ddef6bc7 JJ |
1843 | if (ureg < FIRST_PSEUDO_REGISTER) |
1844 | usize = HARD_REGNO_NREGS (ureg, GET_MODE (usedreg)); | |
1845 | else | |
1846 | usize = ((GET_MODE_SIZE (GET_MODE (usedreg)) | |
1847 | + (REGMODE_NATURAL_SIZE (GET_MODE (usedreg)) - 1)) | |
1848 | / REGMODE_NATURAL_SIZE (GET_MODE (usedreg))); | |
2bbd3819 RS |
1849 | |
1850 | while (GET_CODE (setreg) == SUBREG) | |
1851 | { | |
1852 | if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (setreg))) > UNITS_PER_WORD) | |
1853 | may_save_copy = 0; | |
ddef6bc7 JJ |
1854 | if (REGNO (SUBREG_REG (setreg)) < FIRST_PSEUDO_REGISTER) |
1855 | offset -= subreg_regno_offset (REGNO (SUBREG_REG (setreg)), | |
1856 | GET_MODE (SUBREG_REG (setreg)), | |
1857 | SUBREG_BYTE (setreg), | |
1858 | GET_MODE (setreg)); | |
1859 | else | |
1860 | offset -= (SUBREG_BYTE (setreg) | |
1861 | / REGMODE_NATURAL_SIZE (GET_MODE (setreg))); | |
2bbd3819 RS |
1862 | setreg = SUBREG_REG (setreg); |
1863 | } | |
1864 | if (GET_CODE (setreg) != REG) | |
1865 | return 0; | |
1866 | sreg = REGNO (setreg); | |
ddef6bc7 JJ |
1867 | if (sreg < FIRST_PSEUDO_REGISTER) |
1868 | ssize = HARD_REGNO_NREGS (sreg, GET_MODE (setreg)); | |
1869 | else | |
1870 | ssize = ((GET_MODE_SIZE (GET_MODE (setreg)) | |
1871 | + (REGMODE_NATURAL_SIZE (GET_MODE (setreg)) - 1)) | |
1872 | / REGMODE_NATURAL_SIZE (GET_MODE (setreg))); | |
2bbd3819 RS |
1873 | |
1874 | /* If UREG is a pseudo-register that hasn't already been assigned a | |
1875 | quantity number, it means that it is not local to this block or dies | |
1876 | more than once. In either event, we can't do anything with it. */ | |
1877 | if ((ureg >= FIRST_PSEUDO_REGISTER && reg_qty[ureg] < 0) | |
1878 | /* Do not combine registers unless one fits within the other. */ | |
1879 | || (offset > 0 && usize + offset > ssize) | |
1880 | || (offset < 0 && usize + offset < ssize) | |
1881 | /* Do not combine with a smaller already-assigned object | |
0f41302f | 1882 | if that smaller object is already combined with something bigger. */ |
2bbd3819 | 1883 | || (ssize > usize && ureg >= FIRST_PSEUDO_REGISTER |
a1ed7bdb | 1884 | && usize < qty[reg_qty[ureg]].size) |
2bbd3819 RS |
1885 | /* Can't combine if SREG is not a register we can allocate. */ |
1886 | || (sreg >= FIRST_PSEUDO_REGISTER && reg_qty[sreg] == -1) | |
1887 | /* Don't combine with a pseudo mentioned in a REG_NO_CONFLICT note. | |
1888 | These have already been taken care of. This probably wouldn't | |
1889 | combine anyway, but don't take any chances. */ | |
1890 | || (ureg >= FIRST_PSEUDO_REGISTER | |
1891 | && find_reg_note (insn, REG_NO_CONFLICT, usedreg)) | |
1892 | /* Don't tie something to itself. In most cases it would make no | |
1893 | difference, but it would screw up if the reg being tied to itself | |
1894 | also dies in this insn. */ | |
1895 | || ureg == sreg | |
1896 | /* Don't try to connect two different hardware registers. */ | |
1897 | || (ureg < FIRST_PSEUDO_REGISTER && sreg < FIRST_PSEUDO_REGISTER) | |
1898 | /* Don't connect two different machine modes if they have different | |
1899 | implications as to which registers may be used. */ | |
1900 | || !MODES_TIEABLE_P (GET_MODE (usedreg), GET_MODE (setreg))) | |
1901 | return 0; | |
1902 | ||
1903 | /* Now, if UREG is a hard reg and SREG is a pseudo, record the hard reg in | |
1904 | qty_phys_sugg for the pseudo instead of tying them. | |
1905 | ||
1906 | Return "failure" so that the lifespan of UREG is terminated here; | |
1907 | that way the two lifespans will be disjoint and nothing will prevent | |
1908 | the pseudo reg from being given this hard reg. */ | |
1909 | ||
1910 | if (ureg < FIRST_PSEUDO_REGISTER) | |
1911 | { | |
1912 | /* Allocate a quantity number so we have a place to put our | |
1913 | suggestions. */ | |
1914 | if (reg_qty[sreg] == -2) | |
1915 | reg_is_born (setreg, 2 * insn_number); | |
1916 | ||
1917 | if (reg_qty[sreg] >= 0) | |
1918 | { | |
51b86d8b RK |
1919 | if (may_save_copy |
1920 | && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg)) | |
2bbd3819 RS |
1921 | { |
1922 | SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg); | |
51b86d8b | 1923 | qty_phys_num_copy_sugg[reg_qty[sreg]]++; |
2bbd3819 | 1924 | } |
51b86d8b | 1925 | else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg)) |
2bbd3819 RS |
1926 | { |
1927 | SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg); | |
51b86d8b | 1928 | qty_phys_num_sugg[reg_qty[sreg]]++; |
2bbd3819 RS |
1929 | } |
1930 | } | |
1931 | return 0; | |
1932 | } | |
1933 | ||
1934 | /* Similarly for SREG a hard register and UREG a pseudo register. */ | |
1935 | ||
1936 | if (sreg < FIRST_PSEUDO_REGISTER) | |
1937 | { | |
51b86d8b RK |
1938 | if (may_save_copy |
1939 | && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg)) | |
2bbd3819 RS |
1940 | { |
1941 | SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg); | |
51b86d8b | 1942 | qty_phys_num_copy_sugg[reg_qty[ureg]]++; |
2bbd3819 | 1943 | } |
51b86d8b | 1944 | else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg)) |
2bbd3819 RS |
1945 | { |
1946 | SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg); | |
51b86d8b | 1947 | qty_phys_num_sugg[reg_qty[ureg]]++; |
2bbd3819 RS |
1948 | } |
1949 | return 0; | |
1950 | } | |
1951 | ||
1952 | /* At this point we know that SREG and UREG are both pseudos. | |
1953 | Do nothing if SREG already has a quantity or is a register that we | |
1954 | don't allocate. */ | |
1955 | if (reg_qty[sreg] >= -1 | |
1956 | /* If we are not going to let any regs live across calls, | |
1957 | don't tie a call-crossing reg to a non-call-crossing reg. */ | |
1958 | || (current_function_has_nonlocal_label | |
b1f21e0a MM |
1959 | && ((REG_N_CALLS_CROSSED (ureg) > 0) |
1960 | != (REG_N_CALLS_CROSSED (sreg) > 0)))) | |
2bbd3819 RS |
1961 | return 0; |
1962 | ||
1963 | /* We don't already know about SREG, so tie it to UREG | |
1964 | if this is the last use of UREG, provided the classes they want | |
1965 | are compatible. */ | |
1966 | ||
1967 | if ((already_dead || find_regno_note (insn, REG_DEAD, ureg)) | |
a1ed7bdb | 1968 | && reg_meets_class_p (sreg, qty[reg_qty[ureg]].min_class)) |
2bbd3819 RS |
1969 | { |
1970 | /* Add SREG to UREG's quantity. */ | |
1971 | sqty = reg_qty[ureg]; | |
1972 | reg_qty[sreg] = sqty; | |
1973 | reg_offset[sreg] = reg_offset[ureg] + offset; | |
a1ed7bdb JH |
1974 | reg_next_in_qty[sreg] = qty[sqty].first_reg; |
1975 | qty[sqty].first_reg = sreg; | |
2bbd3819 | 1976 | |
a1ed7bdb | 1977 | /* If SREG's reg class is smaller, set qty[SQTY].min_class. */ |
2bbd3819 RS |
1978 | update_qty_class (sqty, sreg); |
1979 | ||
1980 | /* Update info about quantity SQTY. */ | |
a1ed7bdb JH |
1981 | qty[sqty].n_calls_crossed += REG_N_CALLS_CROSSED (sreg); |
1982 | qty[sqty].n_refs += REG_N_REFS (sreg); | |
b2aec5c0 | 1983 | qty[sqty].freq += REG_FREQ (sreg); |
2bbd3819 RS |
1984 | if (usize < ssize) |
1985 | { | |
1986 | register int i; | |
1987 | ||
a1ed7bdb | 1988 | for (i = qty[sqty].first_reg; i >= 0; i = reg_next_in_qty[i]) |
2bbd3819 RS |
1989 | reg_offset[i] -= offset; |
1990 | ||
a1ed7bdb JH |
1991 | qty[sqty].size = ssize; |
1992 | qty[sqty].mode = GET_MODE (setreg); | |
2bbd3819 RS |
1993 | } |
1994 | } | |
1995 | else | |
1996 | return 0; | |
1997 | ||
1998 | return 1; | |
1999 | } | |
2000 | \f | |
2001 | /* Return 1 if the preferred class of REG allows it to be tied | |
2002 | to a quantity or register whose class is CLASS. | |
2003 | True if REG's reg class either contains or is contained in CLASS. */ | |
2004 | ||
2005 | static int | |
2006 | reg_meets_class_p (reg, class) | |
2007 | int reg; | |
2008 | enum reg_class class; | |
2009 | { | |
2010 | register enum reg_class rclass = reg_preferred_class (reg); | |
2011 | return (reg_class_subset_p (rclass, class) | |
2012 | || reg_class_subset_p (class, rclass)); | |
2013 | } | |
2014 | ||
a1ed7bdb | 2015 | /* Update the class of QTYNO assuming that REG is being tied to it. */ |
2bbd3819 RS |
2016 | |
2017 | static void | |
a1ed7bdb JH |
2018 | update_qty_class (qtyno, reg) |
2019 | int qtyno; | |
2bbd3819 RS |
2020 | int reg; |
2021 | { | |
2022 | enum reg_class rclass = reg_preferred_class (reg); | |
a1ed7bdb JH |
2023 | if (reg_class_subset_p (rclass, qty[qtyno].min_class)) |
2024 | qty[qtyno].min_class = rclass; | |
e4600702 RK |
2025 | |
2026 | rclass = reg_alternate_class (reg); | |
a1ed7bdb JH |
2027 | if (reg_class_subset_p (rclass, qty[qtyno].alternate_class)) |
2028 | qty[qtyno].alternate_class = rclass; | |
0f64b8f6 | 2029 | |
02188693 RH |
2030 | if (REG_CHANGES_MODE (reg)) |
2031 | qty[qtyno].changes_mode = 1; | |
2bbd3819 RS |
2032 | } |
2033 | \f | |
2034 | /* Handle something which alters the value of an rtx REG. | |
2035 | ||
2036 | REG is whatever is set or clobbered. SETTER is the rtx that | |
2037 | is modifying the register. | |
2038 | ||
2039 | If it is not really a register, we do nothing. | |
2040 | The file-global variables `this_insn' and `this_insn_number' | |
2041 | carry info from `block_alloc'. */ | |
2042 | ||
2043 | static void | |
84832317 | 2044 | reg_is_set (reg, setter, data) |
2bbd3819 RS |
2045 | rtx reg; |
2046 | rtx setter; | |
84832317 | 2047 | void *data ATTRIBUTE_UNUSED; |
2bbd3819 RS |
2048 | { |
2049 | /* Note that note_stores will only pass us a SUBREG if it is a SUBREG of | |
2050 | a hard register. These may actually not exist any more. */ | |
2051 | ||
2052 | if (GET_CODE (reg) != SUBREG | |
2053 | && GET_CODE (reg) != REG) | |
2054 | return; | |
2055 | ||
2056 | /* Mark this register as being born. If it is used in a CLOBBER, mark | |
2057 | it as being born halfway between the previous insn and this insn so that | |
2058 | it conflicts with our inputs but not the outputs of the previous insn. */ | |
2059 | ||
2060 | reg_is_born (reg, 2 * this_insn_number - (GET_CODE (setter) == CLOBBER)); | |
2061 | } | |
2062 | \f | |
2063 | /* Handle beginning of the life of register REG. | |
2064 | BIRTH is the index at which this is happening. */ | |
2065 | ||
2066 | static void | |
2067 | reg_is_born (reg, birth) | |
2068 | rtx reg; | |
2069 | int birth; | |
2070 | { | |
2071 | register int regno; | |
64e3a413 | 2072 | |
2bbd3819 | 2073 | if (GET_CODE (reg) == SUBREG) |
ddef6bc7 JJ |
2074 | { |
2075 | regno = REGNO (SUBREG_REG (reg)); | |
2076 | if (regno < FIRST_PSEUDO_REGISTER) | |
2077 | regno = subreg_hard_regno (reg, 1); | |
2078 | } | |
2bbd3819 RS |
2079 | else |
2080 | regno = REGNO (reg); | |
2081 | ||
2082 | if (regno < FIRST_PSEUDO_REGISTER) | |
2083 | { | |
2084 | mark_life (regno, GET_MODE (reg), 1); | |
2085 | ||
2086 | /* If the register was to have been born earlier that the present | |
2087 | insn, mark it as live where it is actually born. */ | |
2088 | if (birth < 2 * this_insn_number) | |
2089 | post_mark_life (regno, GET_MODE (reg), 1, birth, 2 * this_insn_number); | |
2090 | } | |
2091 | else | |
2092 | { | |
2093 | if (reg_qty[regno] == -2) | |
2094 | alloc_qty (regno, GET_MODE (reg), PSEUDO_REGNO_SIZE (regno), birth); | |
2095 | ||
2096 | /* If this register has a quantity number, show that it isn't dead. */ | |
2097 | if (reg_qty[regno] >= 0) | |
a1ed7bdb | 2098 | qty[reg_qty[regno]].death = -1; |
2bbd3819 RS |
2099 | } |
2100 | } | |
2101 | ||
2102 | /* Record the death of REG in the current insn. If OUTPUT_P is non-zero, | |
2103 | REG is an output that is dying (i.e., it is never used), otherwise it | |
333e0f7d RS |
2104 | is an input (the normal case). |
2105 | If OUTPUT_P is 1, then we extend the life past the end of this insn. */ | |
2bbd3819 RS |
2106 | |
2107 | static void | |
2108 | wipe_dead_reg (reg, output_p) | |
2109 | register rtx reg; | |
2110 | int output_p; | |
2111 | { | |
2112 | register int regno = REGNO (reg); | |
2113 | ||
333e0f7d RS |
2114 | /* If this insn has multiple results, |
2115 | and the dead reg is used in one of the results, | |
2116 | extend its life to after this insn, | |
64e3a413 | 2117 | so it won't get allocated together with any other result of this insn. |
941c63ac JL |
2118 | |
2119 | It is unsafe to use !single_set here since it will ignore an unused | |
2120 | output. Just because an output is unused does not mean the compiler | |
2121 | can assume the side effect will not occur. Consider if REG appears | |
2122 | in the address of an output and we reload the output. If we allocate | |
2123 | REG to the same hard register as an unused output we could set the hard | |
2124 | register before the output reload insn. */ | |
333e0f7d | 2125 | if (GET_CODE (PATTERN (this_insn)) == PARALLEL |
941c63ac | 2126 | && multiple_sets (this_insn)) |
333e0f7d RS |
2127 | { |
2128 | int i; | |
2129 | for (i = XVECLEN (PATTERN (this_insn), 0) - 1; i >= 0; i--) | |
2130 | { | |
2131 | rtx set = XVECEXP (PATTERN (this_insn), 0, i); | |
2132 | if (GET_CODE (set) == SET | |
2133 | && GET_CODE (SET_DEST (set)) != REG | |
2134 | && !rtx_equal_p (reg, SET_DEST (set)) | |
2135 | && reg_overlap_mentioned_p (reg, SET_DEST (set))) | |
2136 | output_p = 1; | |
2137 | } | |
2138 | } | |
2139 | ||
c182df0b RK |
2140 | /* If this register is used in an auto-increment address, then extend its |
2141 | life to after this insn, so that it won't get allocated together with | |
2142 | the result of this insn. */ | |
2143 | if (! output_p && find_regno_note (this_insn, REG_INC, regno)) | |
2144 | output_p = 1; | |
2145 | ||
2bbd3819 RS |
2146 | if (regno < FIRST_PSEUDO_REGISTER) |
2147 | { | |
2148 | mark_life (regno, GET_MODE (reg), 0); | |
2149 | ||
2150 | /* If a hard register is dying as an output, mark it as in use at | |
2151 | the beginning of this insn (the above statement would cause this | |
2152 | not to happen). */ | |
2153 | if (output_p) | |
2154 | post_mark_life (regno, GET_MODE (reg), 1, | |
64e3a413 | 2155 | 2 * this_insn_number, 2 * this_insn_number + 1); |
2bbd3819 RS |
2156 | } |
2157 | ||
2158 | else if (reg_qty[regno] >= 0) | |
a1ed7bdb | 2159 | qty[reg_qty[regno]].death = 2 * this_insn_number + output_p; |
2bbd3819 RS |
2160 | } |
2161 | \f | |
2162 | /* Find a block of SIZE words of hard regs in reg_class CLASS | |
2163 | that can hold something of machine-mode MODE | |
2164 | (but actually we test only the first of the block for holding MODE) | |
2165 | and still free between insn BORN_INDEX and insn DEAD_INDEX, | |
2166 | and return the number of the first of them. | |
64e3a413 | 2167 | Return -1 if such a block cannot be found. |
a1ed7bdb | 2168 | If QTYNO crosses calls, insist on a register preserved by calls, |
2bbd3819 RS |
2169 | unless ACCEPT_CALL_CLOBBERED is nonzero. |
2170 | ||
2171 | If JUST_TRY_SUGGESTED is non-zero, only try to see if the suggested | |
2172 | register is available. If not, return -1. */ | |
2173 | ||
2174 | static int | |
a1ed7bdb | 2175 | find_free_reg (class, mode, qtyno, accept_call_clobbered, just_try_suggested, |
2bbd3819 RS |
2176 | born_index, dead_index) |
2177 | enum reg_class class; | |
2178 | enum machine_mode mode; | |
a1ed7bdb | 2179 | int qtyno; |
2bbd3819 RS |
2180 | int accept_call_clobbered; |
2181 | int just_try_suggested; | |
2bbd3819 RS |
2182 | int born_index, dead_index; |
2183 | { | |
2184 | register int i, ins; | |
2185 | #ifdef HARD_REG_SET | |
64e3a413 KH |
2186 | /* Declare it register if it's a scalar. */ |
2187 | register | |
2bbd3819 RS |
2188 | #endif |
2189 | HARD_REG_SET used, first_used; | |
2190 | #ifdef ELIMINABLE_REGS | |
2191 | static struct {int from, to; } eliminables[] = ELIMINABLE_REGS; | |
2192 | #endif | |
2193 | ||
2194 | /* Validate our parameters. */ | |
2195 | if (born_index < 0 || born_index > dead_index) | |
2196 | abort (); | |
2197 | ||
2198 | /* Don't let a pseudo live in a reg across a function call | |
2199 | if we might get a nonlocal goto. */ | |
2200 | if (current_function_has_nonlocal_label | |
a1ed7bdb | 2201 | && qty[qtyno].n_calls_crossed > 0) |
2bbd3819 RS |
2202 | return -1; |
2203 | ||
2204 | if (accept_call_clobbered) | |
2205 | COPY_HARD_REG_SET (used, call_fixed_reg_set); | |
a1ed7bdb | 2206 | else if (qty[qtyno].n_calls_crossed == 0) |
2bbd3819 RS |
2207 | COPY_HARD_REG_SET (used, fixed_reg_set); |
2208 | else | |
2209 | COPY_HARD_REG_SET (used, call_used_reg_set); | |
2210 | ||
6cad67d2 | 2211 | if (accept_call_clobbered) |
c09be6c4 | 2212 | IOR_HARD_REG_SET (used, losing_caller_save_reg_set); |
6cad67d2 | 2213 | |
2bbd3819 RS |
2214 | for (ins = born_index; ins < dead_index; ins++) |
2215 | IOR_HARD_REG_SET (used, regs_live_at[ins]); | |
2216 | ||
2217 | IOR_COMPL_HARD_REG_SET (used, reg_class_contents[(int) class]); | |
2218 | ||
2219 | /* Don't use the frame pointer reg in local-alloc even if | |
2220 | we may omit the frame pointer, because if we do that and then we | |
2221 | need a frame pointer, reload won't know how to move the pseudo | |
2222 | to another hard reg. It can move only regs made by global-alloc. | |
2223 | ||
2224 | This is true of any register that can be eliminated. */ | |
2225 | #ifdef ELIMINABLE_REGS | |
b6a1cbae | 2226 | for (i = 0; i < (int) ARRAY_SIZE (eliminables); i++) |
2bbd3819 | 2227 | SET_HARD_REG_BIT (used, eliminables[i].from); |
c2618f05 DE |
2228 | #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM |
2229 | /* If FRAME_POINTER_REGNUM is not a real register, then protect the one | |
0f41302f | 2230 | that it might be eliminated into. */ |
c2618f05 DE |
2231 | SET_HARD_REG_BIT (used, HARD_FRAME_POINTER_REGNUM); |
2232 | #endif | |
2bbd3819 RS |
2233 | #else |
2234 | SET_HARD_REG_BIT (used, FRAME_POINTER_REGNUM); | |
2235 | #endif | |
2236 | ||
02188693 RH |
2237 | #ifdef CLASS_CANNOT_CHANGE_MODE |
2238 | if (qty[qtyno].changes_mode) | |
899d4140 | 2239 | IOR_HARD_REG_SET (used, |
02188693 | 2240 | reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE]); |
0f64b8f6 RK |
2241 | #endif |
2242 | ||
2bbd3819 RS |
2243 | /* Normally, the registers that can be used for the first register in |
2244 | a multi-register quantity are the same as those that can be used for | |
2245 | subsequent registers. However, if just trying suggested registers, | |
2246 | restrict our consideration to them. If there are copy-suggested | |
2247 | register, try them. Otherwise, try the arithmetic-suggested | |
2248 | registers. */ | |
2249 | COPY_HARD_REG_SET (first_used, used); | |
2250 | ||
2251 | if (just_try_suggested) | |
2252 | { | |
a1ed7bdb JH |
2253 | if (qty_phys_num_copy_sugg[qtyno] != 0) |
2254 | IOR_COMPL_HARD_REG_SET (first_used, qty_phys_copy_sugg[qtyno]); | |
2bbd3819 | 2255 | else |
a1ed7bdb | 2256 | IOR_COMPL_HARD_REG_SET (first_used, qty_phys_sugg[qtyno]); |
2bbd3819 RS |
2257 | } |
2258 | ||
2259 | /* If all registers are excluded, we can't do anything. */ | |
2260 | GO_IF_HARD_REG_SUBSET (reg_class_contents[(int) ALL_REGS], first_used, fail); | |
2261 | ||
2262 | /* If at least one would be suitable, test each hard reg. */ | |
2263 | ||
2264 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
2265 | { | |
2266 | #ifdef REG_ALLOC_ORDER | |
2267 | int regno = reg_alloc_order[i]; | |
2268 | #else | |
2269 | int regno = i; | |
2270 | #endif | |
2271 | if (! TEST_HARD_REG_BIT (first_used, regno) | |
1e326708 | 2272 | && HARD_REGNO_MODE_OK (regno, mode) |
a1ed7bdb | 2273 | && (qty[qtyno].n_calls_crossed == 0 |
1e326708 MH |
2274 | || accept_call_clobbered |
2275 | || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))) | |
2bbd3819 RS |
2276 | { |
2277 | register int j; | |
2278 | register int size1 = HARD_REGNO_NREGS (regno, mode); | |
2279 | for (j = 1; j < size1 && ! TEST_HARD_REG_BIT (used, regno + j); j++); | |
2280 | if (j == size1) | |
2281 | { | |
2282 | /* Mark that this register is in use between its birth and death | |
2283 | insns. */ | |
2284 | post_mark_life (regno, mode, 1, born_index, dead_index); | |
2285 | return regno; | |
2286 | } | |
2287 | #ifndef REG_ALLOC_ORDER | |
64e3a413 KH |
2288 | /* Skip starting points we know will lose. */ |
2289 | i += j; | |
2bbd3819 RS |
2290 | #endif |
2291 | } | |
2292 | } | |
2293 | ||
2294 | fail: | |
2bbd3819 RS |
2295 | /* If we are just trying suggested register, we have just tried copy- |
2296 | suggested registers, and there are arithmetic-suggested registers, | |
2297 | try them. */ | |
64e3a413 | 2298 | |
2bbd3819 RS |
2299 | /* If it would be profitable to allocate a call-clobbered register |
2300 | and save and restore it around calls, do that. */ | |
a1ed7bdb JH |
2301 | if (just_try_suggested && qty_phys_num_copy_sugg[qtyno] != 0 |
2302 | && qty_phys_num_sugg[qtyno] != 0) | |
2bbd3819 RS |
2303 | { |
2304 | /* Don't try the copy-suggested regs again. */ | |
a1ed7bdb JH |
2305 | qty_phys_num_copy_sugg[qtyno] = 0; |
2306 | return find_free_reg (class, mode, qtyno, accept_call_clobbered, 1, | |
2bbd3819 RS |
2307 | born_index, dead_index); |
2308 | } | |
2309 | ||
e19f5192 RK |
2310 | /* We need not check to see if the current function has nonlocal |
2311 | labels because we don't put any pseudos that are live over calls in | |
2312 | registers in that case. */ | |
2313 | ||
2bbd3819 RS |
2314 | if (! accept_call_clobbered |
2315 | && flag_caller_saves | |
2316 | && ! just_try_suggested | |
a1ed7bdb | 2317 | && qty[qtyno].n_calls_crossed != 0 |
64e3a413 KH |
2318 | && CALLER_SAVE_PROFITABLE (qty[qtyno].n_refs, |
2319 | qty[qtyno].n_calls_crossed)) | |
2bbd3819 | 2320 | { |
a1ed7bdb | 2321 | i = find_free_reg (class, mode, qtyno, 1, 0, born_index, dead_index); |
2bbd3819 RS |
2322 | if (i >= 0) |
2323 | caller_save_needed = 1; | |
2324 | return i; | |
2325 | } | |
2326 | return -1; | |
2327 | } | |
2328 | \f | |
2329 | /* Mark that REGNO with machine-mode MODE is live starting from the current | |
2330 | insn (if LIFE is non-zero) or dead starting at the current insn (if LIFE | |
2331 | is zero). */ | |
2332 | ||
2333 | static void | |
2334 | mark_life (regno, mode, life) | |
2335 | register int regno; | |
2336 | enum machine_mode mode; | |
2337 | int life; | |
2338 | { | |
2339 | register int j = HARD_REGNO_NREGS (regno, mode); | |
2340 | if (life) | |
2341 | while (--j >= 0) | |
2342 | SET_HARD_REG_BIT (regs_live, regno + j); | |
2343 | else | |
2344 | while (--j >= 0) | |
2345 | CLEAR_HARD_REG_BIT (regs_live, regno + j); | |
2346 | } | |
2347 | ||
2348 | /* Mark register number REGNO (with machine-mode MODE) as live (if LIFE | |
2349 | is non-zero) or dead (if LIFE is zero) from insn number BIRTH (inclusive) | |
2350 | to insn number DEATH (exclusive). */ | |
2351 | ||
2352 | static void | |
2353 | post_mark_life (regno, mode, life, birth, death) | |
82c68a78 | 2354 | int regno; |
2bbd3819 | 2355 | enum machine_mode mode; |
82c68a78 | 2356 | int life, birth, death; |
2bbd3819 RS |
2357 | { |
2358 | register int j = HARD_REGNO_NREGS (regno, mode); | |
2359 | #ifdef HARD_REG_SET | |
64e3a413 KH |
2360 | /* Declare it register if it's a scalar. */ |
2361 | register | |
2bbd3819 RS |
2362 | #endif |
2363 | HARD_REG_SET this_reg; | |
2364 | ||
2365 | CLEAR_HARD_REG_SET (this_reg); | |
2366 | while (--j >= 0) | |
2367 | SET_HARD_REG_BIT (this_reg, regno + j); | |
2368 | ||
2369 | if (life) | |
2370 | while (birth < death) | |
2371 | { | |
2372 | IOR_HARD_REG_SET (regs_live_at[birth], this_reg); | |
2373 | birth++; | |
2374 | } | |
2375 | else | |
2376 | while (birth < death) | |
2377 | { | |
2378 | AND_COMPL_HARD_REG_SET (regs_live_at[birth], this_reg); | |
2379 | birth++; | |
2380 | } | |
2381 | } | |
2382 | \f | |
2383 | /* INSN is the CLOBBER insn that starts a REG_NO_NOCONFLICT block, R0 | |
2384 | is the register being clobbered, and R1 is a register being used in | |
2385 | the equivalent expression. | |
2386 | ||
2387 | If R1 dies in the block and has a REG_NO_CONFLICT note on every insn | |
2388 | in which it is used, return 1. | |
2389 | ||
2390 | Otherwise, return 0. */ | |
2391 | ||
2392 | static int | |
2393 | no_conflict_p (insn, r0, r1) | |
272df862 | 2394 | rtx insn, r0 ATTRIBUTE_UNUSED, r1; |
2bbd3819 RS |
2395 | { |
2396 | int ok = 0; | |
b1ec3c92 | 2397 | rtx note = find_reg_note (insn, REG_LIBCALL, NULL_RTX); |
2bbd3819 RS |
2398 | rtx p, last; |
2399 | ||
2400 | /* If R1 is a hard register, return 0 since we handle this case | |
2401 | when we scan the insns that actually use it. */ | |
2402 | ||
2403 | if (note == 0 | |
2404 | || (GET_CODE (r1) == REG && REGNO (r1) < FIRST_PSEUDO_REGISTER) | |
2405 | || (GET_CODE (r1) == SUBREG && GET_CODE (SUBREG_REG (r1)) == REG | |
2406 | && REGNO (SUBREG_REG (r1)) < FIRST_PSEUDO_REGISTER)) | |
2407 | return 0; | |
2408 | ||
2409 | last = XEXP (note, 0); | |
2410 | ||
2411 | for (p = NEXT_INSN (insn); p && p != last; p = NEXT_INSN (p)) | |
2c3c49de | 2412 | if (INSN_P (p)) |
2bbd3819 RS |
2413 | { |
2414 | if (find_reg_note (p, REG_DEAD, r1)) | |
2415 | ok = 1; | |
2416 | ||
8bb19658 JW |
2417 | /* There must be a REG_NO_CONFLICT note on every insn, otherwise |
2418 | some earlier optimization pass has inserted instructions into | |
2419 | the sequence, and it is not safe to perform this optimization. | |
2420 | Note that emit_no_conflict_block always ensures that this is | |
2421 | true when these sequences are created. */ | |
2422 | if (! find_reg_note (p, REG_NO_CONFLICT, r1)) | |
2bbd3819 RS |
2423 | return 0; |
2424 | } | |
64e3a413 | 2425 | |
2bbd3819 RS |
2426 | return ok; |
2427 | } | |
2428 | \f | |
3061cc54 RK |
2429 | /* Return the number of alternatives for which the constraint string P |
2430 | indicates that the operand must be equal to operand 0 and that no register | |
2431 | is acceptable. */ | |
2bbd3819 RS |
2432 | |
2433 | static int | |
3061cc54 | 2434 | requires_inout (p) |
64e3a413 | 2435 | const char *p; |
2bbd3819 RS |
2436 | { |
2437 | char c; | |
2438 | int found_zero = 0; | |
3061cc54 RK |
2439 | int reg_allowed = 0; |
2440 | int num_matching_alts = 0; | |
2bbd3819 | 2441 | |
51723711 | 2442 | while ((c = *p++)) |
2bbd3819 RS |
2443 | switch (c) |
2444 | { | |
2bbd3819 RS |
2445 | case '=': case '+': case '?': |
2446 | case '#': case '&': case '!': | |
3061cc54 | 2447 | case '*': case '%': |
c5c76735 JL |
2448 | case '1': case '2': case '3': case '4': case '5': |
2449 | case '6': case '7': case '8': case '9': | |
2bbd3819 RS |
2450 | case 'm': case '<': case '>': case 'V': case 'o': |
2451 | case 'E': case 'F': case 'G': case 'H': | |
2452 | case 's': case 'i': case 'n': | |
2453 | case 'I': case 'J': case 'K': case 'L': | |
2454 | case 'M': case 'N': case 'O': case 'P': | |
2bbd3819 RS |
2455 | case 'X': |
2456 | /* These don't say anything we care about. */ | |
2457 | break; | |
2458 | ||
3061cc54 RK |
2459 | case ',': |
2460 | if (found_zero && ! reg_allowed) | |
2461 | num_matching_alts++; | |
2462 | ||
2463 | found_zero = reg_allowed = 0; | |
2464 | break; | |
2465 | ||
2466 | case '0': | |
2467 | found_zero = 1; | |
2468 | break; | |
2469 | ||
c2cba7a9 RH |
2470 | default: |
2471 | if (REG_CLASS_FROM_LETTER (c) == NO_REGS) | |
2472 | break; | |
2473 | /* FALLTHRU */ | |
2bbd3819 RS |
2474 | case 'p': |
2475 | case 'g': case 'r': | |
3061cc54 RK |
2476 | reg_allowed = 1; |
2477 | break; | |
2bbd3819 RS |
2478 | } |
2479 | ||
3061cc54 RK |
2480 | if (found_zero && ! reg_allowed) |
2481 | num_matching_alts++; | |
2482 | ||
2483 | return num_matching_alts; | |
2bbd3819 RS |
2484 | } |
2485 | \f | |
2486 | void | |
2487 | dump_local_alloc (file) | |
2488 | FILE *file; | |
2489 | { | |
2490 | register int i; | |
2491 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
2492 | if (reg_renumber[i] != -1) | |
2493 | fprintf (file, ";; Register %d in %d.\n", i, reg_renumber[i]); | |
2494 | } |