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50654f6c | 1 | /* Rtl-level induction variable analysis. |
5624e564 | 2 | Copyright (C) 2004-2015 Free Software Foundation, Inc. |
b8698a0f | 3 | |
50654f6c | 4 | This file is part of GCC. |
b8698a0f | 5 | |
50654f6c ZD |
6 | GCC is free software; you can redistribute it and/or modify it |
7 | under the terms of the GNU General Public License as published by the | |
9dcd6f09 | 8 | Free Software Foundation; either version 3, or (at your option) any |
50654f6c | 9 | later version. |
b8698a0f | 10 | |
50654f6c ZD |
11 | GCC is distributed in the hope that it will be useful, but WITHOUT |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
14 | for more details. | |
b8698a0f | 15 | |
50654f6c | 16 | You should have received a copy of the GNU General Public License |
9dcd6f09 NC |
17 | along with GCC; see the file COPYING3. If not see |
18 | <http://www.gnu.org/licenses/>. */ | |
50654f6c | 19 | |
03fd2215 ZD |
20 | /* This is a simple analysis of induction variables of the loop. The major use |
21 | is for determining the number of iterations of a loop for loop unrolling, | |
22 | doloop optimization and branch prediction. The iv information is computed | |
23 | on demand. | |
24 | ||
2b49e1a0 KZ |
25 | Induction variables are analyzed by walking the use-def chains. When |
26 | a basic induction variable (biv) is found, it is cached in the bivs | |
27 | hash table. When register is proved to be a biv, its description | |
28 | is stored to DF_REF_DATA of the def reference. | |
03fd2215 ZD |
29 | |
30 | The analysis works always with one loop -- you must call | |
31 | iv_analysis_loop_init (loop) for it. All the other functions then work with | |
32 | this loop. When you need to work with another loop, just call | |
33 | iv_analysis_loop_init for it. When you no longer need iv analysis, call | |
34 | iv_analysis_done () to clean up the memory. | |
35 | ||
36 | The available functions are: | |
b8698a0f | 37 | |
03fd2215 ZD |
38 | iv_analyze (insn, reg, iv): Stores the description of the induction variable |
39 | corresponding to the use of register REG in INSN to IV. Returns true if | |
40 | REG is an induction variable in INSN. false otherwise. | |
41 | If use of REG is not found in INSN, following insns are scanned (so that | |
42 | we may call this function on insn returned by get_condition). | |
43 | iv_analyze_result (insn, def, iv): Stores to IV the description of the iv | |
44 | corresponding to DEF, which is a register defined in INSN. | |
45 | iv_analyze_expr (insn, rhs, mode, iv): Stores to IV the description of iv | |
46 | corresponding to expression EXPR evaluated at INSN. All registers used bu | |
47 | EXPR must also be used in INSN. | |
6fb5fa3c | 48 | */ |
50654f6c ZD |
49 | |
50 | #include "config.h" | |
51 | #include "system.h" | |
52 | #include "coretypes.h" | |
53 | #include "tm.h" | |
54 | #include "rtl.h" | |
55 | #include "hard-reg-set.h" | |
7932a3db | 56 | #include "obstack.h" |
60393bbc AM |
57 | #include "predict.h" |
58 | #include "vec.h" | |
59 | #include "hashtab.h" | |
60 | #include "hash-set.h" | |
61 | #include "machmode.h" | |
62 | #include "input.h" | |
63 | #include "function.h" | |
64 | #include "dominance.h" | |
65 | #include "cfg.h" | |
50654f6c ZD |
66 | #include "basic-block.h" |
67 | #include "cfgloop.h" | |
40e23961 | 68 | #include "symtab.h" |
36566b39 PK |
69 | #include "flags.h" |
70 | #include "statistics.h" | |
71 | #include "double-int.h" | |
72 | #include "real.h" | |
73 | #include "fixed-value.h" | |
74 | #include "alias.h" | |
75 | #include "wide-int.h" | |
76 | #include "inchash.h" | |
77 | #include "tree.h" | |
78 | #include "insn-config.h" | |
79 | #include "expmed.h" | |
80 | #include "dojump.h" | |
81 | #include "explow.h" | |
82 | #include "calls.h" | |
83 | #include "emit-rtl.h" | |
84 | #include "varasm.h" | |
85 | #include "stmt.h" | |
50654f6c | 86 | #include "expr.h" |
f9cc1a70 | 87 | #include "intl.h" |
718f9c0f | 88 | #include "diagnostic-core.h" |
03fd2215 | 89 | #include "df.h" |
4a8fb1a1 | 90 | #include "hash-table.h" |
7ee2468b | 91 | #include "dumpfile.h" |
4ca29add | 92 | #include "rtl-iter.h" |
50654f6c | 93 | |
03fd2215 | 94 | /* Possible return values of iv_get_reaching_def. */ |
50654f6c | 95 | |
03fd2215 | 96 | enum iv_grd_result |
50654f6c | 97 | { |
03fd2215 ZD |
98 | /* More than one reaching def, or reaching def that does not |
99 | dominate the use. */ | |
100 | GRD_INVALID, | |
50654f6c | 101 | |
03fd2215 ZD |
102 | /* The use is trivial invariant of the loop, i.e. is not changed |
103 | inside the loop. */ | |
104 | GRD_INVARIANT, | |
50654f6c | 105 | |
03fd2215 ZD |
106 | /* The use is reached by initial value and a value from the |
107 | previous iteration. */ | |
108 | GRD_MAYBE_BIV, | |
109 | ||
110 | /* The use has single dominating def. */ | |
111 | GRD_SINGLE_DOM | |
112 | }; | |
113 | ||
114 | /* Information about a biv. */ | |
115 | ||
116 | struct biv_entry | |
117 | { | |
118 | unsigned regno; /* The register of the biv. */ | |
119 | struct rtx_iv iv; /* Value of the biv. */ | |
50654f6c ZD |
120 | }; |
121 | ||
6fb5fa3c DB |
122 | static bool clean_slate = true; |
123 | ||
124 | static unsigned int iv_ref_table_size = 0; | |
125 | ||
126 | /* Table of rtx_ivs indexed by the df_ref uid field. */ | |
127 | static struct rtx_iv ** iv_ref_table; | |
128 | ||
03fd2215 | 129 | /* Induction variable stored at the reference. */ |
c3284718 RS |
130 | #define DF_REF_IV(REF) iv_ref_table[DF_REF_ID (REF)] |
131 | #define DF_REF_IV_SET(REF, IV) iv_ref_table[DF_REF_ID (REF)] = (IV) | |
50654f6c | 132 | |
03fd2215 | 133 | /* The current loop. */ |
50654f6c | 134 | |
03fd2215 | 135 | static struct loop *current_loop; |
50654f6c | 136 | |
4a8fb1a1 LC |
137 | /* Hashtable helper. */ |
138 | ||
139 | struct biv_entry_hasher : typed_free_remove <biv_entry> | |
140 | { | |
67f58944 TS |
141 | typedef biv_entry *value_type; |
142 | typedef rtx_def *compare_type; | |
143 | static inline hashval_t hash (const biv_entry *); | |
144 | static inline bool equal (const biv_entry *, const rtx_def *); | |
4a8fb1a1 LC |
145 | }; |
146 | ||
147 | /* Returns hash value for biv B. */ | |
148 | ||
149 | inline hashval_t | |
67f58944 | 150 | biv_entry_hasher::hash (const biv_entry *b) |
4a8fb1a1 LC |
151 | { |
152 | return b->regno; | |
153 | } | |
154 | ||
155 | /* Compares biv B and register R. */ | |
156 | ||
157 | inline bool | |
67f58944 | 158 | biv_entry_hasher::equal (const biv_entry *b, const rtx_def *r) |
4a8fb1a1 LC |
159 | { |
160 | return b->regno == REGNO (r); | |
161 | } | |
162 | ||
03fd2215 | 163 | /* Bivs of the current loop. */ |
50654f6c | 164 | |
c203e8a7 | 165 | static hash_table<biv_entry_hasher> *bivs; |
50654f6c | 166 | |
1b20d55a | 167 | static bool iv_analyze_op (rtx_insn *, rtx, struct rtx_iv *); |
50654f6c | 168 | |
1c1ad7bb SB |
169 | /* Return the RTX code corresponding to the IV extend code EXTEND. */ |
170 | static inline enum rtx_code | |
171 | iv_extend_to_rtx_code (enum iv_extend_code extend) | |
172 | { | |
173 | switch (extend) | |
174 | { | |
175 | case IV_SIGN_EXTEND: | |
176 | return SIGN_EXTEND; | |
177 | case IV_ZERO_EXTEND: | |
178 | return ZERO_EXTEND; | |
179 | case IV_UNKNOWN_EXTEND: | |
180 | return UNKNOWN; | |
181 | } | |
182 | gcc_unreachable (); | |
183 | } | |
184 | ||
50654f6c ZD |
185 | /* Dumps information about IV to FILE. */ |
186 | ||
187 | extern void dump_iv_info (FILE *, struct rtx_iv *); | |
188 | void | |
189 | dump_iv_info (FILE *file, struct rtx_iv *iv) | |
190 | { | |
191 | if (!iv->base) | |
192 | { | |
193 | fprintf (file, "not simple"); | |
194 | return; | |
195 | } | |
196 | ||
6797f908 ZD |
197 | if (iv->step == const0_rtx |
198 | && !iv->first_special) | |
199 | fprintf (file, "invariant "); | |
50654f6c ZD |
200 | |
201 | print_rtl (file, iv->base); | |
6797f908 ZD |
202 | if (iv->step != const0_rtx) |
203 | { | |
204 | fprintf (file, " + "); | |
205 | print_rtl (file, iv->step); | |
206 | fprintf (file, " * iteration"); | |
207 | } | |
50654f6c ZD |
208 | fprintf (file, " (in %s)", GET_MODE_NAME (iv->mode)); |
209 | ||
210 | if (iv->mode != iv->extend_mode) | |
211 | fprintf (file, " %s to %s", | |
1c1ad7bb | 212 | rtx_name[iv_extend_to_rtx_code (iv->extend)], |
50654f6c ZD |
213 | GET_MODE_NAME (iv->extend_mode)); |
214 | ||
215 | if (iv->mult != const1_rtx) | |
216 | { | |
217 | fprintf (file, " * "); | |
218 | print_rtl (file, iv->mult); | |
219 | } | |
220 | if (iv->delta != const0_rtx) | |
221 | { | |
222 | fprintf (file, " + "); | |
223 | print_rtl (file, iv->delta); | |
224 | } | |
225 | if (iv->first_special) | |
226 | fprintf (file, " (first special)"); | |
227 | } | |
228 | ||
6c3b938d RS |
229 | /* Generates a subreg to get the least significant part of EXPR (in mode |
230 | INNER_MODE) to OUTER_MODE. */ | |
50654f6c | 231 | |
6c3b938d | 232 | rtx |
ef4bddc2 RS |
233 | lowpart_subreg (machine_mode outer_mode, rtx expr, |
234 | machine_mode inner_mode) | |
50654f6c | 235 | { |
6c3b938d RS |
236 | return simplify_gen_subreg (outer_mode, expr, inner_mode, |
237 | subreg_lowpart_offset (outer_mode, inner_mode)); | |
50654f6c ZD |
238 | } |
239 | ||
b8698a0f | 240 | static void |
6fb5fa3c DB |
241 | check_iv_ref_table_size (void) |
242 | { | |
c3284718 | 243 | if (iv_ref_table_size < DF_DEFS_TABLE_SIZE ()) |
6fb5fa3c DB |
244 | { |
245 | unsigned int new_size = DF_DEFS_TABLE_SIZE () + (DF_DEFS_TABLE_SIZE () / 4); | |
d3bfe4de | 246 | iv_ref_table = XRESIZEVEC (struct rtx_iv *, iv_ref_table, new_size); |
b8698a0f | 247 | memset (&iv_ref_table[iv_ref_table_size], 0, |
6fb5fa3c DB |
248 | (new_size - iv_ref_table_size) * sizeof (struct rtx_iv *)); |
249 | iv_ref_table_size = new_size; | |
250 | } | |
251 | } | |
252 | ||
253 | ||
50654f6c ZD |
254 | /* Checks whether REG is a well-behaved register. */ |
255 | ||
256 | static bool | |
257 | simple_reg_p (rtx reg) | |
258 | { | |
259 | unsigned r; | |
260 | ||
261 | if (GET_CODE (reg) == SUBREG) | |
262 | { | |
263 | if (!subreg_lowpart_p (reg)) | |
264 | return false; | |
265 | reg = SUBREG_REG (reg); | |
266 | } | |
267 | ||
268 | if (!REG_P (reg)) | |
269 | return false; | |
270 | ||
271 | r = REGNO (reg); | |
272 | if (HARD_REGISTER_NUM_P (r)) | |
273 | return false; | |
274 | ||
275 | if (GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT) | |
276 | return false; | |
277 | ||
50654f6c ZD |
278 | return true; |
279 | } | |
280 | ||
03fd2215 | 281 | /* Clears the information about ivs stored in df. */ |
50654f6c | 282 | |
03fd2215 ZD |
283 | static void |
284 | clear_iv_info (void) | |
50654f6c | 285 | { |
6fb5fa3c | 286 | unsigned i, n_defs = DF_DEFS_TABLE_SIZE (); |
03fd2215 | 287 | struct rtx_iv *iv; |
50654f6c | 288 | |
6fb5fa3c | 289 | check_iv_ref_table_size (); |
03fd2215 | 290 | for (i = 0; i < n_defs; i++) |
50654f6c | 291 | { |
6fb5fa3c DB |
292 | iv = iv_ref_table[i]; |
293 | if (iv) | |
294 | { | |
295 | free (iv); | |
296 | iv_ref_table[i] = NULL; | |
297 | } | |
50654f6c | 298 | } |
50654f6c | 299 | |
c203e8a7 | 300 | bivs->empty (); |
50654f6c ZD |
301 | } |
302 | ||
50654f6c ZD |
303 | |
304 | /* Prepare the data for an induction variable analysis of a LOOP. */ | |
305 | ||
306 | void | |
307 | iv_analysis_loop_init (struct loop *loop) | |
308 | { | |
03fd2215 | 309 | current_loop = loop; |
50654f6c | 310 | |
03fd2215 | 311 | /* Clear the information from the analysis of the previous loop. */ |
6fb5fa3c | 312 | if (clean_slate) |
7faaba28 | 313 | { |
6fb5fa3c | 314 | df_set_flags (DF_EQ_NOTES + DF_DEFER_INSN_RESCAN); |
c203e8a7 | 315 | bivs = new hash_table<biv_entry_hasher> (10); |
6fb5fa3c | 316 | clean_slate = false; |
7faaba28 ZD |
317 | } |
318 | else | |
319 | clear_iv_info (); | |
50654f6c | 320 | |
6fb5fa3c DB |
321 | /* Get rid of the ud chains before processing the rescans. Then add |
322 | the problem back. */ | |
323 | df_remove_problem (df_chain); | |
324 | df_process_deferred_rescans (); | |
7b19209f | 325 | df_set_flags (DF_RD_PRUNE_DEAD_DEFS); |
6fb5fa3c | 326 | df_chain_add_problem (DF_UD_CHAIN); |
c580edc8 | 327 | df_note_add_problem (); |
7be64667 | 328 | df_analyze_loop (loop); |
6fb5fa3c | 329 | if (dump_file) |
ffd640ed | 330 | df_dump_region (dump_file); |
6fb5fa3c DB |
331 | |
332 | check_iv_ref_table_size (); | |
50654f6c ZD |
333 | } |
334 | ||
03fd2215 ZD |
335 | /* Finds the definition of REG that dominates loop latch and stores |
336 | it to DEF. Returns false if there is not a single definition | |
7002f3bd | 337 | dominating the latch. If REG has no definition in loop, DEF |
03fd2215 | 338 | is set to NULL and true is returned. */ |
50654f6c | 339 | |
03fd2215 | 340 | static bool |
57512f53 | 341 | latch_dominating_def (rtx reg, df_ref *def) |
50654f6c | 342 | { |
57512f53 | 343 | df_ref single_rd = NULL, adef; |
7002f3bd | 344 | unsigned regno = REGNO (reg); |
6fb5fa3c | 345 | struct df_rd_bb_info *bb_info = DF_RD_BB_INFO (current_loop->latch); |
50654f6c | 346 | |
57512f53 | 347 | for (adef = DF_REG_DEF_CHAIN (regno); adef; adef = DF_REF_NEXT_REG (adef)) |
50654f6c | 348 | { |
57512f53 | 349 | if (!bitmap_bit_p (df->blocks_to_analyze, DF_REF_BBNO (adef)) |
b33a91c9 | 350 | || !bitmap_bit_p (&bb_info->out, DF_REF_ID (adef))) |
03fd2215 ZD |
351 | continue; |
352 | ||
7002f3bd | 353 | /* More than one reaching definition. */ |
03fd2215 | 354 | if (single_rd) |
7002f3bd IZ |
355 | return false; |
356 | ||
357 | if (!just_once_each_iteration_p (current_loop, DF_REF_BB (adef))) | |
358 | return false; | |
03fd2215 ZD |
359 | |
360 | single_rd = adef; | |
50654f6c | 361 | } |
50654f6c | 362 | |
03fd2215 ZD |
363 | *def = single_rd; |
364 | return true; | |
365 | } | |
50654f6c | 366 | |
03fd2215 | 367 | /* Gets definition of REG reaching its use in INSN and stores it to DEF. */ |
50654f6c | 368 | |
03fd2215 | 369 | static enum iv_grd_result |
1b20d55a | 370 | iv_get_reaching_def (rtx_insn *insn, rtx reg, df_ref *def) |
03fd2215 | 371 | { |
7002f3bd | 372 | df_ref use, adef; |
03fd2215 | 373 | basic_block def_bb, use_bb; |
1b20d55a | 374 | rtx_insn *def_insn; |
7002f3bd | 375 | bool dom_p; |
b8698a0f | 376 | |
03fd2215 ZD |
377 | *def = NULL; |
378 | if (!simple_reg_p (reg)) | |
379 | return GRD_INVALID; | |
380 | if (GET_CODE (reg) == SUBREG) | |
381 | reg = SUBREG_REG (reg); | |
382 | gcc_assert (REG_P (reg)); | |
50654f6c | 383 | |
6fb5fa3c | 384 | use = df_find_use (insn, reg); |
03fd2215 | 385 | gcc_assert (use != NULL); |
50654f6c | 386 | |
03fd2215 ZD |
387 | if (!DF_REF_CHAIN (use)) |
388 | return GRD_INVARIANT; | |
50654f6c | 389 | |
7002f3bd | 390 | /* More than one reaching def. */ |
03fd2215 | 391 | if (DF_REF_CHAIN (use)->next) |
7002f3bd | 392 | return GRD_INVALID; |
dfd3a76c | 393 | |
7002f3bd | 394 | adef = DF_REF_CHAIN (use)->ref; |
6848da6a ZD |
395 | |
396 | /* We do not handle setting only part of the register. */ | |
57512f53 | 397 | if (DF_REF_FLAGS (adef) & DF_REF_READ_WRITE) |
6848da6a ZD |
398 | return GRD_INVALID; |
399 | ||
03fd2215 ZD |
400 | def_insn = DF_REF_INSN (adef); |
401 | def_bb = DF_REF_BB (adef); | |
402 | use_bb = BLOCK_FOR_INSN (insn); | |
50654f6c | 403 | |
03fd2215 | 404 | if (use_bb == def_bb) |
6fb5fa3c | 405 | dom_p = (DF_INSN_LUID (def_insn) < DF_INSN_LUID (insn)); |
03fd2215 ZD |
406 | else |
407 | dom_p = dominated_by_p (CDI_DOMINATORS, use_bb, def_bb); | |
50654f6c | 408 | |
03fd2215 ZD |
409 | if (dom_p) |
410 | { | |
411 | *def = adef; | |
412 | return GRD_SINGLE_DOM; | |
50654f6c | 413 | } |
03fd2215 ZD |
414 | |
415 | /* The definition does not dominate the use. This is still OK if | |
416 | this may be a use of a biv, i.e. if the def_bb dominates loop | |
7002f3bd IZ |
417 | latch. */ |
418 | if (just_once_each_iteration_p (current_loop, def_bb)) | |
03fd2215 ZD |
419 | return GRD_MAYBE_BIV; |
420 | ||
421 | return GRD_INVALID; | |
50654f6c ZD |
422 | } |
423 | ||
424 | /* Sets IV to invariant CST in MODE. Always returns true (just for | |
425 | consistency with other iv manipulation functions that may fail). */ | |
426 | ||
427 | static bool | |
ef4bddc2 | 428 | iv_constant (struct rtx_iv *iv, rtx cst, machine_mode mode) |
50654f6c ZD |
429 | { |
430 | if (mode == VOIDmode) | |
431 | mode = GET_MODE (cst); | |
432 | ||
50654f6c ZD |
433 | iv->mode = mode; |
434 | iv->base = cst; | |
435 | iv->step = const0_rtx; | |
436 | iv->first_special = false; | |
1c1ad7bb | 437 | iv->extend = IV_UNKNOWN_EXTEND; |
50654f6c ZD |
438 | iv->extend_mode = iv->mode; |
439 | iv->delta = const0_rtx; | |
440 | iv->mult = const1_rtx; | |
441 | ||
442 | return true; | |
443 | } | |
444 | ||
445 | /* Evaluates application of subreg to MODE on IV. */ | |
446 | ||
447 | static bool | |
ef4bddc2 | 448 | iv_subreg (struct rtx_iv *iv, machine_mode mode) |
50654f6c | 449 | { |
6797f908 ZD |
450 | /* If iv is invariant, just calculate the new value. */ |
451 | if (iv->step == const0_rtx | |
452 | && !iv->first_special) | |
453 | { | |
454 | rtx val = get_iv_value (iv, const0_rtx); | |
50fae5a6 JJ |
455 | val = lowpart_subreg (mode, val, |
456 | iv->extend == IV_UNKNOWN_EXTEND | |
457 | ? iv->mode : iv->extend_mode); | |
6797f908 ZD |
458 | |
459 | iv->base = val; | |
1c1ad7bb | 460 | iv->extend = IV_UNKNOWN_EXTEND; |
6797f908 ZD |
461 | iv->mode = iv->extend_mode = mode; |
462 | iv->delta = const0_rtx; | |
463 | iv->mult = const1_rtx; | |
464 | return true; | |
465 | } | |
466 | ||
50654f6c ZD |
467 | if (iv->extend_mode == mode) |
468 | return true; | |
469 | ||
470 | if (GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (iv->mode)) | |
471 | return false; | |
472 | ||
1c1ad7bb | 473 | iv->extend = IV_UNKNOWN_EXTEND; |
50654f6c ZD |
474 | iv->mode = mode; |
475 | ||
476 | iv->base = simplify_gen_binary (PLUS, iv->extend_mode, iv->delta, | |
477 | simplify_gen_binary (MULT, iv->extend_mode, | |
478 | iv->base, iv->mult)); | |
479 | iv->step = simplify_gen_binary (MULT, iv->extend_mode, iv->step, iv->mult); | |
480 | iv->mult = const1_rtx; | |
481 | iv->delta = const0_rtx; | |
482 | iv->first_special = false; | |
483 | ||
484 | return true; | |
485 | } | |
486 | ||
487 | /* Evaluates application of EXTEND to MODE on IV. */ | |
488 | ||
489 | static bool | |
ef4bddc2 | 490 | iv_extend (struct rtx_iv *iv, enum iv_extend_code extend, machine_mode mode) |
50654f6c | 491 | { |
6797f908 ZD |
492 | /* If iv is invariant, just calculate the new value. */ |
493 | if (iv->step == const0_rtx | |
494 | && !iv->first_special) | |
495 | { | |
496 | rtx val = get_iv_value (iv, const0_rtx); | |
50fae5a6 JJ |
497 | if (iv->extend_mode != iv->mode |
498 | && iv->extend != IV_UNKNOWN_EXTEND | |
499 | && iv->extend != extend) | |
500 | val = lowpart_subreg (iv->mode, val, iv->extend_mode); | |
1c1ad7bb | 501 | val = simplify_gen_unary (iv_extend_to_rtx_code (extend), mode, |
50fae5a6 JJ |
502 | val, |
503 | iv->extend == extend | |
504 | ? iv->extend_mode : iv->mode); | |
6797f908 | 505 | iv->base = val; |
1c1ad7bb | 506 | iv->extend = IV_UNKNOWN_EXTEND; |
6797f908 ZD |
507 | iv->mode = iv->extend_mode = mode; |
508 | iv->delta = const0_rtx; | |
509 | iv->mult = const1_rtx; | |
510 | return true; | |
511 | } | |
512 | ||
50654f6c ZD |
513 | if (mode != iv->extend_mode) |
514 | return false; | |
515 | ||
1c1ad7bb | 516 | if (iv->extend != IV_UNKNOWN_EXTEND |
50654f6c ZD |
517 | && iv->extend != extend) |
518 | return false; | |
519 | ||
520 | iv->extend = extend; | |
521 | ||
522 | return true; | |
523 | } | |
524 | ||
525 | /* Evaluates negation of IV. */ | |
526 | ||
527 | static bool | |
528 | iv_neg (struct rtx_iv *iv) | |
529 | { | |
1c1ad7bb | 530 | if (iv->extend == IV_UNKNOWN_EXTEND) |
50654f6c ZD |
531 | { |
532 | iv->base = simplify_gen_unary (NEG, iv->extend_mode, | |
533 | iv->base, iv->extend_mode); | |
534 | iv->step = simplify_gen_unary (NEG, iv->extend_mode, | |
535 | iv->step, iv->extend_mode); | |
536 | } | |
537 | else | |
538 | { | |
539 | iv->delta = simplify_gen_unary (NEG, iv->extend_mode, | |
540 | iv->delta, iv->extend_mode); | |
541 | iv->mult = simplify_gen_unary (NEG, iv->extend_mode, | |
542 | iv->mult, iv->extend_mode); | |
543 | } | |
544 | ||
545 | return true; | |
546 | } | |
547 | ||
548 | /* Evaluates addition or subtraction (according to OP) of IV1 to IV0. */ | |
549 | ||
550 | static bool | |
551 | iv_add (struct rtx_iv *iv0, struct rtx_iv *iv1, enum rtx_code op) | |
552 | { | |
ef4bddc2 | 553 | machine_mode mode; |
50654f6c ZD |
554 | rtx arg; |
555 | ||
a1105617 | 556 | /* Extend the constant to extend_mode of the other operand if necessary. */ |
1c1ad7bb | 557 | if (iv0->extend == IV_UNKNOWN_EXTEND |
50654f6c ZD |
558 | && iv0->mode == iv0->extend_mode |
559 | && iv0->step == const0_rtx | |
560 | && GET_MODE_SIZE (iv0->extend_mode) < GET_MODE_SIZE (iv1->extend_mode)) | |
561 | { | |
562 | iv0->extend_mode = iv1->extend_mode; | |
563 | iv0->base = simplify_gen_unary (ZERO_EXTEND, iv0->extend_mode, | |
564 | iv0->base, iv0->mode); | |
565 | } | |
1c1ad7bb | 566 | if (iv1->extend == IV_UNKNOWN_EXTEND |
50654f6c ZD |
567 | && iv1->mode == iv1->extend_mode |
568 | && iv1->step == const0_rtx | |
569 | && GET_MODE_SIZE (iv1->extend_mode) < GET_MODE_SIZE (iv0->extend_mode)) | |
570 | { | |
571 | iv1->extend_mode = iv0->extend_mode; | |
572 | iv1->base = simplify_gen_unary (ZERO_EXTEND, iv1->extend_mode, | |
573 | iv1->base, iv1->mode); | |
574 | } | |
575 | ||
576 | mode = iv0->extend_mode; | |
577 | if (mode != iv1->extend_mode) | |
578 | return false; | |
579 | ||
1c1ad7bb SB |
580 | if (iv0->extend == IV_UNKNOWN_EXTEND |
581 | && iv1->extend == IV_UNKNOWN_EXTEND) | |
50654f6c ZD |
582 | { |
583 | if (iv0->mode != iv1->mode) | |
584 | return false; | |
585 | ||
586 | iv0->base = simplify_gen_binary (op, mode, iv0->base, iv1->base); | |
587 | iv0->step = simplify_gen_binary (op, mode, iv0->step, iv1->step); | |
588 | ||
589 | return true; | |
590 | } | |
591 | ||
592 | /* Handle addition of constant. */ | |
1c1ad7bb | 593 | if (iv1->extend == IV_UNKNOWN_EXTEND |
50654f6c ZD |
594 | && iv1->mode == mode |
595 | && iv1->step == const0_rtx) | |
596 | { | |
597 | iv0->delta = simplify_gen_binary (op, mode, iv0->delta, iv1->base); | |
598 | return true; | |
599 | } | |
600 | ||
1c1ad7bb | 601 | if (iv0->extend == IV_UNKNOWN_EXTEND |
50654f6c ZD |
602 | && iv0->mode == mode |
603 | && iv0->step == const0_rtx) | |
604 | { | |
605 | arg = iv0->base; | |
606 | *iv0 = *iv1; | |
607 | if (op == MINUS | |
608 | && !iv_neg (iv0)) | |
609 | return false; | |
610 | ||
611 | iv0->delta = simplify_gen_binary (PLUS, mode, iv0->delta, arg); | |
612 | return true; | |
613 | } | |
614 | ||
615 | return false; | |
616 | } | |
617 | ||
618 | /* Evaluates multiplication of IV by constant CST. */ | |
619 | ||
620 | static bool | |
621 | iv_mult (struct rtx_iv *iv, rtx mby) | |
622 | { | |
ef4bddc2 | 623 | machine_mode mode = iv->extend_mode; |
50654f6c ZD |
624 | |
625 | if (GET_MODE (mby) != VOIDmode | |
626 | && GET_MODE (mby) != mode) | |
627 | return false; | |
628 | ||
1c1ad7bb | 629 | if (iv->extend == IV_UNKNOWN_EXTEND) |
50654f6c ZD |
630 | { |
631 | iv->base = simplify_gen_binary (MULT, mode, iv->base, mby); | |
632 | iv->step = simplify_gen_binary (MULT, mode, iv->step, mby); | |
633 | } | |
634 | else | |
635 | { | |
636 | iv->delta = simplify_gen_binary (MULT, mode, iv->delta, mby); | |
637 | iv->mult = simplify_gen_binary (MULT, mode, iv->mult, mby); | |
638 | } | |
639 | ||
640 | return true; | |
641 | } | |
642 | ||
abe0d774 RE |
643 | /* Evaluates shift of IV by constant CST. */ |
644 | ||
645 | static bool | |
646 | iv_shift (struct rtx_iv *iv, rtx mby) | |
647 | { | |
ef4bddc2 | 648 | machine_mode mode = iv->extend_mode; |
abe0d774 RE |
649 | |
650 | if (GET_MODE (mby) != VOIDmode | |
651 | && GET_MODE (mby) != mode) | |
652 | return false; | |
653 | ||
1c1ad7bb | 654 | if (iv->extend == IV_UNKNOWN_EXTEND) |
abe0d774 RE |
655 | { |
656 | iv->base = simplify_gen_binary (ASHIFT, mode, iv->base, mby); | |
657 | iv->step = simplify_gen_binary (ASHIFT, mode, iv->step, mby); | |
658 | } | |
659 | else | |
660 | { | |
661 | iv->delta = simplify_gen_binary (ASHIFT, mode, iv->delta, mby); | |
662 | iv->mult = simplify_gen_binary (ASHIFT, mode, iv->mult, mby); | |
663 | } | |
664 | ||
665 | return true; | |
666 | } | |
667 | ||
50654f6c | 668 | /* The recursive part of get_biv_step. Gets the value of the single value |
03fd2215 | 669 | defined by DEF wrto initial value of REG inside loop, in shape described |
50654f6c ZD |
670 | at get_biv_step. */ |
671 | ||
672 | static bool | |
57512f53 | 673 | get_biv_step_1 (df_ref def, rtx reg, |
ef4bddc2 RS |
674 | rtx *inner_step, machine_mode *inner_mode, |
675 | enum iv_extend_code *extend, machine_mode outer_mode, | |
50654f6c ZD |
676 | rtx *outer_step) |
677 | { | |
3c3f4b56 | 678 | rtx set, rhs, op0 = NULL_RTX, op1 = NULL_RTX; |
03fd2215 | 679 | rtx next, nextr, tmp; |
50654f6c | 680 | enum rtx_code code; |
1b20d55a | 681 | rtx_insn *insn = DF_REF_INSN (def); |
57512f53 | 682 | df_ref next_def; |
03fd2215 | 683 | enum iv_grd_result res; |
50654f6c ZD |
684 | |
685 | set = single_set (insn); | |
03fd2215 ZD |
686 | if (!set) |
687 | return false; | |
688 | ||
50654f6c | 689 | rhs = find_reg_equal_equiv_note (insn); |
0aea6467 ZD |
690 | if (rhs) |
691 | rhs = XEXP (rhs, 0); | |
692 | else | |
50654f6c | 693 | rhs = SET_SRC (set); |
50654f6c ZD |
694 | |
695 | code = GET_CODE (rhs); | |
696 | switch (code) | |
697 | { | |
698 | case SUBREG: | |
699 | case REG: | |
700 | next = rhs; | |
701 | break; | |
702 | ||
703 | case PLUS: | |
704 | case MINUS: | |
705 | op0 = XEXP (rhs, 0); | |
706 | op1 = XEXP (rhs, 1); | |
707 | ||
708 | if (code == PLUS && CONSTANT_P (op0)) | |
709 | { | |
710 | tmp = op0; op0 = op1; op1 = tmp; | |
711 | } | |
712 | ||
713 | if (!simple_reg_p (op0) | |
714 | || !CONSTANT_P (op1)) | |
715 | return false; | |
716 | ||
717 | if (GET_MODE (rhs) != outer_mode) | |
718 | { | |
719 | /* ppc64 uses expressions like | |
720 | ||
721 | (set x:SI (plus:SI (subreg:SI y:DI) 1)). | |
722 | ||
723 | this is equivalent to | |
724 | ||
725 | (set x':DI (plus:DI y:DI 1)) | |
726 | (set x:SI (subreg:SI (x':DI)). */ | |
727 | if (GET_CODE (op0) != SUBREG) | |
728 | return false; | |
729 | if (GET_MODE (SUBREG_REG (op0)) != outer_mode) | |
730 | return false; | |
731 | } | |
732 | ||
733 | next = op0; | |
734 | break; | |
735 | ||
736 | case SIGN_EXTEND: | |
737 | case ZERO_EXTEND: | |
738 | if (GET_MODE (rhs) != outer_mode) | |
739 | return false; | |
740 | ||
741 | op0 = XEXP (rhs, 0); | |
742 | if (!simple_reg_p (op0)) | |
743 | return false; | |
744 | ||
745 | next = op0; | |
746 | break; | |
747 | ||
748 | default: | |
749 | return false; | |
750 | } | |
751 | ||
752 | if (GET_CODE (next) == SUBREG) | |
753 | { | |
754 | if (!subreg_lowpart_p (next)) | |
755 | return false; | |
756 | ||
757 | nextr = SUBREG_REG (next); | |
758 | if (GET_MODE (nextr) != outer_mode) | |
759 | return false; | |
760 | } | |
761 | else | |
762 | nextr = next; | |
763 | ||
03fd2215 ZD |
764 | res = iv_get_reaching_def (insn, nextr, &next_def); |
765 | ||
766 | if (res == GRD_INVALID || res == GRD_INVARIANT) | |
50654f6c ZD |
767 | return false; |
768 | ||
03fd2215 | 769 | if (res == GRD_MAYBE_BIV) |
50654f6c ZD |
770 | { |
771 | if (!rtx_equal_p (nextr, reg)) | |
772 | return false; | |
773 | ||
774 | *inner_step = const0_rtx; | |
1c1ad7bb | 775 | *extend = IV_UNKNOWN_EXTEND; |
50654f6c ZD |
776 | *inner_mode = outer_mode; |
777 | *outer_step = const0_rtx; | |
778 | } | |
03fd2215 | 779 | else if (!get_biv_step_1 (next_def, reg, |
50654f6c ZD |
780 | inner_step, inner_mode, extend, outer_mode, |
781 | outer_step)) | |
782 | return false; | |
783 | ||
784 | if (GET_CODE (next) == SUBREG) | |
785 | { | |
ef4bddc2 | 786 | machine_mode amode = GET_MODE (next); |
50654f6c ZD |
787 | |
788 | if (GET_MODE_SIZE (amode) > GET_MODE_SIZE (*inner_mode)) | |
789 | return false; | |
790 | ||
791 | *inner_mode = amode; | |
792 | *inner_step = simplify_gen_binary (PLUS, outer_mode, | |
793 | *inner_step, *outer_step); | |
794 | *outer_step = const0_rtx; | |
1c1ad7bb | 795 | *extend = IV_UNKNOWN_EXTEND; |
50654f6c ZD |
796 | } |
797 | ||
798 | switch (code) | |
799 | { | |
800 | case REG: | |
801 | case SUBREG: | |
802 | break; | |
803 | ||
804 | case PLUS: | |
805 | case MINUS: | |
806 | if (*inner_mode == outer_mode | |
807 | /* See comment in previous switch. */ | |
808 | || GET_MODE (rhs) != outer_mode) | |
809 | *inner_step = simplify_gen_binary (code, outer_mode, | |
810 | *inner_step, op1); | |
811 | else | |
812 | *outer_step = simplify_gen_binary (code, outer_mode, | |
813 | *outer_step, op1); | |
814 | break; | |
815 | ||
816 | case SIGN_EXTEND: | |
817 | case ZERO_EXTEND: | |
b5e624c6 | 818 | gcc_assert (GET_MODE (op0) == *inner_mode |
1c1ad7bb | 819 | && *extend == IV_UNKNOWN_EXTEND |
b5e624c6 | 820 | && *outer_step == const0_rtx); |
50654f6c | 821 | |
1c1ad7bb | 822 | *extend = (code == SIGN_EXTEND) ? IV_SIGN_EXTEND : IV_ZERO_EXTEND; |
50654f6c ZD |
823 | break; |
824 | ||
825 | default: | |
03fd2215 | 826 | return false; |
50654f6c ZD |
827 | } |
828 | ||
829 | return true; | |
830 | } | |
831 | ||
832 | /* Gets the operation on register REG inside loop, in shape | |
833 | ||
834 | OUTER_STEP + EXTEND_{OUTER_MODE} (SUBREG_{INNER_MODE} (REG + INNER_STEP)) | |
835 | ||
03fd2215 ZD |
836 | If the operation cannot be described in this shape, return false. |
837 | LAST_DEF is the definition of REG that dominates loop latch. */ | |
50654f6c ZD |
838 | |
839 | static bool | |
57512f53 | 840 | get_biv_step (df_ref last_def, rtx reg, rtx *inner_step, |
ef4bddc2 RS |
841 | machine_mode *inner_mode, enum iv_extend_code *extend, |
842 | machine_mode *outer_mode, rtx *outer_step) | |
50654f6c ZD |
843 | { |
844 | *outer_mode = GET_MODE (reg); | |
845 | ||
03fd2215 | 846 | if (!get_biv_step_1 (last_def, reg, |
50654f6c ZD |
847 | inner_step, inner_mode, extend, *outer_mode, |
848 | outer_step)) | |
849 | return false; | |
850 | ||
1c1ad7bb | 851 | gcc_assert ((*inner_mode == *outer_mode) != (*extend != IV_UNKNOWN_EXTEND)); |
b5e624c6 | 852 | gcc_assert (*inner_mode != *outer_mode || *outer_step == const0_rtx); |
50654f6c ZD |
853 | |
854 | return true; | |
855 | } | |
856 | ||
03fd2215 ZD |
857 | /* Records information that DEF is induction variable IV. */ |
858 | ||
859 | static void | |
57512f53 | 860 | record_iv (df_ref def, struct rtx_iv *iv) |
03fd2215 | 861 | { |
5ed6ace5 | 862 | struct rtx_iv *recorded_iv = XNEW (struct rtx_iv); |
03fd2215 ZD |
863 | |
864 | *recorded_iv = *iv; | |
6fb5fa3c | 865 | check_iv_ref_table_size (); |
03fd2215 ZD |
866 | DF_REF_IV_SET (def, recorded_iv); |
867 | } | |
868 | ||
869 | /* If DEF was already analyzed for bivness, store the description of the biv to | |
870 | IV and return true. Otherwise return false. */ | |
871 | ||
872 | static bool | |
873 | analyzed_for_bivness_p (rtx def, struct rtx_iv *iv) | |
874 | { | |
c203e8a7 | 875 | struct biv_entry *biv = bivs->find_with_hash (def, REGNO (def)); |
03fd2215 ZD |
876 | |
877 | if (!biv) | |
878 | return false; | |
879 | ||
880 | *iv = biv->iv; | |
881 | return true; | |
882 | } | |
883 | ||
884 | static void | |
885 | record_biv (rtx def, struct rtx_iv *iv) | |
886 | { | |
5ed6ace5 | 887 | struct biv_entry *biv = XNEW (struct biv_entry); |
c203e8a7 | 888 | biv_entry **slot = bivs->find_slot_with_hash (def, REGNO (def), INSERT); |
03fd2215 ZD |
889 | |
890 | biv->regno = REGNO (def); | |
891 | biv->iv = *iv; | |
892 | gcc_assert (!*slot); | |
893 | *slot = biv; | |
894 | } | |
895 | ||
50654f6c ZD |
896 | /* Determines whether DEF is a biv and if so, stores its description |
897 | to *IV. */ | |
898 | ||
899 | static bool | |
6d4e0ecc | 900 | iv_analyze_biv (rtx def, struct rtx_iv *iv) |
50654f6c | 901 | { |
50654f6c | 902 | rtx inner_step, outer_step; |
ef4bddc2 | 903 | machine_mode inner_mode, outer_mode; |
1c1ad7bb | 904 | enum iv_extend_code extend; |
57512f53 | 905 | df_ref last_def; |
50654f6c | 906 | |
c263766c | 907 | if (dump_file) |
50654f6c | 908 | { |
cc9795d4 | 909 | fprintf (dump_file, "Analyzing "); |
c263766c RH |
910 | print_rtl (dump_file, def); |
911 | fprintf (dump_file, " for bivness.\n"); | |
50654f6c | 912 | } |
b8698a0f | 913 | |
50654f6c ZD |
914 | if (!REG_P (def)) |
915 | { | |
916 | if (!CONSTANT_P (def)) | |
917 | return false; | |
918 | ||
919 | return iv_constant (iv, def, VOIDmode); | |
920 | } | |
921 | ||
03fd2215 | 922 | if (!latch_dominating_def (def, &last_def)) |
50654f6c | 923 | { |
c263766c RH |
924 | if (dump_file) |
925 | fprintf (dump_file, " not simple.\n"); | |
50654f6c ZD |
926 | return false; |
927 | } | |
928 | ||
03fd2215 ZD |
929 | if (!last_def) |
930 | return iv_constant (iv, def, VOIDmode); | |
931 | ||
932 | if (analyzed_for_bivness_p (def, iv)) | |
50654f6c | 933 | { |
c263766c RH |
934 | if (dump_file) |
935 | fprintf (dump_file, " already analysed.\n"); | |
50654f6c ZD |
936 | return iv->base != NULL_RTX; |
937 | } | |
938 | ||
03fd2215 | 939 | if (!get_biv_step (last_def, def, &inner_step, &inner_mode, &extend, |
50654f6c ZD |
940 | &outer_mode, &outer_step)) |
941 | { | |
942 | iv->base = NULL_RTX; | |
943 | goto end; | |
944 | } | |
945 | ||
946 | /* Loop transforms base to es (base + inner_step) + outer_step, | |
947 | where es means extend of subreg between inner_mode and outer_mode. | |
948 | The corresponding induction variable is | |
949 | ||
950 | es ((base - outer_step) + i * (inner_step + outer_step)) + outer_step */ | |
951 | ||
952 | iv->base = simplify_gen_binary (MINUS, outer_mode, def, outer_step); | |
953 | iv->step = simplify_gen_binary (PLUS, outer_mode, inner_step, outer_step); | |
954 | iv->mode = inner_mode; | |
955 | iv->extend_mode = outer_mode; | |
956 | iv->extend = extend; | |
957 | iv->mult = const1_rtx; | |
958 | iv->delta = outer_step; | |
959 | iv->first_special = inner_mode != outer_mode; | |
960 | ||
c263766c RH |
961 | end: |
962 | if (dump_file) | |
50654f6c | 963 | { |
c263766c RH |
964 | fprintf (dump_file, " "); |
965 | dump_iv_info (dump_file, iv); | |
966 | fprintf (dump_file, "\n"); | |
50654f6c ZD |
967 | } |
968 | ||
03fd2215 | 969 | record_biv (def, iv); |
50654f6c ZD |
970 | return iv->base != NULL_RTX; |
971 | } | |
972 | ||
b8698a0f | 973 | /* Analyzes expression RHS used at INSN and stores the result to *IV. |
03fd2215 | 974 | The mode of the induction variable is MODE. */ |
50654f6c | 975 | |
03fd2215 | 976 | bool |
ef4bddc2 | 977 | iv_analyze_expr (rtx_insn *insn, rtx rhs, machine_mode mode, |
1b20d55a | 978 | struct rtx_iv *iv) |
50654f6c | 979 | { |
03fd2215 ZD |
980 | rtx mby = NULL_RTX, tmp; |
981 | rtx op0 = NULL_RTX, op1 = NULL_RTX; | |
982 | struct rtx_iv iv0, iv1; | |
983 | enum rtx_code code = GET_CODE (rhs); | |
ef4bddc2 | 984 | machine_mode omode = mode; |
50654f6c | 985 | |
03fd2215 ZD |
986 | iv->mode = VOIDmode; |
987 | iv->base = NULL_RTX; | |
988 | iv->step = NULL_RTX; | |
50654f6c | 989 | |
03fd2215 | 990 | gcc_assert (GET_MODE (rhs) == mode || GET_MODE (rhs) == VOIDmode); |
50654f6c | 991 | |
03fd2215 ZD |
992 | if (CONSTANT_P (rhs) |
993 | || REG_P (rhs) | |
994 | || code == SUBREG) | |
50654f6c | 995 | { |
03fd2215 ZD |
996 | if (!iv_analyze_op (insn, rhs, iv)) |
997 | return false; | |
b8698a0f | 998 | |
03fd2215 | 999 | if (iv->mode == VOIDmode) |
50654f6c | 1000 | { |
03fd2215 ZD |
1001 | iv->mode = mode; |
1002 | iv->extend_mode = mode; | |
50654f6c | 1003 | } |
03fd2215 ZD |
1004 | |
1005 | return true; | |
50654f6c ZD |
1006 | } |
1007 | ||
03fd2215 | 1008 | switch (code) |
50654f6c | 1009 | { |
03fd2215 ZD |
1010 | case REG: |
1011 | op0 = rhs; | |
1012 | break; | |
50654f6c | 1013 | |
03fd2215 ZD |
1014 | case SIGN_EXTEND: |
1015 | case ZERO_EXTEND: | |
1016 | case NEG: | |
1017 | op0 = XEXP (rhs, 0); | |
1018 | omode = GET_MODE (op0); | |
1019 | break; | |
1020 | ||
1021 | case PLUS: | |
1022 | case MINUS: | |
1023 | op0 = XEXP (rhs, 0); | |
1024 | op1 = XEXP (rhs, 1); | |
1025 | break; | |
1026 | ||
1027 | case MULT: | |
1028 | op0 = XEXP (rhs, 0); | |
1029 | mby = XEXP (rhs, 1); | |
1030 | if (!CONSTANT_P (mby)) | |
50654f6c | 1031 | { |
03fd2215 ZD |
1032 | tmp = op0; |
1033 | op0 = mby; | |
1034 | mby = tmp; | |
50654f6c | 1035 | } |
03fd2215 ZD |
1036 | if (!CONSTANT_P (mby)) |
1037 | return false; | |
1038 | break; | |
50654f6c | 1039 | |
03fd2215 ZD |
1040 | case ASHIFT: |
1041 | op0 = XEXP (rhs, 0); | |
1042 | mby = XEXP (rhs, 1); | |
1043 | if (!CONSTANT_P (mby)) | |
1044 | return false; | |
1045 | break; | |
1046 | ||
1047 | default: | |
50654f6c ZD |
1048 | return false; |
1049 | } | |
1050 | ||
03fd2215 ZD |
1051 | if (op0 |
1052 | && !iv_analyze_expr (insn, op0, omode, &iv0)) | |
1053 | return false; | |
50654f6c | 1054 | |
03fd2215 ZD |
1055 | if (op1 |
1056 | && !iv_analyze_expr (insn, op1, omode, &iv1)) | |
50654f6c ZD |
1057 | return false; |
1058 | ||
03fd2215 | 1059 | switch (code) |
50654f6c | 1060 | { |
03fd2215 | 1061 | case SIGN_EXTEND: |
1c1ad7bb SB |
1062 | if (!iv_extend (&iv0, IV_SIGN_EXTEND, mode)) |
1063 | return false; | |
1064 | break; | |
1065 | ||
03fd2215 | 1066 | case ZERO_EXTEND: |
1c1ad7bb | 1067 | if (!iv_extend (&iv0, IV_ZERO_EXTEND, mode)) |
03fd2215 ZD |
1068 | return false; |
1069 | break; | |
1070 | ||
1071 | case NEG: | |
1072 | if (!iv_neg (&iv0)) | |
50654f6c | 1073 | return false; |
03fd2215 | 1074 | break; |
50654f6c | 1075 | |
03fd2215 ZD |
1076 | case PLUS: |
1077 | case MINUS: | |
1078 | if (!iv_add (&iv0, &iv1, code)) | |
50654f6c | 1079 | return false; |
03fd2215 | 1080 | break; |
50654f6c | 1081 | |
03fd2215 ZD |
1082 | case MULT: |
1083 | if (!iv_mult (&iv0, mby)) | |
1084 | return false; | |
1085 | break; | |
1086 | ||
1087 | case ASHIFT: | |
1088 | if (!iv_shift (&iv0, mby)) | |
1089 | return false; | |
1090 | break; | |
1091 | ||
1092 | default: | |
1093 | break; | |
50654f6c ZD |
1094 | } |
1095 | ||
03fd2215 ZD |
1096 | *iv = iv0; |
1097 | return iv->base != NULL_RTX; | |
1098 | } | |
1099 | ||
1100 | /* Analyzes iv DEF and stores the result to *IV. */ | |
1101 | ||
1102 | static bool | |
57512f53 | 1103 | iv_analyze_def (df_ref def, struct rtx_iv *iv) |
03fd2215 | 1104 | { |
1b20d55a | 1105 | rtx_insn *insn = DF_REF_INSN (def); |
03fd2215 ZD |
1106 | rtx reg = DF_REF_REG (def); |
1107 | rtx set, rhs; | |
50654f6c | 1108 | |
c263766c | 1109 | if (dump_file) |
50654f6c | 1110 | { |
4dad0aca | 1111 | fprintf (dump_file, "Analyzing def of "); |
03fd2215 | 1112 | print_rtl (dump_file, reg); |
c263766c RH |
1113 | fprintf (dump_file, " in insn "); |
1114 | print_rtl_single (dump_file, insn); | |
50654f6c | 1115 | } |
b8698a0f | 1116 | |
6fb5fa3c | 1117 | check_iv_ref_table_size (); |
03fd2215 | 1118 | if (DF_REF_IV (def)) |
50654f6c | 1119 | { |
c263766c RH |
1120 | if (dump_file) |
1121 | fprintf (dump_file, " already analysed.\n"); | |
03fd2215 | 1122 | *iv = *DF_REF_IV (def); |
50654f6c ZD |
1123 | return iv->base != NULL_RTX; |
1124 | } | |
1125 | ||
1126 | iv->mode = VOIDmode; | |
1127 | iv->base = NULL_RTX; | |
1128 | iv->step = NULL_RTX; | |
1129 | ||
6fb5fa3c DB |
1130 | if (!REG_P (reg)) |
1131 | return false; | |
1132 | ||
50654f6c | 1133 | set = single_set (insn); |
6fb5fa3c DB |
1134 | if (!set) |
1135 | return false; | |
1136 | ||
1137 | if (!REG_P (SET_DEST (set))) | |
03fd2215 ZD |
1138 | return false; |
1139 | ||
6fb5fa3c | 1140 | gcc_assert (SET_DEST (set) == reg); |
50654f6c | 1141 | rhs = find_reg_equal_equiv_note (insn); |
0aea6467 ZD |
1142 | if (rhs) |
1143 | rhs = XEXP (rhs, 0); | |
1144 | else | |
50654f6c | 1145 | rhs = SET_SRC (set); |
50654f6c | 1146 | |
03fd2215 ZD |
1147 | iv_analyze_expr (insn, rhs, GET_MODE (reg), iv); |
1148 | record_iv (def, iv); | |
1149 | ||
1150 | if (dump_file) | |
50654f6c | 1151 | { |
03fd2215 ZD |
1152 | print_rtl (dump_file, reg); |
1153 | fprintf (dump_file, " in insn "); | |
1154 | print_rtl_single (dump_file, insn); | |
1155 | fprintf (dump_file, " is "); | |
1156 | dump_iv_info (dump_file, iv); | |
1157 | fprintf (dump_file, "\n"); | |
50654f6c | 1158 | } |
50654f6c | 1159 | |
03fd2215 ZD |
1160 | return iv->base != NULL_RTX; |
1161 | } | |
50654f6c | 1162 | |
03fd2215 | 1163 | /* Analyzes operand OP of INSN and stores the result to *IV. */ |
50654f6c | 1164 | |
03fd2215 | 1165 | static bool |
1b20d55a | 1166 | iv_analyze_op (rtx_insn *insn, rtx op, struct rtx_iv *iv) |
03fd2215 | 1167 | { |
57512f53 | 1168 | df_ref def = NULL; |
03fd2215 | 1169 | enum iv_grd_result res; |
abe0d774 | 1170 | |
03fd2215 ZD |
1171 | if (dump_file) |
1172 | { | |
4dad0aca | 1173 | fprintf (dump_file, "Analyzing operand "); |
03fd2215 ZD |
1174 | print_rtl (dump_file, op); |
1175 | fprintf (dump_file, " of insn "); | |
1176 | print_rtl_single (dump_file, insn); | |
1177 | } | |
abe0d774 | 1178 | |
cdf1bf8b | 1179 | if (function_invariant_p (op)) |
03fd2215 ZD |
1180 | res = GRD_INVARIANT; |
1181 | else if (GET_CODE (op) == SUBREG) | |
1182 | { | |
1183 | if (!subreg_lowpart_p (op)) | |
1184 | return false; | |
50654f6c | 1185 | |
03fd2215 ZD |
1186 | if (!iv_analyze_op (insn, SUBREG_REG (op), iv)) |
1187 | return false; | |
50654f6c | 1188 | |
03fd2215 ZD |
1189 | return iv_subreg (iv, GET_MODE (op)); |
1190 | } | |
1191 | else | |
50654f6c | 1192 | { |
03fd2215 ZD |
1193 | res = iv_get_reaching_def (insn, op, &def); |
1194 | if (res == GRD_INVALID) | |
50654f6c | 1195 | { |
03fd2215 ZD |
1196 | if (dump_file) |
1197 | fprintf (dump_file, " not simple.\n"); | |
1198 | return false; | |
50654f6c ZD |
1199 | } |
1200 | } | |
1201 | ||
03fd2215 | 1202 | if (res == GRD_INVARIANT) |
50654f6c | 1203 | { |
03fd2215 | 1204 | iv_constant (iv, op, VOIDmode); |
50654f6c | 1205 | |
03fd2215 | 1206 | if (dump_file) |
50654f6c | 1207 | { |
03fd2215 ZD |
1208 | fprintf (dump_file, " "); |
1209 | dump_iv_info (dump_file, iv); | |
1210 | fprintf (dump_file, "\n"); | |
50654f6c | 1211 | } |
03fd2215 | 1212 | return true; |
50654f6c ZD |
1213 | } |
1214 | ||
03fd2215 ZD |
1215 | if (res == GRD_MAYBE_BIV) |
1216 | return iv_analyze_biv (op, iv); | |
50654f6c | 1217 | |
03fd2215 ZD |
1218 | return iv_analyze_def (def, iv); |
1219 | } | |
50654f6c | 1220 | |
03fd2215 | 1221 | /* Analyzes value VAL at INSN and stores the result to *IV. */ |
50654f6c | 1222 | |
03fd2215 | 1223 | bool |
1b20d55a | 1224 | iv_analyze (rtx_insn *insn, rtx val, struct rtx_iv *iv) |
03fd2215 ZD |
1225 | { |
1226 | rtx reg; | |
50654f6c | 1227 | |
03fd2215 ZD |
1228 | /* We must find the insn in that val is used, so that we get to UD chains. |
1229 | Since the function is sometimes called on result of get_condition, | |
1230 | this does not necessarily have to be directly INSN; scan also the | |
1231 | following insns. */ | |
1232 | if (simple_reg_p (val)) | |
1233 | { | |
1234 | if (GET_CODE (val) == SUBREG) | |
1235 | reg = SUBREG_REG (val); | |
1236 | else | |
1237 | reg = val; | |
abe0d774 | 1238 | |
6fb5fa3c | 1239 | while (!df_find_use (insn, reg)) |
03fd2215 | 1240 | insn = NEXT_INSN (insn); |
50654f6c ZD |
1241 | } |
1242 | ||
03fd2215 ZD |
1243 | return iv_analyze_op (insn, val, iv); |
1244 | } | |
50654f6c | 1245 | |
03fd2215 | 1246 | /* Analyzes definition of DEF in INSN and stores the result to IV. */ |
50654f6c | 1247 | |
03fd2215 | 1248 | bool |
1b20d55a | 1249 | iv_analyze_result (rtx_insn *insn, rtx def, struct rtx_iv *iv) |
03fd2215 | 1250 | { |
57512f53 | 1251 | df_ref adef; |
50654f6c | 1252 | |
6fb5fa3c | 1253 | adef = df_find_def (insn, def); |
03fd2215 ZD |
1254 | if (!adef) |
1255 | return false; | |
1256 | ||
1257 | return iv_analyze_def (adef, iv); | |
50654f6c ZD |
1258 | } |
1259 | ||
03fd2215 | 1260 | /* Checks whether definition of register REG in INSN is a basic induction |
113d659a ZD |
1261 | variable. IV analysis must have been initialized (via a call to |
1262 | iv_analysis_loop_init) for this function to produce a result. */ | |
1263 | ||
1264 | bool | |
1b20d55a | 1265 | biv_p (rtx_insn *insn, rtx reg) |
113d659a ZD |
1266 | { |
1267 | struct rtx_iv iv; | |
57512f53 | 1268 | df_ref def, last_def; |
113d659a | 1269 | |
03fd2215 | 1270 | if (!simple_reg_p (reg)) |
113d659a ZD |
1271 | return false; |
1272 | ||
6fb5fa3c | 1273 | def = df_find_def (insn, reg); |
03fd2215 ZD |
1274 | gcc_assert (def != NULL); |
1275 | if (!latch_dominating_def (reg, &last_def)) | |
1276 | return false; | |
1277 | if (last_def != def) | |
113d659a ZD |
1278 | return false; |
1279 | ||
03fd2215 ZD |
1280 | if (!iv_analyze_biv (reg, &iv)) |
1281 | return false; | |
1282 | ||
1283 | return iv.step != const0_rtx; | |
113d659a ZD |
1284 | } |
1285 | ||
50654f6c ZD |
1286 | /* Calculates value of IV at ITERATION-th iteration. */ |
1287 | ||
1288 | rtx | |
1289 | get_iv_value (struct rtx_iv *iv, rtx iteration) | |
1290 | { | |
1291 | rtx val; | |
1292 | ||
1293 | /* We would need to generate some if_then_else patterns, and so far | |
1294 | it is not needed anywhere. */ | |
b5e624c6 | 1295 | gcc_assert (!iv->first_special); |
50654f6c ZD |
1296 | |
1297 | if (iv->step != const0_rtx && iteration != const0_rtx) | |
1298 | val = simplify_gen_binary (PLUS, iv->extend_mode, iv->base, | |
1299 | simplify_gen_binary (MULT, iv->extend_mode, | |
1300 | iv->step, iteration)); | |
1301 | else | |
1302 | val = iv->base; | |
1303 | ||
1304 | if (iv->extend_mode == iv->mode) | |
1305 | return val; | |
1306 | ||
6c3b938d | 1307 | val = lowpart_subreg (iv->mode, val, iv->extend_mode); |
50654f6c | 1308 | |
1c1ad7bb | 1309 | if (iv->extend == IV_UNKNOWN_EXTEND) |
50654f6c ZD |
1310 | return val; |
1311 | ||
1c1ad7bb SB |
1312 | val = simplify_gen_unary (iv_extend_to_rtx_code (iv->extend), |
1313 | iv->extend_mode, val, iv->mode); | |
50654f6c ZD |
1314 | val = simplify_gen_binary (PLUS, iv->extend_mode, iv->delta, |
1315 | simplify_gen_binary (MULT, iv->extend_mode, | |
1316 | iv->mult, val)); | |
1317 | ||
1318 | return val; | |
1319 | } | |
1320 | ||
1321 | /* Free the data for an induction variable analysis. */ | |
1322 | ||
1323 | void | |
1324 | iv_analysis_done (void) | |
1325 | { | |
6fb5fa3c | 1326 | if (!clean_slate) |
50654f6c | 1327 | { |
03fd2215 | 1328 | clear_iv_info (); |
6fb5fa3c | 1329 | clean_slate = true; |
0d475361 | 1330 | df_finish_pass (true); |
c203e8a7 TS |
1331 | delete bivs; |
1332 | bivs = NULL; | |
6fb5fa3c DB |
1333 | free (iv_ref_table); |
1334 | iv_ref_table = NULL; | |
1335 | iv_ref_table_size = 0; | |
50654f6c ZD |
1336 | } |
1337 | } | |
1338 | ||
1339 | /* Computes inverse to X modulo (1 << MOD). */ | |
1340 | ||
a9243bfc RB |
1341 | static uint64_t |
1342 | inverse (uint64_t x, int mod) | |
50654f6c | 1343 | { |
a9243bfc RB |
1344 | uint64_t mask = |
1345 | ((uint64_t) 1 << (mod - 1) << 1) - 1; | |
1346 | uint64_t rslt = 1; | |
50654f6c ZD |
1347 | int i; |
1348 | ||
1349 | for (i = 0; i < mod - 1; i++) | |
1350 | { | |
1351 | rslt = (rslt * x) & mask; | |
1352 | x = (x * x) & mask; | |
1353 | } | |
1354 | ||
1355 | return rslt; | |
1356 | } | |
1357 | ||
b42b06e6 | 1358 | /* Checks whether any register in X is in set ALT. */ |
50654f6c | 1359 | |
b42b06e6 RS |
1360 | static bool |
1361 | altered_reg_used (const_rtx x, bitmap alt) | |
50654f6c | 1362 | { |
b42b06e6 RS |
1363 | subrtx_iterator::array_type array; |
1364 | FOR_EACH_SUBRTX (iter, array, x, NONCONST) | |
1365 | { | |
1366 | const_rtx x = *iter; | |
1367 | if (REG_P (x) && REGNO_REG_SET_P (alt, REGNO (x))) | |
1368 | return true; | |
1369 | } | |
1370 | return false; | |
50654f6c ZD |
1371 | } |
1372 | ||
1373 | /* Marks registers altered by EXPR in set ALT. */ | |
1374 | ||
1375 | static void | |
7bc980e1 | 1376 | mark_altered (rtx expr, const_rtx by ATTRIBUTE_UNUSED, void *alt) |
50654f6c ZD |
1377 | { |
1378 | if (GET_CODE (expr) == SUBREG) | |
1379 | expr = SUBREG_REG (expr); | |
1380 | if (!REG_P (expr)) | |
1381 | return; | |
1382 | ||
d3bfe4de | 1383 | SET_REGNO_REG_SET ((bitmap) alt, REGNO (expr)); |
50654f6c ZD |
1384 | } |
1385 | ||
1386 | /* Checks whether RHS is simple enough to process. */ | |
1387 | ||
1388 | static bool | |
1389 | simple_rhs_p (rtx rhs) | |
1390 | { | |
1391 | rtx op0, op1; | |
1392 | ||
cdf1bf8b | 1393 | if (function_invariant_p (rhs) |
4aa97413 | 1394 | || (REG_P (rhs) && !HARD_REGISTER_P (rhs))) |
50654f6c ZD |
1395 | return true; |
1396 | ||
1397 | switch (GET_CODE (rhs)) | |
1398 | { | |
1399 | case PLUS: | |
1400 | case MINUS: | |
b30321cd | 1401 | case AND: |
50654f6c ZD |
1402 | op0 = XEXP (rhs, 0); |
1403 | op1 = XEXP (rhs, 1); | |
b30321cd | 1404 | /* Allow reg OP const and reg OP reg. */ |
dc5b3407 | 1405 | if (!(REG_P (op0) && !HARD_REGISTER_P (op0)) |
ce72fe6c | 1406 | && !function_invariant_p (op0)) |
dc5b3407 ZD |
1407 | return false; |
1408 | if (!(REG_P (op1) && !HARD_REGISTER_P (op1)) | |
ce72fe6c | 1409 | && !function_invariant_p (op1)) |
dc5b3407 | 1410 | return false; |
50654f6c | 1411 | |
dc5b3407 ZD |
1412 | return true; |
1413 | ||
1414 | case ASHIFT: | |
b30321cd BS |
1415 | case ASHIFTRT: |
1416 | case LSHIFTRT: | |
1417 | case MULT: | |
dc5b3407 ZD |
1418 | op0 = XEXP (rhs, 0); |
1419 | op1 = XEXP (rhs, 1); | |
b30321cd | 1420 | /* Allow reg OP const. */ |
dc5b3407 ZD |
1421 | if (!(REG_P (op0) && !HARD_REGISTER_P (op0))) |
1422 | return false; | |
ce72fe6c | 1423 | if (!function_invariant_p (op1)) |
dc5b3407 ZD |
1424 | return false; |
1425 | ||
1426 | return true; | |
50654f6c ZD |
1427 | |
1428 | default: | |
1429 | return false; | |
1430 | } | |
1431 | } | |
1432 | ||
4ca29add RS |
1433 | /* If REGNO has a single definition, return its known value, otherwise return |
1434 | null. */ | |
60081874 | 1435 | |
4ca29add RS |
1436 | static rtx |
1437 | find_single_def_src (unsigned int regno) | |
60081874 | 1438 | { |
60081874 | 1439 | df_ref adef; |
f63426af | 1440 | rtx set, src; |
60081874 | 1441 | |
f63426af BS |
1442 | for (;;) |
1443 | { | |
1444 | rtx note; | |
1445 | adef = DF_REG_DEF_CHAIN (regno); | |
1446 | if (adef == NULL || DF_REF_NEXT_REG (adef) != NULL | |
4ca29add RS |
1447 | || DF_REF_IS_ARTIFICIAL (adef)) |
1448 | return NULL_RTX; | |
f63426af BS |
1449 | |
1450 | set = single_set (DF_REF_INSN (adef)); | |
1451 | if (set == NULL || !REG_P (SET_DEST (set)) | |
1452 | || REGNO (SET_DEST (set)) != regno) | |
4ca29add | 1453 | return NULL_RTX; |
60081874 | 1454 | |
f63426af BS |
1455 | note = find_reg_equal_equiv_note (DF_REF_INSN (adef)); |
1456 | ||
1457 | if (note && function_invariant_p (XEXP (note, 0))) | |
1458 | { | |
1459 | src = XEXP (note, 0); | |
1460 | break; | |
1461 | } | |
1462 | src = SET_SRC (set); | |
1463 | ||
1464 | if (REG_P (src)) | |
1465 | { | |
1466 | regno = REGNO (src); | |
1467 | continue; | |
1468 | } | |
1469 | break; | |
1470 | } | |
1471 | if (!function_invariant_p (src)) | |
4ca29add RS |
1472 | return NULL_RTX; |
1473 | ||
1474 | return src; | |
1475 | } | |
1476 | ||
1477 | /* If any registers in *EXPR that have a single definition, try to replace | |
1478 | them with the known-equivalent values. */ | |
60081874 | 1479 | |
4ca29add RS |
1480 | static void |
1481 | replace_single_def_regs (rtx *expr) | |
1482 | { | |
1483 | subrtx_var_iterator::array_type array; | |
1484 | repeat: | |
1485 | FOR_EACH_SUBRTX_VAR (iter, array, *expr, NONCONST) | |
1486 | { | |
1487 | rtx x = *iter; | |
1488 | if (REG_P (x)) | |
1489 | if (rtx new_x = find_single_def_src (REGNO (x))) | |
1490 | { | |
1491 | *expr = simplify_replace_rtx (*expr, x, new_x); | |
1492 | goto repeat; | |
1493 | } | |
1494 | } | |
60081874 BS |
1495 | } |
1496 | ||
ed853664 BS |
1497 | /* A subroutine of simplify_using_initial_values, this function examines INSN |
1498 | to see if it contains a suitable set that we can use to make a replacement. | |
1499 | If it is suitable, return true and set DEST and SRC to the lhs and rhs of | |
1500 | the set; return false otherwise. */ | |
50654f6c | 1501 | |
ed853664 | 1502 | static bool |
1b20d55a | 1503 | suitable_set_for_replacement (rtx_insn *insn, rtx *dest, rtx *src) |
50654f6c ZD |
1504 | { |
1505 | rtx set = single_set (insn); | |
cddbddb7 | 1506 | rtx lhs = NULL_RTX, rhs; |
50654f6c | 1507 | |
ed853664 BS |
1508 | if (!set) |
1509 | return false; | |
50654f6c | 1510 | |
ed853664 BS |
1511 | lhs = SET_DEST (set); |
1512 | if (!REG_P (lhs)) | |
1513 | return false; | |
50654f6c ZD |
1514 | |
1515 | rhs = find_reg_equal_equiv_note (insn); | |
0aea6467 ZD |
1516 | if (rhs) |
1517 | rhs = XEXP (rhs, 0); | |
1518 | else | |
50654f6c ZD |
1519 | rhs = SET_SRC (set); |
1520 | ||
1521 | if (!simple_rhs_p (rhs)) | |
ed853664 | 1522 | return false; |
50654f6c | 1523 | |
ed853664 BS |
1524 | *dest = lhs; |
1525 | *src = rhs; | |
1526 | return true; | |
50654f6c ZD |
1527 | } |
1528 | ||
60081874 BS |
1529 | /* Using the data returned by suitable_set_for_replacement, replace DEST |
1530 | with SRC in *EXPR and return the new expression. Also call | |
1531 | replace_single_def_regs if the replacement changed something. */ | |
1532 | static void | |
1533 | replace_in_expr (rtx *expr, rtx dest, rtx src) | |
1534 | { | |
1535 | rtx old = *expr; | |
1536 | *expr = simplify_replace_rtx (*expr, dest, src); | |
1537 | if (old == *expr) | |
1538 | return; | |
4ca29add | 1539 | replace_single_def_regs (expr); |
60081874 BS |
1540 | } |
1541 | ||
50654f6c ZD |
1542 | /* Checks whether A implies B. */ |
1543 | ||
1544 | static bool | |
1545 | implies_p (rtx a, rtx b) | |
1546 | { | |
0aea6467 | 1547 | rtx op0, op1, opb0, opb1, r; |
ef4bddc2 | 1548 | machine_mode mode; |
50654f6c | 1549 | |
cca1130d BS |
1550 | if (rtx_equal_p (a, b)) |
1551 | return true; | |
1552 | ||
50654f6c ZD |
1553 | if (GET_CODE (a) == EQ) |
1554 | { | |
1555 | op0 = XEXP (a, 0); | |
1556 | op1 = XEXP (a, 1); | |
1557 | ||
cca1130d BS |
1558 | if (REG_P (op0) |
1559 | || (GET_CODE (op0) == SUBREG | |
1560 | && REG_P (SUBREG_REG (op0)))) | |
50654f6c ZD |
1561 | { |
1562 | r = simplify_replace_rtx (b, op0, op1); | |
1563 | if (r == const_true_rtx) | |
1564 | return true; | |
1565 | } | |
1566 | ||
cca1130d BS |
1567 | if (REG_P (op1) |
1568 | || (GET_CODE (op1) == SUBREG | |
1569 | && REG_P (SUBREG_REG (op1)))) | |
50654f6c ZD |
1570 | { |
1571 | r = simplify_replace_rtx (b, op1, op0); | |
1572 | if (r == const_true_rtx) | |
1573 | return true; | |
1574 | } | |
1575 | } | |
1576 | ||
60683019 BS |
1577 | if (b == const_true_rtx) |
1578 | return true; | |
1579 | ||
1580 | if ((GET_RTX_CLASS (GET_CODE (a)) != RTX_COMM_COMPARE | |
1581 | && GET_RTX_CLASS (GET_CODE (a)) != RTX_COMPARE) | |
1582 | || (GET_RTX_CLASS (GET_CODE (b)) != RTX_COMM_COMPARE | |
1583 | && GET_RTX_CLASS (GET_CODE (b)) != RTX_COMPARE)) | |
1584 | return false; | |
1585 | ||
1586 | op0 = XEXP (a, 0); | |
1587 | op1 = XEXP (a, 1); | |
1588 | opb0 = XEXP (b, 0); | |
1589 | opb1 = XEXP (b, 1); | |
1590 | ||
1591 | mode = GET_MODE (op0); | |
1592 | if (mode != GET_MODE (opb0)) | |
1593 | mode = VOIDmode; | |
1594 | else if (mode == VOIDmode) | |
1595 | { | |
1596 | mode = GET_MODE (op1); | |
1597 | if (mode != GET_MODE (opb1)) | |
1598 | mode = VOIDmode; | |
1599 | } | |
1600 | ||
0aea6467 ZD |
1601 | /* A < B implies A + 1 <= B. */ |
1602 | if ((GET_CODE (a) == GT || GET_CODE (a) == LT) | |
1603 | && (GET_CODE (b) == GE || GET_CODE (b) == LE)) | |
1604 | { | |
0aea6467 ZD |
1605 | |
1606 | if (GET_CODE (a) == GT) | |
1607 | { | |
1608 | r = op0; | |
1609 | op0 = op1; | |
1610 | op1 = r; | |
1611 | } | |
1612 | ||
1613 | if (GET_CODE (b) == GE) | |
1614 | { | |
1615 | r = opb0; | |
1616 | opb0 = opb1; | |
1617 | opb1 = r; | |
1618 | } | |
1619 | ||
d4538829 | 1620 | if (SCALAR_INT_MODE_P (mode) |
0aea6467 ZD |
1621 | && rtx_equal_p (op1, opb1) |
1622 | && simplify_gen_binary (MINUS, mode, opb0, op0) == const1_rtx) | |
1623 | return true; | |
60683019 BS |
1624 | return false; |
1625 | } | |
1626 | ||
1627 | /* A < B or A > B imply A != B. TODO: Likewise | |
1628 | A + n < B implies A != B + n if neither wraps. */ | |
1629 | if (GET_CODE (b) == NE | |
1630 | && (GET_CODE (a) == GT || GET_CODE (a) == GTU | |
1631 | || GET_CODE (a) == LT || GET_CODE (a) == LTU)) | |
1632 | { | |
1633 | if (rtx_equal_p (op0, opb0) | |
1634 | && rtx_equal_p (op1, opb1)) | |
1635 | return true; | |
0aea6467 ZD |
1636 | } |
1637 | ||
60683019 BS |
1638 | /* For unsigned comparisons, A != 0 implies A > 0 and A >= 1. */ |
1639 | if (GET_CODE (a) == NE | |
1640 | && op1 == const0_rtx) | |
1641 | { | |
1642 | if ((GET_CODE (b) == GTU | |
1643 | && opb1 == const0_rtx) | |
1644 | || (GET_CODE (b) == GEU | |
1645 | && opb1 == const1_rtx)) | |
1646 | return rtx_equal_p (op0, opb0); | |
1647 | } | |
1648 | ||
1649 | /* A != N is equivalent to A - (N + 1) <u -1. */ | |
1650 | if (GET_CODE (a) == NE | |
481683e1 | 1651 | && CONST_INT_P (op1) |
60683019 BS |
1652 | && GET_CODE (b) == LTU |
1653 | && opb1 == constm1_rtx | |
1654 | && GET_CODE (opb0) == PLUS | |
481683e1 | 1655 | && CONST_INT_P (XEXP (opb0, 1)) |
60683019 BS |
1656 | /* Avoid overflows. */ |
1657 | && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (opb0, 1)) | |
1658 | != ((unsigned HOST_WIDE_INT)1 | |
1659 | << (HOST_BITS_PER_WIDE_INT - 1)) - 1) | |
1660 | && INTVAL (XEXP (opb0, 1)) + 1 == -INTVAL (op1)) | |
1661 | return rtx_equal_p (op0, XEXP (opb0, 0)); | |
1662 | ||
1663 | /* Likewise, A != N implies A - N > 0. */ | |
1664 | if (GET_CODE (a) == NE | |
481683e1 | 1665 | && CONST_INT_P (op1)) |
60683019 BS |
1666 | { |
1667 | if (GET_CODE (b) == GTU | |
1668 | && GET_CODE (opb0) == PLUS | |
1669 | && opb1 == const0_rtx | |
481683e1 | 1670 | && CONST_INT_P (XEXP (opb0, 1)) |
60683019 BS |
1671 | /* Avoid overflows. */ |
1672 | && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (opb0, 1)) | |
1673 | != ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1))) | |
1674 | && rtx_equal_p (XEXP (opb0, 0), op0)) | |
1675 | return INTVAL (op1) == -INTVAL (XEXP (opb0, 1)); | |
1676 | if (GET_CODE (b) == GEU | |
1677 | && GET_CODE (opb0) == PLUS | |
1678 | && opb1 == const1_rtx | |
481683e1 | 1679 | && CONST_INT_P (XEXP (opb0, 1)) |
60683019 BS |
1680 | /* Avoid overflows. */ |
1681 | && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (opb0, 1)) | |
1682 | != ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1))) | |
1683 | && rtx_equal_p (XEXP (opb0, 0), op0)) | |
1684 | return INTVAL (op1) == -INTVAL (XEXP (opb0, 1)); | |
1685 | } | |
1686 | ||
1687 | /* A >s X, where X is positive, implies A <u Y, if Y is negative. */ | |
1688 | if ((GET_CODE (a) == GT || GET_CODE (a) == GE) | |
481683e1 | 1689 | && CONST_INT_P (op1) |
60683019 BS |
1690 | && ((GET_CODE (a) == GT && op1 == constm1_rtx) |
1691 | || INTVAL (op1) >= 0) | |
1692 | && GET_CODE (b) == LTU | |
481683e1 | 1693 | && CONST_INT_P (opb1) |
b1c92d54 | 1694 | && rtx_equal_p (op0, opb0)) |
60683019 BS |
1695 | return INTVAL (opb1) < 0; |
1696 | ||
50654f6c ZD |
1697 | return false; |
1698 | } | |
1699 | ||
1700 | /* Canonicalizes COND so that | |
1701 | ||
1702 | (1) Ensure that operands are ordered according to | |
1703 | swap_commutative_operands_p. | |
1704 | (2) (LE x const) will be replaced with (LT x <const+1>) and similarly | |
1705 | for GE, GEU, and LEU. */ | |
1706 | ||
1707 | rtx | |
1708 | canon_condition (rtx cond) | |
1709 | { | |
1710 | rtx tem; | |
1711 | rtx op0, op1; | |
1712 | enum rtx_code code; | |
ef4bddc2 | 1713 | machine_mode mode; |
50654f6c ZD |
1714 | |
1715 | code = GET_CODE (cond); | |
1716 | op0 = XEXP (cond, 0); | |
1717 | op1 = XEXP (cond, 1); | |
1718 | ||
1719 | if (swap_commutative_operands_p (op0, op1)) | |
1720 | { | |
1721 | code = swap_condition (code); | |
1722 | tem = op0; | |
1723 | op0 = op1; | |
1724 | op1 = tem; | |
1725 | } | |
1726 | ||
1727 | mode = GET_MODE (op0); | |
1728 | if (mode == VOIDmode) | |
1729 | mode = GET_MODE (op1); | |
b5e624c6 | 1730 | gcc_assert (mode != VOIDmode); |
50654f6c | 1731 | |
674dd710 | 1732 | if (CONST_SCALAR_INT_P (op1) && GET_MODE_CLASS (mode) != MODE_CC) |
50654f6c | 1733 | { |
674dd710 | 1734 | rtx_mode_t const_val (op1, mode); |
50654f6c ZD |
1735 | |
1736 | switch (code) | |
1737 | { | |
1738 | case LE: | |
674dd710 RS |
1739 | if (wi::ne_p (const_val, wi::max_value (mode, SIGNED))) |
1740 | { | |
1741 | code = LT; | |
1742 | op1 = immed_wide_int_const (wi::add (const_val, 1), mode); | |
1743 | } | |
50654f6c ZD |
1744 | break; |
1745 | ||
50654f6c | 1746 | case GE: |
674dd710 RS |
1747 | if (wi::ne_p (const_val, wi::min_value (mode, SIGNED))) |
1748 | { | |
1749 | code = GT; | |
1750 | op1 = immed_wide_int_const (wi::sub (const_val, 1), mode); | |
1751 | } | |
50654f6c ZD |
1752 | break; |
1753 | ||
1754 | case LEU: | |
674dd710 RS |
1755 | if (wi::ne_p (const_val, -1)) |
1756 | { | |
1757 | code = LTU; | |
1758 | op1 = immed_wide_int_const (wi::add (const_val, 1), mode); | |
1759 | } | |
50654f6c ZD |
1760 | break; |
1761 | ||
1762 | case GEU: | |
674dd710 RS |
1763 | if (wi::ne_p (const_val, 0)) |
1764 | { | |
1765 | code = GTU; | |
1766 | op1 = immed_wide_int_const (wi::sub (const_val, 1), mode); | |
1767 | } | |
50654f6c ZD |
1768 | break; |
1769 | ||
1770 | default: | |
1771 | break; | |
1772 | } | |
1773 | } | |
1774 | ||
1775 | if (op0 != XEXP (cond, 0) | |
1776 | || op1 != XEXP (cond, 1) | |
1777 | || code != GET_CODE (cond) | |
1778 | || GET_MODE (cond) != SImode) | |
1779 | cond = gen_rtx_fmt_ee (code, SImode, op0, op1); | |
1780 | ||
1781 | return cond; | |
1782 | } | |
1783 | ||
da4cfeac RB |
1784 | /* Reverses CONDition; returns NULL if we cannot. */ |
1785 | ||
1786 | static rtx | |
1787 | reversed_condition (rtx cond) | |
1788 | { | |
1789 | enum rtx_code reversed; | |
1790 | reversed = reversed_comparison_code (cond, NULL); | |
1791 | if (reversed == UNKNOWN) | |
1792 | return NULL_RTX; | |
1793 | else | |
1794 | return gen_rtx_fmt_ee (reversed, | |
1795 | GET_MODE (cond), XEXP (cond, 0), | |
1796 | XEXP (cond, 1)); | |
1797 | } | |
1798 | ||
50654f6c ZD |
1799 | /* Tries to use the fact that COND holds to simplify EXPR. ALTERED is the |
1800 | set of altered regs. */ | |
1801 | ||
1802 | void | |
1803 | simplify_using_condition (rtx cond, rtx *expr, regset altered) | |
1804 | { | |
1805 | rtx rev, reve, exp = *expr; | |
1806 | ||
50654f6c ZD |
1807 | /* If some register gets altered later, we do not really speak about its |
1808 | value at the time of comparison. */ | |
b42b06e6 | 1809 | if (altered && altered_reg_used (cond, altered)) |
50654f6c ZD |
1810 | return; |
1811 | ||
1569e190 BS |
1812 | if (GET_CODE (cond) == EQ |
1813 | && REG_P (XEXP (cond, 0)) && CONSTANT_P (XEXP (cond, 1))) | |
1814 | { | |
1815 | *expr = simplify_replace_rtx (*expr, XEXP (cond, 0), XEXP (cond, 1)); | |
1816 | return; | |
1817 | } | |
1818 | ||
1819 | if (!COMPARISON_P (exp)) | |
1820 | return; | |
1821 | ||
50654f6c ZD |
1822 | rev = reversed_condition (cond); |
1823 | reve = reversed_condition (exp); | |
1824 | ||
1825 | cond = canon_condition (cond); | |
1826 | exp = canon_condition (exp); | |
1827 | if (rev) | |
1828 | rev = canon_condition (rev); | |
1829 | if (reve) | |
1830 | reve = canon_condition (reve); | |
1831 | ||
1832 | if (rtx_equal_p (exp, cond)) | |
1833 | { | |
1834 | *expr = const_true_rtx; | |
1835 | return; | |
1836 | } | |
1837 | ||
50654f6c ZD |
1838 | if (rev && rtx_equal_p (exp, rev)) |
1839 | { | |
1840 | *expr = const0_rtx; | |
1841 | return; | |
1842 | } | |
1843 | ||
1844 | if (implies_p (cond, exp)) | |
1845 | { | |
1846 | *expr = const_true_rtx; | |
1847 | return; | |
1848 | } | |
b8698a0f | 1849 | |
50654f6c ZD |
1850 | if (reve && implies_p (cond, reve)) |
1851 | { | |
1852 | *expr = const0_rtx; | |
1853 | return; | |
1854 | } | |
1855 | ||
1856 | /* A proof by contradiction. If *EXPR implies (not cond), *EXPR must | |
1857 | be false. */ | |
1858 | if (rev && implies_p (exp, rev)) | |
1859 | { | |
1860 | *expr = const0_rtx; | |
1861 | return; | |
1862 | } | |
1863 | ||
1864 | /* Similarly, If (not *EXPR) implies (not cond), *EXPR must be true. */ | |
1865 | if (rev && reve && implies_p (reve, rev)) | |
1866 | { | |
1867 | *expr = const_true_rtx; | |
1868 | return; | |
1869 | } | |
1870 | ||
1871 | /* We would like to have some other tests here. TODO. */ | |
1872 | ||
1873 | return; | |
1874 | } | |
1875 | ||
1876 | /* Use relationship between A and *B to eventually eliminate *B. | |
1877 | OP is the operation we consider. */ | |
1878 | ||
1879 | static void | |
1880 | eliminate_implied_condition (enum rtx_code op, rtx a, rtx *b) | |
1881 | { | |
b5e624c6 | 1882 | switch (op) |
50654f6c | 1883 | { |
b5e624c6 | 1884 | case AND: |
50654f6c ZD |
1885 | /* If A implies *B, we may replace *B by true. */ |
1886 | if (implies_p (a, *b)) | |
1887 | *b = const_true_rtx; | |
b5e624c6 NS |
1888 | break; |
1889 | ||
1890 | case IOR: | |
50654f6c ZD |
1891 | /* If *B implies A, we may replace *B by false. */ |
1892 | if (implies_p (*b, a)) | |
1893 | *b = const0_rtx; | |
b5e624c6 NS |
1894 | break; |
1895 | ||
1896 | default: | |
1897 | gcc_unreachable (); | |
50654f6c | 1898 | } |
50654f6c ZD |
1899 | } |
1900 | ||
1901 | /* Eliminates the conditions in TAIL that are implied by HEAD. OP is the | |
1902 | operation we consider. */ | |
1903 | ||
1904 | static void | |
1905 | eliminate_implied_conditions (enum rtx_code op, rtx *head, rtx tail) | |
1906 | { | |
1907 | rtx elt; | |
1908 | ||
1909 | for (elt = tail; elt; elt = XEXP (elt, 1)) | |
1910 | eliminate_implied_condition (op, *head, &XEXP (elt, 0)); | |
1911 | for (elt = tail; elt; elt = XEXP (elt, 1)) | |
1912 | eliminate_implied_condition (op, XEXP (elt, 0), head); | |
1913 | } | |
1914 | ||
1915 | /* Simplifies *EXPR using initial values at the start of the LOOP. If *EXPR | |
1916 | is a list, its elements are assumed to be combined using OP. */ | |
1917 | ||
1918 | static void | |
1919 | simplify_using_initial_values (struct loop *loop, enum rtx_code op, rtx *expr) | |
1920 | { | |
ed853664 | 1921 | bool expression_valid; |
2f33ff0a DM |
1922 | rtx head, tail, last_valid_expr; |
1923 | rtx_expr_list *cond_list; | |
1b20d55a | 1924 | rtx_insn *insn; |
50654f6c | 1925 | rtx neutral, aggr; |
ed853664 | 1926 | regset altered, this_altered; |
50654f6c ZD |
1927 | edge e; |
1928 | ||
1929 | if (!*expr) | |
1930 | return; | |
1931 | ||
1932 | if (CONSTANT_P (*expr)) | |
1933 | return; | |
1934 | ||
1935 | if (GET_CODE (*expr) == EXPR_LIST) | |
1936 | { | |
1937 | head = XEXP (*expr, 0); | |
1938 | tail = XEXP (*expr, 1); | |
1939 | ||
1940 | eliminate_implied_conditions (op, &head, tail); | |
1941 | ||
b5e624c6 | 1942 | switch (op) |
50654f6c | 1943 | { |
b5e624c6 | 1944 | case AND: |
50654f6c ZD |
1945 | neutral = const_true_rtx; |
1946 | aggr = const0_rtx; | |
b5e624c6 NS |
1947 | break; |
1948 | ||
1949 | case IOR: | |
50654f6c ZD |
1950 | neutral = const0_rtx; |
1951 | aggr = const_true_rtx; | |
b5e624c6 | 1952 | break; |
50654f6c | 1953 | |
b5e624c6 NS |
1954 | default: |
1955 | gcc_unreachable (); | |
1956 | } | |
b8698a0f | 1957 | |
f822d252 | 1958 | simplify_using_initial_values (loop, UNKNOWN, &head); |
50654f6c ZD |
1959 | if (head == aggr) |
1960 | { | |
1961 | XEXP (*expr, 0) = aggr; | |
1962 | XEXP (*expr, 1) = NULL_RTX; | |
1963 | return; | |
1964 | } | |
1965 | else if (head == neutral) | |
1966 | { | |
1967 | *expr = tail; | |
1968 | simplify_using_initial_values (loop, op, expr); | |
1969 | return; | |
1970 | } | |
1971 | simplify_using_initial_values (loop, op, &tail); | |
1972 | ||
1973 | if (tail && XEXP (tail, 0) == aggr) | |
1974 | { | |
1975 | *expr = tail; | |
1976 | return; | |
1977 | } | |
b8698a0f | 1978 | |
50654f6c ZD |
1979 | XEXP (*expr, 0) = head; |
1980 | XEXP (*expr, 1) = tail; | |
1981 | return; | |
1982 | } | |
1983 | ||
b5e624c6 | 1984 | gcc_assert (op == UNKNOWN); |
50654f6c | 1985 | |
4ca29add | 1986 | replace_single_def_regs (expr); |
60081874 BS |
1987 | if (CONSTANT_P (*expr)) |
1988 | return; | |
1989 | ||
50654f6c | 1990 | e = loop_preheader_edge (loop); |
fefa31b5 | 1991 | if (e->src == ENTRY_BLOCK_PTR_FOR_FN (cfun)) |
50654f6c ZD |
1992 | return; |
1993 | ||
04389919 | 1994 | altered = ALLOC_REG_SET (®_obstack); |
ed853664 | 1995 | this_altered = ALLOC_REG_SET (®_obstack); |
50654f6c | 1996 | |
ed853664 BS |
1997 | expression_valid = true; |
1998 | last_valid_expr = *expr; | |
2f33ff0a | 1999 | cond_list = NULL; |
50654f6c ZD |
2000 | while (1) |
2001 | { | |
2002 | insn = BB_END (e->src); | |
2003 | if (any_condjump_p (insn)) | |
2004 | { | |
45d09c02 | 2005 | rtx cond = get_condition (BB_END (e->src), NULL, false, true); |
1569e190 | 2006 | |
50654f6c ZD |
2007 | if (cond && (e->flags & EDGE_FALLTHRU)) |
2008 | cond = reversed_condition (cond); | |
2009 | if (cond) | |
2010 | { | |
1569e190 | 2011 | rtx old = *expr; |
50654f6c | 2012 | simplify_using_condition (cond, expr, altered); |
1569e190 BS |
2013 | if (old != *expr) |
2014 | { | |
2015 | rtx note; | |
2016 | if (CONSTANT_P (*expr)) | |
2017 | goto out; | |
2018 | for (note = cond_list; note; note = XEXP (note, 1)) | |
2019 | { | |
2020 | simplify_using_condition (XEXP (note, 0), expr, altered); | |
2021 | if (CONSTANT_P (*expr)) | |
2022 | goto out; | |
2023 | } | |
2024 | } | |
2025 | cond_list = alloc_EXPR_LIST (0, cond, cond_list); | |
50654f6c ZD |
2026 | } |
2027 | } | |
2028 | ||
2029 | FOR_BB_INSNS_REVERSE (e->src, insn) | |
2030 | { | |
ed853664 | 2031 | rtx src, dest; |
1569e190 | 2032 | rtx old = *expr; |
ed853664 | 2033 | |
50654f6c ZD |
2034 | if (!INSN_P (insn)) |
2035 | continue; | |
ed853664 BS |
2036 | |
2037 | CLEAR_REG_SET (this_altered); | |
2038 | note_stores (PATTERN (insn), mark_altered, this_altered); | |
2039 | if (CALL_P (insn)) | |
50654f6c | 2040 | { |
ed853664 | 2041 | /* Kill all call clobbered registers. */ |
c7fb4c7a SB |
2042 | unsigned int i; |
2043 | hard_reg_set_iterator hrsi; | |
2044 | EXECUTE_IF_SET_IN_HARD_REG_SET (regs_invalidated_by_call, | |
2045 | 0, i, hrsi) | |
2046 | SET_REGNO_REG_SET (this_altered, i); | |
50654f6c | 2047 | } |
ed853664 BS |
2048 | |
2049 | if (suitable_set_for_replacement (insn, &dest, &src)) | |
48982394 | 2050 | { |
2f33ff0a | 2051 | rtx_expr_list **pnote, **pnote_next; |
1569e190 | 2052 | |
60081874 | 2053 | replace_in_expr (expr, dest, src); |
ed853664 BS |
2054 | if (CONSTANT_P (*expr)) |
2055 | goto out; | |
1569e190 BS |
2056 | |
2057 | for (pnote = &cond_list; *pnote; pnote = pnote_next) | |
2058 | { | |
2059 | rtx note = *pnote; | |
2060 | rtx old_cond = XEXP (note, 0); | |
2061 | ||
2f33ff0a | 2062 | pnote_next = (rtx_expr_list **)&XEXP (note, 1); |
60081874 BS |
2063 | replace_in_expr (&XEXP (note, 0), dest, src); |
2064 | ||
1569e190 BS |
2065 | /* We can no longer use a condition that has been simplified |
2066 | to a constant, and simplify_using_condition will abort if | |
2067 | we try. */ | |
2068 | if (CONSTANT_P (XEXP (note, 0))) | |
2069 | { | |
2070 | *pnote = *pnote_next; | |
2071 | pnote_next = pnote; | |
2072 | free_EXPR_LIST_node (note); | |
2073 | } | |
2074 | /* Retry simplifications with this condition if either the | |
2075 | expression or the condition changed. */ | |
2076 | else if (old_cond != XEXP (note, 0) || old != *expr) | |
2077 | simplify_using_condition (XEXP (note, 0), expr, altered); | |
2078 | } | |
48982394 | 2079 | } |
ed853664 | 2080 | else |
4fc2e37d | 2081 | { |
2f33ff0a | 2082 | rtx_expr_list **pnote, **pnote_next; |
4fc2e37d EB |
2083 | |
2084 | /* If we did not use this insn to make a replacement, any overlap | |
2085 | between stores in this insn and our expression will cause the | |
2086 | expression to become invalid. */ | |
b42b06e6 | 2087 | if (altered_reg_used (*expr, this_altered)) |
4fc2e37d EB |
2088 | goto out; |
2089 | ||
2090 | /* Likewise for the conditions. */ | |
2091 | for (pnote = &cond_list; *pnote; pnote = pnote_next) | |
2092 | { | |
2093 | rtx note = *pnote; | |
2094 | rtx old_cond = XEXP (note, 0); | |
2095 | ||
2f33ff0a | 2096 | pnote_next = (rtx_expr_list **)&XEXP (note, 1); |
b42b06e6 | 2097 | if (altered_reg_used (old_cond, this_altered)) |
4fc2e37d EB |
2098 | { |
2099 | *pnote = *pnote_next; | |
2100 | pnote_next = pnote; | |
2101 | free_EXPR_LIST_node (note); | |
2102 | } | |
2103 | } | |
2104 | } | |
ed853664 | 2105 | |
1569e190 BS |
2106 | if (CONSTANT_P (*expr)) |
2107 | goto out; | |
2108 | ||
ed853664 BS |
2109 | IOR_REG_SET (altered, this_altered); |
2110 | ||
2111 | /* If the expression now contains regs that have been altered, we | |
2112 | can't return it to the caller. However, it is still valid for | |
2113 | further simplification, so keep searching to see if we can | |
2114 | eventually turn it into a constant. */ | |
b42b06e6 | 2115 | if (altered_reg_used (*expr, altered)) |
ed853664 BS |
2116 | expression_valid = false; |
2117 | if (expression_valid) | |
2118 | last_valid_expr = *expr; | |
50654f6c ZD |
2119 | } |
2120 | ||
c5cbcccf | 2121 | if (!single_pred_p (e->src) |
fefa31b5 | 2122 | || single_pred (e->src) == ENTRY_BLOCK_PTR_FOR_FN (cfun)) |
50654f6c | 2123 | break; |
c5cbcccf | 2124 | e = single_pred_edge (e->src); |
50654f6c ZD |
2125 | } |
2126 | ||
ed853664 | 2127 | out: |
1569e190 | 2128 | free_EXPR_LIST_list (&cond_list); |
ed853664 BS |
2129 | if (!CONSTANT_P (*expr)) |
2130 | *expr = last_valid_expr; | |
50654f6c | 2131 | FREE_REG_SET (altered); |
ed853664 | 2132 | FREE_REG_SET (this_altered); |
50654f6c ZD |
2133 | } |
2134 | ||
2135 | /* Transforms invariant IV into MODE. Adds assumptions based on the fact | |
2136 | that IV occurs as left operands of comparison COND and its signedness | |
2137 | is SIGNED_P to DESC. */ | |
2138 | ||
2139 | static void | |
ef4bddc2 | 2140 | shorten_into_mode (struct rtx_iv *iv, machine_mode mode, |
50654f6c ZD |
2141 | enum rtx_code cond, bool signed_p, struct niter_desc *desc) |
2142 | { | |
2143 | rtx mmin, mmax, cond_over, cond_under; | |
2144 | ||
0aea6467 | 2145 | get_mode_bounds (mode, signed_p, iv->extend_mode, &mmin, &mmax); |
50654f6c ZD |
2146 | cond_under = simplify_gen_relational (LT, SImode, iv->extend_mode, |
2147 | iv->base, mmin); | |
2148 | cond_over = simplify_gen_relational (GT, SImode, iv->extend_mode, | |
2149 | iv->base, mmax); | |
2150 | ||
2151 | switch (cond) | |
2152 | { | |
2153 | case LE: | |
2154 | case LT: | |
2155 | case LEU: | |
2156 | case LTU: | |
2157 | if (cond_under != const0_rtx) | |
2158 | desc->infinite = | |
2159 | alloc_EXPR_LIST (0, cond_under, desc->infinite); | |
2160 | if (cond_over != const0_rtx) | |
2161 | desc->noloop_assumptions = | |
2162 | alloc_EXPR_LIST (0, cond_over, desc->noloop_assumptions); | |
2163 | break; | |
2164 | ||
2165 | case GE: | |
2166 | case GT: | |
2167 | case GEU: | |
2168 | case GTU: | |
2169 | if (cond_over != const0_rtx) | |
2170 | desc->infinite = | |
2171 | alloc_EXPR_LIST (0, cond_over, desc->infinite); | |
2172 | if (cond_under != const0_rtx) | |
2173 | desc->noloop_assumptions = | |
2174 | alloc_EXPR_LIST (0, cond_under, desc->noloop_assumptions); | |
2175 | break; | |
2176 | ||
2177 | case NE: | |
2178 | if (cond_over != const0_rtx) | |
2179 | desc->infinite = | |
2180 | alloc_EXPR_LIST (0, cond_over, desc->infinite); | |
2181 | if (cond_under != const0_rtx) | |
2182 | desc->infinite = | |
2183 | alloc_EXPR_LIST (0, cond_under, desc->infinite); | |
2184 | break; | |
2185 | ||
2186 | default: | |
b5e624c6 | 2187 | gcc_unreachable (); |
50654f6c ZD |
2188 | } |
2189 | ||
2190 | iv->mode = mode; | |
1c1ad7bb | 2191 | iv->extend = signed_p ? IV_SIGN_EXTEND : IV_ZERO_EXTEND; |
50654f6c ZD |
2192 | } |
2193 | ||
2194 | /* Transforms IV0 and IV1 compared by COND so that they are both compared as | |
a1105617 | 2195 | subregs of the same mode if possible (sometimes it is necessary to add |
50654f6c ZD |
2196 | some assumptions to DESC). */ |
2197 | ||
2198 | static bool | |
2199 | canonicalize_iv_subregs (struct rtx_iv *iv0, struct rtx_iv *iv1, | |
2200 | enum rtx_code cond, struct niter_desc *desc) | |
2201 | { | |
ef4bddc2 | 2202 | machine_mode comp_mode; |
50654f6c ZD |
2203 | bool signed_p; |
2204 | ||
2205 | /* If the ivs behave specially in the first iteration, or are | |
2206 | added/multiplied after extending, we ignore them. */ | |
2207 | if (iv0->first_special || iv0->mult != const1_rtx || iv0->delta != const0_rtx) | |
2208 | return false; | |
2209 | if (iv1->first_special || iv1->mult != const1_rtx || iv1->delta != const0_rtx) | |
2210 | return false; | |
2211 | ||
2212 | /* If there is some extend, it must match signedness of the comparison. */ | |
2213 | switch (cond) | |
2214 | { | |
2215 | case LE: | |
2216 | case LT: | |
1c1ad7bb SB |
2217 | if (iv0->extend == IV_ZERO_EXTEND |
2218 | || iv1->extend == IV_ZERO_EXTEND) | |
50654f6c ZD |
2219 | return false; |
2220 | signed_p = true; | |
2221 | break; | |
2222 | ||
2223 | case LEU: | |
2224 | case LTU: | |
1c1ad7bb SB |
2225 | if (iv0->extend == IV_SIGN_EXTEND |
2226 | || iv1->extend == IV_SIGN_EXTEND) | |
50654f6c ZD |
2227 | return false; |
2228 | signed_p = false; | |
2229 | break; | |
2230 | ||
2231 | case NE: | |
1c1ad7bb SB |
2232 | if (iv0->extend != IV_UNKNOWN_EXTEND |
2233 | && iv1->extend != IV_UNKNOWN_EXTEND | |
50654f6c ZD |
2234 | && iv0->extend != iv1->extend) |
2235 | return false; | |
2236 | ||
2237 | signed_p = false; | |
1c1ad7bb SB |
2238 | if (iv0->extend != IV_UNKNOWN_EXTEND) |
2239 | signed_p = iv0->extend == IV_SIGN_EXTEND; | |
2240 | if (iv1->extend != IV_UNKNOWN_EXTEND) | |
2241 | signed_p = iv1->extend == IV_SIGN_EXTEND; | |
50654f6c ZD |
2242 | break; |
2243 | ||
2244 | default: | |
b5e624c6 | 2245 | gcc_unreachable (); |
50654f6c ZD |
2246 | } |
2247 | ||
2248 | /* Values of both variables should be computed in the same mode. These | |
2249 | might indeed be different, if we have comparison like | |
2250 | ||
2251 | (compare (subreg:SI (iv0)) (subreg:SI (iv1))) | |
2252 | ||
2253 | and iv0 and iv1 are both ivs iterating in SI mode, but calculated | |
2254 | in different modes. This does not seem impossible to handle, but | |
2255 | it hardly ever occurs in practice. | |
b8698a0f | 2256 | |
50654f6c ZD |
2257 | The only exception is the case when one of operands is invariant. |
2258 | For example pentium 3 generates comparisons like | |
2259 | (lt (subreg:HI (reg:SI)) 100). Here we assign HImode to 100, but we | |
2260 | definitely do not want this prevent the optimization. */ | |
2261 | comp_mode = iv0->extend_mode; | |
2262 | if (GET_MODE_BITSIZE (comp_mode) < GET_MODE_BITSIZE (iv1->extend_mode)) | |
2263 | comp_mode = iv1->extend_mode; | |
2264 | ||
2265 | if (iv0->extend_mode != comp_mode) | |
2266 | { | |
2267 | if (iv0->mode != iv0->extend_mode | |
2268 | || iv0->step != const0_rtx) | |
2269 | return false; | |
2270 | ||
2271 | iv0->base = simplify_gen_unary (signed_p ? SIGN_EXTEND : ZERO_EXTEND, | |
2272 | comp_mode, iv0->base, iv0->mode); | |
2273 | iv0->extend_mode = comp_mode; | |
2274 | } | |
2275 | ||
2276 | if (iv1->extend_mode != comp_mode) | |
2277 | { | |
2278 | if (iv1->mode != iv1->extend_mode | |
2279 | || iv1->step != const0_rtx) | |
2280 | return false; | |
2281 | ||
2282 | iv1->base = simplify_gen_unary (signed_p ? SIGN_EXTEND : ZERO_EXTEND, | |
2283 | comp_mode, iv1->base, iv1->mode); | |
2284 | iv1->extend_mode = comp_mode; | |
2285 | } | |
2286 | ||
2287 | /* Check that both ivs belong to a range of a single mode. If one of the | |
2288 | operands is an invariant, we may need to shorten it into the common | |
2289 | mode. */ | |
2290 | if (iv0->mode == iv0->extend_mode | |
2291 | && iv0->step == const0_rtx | |
2292 | && iv0->mode != iv1->mode) | |
2293 | shorten_into_mode (iv0, iv1->mode, cond, signed_p, desc); | |
2294 | ||
2295 | if (iv1->mode == iv1->extend_mode | |
2296 | && iv1->step == const0_rtx | |
2297 | && iv0->mode != iv1->mode) | |
2298 | shorten_into_mode (iv1, iv0->mode, swap_condition (cond), signed_p, desc); | |
2299 | ||
2300 | if (iv0->mode != iv1->mode) | |
2301 | return false; | |
2302 | ||
2303 | desc->mode = iv0->mode; | |
2304 | desc->signed_p = signed_p; | |
2305 | ||
2306 | return true; | |
2307 | } | |
2308 | ||
daa57386 RG |
2309 | /* Tries to estimate the maximum number of iterations in LOOP, and return the |
2310 | result. This function is called from iv_number_of_iterations with | |
28af33b0 BS |
2311 | a number of fields in DESC already filled in. OLD_NITER is the original |
2312 | expression for the number of iterations, before we tried to simplify it. */ | |
c67dc1a3 | 2313 | |
a9243bfc | 2314 | static uint64_t |
28af33b0 | 2315 | determine_max_iter (struct loop *loop, struct niter_desc *desc, rtx old_niter) |
c67dc1a3 BS |
2316 | { |
2317 | rtx niter = desc->niter_expr; | |
60683019 | 2318 | rtx mmin, mmax, cmp; |
a9243bfc RB |
2319 | uint64_t nmax, inc; |
2320 | uint64_t andmax = 0; | |
43ffba00 JH |
2321 | |
2322 | /* We used to look for constant operand 0 of AND, | |
2323 | but canonicalization should always make this impossible. */ | |
2324 | gcc_checking_assert (GET_CODE (niter) != AND | |
2325 | || !CONST_INT_P (XEXP (niter, 0))); | |
c67dc1a3 BS |
2326 | |
2327 | if (GET_CODE (niter) == AND | |
43ffba00 | 2328 | && CONST_INT_P (XEXP (niter, 1))) |
c67dc1a3 | 2329 | { |
43ffba00 JH |
2330 | andmax = UINTVAL (XEXP (niter, 1)); |
2331 | niter = XEXP (niter, 0); | |
c67dc1a3 BS |
2332 | } |
2333 | ||
2334 | get_mode_bounds (desc->mode, desc->signed_p, desc->mode, &mmin, &mmax); | |
d7ca26e4 | 2335 | nmax = UINTVAL (mmax) - UINTVAL (mmin); |
c67dc1a3 BS |
2336 | |
2337 | if (GET_CODE (niter) == UDIV) | |
2338 | { | |
481683e1 | 2339 | if (!CONST_INT_P (XEXP (niter, 1))) |
daa57386 | 2340 | return nmax; |
c67dc1a3 BS |
2341 | inc = INTVAL (XEXP (niter, 1)); |
2342 | niter = XEXP (niter, 0); | |
2343 | } | |
2344 | else | |
2345 | inc = 1; | |
2346 | ||
60683019 BS |
2347 | /* We could use a binary search here, but for now improving the upper |
2348 | bound by just one eliminates one important corner case. */ | |
28af33b0 BS |
2349 | cmp = simplify_gen_relational (desc->signed_p ? LT : LTU, VOIDmode, |
2350 | desc->mode, old_niter, mmax); | |
60683019 BS |
2351 | simplify_using_initial_values (loop, UNKNOWN, &cmp); |
2352 | if (cmp == const_true_rtx) | |
c67dc1a3 | 2353 | { |
60683019 | 2354 | nmax--; |
c67dc1a3 | 2355 | |
60683019 BS |
2356 | if (dump_file) |
2357 | fprintf (dump_file, ";; improved upper bound by one.\n"); | |
c67dc1a3 | 2358 | } |
43ffba00 JH |
2359 | nmax /= inc; |
2360 | if (andmax) | |
2361 | nmax = MIN (nmax, andmax); | |
2362 | if (dump_file) | |
a9243bfc | 2363 | fprintf (dump_file, ";; Determined upper bound %"PRId64".\n", |
43ffba00 JH |
2364 | nmax); |
2365 | return nmax; | |
c67dc1a3 BS |
2366 | } |
2367 | ||
50654f6c ZD |
2368 | /* Computes number of iterations of the CONDITION in INSN in LOOP and stores |
2369 | the result into DESC. Very similar to determine_number_of_iterations | |
2370 | (basically its rtl version), complicated by things like subregs. */ | |
2371 | ||
e3715ebd | 2372 | static void |
1b20d55a | 2373 | iv_number_of_iterations (struct loop *loop, rtx_insn *insn, rtx condition, |
50654f6c ZD |
2374 | struct niter_desc *desc) |
2375 | { | |
03fd2215 | 2376 | rtx op0, op1, delta, step, bound, may_xform, tmp, tmp0, tmp1; |
50654f6c | 2377 | struct rtx_iv iv0, iv1, tmp_iv; |
0aea6467 | 2378 | rtx assumption, may_not_xform; |
50654f6c | 2379 | enum rtx_code cond; |
ef4bddc2 | 2380 | machine_mode mode, comp_mode; |
0aea6467 | 2381 | rtx mmin, mmax, mode_mmin, mode_mmax; |
a9243bfc RB |
2382 | uint64_t s, size, d, inv, max; |
2383 | int64_t up, down, inc, step_val; | |
50654f6c | 2384 | int was_sharp = false; |
fe3f617f | 2385 | rtx old_niter; |
6b9b7b4c | 2386 | bool step_is_pow2; |
50654f6c ZD |
2387 | |
2388 | /* The meaning of these assumptions is this: | |
2389 | if !assumptions | |
2390 | then the rest of information does not have to be valid | |
2391 | if noloop_assumptions then the loop does not roll | |
2392 | if infinite then this exit is never used */ | |
2393 | ||
2394 | desc->assumptions = NULL_RTX; | |
2395 | desc->noloop_assumptions = NULL_RTX; | |
2396 | desc->infinite = NULL_RTX; | |
2397 | desc->simple_p = true; | |
2398 | ||
2399 | desc->const_iter = false; | |
2400 | desc->niter_expr = NULL_RTX; | |
50654f6c ZD |
2401 | |
2402 | cond = GET_CODE (condition); | |
b5e624c6 | 2403 | gcc_assert (COMPARISON_P (condition)); |
50654f6c ZD |
2404 | |
2405 | mode = GET_MODE (XEXP (condition, 0)); | |
2406 | if (mode == VOIDmode) | |
2407 | mode = GET_MODE (XEXP (condition, 1)); | |
2408 | /* The constant comparisons should be folded. */ | |
b5e624c6 | 2409 | gcc_assert (mode != VOIDmode); |
50654f6c ZD |
2410 | |
2411 | /* We only handle integers or pointers. */ | |
2412 | if (GET_MODE_CLASS (mode) != MODE_INT | |
2413 | && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT) | |
2414 | goto fail; | |
2415 | ||
2416 | op0 = XEXP (condition, 0); | |
03fd2215 | 2417 | if (!iv_analyze (insn, op0, &iv0)) |
50654f6c ZD |
2418 | goto fail; |
2419 | if (iv0.extend_mode == VOIDmode) | |
2420 | iv0.mode = iv0.extend_mode = mode; | |
b8698a0f | 2421 | |
50654f6c | 2422 | op1 = XEXP (condition, 1); |
03fd2215 | 2423 | if (!iv_analyze (insn, op1, &iv1)) |
50654f6c ZD |
2424 | goto fail; |
2425 | if (iv1.extend_mode == VOIDmode) | |
2426 | iv1.mode = iv1.extend_mode = mode; | |
2427 | ||
2428 | if (GET_MODE_BITSIZE (iv0.extend_mode) > HOST_BITS_PER_WIDE_INT | |
2429 | || GET_MODE_BITSIZE (iv1.extend_mode) > HOST_BITS_PER_WIDE_INT) | |
2430 | goto fail; | |
2431 | ||
2432 | /* Check condition and normalize it. */ | |
2433 | ||
2434 | switch (cond) | |
2435 | { | |
2436 | case GE: | |
2437 | case GT: | |
2438 | case GEU: | |
2439 | case GTU: | |
2440 | tmp_iv = iv0; iv0 = iv1; iv1 = tmp_iv; | |
2441 | cond = swap_condition (cond); | |
2442 | break; | |
2443 | case NE: | |
2444 | case LE: | |
2445 | case LEU: | |
2446 | case LT: | |
2447 | case LTU: | |
2448 | break; | |
2449 | default: | |
2450 | goto fail; | |
2451 | } | |
2452 | ||
2453 | /* Handle extends. This is relatively nontrivial, so we only try in some | |
2454 | easy cases, when we can canonicalize the ivs (possibly by adding some | |
2455 | assumptions) to shape subreg (base + i * step). This function also fills | |
2456 | in desc->mode and desc->signed_p. */ | |
2457 | ||
2458 | if (!canonicalize_iv_subregs (&iv0, &iv1, cond, desc)) | |
2459 | goto fail; | |
2460 | ||
2461 | comp_mode = iv0.extend_mode; | |
2462 | mode = iv0.mode; | |
50b6ee8b | 2463 | size = GET_MODE_PRECISION (mode); |
0aea6467 | 2464 | get_mode_bounds (mode, (cond == LE || cond == LT), comp_mode, &mmin, &mmax); |
6c3b938d RS |
2465 | mode_mmin = lowpart_subreg (mode, mmin, comp_mode); |
2466 | mode_mmax = lowpart_subreg (mode, mmax, comp_mode); | |
50654f6c | 2467 | |
481683e1 | 2468 | if (!CONST_INT_P (iv0.step) || !CONST_INT_P (iv1.step)) |
50654f6c ZD |
2469 | goto fail; |
2470 | ||
2471 | /* We can take care of the case of two induction variables chasing each other | |
2472 | if the test is NE. I have never seen a loop using it, but still it is | |
2473 | cool. */ | |
2474 | if (iv0.step != const0_rtx && iv1.step != const0_rtx) | |
2475 | { | |
2476 | if (cond != NE) | |
2477 | goto fail; | |
2478 | ||
2479 | iv0.step = simplify_gen_binary (MINUS, comp_mode, iv0.step, iv1.step); | |
2480 | iv1.step = const0_rtx; | |
2481 | } | |
2482 | ||
3461a16e JJ |
2483 | iv0.step = lowpart_subreg (mode, iv0.step, comp_mode); |
2484 | iv1.step = lowpart_subreg (mode, iv1.step, comp_mode); | |
2485 | ||
50654f6c ZD |
2486 | /* This is either infinite loop or the one that ends immediately, depending |
2487 | on initial values. Unswitching should remove this kind of conditions. */ | |
2488 | if (iv0.step == const0_rtx && iv1.step == const0_rtx) | |
2489 | goto fail; | |
2490 | ||
6b9b7b4c ZD |
2491 | if (cond != NE) |
2492 | { | |
2493 | if (iv0.step == const0_rtx) | |
2494 | step_val = -INTVAL (iv1.step); | |
2495 | else | |
6e17f9c1 | 2496 | step_val = INTVAL (iv0.step); |
6b9b7b4c ZD |
2497 | |
2498 | /* Ignore loops of while (i-- < 10) type. */ | |
2499 | if (step_val < 0) | |
2500 | goto fail; | |
2501 | ||
2502 | step_is_pow2 = !(step_val & (step_val - 1)); | |
2503 | } | |
2504 | else | |
2505 | { | |
2506 | /* We do not care about whether the step is power of two in this | |
2507 | case. */ | |
2508 | step_is_pow2 = false; | |
2509 | step_val = 0; | |
2510 | } | |
50654f6c ZD |
2511 | |
2512 | /* Some more condition normalization. We must record some assumptions | |
2513 | due to overflows. */ | |
2514 | switch (cond) | |
2515 | { | |
2516 | case LT: | |
2517 | case LTU: | |
2518 | /* We want to take care only of non-sharp relationals; this is easy, | |
2519 | as in cases the overflow would make the transformation unsafe | |
2520 | the loop does not roll. Seemingly it would make more sense to want | |
2521 | to take care of sharp relationals instead, as NE is more similar to | |
2522 | them, but the problem is that here the transformation would be more | |
2523 | difficult due to possibly infinite loops. */ | |
2524 | if (iv0.step == const0_rtx) | |
2525 | { | |
6c3b938d | 2526 | tmp = lowpart_subreg (mode, iv0.base, comp_mode); |
0aea6467 ZD |
2527 | assumption = simplify_gen_relational (EQ, SImode, mode, tmp, |
2528 | mode_mmax); | |
50654f6c | 2529 | if (assumption == const_true_rtx) |
4fbe4f91 | 2530 | goto zero_iter_simplify; |
50654f6c ZD |
2531 | iv0.base = simplify_gen_binary (PLUS, comp_mode, |
2532 | iv0.base, const1_rtx); | |
2533 | } | |
2534 | else | |
2535 | { | |
6c3b938d | 2536 | tmp = lowpart_subreg (mode, iv1.base, comp_mode); |
0aea6467 ZD |
2537 | assumption = simplify_gen_relational (EQ, SImode, mode, tmp, |
2538 | mode_mmin); | |
50654f6c | 2539 | if (assumption == const_true_rtx) |
4fbe4f91 | 2540 | goto zero_iter_simplify; |
50654f6c ZD |
2541 | iv1.base = simplify_gen_binary (PLUS, comp_mode, |
2542 | iv1.base, constm1_rtx); | |
2543 | } | |
2544 | ||
2545 | if (assumption != const0_rtx) | |
2546 | desc->noloop_assumptions = | |
2547 | alloc_EXPR_LIST (0, assumption, desc->noloop_assumptions); | |
2548 | cond = (cond == LT) ? LE : LEU; | |
2549 | ||
2550 | /* It will be useful to be able to tell the difference once more in | |
2551 | LE -> NE reduction. */ | |
2552 | was_sharp = true; | |
2553 | break; | |
2554 | default: ; | |
2555 | } | |
2556 | ||
2557 | /* Take care of trivially infinite loops. */ | |
2558 | if (cond != NE) | |
2559 | { | |
2560 | if (iv0.step == const0_rtx) | |
2561 | { | |
6c3b938d | 2562 | tmp = lowpart_subreg (mode, iv0.base, comp_mode); |
0aea6467 | 2563 | if (rtx_equal_p (tmp, mode_mmin)) |
50654f6c ZD |
2564 | { |
2565 | desc->infinite = | |
2566 | alloc_EXPR_LIST (0, const_true_rtx, NULL_RTX); | |
4fbe4f91 ZD |
2567 | /* Fill in the remaining fields somehow. */ |
2568 | goto zero_iter_simplify; | |
50654f6c ZD |
2569 | } |
2570 | } | |
2571 | else | |
2572 | { | |
6c3b938d | 2573 | tmp = lowpart_subreg (mode, iv1.base, comp_mode); |
0aea6467 | 2574 | if (rtx_equal_p (tmp, mode_mmax)) |
50654f6c ZD |
2575 | { |
2576 | desc->infinite = | |
2577 | alloc_EXPR_LIST (0, const_true_rtx, NULL_RTX); | |
4fbe4f91 ZD |
2578 | /* Fill in the remaining fields somehow. */ |
2579 | goto zero_iter_simplify; | |
50654f6c ZD |
2580 | } |
2581 | } | |
2582 | } | |
2583 | ||
2584 | /* If we can we want to take care of NE conditions instead of size | |
2585 | comparisons, as they are much more friendly (most importantly | |
2586 | this takes care of special handling of loops with step 1). We can | |
2587 | do it if we first check that upper bound is greater or equal to | |
2588 | lower bound, their difference is constant c modulo step and that | |
2589 | there is not an overflow. */ | |
2590 | if (cond != NE) | |
2591 | { | |
2592 | if (iv0.step == const0_rtx) | |
2593 | step = simplify_gen_unary (NEG, comp_mode, iv1.step, comp_mode); | |
2594 | else | |
2595 | step = iv0.step; | |
3461a16e | 2596 | step = lowpart_subreg (mode, step, comp_mode); |
50654f6c | 2597 | delta = simplify_gen_binary (MINUS, comp_mode, iv1.base, iv0.base); |
6c3b938d | 2598 | delta = lowpart_subreg (mode, delta, comp_mode); |
50654f6c ZD |
2599 | delta = simplify_gen_binary (UMOD, mode, delta, step); |
2600 | may_xform = const0_rtx; | |
0aea6467 | 2601 | may_not_xform = const_true_rtx; |
50654f6c | 2602 | |
481683e1 | 2603 | if (CONST_INT_P (delta)) |
50654f6c ZD |
2604 | { |
2605 | if (was_sharp && INTVAL (delta) == INTVAL (step) - 1) | |
2606 | { | |
2607 | /* A special case. We have transformed condition of type | |
2608 | for (i = 0; i < 4; i += 4) | |
2609 | into | |
2610 | for (i = 0; i <= 3; i += 4) | |
2611 | obviously if the test for overflow during that transformation | |
2612 | passed, we cannot overflow here. Most importantly any | |
2613 | loop with sharp end condition and step 1 falls into this | |
a1105617 | 2614 | category, so handling this case specially is definitely |
50654f6c ZD |
2615 | worth the troubles. */ |
2616 | may_xform = const_true_rtx; | |
2617 | } | |
2618 | else if (iv0.step == const0_rtx) | |
2619 | { | |
2620 | bound = simplify_gen_binary (PLUS, comp_mode, mmin, step); | |
2621 | bound = simplify_gen_binary (MINUS, comp_mode, bound, delta); | |
6c3b938d RS |
2622 | bound = lowpart_subreg (mode, bound, comp_mode); |
2623 | tmp = lowpart_subreg (mode, iv0.base, comp_mode); | |
50654f6c ZD |
2624 | may_xform = simplify_gen_relational (cond, SImode, mode, |
2625 | bound, tmp); | |
0aea6467 ZD |
2626 | may_not_xform = simplify_gen_relational (reverse_condition (cond), |
2627 | SImode, mode, | |
2628 | bound, tmp); | |
50654f6c ZD |
2629 | } |
2630 | else | |
2631 | { | |
2632 | bound = simplify_gen_binary (MINUS, comp_mode, mmax, step); | |
2633 | bound = simplify_gen_binary (PLUS, comp_mode, bound, delta); | |
6c3b938d RS |
2634 | bound = lowpart_subreg (mode, bound, comp_mode); |
2635 | tmp = lowpart_subreg (mode, iv1.base, comp_mode); | |
50654f6c ZD |
2636 | may_xform = simplify_gen_relational (cond, SImode, mode, |
2637 | tmp, bound); | |
0aea6467 ZD |
2638 | may_not_xform = simplify_gen_relational (reverse_condition (cond), |
2639 | SImode, mode, | |
2640 | tmp, bound); | |
50654f6c ZD |
2641 | } |
2642 | } | |
2643 | ||
2644 | if (may_xform != const0_rtx) | |
2645 | { | |
2646 | /* We perform the transformation always provided that it is not | |
2647 | completely senseless. This is OK, as we would need this assumption | |
2648 | to determine the number of iterations anyway. */ | |
2649 | if (may_xform != const_true_rtx) | |
0aea6467 ZD |
2650 | { |
2651 | /* If the step is a power of two and the final value we have | |
2652 | computed overflows, the cycle is infinite. Otherwise it | |
2653 | is nontrivial to compute the number of iterations. */ | |
6b9b7b4c | 2654 | if (step_is_pow2) |
0aea6467 ZD |
2655 | desc->infinite = alloc_EXPR_LIST (0, may_not_xform, |
2656 | desc->infinite); | |
2657 | else | |
2658 | desc->assumptions = alloc_EXPR_LIST (0, may_xform, | |
2659 | desc->assumptions); | |
2660 | } | |
50654f6c ZD |
2661 | |
2662 | /* We are going to lose some information about upper bound on | |
2663 | number of iterations in this step, so record the information | |
2664 | here. */ | |
2665 | inc = INTVAL (iv0.step) - INTVAL (iv1.step); | |
481683e1 | 2666 | if (CONST_INT_P (iv1.base)) |
50654f6c ZD |
2667 | up = INTVAL (iv1.base); |
2668 | else | |
0aea6467 | 2669 | up = INTVAL (mode_mmax) - inc; |
481683e1 | 2670 | down = INTVAL (CONST_INT_P (iv0.base) |
0aea6467 ZD |
2671 | ? iv0.base |
2672 | : mode_mmin); | |
d7ca26e4 | 2673 | max = (uint64_t) (up - down) / inc + 1; |
bcd8d322 JH |
2674 | if (!desc->infinite |
2675 | && !desc->assumptions) | |
807e902e | 2676 | record_niter_bound (loop, max, false, true); |
50654f6c ZD |
2677 | |
2678 | if (iv0.step == const0_rtx) | |
2679 | { | |
2680 | iv0.base = simplify_gen_binary (PLUS, comp_mode, iv0.base, delta); | |
2681 | iv0.base = simplify_gen_binary (MINUS, comp_mode, iv0.base, step); | |
2682 | } | |
2683 | else | |
2684 | { | |
2685 | iv1.base = simplify_gen_binary (MINUS, comp_mode, iv1.base, delta); | |
2686 | iv1.base = simplify_gen_binary (PLUS, comp_mode, iv1.base, step); | |
2687 | } | |
2688 | ||
6c3b938d RS |
2689 | tmp0 = lowpart_subreg (mode, iv0.base, comp_mode); |
2690 | tmp1 = lowpart_subreg (mode, iv1.base, comp_mode); | |
50654f6c ZD |
2691 | assumption = simplify_gen_relational (reverse_condition (cond), |
2692 | SImode, mode, tmp0, tmp1); | |
2693 | if (assumption == const_true_rtx) | |
4fbe4f91 | 2694 | goto zero_iter_simplify; |
50654f6c ZD |
2695 | else if (assumption != const0_rtx) |
2696 | desc->noloop_assumptions = | |
2697 | alloc_EXPR_LIST (0, assumption, desc->noloop_assumptions); | |
2698 | cond = NE; | |
2699 | } | |
2700 | } | |
2701 | ||
2702 | /* Count the number of iterations. */ | |
2703 | if (cond == NE) | |
2704 | { | |
2705 | /* Everything we do here is just arithmetics modulo size of mode. This | |
2706 | makes us able to do more involved computations of number of iterations | |
2707 | than in other cases. First transform the condition into shape | |
2708 | s * i <> c, with s positive. */ | |
2709 | iv1.base = simplify_gen_binary (MINUS, comp_mode, iv1.base, iv0.base); | |
2710 | iv0.base = const0_rtx; | |
2711 | iv0.step = simplify_gen_binary (MINUS, comp_mode, iv0.step, iv1.step); | |
2712 | iv1.step = const0_rtx; | |
2713 | if (INTVAL (iv0.step) < 0) | |
2714 | { | |
807e902e KZ |
2715 | iv0.step = simplify_gen_unary (NEG, comp_mode, iv0.step, comp_mode); |
2716 | iv1.base = simplify_gen_unary (NEG, comp_mode, iv1.base, comp_mode); | |
50654f6c | 2717 | } |
6c3b938d | 2718 | iv0.step = lowpart_subreg (mode, iv0.step, comp_mode); |
50654f6c ZD |
2719 | |
2720 | /* Let nsd (s, size of mode) = d. If d does not divide c, the loop | |
2721 | is infinite. Otherwise, the number of iterations is | |
2722 | (inverse(s/d) * (c/d)) mod (size of mode/d). */ | |
2723 | s = INTVAL (iv0.step); d = 1; | |
2724 | while (s % 2 != 1) | |
2725 | { | |
2726 | s /= 2; | |
2727 | d *= 2; | |
2728 | size--; | |
2729 | } | |
a9243bfc | 2730 | bound = GEN_INT (((uint64_t) 1 << (size - 1 ) << 1) - 1); |
50654f6c | 2731 | |
6c3b938d | 2732 | tmp1 = lowpart_subreg (mode, iv1.base, comp_mode); |
69a59f0f | 2733 | tmp = simplify_gen_binary (UMOD, mode, tmp1, gen_int_mode (d, mode)); |
50654f6c ZD |
2734 | assumption = simplify_gen_relational (NE, SImode, mode, tmp, const0_rtx); |
2735 | desc->infinite = alloc_EXPR_LIST (0, assumption, desc->infinite); | |
2736 | ||
69a59f0f | 2737 | tmp = simplify_gen_binary (UDIV, mode, tmp1, gen_int_mode (d, mode)); |
0aea6467 | 2738 | inv = inverse (s, size); |
bb80db7b | 2739 | tmp = simplify_gen_binary (MULT, mode, tmp, gen_int_mode (inv, mode)); |
50654f6c ZD |
2740 | desc->niter_expr = simplify_gen_binary (AND, mode, tmp, bound); |
2741 | } | |
2742 | else | |
2743 | { | |
2744 | if (iv1.step == const0_rtx) | |
2745 | /* Condition in shape a + s * i <= b | |
2746 | We must know that b + s does not overflow and a <= b + s and then we | |
2747 | can compute number of iterations as (b + s - a) / s. (It might | |
2748 | seem that we in fact could be more clever about testing the b + s | |
2749 | overflow condition using some information about b - a mod s, | |
2750 | but it was already taken into account during LE -> NE transform). */ | |
2751 | { | |
2752 | step = iv0.step; | |
6c3b938d RS |
2753 | tmp0 = lowpart_subreg (mode, iv0.base, comp_mode); |
2754 | tmp1 = lowpart_subreg (mode, iv1.base, comp_mode); | |
50654f6c | 2755 | |
0aea6467 | 2756 | bound = simplify_gen_binary (MINUS, mode, mode_mmax, |
6c3b938d RS |
2757 | lowpart_subreg (mode, step, |
2758 | comp_mode)); | |
6b9b7b4c ZD |
2759 | if (step_is_pow2) |
2760 | { | |
2761 | rtx t0, t1; | |
2762 | ||
2763 | /* If s is power of 2, we know that the loop is infinite if | |
2764 | a % s <= b % s and b + s overflows. */ | |
2765 | assumption = simplify_gen_relational (reverse_condition (cond), | |
2766 | SImode, mode, | |
2767 | tmp1, bound); | |
2768 | ||
2769 | t0 = simplify_gen_binary (UMOD, mode, copy_rtx (tmp0), step); | |
2770 | t1 = simplify_gen_binary (UMOD, mode, copy_rtx (tmp1), step); | |
2771 | tmp = simplify_gen_relational (cond, SImode, mode, t0, t1); | |
2772 | assumption = simplify_gen_binary (AND, SImode, assumption, tmp); | |
2773 | desc->infinite = | |
2774 | alloc_EXPR_LIST (0, assumption, desc->infinite); | |
2775 | } | |
2776 | else | |
2777 | { | |
2778 | assumption = simplify_gen_relational (cond, SImode, mode, | |
2779 | tmp1, bound); | |
2780 | desc->assumptions = | |
2781 | alloc_EXPR_LIST (0, assumption, desc->assumptions); | |
2782 | } | |
50654f6c ZD |
2783 | |
2784 | tmp = simplify_gen_binary (PLUS, comp_mode, iv1.base, iv0.step); | |
6c3b938d | 2785 | tmp = lowpart_subreg (mode, tmp, comp_mode); |
50654f6c ZD |
2786 | assumption = simplify_gen_relational (reverse_condition (cond), |
2787 | SImode, mode, tmp0, tmp); | |
2788 | ||
2789 | delta = simplify_gen_binary (PLUS, mode, tmp1, step); | |
2790 | delta = simplify_gen_binary (MINUS, mode, delta, tmp0); | |
2791 | } | |
2792 | else | |
2793 | { | |
2794 | /* Condition in shape a <= b - s * i | |
2795 | We must know that a - s does not overflow and a - s <= b and then | |
2796 | we can again compute number of iterations as (b - (a - s)) / s. */ | |
2797 | step = simplify_gen_unary (NEG, mode, iv1.step, mode); | |
6c3b938d RS |
2798 | tmp0 = lowpart_subreg (mode, iv0.base, comp_mode); |
2799 | tmp1 = lowpart_subreg (mode, iv1.base, comp_mode); | |
50654f6c | 2800 | |
c9eb8097 | 2801 | bound = simplify_gen_binary (PLUS, mode, mode_mmin, |
6c3b938d | 2802 | lowpart_subreg (mode, step, comp_mode)); |
6b9b7b4c ZD |
2803 | if (step_is_pow2) |
2804 | { | |
2805 | rtx t0, t1; | |
2806 | ||
2807 | /* If s is power of 2, we know that the loop is infinite if | |
2808 | a % s <= b % s and a - s overflows. */ | |
2809 | assumption = simplify_gen_relational (reverse_condition (cond), | |
2810 | SImode, mode, | |
2811 | bound, tmp0); | |
2812 | ||
2813 | t0 = simplify_gen_binary (UMOD, mode, copy_rtx (tmp0), step); | |
2814 | t1 = simplify_gen_binary (UMOD, mode, copy_rtx (tmp1), step); | |
2815 | tmp = simplify_gen_relational (cond, SImode, mode, t0, t1); | |
2816 | assumption = simplify_gen_binary (AND, SImode, assumption, tmp); | |
2817 | desc->infinite = | |
2818 | alloc_EXPR_LIST (0, assumption, desc->infinite); | |
2819 | } | |
2820 | else | |
2821 | { | |
2822 | assumption = simplify_gen_relational (cond, SImode, mode, | |
2823 | bound, tmp0); | |
2824 | desc->assumptions = | |
2825 | alloc_EXPR_LIST (0, assumption, desc->assumptions); | |
2826 | } | |
50654f6c ZD |
2827 | |
2828 | tmp = simplify_gen_binary (PLUS, comp_mode, iv0.base, iv1.step); | |
6c3b938d | 2829 | tmp = lowpart_subreg (mode, tmp, comp_mode); |
50654f6c ZD |
2830 | assumption = simplify_gen_relational (reverse_condition (cond), |
2831 | SImode, mode, | |
2832 | tmp, tmp1); | |
2833 | delta = simplify_gen_binary (MINUS, mode, tmp0, step); | |
2834 | delta = simplify_gen_binary (MINUS, mode, tmp1, delta); | |
2835 | } | |
2836 | if (assumption == const_true_rtx) | |
4fbe4f91 | 2837 | goto zero_iter_simplify; |
50654f6c ZD |
2838 | else if (assumption != const0_rtx) |
2839 | desc->noloop_assumptions = | |
2840 | alloc_EXPR_LIST (0, assumption, desc->noloop_assumptions); | |
2841 | delta = simplify_gen_binary (UDIV, mode, delta, step); | |
2842 | desc->niter_expr = delta; | |
2843 | } | |
2844 | ||
fe3f617f ZD |
2845 | old_niter = desc->niter_expr; |
2846 | ||
50654f6c ZD |
2847 | simplify_using_initial_values (loop, AND, &desc->assumptions); |
2848 | if (desc->assumptions | |
2849 | && XEXP (desc->assumptions, 0) == const0_rtx) | |
2850 | goto fail; | |
2851 | simplify_using_initial_values (loop, IOR, &desc->noloop_assumptions); | |
2852 | simplify_using_initial_values (loop, IOR, &desc->infinite); | |
f822d252 | 2853 | simplify_using_initial_values (loop, UNKNOWN, &desc->niter_expr); |
50654f6c ZD |
2854 | |
2855 | /* Rerun the simplification. Consider code (created by copying loop headers) | |
2856 | ||
2857 | i = 0; | |
2858 | ||
2859 | if (0 < n) | |
2860 | { | |
2861 | do | |
2862 | { | |
2863 | i++; | |
2864 | } while (i < n); | |
2865 | } | |
2866 | ||
2867 | The first pass determines that i = 0, the second pass uses it to eliminate | |
2868 | noloop assumption. */ | |
2869 | ||
2870 | simplify_using_initial_values (loop, AND, &desc->assumptions); | |
2871 | if (desc->assumptions | |
2872 | && XEXP (desc->assumptions, 0) == const0_rtx) | |
2873 | goto fail; | |
2874 | simplify_using_initial_values (loop, IOR, &desc->noloop_assumptions); | |
2875 | simplify_using_initial_values (loop, IOR, &desc->infinite); | |
f822d252 | 2876 | simplify_using_initial_values (loop, UNKNOWN, &desc->niter_expr); |
50654f6c | 2877 | |
689ba89d ZD |
2878 | if (desc->noloop_assumptions |
2879 | && XEXP (desc->noloop_assumptions, 0) == const_true_rtx) | |
2880 | goto zero_iter; | |
2881 | ||
481683e1 | 2882 | if (CONST_INT_P (desc->niter_expr)) |
50654f6c | 2883 | { |
a9243bfc | 2884 | uint64_t val = INTVAL (desc->niter_expr); |
50654f6c ZD |
2885 | |
2886 | desc->const_iter = true; | |
e3a8f1fa | 2887 | desc->niter = val & GET_MODE_MASK (desc->mode); |
bcd8d322 JH |
2888 | if (!desc->infinite |
2889 | && !desc->assumptions) | |
807e902e | 2890 | record_niter_bound (loop, desc->niter, false, true); |
50654f6c | 2891 | } |
fe3f617f ZD |
2892 | else |
2893 | { | |
daa57386 | 2894 | max = determine_max_iter (loop, desc, old_niter); |
8386a7ea JH |
2895 | if (!max) |
2896 | goto zero_iter_simplify; | |
bcd8d322 JH |
2897 | if (!desc->infinite |
2898 | && !desc->assumptions) | |
807e902e | 2899 | record_niter_bound (loop, max, false, true); |
fe3f617f ZD |
2900 | |
2901 | /* simplify_using_initial_values does a copy propagation on the registers | |
2902 | in the expression for the number of iterations. This prolongs life | |
2903 | ranges of registers and increases register pressure, and usually | |
2904 | brings no gain (and if it happens to do, the cse pass will take care | |
2905 | of it anyway). So prevent this behavior, unless it enabled us to | |
2906 | derive that the number of iterations is a constant. */ | |
2907 | desc->niter_expr = old_niter; | |
2908 | } | |
50654f6c ZD |
2909 | |
2910 | return; | |
2911 | ||
4fbe4f91 ZD |
2912 | zero_iter_simplify: |
2913 | /* Simplify the assumptions. */ | |
2914 | simplify_using_initial_values (loop, AND, &desc->assumptions); | |
2915 | if (desc->assumptions | |
2916 | && XEXP (desc->assumptions, 0) == const0_rtx) | |
2917 | goto fail; | |
2918 | simplify_using_initial_values (loop, IOR, &desc->infinite); | |
50654f6c | 2919 | |
4fbe4f91 | 2920 | /* Fallthru. */ |
50654f6c ZD |
2921 | zero_iter: |
2922 | desc->const_iter = true; | |
2923 | desc->niter = 0; | |
807e902e | 2924 | record_niter_bound (loop, 0, true, true); |
4fbe4f91 | 2925 | desc->noloop_assumptions = NULL_RTX; |
50654f6c ZD |
2926 | desc->niter_expr = const0_rtx; |
2927 | return; | |
4fbe4f91 ZD |
2928 | |
2929 | fail: | |
2930 | desc->simple_p = false; | |
2931 | return; | |
50654f6c ZD |
2932 | } |
2933 | ||
2934 | /* Checks whether E is a simple exit from LOOP and stores its description | |
f2dca510 | 2935 | into DESC. */ |
50654f6c ZD |
2936 | |
2937 | static void | |
2938 | check_simple_exit (struct loop *loop, edge e, struct niter_desc *desc) | |
2939 | { | |
2940 | basic_block exit_bb; | |
61aa0978 DM |
2941 | rtx condition; |
2942 | rtx_insn *at; | |
628f6a4e | 2943 | edge ein; |
50654f6c ZD |
2944 | |
2945 | exit_bb = e->src; | |
2946 | desc->simple_p = false; | |
2947 | ||
2948 | /* It must belong directly to the loop. */ | |
2949 | if (exit_bb->loop_father != loop) | |
2950 | return; | |
2951 | ||
2952 | /* It must be tested (at least) once during any iteration. */ | |
7002f3bd | 2953 | if (!dominated_by_p (CDI_DOMINATORS, loop->latch, exit_bb)) |
50654f6c ZD |
2954 | return; |
2955 | ||
2956 | /* It must end in a simple conditional jump. */ | |
2957 | if (!any_condjump_p (BB_END (exit_bb))) | |
2958 | return; | |
2959 | ||
628f6a4e BE |
2960 | ein = EDGE_SUCC (exit_bb, 0); |
2961 | if (ein == e) | |
2962 | ein = EDGE_SUCC (exit_bb, 1); | |
50654f6c ZD |
2963 | |
2964 | desc->out_edge = e; | |
628f6a4e | 2965 | desc->in_edge = ein; |
50654f6c ZD |
2966 | |
2967 | /* Test whether the condition is suitable. */ | |
628f6a4e | 2968 | if (!(condition = get_condition (BB_END (ein->src), &at, false, false))) |
50654f6c ZD |
2969 | return; |
2970 | ||
628f6a4e | 2971 | if (ein->flags & EDGE_FALLTHRU) |
50654f6c ZD |
2972 | { |
2973 | condition = reversed_condition (condition); | |
2974 | if (!condition) | |
2975 | return; | |
2976 | } | |
2977 | ||
2978 | /* Check that we are able to determine number of iterations and fill | |
2979 | in information about it. */ | |
61aa0978 | 2980 | iv_number_of_iterations (loop, at, condition, desc); |
50654f6c ZD |
2981 | } |
2982 | ||
f2dca510 | 2983 | /* Finds a simple exit of LOOP and stores its description into DESC. */ |
50654f6c ZD |
2984 | |
2985 | void | |
2986 | find_simple_exit (struct loop *loop, struct niter_desc *desc) | |
2987 | { | |
2988 | unsigned i; | |
2989 | basic_block *body; | |
2990 | edge e; | |
2991 | struct niter_desc act; | |
2992 | bool any = false; | |
628f6a4e | 2993 | edge_iterator ei; |
50654f6c ZD |
2994 | |
2995 | desc->simple_p = false; | |
2996 | body = get_loop_body (loop); | |
2997 | ||
2998 | for (i = 0; i < loop->num_nodes; i++) | |
2999 | { | |
628f6a4e | 3000 | FOR_EACH_EDGE (e, ei, body[i]->succs) |
50654f6c ZD |
3001 | { |
3002 | if (flow_bb_inside_loop_p (loop, e->dest)) | |
3003 | continue; | |
b8698a0f | 3004 | |
50654f6c ZD |
3005 | check_simple_exit (loop, e, &act); |
3006 | if (!act.simple_p) | |
3007 | continue; | |
3008 | ||
50654f6c ZD |
3009 | if (!any) |
3010 | any = true; | |
4fbe4f91 ZD |
3011 | else |
3012 | { | |
3013 | /* Prefer constant iterations; the less the better. */ | |
3014 | if (!act.const_iter | |
3015 | || (desc->const_iter && act.niter >= desc->niter)) | |
3016 | continue; | |
3017 | ||
3018 | /* Also if the actual exit may be infinite, while the old one | |
3019 | not, prefer the old one. */ | |
3020 | if (act.infinite && !desc->infinite) | |
3021 | continue; | |
3022 | } | |
b8698a0f | 3023 | |
50654f6c ZD |
3024 | *desc = act; |
3025 | } | |
3026 | } | |
3027 | ||
c263766c | 3028 | if (dump_file) |
50654f6c ZD |
3029 | { |
3030 | if (desc->simple_p) | |
3031 | { | |
c263766c RH |
3032 | fprintf (dump_file, "Loop %d is simple:\n", loop->num); |
3033 | fprintf (dump_file, " simple exit %d -> %d\n", | |
50654f6c ZD |
3034 | desc->out_edge->src->index, |
3035 | desc->out_edge->dest->index); | |
3036 | if (desc->assumptions) | |
3037 | { | |
c263766c RH |
3038 | fprintf (dump_file, " assumptions: "); |
3039 | print_rtl (dump_file, desc->assumptions); | |
3040 | fprintf (dump_file, "\n"); | |
50654f6c ZD |
3041 | } |
3042 | if (desc->noloop_assumptions) | |
3043 | { | |
c263766c RH |
3044 | fprintf (dump_file, " does not roll if: "); |
3045 | print_rtl (dump_file, desc->noloop_assumptions); | |
3046 | fprintf (dump_file, "\n"); | |
50654f6c ZD |
3047 | } |
3048 | if (desc->infinite) | |
3049 | { | |
c263766c RH |
3050 | fprintf (dump_file, " infinite if: "); |
3051 | print_rtl (dump_file, desc->infinite); | |
3052 | fprintf (dump_file, "\n"); | |
50654f6c ZD |
3053 | } |
3054 | ||
c263766c RH |
3055 | fprintf (dump_file, " number of iterations: "); |
3056 | print_rtl (dump_file, desc->niter_expr); | |
3057 | fprintf (dump_file, "\n"); | |
50654f6c | 3058 | |
e3a8f1fa | 3059 | fprintf (dump_file, " upper bound: %li\n", |
1ef88893 | 3060 | (long)get_max_loop_iterations_int (loop)); |
e3a8f1fa | 3061 | fprintf (dump_file, " realistic bound: %li\n", |
1ef88893 | 3062 | (long)get_estimated_loop_iterations_int (loop)); |
50654f6c ZD |
3063 | } |
3064 | else | |
c263766c | 3065 | fprintf (dump_file, "Loop %d is not simple.\n", loop->num); |
50654f6c ZD |
3066 | } |
3067 | ||
3068 | free (body); | |
3069 | } | |
3070 | ||
3071 | /* Creates a simple loop description of LOOP if it was not computed | |
3072 | already. */ | |
3073 | ||
3074 | struct niter_desc * | |
3075 | get_simple_loop_desc (struct loop *loop) | |
3076 | { | |
3077 | struct niter_desc *desc = simple_loop_desc (loop); | |
3078 | ||
3079 | if (desc) | |
3080 | return desc; | |
3081 | ||
1242bc9d R |
3082 | /* At least desc->infinite is not always initialized by |
3083 | find_simple_loop_exit. */ | |
766090c2 | 3084 | desc = ggc_cleared_alloc<niter_desc> (); |
50654f6c ZD |
3085 | iv_analysis_loop_init (loop); |
3086 | find_simple_exit (loop, desc); | |
ef23e6a2 | 3087 | loop->simple_loop_desc = desc; |
50654f6c | 3088 | |
f9cc1a70 PB |
3089 | if (desc->simple_p && (desc->assumptions || desc->infinite)) |
3090 | { | |
b8698a0f | 3091 | const char *wording; |
f9cc1a70 | 3092 | |
b8698a0f | 3093 | /* Assume that no overflow happens and that the loop is finite. |
f9cc1a70 PB |
3094 | We already warned at the tree level if we ran optimizations there. */ |
3095 | if (!flag_tree_loop_optimize && warn_unsafe_loop_optimizations) | |
3096 | { | |
3097 | if (desc->infinite) | |
3098 | { | |
b8698a0f | 3099 | wording = |
f9cc1a70 PB |
3100 | flag_unsafe_loop_optimizations |
3101 | ? N_("assuming that the loop is not infinite") | |
3102 | : N_("cannot optimize possibly infinite loops"); | |
3103 | warning (OPT_Wunsafe_loop_optimizations, "%s", | |
3104 | gettext (wording)); | |
3105 | } | |
3106 | if (desc->assumptions) | |
3107 | { | |
b8698a0f | 3108 | wording = |
f9cc1a70 PB |
3109 | flag_unsafe_loop_optimizations |
3110 | ? N_("assuming that the loop counter does not overflow") | |
3111 | : N_("cannot optimize loop, the loop counter may overflow"); | |
3112 | warning (OPT_Wunsafe_loop_optimizations, "%s", | |
3113 | gettext (wording)); | |
3114 | } | |
3115 | } | |
3116 | ||
3117 | if (flag_unsafe_loop_optimizations) | |
3118 | { | |
3119 | desc->assumptions = NULL_RTX; | |
3120 | desc->infinite = NULL_RTX; | |
3121 | } | |
3122 | } | |
3123 | ||
50654f6c ZD |
3124 | return desc; |
3125 | } | |
3126 | ||
3127 | /* Releases simple loop description for LOOP. */ | |
3128 | ||
3129 | void | |
3130 | free_simple_loop_desc (struct loop *loop) | |
3131 | { | |
3132 | struct niter_desc *desc = simple_loop_desc (loop); | |
3133 | ||
3134 | if (!desc) | |
3135 | return; | |
3136 | ||
ef23e6a2 RB |
3137 | ggc_free (desc); |
3138 | loop->simple_loop_desc = NULL; | |
50654f6c | 3139 | } |