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f9cce2dc | 1 | /* Rtl-level induction variable analysis. |
3aea1f79 | 2 | Copyright (C) 2004-2014 Free Software Foundation, Inc. |
48e1416a | 3 | |
f9cce2dc | 4 | This file is part of GCC. |
48e1416a | 5 | |
f9cce2dc | 6 | GCC is free software; you can redistribute it and/or modify it |
7 | under the terms of the GNU General Public License as published by the | |
8c4c00c1 | 8 | Free Software Foundation; either version 3, or (at your option) any |
f9cce2dc | 9 | later version. |
48e1416a | 10 | |
f9cce2dc | 11 | GCC is distributed in the hope that it will be useful, but WITHOUT |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
14 | for more details. | |
48e1416a | 15 | |
f9cce2dc | 16 | You should have received a copy of the GNU General Public License |
8c4c00c1 | 17 | along with GCC; see the file COPYING3. If not see |
18 | <http://www.gnu.org/licenses/>. */ | |
f9cce2dc | 19 | |
3f37d465 | 20 | /* This is a simple analysis of induction variables of the loop. The major use |
21 | is for determining the number of iterations of a loop for loop unrolling, | |
22 | doloop optimization and branch prediction. The iv information is computed | |
23 | on demand. | |
24 | ||
2e49e3bc | 25 | Induction variables are analyzed by walking the use-def chains. When |
26 | a basic induction variable (biv) is found, it is cached in the bivs | |
27 | hash table. When register is proved to be a biv, its description | |
28 | is stored to DF_REF_DATA of the def reference. | |
3f37d465 | 29 | |
30 | The analysis works always with one loop -- you must call | |
31 | iv_analysis_loop_init (loop) for it. All the other functions then work with | |
32 | this loop. When you need to work with another loop, just call | |
33 | iv_analysis_loop_init for it. When you no longer need iv analysis, call | |
34 | iv_analysis_done () to clean up the memory. | |
35 | ||
36 | The available functions are: | |
48e1416a | 37 | |
3f37d465 | 38 | iv_analyze (insn, reg, iv): Stores the description of the induction variable |
39 | corresponding to the use of register REG in INSN to IV. Returns true if | |
40 | REG is an induction variable in INSN. false otherwise. | |
41 | If use of REG is not found in INSN, following insns are scanned (so that | |
42 | we may call this function on insn returned by get_condition). | |
43 | iv_analyze_result (insn, def, iv): Stores to IV the description of the iv | |
44 | corresponding to DEF, which is a register defined in INSN. | |
45 | iv_analyze_expr (insn, rhs, mode, iv): Stores to IV the description of iv | |
46 | corresponding to expression EXPR evaluated at INSN. All registers used bu | |
47 | EXPR must also be used in INSN. | |
3072d30e | 48 | */ |
f9cce2dc | 49 | |
50 | #include "config.h" | |
51 | #include "system.h" | |
52 | #include "coretypes.h" | |
53 | #include "tm.h" | |
54 | #include "rtl.h" | |
55 | #include "hard-reg-set.h" | |
42fe97ed | 56 | #include "obstack.h" |
f9cce2dc | 57 | #include "basic-block.h" |
58 | #include "cfgloop.h" | |
59 | #include "expr.h" | |
7e3cc681 | 60 | #include "intl.h" |
0b205f4c | 61 | #include "diagnostic-core.h" |
3f37d465 | 62 | #include "df.h" |
d9dd21a8 | 63 | #include "hash-table.h" |
b9ed1410 | 64 | #include "dumpfile.h" |
f9cce2dc | 65 | |
3f37d465 | 66 | /* Possible return values of iv_get_reaching_def. */ |
f9cce2dc | 67 | |
3f37d465 | 68 | enum iv_grd_result |
f9cce2dc | 69 | { |
3f37d465 | 70 | /* More than one reaching def, or reaching def that does not |
71 | dominate the use. */ | |
72 | GRD_INVALID, | |
f9cce2dc | 73 | |
3f37d465 | 74 | /* The use is trivial invariant of the loop, i.e. is not changed |
75 | inside the loop. */ | |
76 | GRD_INVARIANT, | |
f9cce2dc | 77 | |
3f37d465 | 78 | /* The use is reached by initial value and a value from the |
79 | previous iteration. */ | |
80 | GRD_MAYBE_BIV, | |
81 | ||
82 | /* The use has single dominating def. */ | |
83 | GRD_SINGLE_DOM | |
84 | }; | |
85 | ||
86 | /* Information about a biv. */ | |
87 | ||
88 | struct biv_entry | |
89 | { | |
90 | unsigned regno; /* The register of the biv. */ | |
91 | struct rtx_iv iv; /* Value of the biv. */ | |
f9cce2dc | 92 | }; |
93 | ||
3072d30e | 94 | static bool clean_slate = true; |
95 | ||
96 | static unsigned int iv_ref_table_size = 0; | |
97 | ||
98 | /* Table of rtx_ivs indexed by the df_ref uid field. */ | |
99 | static struct rtx_iv ** iv_ref_table; | |
100 | ||
3f37d465 | 101 | /* Induction variable stored at the reference. */ |
9af5ce0c | 102 | #define DF_REF_IV(REF) iv_ref_table[DF_REF_ID (REF)] |
103 | #define DF_REF_IV_SET(REF, IV) iv_ref_table[DF_REF_ID (REF)] = (IV) | |
f9cce2dc | 104 | |
3f37d465 | 105 | /* The current loop. */ |
f9cce2dc | 106 | |
3f37d465 | 107 | static struct loop *current_loop; |
f9cce2dc | 108 | |
d9dd21a8 | 109 | /* Hashtable helper. */ |
110 | ||
111 | struct biv_entry_hasher : typed_free_remove <biv_entry> | |
112 | { | |
113 | typedef biv_entry value_type; | |
114 | typedef rtx_def compare_type; | |
115 | static inline hashval_t hash (const value_type *); | |
116 | static inline bool equal (const value_type *, const compare_type *); | |
117 | }; | |
118 | ||
119 | /* Returns hash value for biv B. */ | |
120 | ||
121 | inline hashval_t | |
122 | biv_entry_hasher::hash (const value_type *b) | |
123 | { | |
124 | return b->regno; | |
125 | } | |
126 | ||
127 | /* Compares biv B and register R. */ | |
128 | ||
129 | inline bool | |
130 | biv_entry_hasher::equal (const value_type *b, const compare_type *r) | |
131 | { | |
132 | return b->regno == REGNO (r); | |
133 | } | |
134 | ||
3f37d465 | 135 | /* Bivs of the current loop. */ |
f9cce2dc | 136 | |
c1f445d2 | 137 | static hash_table<biv_entry_hasher> *bivs; |
f9cce2dc | 138 | |
3eeb4f9a | 139 | static bool iv_analyze_op (rtx_insn *, rtx, struct rtx_iv *); |
f9cce2dc | 140 | |
aedb7bf8 | 141 | /* Return the RTX code corresponding to the IV extend code EXTEND. */ |
142 | static inline enum rtx_code | |
143 | iv_extend_to_rtx_code (enum iv_extend_code extend) | |
144 | { | |
145 | switch (extend) | |
146 | { | |
147 | case IV_SIGN_EXTEND: | |
148 | return SIGN_EXTEND; | |
149 | case IV_ZERO_EXTEND: | |
150 | return ZERO_EXTEND; | |
151 | case IV_UNKNOWN_EXTEND: | |
152 | return UNKNOWN; | |
153 | } | |
154 | gcc_unreachable (); | |
155 | } | |
156 | ||
f9cce2dc | 157 | /* Dumps information about IV to FILE. */ |
158 | ||
159 | extern void dump_iv_info (FILE *, struct rtx_iv *); | |
160 | void | |
161 | dump_iv_info (FILE *file, struct rtx_iv *iv) | |
162 | { | |
163 | if (!iv->base) | |
164 | { | |
165 | fprintf (file, "not simple"); | |
166 | return; | |
167 | } | |
168 | ||
bf9fa951 | 169 | if (iv->step == const0_rtx |
170 | && !iv->first_special) | |
171 | fprintf (file, "invariant "); | |
f9cce2dc | 172 | |
173 | print_rtl (file, iv->base); | |
bf9fa951 | 174 | if (iv->step != const0_rtx) |
175 | { | |
176 | fprintf (file, " + "); | |
177 | print_rtl (file, iv->step); | |
178 | fprintf (file, " * iteration"); | |
179 | } | |
f9cce2dc | 180 | fprintf (file, " (in %s)", GET_MODE_NAME (iv->mode)); |
181 | ||
182 | if (iv->mode != iv->extend_mode) | |
183 | fprintf (file, " %s to %s", | |
aedb7bf8 | 184 | rtx_name[iv_extend_to_rtx_code (iv->extend)], |
f9cce2dc | 185 | GET_MODE_NAME (iv->extend_mode)); |
186 | ||
187 | if (iv->mult != const1_rtx) | |
188 | { | |
189 | fprintf (file, " * "); | |
190 | print_rtl (file, iv->mult); | |
191 | } | |
192 | if (iv->delta != const0_rtx) | |
193 | { | |
194 | fprintf (file, " + "); | |
195 | print_rtl (file, iv->delta); | |
196 | } | |
197 | if (iv->first_special) | |
198 | fprintf (file, " (first special)"); | |
199 | } | |
200 | ||
c0efe3c3 | 201 | /* Generates a subreg to get the least significant part of EXPR (in mode |
202 | INNER_MODE) to OUTER_MODE. */ | |
f9cce2dc | 203 | |
c0efe3c3 | 204 | rtx |
205 | lowpart_subreg (enum machine_mode outer_mode, rtx expr, | |
206 | enum machine_mode inner_mode) | |
f9cce2dc | 207 | { |
c0efe3c3 | 208 | return simplify_gen_subreg (outer_mode, expr, inner_mode, |
209 | subreg_lowpart_offset (outer_mode, inner_mode)); | |
f9cce2dc | 210 | } |
211 | ||
48e1416a | 212 | static void |
3072d30e | 213 | check_iv_ref_table_size (void) |
214 | { | |
9af5ce0c | 215 | if (iv_ref_table_size < DF_DEFS_TABLE_SIZE ()) |
3072d30e | 216 | { |
217 | unsigned int new_size = DF_DEFS_TABLE_SIZE () + (DF_DEFS_TABLE_SIZE () / 4); | |
4077bf7a | 218 | iv_ref_table = XRESIZEVEC (struct rtx_iv *, iv_ref_table, new_size); |
48e1416a | 219 | memset (&iv_ref_table[iv_ref_table_size], 0, |
3072d30e | 220 | (new_size - iv_ref_table_size) * sizeof (struct rtx_iv *)); |
221 | iv_ref_table_size = new_size; | |
222 | } | |
223 | } | |
224 | ||
225 | ||
f9cce2dc | 226 | /* Checks whether REG is a well-behaved register. */ |
227 | ||
228 | static bool | |
229 | simple_reg_p (rtx reg) | |
230 | { | |
231 | unsigned r; | |
232 | ||
233 | if (GET_CODE (reg) == SUBREG) | |
234 | { | |
235 | if (!subreg_lowpart_p (reg)) | |
236 | return false; | |
237 | reg = SUBREG_REG (reg); | |
238 | } | |
239 | ||
240 | if (!REG_P (reg)) | |
241 | return false; | |
242 | ||
243 | r = REGNO (reg); | |
244 | if (HARD_REGISTER_NUM_P (r)) | |
245 | return false; | |
246 | ||
247 | if (GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT) | |
248 | return false; | |
249 | ||
f9cce2dc | 250 | return true; |
251 | } | |
252 | ||
3f37d465 | 253 | /* Clears the information about ivs stored in df. */ |
f9cce2dc | 254 | |
3f37d465 | 255 | static void |
256 | clear_iv_info (void) | |
f9cce2dc | 257 | { |
3072d30e | 258 | unsigned i, n_defs = DF_DEFS_TABLE_SIZE (); |
3f37d465 | 259 | struct rtx_iv *iv; |
f9cce2dc | 260 | |
3072d30e | 261 | check_iv_ref_table_size (); |
3f37d465 | 262 | for (i = 0; i < n_defs; i++) |
f9cce2dc | 263 | { |
3072d30e | 264 | iv = iv_ref_table[i]; |
265 | if (iv) | |
266 | { | |
267 | free (iv); | |
268 | iv_ref_table[i] = NULL; | |
269 | } | |
f9cce2dc | 270 | } |
f9cce2dc | 271 | |
c1f445d2 | 272 | bivs->empty (); |
f9cce2dc | 273 | } |
274 | ||
f9cce2dc | 275 | |
276 | /* Prepare the data for an induction variable analysis of a LOOP. */ | |
277 | ||
278 | void | |
279 | iv_analysis_loop_init (struct loop *loop) | |
280 | { | |
3f37d465 | 281 | current_loop = loop; |
f9cce2dc | 282 | |
3f37d465 | 283 | /* Clear the information from the analysis of the previous loop. */ |
3072d30e | 284 | if (clean_slate) |
b818d1a9 | 285 | { |
3072d30e | 286 | df_set_flags (DF_EQ_NOTES + DF_DEFER_INSN_RESCAN); |
c1f445d2 | 287 | bivs = new hash_table<biv_entry_hasher> (10); |
3072d30e | 288 | clean_slate = false; |
b818d1a9 | 289 | } |
290 | else | |
291 | clear_iv_info (); | |
f9cce2dc | 292 | |
3072d30e | 293 | /* Get rid of the ud chains before processing the rescans. Then add |
294 | the problem back. */ | |
295 | df_remove_problem (df_chain); | |
296 | df_process_deferred_rescans (); | |
ea9538fb | 297 | df_set_flags (DF_RD_PRUNE_DEAD_DEFS); |
3072d30e | 298 | df_chain_add_problem (DF_UD_CHAIN); |
c56a6318 | 299 | df_note_add_problem (); |
67e23d6f | 300 | df_analyze_loop (loop); |
3072d30e | 301 | if (dump_file) |
774f8797 | 302 | df_dump_region (dump_file); |
3072d30e | 303 | |
304 | check_iv_ref_table_size (); | |
f9cce2dc | 305 | } |
306 | ||
3f37d465 | 307 | /* Finds the definition of REG that dominates loop latch and stores |
308 | it to DEF. Returns false if there is not a single definition | |
309 | dominating the latch. If REG has no definition in loop, DEF | |
310 | is set to NULL and true is returned. */ | |
f9cce2dc | 311 | |
3f37d465 | 312 | static bool |
ed6e85ae | 313 | latch_dominating_def (rtx reg, df_ref *def) |
f9cce2dc | 314 | { |
ed6e85ae | 315 | df_ref single_rd = NULL, adef; |
3f37d465 | 316 | unsigned regno = REGNO (reg); |
3072d30e | 317 | struct df_rd_bb_info *bb_info = DF_RD_BB_INFO (current_loop->latch); |
f9cce2dc | 318 | |
ed6e85ae | 319 | for (adef = DF_REG_DEF_CHAIN (regno); adef; adef = DF_REF_NEXT_REG (adef)) |
f9cce2dc | 320 | { |
ed6e85ae | 321 | if (!bitmap_bit_p (df->blocks_to_analyze, DF_REF_BBNO (adef)) |
f53d14b1 | 322 | || !bitmap_bit_p (&bb_info->out, DF_REF_ID (adef))) |
3f37d465 | 323 | continue; |
324 | ||
325 | /* More than one reaching definition. */ | |
326 | if (single_rd) | |
327 | return false; | |
328 | ||
329 | if (!just_once_each_iteration_p (current_loop, DF_REF_BB (adef))) | |
330 | return false; | |
331 | ||
332 | single_rd = adef; | |
f9cce2dc | 333 | } |
f9cce2dc | 334 | |
3f37d465 | 335 | *def = single_rd; |
336 | return true; | |
337 | } | |
f9cce2dc | 338 | |
3f37d465 | 339 | /* Gets definition of REG reaching its use in INSN and stores it to DEF. */ |
f9cce2dc | 340 | |
3f37d465 | 341 | static enum iv_grd_result |
3eeb4f9a | 342 | iv_get_reaching_def (rtx_insn *insn, rtx reg, df_ref *def) |
3f37d465 | 343 | { |
ed6e85ae | 344 | df_ref use, adef; |
3f37d465 | 345 | basic_block def_bb, use_bb; |
3eeb4f9a | 346 | rtx_insn *def_insn; |
3f37d465 | 347 | bool dom_p; |
48e1416a | 348 | |
3f37d465 | 349 | *def = NULL; |
350 | if (!simple_reg_p (reg)) | |
351 | return GRD_INVALID; | |
352 | if (GET_CODE (reg) == SUBREG) | |
353 | reg = SUBREG_REG (reg); | |
354 | gcc_assert (REG_P (reg)); | |
f9cce2dc | 355 | |
3072d30e | 356 | use = df_find_use (insn, reg); |
3f37d465 | 357 | gcc_assert (use != NULL); |
f9cce2dc | 358 | |
3f37d465 | 359 | if (!DF_REF_CHAIN (use)) |
360 | return GRD_INVARIANT; | |
f9cce2dc | 361 | |
3f37d465 | 362 | /* More than one reaching def. */ |
363 | if (DF_REF_CHAIN (use)->next) | |
364 | return GRD_INVALID; | |
f9cce2dc | 365 | |
3f37d465 | 366 | adef = DF_REF_CHAIN (use)->ref; |
605dec4e | 367 | |
368 | /* We do not handle setting only part of the register. */ | |
ed6e85ae | 369 | if (DF_REF_FLAGS (adef) & DF_REF_READ_WRITE) |
605dec4e | 370 | return GRD_INVALID; |
371 | ||
3f37d465 | 372 | def_insn = DF_REF_INSN (adef); |
373 | def_bb = DF_REF_BB (adef); | |
374 | use_bb = BLOCK_FOR_INSN (insn); | |
f9cce2dc | 375 | |
3f37d465 | 376 | if (use_bb == def_bb) |
3072d30e | 377 | dom_p = (DF_INSN_LUID (def_insn) < DF_INSN_LUID (insn)); |
3f37d465 | 378 | else |
379 | dom_p = dominated_by_p (CDI_DOMINATORS, use_bb, def_bb); | |
f9cce2dc | 380 | |
3f37d465 | 381 | if (dom_p) |
382 | { | |
383 | *def = adef; | |
384 | return GRD_SINGLE_DOM; | |
f9cce2dc | 385 | } |
3f37d465 | 386 | |
387 | /* The definition does not dominate the use. This is still OK if | |
388 | this may be a use of a biv, i.e. if the def_bb dominates loop | |
389 | latch. */ | |
390 | if (just_once_each_iteration_p (current_loop, def_bb)) | |
391 | return GRD_MAYBE_BIV; | |
392 | ||
393 | return GRD_INVALID; | |
f9cce2dc | 394 | } |
395 | ||
396 | /* Sets IV to invariant CST in MODE. Always returns true (just for | |
397 | consistency with other iv manipulation functions that may fail). */ | |
398 | ||
399 | static bool | |
400 | iv_constant (struct rtx_iv *iv, rtx cst, enum machine_mode mode) | |
401 | { | |
402 | if (mode == VOIDmode) | |
403 | mode = GET_MODE (cst); | |
404 | ||
f9cce2dc | 405 | iv->mode = mode; |
406 | iv->base = cst; | |
407 | iv->step = const0_rtx; | |
408 | iv->first_special = false; | |
aedb7bf8 | 409 | iv->extend = IV_UNKNOWN_EXTEND; |
f9cce2dc | 410 | iv->extend_mode = iv->mode; |
411 | iv->delta = const0_rtx; | |
412 | iv->mult = const1_rtx; | |
413 | ||
414 | return true; | |
415 | } | |
416 | ||
417 | /* Evaluates application of subreg to MODE on IV. */ | |
418 | ||
419 | static bool | |
420 | iv_subreg (struct rtx_iv *iv, enum machine_mode mode) | |
421 | { | |
bf9fa951 | 422 | /* If iv is invariant, just calculate the new value. */ |
423 | if (iv->step == const0_rtx | |
424 | && !iv->first_special) | |
425 | { | |
426 | rtx val = get_iv_value (iv, const0_rtx); | |
28573ae7 | 427 | val = lowpart_subreg (mode, val, |
428 | iv->extend == IV_UNKNOWN_EXTEND | |
429 | ? iv->mode : iv->extend_mode); | |
bf9fa951 | 430 | |
431 | iv->base = val; | |
aedb7bf8 | 432 | iv->extend = IV_UNKNOWN_EXTEND; |
bf9fa951 | 433 | iv->mode = iv->extend_mode = mode; |
434 | iv->delta = const0_rtx; | |
435 | iv->mult = const1_rtx; | |
436 | return true; | |
437 | } | |
438 | ||
f9cce2dc | 439 | if (iv->extend_mode == mode) |
440 | return true; | |
441 | ||
442 | if (GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (iv->mode)) | |
443 | return false; | |
444 | ||
aedb7bf8 | 445 | iv->extend = IV_UNKNOWN_EXTEND; |
f9cce2dc | 446 | iv->mode = mode; |
447 | ||
448 | iv->base = simplify_gen_binary (PLUS, iv->extend_mode, iv->delta, | |
449 | simplify_gen_binary (MULT, iv->extend_mode, | |
450 | iv->base, iv->mult)); | |
451 | iv->step = simplify_gen_binary (MULT, iv->extend_mode, iv->step, iv->mult); | |
452 | iv->mult = const1_rtx; | |
453 | iv->delta = const0_rtx; | |
454 | iv->first_special = false; | |
455 | ||
456 | return true; | |
457 | } | |
458 | ||
459 | /* Evaluates application of EXTEND to MODE on IV. */ | |
460 | ||
461 | static bool | |
aedb7bf8 | 462 | iv_extend (struct rtx_iv *iv, enum iv_extend_code extend, enum machine_mode mode) |
f9cce2dc | 463 | { |
bf9fa951 | 464 | /* If iv is invariant, just calculate the new value. */ |
465 | if (iv->step == const0_rtx | |
466 | && !iv->first_special) | |
467 | { | |
468 | rtx val = get_iv_value (iv, const0_rtx); | |
28573ae7 | 469 | if (iv->extend_mode != iv->mode |
470 | && iv->extend != IV_UNKNOWN_EXTEND | |
471 | && iv->extend != extend) | |
472 | val = lowpart_subreg (iv->mode, val, iv->extend_mode); | |
aedb7bf8 | 473 | val = simplify_gen_unary (iv_extend_to_rtx_code (extend), mode, |
28573ae7 | 474 | val, |
475 | iv->extend == extend | |
476 | ? iv->extend_mode : iv->mode); | |
bf9fa951 | 477 | iv->base = val; |
aedb7bf8 | 478 | iv->extend = IV_UNKNOWN_EXTEND; |
bf9fa951 | 479 | iv->mode = iv->extend_mode = mode; |
480 | iv->delta = const0_rtx; | |
481 | iv->mult = const1_rtx; | |
482 | return true; | |
483 | } | |
484 | ||
f9cce2dc | 485 | if (mode != iv->extend_mode) |
486 | return false; | |
487 | ||
aedb7bf8 | 488 | if (iv->extend != IV_UNKNOWN_EXTEND |
f9cce2dc | 489 | && iv->extend != extend) |
490 | return false; | |
491 | ||
492 | iv->extend = extend; | |
493 | ||
494 | return true; | |
495 | } | |
496 | ||
497 | /* Evaluates negation of IV. */ | |
498 | ||
499 | static bool | |
500 | iv_neg (struct rtx_iv *iv) | |
501 | { | |
aedb7bf8 | 502 | if (iv->extend == IV_UNKNOWN_EXTEND) |
f9cce2dc | 503 | { |
504 | iv->base = simplify_gen_unary (NEG, iv->extend_mode, | |
505 | iv->base, iv->extend_mode); | |
506 | iv->step = simplify_gen_unary (NEG, iv->extend_mode, | |
507 | iv->step, iv->extend_mode); | |
508 | } | |
509 | else | |
510 | { | |
511 | iv->delta = simplify_gen_unary (NEG, iv->extend_mode, | |
512 | iv->delta, iv->extend_mode); | |
513 | iv->mult = simplify_gen_unary (NEG, iv->extend_mode, | |
514 | iv->mult, iv->extend_mode); | |
515 | } | |
516 | ||
517 | return true; | |
518 | } | |
519 | ||
520 | /* Evaluates addition or subtraction (according to OP) of IV1 to IV0. */ | |
521 | ||
522 | static bool | |
523 | iv_add (struct rtx_iv *iv0, struct rtx_iv *iv1, enum rtx_code op) | |
524 | { | |
525 | enum machine_mode mode; | |
526 | rtx arg; | |
527 | ||
aab2cf92 | 528 | /* Extend the constant to extend_mode of the other operand if necessary. */ |
aedb7bf8 | 529 | if (iv0->extend == IV_UNKNOWN_EXTEND |
f9cce2dc | 530 | && iv0->mode == iv0->extend_mode |
531 | && iv0->step == const0_rtx | |
532 | && GET_MODE_SIZE (iv0->extend_mode) < GET_MODE_SIZE (iv1->extend_mode)) | |
533 | { | |
534 | iv0->extend_mode = iv1->extend_mode; | |
535 | iv0->base = simplify_gen_unary (ZERO_EXTEND, iv0->extend_mode, | |
536 | iv0->base, iv0->mode); | |
537 | } | |
aedb7bf8 | 538 | if (iv1->extend == IV_UNKNOWN_EXTEND |
f9cce2dc | 539 | && iv1->mode == iv1->extend_mode |
540 | && iv1->step == const0_rtx | |
541 | && GET_MODE_SIZE (iv1->extend_mode) < GET_MODE_SIZE (iv0->extend_mode)) | |
542 | { | |
543 | iv1->extend_mode = iv0->extend_mode; | |
544 | iv1->base = simplify_gen_unary (ZERO_EXTEND, iv1->extend_mode, | |
545 | iv1->base, iv1->mode); | |
546 | } | |
547 | ||
548 | mode = iv0->extend_mode; | |
549 | if (mode != iv1->extend_mode) | |
550 | return false; | |
551 | ||
aedb7bf8 | 552 | if (iv0->extend == IV_UNKNOWN_EXTEND |
553 | && iv1->extend == IV_UNKNOWN_EXTEND) | |
f9cce2dc | 554 | { |
555 | if (iv0->mode != iv1->mode) | |
556 | return false; | |
557 | ||
558 | iv0->base = simplify_gen_binary (op, mode, iv0->base, iv1->base); | |
559 | iv0->step = simplify_gen_binary (op, mode, iv0->step, iv1->step); | |
560 | ||
561 | return true; | |
562 | } | |
563 | ||
564 | /* Handle addition of constant. */ | |
aedb7bf8 | 565 | if (iv1->extend == IV_UNKNOWN_EXTEND |
f9cce2dc | 566 | && iv1->mode == mode |
567 | && iv1->step == const0_rtx) | |
568 | { | |
569 | iv0->delta = simplify_gen_binary (op, mode, iv0->delta, iv1->base); | |
570 | return true; | |
571 | } | |
572 | ||
aedb7bf8 | 573 | if (iv0->extend == IV_UNKNOWN_EXTEND |
f9cce2dc | 574 | && iv0->mode == mode |
575 | && iv0->step == const0_rtx) | |
576 | { | |
577 | arg = iv0->base; | |
578 | *iv0 = *iv1; | |
579 | if (op == MINUS | |
580 | && !iv_neg (iv0)) | |
581 | return false; | |
582 | ||
583 | iv0->delta = simplify_gen_binary (PLUS, mode, iv0->delta, arg); | |
584 | return true; | |
585 | } | |
586 | ||
587 | return false; | |
588 | } | |
589 | ||
590 | /* Evaluates multiplication of IV by constant CST. */ | |
591 | ||
592 | static bool | |
593 | iv_mult (struct rtx_iv *iv, rtx mby) | |
594 | { | |
595 | enum machine_mode mode = iv->extend_mode; | |
596 | ||
597 | if (GET_MODE (mby) != VOIDmode | |
598 | && GET_MODE (mby) != mode) | |
599 | return false; | |
600 | ||
aedb7bf8 | 601 | if (iv->extend == IV_UNKNOWN_EXTEND) |
f9cce2dc | 602 | { |
603 | iv->base = simplify_gen_binary (MULT, mode, iv->base, mby); | |
604 | iv->step = simplify_gen_binary (MULT, mode, iv->step, mby); | |
605 | } | |
606 | else | |
607 | { | |
608 | iv->delta = simplify_gen_binary (MULT, mode, iv->delta, mby); | |
609 | iv->mult = simplify_gen_binary (MULT, mode, iv->mult, mby); | |
610 | } | |
611 | ||
612 | return true; | |
613 | } | |
614 | ||
567c3006 | 615 | /* Evaluates shift of IV by constant CST. */ |
616 | ||
617 | static bool | |
618 | iv_shift (struct rtx_iv *iv, rtx mby) | |
619 | { | |
620 | enum machine_mode mode = iv->extend_mode; | |
621 | ||
622 | if (GET_MODE (mby) != VOIDmode | |
623 | && GET_MODE (mby) != mode) | |
624 | return false; | |
625 | ||
aedb7bf8 | 626 | if (iv->extend == IV_UNKNOWN_EXTEND) |
567c3006 | 627 | { |
628 | iv->base = simplify_gen_binary (ASHIFT, mode, iv->base, mby); | |
629 | iv->step = simplify_gen_binary (ASHIFT, mode, iv->step, mby); | |
630 | } | |
631 | else | |
632 | { | |
633 | iv->delta = simplify_gen_binary (ASHIFT, mode, iv->delta, mby); | |
634 | iv->mult = simplify_gen_binary (ASHIFT, mode, iv->mult, mby); | |
635 | } | |
636 | ||
637 | return true; | |
638 | } | |
639 | ||
f9cce2dc | 640 | /* The recursive part of get_biv_step. Gets the value of the single value |
3f37d465 | 641 | defined by DEF wrto initial value of REG inside loop, in shape described |
f9cce2dc | 642 | at get_biv_step. */ |
643 | ||
644 | static bool | |
ed6e85ae | 645 | get_biv_step_1 (df_ref def, rtx reg, |
f9cce2dc | 646 | rtx *inner_step, enum machine_mode *inner_mode, |
aedb7bf8 | 647 | enum iv_extend_code *extend, enum machine_mode outer_mode, |
f9cce2dc | 648 | rtx *outer_step) |
649 | { | |
a6ed3419 | 650 | rtx set, rhs, op0 = NULL_RTX, op1 = NULL_RTX; |
3f37d465 | 651 | rtx next, nextr, tmp; |
f9cce2dc | 652 | enum rtx_code code; |
3eeb4f9a | 653 | rtx_insn *insn = DF_REF_INSN (def); |
ed6e85ae | 654 | df_ref next_def; |
3f37d465 | 655 | enum iv_grd_result res; |
f9cce2dc | 656 | |
657 | set = single_set (insn); | |
3f37d465 | 658 | if (!set) |
659 | return false; | |
660 | ||
f9cce2dc | 661 | rhs = find_reg_equal_equiv_note (insn); |
a6629703 | 662 | if (rhs) |
663 | rhs = XEXP (rhs, 0); | |
664 | else | |
f9cce2dc | 665 | rhs = SET_SRC (set); |
f9cce2dc | 666 | |
667 | code = GET_CODE (rhs); | |
668 | switch (code) | |
669 | { | |
670 | case SUBREG: | |
671 | case REG: | |
672 | next = rhs; | |
673 | break; | |
674 | ||
675 | case PLUS: | |
676 | case MINUS: | |
677 | op0 = XEXP (rhs, 0); | |
678 | op1 = XEXP (rhs, 1); | |
679 | ||
680 | if (code == PLUS && CONSTANT_P (op0)) | |
681 | { | |
682 | tmp = op0; op0 = op1; op1 = tmp; | |
683 | } | |
684 | ||
685 | if (!simple_reg_p (op0) | |
686 | || !CONSTANT_P (op1)) | |
687 | return false; | |
688 | ||
689 | if (GET_MODE (rhs) != outer_mode) | |
690 | { | |
691 | /* ppc64 uses expressions like | |
692 | ||
693 | (set x:SI (plus:SI (subreg:SI y:DI) 1)). | |
694 | ||
695 | this is equivalent to | |
696 | ||
697 | (set x':DI (plus:DI y:DI 1)) | |
698 | (set x:SI (subreg:SI (x':DI)). */ | |
699 | if (GET_CODE (op0) != SUBREG) | |
700 | return false; | |
701 | if (GET_MODE (SUBREG_REG (op0)) != outer_mode) | |
702 | return false; | |
703 | } | |
704 | ||
705 | next = op0; | |
706 | break; | |
707 | ||
708 | case SIGN_EXTEND: | |
709 | case ZERO_EXTEND: | |
710 | if (GET_MODE (rhs) != outer_mode) | |
711 | return false; | |
712 | ||
713 | op0 = XEXP (rhs, 0); | |
714 | if (!simple_reg_p (op0)) | |
715 | return false; | |
716 | ||
717 | next = op0; | |
718 | break; | |
719 | ||
720 | default: | |
721 | return false; | |
722 | } | |
723 | ||
724 | if (GET_CODE (next) == SUBREG) | |
725 | { | |
726 | if (!subreg_lowpart_p (next)) | |
727 | return false; | |
728 | ||
729 | nextr = SUBREG_REG (next); | |
730 | if (GET_MODE (nextr) != outer_mode) | |
731 | return false; | |
732 | } | |
733 | else | |
734 | nextr = next; | |
735 | ||
3f37d465 | 736 | res = iv_get_reaching_def (insn, nextr, &next_def); |
737 | ||
738 | if (res == GRD_INVALID || res == GRD_INVARIANT) | |
f9cce2dc | 739 | return false; |
740 | ||
3f37d465 | 741 | if (res == GRD_MAYBE_BIV) |
f9cce2dc | 742 | { |
743 | if (!rtx_equal_p (nextr, reg)) | |
744 | return false; | |
745 | ||
746 | *inner_step = const0_rtx; | |
aedb7bf8 | 747 | *extend = IV_UNKNOWN_EXTEND; |
f9cce2dc | 748 | *inner_mode = outer_mode; |
749 | *outer_step = const0_rtx; | |
750 | } | |
3f37d465 | 751 | else if (!get_biv_step_1 (next_def, reg, |
f9cce2dc | 752 | inner_step, inner_mode, extend, outer_mode, |
753 | outer_step)) | |
754 | return false; | |
755 | ||
756 | if (GET_CODE (next) == SUBREG) | |
757 | { | |
758 | enum machine_mode amode = GET_MODE (next); | |
759 | ||
760 | if (GET_MODE_SIZE (amode) > GET_MODE_SIZE (*inner_mode)) | |
761 | return false; | |
762 | ||
763 | *inner_mode = amode; | |
764 | *inner_step = simplify_gen_binary (PLUS, outer_mode, | |
765 | *inner_step, *outer_step); | |
766 | *outer_step = const0_rtx; | |
aedb7bf8 | 767 | *extend = IV_UNKNOWN_EXTEND; |
f9cce2dc | 768 | } |
769 | ||
770 | switch (code) | |
771 | { | |
772 | case REG: | |
773 | case SUBREG: | |
774 | break; | |
775 | ||
776 | case PLUS: | |
777 | case MINUS: | |
778 | if (*inner_mode == outer_mode | |
779 | /* See comment in previous switch. */ | |
780 | || GET_MODE (rhs) != outer_mode) | |
781 | *inner_step = simplify_gen_binary (code, outer_mode, | |
782 | *inner_step, op1); | |
783 | else | |
784 | *outer_step = simplify_gen_binary (code, outer_mode, | |
785 | *outer_step, op1); | |
786 | break; | |
787 | ||
788 | case SIGN_EXTEND: | |
789 | case ZERO_EXTEND: | |
972e95af | 790 | gcc_assert (GET_MODE (op0) == *inner_mode |
aedb7bf8 | 791 | && *extend == IV_UNKNOWN_EXTEND |
972e95af | 792 | && *outer_step == const0_rtx); |
f9cce2dc | 793 | |
aedb7bf8 | 794 | *extend = (code == SIGN_EXTEND) ? IV_SIGN_EXTEND : IV_ZERO_EXTEND; |
f9cce2dc | 795 | break; |
796 | ||
797 | default: | |
3f37d465 | 798 | return false; |
f9cce2dc | 799 | } |
800 | ||
801 | return true; | |
802 | } | |
803 | ||
804 | /* Gets the operation on register REG inside loop, in shape | |
805 | ||
806 | OUTER_STEP + EXTEND_{OUTER_MODE} (SUBREG_{INNER_MODE} (REG + INNER_STEP)) | |
807 | ||
3f37d465 | 808 | If the operation cannot be described in this shape, return false. |
809 | LAST_DEF is the definition of REG that dominates loop latch. */ | |
f9cce2dc | 810 | |
811 | static bool | |
ed6e85ae | 812 | get_biv_step (df_ref last_def, rtx reg, rtx *inner_step, |
aedb7bf8 | 813 | enum machine_mode *inner_mode, enum iv_extend_code *extend, |
3f37d465 | 814 | enum machine_mode *outer_mode, rtx *outer_step) |
f9cce2dc | 815 | { |
816 | *outer_mode = GET_MODE (reg); | |
817 | ||
3f37d465 | 818 | if (!get_biv_step_1 (last_def, reg, |
f9cce2dc | 819 | inner_step, inner_mode, extend, *outer_mode, |
820 | outer_step)) | |
821 | return false; | |
822 | ||
aedb7bf8 | 823 | gcc_assert ((*inner_mode == *outer_mode) != (*extend != IV_UNKNOWN_EXTEND)); |
972e95af | 824 | gcc_assert (*inner_mode != *outer_mode || *outer_step == const0_rtx); |
f9cce2dc | 825 | |
826 | return true; | |
827 | } | |
828 | ||
3f37d465 | 829 | /* Records information that DEF is induction variable IV. */ |
830 | ||
831 | static void | |
ed6e85ae | 832 | record_iv (df_ref def, struct rtx_iv *iv) |
3f37d465 | 833 | { |
4c36ffe6 | 834 | struct rtx_iv *recorded_iv = XNEW (struct rtx_iv); |
3f37d465 | 835 | |
836 | *recorded_iv = *iv; | |
3072d30e | 837 | check_iv_ref_table_size (); |
3f37d465 | 838 | DF_REF_IV_SET (def, recorded_iv); |
839 | } | |
840 | ||
841 | /* If DEF was already analyzed for bivness, store the description of the biv to | |
842 | IV and return true. Otherwise return false. */ | |
843 | ||
844 | static bool | |
845 | analyzed_for_bivness_p (rtx def, struct rtx_iv *iv) | |
846 | { | |
c1f445d2 | 847 | struct biv_entry *biv = bivs->find_with_hash (def, REGNO (def)); |
3f37d465 | 848 | |
849 | if (!biv) | |
850 | return false; | |
851 | ||
852 | *iv = biv->iv; | |
853 | return true; | |
854 | } | |
855 | ||
856 | static void | |
857 | record_biv (rtx def, struct rtx_iv *iv) | |
858 | { | |
4c36ffe6 | 859 | struct biv_entry *biv = XNEW (struct biv_entry); |
c1f445d2 | 860 | biv_entry **slot = bivs->find_slot_with_hash (def, REGNO (def), INSERT); |
3f37d465 | 861 | |
862 | biv->regno = REGNO (def); | |
863 | biv->iv = *iv; | |
864 | gcc_assert (!*slot); | |
865 | *slot = biv; | |
866 | } | |
867 | ||
f9cce2dc | 868 | /* Determines whether DEF is a biv and if so, stores its description |
869 | to *IV. */ | |
870 | ||
871 | static bool | |
f08e8669 | 872 | iv_analyze_biv (rtx def, struct rtx_iv *iv) |
f9cce2dc | 873 | { |
f9cce2dc | 874 | rtx inner_step, outer_step; |
875 | enum machine_mode inner_mode, outer_mode; | |
aedb7bf8 | 876 | enum iv_extend_code extend; |
ed6e85ae | 877 | df_ref last_def; |
f9cce2dc | 878 | |
450d042a | 879 | if (dump_file) |
f9cce2dc | 880 | { |
4133d091 | 881 | fprintf (dump_file, "Analyzing "); |
450d042a | 882 | print_rtl (dump_file, def); |
883 | fprintf (dump_file, " for bivness.\n"); | |
f9cce2dc | 884 | } |
48e1416a | 885 | |
f9cce2dc | 886 | if (!REG_P (def)) |
887 | { | |
888 | if (!CONSTANT_P (def)) | |
889 | return false; | |
890 | ||
891 | return iv_constant (iv, def, VOIDmode); | |
892 | } | |
893 | ||
3f37d465 | 894 | if (!latch_dominating_def (def, &last_def)) |
f9cce2dc | 895 | { |
450d042a | 896 | if (dump_file) |
897 | fprintf (dump_file, " not simple.\n"); | |
f9cce2dc | 898 | return false; |
899 | } | |
900 | ||
3f37d465 | 901 | if (!last_def) |
902 | return iv_constant (iv, def, VOIDmode); | |
903 | ||
904 | if (analyzed_for_bivness_p (def, iv)) | |
f9cce2dc | 905 | { |
450d042a | 906 | if (dump_file) |
907 | fprintf (dump_file, " already analysed.\n"); | |
f9cce2dc | 908 | return iv->base != NULL_RTX; |
909 | } | |
910 | ||
3f37d465 | 911 | if (!get_biv_step (last_def, def, &inner_step, &inner_mode, &extend, |
f9cce2dc | 912 | &outer_mode, &outer_step)) |
913 | { | |
914 | iv->base = NULL_RTX; | |
915 | goto end; | |
916 | } | |
917 | ||
918 | /* Loop transforms base to es (base + inner_step) + outer_step, | |
919 | where es means extend of subreg between inner_mode and outer_mode. | |
920 | The corresponding induction variable is | |
921 | ||
922 | es ((base - outer_step) + i * (inner_step + outer_step)) + outer_step */ | |
923 | ||
924 | iv->base = simplify_gen_binary (MINUS, outer_mode, def, outer_step); | |
925 | iv->step = simplify_gen_binary (PLUS, outer_mode, inner_step, outer_step); | |
926 | iv->mode = inner_mode; | |
927 | iv->extend_mode = outer_mode; | |
928 | iv->extend = extend; | |
929 | iv->mult = const1_rtx; | |
930 | iv->delta = outer_step; | |
931 | iv->first_special = inner_mode != outer_mode; | |
932 | ||
450d042a | 933 | end: |
934 | if (dump_file) | |
f9cce2dc | 935 | { |
450d042a | 936 | fprintf (dump_file, " "); |
937 | dump_iv_info (dump_file, iv); | |
938 | fprintf (dump_file, "\n"); | |
f9cce2dc | 939 | } |
940 | ||
3f37d465 | 941 | record_biv (def, iv); |
f9cce2dc | 942 | return iv->base != NULL_RTX; |
943 | } | |
944 | ||
48e1416a | 945 | /* Analyzes expression RHS used at INSN and stores the result to *IV. |
3f37d465 | 946 | The mode of the induction variable is MODE. */ |
f9cce2dc | 947 | |
3f37d465 | 948 | bool |
3eeb4f9a | 949 | iv_analyze_expr (rtx_insn *insn, rtx rhs, enum machine_mode mode, |
950 | struct rtx_iv *iv) | |
f9cce2dc | 951 | { |
3f37d465 | 952 | rtx mby = NULL_RTX, tmp; |
953 | rtx op0 = NULL_RTX, op1 = NULL_RTX; | |
954 | struct rtx_iv iv0, iv1; | |
955 | enum rtx_code code = GET_CODE (rhs); | |
956 | enum machine_mode omode = mode; | |
f9cce2dc | 957 | |
3f37d465 | 958 | iv->mode = VOIDmode; |
959 | iv->base = NULL_RTX; | |
960 | iv->step = NULL_RTX; | |
f9cce2dc | 961 | |
3f37d465 | 962 | gcc_assert (GET_MODE (rhs) == mode || GET_MODE (rhs) == VOIDmode); |
f9cce2dc | 963 | |
3f37d465 | 964 | if (CONSTANT_P (rhs) |
965 | || REG_P (rhs) | |
966 | || code == SUBREG) | |
f9cce2dc | 967 | { |
3f37d465 | 968 | if (!iv_analyze_op (insn, rhs, iv)) |
969 | return false; | |
48e1416a | 970 | |
3f37d465 | 971 | if (iv->mode == VOIDmode) |
f9cce2dc | 972 | { |
3f37d465 | 973 | iv->mode = mode; |
974 | iv->extend_mode = mode; | |
f9cce2dc | 975 | } |
3f37d465 | 976 | |
977 | return true; | |
f9cce2dc | 978 | } |
979 | ||
3f37d465 | 980 | switch (code) |
f9cce2dc | 981 | { |
3f37d465 | 982 | case REG: |
983 | op0 = rhs; | |
984 | break; | |
f9cce2dc | 985 | |
3f37d465 | 986 | case SIGN_EXTEND: |
987 | case ZERO_EXTEND: | |
988 | case NEG: | |
989 | op0 = XEXP (rhs, 0); | |
990 | omode = GET_MODE (op0); | |
991 | break; | |
992 | ||
993 | case PLUS: | |
994 | case MINUS: | |
995 | op0 = XEXP (rhs, 0); | |
996 | op1 = XEXP (rhs, 1); | |
997 | break; | |
998 | ||
999 | case MULT: | |
1000 | op0 = XEXP (rhs, 0); | |
1001 | mby = XEXP (rhs, 1); | |
1002 | if (!CONSTANT_P (mby)) | |
f9cce2dc | 1003 | { |
3f37d465 | 1004 | tmp = op0; |
1005 | op0 = mby; | |
1006 | mby = tmp; | |
f9cce2dc | 1007 | } |
3f37d465 | 1008 | if (!CONSTANT_P (mby)) |
1009 | return false; | |
1010 | break; | |
f9cce2dc | 1011 | |
3f37d465 | 1012 | case ASHIFT: |
1013 | op0 = XEXP (rhs, 0); | |
1014 | mby = XEXP (rhs, 1); | |
1015 | if (!CONSTANT_P (mby)) | |
1016 | return false; | |
1017 | break; | |
1018 | ||
1019 | default: | |
f9cce2dc | 1020 | return false; |
1021 | } | |
1022 | ||
3f37d465 | 1023 | if (op0 |
1024 | && !iv_analyze_expr (insn, op0, omode, &iv0)) | |
1025 | return false; | |
f9cce2dc | 1026 | |
3f37d465 | 1027 | if (op1 |
1028 | && !iv_analyze_expr (insn, op1, omode, &iv1)) | |
f9cce2dc | 1029 | return false; |
1030 | ||
3f37d465 | 1031 | switch (code) |
f9cce2dc | 1032 | { |
3f37d465 | 1033 | case SIGN_EXTEND: |
aedb7bf8 | 1034 | if (!iv_extend (&iv0, IV_SIGN_EXTEND, mode)) |
1035 | return false; | |
1036 | break; | |
1037 | ||
3f37d465 | 1038 | case ZERO_EXTEND: |
aedb7bf8 | 1039 | if (!iv_extend (&iv0, IV_ZERO_EXTEND, mode)) |
3f37d465 | 1040 | return false; |
1041 | break; | |
1042 | ||
1043 | case NEG: | |
1044 | if (!iv_neg (&iv0)) | |
f9cce2dc | 1045 | return false; |
3f37d465 | 1046 | break; |
f9cce2dc | 1047 | |
3f37d465 | 1048 | case PLUS: |
1049 | case MINUS: | |
1050 | if (!iv_add (&iv0, &iv1, code)) | |
f9cce2dc | 1051 | return false; |
3f37d465 | 1052 | break; |
f9cce2dc | 1053 | |
3f37d465 | 1054 | case MULT: |
1055 | if (!iv_mult (&iv0, mby)) | |
1056 | return false; | |
1057 | break; | |
1058 | ||
1059 | case ASHIFT: | |
1060 | if (!iv_shift (&iv0, mby)) | |
1061 | return false; | |
1062 | break; | |
1063 | ||
1064 | default: | |
1065 | break; | |
f9cce2dc | 1066 | } |
1067 | ||
3f37d465 | 1068 | *iv = iv0; |
1069 | return iv->base != NULL_RTX; | |
1070 | } | |
1071 | ||
1072 | /* Analyzes iv DEF and stores the result to *IV. */ | |
1073 | ||
1074 | static bool | |
ed6e85ae | 1075 | iv_analyze_def (df_ref def, struct rtx_iv *iv) |
3f37d465 | 1076 | { |
3eeb4f9a | 1077 | rtx_insn *insn = DF_REF_INSN (def); |
3f37d465 | 1078 | rtx reg = DF_REF_REG (def); |
1079 | rtx set, rhs; | |
f9cce2dc | 1080 | |
450d042a | 1081 | if (dump_file) |
f9cce2dc | 1082 | { |
666137bc | 1083 | fprintf (dump_file, "Analyzing def of "); |
3f37d465 | 1084 | print_rtl (dump_file, reg); |
450d042a | 1085 | fprintf (dump_file, " in insn "); |
1086 | print_rtl_single (dump_file, insn); | |
f9cce2dc | 1087 | } |
48e1416a | 1088 | |
3072d30e | 1089 | check_iv_ref_table_size (); |
3f37d465 | 1090 | if (DF_REF_IV (def)) |
f9cce2dc | 1091 | { |
450d042a | 1092 | if (dump_file) |
1093 | fprintf (dump_file, " already analysed.\n"); | |
3f37d465 | 1094 | *iv = *DF_REF_IV (def); |
f9cce2dc | 1095 | return iv->base != NULL_RTX; |
1096 | } | |
1097 | ||
1098 | iv->mode = VOIDmode; | |
1099 | iv->base = NULL_RTX; | |
1100 | iv->step = NULL_RTX; | |
1101 | ||
3072d30e | 1102 | if (!REG_P (reg)) |
1103 | return false; | |
1104 | ||
f9cce2dc | 1105 | set = single_set (insn); |
3072d30e | 1106 | if (!set) |
1107 | return false; | |
1108 | ||
1109 | if (!REG_P (SET_DEST (set))) | |
3f37d465 | 1110 | return false; |
1111 | ||
3072d30e | 1112 | gcc_assert (SET_DEST (set) == reg); |
f9cce2dc | 1113 | rhs = find_reg_equal_equiv_note (insn); |
a6629703 | 1114 | if (rhs) |
1115 | rhs = XEXP (rhs, 0); | |
1116 | else | |
f9cce2dc | 1117 | rhs = SET_SRC (set); |
f9cce2dc | 1118 | |
3f37d465 | 1119 | iv_analyze_expr (insn, rhs, GET_MODE (reg), iv); |
1120 | record_iv (def, iv); | |
1121 | ||
1122 | if (dump_file) | |
f9cce2dc | 1123 | { |
3f37d465 | 1124 | print_rtl (dump_file, reg); |
1125 | fprintf (dump_file, " in insn "); | |
1126 | print_rtl_single (dump_file, insn); | |
1127 | fprintf (dump_file, " is "); | |
1128 | dump_iv_info (dump_file, iv); | |
1129 | fprintf (dump_file, "\n"); | |
f9cce2dc | 1130 | } |
f9cce2dc | 1131 | |
3f37d465 | 1132 | return iv->base != NULL_RTX; |
1133 | } | |
f9cce2dc | 1134 | |
3f37d465 | 1135 | /* Analyzes operand OP of INSN and stores the result to *IV. */ |
f9cce2dc | 1136 | |
3f37d465 | 1137 | static bool |
3eeb4f9a | 1138 | iv_analyze_op (rtx_insn *insn, rtx op, struct rtx_iv *iv) |
3f37d465 | 1139 | { |
ed6e85ae | 1140 | df_ref def = NULL; |
3f37d465 | 1141 | enum iv_grd_result res; |
567c3006 | 1142 | |
3f37d465 | 1143 | if (dump_file) |
1144 | { | |
666137bc | 1145 | fprintf (dump_file, "Analyzing operand "); |
3f37d465 | 1146 | print_rtl (dump_file, op); |
1147 | fprintf (dump_file, " of insn "); | |
1148 | print_rtl_single (dump_file, insn); | |
1149 | } | |
567c3006 | 1150 | |
e54e3d9f | 1151 | if (function_invariant_p (op)) |
3f37d465 | 1152 | res = GRD_INVARIANT; |
1153 | else if (GET_CODE (op) == SUBREG) | |
1154 | { | |
1155 | if (!subreg_lowpart_p (op)) | |
1156 | return false; | |
f9cce2dc | 1157 | |
3f37d465 | 1158 | if (!iv_analyze_op (insn, SUBREG_REG (op), iv)) |
1159 | return false; | |
f9cce2dc | 1160 | |
3f37d465 | 1161 | return iv_subreg (iv, GET_MODE (op)); |
1162 | } | |
1163 | else | |
f9cce2dc | 1164 | { |
3f37d465 | 1165 | res = iv_get_reaching_def (insn, op, &def); |
1166 | if (res == GRD_INVALID) | |
f9cce2dc | 1167 | { |
3f37d465 | 1168 | if (dump_file) |
1169 | fprintf (dump_file, " not simple.\n"); | |
1170 | return false; | |
f9cce2dc | 1171 | } |
1172 | } | |
1173 | ||
3f37d465 | 1174 | if (res == GRD_INVARIANT) |
f9cce2dc | 1175 | { |
3f37d465 | 1176 | iv_constant (iv, op, VOIDmode); |
f9cce2dc | 1177 | |
3f37d465 | 1178 | if (dump_file) |
f9cce2dc | 1179 | { |
3f37d465 | 1180 | fprintf (dump_file, " "); |
1181 | dump_iv_info (dump_file, iv); | |
1182 | fprintf (dump_file, "\n"); | |
f9cce2dc | 1183 | } |
3f37d465 | 1184 | return true; |
f9cce2dc | 1185 | } |
1186 | ||
3f37d465 | 1187 | if (res == GRD_MAYBE_BIV) |
1188 | return iv_analyze_biv (op, iv); | |
f9cce2dc | 1189 | |
3f37d465 | 1190 | return iv_analyze_def (def, iv); |
1191 | } | |
f9cce2dc | 1192 | |
3f37d465 | 1193 | /* Analyzes value VAL at INSN and stores the result to *IV. */ |
f9cce2dc | 1194 | |
3f37d465 | 1195 | bool |
3eeb4f9a | 1196 | iv_analyze (rtx_insn *insn, rtx val, struct rtx_iv *iv) |
3f37d465 | 1197 | { |
1198 | rtx reg; | |
f9cce2dc | 1199 | |
3f37d465 | 1200 | /* We must find the insn in that val is used, so that we get to UD chains. |
1201 | Since the function is sometimes called on result of get_condition, | |
1202 | this does not necessarily have to be directly INSN; scan also the | |
1203 | following insns. */ | |
1204 | if (simple_reg_p (val)) | |
1205 | { | |
1206 | if (GET_CODE (val) == SUBREG) | |
1207 | reg = SUBREG_REG (val); | |
1208 | else | |
1209 | reg = val; | |
567c3006 | 1210 | |
3072d30e | 1211 | while (!df_find_use (insn, reg)) |
3f37d465 | 1212 | insn = NEXT_INSN (insn); |
f9cce2dc | 1213 | } |
1214 | ||
3f37d465 | 1215 | return iv_analyze_op (insn, val, iv); |
1216 | } | |
f9cce2dc | 1217 | |
3f37d465 | 1218 | /* Analyzes definition of DEF in INSN and stores the result to IV. */ |
f9cce2dc | 1219 | |
3f37d465 | 1220 | bool |
3eeb4f9a | 1221 | iv_analyze_result (rtx_insn *insn, rtx def, struct rtx_iv *iv) |
3f37d465 | 1222 | { |
ed6e85ae | 1223 | df_ref adef; |
f9cce2dc | 1224 | |
3072d30e | 1225 | adef = df_find_def (insn, def); |
3f37d465 | 1226 | if (!adef) |
1227 | return false; | |
1228 | ||
1229 | return iv_analyze_def (adef, iv); | |
f9cce2dc | 1230 | } |
1231 | ||
3f37d465 | 1232 | /* Checks whether definition of register REG in INSN is a basic induction |
a9989fb4 | 1233 | variable. IV analysis must have been initialized (via a call to |
1234 | iv_analysis_loop_init) for this function to produce a result. */ | |
1235 | ||
1236 | bool | |
3eeb4f9a | 1237 | biv_p (rtx_insn *insn, rtx reg) |
a9989fb4 | 1238 | { |
1239 | struct rtx_iv iv; | |
ed6e85ae | 1240 | df_ref def, last_def; |
a9989fb4 | 1241 | |
3f37d465 | 1242 | if (!simple_reg_p (reg)) |
a9989fb4 | 1243 | return false; |
1244 | ||
3072d30e | 1245 | def = df_find_def (insn, reg); |
3f37d465 | 1246 | gcc_assert (def != NULL); |
1247 | if (!latch_dominating_def (reg, &last_def)) | |
1248 | return false; | |
1249 | if (last_def != def) | |
a9989fb4 | 1250 | return false; |
1251 | ||
3f37d465 | 1252 | if (!iv_analyze_biv (reg, &iv)) |
1253 | return false; | |
1254 | ||
1255 | return iv.step != const0_rtx; | |
a9989fb4 | 1256 | } |
1257 | ||
f9cce2dc | 1258 | /* Calculates value of IV at ITERATION-th iteration. */ |
1259 | ||
1260 | rtx | |
1261 | get_iv_value (struct rtx_iv *iv, rtx iteration) | |
1262 | { | |
1263 | rtx val; | |
1264 | ||
1265 | /* We would need to generate some if_then_else patterns, and so far | |
1266 | it is not needed anywhere. */ | |
972e95af | 1267 | gcc_assert (!iv->first_special); |
f9cce2dc | 1268 | |
1269 | if (iv->step != const0_rtx && iteration != const0_rtx) | |
1270 | val = simplify_gen_binary (PLUS, iv->extend_mode, iv->base, | |
1271 | simplify_gen_binary (MULT, iv->extend_mode, | |
1272 | iv->step, iteration)); | |
1273 | else | |
1274 | val = iv->base; | |
1275 | ||
1276 | if (iv->extend_mode == iv->mode) | |
1277 | return val; | |
1278 | ||
c0efe3c3 | 1279 | val = lowpart_subreg (iv->mode, val, iv->extend_mode); |
f9cce2dc | 1280 | |
aedb7bf8 | 1281 | if (iv->extend == IV_UNKNOWN_EXTEND) |
f9cce2dc | 1282 | return val; |
1283 | ||
aedb7bf8 | 1284 | val = simplify_gen_unary (iv_extend_to_rtx_code (iv->extend), |
1285 | iv->extend_mode, val, iv->mode); | |
f9cce2dc | 1286 | val = simplify_gen_binary (PLUS, iv->extend_mode, iv->delta, |
1287 | simplify_gen_binary (MULT, iv->extend_mode, | |
1288 | iv->mult, val)); | |
1289 | ||
1290 | return val; | |
1291 | } | |
1292 | ||
1293 | /* Free the data for an induction variable analysis. */ | |
1294 | ||
1295 | void | |
1296 | iv_analysis_done (void) | |
1297 | { | |
3072d30e | 1298 | if (!clean_slate) |
f9cce2dc | 1299 | { |
3f37d465 | 1300 | clear_iv_info (); |
3072d30e | 1301 | clean_slate = true; |
314966f4 | 1302 | df_finish_pass (true); |
c1f445d2 | 1303 | delete bivs; |
1304 | bivs = NULL; | |
3072d30e | 1305 | free (iv_ref_table); |
1306 | iv_ref_table = NULL; | |
1307 | iv_ref_table_size = 0; | |
f9cce2dc | 1308 | } |
1309 | } | |
1310 | ||
1311 | /* Computes inverse to X modulo (1 << MOD). */ | |
1312 | ||
3a4303e7 | 1313 | static uint64_t |
1314 | inverse (uint64_t x, int mod) | |
f9cce2dc | 1315 | { |
3a4303e7 | 1316 | uint64_t mask = |
1317 | ((uint64_t) 1 << (mod - 1) << 1) - 1; | |
1318 | uint64_t rslt = 1; | |
f9cce2dc | 1319 | int i; |
1320 | ||
1321 | for (i = 0; i < mod - 1; i++) | |
1322 | { | |
1323 | rslt = (rslt * x) & mask; | |
1324 | x = (x * x) & mask; | |
1325 | } | |
1326 | ||
1327 | return rslt; | |
1328 | } | |
1329 | ||
f9cce2dc | 1330 | /* Checks whether register *REG is in set ALT. Callback for for_each_rtx. */ |
1331 | ||
1332 | static int | |
1333 | altered_reg_used (rtx *reg, void *alt) | |
1334 | { | |
1335 | if (!REG_P (*reg)) | |
1336 | return 0; | |
1337 | ||
4077bf7a | 1338 | return REGNO_REG_SET_P ((bitmap) alt, REGNO (*reg)); |
f9cce2dc | 1339 | } |
1340 | ||
1341 | /* Marks registers altered by EXPR in set ALT. */ | |
1342 | ||
1343 | static void | |
81a410b1 | 1344 | mark_altered (rtx expr, const_rtx by ATTRIBUTE_UNUSED, void *alt) |
f9cce2dc | 1345 | { |
1346 | if (GET_CODE (expr) == SUBREG) | |
1347 | expr = SUBREG_REG (expr); | |
1348 | if (!REG_P (expr)) | |
1349 | return; | |
1350 | ||
4077bf7a | 1351 | SET_REGNO_REG_SET ((bitmap) alt, REGNO (expr)); |
f9cce2dc | 1352 | } |
1353 | ||
1354 | /* Checks whether RHS is simple enough to process. */ | |
1355 | ||
1356 | static bool | |
1357 | simple_rhs_p (rtx rhs) | |
1358 | { | |
1359 | rtx op0, op1; | |
1360 | ||
e54e3d9f | 1361 | if (function_invariant_p (rhs) |
b06b27dd | 1362 | || (REG_P (rhs) && !HARD_REGISTER_P (rhs))) |
f9cce2dc | 1363 | return true; |
1364 | ||
1365 | switch (GET_CODE (rhs)) | |
1366 | { | |
1367 | case PLUS: | |
1368 | case MINUS: | |
b908751e | 1369 | case AND: |
f9cce2dc | 1370 | op0 = XEXP (rhs, 0); |
1371 | op1 = XEXP (rhs, 1); | |
b908751e | 1372 | /* Allow reg OP const and reg OP reg. */ |
b718fe63 | 1373 | if (!(REG_P (op0) && !HARD_REGISTER_P (op0)) |
cf36214f | 1374 | && !function_invariant_p (op0)) |
b718fe63 | 1375 | return false; |
1376 | if (!(REG_P (op1) && !HARD_REGISTER_P (op1)) | |
cf36214f | 1377 | && !function_invariant_p (op1)) |
b718fe63 | 1378 | return false; |
f9cce2dc | 1379 | |
b718fe63 | 1380 | return true; |
1381 | ||
1382 | case ASHIFT: | |
b908751e | 1383 | case ASHIFTRT: |
1384 | case LSHIFTRT: | |
1385 | case MULT: | |
b718fe63 | 1386 | op0 = XEXP (rhs, 0); |
1387 | op1 = XEXP (rhs, 1); | |
b908751e | 1388 | /* Allow reg OP const. */ |
b718fe63 | 1389 | if (!(REG_P (op0) && !HARD_REGISTER_P (op0))) |
1390 | return false; | |
cf36214f | 1391 | if (!function_invariant_p (op1)) |
b718fe63 | 1392 | return false; |
1393 | ||
1394 | return true; | |
f9cce2dc | 1395 | |
1396 | default: | |
1397 | return false; | |
1398 | } | |
1399 | } | |
1400 | ||
767cb310 | 1401 | /* If REG has a single definition, replace it with its known value in EXPR. |
1402 | Callback for for_each_rtx. */ | |
1403 | ||
1404 | static int | |
1405 | replace_single_def_regs (rtx *reg, void *expr1) | |
1406 | { | |
1407 | unsigned regno; | |
1408 | df_ref adef; | |
3a40262c | 1409 | rtx set, src; |
767cb310 | 1410 | rtx *expr = (rtx *)expr1; |
1411 | ||
1412 | if (!REG_P (*reg)) | |
1413 | return 0; | |
1414 | ||
1415 | regno = REGNO (*reg); | |
3a40262c | 1416 | for (;;) |
1417 | { | |
1418 | rtx note; | |
1419 | adef = DF_REG_DEF_CHAIN (regno); | |
1420 | if (adef == NULL || DF_REF_NEXT_REG (adef) != NULL | |
1421 | || DF_REF_IS_ARTIFICIAL (adef)) | |
1422 | return -1; | |
1423 | ||
1424 | set = single_set (DF_REF_INSN (adef)); | |
1425 | if (set == NULL || !REG_P (SET_DEST (set)) | |
1426 | || REGNO (SET_DEST (set)) != regno) | |
1427 | return -1; | |
767cb310 | 1428 | |
3a40262c | 1429 | note = find_reg_equal_equiv_note (DF_REF_INSN (adef)); |
1430 | ||
1431 | if (note && function_invariant_p (XEXP (note, 0))) | |
1432 | { | |
1433 | src = XEXP (note, 0); | |
1434 | break; | |
1435 | } | |
1436 | src = SET_SRC (set); | |
1437 | ||
1438 | if (REG_P (src)) | |
1439 | { | |
1440 | regno = REGNO (src); | |
1441 | continue; | |
1442 | } | |
1443 | break; | |
1444 | } | |
1445 | if (!function_invariant_p (src)) | |
767cb310 | 1446 | return -1; |
1447 | ||
3a40262c | 1448 | *expr = simplify_replace_rtx (*expr, *reg, src); |
767cb310 | 1449 | return 1; |
1450 | } | |
1451 | ||
9bb5f693 | 1452 | /* A subroutine of simplify_using_initial_values, this function examines INSN |
1453 | to see if it contains a suitable set that we can use to make a replacement. | |
1454 | If it is suitable, return true and set DEST and SRC to the lhs and rhs of | |
1455 | the set; return false otherwise. */ | |
f9cce2dc | 1456 | |
9bb5f693 | 1457 | static bool |
3eeb4f9a | 1458 | suitable_set_for_replacement (rtx_insn *insn, rtx *dest, rtx *src) |
f9cce2dc | 1459 | { |
1460 | rtx set = single_set (insn); | |
1b425b8e | 1461 | rtx lhs = NULL_RTX, rhs; |
f9cce2dc | 1462 | |
9bb5f693 | 1463 | if (!set) |
1464 | return false; | |
f9cce2dc | 1465 | |
9bb5f693 | 1466 | lhs = SET_DEST (set); |
1467 | if (!REG_P (lhs)) | |
1468 | return false; | |
f9cce2dc | 1469 | |
1470 | rhs = find_reg_equal_equiv_note (insn); | |
a6629703 | 1471 | if (rhs) |
1472 | rhs = XEXP (rhs, 0); | |
1473 | else | |
f9cce2dc | 1474 | rhs = SET_SRC (set); |
1475 | ||
1476 | if (!simple_rhs_p (rhs)) | |
9bb5f693 | 1477 | return false; |
f9cce2dc | 1478 | |
9bb5f693 | 1479 | *dest = lhs; |
1480 | *src = rhs; | |
1481 | return true; | |
f9cce2dc | 1482 | } |
1483 | ||
767cb310 | 1484 | /* Using the data returned by suitable_set_for_replacement, replace DEST |
1485 | with SRC in *EXPR and return the new expression. Also call | |
1486 | replace_single_def_regs if the replacement changed something. */ | |
1487 | static void | |
1488 | replace_in_expr (rtx *expr, rtx dest, rtx src) | |
1489 | { | |
1490 | rtx old = *expr; | |
1491 | *expr = simplify_replace_rtx (*expr, dest, src); | |
1492 | if (old == *expr) | |
1493 | return; | |
1494 | while (for_each_rtx (expr, replace_single_def_regs, expr) != 0) | |
1495 | continue; | |
1496 | } | |
1497 | ||
f9cce2dc | 1498 | /* Checks whether A implies B. */ |
1499 | ||
1500 | static bool | |
1501 | implies_p (rtx a, rtx b) | |
1502 | { | |
a6629703 | 1503 | rtx op0, op1, opb0, opb1, r; |
1504 | enum machine_mode mode; | |
f9cce2dc | 1505 | |
a6d46489 | 1506 | if (rtx_equal_p (a, b)) |
1507 | return true; | |
1508 | ||
f9cce2dc | 1509 | if (GET_CODE (a) == EQ) |
1510 | { | |
1511 | op0 = XEXP (a, 0); | |
1512 | op1 = XEXP (a, 1); | |
1513 | ||
a6d46489 | 1514 | if (REG_P (op0) |
1515 | || (GET_CODE (op0) == SUBREG | |
1516 | && REG_P (SUBREG_REG (op0)))) | |
f9cce2dc | 1517 | { |
1518 | r = simplify_replace_rtx (b, op0, op1); | |
1519 | if (r == const_true_rtx) | |
1520 | return true; | |
1521 | } | |
1522 | ||
a6d46489 | 1523 | if (REG_P (op1) |
1524 | || (GET_CODE (op1) == SUBREG | |
1525 | && REG_P (SUBREG_REG (op1)))) | |
f9cce2dc | 1526 | { |
1527 | r = simplify_replace_rtx (b, op1, op0); | |
1528 | if (r == const_true_rtx) | |
1529 | return true; | |
1530 | } | |
1531 | } | |
1532 | ||
731d95c8 | 1533 | if (b == const_true_rtx) |
1534 | return true; | |
1535 | ||
1536 | if ((GET_RTX_CLASS (GET_CODE (a)) != RTX_COMM_COMPARE | |
1537 | && GET_RTX_CLASS (GET_CODE (a)) != RTX_COMPARE) | |
1538 | || (GET_RTX_CLASS (GET_CODE (b)) != RTX_COMM_COMPARE | |
1539 | && GET_RTX_CLASS (GET_CODE (b)) != RTX_COMPARE)) | |
1540 | return false; | |
1541 | ||
1542 | op0 = XEXP (a, 0); | |
1543 | op1 = XEXP (a, 1); | |
1544 | opb0 = XEXP (b, 0); | |
1545 | opb1 = XEXP (b, 1); | |
1546 | ||
1547 | mode = GET_MODE (op0); | |
1548 | if (mode != GET_MODE (opb0)) | |
1549 | mode = VOIDmode; | |
1550 | else if (mode == VOIDmode) | |
1551 | { | |
1552 | mode = GET_MODE (op1); | |
1553 | if (mode != GET_MODE (opb1)) | |
1554 | mode = VOIDmode; | |
1555 | } | |
1556 | ||
a6629703 | 1557 | /* A < B implies A + 1 <= B. */ |
1558 | if ((GET_CODE (a) == GT || GET_CODE (a) == LT) | |
1559 | && (GET_CODE (b) == GE || GET_CODE (b) == LE)) | |
1560 | { | |
a6629703 | 1561 | |
1562 | if (GET_CODE (a) == GT) | |
1563 | { | |
1564 | r = op0; | |
1565 | op0 = op1; | |
1566 | op1 = r; | |
1567 | } | |
1568 | ||
1569 | if (GET_CODE (b) == GE) | |
1570 | { | |
1571 | r = opb0; | |
1572 | opb0 = opb1; | |
1573 | opb1 = r; | |
1574 | } | |
1575 | ||
873983a1 | 1576 | if (SCALAR_INT_MODE_P (mode) |
a6629703 | 1577 | && rtx_equal_p (op1, opb1) |
1578 | && simplify_gen_binary (MINUS, mode, opb0, op0) == const1_rtx) | |
1579 | return true; | |
731d95c8 | 1580 | return false; |
1581 | } | |
1582 | ||
1583 | /* A < B or A > B imply A != B. TODO: Likewise | |
1584 | A + n < B implies A != B + n if neither wraps. */ | |
1585 | if (GET_CODE (b) == NE | |
1586 | && (GET_CODE (a) == GT || GET_CODE (a) == GTU | |
1587 | || GET_CODE (a) == LT || GET_CODE (a) == LTU)) | |
1588 | { | |
1589 | if (rtx_equal_p (op0, opb0) | |
1590 | && rtx_equal_p (op1, opb1)) | |
1591 | return true; | |
a6629703 | 1592 | } |
1593 | ||
731d95c8 | 1594 | /* For unsigned comparisons, A != 0 implies A > 0 and A >= 1. */ |
1595 | if (GET_CODE (a) == NE | |
1596 | && op1 == const0_rtx) | |
1597 | { | |
1598 | if ((GET_CODE (b) == GTU | |
1599 | && opb1 == const0_rtx) | |
1600 | || (GET_CODE (b) == GEU | |
1601 | && opb1 == const1_rtx)) | |
1602 | return rtx_equal_p (op0, opb0); | |
1603 | } | |
1604 | ||
1605 | /* A != N is equivalent to A - (N + 1) <u -1. */ | |
1606 | if (GET_CODE (a) == NE | |
971ba038 | 1607 | && CONST_INT_P (op1) |
731d95c8 | 1608 | && GET_CODE (b) == LTU |
1609 | && opb1 == constm1_rtx | |
1610 | && GET_CODE (opb0) == PLUS | |
971ba038 | 1611 | && CONST_INT_P (XEXP (opb0, 1)) |
731d95c8 | 1612 | /* Avoid overflows. */ |
1613 | && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (opb0, 1)) | |
1614 | != ((unsigned HOST_WIDE_INT)1 | |
1615 | << (HOST_BITS_PER_WIDE_INT - 1)) - 1) | |
1616 | && INTVAL (XEXP (opb0, 1)) + 1 == -INTVAL (op1)) | |
1617 | return rtx_equal_p (op0, XEXP (opb0, 0)); | |
1618 | ||
1619 | /* Likewise, A != N implies A - N > 0. */ | |
1620 | if (GET_CODE (a) == NE | |
971ba038 | 1621 | && CONST_INT_P (op1)) |
731d95c8 | 1622 | { |
1623 | if (GET_CODE (b) == GTU | |
1624 | && GET_CODE (opb0) == PLUS | |
1625 | && opb1 == const0_rtx | |
971ba038 | 1626 | && CONST_INT_P (XEXP (opb0, 1)) |
731d95c8 | 1627 | /* Avoid overflows. */ |
1628 | && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (opb0, 1)) | |
1629 | != ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1))) | |
1630 | && rtx_equal_p (XEXP (opb0, 0), op0)) | |
1631 | return INTVAL (op1) == -INTVAL (XEXP (opb0, 1)); | |
1632 | if (GET_CODE (b) == GEU | |
1633 | && GET_CODE (opb0) == PLUS | |
1634 | && opb1 == const1_rtx | |
971ba038 | 1635 | && CONST_INT_P (XEXP (opb0, 1)) |
731d95c8 | 1636 | /* Avoid overflows. */ |
1637 | && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (opb0, 1)) | |
1638 | != ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1))) | |
1639 | && rtx_equal_p (XEXP (opb0, 0), op0)) | |
1640 | return INTVAL (op1) == -INTVAL (XEXP (opb0, 1)); | |
1641 | } | |
1642 | ||
1643 | /* A >s X, where X is positive, implies A <u Y, if Y is negative. */ | |
1644 | if ((GET_CODE (a) == GT || GET_CODE (a) == GE) | |
971ba038 | 1645 | && CONST_INT_P (op1) |
731d95c8 | 1646 | && ((GET_CODE (a) == GT && op1 == constm1_rtx) |
1647 | || INTVAL (op1) >= 0) | |
1648 | && GET_CODE (b) == LTU | |
971ba038 | 1649 | && CONST_INT_P (opb1) |
27440859 | 1650 | && rtx_equal_p (op0, opb0)) |
731d95c8 | 1651 | return INTVAL (opb1) < 0; |
1652 | ||
f9cce2dc | 1653 | return false; |
1654 | } | |
1655 | ||
1656 | /* Canonicalizes COND so that | |
1657 | ||
1658 | (1) Ensure that operands are ordered according to | |
1659 | swap_commutative_operands_p. | |
1660 | (2) (LE x const) will be replaced with (LT x <const+1>) and similarly | |
1661 | for GE, GEU, and LEU. */ | |
1662 | ||
1663 | rtx | |
1664 | canon_condition (rtx cond) | |
1665 | { | |
1666 | rtx tem; | |
1667 | rtx op0, op1; | |
1668 | enum rtx_code code; | |
1669 | enum machine_mode mode; | |
1670 | ||
1671 | code = GET_CODE (cond); | |
1672 | op0 = XEXP (cond, 0); | |
1673 | op1 = XEXP (cond, 1); | |
1674 | ||
1675 | if (swap_commutative_operands_p (op0, op1)) | |
1676 | { | |
1677 | code = swap_condition (code); | |
1678 | tem = op0; | |
1679 | op0 = op1; | |
1680 | op1 = tem; | |
1681 | } | |
1682 | ||
1683 | mode = GET_MODE (op0); | |
1684 | if (mode == VOIDmode) | |
1685 | mode = GET_MODE (op1); | |
972e95af | 1686 | gcc_assert (mode != VOIDmode); |
f9cce2dc | 1687 | |
971ba038 | 1688 | if (CONST_INT_P (op1) |
f9cce2dc | 1689 | && GET_MODE_CLASS (mode) != MODE_CC |
1690 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) | |
1691 | { | |
1692 | HOST_WIDE_INT const_val = INTVAL (op1); | |
1693 | unsigned HOST_WIDE_INT uconst_val = const_val; | |
1694 | unsigned HOST_WIDE_INT max_val | |
1695 | = (unsigned HOST_WIDE_INT) GET_MODE_MASK (mode); | |
1696 | ||
1697 | switch (code) | |
1698 | { | |
1699 | case LE: | |
1700 | if ((unsigned HOST_WIDE_INT) const_val != max_val >> 1) | |
1701 | code = LT, op1 = gen_int_mode (const_val + 1, GET_MODE (op0)); | |
1702 | break; | |
1703 | ||
1704 | /* When cross-compiling, const_val might be sign-extended from | |
1705 | BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */ | |
1706 | case GE: | |
1707 | if ((HOST_WIDE_INT) (const_val & max_val) | |
1708 | != (((HOST_WIDE_INT) 1 | |
1709 | << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1)))) | |
1710 | code = GT, op1 = gen_int_mode (const_val - 1, mode); | |
1711 | break; | |
1712 | ||
1713 | case LEU: | |
1714 | if (uconst_val < max_val) | |
1715 | code = LTU, op1 = gen_int_mode (uconst_val + 1, mode); | |
1716 | break; | |
1717 | ||
1718 | case GEU: | |
1719 | if (uconst_val != 0) | |
1720 | code = GTU, op1 = gen_int_mode (uconst_val - 1, mode); | |
1721 | break; | |
1722 | ||
1723 | default: | |
1724 | break; | |
1725 | } | |
1726 | } | |
1727 | ||
1728 | if (op0 != XEXP (cond, 0) | |
1729 | || op1 != XEXP (cond, 1) | |
1730 | || code != GET_CODE (cond) | |
1731 | || GET_MODE (cond) != SImode) | |
1732 | cond = gen_rtx_fmt_ee (code, SImode, op0, op1); | |
1733 | ||
1734 | return cond; | |
1735 | } | |
1736 | ||
b99ab275 | 1737 | /* Reverses CONDition; returns NULL if we cannot. */ |
1738 | ||
1739 | static rtx | |
1740 | reversed_condition (rtx cond) | |
1741 | { | |
1742 | enum rtx_code reversed; | |
1743 | reversed = reversed_comparison_code (cond, NULL); | |
1744 | if (reversed == UNKNOWN) | |
1745 | return NULL_RTX; | |
1746 | else | |
1747 | return gen_rtx_fmt_ee (reversed, | |
1748 | GET_MODE (cond), XEXP (cond, 0), | |
1749 | XEXP (cond, 1)); | |
1750 | } | |
1751 | ||
f9cce2dc | 1752 | /* Tries to use the fact that COND holds to simplify EXPR. ALTERED is the |
1753 | set of altered regs. */ | |
1754 | ||
1755 | void | |
1756 | simplify_using_condition (rtx cond, rtx *expr, regset altered) | |
1757 | { | |
1758 | rtx rev, reve, exp = *expr; | |
1759 | ||
f9cce2dc | 1760 | /* If some register gets altered later, we do not really speak about its |
1761 | value at the time of comparison. */ | |
1762 | if (altered | |
1763 | && for_each_rtx (&cond, altered_reg_used, altered)) | |
1764 | return; | |
1765 | ||
7f7a6f4a | 1766 | if (GET_CODE (cond) == EQ |
1767 | && REG_P (XEXP (cond, 0)) && CONSTANT_P (XEXP (cond, 1))) | |
1768 | { | |
1769 | *expr = simplify_replace_rtx (*expr, XEXP (cond, 0), XEXP (cond, 1)); | |
1770 | return; | |
1771 | } | |
1772 | ||
1773 | if (!COMPARISON_P (exp)) | |
1774 | return; | |
1775 | ||
f9cce2dc | 1776 | rev = reversed_condition (cond); |
1777 | reve = reversed_condition (exp); | |
1778 | ||
1779 | cond = canon_condition (cond); | |
1780 | exp = canon_condition (exp); | |
1781 | if (rev) | |
1782 | rev = canon_condition (rev); | |
1783 | if (reve) | |
1784 | reve = canon_condition (reve); | |
1785 | ||
1786 | if (rtx_equal_p (exp, cond)) | |
1787 | { | |
1788 | *expr = const_true_rtx; | |
1789 | return; | |
1790 | } | |
1791 | ||
f9cce2dc | 1792 | if (rev && rtx_equal_p (exp, rev)) |
1793 | { | |
1794 | *expr = const0_rtx; | |
1795 | return; | |
1796 | } | |
1797 | ||
1798 | if (implies_p (cond, exp)) | |
1799 | { | |
1800 | *expr = const_true_rtx; | |
1801 | return; | |
1802 | } | |
48e1416a | 1803 | |
f9cce2dc | 1804 | if (reve && implies_p (cond, reve)) |
1805 | { | |
1806 | *expr = const0_rtx; | |
1807 | return; | |
1808 | } | |
1809 | ||
1810 | /* A proof by contradiction. If *EXPR implies (not cond), *EXPR must | |
1811 | be false. */ | |
1812 | if (rev && implies_p (exp, rev)) | |
1813 | { | |
1814 | *expr = const0_rtx; | |
1815 | return; | |
1816 | } | |
1817 | ||
1818 | /* Similarly, If (not *EXPR) implies (not cond), *EXPR must be true. */ | |
1819 | if (rev && reve && implies_p (reve, rev)) | |
1820 | { | |
1821 | *expr = const_true_rtx; | |
1822 | return; | |
1823 | } | |
1824 | ||
1825 | /* We would like to have some other tests here. TODO. */ | |
1826 | ||
1827 | return; | |
1828 | } | |
1829 | ||
1830 | /* Use relationship between A and *B to eventually eliminate *B. | |
1831 | OP is the operation we consider. */ | |
1832 | ||
1833 | static void | |
1834 | eliminate_implied_condition (enum rtx_code op, rtx a, rtx *b) | |
1835 | { | |
972e95af | 1836 | switch (op) |
f9cce2dc | 1837 | { |
972e95af | 1838 | case AND: |
f9cce2dc | 1839 | /* If A implies *B, we may replace *B by true. */ |
1840 | if (implies_p (a, *b)) | |
1841 | *b = const_true_rtx; | |
972e95af | 1842 | break; |
1843 | ||
1844 | case IOR: | |
f9cce2dc | 1845 | /* If *B implies A, we may replace *B by false. */ |
1846 | if (implies_p (*b, a)) | |
1847 | *b = const0_rtx; | |
972e95af | 1848 | break; |
1849 | ||
1850 | default: | |
1851 | gcc_unreachable (); | |
f9cce2dc | 1852 | } |
f9cce2dc | 1853 | } |
1854 | ||
1855 | /* Eliminates the conditions in TAIL that are implied by HEAD. OP is the | |
1856 | operation we consider. */ | |
1857 | ||
1858 | static void | |
1859 | eliminate_implied_conditions (enum rtx_code op, rtx *head, rtx tail) | |
1860 | { | |
1861 | rtx elt; | |
1862 | ||
1863 | for (elt = tail; elt; elt = XEXP (elt, 1)) | |
1864 | eliminate_implied_condition (op, *head, &XEXP (elt, 0)); | |
1865 | for (elt = tail; elt; elt = XEXP (elt, 1)) | |
1866 | eliminate_implied_condition (op, XEXP (elt, 0), head); | |
1867 | } | |
1868 | ||
1869 | /* Simplifies *EXPR using initial values at the start of the LOOP. If *EXPR | |
1870 | is a list, its elements are assumed to be combined using OP. */ | |
1871 | ||
1872 | static void | |
1873 | simplify_using_initial_values (struct loop *loop, enum rtx_code op, rtx *expr) | |
1874 | { | |
9bb5f693 | 1875 | bool expression_valid; |
8e56831f | 1876 | rtx head, tail, last_valid_expr; |
1877 | rtx_expr_list *cond_list; | |
3eeb4f9a | 1878 | rtx_insn *insn; |
f9cce2dc | 1879 | rtx neutral, aggr; |
9bb5f693 | 1880 | regset altered, this_altered; |
f9cce2dc | 1881 | edge e; |
1882 | ||
1883 | if (!*expr) | |
1884 | return; | |
1885 | ||
1886 | if (CONSTANT_P (*expr)) | |
1887 | return; | |
1888 | ||
1889 | if (GET_CODE (*expr) == EXPR_LIST) | |
1890 | { | |
1891 | head = XEXP (*expr, 0); | |
1892 | tail = XEXP (*expr, 1); | |
1893 | ||
1894 | eliminate_implied_conditions (op, &head, tail); | |
1895 | ||
972e95af | 1896 | switch (op) |
f9cce2dc | 1897 | { |
972e95af | 1898 | case AND: |
f9cce2dc | 1899 | neutral = const_true_rtx; |
1900 | aggr = const0_rtx; | |
972e95af | 1901 | break; |
1902 | ||
1903 | case IOR: | |
f9cce2dc | 1904 | neutral = const0_rtx; |
1905 | aggr = const_true_rtx; | |
972e95af | 1906 | break; |
f9cce2dc | 1907 | |
972e95af | 1908 | default: |
1909 | gcc_unreachable (); | |
1910 | } | |
48e1416a | 1911 | |
21f1e711 | 1912 | simplify_using_initial_values (loop, UNKNOWN, &head); |
f9cce2dc | 1913 | if (head == aggr) |
1914 | { | |
1915 | XEXP (*expr, 0) = aggr; | |
1916 | XEXP (*expr, 1) = NULL_RTX; | |
1917 | return; | |
1918 | } | |
1919 | else if (head == neutral) | |
1920 | { | |
1921 | *expr = tail; | |
1922 | simplify_using_initial_values (loop, op, expr); | |
1923 | return; | |
1924 | } | |
1925 | simplify_using_initial_values (loop, op, &tail); | |
1926 | ||
1927 | if (tail && XEXP (tail, 0) == aggr) | |
1928 | { | |
1929 | *expr = tail; | |
1930 | return; | |
1931 | } | |
48e1416a | 1932 | |
f9cce2dc | 1933 | XEXP (*expr, 0) = head; |
1934 | XEXP (*expr, 1) = tail; | |
1935 | return; | |
1936 | } | |
1937 | ||
972e95af | 1938 | gcc_assert (op == UNKNOWN); |
f9cce2dc | 1939 | |
767cb310 | 1940 | for (;;) |
1941 | if (for_each_rtx (expr, replace_single_def_regs, expr) == 0) | |
1942 | break; | |
1943 | if (CONSTANT_P (*expr)) | |
1944 | return; | |
1945 | ||
f9cce2dc | 1946 | e = loop_preheader_edge (loop); |
34154e27 | 1947 | if (e->src == ENTRY_BLOCK_PTR_FOR_FN (cfun)) |
f9cce2dc | 1948 | return; |
1949 | ||
ae85a37a | 1950 | altered = ALLOC_REG_SET (®_obstack); |
9bb5f693 | 1951 | this_altered = ALLOC_REG_SET (®_obstack); |
f9cce2dc | 1952 | |
9bb5f693 | 1953 | expression_valid = true; |
1954 | last_valid_expr = *expr; | |
8e56831f | 1955 | cond_list = NULL; |
f9cce2dc | 1956 | while (1) |
1957 | { | |
1958 | insn = BB_END (e->src); | |
1959 | if (any_condjump_p (insn)) | |
1960 | { | |
a255f65a | 1961 | rtx cond = get_condition (BB_END (e->src), NULL, false, true); |
7f7a6f4a | 1962 | |
f9cce2dc | 1963 | if (cond && (e->flags & EDGE_FALLTHRU)) |
1964 | cond = reversed_condition (cond); | |
1965 | if (cond) | |
1966 | { | |
7f7a6f4a | 1967 | rtx old = *expr; |
f9cce2dc | 1968 | simplify_using_condition (cond, expr, altered); |
7f7a6f4a | 1969 | if (old != *expr) |
1970 | { | |
1971 | rtx note; | |
1972 | if (CONSTANT_P (*expr)) | |
1973 | goto out; | |
1974 | for (note = cond_list; note; note = XEXP (note, 1)) | |
1975 | { | |
1976 | simplify_using_condition (XEXP (note, 0), expr, altered); | |
1977 | if (CONSTANT_P (*expr)) | |
1978 | goto out; | |
1979 | } | |
1980 | } | |
1981 | cond_list = alloc_EXPR_LIST (0, cond, cond_list); | |
f9cce2dc | 1982 | } |
1983 | } | |
1984 | ||
1985 | FOR_BB_INSNS_REVERSE (e->src, insn) | |
1986 | { | |
9bb5f693 | 1987 | rtx src, dest; |
7f7a6f4a | 1988 | rtx old = *expr; |
9bb5f693 | 1989 | |
f9cce2dc | 1990 | if (!INSN_P (insn)) |
1991 | continue; | |
9bb5f693 | 1992 | |
1993 | CLEAR_REG_SET (this_altered); | |
1994 | note_stores (PATTERN (insn), mark_altered, this_altered); | |
1995 | if (CALL_P (insn)) | |
f9cce2dc | 1996 | { |
9bb5f693 | 1997 | /* Kill all call clobbered registers. */ |
24ec6636 | 1998 | unsigned int i; |
1999 | hard_reg_set_iterator hrsi; | |
2000 | EXECUTE_IF_SET_IN_HARD_REG_SET (regs_invalidated_by_call, | |
2001 | 0, i, hrsi) | |
2002 | SET_REGNO_REG_SET (this_altered, i); | |
f9cce2dc | 2003 | } |
9bb5f693 | 2004 | |
2005 | if (suitable_set_for_replacement (insn, &dest, &src)) | |
9676249d | 2006 | { |
8e56831f | 2007 | rtx_expr_list **pnote, **pnote_next; |
7f7a6f4a | 2008 | |
767cb310 | 2009 | replace_in_expr (expr, dest, src); |
9bb5f693 | 2010 | if (CONSTANT_P (*expr)) |
2011 | goto out; | |
7f7a6f4a | 2012 | |
2013 | for (pnote = &cond_list; *pnote; pnote = pnote_next) | |
2014 | { | |
2015 | rtx note = *pnote; | |
2016 | rtx old_cond = XEXP (note, 0); | |
2017 | ||
8e56831f | 2018 | pnote_next = (rtx_expr_list **)&XEXP (note, 1); |
767cb310 | 2019 | replace_in_expr (&XEXP (note, 0), dest, src); |
2020 | ||
7f7a6f4a | 2021 | /* We can no longer use a condition that has been simplified |
2022 | to a constant, and simplify_using_condition will abort if | |
2023 | we try. */ | |
2024 | if (CONSTANT_P (XEXP (note, 0))) | |
2025 | { | |
2026 | *pnote = *pnote_next; | |
2027 | pnote_next = pnote; | |
2028 | free_EXPR_LIST_node (note); | |
2029 | } | |
2030 | /* Retry simplifications with this condition if either the | |
2031 | expression or the condition changed. */ | |
2032 | else if (old_cond != XEXP (note, 0) || old != *expr) | |
2033 | simplify_using_condition (XEXP (note, 0), expr, altered); | |
2034 | } | |
9676249d | 2035 | } |
9bb5f693 | 2036 | else |
1c18ed19 | 2037 | { |
8e56831f | 2038 | rtx_expr_list **pnote, **pnote_next; |
1c18ed19 | 2039 | |
2040 | /* If we did not use this insn to make a replacement, any overlap | |
2041 | between stores in this insn and our expression will cause the | |
2042 | expression to become invalid. */ | |
2043 | if (for_each_rtx (expr, altered_reg_used, this_altered)) | |
2044 | goto out; | |
2045 | ||
2046 | /* Likewise for the conditions. */ | |
2047 | for (pnote = &cond_list; *pnote; pnote = pnote_next) | |
2048 | { | |
2049 | rtx note = *pnote; | |
2050 | rtx old_cond = XEXP (note, 0); | |
2051 | ||
8e56831f | 2052 | pnote_next = (rtx_expr_list **)&XEXP (note, 1); |
1c18ed19 | 2053 | if (for_each_rtx (&old_cond, altered_reg_used, this_altered)) |
2054 | { | |
2055 | *pnote = *pnote_next; | |
2056 | pnote_next = pnote; | |
2057 | free_EXPR_LIST_node (note); | |
2058 | } | |
2059 | } | |
2060 | } | |
9bb5f693 | 2061 | |
7f7a6f4a | 2062 | if (CONSTANT_P (*expr)) |
2063 | goto out; | |
2064 | ||
9bb5f693 | 2065 | IOR_REG_SET (altered, this_altered); |
2066 | ||
2067 | /* If the expression now contains regs that have been altered, we | |
2068 | can't return it to the caller. However, it is still valid for | |
2069 | further simplification, so keep searching to see if we can | |
2070 | eventually turn it into a constant. */ | |
2071 | if (for_each_rtx (expr, altered_reg_used, altered)) | |
2072 | expression_valid = false; | |
2073 | if (expression_valid) | |
2074 | last_valid_expr = *expr; | |
f9cce2dc | 2075 | } |
2076 | ||
ea091dfd | 2077 | if (!single_pred_p (e->src) |
34154e27 | 2078 | || single_pred (e->src) == ENTRY_BLOCK_PTR_FOR_FN (cfun)) |
f9cce2dc | 2079 | break; |
ea091dfd | 2080 | e = single_pred_edge (e->src); |
f9cce2dc | 2081 | } |
2082 | ||
9bb5f693 | 2083 | out: |
7f7a6f4a | 2084 | free_EXPR_LIST_list (&cond_list); |
9bb5f693 | 2085 | if (!CONSTANT_P (*expr)) |
2086 | *expr = last_valid_expr; | |
f9cce2dc | 2087 | FREE_REG_SET (altered); |
9bb5f693 | 2088 | FREE_REG_SET (this_altered); |
f9cce2dc | 2089 | } |
2090 | ||
2091 | /* Transforms invariant IV into MODE. Adds assumptions based on the fact | |
2092 | that IV occurs as left operands of comparison COND and its signedness | |
2093 | is SIGNED_P to DESC. */ | |
2094 | ||
2095 | static void | |
2096 | shorten_into_mode (struct rtx_iv *iv, enum machine_mode mode, | |
2097 | enum rtx_code cond, bool signed_p, struct niter_desc *desc) | |
2098 | { | |
2099 | rtx mmin, mmax, cond_over, cond_under; | |
2100 | ||
a6629703 | 2101 | get_mode_bounds (mode, signed_p, iv->extend_mode, &mmin, &mmax); |
f9cce2dc | 2102 | cond_under = simplify_gen_relational (LT, SImode, iv->extend_mode, |
2103 | iv->base, mmin); | |
2104 | cond_over = simplify_gen_relational (GT, SImode, iv->extend_mode, | |
2105 | iv->base, mmax); | |
2106 | ||
2107 | switch (cond) | |
2108 | { | |
2109 | case LE: | |
2110 | case LT: | |
2111 | case LEU: | |
2112 | case LTU: | |
2113 | if (cond_under != const0_rtx) | |
2114 | desc->infinite = | |
2115 | alloc_EXPR_LIST (0, cond_under, desc->infinite); | |
2116 | if (cond_over != const0_rtx) | |
2117 | desc->noloop_assumptions = | |
2118 | alloc_EXPR_LIST (0, cond_over, desc->noloop_assumptions); | |
2119 | break; | |
2120 | ||
2121 | case GE: | |
2122 | case GT: | |
2123 | case GEU: | |
2124 | case GTU: | |
2125 | if (cond_over != const0_rtx) | |
2126 | desc->infinite = | |
2127 | alloc_EXPR_LIST (0, cond_over, desc->infinite); | |
2128 | if (cond_under != const0_rtx) | |
2129 | desc->noloop_assumptions = | |
2130 | alloc_EXPR_LIST (0, cond_under, desc->noloop_assumptions); | |
2131 | break; | |
2132 | ||
2133 | case NE: | |
2134 | if (cond_over != const0_rtx) | |
2135 | desc->infinite = | |
2136 | alloc_EXPR_LIST (0, cond_over, desc->infinite); | |
2137 | if (cond_under != const0_rtx) | |
2138 | desc->infinite = | |
2139 | alloc_EXPR_LIST (0, cond_under, desc->infinite); | |
2140 | break; | |
2141 | ||
2142 | default: | |
972e95af | 2143 | gcc_unreachable (); |
f9cce2dc | 2144 | } |
2145 | ||
2146 | iv->mode = mode; | |
aedb7bf8 | 2147 | iv->extend = signed_p ? IV_SIGN_EXTEND : IV_ZERO_EXTEND; |
f9cce2dc | 2148 | } |
2149 | ||
2150 | /* Transforms IV0 and IV1 compared by COND so that they are both compared as | |
aab2cf92 | 2151 | subregs of the same mode if possible (sometimes it is necessary to add |
f9cce2dc | 2152 | some assumptions to DESC). */ |
2153 | ||
2154 | static bool | |
2155 | canonicalize_iv_subregs (struct rtx_iv *iv0, struct rtx_iv *iv1, | |
2156 | enum rtx_code cond, struct niter_desc *desc) | |
2157 | { | |
2158 | enum machine_mode comp_mode; | |
2159 | bool signed_p; | |
2160 | ||
2161 | /* If the ivs behave specially in the first iteration, or are | |
2162 | added/multiplied after extending, we ignore them. */ | |
2163 | if (iv0->first_special || iv0->mult != const1_rtx || iv0->delta != const0_rtx) | |
2164 | return false; | |
2165 | if (iv1->first_special || iv1->mult != const1_rtx || iv1->delta != const0_rtx) | |
2166 | return false; | |
2167 | ||
2168 | /* If there is some extend, it must match signedness of the comparison. */ | |
2169 | switch (cond) | |
2170 | { | |
2171 | case LE: | |
2172 | case LT: | |
aedb7bf8 | 2173 | if (iv0->extend == IV_ZERO_EXTEND |
2174 | || iv1->extend == IV_ZERO_EXTEND) | |
f9cce2dc | 2175 | return false; |
2176 | signed_p = true; | |
2177 | break; | |
2178 | ||
2179 | case LEU: | |
2180 | case LTU: | |
aedb7bf8 | 2181 | if (iv0->extend == IV_SIGN_EXTEND |
2182 | || iv1->extend == IV_SIGN_EXTEND) | |
f9cce2dc | 2183 | return false; |
2184 | signed_p = false; | |
2185 | break; | |
2186 | ||
2187 | case NE: | |
aedb7bf8 | 2188 | if (iv0->extend != IV_UNKNOWN_EXTEND |
2189 | && iv1->extend != IV_UNKNOWN_EXTEND | |
f9cce2dc | 2190 | && iv0->extend != iv1->extend) |
2191 | return false; | |
2192 | ||
2193 | signed_p = false; | |
aedb7bf8 | 2194 | if (iv0->extend != IV_UNKNOWN_EXTEND) |
2195 | signed_p = iv0->extend == IV_SIGN_EXTEND; | |
2196 | if (iv1->extend != IV_UNKNOWN_EXTEND) | |
2197 | signed_p = iv1->extend == IV_SIGN_EXTEND; | |
f9cce2dc | 2198 | break; |
2199 | ||
2200 | default: | |
972e95af | 2201 | gcc_unreachable (); |
f9cce2dc | 2202 | } |
2203 | ||
2204 | /* Values of both variables should be computed in the same mode. These | |
2205 | might indeed be different, if we have comparison like | |
2206 | ||
2207 | (compare (subreg:SI (iv0)) (subreg:SI (iv1))) | |
2208 | ||
2209 | and iv0 and iv1 are both ivs iterating in SI mode, but calculated | |
2210 | in different modes. This does not seem impossible to handle, but | |
2211 | it hardly ever occurs in practice. | |
48e1416a | 2212 | |
f9cce2dc | 2213 | The only exception is the case when one of operands is invariant. |
2214 | For example pentium 3 generates comparisons like | |
2215 | (lt (subreg:HI (reg:SI)) 100). Here we assign HImode to 100, but we | |
2216 | definitely do not want this prevent the optimization. */ | |
2217 | comp_mode = iv0->extend_mode; | |
2218 | if (GET_MODE_BITSIZE (comp_mode) < GET_MODE_BITSIZE (iv1->extend_mode)) | |
2219 | comp_mode = iv1->extend_mode; | |
2220 | ||
2221 | if (iv0->extend_mode != comp_mode) | |
2222 | { | |
2223 | if (iv0->mode != iv0->extend_mode | |
2224 | || iv0->step != const0_rtx) | |
2225 | return false; | |
2226 | ||
2227 | iv0->base = simplify_gen_unary (signed_p ? SIGN_EXTEND : ZERO_EXTEND, | |
2228 | comp_mode, iv0->base, iv0->mode); | |
2229 | iv0->extend_mode = comp_mode; | |
2230 | } | |
2231 | ||
2232 | if (iv1->extend_mode != comp_mode) | |
2233 | { | |
2234 | if (iv1->mode != iv1->extend_mode | |
2235 | || iv1->step != const0_rtx) | |
2236 | return false; | |
2237 | ||
2238 | iv1->base = simplify_gen_unary (signed_p ? SIGN_EXTEND : ZERO_EXTEND, | |
2239 | comp_mode, iv1->base, iv1->mode); | |
2240 | iv1->extend_mode = comp_mode; | |
2241 | } | |
2242 | ||
2243 | /* Check that both ivs belong to a range of a single mode. If one of the | |
2244 | operands is an invariant, we may need to shorten it into the common | |
2245 | mode. */ | |
2246 | if (iv0->mode == iv0->extend_mode | |
2247 | && iv0->step == const0_rtx | |
2248 | && iv0->mode != iv1->mode) | |
2249 | shorten_into_mode (iv0, iv1->mode, cond, signed_p, desc); | |
2250 | ||
2251 | if (iv1->mode == iv1->extend_mode | |
2252 | && iv1->step == const0_rtx | |
2253 | && iv0->mode != iv1->mode) | |
2254 | shorten_into_mode (iv1, iv0->mode, swap_condition (cond), signed_p, desc); | |
2255 | ||
2256 | if (iv0->mode != iv1->mode) | |
2257 | return false; | |
2258 | ||
2259 | desc->mode = iv0->mode; | |
2260 | desc->signed_p = signed_p; | |
2261 | ||
2262 | return true; | |
2263 | } | |
2264 | ||
8fb72e03 | 2265 | /* Tries to estimate the maximum number of iterations in LOOP, and return the |
2266 | result. This function is called from iv_number_of_iterations with | |
f77c1bb0 | 2267 | a number of fields in DESC already filled in. OLD_NITER is the original |
2268 | expression for the number of iterations, before we tried to simplify it. */ | |
c9d59418 | 2269 | |
3a4303e7 | 2270 | static uint64_t |
f77c1bb0 | 2271 | determine_max_iter (struct loop *loop, struct niter_desc *desc, rtx old_niter) |
c9d59418 | 2272 | { |
2273 | rtx niter = desc->niter_expr; | |
731d95c8 | 2274 | rtx mmin, mmax, cmp; |
3a4303e7 | 2275 | uint64_t nmax, inc; |
2276 | uint64_t andmax = 0; | |
4678223d | 2277 | |
2278 | /* We used to look for constant operand 0 of AND, | |
2279 | but canonicalization should always make this impossible. */ | |
2280 | gcc_checking_assert (GET_CODE (niter) != AND | |
2281 | || !CONST_INT_P (XEXP (niter, 0))); | |
c9d59418 | 2282 | |
2283 | if (GET_CODE (niter) == AND | |
4678223d | 2284 | && CONST_INT_P (XEXP (niter, 1))) |
c9d59418 | 2285 | { |
4678223d | 2286 | andmax = UINTVAL (XEXP (niter, 1)); |
2287 | niter = XEXP (niter, 0); | |
c9d59418 | 2288 | } |
2289 | ||
2290 | get_mode_bounds (desc->mode, desc->signed_p, desc->mode, &mmin, &mmax); | |
2291 | nmax = INTVAL (mmax) - INTVAL (mmin); | |
2292 | ||
2293 | if (GET_CODE (niter) == UDIV) | |
2294 | { | |
971ba038 | 2295 | if (!CONST_INT_P (XEXP (niter, 1))) |
8fb72e03 | 2296 | return nmax; |
c9d59418 | 2297 | inc = INTVAL (XEXP (niter, 1)); |
2298 | niter = XEXP (niter, 0); | |
2299 | } | |
2300 | else | |
2301 | inc = 1; | |
2302 | ||
731d95c8 | 2303 | /* We could use a binary search here, but for now improving the upper |
2304 | bound by just one eliminates one important corner case. */ | |
f77c1bb0 | 2305 | cmp = simplify_gen_relational (desc->signed_p ? LT : LTU, VOIDmode, |
2306 | desc->mode, old_niter, mmax); | |
731d95c8 | 2307 | simplify_using_initial_values (loop, UNKNOWN, &cmp); |
2308 | if (cmp == const_true_rtx) | |
c9d59418 | 2309 | { |
731d95c8 | 2310 | nmax--; |
c9d59418 | 2311 | |
731d95c8 | 2312 | if (dump_file) |
2313 | fprintf (dump_file, ";; improved upper bound by one.\n"); | |
c9d59418 | 2314 | } |
4678223d | 2315 | nmax /= inc; |
2316 | if (andmax) | |
2317 | nmax = MIN (nmax, andmax); | |
2318 | if (dump_file) | |
3a4303e7 | 2319 | fprintf (dump_file, ";; Determined upper bound %"PRId64".\n", |
4678223d | 2320 | nmax); |
2321 | return nmax; | |
c9d59418 | 2322 | } |
2323 | ||
f9cce2dc | 2324 | /* Computes number of iterations of the CONDITION in INSN in LOOP and stores |
2325 | the result into DESC. Very similar to determine_number_of_iterations | |
2326 | (basically its rtl version), complicated by things like subregs. */ | |
2327 | ||
d9918998 | 2328 | static void |
3eeb4f9a | 2329 | iv_number_of_iterations (struct loop *loop, rtx_insn *insn, rtx condition, |
f9cce2dc | 2330 | struct niter_desc *desc) |
2331 | { | |
3f37d465 | 2332 | rtx op0, op1, delta, step, bound, may_xform, tmp, tmp0, tmp1; |
f9cce2dc | 2333 | struct rtx_iv iv0, iv1, tmp_iv; |
a6629703 | 2334 | rtx assumption, may_not_xform; |
f9cce2dc | 2335 | enum rtx_code cond; |
2336 | enum machine_mode mode, comp_mode; | |
a6629703 | 2337 | rtx mmin, mmax, mode_mmin, mode_mmax; |
3a4303e7 | 2338 | uint64_t s, size, d, inv, max; |
2339 | int64_t up, down, inc, step_val; | |
f9cce2dc | 2340 | int was_sharp = false; |
1e8e4a1d | 2341 | rtx old_niter; |
f8f90b50 | 2342 | bool step_is_pow2; |
f9cce2dc | 2343 | |
2344 | /* The meaning of these assumptions is this: | |
2345 | if !assumptions | |
2346 | then the rest of information does not have to be valid | |
2347 | if noloop_assumptions then the loop does not roll | |
2348 | if infinite then this exit is never used */ | |
2349 | ||
2350 | desc->assumptions = NULL_RTX; | |
2351 | desc->noloop_assumptions = NULL_RTX; | |
2352 | desc->infinite = NULL_RTX; | |
2353 | desc->simple_p = true; | |
2354 | ||
2355 | desc->const_iter = false; | |
2356 | desc->niter_expr = NULL_RTX; | |
f9cce2dc | 2357 | |
2358 | cond = GET_CODE (condition); | |
972e95af | 2359 | gcc_assert (COMPARISON_P (condition)); |
f9cce2dc | 2360 | |
2361 | mode = GET_MODE (XEXP (condition, 0)); | |
2362 | if (mode == VOIDmode) | |
2363 | mode = GET_MODE (XEXP (condition, 1)); | |
2364 | /* The constant comparisons should be folded. */ | |
972e95af | 2365 | gcc_assert (mode != VOIDmode); |
f9cce2dc | 2366 | |
2367 | /* We only handle integers or pointers. */ | |
2368 | if (GET_MODE_CLASS (mode) != MODE_INT | |
2369 | && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT) | |
2370 | goto fail; | |
2371 | ||
2372 | op0 = XEXP (condition, 0); | |
3f37d465 | 2373 | if (!iv_analyze (insn, op0, &iv0)) |
f9cce2dc | 2374 | goto fail; |
2375 | if (iv0.extend_mode == VOIDmode) | |
2376 | iv0.mode = iv0.extend_mode = mode; | |
48e1416a | 2377 | |
f9cce2dc | 2378 | op1 = XEXP (condition, 1); |
3f37d465 | 2379 | if (!iv_analyze (insn, op1, &iv1)) |
f9cce2dc | 2380 | goto fail; |
2381 | if (iv1.extend_mode == VOIDmode) | |
2382 | iv1.mode = iv1.extend_mode = mode; | |
2383 | ||
2384 | if (GET_MODE_BITSIZE (iv0.extend_mode) > HOST_BITS_PER_WIDE_INT | |
2385 | || GET_MODE_BITSIZE (iv1.extend_mode) > HOST_BITS_PER_WIDE_INT) | |
2386 | goto fail; | |
2387 | ||
2388 | /* Check condition and normalize it. */ | |
2389 | ||
2390 | switch (cond) | |
2391 | { | |
2392 | case GE: | |
2393 | case GT: | |
2394 | case GEU: | |
2395 | case GTU: | |
2396 | tmp_iv = iv0; iv0 = iv1; iv1 = tmp_iv; | |
2397 | cond = swap_condition (cond); | |
2398 | break; | |
2399 | case NE: | |
2400 | case LE: | |
2401 | case LEU: | |
2402 | case LT: | |
2403 | case LTU: | |
2404 | break; | |
2405 | default: | |
2406 | goto fail; | |
2407 | } | |
2408 | ||
2409 | /* Handle extends. This is relatively nontrivial, so we only try in some | |
2410 | easy cases, when we can canonicalize the ivs (possibly by adding some | |
2411 | assumptions) to shape subreg (base + i * step). This function also fills | |
2412 | in desc->mode and desc->signed_p. */ | |
2413 | ||
2414 | if (!canonicalize_iv_subregs (&iv0, &iv1, cond, desc)) | |
2415 | goto fail; | |
2416 | ||
2417 | comp_mode = iv0.extend_mode; | |
2418 | mode = iv0.mode; | |
2419 | size = GET_MODE_BITSIZE (mode); | |
a6629703 | 2420 | get_mode_bounds (mode, (cond == LE || cond == LT), comp_mode, &mmin, &mmax); |
c0efe3c3 | 2421 | mode_mmin = lowpart_subreg (mode, mmin, comp_mode); |
2422 | mode_mmax = lowpart_subreg (mode, mmax, comp_mode); | |
f9cce2dc | 2423 | |
971ba038 | 2424 | if (!CONST_INT_P (iv0.step) || !CONST_INT_P (iv1.step)) |
f9cce2dc | 2425 | goto fail; |
2426 | ||
2427 | /* We can take care of the case of two induction variables chasing each other | |
2428 | if the test is NE. I have never seen a loop using it, but still it is | |
2429 | cool. */ | |
2430 | if (iv0.step != const0_rtx && iv1.step != const0_rtx) | |
2431 | { | |
2432 | if (cond != NE) | |
2433 | goto fail; | |
2434 | ||
2435 | iv0.step = simplify_gen_binary (MINUS, comp_mode, iv0.step, iv1.step); | |
2436 | iv1.step = const0_rtx; | |
2437 | } | |
2438 | ||
e4bef271 | 2439 | iv0.step = lowpart_subreg (mode, iv0.step, comp_mode); |
2440 | iv1.step = lowpart_subreg (mode, iv1.step, comp_mode); | |
2441 | ||
f9cce2dc | 2442 | /* This is either infinite loop or the one that ends immediately, depending |
2443 | on initial values. Unswitching should remove this kind of conditions. */ | |
2444 | if (iv0.step == const0_rtx && iv1.step == const0_rtx) | |
2445 | goto fail; | |
2446 | ||
f8f90b50 | 2447 | if (cond != NE) |
2448 | { | |
2449 | if (iv0.step == const0_rtx) | |
2450 | step_val = -INTVAL (iv1.step); | |
2451 | else | |
15943825 | 2452 | step_val = INTVAL (iv0.step); |
f8f90b50 | 2453 | |
2454 | /* Ignore loops of while (i-- < 10) type. */ | |
2455 | if (step_val < 0) | |
2456 | goto fail; | |
2457 | ||
2458 | step_is_pow2 = !(step_val & (step_val - 1)); | |
2459 | } | |
2460 | else | |
2461 | { | |
2462 | /* We do not care about whether the step is power of two in this | |
2463 | case. */ | |
2464 | step_is_pow2 = false; | |
2465 | step_val = 0; | |
2466 | } | |
f9cce2dc | 2467 | |
2468 | /* Some more condition normalization. We must record some assumptions | |
2469 | due to overflows. */ | |
2470 | switch (cond) | |
2471 | { | |
2472 | case LT: | |
2473 | case LTU: | |
2474 | /* We want to take care only of non-sharp relationals; this is easy, | |
2475 | as in cases the overflow would make the transformation unsafe | |
2476 | the loop does not roll. Seemingly it would make more sense to want | |
2477 | to take care of sharp relationals instead, as NE is more similar to | |
2478 | them, but the problem is that here the transformation would be more | |
2479 | difficult due to possibly infinite loops. */ | |
2480 | if (iv0.step == const0_rtx) | |
2481 | { | |
c0efe3c3 | 2482 | tmp = lowpart_subreg (mode, iv0.base, comp_mode); |
a6629703 | 2483 | assumption = simplify_gen_relational (EQ, SImode, mode, tmp, |
2484 | mode_mmax); | |
f9cce2dc | 2485 | if (assumption == const_true_rtx) |
f30c7901 | 2486 | goto zero_iter_simplify; |
f9cce2dc | 2487 | iv0.base = simplify_gen_binary (PLUS, comp_mode, |
2488 | iv0.base, const1_rtx); | |
2489 | } | |
2490 | else | |
2491 | { | |
c0efe3c3 | 2492 | tmp = lowpart_subreg (mode, iv1.base, comp_mode); |
a6629703 | 2493 | assumption = simplify_gen_relational (EQ, SImode, mode, tmp, |
2494 | mode_mmin); | |
f9cce2dc | 2495 | if (assumption == const_true_rtx) |
f30c7901 | 2496 | goto zero_iter_simplify; |
f9cce2dc | 2497 | iv1.base = simplify_gen_binary (PLUS, comp_mode, |
2498 | iv1.base, constm1_rtx); | |
2499 | } | |
2500 | ||
2501 | if (assumption != const0_rtx) | |
2502 | desc->noloop_assumptions = | |
2503 | alloc_EXPR_LIST (0, assumption, desc->noloop_assumptions); | |
2504 | cond = (cond == LT) ? LE : LEU; | |
2505 | ||
2506 | /* It will be useful to be able to tell the difference once more in | |
2507 | LE -> NE reduction. */ | |
2508 | was_sharp = true; | |
2509 | break; | |
2510 | default: ; | |
2511 | } | |
2512 | ||
2513 | /* Take care of trivially infinite loops. */ | |
2514 | if (cond != NE) | |
2515 | { | |
2516 | if (iv0.step == const0_rtx) | |
2517 | { | |
c0efe3c3 | 2518 | tmp = lowpart_subreg (mode, iv0.base, comp_mode); |
a6629703 | 2519 | if (rtx_equal_p (tmp, mode_mmin)) |
f9cce2dc | 2520 | { |
2521 | desc->infinite = | |
2522 | alloc_EXPR_LIST (0, const_true_rtx, NULL_RTX); | |
f30c7901 | 2523 | /* Fill in the remaining fields somehow. */ |
2524 | goto zero_iter_simplify; | |
f9cce2dc | 2525 | } |
2526 | } | |
2527 | else | |
2528 | { | |
c0efe3c3 | 2529 | tmp = lowpart_subreg (mode, iv1.base, comp_mode); |
a6629703 | 2530 | if (rtx_equal_p (tmp, mode_mmax)) |
f9cce2dc | 2531 | { |
2532 | desc->infinite = | |
2533 | alloc_EXPR_LIST (0, const_true_rtx, NULL_RTX); | |
f30c7901 | 2534 | /* Fill in the remaining fields somehow. */ |
2535 | goto zero_iter_simplify; | |
f9cce2dc | 2536 | } |
2537 | } | |
2538 | } | |
2539 | ||
2540 | /* If we can we want to take care of NE conditions instead of size | |
2541 | comparisons, as they are much more friendly (most importantly | |
2542 | this takes care of special handling of loops with step 1). We can | |
2543 | do it if we first check that upper bound is greater or equal to | |
2544 | lower bound, their difference is constant c modulo step and that | |
2545 | there is not an overflow. */ | |
2546 | if (cond != NE) | |
2547 | { | |
2548 | if (iv0.step == const0_rtx) | |
2549 | step = simplify_gen_unary (NEG, comp_mode, iv1.step, comp_mode); | |
2550 | else | |
2551 | step = iv0.step; | |
e4bef271 | 2552 | step = lowpart_subreg (mode, step, comp_mode); |
f9cce2dc | 2553 | delta = simplify_gen_binary (MINUS, comp_mode, iv1.base, iv0.base); |
c0efe3c3 | 2554 | delta = lowpart_subreg (mode, delta, comp_mode); |
f9cce2dc | 2555 | delta = simplify_gen_binary (UMOD, mode, delta, step); |
2556 | may_xform = const0_rtx; | |
a6629703 | 2557 | may_not_xform = const_true_rtx; |
f9cce2dc | 2558 | |
971ba038 | 2559 | if (CONST_INT_P (delta)) |
f9cce2dc | 2560 | { |
2561 | if (was_sharp && INTVAL (delta) == INTVAL (step) - 1) | |
2562 | { | |
2563 | /* A special case. We have transformed condition of type | |
2564 | for (i = 0; i < 4; i += 4) | |
2565 | into | |
2566 | for (i = 0; i <= 3; i += 4) | |
2567 | obviously if the test for overflow during that transformation | |
2568 | passed, we cannot overflow here. Most importantly any | |
2569 | loop with sharp end condition and step 1 falls into this | |
aab2cf92 | 2570 | category, so handling this case specially is definitely |
f9cce2dc | 2571 | worth the troubles. */ |
2572 | may_xform = const_true_rtx; | |
2573 | } | |
2574 | else if (iv0.step == const0_rtx) | |
2575 | { | |
2576 | bound = simplify_gen_binary (PLUS, comp_mode, mmin, step); | |
2577 | bound = simplify_gen_binary (MINUS, comp_mode, bound, delta); | |
c0efe3c3 | 2578 | bound = lowpart_subreg (mode, bound, comp_mode); |
2579 | tmp = lowpart_subreg (mode, iv0.base, comp_mode); | |
f9cce2dc | 2580 | may_xform = simplify_gen_relational (cond, SImode, mode, |
2581 | bound, tmp); | |
a6629703 | 2582 | may_not_xform = simplify_gen_relational (reverse_condition (cond), |
2583 | SImode, mode, | |
2584 | bound, tmp); | |
f9cce2dc | 2585 | } |
2586 | else | |
2587 | { | |
2588 | bound = simplify_gen_binary (MINUS, comp_mode, mmax, step); | |
2589 | bound = simplify_gen_binary (PLUS, comp_mode, bound, delta); | |
c0efe3c3 | 2590 | bound = lowpart_subreg (mode, bound, comp_mode); |
2591 | tmp = lowpart_subreg (mode, iv1.base, comp_mode); | |
f9cce2dc | 2592 | may_xform = simplify_gen_relational (cond, SImode, mode, |
2593 | tmp, bound); | |
a6629703 | 2594 | may_not_xform = simplify_gen_relational (reverse_condition (cond), |
2595 | SImode, mode, | |
2596 | tmp, bound); | |
f9cce2dc | 2597 | } |
2598 | } | |
2599 | ||
2600 | if (may_xform != const0_rtx) | |
2601 | { | |
2602 | /* We perform the transformation always provided that it is not | |
2603 | completely senseless. This is OK, as we would need this assumption | |
2604 | to determine the number of iterations anyway. */ | |
2605 | if (may_xform != const_true_rtx) | |
a6629703 | 2606 | { |
2607 | /* If the step is a power of two and the final value we have | |
2608 | computed overflows, the cycle is infinite. Otherwise it | |
2609 | is nontrivial to compute the number of iterations. */ | |
f8f90b50 | 2610 | if (step_is_pow2) |
a6629703 | 2611 | desc->infinite = alloc_EXPR_LIST (0, may_not_xform, |
2612 | desc->infinite); | |
2613 | else | |
2614 | desc->assumptions = alloc_EXPR_LIST (0, may_xform, | |
2615 | desc->assumptions); | |
2616 | } | |
f9cce2dc | 2617 | |
2618 | /* We are going to lose some information about upper bound on | |
2619 | number of iterations in this step, so record the information | |
2620 | here. */ | |
2621 | inc = INTVAL (iv0.step) - INTVAL (iv1.step); | |
971ba038 | 2622 | if (CONST_INT_P (iv1.base)) |
f9cce2dc | 2623 | up = INTVAL (iv1.base); |
2624 | else | |
a6629703 | 2625 | up = INTVAL (mode_mmax) - inc; |
971ba038 | 2626 | down = INTVAL (CONST_INT_P (iv0.base) |
a6629703 | 2627 | ? iv0.base |
2628 | : mode_mmin); | |
8fb72e03 | 2629 | max = (up - down) / inc + 1; |
43780738 | 2630 | if (!desc->infinite |
2631 | && !desc->assumptions) | |
e913b5cd | 2632 | record_niter_bound (loop, max, false, true); |
f9cce2dc | 2633 | |
2634 | if (iv0.step == const0_rtx) | |
2635 | { | |
2636 | iv0.base = simplify_gen_binary (PLUS, comp_mode, iv0.base, delta); | |
2637 | iv0.base = simplify_gen_binary (MINUS, comp_mode, iv0.base, step); | |
2638 | } | |
2639 | else | |
2640 | { | |
2641 | iv1.base = simplify_gen_binary (MINUS, comp_mode, iv1.base, delta); | |
2642 | iv1.base = simplify_gen_binary (PLUS, comp_mode, iv1.base, step); | |
2643 | } | |
2644 | ||
c0efe3c3 | 2645 | tmp0 = lowpart_subreg (mode, iv0.base, comp_mode); |
2646 | tmp1 = lowpart_subreg (mode, iv1.base, comp_mode); | |
f9cce2dc | 2647 | assumption = simplify_gen_relational (reverse_condition (cond), |
2648 | SImode, mode, tmp0, tmp1); | |
2649 | if (assumption == const_true_rtx) | |
f30c7901 | 2650 | goto zero_iter_simplify; |
f9cce2dc | 2651 | else if (assumption != const0_rtx) |
2652 | desc->noloop_assumptions = | |
2653 | alloc_EXPR_LIST (0, assumption, desc->noloop_assumptions); | |
2654 | cond = NE; | |
2655 | } | |
2656 | } | |
2657 | ||
2658 | /* Count the number of iterations. */ | |
2659 | if (cond == NE) | |
2660 | { | |
2661 | /* Everything we do here is just arithmetics modulo size of mode. This | |
2662 | makes us able to do more involved computations of number of iterations | |
2663 | than in other cases. First transform the condition into shape | |
2664 | s * i <> c, with s positive. */ | |
2665 | iv1.base = simplify_gen_binary (MINUS, comp_mode, iv1.base, iv0.base); | |
2666 | iv0.base = const0_rtx; | |
2667 | iv0.step = simplify_gen_binary (MINUS, comp_mode, iv0.step, iv1.step); | |
2668 | iv1.step = const0_rtx; | |
2669 | if (INTVAL (iv0.step) < 0) | |
2670 | { | |
e913b5cd | 2671 | iv0.step = simplify_gen_unary (NEG, comp_mode, iv0.step, comp_mode); |
2672 | iv1.base = simplify_gen_unary (NEG, comp_mode, iv1.base, comp_mode); | |
f9cce2dc | 2673 | } |
c0efe3c3 | 2674 | iv0.step = lowpart_subreg (mode, iv0.step, comp_mode); |
f9cce2dc | 2675 | |
2676 | /* Let nsd (s, size of mode) = d. If d does not divide c, the loop | |
2677 | is infinite. Otherwise, the number of iterations is | |
2678 | (inverse(s/d) * (c/d)) mod (size of mode/d). */ | |
2679 | s = INTVAL (iv0.step); d = 1; | |
2680 | while (s % 2 != 1) | |
2681 | { | |
2682 | s /= 2; | |
2683 | d *= 2; | |
2684 | size--; | |
2685 | } | |
3a4303e7 | 2686 | bound = GEN_INT (((uint64_t) 1 << (size - 1 ) << 1) - 1); |
f9cce2dc | 2687 | |
c0efe3c3 | 2688 | tmp1 = lowpart_subreg (mode, iv1.base, comp_mode); |
5d5ee71f | 2689 | tmp = simplify_gen_binary (UMOD, mode, tmp1, gen_int_mode (d, mode)); |
f9cce2dc | 2690 | assumption = simplify_gen_relational (NE, SImode, mode, tmp, const0_rtx); |
2691 | desc->infinite = alloc_EXPR_LIST (0, assumption, desc->infinite); | |
2692 | ||
5d5ee71f | 2693 | tmp = simplify_gen_binary (UDIV, mode, tmp1, gen_int_mode (d, mode)); |
a6629703 | 2694 | inv = inverse (s, size); |
69e41517 | 2695 | tmp = simplify_gen_binary (MULT, mode, tmp, gen_int_mode (inv, mode)); |
f9cce2dc | 2696 | desc->niter_expr = simplify_gen_binary (AND, mode, tmp, bound); |
2697 | } | |
2698 | else | |
2699 | { | |
2700 | if (iv1.step == const0_rtx) | |
2701 | /* Condition in shape a + s * i <= b | |
2702 | We must know that b + s does not overflow and a <= b + s and then we | |
2703 | can compute number of iterations as (b + s - a) / s. (It might | |
2704 | seem that we in fact could be more clever about testing the b + s | |
2705 | overflow condition using some information about b - a mod s, | |
2706 | but it was already taken into account during LE -> NE transform). */ | |
2707 | { | |
2708 | step = iv0.step; | |
c0efe3c3 | 2709 | tmp0 = lowpart_subreg (mode, iv0.base, comp_mode); |
2710 | tmp1 = lowpart_subreg (mode, iv1.base, comp_mode); | |
f9cce2dc | 2711 | |
a6629703 | 2712 | bound = simplify_gen_binary (MINUS, mode, mode_mmax, |
c0efe3c3 | 2713 | lowpart_subreg (mode, step, |
2714 | comp_mode)); | |
f8f90b50 | 2715 | if (step_is_pow2) |
2716 | { | |
2717 | rtx t0, t1; | |
2718 | ||
2719 | /* If s is power of 2, we know that the loop is infinite if | |
2720 | a % s <= b % s and b + s overflows. */ | |
2721 | assumption = simplify_gen_relational (reverse_condition (cond), | |
2722 | SImode, mode, | |
2723 | tmp1, bound); | |
2724 | ||
2725 | t0 = simplify_gen_binary (UMOD, mode, copy_rtx (tmp0), step); | |
2726 | t1 = simplify_gen_binary (UMOD, mode, copy_rtx (tmp1), step); | |
2727 | tmp = simplify_gen_relational (cond, SImode, mode, t0, t1); | |
2728 | assumption = simplify_gen_binary (AND, SImode, assumption, tmp); | |
2729 | desc->infinite = | |
2730 | alloc_EXPR_LIST (0, assumption, desc->infinite); | |
2731 | } | |
2732 | else | |
2733 | { | |
2734 | assumption = simplify_gen_relational (cond, SImode, mode, | |
2735 | tmp1, bound); | |
2736 | desc->assumptions = | |
2737 | alloc_EXPR_LIST (0, assumption, desc->assumptions); | |
2738 | } | |
f9cce2dc | 2739 | |
2740 | tmp = simplify_gen_binary (PLUS, comp_mode, iv1.base, iv0.step); | |
c0efe3c3 | 2741 | tmp = lowpart_subreg (mode, tmp, comp_mode); |
f9cce2dc | 2742 | assumption = simplify_gen_relational (reverse_condition (cond), |
2743 | SImode, mode, tmp0, tmp); | |
2744 | ||
2745 | delta = simplify_gen_binary (PLUS, mode, tmp1, step); | |
2746 | delta = simplify_gen_binary (MINUS, mode, delta, tmp0); | |
2747 | } | |
2748 | else | |
2749 | { | |
2750 | /* Condition in shape a <= b - s * i | |
2751 | We must know that a - s does not overflow and a - s <= b and then | |
2752 | we can again compute number of iterations as (b - (a - s)) / s. */ | |
2753 | step = simplify_gen_unary (NEG, mode, iv1.step, mode); | |
c0efe3c3 | 2754 | tmp0 = lowpart_subreg (mode, iv0.base, comp_mode); |
2755 | tmp1 = lowpart_subreg (mode, iv1.base, comp_mode); | |
f9cce2dc | 2756 | |
58379c86 | 2757 | bound = simplify_gen_binary (PLUS, mode, mode_mmin, |
c0efe3c3 | 2758 | lowpart_subreg (mode, step, comp_mode)); |
f8f90b50 | 2759 | if (step_is_pow2) |
2760 | { | |
2761 | rtx t0, t1; | |
2762 | ||
2763 | /* If s is power of 2, we know that the loop is infinite if | |
2764 | a % s <= b % s and a - s overflows. */ | |
2765 | assumption = simplify_gen_relational (reverse_condition (cond), | |
2766 | SImode, mode, | |
2767 | bound, tmp0); | |
2768 | ||
2769 | t0 = simplify_gen_binary (UMOD, mode, copy_rtx (tmp0), step); | |
2770 | t1 = simplify_gen_binary (UMOD, mode, copy_rtx (tmp1), step); | |
2771 | tmp = simplify_gen_relational (cond, SImode, mode, t0, t1); | |
2772 | assumption = simplify_gen_binary (AND, SImode, assumption, tmp); | |
2773 | desc->infinite = | |
2774 | alloc_EXPR_LIST (0, assumption, desc->infinite); | |
2775 | } | |
2776 | else | |
2777 | { | |
2778 | assumption = simplify_gen_relational (cond, SImode, mode, | |
2779 | bound, tmp0); | |
2780 | desc->assumptions = | |
2781 | alloc_EXPR_LIST (0, assumption, desc->assumptions); | |
2782 | } | |
f9cce2dc | 2783 | |
2784 | tmp = simplify_gen_binary (PLUS, comp_mode, iv0.base, iv1.step); | |
c0efe3c3 | 2785 | tmp = lowpart_subreg (mode, tmp, comp_mode); |
f9cce2dc | 2786 | assumption = simplify_gen_relational (reverse_condition (cond), |
2787 | SImode, mode, | |
2788 | tmp, tmp1); | |
2789 | delta = simplify_gen_binary (MINUS, mode, tmp0, step); | |
2790 | delta = simplify_gen_binary (MINUS, mode, tmp1, delta); | |
2791 | } | |
2792 | if (assumption == const_true_rtx) | |
f30c7901 | 2793 | goto zero_iter_simplify; |
f9cce2dc | 2794 | else if (assumption != const0_rtx) |
2795 | desc->noloop_assumptions = | |
2796 | alloc_EXPR_LIST (0, assumption, desc->noloop_assumptions); | |
2797 | delta = simplify_gen_binary (UDIV, mode, delta, step); | |
2798 | desc->niter_expr = delta; | |
2799 | } | |
2800 | ||
1e8e4a1d | 2801 | old_niter = desc->niter_expr; |
2802 | ||
f9cce2dc | 2803 | simplify_using_initial_values (loop, AND, &desc->assumptions); |
2804 | if (desc->assumptions | |
2805 | && XEXP (desc->assumptions, 0) == const0_rtx) | |
2806 | goto fail; | |
2807 | simplify_using_initial_values (loop, IOR, &desc->noloop_assumptions); | |
2808 | simplify_using_initial_values (loop, IOR, &desc->infinite); | |
21f1e711 | 2809 | simplify_using_initial_values (loop, UNKNOWN, &desc->niter_expr); |
f9cce2dc | 2810 | |
2811 | /* Rerun the simplification. Consider code (created by copying loop headers) | |
2812 | ||
2813 | i = 0; | |
2814 | ||
2815 | if (0 < n) | |
2816 | { | |
2817 | do | |
2818 | { | |
2819 | i++; | |
2820 | } while (i < n); | |
2821 | } | |
2822 | ||
2823 | The first pass determines that i = 0, the second pass uses it to eliminate | |
2824 | noloop assumption. */ | |
2825 | ||
2826 | simplify_using_initial_values (loop, AND, &desc->assumptions); | |
2827 | if (desc->assumptions | |
2828 | && XEXP (desc->assumptions, 0) == const0_rtx) | |
2829 | goto fail; | |
2830 | simplify_using_initial_values (loop, IOR, &desc->noloop_assumptions); | |
2831 | simplify_using_initial_values (loop, IOR, &desc->infinite); | |
21f1e711 | 2832 | simplify_using_initial_values (loop, UNKNOWN, &desc->niter_expr); |
f9cce2dc | 2833 | |
2d49f824 | 2834 | if (desc->noloop_assumptions |
2835 | && XEXP (desc->noloop_assumptions, 0) == const_true_rtx) | |
2836 | goto zero_iter; | |
2837 | ||
971ba038 | 2838 | if (CONST_INT_P (desc->niter_expr)) |
f9cce2dc | 2839 | { |
3a4303e7 | 2840 | uint64_t val = INTVAL (desc->niter_expr); |
f9cce2dc | 2841 | |
2842 | desc->const_iter = true; | |
a9ef9877 | 2843 | desc->niter = val & GET_MODE_MASK (desc->mode); |
43780738 | 2844 | if (!desc->infinite |
2845 | && !desc->assumptions) | |
e913b5cd | 2846 | record_niter_bound (loop, desc->niter, false, true); |
f9cce2dc | 2847 | } |
1e8e4a1d | 2848 | else |
2849 | { | |
8fb72e03 | 2850 | max = determine_max_iter (loop, desc, old_niter); |
9ce07db4 | 2851 | if (!max) |
2852 | goto zero_iter_simplify; | |
43780738 | 2853 | if (!desc->infinite |
2854 | && !desc->assumptions) | |
e913b5cd | 2855 | record_niter_bound (loop, max, false, true); |
1e8e4a1d | 2856 | |
2857 | /* simplify_using_initial_values does a copy propagation on the registers | |
2858 | in the expression for the number of iterations. This prolongs life | |
2859 | ranges of registers and increases register pressure, and usually | |
2860 | brings no gain (and if it happens to do, the cse pass will take care | |
2861 | of it anyway). So prevent this behavior, unless it enabled us to | |
2862 | derive that the number of iterations is a constant. */ | |
2863 | desc->niter_expr = old_niter; | |
2864 | } | |
f9cce2dc | 2865 | |
2866 | return; | |
2867 | ||
f30c7901 | 2868 | zero_iter_simplify: |
2869 | /* Simplify the assumptions. */ | |
2870 | simplify_using_initial_values (loop, AND, &desc->assumptions); | |
2871 | if (desc->assumptions | |
2872 | && XEXP (desc->assumptions, 0) == const0_rtx) | |
2873 | goto fail; | |
2874 | simplify_using_initial_values (loop, IOR, &desc->infinite); | |
f9cce2dc | 2875 | |
f30c7901 | 2876 | /* Fallthru. */ |
f9cce2dc | 2877 | zero_iter: |
2878 | desc->const_iter = true; | |
2879 | desc->niter = 0; | |
e913b5cd | 2880 | record_niter_bound (loop, 0, true, true); |
f30c7901 | 2881 | desc->noloop_assumptions = NULL_RTX; |
f9cce2dc | 2882 | desc->niter_expr = const0_rtx; |
2883 | return; | |
f30c7901 | 2884 | |
2885 | fail: | |
2886 | desc->simple_p = false; | |
2887 | return; | |
f9cce2dc | 2888 | } |
2889 | ||
2890 | /* Checks whether E is a simple exit from LOOP and stores its description | |
9c1ccc0f | 2891 | into DESC. */ |
f9cce2dc | 2892 | |
2893 | static void | |
2894 | check_simple_exit (struct loop *loop, edge e, struct niter_desc *desc) | |
2895 | { | |
2896 | basic_block exit_bb; | |
2d650f54 | 2897 | rtx condition; |
2898 | rtx_insn *at; | |
cd665a06 | 2899 | edge ein; |
f9cce2dc | 2900 | |
2901 | exit_bb = e->src; | |
2902 | desc->simple_p = false; | |
2903 | ||
2904 | /* It must belong directly to the loop. */ | |
2905 | if (exit_bb->loop_father != loop) | |
2906 | return; | |
2907 | ||
2908 | /* It must be tested (at least) once during any iteration. */ | |
2909 | if (!dominated_by_p (CDI_DOMINATORS, loop->latch, exit_bb)) | |
2910 | return; | |
2911 | ||
2912 | /* It must end in a simple conditional jump. */ | |
2913 | if (!any_condjump_p (BB_END (exit_bb))) | |
2914 | return; | |
2915 | ||
cd665a06 | 2916 | ein = EDGE_SUCC (exit_bb, 0); |
2917 | if (ein == e) | |
2918 | ein = EDGE_SUCC (exit_bb, 1); | |
f9cce2dc | 2919 | |
2920 | desc->out_edge = e; | |
cd665a06 | 2921 | desc->in_edge = ein; |
f9cce2dc | 2922 | |
2923 | /* Test whether the condition is suitable. */ | |
cd665a06 | 2924 | if (!(condition = get_condition (BB_END (ein->src), &at, false, false))) |
f9cce2dc | 2925 | return; |
2926 | ||
cd665a06 | 2927 | if (ein->flags & EDGE_FALLTHRU) |
f9cce2dc | 2928 | { |
2929 | condition = reversed_condition (condition); | |
2930 | if (!condition) | |
2931 | return; | |
2932 | } | |
2933 | ||
2934 | /* Check that we are able to determine number of iterations and fill | |
2935 | in information about it. */ | |
2d650f54 | 2936 | iv_number_of_iterations (loop, at, condition, desc); |
f9cce2dc | 2937 | } |
2938 | ||
9c1ccc0f | 2939 | /* Finds a simple exit of LOOP and stores its description into DESC. */ |
f9cce2dc | 2940 | |
2941 | void | |
2942 | find_simple_exit (struct loop *loop, struct niter_desc *desc) | |
2943 | { | |
2944 | unsigned i; | |
2945 | basic_block *body; | |
2946 | edge e; | |
2947 | struct niter_desc act; | |
2948 | bool any = false; | |
cd665a06 | 2949 | edge_iterator ei; |
f9cce2dc | 2950 | |
2951 | desc->simple_p = false; | |
2952 | body = get_loop_body (loop); | |
2953 | ||
2954 | for (i = 0; i < loop->num_nodes; i++) | |
2955 | { | |
cd665a06 | 2956 | FOR_EACH_EDGE (e, ei, body[i]->succs) |
f9cce2dc | 2957 | { |
2958 | if (flow_bb_inside_loop_p (loop, e->dest)) | |
2959 | continue; | |
48e1416a | 2960 | |
f9cce2dc | 2961 | check_simple_exit (loop, e, &act); |
2962 | if (!act.simple_p) | |
2963 | continue; | |
2964 | ||
f9cce2dc | 2965 | if (!any) |
2966 | any = true; | |
f30c7901 | 2967 | else |
2968 | { | |
2969 | /* Prefer constant iterations; the less the better. */ | |
2970 | if (!act.const_iter | |
2971 | || (desc->const_iter && act.niter >= desc->niter)) | |
2972 | continue; | |
2973 | ||
2974 | /* Also if the actual exit may be infinite, while the old one | |
2975 | not, prefer the old one. */ | |
2976 | if (act.infinite && !desc->infinite) | |
2977 | continue; | |
2978 | } | |
48e1416a | 2979 | |
f9cce2dc | 2980 | *desc = act; |
2981 | } | |
2982 | } | |
2983 | ||
450d042a | 2984 | if (dump_file) |
f9cce2dc | 2985 | { |
2986 | if (desc->simple_p) | |
2987 | { | |
450d042a | 2988 | fprintf (dump_file, "Loop %d is simple:\n", loop->num); |
2989 | fprintf (dump_file, " simple exit %d -> %d\n", | |
f9cce2dc | 2990 | desc->out_edge->src->index, |
2991 | desc->out_edge->dest->index); | |
2992 | if (desc->assumptions) | |
2993 | { | |
450d042a | 2994 | fprintf (dump_file, " assumptions: "); |
2995 | print_rtl (dump_file, desc->assumptions); | |
2996 | fprintf (dump_file, "\n"); | |
f9cce2dc | 2997 | } |
2998 | if (desc->noloop_assumptions) | |
2999 | { | |
450d042a | 3000 | fprintf (dump_file, " does not roll if: "); |
3001 | print_rtl (dump_file, desc->noloop_assumptions); | |
3002 | fprintf (dump_file, "\n"); | |
f9cce2dc | 3003 | } |
3004 | if (desc->infinite) | |
3005 | { | |
450d042a | 3006 | fprintf (dump_file, " infinite if: "); |
3007 | print_rtl (dump_file, desc->infinite); | |
3008 | fprintf (dump_file, "\n"); | |
f9cce2dc | 3009 | } |
3010 | ||
450d042a | 3011 | fprintf (dump_file, " number of iterations: "); |
3012 | print_rtl (dump_file, desc->niter_expr); | |
3013 | fprintf (dump_file, "\n"); | |
f9cce2dc | 3014 | |
a9ef9877 | 3015 | fprintf (dump_file, " upper bound: %li\n", |
4e948f5a | 3016 | (long)get_max_loop_iterations_int (loop)); |
a9ef9877 | 3017 | fprintf (dump_file, " realistic bound: %li\n", |
4e948f5a | 3018 | (long)get_estimated_loop_iterations_int (loop)); |
f9cce2dc | 3019 | } |
3020 | else | |
450d042a | 3021 | fprintf (dump_file, "Loop %d is not simple.\n", loop->num); |
f9cce2dc | 3022 | } |
3023 | ||
3024 | free (body); | |
3025 | } | |
3026 | ||
3027 | /* Creates a simple loop description of LOOP if it was not computed | |
3028 | already. */ | |
3029 | ||
3030 | struct niter_desc * | |
3031 | get_simple_loop_desc (struct loop *loop) | |
3032 | { | |
3033 | struct niter_desc *desc = simple_loop_desc (loop); | |
3034 | ||
3035 | if (desc) | |
3036 | return desc; | |
3037 | ||
242753ba | 3038 | /* At least desc->infinite is not always initialized by |
3039 | find_simple_loop_exit. */ | |
25a27413 | 3040 | desc = ggc_cleared_alloc<niter_desc> (); |
f9cce2dc | 3041 | iv_analysis_loop_init (loop); |
3042 | find_simple_exit (loop, desc); | |
427286b3 | 3043 | loop->simple_loop_desc = desc; |
f9cce2dc | 3044 | |
7e3cc681 | 3045 | if (desc->simple_p && (desc->assumptions || desc->infinite)) |
3046 | { | |
48e1416a | 3047 | const char *wording; |
7e3cc681 | 3048 | |
48e1416a | 3049 | /* Assume that no overflow happens and that the loop is finite. |
7e3cc681 | 3050 | We already warned at the tree level if we ran optimizations there. */ |
3051 | if (!flag_tree_loop_optimize && warn_unsafe_loop_optimizations) | |
3052 | { | |
3053 | if (desc->infinite) | |
3054 | { | |
48e1416a | 3055 | wording = |
7e3cc681 | 3056 | flag_unsafe_loop_optimizations |
3057 | ? N_("assuming that the loop is not infinite") | |
3058 | : N_("cannot optimize possibly infinite loops"); | |
3059 | warning (OPT_Wunsafe_loop_optimizations, "%s", | |
3060 | gettext (wording)); | |
3061 | } | |
3062 | if (desc->assumptions) | |
3063 | { | |
48e1416a | 3064 | wording = |
7e3cc681 | 3065 | flag_unsafe_loop_optimizations |
3066 | ? N_("assuming that the loop counter does not overflow") | |
3067 | : N_("cannot optimize loop, the loop counter may overflow"); | |
3068 | warning (OPT_Wunsafe_loop_optimizations, "%s", | |
3069 | gettext (wording)); | |
3070 | } | |
3071 | } | |
3072 | ||
3073 | if (flag_unsafe_loop_optimizations) | |
3074 | { | |
3075 | desc->assumptions = NULL_RTX; | |
3076 | desc->infinite = NULL_RTX; | |
3077 | } | |
3078 | } | |
3079 | ||
f9cce2dc | 3080 | return desc; |
3081 | } | |
3082 | ||
3083 | /* Releases simple loop description for LOOP. */ | |
3084 | ||
3085 | void | |
3086 | free_simple_loop_desc (struct loop *loop) | |
3087 | { | |
3088 | struct niter_desc *desc = simple_loop_desc (loop); | |
3089 | ||
3090 | if (!desc) | |
3091 | return; | |
3092 | ||
427286b3 | 3093 | ggc_free (desc); |
3094 | loop->simple_loop_desc = NULL; | |
f9cce2dc | 3095 | } |