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f9cce2dc | 1 | /* Rtl-level induction variable analysis. |
92468061 | 2 | Copyright (C) 2004, 2005, 2006, 2007, 2008, 2009, 2010 |
cfaf579d | 3 | Free Software Foundation, Inc. |
48e1416a | 4 | |
f9cce2dc | 5 | This file is part of GCC. |
48e1416a | 6 | |
f9cce2dc | 7 | GCC is free software; you can redistribute it and/or modify it |
8 | under the terms of the GNU General Public License as published by the | |
8c4c00c1 | 9 | Free Software Foundation; either version 3, or (at your option) any |
f9cce2dc | 10 | later version. |
48e1416a | 11 | |
f9cce2dc | 12 | GCC is distributed in the hope that it will be useful, but WITHOUT |
13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
48e1416a | 16 | |
f9cce2dc | 17 | You should have received a copy of the GNU General Public License |
8c4c00c1 | 18 | along with GCC; see the file COPYING3. If not see |
19 | <http://www.gnu.org/licenses/>. */ | |
f9cce2dc | 20 | |
3f37d465 | 21 | /* This is a simple analysis of induction variables of the loop. The major use |
22 | is for determining the number of iterations of a loop for loop unrolling, | |
23 | doloop optimization and branch prediction. The iv information is computed | |
24 | on demand. | |
25 | ||
2e49e3bc | 26 | Induction variables are analyzed by walking the use-def chains. When |
27 | a basic induction variable (biv) is found, it is cached in the bivs | |
28 | hash table. When register is proved to be a biv, its description | |
29 | is stored to DF_REF_DATA of the def reference. | |
3f37d465 | 30 | |
31 | The analysis works always with one loop -- you must call | |
32 | iv_analysis_loop_init (loop) for it. All the other functions then work with | |
33 | this loop. When you need to work with another loop, just call | |
34 | iv_analysis_loop_init for it. When you no longer need iv analysis, call | |
35 | iv_analysis_done () to clean up the memory. | |
36 | ||
37 | The available functions are: | |
48e1416a | 38 | |
3f37d465 | 39 | iv_analyze (insn, reg, iv): Stores the description of the induction variable |
40 | corresponding to the use of register REG in INSN to IV. Returns true if | |
41 | REG is an induction variable in INSN. false otherwise. | |
42 | If use of REG is not found in INSN, following insns are scanned (so that | |
43 | we may call this function on insn returned by get_condition). | |
44 | iv_analyze_result (insn, def, iv): Stores to IV the description of the iv | |
45 | corresponding to DEF, which is a register defined in INSN. | |
46 | iv_analyze_expr (insn, rhs, mode, iv): Stores to IV the description of iv | |
47 | corresponding to expression EXPR evaluated at INSN. All registers used bu | |
48 | EXPR must also be used in INSN. | |
3072d30e | 49 | */ |
f9cce2dc | 50 | |
51 | #include "config.h" | |
52 | #include "system.h" | |
53 | #include "coretypes.h" | |
54 | #include "tm.h" | |
55 | #include "rtl.h" | |
56 | #include "hard-reg-set.h" | |
42fe97ed | 57 | #include "obstack.h" |
f9cce2dc | 58 | #include "basic-block.h" |
59 | #include "cfgloop.h" | |
60 | #include "expr.h" | |
7e3cc681 | 61 | #include "intl.h" |
f9cce2dc | 62 | #include "output.h" |
0b205f4c | 63 | #include "diagnostic-core.h" |
3f37d465 | 64 | #include "df.h" |
65 | #include "hashtab.h" | |
f9cce2dc | 66 | |
3f37d465 | 67 | /* Possible return values of iv_get_reaching_def. */ |
f9cce2dc | 68 | |
3f37d465 | 69 | enum iv_grd_result |
f9cce2dc | 70 | { |
3f37d465 | 71 | /* More than one reaching def, or reaching def that does not |
72 | dominate the use. */ | |
73 | GRD_INVALID, | |
f9cce2dc | 74 | |
3f37d465 | 75 | /* The use is trivial invariant of the loop, i.e. is not changed |
76 | inside the loop. */ | |
77 | GRD_INVARIANT, | |
f9cce2dc | 78 | |
3f37d465 | 79 | /* The use is reached by initial value and a value from the |
80 | previous iteration. */ | |
81 | GRD_MAYBE_BIV, | |
82 | ||
83 | /* The use has single dominating def. */ | |
84 | GRD_SINGLE_DOM | |
85 | }; | |
86 | ||
87 | /* Information about a biv. */ | |
88 | ||
89 | struct biv_entry | |
90 | { | |
91 | unsigned regno; /* The register of the biv. */ | |
92 | struct rtx_iv iv; /* Value of the biv. */ | |
f9cce2dc | 93 | }; |
94 | ||
3072d30e | 95 | static bool clean_slate = true; |
96 | ||
97 | static unsigned int iv_ref_table_size = 0; | |
98 | ||
99 | /* Table of rtx_ivs indexed by the df_ref uid field. */ | |
100 | static struct rtx_iv ** iv_ref_table; | |
101 | ||
3f37d465 | 102 | /* Induction variable stored at the reference. */ |
3072d30e | 103 | #define DF_REF_IV(REF) iv_ref_table[DF_REF_ID(REF)] |
104 | #define DF_REF_IV_SET(REF, IV) iv_ref_table[DF_REF_ID(REF)] = (IV) | |
f9cce2dc | 105 | |
3f37d465 | 106 | /* The current loop. */ |
f9cce2dc | 107 | |
3f37d465 | 108 | static struct loop *current_loop; |
f9cce2dc | 109 | |
3f37d465 | 110 | /* Bivs of the current loop. */ |
f9cce2dc | 111 | |
3f37d465 | 112 | static htab_t bivs; |
f9cce2dc | 113 | |
3f37d465 | 114 | static bool iv_analyze_op (rtx, rtx, struct rtx_iv *); |
f9cce2dc | 115 | |
116 | /* Dumps information about IV to FILE. */ | |
117 | ||
118 | extern void dump_iv_info (FILE *, struct rtx_iv *); | |
119 | void | |
120 | dump_iv_info (FILE *file, struct rtx_iv *iv) | |
121 | { | |
122 | if (!iv->base) | |
123 | { | |
124 | fprintf (file, "not simple"); | |
125 | return; | |
126 | } | |
127 | ||
bf9fa951 | 128 | if (iv->step == const0_rtx |
129 | && !iv->first_special) | |
130 | fprintf (file, "invariant "); | |
f9cce2dc | 131 | |
132 | print_rtl (file, iv->base); | |
bf9fa951 | 133 | if (iv->step != const0_rtx) |
134 | { | |
135 | fprintf (file, " + "); | |
136 | print_rtl (file, iv->step); | |
137 | fprintf (file, " * iteration"); | |
138 | } | |
f9cce2dc | 139 | fprintf (file, " (in %s)", GET_MODE_NAME (iv->mode)); |
140 | ||
141 | if (iv->mode != iv->extend_mode) | |
142 | fprintf (file, " %s to %s", | |
143 | rtx_name[iv->extend], | |
144 | GET_MODE_NAME (iv->extend_mode)); | |
145 | ||
146 | if (iv->mult != const1_rtx) | |
147 | { | |
148 | fprintf (file, " * "); | |
149 | print_rtl (file, iv->mult); | |
150 | } | |
151 | if (iv->delta != const0_rtx) | |
152 | { | |
153 | fprintf (file, " + "); | |
154 | print_rtl (file, iv->delta); | |
155 | } | |
156 | if (iv->first_special) | |
157 | fprintf (file, " (first special)"); | |
158 | } | |
159 | ||
c0efe3c3 | 160 | /* Generates a subreg to get the least significant part of EXPR (in mode |
161 | INNER_MODE) to OUTER_MODE. */ | |
f9cce2dc | 162 | |
c0efe3c3 | 163 | rtx |
164 | lowpart_subreg (enum machine_mode outer_mode, rtx expr, | |
165 | enum machine_mode inner_mode) | |
f9cce2dc | 166 | { |
c0efe3c3 | 167 | return simplify_gen_subreg (outer_mode, expr, inner_mode, |
168 | subreg_lowpart_offset (outer_mode, inner_mode)); | |
f9cce2dc | 169 | } |
170 | ||
48e1416a | 171 | static void |
3072d30e | 172 | check_iv_ref_table_size (void) |
173 | { | |
174 | if (iv_ref_table_size < DF_DEFS_TABLE_SIZE()) | |
175 | { | |
176 | unsigned int new_size = DF_DEFS_TABLE_SIZE () + (DF_DEFS_TABLE_SIZE () / 4); | |
4077bf7a | 177 | iv_ref_table = XRESIZEVEC (struct rtx_iv *, iv_ref_table, new_size); |
48e1416a | 178 | memset (&iv_ref_table[iv_ref_table_size], 0, |
3072d30e | 179 | (new_size - iv_ref_table_size) * sizeof (struct rtx_iv *)); |
180 | iv_ref_table_size = new_size; | |
181 | } | |
182 | } | |
183 | ||
184 | ||
f9cce2dc | 185 | /* Checks whether REG is a well-behaved register. */ |
186 | ||
187 | static bool | |
188 | simple_reg_p (rtx reg) | |
189 | { | |
190 | unsigned r; | |
191 | ||
192 | if (GET_CODE (reg) == SUBREG) | |
193 | { | |
194 | if (!subreg_lowpart_p (reg)) | |
195 | return false; | |
196 | reg = SUBREG_REG (reg); | |
197 | } | |
198 | ||
199 | if (!REG_P (reg)) | |
200 | return false; | |
201 | ||
202 | r = REGNO (reg); | |
203 | if (HARD_REGISTER_NUM_P (r)) | |
204 | return false; | |
205 | ||
206 | if (GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT) | |
207 | return false; | |
208 | ||
f9cce2dc | 209 | return true; |
210 | } | |
211 | ||
3f37d465 | 212 | /* Clears the information about ivs stored in df. */ |
f9cce2dc | 213 | |
3f37d465 | 214 | static void |
215 | clear_iv_info (void) | |
f9cce2dc | 216 | { |
3072d30e | 217 | unsigned i, n_defs = DF_DEFS_TABLE_SIZE (); |
3f37d465 | 218 | struct rtx_iv *iv; |
f9cce2dc | 219 | |
3072d30e | 220 | check_iv_ref_table_size (); |
3f37d465 | 221 | for (i = 0; i < n_defs; i++) |
f9cce2dc | 222 | { |
3072d30e | 223 | iv = iv_ref_table[i]; |
224 | if (iv) | |
225 | { | |
226 | free (iv); | |
227 | iv_ref_table[i] = NULL; | |
228 | } | |
f9cce2dc | 229 | } |
f9cce2dc | 230 | |
3f37d465 | 231 | htab_empty (bivs); |
f9cce2dc | 232 | } |
233 | ||
3f37d465 | 234 | /* Returns hash value for biv B. */ |
f9cce2dc | 235 | |
3f37d465 | 236 | static hashval_t |
237 | biv_hash (const void *b) | |
f9cce2dc | 238 | { |
3f37d465 | 239 | return ((const struct biv_entry *) b)->regno; |
f9cce2dc | 240 | } |
241 | ||
3f37d465 | 242 | /* Compares biv B and register R. */ |
f9cce2dc | 243 | |
3f37d465 | 244 | static int |
245 | biv_eq (const void *b, const void *r) | |
f9cce2dc | 246 | { |
dd9b9fc5 | 247 | return ((const struct biv_entry *) b)->regno == REGNO ((const_rtx) r); |
f9cce2dc | 248 | } |
249 | ||
250 | /* Prepare the data for an induction variable analysis of a LOOP. */ | |
251 | ||
252 | void | |
253 | iv_analysis_loop_init (struct loop *loop) | |
254 | { | |
3f37d465 | 255 | basic_block *body = get_loop_body_in_dom_order (loop), bb; |
256 | bitmap blocks = BITMAP_ALLOC (NULL); | |
257 | unsigned i; | |
f9cce2dc | 258 | |
3f37d465 | 259 | current_loop = loop; |
f9cce2dc | 260 | |
3f37d465 | 261 | /* Clear the information from the analysis of the previous loop. */ |
3072d30e | 262 | if (clean_slate) |
b818d1a9 | 263 | { |
3072d30e | 264 | df_set_flags (DF_EQ_NOTES + DF_DEFER_INSN_RESCAN); |
b818d1a9 | 265 | bivs = htab_create (10, biv_hash, biv_eq, free); |
3072d30e | 266 | clean_slate = false; |
b818d1a9 | 267 | } |
268 | else | |
269 | clear_iv_info (); | |
f9cce2dc | 270 | |
3f37d465 | 271 | for (i = 0; i < loop->num_nodes; i++) |
f9cce2dc | 272 | { |
3f37d465 | 273 | bb = body[i]; |
274 | bitmap_set_bit (blocks, bb->index); | |
f9cce2dc | 275 | } |
3072d30e | 276 | /* Get rid of the ud chains before processing the rescans. Then add |
277 | the problem back. */ | |
278 | df_remove_problem (df_chain); | |
279 | df_process_deferred_rescans (); | |
280 | df_chain_add_problem (DF_UD_CHAIN); | |
c56a6318 | 281 | df_note_add_problem (); |
3072d30e | 282 | df_set_blocks (blocks); |
283 | df_analyze (); | |
284 | if (dump_file) | |
774f8797 | 285 | df_dump_region (dump_file); |
3072d30e | 286 | |
287 | check_iv_ref_table_size (); | |
3f37d465 | 288 | BITMAP_FREE (blocks); |
f9cce2dc | 289 | free (body); |
290 | } | |
291 | ||
3f37d465 | 292 | /* Finds the definition of REG that dominates loop latch and stores |
293 | it to DEF. Returns false if there is not a single definition | |
294 | dominating the latch. If REG has no definition in loop, DEF | |
295 | is set to NULL and true is returned. */ | |
f9cce2dc | 296 | |
3f37d465 | 297 | static bool |
ed6e85ae | 298 | latch_dominating_def (rtx reg, df_ref *def) |
f9cce2dc | 299 | { |
ed6e85ae | 300 | df_ref single_rd = NULL, adef; |
3f37d465 | 301 | unsigned regno = REGNO (reg); |
3072d30e | 302 | struct df_rd_bb_info *bb_info = DF_RD_BB_INFO (current_loop->latch); |
f9cce2dc | 303 | |
ed6e85ae | 304 | for (adef = DF_REG_DEF_CHAIN (regno); adef; adef = DF_REF_NEXT_REG (adef)) |
f9cce2dc | 305 | { |
ed6e85ae | 306 | if (!bitmap_bit_p (df->blocks_to_analyze, DF_REF_BBNO (adef)) |
f53d14b1 | 307 | || !bitmap_bit_p (&bb_info->out, DF_REF_ID (adef))) |
3f37d465 | 308 | continue; |
309 | ||
310 | /* More than one reaching definition. */ | |
311 | if (single_rd) | |
312 | return false; | |
313 | ||
314 | if (!just_once_each_iteration_p (current_loop, DF_REF_BB (adef))) | |
315 | return false; | |
316 | ||
317 | single_rd = adef; | |
f9cce2dc | 318 | } |
f9cce2dc | 319 | |
3f37d465 | 320 | *def = single_rd; |
321 | return true; | |
322 | } | |
f9cce2dc | 323 | |
3f37d465 | 324 | /* Gets definition of REG reaching its use in INSN and stores it to DEF. */ |
f9cce2dc | 325 | |
3f37d465 | 326 | static enum iv_grd_result |
ed6e85ae | 327 | iv_get_reaching_def (rtx insn, rtx reg, df_ref *def) |
3f37d465 | 328 | { |
ed6e85ae | 329 | df_ref use, adef; |
3f37d465 | 330 | basic_block def_bb, use_bb; |
331 | rtx def_insn; | |
332 | bool dom_p; | |
48e1416a | 333 | |
3f37d465 | 334 | *def = NULL; |
335 | if (!simple_reg_p (reg)) | |
336 | return GRD_INVALID; | |
337 | if (GET_CODE (reg) == SUBREG) | |
338 | reg = SUBREG_REG (reg); | |
339 | gcc_assert (REG_P (reg)); | |
f9cce2dc | 340 | |
3072d30e | 341 | use = df_find_use (insn, reg); |
3f37d465 | 342 | gcc_assert (use != NULL); |
f9cce2dc | 343 | |
3f37d465 | 344 | if (!DF_REF_CHAIN (use)) |
345 | return GRD_INVARIANT; | |
f9cce2dc | 346 | |
3f37d465 | 347 | /* More than one reaching def. */ |
348 | if (DF_REF_CHAIN (use)->next) | |
349 | return GRD_INVALID; | |
f9cce2dc | 350 | |
3f37d465 | 351 | adef = DF_REF_CHAIN (use)->ref; |
605dec4e | 352 | |
353 | /* We do not handle setting only part of the register. */ | |
ed6e85ae | 354 | if (DF_REF_FLAGS (adef) & DF_REF_READ_WRITE) |
605dec4e | 355 | return GRD_INVALID; |
356 | ||
3f37d465 | 357 | def_insn = DF_REF_INSN (adef); |
358 | def_bb = DF_REF_BB (adef); | |
359 | use_bb = BLOCK_FOR_INSN (insn); | |
f9cce2dc | 360 | |
3f37d465 | 361 | if (use_bb == def_bb) |
3072d30e | 362 | dom_p = (DF_INSN_LUID (def_insn) < DF_INSN_LUID (insn)); |
3f37d465 | 363 | else |
364 | dom_p = dominated_by_p (CDI_DOMINATORS, use_bb, def_bb); | |
f9cce2dc | 365 | |
3f37d465 | 366 | if (dom_p) |
367 | { | |
368 | *def = adef; | |
369 | return GRD_SINGLE_DOM; | |
f9cce2dc | 370 | } |
3f37d465 | 371 | |
372 | /* The definition does not dominate the use. This is still OK if | |
373 | this may be a use of a biv, i.e. if the def_bb dominates loop | |
374 | latch. */ | |
375 | if (just_once_each_iteration_p (current_loop, def_bb)) | |
376 | return GRD_MAYBE_BIV; | |
377 | ||
378 | return GRD_INVALID; | |
f9cce2dc | 379 | } |
380 | ||
381 | /* Sets IV to invariant CST in MODE. Always returns true (just for | |
382 | consistency with other iv manipulation functions that may fail). */ | |
383 | ||
384 | static bool | |
385 | iv_constant (struct rtx_iv *iv, rtx cst, enum machine_mode mode) | |
386 | { | |
387 | if (mode == VOIDmode) | |
388 | mode = GET_MODE (cst); | |
389 | ||
f9cce2dc | 390 | iv->mode = mode; |
391 | iv->base = cst; | |
392 | iv->step = const0_rtx; | |
393 | iv->first_special = false; | |
21f1e711 | 394 | iv->extend = UNKNOWN; |
f9cce2dc | 395 | iv->extend_mode = iv->mode; |
396 | iv->delta = const0_rtx; | |
397 | iv->mult = const1_rtx; | |
398 | ||
399 | return true; | |
400 | } | |
401 | ||
402 | /* Evaluates application of subreg to MODE on IV. */ | |
403 | ||
404 | static bool | |
405 | iv_subreg (struct rtx_iv *iv, enum machine_mode mode) | |
406 | { | |
bf9fa951 | 407 | /* If iv is invariant, just calculate the new value. */ |
408 | if (iv->step == const0_rtx | |
409 | && !iv->first_special) | |
410 | { | |
411 | rtx val = get_iv_value (iv, const0_rtx); | |
c0efe3c3 | 412 | val = lowpart_subreg (mode, val, iv->extend_mode); |
bf9fa951 | 413 | |
414 | iv->base = val; | |
21f1e711 | 415 | iv->extend = UNKNOWN; |
bf9fa951 | 416 | iv->mode = iv->extend_mode = mode; |
417 | iv->delta = const0_rtx; | |
418 | iv->mult = const1_rtx; | |
419 | return true; | |
420 | } | |
421 | ||
f9cce2dc | 422 | if (iv->extend_mode == mode) |
423 | return true; | |
424 | ||
425 | if (GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (iv->mode)) | |
426 | return false; | |
427 | ||
21f1e711 | 428 | iv->extend = UNKNOWN; |
f9cce2dc | 429 | iv->mode = mode; |
430 | ||
431 | iv->base = simplify_gen_binary (PLUS, iv->extend_mode, iv->delta, | |
432 | simplify_gen_binary (MULT, iv->extend_mode, | |
433 | iv->base, iv->mult)); | |
434 | iv->step = simplify_gen_binary (MULT, iv->extend_mode, iv->step, iv->mult); | |
435 | iv->mult = const1_rtx; | |
436 | iv->delta = const0_rtx; | |
437 | iv->first_special = false; | |
438 | ||
439 | return true; | |
440 | } | |
441 | ||
442 | /* Evaluates application of EXTEND to MODE on IV. */ | |
443 | ||
444 | static bool | |
445 | iv_extend (struct rtx_iv *iv, enum rtx_code extend, enum machine_mode mode) | |
446 | { | |
bf9fa951 | 447 | /* If iv is invariant, just calculate the new value. */ |
448 | if (iv->step == const0_rtx | |
449 | && !iv->first_special) | |
450 | { | |
451 | rtx val = get_iv_value (iv, const0_rtx); | |
452 | val = simplify_gen_unary (extend, mode, val, iv->extend_mode); | |
453 | ||
454 | iv->base = val; | |
21f1e711 | 455 | iv->extend = UNKNOWN; |
bf9fa951 | 456 | iv->mode = iv->extend_mode = mode; |
457 | iv->delta = const0_rtx; | |
458 | iv->mult = const1_rtx; | |
459 | return true; | |
460 | } | |
461 | ||
f9cce2dc | 462 | if (mode != iv->extend_mode) |
463 | return false; | |
464 | ||
21f1e711 | 465 | if (iv->extend != UNKNOWN |
f9cce2dc | 466 | && iv->extend != extend) |
467 | return false; | |
468 | ||
469 | iv->extend = extend; | |
470 | ||
471 | return true; | |
472 | } | |
473 | ||
474 | /* Evaluates negation of IV. */ | |
475 | ||
476 | static bool | |
477 | iv_neg (struct rtx_iv *iv) | |
478 | { | |
21f1e711 | 479 | if (iv->extend == UNKNOWN) |
f9cce2dc | 480 | { |
481 | iv->base = simplify_gen_unary (NEG, iv->extend_mode, | |
482 | iv->base, iv->extend_mode); | |
483 | iv->step = simplify_gen_unary (NEG, iv->extend_mode, | |
484 | iv->step, iv->extend_mode); | |
485 | } | |
486 | else | |
487 | { | |
488 | iv->delta = simplify_gen_unary (NEG, iv->extend_mode, | |
489 | iv->delta, iv->extend_mode); | |
490 | iv->mult = simplify_gen_unary (NEG, iv->extend_mode, | |
491 | iv->mult, iv->extend_mode); | |
492 | } | |
493 | ||
494 | return true; | |
495 | } | |
496 | ||
497 | /* Evaluates addition or subtraction (according to OP) of IV1 to IV0. */ | |
498 | ||
499 | static bool | |
500 | iv_add (struct rtx_iv *iv0, struct rtx_iv *iv1, enum rtx_code op) | |
501 | { | |
502 | enum machine_mode mode; | |
503 | rtx arg; | |
504 | ||
aab2cf92 | 505 | /* Extend the constant to extend_mode of the other operand if necessary. */ |
21f1e711 | 506 | if (iv0->extend == UNKNOWN |
f9cce2dc | 507 | && iv0->mode == iv0->extend_mode |
508 | && iv0->step == const0_rtx | |
509 | && GET_MODE_SIZE (iv0->extend_mode) < GET_MODE_SIZE (iv1->extend_mode)) | |
510 | { | |
511 | iv0->extend_mode = iv1->extend_mode; | |
512 | iv0->base = simplify_gen_unary (ZERO_EXTEND, iv0->extend_mode, | |
513 | iv0->base, iv0->mode); | |
514 | } | |
21f1e711 | 515 | if (iv1->extend == UNKNOWN |
f9cce2dc | 516 | && iv1->mode == iv1->extend_mode |
517 | && iv1->step == const0_rtx | |
518 | && GET_MODE_SIZE (iv1->extend_mode) < GET_MODE_SIZE (iv0->extend_mode)) | |
519 | { | |
520 | iv1->extend_mode = iv0->extend_mode; | |
521 | iv1->base = simplify_gen_unary (ZERO_EXTEND, iv1->extend_mode, | |
522 | iv1->base, iv1->mode); | |
523 | } | |
524 | ||
525 | mode = iv0->extend_mode; | |
526 | if (mode != iv1->extend_mode) | |
527 | return false; | |
528 | ||
21f1e711 | 529 | if (iv0->extend == UNKNOWN && iv1->extend == UNKNOWN) |
f9cce2dc | 530 | { |
531 | if (iv0->mode != iv1->mode) | |
532 | return false; | |
533 | ||
534 | iv0->base = simplify_gen_binary (op, mode, iv0->base, iv1->base); | |
535 | iv0->step = simplify_gen_binary (op, mode, iv0->step, iv1->step); | |
536 | ||
537 | return true; | |
538 | } | |
539 | ||
540 | /* Handle addition of constant. */ | |
21f1e711 | 541 | if (iv1->extend == UNKNOWN |
f9cce2dc | 542 | && iv1->mode == mode |
543 | && iv1->step == const0_rtx) | |
544 | { | |
545 | iv0->delta = simplify_gen_binary (op, mode, iv0->delta, iv1->base); | |
546 | return true; | |
547 | } | |
548 | ||
21f1e711 | 549 | if (iv0->extend == UNKNOWN |
f9cce2dc | 550 | && iv0->mode == mode |
551 | && iv0->step == const0_rtx) | |
552 | { | |
553 | arg = iv0->base; | |
554 | *iv0 = *iv1; | |
555 | if (op == MINUS | |
556 | && !iv_neg (iv0)) | |
557 | return false; | |
558 | ||
559 | iv0->delta = simplify_gen_binary (PLUS, mode, iv0->delta, arg); | |
560 | return true; | |
561 | } | |
562 | ||
563 | return false; | |
564 | } | |
565 | ||
566 | /* Evaluates multiplication of IV by constant CST. */ | |
567 | ||
568 | static bool | |
569 | iv_mult (struct rtx_iv *iv, rtx mby) | |
570 | { | |
571 | enum machine_mode mode = iv->extend_mode; | |
572 | ||
573 | if (GET_MODE (mby) != VOIDmode | |
574 | && GET_MODE (mby) != mode) | |
575 | return false; | |
576 | ||
21f1e711 | 577 | if (iv->extend == UNKNOWN) |
f9cce2dc | 578 | { |
579 | iv->base = simplify_gen_binary (MULT, mode, iv->base, mby); | |
580 | iv->step = simplify_gen_binary (MULT, mode, iv->step, mby); | |
581 | } | |
582 | else | |
583 | { | |
584 | iv->delta = simplify_gen_binary (MULT, mode, iv->delta, mby); | |
585 | iv->mult = simplify_gen_binary (MULT, mode, iv->mult, mby); | |
586 | } | |
587 | ||
588 | return true; | |
589 | } | |
590 | ||
567c3006 | 591 | /* Evaluates shift of IV by constant CST. */ |
592 | ||
593 | static bool | |
594 | iv_shift (struct rtx_iv *iv, rtx mby) | |
595 | { | |
596 | enum machine_mode mode = iv->extend_mode; | |
597 | ||
598 | if (GET_MODE (mby) != VOIDmode | |
599 | && GET_MODE (mby) != mode) | |
600 | return false; | |
601 | ||
21f1e711 | 602 | if (iv->extend == UNKNOWN) |
567c3006 | 603 | { |
604 | iv->base = simplify_gen_binary (ASHIFT, mode, iv->base, mby); | |
605 | iv->step = simplify_gen_binary (ASHIFT, mode, iv->step, mby); | |
606 | } | |
607 | else | |
608 | { | |
609 | iv->delta = simplify_gen_binary (ASHIFT, mode, iv->delta, mby); | |
610 | iv->mult = simplify_gen_binary (ASHIFT, mode, iv->mult, mby); | |
611 | } | |
612 | ||
613 | return true; | |
614 | } | |
615 | ||
f9cce2dc | 616 | /* The recursive part of get_biv_step. Gets the value of the single value |
3f37d465 | 617 | defined by DEF wrto initial value of REG inside loop, in shape described |
f9cce2dc | 618 | at get_biv_step. */ |
619 | ||
620 | static bool | |
ed6e85ae | 621 | get_biv_step_1 (df_ref def, rtx reg, |
f9cce2dc | 622 | rtx *inner_step, enum machine_mode *inner_mode, |
623 | enum rtx_code *extend, enum machine_mode outer_mode, | |
624 | rtx *outer_step) | |
625 | { | |
a6ed3419 | 626 | rtx set, rhs, op0 = NULL_RTX, op1 = NULL_RTX; |
3f37d465 | 627 | rtx next, nextr, tmp; |
f9cce2dc | 628 | enum rtx_code code; |
3f37d465 | 629 | rtx insn = DF_REF_INSN (def); |
ed6e85ae | 630 | df_ref next_def; |
3f37d465 | 631 | enum iv_grd_result res; |
f9cce2dc | 632 | |
633 | set = single_set (insn); | |
3f37d465 | 634 | if (!set) |
635 | return false; | |
636 | ||
f9cce2dc | 637 | rhs = find_reg_equal_equiv_note (insn); |
a6629703 | 638 | if (rhs) |
639 | rhs = XEXP (rhs, 0); | |
640 | else | |
f9cce2dc | 641 | rhs = SET_SRC (set); |
f9cce2dc | 642 | |
643 | code = GET_CODE (rhs); | |
644 | switch (code) | |
645 | { | |
646 | case SUBREG: | |
647 | case REG: | |
648 | next = rhs; | |
649 | break; | |
650 | ||
651 | case PLUS: | |
652 | case MINUS: | |
653 | op0 = XEXP (rhs, 0); | |
654 | op1 = XEXP (rhs, 1); | |
655 | ||
656 | if (code == PLUS && CONSTANT_P (op0)) | |
657 | { | |
658 | tmp = op0; op0 = op1; op1 = tmp; | |
659 | } | |
660 | ||
661 | if (!simple_reg_p (op0) | |
662 | || !CONSTANT_P (op1)) | |
663 | return false; | |
664 | ||
665 | if (GET_MODE (rhs) != outer_mode) | |
666 | { | |
667 | /* ppc64 uses expressions like | |
668 | ||
669 | (set x:SI (plus:SI (subreg:SI y:DI) 1)). | |
670 | ||
671 | this is equivalent to | |
672 | ||
673 | (set x':DI (plus:DI y:DI 1)) | |
674 | (set x:SI (subreg:SI (x':DI)). */ | |
675 | if (GET_CODE (op0) != SUBREG) | |
676 | return false; | |
677 | if (GET_MODE (SUBREG_REG (op0)) != outer_mode) | |
678 | return false; | |
679 | } | |
680 | ||
681 | next = op0; | |
682 | break; | |
683 | ||
684 | case SIGN_EXTEND: | |
685 | case ZERO_EXTEND: | |
686 | if (GET_MODE (rhs) != outer_mode) | |
687 | return false; | |
688 | ||
689 | op0 = XEXP (rhs, 0); | |
690 | if (!simple_reg_p (op0)) | |
691 | return false; | |
692 | ||
693 | next = op0; | |
694 | break; | |
695 | ||
696 | default: | |
697 | return false; | |
698 | } | |
699 | ||
700 | if (GET_CODE (next) == SUBREG) | |
701 | { | |
702 | if (!subreg_lowpart_p (next)) | |
703 | return false; | |
704 | ||
705 | nextr = SUBREG_REG (next); | |
706 | if (GET_MODE (nextr) != outer_mode) | |
707 | return false; | |
708 | } | |
709 | else | |
710 | nextr = next; | |
711 | ||
3f37d465 | 712 | res = iv_get_reaching_def (insn, nextr, &next_def); |
713 | ||
714 | if (res == GRD_INVALID || res == GRD_INVARIANT) | |
f9cce2dc | 715 | return false; |
716 | ||
3f37d465 | 717 | if (res == GRD_MAYBE_BIV) |
f9cce2dc | 718 | { |
719 | if (!rtx_equal_p (nextr, reg)) | |
720 | return false; | |
721 | ||
722 | *inner_step = const0_rtx; | |
21f1e711 | 723 | *extend = UNKNOWN; |
f9cce2dc | 724 | *inner_mode = outer_mode; |
725 | *outer_step = const0_rtx; | |
726 | } | |
3f37d465 | 727 | else if (!get_biv_step_1 (next_def, reg, |
f9cce2dc | 728 | inner_step, inner_mode, extend, outer_mode, |
729 | outer_step)) | |
730 | return false; | |
731 | ||
732 | if (GET_CODE (next) == SUBREG) | |
733 | { | |
734 | enum machine_mode amode = GET_MODE (next); | |
735 | ||
736 | if (GET_MODE_SIZE (amode) > GET_MODE_SIZE (*inner_mode)) | |
737 | return false; | |
738 | ||
739 | *inner_mode = amode; | |
740 | *inner_step = simplify_gen_binary (PLUS, outer_mode, | |
741 | *inner_step, *outer_step); | |
742 | *outer_step = const0_rtx; | |
21f1e711 | 743 | *extend = UNKNOWN; |
f9cce2dc | 744 | } |
745 | ||
746 | switch (code) | |
747 | { | |
748 | case REG: | |
749 | case SUBREG: | |
750 | break; | |
751 | ||
752 | case PLUS: | |
753 | case MINUS: | |
754 | if (*inner_mode == outer_mode | |
755 | /* See comment in previous switch. */ | |
756 | || GET_MODE (rhs) != outer_mode) | |
757 | *inner_step = simplify_gen_binary (code, outer_mode, | |
758 | *inner_step, op1); | |
759 | else | |
760 | *outer_step = simplify_gen_binary (code, outer_mode, | |
761 | *outer_step, op1); | |
762 | break; | |
763 | ||
764 | case SIGN_EXTEND: | |
765 | case ZERO_EXTEND: | |
972e95af | 766 | gcc_assert (GET_MODE (op0) == *inner_mode |
767 | && *extend == UNKNOWN | |
768 | && *outer_step == const0_rtx); | |
f9cce2dc | 769 | |
770 | *extend = code; | |
771 | break; | |
772 | ||
773 | default: | |
3f37d465 | 774 | return false; |
f9cce2dc | 775 | } |
776 | ||
777 | return true; | |
778 | } | |
779 | ||
780 | /* Gets the operation on register REG inside loop, in shape | |
781 | ||
782 | OUTER_STEP + EXTEND_{OUTER_MODE} (SUBREG_{INNER_MODE} (REG + INNER_STEP)) | |
783 | ||
3f37d465 | 784 | If the operation cannot be described in this shape, return false. |
785 | LAST_DEF is the definition of REG that dominates loop latch. */ | |
f9cce2dc | 786 | |
787 | static bool | |
ed6e85ae | 788 | get_biv_step (df_ref last_def, rtx reg, rtx *inner_step, |
3f37d465 | 789 | enum machine_mode *inner_mode, enum rtx_code *extend, |
790 | enum machine_mode *outer_mode, rtx *outer_step) | |
f9cce2dc | 791 | { |
792 | *outer_mode = GET_MODE (reg); | |
793 | ||
3f37d465 | 794 | if (!get_biv_step_1 (last_def, reg, |
f9cce2dc | 795 | inner_step, inner_mode, extend, *outer_mode, |
796 | outer_step)) | |
797 | return false; | |
798 | ||
972e95af | 799 | gcc_assert ((*inner_mode == *outer_mode) != (*extend != UNKNOWN)); |
800 | gcc_assert (*inner_mode != *outer_mode || *outer_step == const0_rtx); | |
f9cce2dc | 801 | |
802 | return true; | |
803 | } | |
804 | ||
3f37d465 | 805 | /* Records information that DEF is induction variable IV. */ |
806 | ||
807 | static void | |
ed6e85ae | 808 | record_iv (df_ref def, struct rtx_iv *iv) |
3f37d465 | 809 | { |
4c36ffe6 | 810 | struct rtx_iv *recorded_iv = XNEW (struct rtx_iv); |
3f37d465 | 811 | |
812 | *recorded_iv = *iv; | |
3072d30e | 813 | check_iv_ref_table_size (); |
3f37d465 | 814 | DF_REF_IV_SET (def, recorded_iv); |
815 | } | |
816 | ||
817 | /* If DEF was already analyzed for bivness, store the description of the biv to | |
818 | IV and return true. Otherwise return false. */ | |
819 | ||
820 | static bool | |
821 | analyzed_for_bivness_p (rtx def, struct rtx_iv *iv) | |
822 | { | |
4077bf7a | 823 | struct biv_entry *biv = |
824 | (struct biv_entry *) htab_find_with_hash (bivs, def, REGNO (def)); | |
3f37d465 | 825 | |
826 | if (!biv) | |
827 | return false; | |
828 | ||
829 | *iv = biv->iv; | |
830 | return true; | |
831 | } | |
832 | ||
833 | static void | |
834 | record_biv (rtx def, struct rtx_iv *iv) | |
835 | { | |
4c36ffe6 | 836 | struct biv_entry *biv = XNEW (struct biv_entry); |
3f37d465 | 837 | void **slot = htab_find_slot_with_hash (bivs, def, REGNO (def), INSERT); |
838 | ||
839 | biv->regno = REGNO (def); | |
840 | biv->iv = *iv; | |
841 | gcc_assert (!*slot); | |
842 | *slot = biv; | |
843 | } | |
844 | ||
f9cce2dc | 845 | /* Determines whether DEF is a biv and if so, stores its description |
846 | to *IV. */ | |
847 | ||
848 | static bool | |
f08e8669 | 849 | iv_analyze_biv (rtx def, struct rtx_iv *iv) |
f9cce2dc | 850 | { |
f9cce2dc | 851 | rtx inner_step, outer_step; |
852 | enum machine_mode inner_mode, outer_mode; | |
853 | enum rtx_code extend; | |
ed6e85ae | 854 | df_ref last_def; |
f9cce2dc | 855 | |
450d042a | 856 | if (dump_file) |
f9cce2dc | 857 | { |
4133d091 | 858 | fprintf (dump_file, "Analyzing "); |
450d042a | 859 | print_rtl (dump_file, def); |
860 | fprintf (dump_file, " for bivness.\n"); | |
f9cce2dc | 861 | } |
48e1416a | 862 | |
f9cce2dc | 863 | if (!REG_P (def)) |
864 | { | |
865 | if (!CONSTANT_P (def)) | |
866 | return false; | |
867 | ||
868 | return iv_constant (iv, def, VOIDmode); | |
869 | } | |
870 | ||
3f37d465 | 871 | if (!latch_dominating_def (def, &last_def)) |
f9cce2dc | 872 | { |
450d042a | 873 | if (dump_file) |
874 | fprintf (dump_file, " not simple.\n"); | |
f9cce2dc | 875 | return false; |
876 | } | |
877 | ||
3f37d465 | 878 | if (!last_def) |
879 | return iv_constant (iv, def, VOIDmode); | |
880 | ||
881 | if (analyzed_for_bivness_p (def, iv)) | |
f9cce2dc | 882 | { |
450d042a | 883 | if (dump_file) |
884 | fprintf (dump_file, " already analysed.\n"); | |
f9cce2dc | 885 | return iv->base != NULL_RTX; |
886 | } | |
887 | ||
3f37d465 | 888 | if (!get_biv_step (last_def, def, &inner_step, &inner_mode, &extend, |
f9cce2dc | 889 | &outer_mode, &outer_step)) |
890 | { | |
891 | iv->base = NULL_RTX; | |
892 | goto end; | |
893 | } | |
894 | ||
895 | /* Loop transforms base to es (base + inner_step) + outer_step, | |
896 | where es means extend of subreg between inner_mode and outer_mode. | |
897 | The corresponding induction variable is | |
898 | ||
899 | es ((base - outer_step) + i * (inner_step + outer_step)) + outer_step */ | |
900 | ||
901 | iv->base = simplify_gen_binary (MINUS, outer_mode, def, outer_step); | |
902 | iv->step = simplify_gen_binary (PLUS, outer_mode, inner_step, outer_step); | |
903 | iv->mode = inner_mode; | |
904 | iv->extend_mode = outer_mode; | |
905 | iv->extend = extend; | |
906 | iv->mult = const1_rtx; | |
907 | iv->delta = outer_step; | |
908 | iv->first_special = inner_mode != outer_mode; | |
909 | ||
450d042a | 910 | end: |
911 | if (dump_file) | |
f9cce2dc | 912 | { |
450d042a | 913 | fprintf (dump_file, " "); |
914 | dump_iv_info (dump_file, iv); | |
915 | fprintf (dump_file, "\n"); | |
f9cce2dc | 916 | } |
917 | ||
3f37d465 | 918 | record_biv (def, iv); |
f9cce2dc | 919 | return iv->base != NULL_RTX; |
920 | } | |
921 | ||
48e1416a | 922 | /* Analyzes expression RHS used at INSN and stores the result to *IV. |
3f37d465 | 923 | The mode of the induction variable is MODE. */ |
f9cce2dc | 924 | |
3f37d465 | 925 | bool |
926 | iv_analyze_expr (rtx insn, rtx rhs, enum machine_mode mode, struct rtx_iv *iv) | |
f9cce2dc | 927 | { |
3f37d465 | 928 | rtx mby = NULL_RTX, tmp; |
929 | rtx op0 = NULL_RTX, op1 = NULL_RTX; | |
930 | struct rtx_iv iv0, iv1; | |
931 | enum rtx_code code = GET_CODE (rhs); | |
932 | enum machine_mode omode = mode; | |
f9cce2dc | 933 | |
3f37d465 | 934 | iv->mode = VOIDmode; |
935 | iv->base = NULL_RTX; | |
936 | iv->step = NULL_RTX; | |
f9cce2dc | 937 | |
3f37d465 | 938 | gcc_assert (GET_MODE (rhs) == mode || GET_MODE (rhs) == VOIDmode); |
f9cce2dc | 939 | |
3f37d465 | 940 | if (CONSTANT_P (rhs) |
941 | || REG_P (rhs) | |
942 | || code == SUBREG) | |
f9cce2dc | 943 | { |
3f37d465 | 944 | if (!iv_analyze_op (insn, rhs, iv)) |
945 | return false; | |
48e1416a | 946 | |
3f37d465 | 947 | if (iv->mode == VOIDmode) |
f9cce2dc | 948 | { |
3f37d465 | 949 | iv->mode = mode; |
950 | iv->extend_mode = mode; | |
f9cce2dc | 951 | } |
3f37d465 | 952 | |
953 | return true; | |
f9cce2dc | 954 | } |
955 | ||
3f37d465 | 956 | switch (code) |
f9cce2dc | 957 | { |
3f37d465 | 958 | case REG: |
959 | op0 = rhs; | |
960 | break; | |
f9cce2dc | 961 | |
3f37d465 | 962 | case SIGN_EXTEND: |
963 | case ZERO_EXTEND: | |
964 | case NEG: | |
965 | op0 = XEXP (rhs, 0); | |
966 | omode = GET_MODE (op0); | |
967 | break; | |
968 | ||
969 | case PLUS: | |
970 | case MINUS: | |
971 | op0 = XEXP (rhs, 0); | |
972 | op1 = XEXP (rhs, 1); | |
973 | break; | |
974 | ||
975 | case MULT: | |
976 | op0 = XEXP (rhs, 0); | |
977 | mby = XEXP (rhs, 1); | |
978 | if (!CONSTANT_P (mby)) | |
f9cce2dc | 979 | { |
3f37d465 | 980 | tmp = op0; |
981 | op0 = mby; | |
982 | mby = tmp; | |
f9cce2dc | 983 | } |
3f37d465 | 984 | if (!CONSTANT_P (mby)) |
985 | return false; | |
986 | break; | |
f9cce2dc | 987 | |
3f37d465 | 988 | case ASHIFT: |
989 | op0 = XEXP (rhs, 0); | |
990 | mby = XEXP (rhs, 1); | |
991 | if (!CONSTANT_P (mby)) | |
992 | return false; | |
993 | break; | |
994 | ||
995 | default: | |
f9cce2dc | 996 | return false; |
997 | } | |
998 | ||
3f37d465 | 999 | if (op0 |
1000 | && !iv_analyze_expr (insn, op0, omode, &iv0)) | |
1001 | return false; | |
f9cce2dc | 1002 | |
3f37d465 | 1003 | if (op1 |
1004 | && !iv_analyze_expr (insn, op1, omode, &iv1)) | |
f9cce2dc | 1005 | return false; |
1006 | ||
3f37d465 | 1007 | switch (code) |
f9cce2dc | 1008 | { |
3f37d465 | 1009 | case SIGN_EXTEND: |
1010 | case ZERO_EXTEND: | |
1011 | if (!iv_extend (&iv0, code, mode)) | |
1012 | return false; | |
1013 | break; | |
1014 | ||
1015 | case NEG: | |
1016 | if (!iv_neg (&iv0)) | |
f9cce2dc | 1017 | return false; |
3f37d465 | 1018 | break; |
f9cce2dc | 1019 | |
3f37d465 | 1020 | case PLUS: |
1021 | case MINUS: | |
1022 | if (!iv_add (&iv0, &iv1, code)) | |
f9cce2dc | 1023 | return false; |
3f37d465 | 1024 | break; |
f9cce2dc | 1025 | |
3f37d465 | 1026 | case MULT: |
1027 | if (!iv_mult (&iv0, mby)) | |
1028 | return false; | |
1029 | break; | |
1030 | ||
1031 | case ASHIFT: | |
1032 | if (!iv_shift (&iv0, mby)) | |
1033 | return false; | |
1034 | break; | |
1035 | ||
1036 | default: | |
1037 | break; | |
f9cce2dc | 1038 | } |
1039 | ||
3f37d465 | 1040 | *iv = iv0; |
1041 | return iv->base != NULL_RTX; | |
1042 | } | |
1043 | ||
1044 | /* Analyzes iv DEF and stores the result to *IV. */ | |
1045 | ||
1046 | static bool | |
ed6e85ae | 1047 | iv_analyze_def (df_ref def, struct rtx_iv *iv) |
3f37d465 | 1048 | { |
1049 | rtx insn = DF_REF_INSN (def); | |
1050 | rtx reg = DF_REF_REG (def); | |
1051 | rtx set, rhs; | |
f9cce2dc | 1052 | |
450d042a | 1053 | if (dump_file) |
f9cce2dc | 1054 | { |
666137bc | 1055 | fprintf (dump_file, "Analyzing def of "); |
3f37d465 | 1056 | print_rtl (dump_file, reg); |
450d042a | 1057 | fprintf (dump_file, " in insn "); |
1058 | print_rtl_single (dump_file, insn); | |
f9cce2dc | 1059 | } |
48e1416a | 1060 | |
3072d30e | 1061 | check_iv_ref_table_size (); |
3f37d465 | 1062 | if (DF_REF_IV (def)) |
f9cce2dc | 1063 | { |
450d042a | 1064 | if (dump_file) |
1065 | fprintf (dump_file, " already analysed.\n"); | |
3f37d465 | 1066 | *iv = *DF_REF_IV (def); |
f9cce2dc | 1067 | return iv->base != NULL_RTX; |
1068 | } | |
1069 | ||
1070 | iv->mode = VOIDmode; | |
1071 | iv->base = NULL_RTX; | |
1072 | iv->step = NULL_RTX; | |
1073 | ||
3072d30e | 1074 | if (!REG_P (reg)) |
1075 | return false; | |
1076 | ||
f9cce2dc | 1077 | set = single_set (insn); |
3072d30e | 1078 | if (!set) |
1079 | return false; | |
1080 | ||
1081 | if (!REG_P (SET_DEST (set))) | |
3f37d465 | 1082 | return false; |
1083 | ||
3072d30e | 1084 | gcc_assert (SET_DEST (set) == reg); |
f9cce2dc | 1085 | rhs = find_reg_equal_equiv_note (insn); |
a6629703 | 1086 | if (rhs) |
1087 | rhs = XEXP (rhs, 0); | |
1088 | else | |
f9cce2dc | 1089 | rhs = SET_SRC (set); |
f9cce2dc | 1090 | |
3f37d465 | 1091 | iv_analyze_expr (insn, rhs, GET_MODE (reg), iv); |
1092 | record_iv (def, iv); | |
1093 | ||
1094 | if (dump_file) | |
f9cce2dc | 1095 | { |
3f37d465 | 1096 | print_rtl (dump_file, reg); |
1097 | fprintf (dump_file, " in insn "); | |
1098 | print_rtl_single (dump_file, insn); | |
1099 | fprintf (dump_file, " is "); | |
1100 | dump_iv_info (dump_file, iv); | |
1101 | fprintf (dump_file, "\n"); | |
f9cce2dc | 1102 | } |
f9cce2dc | 1103 | |
3f37d465 | 1104 | return iv->base != NULL_RTX; |
1105 | } | |
f9cce2dc | 1106 | |
3f37d465 | 1107 | /* Analyzes operand OP of INSN and stores the result to *IV. */ |
f9cce2dc | 1108 | |
3f37d465 | 1109 | static bool |
1110 | iv_analyze_op (rtx insn, rtx op, struct rtx_iv *iv) | |
1111 | { | |
ed6e85ae | 1112 | df_ref def = NULL; |
3f37d465 | 1113 | enum iv_grd_result res; |
567c3006 | 1114 | |
3f37d465 | 1115 | if (dump_file) |
1116 | { | |
666137bc | 1117 | fprintf (dump_file, "Analyzing operand "); |
3f37d465 | 1118 | print_rtl (dump_file, op); |
1119 | fprintf (dump_file, " of insn "); | |
1120 | print_rtl_single (dump_file, insn); | |
1121 | } | |
567c3006 | 1122 | |
e54e3d9f | 1123 | if (function_invariant_p (op)) |
3f37d465 | 1124 | res = GRD_INVARIANT; |
1125 | else if (GET_CODE (op) == SUBREG) | |
1126 | { | |
1127 | if (!subreg_lowpart_p (op)) | |
1128 | return false; | |
f9cce2dc | 1129 | |
3f37d465 | 1130 | if (!iv_analyze_op (insn, SUBREG_REG (op), iv)) |
1131 | return false; | |
f9cce2dc | 1132 | |
3f37d465 | 1133 | return iv_subreg (iv, GET_MODE (op)); |
1134 | } | |
1135 | else | |
f9cce2dc | 1136 | { |
3f37d465 | 1137 | res = iv_get_reaching_def (insn, op, &def); |
1138 | if (res == GRD_INVALID) | |
f9cce2dc | 1139 | { |
3f37d465 | 1140 | if (dump_file) |
1141 | fprintf (dump_file, " not simple.\n"); | |
1142 | return false; | |
f9cce2dc | 1143 | } |
1144 | } | |
1145 | ||
3f37d465 | 1146 | if (res == GRD_INVARIANT) |
f9cce2dc | 1147 | { |
3f37d465 | 1148 | iv_constant (iv, op, VOIDmode); |
f9cce2dc | 1149 | |
3f37d465 | 1150 | if (dump_file) |
f9cce2dc | 1151 | { |
3f37d465 | 1152 | fprintf (dump_file, " "); |
1153 | dump_iv_info (dump_file, iv); | |
1154 | fprintf (dump_file, "\n"); | |
f9cce2dc | 1155 | } |
3f37d465 | 1156 | return true; |
f9cce2dc | 1157 | } |
1158 | ||
3f37d465 | 1159 | if (res == GRD_MAYBE_BIV) |
1160 | return iv_analyze_biv (op, iv); | |
f9cce2dc | 1161 | |
3f37d465 | 1162 | return iv_analyze_def (def, iv); |
1163 | } | |
f9cce2dc | 1164 | |
3f37d465 | 1165 | /* Analyzes value VAL at INSN and stores the result to *IV. */ |
f9cce2dc | 1166 | |
3f37d465 | 1167 | bool |
1168 | iv_analyze (rtx insn, rtx val, struct rtx_iv *iv) | |
1169 | { | |
1170 | rtx reg; | |
f9cce2dc | 1171 | |
3f37d465 | 1172 | /* We must find the insn in that val is used, so that we get to UD chains. |
1173 | Since the function is sometimes called on result of get_condition, | |
1174 | this does not necessarily have to be directly INSN; scan also the | |
1175 | following insns. */ | |
1176 | if (simple_reg_p (val)) | |
1177 | { | |
1178 | if (GET_CODE (val) == SUBREG) | |
1179 | reg = SUBREG_REG (val); | |
1180 | else | |
1181 | reg = val; | |
567c3006 | 1182 | |
3072d30e | 1183 | while (!df_find_use (insn, reg)) |
3f37d465 | 1184 | insn = NEXT_INSN (insn); |
f9cce2dc | 1185 | } |
1186 | ||
3f37d465 | 1187 | return iv_analyze_op (insn, val, iv); |
1188 | } | |
f9cce2dc | 1189 | |
3f37d465 | 1190 | /* Analyzes definition of DEF in INSN and stores the result to IV. */ |
f9cce2dc | 1191 | |
3f37d465 | 1192 | bool |
1193 | iv_analyze_result (rtx insn, rtx def, struct rtx_iv *iv) | |
1194 | { | |
ed6e85ae | 1195 | df_ref adef; |
f9cce2dc | 1196 | |
3072d30e | 1197 | adef = df_find_def (insn, def); |
3f37d465 | 1198 | if (!adef) |
1199 | return false; | |
1200 | ||
1201 | return iv_analyze_def (adef, iv); | |
f9cce2dc | 1202 | } |
1203 | ||
3f37d465 | 1204 | /* Checks whether definition of register REG in INSN is a basic induction |
a9989fb4 | 1205 | variable. IV analysis must have been initialized (via a call to |
1206 | iv_analysis_loop_init) for this function to produce a result. */ | |
1207 | ||
1208 | bool | |
1209 | biv_p (rtx insn, rtx reg) | |
1210 | { | |
1211 | struct rtx_iv iv; | |
ed6e85ae | 1212 | df_ref def, last_def; |
a9989fb4 | 1213 | |
3f37d465 | 1214 | if (!simple_reg_p (reg)) |
a9989fb4 | 1215 | return false; |
1216 | ||
3072d30e | 1217 | def = df_find_def (insn, reg); |
3f37d465 | 1218 | gcc_assert (def != NULL); |
1219 | if (!latch_dominating_def (reg, &last_def)) | |
1220 | return false; | |
1221 | if (last_def != def) | |
a9989fb4 | 1222 | return false; |
1223 | ||
3f37d465 | 1224 | if (!iv_analyze_biv (reg, &iv)) |
1225 | return false; | |
1226 | ||
1227 | return iv.step != const0_rtx; | |
a9989fb4 | 1228 | } |
1229 | ||
f9cce2dc | 1230 | /* Calculates value of IV at ITERATION-th iteration. */ |
1231 | ||
1232 | rtx | |
1233 | get_iv_value (struct rtx_iv *iv, rtx iteration) | |
1234 | { | |
1235 | rtx val; | |
1236 | ||
1237 | /* We would need to generate some if_then_else patterns, and so far | |
1238 | it is not needed anywhere. */ | |
972e95af | 1239 | gcc_assert (!iv->first_special); |
f9cce2dc | 1240 | |
1241 | if (iv->step != const0_rtx && iteration != const0_rtx) | |
1242 | val = simplify_gen_binary (PLUS, iv->extend_mode, iv->base, | |
1243 | simplify_gen_binary (MULT, iv->extend_mode, | |
1244 | iv->step, iteration)); | |
1245 | else | |
1246 | val = iv->base; | |
1247 | ||
1248 | if (iv->extend_mode == iv->mode) | |
1249 | return val; | |
1250 | ||
c0efe3c3 | 1251 | val = lowpart_subreg (iv->mode, val, iv->extend_mode); |
f9cce2dc | 1252 | |
21f1e711 | 1253 | if (iv->extend == UNKNOWN) |
f9cce2dc | 1254 | return val; |
1255 | ||
1256 | val = simplify_gen_unary (iv->extend, iv->extend_mode, val, iv->mode); | |
1257 | val = simplify_gen_binary (PLUS, iv->extend_mode, iv->delta, | |
1258 | simplify_gen_binary (MULT, iv->extend_mode, | |
1259 | iv->mult, val)); | |
1260 | ||
1261 | return val; | |
1262 | } | |
1263 | ||
1264 | /* Free the data for an induction variable analysis. */ | |
1265 | ||
1266 | void | |
1267 | iv_analysis_done (void) | |
1268 | { | |
3072d30e | 1269 | if (!clean_slate) |
f9cce2dc | 1270 | { |
3f37d465 | 1271 | clear_iv_info (); |
3072d30e | 1272 | clean_slate = true; |
314966f4 | 1273 | df_finish_pass (true); |
3f37d465 | 1274 | htab_delete (bivs); |
3072d30e | 1275 | free (iv_ref_table); |
1276 | iv_ref_table = NULL; | |
1277 | iv_ref_table_size = 0; | |
f9cce2dc | 1278 | bivs = NULL; |
1279 | } | |
1280 | } | |
1281 | ||
1282 | /* Computes inverse to X modulo (1 << MOD). */ | |
1283 | ||
1284 | static unsigned HOST_WIDEST_INT | |
1285 | inverse (unsigned HOST_WIDEST_INT x, int mod) | |
1286 | { | |
1287 | unsigned HOST_WIDEST_INT mask = | |
1288 | ((unsigned HOST_WIDEST_INT) 1 << (mod - 1) << 1) - 1; | |
1289 | unsigned HOST_WIDEST_INT rslt = 1; | |
1290 | int i; | |
1291 | ||
1292 | for (i = 0; i < mod - 1; i++) | |
1293 | { | |
1294 | rslt = (rslt * x) & mask; | |
1295 | x = (x * x) & mask; | |
1296 | } | |
1297 | ||
1298 | return rslt; | |
1299 | } | |
1300 | ||
f9cce2dc | 1301 | /* Checks whether register *REG is in set ALT. Callback for for_each_rtx. */ |
1302 | ||
1303 | static int | |
1304 | altered_reg_used (rtx *reg, void *alt) | |
1305 | { | |
1306 | if (!REG_P (*reg)) | |
1307 | return 0; | |
1308 | ||
4077bf7a | 1309 | return REGNO_REG_SET_P ((bitmap) alt, REGNO (*reg)); |
f9cce2dc | 1310 | } |
1311 | ||
1312 | /* Marks registers altered by EXPR in set ALT. */ | |
1313 | ||
1314 | static void | |
81a410b1 | 1315 | mark_altered (rtx expr, const_rtx by ATTRIBUTE_UNUSED, void *alt) |
f9cce2dc | 1316 | { |
1317 | if (GET_CODE (expr) == SUBREG) | |
1318 | expr = SUBREG_REG (expr); | |
1319 | if (!REG_P (expr)) | |
1320 | return; | |
1321 | ||
4077bf7a | 1322 | SET_REGNO_REG_SET ((bitmap) alt, REGNO (expr)); |
f9cce2dc | 1323 | } |
1324 | ||
1325 | /* Checks whether RHS is simple enough to process. */ | |
1326 | ||
1327 | static bool | |
1328 | simple_rhs_p (rtx rhs) | |
1329 | { | |
1330 | rtx op0, op1; | |
1331 | ||
e54e3d9f | 1332 | if (function_invariant_p (rhs) |
b06b27dd | 1333 | || (REG_P (rhs) && !HARD_REGISTER_P (rhs))) |
f9cce2dc | 1334 | return true; |
1335 | ||
1336 | switch (GET_CODE (rhs)) | |
1337 | { | |
1338 | case PLUS: | |
1339 | case MINUS: | |
b908751e | 1340 | case AND: |
f9cce2dc | 1341 | op0 = XEXP (rhs, 0); |
1342 | op1 = XEXP (rhs, 1); | |
b908751e | 1343 | /* Allow reg OP const and reg OP reg. */ |
b718fe63 | 1344 | if (!(REG_P (op0) && !HARD_REGISTER_P (op0)) |
cf36214f | 1345 | && !function_invariant_p (op0)) |
b718fe63 | 1346 | return false; |
1347 | if (!(REG_P (op1) && !HARD_REGISTER_P (op1)) | |
cf36214f | 1348 | && !function_invariant_p (op1)) |
b718fe63 | 1349 | return false; |
f9cce2dc | 1350 | |
b718fe63 | 1351 | return true; |
1352 | ||
1353 | case ASHIFT: | |
b908751e | 1354 | case ASHIFTRT: |
1355 | case LSHIFTRT: | |
1356 | case MULT: | |
b718fe63 | 1357 | op0 = XEXP (rhs, 0); |
1358 | op1 = XEXP (rhs, 1); | |
b908751e | 1359 | /* Allow reg OP const. */ |
b718fe63 | 1360 | if (!(REG_P (op0) && !HARD_REGISTER_P (op0))) |
1361 | return false; | |
cf36214f | 1362 | if (!function_invariant_p (op1)) |
b718fe63 | 1363 | return false; |
1364 | ||
1365 | return true; | |
f9cce2dc | 1366 | |
1367 | default: | |
1368 | return false; | |
1369 | } | |
1370 | } | |
1371 | ||
767cb310 | 1372 | /* If REG has a single definition, replace it with its known value in EXPR. |
1373 | Callback for for_each_rtx. */ | |
1374 | ||
1375 | static int | |
1376 | replace_single_def_regs (rtx *reg, void *expr1) | |
1377 | { | |
1378 | unsigned regno; | |
1379 | df_ref adef; | |
3a40262c | 1380 | rtx set, src; |
767cb310 | 1381 | rtx *expr = (rtx *)expr1; |
1382 | ||
1383 | if (!REG_P (*reg)) | |
1384 | return 0; | |
1385 | ||
1386 | regno = REGNO (*reg); | |
3a40262c | 1387 | for (;;) |
1388 | { | |
1389 | rtx note; | |
1390 | adef = DF_REG_DEF_CHAIN (regno); | |
1391 | if (adef == NULL || DF_REF_NEXT_REG (adef) != NULL | |
1392 | || DF_REF_IS_ARTIFICIAL (adef)) | |
1393 | return -1; | |
1394 | ||
1395 | set = single_set (DF_REF_INSN (adef)); | |
1396 | if (set == NULL || !REG_P (SET_DEST (set)) | |
1397 | || REGNO (SET_DEST (set)) != regno) | |
1398 | return -1; | |
767cb310 | 1399 | |
3a40262c | 1400 | note = find_reg_equal_equiv_note (DF_REF_INSN (adef)); |
1401 | ||
1402 | if (note && function_invariant_p (XEXP (note, 0))) | |
1403 | { | |
1404 | src = XEXP (note, 0); | |
1405 | break; | |
1406 | } | |
1407 | src = SET_SRC (set); | |
1408 | ||
1409 | if (REG_P (src)) | |
1410 | { | |
1411 | regno = REGNO (src); | |
1412 | continue; | |
1413 | } | |
1414 | break; | |
1415 | } | |
1416 | if (!function_invariant_p (src)) | |
767cb310 | 1417 | return -1; |
1418 | ||
3a40262c | 1419 | *expr = simplify_replace_rtx (*expr, *reg, src); |
767cb310 | 1420 | return 1; |
1421 | } | |
1422 | ||
9bb5f693 | 1423 | /* A subroutine of simplify_using_initial_values, this function examines INSN |
1424 | to see if it contains a suitable set that we can use to make a replacement. | |
1425 | If it is suitable, return true and set DEST and SRC to the lhs and rhs of | |
1426 | the set; return false otherwise. */ | |
f9cce2dc | 1427 | |
9bb5f693 | 1428 | static bool |
1429 | suitable_set_for_replacement (rtx insn, rtx *dest, rtx *src) | |
f9cce2dc | 1430 | { |
1431 | rtx set = single_set (insn); | |
1b425b8e | 1432 | rtx lhs = NULL_RTX, rhs; |
f9cce2dc | 1433 | |
9bb5f693 | 1434 | if (!set) |
1435 | return false; | |
f9cce2dc | 1436 | |
9bb5f693 | 1437 | lhs = SET_DEST (set); |
1438 | if (!REG_P (lhs)) | |
1439 | return false; | |
f9cce2dc | 1440 | |
1441 | rhs = find_reg_equal_equiv_note (insn); | |
a6629703 | 1442 | if (rhs) |
1443 | rhs = XEXP (rhs, 0); | |
1444 | else | |
f9cce2dc | 1445 | rhs = SET_SRC (set); |
1446 | ||
1447 | if (!simple_rhs_p (rhs)) | |
9bb5f693 | 1448 | return false; |
f9cce2dc | 1449 | |
9bb5f693 | 1450 | *dest = lhs; |
1451 | *src = rhs; | |
1452 | return true; | |
f9cce2dc | 1453 | } |
1454 | ||
767cb310 | 1455 | /* Using the data returned by suitable_set_for_replacement, replace DEST |
1456 | with SRC in *EXPR and return the new expression. Also call | |
1457 | replace_single_def_regs if the replacement changed something. */ | |
1458 | static void | |
1459 | replace_in_expr (rtx *expr, rtx dest, rtx src) | |
1460 | { | |
1461 | rtx old = *expr; | |
1462 | *expr = simplify_replace_rtx (*expr, dest, src); | |
1463 | if (old == *expr) | |
1464 | return; | |
1465 | while (for_each_rtx (expr, replace_single_def_regs, expr) != 0) | |
1466 | continue; | |
1467 | } | |
1468 | ||
f9cce2dc | 1469 | /* Checks whether A implies B. */ |
1470 | ||
1471 | static bool | |
1472 | implies_p (rtx a, rtx b) | |
1473 | { | |
a6629703 | 1474 | rtx op0, op1, opb0, opb1, r; |
1475 | enum machine_mode mode; | |
f9cce2dc | 1476 | |
1477 | if (GET_CODE (a) == EQ) | |
1478 | { | |
1479 | op0 = XEXP (a, 0); | |
1480 | op1 = XEXP (a, 1); | |
1481 | ||
1482 | if (REG_P (op0)) | |
1483 | { | |
1484 | r = simplify_replace_rtx (b, op0, op1); | |
1485 | if (r == const_true_rtx) | |
1486 | return true; | |
1487 | } | |
1488 | ||
1489 | if (REG_P (op1)) | |
1490 | { | |
1491 | r = simplify_replace_rtx (b, op1, op0); | |
1492 | if (r == const_true_rtx) | |
1493 | return true; | |
1494 | } | |
1495 | } | |
1496 | ||
731d95c8 | 1497 | if (b == const_true_rtx) |
1498 | return true; | |
1499 | ||
1500 | if ((GET_RTX_CLASS (GET_CODE (a)) != RTX_COMM_COMPARE | |
1501 | && GET_RTX_CLASS (GET_CODE (a)) != RTX_COMPARE) | |
1502 | || (GET_RTX_CLASS (GET_CODE (b)) != RTX_COMM_COMPARE | |
1503 | && GET_RTX_CLASS (GET_CODE (b)) != RTX_COMPARE)) | |
1504 | return false; | |
1505 | ||
1506 | op0 = XEXP (a, 0); | |
1507 | op1 = XEXP (a, 1); | |
1508 | opb0 = XEXP (b, 0); | |
1509 | opb1 = XEXP (b, 1); | |
1510 | ||
1511 | mode = GET_MODE (op0); | |
1512 | if (mode != GET_MODE (opb0)) | |
1513 | mode = VOIDmode; | |
1514 | else if (mode == VOIDmode) | |
1515 | { | |
1516 | mode = GET_MODE (op1); | |
1517 | if (mode != GET_MODE (opb1)) | |
1518 | mode = VOIDmode; | |
1519 | } | |
1520 | ||
a6629703 | 1521 | /* A < B implies A + 1 <= B. */ |
1522 | if ((GET_CODE (a) == GT || GET_CODE (a) == LT) | |
1523 | && (GET_CODE (b) == GE || GET_CODE (b) == LE)) | |
1524 | { | |
a6629703 | 1525 | |
1526 | if (GET_CODE (a) == GT) | |
1527 | { | |
1528 | r = op0; | |
1529 | op0 = op1; | |
1530 | op1 = r; | |
1531 | } | |
1532 | ||
1533 | if (GET_CODE (b) == GE) | |
1534 | { | |
1535 | r = opb0; | |
1536 | opb0 = opb1; | |
1537 | opb1 = r; | |
1538 | } | |
1539 | ||
873983a1 | 1540 | if (SCALAR_INT_MODE_P (mode) |
a6629703 | 1541 | && rtx_equal_p (op1, opb1) |
1542 | && simplify_gen_binary (MINUS, mode, opb0, op0) == const1_rtx) | |
1543 | return true; | |
731d95c8 | 1544 | return false; |
1545 | } | |
1546 | ||
1547 | /* A < B or A > B imply A != B. TODO: Likewise | |
1548 | A + n < B implies A != B + n if neither wraps. */ | |
1549 | if (GET_CODE (b) == NE | |
1550 | && (GET_CODE (a) == GT || GET_CODE (a) == GTU | |
1551 | || GET_CODE (a) == LT || GET_CODE (a) == LTU)) | |
1552 | { | |
1553 | if (rtx_equal_p (op0, opb0) | |
1554 | && rtx_equal_p (op1, opb1)) | |
1555 | return true; | |
a6629703 | 1556 | } |
1557 | ||
731d95c8 | 1558 | /* For unsigned comparisons, A != 0 implies A > 0 and A >= 1. */ |
1559 | if (GET_CODE (a) == NE | |
1560 | && op1 == const0_rtx) | |
1561 | { | |
1562 | if ((GET_CODE (b) == GTU | |
1563 | && opb1 == const0_rtx) | |
1564 | || (GET_CODE (b) == GEU | |
1565 | && opb1 == const1_rtx)) | |
1566 | return rtx_equal_p (op0, opb0); | |
1567 | } | |
1568 | ||
1569 | /* A != N is equivalent to A - (N + 1) <u -1. */ | |
1570 | if (GET_CODE (a) == NE | |
971ba038 | 1571 | && CONST_INT_P (op1) |
731d95c8 | 1572 | && GET_CODE (b) == LTU |
1573 | && opb1 == constm1_rtx | |
1574 | && GET_CODE (opb0) == PLUS | |
971ba038 | 1575 | && CONST_INT_P (XEXP (opb0, 1)) |
731d95c8 | 1576 | /* Avoid overflows. */ |
1577 | && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (opb0, 1)) | |
1578 | != ((unsigned HOST_WIDE_INT)1 | |
1579 | << (HOST_BITS_PER_WIDE_INT - 1)) - 1) | |
1580 | && INTVAL (XEXP (opb0, 1)) + 1 == -INTVAL (op1)) | |
1581 | return rtx_equal_p (op0, XEXP (opb0, 0)); | |
1582 | ||
1583 | /* Likewise, A != N implies A - N > 0. */ | |
1584 | if (GET_CODE (a) == NE | |
971ba038 | 1585 | && CONST_INT_P (op1)) |
731d95c8 | 1586 | { |
1587 | if (GET_CODE (b) == GTU | |
1588 | && GET_CODE (opb0) == PLUS | |
1589 | && opb1 == const0_rtx | |
971ba038 | 1590 | && CONST_INT_P (XEXP (opb0, 1)) |
731d95c8 | 1591 | /* Avoid overflows. */ |
1592 | && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (opb0, 1)) | |
1593 | != ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1))) | |
1594 | && rtx_equal_p (XEXP (opb0, 0), op0)) | |
1595 | return INTVAL (op1) == -INTVAL (XEXP (opb0, 1)); | |
1596 | if (GET_CODE (b) == GEU | |
1597 | && GET_CODE (opb0) == PLUS | |
1598 | && opb1 == const1_rtx | |
971ba038 | 1599 | && CONST_INT_P (XEXP (opb0, 1)) |
731d95c8 | 1600 | /* Avoid overflows. */ |
1601 | && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (opb0, 1)) | |
1602 | != ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1))) | |
1603 | && rtx_equal_p (XEXP (opb0, 0), op0)) | |
1604 | return INTVAL (op1) == -INTVAL (XEXP (opb0, 1)); | |
1605 | } | |
1606 | ||
1607 | /* A >s X, where X is positive, implies A <u Y, if Y is negative. */ | |
1608 | if ((GET_CODE (a) == GT || GET_CODE (a) == GE) | |
971ba038 | 1609 | && CONST_INT_P (op1) |
731d95c8 | 1610 | && ((GET_CODE (a) == GT && op1 == constm1_rtx) |
1611 | || INTVAL (op1) >= 0) | |
1612 | && GET_CODE (b) == LTU | |
971ba038 | 1613 | && CONST_INT_P (opb1) |
27440859 | 1614 | && rtx_equal_p (op0, opb0)) |
731d95c8 | 1615 | return INTVAL (opb1) < 0; |
1616 | ||
f9cce2dc | 1617 | return false; |
1618 | } | |
1619 | ||
1620 | /* Canonicalizes COND so that | |
1621 | ||
1622 | (1) Ensure that operands are ordered according to | |
1623 | swap_commutative_operands_p. | |
1624 | (2) (LE x const) will be replaced with (LT x <const+1>) and similarly | |
1625 | for GE, GEU, and LEU. */ | |
1626 | ||
1627 | rtx | |
1628 | canon_condition (rtx cond) | |
1629 | { | |
1630 | rtx tem; | |
1631 | rtx op0, op1; | |
1632 | enum rtx_code code; | |
1633 | enum machine_mode mode; | |
1634 | ||
1635 | code = GET_CODE (cond); | |
1636 | op0 = XEXP (cond, 0); | |
1637 | op1 = XEXP (cond, 1); | |
1638 | ||
1639 | if (swap_commutative_operands_p (op0, op1)) | |
1640 | { | |
1641 | code = swap_condition (code); | |
1642 | tem = op0; | |
1643 | op0 = op1; | |
1644 | op1 = tem; | |
1645 | } | |
1646 | ||
1647 | mode = GET_MODE (op0); | |
1648 | if (mode == VOIDmode) | |
1649 | mode = GET_MODE (op1); | |
972e95af | 1650 | gcc_assert (mode != VOIDmode); |
f9cce2dc | 1651 | |
971ba038 | 1652 | if (CONST_INT_P (op1) |
f9cce2dc | 1653 | && GET_MODE_CLASS (mode) != MODE_CC |
1654 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) | |
1655 | { | |
1656 | HOST_WIDE_INT const_val = INTVAL (op1); | |
1657 | unsigned HOST_WIDE_INT uconst_val = const_val; | |
1658 | unsigned HOST_WIDE_INT max_val | |
1659 | = (unsigned HOST_WIDE_INT) GET_MODE_MASK (mode); | |
1660 | ||
1661 | switch (code) | |
1662 | { | |
1663 | case LE: | |
1664 | if ((unsigned HOST_WIDE_INT) const_val != max_val >> 1) | |
1665 | code = LT, op1 = gen_int_mode (const_val + 1, GET_MODE (op0)); | |
1666 | break; | |
1667 | ||
1668 | /* When cross-compiling, const_val might be sign-extended from | |
1669 | BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */ | |
1670 | case GE: | |
1671 | if ((HOST_WIDE_INT) (const_val & max_val) | |
1672 | != (((HOST_WIDE_INT) 1 | |
1673 | << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1)))) | |
1674 | code = GT, op1 = gen_int_mode (const_val - 1, mode); | |
1675 | break; | |
1676 | ||
1677 | case LEU: | |
1678 | if (uconst_val < max_val) | |
1679 | code = LTU, op1 = gen_int_mode (uconst_val + 1, mode); | |
1680 | break; | |
1681 | ||
1682 | case GEU: | |
1683 | if (uconst_val != 0) | |
1684 | code = GTU, op1 = gen_int_mode (uconst_val - 1, mode); | |
1685 | break; | |
1686 | ||
1687 | default: | |
1688 | break; | |
1689 | } | |
1690 | } | |
1691 | ||
1692 | if (op0 != XEXP (cond, 0) | |
1693 | || op1 != XEXP (cond, 1) | |
1694 | || code != GET_CODE (cond) | |
1695 | || GET_MODE (cond) != SImode) | |
1696 | cond = gen_rtx_fmt_ee (code, SImode, op0, op1); | |
1697 | ||
1698 | return cond; | |
1699 | } | |
1700 | ||
1701 | /* Tries to use the fact that COND holds to simplify EXPR. ALTERED is the | |
1702 | set of altered regs. */ | |
1703 | ||
1704 | void | |
1705 | simplify_using_condition (rtx cond, rtx *expr, regset altered) | |
1706 | { | |
1707 | rtx rev, reve, exp = *expr; | |
1708 | ||
f9cce2dc | 1709 | /* If some register gets altered later, we do not really speak about its |
1710 | value at the time of comparison. */ | |
1711 | if (altered | |
1712 | && for_each_rtx (&cond, altered_reg_used, altered)) | |
1713 | return; | |
1714 | ||
7f7a6f4a | 1715 | if (GET_CODE (cond) == EQ |
1716 | && REG_P (XEXP (cond, 0)) && CONSTANT_P (XEXP (cond, 1))) | |
1717 | { | |
1718 | *expr = simplify_replace_rtx (*expr, XEXP (cond, 0), XEXP (cond, 1)); | |
1719 | return; | |
1720 | } | |
1721 | ||
1722 | if (!COMPARISON_P (exp)) | |
1723 | return; | |
1724 | ||
f9cce2dc | 1725 | rev = reversed_condition (cond); |
1726 | reve = reversed_condition (exp); | |
1727 | ||
1728 | cond = canon_condition (cond); | |
1729 | exp = canon_condition (exp); | |
1730 | if (rev) | |
1731 | rev = canon_condition (rev); | |
1732 | if (reve) | |
1733 | reve = canon_condition (reve); | |
1734 | ||
1735 | if (rtx_equal_p (exp, cond)) | |
1736 | { | |
1737 | *expr = const_true_rtx; | |
1738 | return; | |
1739 | } | |
1740 | ||
f9cce2dc | 1741 | if (rev && rtx_equal_p (exp, rev)) |
1742 | { | |
1743 | *expr = const0_rtx; | |
1744 | return; | |
1745 | } | |
1746 | ||
1747 | if (implies_p (cond, exp)) | |
1748 | { | |
1749 | *expr = const_true_rtx; | |
1750 | return; | |
1751 | } | |
48e1416a | 1752 | |
f9cce2dc | 1753 | if (reve && implies_p (cond, reve)) |
1754 | { | |
1755 | *expr = const0_rtx; | |
1756 | return; | |
1757 | } | |
1758 | ||
1759 | /* A proof by contradiction. If *EXPR implies (not cond), *EXPR must | |
1760 | be false. */ | |
1761 | if (rev && implies_p (exp, rev)) | |
1762 | { | |
1763 | *expr = const0_rtx; | |
1764 | return; | |
1765 | } | |
1766 | ||
1767 | /* Similarly, If (not *EXPR) implies (not cond), *EXPR must be true. */ | |
1768 | if (rev && reve && implies_p (reve, rev)) | |
1769 | { | |
1770 | *expr = const_true_rtx; | |
1771 | return; | |
1772 | } | |
1773 | ||
1774 | /* We would like to have some other tests here. TODO. */ | |
1775 | ||
1776 | return; | |
1777 | } | |
1778 | ||
1779 | /* Use relationship between A and *B to eventually eliminate *B. | |
1780 | OP is the operation we consider. */ | |
1781 | ||
1782 | static void | |
1783 | eliminate_implied_condition (enum rtx_code op, rtx a, rtx *b) | |
1784 | { | |
972e95af | 1785 | switch (op) |
f9cce2dc | 1786 | { |
972e95af | 1787 | case AND: |
f9cce2dc | 1788 | /* If A implies *B, we may replace *B by true. */ |
1789 | if (implies_p (a, *b)) | |
1790 | *b = const_true_rtx; | |
972e95af | 1791 | break; |
1792 | ||
1793 | case IOR: | |
f9cce2dc | 1794 | /* If *B implies A, we may replace *B by false. */ |
1795 | if (implies_p (*b, a)) | |
1796 | *b = const0_rtx; | |
972e95af | 1797 | break; |
1798 | ||
1799 | default: | |
1800 | gcc_unreachable (); | |
f9cce2dc | 1801 | } |
f9cce2dc | 1802 | } |
1803 | ||
1804 | /* Eliminates the conditions in TAIL that are implied by HEAD. OP is the | |
1805 | operation we consider. */ | |
1806 | ||
1807 | static void | |
1808 | eliminate_implied_conditions (enum rtx_code op, rtx *head, rtx tail) | |
1809 | { | |
1810 | rtx elt; | |
1811 | ||
1812 | for (elt = tail; elt; elt = XEXP (elt, 1)) | |
1813 | eliminate_implied_condition (op, *head, &XEXP (elt, 0)); | |
1814 | for (elt = tail; elt; elt = XEXP (elt, 1)) | |
1815 | eliminate_implied_condition (op, XEXP (elt, 0), head); | |
1816 | } | |
1817 | ||
1818 | /* Simplifies *EXPR using initial values at the start of the LOOP. If *EXPR | |
1819 | is a list, its elements are assumed to be combined using OP. */ | |
1820 | ||
1821 | static void | |
1822 | simplify_using_initial_values (struct loop *loop, enum rtx_code op, rtx *expr) | |
1823 | { | |
9bb5f693 | 1824 | bool expression_valid; |
7f7a6f4a | 1825 | rtx head, tail, insn, cond_list, last_valid_expr; |
f9cce2dc | 1826 | rtx neutral, aggr; |
9bb5f693 | 1827 | regset altered, this_altered; |
f9cce2dc | 1828 | edge e; |
1829 | ||
1830 | if (!*expr) | |
1831 | return; | |
1832 | ||
1833 | if (CONSTANT_P (*expr)) | |
1834 | return; | |
1835 | ||
1836 | if (GET_CODE (*expr) == EXPR_LIST) | |
1837 | { | |
1838 | head = XEXP (*expr, 0); | |
1839 | tail = XEXP (*expr, 1); | |
1840 | ||
1841 | eliminate_implied_conditions (op, &head, tail); | |
1842 | ||
972e95af | 1843 | switch (op) |
f9cce2dc | 1844 | { |
972e95af | 1845 | case AND: |
f9cce2dc | 1846 | neutral = const_true_rtx; |
1847 | aggr = const0_rtx; | |
972e95af | 1848 | break; |
1849 | ||
1850 | case IOR: | |
f9cce2dc | 1851 | neutral = const0_rtx; |
1852 | aggr = const_true_rtx; | |
972e95af | 1853 | break; |
f9cce2dc | 1854 | |
972e95af | 1855 | default: |
1856 | gcc_unreachable (); | |
1857 | } | |
48e1416a | 1858 | |
21f1e711 | 1859 | simplify_using_initial_values (loop, UNKNOWN, &head); |
f9cce2dc | 1860 | if (head == aggr) |
1861 | { | |
1862 | XEXP (*expr, 0) = aggr; | |
1863 | XEXP (*expr, 1) = NULL_RTX; | |
1864 | return; | |
1865 | } | |
1866 | else if (head == neutral) | |
1867 | { | |
1868 | *expr = tail; | |
1869 | simplify_using_initial_values (loop, op, expr); | |
1870 | return; | |
1871 | } | |
1872 | simplify_using_initial_values (loop, op, &tail); | |
1873 | ||
1874 | if (tail && XEXP (tail, 0) == aggr) | |
1875 | { | |
1876 | *expr = tail; | |
1877 | return; | |
1878 | } | |
48e1416a | 1879 | |
f9cce2dc | 1880 | XEXP (*expr, 0) = head; |
1881 | XEXP (*expr, 1) = tail; | |
1882 | return; | |
1883 | } | |
1884 | ||
972e95af | 1885 | gcc_assert (op == UNKNOWN); |
f9cce2dc | 1886 | |
767cb310 | 1887 | for (;;) |
1888 | if (for_each_rtx (expr, replace_single_def_regs, expr) == 0) | |
1889 | break; | |
1890 | if (CONSTANT_P (*expr)) | |
1891 | return; | |
1892 | ||
f9cce2dc | 1893 | e = loop_preheader_edge (loop); |
1894 | if (e->src == ENTRY_BLOCK_PTR) | |
1895 | return; | |
1896 | ||
ae85a37a | 1897 | altered = ALLOC_REG_SET (®_obstack); |
9bb5f693 | 1898 | this_altered = ALLOC_REG_SET (®_obstack); |
f9cce2dc | 1899 | |
9bb5f693 | 1900 | expression_valid = true; |
1901 | last_valid_expr = *expr; | |
7f7a6f4a | 1902 | cond_list = NULL_RTX; |
f9cce2dc | 1903 | while (1) |
1904 | { | |
1905 | insn = BB_END (e->src); | |
1906 | if (any_condjump_p (insn)) | |
1907 | { | |
a255f65a | 1908 | rtx cond = get_condition (BB_END (e->src), NULL, false, true); |
7f7a6f4a | 1909 | |
f9cce2dc | 1910 | if (cond && (e->flags & EDGE_FALLTHRU)) |
1911 | cond = reversed_condition (cond); | |
1912 | if (cond) | |
1913 | { | |
7f7a6f4a | 1914 | rtx old = *expr; |
f9cce2dc | 1915 | simplify_using_condition (cond, expr, altered); |
7f7a6f4a | 1916 | if (old != *expr) |
1917 | { | |
1918 | rtx note; | |
1919 | if (CONSTANT_P (*expr)) | |
1920 | goto out; | |
1921 | for (note = cond_list; note; note = XEXP (note, 1)) | |
1922 | { | |
1923 | simplify_using_condition (XEXP (note, 0), expr, altered); | |
1924 | if (CONSTANT_P (*expr)) | |
1925 | goto out; | |
1926 | } | |
1927 | } | |
1928 | cond_list = alloc_EXPR_LIST (0, cond, cond_list); | |
f9cce2dc | 1929 | } |
1930 | } | |
1931 | ||
1932 | FOR_BB_INSNS_REVERSE (e->src, insn) | |
1933 | { | |
9bb5f693 | 1934 | rtx src, dest; |
7f7a6f4a | 1935 | rtx old = *expr; |
9bb5f693 | 1936 | |
f9cce2dc | 1937 | if (!INSN_P (insn)) |
1938 | continue; | |
9bb5f693 | 1939 | |
1940 | CLEAR_REG_SET (this_altered); | |
1941 | note_stores (PATTERN (insn), mark_altered, this_altered); | |
1942 | if (CALL_P (insn)) | |
f9cce2dc | 1943 | { |
9bb5f693 | 1944 | int i; |
48e1416a | 1945 | |
9bb5f693 | 1946 | /* Kill all call clobbered registers. */ |
1947 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1948 | if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i)) | |
1949 | SET_REGNO_REG_SET (this_altered, i); | |
f9cce2dc | 1950 | } |
9bb5f693 | 1951 | |
1952 | if (suitable_set_for_replacement (insn, &dest, &src)) | |
9676249d | 1953 | { |
7f7a6f4a | 1954 | rtx *pnote, *pnote_next; |
1955 | ||
767cb310 | 1956 | replace_in_expr (expr, dest, src); |
9bb5f693 | 1957 | if (CONSTANT_P (*expr)) |
1958 | goto out; | |
7f7a6f4a | 1959 | |
1960 | for (pnote = &cond_list; *pnote; pnote = pnote_next) | |
1961 | { | |
1962 | rtx note = *pnote; | |
1963 | rtx old_cond = XEXP (note, 0); | |
1964 | ||
1965 | pnote_next = &XEXP (note, 1); | |
767cb310 | 1966 | replace_in_expr (&XEXP (note, 0), dest, src); |
1967 | ||
7f7a6f4a | 1968 | /* We can no longer use a condition that has been simplified |
1969 | to a constant, and simplify_using_condition will abort if | |
1970 | we try. */ | |
1971 | if (CONSTANT_P (XEXP (note, 0))) | |
1972 | { | |
1973 | *pnote = *pnote_next; | |
1974 | pnote_next = pnote; | |
1975 | free_EXPR_LIST_node (note); | |
1976 | } | |
1977 | /* Retry simplifications with this condition if either the | |
1978 | expression or the condition changed. */ | |
1979 | else if (old_cond != XEXP (note, 0) || old != *expr) | |
1980 | simplify_using_condition (XEXP (note, 0), expr, altered); | |
1981 | } | |
9676249d | 1982 | } |
9bb5f693 | 1983 | else |
1984 | /* If we did not use this insn to make a replacement, any overlap | |
1985 | between stores in this insn and our expression will cause the | |
1986 | expression to become invalid. */ | |
1987 | if (for_each_rtx (expr, altered_reg_used, this_altered)) | |
1988 | goto out; | |
1989 | ||
7f7a6f4a | 1990 | if (CONSTANT_P (*expr)) |
1991 | goto out; | |
1992 | ||
9bb5f693 | 1993 | IOR_REG_SET (altered, this_altered); |
1994 | ||
1995 | /* If the expression now contains regs that have been altered, we | |
1996 | can't return it to the caller. However, it is still valid for | |
1997 | further simplification, so keep searching to see if we can | |
1998 | eventually turn it into a constant. */ | |
1999 | if (for_each_rtx (expr, altered_reg_used, altered)) | |
2000 | expression_valid = false; | |
2001 | if (expression_valid) | |
2002 | last_valid_expr = *expr; | |
f9cce2dc | 2003 | } |
2004 | ||
ea091dfd | 2005 | if (!single_pred_p (e->src) |
2006 | || single_pred (e->src) == ENTRY_BLOCK_PTR) | |
f9cce2dc | 2007 | break; |
ea091dfd | 2008 | e = single_pred_edge (e->src); |
f9cce2dc | 2009 | } |
2010 | ||
9bb5f693 | 2011 | out: |
7f7a6f4a | 2012 | free_EXPR_LIST_list (&cond_list); |
9bb5f693 | 2013 | if (!CONSTANT_P (*expr)) |
2014 | *expr = last_valid_expr; | |
f9cce2dc | 2015 | FREE_REG_SET (altered); |
9bb5f693 | 2016 | FREE_REG_SET (this_altered); |
f9cce2dc | 2017 | } |
2018 | ||
2019 | /* Transforms invariant IV into MODE. Adds assumptions based on the fact | |
2020 | that IV occurs as left operands of comparison COND and its signedness | |
2021 | is SIGNED_P to DESC. */ | |
2022 | ||
2023 | static void | |
2024 | shorten_into_mode (struct rtx_iv *iv, enum machine_mode mode, | |
2025 | enum rtx_code cond, bool signed_p, struct niter_desc *desc) | |
2026 | { | |
2027 | rtx mmin, mmax, cond_over, cond_under; | |
2028 | ||
a6629703 | 2029 | get_mode_bounds (mode, signed_p, iv->extend_mode, &mmin, &mmax); |
f9cce2dc | 2030 | cond_under = simplify_gen_relational (LT, SImode, iv->extend_mode, |
2031 | iv->base, mmin); | |
2032 | cond_over = simplify_gen_relational (GT, SImode, iv->extend_mode, | |
2033 | iv->base, mmax); | |
2034 | ||
2035 | switch (cond) | |
2036 | { | |
2037 | case LE: | |
2038 | case LT: | |
2039 | case LEU: | |
2040 | case LTU: | |
2041 | if (cond_under != const0_rtx) | |
2042 | desc->infinite = | |
2043 | alloc_EXPR_LIST (0, cond_under, desc->infinite); | |
2044 | if (cond_over != const0_rtx) | |
2045 | desc->noloop_assumptions = | |
2046 | alloc_EXPR_LIST (0, cond_over, desc->noloop_assumptions); | |
2047 | break; | |
2048 | ||
2049 | case GE: | |
2050 | case GT: | |
2051 | case GEU: | |
2052 | case GTU: | |
2053 | if (cond_over != const0_rtx) | |
2054 | desc->infinite = | |
2055 | alloc_EXPR_LIST (0, cond_over, desc->infinite); | |
2056 | if (cond_under != const0_rtx) | |
2057 | desc->noloop_assumptions = | |
2058 | alloc_EXPR_LIST (0, cond_under, desc->noloop_assumptions); | |
2059 | break; | |
2060 | ||
2061 | case NE: | |
2062 | if (cond_over != const0_rtx) | |
2063 | desc->infinite = | |
2064 | alloc_EXPR_LIST (0, cond_over, desc->infinite); | |
2065 | if (cond_under != const0_rtx) | |
2066 | desc->infinite = | |
2067 | alloc_EXPR_LIST (0, cond_under, desc->infinite); | |
2068 | break; | |
2069 | ||
2070 | default: | |
972e95af | 2071 | gcc_unreachable (); |
f9cce2dc | 2072 | } |
2073 | ||
2074 | iv->mode = mode; | |
2075 | iv->extend = signed_p ? SIGN_EXTEND : ZERO_EXTEND; | |
2076 | } | |
2077 | ||
2078 | /* Transforms IV0 and IV1 compared by COND so that they are both compared as | |
aab2cf92 | 2079 | subregs of the same mode if possible (sometimes it is necessary to add |
f9cce2dc | 2080 | some assumptions to DESC). */ |
2081 | ||
2082 | static bool | |
2083 | canonicalize_iv_subregs (struct rtx_iv *iv0, struct rtx_iv *iv1, | |
2084 | enum rtx_code cond, struct niter_desc *desc) | |
2085 | { | |
2086 | enum machine_mode comp_mode; | |
2087 | bool signed_p; | |
2088 | ||
2089 | /* If the ivs behave specially in the first iteration, or are | |
2090 | added/multiplied after extending, we ignore them. */ | |
2091 | if (iv0->first_special || iv0->mult != const1_rtx || iv0->delta != const0_rtx) | |
2092 | return false; | |
2093 | if (iv1->first_special || iv1->mult != const1_rtx || iv1->delta != const0_rtx) | |
2094 | return false; | |
2095 | ||
2096 | /* If there is some extend, it must match signedness of the comparison. */ | |
2097 | switch (cond) | |
2098 | { | |
2099 | case LE: | |
2100 | case LT: | |
2101 | if (iv0->extend == ZERO_EXTEND | |
2102 | || iv1->extend == ZERO_EXTEND) | |
2103 | return false; | |
2104 | signed_p = true; | |
2105 | break; | |
2106 | ||
2107 | case LEU: | |
2108 | case LTU: | |
2109 | if (iv0->extend == SIGN_EXTEND | |
2110 | || iv1->extend == SIGN_EXTEND) | |
2111 | return false; | |
2112 | signed_p = false; | |
2113 | break; | |
2114 | ||
2115 | case NE: | |
21f1e711 | 2116 | if (iv0->extend != UNKNOWN |
2117 | && iv1->extend != UNKNOWN | |
f9cce2dc | 2118 | && iv0->extend != iv1->extend) |
2119 | return false; | |
2120 | ||
2121 | signed_p = false; | |
21f1e711 | 2122 | if (iv0->extend != UNKNOWN) |
f9cce2dc | 2123 | signed_p = iv0->extend == SIGN_EXTEND; |
21f1e711 | 2124 | if (iv1->extend != UNKNOWN) |
f9cce2dc | 2125 | signed_p = iv1->extend == SIGN_EXTEND; |
2126 | break; | |
2127 | ||
2128 | default: | |
972e95af | 2129 | gcc_unreachable (); |
f9cce2dc | 2130 | } |
2131 | ||
2132 | /* Values of both variables should be computed in the same mode. These | |
2133 | might indeed be different, if we have comparison like | |
2134 | ||
2135 | (compare (subreg:SI (iv0)) (subreg:SI (iv1))) | |
2136 | ||
2137 | and iv0 and iv1 are both ivs iterating in SI mode, but calculated | |
2138 | in different modes. This does not seem impossible to handle, but | |
2139 | it hardly ever occurs in practice. | |
48e1416a | 2140 | |
f9cce2dc | 2141 | The only exception is the case when one of operands is invariant. |
2142 | For example pentium 3 generates comparisons like | |
2143 | (lt (subreg:HI (reg:SI)) 100). Here we assign HImode to 100, but we | |
2144 | definitely do not want this prevent the optimization. */ | |
2145 | comp_mode = iv0->extend_mode; | |
2146 | if (GET_MODE_BITSIZE (comp_mode) < GET_MODE_BITSIZE (iv1->extend_mode)) | |
2147 | comp_mode = iv1->extend_mode; | |
2148 | ||
2149 | if (iv0->extend_mode != comp_mode) | |
2150 | { | |
2151 | if (iv0->mode != iv0->extend_mode | |
2152 | || iv0->step != const0_rtx) | |
2153 | return false; | |
2154 | ||
2155 | iv0->base = simplify_gen_unary (signed_p ? SIGN_EXTEND : ZERO_EXTEND, | |
2156 | comp_mode, iv0->base, iv0->mode); | |
2157 | iv0->extend_mode = comp_mode; | |
2158 | } | |
2159 | ||
2160 | if (iv1->extend_mode != comp_mode) | |
2161 | { | |
2162 | if (iv1->mode != iv1->extend_mode | |
2163 | || iv1->step != const0_rtx) | |
2164 | return false; | |
2165 | ||
2166 | iv1->base = simplify_gen_unary (signed_p ? SIGN_EXTEND : ZERO_EXTEND, | |
2167 | comp_mode, iv1->base, iv1->mode); | |
2168 | iv1->extend_mode = comp_mode; | |
2169 | } | |
2170 | ||
2171 | /* Check that both ivs belong to a range of a single mode. If one of the | |
2172 | operands is an invariant, we may need to shorten it into the common | |
2173 | mode. */ | |
2174 | if (iv0->mode == iv0->extend_mode | |
2175 | && iv0->step == const0_rtx | |
2176 | && iv0->mode != iv1->mode) | |
2177 | shorten_into_mode (iv0, iv1->mode, cond, signed_p, desc); | |
2178 | ||
2179 | if (iv1->mode == iv1->extend_mode | |
2180 | && iv1->step == const0_rtx | |
2181 | && iv0->mode != iv1->mode) | |
2182 | shorten_into_mode (iv1, iv0->mode, swap_condition (cond), signed_p, desc); | |
2183 | ||
2184 | if (iv0->mode != iv1->mode) | |
2185 | return false; | |
2186 | ||
2187 | desc->mode = iv0->mode; | |
2188 | desc->signed_p = signed_p; | |
2189 | ||
2190 | return true; | |
2191 | } | |
2192 | ||
8fb72e03 | 2193 | /* Tries to estimate the maximum number of iterations in LOOP, and return the |
2194 | result. This function is called from iv_number_of_iterations with | |
f77c1bb0 | 2195 | a number of fields in DESC already filled in. OLD_NITER is the original |
2196 | expression for the number of iterations, before we tried to simplify it. */ | |
c9d59418 | 2197 | |
2198 | static unsigned HOST_WIDEST_INT | |
f77c1bb0 | 2199 | determine_max_iter (struct loop *loop, struct niter_desc *desc, rtx old_niter) |
c9d59418 | 2200 | { |
2201 | rtx niter = desc->niter_expr; | |
731d95c8 | 2202 | rtx mmin, mmax, cmp; |
c9d59418 | 2203 | unsigned HOST_WIDEST_INT nmax, inc; |
2204 | ||
2205 | if (GET_CODE (niter) == AND | |
971ba038 | 2206 | && CONST_INT_P (XEXP (niter, 0))) |
c9d59418 | 2207 | { |
2208 | nmax = INTVAL (XEXP (niter, 0)); | |
2209 | if (!(nmax & (nmax + 1))) | |
8fb72e03 | 2210 | return nmax; |
c9d59418 | 2211 | } |
2212 | ||
2213 | get_mode_bounds (desc->mode, desc->signed_p, desc->mode, &mmin, &mmax); | |
2214 | nmax = INTVAL (mmax) - INTVAL (mmin); | |
2215 | ||
2216 | if (GET_CODE (niter) == UDIV) | |
2217 | { | |
971ba038 | 2218 | if (!CONST_INT_P (XEXP (niter, 1))) |
8fb72e03 | 2219 | return nmax; |
c9d59418 | 2220 | inc = INTVAL (XEXP (niter, 1)); |
2221 | niter = XEXP (niter, 0); | |
2222 | } | |
2223 | else | |
2224 | inc = 1; | |
2225 | ||
731d95c8 | 2226 | /* We could use a binary search here, but for now improving the upper |
2227 | bound by just one eliminates one important corner case. */ | |
f77c1bb0 | 2228 | cmp = simplify_gen_relational (desc->signed_p ? LT : LTU, VOIDmode, |
2229 | desc->mode, old_niter, mmax); | |
731d95c8 | 2230 | simplify_using_initial_values (loop, UNKNOWN, &cmp); |
2231 | if (cmp == const_true_rtx) | |
c9d59418 | 2232 | { |
731d95c8 | 2233 | nmax--; |
c9d59418 | 2234 | |
731d95c8 | 2235 | if (dump_file) |
2236 | fprintf (dump_file, ";; improved upper bound by one.\n"); | |
c9d59418 | 2237 | } |
c9d59418 | 2238 | return nmax / inc; |
2239 | } | |
2240 | ||
f9cce2dc | 2241 | /* Computes number of iterations of the CONDITION in INSN in LOOP and stores |
2242 | the result into DESC. Very similar to determine_number_of_iterations | |
2243 | (basically its rtl version), complicated by things like subregs. */ | |
2244 | ||
d9918998 | 2245 | static void |
f9cce2dc | 2246 | iv_number_of_iterations (struct loop *loop, rtx insn, rtx condition, |
2247 | struct niter_desc *desc) | |
2248 | { | |
3f37d465 | 2249 | rtx op0, op1, delta, step, bound, may_xform, tmp, tmp0, tmp1; |
f9cce2dc | 2250 | struct rtx_iv iv0, iv1, tmp_iv; |
a6629703 | 2251 | rtx assumption, may_not_xform; |
f9cce2dc | 2252 | enum rtx_code cond; |
2253 | enum machine_mode mode, comp_mode; | |
a6629703 | 2254 | rtx mmin, mmax, mode_mmin, mode_mmax; |
8fb72e03 | 2255 | unsigned HOST_WIDEST_INT s, size, d, inv, max; |
f8f90b50 | 2256 | HOST_WIDEST_INT up, down, inc, step_val; |
f9cce2dc | 2257 | int was_sharp = false; |
1e8e4a1d | 2258 | rtx old_niter; |
f8f90b50 | 2259 | bool step_is_pow2; |
f9cce2dc | 2260 | |
2261 | /* The meaning of these assumptions is this: | |
2262 | if !assumptions | |
2263 | then the rest of information does not have to be valid | |
2264 | if noloop_assumptions then the loop does not roll | |
2265 | if infinite then this exit is never used */ | |
2266 | ||
2267 | desc->assumptions = NULL_RTX; | |
2268 | desc->noloop_assumptions = NULL_RTX; | |
2269 | desc->infinite = NULL_RTX; | |
2270 | desc->simple_p = true; | |
2271 | ||
2272 | desc->const_iter = false; | |
2273 | desc->niter_expr = NULL_RTX; | |
2274 | desc->niter_max = 0; | |
8fb72e03 | 2275 | if (loop->any_upper_bound |
2276 | && double_int_fits_in_uhwi_p (loop->nb_iterations_upper_bound)) | |
2277 | desc->niter_max = loop->nb_iterations_upper_bound.low; | |
f9cce2dc | 2278 | |
2279 | cond = GET_CODE (condition); | |
972e95af | 2280 | gcc_assert (COMPARISON_P (condition)); |
f9cce2dc | 2281 | |
2282 | mode = GET_MODE (XEXP (condition, 0)); | |
2283 | if (mode == VOIDmode) | |
2284 | mode = GET_MODE (XEXP (condition, 1)); | |
2285 | /* The constant comparisons should be folded. */ | |
972e95af | 2286 | gcc_assert (mode != VOIDmode); |
f9cce2dc | 2287 | |
2288 | /* We only handle integers or pointers. */ | |
2289 | if (GET_MODE_CLASS (mode) != MODE_INT | |
2290 | && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT) | |
2291 | goto fail; | |
2292 | ||
2293 | op0 = XEXP (condition, 0); | |
3f37d465 | 2294 | if (!iv_analyze (insn, op0, &iv0)) |
f9cce2dc | 2295 | goto fail; |
2296 | if (iv0.extend_mode == VOIDmode) | |
2297 | iv0.mode = iv0.extend_mode = mode; | |
48e1416a | 2298 | |
f9cce2dc | 2299 | op1 = XEXP (condition, 1); |
3f37d465 | 2300 | if (!iv_analyze (insn, op1, &iv1)) |
f9cce2dc | 2301 | goto fail; |
2302 | if (iv1.extend_mode == VOIDmode) | |
2303 | iv1.mode = iv1.extend_mode = mode; | |
2304 | ||
2305 | if (GET_MODE_BITSIZE (iv0.extend_mode) > HOST_BITS_PER_WIDE_INT | |
2306 | || GET_MODE_BITSIZE (iv1.extend_mode) > HOST_BITS_PER_WIDE_INT) | |
2307 | goto fail; | |
2308 | ||
2309 | /* Check condition and normalize it. */ | |
2310 | ||
2311 | switch (cond) | |
2312 | { | |
2313 | case GE: | |
2314 | case GT: | |
2315 | case GEU: | |
2316 | case GTU: | |
2317 | tmp_iv = iv0; iv0 = iv1; iv1 = tmp_iv; | |
2318 | cond = swap_condition (cond); | |
2319 | break; | |
2320 | case NE: | |
2321 | case LE: | |
2322 | case LEU: | |
2323 | case LT: | |
2324 | case LTU: | |
2325 | break; | |
2326 | default: | |
2327 | goto fail; | |
2328 | } | |
2329 | ||
2330 | /* Handle extends. This is relatively nontrivial, so we only try in some | |
2331 | easy cases, when we can canonicalize the ivs (possibly by adding some | |
2332 | assumptions) to shape subreg (base + i * step). This function also fills | |
2333 | in desc->mode and desc->signed_p. */ | |
2334 | ||
2335 | if (!canonicalize_iv_subregs (&iv0, &iv1, cond, desc)) | |
2336 | goto fail; | |
2337 | ||
2338 | comp_mode = iv0.extend_mode; | |
2339 | mode = iv0.mode; | |
2340 | size = GET_MODE_BITSIZE (mode); | |
a6629703 | 2341 | get_mode_bounds (mode, (cond == LE || cond == LT), comp_mode, &mmin, &mmax); |
c0efe3c3 | 2342 | mode_mmin = lowpart_subreg (mode, mmin, comp_mode); |
2343 | mode_mmax = lowpart_subreg (mode, mmax, comp_mode); | |
f9cce2dc | 2344 | |
971ba038 | 2345 | if (!CONST_INT_P (iv0.step) || !CONST_INT_P (iv1.step)) |
f9cce2dc | 2346 | goto fail; |
2347 | ||
2348 | /* We can take care of the case of two induction variables chasing each other | |
2349 | if the test is NE. I have never seen a loop using it, but still it is | |
2350 | cool. */ | |
2351 | if (iv0.step != const0_rtx && iv1.step != const0_rtx) | |
2352 | { | |
2353 | if (cond != NE) | |
2354 | goto fail; | |
2355 | ||
2356 | iv0.step = simplify_gen_binary (MINUS, comp_mode, iv0.step, iv1.step); | |
2357 | iv1.step = const0_rtx; | |
2358 | } | |
2359 | ||
2360 | /* This is either infinite loop or the one that ends immediately, depending | |
2361 | on initial values. Unswitching should remove this kind of conditions. */ | |
2362 | if (iv0.step == const0_rtx && iv1.step == const0_rtx) | |
2363 | goto fail; | |
2364 | ||
f8f90b50 | 2365 | if (cond != NE) |
2366 | { | |
2367 | if (iv0.step == const0_rtx) | |
2368 | step_val = -INTVAL (iv1.step); | |
2369 | else | |
15943825 | 2370 | step_val = INTVAL (iv0.step); |
f8f90b50 | 2371 | |
2372 | /* Ignore loops of while (i-- < 10) type. */ | |
2373 | if (step_val < 0) | |
2374 | goto fail; | |
2375 | ||
2376 | step_is_pow2 = !(step_val & (step_val - 1)); | |
2377 | } | |
2378 | else | |
2379 | { | |
2380 | /* We do not care about whether the step is power of two in this | |
2381 | case. */ | |
2382 | step_is_pow2 = false; | |
2383 | step_val = 0; | |
2384 | } | |
f9cce2dc | 2385 | |
2386 | /* Some more condition normalization. We must record some assumptions | |
2387 | due to overflows. */ | |
2388 | switch (cond) | |
2389 | { | |
2390 | case LT: | |
2391 | case LTU: | |
2392 | /* We want to take care only of non-sharp relationals; this is easy, | |
2393 | as in cases the overflow would make the transformation unsafe | |
2394 | the loop does not roll. Seemingly it would make more sense to want | |
2395 | to take care of sharp relationals instead, as NE is more similar to | |
2396 | them, but the problem is that here the transformation would be more | |
2397 | difficult due to possibly infinite loops. */ | |
2398 | if (iv0.step == const0_rtx) | |
2399 | { | |
c0efe3c3 | 2400 | tmp = lowpart_subreg (mode, iv0.base, comp_mode); |
a6629703 | 2401 | assumption = simplify_gen_relational (EQ, SImode, mode, tmp, |
2402 | mode_mmax); | |
f9cce2dc | 2403 | if (assumption == const_true_rtx) |
f30c7901 | 2404 | goto zero_iter_simplify; |
f9cce2dc | 2405 | iv0.base = simplify_gen_binary (PLUS, comp_mode, |
2406 | iv0.base, const1_rtx); | |
2407 | } | |
2408 | else | |
2409 | { | |
c0efe3c3 | 2410 | tmp = lowpart_subreg (mode, iv1.base, comp_mode); |
a6629703 | 2411 | assumption = simplify_gen_relational (EQ, SImode, mode, tmp, |
2412 | mode_mmin); | |
f9cce2dc | 2413 | if (assumption == const_true_rtx) |
f30c7901 | 2414 | goto zero_iter_simplify; |
f9cce2dc | 2415 | iv1.base = simplify_gen_binary (PLUS, comp_mode, |
2416 | iv1.base, constm1_rtx); | |
2417 | } | |
2418 | ||
2419 | if (assumption != const0_rtx) | |
2420 | desc->noloop_assumptions = | |
2421 | alloc_EXPR_LIST (0, assumption, desc->noloop_assumptions); | |
2422 | cond = (cond == LT) ? LE : LEU; | |
2423 | ||
2424 | /* It will be useful to be able to tell the difference once more in | |
2425 | LE -> NE reduction. */ | |
2426 | was_sharp = true; | |
2427 | break; | |
2428 | default: ; | |
2429 | } | |
2430 | ||
2431 | /* Take care of trivially infinite loops. */ | |
2432 | if (cond != NE) | |
2433 | { | |
2434 | if (iv0.step == const0_rtx) | |
2435 | { | |
c0efe3c3 | 2436 | tmp = lowpart_subreg (mode, iv0.base, comp_mode); |
a6629703 | 2437 | if (rtx_equal_p (tmp, mode_mmin)) |
f9cce2dc | 2438 | { |
2439 | desc->infinite = | |
2440 | alloc_EXPR_LIST (0, const_true_rtx, NULL_RTX); | |
f30c7901 | 2441 | /* Fill in the remaining fields somehow. */ |
2442 | goto zero_iter_simplify; | |
f9cce2dc | 2443 | } |
2444 | } | |
2445 | else | |
2446 | { | |
c0efe3c3 | 2447 | tmp = lowpart_subreg (mode, iv1.base, comp_mode); |
a6629703 | 2448 | if (rtx_equal_p (tmp, mode_mmax)) |
f9cce2dc | 2449 | { |
2450 | desc->infinite = | |
2451 | alloc_EXPR_LIST (0, const_true_rtx, NULL_RTX); | |
f30c7901 | 2452 | /* Fill in the remaining fields somehow. */ |
2453 | goto zero_iter_simplify; | |
f9cce2dc | 2454 | } |
2455 | } | |
2456 | } | |
2457 | ||
2458 | /* If we can we want to take care of NE conditions instead of size | |
2459 | comparisons, as they are much more friendly (most importantly | |
2460 | this takes care of special handling of loops with step 1). We can | |
2461 | do it if we first check that upper bound is greater or equal to | |
2462 | lower bound, their difference is constant c modulo step and that | |
2463 | there is not an overflow. */ | |
2464 | if (cond != NE) | |
2465 | { | |
2466 | if (iv0.step == const0_rtx) | |
2467 | step = simplify_gen_unary (NEG, comp_mode, iv1.step, comp_mode); | |
2468 | else | |
2469 | step = iv0.step; | |
2470 | delta = simplify_gen_binary (MINUS, comp_mode, iv1.base, iv0.base); | |
c0efe3c3 | 2471 | delta = lowpart_subreg (mode, delta, comp_mode); |
f9cce2dc | 2472 | delta = simplify_gen_binary (UMOD, mode, delta, step); |
2473 | may_xform = const0_rtx; | |
a6629703 | 2474 | may_not_xform = const_true_rtx; |
f9cce2dc | 2475 | |
971ba038 | 2476 | if (CONST_INT_P (delta)) |
f9cce2dc | 2477 | { |
2478 | if (was_sharp && INTVAL (delta) == INTVAL (step) - 1) | |
2479 | { | |
2480 | /* A special case. We have transformed condition of type | |
2481 | for (i = 0; i < 4; i += 4) | |
2482 | into | |
2483 | for (i = 0; i <= 3; i += 4) | |
2484 | obviously if the test for overflow during that transformation | |
2485 | passed, we cannot overflow here. Most importantly any | |
2486 | loop with sharp end condition and step 1 falls into this | |
aab2cf92 | 2487 | category, so handling this case specially is definitely |
f9cce2dc | 2488 | worth the troubles. */ |
2489 | may_xform = const_true_rtx; | |
2490 | } | |
2491 | else if (iv0.step == const0_rtx) | |
2492 | { | |
2493 | bound = simplify_gen_binary (PLUS, comp_mode, mmin, step); | |
2494 | bound = simplify_gen_binary (MINUS, comp_mode, bound, delta); | |
c0efe3c3 | 2495 | bound = lowpart_subreg (mode, bound, comp_mode); |
2496 | tmp = lowpart_subreg (mode, iv0.base, comp_mode); | |
f9cce2dc | 2497 | may_xform = simplify_gen_relational (cond, SImode, mode, |
2498 | bound, tmp); | |
a6629703 | 2499 | may_not_xform = simplify_gen_relational (reverse_condition (cond), |
2500 | SImode, mode, | |
2501 | bound, tmp); | |
f9cce2dc | 2502 | } |
2503 | else | |
2504 | { | |
2505 | bound = simplify_gen_binary (MINUS, comp_mode, mmax, step); | |
2506 | bound = simplify_gen_binary (PLUS, comp_mode, bound, delta); | |
c0efe3c3 | 2507 | bound = lowpart_subreg (mode, bound, comp_mode); |
2508 | tmp = lowpart_subreg (mode, iv1.base, comp_mode); | |
f9cce2dc | 2509 | may_xform = simplify_gen_relational (cond, SImode, mode, |
2510 | tmp, bound); | |
a6629703 | 2511 | may_not_xform = simplify_gen_relational (reverse_condition (cond), |
2512 | SImode, mode, | |
2513 | tmp, bound); | |
f9cce2dc | 2514 | } |
2515 | } | |
2516 | ||
2517 | if (may_xform != const0_rtx) | |
2518 | { | |
2519 | /* We perform the transformation always provided that it is not | |
2520 | completely senseless. This is OK, as we would need this assumption | |
2521 | to determine the number of iterations anyway. */ | |
2522 | if (may_xform != const_true_rtx) | |
a6629703 | 2523 | { |
2524 | /* If the step is a power of two and the final value we have | |
2525 | computed overflows, the cycle is infinite. Otherwise it | |
2526 | is nontrivial to compute the number of iterations. */ | |
f8f90b50 | 2527 | if (step_is_pow2) |
a6629703 | 2528 | desc->infinite = alloc_EXPR_LIST (0, may_not_xform, |
2529 | desc->infinite); | |
2530 | else | |
2531 | desc->assumptions = alloc_EXPR_LIST (0, may_xform, | |
2532 | desc->assumptions); | |
2533 | } | |
f9cce2dc | 2534 | |
2535 | /* We are going to lose some information about upper bound on | |
2536 | number of iterations in this step, so record the information | |
2537 | here. */ | |
2538 | inc = INTVAL (iv0.step) - INTVAL (iv1.step); | |
971ba038 | 2539 | if (CONST_INT_P (iv1.base)) |
f9cce2dc | 2540 | up = INTVAL (iv1.base); |
2541 | else | |
a6629703 | 2542 | up = INTVAL (mode_mmax) - inc; |
971ba038 | 2543 | down = INTVAL (CONST_INT_P (iv0.base) |
a6629703 | 2544 | ? iv0.base |
2545 | : mode_mmin); | |
8fb72e03 | 2546 | max = (up - down) / inc + 1; |
2547 | if (!desc->niter_max | |
2548 | || max < desc->niter_max) | |
2549 | desc->niter_max = max; | |
f9cce2dc | 2550 | |
2551 | if (iv0.step == const0_rtx) | |
2552 | { | |
2553 | iv0.base = simplify_gen_binary (PLUS, comp_mode, iv0.base, delta); | |
2554 | iv0.base = simplify_gen_binary (MINUS, comp_mode, iv0.base, step); | |
2555 | } | |
2556 | else | |
2557 | { | |
2558 | iv1.base = simplify_gen_binary (MINUS, comp_mode, iv1.base, delta); | |
2559 | iv1.base = simplify_gen_binary (PLUS, comp_mode, iv1.base, step); | |
2560 | } | |
2561 | ||
c0efe3c3 | 2562 | tmp0 = lowpart_subreg (mode, iv0.base, comp_mode); |
2563 | tmp1 = lowpart_subreg (mode, iv1.base, comp_mode); | |
f9cce2dc | 2564 | assumption = simplify_gen_relational (reverse_condition (cond), |
2565 | SImode, mode, tmp0, tmp1); | |
2566 | if (assumption == const_true_rtx) | |
f30c7901 | 2567 | goto zero_iter_simplify; |
f9cce2dc | 2568 | else if (assumption != const0_rtx) |
2569 | desc->noloop_assumptions = | |
2570 | alloc_EXPR_LIST (0, assumption, desc->noloop_assumptions); | |
2571 | cond = NE; | |
2572 | } | |
2573 | } | |
2574 | ||
2575 | /* Count the number of iterations. */ | |
2576 | if (cond == NE) | |
2577 | { | |
2578 | /* Everything we do here is just arithmetics modulo size of mode. This | |
2579 | makes us able to do more involved computations of number of iterations | |
2580 | than in other cases. First transform the condition into shape | |
2581 | s * i <> c, with s positive. */ | |
2582 | iv1.base = simplify_gen_binary (MINUS, comp_mode, iv1.base, iv0.base); | |
2583 | iv0.base = const0_rtx; | |
2584 | iv0.step = simplify_gen_binary (MINUS, comp_mode, iv0.step, iv1.step); | |
2585 | iv1.step = const0_rtx; | |
2586 | if (INTVAL (iv0.step) < 0) | |
2587 | { | |
2588 | iv0.step = simplify_gen_unary (NEG, comp_mode, iv0.step, mode); | |
2589 | iv1.base = simplify_gen_unary (NEG, comp_mode, iv1.base, mode); | |
2590 | } | |
c0efe3c3 | 2591 | iv0.step = lowpart_subreg (mode, iv0.step, comp_mode); |
f9cce2dc | 2592 | |
2593 | /* Let nsd (s, size of mode) = d. If d does not divide c, the loop | |
2594 | is infinite. Otherwise, the number of iterations is | |
2595 | (inverse(s/d) * (c/d)) mod (size of mode/d). */ | |
2596 | s = INTVAL (iv0.step); d = 1; | |
2597 | while (s % 2 != 1) | |
2598 | { | |
2599 | s /= 2; | |
2600 | d *= 2; | |
2601 | size--; | |
2602 | } | |
2603 | bound = GEN_INT (((unsigned HOST_WIDEST_INT) 1 << (size - 1 ) << 1) - 1); | |
2604 | ||
c0efe3c3 | 2605 | tmp1 = lowpart_subreg (mode, iv1.base, comp_mode); |
f9cce2dc | 2606 | tmp = simplify_gen_binary (UMOD, mode, tmp1, GEN_INT (d)); |
2607 | assumption = simplify_gen_relational (NE, SImode, mode, tmp, const0_rtx); | |
2608 | desc->infinite = alloc_EXPR_LIST (0, assumption, desc->infinite); | |
2609 | ||
2610 | tmp = simplify_gen_binary (UDIV, mode, tmp1, GEN_INT (d)); | |
a6629703 | 2611 | inv = inverse (s, size); |
69e41517 | 2612 | tmp = simplify_gen_binary (MULT, mode, tmp, gen_int_mode (inv, mode)); |
f9cce2dc | 2613 | desc->niter_expr = simplify_gen_binary (AND, mode, tmp, bound); |
2614 | } | |
2615 | else | |
2616 | { | |
2617 | if (iv1.step == const0_rtx) | |
2618 | /* Condition in shape a + s * i <= b | |
2619 | We must know that b + s does not overflow and a <= b + s and then we | |
2620 | can compute number of iterations as (b + s - a) / s. (It might | |
2621 | seem that we in fact could be more clever about testing the b + s | |
2622 | overflow condition using some information about b - a mod s, | |
2623 | but it was already taken into account during LE -> NE transform). */ | |
2624 | { | |
2625 | step = iv0.step; | |
c0efe3c3 | 2626 | tmp0 = lowpart_subreg (mode, iv0.base, comp_mode); |
2627 | tmp1 = lowpart_subreg (mode, iv1.base, comp_mode); | |
f9cce2dc | 2628 | |
a6629703 | 2629 | bound = simplify_gen_binary (MINUS, mode, mode_mmax, |
c0efe3c3 | 2630 | lowpart_subreg (mode, step, |
2631 | comp_mode)); | |
f8f90b50 | 2632 | if (step_is_pow2) |
2633 | { | |
2634 | rtx t0, t1; | |
2635 | ||
2636 | /* If s is power of 2, we know that the loop is infinite if | |
2637 | a % s <= b % s and b + s overflows. */ | |
2638 | assumption = simplify_gen_relational (reverse_condition (cond), | |
2639 | SImode, mode, | |
2640 | tmp1, bound); | |
2641 | ||
2642 | t0 = simplify_gen_binary (UMOD, mode, copy_rtx (tmp0), step); | |
2643 | t1 = simplify_gen_binary (UMOD, mode, copy_rtx (tmp1), step); | |
2644 | tmp = simplify_gen_relational (cond, SImode, mode, t0, t1); | |
2645 | assumption = simplify_gen_binary (AND, SImode, assumption, tmp); | |
2646 | desc->infinite = | |
2647 | alloc_EXPR_LIST (0, assumption, desc->infinite); | |
2648 | } | |
2649 | else | |
2650 | { | |
2651 | assumption = simplify_gen_relational (cond, SImode, mode, | |
2652 | tmp1, bound); | |
2653 | desc->assumptions = | |
2654 | alloc_EXPR_LIST (0, assumption, desc->assumptions); | |
2655 | } | |
f9cce2dc | 2656 | |
2657 | tmp = simplify_gen_binary (PLUS, comp_mode, iv1.base, iv0.step); | |
c0efe3c3 | 2658 | tmp = lowpart_subreg (mode, tmp, comp_mode); |
f9cce2dc | 2659 | assumption = simplify_gen_relational (reverse_condition (cond), |
2660 | SImode, mode, tmp0, tmp); | |
2661 | ||
2662 | delta = simplify_gen_binary (PLUS, mode, tmp1, step); | |
2663 | delta = simplify_gen_binary (MINUS, mode, delta, tmp0); | |
2664 | } | |
2665 | else | |
2666 | { | |
2667 | /* Condition in shape a <= b - s * i | |
2668 | We must know that a - s does not overflow and a - s <= b and then | |
2669 | we can again compute number of iterations as (b - (a - s)) / s. */ | |
2670 | step = simplify_gen_unary (NEG, mode, iv1.step, mode); | |
c0efe3c3 | 2671 | tmp0 = lowpart_subreg (mode, iv0.base, comp_mode); |
2672 | tmp1 = lowpart_subreg (mode, iv1.base, comp_mode); | |
f9cce2dc | 2673 | |
58379c86 | 2674 | bound = simplify_gen_binary (PLUS, mode, mode_mmin, |
c0efe3c3 | 2675 | lowpart_subreg (mode, step, comp_mode)); |
f8f90b50 | 2676 | if (step_is_pow2) |
2677 | { | |
2678 | rtx t0, t1; | |
2679 | ||
2680 | /* If s is power of 2, we know that the loop is infinite if | |
2681 | a % s <= b % s and a - s overflows. */ | |
2682 | assumption = simplify_gen_relational (reverse_condition (cond), | |
2683 | SImode, mode, | |
2684 | bound, tmp0); | |
2685 | ||
2686 | t0 = simplify_gen_binary (UMOD, mode, copy_rtx (tmp0), step); | |
2687 | t1 = simplify_gen_binary (UMOD, mode, copy_rtx (tmp1), step); | |
2688 | tmp = simplify_gen_relational (cond, SImode, mode, t0, t1); | |
2689 | assumption = simplify_gen_binary (AND, SImode, assumption, tmp); | |
2690 | desc->infinite = | |
2691 | alloc_EXPR_LIST (0, assumption, desc->infinite); | |
2692 | } | |
2693 | else | |
2694 | { | |
2695 | assumption = simplify_gen_relational (cond, SImode, mode, | |
2696 | bound, tmp0); | |
2697 | desc->assumptions = | |
2698 | alloc_EXPR_LIST (0, assumption, desc->assumptions); | |
2699 | } | |
f9cce2dc | 2700 | |
2701 | tmp = simplify_gen_binary (PLUS, comp_mode, iv0.base, iv1.step); | |
c0efe3c3 | 2702 | tmp = lowpart_subreg (mode, tmp, comp_mode); |
f9cce2dc | 2703 | assumption = simplify_gen_relational (reverse_condition (cond), |
2704 | SImode, mode, | |
2705 | tmp, tmp1); | |
2706 | delta = simplify_gen_binary (MINUS, mode, tmp0, step); | |
2707 | delta = simplify_gen_binary (MINUS, mode, tmp1, delta); | |
2708 | } | |
2709 | if (assumption == const_true_rtx) | |
f30c7901 | 2710 | goto zero_iter_simplify; |
f9cce2dc | 2711 | else if (assumption != const0_rtx) |
2712 | desc->noloop_assumptions = | |
2713 | alloc_EXPR_LIST (0, assumption, desc->noloop_assumptions); | |
2714 | delta = simplify_gen_binary (UDIV, mode, delta, step); | |
2715 | desc->niter_expr = delta; | |
2716 | } | |
2717 | ||
1e8e4a1d | 2718 | old_niter = desc->niter_expr; |
2719 | ||
f9cce2dc | 2720 | simplify_using_initial_values (loop, AND, &desc->assumptions); |
2721 | if (desc->assumptions | |
2722 | && XEXP (desc->assumptions, 0) == const0_rtx) | |
2723 | goto fail; | |
2724 | simplify_using_initial_values (loop, IOR, &desc->noloop_assumptions); | |
2725 | simplify_using_initial_values (loop, IOR, &desc->infinite); | |
21f1e711 | 2726 | simplify_using_initial_values (loop, UNKNOWN, &desc->niter_expr); |
f9cce2dc | 2727 | |
2728 | /* Rerun the simplification. Consider code (created by copying loop headers) | |
2729 | ||
2730 | i = 0; | |
2731 | ||
2732 | if (0 < n) | |
2733 | { | |
2734 | do | |
2735 | { | |
2736 | i++; | |
2737 | } while (i < n); | |
2738 | } | |
2739 | ||
2740 | The first pass determines that i = 0, the second pass uses it to eliminate | |
2741 | noloop assumption. */ | |
2742 | ||
2743 | simplify_using_initial_values (loop, AND, &desc->assumptions); | |
2744 | if (desc->assumptions | |
2745 | && XEXP (desc->assumptions, 0) == const0_rtx) | |
2746 | goto fail; | |
2747 | simplify_using_initial_values (loop, IOR, &desc->noloop_assumptions); | |
2748 | simplify_using_initial_values (loop, IOR, &desc->infinite); | |
21f1e711 | 2749 | simplify_using_initial_values (loop, UNKNOWN, &desc->niter_expr); |
f9cce2dc | 2750 | |
2d49f824 | 2751 | if (desc->noloop_assumptions |
2752 | && XEXP (desc->noloop_assumptions, 0) == const_true_rtx) | |
2753 | goto zero_iter; | |
2754 | ||
971ba038 | 2755 | if (CONST_INT_P (desc->niter_expr)) |
f9cce2dc | 2756 | { |
2757 | unsigned HOST_WIDEST_INT val = INTVAL (desc->niter_expr); | |
2758 | ||
2759 | desc->const_iter = true; | |
2760 | desc->niter_max = desc->niter = val & GET_MODE_MASK (desc->mode); | |
2761 | } | |
1e8e4a1d | 2762 | else |
2763 | { | |
8fb72e03 | 2764 | max = determine_max_iter (loop, desc, old_niter); |
2765 | if (!desc->niter_max | |
2766 | || max < desc->niter_max) | |
2767 | desc->niter_max = max; | |
1e8e4a1d | 2768 | |
2769 | /* simplify_using_initial_values does a copy propagation on the registers | |
2770 | in the expression for the number of iterations. This prolongs life | |
2771 | ranges of registers and increases register pressure, and usually | |
2772 | brings no gain (and if it happens to do, the cse pass will take care | |
2773 | of it anyway). So prevent this behavior, unless it enabled us to | |
2774 | derive that the number of iterations is a constant. */ | |
2775 | desc->niter_expr = old_niter; | |
2776 | } | |
f9cce2dc | 2777 | |
2778 | return; | |
2779 | ||
f30c7901 | 2780 | zero_iter_simplify: |
2781 | /* Simplify the assumptions. */ | |
2782 | simplify_using_initial_values (loop, AND, &desc->assumptions); | |
2783 | if (desc->assumptions | |
2784 | && XEXP (desc->assumptions, 0) == const0_rtx) | |
2785 | goto fail; | |
2786 | simplify_using_initial_values (loop, IOR, &desc->infinite); | |
f9cce2dc | 2787 | |
f30c7901 | 2788 | /* Fallthru. */ |
f9cce2dc | 2789 | zero_iter: |
2790 | desc->const_iter = true; | |
2791 | desc->niter = 0; | |
2792 | desc->niter_max = 0; | |
f30c7901 | 2793 | desc->noloop_assumptions = NULL_RTX; |
f9cce2dc | 2794 | desc->niter_expr = const0_rtx; |
2795 | return; | |
f30c7901 | 2796 | |
2797 | fail: | |
2798 | desc->simple_p = false; | |
2799 | return; | |
f9cce2dc | 2800 | } |
2801 | ||
2802 | /* Checks whether E is a simple exit from LOOP and stores its description | |
9c1ccc0f | 2803 | into DESC. */ |
f9cce2dc | 2804 | |
2805 | static void | |
2806 | check_simple_exit (struct loop *loop, edge e, struct niter_desc *desc) | |
2807 | { | |
2808 | basic_block exit_bb; | |
2809 | rtx condition, at; | |
cd665a06 | 2810 | edge ein; |
f9cce2dc | 2811 | |
2812 | exit_bb = e->src; | |
2813 | desc->simple_p = false; | |
2814 | ||
2815 | /* It must belong directly to the loop. */ | |
2816 | if (exit_bb->loop_father != loop) | |
2817 | return; | |
2818 | ||
2819 | /* It must be tested (at least) once during any iteration. */ | |
2820 | if (!dominated_by_p (CDI_DOMINATORS, loop->latch, exit_bb)) | |
2821 | return; | |
2822 | ||
2823 | /* It must end in a simple conditional jump. */ | |
2824 | if (!any_condjump_p (BB_END (exit_bb))) | |
2825 | return; | |
2826 | ||
cd665a06 | 2827 | ein = EDGE_SUCC (exit_bb, 0); |
2828 | if (ein == e) | |
2829 | ein = EDGE_SUCC (exit_bb, 1); | |
f9cce2dc | 2830 | |
2831 | desc->out_edge = e; | |
cd665a06 | 2832 | desc->in_edge = ein; |
f9cce2dc | 2833 | |
2834 | /* Test whether the condition is suitable. */ | |
cd665a06 | 2835 | if (!(condition = get_condition (BB_END (ein->src), &at, false, false))) |
f9cce2dc | 2836 | return; |
2837 | ||
cd665a06 | 2838 | if (ein->flags & EDGE_FALLTHRU) |
f9cce2dc | 2839 | { |
2840 | condition = reversed_condition (condition); | |
2841 | if (!condition) | |
2842 | return; | |
2843 | } | |
2844 | ||
2845 | /* Check that we are able to determine number of iterations and fill | |
2846 | in information about it. */ | |
2847 | iv_number_of_iterations (loop, at, condition, desc); | |
2848 | } | |
2849 | ||
9c1ccc0f | 2850 | /* Finds a simple exit of LOOP and stores its description into DESC. */ |
f9cce2dc | 2851 | |
2852 | void | |
2853 | find_simple_exit (struct loop *loop, struct niter_desc *desc) | |
2854 | { | |
2855 | unsigned i; | |
2856 | basic_block *body; | |
2857 | edge e; | |
2858 | struct niter_desc act; | |
2859 | bool any = false; | |
cd665a06 | 2860 | edge_iterator ei; |
f9cce2dc | 2861 | |
2862 | desc->simple_p = false; | |
2863 | body = get_loop_body (loop); | |
2864 | ||
2865 | for (i = 0; i < loop->num_nodes; i++) | |
2866 | { | |
cd665a06 | 2867 | FOR_EACH_EDGE (e, ei, body[i]->succs) |
f9cce2dc | 2868 | { |
2869 | if (flow_bb_inside_loop_p (loop, e->dest)) | |
2870 | continue; | |
48e1416a | 2871 | |
f9cce2dc | 2872 | check_simple_exit (loop, e, &act); |
2873 | if (!act.simple_p) | |
2874 | continue; | |
2875 | ||
f9cce2dc | 2876 | if (!any) |
2877 | any = true; | |
f30c7901 | 2878 | else |
2879 | { | |
2880 | /* Prefer constant iterations; the less the better. */ | |
2881 | if (!act.const_iter | |
2882 | || (desc->const_iter && act.niter >= desc->niter)) | |
2883 | continue; | |
2884 | ||
2885 | /* Also if the actual exit may be infinite, while the old one | |
2886 | not, prefer the old one. */ | |
2887 | if (act.infinite && !desc->infinite) | |
2888 | continue; | |
2889 | } | |
48e1416a | 2890 | |
f9cce2dc | 2891 | *desc = act; |
2892 | } | |
2893 | } | |
2894 | ||
450d042a | 2895 | if (dump_file) |
f9cce2dc | 2896 | { |
2897 | if (desc->simple_p) | |
2898 | { | |
450d042a | 2899 | fprintf (dump_file, "Loop %d is simple:\n", loop->num); |
2900 | fprintf (dump_file, " simple exit %d -> %d\n", | |
f9cce2dc | 2901 | desc->out_edge->src->index, |
2902 | desc->out_edge->dest->index); | |
2903 | if (desc->assumptions) | |
2904 | { | |
450d042a | 2905 | fprintf (dump_file, " assumptions: "); |
2906 | print_rtl (dump_file, desc->assumptions); | |
2907 | fprintf (dump_file, "\n"); | |
f9cce2dc | 2908 | } |
2909 | if (desc->noloop_assumptions) | |
2910 | { | |
450d042a | 2911 | fprintf (dump_file, " does not roll if: "); |
2912 | print_rtl (dump_file, desc->noloop_assumptions); | |
2913 | fprintf (dump_file, "\n"); | |
f9cce2dc | 2914 | } |
2915 | if (desc->infinite) | |
2916 | { | |
450d042a | 2917 | fprintf (dump_file, " infinite if: "); |
2918 | print_rtl (dump_file, desc->infinite); | |
2919 | fprintf (dump_file, "\n"); | |
f9cce2dc | 2920 | } |
2921 | ||
450d042a | 2922 | fprintf (dump_file, " number of iterations: "); |
2923 | print_rtl (dump_file, desc->niter_expr); | |
2924 | fprintf (dump_file, "\n"); | |
f9cce2dc | 2925 | |
450d042a | 2926 | fprintf (dump_file, " upper bound: "); |
2927 | fprintf (dump_file, HOST_WIDEST_INT_PRINT_DEC, desc->niter_max); | |
2928 | fprintf (dump_file, "\n"); | |
f9cce2dc | 2929 | } |
2930 | else | |
450d042a | 2931 | fprintf (dump_file, "Loop %d is not simple.\n", loop->num); |
f9cce2dc | 2932 | } |
2933 | ||
2934 | free (body); | |
2935 | } | |
2936 | ||
2937 | /* Creates a simple loop description of LOOP if it was not computed | |
2938 | already. */ | |
2939 | ||
2940 | struct niter_desc * | |
2941 | get_simple_loop_desc (struct loop *loop) | |
2942 | { | |
2943 | struct niter_desc *desc = simple_loop_desc (loop); | |
2944 | ||
2945 | if (desc) | |
2946 | return desc; | |
2947 | ||
242753ba | 2948 | /* At least desc->infinite is not always initialized by |
2949 | find_simple_loop_exit. */ | |
2950 | desc = XCNEW (struct niter_desc); | |
f9cce2dc | 2951 | iv_analysis_loop_init (loop); |
2952 | find_simple_exit (loop, desc); | |
2953 | loop->aux = desc; | |
2954 | ||
7e3cc681 | 2955 | if (desc->simple_p && (desc->assumptions || desc->infinite)) |
2956 | { | |
48e1416a | 2957 | const char *wording; |
7e3cc681 | 2958 | |
48e1416a | 2959 | /* Assume that no overflow happens and that the loop is finite. |
7e3cc681 | 2960 | We already warned at the tree level if we ran optimizations there. */ |
2961 | if (!flag_tree_loop_optimize && warn_unsafe_loop_optimizations) | |
2962 | { | |
2963 | if (desc->infinite) | |
2964 | { | |
48e1416a | 2965 | wording = |
7e3cc681 | 2966 | flag_unsafe_loop_optimizations |
2967 | ? N_("assuming that the loop is not infinite") | |
2968 | : N_("cannot optimize possibly infinite loops"); | |
2969 | warning (OPT_Wunsafe_loop_optimizations, "%s", | |
2970 | gettext (wording)); | |
2971 | } | |
2972 | if (desc->assumptions) | |
2973 | { | |
48e1416a | 2974 | wording = |
7e3cc681 | 2975 | flag_unsafe_loop_optimizations |
2976 | ? N_("assuming that the loop counter does not overflow") | |
2977 | : N_("cannot optimize loop, the loop counter may overflow"); | |
2978 | warning (OPT_Wunsafe_loop_optimizations, "%s", | |
2979 | gettext (wording)); | |
2980 | } | |
2981 | } | |
2982 | ||
2983 | if (flag_unsafe_loop_optimizations) | |
2984 | { | |
2985 | desc->assumptions = NULL_RTX; | |
2986 | desc->infinite = NULL_RTX; | |
2987 | } | |
2988 | } | |
2989 | ||
f9cce2dc | 2990 | return desc; |
2991 | } | |
2992 | ||
2993 | /* Releases simple loop description for LOOP. */ | |
2994 | ||
2995 | void | |
2996 | free_simple_loop_desc (struct loop *loop) | |
2997 | { | |
2998 | struct niter_desc *desc = simple_loop_desc (loop); | |
2999 | ||
3000 | if (!desc) | |
3001 | return; | |
3002 | ||
3003 | free (desc); | |
3004 | loop->aux = NULL; | |
3005 | } |