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1a6a0f2a | 1 | /* Decompose multiword subregs. |
2 | Copyright (C) 2007 Free Software Foundation, Inc. | |
3 | Contributed by Richard Henderson <rth@redhat.com> | |
4 | Ian Lance Taylor <iant@google.com> | |
5 | ||
6 | This file is part of GCC. | |
7 | ||
8 | GCC is free software; you can redistribute it and/or modify it under | |
9 | the terms of the GNU General Public License as published by the Free | |
10 | Software Foundation; either version 2, or (at your option) any later | |
11 | version. | |
12 | ||
13 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
14 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GCC; see the file COPYING. If not, write to the Free | |
20 | Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA | |
21 | 02110-1301, USA. */ | |
22 | ||
23 | #include "config.h" | |
24 | #include "system.h" | |
25 | #include "coretypes.h" | |
26 | #include "machmode.h" | |
27 | #include "tm.h" | |
28 | #include "rtl.h" | |
29 | #include "tm_p.h" | |
30 | #include "timevar.h" | |
31 | #include "flags.h" | |
32 | #include "insn-config.h" | |
33 | #include "obstack.h" | |
34 | #include "basic-block.h" | |
35 | #include "recog.h" | |
36 | #include "bitmap.h" | |
37 | #include "expr.h" | |
db1c50be | 38 | #include "except.h" |
1a6a0f2a | 39 | #include "regs.h" |
40 | #include "tree-pass.h" | |
3072d30e | 41 | #include "df.h" |
1a6a0f2a | 42 | |
43 | #ifdef STACK_GROWS_DOWNWARD | |
44 | # undef STACK_GROWS_DOWNWARD | |
45 | # define STACK_GROWS_DOWNWARD 1 | |
46 | #else | |
47 | # define STACK_GROWS_DOWNWARD 0 | |
48 | #endif | |
49 | ||
50 | DEF_VEC_P (bitmap); | |
51 | DEF_VEC_ALLOC_P (bitmap,heap); | |
52 | ||
53 | /* Decompose multi-word pseudo-registers into individual | |
54 | pseudo-registers when possible. This is possible when all the uses | |
55 | of a multi-word register are via SUBREG, or are copies of the | |
56 | register to another location. Breaking apart the register permits | |
57 | more CSE and permits better register allocation. */ | |
58 | ||
59 | /* Bit N in this bitmap is set if regno N is used in a context in | |
60 | which we can decompose it. */ | |
61 | static bitmap decomposable_context; | |
62 | ||
63 | /* Bit N in this bitmap is set if regno N is used in a context in | |
64 | which it can not be decomposed. */ | |
65 | static bitmap non_decomposable_context; | |
66 | ||
67 | /* Bit N in the bitmap in element M of this array is set if there is a | |
68 | copy from reg M to reg N. */ | |
69 | static VEC(bitmap,heap) *reg_copy_graph; | |
70 | ||
67c3f580 | 71 | /* Return whether X is a simple object which we can take a word_mode |
72 | subreg of. */ | |
73 | ||
74 | static bool | |
75 | simple_move_operand (rtx x) | |
76 | { | |
77 | if (GET_CODE (x) == SUBREG) | |
78 | x = SUBREG_REG (x); | |
79 | ||
80 | if (!OBJECT_P (x)) | |
81 | return false; | |
82 | ||
83 | if (GET_CODE (x) == LABEL_REF | |
84 | || GET_CODE (x) == SYMBOL_REF | |
ab9eaa97 | 85 | || GET_CODE (x) == HIGH |
86 | || GET_CODE (x) == CONST) | |
67c3f580 | 87 | return false; |
88 | ||
89 | if (MEM_P (x) | |
90 | && (MEM_VOLATILE_P (x) | |
91 | || mode_dependent_address_p (XEXP (x, 0)))) | |
92 | return false; | |
93 | ||
94 | return true; | |
95 | } | |
96 | ||
1a6a0f2a | 97 | /* If INSN is a single set between two objects, return the single set. |
98 | Such an insn can always be decomposed. INSN should have been | |
99 | passed to recog and extract_insn before this is called. */ | |
100 | ||
101 | static rtx | |
102 | simple_move (rtx insn) | |
103 | { | |
104 | rtx x; | |
105 | rtx set; | |
106 | enum machine_mode mode; | |
107 | ||
108 | if (recog_data.n_operands != 2) | |
109 | return NULL_RTX; | |
110 | ||
111 | set = single_set (insn); | |
112 | if (!set) | |
113 | return NULL_RTX; | |
114 | ||
115 | x = SET_DEST (set); | |
116 | if (x != recog_data.operand[0] && x != recog_data.operand[1]) | |
117 | return NULL_RTX; | |
67c3f580 | 118 | if (!simple_move_operand (x)) |
1a6a0f2a | 119 | return NULL_RTX; |
120 | ||
121 | x = SET_SRC (set); | |
122 | if (x != recog_data.operand[0] && x != recog_data.operand[1]) | |
123 | return NULL_RTX; | |
67c3f580 | 124 | /* For the src we can handle ASM_OPERANDS, and it is beneficial for |
125 | things like x86 rdtsc which returns a DImode value. */ | |
126 | if (GET_CODE (x) != ASM_OPERANDS | |
127 | && !simple_move_operand (x)) | |
1a6a0f2a | 128 | return NULL_RTX; |
129 | ||
130 | /* We try to decompose in integer modes, to avoid generating | |
131 | inefficient code copying between integer and floating point | |
132 | registers. That means that we can't decompose if this is a | |
133 | non-integer mode for which there is no integer mode of the same | |
134 | size. */ | |
135 | mode = GET_MODE (SET_SRC (set)); | |
136 | if (!SCALAR_INT_MODE_P (mode) | |
137 | && (mode_for_size (GET_MODE_SIZE (mode) * BITS_PER_UNIT, MODE_INT, 0) | |
138 | == BLKmode)) | |
139 | return NULL_RTX; | |
140 | ||
5e016dfc | 141 | /* Reject PARTIAL_INT modes. They are used for processor specific |
142 | purposes and it's probably best not to tamper with them. */ | |
143 | if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT) | |
144 | return NULL_RTX; | |
145 | ||
1a6a0f2a | 146 | return set; |
147 | } | |
148 | ||
149 | /* If SET is a copy from one multi-word pseudo-register to another, | |
150 | record that in reg_copy_graph. Return whether it is such a | |
151 | copy. */ | |
152 | ||
153 | static bool | |
154 | find_pseudo_copy (rtx set) | |
155 | { | |
156 | rtx dest = SET_DEST (set); | |
157 | rtx src = SET_SRC (set); | |
158 | unsigned int rd, rs; | |
159 | bitmap b; | |
160 | ||
161 | if (!REG_P (dest) || !REG_P (src)) | |
162 | return false; | |
163 | ||
164 | rd = REGNO (dest); | |
165 | rs = REGNO (src); | |
166 | if (HARD_REGISTER_NUM_P (rd) || HARD_REGISTER_NUM_P (rs)) | |
167 | return false; | |
168 | ||
169 | if (GET_MODE_SIZE (GET_MODE (dest)) <= UNITS_PER_WORD) | |
170 | return false; | |
171 | ||
172 | b = VEC_index (bitmap, reg_copy_graph, rs); | |
173 | if (b == NULL) | |
174 | { | |
175 | b = BITMAP_ALLOC (NULL); | |
176 | VEC_replace (bitmap, reg_copy_graph, rs, b); | |
177 | } | |
178 | ||
179 | bitmap_set_bit (b, rd); | |
180 | ||
181 | return true; | |
182 | } | |
183 | ||
184 | /* Look through the registers in DECOMPOSABLE_CONTEXT. For each case | |
185 | where they are copied to another register, add the register to | |
186 | which they are copied to DECOMPOSABLE_CONTEXT. Use | |
187 | NON_DECOMPOSABLE_CONTEXT to limit this--we don't bother to track | |
188 | copies of registers which are in NON_DECOMPOSABLE_CONTEXT. */ | |
189 | ||
190 | static void | |
191 | propagate_pseudo_copies (void) | |
192 | { | |
193 | bitmap queue, propagate; | |
194 | ||
195 | queue = BITMAP_ALLOC (NULL); | |
196 | propagate = BITMAP_ALLOC (NULL); | |
197 | ||
198 | bitmap_copy (queue, decomposable_context); | |
199 | do | |
200 | { | |
201 | bitmap_iterator iter; | |
202 | unsigned int i; | |
203 | ||
204 | bitmap_clear (propagate); | |
205 | ||
206 | EXECUTE_IF_SET_IN_BITMAP (queue, 0, i, iter) | |
207 | { | |
208 | bitmap b = VEC_index (bitmap, reg_copy_graph, i); | |
209 | if (b) | |
210 | bitmap_ior_and_compl_into (propagate, b, non_decomposable_context); | |
211 | } | |
212 | ||
213 | bitmap_and_compl (queue, propagate, decomposable_context); | |
214 | bitmap_ior_into (decomposable_context, propagate); | |
215 | } | |
216 | while (!bitmap_empty_p (queue)); | |
217 | ||
218 | BITMAP_FREE (queue); | |
219 | BITMAP_FREE (propagate); | |
220 | } | |
221 | ||
222 | /* A pointer to one of these values is passed to | |
223 | find_decomposable_subregs via for_each_rtx. */ | |
224 | ||
225 | enum classify_move_insn | |
226 | { | |
227 | /* Not a simple move from one location to another. */ | |
228 | NOT_SIMPLE_MOVE, | |
229 | /* A simple move from one pseudo-register to another with no | |
230 | REG_RETVAL note. */ | |
231 | SIMPLE_PSEUDO_REG_MOVE, | |
232 | /* A simple move involving a non-pseudo-register, or from one | |
233 | pseudo-register to another with a REG_RETVAL note. */ | |
234 | SIMPLE_MOVE | |
235 | }; | |
236 | ||
237 | /* This is called via for_each_rtx. If we find a SUBREG which we | |
238 | could use to decompose a pseudo-register, set a bit in | |
239 | DECOMPOSABLE_CONTEXT. If we find an unadorned register which is | |
240 | not a simple pseudo-register copy, DATA will point at the type of | |
241 | move, and we set a bit in DECOMPOSABLE_CONTEXT or | |
242 | NON_DECOMPOSABLE_CONTEXT as appropriate. */ | |
243 | ||
244 | static int | |
245 | find_decomposable_subregs (rtx *px, void *data) | |
246 | { | |
247 | enum classify_move_insn *pcmi = (enum classify_move_insn *) data; | |
248 | rtx x = *px; | |
249 | ||
250 | if (x == NULL_RTX) | |
251 | return 0; | |
252 | ||
253 | if (GET_CODE (x) == SUBREG) | |
254 | { | |
255 | rtx inner = SUBREG_REG (x); | |
256 | unsigned int regno, outer_size, inner_size, outer_words, inner_words; | |
257 | ||
258 | if (!REG_P (inner)) | |
259 | return 0; | |
260 | ||
261 | regno = REGNO (inner); | |
262 | if (HARD_REGISTER_NUM_P (regno)) | |
263 | return -1; | |
264 | ||
265 | outer_size = GET_MODE_SIZE (GET_MODE (x)); | |
266 | inner_size = GET_MODE_SIZE (GET_MODE (inner)); | |
267 | outer_words = (outer_size + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
268 | inner_words = (inner_size + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
269 | ||
270 | /* We only try to decompose single word subregs of multi-word | |
271 | registers. When we find one, we return -1 to avoid iterating | |
272 | over the inner register. | |
273 | ||
274 | ??? This doesn't allow, e.g., DImode subregs of TImode values | |
275 | on 32-bit targets. We would need to record the way the | |
276 | pseudo-register was used, and only decompose if all the uses | |
277 | were the same number and size of pieces. Hopefully this | |
278 | doesn't happen much. */ | |
279 | ||
280 | if (outer_words == 1 && inner_words > 1) | |
281 | { | |
282 | bitmap_set_bit (decomposable_context, regno); | |
283 | return -1; | |
284 | } | |
4e7a1eb8 | 285 | |
286 | /* If this is a cast from one mode to another, where the modes | |
287 | have the same size, and they are not tieable, then mark this | |
288 | register as non-decomposable. If we decompose it we are | |
289 | likely to mess up whatever the backend is trying to do. */ | |
290 | if (outer_words > 1 | |
291 | && outer_size == inner_size | |
292 | && !MODES_TIEABLE_P (GET_MODE (x), GET_MODE (inner))) | |
293 | { | |
294 | bitmap_set_bit (non_decomposable_context, regno); | |
295 | return -1; | |
296 | } | |
1a6a0f2a | 297 | } |
67c3f580 | 298 | else if (REG_P (x)) |
1a6a0f2a | 299 | { |
300 | unsigned int regno; | |
301 | ||
302 | /* We will see an outer SUBREG before we see the inner REG, so | |
303 | when we see a plain REG here it means a direct reference to | |
304 | the register. | |
305 | ||
306 | If this is not a simple copy from one location to another, | |
307 | then we can not decompose this register. If this is a simple | |
308 | copy from one pseudo-register to another, with no REG_RETVAL | |
309 | note, and the mode is right, then we mark the register as | |
310 | decomposable. Otherwise we don't say anything about this | |
311 | register--it could be decomposed, but whether that would be | |
312 | profitable depends upon how it is used elsewhere. | |
313 | ||
314 | We only set bits in the bitmap for multi-word | |
315 | pseudo-registers, since those are the only ones we care about | |
316 | and it keeps the size of the bitmaps down. */ | |
317 | ||
318 | regno = REGNO (x); | |
319 | if (!HARD_REGISTER_NUM_P (regno) | |
320 | && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD) | |
321 | { | |
322 | switch (*pcmi) | |
323 | { | |
324 | case NOT_SIMPLE_MOVE: | |
325 | bitmap_set_bit (non_decomposable_context, regno); | |
326 | break; | |
327 | case SIMPLE_PSEUDO_REG_MOVE: | |
328 | if (MODES_TIEABLE_P (GET_MODE (x), word_mode)) | |
329 | bitmap_set_bit (decomposable_context, regno); | |
330 | break; | |
331 | case SIMPLE_MOVE: | |
332 | break; | |
333 | default: | |
334 | gcc_unreachable (); | |
335 | } | |
336 | } | |
337 | } | |
67c3f580 | 338 | else if (MEM_P (x)) |
339 | { | |
340 | enum classify_move_insn cmi_mem = NOT_SIMPLE_MOVE; | |
341 | ||
342 | /* Any registers used in a MEM do not participate in a | |
343 | SIMPLE_MOVE or SIMPLE_PSEUDO_REG_MOVE. Do our own recursion | |
344 | here, and return -1 to block the parent's recursion. */ | |
345 | for_each_rtx (&XEXP (x, 0), find_decomposable_subregs, &cmi_mem); | |
346 | return -1; | |
347 | } | |
1a6a0f2a | 348 | |
349 | return 0; | |
350 | } | |
351 | ||
352 | /* Decompose REGNO into word-sized components. We smash the REG node | |
353 | in place. This ensures that (1) something goes wrong quickly if we | |
354 | fail to make some replacement, and (2) the debug information inside | |
355 | the symbol table is automatically kept up to date. */ | |
356 | ||
357 | static void | |
358 | decompose_register (unsigned int regno) | |
359 | { | |
360 | rtx reg; | |
361 | unsigned int words, i; | |
362 | rtvec v; | |
363 | ||
364 | reg = regno_reg_rtx[regno]; | |
365 | ||
366 | regno_reg_rtx[regno] = NULL_RTX; | |
1a6a0f2a | 367 | |
368 | words = GET_MODE_SIZE (GET_MODE (reg)); | |
369 | words = (words + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
370 | ||
371 | v = rtvec_alloc (words); | |
372 | for (i = 0; i < words; ++i) | |
373 | RTVEC_ELT (v, i) = gen_reg_rtx_offset (reg, word_mode, i * UNITS_PER_WORD); | |
374 | ||
375 | PUT_CODE (reg, CONCATN); | |
376 | XVEC (reg, 0) = v; | |
377 | ||
378 | if (dump_file) | |
379 | { | |
380 | fprintf (dump_file, "; Splitting reg %u ->", regno); | |
381 | for (i = 0; i < words; ++i) | |
382 | fprintf (dump_file, " %u", REGNO (XVECEXP (reg, 0, i))); | |
383 | fputc ('\n', dump_file); | |
384 | } | |
385 | } | |
386 | ||
387 | /* Get a SUBREG of a CONCATN. */ | |
388 | ||
389 | static rtx | |
390 | simplify_subreg_concatn (enum machine_mode outermode, rtx op, | |
391 | unsigned int byte) | |
392 | { | |
393 | unsigned int inner_size; | |
394 | enum machine_mode innermode; | |
395 | rtx part; | |
396 | unsigned int final_offset; | |
397 | ||
398 | gcc_assert (GET_CODE (op) == CONCATN); | |
399 | gcc_assert (byte % GET_MODE_SIZE (outermode) == 0); | |
400 | ||
401 | innermode = GET_MODE (op); | |
402 | gcc_assert (byte < GET_MODE_SIZE (innermode)); | |
403 | gcc_assert (GET_MODE_SIZE (outermode) <= GET_MODE_SIZE (innermode)); | |
404 | ||
405 | inner_size = GET_MODE_SIZE (innermode) / XVECLEN (op, 0); | |
406 | part = XVECEXP (op, 0, byte / inner_size); | |
407 | final_offset = byte % inner_size; | |
408 | if (final_offset + GET_MODE_SIZE (outermode) > inner_size) | |
409 | return NULL_RTX; | |
410 | ||
411 | return simplify_gen_subreg (outermode, part, GET_MODE (part), final_offset); | |
412 | } | |
413 | ||
414 | /* Wrapper around simplify_gen_subreg which handles CONCATN. */ | |
415 | ||
416 | static rtx | |
417 | simplify_gen_subreg_concatn (enum machine_mode outermode, rtx op, | |
418 | enum machine_mode innermode, unsigned int byte) | |
419 | { | |
3fa57b79 | 420 | rtx ret; |
421 | ||
1a6a0f2a | 422 | /* We have to handle generating a SUBREG of a SUBREG of a CONCATN. |
423 | If OP is a SUBREG of a CONCATN, then it must be a simple mode | |
424 | change with the same size and offset 0, or it must extract a | |
425 | part. We shouldn't see anything else here. */ | |
426 | if (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == CONCATN) | |
427 | { | |
428 | rtx op2; | |
429 | ||
430 | if ((GET_MODE_SIZE (GET_MODE (op)) | |
431 | == GET_MODE_SIZE (GET_MODE (SUBREG_REG (op)))) | |
432 | && SUBREG_BYTE (op) == 0) | |
433 | return simplify_gen_subreg_concatn (outermode, SUBREG_REG (op), | |
434 | GET_MODE (SUBREG_REG (op)), byte); | |
435 | ||
436 | op2 = simplify_subreg_concatn (GET_MODE (op), SUBREG_REG (op), | |
437 | SUBREG_BYTE (op)); | |
438 | if (op2 == NULL_RTX) | |
439 | { | |
440 | /* We don't handle paradoxical subregs here. */ | |
441 | gcc_assert (GET_MODE_SIZE (outermode) | |
442 | <= GET_MODE_SIZE (GET_MODE (op))); | |
443 | gcc_assert (GET_MODE_SIZE (GET_MODE (op)) | |
444 | <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (op)))); | |
445 | op2 = simplify_subreg_concatn (outermode, SUBREG_REG (op), | |
446 | byte + SUBREG_BYTE (op)); | |
447 | gcc_assert (op2 != NULL_RTX); | |
448 | return op2; | |
449 | } | |
450 | ||
451 | op = op2; | |
452 | gcc_assert (op != NULL_RTX); | |
453 | gcc_assert (innermode == GET_MODE (op)); | |
454 | } | |
3fa57b79 | 455 | |
1a6a0f2a | 456 | if (GET_CODE (op) == CONCATN) |
457 | return simplify_subreg_concatn (outermode, op, byte); | |
3fa57b79 | 458 | |
459 | ret = simplify_gen_subreg (outermode, op, innermode, byte); | |
460 | ||
461 | /* If we see an insn like (set (reg:DI) (subreg:DI (reg:SI) 0)) then | |
462 | resolve_simple_move will ask for the high part of the paradoxical | |
463 | subreg, which does not have a value. Just return a zero. */ | |
464 | if (ret == NULL_RTX | |
465 | && GET_CODE (op) == SUBREG | |
466 | && SUBREG_BYTE (op) == 0 | |
467 | && (GET_MODE_SIZE (innermode) | |
468 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))))) | |
469 | return CONST0_RTX (outermode); | |
470 | ||
471 | gcc_assert (ret != NULL_RTX); | |
472 | return ret; | |
1a6a0f2a | 473 | } |
474 | ||
475 | /* Return whether we should resolve X into the registers into which it | |
476 | was decomposed. */ | |
477 | ||
478 | static bool | |
479 | resolve_reg_p (rtx x) | |
480 | { | |
481 | return GET_CODE (x) == CONCATN; | |
482 | } | |
483 | ||
484 | /* Return whether X is a SUBREG of a register which we need to | |
485 | resolve. */ | |
486 | ||
487 | static bool | |
488 | resolve_subreg_p (rtx x) | |
489 | { | |
490 | if (GET_CODE (x) != SUBREG) | |
491 | return false; | |
492 | return resolve_reg_p (SUBREG_REG (x)); | |
493 | } | |
494 | ||
495 | /* This is called via for_each_rtx. Look for SUBREGs which need to be | |
496 | decomposed. */ | |
497 | ||
498 | static int | |
499 | resolve_subreg_use (rtx *px, void *data) | |
500 | { | |
501 | rtx insn = (rtx) data; | |
502 | rtx x = *px; | |
503 | ||
504 | if (x == NULL_RTX) | |
505 | return 0; | |
506 | ||
507 | if (resolve_subreg_p (x)) | |
508 | { | |
509 | x = simplify_subreg_concatn (GET_MODE (x), SUBREG_REG (x), | |
510 | SUBREG_BYTE (x)); | |
511 | ||
512 | /* It is possible for a note to contain a reference which we can | |
513 | decompose. In this case, return 1 to the caller to indicate | |
514 | that the note must be removed. */ | |
515 | if (!x) | |
516 | { | |
ccd1ec59 | 517 | gcc_assert (!insn); |
1a6a0f2a | 518 | return 1; |
519 | } | |
520 | ||
521 | validate_change (insn, px, x, 1); | |
522 | return -1; | |
523 | } | |
524 | ||
525 | if (resolve_reg_p (x)) | |
526 | { | |
527 | /* Return 1 to the caller to indicate that we found a direct | |
528 | reference to a register which is being decomposed. This can | |
529 | happen inside notes. */ | |
530 | gcc_assert (!insn); | |
531 | return 1; | |
532 | } | |
533 | ||
534 | return 0; | |
535 | } | |
536 | ||
97bb2849 | 537 | /* We are deleting INSN. Move any EH_REGION notes to INSNS. */ |
538 | ||
539 | static void | |
540 | move_eh_region_note (rtx insn, rtx insns) | |
541 | { | |
542 | rtx note, p; | |
543 | ||
544 | note = find_reg_note (insn, REG_EH_REGION, NULL_RTX); | |
545 | if (note == NULL_RTX) | |
546 | return; | |
547 | ||
548 | gcc_assert (CALL_P (insn) | |
549 | || (flag_non_call_exceptions && may_trap_p (PATTERN (insn)))); | |
550 | ||
551 | for (p = insns; p != NULL_RTX; p = NEXT_INSN (p)) | |
552 | { | |
553 | if (CALL_P (p) | |
554 | || (flag_non_call_exceptions | |
555 | && INSN_P (p) | |
556 | && may_trap_p (PATTERN (p)))) | |
557 | REG_NOTES (p) = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (note, 0), | |
558 | REG_NOTES (p)); | |
559 | } | |
560 | } | |
561 | ||
1a6a0f2a | 562 | /* If there is a REG_LIBCALL note on OLD_START, move it to NEW_START, |
563 | and link the corresponding REG_RETVAL note to NEW_START. */ | |
564 | ||
565 | static void | |
566 | move_libcall_note (rtx old_start, rtx new_start) | |
567 | { | |
568 | rtx note0, note1, end; | |
569 | ||
570 | note0 = find_reg_note (old_start, REG_LIBCALL, NULL); | |
571 | if (note0 == NULL_RTX) | |
572 | return; | |
573 | ||
574 | remove_note (old_start, note0); | |
575 | end = XEXP (note0, 0); | |
576 | note1 = find_reg_note (end, REG_RETVAL, NULL); | |
577 | ||
578 | XEXP (note0, 1) = REG_NOTES (new_start); | |
579 | REG_NOTES (new_start) = note0; | |
580 | XEXP (note1, 0) = new_start; | |
581 | } | |
582 | ||
583 | /* Remove any REG_RETVAL note, the corresponding REG_LIBCALL note, and | |
584 | any markers for a no-conflict block. We have decomposed the | |
585 | registers so the non-conflict is now obvious. */ | |
586 | ||
587 | static void | |
588 | remove_retval_note (rtx insn1) | |
589 | { | |
590 | rtx note0, insn0, note1, insn; | |
591 | ||
592 | note1 = find_reg_note (insn1, REG_RETVAL, NULL); | |
593 | if (note1 == NULL_RTX) | |
594 | return; | |
595 | ||
596 | insn0 = XEXP (note1, 0); | |
597 | note0 = find_reg_note (insn0, REG_LIBCALL, NULL); | |
598 | ||
599 | remove_note (insn0, note0); | |
600 | remove_note (insn1, note1); | |
601 | ||
602 | for (insn = insn0; insn != insn1; insn = NEXT_INSN (insn)) | |
603 | { | |
604 | while (1) | |
605 | { | |
606 | rtx note; | |
607 | ||
608 | note = find_reg_note (insn, REG_NO_CONFLICT, NULL); | |
609 | if (note == NULL_RTX) | |
610 | break; | |
611 | remove_note (insn, note); | |
612 | } | |
613 | } | |
614 | } | |
615 | ||
616 | /* Resolve any decomposed registers which appear in register notes on | |
617 | INSN. */ | |
618 | ||
619 | static void | |
620 | resolve_reg_notes (rtx insn) | |
621 | { | |
622 | rtx *pnote, note; | |
623 | ||
624 | note = find_reg_equal_equiv_note (insn); | |
625 | if (note) | |
626 | { | |
3072d30e | 627 | int old_count = num_validated_changes (); |
1a6a0f2a | 628 | if (for_each_rtx (&XEXP (note, 0), resolve_subreg_use, NULL)) |
629 | { | |
630 | remove_note (insn, note); | |
631 | remove_retval_note (insn); | |
632 | } | |
3072d30e | 633 | else |
634 | if (old_count != num_validated_changes ()) | |
635 | df_notes_rescan (insn); | |
1a6a0f2a | 636 | } |
637 | ||
638 | pnote = ®_NOTES (insn); | |
639 | while (*pnote != NULL_RTX) | |
640 | { | |
641 | bool delete = false; | |
642 | ||
643 | note = *pnote; | |
644 | switch (REG_NOTE_KIND (note)) | |
645 | { | |
646 | case REG_NO_CONFLICT: | |
3072d30e | 647 | case REG_DEAD: |
648 | case REG_UNUSED: | |
1a6a0f2a | 649 | if (resolve_reg_p (XEXP (note, 0))) |
650 | delete = true; | |
651 | break; | |
652 | ||
653 | default: | |
654 | break; | |
655 | } | |
656 | ||
657 | if (delete) | |
658 | *pnote = XEXP (note, 1); | |
659 | else | |
660 | pnote = &XEXP (note, 1); | |
661 | } | |
662 | } | |
663 | ||
67c3f580 | 664 | /* Return whether X can be decomposed into subwords. */ |
1a6a0f2a | 665 | |
666 | static bool | |
67c3f580 | 667 | can_decompose_p (rtx x) |
1a6a0f2a | 668 | { |
669 | if (REG_P (x)) | |
670 | { | |
671 | unsigned int regno = REGNO (x); | |
672 | ||
673 | if (HARD_REGISTER_NUM_P (regno)) | |
67c3f580 | 674 | return (validate_subreg (word_mode, GET_MODE (x), x, UNITS_PER_WORD) |
675 | && HARD_REGNO_MODE_OK (regno, word_mode)); | |
1a6a0f2a | 676 | else |
67c3f580 | 677 | return !bitmap_bit_p (non_decomposable_context, regno); |
1a6a0f2a | 678 | } |
679 | ||
67c3f580 | 680 | return true; |
1a6a0f2a | 681 | } |
682 | ||
683 | /* Decompose the registers used in a simple move SET within INSN. If | |
684 | we don't change anything, return INSN, otherwise return the start | |
685 | of the sequence of moves. */ | |
686 | ||
687 | static rtx | |
688 | resolve_simple_move (rtx set, rtx insn) | |
689 | { | |
690 | rtx src, dest, real_dest, insns; | |
691 | enum machine_mode orig_mode, dest_mode; | |
692 | unsigned int words; | |
693 | bool pushing; | |
694 | ||
695 | src = SET_SRC (set); | |
696 | dest = SET_DEST (set); | |
697 | orig_mode = GET_MODE (dest); | |
698 | ||
699 | words = (GET_MODE_SIZE (orig_mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
700 | if (words <= 1) | |
701 | return insn; | |
702 | ||
703 | start_sequence (); | |
704 | ||
705 | /* We have to handle copying from a SUBREG of a decomposed reg where | |
706 | the SUBREG is larger than word size. Rather than assume that we | |
707 | can take a word_mode SUBREG of the destination, we copy to a new | |
708 | register and then copy that to the destination. */ | |
709 | ||
710 | real_dest = NULL_RTX; | |
711 | ||
712 | if (GET_CODE (src) == SUBREG | |
713 | && resolve_reg_p (SUBREG_REG (src)) | |
714 | && (SUBREG_BYTE (src) != 0 | |
715 | || (GET_MODE_SIZE (orig_mode) | |
716 | != GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))))) | |
717 | { | |
718 | real_dest = dest; | |
719 | dest = gen_reg_rtx (orig_mode); | |
720 | if (REG_P (real_dest)) | |
721 | REG_ATTRS (dest) = REG_ATTRS (real_dest); | |
722 | } | |
723 | ||
724 | /* Similarly if we are copying to a SUBREG of a decomposed reg where | |
725 | the SUBREG is larger than word size. */ | |
726 | ||
727 | if (GET_CODE (dest) == SUBREG | |
728 | && resolve_reg_p (SUBREG_REG (dest)) | |
729 | && (SUBREG_BYTE (dest) != 0 | |
730 | || (GET_MODE_SIZE (orig_mode) | |
731 | != GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))))) | |
732 | { | |
733 | rtx reg, minsn, smove; | |
734 | ||
735 | reg = gen_reg_rtx (orig_mode); | |
736 | minsn = emit_move_insn (reg, src); | |
737 | smove = single_set (minsn); | |
738 | gcc_assert (smove != NULL_RTX); | |
739 | resolve_simple_move (smove, minsn); | |
740 | src = reg; | |
741 | } | |
742 | ||
743 | /* If we didn't have any big SUBREGS of decomposed registers, and | |
744 | neither side of the move is a register we are decomposing, then | |
745 | we don't have to do anything here. */ | |
746 | ||
747 | if (src == SET_SRC (set) | |
748 | && dest == SET_DEST (set) | |
749 | && !resolve_reg_p (src) | |
750 | && !resolve_subreg_p (src) | |
751 | && !resolve_reg_p (dest) | |
752 | && !resolve_subreg_p (dest)) | |
753 | { | |
754 | end_sequence (); | |
755 | return insn; | |
756 | } | |
757 | ||
ccd1ec59 | 758 | /* It's possible for the code to use a subreg of a decomposed |
759 | register while forming an address. We need to handle that before | |
760 | passing the address to emit_move_insn. We pass NULL_RTX as the | |
761 | insn parameter to resolve_subreg_use because we can not validate | |
762 | the insn yet. */ | |
763 | if (MEM_P (src) || MEM_P (dest)) | |
764 | { | |
765 | int acg; | |
766 | ||
767 | if (MEM_P (src)) | |
768 | for_each_rtx (&XEXP (src, 0), resolve_subreg_use, NULL_RTX); | |
769 | if (MEM_P (dest)) | |
770 | for_each_rtx (&XEXP (dest, 0), resolve_subreg_use, NULL_RTX); | |
771 | acg = apply_change_group (); | |
772 | gcc_assert (acg); | |
773 | } | |
774 | ||
1a6a0f2a | 775 | /* If SRC is a register which we can't decompose, or has side |
776 | effects, we need to move via a temporary register. */ | |
777 | ||
67c3f580 | 778 | if (!can_decompose_p (src) |
1a6a0f2a | 779 | || side_effects_p (src) |
780 | || GET_CODE (src) == ASM_OPERANDS) | |
781 | { | |
782 | rtx reg; | |
783 | ||
784 | reg = gen_reg_rtx (orig_mode); | |
785 | emit_move_insn (reg, src); | |
786 | src = reg; | |
787 | } | |
788 | ||
789 | /* If DEST is a register which we can't decompose, or has side | |
790 | effects, we need to first move to a temporary register. We | |
791 | handle the common case of pushing an operand directly. We also | |
792 | go through a temporary register if it holds a floating point | |
793 | value. This gives us better code on systems which can't move | |
794 | data easily between integer and floating point registers. */ | |
795 | ||
796 | dest_mode = orig_mode; | |
797 | pushing = push_operand (dest, dest_mode); | |
67c3f580 | 798 | if (!can_decompose_p (dest) |
1a6a0f2a | 799 | || (side_effects_p (dest) && !pushing) |
800 | || (!SCALAR_INT_MODE_P (dest_mode) | |
801 | && !resolve_reg_p (dest) | |
802 | && !resolve_subreg_p (dest))) | |
803 | { | |
804 | if (real_dest == NULL_RTX) | |
805 | real_dest = dest; | |
806 | if (!SCALAR_INT_MODE_P (dest_mode)) | |
807 | { | |
808 | dest_mode = mode_for_size (GET_MODE_SIZE (dest_mode) * BITS_PER_UNIT, | |
809 | MODE_INT, 0); | |
810 | gcc_assert (dest_mode != BLKmode); | |
811 | } | |
812 | dest = gen_reg_rtx (dest_mode); | |
813 | if (REG_P (real_dest)) | |
814 | REG_ATTRS (dest) = REG_ATTRS (real_dest); | |
815 | } | |
816 | ||
817 | if (pushing) | |
818 | { | |
819 | unsigned int i, j, jinc; | |
820 | ||
821 | gcc_assert (GET_MODE_SIZE (orig_mode) % UNITS_PER_WORD == 0); | |
822 | gcc_assert (GET_CODE (XEXP (dest, 0)) != PRE_MODIFY); | |
823 | gcc_assert (GET_CODE (XEXP (dest, 0)) != POST_MODIFY); | |
824 | ||
825 | if (WORDS_BIG_ENDIAN == STACK_GROWS_DOWNWARD) | |
826 | { | |
827 | j = 0; | |
828 | jinc = 1; | |
829 | } | |
830 | else | |
831 | { | |
832 | j = words - 1; | |
833 | jinc = -1; | |
834 | } | |
835 | ||
836 | for (i = 0; i < words; ++i, j += jinc) | |
837 | { | |
838 | rtx temp; | |
839 | ||
840 | temp = copy_rtx (XEXP (dest, 0)); | |
841 | temp = adjust_automodify_address_nv (dest, word_mode, temp, | |
842 | j * UNITS_PER_WORD); | |
843 | emit_move_insn (temp, | |
844 | simplify_gen_subreg_concatn (word_mode, src, | |
845 | orig_mode, | |
846 | j * UNITS_PER_WORD)); | |
847 | } | |
848 | } | |
849 | else | |
850 | { | |
851 | unsigned int i; | |
852 | ||
853 | if (REG_P (dest) && !HARD_REGISTER_NUM_P (REGNO (dest))) | |
854 | emit_insn (gen_rtx_CLOBBER (VOIDmode, dest)); | |
855 | ||
856 | for (i = 0; i < words; ++i) | |
857 | emit_move_insn (simplify_gen_subreg_concatn (word_mode, dest, | |
858 | dest_mode, | |
859 | i * UNITS_PER_WORD), | |
860 | simplify_gen_subreg_concatn (word_mode, src, | |
861 | orig_mode, | |
862 | i * UNITS_PER_WORD)); | |
863 | } | |
864 | ||
865 | if (real_dest != NULL_RTX) | |
866 | { | |
867 | rtx mdest, minsn, smove; | |
868 | ||
869 | if (dest_mode == orig_mode) | |
870 | mdest = dest; | |
871 | else | |
872 | mdest = simplify_gen_subreg (orig_mode, dest, GET_MODE (dest), 0); | |
873 | minsn = emit_move_insn (real_dest, mdest); | |
874 | ||
875 | smove = single_set (minsn); | |
876 | gcc_assert (smove != NULL_RTX); | |
877 | ||
878 | resolve_simple_move (smove, minsn); | |
879 | } | |
880 | ||
881 | insns = get_insns (); | |
882 | end_sequence (); | |
883 | ||
97bb2849 | 884 | move_eh_region_note (insn, insns); |
885 | ||
1a6a0f2a | 886 | emit_insn_before (insns, insn); |
887 | ||
888 | move_libcall_note (insn, insns); | |
889 | remove_retval_note (insn); | |
890 | delete_insn (insn); | |
891 | ||
892 | return insns; | |
893 | } | |
894 | ||
895 | /* Change a CLOBBER of a decomposed register into a CLOBBER of the | |
896 | component registers. Return whether we changed something. */ | |
897 | ||
898 | static bool | |
899 | resolve_clobber (rtx pat, rtx insn) | |
900 | { | |
901 | rtx reg; | |
902 | enum machine_mode orig_mode; | |
903 | unsigned int words, i; | |
ab9eaa97 | 904 | int ret; |
1a6a0f2a | 905 | |
906 | reg = XEXP (pat, 0); | |
2289a5f2 | 907 | if (!resolve_reg_p (reg) && !resolve_subreg_p (reg)) |
1a6a0f2a | 908 | return false; |
909 | ||
910 | orig_mode = GET_MODE (reg); | |
911 | words = GET_MODE_SIZE (orig_mode); | |
912 | words = (words + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
913 | ||
ab9eaa97 | 914 | ret = validate_change (NULL_RTX, &XEXP (pat, 0), |
915 | simplify_gen_subreg_concatn (word_mode, reg, | |
916 | orig_mode, 0), | |
917 | 0); | |
3072d30e | 918 | df_insn_rescan (insn); |
ab9eaa97 | 919 | gcc_assert (ret != 0); |
920 | ||
1a6a0f2a | 921 | for (i = words - 1; i > 0; --i) |
922 | { | |
923 | rtx x; | |
924 | ||
2289a5f2 | 925 | x = simplify_gen_subreg_concatn (word_mode, reg, orig_mode, |
926 | i * UNITS_PER_WORD); | |
1a6a0f2a | 927 | x = gen_rtx_CLOBBER (VOIDmode, x); |
928 | emit_insn_after (x, insn); | |
929 | } | |
930 | ||
931 | return true; | |
932 | } | |
933 | ||
934 | /* A USE of a decomposed register is no longer meaningful. Return | |
935 | whether we changed something. */ | |
936 | ||
937 | static bool | |
938 | resolve_use (rtx pat, rtx insn) | |
939 | { | |
940 | if (resolve_reg_p (XEXP (pat, 0)) || resolve_subreg_p (XEXP (pat, 0))) | |
941 | { | |
942 | delete_insn (insn); | |
943 | return true; | |
944 | } | |
945 | return false; | |
946 | } | |
947 | ||
948 | /* Look for registers which are always accessed via word-sized SUBREGs | |
949 | or via copies. Decompose these registers into several word-sized | |
950 | pseudo-registers. */ | |
951 | ||
952 | static void | |
3072d30e | 953 | decompose_multiword_subregs (void) |
1a6a0f2a | 954 | { |
955 | unsigned int max; | |
956 | basic_block bb; | |
957 | ||
3072d30e | 958 | if (df) |
959 | df_set_flags (DF_DEFER_INSN_RESCAN); | |
960 | ||
1a6a0f2a | 961 | max = max_reg_num (); |
962 | ||
963 | /* First see if there are any multi-word pseudo-registers. If there | |
964 | aren't, there is nothing we can do. This should speed up this | |
965 | pass in the normal case, since it should be faster than scanning | |
966 | all the insns. */ | |
967 | { | |
968 | unsigned int i; | |
969 | ||
970 | for (i = FIRST_PSEUDO_REGISTER; i < max; ++i) | |
971 | { | |
972 | if (regno_reg_rtx[i] != NULL | |
973 | && GET_MODE_SIZE (GET_MODE (regno_reg_rtx[i])) > UNITS_PER_WORD) | |
974 | break; | |
975 | } | |
976 | if (i == max) | |
977 | return; | |
978 | } | |
979 | ||
980 | /* FIXME: When the dataflow branch is merged, we can change this | |
981 | code to look for each multi-word pseudo-register and to find each | |
982 | insn which sets or uses that register. That should be faster | |
983 | than scanning all the insns. */ | |
984 | ||
985 | decomposable_context = BITMAP_ALLOC (NULL); | |
986 | non_decomposable_context = BITMAP_ALLOC (NULL); | |
987 | ||
988 | reg_copy_graph = VEC_alloc (bitmap, heap, max); | |
989 | VEC_safe_grow (bitmap, heap, reg_copy_graph, max); | |
990 | memset (VEC_address (bitmap, reg_copy_graph), 0, sizeof (bitmap) * max); | |
991 | ||
992 | FOR_EACH_BB (bb) | |
993 | { | |
994 | rtx insn; | |
995 | ||
996 | FOR_BB_INSNS (bb, insn) | |
997 | { | |
998 | rtx set; | |
999 | enum classify_move_insn cmi; | |
1000 | int i, n; | |
1001 | ||
1002 | if (!INSN_P (insn) | |
1003 | || GET_CODE (PATTERN (insn)) == CLOBBER | |
1004 | || GET_CODE (PATTERN (insn)) == USE) | |
1005 | continue; | |
1006 | ||
1007 | recog_memoized (insn); | |
1008 | extract_insn (insn); | |
1009 | ||
1010 | set = simple_move (insn); | |
1011 | ||
1012 | if (!set) | |
1013 | cmi = NOT_SIMPLE_MOVE; | |
1014 | else | |
1015 | { | |
1016 | bool retval; | |
1017 | ||
1018 | retval = find_reg_note (insn, REG_RETVAL, NULL_RTX) != NULL_RTX; | |
1019 | ||
1020 | if (find_pseudo_copy (set) && !retval) | |
1021 | cmi = SIMPLE_PSEUDO_REG_MOVE; | |
1022 | else if (retval | |
1023 | && REG_P (SET_SRC (set)) | |
1024 | && HARD_REGISTER_P (SET_SRC (set))) | |
1025 | { | |
1026 | rtx note; | |
1027 | ||
1028 | /* We don't want to decompose an assignment which | |
1029 | copies the value returned by a libcall to a | |
1030 | pseudo-register. Doing that will lose the RETVAL | |
1031 | note with no real gain. */ | |
1032 | cmi = NOT_SIMPLE_MOVE; | |
1033 | ||
1034 | /* If we have a RETVAL note, there should be an | |
1035 | EQUAL note. We don't want to decompose any | |
1036 | registers which that EQUAL note refers to | |
1037 | directly. If we do, we will no longer know the | |
1038 | value of the libcall. */ | |
1039 | note = find_reg_equal_equiv_note (insn); | |
1040 | if (note != NULL_RTX) | |
1041 | for_each_rtx (&XEXP (note, 0), find_decomposable_subregs, | |
1042 | &cmi); | |
1043 | } | |
1044 | else | |
1045 | cmi = SIMPLE_MOVE; | |
1046 | } | |
1047 | ||
1048 | n = recog_data.n_operands; | |
1049 | for (i = 0; i < n; ++i) | |
1050 | { | |
1051 | for_each_rtx (&recog_data.operand[i], | |
1052 | find_decomposable_subregs, | |
1053 | &cmi); | |
1054 | ||
1055 | /* We handle ASM_OPERANDS as a special case to support | |
1056 | things like x86 rdtsc which returns a DImode value. | |
1057 | We can decompose the output, which will certainly be | |
1058 | operand 0, but not the inputs. */ | |
1059 | ||
1060 | if (cmi == SIMPLE_MOVE | |
1061 | && GET_CODE (SET_SRC (set)) == ASM_OPERANDS) | |
1062 | { | |
1063 | gcc_assert (i == 0); | |
1064 | cmi = NOT_SIMPLE_MOVE; | |
1065 | } | |
1066 | } | |
1067 | } | |
1068 | } | |
1069 | ||
1070 | bitmap_and_compl_into (decomposable_context, non_decomposable_context); | |
1071 | if (!bitmap_empty_p (decomposable_context)) | |
1072 | { | |
1073 | int hold_no_new_pseudos = no_new_pseudos; | |
97bb2849 | 1074 | sbitmap sub_blocks; |
db1c50be | 1075 | unsigned int i; |
1076 | sbitmap_iterator sbi; | |
1a6a0f2a | 1077 | bitmap_iterator iter; |
1078 | unsigned int regno; | |
1079 | ||
1080 | propagate_pseudo_copies (); | |
1081 | ||
1082 | no_new_pseudos = 0; | |
97bb2849 | 1083 | sub_blocks = sbitmap_alloc (last_basic_block); |
1084 | sbitmap_zero (sub_blocks); | |
1a6a0f2a | 1085 | |
1086 | EXECUTE_IF_SET_IN_BITMAP (decomposable_context, 0, regno, iter) | |
1087 | decompose_register (regno); | |
1088 | ||
1089 | FOR_EACH_BB (bb) | |
1090 | { | |
1091 | rtx insn; | |
1092 | ||
1093 | FOR_BB_INSNS (bb, insn) | |
1094 | { | |
1095 | rtx next, pat; | |
1096 | bool changed; | |
1097 | ||
1098 | if (!INSN_P (insn)) | |
1099 | continue; | |
1100 | ||
1101 | next = NEXT_INSN (insn); | |
1102 | changed = false; | |
1103 | ||
1104 | pat = PATTERN (insn); | |
1105 | if (GET_CODE (pat) == CLOBBER) | |
1106 | { | |
1107 | if (resolve_clobber (pat, insn)) | |
1108 | changed = true; | |
1109 | } | |
1110 | else if (GET_CODE (pat) == USE) | |
1111 | { | |
1112 | if (resolve_use (pat, insn)) | |
1113 | changed = true; | |
1114 | } | |
1115 | else | |
1116 | { | |
1117 | rtx set; | |
1118 | int i; | |
1119 | ||
1120 | recog_memoized (insn); | |
1121 | extract_insn (insn); | |
1122 | ||
1123 | set = simple_move (insn); | |
1124 | if (set) | |
1125 | { | |
1126 | rtx orig_insn = insn; | |
97bb2849 | 1127 | bool cfi = control_flow_insn_p (insn); |
1a6a0f2a | 1128 | |
db1c50be | 1129 | /* We can end up splitting loads to multi-word pseudos |
1130 | into separate loads to machine word size pseudos. | |
1131 | When this happens, we first had one load that can | |
1132 | throw, and after resolve_simple_move we'll have a | |
1133 | bunch of loads (at least two). All those loads may | |
1134 | trap if we can have non-call exceptions, so they | |
1135 | all will end the current basic block. We split the | |
1136 | block after the outer loop over all insns, but we | |
1137 | make sure here that we will be able to split the | |
1138 | basic block and still produce the correct control | |
1139 | flow graph for it. */ | |
1140 | gcc_assert (!cfi | |
1141 | || (flag_non_call_exceptions | |
1142 | && can_throw_internal (insn))); | |
1143 | ||
1a6a0f2a | 1144 | insn = resolve_simple_move (set, insn); |
1145 | if (insn != orig_insn) | |
1146 | { | |
1147 | changed = true; | |
1148 | ||
44e61675 | 1149 | remove_retval_note (insn); |
1150 | ||
1a6a0f2a | 1151 | recog_memoized (insn); |
1152 | extract_insn (insn); | |
97bb2849 | 1153 | |
1154 | if (cfi) | |
1155 | SET_BIT (sub_blocks, bb->index); | |
1a6a0f2a | 1156 | } |
1157 | } | |
1158 | ||
1159 | for (i = recog_data.n_operands - 1; i >= 0; --i) | |
1160 | for_each_rtx (recog_data.operand_loc[i], | |
1161 | resolve_subreg_use, | |
1162 | insn); | |
1163 | ||
1164 | resolve_reg_notes (insn); | |
1165 | ||
1166 | if (num_validated_changes () > 0) | |
1167 | { | |
1168 | for (i = recog_data.n_dups - 1; i >= 0; --i) | |
1169 | { | |
1170 | rtx *pl = recog_data.dup_loc[i]; | |
1171 | int dup_num = recog_data.dup_num[i]; | |
1172 | rtx *px = recog_data.operand_loc[dup_num]; | |
1173 | ||
1174 | validate_change (insn, pl, *px, 1); | |
1175 | } | |
1176 | ||
1177 | i = apply_change_group (); | |
1178 | gcc_assert (i); | |
1179 | ||
44e61675 | 1180 | remove_retval_note (insn); |
1181 | ||
1a6a0f2a | 1182 | changed = true; |
1183 | } | |
1184 | } | |
1a6a0f2a | 1185 | } |
1186 | } | |
1187 | ||
1188 | no_new_pseudos = hold_no_new_pseudos; | |
1189 | ||
db1c50be | 1190 | /* If we had insns to split that caused control flow insns in the middle |
1191 | of a basic block, split those blocks now. Note that we only handle | |
1192 | the case where splitting a load has caused multiple possibly trapping | |
1193 | loads to appear. */ | |
1194 | EXECUTE_IF_SET_IN_SBITMAP (sub_blocks, 0, i, sbi) | |
1195 | { | |
1196 | rtx insn, end; | |
1197 | edge fallthru; | |
1198 | ||
1199 | bb = BASIC_BLOCK (i); | |
1200 | insn = BB_HEAD (bb); | |
1201 | end = BB_END (bb); | |
1202 | ||
1203 | while (insn != end) | |
1204 | { | |
1205 | if (control_flow_insn_p (insn)) | |
1206 | { | |
1207 | /* Split the block after insn. There will be a fallthru | |
1208 | edge, which is OK so we keep it. We have to create the | |
1209 | exception edges ourselves. */ | |
1210 | fallthru = split_block (bb, insn); | |
1211 | rtl_make_eh_edge (NULL, bb, BB_END (bb)); | |
1212 | bb = fallthru->dest; | |
1213 | insn = BB_HEAD (bb); | |
1214 | } | |
1215 | else | |
1216 | insn = NEXT_INSN (insn); | |
1217 | } | |
1218 | } | |
97bb2849 | 1219 | |
97bb2849 | 1220 | sbitmap_free (sub_blocks); |
1a6a0f2a | 1221 | } |
1222 | ||
1223 | { | |
1224 | unsigned int i; | |
1225 | bitmap b; | |
1226 | ||
1227 | for (i = 0; VEC_iterate (bitmap, reg_copy_graph, i, b); ++i) | |
1228 | if (b) | |
1229 | BITMAP_FREE (b); | |
1230 | } | |
1231 | ||
1232 | VEC_free (bitmap, heap, reg_copy_graph); | |
1233 | ||
1234 | BITMAP_FREE (decomposable_context); | |
1235 | BITMAP_FREE (non_decomposable_context); | |
1236 | } | |
1237 | \f | |
1238 | /* Gate function for lower subreg pass. */ | |
1239 | ||
1240 | static bool | |
1241 | gate_handle_lower_subreg (void) | |
1242 | { | |
1243 | return flag_split_wide_types != 0; | |
1244 | } | |
1245 | ||
1246 | /* Implement first lower subreg pass. */ | |
1247 | ||
1248 | static unsigned int | |
1249 | rest_of_handle_lower_subreg (void) | |
1250 | { | |
3072d30e | 1251 | decompose_multiword_subregs (); |
1a6a0f2a | 1252 | return 0; |
1253 | } | |
1254 | ||
1255 | /* Implement second lower subreg pass. */ | |
1256 | ||
1257 | static unsigned int | |
1258 | rest_of_handle_lower_subreg2 (void) | |
1259 | { | |
3072d30e | 1260 | decompose_multiword_subregs (); |
1a6a0f2a | 1261 | return 0; |
1262 | } | |
1263 | ||
1264 | struct tree_opt_pass pass_lower_subreg = | |
1265 | { | |
1266 | "subreg", /* name */ | |
1267 | gate_handle_lower_subreg, /* gate */ | |
1268 | rest_of_handle_lower_subreg, /* execute */ | |
1269 | NULL, /* sub */ | |
1270 | NULL, /* next */ | |
1271 | 0, /* static_pass_number */ | |
1272 | TV_LOWER_SUBREG, /* tv_id */ | |
1273 | 0, /* properties_required */ | |
1274 | 0, /* properties_provided */ | |
1275 | 0, /* properties_destroyed */ | |
1276 | 0, /* todo_flags_start */ | |
1277 | TODO_dump_func | | |
97bb2849 | 1278 | TODO_ggc_collect | |
1279 | TODO_verify_flow, /* todo_flags_finish */ | |
1a6a0f2a | 1280 | 'u' /* letter */ |
1281 | }; | |
1282 | ||
1283 | struct tree_opt_pass pass_lower_subreg2 = | |
1284 | { | |
1285 | "subreg2", /* name */ | |
1286 | gate_handle_lower_subreg, /* gate */ | |
1287 | rest_of_handle_lower_subreg2, /* execute */ | |
1288 | NULL, /* sub */ | |
1289 | NULL, /* next */ | |
1290 | 0, /* static_pass_number */ | |
1291 | TV_LOWER_SUBREG, /* tv_id */ | |
1292 | 0, /* properties_required */ | |
1293 | 0, /* properties_provided */ | |
1294 | 0, /* properties_destroyed */ | |
1295 | 0, /* todo_flags_start */ | |
3072d30e | 1296 | TODO_df_finish | |
1a6a0f2a | 1297 | TODO_dump_func | |
97bb2849 | 1298 | TODO_ggc_collect | |
1299 | TODO_verify_flow, /* todo_flags_finish */ | |
1a6a0f2a | 1300 | 'U' /* letter */ |
1301 | }; |