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55a2c322 | 1 | /* Assign reload pseudos. |
a945c346 | 2 | Copyright (C) 2010-2024 Free Software Foundation, Inc. |
55a2c322 VM |
3 | Contributed by Vladimir Makarov <vmakarov@redhat.com>. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it under | |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 3, or (at your option) any later | |
10 | version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | ||
22 | /* This file's main objective is to assign hard registers to reload | |
23 | pseudos. It also tries to allocate hard registers to other | |
24 | pseudos, but at a lower priority than the reload pseudos. The pass | |
25 | does not transform the RTL. | |
26 | ||
27 | We must allocate a hard register to every reload pseudo. We try to | |
28 | increase the chances of finding a viable allocation by assigning | |
29 | the pseudos in order of fewest available hard registers first. If | |
30 | we still fail to find a hard register, we spill other (non-reload) | |
31 | pseudos in order to make room. | |
32 | ||
33 | find_hard_regno_for finds hard registers for allocation without | |
34 | spilling. spill_for does the same with spilling. Both functions | |
35 | use a cost model to determine the most profitable choice of hard | |
36 | and spill registers. | |
37 | ||
38 | Once we have finished allocating reload pseudos, we also try to | |
39 | assign registers to other (non-reload) pseudos. This is useful if | |
40 | hard registers were freed up by the spilling just described. | |
41 | ||
42 | We try to assign hard registers by collecting pseudos into threads. | |
43 | These threads contain reload and inheritance pseudos that are | |
44 | connected by copies (move insns). Doing this improves the chances | |
45 | of pseudos in the thread getting the same hard register and, as a | |
46 | result, of allowing some move insns to be deleted. | |
47 | ||
48 | When we assign a hard register to a pseudo, we decrease the cost of | |
49 | using the same hard register for pseudos that are connected by | |
50 | copies. | |
51 | ||
52 | If two hard registers have the same frequency-derived cost, we | |
53 | prefer hard registers with higher priorities. The mapping of | |
54 | registers to priorities is controlled by the register_priority | |
55 | target hook. For example, x86-64 has a few register priorities: | |
56 | hard registers with and without REX prefixes have different | |
57 | priorities. This permits us to generate smaller code as insns | |
58 | without REX prefixes are shorter. | |
59 | ||
60 | If a few hard registers are still equally good for the assignment, | |
61 | we choose the least used hard register. It is called leveling and | |
62 | may be profitable for some targets. | |
63 | ||
64 | Only insns with changed allocation pseudos are processed on the | |
65 | next constraint pass. | |
66 | ||
67 | The pseudo live-ranges are used to find conflicting pseudos. | |
68 | ||
69 | For understanding the code, it is important to keep in mind that | |
70 | inheritance, split, and reload pseudos created since last | |
71 | constraint pass have regno >= lra_constraint_new_regno_start. | |
72 | Inheritance and split pseudos created on any pass are in the | |
73 | corresponding bitmaps. Inheritance and split pseudos since the | |
74 | last constraint pass have also the corresponding non-negative | |
75 | restore_regno. */ | |
76 | ||
77 | #include "config.h" | |
78 | #include "system.h" | |
79 | #include "coretypes.h" | |
c7131fb2 | 80 | #include "backend.h" |
957060b5 | 81 | #include "target.h" |
55a2c322 | 82 | #include "rtl.h" |
957060b5 AM |
83 | #include "tree.h" |
84 | #include "predict.h" | |
c7131fb2 | 85 | #include "df.h" |
4d0cdd0c | 86 | #include "memmodel.h" |
55a2c322 | 87 | #include "tm_p.h" |
55a2c322 | 88 | #include "insn-config.h" |
957060b5 AM |
89 | #include "regs.h" |
90 | #include "ira.h" | |
55a2c322 | 91 | #include "recog.h" |
957060b5 | 92 | #include "rtl-error.h" |
55a2c322 | 93 | #include "sparseset.h" |
c7131fb2 | 94 | #include "lra.h" |
55a2c322 | 95 | #include "lra-int.h" |
a1e6ee38 | 96 | #include "function-abi.h" |
55a2c322 | 97 | |
f54437d5 VM |
98 | /* Current iteration number of the pass and current iteration number |
99 | of the pass after the latest spill pass when any former reload | |
100 | pseudo was spilled. */ | |
101 | int lra_assignment_iter; | |
102 | int lra_assignment_iter_after_spill; | |
103 | ||
104 | /* Flag of spilling former reload pseudos on this pass. */ | |
105 | static bool former_reload_pseudo_spill_p; | |
106 | ||
55a2c322 VM |
107 | /* Array containing corresponding values of function |
108 | lra_get_allocno_class. It is used to speed up the code. */ | |
109 | static enum reg_class *regno_allocno_class_array; | |
110 | ||
8a8330b7 VM |
111 | /* Array containing lengths of pseudo live ranges. It is used to |
112 | speed up the code. */ | |
113 | static int *regno_live_length; | |
114 | ||
55a2c322 VM |
115 | /* Information about the thread to which a pseudo belongs. Threads are |
116 | a set of connected reload and inheritance pseudos with the same set of | |
117 | available hard registers. Lone registers belong to their own threads. */ | |
118 | struct regno_assign_info | |
119 | { | |
120 | /* First/next pseudo of the same thread. */ | |
121 | int first, next; | |
122 | /* Frequency of the thread (execution frequency of only reload | |
123 | pseudos in the thread when the thread contains a reload pseudo). | |
124 | Defined only for the first thread pseudo. */ | |
125 | int freq; | |
126 | }; | |
127 | ||
128 | /* Map regno to the corresponding regno assignment info. */ | |
129 | static struct regno_assign_info *regno_assign_info; | |
130 | ||
bc404e1b VM |
131 | /* All inherited, subreg or optional pseudos created before last spill |
132 | sub-pass. Such pseudos are permitted to get memory instead of hard | |
133 | regs. */ | |
134 | static bitmap_head non_reload_pseudos; | |
135 | ||
55a2c322 VM |
136 | /* Process a pseudo copy with execution frequency COPY_FREQ connecting |
137 | REGNO1 and REGNO2 to form threads. */ | |
138 | static void | |
139 | process_copy_to_form_thread (int regno1, int regno2, int copy_freq) | |
140 | { | |
141 | int last, regno1_first, regno2_first; | |
142 | ||
143 | lra_assert (regno1 >= lra_constraint_new_regno_start | |
144 | && regno2 >= lra_constraint_new_regno_start); | |
145 | regno1_first = regno_assign_info[regno1].first; | |
146 | regno2_first = regno_assign_info[regno2].first; | |
147 | if (regno1_first != regno2_first) | |
148 | { | |
149 | for (last = regno2_first; | |
150 | regno_assign_info[last].next >= 0; | |
151 | last = regno_assign_info[last].next) | |
152 | regno_assign_info[last].first = regno1_first; | |
153 | regno_assign_info[last].first = regno1_first; | |
154 | regno_assign_info[last].next = regno_assign_info[regno1_first].next; | |
155 | regno_assign_info[regno1_first].next = regno2_first; | |
156 | regno_assign_info[regno1_first].freq | |
157 | += regno_assign_info[regno2_first].freq; | |
158 | } | |
159 | regno_assign_info[regno1_first].freq -= 2 * copy_freq; | |
160 | lra_assert (regno_assign_info[regno1_first].freq >= 0); | |
161 | } | |
162 | ||
163 | /* Initialize REGNO_ASSIGN_INFO and form threads. */ | |
164 | static void | |
165 | init_regno_assign_info (void) | |
166 | { | |
167 | int i, regno1, regno2, max_regno = max_reg_num (); | |
168 | lra_copy_t cp; | |
f4eafc30 | 169 | |
55a2c322 VM |
170 | regno_assign_info = XNEWVEC (struct regno_assign_info, max_regno); |
171 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
172 | { | |
173 | regno_assign_info[i].first = i; | |
174 | regno_assign_info[i].next = -1; | |
175 | regno_assign_info[i].freq = lra_reg_info[i].freq; | |
176 | } | |
177 | /* Form the threads. */ | |
178 | for (i = 0; (cp = lra_get_copy (i)) != NULL; i++) | |
179 | if ((regno1 = cp->regno1) >= lra_constraint_new_regno_start | |
180 | && (regno2 = cp->regno2) >= lra_constraint_new_regno_start | |
181 | && reg_renumber[regno1] < 0 && lra_reg_info[regno1].nrefs != 0 | |
182 | && reg_renumber[regno2] < 0 && lra_reg_info[regno2].nrefs != 0 | |
183 | && (ira_class_hard_regs_num[regno_allocno_class_array[regno1]] | |
184 | == ira_class_hard_regs_num[regno_allocno_class_array[regno2]])) | |
185 | process_copy_to_form_thread (regno1, regno2, cp->freq); | |
186 | } | |
187 | ||
188 | /* Free REGNO_ASSIGN_INFO. */ | |
189 | static void | |
190 | finish_regno_assign_info (void) | |
191 | { | |
192 | free (regno_assign_info); | |
193 | } | |
194 | ||
195 | /* The function is used to sort *reload* and *inheritance* pseudos to | |
196 | try to assign them hard registers. We put pseudos from the same | |
197 | thread always nearby. */ | |
198 | static int | |
199 | reload_pseudo_compare_func (const void *v1p, const void *v2p) | |
200 | { | |
201 | int r1 = *(const int *) v1p, r2 = *(const int *) v2p; | |
202 | enum reg_class cl1 = regno_allocno_class_array[r1]; | |
203 | enum reg_class cl2 = regno_allocno_class_array[r2]; | |
204 | int diff; | |
f4eafc30 | 205 | |
55a2c322 VM |
206 | lra_assert (r1 >= lra_constraint_new_regno_start |
207 | && r2 >= lra_constraint_new_regno_start); | |
f4eafc30 | 208 | |
55a2c322 VM |
209 | /* Prefer to assign reload registers with smaller classes first to |
210 | guarantee assignment to all reload registers. */ | |
211 | if ((diff = (ira_class_hard_regs_num[cl1] | |
212 | - ira_class_hard_regs_num[cl2])) != 0) | |
213 | return diff; | |
47918951 VM |
214 | /* Allocate bigger pseudos first to avoid register file |
215 | fragmentation. */ | |
216 | if ((diff | |
217 | = (ira_reg_class_max_nregs[cl2][lra_reg_info[r2].biggest_mode] | |
218 | - ira_reg_class_max_nregs[cl1][lra_reg_info[r1].biggest_mode])) != 0) | |
219 | return diff; | |
ffaea117 AM |
220 | if ((diff = (regno_assign_info[regno_assign_info[r2].first].freq |
221 | - regno_assign_info[regno_assign_info[r1].first].freq)) != 0) | |
222 | return diff; | |
55a2c322 VM |
223 | /* Put pseudos from the thread nearby. */ |
224 | if ((diff = regno_assign_info[r1].first - regno_assign_info[r2].first) != 0) | |
225 | return diff; | |
8a8330b7 VM |
226 | /* Prefer pseudos with longer live ranges. It sets up better |
227 | prefered hard registers for the thread pseudos and decreases | |
228 | register-register moves between the thread pseudos. */ | |
229 | if ((diff = regno_live_length[r2] - regno_live_length[r1]) != 0) | |
230 | return diff; | |
55a2c322 VM |
231 | /* If regs are equally good, sort by their numbers, so that the |
232 | results of qsort leave nothing to chance. */ | |
233 | return r1 - r2; | |
234 | } | |
235 | ||
236 | /* The function is used to sort *non-reload* pseudos to try to assign | |
237 | them hard registers. The order calculation is simpler than in the | |
238 | previous function and based on the pseudo frequency usage. */ | |
239 | static int | |
240 | pseudo_compare_func (const void *v1p, const void *v2p) | |
241 | { | |
242 | int r1 = *(const int *) v1p, r2 = *(const int *) v2p; | |
243 | int diff; | |
244 | ||
b81a2f0d VM |
245 | /* Assign hard reg to static chain pointer first pseudo when |
246 | non-local goto is used. */ | |
f0a40456 AM |
247 | if ((diff = (non_spilled_static_chain_regno_p (r2) |
248 | - non_spilled_static_chain_regno_p (r1))) != 0) | |
249 | return diff; | |
b81a2f0d | 250 | |
55a2c322 VM |
251 | /* Prefer to assign more frequently used registers first. */ |
252 | if ((diff = lra_reg_info[r2].freq - lra_reg_info[r1].freq) != 0) | |
253 | return diff; | |
f4eafc30 | 254 | |
55a2c322 VM |
255 | /* If regs are equally good, sort by their numbers, so that the |
256 | results of qsort leave nothing to chance. */ | |
257 | return r1 - r2; | |
258 | } | |
259 | ||
260 | /* Arrays of size LRA_LIVE_MAX_POINT mapping a program point to the | |
261 | pseudo live ranges with given start point. We insert only live | |
262 | ranges of pseudos interesting for assignment purposes. They are | |
263 | reload pseudos and pseudos assigned to hard registers. */ | |
264 | static lra_live_range_t *start_point_ranges; | |
265 | ||
266 | /* Used as a flag that a live range is not inserted in the start point | |
267 | chain. */ | |
268 | static struct lra_live_range not_in_chain_mark; | |
269 | ||
270 | /* Create and set up START_POINT_RANGES. */ | |
271 | static void | |
272 | create_live_range_start_chains (void) | |
273 | { | |
274 | int i, max_regno; | |
275 | lra_live_range_t r; | |
276 | ||
277 | start_point_ranges = XCNEWVEC (lra_live_range_t, lra_live_max_point); | |
278 | max_regno = max_reg_num (); | |
279 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
280 | if (i >= lra_constraint_new_regno_start || reg_renumber[i] >= 0) | |
281 | { | |
282 | for (r = lra_reg_info[i].live_ranges; r != NULL; r = r->next) | |
283 | { | |
284 | r->start_next = start_point_ranges[r->start]; | |
285 | start_point_ranges[r->start] = r; | |
286 | } | |
287 | } | |
288 | else | |
289 | { | |
290 | for (r = lra_reg_info[i].live_ranges; r != NULL; r = r->next) | |
291 | r->start_next = ¬_in_chain_mark; | |
292 | } | |
293 | } | |
294 | ||
295 | /* Insert live ranges of pseudo REGNO into start chains if they are | |
296 | not there yet. */ | |
297 | static void | |
298 | insert_in_live_range_start_chain (int regno) | |
299 | { | |
300 | lra_live_range_t r = lra_reg_info[regno].live_ranges; | |
301 | ||
302 | if (r->start_next != ¬_in_chain_mark) | |
303 | return; | |
304 | for (; r != NULL; r = r->next) | |
305 | { | |
306 | r->start_next = start_point_ranges[r->start]; | |
307 | start_point_ranges[r->start] = r; | |
308 | } | |
309 | } | |
310 | ||
311 | /* Free START_POINT_RANGES. */ | |
312 | static void | |
313 | finish_live_range_start_chains (void) | |
314 | { | |
315 | gcc_assert (start_point_ranges != NULL); | |
316 | free (start_point_ranges); | |
317 | start_point_ranges = NULL; | |
318 | } | |
319 | ||
320 | /* Map: program point -> bitmap of all pseudos living at the point and | |
321 | assigned to hard registers. */ | |
322 | static bitmap_head *live_hard_reg_pseudos; | |
323 | static bitmap_obstack live_hard_reg_pseudos_bitmap_obstack; | |
324 | ||
325 | /* reg_renumber corresponding to pseudos marked in | |
326 | live_hard_reg_pseudos. reg_renumber might be not matched to | |
327 | live_hard_reg_pseudos but live_pseudos_reg_renumber always reflects | |
328 | live_hard_reg_pseudos. */ | |
329 | static int *live_pseudos_reg_renumber; | |
330 | ||
331 | /* Sparseset used to calculate living hard reg pseudos for some program | |
332 | point range. */ | |
333 | static sparseset live_range_hard_reg_pseudos; | |
334 | ||
335 | /* Sparseset used to calculate living reload/inheritance pseudos for | |
336 | some program point range. */ | |
337 | static sparseset live_range_reload_inheritance_pseudos; | |
338 | ||
339 | /* Allocate and initialize the data about living pseudos at program | |
340 | points. */ | |
341 | static void | |
342 | init_lives (void) | |
343 | { | |
344 | int i, max_regno = max_reg_num (); | |
345 | ||
346 | live_range_hard_reg_pseudos = sparseset_alloc (max_regno); | |
347 | live_range_reload_inheritance_pseudos = sparseset_alloc (max_regno); | |
348 | live_hard_reg_pseudos = XNEWVEC (bitmap_head, lra_live_max_point); | |
349 | bitmap_obstack_initialize (&live_hard_reg_pseudos_bitmap_obstack); | |
350 | for (i = 0; i < lra_live_max_point; i++) | |
351 | bitmap_initialize (&live_hard_reg_pseudos[i], | |
352 | &live_hard_reg_pseudos_bitmap_obstack); | |
353 | live_pseudos_reg_renumber = XNEWVEC (int, max_regno); | |
354 | for (i = 0; i < max_regno; i++) | |
355 | live_pseudos_reg_renumber[i] = -1; | |
356 | } | |
357 | ||
358 | /* Free the data about living pseudos at program points. */ | |
359 | static void | |
360 | finish_lives (void) | |
361 | { | |
362 | sparseset_free (live_range_hard_reg_pseudos); | |
363 | sparseset_free (live_range_reload_inheritance_pseudos); | |
364 | free (live_hard_reg_pseudos); | |
365 | bitmap_obstack_release (&live_hard_reg_pseudos_bitmap_obstack); | |
366 | free (live_pseudos_reg_renumber); | |
367 | } | |
368 | ||
369 | /* Update the LIVE_HARD_REG_PSEUDOS and LIVE_PSEUDOS_REG_RENUMBER | |
370 | entries for pseudo REGNO. Assume that the register has been | |
371 | spilled if FREE_P, otherwise assume that it has been assigned | |
372 | reg_renumber[REGNO] (if >= 0). We also insert the pseudo live | |
373 | ranges in the start chains when it is assumed to be assigned to a | |
374 | hard register because we use the chains of pseudos assigned to hard | |
375 | registers during allocation. */ | |
376 | static void | |
377 | update_lives (int regno, bool free_p) | |
378 | { | |
379 | int p; | |
380 | lra_live_range_t r; | |
381 | ||
382 | if (reg_renumber[regno] < 0) | |
383 | return; | |
384 | live_pseudos_reg_renumber[regno] = free_p ? -1 : reg_renumber[regno]; | |
385 | for (r = lra_reg_info[regno].live_ranges; r != NULL; r = r->next) | |
386 | { | |
387 | for (p = r->start; p <= r->finish; p++) | |
388 | if (free_p) | |
389 | bitmap_clear_bit (&live_hard_reg_pseudos[p], regno); | |
390 | else | |
391 | { | |
392 | bitmap_set_bit (&live_hard_reg_pseudos[p], regno); | |
393 | insert_in_live_range_start_chain (regno); | |
394 | } | |
395 | } | |
396 | } | |
397 | ||
398 | /* Sparseset used to calculate reload pseudos conflicting with a given | |
399 | pseudo when we are trying to find a hard register for the given | |
400 | pseudo. */ | |
401 | static sparseset conflict_reload_and_inheritance_pseudos; | |
402 | ||
403 | /* Map: program point -> bitmap of all reload and inheritance pseudos | |
404 | living at the point. */ | |
405 | static bitmap_head *live_reload_and_inheritance_pseudos; | |
406 | static bitmap_obstack live_reload_and_inheritance_pseudos_bitmap_obstack; | |
407 | ||
408 | /* Allocate and initialize data about living reload pseudos at any | |
409 | given program point. */ | |
410 | static void | |
411 | init_live_reload_and_inheritance_pseudos (void) | |
412 | { | |
413 | int i, p, max_regno = max_reg_num (); | |
414 | lra_live_range_t r; | |
f4eafc30 | 415 | |
55a2c322 VM |
416 | conflict_reload_and_inheritance_pseudos = sparseset_alloc (max_regno); |
417 | live_reload_and_inheritance_pseudos = XNEWVEC (bitmap_head, lra_live_max_point); | |
418 | bitmap_obstack_initialize (&live_reload_and_inheritance_pseudos_bitmap_obstack); | |
419 | for (p = 0; p < lra_live_max_point; p++) | |
420 | bitmap_initialize (&live_reload_and_inheritance_pseudos[p], | |
421 | &live_reload_and_inheritance_pseudos_bitmap_obstack); | |
422 | for (i = lra_constraint_new_regno_start; i < max_regno; i++) | |
423 | { | |
424 | for (r = lra_reg_info[i].live_ranges; r != NULL; r = r->next) | |
425 | for (p = r->start; p <= r->finish; p++) | |
426 | bitmap_set_bit (&live_reload_and_inheritance_pseudos[p], i); | |
427 | } | |
428 | } | |
429 | ||
430 | /* Finalize data about living reload pseudos at any given program | |
431 | point. */ | |
432 | static void | |
433 | finish_live_reload_and_inheritance_pseudos (void) | |
434 | { | |
435 | sparseset_free (conflict_reload_and_inheritance_pseudos); | |
436 | free (live_reload_and_inheritance_pseudos); | |
437 | bitmap_obstack_release (&live_reload_and_inheritance_pseudos_bitmap_obstack); | |
438 | } | |
439 | ||
440 | /* The value used to check that cost of given hard reg is really | |
441 | defined currently. */ | |
442 | static int curr_hard_regno_costs_check = 0; | |
443 | /* Array used to check that cost of the corresponding hard reg (the | |
444 | array element index) is really defined currently. */ | |
445 | static int hard_regno_costs_check[FIRST_PSEUDO_REGISTER]; | |
446 | /* The current costs of allocation of hard regs. Defined only if the | |
447 | value of the corresponding element of the previous array is equal to | |
448 | CURR_HARD_REGNO_COSTS_CHECK. */ | |
449 | static int hard_regno_costs[FIRST_PSEUDO_REGISTER]; | |
450 | ||
451 | /* Adjust cost of HARD_REGNO by INCR. Reset the cost first if it is | |
452 | not defined yet. */ | |
453 | static inline void | |
454 | adjust_hard_regno_cost (int hard_regno, int incr) | |
455 | { | |
456 | if (hard_regno_costs_check[hard_regno] != curr_hard_regno_costs_check) | |
457 | hard_regno_costs[hard_regno] = 0; | |
458 | hard_regno_costs_check[hard_regno] = curr_hard_regno_costs_check; | |
459 | hard_regno_costs[hard_regno] += incr; | |
460 | } | |
461 | ||
462 | /* Try to find a free hard register for pseudo REGNO. Return the | |
463 | hard register on success and set *COST to the cost of using | |
464 | that register. (If several registers have equal cost, the one with | |
465 | the highest priority wins.) Return -1 on failure. | |
466 | ||
9e038952 VM |
467 | If FIRST_P, return the first available hard reg ignoring other |
468 | criteria, e.g. allocation cost. This approach results in less hard | |
469 | reg pool fragmentation and permit to allocate hard regs to reload | |
470 | pseudos in complicated situations where pseudo sizes are different. | |
471 | ||
55a2c322 | 472 | If TRY_ONLY_HARD_REGNO >= 0, consider only that hard register, |
34349d55 VM |
473 | otherwise consider all hard registers in REGNO's class. |
474 | ||
475 | If REGNO_SET is not empty, only hard registers from the set are | |
476 | considered. */ | |
55a2c322 | 477 | static int |
34349d55 VM |
478 | find_hard_regno_for_1 (int regno, int *cost, int try_only_hard_regno, |
479 | bool first_p, HARD_REG_SET regno_set) | |
55a2c322 VM |
480 | { |
481 | HARD_REG_SET conflict_set; | |
482 | int best_cost = INT_MAX, best_priority = INT_MIN, best_usage = INT_MAX; | |
483 | lra_live_range_t r; | |
484 | int p, i, j, rclass_size, best_hard_regno, priority, hard_regno; | |
485 | int hr, conflict_hr, nregs; | |
ef4bddc2 | 486 | machine_mode biggest_mode; |
55a2c322 | 487 | unsigned int k, conflict_regno; |
73ca989c RS |
488 | poly_int64 offset; |
489 | int val, biggest_nregs, nregs_diff; | |
55a2c322 VM |
490 | enum reg_class rclass; |
491 | bitmap_iterator bi; | |
492 | bool *rclass_intersect_p; | |
a4971e68 | 493 | HARD_REG_SET impossible_start_hard_regs, available_regs; |
55a2c322 | 494 | |
34349d55 | 495 | if (hard_reg_set_empty_p (regno_set)) |
6576d245 | 496 | conflict_set = lra_no_alloc_regs; |
34349d55 | 497 | else |
44942965 | 498 | conflict_set = ~regno_set | lra_no_alloc_regs; |
55a2c322 VM |
499 | rclass = regno_allocno_class_array[regno]; |
500 | rclass_intersect_p = ira_reg_classes_intersect_p[rclass]; | |
501 | curr_hard_regno_costs_check++; | |
502 | sparseset_clear (conflict_reload_and_inheritance_pseudos); | |
503 | sparseset_clear (live_range_hard_reg_pseudos); | |
44942965 | 504 | conflict_set |= lra_reg_info[regno].conflict_hard_regs; |
55a2c322 VM |
505 | biggest_mode = lra_reg_info[regno].biggest_mode; |
506 | for (r = lra_reg_info[regno].live_ranges; r != NULL; r = r->next) | |
507 | { | |
508 | EXECUTE_IF_SET_IN_BITMAP (&live_hard_reg_pseudos[r->start], 0, k, bi) | |
509 | if (rclass_intersect_p[regno_allocno_class_array[k]]) | |
510 | sparseset_set_bit (live_range_hard_reg_pseudos, k); | |
511 | EXECUTE_IF_SET_IN_BITMAP (&live_reload_and_inheritance_pseudos[r->start], | |
512 | 0, k, bi) | |
513 | if (lra_reg_info[k].preferred_hard_regno1 >= 0 | |
514 | && live_pseudos_reg_renumber[k] < 0 | |
515 | && rclass_intersect_p[regno_allocno_class_array[k]]) | |
516 | sparseset_set_bit (conflict_reload_and_inheritance_pseudos, k); | |
517 | for (p = r->start + 1; p <= r->finish; p++) | |
518 | { | |
519 | lra_live_range_t r2; | |
f4eafc30 | 520 | |
55a2c322 VM |
521 | for (r2 = start_point_ranges[p]; |
522 | r2 != NULL; | |
523 | r2 = r2->start_next) | |
524 | { | |
b66e613a RB |
525 | if (live_pseudos_reg_renumber[r2->regno] < 0 |
526 | && r2->regno >= lra_constraint_new_regno_start | |
55a2c322 | 527 | && lra_reg_info[r2->regno].preferred_hard_regno1 >= 0 |
55a2c322 VM |
528 | && rclass_intersect_p[regno_allocno_class_array[r2->regno]]) |
529 | sparseset_set_bit (conflict_reload_and_inheritance_pseudos, | |
530 | r2->regno); | |
b66e613a RB |
531 | else if (live_pseudos_reg_renumber[r2->regno] >= 0 |
532 | && rclass_intersect_p | |
533 | [regno_allocno_class_array[r2->regno]]) | |
55a2c322 VM |
534 | sparseset_set_bit (live_range_hard_reg_pseudos, r2->regno); |
535 | } | |
536 | } | |
537 | } | |
538 | if ((hard_regno = lra_reg_info[regno].preferred_hard_regno1) >= 0) | |
539 | { | |
540 | adjust_hard_regno_cost | |
541 | (hard_regno, -lra_reg_info[regno].preferred_hard_regno_profit1); | |
542 | if ((hard_regno = lra_reg_info[regno].preferred_hard_regno2) >= 0) | |
543 | adjust_hard_regno_cost | |
544 | (hard_regno, -lra_reg_info[regno].preferred_hard_regno_profit2); | |
545 | } | |
546 | #ifdef STACK_REGS | |
547 | if (lra_reg_info[regno].no_stack_p) | |
548 | for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++) | |
549 | SET_HARD_REG_BIT (conflict_set, i); | |
550 | #endif | |
551 | sparseset_clear_bit (conflict_reload_and_inheritance_pseudos, regno); | |
552 | val = lra_reg_info[regno].val; | |
d70a81dd | 553 | offset = lra_reg_info[regno].offset; |
85419ac5 | 554 | impossible_start_hard_regs = lra_reg_info[regno].exclude_start_hard_regs; |
55a2c322 | 555 | EXECUTE_IF_SET_IN_SPARSESET (live_range_hard_reg_pseudos, conflict_regno) |
9eb7045b VM |
556 | { |
557 | conflict_hr = live_pseudos_reg_renumber[conflict_regno]; | |
558 | if (lra_reg_val_equal_p (conflict_regno, val, offset)) | |
559 | { | |
560 | conflict_hr = live_pseudos_reg_renumber[conflict_regno]; | |
ad474626 RS |
561 | nregs = hard_regno_nregs (conflict_hr, |
562 | lra_reg_info[conflict_regno].biggest_mode); | |
9eb7045b VM |
563 | /* Remember about multi-register pseudos. For example, 2 |
564 | hard register pseudos can start on the same hard register | |
67914693 | 565 | but cannot start on HR and HR+1/HR-1. */ |
9eb7045b VM |
566 | for (hr = conflict_hr + 1; |
567 | hr < FIRST_PSEUDO_REGISTER && hr < conflict_hr + nregs; | |
568 | hr++) | |
569 | SET_HARD_REG_BIT (impossible_start_hard_regs, hr); | |
570 | for (hr = conflict_hr - 1; | |
4edd6298 | 571 | hr >= 0 && (int) end_hard_regno (biggest_mode, hr) > conflict_hr; |
9eb7045b VM |
572 | hr--) |
573 | SET_HARD_REG_BIT (impossible_start_hard_regs, hr); | |
574 | } | |
575 | else | |
576 | { | |
b8506a8a | 577 | machine_mode biggest_conflict_mode |
9eb7045b VM |
578 | = lra_reg_info[conflict_regno].biggest_mode; |
579 | int biggest_conflict_nregs | |
ad474626 | 580 | = hard_regno_nregs (conflict_hr, biggest_conflict_mode); |
9eb7045b | 581 | |
ad474626 RS |
582 | nregs_diff |
583 | = (biggest_conflict_nregs | |
584 | - hard_regno_nregs (conflict_hr, | |
585 | PSEUDO_REGNO_MODE (conflict_regno))); | |
9eb7045b VM |
586 | add_to_hard_reg_set (&conflict_set, |
587 | biggest_conflict_mode, | |
588 | conflict_hr | |
589 | - (WORDS_BIG_ENDIAN ? nregs_diff : 0)); | |
590 | if (hard_reg_set_subset_p (reg_class_contents[rclass], | |
591 | conflict_set)) | |
592 | return -1; | |
593 | } | |
594 | } | |
55a2c322 VM |
595 | EXECUTE_IF_SET_IN_SPARSESET (conflict_reload_and_inheritance_pseudos, |
596 | conflict_regno) | |
d70a81dd | 597 | if (!lra_reg_val_equal_p (conflict_regno, val, offset)) |
55a2c322 VM |
598 | { |
599 | lra_assert (live_pseudos_reg_renumber[conflict_regno] < 0); | |
600 | if ((hard_regno | |
601 | = lra_reg_info[conflict_regno].preferred_hard_regno1) >= 0) | |
602 | { | |
603 | adjust_hard_regno_cost | |
604 | (hard_regno, | |
605 | lra_reg_info[conflict_regno].preferred_hard_regno_profit1); | |
606 | if ((hard_regno | |
607 | = lra_reg_info[conflict_regno].preferred_hard_regno2) >= 0) | |
608 | adjust_hard_regno_cost | |
609 | (hard_regno, | |
610 | lra_reg_info[conflict_regno].preferred_hard_regno_profit2); | |
611 | } | |
612 | } | |
613 | /* Make sure that all registers in a multi-word pseudo belong to the | |
614 | required class. */ | |
4897c5aa | 615 | conflict_set |= ~reg_class_contents[rclass]; |
55a2c322 VM |
616 | lra_assert (rclass != NO_REGS); |
617 | rclass_size = ira_class_hard_regs_num[rclass]; | |
618 | best_hard_regno = -1; | |
619 | hard_regno = ira_class_hard_regs[rclass][0]; | |
ad474626 | 620 | biggest_nregs = hard_regno_nregs (hard_regno, biggest_mode); |
55a2c322 | 621 | nregs_diff = (biggest_nregs |
ad474626 | 622 | - hard_regno_nregs (hard_regno, PSEUDO_REGNO_MODE (regno))); |
d15e5131 | 623 | available_regs = reg_class_contents[rclass] & ~lra_no_alloc_regs; |
55a2c322 VM |
624 | for (i = 0; i < rclass_size; i++) |
625 | { | |
626 | if (try_only_hard_regno >= 0) | |
627 | hard_regno = try_only_hard_regno; | |
628 | else | |
629 | hard_regno = ira_class_hard_regs[rclass][i]; | |
630 | if (! overlaps_hard_reg_set_p (conflict_set, | |
631 | PSEUDO_REGNO_MODE (regno), hard_regno) | |
f939c3e6 RS |
632 | && targetm.hard_regno_mode_ok (hard_regno, |
633 | PSEUDO_REGNO_MODE (regno)) | |
67914693 | 634 | /* We cannot use prohibited_class_mode_regs for all classes |
7e964f49 VM |
635 | because it is not defined for all classes. */ |
636 | && (ira_allocno_class_translate[rclass] != rclass | |
637 | || ! TEST_HARD_REG_BIT (ira_prohibited_class_mode_regs | |
638 | [rclass][PSEUDO_REGNO_MODE (regno)], | |
639 | hard_regno)) | |
55a2c322 VM |
640 | && ! TEST_HARD_REG_BIT (impossible_start_hard_regs, hard_regno) |
641 | && (nregs_diff == 0 | |
a1b46e46 JR |
642 | || (WORDS_BIG_ENDIAN |
643 | ? (hard_regno - nregs_diff >= 0 | |
a4971e68 | 644 | && TEST_HARD_REG_BIT (available_regs, |
a1b46e46 | 645 | hard_regno - nregs_diff)) |
a4971e68 | 646 | : TEST_HARD_REG_BIT (available_regs, |
a1b46e46 | 647 | hard_regno + nregs_diff)))) |
55a2c322 VM |
648 | { |
649 | if (hard_regno_costs_check[hard_regno] | |
650 | != curr_hard_regno_costs_check) | |
651 | { | |
652 | hard_regno_costs_check[hard_regno] = curr_hard_regno_costs_check; | |
653 | hard_regno_costs[hard_regno] = 0; | |
654 | } | |
655 | for (j = 0; | |
ad474626 | 656 | j < hard_regno_nregs (hard_regno, PSEUDO_REGNO_MODE (regno)); |
55a2c322 | 657 | j++) |
a1e6ee38 | 658 | if (! crtl->abi->clobbers_full_reg_p (hard_regno + j) |
55a2c322 VM |
659 | && ! df_regs_ever_live_p (hard_regno + j)) |
660 | /* It needs save restore. */ | |
661 | hard_regno_costs[hard_regno] | |
fef37404 VM |
662 | += (2 |
663 | * REG_FREQ_FROM_BB (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb) | |
664 | + 1); | |
55a2c322 VM |
665 | priority = targetm.register_priority (hard_regno); |
666 | if (best_hard_regno < 0 || hard_regno_costs[hard_regno] < best_cost | |
667 | || (hard_regno_costs[hard_regno] == best_cost | |
668 | && (priority > best_priority | |
3b9ceb4b | 669 | || (targetm.register_usage_leveling_p () |
55a2c322 VM |
670 | && priority == best_priority |
671 | && best_usage > lra_hard_reg_usage[hard_regno])))) | |
672 | { | |
673 | best_hard_regno = hard_regno; | |
674 | best_cost = hard_regno_costs[hard_regno]; | |
675 | best_priority = priority; | |
676 | best_usage = lra_hard_reg_usage[hard_regno]; | |
677 | } | |
678 | } | |
9e038952 | 679 | if (try_only_hard_regno >= 0 || (first_p && best_hard_regno >= 0)) |
55a2c322 VM |
680 | break; |
681 | } | |
682 | if (best_hard_regno >= 0) | |
683 | *cost = best_cost - lra_reg_info[regno].freq; | |
684 | return best_hard_regno; | |
685 | } | |
686 | ||
34349d55 VM |
687 | /* A wrapper for find_hard_regno_for_1 (see comments for that function |
688 | description). This function tries to find a hard register for | |
689 | preferred class first if it is worth. */ | |
690 | static int | |
691 | find_hard_regno_for (int regno, int *cost, int try_only_hard_regno, bool first_p) | |
692 | { | |
693 | int hard_regno; | |
694 | HARD_REG_SET regno_set; | |
695 | ||
696 | /* Only original pseudos can have a different preferred class. */ | |
697 | if (try_only_hard_regno < 0 && regno < lra_new_regno_start) | |
698 | { | |
699 | enum reg_class pref_class = reg_preferred_class (regno); | |
700 | ||
701 | if (regno_allocno_class_array[regno] != pref_class) | |
702 | { | |
703 | hard_regno = find_hard_regno_for_1 (regno, cost, -1, first_p, | |
704 | reg_class_contents[pref_class]); | |
705 | if (hard_regno >= 0) | |
706 | return hard_regno; | |
707 | } | |
708 | } | |
709 | CLEAR_HARD_REG_SET (regno_set); | |
710 | return find_hard_regno_for_1 (regno, cost, try_only_hard_regno, first_p, | |
711 | regno_set); | |
712 | } | |
713 | ||
55a2c322 VM |
714 | /* Current value used for checking elements in |
715 | update_hard_regno_preference_check. */ | |
716 | static int curr_update_hard_regno_preference_check; | |
717 | /* If an element value is equal to the above variable value, then the | |
718 | corresponding regno has been processed for preference | |
719 | propagation. */ | |
720 | static int *update_hard_regno_preference_check; | |
721 | ||
722 | /* Update the preference for using HARD_REGNO for pseudos that are | |
723 | connected directly or indirectly with REGNO. Apply divisor DIV | |
724 | to any preference adjustments. | |
725 | ||
726 | The more indirectly a pseudo is connected, the smaller its effect | |
727 | should be. We therefore increase DIV on each "hop". */ | |
728 | static void | |
729 | update_hard_regno_preference (int regno, int hard_regno, int div) | |
730 | { | |
731 | int another_regno, cost; | |
732 | lra_copy_t cp, next_cp; | |
733 | ||
734 | /* Search depth 5 seems to be enough. */ | |
735 | if (div > (1 << 5)) | |
736 | return; | |
737 | for (cp = lra_reg_info[regno].copies; cp != NULL; cp = next_cp) | |
738 | { | |
739 | if (cp->regno1 == regno) | |
740 | { | |
741 | next_cp = cp->regno1_next; | |
742 | another_regno = cp->regno2; | |
743 | } | |
744 | else if (cp->regno2 == regno) | |
745 | { | |
746 | next_cp = cp->regno2_next; | |
747 | another_regno = cp->regno1; | |
748 | } | |
749 | else | |
750 | gcc_unreachable (); | |
751 | if (reg_renumber[another_regno] < 0 | |
752 | && (update_hard_regno_preference_check[another_regno] | |
753 | != curr_update_hard_regno_preference_check)) | |
754 | { | |
755 | update_hard_regno_preference_check[another_regno] | |
756 | = curr_update_hard_regno_preference_check; | |
757 | cost = cp->freq < div ? 1 : cp->freq / div; | |
758 | lra_setup_reload_pseudo_preferenced_hard_reg | |
759 | (another_regno, hard_regno, cost); | |
760 | update_hard_regno_preference (another_regno, hard_regno, div * 2); | |
761 | } | |
762 | } | |
763 | } | |
764 | ||
2b778c9d VM |
765 | /* Return prefix title for pseudo REGNO. */ |
766 | static const char * | |
767 | pseudo_prefix_title (int regno) | |
768 | { | |
769 | return | |
770 | (regno < lra_constraint_new_regno_start ? "" | |
771 | : bitmap_bit_p (&lra_inheritance_pseudos, regno) ? "inheritance " | |
772 | : bitmap_bit_p (&lra_split_regs, regno) ? "split " | |
773 | : bitmap_bit_p (&lra_optional_reload_pseudos, regno) ? "optional reload " | |
774 | : bitmap_bit_p (&lra_subreg_reload_pseudos, regno) ? "subreg reload " | |
775 | : "reload "); | |
776 | } | |
777 | ||
55a2c322 VM |
778 | /* Update REG_RENUMBER and other pseudo preferences by assignment of |
779 | HARD_REGNO to pseudo REGNO and print about it if PRINT_P. */ | |
780 | void | |
781 | lra_setup_reg_renumber (int regno, int hard_regno, bool print_p) | |
782 | { | |
783 | int i, hr; | |
784 | ||
67914693 | 785 | /* We cannot just reassign hard register. */ |
55a2c322 VM |
786 | lra_assert (hard_regno < 0 || reg_renumber[regno] < 0); |
787 | if ((hr = hard_regno) < 0) | |
788 | hr = reg_renumber[regno]; | |
789 | reg_renumber[regno] = hard_regno; | |
790 | lra_assert (hr >= 0); | |
ad474626 | 791 | for (i = 0; i < hard_regno_nregs (hr, PSEUDO_REGNO_MODE (regno)); i++) |
55a2c322 VM |
792 | if (hard_regno < 0) |
793 | lra_hard_reg_usage[hr + i] -= lra_reg_info[regno].freq; | |
794 | else | |
795 | lra_hard_reg_usage[hr + i] += lra_reg_info[regno].freq; | |
796 | if (print_p && lra_dump_file != NULL) | |
797 | fprintf (lra_dump_file, " Assign %d to %sr%d (freq=%d)\n", | |
2b778c9d | 798 | reg_renumber[regno], pseudo_prefix_title (regno), |
55a2c322 VM |
799 | regno, lra_reg_info[regno].freq); |
800 | if (hard_regno >= 0) | |
801 | { | |
802 | curr_update_hard_regno_preference_check++; | |
803 | update_hard_regno_preference (regno, hard_regno, 1); | |
804 | } | |
805 | } | |
806 | ||
807 | /* Pseudos which occur in insns containing a particular pseudo. */ | |
808 | static bitmap_head insn_conflict_pseudos; | |
809 | ||
810 | /* Bitmaps used to contain spill pseudos for given pseudo hard regno | |
811 | and best spill pseudos for given pseudo (and best hard regno). */ | |
812 | static bitmap_head spill_pseudos_bitmap, best_spill_pseudos_bitmap; | |
813 | ||
814 | /* Current pseudo check for validity of elements in | |
815 | TRY_HARD_REG_PSEUDOS. */ | |
816 | static int curr_pseudo_check; | |
817 | /* Array used for validity of elements in TRY_HARD_REG_PSEUDOS. */ | |
818 | static int try_hard_reg_pseudos_check[FIRST_PSEUDO_REGISTER]; | |
819 | /* Pseudos who hold given hard register at the considered points. */ | |
820 | static bitmap_head try_hard_reg_pseudos[FIRST_PSEUDO_REGISTER]; | |
821 | ||
822 | /* Set up try_hard_reg_pseudos for given program point P and class | |
823 | RCLASS. Those are pseudos living at P and assigned to a hard | |
824 | register of RCLASS. In other words, those are pseudos which can be | |
825 | spilled to assign a hard register of RCLASS to a pseudo living at | |
826 | P. */ | |
827 | static void | |
828 | setup_try_hard_regno_pseudos (int p, enum reg_class rclass) | |
829 | { | |
830 | int i, hard_regno; | |
ef4bddc2 | 831 | machine_mode mode; |
55a2c322 VM |
832 | unsigned int spill_regno; |
833 | bitmap_iterator bi; | |
834 | ||
835 | /* Find what pseudos could be spilled. */ | |
836 | EXECUTE_IF_SET_IN_BITMAP (&live_hard_reg_pseudos[p], 0, spill_regno, bi) | |
837 | { | |
838 | mode = PSEUDO_REGNO_MODE (spill_regno); | |
839 | hard_regno = live_pseudos_reg_renumber[spill_regno]; | |
840 | if (overlaps_hard_reg_set_p (reg_class_contents[rclass], | |
841 | mode, hard_regno)) | |
842 | { | |
ad474626 | 843 | for (i = hard_regno_nregs (hard_regno, mode) - 1; i >= 0; i--) |
55a2c322 VM |
844 | { |
845 | if (try_hard_reg_pseudos_check[hard_regno + i] | |
846 | != curr_pseudo_check) | |
847 | { | |
848 | try_hard_reg_pseudos_check[hard_regno + i] | |
849 | = curr_pseudo_check; | |
850 | bitmap_clear (&try_hard_reg_pseudos[hard_regno + i]); | |
851 | } | |
852 | bitmap_set_bit (&try_hard_reg_pseudos[hard_regno + i], | |
853 | spill_regno); | |
854 | } | |
855 | } | |
856 | } | |
857 | } | |
858 | ||
859 | /* Assign temporarily HARD_REGNO to pseudo REGNO. Temporary | |
860 | assignment means that we might undo the data change. */ | |
861 | static void | |
862 | assign_temporarily (int regno, int hard_regno) | |
863 | { | |
864 | int p; | |
865 | lra_live_range_t r; | |
866 | ||
867 | for (r = lra_reg_info[regno].live_ranges; r != NULL; r = r->next) | |
868 | { | |
869 | for (p = r->start; p <= r->finish; p++) | |
870 | if (hard_regno < 0) | |
871 | bitmap_clear_bit (&live_hard_reg_pseudos[p], regno); | |
872 | else | |
873 | { | |
874 | bitmap_set_bit (&live_hard_reg_pseudos[p], regno); | |
875 | insert_in_live_range_start_chain (regno); | |
876 | } | |
877 | } | |
878 | live_pseudos_reg_renumber[regno] = hard_regno; | |
879 | } | |
880 | ||
8f2f6381 BS |
881 | /* Return true iff there is a reason why pseudo SPILL_REGNO should not |
882 | be spilled. */ | |
883 | static bool | |
884 | must_not_spill_p (unsigned spill_regno) | |
885 | { | |
886 | if ((pic_offset_table_rtx != NULL | |
887 | && spill_regno == REGNO (pic_offset_table_rtx)) | |
888 | || ((int) spill_regno >= lra_constraint_new_regno_start | |
889 | && ! bitmap_bit_p (&lra_inheritance_pseudos, spill_regno) | |
890 | && ! bitmap_bit_p (&lra_split_regs, spill_regno) | |
891 | && ! bitmap_bit_p (&lra_subreg_reload_pseudos, spill_regno) | |
892 | && ! bitmap_bit_p (&lra_optional_reload_pseudos, spill_regno))) | |
893 | return true; | |
894 | /* A reload pseudo that requires a singleton register class should | |
895 | not be spilled. | |
896 | FIXME: this mitigates the issue on certain i386 patterns, but | |
897 | does not solve the general case where existing reloads fully | |
898 | cover a limited register class. */ | |
899 | if (!bitmap_bit_p (&non_reload_pseudos, spill_regno) | |
5da906ca BS |
900 | && reg_class_size [reg_preferred_class (spill_regno)] == 1 |
901 | && reg_alternate_class (spill_regno) == NO_REGS) | |
8f2f6381 BS |
902 | return true; |
903 | return false; | |
904 | } | |
905 | ||
55a2c322 VM |
906 | /* Array used for sorting reload pseudos for subsequent allocation |
907 | after spilling some pseudo. */ | |
908 | static int *sorted_reload_pseudos; | |
909 | ||
910 | /* Spill some pseudos for a reload pseudo REGNO and return hard | |
911 | register which should be used for pseudo after spilling. The | |
912 | function adds spilled pseudos to SPILLED_PSEUDO_BITMAP. When we | |
913 | choose hard register (and pseudos occupying the hard registers and | |
914 | to be spilled), we take into account not only how REGNO will | |
915 | benefit from the spills but also how other reload pseudos not yet | |
916 | assigned to hard registers benefit from the spills too. In very | |
9e038952 VM |
917 | rare cases, the function can fail and return -1. |
918 | ||
919 | If FIRST_P, return the first available hard reg ignoring other | |
920 | criteria, e.g. allocation cost and cost of spilling non-reload | |
921 | pseudos. This approach results in less hard reg pool fragmentation | |
922 | and permit to allocate hard regs to reload pseudos in complicated | |
923 | situations where pseudo sizes are different. */ | |
55a2c322 | 924 | static int |
9e038952 | 925 | spill_for (int regno, bitmap spilled_pseudo_bitmap, bool first_p) |
55a2c322 VM |
926 | { |
927 | int i, j, n, p, hard_regno, best_hard_regno, cost, best_cost, rclass_size; | |
928 | int reload_hard_regno, reload_cost; | |
b81a2f0d | 929 | bool static_p, best_static_p; |
ef4bddc2 | 930 | machine_mode mode; |
55a2c322 | 931 | enum reg_class rclass; |
55a2c322 VM |
932 | unsigned int spill_regno, reload_regno, uid; |
933 | int insn_pseudos_num, best_insn_pseudos_num; | |
8fd827b8 | 934 | int bad_spills_num, smallest_bad_spills_num; |
55a2c322 VM |
935 | lra_live_range_t r; |
936 | bitmap_iterator bi; | |
937 | ||
938 | rclass = regno_allocno_class_array[regno]; | |
939 | lra_assert (reg_renumber[regno] < 0 && rclass != NO_REGS); | |
940 | bitmap_clear (&insn_conflict_pseudos); | |
941 | bitmap_clear (&best_spill_pseudos_bitmap); | |
942 | EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi) | |
943 | { | |
944 | struct lra_insn_reg *ir; | |
f4eafc30 | 945 | |
55a2c322 VM |
946 | for (ir = lra_get_insn_regs (uid); ir != NULL; ir = ir->next) |
947 | if (ir->regno >= FIRST_PSEUDO_REGISTER) | |
948 | bitmap_set_bit (&insn_conflict_pseudos, ir->regno); | |
949 | } | |
950 | best_hard_regno = -1; | |
951 | best_cost = INT_MAX; | |
ad71cd89 | 952 | best_static_p = true; |
55a2c322 | 953 | best_insn_pseudos_num = INT_MAX; |
8fd827b8 | 954 | smallest_bad_spills_num = INT_MAX; |
55a2c322 VM |
955 | rclass_size = ira_class_hard_regs_num[rclass]; |
956 | mode = PSEUDO_REGNO_MODE (regno); | |
957 | /* Invalidate try_hard_reg_pseudos elements. */ | |
958 | curr_pseudo_check++; | |
959 | for (r = lra_reg_info[regno].live_ranges; r != NULL; r = r->next) | |
960 | for (p = r->start; p <= r->finish; p++) | |
961 | setup_try_hard_regno_pseudos (p, rclass); | |
962 | for (i = 0; i < rclass_size; i++) | |
963 | { | |
964 | hard_regno = ira_class_hard_regs[rclass][i]; | |
965 | bitmap_clear (&spill_pseudos_bitmap); | |
ad474626 | 966 | for (j = hard_regno_nregs (hard_regno, mode) - 1; j >= 0; j--) |
55a2c322 | 967 | { |
d26f37a1 VM |
968 | if (hard_regno + j >= FIRST_PSEUDO_REGISTER) |
969 | break; | |
55a2c322 VM |
970 | if (try_hard_reg_pseudos_check[hard_regno + j] != curr_pseudo_check) |
971 | continue; | |
972 | lra_assert (!bitmap_empty_p (&try_hard_reg_pseudos[hard_regno + j])); | |
973 | bitmap_ior_into (&spill_pseudos_bitmap, | |
974 | &try_hard_reg_pseudos[hard_regno + j]); | |
975 | } | |
976 | /* Spill pseudos. */ | |
b81a2f0d | 977 | static_p = false; |
55a2c322 | 978 | EXECUTE_IF_SET_IN_BITMAP (&spill_pseudos_bitmap, 0, spill_regno, bi) |
8f2f6381 | 979 | if (must_not_spill_p (spill_regno)) |
55a2c322 | 980 | goto fail; |
b81a2f0d VM |
981 | else if (non_spilled_static_chain_regno_p (spill_regno)) |
982 | static_p = true; | |
55a2c322 | 983 | insn_pseudos_num = 0; |
8fd827b8 | 984 | bad_spills_num = 0; |
55a2c322 VM |
985 | if (lra_dump_file != NULL) |
986 | fprintf (lra_dump_file, " Trying %d:", hard_regno); | |
987 | sparseset_clear (live_range_reload_inheritance_pseudos); | |
988 | EXECUTE_IF_SET_IN_BITMAP (&spill_pseudos_bitmap, 0, spill_regno, bi) | |
989 | { | |
990 | if (bitmap_bit_p (&insn_conflict_pseudos, spill_regno)) | |
991 | insn_pseudos_num++; | |
8fd827b8 VM |
992 | if (spill_regno >= (unsigned int) lra_bad_spill_regno_start) |
993 | bad_spills_num++; | |
55a2c322 VM |
994 | for (r = lra_reg_info[spill_regno].live_ranges; |
995 | r != NULL; | |
996 | r = r->next) | |
997 | { | |
998 | for (p = r->start; p <= r->finish; p++) | |
999 | { | |
1000 | lra_live_range_t r2; | |
f4eafc30 | 1001 | |
55a2c322 VM |
1002 | for (r2 = start_point_ranges[p]; |
1003 | r2 != NULL; | |
1004 | r2 = r2->start_next) | |
1005 | if (r2->regno >= lra_constraint_new_regno_start) | |
1006 | sparseset_set_bit (live_range_reload_inheritance_pseudos, | |
1007 | r2->regno); | |
1008 | } | |
1009 | } | |
1010 | } | |
295d875c | 1011 | n = 0; |
88def637 | 1012 | if (sparseset_cardinality (live_range_reload_inheritance_pseudos) |
028d4092 | 1013 | <= (unsigned)param_lra_max_considered_reload_pseudos) |
88def637 VM |
1014 | EXECUTE_IF_SET_IN_SPARSESET (live_range_reload_inheritance_pseudos, |
1015 | reload_regno) | |
1016 | if ((int) reload_regno != regno | |
1017 | && (ira_reg_classes_intersect_p | |
1018 | [rclass][regno_allocno_class_array[reload_regno]]) | |
1019 | && live_pseudos_reg_renumber[reload_regno] < 0 | |
9e038952 | 1020 | && find_hard_regno_for (reload_regno, &cost, -1, first_p) < 0) |
88def637 | 1021 | sorted_reload_pseudos[n++] = reload_regno; |
295d875c VM |
1022 | EXECUTE_IF_SET_IN_BITMAP (&spill_pseudos_bitmap, 0, spill_regno, bi) |
1023 | { | |
1024 | update_lives (spill_regno, true); | |
1025 | if (lra_dump_file != NULL) | |
1026 | fprintf (lra_dump_file, " spill %d(freq=%d)", | |
1027 | spill_regno, lra_reg_info[spill_regno].freq); | |
1028 | } | |
9e038952 | 1029 | hard_regno = find_hard_regno_for (regno, &cost, -1, first_p); |
55a2c322 VM |
1030 | if (hard_regno >= 0) |
1031 | { | |
1032 | assign_temporarily (regno, hard_regno); | |
55a2c322 VM |
1033 | qsort (sorted_reload_pseudos, n, sizeof (int), |
1034 | reload_pseudo_compare_func); | |
1035 | for (j = 0; j < n; j++) | |
1036 | { | |
1037 | reload_regno = sorted_reload_pseudos[j]; | |
1038 | lra_assert (live_pseudos_reg_renumber[reload_regno] < 0); | |
1039 | if ((reload_hard_regno | |
1040 | = find_hard_regno_for (reload_regno, | |
9e038952 | 1041 | &reload_cost, -1, first_p)) >= 0) |
55a2c322 VM |
1042 | { |
1043 | if (lra_dump_file != NULL) | |
1044 | fprintf (lra_dump_file, " assign %d(cost=%d)", | |
1045 | reload_regno, reload_cost); | |
1046 | assign_temporarily (reload_regno, reload_hard_regno); | |
1047 | cost += reload_cost; | |
1048 | } | |
1049 | } | |
1050 | EXECUTE_IF_SET_IN_BITMAP (&spill_pseudos_bitmap, 0, spill_regno, bi) | |
1051 | { | |
0cc97fc5 | 1052 | rtx_insn_list *x; |
f4eafc30 | 1053 | |
55a2c322 VM |
1054 | cost += lra_reg_info[spill_regno].freq; |
1055 | if (ira_reg_equiv[spill_regno].memory != NULL | |
1056 | || ira_reg_equiv[spill_regno].constant != NULL) | |
1057 | for (x = ira_reg_equiv[spill_regno].init_insns; | |
1058 | x != NULL; | |
0cc97fc5 DM |
1059 | x = x->next ()) |
1060 | cost -= REG_FREQ_FROM_BB (BLOCK_FOR_INSN (x->insn ())); | |
55a2c322 | 1061 | } |
b81a2f0d VM |
1062 | /* Avoid spilling static chain pointer pseudo when non-local |
1063 | goto is used. */ | |
1064 | if ((! static_p && best_static_p) | |
1065 | || (static_p == best_static_p | |
1066 | && (best_insn_pseudos_num > insn_pseudos_num | |
1067 | || (best_insn_pseudos_num == insn_pseudos_num | |
1068 | && (bad_spills_num < smallest_bad_spills_num | |
1069 | || (bad_spills_num == smallest_bad_spills_num | |
1070 | && best_cost > cost)))))) | |
55a2c322 VM |
1071 | { |
1072 | best_insn_pseudos_num = insn_pseudos_num; | |
54e915b3 | 1073 | smallest_bad_spills_num = bad_spills_num; |
b81a2f0d | 1074 | best_static_p = static_p; |
55a2c322 VM |
1075 | best_cost = cost; |
1076 | best_hard_regno = hard_regno; | |
1077 | bitmap_copy (&best_spill_pseudos_bitmap, &spill_pseudos_bitmap); | |
1078 | if (lra_dump_file != NULL) | |
54e915b3 VM |
1079 | fprintf (lra_dump_file, |
1080 | " Now best %d(cost=%d, bad_spills=%d, insn_pseudos=%d)\n", | |
1081 | hard_regno, cost, bad_spills_num, insn_pseudos_num); | |
55a2c322 VM |
1082 | } |
1083 | assign_temporarily (regno, -1); | |
1084 | for (j = 0; j < n; j++) | |
1085 | { | |
1086 | reload_regno = sorted_reload_pseudos[j]; | |
1087 | if (live_pseudos_reg_renumber[reload_regno] >= 0) | |
1088 | assign_temporarily (reload_regno, -1); | |
1089 | } | |
1090 | } | |
1091 | if (lra_dump_file != NULL) | |
1092 | fprintf (lra_dump_file, "\n"); | |
1093 | /* Restore the live hard reg pseudo info for spilled pseudos. */ | |
1094 | EXECUTE_IF_SET_IN_BITMAP (&spill_pseudos_bitmap, 0, spill_regno, bi) | |
1095 | update_lives (spill_regno, false); | |
1096 | fail: | |
1097 | ; | |
1098 | } | |
1099 | /* Spill: */ | |
1100 | EXECUTE_IF_SET_IN_BITMAP (&best_spill_pseudos_bitmap, 0, spill_regno, bi) | |
1101 | { | |
f54437d5 VM |
1102 | if ((int) spill_regno >= lra_constraint_new_regno_start) |
1103 | former_reload_pseudo_spill_p = true; | |
55a2c322 VM |
1104 | if (lra_dump_file != NULL) |
1105 | fprintf (lra_dump_file, " Spill %sr%d(hr=%d, freq=%d) for r%d\n", | |
2b778c9d | 1106 | pseudo_prefix_title (spill_regno), |
55a2c322 VM |
1107 | spill_regno, reg_renumber[spill_regno], |
1108 | lra_reg_info[spill_regno].freq, regno); | |
1109 | update_lives (spill_regno, true); | |
1110 | lra_setup_reg_renumber (spill_regno, -1, false); | |
1111 | } | |
1112 | bitmap_ior_into (spilled_pseudo_bitmap, &best_spill_pseudos_bitmap); | |
1113 | return best_hard_regno; | |
1114 | } | |
1115 | ||
1116 | /* Assign HARD_REGNO to REGNO. */ | |
1117 | static void | |
1118 | assign_hard_regno (int hard_regno, int regno) | |
1119 | { | |
1120 | int i; | |
1121 | ||
1122 | lra_assert (hard_regno >= 0); | |
1123 | lra_setup_reg_renumber (regno, hard_regno, true); | |
1124 | update_lives (regno, false); | |
1125 | for (i = 0; | |
ad474626 | 1126 | i < hard_regno_nregs (hard_regno, lra_reg_info[regno].biggest_mode); |
55a2c322 VM |
1127 | i++) |
1128 | df_set_regs_ever_live (hard_regno + i, true); | |
1129 | } | |
1130 | ||
1131 | /* Array used for sorting different pseudos. */ | |
1132 | static int *sorted_pseudos; | |
1133 | ||
1134 | /* The constraints pass is allowed to create equivalences between | |
1135 | pseudos that make the current allocation "incorrect" (in the sense | |
1136 | that pseudos are assigned to hard registers from their own conflict | |
7436a1c6 | 1137 | sets). The global variable check_and_force_assignment_correctness_p says |
55a2c322 VM |
1138 | whether this might have happened. |
1139 | ||
1140 | Process pseudos assigned to hard registers (less frequently used | |
1141 | first), spill if a conflict is found, and mark the spilled pseudos | |
1142 | in SPILLED_PSEUDO_BITMAP. Set up LIVE_HARD_REG_PSEUDOS from | |
1143 | pseudos, assigned to hard registers. */ | |
1144 | static void | |
1145 | setup_live_pseudos_and_spill_after_risky_transforms (bitmap | |
1146 | spilled_pseudo_bitmap) | |
1147 | { | |
7e4d17a8 | 1148 | int p, i, j, n, regno, hard_regno, biggest_nregs, nregs_diff; |
55a2c322 | 1149 | unsigned int k, conflict_regno; |
73ca989c RS |
1150 | poly_int64 offset; |
1151 | int val; | |
55a2c322 | 1152 | HARD_REG_SET conflict_set; |
7e4d17a8 | 1153 | machine_mode mode, biggest_mode; |
55a2c322 VM |
1154 | lra_live_range_t r; |
1155 | bitmap_iterator bi; | |
1156 | int max_regno = max_reg_num (); | |
1157 | ||
7436a1c6 | 1158 | if (! check_and_force_assignment_correctness_p) |
55a2c322 VM |
1159 | { |
1160 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
1161 | if (reg_renumber[i] >= 0 && lra_reg_info[i].nrefs > 0) | |
1162 | update_lives (i, false); | |
1163 | return; | |
1164 | } | |
1165 | for (n = 0, i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
bcb21886 KY |
1166 | if ((pic_offset_table_rtx == NULL_RTX |
1167 | || i != (int) REGNO (pic_offset_table_rtx)) | |
7e4d17a8 VM |
1168 | && (hard_regno = reg_renumber[i]) >= 0 && lra_reg_info[i].nrefs > 0) |
1169 | { | |
1170 | biggest_mode = lra_reg_info[i].biggest_mode; | |
1171 | biggest_nregs = hard_regno_nregs (hard_regno, biggest_mode); | |
1172 | nregs_diff = (biggest_nregs | |
1173 | - hard_regno_nregs (hard_regno, PSEUDO_REGNO_MODE (i))); | |
1174 | enum reg_class rclass = lra_get_allocno_class (i); | |
1175 | ||
4321da7b VM |
1176 | if ((WORDS_BIG_ENDIAN |
1177 | && (hard_regno - nregs_diff < 0 | |
1178 | || !TEST_HARD_REG_BIT (reg_class_contents[rclass], | |
1179 | hard_regno - nregs_diff))) | |
1180 | || (!WORDS_BIG_ENDIAN | |
1181 | && (hard_regno + nregs_diff >= FIRST_PSEUDO_REGISTER | |
1182 | || !TEST_HARD_REG_BIT (reg_class_contents[rclass], | |
1183 | hard_regno + nregs_diff)))) | |
7e4d17a8 VM |
1184 | { |
1185 | /* Hard registers of paradoxical sub-registers are out of | |
1186 | range of pseudo register class. Spill the pseudo. */ | |
1187 | reg_renumber[i] = -1; | |
1188 | continue; | |
1189 | } | |
1190 | sorted_pseudos[n++] = i; | |
1191 | } | |
55a2c322 | 1192 | qsort (sorted_pseudos, n, sizeof (int), pseudo_compare_func); |
bcb21886 KY |
1193 | if (pic_offset_table_rtx != NULL_RTX |
1194 | && (regno = REGNO (pic_offset_table_rtx)) >= FIRST_PSEUDO_REGISTER | |
1195 | && reg_renumber[regno] >= 0 && lra_reg_info[regno].nrefs > 0) | |
1196 | sorted_pseudos[n++] = regno; | |
55a2c322 VM |
1197 | for (i = n - 1; i >= 0; i--) |
1198 | { | |
1199 | regno = sorted_pseudos[i]; | |
1200 | hard_regno = reg_renumber[regno]; | |
1201 | lra_assert (hard_regno >= 0); | |
1202 | mode = lra_reg_info[regno].biggest_mode; | |
1203 | sparseset_clear (live_range_hard_reg_pseudos); | |
1204 | for (r = lra_reg_info[regno].live_ranges; r != NULL; r = r->next) | |
1205 | { | |
1206 | EXECUTE_IF_SET_IN_BITMAP (&live_hard_reg_pseudos[r->start], 0, k, bi) | |
1207 | sparseset_set_bit (live_range_hard_reg_pseudos, k); | |
1208 | for (p = r->start + 1; p <= r->finish; p++) | |
1209 | { | |
1210 | lra_live_range_t r2; | |
f4eafc30 | 1211 | |
55a2c322 VM |
1212 | for (r2 = start_point_ranges[p]; |
1213 | r2 != NULL; | |
1214 | r2 = r2->start_next) | |
1215 | if (live_pseudos_reg_renumber[r2->regno] >= 0) | |
1216 | sparseset_set_bit (live_range_hard_reg_pseudos, r2->regno); | |
1217 | } | |
1218 | } | |
6576d245 | 1219 | conflict_set = lra_no_alloc_regs; |
44942965 | 1220 | conflict_set |= lra_reg_info[regno].conflict_hard_regs; |
55a2c322 | 1221 | val = lra_reg_info[regno].val; |
d70a81dd | 1222 | offset = lra_reg_info[regno].offset; |
55a2c322 | 1223 | EXECUTE_IF_SET_IN_SPARSESET (live_range_hard_reg_pseudos, conflict_regno) |
d70a81dd | 1224 | if (!lra_reg_val_equal_p (conflict_regno, val, offset) |
55a2c322 VM |
1225 | /* If it is multi-register pseudos they should start on |
1226 | the same hard register. */ | |
1227 | || hard_regno != reg_renumber[conflict_regno]) | |
15961e4a VM |
1228 | { |
1229 | int conflict_hard_regno = reg_renumber[conflict_regno]; | |
7e4d17a8 VM |
1230 | |
1231 | biggest_mode = lra_reg_info[conflict_regno].biggest_mode; | |
1232 | biggest_nregs = hard_regno_nregs (conflict_hard_regno, | |
1233 | biggest_mode); | |
1234 | nregs_diff | |
ad474626 RS |
1235 | = (biggest_nregs |
1236 | - hard_regno_nregs (conflict_hard_regno, | |
1237 | PSEUDO_REGNO_MODE (conflict_regno))); | |
15961e4a VM |
1238 | add_to_hard_reg_set (&conflict_set, |
1239 | biggest_mode, | |
1240 | conflict_hard_regno | |
1241 | - (WORDS_BIG_ENDIAN ? nregs_diff : 0)); | |
1242 | } | |
55a2c322 VM |
1243 | if (! overlaps_hard_reg_set_p (conflict_set, mode, hard_regno)) |
1244 | { | |
1245 | update_lives (regno, false); | |
1246 | continue; | |
1247 | } | |
1248 | bitmap_set_bit (spilled_pseudo_bitmap, regno); | |
1249 | for (j = 0; | |
ad474626 | 1250 | j < hard_regno_nregs (hard_regno, PSEUDO_REGNO_MODE (regno)); |
55a2c322 VM |
1251 | j++) |
1252 | lra_hard_reg_usage[hard_regno + j] -= lra_reg_info[regno].freq; | |
1253 | reg_renumber[regno] = -1; | |
f54437d5 VM |
1254 | if (regno >= lra_constraint_new_regno_start) |
1255 | former_reload_pseudo_spill_p = true; | |
55a2c322 VM |
1256 | if (lra_dump_file != NULL) |
1257 | fprintf (lra_dump_file, " Spill r%d after risky transformations\n", | |
1258 | regno); | |
1259 | } | |
1260 | } | |
1261 | ||
1262 | /* Improve allocation by assigning the same hard regno of inheritance | |
1263 | pseudos to the connected pseudos. We need this because inheritance | |
1264 | pseudos are allocated after reload pseudos in the thread and when | |
1265 | we assign a hard register to a reload pseudo we don't know yet that | |
1266 | the connected inheritance pseudos can get the same hard register. | |
1267 | Add pseudos with changed allocation to bitmap CHANGED_PSEUDOS. */ | |
1268 | static void | |
1269 | improve_inheritance (bitmap changed_pseudos) | |
1270 | { | |
1271 | unsigned int k; | |
1272 | int regno, another_regno, hard_regno, another_hard_regno, cost, i, n; | |
1273 | lra_copy_t cp, next_cp; | |
1274 | bitmap_iterator bi; | |
1275 | ||
8e3a4869 VM |
1276 | if (lra_inheritance_iter > LRA_MAX_INHERITANCE_PASSES) |
1277 | return; | |
55a2c322 VM |
1278 | n = 0; |
1279 | EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos, 0, k, bi) | |
1280 | if (reg_renumber[k] >= 0 && lra_reg_info[k].nrefs != 0) | |
1281 | sorted_pseudos[n++] = k; | |
1282 | qsort (sorted_pseudos, n, sizeof (int), pseudo_compare_func); | |
1283 | for (i = 0; i < n; i++) | |
1284 | { | |
1285 | regno = sorted_pseudos[i]; | |
1286 | hard_regno = reg_renumber[regno]; | |
1287 | lra_assert (hard_regno >= 0); | |
1288 | for (cp = lra_reg_info[regno].copies; cp != NULL; cp = next_cp) | |
1289 | { | |
1290 | if (cp->regno1 == regno) | |
1291 | { | |
1292 | next_cp = cp->regno1_next; | |
1293 | another_regno = cp->regno2; | |
1294 | } | |
1295 | else if (cp->regno2 == regno) | |
1296 | { | |
1297 | next_cp = cp->regno2_next; | |
1298 | another_regno = cp->regno1; | |
1299 | } | |
1300 | else | |
1301 | gcc_unreachable (); | |
1302 | /* Don't change reload pseudo allocation. It might have | |
1303 | this allocation for a purpose and changing it can result | |
1304 | in LRA cycling. */ | |
1305 | if ((another_regno < lra_constraint_new_regno_start | |
1306 | || bitmap_bit_p (&lra_inheritance_pseudos, another_regno)) | |
1307 | && (another_hard_regno = reg_renumber[another_regno]) >= 0 | |
1308 | && another_hard_regno != hard_regno) | |
1309 | { | |
1310 | if (lra_dump_file != NULL) | |
1311 | fprintf | |
1312 | (lra_dump_file, | |
1313 | " Improving inheritance for %d(%d) and %d(%d)...\n", | |
1314 | regno, hard_regno, another_regno, another_hard_regno); | |
1315 | update_lives (another_regno, true); | |
1316 | lra_setup_reg_renumber (another_regno, -1, false); | |
9e038952 VM |
1317 | if (hard_regno == find_hard_regno_for (another_regno, &cost, |
1318 | hard_regno, false)) | |
55a2c322 VM |
1319 | assign_hard_regno (hard_regno, another_regno); |
1320 | else | |
1321 | assign_hard_regno (another_hard_regno, another_regno); | |
1322 | bitmap_set_bit (changed_pseudos, another_regno); | |
1323 | } | |
1324 | } | |
1325 | } | |
1326 | } | |
1327 | ||
1328 | ||
1329 | /* Bitmap finally containing all pseudos spilled on this assignment | |
1330 | pass. */ | |
1331 | static bitmap_head all_spilled_pseudos; | |
1332 | /* All pseudos whose allocation was changed. */ | |
1333 | static bitmap_head changed_pseudo_bitmap; | |
1334 | ||
9e038952 VM |
1335 | |
1336 | /* Add to LIVE_RANGE_HARD_REG_PSEUDOS all pseudos conflicting with | |
1337 | REGNO and whose hard regs can be assigned to REGNO. */ | |
1338 | static void | |
1339 | find_all_spills_for (int regno) | |
1340 | { | |
1341 | int p; | |
1342 | lra_live_range_t r; | |
1343 | unsigned int k; | |
1344 | bitmap_iterator bi; | |
1345 | enum reg_class rclass; | |
1346 | bool *rclass_intersect_p; | |
1347 | ||
1348 | rclass = regno_allocno_class_array[regno]; | |
1349 | rclass_intersect_p = ira_reg_classes_intersect_p[rclass]; | |
1350 | for (r = lra_reg_info[regno].live_ranges; r != NULL; r = r->next) | |
1351 | { | |
1352 | EXECUTE_IF_SET_IN_BITMAP (&live_hard_reg_pseudos[r->start], 0, k, bi) | |
1353 | if (rclass_intersect_p[regno_allocno_class_array[k]]) | |
1354 | sparseset_set_bit (live_range_hard_reg_pseudos, k); | |
1355 | for (p = r->start + 1; p <= r->finish; p++) | |
1356 | { | |
1357 | lra_live_range_t r2; | |
1358 | ||
1359 | for (r2 = start_point_ranges[p]; | |
1360 | r2 != NULL; | |
1361 | r2 = r2->start_next) | |
1362 | { | |
1363 | if (live_pseudos_reg_renumber[r2->regno] >= 0 | |
6027ea4c VM |
1364 | && ! sparseset_bit_p (live_range_hard_reg_pseudos, r2->regno) |
1365 | && rclass_intersect_p[regno_allocno_class_array[r2->regno]] | |
1366 | && ((int) r2->regno < lra_constraint_new_regno_start | |
1367 | || bitmap_bit_p (&lra_inheritance_pseudos, r2->regno) | |
1368 | || bitmap_bit_p (&lra_split_regs, r2->regno) | |
1369 | || bitmap_bit_p (&lra_optional_reload_pseudos, r2->regno) | |
1370 | /* There is no sense to consider another reload | |
1371 | pseudo if it has the same class. */ | |
1372 | || regno_allocno_class_array[r2->regno] != rclass)) | |
9e038952 VM |
1373 | sparseset_set_bit (live_range_hard_reg_pseudos, r2->regno); |
1374 | } | |
1375 | } | |
1376 | } | |
1377 | } | |
1378 | ||
6027ea4c VM |
1379 | /* Assign hard registers to reload pseudos and other pseudos. Return |
1380 | true if we was not able to assign hard registers to all reload | |
1381 | pseudos. */ | |
1382 | static bool | |
55a2c322 VM |
1383 | assign_by_spills (void) |
1384 | { | |
6027ea4c | 1385 | int i, n, nfails, iter, regno, regno2, hard_regno, cost; |
8a8330b7 | 1386 | rtx restore_rtx; |
55a2c322 | 1387 | bitmap_head changed_insns, do_not_assign_nonreload_pseudos; |
9e038952 | 1388 | unsigned int u, conflict_regno; |
55a2c322 | 1389 | bitmap_iterator bi; |
6027ea4c | 1390 | bool reload_p, fails_p = false; |
55a2c322 VM |
1391 | int max_regno = max_reg_num (); |
1392 | ||
1393 | for (n = 0, i = lra_constraint_new_regno_start; i < max_regno; i++) | |
1394 | if (reg_renumber[i] < 0 && lra_reg_info[i].nrefs != 0 | |
1395 | && regno_allocno_class_array[i] != NO_REGS) | |
1396 | sorted_pseudos[n++] = i; | |
1397 | bitmap_initialize (&insn_conflict_pseudos, ®_obstack); | |
1398 | bitmap_initialize (&spill_pseudos_bitmap, ®_obstack); | |
1399 | bitmap_initialize (&best_spill_pseudos_bitmap, ®_obstack); | |
1400 | update_hard_regno_preference_check = XCNEWVEC (int, max_regno); | |
1401 | curr_update_hard_regno_preference_check = 0; | |
1402 | memset (try_hard_reg_pseudos_check, 0, sizeof (try_hard_reg_pseudos_check)); | |
1403 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1404 | bitmap_initialize (&try_hard_reg_pseudos[i], ®_obstack); | |
1405 | curr_pseudo_check = 0; | |
1406 | bitmap_initialize (&changed_insns, ®_obstack); | |
1407 | bitmap_initialize (&non_reload_pseudos, ®_obstack); | |
1408 | bitmap_ior (&non_reload_pseudos, &lra_inheritance_pseudos, &lra_split_regs); | |
2b778c9d | 1409 | bitmap_ior_into (&non_reload_pseudos, &lra_subreg_reload_pseudos); |
55a2c322 VM |
1410 | bitmap_ior_into (&non_reload_pseudos, &lra_optional_reload_pseudos); |
1411 | for (iter = 0; iter <= 1; iter++) | |
1412 | { | |
1413 | qsort (sorted_pseudos, n, sizeof (int), reload_pseudo_compare_func); | |
1414 | nfails = 0; | |
1415 | for (i = 0; i < n; i++) | |
1416 | { | |
1417 | regno = sorted_pseudos[i]; | |
8a8330b7 VM |
1418 | if (reg_renumber[regno] >= 0) |
1419 | continue; | |
55a2c322 VM |
1420 | if (lra_dump_file != NULL) |
1421 | fprintf (lra_dump_file, " Assigning to %d " | |
1422 | "(cl=%s, orig=%d, freq=%d, tfirst=%d, tfreq=%d)...\n", | |
1423 | regno, reg_class_names[regno_allocno_class_array[regno]], | |
1424 | ORIGINAL_REGNO (regno_reg_rtx[regno]), | |
1425 | lra_reg_info[regno].freq, regno_assign_info[regno].first, | |
1426 | regno_assign_info[regno_assign_info[regno].first].freq); | |
9e038952 | 1427 | hard_regno = find_hard_regno_for (regno, &cost, -1, iter == 1); |
992ca0f0 VM |
1428 | reload_p = ! bitmap_bit_p (&non_reload_pseudos, regno); |
1429 | if (hard_regno < 0 && reload_p) | |
9e038952 | 1430 | hard_regno = spill_for (regno, &all_spilled_pseudos, iter == 1); |
55a2c322 VM |
1431 | if (hard_regno < 0) |
1432 | { | |
cebbaa2a VM |
1433 | if (reload_p) |
1434 | { | |
1435 | /* Put unassigned reload pseudo first in the array. */ | |
1436 | regno2 = sorted_pseudos[nfails]; | |
1437 | sorted_pseudos[nfails++] = regno; | |
1438 | sorted_pseudos[i] = regno2; | |
1439 | } | |
1440 | else | |
1441 | { | |
1442 | /* Consider all alternatives on the next constraint | |
1443 | subpass. */ | |
1444 | bitmap_set_bit (&all_spilled_pseudos, regno); | |
1445 | } | |
55a2c322 VM |
1446 | } |
1447 | else | |
1448 | { | |
1449 | /* This register might have been spilled by the previous | |
1450 | pass. Indicate that it is no longer spilled. */ | |
1451 | bitmap_clear_bit (&all_spilled_pseudos, regno); | |
1452 | assign_hard_regno (hard_regno, regno); | |
1f7e5a7b VM |
1453 | if (! reload_p || regno_allocno_class_array[regno] == ALL_REGS) |
1454 | /* As non-reload pseudo assignment is changed we should | |
1455 | reconsider insns referring for the pseudo. Do the same if a | |
1456 | reload pseudo did not refine its class which can happens | |
1457 | when the pseudo occurs only in reload insns. */ | |
992ca0f0 | 1458 | bitmap_set_bit (&changed_pseudo_bitmap, regno); |
55a2c322 VM |
1459 | } |
1460 | } | |
6027ea4c | 1461 | if (nfails == 0 || iter > 0) |
ce940020 | 1462 | { |
6027ea4c | 1463 | fails_p = nfails != 0; |
ce940020 VM |
1464 | break; |
1465 | } | |
67914693 | 1466 | /* This is a very rare event. We cannot assign a hard register |
9e038952 VM |
1467 | to reload pseudo because the hard register was assigned to |
1468 | another reload pseudo on a previous assignment pass. For x86 | |
1469 | example, on the 1st pass we assigned CX (although another | |
1470 | hard register could be used for this) to reload pseudo in an | |
1471 | insn, on the 2nd pass we need CX (and only this) hard | |
1472 | register for a new reload pseudo in the same insn. Another | |
1473 | possible situation may occur in assigning to multi-regs | |
1474 | reload pseudos when hard regs pool is too fragmented even | |
1475 | after spilling non-reload pseudos. | |
1476 | ||
1477 | We should do something radical here to succeed. Here we | |
1478 | spill *all* conflicting pseudos and reassign them. */ | |
55a2c322 VM |
1479 | if (lra_dump_file != NULL) |
1480 | fprintf (lra_dump_file, " 2nd iter for reload pseudo assignments:\n"); | |
9e038952 | 1481 | sparseset_clear (live_range_hard_reg_pseudos); |
55a2c322 VM |
1482 | for (i = 0; i < nfails; i++) |
1483 | { | |
1484 | if (lra_dump_file != NULL) | |
1485 | fprintf (lra_dump_file, " Reload r%d assignment failure\n", | |
1486 | sorted_pseudos[i]); | |
9e038952 VM |
1487 | find_all_spills_for (sorted_pseudos[i]); |
1488 | } | |
1489 | EXECUTE_IF_SET_IN_SPARSESET (live_range_hard_reg_pseudos, conflict_regno) | |
1490 | { | |
1491 | if ((int) conflict_regno >= lra_constraint_new_regno_start) | |
f54437d5 VM |
1492 | { |
1493 | sorted_pseudos[nfails++] = conflict_regno; | |
1494 | former_reload_pseudo_spill_p = true; | |
1495 | } | |
fdcfea63 VM |
1496 | else |
1497 | /* It is better to do reloads before spilling as after the | |
1498 | spill-subpass we will reload memory instead of pseudos | |
1499 | and this will make reusing reload pseudos more | |
1500 | complicated. Going directly to the spill pass in such | |
1501 | case might result in worse code performance or even LRA | |
1502 | cycling if we have few registers. */ | |
1503 | bitmap_set_bit (&all_spilled_pseudos, conflict_regno); | |
9e038952 VM |
1504 | if (lra_dump_file != NULL) |
1505 | fprintf (lra_dump_file, " Spill %s r%d(hr=%d, freq=%d)\n", | |
1506 | pseudo_prefix_title (conflict_regno), conflict_regno, | |
1507 | reg_renumber[conflict_regno], | |
1508 | lra_reg_info[conflict_regno].freq); | |
1509 | update_lives (conflict_regno, true); | |
1510 | lra_setup_reg_renumber (conflict_regno, -1, false); | |
55a2c322 | 1511 | } |
6027ea4c VM |
1512 | if (n < nfails) |
1513 | n = nfails; | |
55a2c322 VM |
1514 | } |
1515 | improve_inheritance (&changed_pseudo_bitmap); | |
1516 | bitmap_clear (&non_reload_pseudos); | |
1517 | bitmap_clear (&changed_insns); | |
1518 | if (! lra_simple_p) | |
1519 | { | |
1520 | /* We should not assign to original pseudos of inheritance | |
1521 | pseudos or split pseudos if any its inheritance pseudo did | |
1522 | not get hard register or any its split pseudo was not split | |
1523 | because undo inheritance/split pass will extend live range of | |
1524 | such inheritance or split pseudos. */ | |
1525 | bitmap_initialize (&do_not_assign_nonreload_pseudos, ®_obstack); | |
1526 | EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos, 0, u, bi) | |
8a8330b7 VM |
1527 | if ((restore_rtx = lra_reg_info[u].restore_rtx) != NULL_RTX |
1528 | && REG_P (restore_rtx) | |
55a2c322 VM |
1529 | && reg_renumber[u] < 0 |
1530 | && bitmap_bit_p (&lra_inheritance_pseudos, u)) | |
8a8330b7 | 1531 | bitmap_set_bit (&do_not_assign_nonreload_pseudos, REGNO (restore_rtx)); |
55a2c322 | 1532 | EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs, 0, u, bi) |
8a8330b7 | 1533 | if ((restore_rtx = lra_reg_info[u].restore_rtx) != NULL_RTX |
55a2c322 | 1534 | && reg_renumber[u] >= 0) |
8a8330b7 VM |
1535 | { |
1536 | lra_assert (REG_P (restore_rtx)); | |
1537 | bitmap_set_bit (&do_not_assign_nonreload_pseudos, REGNO (restore_rtx)); | |
1538 | } | |
55a2c322 VM |
1539 | for (n = 0, i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) |
1540 | if (((i < lra_constraint_new_regno_start | |
1541 | && ! bitmap_bit_p (&do_not_assign_nonreload_pseudos, i)) | |
1542 | || (bitmap_bit_p (&lra_inheritance_pseudos, i) | |
8a8330b7 | 1543 | && lra_reg_info[i].restore_rtx != NULL_RTX) |
55a2c322 | 1544 | || (bitmap_bit_p (&lra_split_regs, i) |
8a8330b7 | 1545 | && lra_reg_info[i].restore_rtx != NULL_RTX) |
2b778c9d | 1546 | || bitmap_bit_p (&lra_subreg_reload_pseudos, i) |
55a2c322 VM |
1547 | || bitmap_bit_p (&lra_optional_reload_pseudos, i)) |
1548 | && reg_renumber[i] < 0 && lra_reg_info[i].nrefs != 0 | |
1549 | && regno_allocno_class_array[i] != NO_REGS) | |
1550 | sorted_pseudos[n++] = i; | |
1551 | bitmap_clear (&do_not_assign_nonreload_pseudos); | |
1552 | if (n != 0 && lra_dump_file != NULL) | |
1553 | fprintf (lra_dump_file, " Reassigning non-reload pseudos\n"); | |
1554 | qsort (sorted_pseudos, n, sizeof (int), pseudo_compare_func); | |
1555 | for (i = 0; i < n; i++) | |
1556 | { | |
1557 | regno = sorted_pseudos[i]; | |
9e038952 | 1558 | hard_regno = find_hard_regno_for (regno, &cost, -1, false); |
55a2c322 VM |
1559 | if (hard_regno >= 0) |
1560 | { | |
1561 | assign_hard_regno (hard_regno, regno); | |
992ca0f0 VM |
1562 | /* We change allocation for non-reload pseudo on this |
1563 | iteration -- mark the pseudo for invalidation of used | |
1564 | alternatives of insns containing the pseudo. */ | |
55a2c322 VM |
1565 | bitmap_set_bit (&changed_pseudo_bitmap, regno); |
1566 | } | |
9afb455c VM |
1567 | else |
1568 | { | |
1569 | enum reg_class rclass = lra_get_allocno_class (regno); | |
1570 | enum reg_class spill_class; | |
1571 | ||
1df2287f | 1572 | if (targetm.spill_class == NULL |
8a8330b7 | 1573 | || lra_reg_info[regno].restore_rtx == NULL_RTX |
9afb455c VM |
1574 | || ! bitmap_bit_p (&lra_inheritance_pseudos, regno) |
1575 | || (spill_class | |
1576 | = ((enum reg_class) | |
1577 | targetm.spill_class | |
1578 | ((reg_class_t) rclass, | |
1579 | PSEUDO_REGNO_MODE (regno)))) == NO_REGS) | |
1580 | continue; | |
1581 | regno_allocno_class_array[regno] = spill_class; | |
1582 | hard_regno = find_hard_regno_for (regno, &cost, -1, false); | |
1583 | if (hard_regno < 0) | |
1584 | regno_allocno_class_array[regno] = rclass; | |
1585 | else | |
1586 | { | |
1587 | setup_reg_classes | |
1588 | (regno, spill_class, spill_class, spill_class); | |
1589 | assign_hard_regno (hard_regno, regno); | |
1590 | bitmap_set_bit (&changed_pseudo_bitmap, regno); | |
1591 | } | |
1592 | } | |
55a2c322 VM |
1593 | } |
1594 | } | |
1595 | free (update_hard_regno_preference_check); | |
1596 | bitmap_clear (&best_spill_pseudos_bitmap); | |
1597 | bitmap_clear (&spill_pseudos_bitmap); | |
1598 | bitmap_clear (&insn_conflict_pseudos); | |
6027ea4c | 1599 | return fails_p; |
55a2c322 VM |
1600 | } |
1601 | ||
55a2c322 VM |
1602 | /* Entry function to assign hard registers to new reload pseudos |
1603 | starting with LRA_CONSTRAINT_NEW_REGNO_START (by possible spilling | |
1604 | of old pseudos) and possibly to the old pseudos. The function adds | |
1605 | what insns to process for the next constraint pass. Those are all | |
1606 | insns who contains non-reload and non-inheritance pseudos with | |
1607 | changed allocation. | |
1608 | ||
1609 | Return true if we did not spill any non-reload and non-inheritance | |
6027ea4c VM |
1610 | pseudos. Set up FAILS_P if we failed to assign hard registers to |
1611 | all reload pseudos. */ | |
55a2c322 | 1612 | bool |
6027ea4c | 1613 | lra_assign (bool &fails_p) |
55a2c322 VM |
1614 | { |
1615 | int i; | |
1616 | unsigned int u; | |
1617 | bitmap_iterator bi; | |
1618 | bitmap_head insns_to_process; | |
1619 | bool no_spills_p; | |
1620 | int max_regno = max_reg_num (); | |
1621 | ||
1622 | timevar_push (TV_LRA_ASSIGN); | |
f54437d5 VM |
1623 | lra_assignment_iter++; |
1624 | if (lra_dump_file != NULL) | |
1625 | fprintf (lra_dump_file, "\n********** Assignment #%d: **********\n\n", | |
1626 | lra_assignment_iter); | |
55a2c322 VM |
1627 | init_lives (); |
1628 | sorted_pseudos = XNEWVEC (int, max_regno); | |
1629 | sorted_reload_pseudos = XNEWVEC (int, max_regno); | |
1630 | regno_allocno_class_array = XNEWVEC (enum reg_class, max_regno); | |
8a8330b7 | 1631 | regno_live_length = XNEWVEC (int, max_regno); |
55a2c322 | 1632 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) |
8a8330b7 VM |
1633 | { |
1634 | int l; | |
1635 | lra_live_range_t r; | |
1636 | ||
1637 | regno_allocno_class_array[i] = lra_get_allocno_class (i); | |
1638 | for (l = 0, r = lra_reg_info[i].live_ranges; r != NULL; r = r->next) | |
1639 | l += r->finish - r->start + 1; | |
1640 | regno_live_length[i] = l; | |
1641 | } | |
f54437d5 | 1642 | former_reload_pseudo_spill_p = false; |
55a2c322 VM |
1643 | init_regno_assign_info (); |
1644 | bitmap_initialize (&all_spilled_pseudos, ®_obstack); | |
1645 | create_live_range_start_chains (); | |
1646 | setup_live_pseudos_and_spill_after_risky_transforms (&all_spilled_pseudos); | |
15a47f43 VM |
1647 | if (! lra_hard_reg_split_p && ! lra_asm_error_p && flag_checking) |
1648 | /* Check correctness of allocation but only when there are no hard reg | |
1649 | splits and asm errors as in the case of errors explicit insns involving | |
1650 | hard regs are added or the asm is removed and this can result in | |
1651 | incorrect allocation. */ | |
10e1bdb2 | 1652 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) |
a1e6ee38 RS |
1653 | if (lra_reg_info[i].nrefs != 0 |
1654 | && reg_renumber[i] >= 0 | |
1655 | && overlaps_hard_reg_set_p (lra_reg_info[i].conflict_hard_regs, | |
10e1bdb2 TV |
1656 | PSEUDO_REGNO_MODE (i), reg_renumber[i])) |
1657 | gcc_unreachable (); | |
55a2c322 VM |
1658 | /* Setup insns to process on the next constraint pass. */ |
1659 | bitmap_initialize (&changed_pseudo_bitmap, ®_obstack); | |
1660 | init_live_reload_and_inheritance_pseudos (); | |
6027ea4c | 1661 | fails_p = assign_by_spills (); |
55a2c322 VM |
1662 | finish_live_reload_and_inheritance_pseudos (); |
1663 | bitmap_ior_into (&changed_pseudo_bitmap, &all_spilled_pseudos); | |
1664 | no_spills_p = true; | |
1665 | EXECUTE_IF_SET_IN_BITMAP (&all_spilled_pseudos, 0, u, bi) | |
1666 | /* We ignore spilled pseudos created on last inheritance pass | |
1667 | because they will be removed. */ | |
8a8330b7 | 1668 | if (lra_reg_info[u].restore_rtx == NULL_RTX) |
55a2c322 VM |
1669 | { |
1670 | no_spills_p = false; | |
1671 | break; | |
1672 | } | |
1673 | finish_live_range_start_chains (); | |
1674 | bitmap_clear (&all_spilled_pseudos); | |
1675 | bitmap_initialize (&insns_to_process, ®_obstack); | |
1676 | EXECUTE_IF_SET_IN_BITMAP (&changed_pseudo_bitmap, 0, u, bi) | |
1677 | bitmap_ior_into (&insns_to_process, &lra_reg_info[u].insn_bitmap); | |
1678 | bitmap_clear (&changed_pseudo_bitmap); | |
1679 | EXECUTE_IF_SET_IN_BITMAP (&insns_to_process, 0, u, bi) | |
1680 | { | |
1681 | lra_push_insn_by_uid (u); | |
1682 | /* Invalidate alternatives for insn should be processed. */ | |
1683 | lra_set_used_insn_alternative_by_uid (u, -1); | |
1684 | } | |
1685 | bitmap_clear (&insns_to_process); | |
1686 | finish_regno_assign_info (); | |
8a8330b7 | 1687 | free (regno_live_length); |
55a2c322 VM |
1688 | free (regno_allocno_class_array); |
1689 | free (sorted_pseudos); | |
1690 | free (sorted_reload_pseudos); | |
1691 | finish_lives (); | |
1692 | timevar_pop (TV_LRA_ASSIGN); | |
f54437d5 VM |
1693 | if (former_reload_pseudo_spill_p) |
1694 | lra_assignment_iter_after_spill++; | |
b6c38c69 BS |
1695 | /* This is conditional on flag_checking because valid code can take |
1696 | more than this maximum number of iteration, but at the same time | |
1697 | the test can uncover errors in machine descriptions. */ | |
1698 | if (flag_checking | |
1699 | && (lra_assignment_iter_after_spill | |
1700 | > LRA_MAX_ASSIGNMENT_ITERATION_NUMBER)) | |
f54437d5 | 1701 | internal_error |
a9c697b8 | 1702 | ("maximum number of LRA assignment passes is achieved (%d)", |
f54437d5 | 1703 | LRA_MAX_ASSIGNMENT_ITERATION_NUMBER); |
7436a1c6 VM |
1704 | /* Reset the assignment correctness flag: */ |
1705 | check_and_force_assignment_correctness_p = false; | |
55a2c322 VM |
1706 | return no_spills_p; |
1707 | } | |
8a8330b7 | 1708 | |
6027ea4c VM |
1709 | /* Find start and finish insns for reload pseudo REGNO. Return true |
1710 | if we managed to find the expected insns. Return false, | |
1711 | otherwise. */ | |
1712 | static bool | |
1713 | find_reload_regno_insns (int regno, rtx_insn * &start, rtx_insn * &finish) | |
1714 | { | |
1715 | unsigned int uid; | |
1716 | bitmap_iterator bi; | |
0c016888 VM |
1717 | int insns_num = 0; |
1718 | bool clobber_p = false; | |
6027ea4c VM |
1719 | rtx_insn *prev_insn, *next_insn; |
1720 | rtx_insn *start_insn = NULL, *first_insn = NULL, *second_insn = NULL; | |
1721 | ||
1722 | EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi) | |
1723 | { | |
1724 | if (start_insn == NULL) | |
1725 | start_insn = lra_insn_recog_data[uid]->insn; | |
0c016888 VM |
1726 | if (GET_CODE (PATTERN (lra_insn_recog_data[uid]->insn)) == CLOBBER) |
1727 | clobber_p = true; | |
1728 | else | |
1729 | insns_num++; | |
6027ea4c | 1730 | } |
0c016888 | 1731 | /* For reload pseudo we should have at most 3 insns besides clobber referring for |
e3b3b596 | 1732 | it: input/output reload insns and the original insn. */ |
0c016888 | 1733 | if (insns_num > 3) |
6027ea4c | 1734 | return false; |
0c016888 VM |
1735 | if (clobber_p) |
1736 | insns_num++; | |
1737 | if (insns_num > 1) | |
6027ea4c VM |
1738 | { |
1739 | for (prev_insn = PREV_INSN (start_insn), | |
1740 | next_insn = NEXT_INSN (start_insn); | |
22b0476a VM |
1741 | insns_num != 1 && (prev_insn != NULL |
1742 | || (next_insn != NULL && second_insn == NULL)); ) | |
6027ea4c | 1743 | { |
0c016888 | 1744 | if (prev_insn != NULL) |
6027ea4c | 1745 | { |
0c016888 VM |
1746 | if (bitmap_bit_p (&lra_reg_info[regno].insn_bitmap, |
1747 | INSN_UID (prev_insn))) | |
6027ea4c VM |
1748 | { |
1749 | first_insn = prev_insn; | |
0c016888 | 1750 | insns_num--; |
6027ea4c | 1751 | } |
0c016888 | 1752 | prev_insn = PREV_INSN (prev_insn); |
6027ea4c VM |
1753 | } |
1754 | if (next_insn != NULL && second_insn == NULL) | |
1755 | { | |
1756 | if (! bitmap_bit_p (&lra_reg_info[regno].insn_bitmap, | |
1757 | INSN_UID (next_insn))) | |
1758 | next_insn = NEXT_INSN (next_insn); | |
1759 | else | |
1760 | { | |
1761 | second_insn = next_insn; | |
0c016888 | 1762 | insns_num--; |
6027ea4c VM |
1763 | } |
1764 | } | |
1765 | } | |
0c016888 | 1766 | if (insns_num > 1) |
6027ea4c VM |
1767 | return false; |
1768 | } | |
1769 | start = first_insn != NULL ? first_insn : start_insn; | |
1770 | finish = second_insn != NULL ? second_insn : start_insn; | |
1771 | return true; | |
1772 | } | |
1773 | ||
1774 | /* Process reload pseudos which did not get a hard reg, split a hard | |
1775 | reg live range in live range of a reload pseudo, and then return | |
1776 | TRUE. If we did not split a hard reg live range, report an error, | |
1777 | and return FALSE. */ | |
1778 | bool | |
1779 | lra_split_hard_reg_for (void) | |
1780 | { | |
7293e3f5 | 1781 | int i, regno; |
6027ea4c VM |
1782 | rtx_insn *insn, *first, *last; |
1783 | unsigned int u; | |
1784 | bitmap_iterator bi; | |
7293e3f5 | 1785 | enum reg_class rclass; |
6027ea4c VM |
1786 | int max_regno = max_reg_num (); |
1787 | /* We did not assign hard regs to reload pseudos after two | |
1788 | iterations. Either it's an asm and something is wrong with the | |
1789 | constraints, or we have run out of spill registers; error out in | |
1790 | either case. */ | |
ec1b9ba2 VM |
1791 | bool asm_p = false, spill_p = false; |
1792 | bitmap_head failed_reload_insns, failed_reload_pseudos, over_split_insns; | |
6027ea4c VM |
1793 | |
1794 | if (lra_dump_file != NULL) | |
1795 | fprintf (lra_dump_file, | |
1796 | "\n****** Splitting a hard reg after assignment #%d: ******\n\n", | |
1797 | lra_assignment_iter); | |
7293e3f5 | 1798 | bitmap_initialize (&failed_reload_pseudos, ®_obstack); |
003cd04c VM |
1799 | bitmap_initialize (&non_reload_pseudos, ®_obstack); |
1800 | bitmap_ior (&non_reload_pseudos, &lra_inheritance_pseudos, &lra_split_regs); | |
1801 | bitmap_ior_into (&non_reload_pseudos, &lra_subreg_reload_pseudos); | |
1802 | bitmap_ior_into (&non_reload_pseudos, &lra_optional_reload_pseudos); | |
ec1b9ba2 | 1803 | bitmap_initialize (&over_split_insns, ®_obstack); |
7293e3f5 | 1804 | for (i = lra_constraint_new_regno_start; i < max_regno; i++) |
6027ea4c | 1805 | if (reg_renumber[i] < 0 && lra_reg_info[i].nrefs != 0 |
7293e3f5 | 1806 | && (rclass = lra_get_allocno_class (i)) != NO_REGS |
6027ea4c VM |
1807 | && ! bitmap_bit_p (&non_reload_pseudos, i)) |
1808 | { | |
6027ea4c VM |
1809 | if (! find_reload_regno_insns (i, first, last)) |
1810 | continue; | |
ec1b9ba2 | 1811 | if (BLOCK_FOR_INSN (first) == BLOCK_FOR_INSN (last)) |
7293e3f5 | 1812 | { |
ec1b9ba2 VM |
1813 | /* Check that we are not trying to split over the same insn |
1814 | requiring reloads to avoid splitting the same hard reg twice or | |
1815 | more. If we need several hard regs splitting over the same insn | |
1816 | it can be finished on the next iterations. | |
1817 | ||
1818 | The following loop iteration number is small as we split hard | |
1819 | reg in a very small range. */ | |
1820 | for (insn = first; | |
1821 | insn != NEXT_INSN (last); | |
1822 | insn = NEXT_INSN (insn)) | |
1823 | if (bitmap_bit_p (&over_split_insns, INSN_UID (insn))) | |
1824 | break; | |
1825 | if (insn != NEXT_INSN (last) | |
1826 | || !spill_hard_reg_in_range (i, rclass, first, last)) | |
1827 | { | |
1828 | bitmap_set_bit (&failed_reload_pseudos, i); | |
1829 | } | |
1830 | else | |
1831 | { | |
1832 | for (insn = first; | |
1833 | insn != NEXT_INSN (last); | |
1834 | insn = NEXT_INSN (insn)) | |
1835 | bitmap_set_bit (&over_split_insns, INSN_UID (insn)); | |
1836 | spill_p = true; | |
1837 | } | |
7293e3f5 | 1838 | } |
6027ea4c | 1839 | } |
ec1b9ba2 VM |
1840 | bitmap_clear (&over_split_insns); |
1841 | if (spill_p) | |
1842 | { | |
1843 | bitmap_clear (&failed_reload_pseudos); | |
1390bf52 | 1844 | lra_dump_insns_if_possible ("changed func after splitting hard regs"); |
ec1b9ba2 VM |
1845 | return true; |
1846 | } | |
003cd04c | 1847 | bitmap_clear (&non_reload_pseudos); |
6027ea4c | 1848 | bitmap_initialize (&failed_reload_insns, ®_obstack); |
7293e3f5 | 1849 | EXECUTE_IF_SET_IN_BITMAP (&failed_reload_pseudos, 0, u, bi) |
6027ea4c | 1850 | { |
7293e3f5 | 1851 | regno = u; |
6027ea4c VM |
1852 | bitmap_ior_into (&failed_reload_insns, |
1853 | &lra_reg_info[regno].insn_bitmap); | |
7293e3f5 VM |
1854 | lra_setup_reg_renumber |
1855 | (regno, ira_class_hard_regs[lra_get_allocno_class (regno)][0], false); | |
6027ea4c VM |
1856 | } |
1857 | EXECUTE_IF_SET_IN_BITMAP (&failed_reload_insns, 0, u, bi) | |
1858 | { | |
1859 | insn = lra_insn_recog_data[u]->insn; | |
1860 | if (asm_noperands (PATTERN (insn)) >= 0) | |
1861 | { | |
b175b488 VM |
1862 | asm_p = true; |
1863 | lra_asm_insn_error (insn); | |
6027ea4c VM |
1864 | } |
1865 | else if (!asm_p) | |
1866 | { | |
1867 | error ("unable to find a register to spill"); | |
1868 | fatal_insn ("this is the insn:", insn); | |
1869 | } | |
1870 | } | |
7293e3f5 VM |
1871 | bitmap_clear (&failed_reload_pseudos); |
1872 | bitmap_clear (&failed_reload_insns); | |
6027ea4c VM |
1873 | return false; |
1874 | } |