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c6a6cdaa | 1 | /* Code for RTL transformations to satisfy insn constraints. |
fbd26352 | 2 | Copyright (C) 2010-2019 Free Software Foundation, Inc. |
c6a6cdaa | 3 | Contributed by Vladimir Makarov <vmakarov@redhat.com>. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it under | |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 3, or (at your option) any later | |
10 | version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | ||
22 | /* This file contains code for 3 passes: constraint pass, | |
23 | inheritance/split pass, and pass for undoing failed inheritance and | |
24 | split. | |
25 | ||
26 | The major goal of constraint pass is to transform RTL to satisfy | |
27 | insn and address constraints by: | |
28 | o choosing insn alternatives; | |
29 | o generating *reload insns* (or reloads in brief) and *reload | |
30 | pseudos* which will get necessary hard registers later; | |
31 | o substituting pseudos with equivalent values and removing the | |
32 | instructions that initialized those pseudos. | |
33 | ||
34 | The constraint pass has biggest and most complicated code in LRA. | |
35 | There are a lot of important details like: | |
36 | o reuse of input reload pseudos to simplify reload pseudo | |
37 | allocations; | |
38 | o some heuristics to choose insn alternative to improve the | |
39 | inheritance; | |
40 | o early clobbers etc. | |
41 | ||
42 | The pass is mimicking former reload pass in alternative choosing | |
43 | because the reload pass is oriented to current machine description | |
44 | model. It might be changed if the machine description model is | |
45 | changed. | |
46 | ||
47 | There is special code for preventing all LRA and this pass cycling | |
48 | in case of bugs. | |
49 | ||
50 | On the first iteration of the pass we process every instruction and | |
51 | choose an alternative for each one. On subsequent iterations we try | |
52 | to avoid reprocessing instructions if we can be sure that the old | |
53 | choice is still valid. | |
54 | ||
55 | The inheritance/spilt pass is to transform code to achieve | |
56 | ineheritance and live range splitting. It is done on backward | |
57 | traversal of EBBs. | |
58 | ||
59 | The inheritance optimization goal is to reuse values in hard | |
60 | registers. There is analogous optimization in old reload pass. The | |
61 | inheritance is achieved by following transformation: | |
62 | ||
63 | reload_p1 <- p reload_p1 <- p | |
64 | ... new_p <- reload_p1 | |
65 | ... => ... | |
66 | reload_p2 <- p reload_p2 <- new_p | |
67 | ||
68 | where p is spilled and not changed between the insns. Reload_p1 is | |
69 | also called *original pseudo* and new_p is called *inheritance | |
70 | pseudo*. | |
71 | ||
72 | The subsequent assignment pass will try to assign the same (or | |
73 | another if it is not possible) hard register to new_p as to | |
74 | reload_p1 or reload_p2. | |
75 | ||
76 | If the assignment pass fails to assign a hard register to new_p, | |
77 | this file will undo the inheritance and restore the original code. | |
78 | This is because implementing the above sequence with a spilled | |
79 | new_p would make the code much worse. The inheritance is done in | |
80 | EBB scope. The above is just a simplified example to get an idea | |
81 | of the inheritance as the inheritance is also done for non-reload | |
82 | insns. | |
83 | ||
84 | Splitting (transformation) is also done in EBB scope on the same | |
85 | pass as the inheritance: | |
86 | ||
87 | r <- ... or ... <- r r <- ... or ... <- r | |
88 | ... s <- r (new insn -- save) | |
1a8f8886 | 89 | ... => |
c6a6cdaa | 90 | ... r <- s (new insn -- restore) |
91 | ... <- r ... <- r | |
92 | ||
93 | The *split pseudo* s is assigned to the hard register of the | |
94 | original pseudo or hard register r. | |
95 | ||
96 | Splitting is done: | |
97 | o In EBBs with high register pressure for global pseudos (living | |
98 | in at least 2 BBs) and assigned to hard registers when there | |
99 | are more one reloads needing the hard registers; | |
100 | o for pseudos needing save/restore code around calls. | |
101 | ||
102 | If the split pseudo still has the same hard register as the | |
103 | original pseudo after the subsequent assignment pass or the | |
104 | original pseudo was split, the opposite transformation is done on | |
105 | the same pass for undoing inheritance. */ | |
106 | ||
107 | #undef REG_OK_STRICT | |
108 | ||
109 | #include "config.h" | |
110 | #include "system.h" | |
111 | #include "coretypes.h" | |
9ef16211 | 112 | #include "backend.h" |
7c29e30e | 113 | #include "target.h" |
c6a6cdaa | 114 | #include "rtl.h" |
7c29e30e | 115 | #include "tree.h" |
116 | #include "predict.h" | |
9ef16211 | 117 | #include "df.h" |
ad7b10a2 | 118 | #include "memmodel.h" |
c6a6cdaa | 119 | #include "tm_p.h" |
7c29e30e | 120 | #include "expmed.h" |
121 | #include "optabs.h" | |
c6a6cdaa | 122 | #include "regs.h" |
7c29e30e | 123 | #include "ira.h" |
c6a6cdaa | 124 | #include "recog.h" |
125 | #include "output.h" | |
126 | #include "addresses.h" | |
c6a6cdaa | 127 | #include "expr.h" |
94ea8568 | 128 | #include "cfgrtl.h" |
c6a6cdaa | 129 | #include "rtl-error.h" |
4b69081d | 130 | #include "params.h" |
9ef16211 | 131 | #include "lra.h" |
c6a6cdaa | 132 | #include "lra-int.h" |
397881d3 | 133 | #include "print-rtl.h" |
f97d6f47 | 134 | #include "function-abi.h" |
c6a6cdaa | 135 | |
136 | /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current | |
137 | insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted | |
138 | reload insns. */ | |
139 | static int bb_reload_num; | |
140 | ||
ea99c7a1 | 141 | /* The current insn being processed and corresponding its single set |
142 | (NULL otherwise), its data (basic block, the insn data, the insn | |
143 | static data, and the mode of each operand). */ | |
7f836b57 | 144 | static rtx_insn *curr_insn; |
ea99c7a1 | 145 | static rtx curr_insn_set; |
c6a6cdaa | 146 | static basic_block curr_bb; |
147 | static lra_insn_recog_data_t curr_id; | |
148 | static struct lra_static_insn_data *curr_static_id; | |
3754d046 | 149 | static machine_mode curr_operand_mode[MAX_RECOG_OPERANDS]; |
1aae95ec | 150 | /* Mode of the register substituted by its equivalence with VOIDmode |
151 | (e.g. constant) and whose subreg is given operand of the current | |
152 | insn. VOIDmode in all other cases. */ | |
153 | static machine_mode original_subreg_reg_mode[MAX_RECOG_OPERANDS]; | |
c6a6cdaa | 154 | |
155 | \f | |
156 | ||
157 | /* Start numbers for new registers and insns at the current constraints | |
158 | pass start. */ | |
159 | static int new_regno_start; | |
160 | static int new_insn_uid_start; | |
161 | ||
1efe9e9d | 162 | /* If LOC is nonnull, strip any outer subreg from it. */ |
163 | static inline rtx * | |
164 | strip_subreg (rtx *loc) | |
165 | { | |
166 | return loc && GET_CODE (*loc) == SUBREG ? &SUBREG_REG (*loc) : loc; | |
167 | } | |
168 | ||
c6a6cdaa | 169 | /* Return hard regno of REGNO or if it is was not assigned to a hard |
170 | register, use a hard register from its allocno class. */ | |
171 | static int | |
172 | get_try_hard_regno (int regno) | |
173 | { | |
174 | int hard_regno; | |
175 | enum reg_class rclass; | |
176 | ||
177 | if ((hard_regno = regno) >= FIRST_PSEUDO_REGISTER) | |
178 | hard_regno = lra_get_regno_hard_regno (regno); | |
179 | if (hard_regno >= 0) | |
180 | return hard_regno; | |
181 | rclass = lra_get_allocno_class (regno); | |
182 | if (rclass == NO_REGS) | |
183 | return -1; | |
184 | return ira_class_hard_regs[rclass][0]; | |
185 | } | |
186 | ||
9731eaaf | 187 | /* Return the hard regno of X after removing its subreg. If X is not |
188 | a register or a subreg of a register, return -1. If X is a pseudo, | |
331a9ecc | 189 | use its assignment. If FINAL_P return the final hard regno which will |
190 | be after elimination. */ | |
c6a6cdaa | 191 | static int |
331a9ecc | 192 | get_hard_regno (rtx x, bool final_p) |
c6a6cdaa | 193 | { |
194 | rtx reg; | |
331a9ecc | 195 | int hard_regno; |
c6a6cdaa | 196 | |
197 | reg = x; | |
9731eaaf | 198 | if (SUBREG_P (x)) |
c6a6cdaa | 199 | reg = SUBREG_REG (x); |
200 | if (! REG_P (reg)) | |
201 | return -1; | |
9731eaaf | 202 | if (! HARD_REGISTER_NUM_P (hard_regno = REGNO (reg))) |
c6a6cdaa | 203 | hard_regno = lra_get_regno_hard_regno (hard_regno); |
204 | if (hard_regno < 0) | |
205 | return -1; | |
331a9ecc | 206 | if (final_p) |
207 | hard_regno = lra_get_elimination_hard_regno (hard_regno); | |
9731eaaf | 208 | if (SUBREG_P (x)) |
331a9ecc | 209 | hard_regno += subreg_regno_offset (hard_regno, GET_MODE (reg), |
210 | SUBREG_BYTE (x), GET_MODE (x)); | |
211 | return hard_regno; | |
c6a6cdaa | 212 | } |
213 | ||
214 | /* If REGNO is a hard register or has been allocated a hard register, | |
215 | return the class of that register. If REGNO is a reload pseudo | |
216 | created by the current constraints pass, return its allocno class. | |
217 | Return NO_REGS otherwise. */ | |
218 | static enum reg_class | |
219 | get_reg_class (int regno) | |
220 | { | |
221 | int hard_regno; | |
222 | ||
331a9ecc | 223 | if (! HARD_REGISTER_NUM_P (hard_regno = regno)) |
c6a6cdaa | 224 | hard_regno = lra_get_regno_hard_regno (regno); |
225 | if (hard_regno >= 0) | |
226 | { | |
331a9ecc | 227 | hard_regno = lra_get_elimination_hard_regno (hard_regno); |
c6a6cdaa | 228 | return REGNO_REG_CLASS (hard_regno); |
229 | } | |
230 | if (regno >= new_regno_start) | |
231 | return lra_get_allocno_class (regno); | |
232 | return NO_REGS; | |
233 | } | |
234 | ||
235 | /* Return true if REG satisfies (or will satisfy) reg class constraint | |
236 | CL. Use elimination first if REG is a hard register. If REG is a | |
237 | reload pseudo created by this constraints pass, assume that it will | |
238 | be allocated a hard register from its allocno class, but allow that | |
239 | class to be narrowed to CL if it is currently a superset of CL. | |
240 | ||
241 | If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of | |
242 | REGNO (reg), or NO_REGS if no change in its class was needed. */ | |
243 | static bool | |
244 | in_class_p (rtx reg, enum reg_class cl, enum reg_class *new_class) | |
245 | { | |
246 | enum reg_class rclass, common_class; | |
3754d046 | 247 | machine_mode reg_mode; |
c6a6cdaa | 248 | int class_size, hard_regno, nregs, i, j; |
249 | int regno = REGNO (reg); | |
1a8f8886 | 250 | |
c6a6cdaa | 251 | if (new_class != NULL) |
252 | *new_class = NO_REGS; | |
253 | if (regno < FIRST_PSEUDO_REGISTER) | |
254 | { | |
255 | rtx final_reg = reg; | |
256 | rtx *final_loc = &final_reg; | |
1a8f8886 | 257 | |
c6a6cdaa | 258 | lra_eliminate_reg_if_possible (final_loc); |
259 | return TEST_HARD_REG_BIT (reg_class_contents[cl], REGNO (*final_loc)); | |
260 | } | |
261 | reg_mode = GET_MODE (reg); | |
262 | rclass = get_reg_class (regno); | |
263 | if (regno < new_regno_start | |
264 | /* Do not allow the constraints for reload instructions to | |
265 | influence the classes of new pseudos. These reloads are | |
266 | typically moves that have many alternatives, and restricting | |
267 | reload pseudos for one alternative may lead to situations | |
268 | where other reload pseudos are no longer allocatable. */ | |
7619e612 | 269 | || (INSN_UID (curr_insn) >= new_insn_uid_start |
270 | && curr_insn_set != NULL | |
58f94f4a | 271 | && ((OBJECT_P (SET_SRC (curr_insn_set)) |
272 | && ! CONSTANT_P (SET_SRC (curr_insn_set))) | |
7619e612 | 273 | || (GET_CODE (SET_SRC (curr_insn_set)) == SUBREG |
58f94f4a | 274 | && OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set))) |
275 | && ! CONSTANT_P (SUBREG_REG (SET_SRC (curr_insn_set))))))) | |
c6a6cdaa | 276 | /* When we don't know what class will be used finally for reload |
277 | pseudos, we use ALL_REGS. */ | |
278 | return ((regno >= new_regno_start && rclass == ALL_REGS) | |
279 | || (rclass != NO_REGS && ira_class_subset_p[rclass][cl] | |
280 | && ! hard_reg_set_subset_p (reg_class_contents[cl], | |
281 | lra_no_alloc_regs))); | |
282 | else | |
283 | { | |
284 | common_class = ira_reg_class_subset[rclass][cl]; | |
285 | if (new_class != NULL) | |
286 | *new_class = common_class; | |
287 | if (hard_reg_set_subset_p (reg_class_contents[common_class], | |
288 | lra_no_alloc_regs)) | |
289 | return false; | |
290 | /* Check that there are enough allocatable regs. */ | |
291 | class_size = ira_class_hard_regs_num[common_class]; | |
292 | for (i = 0; i < class_size; i++) | |
293 | { | |
294 | hard_regno = ira_class_hard_regs[common_class][i]; | |
92d2aec3 | 295 | nregs = hard_regno_nregs (hard_regno, reg_mode); |
c6a6cdaa | 296 | if (nregs == 1) |
297 | return true; | |
298 | for (j = 0; j < nregs; j++) | |
68132dc4 | 299 | if (TEST_HARD_REG_BIT (lra_no_alloc_regs, hard_regno + j) |
300 | || ! TEST_HARD_REG_BIT (reg_class_contents[common_class], | |
301 | hard_regno + j)) | |
c6a6cdaa | 302 | break; |
303 | if (j >= nregs) | |
304 | return true; | |
305 | } | |
306 | return false; | |
307 | } | |
308 | } | |
309 | ||
310 | /* Return true if REGNO satisfies a memory constraint. */ | |
311 | static bool | |
312 | in_mem_p (int regno) | |
313 | { | |
314 | return get_reg_class (regno) == NO_REGS; | |
315 | } | |
316 | ||
67e22af9 | 317 | /* Return 1 if ADDR is a valid memory address for mode MODE in address |
318 | space AS, and check that each pseudo has the proper kind of hard | |
319 | reg. */ | |
320 | static int | |
3754d046 | 321 | valid_address_p (machine_mode mode ATTRIBUTE_UNUSED, |
67e22af9 | 322 | rtx addr, addr_space_t as) |
323 | { | |
324 | #ifdef GO_IF_LEGITIMATE_ADDRESS | |
325 | lra_assert (ADDR_SPACE_GENERIC_P (as)); | |
326 | GO_IF_LEGITIMATE_ADDRESS (mode, addr, win); | |
327 | return 0; | |
328 | ||
329 | win: | |
330 | return 1; | |
331 | #else | |
332 | return targetm.addr_space.legitimate_address_p (mode, addr, 0, as); | |
333 | #endif | |
334 | } | |
335 | ||
336 | namespace { | |
337 | /* Temporarily eliminates registers in an address (for the lifetime of | |
338 | the object). */ | |
339 | class address_eliminator { | |
340 | public: | |
341 | address_eliminator (struct address_info *ad); | |
342 | ~address_eliminator (); | |
343 | ||
344 | private: | |
345 | struct address_info *m_ad; | |
346 | rtx *m_base_loc; | |
347 | rtx m_base_reg; | |
348 | rtx *m_index_loc; | |
349 | rtx m_index_reg; | |
350 | }; | |
351 | } | |
352 | ||
353 | address_eliminator::address_eliminator (struct address_info *ad) | |
354 | : m_ad (ad), | |
355 | m_base_loc (strip_subreg (ad->base_term)), | |
356 | m_base_reg (NULL_RTX), | |
357 | m_index_loc (strip_subreg (ad->index_term)), | |
358 | m_index_reg (NULL_RTX) | |
359 | { | |
360 | if (m_base_loc != NULL) | |
361 | { | |
362 | m_base_reg = *m_base_loc; | |
6dc6c0a7 | 363 | /* If we have non-legitimate address which is decomposed not in |
364 | the way we expected, don't do elimination here. In such case | |
365 | the address will be reloaded and elimination will be done in | |
366 | reload insn finally. */ | |
367 | if (REG_P (m_base_reg)) | |
368 | lra_eliminate_reg_if_possible (m_base_loc); | |
67e22af9 | 369 | if (m_ad->base_term2 != NULL) |
370 | *m_ad->base_term2 = *m_ad->base_term; | |
371 | } | |
372 | if (m_index_loc != NULL) | |
373 | { | |
374 | m_index_reg = *m_index_loc; | |
6dc6c0a7 | 375 | if (REG_P (m_index_reg)) |
376 | lra_eliminate_reg_if_possible (m_index_loc); | |
67e22af9 | 377 | } |
378 | } | |
379 | ||
380 | address_eliminator::~address_eliminator () | |
381 | { | |
382 | if (m_base_loc && *m_base_loc != m_base_reg) | |
383 | { | |
384 | *m_base_loc = m_base_reg; | |
385 | if (m_ad->base_term2 != NULL) | |
386 | *m_ad->base_term2 = *m_ad->base_term; | |
387 | } | |
388 | if (m_index_loc && *m_index_loc != m_index_reg) | |
389 | *m_index_loc = m_index_reg; | |
390 | } | |
391 | ||
392 | /* Return true if the eliminated form of AD is a legitimate target address. */ | |
393 | static bool | |
394 | valid_address_p (struct address_info *ad) | |
395 | { | |
396 | address_eliminator eliminator (ad); | |
397 | return valid_address_p (ad->mode, *ad->outer, ad->as); | |
398 | } | |
399 | ||
67e22af9 | 400 | /* Return true if the eliminated form of memory reference OP satisfies |
6b3b345a | 401 | extra (special) memory constraint CONSTRAINT. */ |
67e22af9 | 402 | static bool |
79bc09fb | 403 | satisfies_memory_constraint_p (rtx op, enum constraint_num constraint) |
67e22af9 | 404 | { |
405 | struct address_info ad; | |
406 | ||
407 | decompose_mem_address (&ad, op); | |
408 | address_eliminator eliminator (&ad); | |
79bc09fb | 409 | return constraint_satisfied_p (op, constraint); |
67e22af9 | 410 | } |
411 | ||
412 | /* Return true if the eliminated form of address AD satisfies extra | |
413 | address constraint CONSTRAINT. */ | |
414 | static bool | |
415 | satisfies_address_constraint_p (struct address_info *ad, | |
79bc09fb | 416 | enum constraint_num constraint) |
67e22af9 | 417 | { |
418 | address_eliminator eliminator (ad); | |
79bc09fb | 419 | return constraint_satisfied_p (*ad->outer, constraint); |
67e22af9 | 420 | } |
421 | ||
422 | /* Return true if the eliminated form of address OP satisfies extra | |
423 | address constraint CONSTRAINT. */ | |
424 | static bool | |
79bc09fb | 425 | satisfies_address_constraint_p (rtx op, enum constraint_num constraint) |
67e22af9 | 426 | { |
427 | struct address_info ad; | |
428 | ||
429 | decompose_lea_address (&ad, &op); | |
430 | return satisfies_address_constraint_p (&ad, constraint); | |
431 | } | |
67e22af9 | 432 | |
61cd3e57 | 433 | /* Initiate equivalences for LRA. As we keep original equivalences |
434 | before any elimination, we need to make copies otherwise any change | |
435 | in insns might change the equivalences. */ | |
436 | void | |
437 | lra_init_equiv (void) | |
438 | { | |
439 | ira_expand_reg_equiv (); | |
440 | for (int i = FIRST_PSEUDO_REGISTER; i < max_reg_num (); i++) | |
441 | { | |
442 | rtx res; | |
443 | ||
444 | if ((res = ira_reg_equiv[i].memory) != NULL_RTX) | |
445 | ira_reg_equiv[i].memory = copy_rtx (res); | |
446 | if ((res = ira_reg_equiv[i].invariant) != NULL_RTX) | |
447 | ira_reg_equiv[i].invariant = copy_rtx (res); | |
448 | } | |
449 | } | |
450 | ||
451 | static rtx loc_equivalence_callback (rtx, const_rtx, void *); | |
452 | ||
453 | /* Update equivalence for REGNO. We need to this as the equivalence | |
454 | might contain other pseudos which are changed by their | |
455 | equivalences. */ | |
456 | static void | |
457 | update_equiv (int regno) | |
458 | { | |
459 | rtx x; | |
460 | ||
461 | if ((x = ira_reg_equiv[regno].memory) != NULL_RTX) | |
462 | ira_reg_equiv[regno].memory | |
463 | = simplify_replace_fn_rtx (x, NULL_RTX, loc_equivalence_callback, | |
464 | NULL_RTX); | |
465 | if ((x = ira_reg_equiv[regno].invariant) != NULL_RTX) | |
466 | ira_reg_equiv[regno].invariant | |
467 | = simplify_replace_fn_rtx (x, NULL_RTX, loc_equivalence_callback, | |
468 | NULL_RTX); | |
469 | } | |
470 | ||
c6a6cdaa | 471 | /* If we have decided to substitute X with another value, return that |
472 | value, otherwise return X. */ | |
473 | static rtx | |
3b3a5e5f | 474 | get_equiv (rtx x) |
c6a6cdaa | 475 | { |
476 | int regno; | |
477 | rtx res; | |
478 | ||
479 | if (! REG_P (x) || (regno = REGNO (x)) < FIRST_PSEUDO_REGISTER | |
480 | || ! ira_reg_equiv[regno].defined_p | |
481 | || ! ira_reg_equiv[regno].profitable_p | |
482 | || lra_get_regno_hard_regno (regno) >= 0) | |
483 | return x; | |
484 | if ((res = ira_reg_equiv[regno].memory) != NULL_RTX) | |
f4447329 | 485 | { |
486 | if (targetm.cannot_substitute_mem_equiv_p (res)) | |
487 | return x; | |
488 | return res; | |
489 | } | |
c6a6cdaa | 490 | if ((res = ira_reg_equiv[regno].constant) != NULL_RTX) |
491 | return res; | |
492 | if ((res = ira_reg_equiv[regno].invariant) != NULL_RTX) | |
493 | return res; | |
494 | gcc_unreachable (); | |
495 | } | |
496 | ||
3b3a5e5f | 497 | /* If we have decided to substitute X with the equivalent value, |
498 | return that value after elimination for INSN, otherwise return | |
499 | X. */ | |
500 | static rtx | |
7f836b57 | 501 | get_equiv_with_elimination (rtx x, rtx_insn *insn) |
3b3a5e5f | 502 | { |
503 | rtx res = get_equiv (x); | |
504 | ||
505 | if (x == res || CONSTANT_P (res)) | |
506 | return res; | |
497ba60f | 507 | return lra_eliminate_regs_1 (insn, res, GET_MODE (res), |
99535fab | 508 | false, false, 0, true); |
3b3a5e5f | 509 | } |
510 | ||
c6a6cdaa | 511 | /* Set up curr_operand_mode. */ |
512 | static void | |
513 | init_curr_operand_mode (void) | |
514 | { | |
515 | int nop = curr_static_id->n_operands; | |
516 | for (int i = 0; i < nop; i++) | |
517 | { | |
3754d046 | 518 | machine_mode mode = GET_MODE (*curr_id->operand_loc[i]); |
c6a6cdaa | 519 | if (mode == VOIDmode) |
520 | { | |
521 | /* The .md mode for address operands is the mode of the | |
522 | addressed value rather than the mode of the address itself. */ | |
523 | if (curr_id->icode >= 0 && curr_static_id->operand[i].is_address) | |
524 | mode = Pmode; | |
525 | else | |
526 | mode = curr_static_id->operand[i].mode; | |
527 | } | |
528 | curr_operand_mode[i] = mode; | |
529 | } | |
530 | } | |
531 | ||
532 | \f | |
533 | ||
534 | /* The page contains code to reuse input reloads. */ | |
535 | ||
536 | /* Structure describes input reload of the current insns. */ | |
537 | struct input_reload | |
538 | { | |
bd13359a | 539 | /* True for input reload of matched operands. */ |
540 | bool match_p; | |
c6a6cdaa | 541 | /* Reloaded value. */ |
542 | rtx input; | |
543 | /* Reload pseudo used. */ | |
544 | rtx reg; | |
545 | }; | |
546 | ||
547 | /* The number of elements in the following array. */ | |
548 | static int curr_insn_input_reloads_num; | |
549 | /* Array containing info about input reloads. It is used to find the | |
550 | same input reload and reuse the reload pseudo in this case. */ | |
551 | static struct input_reload curr_insn_input_reloads[LRA_MAX_INSN_RELOADS]; | |
552 | ||
553 | /* Initiate data concerning reuse of input reloads for the current | |
554 | insn. */ | |
555 | static void | |
556 | init_curr_insn_input_reloads (void) | |
557 | { | |
558 | curr_insn_input_reloads_num = 0; | |
559 | } | |
560 | ||
c6a6cdaa | 561 | /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already |
6cadc8f7 | 562 | created input reload pseudo (only if TYPE is not OP_OUT). Don't |
563 | reuse pseudo if IN_SUBREG_P is true and the reused pseudo should be | |
564 | wrapped up in SUBREG. The result pseudo is returned through | |
565 | RESULT_REG. Return TRUE if we created a new pseudo, FALSE if we | |
566 | reused the already created input reload pseudo. Use TITLE to | |
567 | describe new registers for debug purposes. */ | |
c6a6cdaa | 568 | static bool |
3754d046 | 569 | get_reload_reg (enum op_type type, machine_mode mode, rtx original, |
6cadc8f7 | 570 | enum reg_class rclass, bool in_subreg_p, |
571 | const char *title, rtx *result_reg) | |
c6a6cdaa | 572 | { |
573 | int i, regno; | |
574 | enum reg_class new_class; | |
bd13359a | 575 | bool unique_p = false; |
c6a6cdaa | 576 | |
577 | if (type == OP_OUT) | |
578 | { | |
579 | *result_reg | |
580 | = lra_create_new_reg_with_unique_value (mode, original, rclass, title); | |
581 | return true; | |
582 | } | |
85276115 | 583 | /* Prevent reuse value of expression with side effects, |
584 | e.g. volatile memory. */ | |
585 | if (! side_effects_p (original)) | |
586 | for (i = 0; i < curr_insn_input_reloads_num; i++) | |
bd13359a | 587 | { |
588 | if (! curr_insn_input_reloads[i].match_p | |
589 | && rtx_equal_p (curr_insn_input_reloads[i].input, original) | |
590 | && in_class_p (curr_insn_input_reloads[i].reg, rclass, &new_class)) | |
591 | { | |
592 | rtx reg = curr_insn_input_reloads[i].reg; | |
593 | regno = REGNO (reg); | |
594 | /* If input is equal to original and both are VOIDmode, | |
595 | GET_MODE (reg) might be still different from mode. | |
596 | Ensure we don't return *result_reg with wrong mode. */ | |
597 | if (GET_MODE (reg) != mode) | |
598 | { | |
599 | if (in_subreg_p) | |
600 | continue; | |
52acb7ae | 601 | if (maybe_lt (GET_MODE_SIZE (GET_MODE (reg)), |
602 | GET_MODE_SIZE (mode))) | |
bd13359a | 603 | continue; |
604 | reg = lowpart_subreg (mode, reg, GET_MODE (reg)); | |
605 | if (reg == NULL_RTX || GET_CODE (reg) != SUBREG) | |
606 | continue; | |
607 | } | |
608 | *result_reg = reg; | |
609 | if (lra_dump_file != NULL) | |
610 | { | |
611 | fprintf (lra_dump_file, " Reuse r%d for reload ", regno); | |
612 | dump_value_slim (lra_dump_file, original, 1); | |
613 | } | |
614 | if (new_class != lra_get_allocno_class (regno)) | |
615 | lra_change_class (regno, new_class, ", change to", false); | |
616 | if (lra_dump_file != NULL) | |
617 | fprintf (lra_dump_file, "\n"); | |
618 | return false; | |
619 | } | |
620 | /* If we have an input reload with a different mode, make sure it | |
621 | will get a different hard reg. */ | |
622 | else if (REG_P (original) | |
623 | && REG_P (curr_insn_input_reloads[i].input) | |
624 | && REGNO (original) == REGNO (curr_insn_input_reloads[i].input) | |
625 | && (GET_MODE (original) | |
626 | != GET_MODE (curr_insn_input_reloads[i].input))) | |
627 | unique_p = true; | |
628 | } | |
629 | *result_reg = (unique_p | |
630 | ? lra_create_new_reg_with_unique_value | |
631 | : lra_create_new_reg) (mode, original, rclass, title); | |
c6a6cdaa | 632 | lra_assert (curr_insn_input_reloads_num < LRA_MAX_INSN_RELOADS); |
633 | curr_insn_input_reloads[curr_insn_input_reloads_num].input = original; | |
bd13359a | 634 | curr_insn_input_reloads[curr_insn_input_reloads_num].match_p = false; |
c6a6cdaa | 635 | curr_insn_input_reloads[curr_insn_input_reloads_num++].reg = *result_reg; |
636 | return true; | |
637 | } | |
638 | ||
639 | \f | |
c6a6cdaa | 640 | /* The page contains major code to choose the current insn alternative |
641 | and generate reloads for it. */ | |
642 | ||
643 | /* Return the offset from REGNO of the least significant register | |
644 | in (reg:MODE REGNO). | |
645 | ||
646 | This function is used to tell whether two registers satisfy | |
647 | a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if: | |
648 | ||
649 | REGNO1 + lra_constraint_offset (REGNO1, MODE1) | |
650 | == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */ | |
651 | int | |
3754d046 | 652 | lra_constraint_offset (int regno, machine_mode mode) |
c6a6cdaa | 653 | { |
654 | lra_assert (regno < FIRST_PSEUDO_REGISTER); | |
8974b7a3 | 655 | |
656 | scalar_int_mode int_mode; | |
657 | if (WORDS_BIG_ENDIAN | |
658 | && is_a <scalar_int_mode> (mode, &int_mode) | |
659 | && GET_MODE_SIZE (int_mode) > UNITS_PER_WORD) | |
92d2aec3 | 660 | return hard_regno_nregs (regno, mode) - 1; |
c6a6cdaa | 661 | return 0; |
662 | } | |
663 | ||
664 | /* Like rtx_equal_p except that it allows a REG and a SUBREG to match | |
665 | if they are the same hard reg, and has special hacks for | |
666 | auto-increment and auto-decrement. This is specifically intended for | |
667 | process_alt_operands to use in determining whether two operands | |
668 | match. X is the operand whose number is the lower of the two. | |
669 | ||
670 | It is supposed that X is the output operand and Y is the input | |
671 | operand. Y_HARD_REGNO is the final hard regno of register Y or | |
672 | register in subreg Y as we know it now. Otherwise, it is a | |
673 | negative value. */ | |
674 | static bool | |
675 | operands_match_p (rtx x, rtx y, int y_hard_regno) | |
676 | { | |
677 | int i; | |
678 | RTX_CODE code = GET_CODE (x); | |
679 | const char *fmt; | |
680 | ||
681 | if (x == y) | |
682 | return true; | |
683 | if ((code == REG || (code == SUBREG && REG_P (SUBREG_REG (x)))) | |
684 | && (REG_P (y) || (GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y))))) | |
685 | { | |
686 | int j; | |
1a8f8886 | 687 | |
331a9ecc | 688 | i = get_hard_regno (x, false); |
c6a6cdaa | 689 | if (i < 0) |
690 | goto slow; | |
691 | ||
692 | if ((j = y_hard_regno) < 0) | |
693 | goto slow; | |
694 | ||
695 | i += lra_constraint_offset (i, GET_MODE (x)); | |
696 | j += lra_constraint_offset (j, GET_MODE (y)); | |
697 | ||
698 | return i == j; | |
699 | } | |
700 | ||
701 | /* If two operands must match, because they are really a single | |
702 | operand of an assembler insn, then two post-increments are invalid | |
703 | because the assembler insn would increment only once. On the | |
704 | other hand, a post-increment matches ordinary indexing if the | |
705 | post-increment is the output operand. */ | |
706 | if (code == POST_DEC || code == POST_INC || code == POST_MODIFY) | |
707 | return operands_match_p (XEXP (x, 0), y, y_hard_regno); | |
708 | ||
709 | /* Two pre-increments are invalid because the assembler insn would | |
710 | increment only once. On the other hand, a pre-increment matches | |
711 | ordinary indexing if the pre-increment is the input operand. */ | |
712 | if (GET_CODE (y) == PRE_DEC || GET_CODE (y) == PRE_INC | |
713 | || GET_CODE (y) == PRE_MODIFY) | |
714 | return operands_match_p (x, XEXP (y, 0), -1); | |
1a8f8886 | 715 | |
c6a6cdaa | 716 | slow: |
717 | ||
15183fd2 | 718 | if (code == REG && REG_P (y)) |
719 | return REGNO (x) == REGNO (y); | |
720 | ||
c6a6cdaa | 721 | if (code == REG && GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y)) |
722 | && x == SUBREG_REG (y)) | |
723 | return true; | |
724 | if (GET_CODE (y) == REG && code == SUBREG && REG_P (SUBREG_REG (x)) | |
725 | && SUBREG_REG (x) == y) | |
726 | return true; | |
727 | ||
728 | /* Now we have disposed of all the cases in which different rtx | |
729 | codes can match. */ | |
730 | if (code != GET_CODE (y)) | |
731 | return false; | |
732 | ||
733 | /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */ | |
734 | if (GET_MODE (x) != GET_MODE (y)) | |
735 | return false; | |
736 | ||
737 | switch (code) | |
738 | { | |
739 | CASE_CONST_UNIQUE: | |
740 | return false; | |
741 | ||
742 | case LABEL_REF: | |
c7799456 | 743 | return label_ref_label (x) == label_ref_label (y); |
c6a6cdaa | 744 | case SYMBOL_REF: |
745 | return XSTR (x, 0) == XSTR (y, 0); | |
746 | ||
747 | default: | |
748 | break; | |
749 | } | |
750 | ||
751 | /* Compare the elements. If any pair of corresponding elements fail | |
752 | to match, return false for the whole things. */ | |
753 | ||
754 | fmt = GET_RTX_FORMAT (code); | |
755 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
756 | { | |
757 | int val, j; | |
758 | switch (fmt[i]) | |
759 | { | |
760 | case 'w': | |
761 | if (XWINT (x, i) != XWINT (y, i)) | |
762 | return false; | |
763 | break; | |
764 | ||
765 | case 'i': | |
766 | if (XINT (x, i) != XINT (y, i)) | |
767 | return false; | |
768 | break; | |
769 | ||
9edf7ea8 | 770 | case 'p': |
771 | if (maybe_ne (SUBREG_BYTE (x), SUBREG_BYTE (y))) | |
772 | return false; | |
773 | break; | |
774 | ||
c6a6cdaa | 775 | case 'e': |
776 | val = operands_match_p (XEXP (x, i), XEXP (y, i), -1); | |
777 | if (val == 0) | |
778 | return false; | |
779 | break; | |
780 | ||
781 | case '0': | |
782 | break; | |
783 | ||
784 | case 'E': | |
785 | if (XVECLEN (x, i) != XVECLEN (y, i)) | |
786 | return false; | |
787 | for (j = XVECLEN (x, i) - 1; j >= 0; --j) | |
788 | { | |
789 | val = operands_match_p (XVECEXP (x, i, j), XVECEXP (y, i, j), -1); | |
790 | if (val == 0) | |
791 | return false; | |
792 | } | |
793 | break; | |
794 | ||
795 | /* It is believed that rtx's at this level will never | |
796 | contain anything but integers and other rtx's, except for | |
797 | within LABEL_REFs and SYMBOL_REFs. */ | |
798 | default: | |
799 | gcc_unreachable (); | |
800 | } | |
801 | } | |
802 | return true; | |
803 | } | |
804 | ||
805 | /* True if X is a constant that can be forced into the constant pool. | |
806 | MODE is the mode of the operand, or VOIDmode if not known. */ | |
807 | #define CONST_POOL_OK_P(MODE, X) \ | |
808 | ((MODE) != VOIDmode \ | |
809 | && CONSTANT_P (X) \ | |
810 | && GET_CODE (X) != HIGH \ | |
52acb7ae | 811 | && GET_MODE_SIZE (MODE).is_constant () \ |
c6a6cdaa | 812 | && !targetm.cannot_force_const_mem (MODE, X)) |
813 | ||
814 | /* True if C is a non-empty register class that has too few registers | |
815 | to be safely used as a reload target class. */ | |
4f428208 | 816 | #define SMALL_REGISTER_CLASS_P(C) \ |
817 | (ira_class_hard_regs_num [(C)] == 1 \ | |
818 | || (ira_class_hard_regs_num [(C)] >= 1 \ | |
819 | && targetm.class_likely_spilled_p (C))) | |
c6a6cdaa | 820 | |
821 | /* If REG is a reload pseudo, try to make its class satisfying CL. */ | |
822 | static void | |
823 | narrow_reload_pseudo_class (rtx reg, enum reg_class cl) | |
824 | { | |
825 | enum reg_class rclass; | |
826 | ||
827 | /* Do not make more accurate class from reloads generated. They are | |
828 | mostly moves with a lot of constraints. Making more accurate | |
829 | class may results in very narrow class and impossibility of find | |
830 | registers for several reloads of one insn. */ | |
831 | if (INSN_UID (curr_insn) >= new_insn_uid_start) | |
832 | return; | |
833 | if (GET_CODE (reg) == SUBREG) | |
834 | reg = SUBREG_REG (reg); | |
835 | if (! REG_P (reg) || (int) REGNO (reg) < new_regno_start) | |
836 | return; | |
837 | if (in_class_p (reg, cl, &rclass) && rclass != cl) | |
7619e612 | 838 | lra_change_class (REGNO (reg), rclass, " Change to", true); |
c6a6cdaa | 839 | } |
840 | ||
f64b137f | 841 | /* Searches X for any reference to a reg with the same value as REGNO, |
842 | returning the rtx of the reference found if any. Otherwise, | |
843 | returns NULL_RTX. */ | |
844 | static rtx | |
845 | regno_val_use_in (unsigned int regno, rtx x) | |
846 | { | |
847 | const char *fmt; | |
848 | int i, j; | |
849 | rtx tem; | |
850 | ||
851 | if (REG_P (x) && lra_reg_info[REGNO (x)].val == lra_reg_info[regno].val) | |
852 | return x; | |
853 | ||
854 | fmt = GET_RTX_FORMAT (GET_CODE (x)); | |
855 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) | |
856 | { | |
857 | if (fmt[i] == 'e') | |
858 | { | |
859 | if ((tem = regno_val_use_in (regno, XEXP (x, i)))) | |
860 | return tem; | |
861 | } | |
862 | else if (fmt[i] == 'E') | |
863 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
864 | if ((tem = regno_val_use_in (regno , XVECEXP (x, i, j)))) | |
865 | return tem; | |
866 | } | |
867 | ||
868 | return NULL_RTX; | |
869 | } | |
870 | ||
099c19e2 | 871 | /* Return true if all current insn non-output operands except INS (it |
872 | has a negaitve end marker) do not use pseudos with the same value | |
873 | as REGNO. */ | |
874 | static bool | |
875 | check_conflict_input_operands (int regno, signed char *ins) | |
876 | { | |
877 | int in; | |
878 | int n_operands = curr_static_id->n_operands; | |
879 | ||
880 | for (int nop = 0; nop < n_operands; nop++) | |
881 | if (! curr_static_id->operand[nop].is_operator | |
882 | && curr_static_id->operand[nop].type != OP_OUT) | |
883 | { | |
884 | for (int i = 0; (in = ins[i]) >= 0; i++) | |
885 | if (in == nop) | |
886 | break; | |
887 | if (in < 0 | |
888 | && regno_val_use_in (regno, *curr_id->operand_loc[nop]) != NULL_RTX) | |
889 | return false; | |
890 | } | |
891 | return true; | |
892 | } | |
893 | ||
c6a6cdaa | 894 | /* Generate reloads for matching OUT and INS (array of input operand |
dd083a02 | 895 | numbers with end marker -1) with reg class GOAL_CLASS, considering |
896 | output operands OUTS (similar array to INS) needing to be in different | |
897 | registers. Add input and output reloads correspondingly to the lists | |
898 | *BEFORE and *AFTER. OUT might be negative. In this case we generate | |
899 | input reloads for matched input operands INS. EARLY_CLOBBER_P is a flag | |
900 | that the output operand is early clobbered for chosen alternative. */ | |
c6a6cdaa | 901 | static void |
dd083a02 | 902 | match_reload (signed char out, signed char *ins, signed char *outs, |
903 | enum reg_class goal_class, rtx_insn **before, | |
904 | rtx_insn **after, bool early_clobber_p) | |
c6a6cdaa | 905 | { |
dd083a02 | 906 | bool out_conflict; |
c6a6cdaa | 907 | int i, in; |
9ed997be | 908 | rtx new_in_reg, new_out_reg, reg; |
3754d046 | 909 | machine_mode inmode, outmode; |
c6a6cdaa | 910 | rtx in_rtx = *curr_id->operand_loc[ins[0]]; |
aa3ce8ba | 911 | rtx out_rtx = out < 0 ? in_rtx : *curr_id->operand_loc[out]; |
c6a6cdaa | 912 | |
c6a6cdaa | 913 | inmode = curr_operand_mode[ins[0]]; |
aa3ce8ba | 914 | outmode = out < 0 ? inmode : curr_operand_mode[out]; |
c6a6cdaa | 915 | push_to_sequence (*before); |
916 | if (inmode != outmode) | |
917 | { | |
e23bf764 | 918 | /* process_alt_operands has already checked that the mode sizes |
919 | are ordered. */ | |
974534ab | 920 | if (partial_subreg_p (outmode, inmode)) |
c6a6cdaa | 921 | { |
922 | reg = new_in_reg | |
923 | = lra_create_new_reg_with_unique_value (inmode, in_rtx, | |
924 | goal_class, ""); | |
9346305f | 925 | new_out_reg = gen_lowpart_SUBREG (outmode, reg); |
ea99c7a1 | 926 | LRA_SUBREG_P (new_out_reg) = 1; |
ad6dc746 | 927 | /* If the input reg is dying here, we can use the same hard |
edfb1d8f | 928 | register for REG and IN_RTX. We do it only for original |
929 | pseudos as reload pseudos can die although original | |
930 | pseudos still live where reload pseudos dies. */ | |
931 | if (REG_P (in_rtx) && (int) REGNO (in_rtx) < lra_new_regno_start | |
099c19e2 | 932 | && find_regno_note (curr_insn, REG_DEAD, REGNO (in_rtx)) |
933 | && (!early_clobber_p | |
934 | || check_conflict_input_operands(REGNO (in_rtx), ins))) | |
a1064490 | 935 | lra_assign_reg_val (REGNO (in_rtx), REGNO (reg)); |
c6a6cdaa | 936 | } |
937 | else | |
938 | { | |
939 | reg = new_out_reg | |
940 | = lra_create_new_reg_with_unique_value (outmode, out_rtx, | |
941 | goal_class, ""); | |
9346305f | 942 | new_in_reg = gen_lowpart_SUBREG (inmode, reg); |
c6a6cdaa | 943 | /* NEW_IN_REG is non-paradoxical subreg. We don't want |
944 | NEW_OUT_REG living above. We add clobber clause for | |
ae72d5b2 | 945 | this. This is just a temporary clobber. We can remove |
946 | it at the end of LRA work. */ | |
9ed997be | 947 | rtx_insn *clobber = emit_clobber (new_out_reg); |
ae72d5b2 | 948 | LRA_TEMP_CLOBBER_P (PATTERN (clobber)) = 1; |
ea99c7a1 | 949 | LRA_SUBREG_P (new_in_reg) = 1; |
ad6dc746 | 950 | if (GET_CODE (in_rtx) == SUBREG) |
951 | { | |
952 | rtx subreg_reg = SUBREG_REG (in_rtx); | |
953 | ||
954 | /* If SUBREG_REG is dying here and sub-registers IN_RTX | |
955 | and NEW_IN_REG are similar, we can use the same hard | |
956 | register for REG and SUBREG_REG. */ | |
edfb1d8f | 957 | if (REG_P (subreg_reg) |
958 | && (int) REGNO (subreg_reg) < lra_new_regno_start | |
959 | && GET_MODE (subreg_reg) == outmode | |
9edf7ea8 | 960 | && known_eq (SUBREG_BYTE (in_rtx), SUBREG_BYTE (new_in_reg)) |
099c19e2 | 961 | && find_regno_note (curr_insn, REG_DEAD, REGNO (subreg_reg)) |
962 | && (! early_clobber_p | |
963 | || check_conflict_input_operands (REGNO (subreg_reg), | |
964 | ins))) | |
a1064490 | 965 | lra_assign_reg_val (REGNO (subreg_reg), REGNO (reg)); |
ad6dc746 | 966 | } |
c6a6cdaa | 967 | } |
968 | } | |
969 | else | |
970 | { | |
971 | /* Pseudos have values -- see comments for lra_reg_info. | |
972 | Different pseudos with the same value do not conflict even if | |
973 | they live in the same place. When we create a pseudo we | |
974 | assign value of original pseudo (if any) from which we | |
975 | created the new pseudo. If we create the pseudo from the | |
0af99ebf | 976 | input pseudo, the new pseudo will have no conflict with the |
977 | input pseudo which is wrong when the input pseudo lives after | |
978 | the insn and as the new pseudo value is changed by the insn | |
979 | output. Therefore we create the new pseudo from the output | |
980 | except the case when we have single matched dying input | |
981 | pseudo. | |
1a8f8886 | 982 | |
c6a6cdaa | 983 | We cannot reuse the current output register because we might |
984 | have a situation like "a <- a op b", where the constraints | |
985 | force the second input operand ("b") to match the output | |
986 | operand ("a"). "b" must then be copied into a new register | |
72460f4d | 987 | so that it doesn't clobber the current value of "a". |
988 | ||
f4d3c071 | 989 | We cannot use the same value if the output pseudo is |
72460f4d | 990 | early clobbered or the input pseudo is mentioned in the |
991 | output, e.g. as an address part in memory, because | |
992 | output reload will actually extend the pseudo liveness. | |
993 | We don't care about eliminable hard regs here as we are | |
994 | interesting only in pseudos. */ | |
1a8f8886 | 995 | |
dd083a02 | 996 | /* Matching input's register value is the same as one of the other |
997 | output operand. Output operands in a parallel insn must be in | |
998 | different registers. */ | |
999 | out_conflict = false; | |
1000 | if (REG_P (in_rtx)) | |
1001 | { | |
1002 | for (i = 0; outs[i] >= 0; i++) | |
1003 | { | |
1004 | rtx other_out_rtx = *curr_id->operand_loc[outs[i]]; | |
1005 | if (REG_P (other_out_rtx) | |
1006 | && (regno_val_use_in (REGNO (in_rtx), other_out_rtx) | |
1007 | != NULL_RTX)) | |
1008 | { | |
1009 | out_conflict = true; | |
1010 | break; | |
1011 | } | |
1012 | } | |
1013 | } | |
1014 | ||
c6a6cdaa | 1015 | new_in_reg = new_out_reg |
72460f4d | 1016 | = (! early_clobber_p && ins[1] < 0 && REG_P (in_rtx) |
0af99ebf | 1017 | && (int) REGNO (in_rtx) < lra_new_regno_start |
1018 | && find_regno_note (curr_insn, REG_DEAD, REGNO (in_rtx)) | |
099c19e2 | 1019 | && (! early_clobber_p |
1020 | || check_conflict_input_operands (REGNO (in_rtx), ins)) | |
f64b137f | 1021 | && (out < 0 |
1022 | || regno_val_use_in (REGNO (in_rtx), out_rtx) == NULL_RTX) | |
dd083a02 | 1023 | && !out_conflict |
0af99ebf | 1024 | ? lra_create_new_reg (inmode, in_rtx, goal_class, "") |
1025 | : lra_create_new_reg_with_unique_value (outmode, out_rtx, | |
1026 | goal_class, "")); | |
c6a6cdaa | 1027 | } |
aa3ce8ba | 1028 | /* In operand can be got from transformations before processing insn |
1029 | constraints. One example of such transformations is subreg | |
1030 | reloading (see function simplify_operand_subreg). The new | |
1031 | pseudos created by the transformations might have inaccurate | |
c6a6cdaa | 1032 | class (ALL_REGS) and we should make their classes more |
1033 | accurate. */ | |
1034 | narrow_reload_pseudo_class (in_rtx, goal_class); | |
c6a6cdaa | 1035 | lra_emit_move (copy_rtx (new_in_reg), in_rtx); |
1036 | *before = get_insns (); | |
1037 | end_sequence (); | |
bd13359a | 1038 | /* Add the new pseudo to consider values of subsequent input reload |
1039 | pseudos. */ | |
1040 | lra_assert (curr_insn_input_reloads_num < LRA_MAX_INSN_RELOADS); | |
1041 | curr_insn_input_reloads[curr_insn_input_reloads_num].input = in_rtx; | |
1042 | curr_insn_input_reloads[curr_insn_input_reloads_num].match_p = true; | |
1043 | curr_insn_input_reloads[curr_insn_input_reloads_num++].reg = new_in_reg; | |
c6a6cdaa | 1044 | for (i = 0; (in = ins[i]) >= 0; i++) |
1045 | { | |
1046 | lra_assert | |
1047 | (GET_MODE (*curr_id->operand_loc[in]) == VOIDmode | |
1048 | || GET_MODE (new_in_reg) == GET_MODE (*curr_id->operand_loc[in])); | |
1049 | *curr_id->operand_loc[in] = new_in_reg; | |
1050 | } | |
1051 | lra_update_dups (curr_id, ins); | |
aa3ce8ba | 1052 | if (out < 0) |
1053 | return; | |
1054 | /* See a comment for the input operand above. */ | |
1055 | narrow_reload_pseudo_class (out_rtx, goal_class); | |
c6a6cdaa | 1056 | if (find_reg_note (curr_insn, REG_UNUSED, out_rtx) == NULL_RTX) |
1057 | { | |
1058 | start_sequence (); | |
1059 | lra_emit_move (out_rtx, copy_rtx (new_out_reg)); | |
1060 | emit_insn (*after); | |
1061 | *after = get_insns (); | |
1062 | end_sequence (); | |
1063 | } | |
1064 | *curr_id->operand_loc[out] = new_out_reg; | |
1065 | lra_update_dup (curr_id, out); | |
1066 | } | |
1067 | ||
1068 | /* Return register class which is union of all reg classes in insn | |
1069 | constraint alternative string starting with P. */ | |
1070 | static enum reg_class | |
1071 | reg_class_from_constraints (const char *p) | |
1072 | { | |
1073 | int c, len; | |
1074 | enum reg_class op_class = NO_REGS; | |
1075 | ||
1076 | do | |
1077 | switch ((c = *p, len = CONSTRAINT_LEN (c, p)), c) | |
1078 | { | |
1079 | case '#': | |
1080 | case ',': | |
1081 | return op_class; | |
1082 | ||
c6a6cdaa | 1083 | case 'g': |
c6a6cdaa | 1084 | op_class = reg_class_subunion[op_class][GENERAL_REGS]; |
1085 | break; | |
1a8f8886 | 1086 | |
c6a6cdaa | 1087 | default: |
79bc09fb | 1088 | enum constraint_num cn = lookup_constraint (p); |
1089 | enum reg_class cl = reg_class_for_constraint (cn); | |
1090 | if (cl == NO_REGS) | |
c6a6cdaa | 1091 | { |
79bc09fb | 1092 | if (insn_extra_address_constraint (cn)) |
c6a6cdaa | 1093 | op_class |
1094 | = (reg_class_subunion | |
1095 | [op_class][base_reg_class (VOIDmode, ADDR_SPACE_GENERIC, | |
1096 | ADDRESS, SCRATCH)]); | |
c6a6cdaa | 1097 | break; |
1098 | } | |
1a8f8886 | 1099 | |
79bc09fb | 1100 | op_class = reg_class_subunion[op_class][cl]; |
1101 | break; | |
c6a6cdaa | 1102 | } |
1103 | while ((p += len), c); | |
1104 | return op_class; | |
1105 | } | |
1106 | ||
1107 | /* If OP is a register, return the class of the register as per | |
1108 | get_reg_class, otherwise return NO_REGS. */ | |
1109 | static inline enum reg_class | |
1110 | get_op_class (rtx op) | |
1111 | { | |
1112 | return REG_P (op) ? get_reg_class (REGNO (op)) : NO_REGS; | |
1113 | } | |
1114 | ||
1115 | /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo | |
1116 | otherwise. If modes of MEM_PSEUDO and VAL are different, use | |
1117 | SUBREG for VAL to make them equal. */ | |
7f836b57 | 1118 | static rtx_insn * |
c6a6cdaa | 1119 | emit_spill_move (bool to_p, rtx mem_pseudo, rtx val) |
1120 | { | |
1121 | if (GET_MODE (mem_pseudo) != GET_MODE (val)) | |
ea99c7a1 | 1122 | { |
34575461 | 1123 | /* Usually size of mem_pseudo is greater than val size but in |
1124 | rare cases it can be less as it can be defined by target | |
1125 | dependent macro HARD_REGNO_CALLER_SAVE_MODE. */ | |
cc0dc61b | 1126 | if (! MEM_P (val)) |
1127 | { | |
05856efc | 1128 | val = gen_lowpart_SUBREG (GET_MODE (mem_pseudo), |
1129 | GET_CODE (val) == SUBREG | |
1130 | ? SUBREG_REG (val) : val); | |
cc0dc61b | 1131 | LRA_SUBREG_P (val) = 1; |
1132 | } | |
1133 | else | |
1134 | { | |
1135 | mem_pseudo = gen_lowpart_SUBREG (GET_MODE (val), mem_pseudo); | |
1136 | LRA_SUBREG_P (mem_pseudo) = 1; | |
1137 | } | |
ea99c7a1 | 1138 | } |
f9a00e9e | 1139 | return to_p ? gen_move_insn (mem_pseudo, val) |
1140 | : gen_move_insn (val, mem_pseudo); | |
c6a6cdaa | 1141 | } |
1142 | ||
1143 | /* Process a special case insn (register move), return true if we | |
ea99c7a1 | 1144 | don't need to process it anymore. INSN should be a single set |
c836e75b | 1145 | insn. Set up that RTL was changed through CHANGE_P and that hook |
1146 | TARGET_SECONDARY_MEMORY_NEEDED says to use secondary memory through | |
ea99c7a1 | 1147 | SEC_MEM_P. */ |
c6a6cdaa | 1148 | static bool |
ea99c7a1 | 1149 | check_and_process_move (bool *change_p, bool *sec_mem_p ATTRIBUTE_UNUSED) |
c6a6cdaa | 1150 | { |
1151 | int sregno, dregno; | |
28323099 | 1152 | rtx dest, src, dreg, sreg, new_reg, scratch_reg; |
7f836b57 | 1153 | rtx_insn *before; |
c6a6cdaa | 1154 | enum reg_class dclass, sclass, secondary_class; |
c6a6cdaa | 1155 | secondary_reload_info sri; |
1156 | ||
ea99c7a1 | 1157 | lra_assert (curr_insn_set != NULL_RTX); |
1158 | dreg = dest = SET_DEST (curr_insn_set); | |
1159 | sreg = src = SET_SRC (curr_insn_set); | |
c6a6cdaa | 1160 | if (GET_CODE (dest) == SUBREG) |
1161 | dreg = SUBREG_REG (dest); | |
1162 | if (GET_CODE (src) == SUBREG) | |
1163 | sreg = SUBREG_REG (src); | |
cc0dc61b | 1164 | if (! (REG_P (dreg) || MEM_P (dreg)) || ! (REG_P (sreg) || MEM_P (sreg))) |
c6a6cdaa | 1165 | return false; |
1166 | sclass = dclass = NO_REGS; | |
c6a6cdaa | 1167 | if (REG_P (dreg)) |
1168 | dclass = get_reg_class (REGNO (dreg)); | |
68e1f2b7 | 1169 | gcc_assert (dclass < LIM_REG_CLASSES); |
c6a6cdaa | 1170 | if (dclass == ALL_REGS) |
1171 | /* ALL_REGS is used for new pseudos created by transformations | |
1172 | like reload of SUBREG_REG (see function | |
1173 | simplify_operand_subreg). We don't know their class yet. We | |
1174 | should figure out the class from processing the insn | |
1175 | constraints not in this fast path function. Even if ALL_REGS | |
1176 | were a right class for the pseudo, secondary_... hooks usually | |
1177 | are not define for ALL_REGS. */ | |
1178 | return false; | |
c6a6cdaa | 1179 | if (REG_P (sreg)) |
1180 | sclass = get_reg_class (REGNO (sreg)); | |
68e1f2b7 | 1181 | gcc_assert (sclass < LIM_REG_CLASSES); |
c6a6cdaa | 1182 | if (sclass == ALL_REGS) |
1183 | /* See comments above. */ | |
1184 | return false; | |
cc0dc61b | 1185 | if (sclass == NO_REGS && dclass == NO_REGS) |
1186 | return false; | |
c836e75b | 1187 | if (targetm.secondary_memory_needed (GET_MODE (src), sclass, dclass) |
cc0dc61b | 1188 | && ((sclass != NO_REGS && dclass != NO_REGS) |
1041f930 | 1189 | || (GET_MODE (src) |
1190 | != targetm.secondary_memory_needed_mode (GET_MODE (src))))) | |
c6a6cdaa | 1191 | { |
1192 | *sec_mem_p = true; | |
1193 | return false; | |
1194 | } | |
cc0dc61b | 1195 | if (! REG_P (dreg) || ! REG_P (sreg)) |
1196 | return false; | |
c6a6cdaa | 1197 | sri.prev_sri = NULL; |
1198 | sri.icode = CODE_FOR_nothing; | |
1199 | sri.extra_cost = 0; | |
1200 | secondary_class = NO_REGS; | |
1201 | /* Set up hard register for a reload pseudo for hook | |
1202 | secondary_reload because some targets just ignore unassigned | |
1203 | pseudos in the hook. */ | |
1204 | if (dclass != NO_REGS && lra_get_regno_hard_regno (REGNO (dreg)) < 0) | |
1205 | { | |
1206 | dregno = REGNO (dreg); | |
1207 | reg_renumber[dregno] = ira_class_hard_regs[dclass][0]; | |
1208 | } | |
1209 | else | |
1210 | dregno = -1; | |
1211 | if (sclass != NO_REGS && lra_get_regno_hard_regno (REGNO (sreg)) < 0) | |
1212 | { | |
1213 | sregno = REGNO (sreg); | |
1214 | reg_renumber[sregno] = ira_class_hard_regs[sclass][0]; | |
1215 | } | |
1216 | else | |
1217 | sregno = -1; | |
1218 | if (sclass != NO_REGS) | |
1219 | secondary_class | |
1220 | = (enum reg_class) targetm.secondary_reload (false, dest, | |
1221 | (reg_class_t) sclass, | |
1222 | GET_MODE (src), &sri); | |
1223 | if (sclass == NO_REGS | |
1224 | || ((secondary_class != NO_REGS || sri.icode != CODE_FOR_nothing) | |
1225 | && dclass != NO_REGS)) | |
1226 | { | |
c6a6cdaa | 1227 | enum reg_class old_sclass = secondary_class; |
1228 | secondary_reload_info old_sri = sri; | |
c6a6cdaa | 1229 | |
1230 | sri.prev_sri = NULL; | |
1231 | sri.icode = CODE_FOR_nothing; | |
1232 | sri.extra_cost = 0; | |
1233 | secondary_class | |
28323099 | 1234 | = (enum reg_class) targetm.secondary_reload (true, src, |
c6a6cdaa | 1235 | (reg_class_t) dclass, |
28323099 | 1236 | GET_MODE (src), &sri); |
c6a6cdaa | 1237 | /* Check the target hook consistency. */ |
1238 | lra_assert | |
1239 | ((secondary_class == NO_REGS && sri.icode == CODE_FOR_nothing) | |
1240 | || (old_sclass == NO_REGS && old_sri.icode == CODE_FOR_nothing) | |
1241 | || (secondary_class == old_sclass && sri.icode == old_sri.icode)); | |
1242 | } | |
1243 | if (sregno >= 0) | |
1244 | reg_renumber [sregno] = -1; | |
1245 | if (dregno >= 0) | |
1246 | reg_renumber [dregno] = -1; | |
1247 | if (secondary_class == NO_REGS && sri.icode == CODE_FOR_nothing) | |
1248 | return false; | |
1249 | *change_p = true; | |
1250 | new_reg = NULL_RTX; | |
1251 | if (secondary_class != NO_REGS) | |
28323099 | 1252 | new_reg = lra_create_new_reg_with_unique_value (GET_MODE (src), NULL_RTX, |
c6a6cdaa | 1253 | secondary_class, |
1254 | "secondary"); | |
1255 | start_sequence (); | |
c6a6cdaa | 1256 | if (sri.icode == CODE_FOR_nothing) |
28323099 | 1257 | lra_emit_move (new_reg, src); |
c6a6cdaa | 1258 | else |
1259 | { | |
1260 | enum reg_class scratch_class; | |
1261 | ||
1262 | scratch_class = (reg_class_from_constraints | |
1263 | (insn_data[sri.icode].operand[2].constraint)); | |
1264 | scratch_reg = (lra_create_new_reg_with_unique_value | |
1265 | (insn_data[sri.icode].operand[2].mode, NULL_RTX, | |
1266 | scratch_class, "scratch")); | |
1267 | emit_insn (GEN_FCN (sri.icode) (new_reg != NULL_RTX ? new_reg : dest, | |
28323099 | 1268 | src, scratch_reg)); |
c6a6cdaa | 1269 | } |
1270 | before = get_insns (); | |
1271 | end_sequence (); | |
7f836b57 | 1272 | lra_process_new_insns (curr_insn, before, NULL, "Inserting the move"); |
c6a6cdaa | 1273 | if (new_reg != NULL_RTX) |
28323099 | 1274 | SET_SRC (curr_insn_set) = new_reg; |
c6a6cdaa | 1275 | else |
1276 | { | |
1277 | if (lra_dump_file != NULL) | |
1278 | { | |
1279 | fprintf (lra_dump_file, "Deleting move %u\n", INSN_UID (curr_insn)); | |
6dde9719 | 1280 | dump_insn_slim (lra_dump_file, curr_insn); |
c6a6cdaa | 1281 | } |
1282 | lra_set_insn_deleted (curr_insn); | |
1283 | return true; | |
1284 | } | |
1285 | return false; | |
1286 | } | |
1287 | ||
1288 | /* The following data describe the result of process_alt_operands. | |
1289 | The data are used in curr_insn_transform to generate reloads. */ | |
1290 | ||
1291 | /* The chosen reg classes which should be used for the corresponding | |
1292 | operands. */ | |
1293 | static enum reg_class goal_alt[MAX_RECOG_OPERANDS]; | |
1294 | /* True if the operand should be the same as another operand and that | |
1295 | other operand does not need a reload. */ | |
1296 | static bool goal_alt_match_win[MAX_RECOG_OPERANDS]; | |
1297 | /* True if the operand does not need a reload. */ | |
1298 | static bool goal_alt_win[MAX_RECOG_OPERANDS]; | |
1299 | /* True if the operand can be offsetable memory. */ | |
1300 | static bool goal_alt_offmemok[MAX_RECOG_OPERANDS]; | |
1301 | /* The number of an operand to which given operand can be matched to. */ | |
1302 | static int goal_alt_matches[MAX_RECOG_OPERANDS]; | |
1303 | /* The number of elements in the following array. */ | |
1304 | static int goal_alt_dont_inherit_ops_num; | |
1305 | /* Numbers of operands whose reload pseudos should not be inherited. */ | |
1306 | static int goal_alt_dont_inherit_ops[MAX_RECOG_OPERANDS]; | |
1307 | /* True if the insn commutative operands should be swapped. */ | |
1308 | static bool goal_alt_swapped; | |
1309 | /* The chosen insn alternative. */ | |
1310 | static int goal_alt_number; | |
1311 | ||
003000a4 | 1312 | /* True if the corresponding operand is the result of an equivalence |
1313 | substitution. */ | |
1314 | static bool equiv_substition_p[MAX_RECOG_OPERANDS]; | |
1315 | ||
c6a6cdaa | 1316 | /* The following five variables are used to choose the best insn |
1317 | alternative. They reflect final characteristics of the best | |
1318 | alternative. */ | |
1319 | ||
1320 | /* Number of necessary reloads and overall cost reflecting the | |
1321 | previous value and other unpleasantness of the best alternative. */ | |
1322 | static int best_losers, best_overall; | |
c6a6cdaa | 1323 | /* Overall number hard registers used for reloads. For example, on |
1324 | some targets we need 2 general registers to reload DFmode and only | |
1325 | one floating point register. */ | |
1326 | static int best_reload_nregs; | |
1327 | /* Overall number reflecting distances of previous reloading the same | |
1328 | value. The distances are counted from the current BB start. It is | |
1329 | used to improve inheritance chances. */ | |
1330 | static int best_reload_sum; | |
1331 | ||
1332 | /* True if the current insn should have no correspondingly input or | |
1333 | output reloads. */ | |
1334 | static bool no_input_reloads_p, no_output_reloads_p; | |
1335 | ||
1336 | /* True if we swapped the commutative operands in the current | |
1337 | insn. */ | |
1338 | static int curr_swapped; | |
1339 | ||
497ba60f | 1340 | /* if CHECK_ONLY_P is false, arrange for address element *LOC to be a |
1341 | register of class CL. Add any input reloads to list BEFORE. AFTER | |
1342 | is nonnull if *LOC is an automodified value; handle that case by | |
1343 | adding the required output reloads to list AFTER. Return true if | |
1344 | the RTL was changed. | |
1345 | ||
1346 | if CHECK_ONLY_P is true, check that the *LOC is a correct address | |
1347 | register. Return false if the address register is correct. */ | |
c6a6cdaa | 1348 | static bool |
497ba60f | 1349 | process_addr_reg (rtx *loc, bool check_only_p, rtx_insn **before, rtx_insn **after, |
7f836b57 | 1350 | enum reg_class cl) |
c6a6cdaa | 1351 | { |
1352 | int regno; | |
1353 | enum reg_class rclass, new_class; | |
1efe9e9d | 1354 | rtx reg; |
c6a6cdaa | 1355 | rtx new_reg; |
3754d046 | 1356 | machine_mode mode; |
6cadc8f7 | 1357 | bool subreg_p, before_p = false; |
c6a6cdaa | 1358 | |
6cadc8f7 | 1359 | subreg_p = GET_CODE (*loc) == SUBREG; |
1360 | if (subreg_p) | |
4fe01ba9 | 1361 | { |
1362 | reg = SUBREG_REG (*loc); | |
1363 | mode = GET_MODE (reg); | |
1364 | ||
1365 | /* For mode with size bigger than ptr_mode, there unlikely to be "mov" | |
1366 | between two registers with different classes, but there normally will | |
1367 | be "mov" which transfers element of vector register into the general | |
1368 | register, and this normally will be a subreg which should be reloaded | |
1369 | as a whole. This is particularly likely to be triggered when | |
1370 | -fno-split-wide-types specified. */ | |
2e9acae0 | 1371 | if (!REG_P (reg) |
1372 | || in_class_p (reg, cl, &new_class) | |
52acb7ae | 1373 | || known_le (GET_MODE_SIZE (mode), GET_MODE_SIZE (ptr_mode))) |
4fe01ba9 | 1374 | loc = &SUBREG_REG (*loc); |
1375 | } | |
1376 | ||
1efe9e9d | 1377 | reg = *loc; |
c6a6cdaa | 1378 | mode = GET_MODE (reg); |
1379 | if (! REG_P (reg)) | |
1380 | { | |
497ba60f | 1381 | if (check_only_p) |
1382 | return true; | |
c6a6cdaa | 1383 | /* Always reload memory in an address even if the target supports |
1384 | such addresses. */ | |
1385 | new_reg = lra_create_new_reg_with_unique_value (mode, reg, cl, "address"); | |
1386 | before_p = true; | |
1387 | } | |
1388 | else | |
1389 | { | |
1390 | regno = REGNO (reg); | |
1391 | rclass = get_reg_class (regno); | |
497ba60f | 1392 | if (! check_only_p |
1393 | && (*loc = get_equiv_with_elimination (reg, curr_insn)) != reg) | |
c6a6cdaa | 1394 | { |
1395 | if (lra_dump_file != NULL) | |
1396 | { | |
1397 | fprintf (lra_dump_file, | |
1398 | "Changing pseudo %d in address of insn %u on equiv ", | |
1399 | REGNO (reg), INSN_UID (curr_insn)); | |
6dde9719 | 1400 | dump_value_slim (lra_dump_file, *loc, 1); |
c6a6cdaa | 1401 | fprintf (lra_dump_file, "\n"); |
1402 | } | |
1403 | *loc = copy_rtx (*loc); | |
1404 | } | |
1405 | if (*loc != reg || ! in_class_p (reg, cl, &new_class)) | |
1406 | { | |
497ba60f | 1407 | if (check_only_p) |
1408 | return true; | |
c6a6cdaa | 1409 | reg = *loc; |
1410 | if (get_reload_reg (after == NULL ? OP_IN : OP_INOUT, | |
6cadc8f7 | 1411 | mode, reg, cl, subreg_p, "address", &new_reg)) |
c6a6cdaa | 1412 | before_p = true; |
1413 | } | |
1414 | else if (new_class != NO_REGS && rclass != new_class) | |
1415 | { | |
497ba60f | 1416 | if (check_only_p) |
1417 | return true; | |
7619e612 | 1418 | lra_change_class (regno, new_class, " Change to", true); |
c6a6cdaa | 1419 | return false; |
1420 | } | |
1421 | else | |
1422 | return false; | |
1423 | } | |
1424 | if (before_p) | |
1425 | { | |
1426 | push_to_sequence (*before); | |
1427 | lra_emit_move (new_reg, reg); | |
1428 | *before = get_insns (); | |
1429 | end_sequence (); | |
1430 | } | |
1431 | *loc = new_reg; | |
1432 | if (after != NULL) | |
1433 | { | |
1434 | start_sequence (); | |
c8f7cecf | 1435 | lra_emit_move (before_p ? copy_rtx (reg) : reg, new_reg); |
c6a6cdaa | 1436 | emit_insn (*after); |
1437 | *after = get_insns (); | |
1438 | end_sequence (); | |
1439 | } | |
1440 | return true; | |
1441 | } | |
1442 | ||
c5334148 | 1443 | /* Insert move insn in simplify_operand_subreg. BEFORE returns |
1444 | the insn to be inserted before curr insn. AFTER returns the | |
1445 | the insn to be inserted after curr insn. ORIGREG and NEWREG | |
1446 | are the original reg and new reg for reload. */ | |
1447 | static void | |
7f836b57 | 1448 | insert_move_for_subreg (rtx_insn **before, rtx_insn **after, rtx origreg, |
1449 | rtx newreg) | |
c5334148 | 1450 | { |
1451 | if (before) | |
1452 | { | |
1453 | push_to_sequence (*before); | |
1454 | lra_emit_move (newreg, origreg); | |
1455 | *before = get_insns (); | |
1456 | end_sequence (); | |
1457 | } | |
1458 | if (after) | |
1459 | { | |
1460 | start_sequence (); | |
1461 | lra_emit_move (origreg, newreg); | |
1462 | emit_insn (*after); | |
1463 | *after = get_insns (); | |
1464 | end_sequence (); | |
1465 | } | |
1466 | } | |
1467 | ||
3754d046 | 1468 | static int valid_address_p (machine_mode mode, rtx addr, addr_space_t as); |
856bd6f2 | 1469 | static bool process_address (int, bool, rtx_insn **, rtx_insn **); |
1a68e833 | 1470 | |
c6a6cdaa | 1471 | /* Make reloads for subreg in operand NOP with internal subreg mode |
1472 | REG_MODE, add new reloads for further processing. Return true if | |
1aae95ec | 1473 | any change was done. */ |
c6a6cdaa | 1474 | static bool |
3754d046 | 1475 | simplify_operand_subreg (int nop, machine_mode reg_mode) |
c6a6cdaa | 1476 | { |
1477 | int hard_regno; | |
7f836b57 | 1478 | rtx_insn *before, *after; |
1aae95ec | 1479 | machine_mode mode, innermode; |
c6a6cdaa | 1480 | rtx reg, new_reg; |
1481 | rtx operand = *curr_id->operand_loc[nop]; | |
c5334148 | 1482 | enum reg_class regclass; |
1483 | enum op_type type; | |
c6a6cdaa | 1484 | |
7f836b57 | 1485 | before = after = NULL; |
c6a6cdaa | 1486 | |
1487 | if (GET_CODE (operand) != SUBREG) | |
1488 | return false; | |
1a8f8886 | 1489 | |
c6a6cdaa | 1490 | mode = GET_MODE (operand); |
1491 | reg = SUBREG_REG (operand); | |
1aae95ec | 1492 | innermode = GET_MODE (reg); |
c5334148 | 1493 | type = curr_static_id->operand[nop].type; |
2d2b78a1 | 1494 | if (MEM_P (reg)) |
1a68e833 | 1495 | { |
856bd6f2 | 1496 | const bool addr_was_valid |
1497 | = valid_address_p (innermode, XEXP (reg, 0), MEM_ADDR_SPACE (reg)); | |
1a68e833 | 1498 | alter_subreg (curr_id->operand_loc[nop], false); |
856bd6f2 | 1499 | rtx subst = *curr_id->operand_loc[nop]; |
1a68e833 | 1500 | lra_assert (MEM_P (subst)); |
3143c7ef | 1501 | const bool addr_is_valid = valid_address_p (GET_MODE (subst), |
1502 | XEXP (subst, 0), | |
1503 | MEM_ADDR_SPACE (subst)); | |
856bd6f2 | 1504 | if (!addr_was_valid |
3143c7ef | 1505 | || addr_is_valid |
2d2b78a1 | 1506 | || ((get_constraint_type (lookup_constraint |
1507 | (curr_static_id->operand[nop].constraint)) | |
1508 | != CT_SPECIAL_MEMORY) | |
1509 | /* We still can reload address and if the address is | |
1510 | valid, we can remove subreg without reloading its | |
1511 | inner memory. */ | |
1512 | && valid_address_p (GET_MODE (subst), | |
1513 | regno_reg_rtx | |
1514 | [ira_class_hard_regs | |
1515 | [base_reg_class (GET_MODE (subst), | |
1516 | MEM_ADDR_SPACE (subst), | |
1517 | ADDRESS, SCRATCH)][0]], | |
1518 | MEM_ADDR_SPACE (subst)))) | |
1519 | { | |
856bd6f2 | 1520 | /* If we change the address for a paradoxical subreg of memory, the |
b0f26d5e | 1521 | new address might violate the necessary alignment or the access |
1522 | might be slow; take this into consideration. We need not worry | |
856bd6f2 | 1523 | about accesses beyond allocated memory for paradoxical memory |
2d2b78a1 | 1524 | subregs as we don't substitute such equiv memory (see processing |
1525 | equivalences in function lra_constraints) and because for spilled | |
1526 | pseudos we allocate stack memory enough for the biggest | |
8d7a5013 | 1527 | corresponding paradoxical subreg. |
1528 | ||
1529 | However, do not blindly simplify a (subreg (mem ...)) for | |
1530 | WORD_REGISTER_OPERATIONS targets as this may lead to loading junk | |
1531 | data into a register when the inner is narrower than outer or | |
1532 | missing important data from memory when the inner is wider than | |
1533 | outer. This rule only applies to modes that are no wider than | |
3143c7ef | 1534 | a word. |
1535 | ||
1536 | If valid memory becomes invalid after subreg elimination | |
c2041c0a | 1537 | and address might be different we still have to reload |
1538 | memory. | |
3143c7ef | 1539 | */ |
c2041c0a | 1540 | if ((! addr_was_valid |
1541 | || addr_is_valid | |
1542 | || known_eq (GET_MODE_SIZE (mode), GET_MODE_SIZE (innermode))) | |
3143c7ef | 1543 | && !(maybe_ne (GET_MODE_PRECISION (mode), |
1544 | GET_MODE_PRECISION (innermode)) | |
1545 | && known_le (GET_MODE_SIZE (mode), UNITS_PER_WORD) | |
1546 | && known_le (GET_MODE_SIZE (innermode), UNITS_PER_WORD) | |
1547 | && WORD_REGISTER_OPERATIONS) | |
8d7a5013 | 1548 | && (!(MEM_ALIGN (subst) < GET_MODE_ALIGNMENT (mode) |
dfdced85 | 1549 | && targetm.slow_unaligned_access (mode, MEM_ALIGN (subst))) |
8d7a5013 | 1550 | || (MEM_ALIGN (reg) < GET_MODE_ALIGNMENT (innermode) |
dfdced85 | 1551 | && targetm.slow_unaligned_access (innermode, |
1552 | MEM_ALIGN (reg))))) | |
2d2b78a1 | 1553 | return true; |
1554 | ||
856bd6f2 | 1555 | *curr_id->operand_loc[nop] = operand; |
1556 | ||
1557 | /* But if the address was not valid, we cannot reload the MEM without | |
1558 | reloading the address first. */ | |
1559 | if (!addr_was_valid) | |
1560 | process_address (nop, false, &before, &after); | |
1561 | ||
2d2b78a1 | 1562 | /* INNERMODE is fast, MODE slow. Reload the mem in INNERMODE. */ |
1563 | enum reg_class rclass | |
1564 | = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS); | |
856bd6f2 | 1565 | if (get_reload_reg (curr_static_id->operand[nop].type, innermode, |
3143c7ef | 1566 | reg, rclass, TRUE, "slow/invalid mem", &new_reg)) |
2d2b78a1 | 1567 | { |
1568 | bool insert_before, insert_after; | |
1569 | bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg)); | |
1570 | ||
1571 | insert_before = (type != OP_OUT | |
974534ab | 1572 | || partial_subreg_p (mode, innermode)); |
2d2b78a1 | 1573 | insert_after = type != OP_IN; |
1574 | insert_move_for_subreg (insert_before ? &before : NULL, | |
1575 | insert_after ? &after : NULL, | |
1576 | reg, new_reg); | |
1577 | } | |
2d2b78a1 | 1578 | SUBREG_REG (operand) = new_reg; |
1579 | ||
1580 | /* Convert to MODE. */ | |
1581 | reg = operand; | |
856bd6f2 | 1582 | rclass |
1583 | = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS); | |
2d2b78a1 | 1584 | if (get_reload_reg (curr_static_id->operand[nop].type, mode, reg, |
3143c7ef | 1585 | rclass, TRUE, "slow/invalid mem", &new_reg)) |
2d2b78a1 | 1586 | { |
1587 | bool insert_before, insert_after; | |
1588 | bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg)); | |
1589 | ||
1590 | insert_before = type != OP_OUT; | |
1591 | insert_after = type != OP_IN; | |
1592 | insert_move_for_subreg (insert_before ? &before : NULL, | |
1593 | insert_after ? &after : NULL, | |
1594 | reg, new_reg); | |
1595 | } | |
1596 | *curr_id->operand_loc[nop] = new_reg; | |
1597 | lra_process_new_insns (curr_insn, before, after, | |
3143c7ef | 1598 | "Inserting slow/invalid mem reload"); |
2d2b78a1 | 1599 | return true; |
1600 | } | |
401bd0c8 | 1601 | |
1a68e833 | 1602 | /* If the address was valid and became invalid, prefer to reload |
1603 | the memory. Typical case is when the index scale should | |
1604 | correspond the memory. */ | |
2d2b78a1 | 1605 | *curr_id->operand_loc[nop] = operand; |
483f7b77 | 1606 | /* Do not return false here as the MEM_P (reg) will be processed |
1607 | later in this function. */ | |
1a68e833 | 1608 | } |
1609 | else if (REG_P (reg) && REGNO (reg) < FIRST_PSEUDO_REGISTER) | |
c6a6cdaa | 1610 | { |
1611 | alter_subreg (curr_id->operand_loc[nop], false); | |
1612 | return true; | |
1613 | } | |
1aae95ec | 1614 | else if (CONSTANT_P (reg)) |
1615 | { | |
1616 | /* Try to simplify subreg of constant. It is usually result of | |
1617 | equivalence substitution. */ | |
1618 | if (innermode == VOIDmode | |
1619 | && (innermode = original_subreg_reg_mode[nop]) == VOIDmode) | |
1620 | innermode = curr_static_id->operand[nop].mode; | |
1621 | if ((new_reg = simplify_subreg (mode, reg, innermode, | |
1622 | SUBREG_BYTE (operand))) != NULL_RTX) | |
1623 | { | |
1624 | *curr_id->operand_loc[nop] = new_reg; | |
1625 | return true; | |
1626 | } | |
1627 | } | |
c6a6cdaa | 1628 | /* Put constant into memory when we have mixed modes. It generates |
1629 | a better code in most cases as it does not need a secondary | |
1630 | reload memory. It also prevents LRA looping when LRA is using | |
1631 | secondary reload memory again and again. */ | |
1632 | if (CONSTANT_P (reg) && CONST_POOL_OK_P (reg_mode, reg) | |
1633 | && SCALAR_INT_MODE_P (reg_mode) != SCALAR_INT_MODE_P (mode)) | |
1634 | { | |
1635 | SUBREG_REG (operand) = force_const_mem (reg_mode, reg); | |
1636 | alter_subreg (curr_id->operand_loc[nop], false); | |
1637 | return true; | |
1638 | } | |
1639 | /* Force a reload of the SUBREG_REG if this is a constant or PLUS or | |
1640 | if there may be a problem accessing OPERAND in the outer | |
1641 | mode. */ | |
1642 | if ((REG_P (reg) | |
1643 | && REGNO (reg) >= FIRST_PSEUDO_REGISTER | |
1644 | && (hard_regno = lra_get_regno_hard_regno (REGNO (reg))) >= 0 | |
1645 | /* Don't reload paradoxical subregs because we could be looping | |
1646 | having repeatedly final regno out of hard regs range. */ | |
92d2aec3 | 1647 | && (hard_regno_nregs (hard_regno, innermode) |
1648 | >= hard_regno_nregs (hard_regno, mode)) | |
1aae95ec | 1649 | && simplify_subreg_regno (hard_regno, innermode, |
ea99c7a1 | 1650 | SUBREG_BYTE (operand), mode) < 0 |
1651 | /* Don't reload subreg for matching reload. It is actually | |
1652 | valid subreg in LRA. */ | |
1653 | && ! LRA_SUBREG_P (operand)) | |
c6a6cdaa | 1654 | || CONSTANT_P (reg) || GET_CODE (reg) == PLUS || MEM_P (reg)) |
1655 | { | |
9c8190ea | 1656 | enum reg_class rclass; |
1657 | ||
6ba9136f | 1658 | if (REG_P (reg)) |
1659 | /* There is a big probability that we will get the same class | |
9c8190ea | 1660 | for the new pseudo and we will get the same insn which |
1661 | means infinite looping. So spill the new pseudo. */ | |
1662 | rclass = NO_REGS; | |
1663 | else | |
1664 | /* The class will be defined later in curr_insn_transform. */ | |
1665 | rclass | |
1666 | = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS); | |
c6a6cdaa | 1667 | |
4aa54340 | 1668 | if (get_reload_reg (curr_static_id->operand[nop].type, reg_mode, reg, |
6cadc8f7 | 1669 | rclass, TRUE, "subreg reg", &new_reg)) |
c6a6cdaa | 1670 | { |
c5334148 | 1671 | bool insert_before, insert_after; |
1f3a048a | 1672 | bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg)); |
c5334148 | 1673 | |
1674 | insert_before = (type != OP_OUT | |
9f2c0e68 | 1675 | || read_modify_subreg_p (operand)); |
c5334148 | 1676 | insert_after = (type != OP_IN); |
1677 | insert_move_for_subreg (insert_before ? &before : NULL, | |
1678 | insert_after ? &after : NULL, | |
1679 | reg, new_reg); | |
c6a6cdaa | 1680 | } |
1681 | SUBREG_REG (operand) = new_reg; | |
1682 | lra_process_new_insns (curr_insn, before, after, | |
1683 | "Inserting subreg reload"); | |
1684 | return true; | |
1685 | } | |
c5334148 | 1686 | /* Force a reload for a paradoxical subreg. For paradoxical subreg, |
1687 | IRA allocates hardreg to the inner pseudo reg according to its mode | |
1688 | instead of the outermode, so the size of the hardreg may not be enough | |
1689 | to contain the outermode operand, in that case we may need to insert | |
1690 | reload for the reg. For the following two types of paradoxical subreg, | |
1691 | we need to insert reload: | |
1692 | 1. If the op_type is OP_IN, and the hardreg could not be paired with | |
1693 | other hardreg to contain the outermode operand | |
1694 | (checked by in_hard_reg_set_p), we need to insert the reload. | |
1695 | 2. If the op_type is OP_OUT or OP_INOUT. | |
1696 | ||
1697 | Here is a paradoxical subreg example showing how the reload is generated: | |
1698 | ||
1699 | (insn 5 4 7 2 (set (reg:TI 106 [ __comp ]) | |
1700 | (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64} | |
1701 | ||
1702 | In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example | |
1703 | here, if reg107 is assigned to hardreg R15, because R15 is the last | |
1704 | hardreg, compiler cannot find another hardreg to pair with R15 to | |
1705 | contain TImode data. So we insert a TImode reload reg180 for it. | |
1706 | After reload is inserted: | |
1707 | ||
1708 | (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0) | |
1709 | (reg:DI 107 [ __comp ])) -1 | |
1710 | (insn 5 4 7 2 (set (reg:TI 106 [ __comp ]) | |
1711 | (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64} | |
1712 | ||
1713 | Two reload hard registers will be allocated to reg180 to save TImode data | |
4b6df2e8 | 1714 | in LRA_assign. |
1715 | ||
1716 | For LRA pseudos this should normally be handled by the biggest_mode | |
1717 | mechanism. However, it's possible for new uses of an LRA pseudo | |
1718 | to be introduced after we've allocated it, such as when undoing | |
1719 | inheritance, and the allocated register might not then be appropriate | |
1720 | for the new uses. */ | |
c5334148 | 1721 | else if (REG_P (reg) |
1722 | && REGNO (reg) >= FIRST_PSEUDO_REGISTER | |
1723 | && (hard_regno = lra_get_regno_hard_regno (REGNO (reg))) >= 0 | |
92d2aec3 | 1724 | && (hard_regno_nregs (hard_regno, innermode) |
1725 | < hard_regno_nregs (hard_regno, mode)) | |
c5334148 | 1726 | && (regclass = lra_get_allocno_class (REGNO (reg))) |
1727 | && (type != OP_IN | |
1728 | || !in_hard_reg_set_p (reg_class_contents[regclass], | |
4b6df2e8 | 1729 | mode, hard_regno) |
1730 | || overlaps_hard_reg_set_p (lra_no_alloc_regs, | |
1731 | mode, hard_regno))) | |
c5334148 | 1732 | { |
1733 | /* The class will be defined later in curr_insn_transform. */ | |
1734 | enum reg_class rclass | |
1735 | = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS); | |
1736 | ||
1737 | if (get_reload_reg (curr_static_id->operand[nop].type, mode, reg, | |
6cadc8f7 | 1738 | rclass, TRUE, "paradoxical subreg", &new_reg)) |
c5334148 | 1739 | { |
1740 | rtx subreg; | |
1741 | bool insert_before, insert_after; | |
1742 | ||
1743 | PUT_MODE (new_reg, mode); | |
48a08d24 | 1744 | subreg = gen_lowpart_SUBREG (innermode, new_reg); |
c5334148 | 1745 | bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg)); |
1746 | ||
1747 | insert_before = (type != OP_OUT); | |
1748 | insert_after = (type != OP_IN); | |
1749 | insert_move_for_subreg (insert_before ? &before : NULL, | |
1750 | insert_after ? &after : NULL, | |
1751 | reg, subreg); | |
1752 | } | |
1753 | SUBREG_REG (operand) = new_reg; | |
1754 | lra_process_new_insns (curr_insn, before, after, | |
1755 | "Inserting paradoxical subreg reload"); | |
1756 | return true; | |
1757 | } | |
c6a6cdaa | 1758 | return false; |
1759 | } | |
1760 | ||
1761 | /* Return TRUE if X refers for a hard register from SET. */ | |
1762 | static bool | |
1763 | uses_hard_regs_p (rtx x, HARD_REG_SET set) | |
1764 | { | |
1765 | int i, j, x_hard_regno; | |
3754d046 | 1766 | machine_mode mode; |
c6a6cdaa | 1767 | const char *fmt; |
1768 | enum rtx_code code; | |
1769 | ||
1770 | if (x == NULL_RTX) | |
1771 | return false; | |
1772 | code = GET_CODE (x); | |
1773 | mode = GET_MODE (x); | |
3a7d0e9f | 1774 | |
c6a6cdaa | 1775 | if (code == SUBREG) |
1776 | { | |
3a7d0e9f | 1777 | /* For all SUBREGs we want to check whether the full multi-register |
1778 | overlaps the set. For normal SUBREGs this means 'get_hard_regno' of | |
1779 | the inner register, for paradoxical SUBREGs this means the | |
1780 | 'get_hard_regno' of the full SUBREG and for complete SUBREGs either is | |
1781 | fine. Use the wider mode for all cases. */ | |
1782 | rtx subreg = SUBREG_REG (x); | |
081c1d32 | 1783 | mode = wider_subreg_mode (x); |
3a7d0e9f | 1784 | if (mode == GET_MODE (subreg)) |
1785 | { | |
1786 | x = subreg; | |
1787 | code = GET_CODE (x); | |
1788 | } | |
c6a6cdaa | 1789 | } |
1a8f8886 | 1790 | |
3a7d0e9f | 1791 | if (REG_P (x) || SUBREG_P (x)) |
c6a6cdaa | 1792 | { |
331a9ecc | 1793 | x_hard_regno = get_hard_regno (x, true); |
c6a6cdaa | 1794 | return (x_hard_regno >= 0 |
1795 | && overlaps_hard_reg_set_p (set, mode, x_hard_regno)); | |
1796 | } | |
1797 | if (MEM_P (x)) | |
1798 | { | |
1efe9e9d | 1799 | struct address_info ad; |
c6a6cdaa | 1800 | |
1efe9e9d | 1801 | decompose_mem_address (&ad, x); |
1802 | if (ad.base_term != NULL && uses_hard_regs_p (*ad.base_term, set)) | |
1803 | return true; | |
1804 | if (ad.index_term != NULL && uses_hard_regs_p (*ad.index_term, set)) | |
1805 | return true; | |
c6a6cdaa | 1806 | } |
1807 | fmt = GET_RTX_FORMAT (code); | |
1808 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1809 | { | |
1810 | if (fmt[i] == 'e') | |
1811 | { | |
1812 | if (uses_hard_regs_p (XEXP (x, i), set)) | |
1813 | return true; | |
1814 | } | |
1815 | else if (fmt[i] == 'E') | |
1816 | { | |
1817 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
1818 | if (uses_hard_regs_p (XVECEXP (x, i, j), set)) | |
1819 | return true; | |
1820 | } | |
1821 | } | |
1822 | return false; | |
1823 | } | |
1824 | ||
1825 | /* Return true if OP is a spilled pseudo. */ | |
1826 | static inline bool | |
1827 | spilled_pseudo_p (rtx op) | |
1828 | { | |
1829 | return (REG_P (op) | |
1830 | && REGNO (op) >= FIRST_PSEUDO_REGISTER && in_mem_p (REGNO (op))); | |
1831 | } | |
1832 | ||
1833 | /* Return true if X is a general constant. */ | |
1834 | static inline bool | |
1835 | general_constant_p (rtx x) | |
1836 | { | |
1837 | return CONSTANT_P (x) && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (x)); | |
1838 | } | |
1839 | ||
ea99c7a1 | 1840 | static bool |
1841 | reg_in_class_p (rtx reg, enum reg_class cl) | |
1842 | { | |
1843 | if (cl == NO_REGS) | |
1844 | return get_reg_class (REGNO (reg)) == NO_REGS; | |
1845 | return in_class_p (reg, cl, NULL); | |
1846 | } | |
1847 | ||
25cd984c | 1848 | /* Return true if SET of RCLASS contains no hard regs which can be |
1849 | used in MODE. */ | |
1850 | static bool | |
1851 | prohibited_class_reg_set_mode_p (enum reg_class rclass, | |
1852 | HARD_REG_SET &set, | |
582adad1 | 1853 | machine_mode mode) |
25cd984c | 1854 | { |
1855 | HARD_REG_SET temp; | |
1856 | ||
e6ea917c | 1857 | lra_assert (hard_reg_set_subset_p (reg_class_contents[rclass], set)); |
9cfad810 | 1858 | temp = set & ~lra_no_alloc_regs; |
25cd984c | 1859 | return (hard_reg_set_subset_p |
1860 | (temp, ira_prohibited_class_mode_regs[rclass][mode])); | |
1861 | } | |
1862 | ||
8afaf3bf | 1863 | |
1864 | /* Used to check validity info about small class input operands. It | |
1865 | should be incremented at start of processing an insn | |
1866 | alternative. */ | |
1867 | static unsigned int curr_small_class_check = 0; | |
1868 | ||
8df3e7a5 | 1869 | /* Update number of used inputs of class OP_CLASS for operand NOP |
1870 | of alternative NALT. Return true if we have more such class operands | |
1871 | than the number of available regs. */ | |
8afaf3bf | 1872 | static bool |
8df3e7a5 | 1873 | update_and_check_small_class_inputs (int nop, int nalt, |
1874 | enum reg_class op_class) | |
8afaf3bf | 1875 | { |
1876 | static unsigned int small_class_check[LIM_REG_CLASSES]; | |
1877 | static int small_class_input_nums[LIM_REG_CLASSES]; | |
1878 | ||
1879 | if (SMALL_REGISTER_CLASS_P (op_class) | |
1880 | /* We are interesting in classes became small because of fixing | |
1881 | some hard regs, e.g. by an user through GCC options. */ | |
1882 | && hard_reg_set_intersect_p (reg_class_contents[op_class], | |
1883 | ira_no_alloc_regs) | |
1884 | && (curr_static_id->operand[nop].type != OP_OUT | |
8df3e7a5 | 1885 | || TEST_BIT (curr_static_id->operand[nop].early_clobber_alts, nalt))) |
8afaf3bf | 1886 | { |
1887 | if (small_class_check[op_class] == curr_small_class_check) | |
1888 | small_class_input_nums[op_class]++; | |
1889 | else | |
1890 | { | |
1891 | small_class_check[op_class] = curr_small_class_check; | |
1892 | small_class_input_nums[op_class] = 1; | |
1893 | } | |
1894 | if (small_class_input_nums[op_class] > ira_class_hard_regs_num[op_class]) | |
1895 | return true; | |
1896 | } | |
1897 | return false; | |
1898 | } | |
1899 | ||
c6a6cdaa | 1900 | /* Major function to choose the current insn alternative and what |
1901 | operands should be reloaded and how. If ONLY_ALTERNATIVE is not | |
1902 | negative we should consider only this alternative. Return false if | |
f4d3c071 | 1903 | we cannot choose the alternative or find how to reload the |
c6a6cdaa | 1904 | operands. */ |
1905 | static bool | |
1906 | process_alt_operands (int only_alternative) | |
1907 | { | |
1908 | bool ok_p = false; | |
273c330a | 1909 | int nop, overall, nalt; |
c6a6cdaa | 1910 | int n_alternatives = curr_static_id->n_alternatives; |
1911 | int n_operands = curr_static_id->n_operands; | |
1912 | /* LOSERS counts the operands that don't fit this alternative and | |
1913 | would require loading. */ | |
1914 | int losers; | |
eb70a065 | 1915 | int addr_losers; |
c6a6cdaa | 1916 | /* REJECT is a count of how undesirable this alternative says it is |
1917 | if any reloading is required. If the alternative matches exactly | |
1918 | then REJECT is ignored, but otherwise it gets this much counted | |
1919 | against it in addition to the reloading needed. */ | |
1920 | int reject; | |
eb70a065 | 1921 | /* This is defined by '!' or '?' alternative constraint and added to |
1922 | reject. But in some cases it can be ignored. */ | |
1923 | int static_reject; | |
ed6272f7 | 1924 | int op_reject; |
c6a6cdaa | 1925 | /* The number of elements in the following array. */ |
1926 | int early_clobbered_regs_num; | |
1927 | /* Numbers of operands which are early clobber registers. */ | |
1928 | int early_clobbered_nops[MAX_RECOG_OPERANDS]; | |
1929 | enum reg_class curr_alt[MAX_RECOG_OPERANDS]; | |
1930 | HARD_REG_SET curr_alt_set[MAX_RECOG_OPERANDS]; | |
1931 | bool curr_alt_match_win[MAX_RECOG_OPERANDS]; | |
1932 | bool curr_alt_win[MAX_RECOG_OPERANDS]; | |
1933 | bool curr_alt_offmemok[MAX_RECOG_OPERANDS]; | |
1934 | int curr_alt_matches[MAX_RECOG_OPERANDS]; | |
1935 | /* The number of elements in the following array. */ | |
1936 | int curr_alt_dont_inherit_ops_num; | |
1937 | /* Numbers of operands whose reload pseudos should not be inherited. */ | |
1938 | int curr_alt_dont_inherit_ops[MAX_RECOG_OPERANDS]; | |
1939 | rtx op; | |
1940 | /* The register when the operand is a subreg of register, otherwise the | |
1941 | operand itself. */ | |
1942 | rtx no_subreg_reg_operand[MAX_RECOG_OPERANDS]; | |
1943 | /* The register if the operand is a register or subreg of register, | |
1944 | otherwise NULL. */ | |
1945 | rtx operand_reg[MAX_RECOG_OPERANDS]; | |
1946 | int hard_regno[MAX_RECOG_OPERANDS]; | |
3754d046 | 1947 | machine_mode biggest_mode[MAX_RECOG_OPERANDS]; |
c6a6cdaa | 1948 | int reload_nregs, reload_sum; |
1949 | bool costly_p; | |
1950 | enum reg_class cl; | |
1951 | ||
1952 | /* Calculate some data common for all alternatives to speed up the | |
1953 | function. */ | |
1954 | for (nop = 0; nop < n_operands; nop++) | |
1955 | { | |
0244be31 | 1956 | rtx reg; |
1957 | ||
c6a6cdaa | 1958 | op = no_subreg_reg_operand[nop] = *curr_id->operand_loc[nop]; |
1959 | /* The real hard regno of the operand after the allocation. */ | |
331a9ecc | 1960 | hard_regno[nop] = get_hard_regno (op, true); |
1a8f8886 | 1961 | |
0244be31 | 1962 | operand_reg[nop] = reg = op; |
1963 | biggest_mode[nop] = GET_MODE (op); | |
1964 | if (GET_CODE (op) == SUBREG) | |
c6a6cdaa | 1965 | { |
081c1d32 | 1966 | biggest_mode[nop] = wider_subreg_mode (op); |
0244be31 | 1967 | operand_reg[nop] = reg = SUBREG_REG (op); |
c6a6cdaa | 1968 | } |
0244be31 | 1969 | if (! REG_P (reg)) |
c6a6cdaa | 1970 | operand_reg[nop] = NULL_RTX; |
0244be31 | 1971 | else if (REGNO (reg) >= FIRST_PSEUDO_REGISTER |
1972 | || ((int) REGNO (reg) | |
1973 | == lra_get_elimination_hard_regno (REGNO (reg)))) | |
1974 | no_subreg_reg_operand[nop] = reg; | |
1975 | else | |
1976 | operand_reg[nop] = no_subreg_reg_operand[nop] | |
1977 | /* Just use natural mode for elimination result. It should | |
1978 | be enough for extra constraints hooks. */ | |
1979 | = regno_reg_rtx[hard_regno[nop]]; | |
c6a6cdaa | 1980 | } |
1981 | ||
1982 | /* The constraints are made of several alternatives. Each operand's | |
1983 | constraint looks like foo,bar,... with commas separating the | |
1984 | alternatives. The first alternatives for all operands go | |
1985 | together, the second alternatives go together, etc. | |
1986 | ||
1987 | First loop over alternatives. */ | |
e1a797ad | 1988 | alternative_mask preferred = curr_id->preferred_alternatives; |
d2b854bc | 1989 | if (only_alternative >= 0) |
e1a797ad | 1990 | preferred &= ALTERNATIVE_BIT (only_alternative); |
d2b854bc | 1991 | |
c6a6cdaa | 1992 | for (nalt = 0; nalt < n_alternatives; nalt++) |
1993 | { | |
1994 | /* Loop over operands for one constraint alternative. */ | |
e1a797ad | 1995 | if (!TEST_BIT (preferred, nalt)) |
c6a6cdaa | 1996 | continue; |
1997 | ||
3dfcf76a | 1998 | bool matching_early_clobber[MAX_RECOG_OPERANDS]; |
8afaf3bf | 1999 | curr_small_class_check++; |
eb70a065 | 2000 | overall = losers = addr_losers = 0; |
2001 | static_reject = reject = reload_nregs = reload_sum = 0; | |
c6a6cdaa | 2002 | for (nop = 0; nop < n_operands; nop++) |
34575461 | 2003 | { |
2004 | int inc = (curr_static_id | |
2005 | ->operand_alternative[nalt * n_operands + nop].reject); | |
2006 | if (lra_dump_file != NULL && inc != 0) | |
2007 | fprintf (lra_dump_file, | |
2008 | " Staticly defined alt reject+=%d\n", inc); | |
eb70a065 | 2009 | static_reject += inc; |
3dfcf76a | 2010 | matching_early_clobber[nop] = 0; |
34575461 | 2011 | } |
eb70a065 | 2012 | reject += static_reject; |
c6a6cdaa | 2013 | early_clobbered_regs_num = 0; |
2014 | ||
2015 | for (nop = 0; nop < n_operands; nop++) | |
2016 | { | |
2017 | const char *p; | |
2018 | char *end; | |
2019 | int len, c, m, i, opalt_num, this_alternative_matches; | |
2020 | bool win, did_match, offmemok, early_clobber_p; | |
2021 | /* false => this operand can be reloaded somehow for this | |
2022 | alternative. */ | |
2023 | bool badop; | |
2024 | /* true => this operand can be reloaded if the alternative | |
2025 | allows regs. */ | |
2026 | bool winreg; | |
2027 | /* True if a constant forced into memory would be OK for | |
2028 | this operand. */ | |
2029 | bool constmemok; | |
2030 | enum reg_class this_alternative, this_costly_alternative; | |
2031 | HARD_REG_SET this_alternative_set, this_costly_alternative_set; | |
2032 | bool this_alternative_match_win, this_alternative_win; | |
2033 | bool this_alternative_offmemok; | |
2b1732ad | 2034 | bool scratch_p; |
3754d046 | 2035 | machine_mode mode; |
79bc09fb | 2036 | enum constraint_num cn; |
c6a6cdaa | 2037 | |
2038 | opalt_num = nalt * n_operands + nop; | |
2039 | if (curr_static_id->operand_alternative[opalt_num].anything_ok) | |
2040 | { | |
2041 | /* Fast track for no constraints at all. */ | |
2042 | curr_alt[nop] = NO_REGS; | |
2043 | CLEAR_HARD_REG_SET (curr_alt_set[nop]); | |
2044 | curr_alt_win[nop] = true; | |
2045 | curr_alt_match_win[nop] = false; | |
2046 | curr_alt_offmemok[nop] = false; | |
2047 | curr_alt_matches[nop] = -1; | |
2048 | continue; | |
2049 | } | |
1a8f8886 | 2050 | |
c6a6cdaa | 2051 | op = no_subreg_reg_operand[nop]; |
2052 | mode = curr_operand_mode[nop]; | |
2053 | ||
2054 | win = did_match = winreg = offmemok = constmemok = false; | |
2055 | badop = true; | |
1a8f8886 | 2056 | |
c6a6cdaa | 2057 | early_clobber_p = false; |
2058 | p = curr_static_id->operand_alternative[opalt_num].constraint; | |
1a8f8886 | 2059 | |
c6a6cdaa | 2060 | this_costly_alternative = this_alternative = NO_REGS; |
2061 | /* We update set of possible hard regs besides its class | |
2062 | because reg class might be inaccurate. For example, | |
2063 | union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM | |
2064 | is translated in HI_REGS because classes are merged by | |
2065 | pairs and there is no accurate intermediate class. */ | |
2066 | CLEAR_HARD_REG_SET (this_alternative_set); | |
2067 | CLEAR_HARD_REG_SET (this_costly_alternative_set); | |
2068 | this_alternative_win = false; | |
2069 | this_alternative_match_win = false; | |
2070 | this_alternative_offmemok = false; | |
2071 | this_alternative_matches = -1; | |
1a8f8886 | 2072 | |
c6a6cdaa | 2073 | /* An empty constraint should be excluded by the fast |
2074 | track. */ | |
2075 | lra_assert (*p != 0 && *p != ','); | |
1a8f8886 | 2076 | |
ed6272f7 | 2077 | op_reject = 0; |
c6a6cdaa | 2078 | /* Scan this alternative's specs for this operand; set WIN |
2079 | if the operand fits any letter in this alternative. | |
2080 | Otherwise, clear BADOP if this operand could fit some | |
2081 | letter after reloads, or set WINREG if this operand could | |
2082 | fit after reloads provided the constraint allows some | |
2083 | registers. */ | |
2084 | costly_p = false; | |
2085 | do | |
2086 | { | |
2087 | switch ((c = *p, len = CONSTRAINT_LEN (c, p)), c) | |
2088 | { | |
2089 | case '\0': | |
2090 | len = 0; | |
2091 | break; | |
2092 | case ',': | |
2093 | c = '\0'; | |
2094 | break; | |
1a8f8886 | 2095 | |
c6a6cdaa | 2096 | case '&': |
2097 | early_clobber_p = true; | |
2098 | break; | |
1a8f8886 | 2099 | |
ed6272f7 | 2100 | case '$': |
2101 | op_reject += LRA_MAX_REJECT; | |
2102 | break; | |
2103 | case '^': | |
2104 | op_reject += LRA_LOSER_COST_FACTOR; | |
2105 | break; | |
2106 | ||
c6a6cdaa | 2107 | case '#': |
2108 | /* Ignore rest of this alternative. */ | |
2109 | c = '\0'; | |
2110 | break; | |
1a8f8886 | 2111 | |
c6a6cdaa | 2112 | case '0': case '1': case '2': case '3': case '4': |
2113 | case '5': case '6': case '7': case '8': case '9': | |
2114 | { | |
2115 | int m_hregno; | |
2116 | bool match_p; | |
1a8f8886 | 2117 | |
c6a6cdaa | 2118 | m = strtoul (p, &end, 10); |
2119 | p = end; | |
2120 | len = 0; | |
2121 | lra_assert (nop > m); | |
1a8f8886 | 2122 | |
e23bf764 | 2123 | /* Reject matches if we don't know which operand is |
2124 | bigger. This situation would arguably be a bug in | |
2125 | an .md pattern, but could also occur in a user asm. */ | |
2126 | if (!ordered_p (GET_MODE_SIZE (biggest_mode[m]), | |
2127 | GET_MODE_SIZE (biggest_mode[nop]))) | |
2128 | break; | |
2129 | ||
529fdbd1 | 2130 | /* Don't match wrong asm insn operands for proper |
2131 | diagnostic later. */ | |
2132 | if (INSN_CODE (curr_insn) < 0 | |
2133 | && (curr_operand_mode[m] == BLKmode | |
2134 | || curr_operand_mode[nop] == BLKmode) | |
2135 | && curr_operand_mode[m] != curr_operand_mode[nop]) | |
2136 | break; | |
2137 | ||
331a9ecc | 2138 | m_hregno = get_hard_regno (*curr_id->operand_loc[m], false); |
c6a6cdaa | 2139 | /* We are supposed to match a previous operand. |
2140 | If we do, we win if that one did. If we do | |
2141 | not, count both of the operands as losers. | |
2142 | (This is too conservative, since most of the | |
2143 | time only a single reload insn will be needed | |
2144 | to make the two operands win. As a result, | |
2145 | this alternative may be rejected when it is | |
2146 | actually desirable.) */ | |
2147 | match_p = false; | |
2148 | if (operands_match_p (*curr_id->operand_loc[nop], | |
2149 | *curr_id->operand_loc[m], m_hregno)) | |
2150 | { | |
2151 | /* We should reject matching of an early | |
2152 | clobber operand if the matching operand is | |
2153 | not dying in the insn. */ | |
8df3e7a5 | 2154 | if (!TEST_BIT (curr_static_id->operand[m] |
2155 | .early_clobber_alts, nalt) | |
c6a6cdaa | 2156 | || operand_reg[nop] == NULL_RTX |
2157 | || (find_regno_note (curr_insn, REG_DEAD, | |
89c2edcf | 2158 | REGNO (op)) |
2159 | || REGNO (op) == REGNO (operand_reg[m]))) | |
c6a6cdaa | 2160 | match_p = true; |
2161 | } | |
2162 | if (match_p) | |
2163 | { | |
2164 | /* If we are matching a non-offsettable | |
2165 | address where an offsettable address was | |
2166 | expected, then we must reject this | |
2167 | combination, because we can't reload | |
2168 | it. */ | |
2169 | if (curr_alt_offmemok[m] | |
2170 | && MEM_P (*curr_id->operand_loc[m]) | |
2171 | && curr_alt[m] == NO_REGS && ! curr_alt_win[m]) | |
2172 | continue; | |
c6a6cdaa | 2173 | } |
2174 | else | |
2175 | { | |
85d69302 | 2176 | /* If the operands do not match and one |
2177 | operand is INOUT, we can not match them. | |
2178 | Try other possibilities, e.g. other | |
2179 | alternatives or commutative operand | |
2180 | exchange. */ | |
2181 | if (curr_static_id->operand[nop].type == OP_INOUT | |
2182 | || curr_static_id->operand[m].type == OP_INOUT) | |
2183 | break; | |
b782636f | 2184 | /* Operands don't match. If the operands are |
c2930418 | 2185 | different user defined explicit hard |
2186 | registers, then we cannot make them match | |
2187 | when one is early clobber operand. */ | |
b782636f | 2188 | if ((REG_P (*curr_id->operand_loc[nop]) |
2189 | || SUBREG_P (*curr_id->operand_loc[nop])) | |
2190 | && (REG_P (*curr_id->operand_loc[m]) | |
2191 | || SUBREG_P (*curr_id->operand_loc[m]))) | |
2192 | { | |
2193 | rtx nop_reg = *curr_id->operand_loc[nop]; | |
2194 | if (SUBREG_P (nop_reg)) | |
2195 | nop_reg = SUBREG_REG (nop_reg); | |
2196 | rtx m_reg = *curr_id->operand_loc[m]; | |
2197 | if (SUBREG_P (m_reg)) | |
2198 | m_reg = SUBREG_REG (m_reg); | |
2199 | ||
2200 | if (REG_P (nop_reg) | |
2201 | && HARD_REGISTER_P (nop_reg) | |
2202 | && REG_USERVAR_P (nop_reg) | |
2203 | && REG_P (m_reg) | |
2204 | && HARD_REGISTER_P (m_reg) | |
2205 | && REG_USERVAR_P (m_reg)) | |
c2930418 | 2206 | { |
2207 | int i; | |
2208 | ||
2209 | for (i = 0; i < early_clobbered_regs_num; i++) | |
2210 | if (m == early_clobbered_nops[i]) | |
2211 | break; | |
2212 | if (i < early_clobbered_regs_num | |
2213 | || early_clobber_p) | |
2214 | break; | |
2215 | } | |
b782636f | 2216 | } |
b782636f | 2217 | /* Both operands must allow a reload register, |
2218 | otherwise we cannot make them match. */ | |
c6a6cdaa | 2219 | if (curr_alt[m] == NO_REGS) |
2220 | break; | |
2221 | /* Retroactively mark the operand we had to | |
2222 | match as a loser, if it wasn't already and | |
2223 | it wasn't matched to a register constraint | |
2224 | (e.g it might be matched by memory). */ | |
2225 | if (curr_alt_win[m] | |
2226 | && (operand_reg[m] == NULL_RTX | |
2227 | || hard_regno[m] < 0)) | |
2228 | { | |
2229 | losers++; | |
2230 | reload_nregs | |
2231 | += (ira_reg_class_max_nregs[curr_alt[m]] | |
2232 | [GET_MODE (*curr_id->operand_loc[m])]); | |
2233 | } | |
1a8f8886 | 2234 | |
53f1eb5d | 2235 | /* Prefer matching earlyclobber alternative as |
2236 | it results in less hard regs required for | |
2237 | the insn than a non-matching earlyclobber | |
2238 | alternative. */ | |
8df3e7a5 | 2239 | if (TEST_BIT (curr_static_id->operand[m] |
2240 | .early_clobber_alts, nalt)) | |
53f1eb5d | 2241 | { |
2242 | if (lra_dump_file != NULL) | |
2243 | fprintf | |
2244 | (lra_dump_file, | |
2245 | " %d Matching earlyclobber alt:" | |
2246 | " reject--\n", | |
2247 | nop); | |
3dfcf76a | 2248 | if (!matching_early_clobber[m]) |
2249 | { | |
2250 | reject--; | |
2251 | matching_early_clobber[m] = 1; | |
2252 | } | |
53f1eb5d | 2253 | } |
2254 | /* Otherwise we prefer no matching | |
2255 | alternatives because it gives more freedom | |
2256 | in RA. */ | |
2257 | else if (operand_reg[nop] == NULL_RTX | |
2258 | || (find_regno_note (curr_insn, REG_DEAD, | |
2259 | REGNO (operand_reg[nop])) | |
2260 | == NULL_RTX)) | |
34575461 | 2261 | { |
2262 | if (lra_dump_file != NULL) | |
2263 | fprintf | |
2264 | (lra_dump_file, | |
2265 | " %d Matching alt: reject+=2\n", | |
2266 | nop); | |
2267 | reject += 2; | |
2268 | } | |
c6a6cdaa | 2269 | } |
2270 | /* If we have to reload this operand and some | |
2271 | previous operand also had to match the same | |
2272 | thing as this operand, we don't know how to do | |
2273 | that. */ | |
2274 | if (!match_p || !curr_alt_win[m]) | |
2275 | { | |
2276 | for (i = 0; i < nop; i++) | |
2277 | if (curr_alt_matches[i] == m) | |
2278 | break; | |
2279 | if (i < nop) | |
2280 | break; | |
2281 | } | |
2282 | else | |
2283 | did_match = true; | |
1a8f8886 | 2284 | |
7ceb795f | 2285 | this_alternative_matches = m; |
c6a6cdaa | 2286 | /* This can be fixed with reloads if the operand |
2287 | we are supposed to match can be fixed with | |
2288 | reloads. */ | |
2289 | badop = false; | |
2290 | this_alternative = curr_alt[m]; | |
de7358ed | 2291 | this_alternative_set = curr_alt_set[m]; |
4b3aba76 | 2292 | winreg = this_alternative != NO_REGS; |
c6a6cdaa | 2293 | break; |
2294 | } | |
1a8f8886 | 2295 | |
c6a6cdaa | 2296 | case 'g': |
2297 | if (MEM_P (op) | |
2298 | || general_constant_p (op) | |
2299 | || spilled_pseudo_p (op)) | |
2300 | win = true; | |
79bc09fb | 2301 | cl = GENERAL_REGS; |
c6a6cdaa | 2302 | goto reg; |
1a8f8886 | 2303 | |
c6a6cdaa | 2304 | default: |
79bc09fb | 2305 | cn = lookup_constraint (p); |
2306 | switch (get_constraint_type (cn)) | |
c6a6cdaa | 2307 | { |
79bc09fb | 2308 | case CT_REGISTER: |
2309 | cl = reg_class_for_constraint (cn); | |
2310 | if (cl != NO_REGS) | |
2311 | goto reg; | |
2312 | break; | |
1a8f8886 | 2313 | |
4e67d0bf | 2314 | case CT_CONST_INT: |
2315 | if (CONST_INT_P (op) | |
2316 | && insn_const_int_ok_for_constraint (INTVAL (op), cn)) | |
2317 | win = true; | |
2318 | break; | |
2319 | ||
79bc09fb | 2320 | case CT_MEMORY: |
2321 | if (MEM_P (op) | |
2322 | && satisfies_memory_constraint_p (op, cn)) | |
2323 | win = true; | |
2324 | else if (spilled_pseudo_p (op)) | |
2325 | win = true; | |
2326 | ||
2327 | /* If we didn't already win, we can reload constants | |
2328 | via force_const_mem or put the pseudo value into | |
2329 | memory, or make other memory by reloading the | |
2330 | address like for 'o'. */ | |
2331 | if (CONST_POOL_OK_P (mode, op) | |
003000a4 | 2332 | || MEM_P (op) || REG_P (op) |
2333 | /* We can restore the equiv insn by a | |
2334 | reload. */ | |
2335 | || equiv_substition_p[nop]) | |
79bc09fb | 2336 | badop = false; |
2337 | constmemok = true; | |
2338 | offmemok = true; | |
2339 | break; | |
2340 | ||
2341 | case CT_ADDRESS: | |
afca8a73 | 2342 | /* An asm operand with an address constraint |
2343 | that doesn't satisfy address_operand has | |
2344 | is_address cleared, so that we don't try to | |
2345 | make a non-address fit. */ | |
2346 | if (!curr_static_id->operand[nop].is_address) | |
2347 | break; | |
79bc09fb | 2348 | /* If we didn't already win, we can reload the address |
2349 | into a base register. */ | |
2350 | if (satisfies_address_constraint_p (op, cn)) | |
2351 | win = true; | |
2352 | cl = base_reg_class (VOIDmode, ADDR_SPACE_GENERIC, | |
2353 | ADDRESS, SCRATCH); | |
2354 | badop = false; | |
2355 | goto reg; | |
2356 | ||
2357 | case CT_FIXED_FORM: | |
2358 | if (constraint_satisfied_p (op, cn)) | |
c6a6cdaa | 2359 | win = true; |
c6a6cdaa | 2360 | break; |
6b3b345a | 2361 | |
2362 | case CT_SPECIAL_MEMORY: | |
2363 | if (MEM_P (op) | |
2364 | && satisfies_memory_constraint_p (op, cn)) | |
2365 | win = true; | |
2366 | else if (spilled_pseudo_p (op)) | |
2367 | win = true; | |
2368 | break; | |
c6a6cdaa | 2369 | } |
79bc09fb | 2370 | break; |
1a8f8886 | 2371 | |
79bc09fb | 2372 | reg: |
fcf9e045 | 2373 | if (mode == BLKmode) |
2374 | break; | |
c6a6cdaa | 2375 | this_alternative = reg_class_subunion[this_alternative][cl]; |
247f191e | 2376 | this_alternative_set |= reg_class_contents[cl]; |
c6a6cdaa | 2377 | if (costly_p) |
2378 | { | |
2379 | this_costly_alternative | |
2380 | = reg_class_subunion[this_costly_alternative][cl]; | |
247f191e | 2381 | this_costly_alternative_set |= reg_class_contents[cl]; |
c6a6cdaa | 2382 | } |
c6a6cdaa | 2383 | winreg = true; |
2384 | if (REG_P (op)) | |
2385 | { | |
2386 | if (hard_regno[nop] >= 0 | |
2387 | && in_hard_reg_set_p (this_alternative_set, | |
2388 | mode, hard_regno[nop])) | |
2389 | win = true; | |
2390 | else if (hard_regno[nop] < 0 | |
2391 | && in_class_p (op, this_alternative, NULL)) | |
2392 | win = true; | |
2393 | } | |
2394 | break; | |
2395 | } | |
2396 | if (c != ' ' && c != '\t') | |
2397 | costly_p = c == '*'; | |
2398 | } | |
2399 | while ((p += len), c); | |
1a8f8886 | 2400 | |
2b1732ad | 2401 | scratch_p = (operand_reg[nop] != NULL_RTX |
2402 | && lra_former_scratch_p (REGNO (operand_reg[nop]))); | |
c6a6cdaa | 2403 | /* Record which operands fit this alternative. */ |
2404 | if (win) | |
2405 | { | |
2406 | this_alternative_win = true; | |
2407 | if (operand_reg[nop] != NULL_RTX) | |
2408 | { | |
2409 | if (hard_regno[nop] >= 0) | |
2410 | { | |
2411 | if (in_hard_reg_set_p (this_costly_alternative_set, | |
2412 | mode, hard_regno[nop])) | |
34575461 | 2413 | { |
2414 | if (lra_dump_file != NULL) | |
2415 | fprintf (lra_dump_file, | |
2416 | " %d Costly set: reject++\n", | |
2417 | nop); | |
2418 | reject++; | |
2419 | } | |
c6a6cdaa | 2420 | } |
2421 | else | |
2422 | { | |
2b1732ad | 2423 | /* Prefer won reg to spilled pseudo under other |
2424 | equal conditions for possibe inheritance. */ | |
2425 | if (! scratch_p) | |
2426 | { | |
2427 | if (lra_dump_file != NULL) | |
2428 | fprintf | |
2429 | (lra_dump_file, | |
2430 | " %d Non pseudo reload: reject++\n", | |
2431 | nop); | |
2432 | reject++; | |
2433 | } | |
c6a6cdaa | 2434 | if (in_class_p (operand_reg[nop], |
2435 | this_costly_alternative, NULL)) | |
34575461 | 2436 | { |
2437 | if (lra_dump_file != NULL) | |
2438 | fprintf | |
2439 | (lra_dump_file, | |
2440 | " %d Non pseudo costly reload:" | |
2441 | " reject++\n", | |
2442 | nop); | |
2443 | reject++; | |
2444 | } | |
c6a6cdaa | 2445 | } |
67cf9b55 | 2446 | /* We simulate the behavior of old reload here. |
c6a6cdaa | 2447 | Although scratches need hard registers and it |
2448 | might result in spilling other pseudos, no reload | |
2449 | insns are generated for the scratches. So it | |
2450 | might cost something but probably less than old | |
2451 | reload pass believes. */ | |
2b1732ad | 2452 | if (scratch_p) |
34575461 | 2453 | { |
2454 | if (lra_dump_file != NULL) | |
2455 | fprintf (lra_dump_file, | |
2b1732ad | 2456 | " %d Scratch win: reject+=2\n", |
34575461 | 2457 | nop); |
2b1732ad | 2458 | reject += 2; |
34575461 | 2459 | } |
c6a6cdaa | 2460 | } |
2461 | } | |
2462 | else if (did_match) | |
2463 | this_alternative_match_win = true; | |
2464 | else | |
2465 | { | |
2466 | int const_to_mem = 0; | |
2467 | bool no_regs_p; | |
2468 | ||
ed6272f7 | 2469 | reject += op_reject; |
3b3a5e5f | 2470 | /* Never do output reload of stack pointer. It makes |
2471 | impossible to do elimination when SP is changed in | |
2472 | RTL. */ | |
2473 | if (op == stack_pointer_rtx && ! frame_pointer_needed | |
2474 | && curr_static_id->operand[nop].type != OP_IN) | |
2475 | goto fail; | |
2476 | ||
aa46b107 | 2477 | /* If this alternative asks for a specific reg class, see if there |
2478 | is at least one allocatable register in that class. */ | |
c6a6cdaa | 2479 | no_regs_p |
2480 | = (this_alternative == NO_REGS | |
2481 | || (hard_reg_set_subset_p | |
2482 | (reg_class_contents[this_alternative], | |
2483 | lra_no_alloc_regs))); | |
aa46b107 | 2484 | |
2485 | /* For asms, verify that the class for this alternative is possible | |
2486 | for the mode that is specified. */ | |
1524bcdc | 2487 | if (!no_regs_p && INSN_CODE (curr_insn) < 0) |
aa46b107 | 2488 | { |
2489 | int i; | |
2490 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
b395382f | 2491 | if (targetm.hard_regno_mode_ok (i, mode) |
b3d446cb | 2492 | && in_hard_reg_set_p (reg_class_contents[this_alternative], |
2493 | mode, i)) | |
aa46b107 | 2494 | break; |
2495 | if (i == FIRST_PSEUDO_REGISTER) | |
2496 | winreg = false; | |
2497 | } | |
2498 | ||
c6a6cdaa | 2499 | /* If this operand accepts a register, and if the |
2500 | register class has at least one allocatable register, | |
2501 | then this operand can be reloaded. */ | |
2502 | if (winreg && !no_regs_p) | |
2503 | badop = false; | |
1a8f8886 | 2504 | |
c6a6cdaa | 2505 | if (badop) |
b3d446cb | 2506 | { |
2507 | if (lra_dump_file != NULL) | |
2508 | fprintf (lra_dump_file, | |
2509 | " alt=%d: Bad operand -- refuse\n", | |
2510 | nalt); | |
2511 | goto fail; | |
2512 | } | |
c6a6cdaa | 2513 | |
a2ebcb84 | 2514 | if (this_alternative != NO_REGS) |
2515 | { | |
9cfad810 | 2516 | HARD_REG_SET available_regs |
2517 | = (reg_class_contents[this_alternative] | |
2518 | & ~((ira_prohibited_class_mode_regs | |
2519 | [this_alternative][mode]) | |
2520 | | lra_no_alloc_regs)); | |
a2ebcb84 | 2521 | if (hard_reg_set_empty_p (available_regs)) |
2522 | { | |
2523 | /* There are no hard regs holding a value of given | |
2524 | mode. */ | |
2525 | if (offmemok) | |
2526 | { | |
2527 | this_alternative = NO_REGS; | |
2528 | if (lra_dump_file != NULL) | |
2529 | fprintf (lra_dump_file, | |
2530 | " %d Using memory because of" | |
2531 | " a bad mode: reject+=2\n", | |
2532 | nop); | |
2533 | reject += 2; | |
2534 | } | |
2535 | else | |
2536 | { | |
2537 | if (lra_dump_file != NULL) | |
2538 | fprintf (lra_dump_file, | |
2539 | " alt=%d: Wrong mode -- refuse\n", | |
2540 | nalt); | |
2541 | goto fail; | |
2542 | } | |
2543 | } | |
2544 | } | |
2545 | ||
77a00b11 | 2546 | /* If not assigned pseudo has a class which a subset of |
2547 | required reg class, it is a less costly alternative | |
2548 | as the pseudo still can get a hard reg of necessary | |
2549 | class. */ | |
2550 | if (! no_regs_p && REG_P (op) && hard_regno[nop] < 0 | |
2551 | && (cl = get_reg_class (REGNO (op))) != NO_REGS | |
2552 | && ira_class_subset_p[this_alternative][cl]) | |
2553 | { | |
2554 | if (lra_dump_file != NULL) | |
2555 | fprintf | |
2556 | (lra_dump_file, | |
2557 | " %d Super set class reg: reject-=3\n", nop); | |
2558 | reject -= 3; | |
2559 | } | |
2560 | ||
c6a6cdaa | 2561 | this_alternative_offmemok = offmemok; |
2562 | if (this_costly_alternative != NO_REGS) | |
34575461 | 2563 | { |
2564 | if (lra_dump_file != NULL) | |
2565 | fprintf (lra_dump_file, | |
2566 | " %d Costly loser: reject++\n", nop); | |
2567 | reject++; | |
2568 | } | |
c6a6cdaa | 2569 | /* If the operand is dying, has a matching constraint, |
2570 | and satisfies constraints of the matched operand | |
53f1eb5d | 2571 | which failed to satisfy the own constraints, most probably |
4f428208 | 2572 | the reload for this operand will be gone. */ |
2573 | if (this_alternative_matches >= 0 | |
2574 | && !curr_alt_win[this_alternative_matches] | |
2575 | && REG_P (op) | |
2576 | && find_regno_note (curr_insn, REG_DEAD, REGNO (op)) | |
2577 | && (hard_regno[nop] >= 0 | |
2578 | ? in_hard_reg_set_p (this_alternative_set, | |
2579 | mode, hard_regno[nop]) | |
2580 | : in_class_p (op, this_alternative, NULL))) | |
2581 | { | |
2582 | if (lra_dump_file != NULL) | |
2583 | fprintf | |
2584 | (lra_dump_file, | |
2585 | " %d Dying matched operand reload: reject++\n", | |
2586 | nop); | |
2587 | reject++; | |
2588 | } | |
2589 | else | |
2e620dc7 | 2590 | { |
92dfb77d | 2591 | /* Strict_low_part requires to reload the register |
2592 | not the sub-register. In this case we should | |
2593 | check that a final reload hard reg can hold the | |
2594 | value mode. */ | |
2e620dc7 | 2595 | if (curr_static_id->operand[nop].strict_low |
2596 | && REG_P (op) | |
2597 | && hard_regno[nop] < 0 | |
2598 | && GET_CODE (*curr_id->operand_loc[nop]) == SUBREG | |
2599 | && ira_class_hard_regs_num[this_alternative] > 0 | |
b395382f | 2600 | && (!targetm.hard_regno_mode_ok |
2601 | (ira_class_hard_regs[this_alternative][0], | |
2602 | GET_MODE (*curr_id->operand_loc[nop])))) | |
b3d446cb | 2603 | { |
2604 | if (lra_dump_file != NULL) | |
2605 | fprintf | |
2606 | (lra_dump_file, | |
2607 | " alt=%d: Strict low subreg reload -- refuse\n", | |
2608 | nalt); | |
2609 | goto fail; | |
2610 | } | |
2e620dc7 | 2611 | losers++; |
2612 | } | |
c6a6cdaa | 2613 | if (operand_reg[nop] != NULL_RTX |
2614 | /* Output operands and matched input operands are | |
2615 | not inherited. The following conditions do not | |
2616 | exactly describe the previous statement but they | |
2617 | are pretty close. */ | |
2618 | && curr_static_id->operand[nop].type != OP_OUT | |
2619 | && (this_alternative_matches < 0 | |
2620 | || curr_static_id->operand[nop].type != OP_IN)) | |
2621 | { | |
2622 | int last_reload = (lra_reg_info[ORIGINAL_REGNO | |
2623 | (operand_reg[nop])] | |
2624 | .last_reload); | |
2625 | ||
92b64c52 | 2626 | /* The value of reload_sum has sense only if we |
2627 | process insns in their order. It happens only on | |
2628 | the first constraints sub-pass when we do most of | |
2629 | reload work. */ | |
2630 | if (lra_constraint_iter == 1 && last_reload > bb_reload_num) | |
c6a6cdaa | 2631 | reload_sum += last_reload - bb_reload_num; |
2632 | } | |
2633 | /* If this is a constant that is reloaded into the | |
2634 | desired class by copying it to memory first, count | |
2635 | that as another reload. This is consistent with | |
2636 | other code and is required to avoid choosing another | |
2637 | alternative when the constant is moved into memory. | |
2638 | Note that the test here is precisely the same as in | |
2639 | the code below that calls force_const_mem. */ | |
2640 | if (CONST_POOL_OK_P (mode, op) | |
2641 | && ((targetm.preferred_reload_class | |
2642 | (op, this_alternative) == NO_REGS) | |
2643 | || no_input_reloads_p)) | |
2644 | { | |
2645 | const_to_mem = 1; | |
2646 | if (! no_regs_p) | |
2647 | losers++; | |
2648 | } | |
1a8f8886 | 2649 | |
c6a6cdaa | 2650 | /* Alternative loses if it requires a type of reload not |
2651 | permitted for this insn. We can always reload | |
2652 | objects with a REG_UNUSED note. */ | |
2653 | if ((curr_static_id->operand[nop].type != OP_IN | |
2654 | && no_output_reloads_p | |
2655 | && ! find_reg_note (curr_insn, REG_UNUSED, op)) | |
2656 | || (curr_static_id->operand[nop].type != OP_OUT | |
b3d446cb | 2657 | && no_input_reloads_p && ! const_to_mem) |
2658 | || (this_alternative_matches >= 0 | |
fe5cb3e1 | 2659 | && (no_input_reloads_p |
2660 | || (no_output_reloads_p | |
2661 | && (curr_static_id->operand | |
2662 | [this_alternative_matches].type != OP_IN) | |
2663 | && ! find_reg_note (curr_insn, REG_UNUSED, | |
2664 | no_subreg_reg_operand | |
2665 | [this_alternative_matches]))))) | |
b3d446cb | 2666 | { |
2667 | if (lra_dump_file != NULL) | |
2668 | fprintf | |
2669 | (lra_dump_file, | |
2670 | " alt=%d: No input/otput reload -- refuse\n", | |
2671 | nalt); | |
2672 | goto fail; | |
2673 | } | |
1a8f8886 | 2674 | |
f4d3c071 | 2675 | /* Alternative loses if it required class pseudo cannot |
2e19c420 | 2676 | hold value of required mode. Such insns can be |
2bd08537 | 2677 | described by insn definitions with mode iterators. */ |
2e19c420 | 2678 | if (GET_MODE (*curr_id->operand_loc[nop]) != VOIDmode |
2679 | && ! hard_reg_set_empty_p (this_alternative_set) | |
2bd08537 | 2680 | /* It is common practice for constraints to use a |
2681 | class which does not have actually enough regs to | |
2682 | hold the value (e.g. x86 AREG for mode requiring | |
2683 | more one general reg). Therefore we have 2 | |
07c11f2b | 2684 | conditions to check that the reload pseudo cannot |
2685 | hold the mode value. */ | |
b395382f | 2686 | && (!targetm.hard_regno_mode_ok |
2687 | (ira_class_hard_regs[this_alternative][0], | |
2688 | GET_MODE (*curr_id->operand_loc[nop]))) | |
2bd08537 | 2689 | /* The above condition is not enough as the first |
2690 | reg in ira_class_hard_regs can be not aligned for | |
2691 | multi-words mode values. */ | |
25cd984c | 2692 | && (prohibited_class_reg_set_mode_p |
2693 | (this_alternative, this_alternative_set, | |
2694 | GET_MODE (*curr_id->operand_loc[nop])))) | |
2695 | { | |
2696 | if (lra_dump_file != NULL) | |
2697 | fprintf (lra_dump_file, | |
2698 | " alt=%d: reload pseudo for op %d " | |
000969f9 | 2699 | "cannot hold the mode value -- refuse\n", |
25cd984c | 2700 | nalt, nop); |
2701 | goto fail; | |
2e19c420 | 2702 | } |
2703 | ||
4b3aba76 | 2704 | /* Check strong discouragement of reload of non-constant |
2705 | into class THIS_ALTERNATIVE. */ | |
2706 | if (! CONSTANT_P (op) && ! no_regs_p | |
2707 | && (targetm.preferred_reload_class | |
2708 | (op, this_alternative) == NO_REGS | |
2709 | || (curr_static_id->operand[nop].type == OP_OUT | |
2710 | && (targetm.preferred_output_reload_class | |
2711 | (op, this_alternative) == NO_REGS)))) | |
34575461 | 2712 | { |
2713 | if (lra_dump_file != NULL) | |
2714 | fprintf (lra_dump_file, | |
2715 | " %d Non-prefered reload: reject+=%d\n", | |
2716 | nop, LRA_MAX_REJECT); | |
2717 | reject += LRA_MAX_REJECT; | |
2718 | } | |
1a8f8886 | 2719 | |
0178c26e | 2720 | if (! (MEM_P (op) && offmemok) |
2721 | && ! (const_to_mem && constmemok)) | |
c6a6cdaa | 2722 | { |
2723 | /* We prefer to reload pseudos over reloading other | |
2724 | things, since such reloads may be able to be | |
2725 | eliminated later. So bump REJECT in other cases. | |
2726 | Don't do this in the case where we are forcing a | |
2727 | constant into memory and it will then win since | |
2728 | we don't want to have a different alternative | |
2729 | match then. */ | |
2730 | if (! (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER)) | |
34575461 | 2731 | { |
2732 | if (lra_dump_file != NULL) | |
2733 | fprintf | |
2734 | (lra_dump_file, | |
2735 | " %d Non-pseudo reload: reject+=2\n", | |
2736 | nop); | |
2737 | reject += 2; | |
2738 | } | |
1a8f8886 | 2739 | |
c6a6cdaa | 2740 | if (! no_regs_p) |
2741 | reload_nregs | |
2742 | += ira_reg_class_max_nregs[this_alternative][mode]; | |
273c330a | 2743 | |
2744 | if (SMALL_REGISTER_CLASS_P (this_alternative)) | |
34575461 | 2745 | { |
2746 | if (lra_dump_file != NULL) | |
2747 | fprintf | |
2748 | (lra_dump_file, | |
2749 | " %d Small class reload: reject+=%d\n", | |
2750 | nop, LRA_LOSER_COST_FACTOR / 2); | |
2751 | reject += LRA_LOSER_COST_FACTOR / 2; | |
2752 | } | |
c6a6cdaa | 2753 | } |
2754 | ||
70892847 | 2755 | /* We are trying to spill pseudo into memory. It is |
2756 | usually more costly than moving to a hard register | |
2757 | although it might takes the same number of | |
b02d1ebc | 2758 | reloads. |
2759 | ||
2760 | Non-pseudo spill may happen also. Suppose a target allows both | |
2761 | register and memory in the operand constraint alternatives, | |
2762 | then it's typical that an eliminable register has a substition | |
2763 | of "base + offset" which can either be reloaded by a simple | |
2764 | "new_reg <= base + offset" which will match the register | |
2765 | constraint, or a similar reg addition followed by further spill | |
2766 | to and reload from memory which will match the memory | |
2767 | constraint, but this memory spill will be much more costly | |
2768 | usually. | |
2769 | ||
2770 | Code below increases the reject for both pseudo and non-pseudo | |
2771 | spill. */ | |
21b32b46 | 2772 | if (no_regs_p |
2773 | && !(MEM_P (op) && offmemok) | |
2774 | && !(REG_P (op) && hard_regno[nop] < 0)) | |
34575461 | 2775 | { |
2776 | if (lra_dump_file != NULL) | |
2777 | fprintf | |
2778 | (lra_dump_file, | |
b02d1ebc | 2779 | " %d Spill %spseudo into memory: reject+=3\n", |
2780 | nop, REG_P (op) ? "" : "Non-"); | |
34575461 | 2781 | reject += 3; |
c2d1c3eb | 2782 | if (VECTOR_MODE_P (mode)) |
2783 | { | |
2784 | /* Spilling vectors into memory is usually more | |
2785 | costly as they contain big values. */ | |
2786 | if (lra_dump_file != NULL) | |
2787 | fprintf | |
2788 | (lra_dump_file, | |
2789 | " %d Spill vector pseudo: reject+=2\n", | |
2790 | nop); | |
2791 | reject += 2; | |
2792 | } | |
34575461 | 2793 | } |
70892847 | 2794 | |
9cd589b8 | 2795 | /* When we use an operand requiring memory in given |
2796 | alternative, the insn should write *and* read the | |
2797 | value to/from memory it is costly in comparison with | |
2798 | an insn alternative which does not use memory | |
2799 | (e.g. register or immediate operand). We exclude | |
2800 | memory operand for such case as we can satisfy the | |
2801 | memory constraints by reloading address. */ | |
2802 | if (no_regs_p && offmemok && !MEM_P (op)) | |
8afaf3bf | 2803 | { |
2804 | if (lra_dump_file != NULL) | |
2805 | fprintf | |
2806 | (lra_dump_file, | |
2807 | " Using memory insn operand %d: reject+=3\n", | |
2808 | nop); | |
2809 | reject += 3; | |
2810 | } | |
2811 | ||
2590979b | 2812 | /* If reload requires moving value through secondary |
2813 | memory, it will need one more insn at least. */ | |
2814 | if (this_alternative != NO_REGS | |
2815 | && REG_P (op) && (cl = get_reg_class (REGNO (op))) != NO_REGS | |
2816 | && ((curr_static_id->operand[nop].type != OP_OUT | |
c836e75b | 2817 | && targetm.secondary_memory_needed (GET_MODE (op), cl, |
2818 | this_alternative)) | |
2590979b | 2819 | || (curr_static_id->operand[nop].type != OP_IN |
c836e75b | 2820 | && (targetm.secondary_memory_needed |
2821 | (GET_MODE (op), this_alternative, cl))))) | |
2590979b | 2822 | losers++; |
c836e75b | 2823 | |
eb70a065 | 2824 | if (MEM_P (op) && offmemok) |
2825 | addr_losers++; | |
67f1426f | 2826 | else |
44cafa9a | 2827 | { |
67f1426f | 2828 | /* Input reloads can be inherited more often than |
2829 | output reloads can be removed, so penalize output | |
2830 | reloads. */ | |
2831 | if (!REG_P (op) || curr_static_id->operand[nop].type != OP_IN) | |
2832 | { | |
2833 | if (lra_dump_file != NULL) | |
2834 | fprintf | |
2835 | (lra_dump_file, | |
2836 | " %d Non input pseudo reload: reject++\n", | |
2837 | nop); | |
2838 | reject++; | |
2839 | } | |
2840 | ||
2841 | if (curr_static_id->operand[nop].type == OP_INOUT) | |
2842 | { | |
2843 | if (lra_dump_file != NULL) | |
2844 | fprintf | |
2845 | (lra_dump_file, | |
2846 | " %d Input/Output reload: reject+=%d\n", | |
2847 | nop, LRA_LOSER_COST_FACTOR); | |
2848 | reject += LRA_LOSER_COST_FACTOR; | |
2849 | } | |
44cafa9a | 2850 | } |
c6a6cdaa | 2851 | } |
1a8f8886 | 2852 | |
2b1732ad | 2853 | if (early_clobber_p && ! scratch_p) |
34575461 | 2854 | { |
2855 | if (lra_dump_file != NULL) | |
2856 | fprintf (lra_dump_file, | |
2857 | " %d Early clobber: reject++\n", nop); | |
2858 | reject++; | |
2859 | } | |
c6a6cdaa | 2860 | /* ??? We check early clobbers after processing all operands |
2861 | (see loop below) and there we update the costs more. | |
2862 | Should we update the cost (may be approximately) here | |
2863 | because of early clobber register reloads or it is a rare | |
2864 | or non-important thing to be worth to do it. */ | |
eb70a065 | 2865 | overall = (losers * LRA_LOSER_COST_FACTOR + reject |
2866 | - (addr_losers == losers ? static_reject : 0)); | |
c6a6cdaa | 2867 | if ((best_losers == 0 || losers != 0) && best_overall < overall) |
f7c98bb1 | 2868 | { |
2869 | if (lra_dump_file != NULL) | |
2870 | fprintf (lra_dump_file, | |
34575461 | 2871 | " alt=%d,overall=%d,losers=%d -- refuse\n", |
f7c98bb1 | 2872 | nalt, overall, losers); |
2873 | goto fail; | |
2874 | } | |
c6a6cdaa | 2875 | |
8df3e7a5 | 2876 | if (update_and_check_small_class_inputs (nop, nalt, |
2877 | this_alternative)) | |
8afaf3bf | 2878 | { |
2879 | if (lra_dump_file != NULL) | |
2880 | fprintf (lra_dump_file, | |
2881 | " alt=%d, not enough small class regs -- refuse\n", | |
2882 | nalt); | |
2883 | goto fail; | |
2884 | } | |
c6a6cdaa | 2885 | curr_alt[nop] = this_alternative; |
de7358ed | 2886 | curr_alt_set[nop] = this_alternative_set; |
c6a6cdaa | 2887 | curr_alt_win[nop] = this_alternative_win; |
2888 | curr_alt_match_win[nop] = this_alternative_match_win; | |
2889 | curr_alt_offmemok[nop] = this_alternative_offmemok; | |
2890 | curr_alt_matches[nop] = this_alternative_matches; | |
1a8f8886 | 2891 | |
c6a6cdaa | 2892 | if (this_alternative_matches >= 0 |
2893 | && !did_match && !this_alternative_win) | |
2894 | curr_alt_win[this_alternative_matches] = false; | |
1a8f8886 | 2895 | |
c6a6cdaa | 2896 | if (early_clobber_p && operand_reg[nop] != NULL_RTX) |
2897 | early_clobbered_nops[early_clobbered_regs_num++] = nop; | |
2898 | } | |
eb70a065 | 2899 | |
ea99c7a1 | 2900 | if (curr_insn_set != NULL_RTX && n_operands == 2 |
2901 | /* Prevent processing non-move insns. */ | |
2902 | && (GET_CODE (SET_SRC (curr_insn_set)) == SUBREG | |
2903 | || SET_SRC (curr_insn_set) == no_subreg_reg_operand[1]) | |
2904 | && ((! curr_alt_win[0] && ! curr_alt_win[1] | |
2905 | && REG_P (no_subreg_reg_operand[0]) | |
2906 | && REG_P (no_subreg_reg_operand[1]) | |
2907 | && (reg_in_class_p (no_subreg_reg_operand[0], curr_alt[1]) | |
2908 | || reg_in_class_p (no_subreg_reg_operand[1], curr_alt[0]))) | |
2909 | || (! curr_alt_win[0] && curr_alt_win[1] | |
2910 | && REG_P (no_subreg_reg_operand[1]) | |
eb70a065 | 2911 | /* Check that we reload memory not the memory |
2912 | address. */ | |
9782b2bc | 2913 | && ! (curr_alt_offmemok[0] |
2914 | && MEM_P (no_subreg_reg_operand[0])) | |
ea99c7a1 | 2915 | && reg_in_class_p (no_subreg_reg_operand[1], curr_alt[0])) |
2916 | || (curr_alt_win[0] && ! curr_alt_win[1] | |
2917 | && REG_P (no_subreg_reg_operand[0]) | |
eb70a065 | 2918 | /* Check that we reload memory not the memory |
2919 | address. */ | |
9782b2bc | 2920 | && ! (curr_alt_offmemok[1] |
2921 | && MEM_P (no_subreg_reg_operand[1])) | |
ea99c7a1 | 2922 | && reg_in_class_p (no_subreg_reg_operand[0], curr_alt[1]) |
2923 | && (! CONST_POOL_OK_P (curr_operand_mode[1], | |
2924 | no_subreg_reg_operand[1]) | |
2925 | || (targetm.preferred_reload_class | |
2926 | (no_subreg_reg_operand[1], | |
2927 | (enum reg_class) curr_alt[1]) != NO_REGS)) | |
2928 | /* If it is a result of recent elimination in move | |
2929 | insn we can transform it into an add still by | |
2930 | using this alternative. */ | |
69f0f127 | 2931 | && GET_CODE (no_subreg_reg_operand[1]) != PLUS |
2932 | /* Likewise if the source has been replaced with an | |
2933 | equivalent value. This only happens once -- the reload | |
2934 | will use the equivalent value instead of the register it | |
2935 | replaces -- so there should be no danger of cycling. */ | |
2936 | && !equiv_substition_p[1]))) | |
34575461 | 2937 | { |
2938 | /* We have a move insn and a new reload insn will be similar | |
9782b2bc | 2939 | to the current insn. We should avoid such situation as |
2940 | it results in LRA cycling. */ | |
2941 | if (lra_dump_file != NULL) | |
2942 | fprintf (lra_dump_file, | |
2943 | " Cycle danger: overall += LRA_MAX_REJECT\n"); | |
34575461 | 2944 | overall += LRA_MAX_REJECT; |
2945 | } | |
c6a6cdaa | 2946 | ok_p = true; |
2947 | curr_alt_dont_inherit_ops_num = 0; | |
2948 | for (nop = 0; nop < early_clobbered_regs_num; nop++) | |
2949 | { | |
8c3a9b39 | 2950 | int i, j, clobbered_hard_regno, first_conflict_j, last_conflict_j; |
c6a6cdaa | 2951 | HARD_REG_SET temp_set; |
2952 | ||
2953 | i = early_clobbered_nops[nop]; | |
2954 | if ((! curr_alt_win[i] && ! curr_alt_match_win[i]) | |
2955 | || hard_regno[i] < 0) | |
2956 | continue; | |
89c2edcf | 2957 | lra_assert (operand_reg[i] != NULL_RTX); |
c6a6cdaa | 2958 | clobbered_hard_regno = hard_regno[i]; |
2959 | CLEAR_HARD_REG_SET (temp_set); | |
2960 | add_to_hard_reg_set (&temp_set, biggest_mode[i], clobbered_hard_regno); | |
8c3a9b39 | 2961 | first_conflict_j = last_conflict_j = -1; |
c6a6cdaa | 2962 | for (j = 0; j < n_operands; j++) |
2963 | if (j == i | |
2964 | /* We don't want process insides of match_operator and | |
2965 | match_parallel because otherwise we would process | |
2966 | their operands once again generating a wrong | |
2967 | code. */ | |
2968 | || curr_static_id->operand[j].is_operator) | |
2969 | continue; | |
2970 | else if ((curr_alt_matches[j] == i && curr_alt_match_win[j]) | |
2971 | || (curr_alt_matches[i] == j && curr_alt_match_win[i])) | |
2972 | continue; | |
89c2edcf | 2973 | /* If we don't reload j-th operand, check conflicts. */ |
2974 | else if ((curr_alt_win[j] || curr_alt_match_win[j]) | |
2975 | && uses_hard_regs_p (*curr_id->operand_loc[j], temp_set)) | |
8c3a9b39 | 2976 | { |
2977 | if (first_conflict_j < 0) | |
2978 | first_conflict_j = j; | |
2979 | last_conflict_j = j; | |
b782636f | 2980 | /* Both the earlyclobber operand and conflicting operand |
2981 | cannot both be user defined hard registers. */ | |
2982 | if (HARD_REGISTER_P (operand_reg[i]) | |
2983 | && REG_USERVAR_P (operand_reg[i]) | |
2984 | && operand_reg[j] != NULL_RTX | |
2985 | && HARD_REGISTER_P (operand_reg[j]) | |
2986 | && REG_USERVAR_P (operand_reg[j])) | |
2987 | fatal_insn ("unable to generate reloads for " | |
2988 | "impossible constraints:", curr_insn); | |
8c3a9b39 | 2989 | } |
2990 | if (last_conflict_j < 0) | |
c6a6cdaa | 2991 | continue; |
b782636f | 2992 | |
2993 | /* If an earlyclobber operand conflicts with another non-matching | |
2994 | operand (ie, they have been assigned the same hard register), | |
2995 | then it is better to reload the other operand, as there may | |
2996 | exist yet another operand with a matching constraint associated | |
2997 | with the earlyclobber operand. However, if one of the operands | |
2998 | is an explicit use of a hard register, then we must reload the | |
2999 | other non-hard register operand. */ | |
3000 | if (HARD_REGISTER_P (operand_reg[i]) | |
3001 | || (first_conflict_j == last_conflict_j | |
3002 | && operand_reg[last_conflict_j] != NULL_RTX | |
3003 | && !curr_alt_match_win[last_conflict_j] | |
3004 | && !HARD_REGISTER_P (operand_reg[last_conflict_j]))) | |
89c2edcf | 3005 | { |
8c3a9b39 | 3006 | curr_alt_win[last_conflict_j] = false; |
3007 | curr_alt_dont_inherit_ops[curr_alt_dont_inherit_ops_num++] | |
3008 | = last_conflict_j; | |
89c2edcf | 3009 | losers++; |
34575461 | 3010 | if (lra_dump_file != NULL) |
3011 | fprintf | |
3012 | (lra_dump_file, | |
3013 | " %d Conflict early clobber reload: reject--\n", | |
3014 | i); | |
89c2edcf | 3015 | } |
c6a6cdaa | 3016 | else |
3017 | { | |
89c2edcf | 3018 | /* We need to reload early clobbered register and the |
3019 | matched registers. */ | |
3020 | for (j = 0; j < n_operands; j++) | |
3021 | if (curr_alt_matches[j] == i) | |
3022 | { | |
3023 | curr_alt_match_win[j] = false; | |
3024 | losers++; | |
3025 | overall += LRA_LOSER_COST_FACTOR; | |
3026 | } | |
3027 | if (! curr_alt_match_win[i]) | |
3028 | curr_alt_dont_inherit_ops[curr_alt_dont_inherit_ops_num++] = i; | |
3029 | else | |
3030 | { | |
3031 | /* Remember pseudos used for match reloads are never | |
3032 | inherited. */ | |
3033 | lra_assert (curr_alt_matches[i] >= 0); | |
3034 | curr_alt_win[curr_alt_matches[i]] = false; | |
3035 | } | |
3036 | curr_alt_win[i] = curr_alt_match_win[i] = false; | |
3037 | losers++; | |
34575461 | 3038 | if (lra_dump_file != NULL) |
3039 | fprintf | |
3040 | (lra_dump_file, | |
19efce70 | 3041 | " %d Matched conflict early clobber reloads: " |
34575461 | 3042 | "reject--\n", |
3043 | i); | |
3dfcf76a | 3044 | } |
3045 | /* Early clobber was already reflected in REJECT. */ | |
3046 | if (!matching_early_clobber[i]) | |
3047 | { | |
3048 | lra_assert (reject > 0); | |
f7c98bb1 | 3049 | reject--; |
3dfcf76a | 3050 | matching_early_clobber[i] = 1; |
c6a6cdaa | 3051 | } |
3dfcf76a | 3052 | overall += LRA_LOSER_COST_FACTOR - 1; |
c6a6cdaa | 3053 | } |
f7c98bb1 | 3054 | if (lra_dump_file != NULL) |
273c330a | 3055 | fprintf (lra_dump_file, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n", |
3056 | nalt, overall, losers, reload_nregs); | |
f7c98bb1 | 3057 | |
c6a6cdaa | 3058 | /* If this alternative can be made to work by reloading, and it |
3059 | needs less reloading than the others checked so far, record | |
3060 | it as the chosen goal for reloading. */ | |
3061 | if ((best_losers != 0 && losers == 0) | |
3062 | || (((best_losers == 0 && losers == 0) | |
3063 | || (best_losers != 0 && losers != 0)) | |
3064 | && (best_overall > overall | |
3065 | || (best_overall == overall | |
3066 | /* If the cost of the reloads is the same, | |
3067 | prefer alternative which requires minimal | |
273c330a | 3068 | number of reload regs. */ |
3069 | && (reload_nregs < best_reload_nregs | |
3070 | || (reload_nregs == best_reload_nregs | |
04dda2a2 | 3071 | && (best_reload_sum < reload_sum |
3072 | || (best_reload_sum == reload_sum | |
3073 | && nalt < goal_alt_number)))))))) | |
c6a6cdaa | 3074 | { |
3075 | for (nop = 0; nop < n_operands; nop++) | |
3076 | { | |
3077 | goal_alt_win[nop] = curr_alt_win[nop]; | |
3078 | goal_alt_match_win[nop] = curr_alt_match_win[nop]; | |
3079 | goal_alt_matches[nop] = curr_alt_matches[nop]; | |
3080 | goal_alt[nop] = curr_alt[nop]; | |
3081 | goal_alt_offmemok[nop] = curr_alt_offmemok[nop]; | |
3082 | } | |
3083 | goal_alt_dont_inherit_ops_num = curr_alt_dont_inherit_ops_num; | |
3084 | for (nop = 0; nop < curr_alt_dont_inherit_ops_num; nop++) | |
3085 | goal_alt_dont_inherit_ops[nop] = curr_alt_dont_inherit_ops[nop]; | |
3086 | goal_alt_swapped = curr_swapped; | |
3087 | best_overall = overall; | |
3088 | best_losers = losers; | |
c6a6cdaa | 3089 | best_reload_nregs = reload_nregs; |
3090 | best_reload_sum = reload_sum; | |
3091 | goal_alt_number = nalt; | |
3092 | } | |
3093 | if (losers == 0) | |
3094 | /* Everything is satisfied. Do not process alternatives | |
1a8f8886 | 3095 | anymore. */ |
c6a6cdaa | 3096 | break; |
3097 | fail: | |
3098 | ; | |
3099 | } | |
3100 | return ok_p; | |
3101 | } | |
3102 | ||
d03288b6 | 3103 | /* Make reload base reg from address AD. */ |
3104 | static rtx | |
3105 | base_to_reg (struct address_info *ad) | |
3106 | { | |
3107 | enum reg_class cl; | |
3108 | int code = -1; | |
3109 | rtx new_inner = NULL_RTX; | |
3110 | rtx new_reg = NULL_RTX; | |
57c26b3a | 3111 | rtx_insn *insn; |
3112 | rtx_insn *last_insn = get_last_insn(); | |
d03288b6 | 3113 | |
0508f466 | 3114 | lra_assert (ad->disp == ad->disp_term); |
d03288b6 | 3115 | cl = base_reg_class (ad->mode, ad->as, ad->base_outer_code, |
3116 | get_index_code (ad)); | |
0508f466 | 3117 | new_reg = lra_create_new_reg (GET_MODE (*ad->base), NULL_RTX, |
d03288b6 | 3118 | cl, "base"); |
3119 | new_inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), new_reg, | |
3120 | ad->disp_term == NULL | |
0508f466 | 3121 | ? const0_rtx |
d03288b6 | 3122 | : *ad->disp_term); |
3123 | if (!valid_address_p (ad->mode, new_inner, ad->as)) | |
3124 | return NULL_RTX; | |
0508f466 | 3125 | insn = emit_insn (gen_rtx_SET (new_reg, *ad->base)); |
d03288b6 | 3126 | code = recog_memoized (insn); |
3127 | if (code < 0) | |
3128 | { | |
3129 | delete_insns_since (last_insn); | |
3130 | return NULL_RTX; | |
3131 | } | |
3132 | ||
3133 | return new_inner; | |
3134 | } | |
3135 | ||
6cc181b3 | 3136 | /* Make reload base reg + DISP from address AD. Return the new pseudo. */ |
c6a6cdaa | 3137 | static rtx |
6cc181b3 | 3138 | base_plus_disp_to_reg (struct address_info *ad, rtx disp) |
c6a6cdaa | 3139 | { |
3140 | enum reg_class cl; | |
3141 | rtx new_reg; | |
3142 | ||
6cc181b3 | 3143 | lra_assert (ad->base == ad->base_term); |
1efe9e9d | 3144 | cl = base_reg_class (ad->mode, ad->as, ad->base_outer_code, |
3145 | get_index_code (ad)); | |
3146 | new_reg = lra_create_new_reg (GET_MODE (*ad->base_term), NULL_RTX, | |
3147 | cl, "base + disp"); | |
6cc181b3 | 3148 | lra_emit_add (new_reg, *ad->base_term, disp); |
c6a6cdaa | 3149 | return new_reg; |
3150 | } | |
3151 | ||
28f7a2af | 3152 | /* Make reload of index part of address AD. Return the new |
3153 | pseudo. */ | |
3154 | static rtx | |
3155 | index_part_to_reg (struct address_info *ad) | |
3156 | { | |
3157 | rtx new_reg; | |
3158 | ||
3159 | new_reg = lra_create_new_reg (GET_MODE (*ad->index), NULL_RTX, | |
3160 | INDEX_REG_CLASS, "index term"); | |
3161 | expand_mult (GET_MODE (*ad->index), *ad->index_term, | |
3162 | GEN_INT (get_index_scale (ad)), new_reg, 1); | |
3163 | return new_reg; | |
3164 | } | |
3165 | ||
1efe9e9d | 3166 | /* Return true if we can add a displacement to address AD, even if that |
3167 | makes the address invalid. The fix-up code requires any new address | |
3168 | to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */ | |
809320f0 | 3169 | static bool |
1efe9e9d | 3170 | can_add_disp_p (struct address_info *ad) |
809320f0 | 3171 | { |
1efe9e9d | 3172 | return (!ad->autoinc_p |
3173 | && ad->segment == NULL | |
3174 | && ad->base == ad->base_term | |
3175 | && ad->disp == ad->disp_term); | |
809320f0 | 3176 | } |
3177 | ||
1efe9e9d | 3178 | /* Make equiv substitution in address AD. Return true if a substitution |
3179 | was made. */ | |
c6a6cdaa | 3180 | static bool |
1efe9e9d | 3181 | equiv_address_substitution (struct address_info *ad) |
c6a6cdaa | 3182 | { |
1efe9e9d | 3183 | rtx base_reg, new_base_reg, index_reg, new_index_reg, *base_term, *index_term; |
a4686d0a | 3184 | poly_int64 disp; |
3185 | HOST_WIDE_INT scale; | |
c6a6cdaa | 3186 | bool change_p; |
3187 | ||
1efe9e9d | 3188 | base_term = strip_subreg (ad->base_term); |
3189 | if (base_term == NULL) | |
c6a6cdaa | 3190 | base_reg = new_base_reg = NULL_RTX; |
3191 | else | |
3192 | { | |
1efe9e9d | 3193 | base_reg = *base_term; |
3b3a5e5f | 3194 | new_base_reg = get_equiv_with_elimination (base_reg, curr_insn); |
c6a6cdaa | 3195 | } |
1efe9e9d | 3196 | index_term = strip_subreg (ad->index_term); |
3197 | if (index_term == NULL) | |
c6a6cdaa | 3198 | index_reg = new_index_reg = NULL_RTX; |
3199 | else | |
3200 | { | |
1efe9e9d | 3201 | index_reg = *index_term; |
3b3a5e5f | 3202 | new_index_reg = get_equiv_with_elimination (index_reg, curr_insn); |
c6a6cdaa | 3203 | } |
3204 | if (base_reg == new_base_reg && index_reg == new_index_reg) | |
3205 | return false; | |
3206 | disp = 0; | |
3207 | change_p = false; | |
3208 | if (lra_dump_file != NULL) | |
3209 | { | |
3210 | fprintf (lra_dump_file, "Changing address in insn %d ", | |
3211 | INSN_UID (curr_insn)); | |
6dde9719 | 3212 | dump_value_slim (lra_dump_file, *ad->outer, 1); |
c6a6cdaa | 3213 | } |
3214 | if (base_reg != new_base_reg) | |
3215 | { | |
a4686d0a | 3216 | poly_int64 offset; |
c6a6cdaa | 3217 | if (REG_P (new_base_reg)) |
3218 | { | |
1efe9e9d | 3219 | *base_term = new_base_reg; |
c6a6cdaa | 3220 | change_p = true; |
3221 | } | |
3222 | else if (GET_CODE (new_base_reg) == PLUS | |
3223 | && REG_P (XEXP (new_base_reg, 0)) | |
a4686d0a | 3224 | && poly_int_rtx_p (XEXP (new_base_reg, 1), &offset) |
1efe9e9d | 3225 | && can_add_disp_p (ad)) |
c6a6cdaa | 3226 | { |
a4686d0a | 3227 | disp += offset; |
1efe9e9d | 3228 | *base_term = XEXP (new_base_reg, 0); |
c6a6cdaa | 3229 | change_p = true; |
3230 | } | |
1efe9e9d | 3231 | if (ad->base_term2 != NULL) |
3232 | *ad->base_term2 = *ad->base_term; | |
c6a6cdaa | 3233 | } |
c6a6cdaa | 3234 | if (index_reg != new_index_reg) |
3235 | { | |
a4686d0a | 3236 | poly_int64 offset; |
c6a6cdaa | 3237 | if (REG_P (new_index_reg)) |
3238 | { | |
1efe9e9d | 3239 | *index_term = new_index_reg; |
c6a6cdaa | 3240 | change_p = true; |
3241 | } | |
3242 | else if (GET_CODE (new_index_reg) == PLUS | |
3243 | && REG_P (XEXP (new_index_reg, 0)) | |
a4686d0a | 3244 | && poly_int_rtx_p (XEXP (new_index_reg, 1), &offset) |
1efe9e9d | 3245 | && can_add_disp_p (ad) |
809320f0 | 3246 | && (scale = get_index_scale (ad))) |
c6a6cdaa | 3247 | { |
a4686d0a | 3248 | disp += offset * scale; |
1efe9e9d | 3249 | *index_term = XEXP (new_index_reg, 0); |
c6a6cdaa | 3250 | change_p = true; |
3251 | } | |
3252 | } | |
a4686d0a | 3253 | if (maybe_ne (disp, 0)) |
c6a6cdaa | 3254 | { |
1efe9e9d | 3255 | if (ad->disp != NULL) |
3256 | *ad->disp = plus_constant (GET_MODE (*ad->inner), *ad->disp, disp); | |
c6a6cdaa | 3257 | else |
3258 | { | |
1efe9e9d | 3259 | *ad->inner = plus_constant (GET_MODE (*ad->inner), *ad->inner, disp); |
3260 | update_address (ad); | |
c6a6cdaa | 3261 | } |
3262 | change_p = true; | |
3263 | } | |
3264 | if (lra_dump_file != NULL) | |
3265 | { | |
3266 | if (! change_p) | |
3267 | fprintf (lra_dump_file, " -- no change\n"); | |
3268 | else | |
3269 | { | |
3270 | fprintf (lra_dump_file, " on equiv "); | |
6dde9719 | 3271 | dump_value_slim (lra_dump_file, *ad->outer, 1); |
c6a6cdaa | 3272 | fprintf (lra_dump_file, "\n"); |
3273 | } | |
3274 | } | |
3275 | return change_p; | |
3276 | } | |
3277 | ||
497ba60f | 3278 | /* Major function to make reloads for an address in operand NOP or |
3279 | check its correctness (If CHECK_ONLY_P is true). The supported | |
3280 | cases are: | |
d9b69682 | 3281 | |
c625778b | 3282 | 1) an address that existed before LRA started, at which point it |
3283 | must have been valid. These addresses are subject to elimination | |
3284 | and may have become invalid due to the elimination offset being out | |
3285 | of range. | |
d9b69682 | 3286 | |
c625778b | 3287 | 2) an address created by forcing a constant to memory |
3288 | (force_const_to_mem). The initial form of these addresses might | |
3289 | not be valid, and it is this function's job to make them valid. | |
d9b69682 | 3290 | |
3291 | 3) a frame address formed from a register and a (possibly zero) | |
c625778b | 3292 | constant offset. As above, these addresses might not be valid and |
3293 | this function must make them so. | |
d9b69682 | 3294 | |
3295 | Add reloads to the lists *BEFORE and *AFTER. We might need to add | |
c6a6cdaa | 3296 | reloads to *AFTER because of inc/dec, {pre, post} modify in the |
dcd5393f | 3297 | address. Return true for any RTL change. |
3298 | ||
3299 | The function is a helper function which does not produce all | |
497ba60f | 3300 | transformations (when CHECK_ONLY_P is false) which can be |
3301 | necessary. It does just basic steps. To do all necessary | |
3302 | transformations use function process_address. */ | |
c6a6cdaa | 3303 | static bool |
497ba60f | 3304 | process_address_1 (int nop, bool check_only_p, |
3305 | rtx_insn **before, rtx_insn **after) | |
c6a6cdaa | 3306 | { |
1efe9e9d | 3307 | struct address_info ad; |
3308 | rtx new_reg; | |
72234ee9 | 3309 | HOST_WIDE_INT scale; |
c6a6cdaa | 3310 | rtx op = *curr_id->operand_loc[nop]; |
3311 | const char *constraint = curr_static_id->operand[nop].constraint; | |
79bc09fb | 3312 | enum constraint_num cn = lookup_constraint (constraint); |
497ba60f | 3313 | bool change_p = false; |
c6a6cdaa | 3314 | |
556c2dd1 | 3315 | if (MEM_P (op) |
3316 | && GET_MODE (op) == BLKmode | |
3317 | && GET_CODE (XEXP (op, 0)) == SCRATCH) | |
3318 | return false; | |
3319 | ||
afca8a73 | 3320 | if (insn_extra_address_constraint (cn) |
3321 | /* When we find an asm operand with an address constraint that | |
3322 | doesn't satisfy address_operand to begin with, we clear | |
3323 | is_address, so that we don't try to make a non-address fit. | |
3324 | If the asm statement got this far, it's because other | |
3325 | constraints are available, and we'll use them, disregarding | |
3326 | the unsatisfiable address ones. */ | |
3327 | && curr_static_id->operand[nop].is_address) | |
1efe9e9d | 3328 | decompose_lea_address (&ad, curr_id->operand_loc[nop]); |
efd3cce2 | 3329 | /* Do not attempt to decompose arbitrary addresses generated by combine |
3330 | for asm operands with loose constraints, e.g 'X'. */ | |
3331 | else if (MEM_P (op) | |
5e0f6ab6 | 3332 | && !(INSN_CODE (curr_insn) < 0 |
3333 | && get_constraint_type (cn) == CT_FIXED_FORM | |
efd3cce2 | 3334 | && constraint_satisfied_p (op, cn))) |
1efe9e9d | 3335 | decompose_mem_address (&ad, op); |
c6a6cdaa | 3336 | else if (GET_CODE (op) == SUBREG |
3337 | && MEM_P (SUBREG_REG (op))) | |
1efe9e9d | 3338 | decompose_mem_address (&ad, SUBREG_REG (op)); |
c6a6cdaa | 3339 | else |
3340 | return false; | |
382efce6 | 3341 | /* If INDEX_REG_CLASS is assigned to base_term already and isn't to |
3342 | index_term, swap them so to avoid assigning INDEX_REG_CLASS to both | |
3343 | when INDEX_REG_CLASS is a single register class. */ | |
3344 | if (ad.base_term != NULL | |
3345 | && ad.index_term != NULL | |
3346 | && ira_class_hard_regs_num[INDEX_REG_CLASS] == 1 | |
3347 | && REG_P (*ad.base_term) | |
3348 | && REG_P (*ad.index_term) | |
3349 | && in_class_p (*ad.base_term, INDEX_REG_CLASS, NULL) | |
3350 | && ! in_class_p (*ad.index_term, INDEX_REG_CLASS, NULL)) | |
3351 | { | |
3352 | std::swap (ad.base, ad.index); | |
3353 | std::swap (ad.base_term, ad.index_term); | |
3354 | } | |
497ba60f | 3355 | if (! check_only_p) |
3356 | change_p = equiv_address_substitution (&ad); | |
1efe9e9d | 3357 | if (ad.base_term != NULL |
c6a6cdaa | 3358 | && (process_addr_reg |
497ba60f | 3359 | (ad.base_term, check_only_p, before, |
1efe9e9d | 3360 | (ad.autoinc_p |
3361 | && !(REG_P (*ad.base_term) | |
3362 | && find_regno_note (curr_insn, REG_DEAD, | |
3363 | REGNO (*ad.base_term)) != NULL_RTX) | |
c6a6cdaa | 3364 | ? after : NULL), |
1efe9e9d | 3365 | base_reg_class (ad.mode, ad.as, ad.base_outer_code, |
3366 | get_index_code (&ad))))) | |
c6a6cdaa | 3367 | { |
3368 | change_p = true; | |
1efe9e9d | 3369 | if (ad.base_term2 != NULL) |
3370 | *ad.base_term2 = *ad.base_term; | |
c6a6cdaa | 3371 | } |
1efe9e9d | 3372 | if (ad.index_term != NULL |
497ba60f | 3373 | && process_addr_reg (ad.index_term, check_only_p, |
3374 | before, NULL, INDEX_REG_CLASS)) | |
c6a6cdaa | 3375 | change_p = true; |
3376 | ||
79bc09fb | 3377 | /* Target hooks sometimes don't treat extra-constraint addresses as |
3378 | legitimate address_operands, so handle them specially. */ | |
69449463 | 3379 | if (insn_extra_address_constraint (cn) |
79bc09fb | 3380 | && satisfies_address_constraint_p (&ad, cn)) |
ea99c7a1 | 3381 | return change_p; |
ea99c7a1 | 3382 | |
497ba60f | 3383 | if (check_only_p) |
3384 | return change_p; | |
3385 | ||
1efe9e9d | 3386 | /* There are three cases where the shape of *AD.INNER may now be invalid: |
d9b69682 | 3387 | |
3388 | 1) the original address was valid, but either elimination or | |
c625778b | 3389 | equiv_address_substitution was applied and that made |
3390 | the address invalid. | |
d9b69682 | 3391 | |
3392 | 2) the address is an invalid symbolic address created by | |
c625778b | 3393 | force_const_to_mem. |
d9b69682 | 3394 | |
3395 | 3) the address is a frame address with an invalid offset. | |
3396 | ||
d03288b6 | 3397 | 4) the address is a frame address with an invalid base. |
3398 | ||
ea99c7a1 | 3399 | All these cases involve a non-autoinc address, so there is no |
3400 | point revalidating other types. */ | |
3401 | if (ad.autoinc_p || valid_address_p (&ad)) | |
c6a6cdaa | 3402 | return change_p; |
3403 | ||
d9b69682 | 3404 | /* Any index existed before LRA started, so we can assume that the |
3405 | presence and shape of the index is valid. */ | |
c6a6cdaa | 3406 | push_to_sequence (*before); |
ea99c7a1 | 3407 | lra_assert (ad.disp == ad.disp_term); |
1efe9e9d | 3408 | if (ad.base == NULL) |
c6a6cdaa | 3409 | { |
1efe9e9d | 3410 | if (ad.index == NULL) |
c6a6cdaa | 3411 | { |
401bd0c8 | 3412 | rtx_insn *insn; |
3413 | rtx_insn *last = get_last_insn (); | |
c6a6cdaa | 3414 | int code = -1; |
1efe9e9d | 3415 | enum reg_class cl = base_reg_class (ad.mode, ad.as, |
3416 | SCRATCH, SCRATCH); | |
ea99c7a1 | 3417 | rtx addr = *ad.inner; |
1efe9e9d | 3418 | |
ea99c7a1 | 3419 | new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "addr"); |
6cc3d6ec | 3420 | if (HAVE_lo_sum) |
3421 | { | |
6cc3d6ec | 3422 | /* addr => lo_sum (new_base, addr), case (2) above. */ |
3423 | insn = emit_insn (gen_rtx_SET | |
3424 | (new_reg, | |
3425 | gen_rtx_HIGH (Pmode, copy_rtx (addr)))); | |
3426 | code = recog_memoized (insn); | |
3427 | if (code >= 0) | |
3428 | { | |
3429 | *ad.inner = gen_rtx_LO_SUM (Pmode, new_reg, addr); | |
3430 | if (! valid_address_p (ad.mode, *ad.outer, ad.as)) | |
3431 | { | |
3432 | /* Try to put lo_sum into register. */ | |
3433 | insn = emit_insn (gen_rtx_SET | |
3434 | (new_reg, | |
3435 | gen_rtx_LO_SUM (Pmode, new_reg, addr))); | |
3436 | code = recog_memoized (insn); | |
3437 | if (code >= 0) | |
3438 | { | |
3439 | *ad.inner = new_reg; | |
3440 | if (! valid_address_p (ad.mode, *ad.outer, ad.as)) | |
3441 | { | |
3442 | *ad.inner = addr; | |
3443 | code = -1; | |
3444 | } | |
3445 | } | |
3446 | ||
3447 | } | |
3448 | } | |
3449 | if (code < 0) | |
3450 | delete_insns_since (last); | |
3451 | } | |
3452 | ||
c6a6cdaa | 3453 | if (code < 0) |
3454 | { | |
ea99c7a1 | 3455 | /* addr => new_base, case (2) above. */ |
3456 | lra_emit_move (new_reg, addr); | |
401bd0c8 | 3457 | |
3458 | for (insn = last == NULL_RTX ? get_insns () : NEXT_INSN (last); | |
3459 | insn != NULL_RTX; | |
3460 | insn = NEXT_INSN (insn)) | |
3461 | if (recog_memoized (insn) < 0) | |
3462 | break; | |
3463 | if (insn != NULL_RTX) | |
3464 | { | |
3465 | /* Do nothing if we cannot generate right insns. | |
67cf9b55 | 3466 | This is analogous to reload pass behavior. */ |
401bd0c8 | 3467 | delete_insns_since (last); |
3468 | end_sequence (); | |
3469 | return false; | |
3470 | } | |
ea99c7a1 | 3471 | *ad.inner = new_reg; |
c6a6cdaa | 3472 | } |
3473 | } | |
3474 | else | |
3475 | { | |
d9b69682 | 3476 | /* index * scale + disp => new base + index * scale, |
3477 | case (1) above. */ | |
1efe9e9d | 3478 | enum reg_class cl = base_reg_class (ad.mode, ad.as, PLUS, |
3479 | GET_CODE (*ad.index)); | |
c6a6cdaa | 3480 | |
3481 | lra_assert (INDEX_REG_CLASS != NO_REGS); | |
3482 | new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "disp"); | |
1efe9e9d | 3483 | lra_emit_move (new_reg, *ad.disp); |
3484 | *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), | |
3485 | new_reg, *ad.index); | |
c6a6cdaa | 3486 | } |
3487 | } | |
1efe9e9d | 3488 | else if (ad.index == NULL) |
c6a6cdaa | 3489 | { |
c625778b | 3490 | int regno; |
3491 | enum reg_class cl; | |
7f836b57 | 3492 | rtx set; |
3493 | rtx_insn *insns, *last_insn; | |
d03288b6 | 3494 | /* Try to reload base into register only if the base is invalid |
3495 | for the address but with valid offset, case (4) above. */ | |
3496 | start_sequence (); | |
3497 | new_reg = base_to_reg (&ad); | |
3498 | ||
d9b69682 | 3499 | /* base + disp => new base, cases (1) and (3) above. */ |
c6a6cdaa | 3500 | /* Another option would be to reload the displacement into an |
3501 | index register. However, postreload has code to optimize | |
3502 | address reloads that have the same base and different | |
3503 | displacements, so reloading into an index register would | |
3504 | not necessarily be a win. */ | |
d03288b6 | 3505 | if (new_reg == NULL_RTX) |
6cc181b3 | 3506 | { |
3507 | /* See if the target can split the displacement into a | |
3508 | legitimate new displacement from a local anchor. */ | |
3509 | gcc_assert (ad.disp == ad.disp_term); | |
3510 | poly_int64 orig_offset; | |
3511 | rtx offset1, offset2; | |
3512 | if (poly_int_rtx_p (*ad.disp, &orig_offset) | |
3513 | && targetm.legitimize_address_displacement (&offset1, &offset2, | |
3514 | orig_offset, | |
3515 | ad.mode)) | |
3516 | { | |
3517 | new_reg = base_plus_disp_to_reg (&ad, offset1); | |
3518 | new_reg = gen_rtx_PLUS (GET_MODE (new_reg), new_reg, offset2); | |
3519 | } | |
3520 | else | |
3521 | new_reg = base_plus_disp_to_reg (&ad, *ad.disp); | |
3522 | } | |
c625778b | 3523 | insns = get_insns (); |
3524 | last_insn = get_last_insn (); | |
3525 | /* If we generated at least two insns, try last insn source as | |
3526 | an address. If we succeed, we generate one less insn. */ | |
6cc181b3 | 3527 | if (REG_P (new_reg) |
3528 | && last_insn != insns | |
3529 | && (set = single_set (last_insn)) != NULL_RTX | |
c625778b | 3530 | && GET_CODE (SET_SRC (set)) == PLUS |
3531 | && REG_P (XEXP (SET_SRC (set), 0)) | |
3532 | && CONSTANT_P (XEXP (SET_SRC (set), 1))) | |
3533 | { | |
3534 | *ad.inner = SET_SRC (set); | |
3535 | if (valid_address_p (ad.mode, *ad.outer, ad.as)) | |
3536 | { | |
3537 | *ad.base_term = XEXP (SET_SRC (set), 0); | |
3538 | *ad.disp_term = XEXP (SET_SRC (set), 1); | |
3539 | cl = base_reg_class (ad.mode, ad.as, ad.base_outer_code, | |
3540 | get_index_code (&ad)); | |
3541 | regno = REGNO (*ad.base_term); | |
3542 | if (regno >= FIRST_PSEUDO_REGISTER | |
3543 | && cl != lra_get_allocno_class (regno)) | |
7619e612 | 3544 | lra_change_class (regno, cl, " Change to", true); |
c625778b | 3545 | new_reg = SET_SRC (set); |
3546 | delete_insns_since (PREV_INSN (last_insn)); | |
3547 | } | |
3548 | } | |
3549 | end_sequence (); | |
3550 | emit_insn (insns); | |
1efe9e9d | 3551 | *ad.inner = new_reg; |
c6a6cdaa | 3552 | } |
28f7a2af | 3553 | else if (ad.disp_term != NULL) |
c6a6cdaa | 3554 | { |
d9b69682 | 3555 | /* base + scale * index + disp => new base + scale * index, |
3556 | case (1) above. */ | |
6cc181b3 | 3557 | gcc_assert (ad.disp == ad.disp_term); |
3558 | new_reg = base_plus_disp_to_reg (&ad, *ad.disp); | |
1efe9e9d | 3559 | *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), |
3560 | new_reg, *ad.index); | |
c6a6cdaa | 3561 | } |
72234ee9 | 3562 | else if ((scale = get_index_scale (&ad)) == 1) |
bbf73e27 | 3563 | { |
3564 | /* The last transformation to one reg will be made in | |
3565 | curr_insn_transform function. */ | |
3566 | end_sequence (); | |
3567 | return false; | |
3568 | } | |
72234ee9 | 3569 | else if (scale != 0) |
28f7a2af | 3570 | { |
3571 | /* base + scale * index => base + new_reg, | |
3572 | case (1) above. | |
3573 | Index part of address may become invalid. For example, we | |
3574 | changed pseudo on the equivalent memory and a subreg of the | |
3575 | pseudo onto the memory of different mode for which the scale is | |
3576 | prohibitted. */ | |
3577 | new_reg = index_part_to_reg (&ad); | |
3578 | *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), | |
3579 | *ad.base_term, new_reg); | |
3580 | } | |
72234ee9 | 3581 | else |
3582 | { | |
3583 | enum reg_class cl = base_reg_class (ad.mode, ad.as, | |
3584 | SCRATCH, SCRATCH); | |
3585 | rtx addr = *ad.inner; | |
3586 | ||
3587 | new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "addr"); | |
3588 | /* addr => new_base. */ | |
3589 | lra_emit_move (new_reg, addr); | |
3590 | *ad.inner = new_reg; | |
3591 | } | |
c6a6cdaa | 3592 | *before = get_insns (); |
3593 | end_sequence (); | |
3594 | return true; | |
3595 | } | |
3596 | ||
497ba60f | 3597 | /* If CHECK_ONLY_P is false, do address reloads until it is necessary. |
3598 | Use process_address_1 as a helper function. Return true for any | |
3599 | RTL changes. | |
3600 | ||
3601 | If CHECK_ONLY_P is true, just check address correctness. Return | |
3602 | false if the address correct. */ | |
dcd5393f | 3603 | static bool |
497ba60f | 3604 | process_address (int nop, bool check_only_p, |
3605 | rtx_insn **before, rtx_insn **after) | |
dcd5393f | 3606 | { |
3607 | bool res = false; | |
3608 | ||
497ba60f | 3609 | while (process_address_1 (nop, check_only_p, before, after)) |
3610 | { | |
3611 | if (check_only_p) | |
3612 | return true; | |
3613 | res = true; | |
3614 | } | |
dcd5393f | 3615 | return res; |
3616 | } | |
3617 | ||
c6a6cdaa | 3618 | /* Emit insns to reload VALUE into a new register. VALUE is an |
3619 | auto-increment or auto-decrement RTX whose operand is a register or | |
3620 | memory location; so reloading involves incrementing that location. | |
3621 | IN is either identical to VALUE, or some cheaper place to reload | |
3622 | value being incremented/decremented from. | |
3623 | ||
3624 | INC_AMOUNT is the number to increment or decrement by (always | |
3625 | positive and ignored for POST_MODIFY/PRE_MODIFY). | |
3626 | ||
3627 | Return pseudo containing the result. */ | |
3628 | static rtx | |
3173f31b | 3629 | emit_inc (enum reg_class new_rclass, rtx in, rtx value, poly_int64 inc_amount) |
c6a6cdaa | 3630 | { |
3631 | /* REG or MEM to be copied and incremented. */ | |
3632 | rtx incloc = XEXP (value, 0); | |
3633 | /* Nonzero if increment after copying. */ | |
3634 | int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC | |
3635 | || GET_CODE (value) == POST_MODIFY); | |
7f836b57 | 3636 | rtx_insn *last; |
c6a6cdaa | 3637 | rtx inc; |
ed3e6e5d | 3638 | rtx_insn *add_insn; |
c6a6cdaa | 3639 | int code; |
3640 | rtx real_in = in == value ? incloc : in; | |
3641 | rtx result; | |
3642 | bool plus_p = true; | |
3643 | ||
3644 | if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY) | |
3645 | { | |
3646 | lra_assert (GET_CODE (XEXP (value, 1)) == PLUS | |
3647 | || GET_CODE (XEXP (value, 1)) == MINUS); | |
3648 | lra_assert (rtx_equal_p (XEXP (XEXP (value, 1), 0), XEXP (value, 0))); | |
3649 | plus_p = GET_CODE (XEXP (value, 1)) == PLUS; | |
3650 | inc = XEXP (XEXP (value, 1), 1); | |
3651 | } | |
3652 | else | |
3653 | { | |
3654 | if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC) | |
3655 | inc_amount = -inc_amount; | |
3656 | ||
3173f31b | 3657 | inc = gen_int_mode (inc_amount, GET_MODE (value)); |
c6a6cdaa | 3658 | } |
3659 | ||
3660 | if (! post && REG_P (incloc)) | |
3661 | result = incloc; | |
3662 | else | |
3663 | result = lra_create_new_reg (GET_MODE (value), value, new_rclass, | |
3664 | "INC/DEC result"); | |
3665 | ||
3666 | if (real_in != result) | |
3667 | { | |
3668 | /* First copy the location to the result register. */ | |
3669 | lra_assert (REG_P (result)); | |
3670 | emit_insn (gen_move_insn (result, real_in)); | |
3671 | } | |
3672 | ||
3673 | /* We suppose that there are insns to add/sub with the constant | |
3674 | increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the | |
3675 | old reload worked with this assumption. If the assumption | |
3676 | becomes wrong, we should use approach in function | |
3677 | base_plus_disp_to_reg. */ | |
3678 | if (in == value) | |
3679 | { | |
3680 | /* See if we can directly increment INCLOC. */ | |
3681 | last = get_last_insn (); | |
3682 | add_insn = emit_insn (plus_p | |
3683 | ? gen_add2_insn (incloc, inc) | |
3684 | : gen_sub2_insn (incloc, inc)); | |
3685 | ||
3686 | code = recog_memoized (add_insn); | |
3687 | if (code >= 0) | |
3688 | { | |
3689 | if (! post && result != incloc) | |
3690 | emit_insn (gen_move_insn (result, incloc)); | |
3691 | return result; | |
3692 | } | |
3693 | delete_insns_since (last); | |
3694 | } | |
3695 | ||
3696 | /* If couldn't do the increment directly, must increment in RESULT. | |
3697 | The way we do this depends on whether this is pre- or | |
3698 | post-increment. For pre-increment, copy INCLOC to the reload | |
3699 | register, increment it there, then save back. */ | |
3700 | if (! post) | |
3701 | { | |
3702 | if (real_in != result) | |
3703 | emit_insn (gen_move_insn (result, real_in)); | |
3704 | if (plus_p) | |
3705 | emit_insn (gen_add2_insn (result, inc)); | |
3706 | else | |
3707 | emit_insn (gen_sub2_insn (result, inc)); | |
3708 | if (result != incloc) | |
3709 | emit_insn (gen_move_insn (incloc, result)); | |
3710 | } | |
3711 | else | |
3712 | { | |
3713 | /* Post-increment. | |
3714 | ||
3715 | Because this might be a jump insn or a compare, and because | |
3716 | RESULT may not be available after the insn in an input | |
3717 | reload, we must do the incrementing before the insn being | |
3718 | reloaded for. | |
3719 | ||
3720 | We have already copied IN to RESULT. Increment the copy in | |
3721 | RESULT, save that back, then decrement RESULT so it has | |
3722 | the original value. */ | |
3723 | if (plus_p) | |
3724 | emit_insn (gen_add2_insn (result, inc)); | |
3725 | else | |
3726 | emit_insn (gen_sub2_insn (result, inc)); | |
3727 | emit_insn (gen_move_insn (incloc, result)); | |
3728 | /* Restore non-modified value for the result. We prefer this | |
3729 | way because it does not require an additional hard | |
3730 | register. */ | |
3731 | if (plus_p) | |
3732 | { | |
a4686d0a | 3733 | poly_int64 offset; |
3734 | if (poly_int_rtx_p (inc, &offset)) | |
d11aedc7 | 3735 | emit_insn (gen_add2_insn (result, |
a4686d0a | 3736 | gen_int_mode (-offset, |
d11aedc7 | 3737 | GET_MODE (result)))); |
c6a6cdaa | 3738 | else |
3739 | emit_insn (gen_sub2_insn (result, inc)); | |
3740 | } | |
3741 | else | |
3742 | emit_insn (gen_add2_insn (result, inc)); | |
3743 | } | |
3744 | return result; | |
3745 | } | |
3746 | ||
ea99c7a1 | 3747 | /* Return true if the current move insn does not need processing as we |
3748 | already know that it satisfies its constraints. */ | |
3749 | static bool | |
3750 | simple_move_p (void) | |
3751 | { | |
3752 | rtx dest, src; | |
3753 | enum reg_class dclass, sclass; | |
3754 | ||
3755 | lra_assert (curr_insn_set != NULL_RTX); | |
3756 | dest = SET_DEST (curr_insn_set); | |
3757 | src = SET_SRC (curr_insn_set); | |
532322d3 | 3758 | |
3759 | /* If the instruction has multiple sets we need to process it even if it | |
3760 | is single_set. This can happen if one or more of the SETs are dead. | |
3761 | See PR73650. */ | |
3762 | if (multiple_sets (curr_insn)) | |
3763 | return false; | |
3764 | ||
ea99c7a1 | 3765 | return ((dclass = get_op_class (dest)) != NO_REGS |
3766 | && (sclass = get_op_class (src)) != NO_REGS | |
3767 | /* The backend guarantees that register moves of cost 2 | |
3768 | never need reloads. */ | |
06d288a6 | 3769 | && targetm.register_move_cost (GET_MODE (src), sclass, dclass) == 2); |
ea99c7a1 | 3770 | } |
3771 | ||
c6a6cdaa | 3772 | /* Swap operands NOP and NOP + 1. */ |
3773 | static inline void | |
3774 | swap_operands (int nop) | |
3775 | { | |
dfcf26a5 | 3776 | std::swap (curr_operand_mode[nop], curr_operand_mode[nop + 1]); |
3777 | std::swap (original_subreg_reg_mode[nop], original_subreg_reg_mode[nop + 1]); | |
3778 | std::swap (*curr_id->operand_loc[nop], *curr_id->operand_loc[nop + 1]); | |
003000a4 | 3779 | std::swap (equiv_substition_p[nop], equiv_substition_p[nop + 1]); |
c6a6cdaa | 3780 | /* Swap the duplicates too. */ |
3781 | lra_update_dup (curr_id, nop); | |
3782 | lra_update_dup (curr_id, nop + 1); | |
3783 | } | |
3784 | ||
3785 | /* Main entry point of the constraint code: search the body of the | |
3786 | current insn to choose the best alternative. It is mimicking insn | |
3787 | alternative cost calculation model of former reload pass. That is | |
3788 | because machine descriptions were written to use this model. This | |
3789 | model can be changed in future. Make commutative operand exchange | |
3790 | if it is chosen. | |
3791 | ||
497ba60f | 3792 | if CHECK_ONLY_P is false, do RTL changes to satisfy the |
3793 | constraints. Return true if any change happened during function | |
3794 | call. | |
3795 | ||
3796 | If CHECK_ONLY_P is true then don't do any transformation. Just | |
3797 | check that the insn satisfies all constraints. If the insn does | |
3798 | not satisfy any constraint, return true. */ | |
c6a6cdaa | 3799 | static bool |
497ba60f | 3800 | curr_insn_transform (bool check_only_p) |
c6a6cdaa | 3801 | { |
3802 | int i, j, k; | |
3803 | int n_operands; | |
3804 | int n_alternatives; | |
dd083a02 | 3805 | int n_outputs; |
c6a6cdaa | 3806 | int commutative; |
3807 | signed char goal_alt_matched[MAX_RECOG_OPERANDS][MAX_RECOG_OPERANDS]; | |
aa3ce8ba | 3808 | signed char match_inputs[MAX_RECOG_OPERANDS + 1]; |
dd083a02 | 3809 | signed char outputs[MAX_RECOG_OPERANDS + 1]; |
7f836b57 | 3810 | rtx_insn *before, *after; |
c6a6cdaa | 3811 | bool alt_p = false; |
3812 | /* Flag that the insn has been changed through a transformation. */ | |
3813 | bool change_p; | |
3814 | bool sec_mem_p; | |
c6a6cdaa | 3815 | bool use_sec_mem_p; |
c6a6cdaa | 3816 | int max_regno_before; |
3817 | int reused_alternative_num; | |
3818 | ||
ea99c7a1 | 3819 | curr_insn_set = single_set (curr_insn); |
3820 | if (curr_insn_set != NULL_RTX && simple_move_p ()) | |
71d47a14 | 3821 | { |
3822 | /* We assume that the corresponding insn alternative has no | |
3823 | earlier clobbers. If it is not the case, don't define move | |
3824 | cost equal to 2 for the corresponding register classes. */ | |
3825 | lra_set_used_insn_alternative (curr_insn, LRA_NON_CLOBBERED_ALT); | |
3826 | return false; | |
3827 | } | |
ea99c7a1 | 3828 | |
c6a6cdaa | 3829 | no_input_reloads_p = no_output_reloads_p = false; |
3830 | goal_alt_number = -1; | |
ea99c7a1 | 3831 | change_p = sec_mem_p = false; |
c6a6cdaa | 3832 | /* JUMP_INSNs and CALL_INSNs are not allowed to have any output |
3833 | reloads; neither are insns that SET cc0. Insns that use CC0 are | |
3834 | not allowed to have any input reloads. */ | |
3835 | if (JUMP_P (curr_insn) || CALL_P (curr_insn)) | |
3836 | no_output_reloads_p = true; | |
3837 | ||
ff900b8e | 3838 | if (HAVE_cc0 && reg_referenced_p (cc0_rtx, PATTERN (curr_insn))) |
c6a6cdaa | 3839 | no_input_reloads_p = true; |
ff900b8e | 3840 | if (HAVE_cc0 && reg_set_p (cc0_rtx, PATTERN (curr_insn))) |
c6a6cdaa | 3841 | no_output_reloads_p = true; |
c6a6cdaa | 3842 | |
3843 | n_operands = curr_static_id->n_operands; | |
3844 | n_alternatives = curr_static_id->n_alternatives; | |
3845 | ||
3846 | /* Just return "no reloads" if insn has no operands with | |
3847 | constraints. */ | |
3848 | if (n_operands == 0 || n_alternatives == 0) | |
3849 | return false; | |
3850 | ||
3851 | max_regno_before = max_reg_num (); | |
3852 | ||
3853 | for (i = 0; i < n_operands; i++) | |
3854 | { | |
3855 | goal_alt_matched[i][0] = -1; | |
3856 | goal_alt_matches[i] = -1; | |
3857 | } | |
3858 | ||
3859 | commutative = curr_static_id->commutative; | |
3860 | ||
3861 | /* Now see what we need for pseudos that didn't get hard regs or got | |
3862 | the wrong kind of hard reg. For this, we must consider all the | |
3863 | operands together against the register constraints. */ | |
3864 | ||
4b3aba76 | 3865 | best_losers = best_overall = INT_MAX; |
273c330a | 3866 | best_reload_sum = 0; |
c6a6cdaa | 3867 | |
3868 | curr_swapped = false; | |
3869 | goal_alt_swapped = false; | |
3870 | ||
497ba60f | 3871 | if (! check_only_p) |
3872 | /* Make equivalence substitution and memory subreg elimination | |
3873 | before address processing because an address legitimacy can | |
3874 | depend on memory mode. */ | |
3875 | for (i = 0; i < n_operands; i++) | |
3876 | { | |
af121a86 | 3877 | rtx op, subst, old; |
497ba60f | 3878 | bool op_change_p = false; |
af121a86 | 3879 | |
3880 | if (curr_static_id->operand[i].is_operator) | |
3881 | continue; | |
497ba60f | 3882 | |
af121a86 | 3883 | old = op = *curr_id->operand_loc[i]; |
497ba60f | 3884 | if (GET_CODE (old) == SUBREG) |
3885 | old = SUBREG_REG (old); | |
3886 | subst = get_equiv_with_elimination (old, curr_insn); | |
1aae95ec | 3887 | original_subreg_reg_mode[i] = VOIDmode; |
003000a4 | 3888 | equiv_substition_p[i] = false; |
497ba60f | 3889 | if (subst != old) |
3890 | { | |
003000a4 | 3891 | equiv_substition_p[i] = true; |
497ba60f | 3892 | subst = copy_rtx (subst); |
3893 | lra_assert (REG_P (old)); | |
1aae95ec | 3894 | if (GET_CODE (op) != SUBREG) |
497ba60f | 3895 | *curr_id->operand_loc[i] = subst; |
1aae95ec | 3896 | else |
3897 | { | |
3898 | SUBREG_REG (op) = subst; | |
3899 | if (GET_MODE (subst) == VOIDmode) | |
3900 | original_subreg_reg_mode[i] = GET_MODE (old); | |
3901 | } | |
497ba60f | 3902 | if (lra_dump_file != NULL) |
3903 | { | |
3904 | fprintf (lra_dump_file, | |
3905 | "Changing pseudo %d in operand %i of insn %u on equiv ", | |
3906 | REGNO (old), i, INSN_UID (curr_insn)); | |
3907 | dump_value_slim (lra_dump_file, subst, 1); | |
1aae95ec | 3908 | fprintf (lra_dump_file, "\n"); |
497ba60f | 3909 | } |
3910 | op_change_p = change_p = true; | |
3911 | } | |
3912 | if (simplify_operand_subreg (i, GET_MODE (old)) || op_change_p) | |
3913 | { | |
3914 | change_p = true; | |
3915 | lra_update_dup (curr_id, i); | |
3916 | } | |
3917 | } | |
c6a6cdaa | 3918 | |
3919 | /* Reload address registers and displacements. We do it before | |
3920 | finding an alternative because of memory constraints. */ | |
7f836b57 | 3921 | before = after = NULL; |
c6a6cdaa | 3922 | for (i = 0; i < n_operands; i++) |
3923 | if (! curr_static_id->operand[i].is_operator | |
497ba60f | 3924 | && process_address (i, check_only_p, &before, &after)) |
c6a6cdaa | 3925 | { |
497ba60f | 3926 | if (check_only_p) |
3927 | return true; | |
c6a6cdaa | 3928 | change_p = true; |
3929 | lra_update_dup (curr_id, i); | |
3930 | } | |
dcd5393f | 3931 | |
c6a6cdaa | 3932 | if (change_p) |
3933 | /* If we've changed the instruction then any alternative that | |
3934 | we chose previously may no longer be valid. */ | |
71d47a14 | 3935 | lra_set_used_insn_alternative (curr_insn, LRA_UNKNOWN_ALT); |
c6a6cdaa | 3936 | |
497ba60f | 3937 | if (! check_only_p && curr_insn_set != NULL_RTX |
ea99c7a1 | 3938 | && check_and_process_move (&change_p, &sec_mem_p)) |
3939 | return change_p; | |
3940 | ||
c6a6cdaa | 3941 | try_swapped: |
3942 | ||
71d47a14 | 3943 | reused_alternative_num = check_only_p ? LRA_UNKNOWN_ALT : curr_id->used_insn_alternative; |
c6a6cdaa | 3944 | if (lra_dump_file != NULL && reused_alternative_num >= 0) |
3945 | fprintf (lra_dump_file, "Reusing alternative %d for insn #%u\n", | |
3946 | reused_alternative_num, INSN_UID (curr_insn)); | |
3947 | ||
3948 | if (process_alt_operands (reused_alternative_num)) | |
3949 | alt_p = true; | |
3950 | ||
497ba60f | 3951 | if (check_only_p) |
3952 | return ! alt_p || best_losers != 0; | |
3953 | ||
c6a6cdaa | 3954 | /* If insn is commutative (it's safe to exchange a certain pair of |
3955 | operands) then we need to try each alternative twice, the second | |
3956 | time matching those two operands as if we had exchanged them. To | |
3957 | do this, really exchange them in operands. | |
3958 | ||
3959 | If we have just tried the alternatives the second time, return | |
3960 | operands to normal and drop through. */ | |
3961 | ||
3962 | if (reused_alternative_num < 0 && commutative >= 0) | |
3963 | { | |
3964 | curr_swapped = !curr_swapped; | |
3965 | if (curr_swapped) | |
3966 | { | |
3967 | swap_operands (commutative); | |
3968 | goto try_swapped; | |
3969 | } | |
3970 | else | |
3971 | swap_operands (commutative); | |
3972 | } | |
3973 | ||
c6a6cdaa | 3974 | if (! alt_p && ! sec_mem_p) |
3975 | { | |
3976 | /* No alternative works with reloads?? */ | |
3977 | if (INSN_CODE (curr_insn) >= 0) | |
3978 | fatal_insn ("unable to generate reloads for:", curr_insn); | |
3979 | error_for_asm (curr_insn, | |
3980 | "inconsistent operand constraints in an %<asm%>"); | |
3923c63e | 3981 | lra_asm_error_p = true; |
127e79a7 | 3982 | /* Avoid further trouble with this insn. Don't generate use |
3983 | pattern here as we could use the insn SP offset. */ | |
3984 | lra_set_insn_deleted (curr_insn); | |
c6a6cdaa | 3985 | return true; |
3986 | } | |
3987 | ||
3988 | /* If the best alternative is with operands 1 and 2 swapped, swap | |
3989 | them. Update the operand numbers of any reloads already | |
3990 | pushed. */ | |
3991 | ||
3992 | if (goal_alt_swapped) | |
3993 | { | |
3994 | if (lra_dump_file != NULL) | |
3995 | fprintf (lra_dump_file, " Commutative operand exchange in insn %u\n", | |
3996 | INSN_UID (curr_insn)); | |
3997 | ||
3998 | /* Swap the duplicates too. */ | |
3999 | swap_operands (commutative); | |
4000 | change_p = true; | |
4001 | } | |
4002 | ||
c836e75b | 4003 | /* Some targets' TARGET_SECONDARY_MEMORY_NEEDED (e.g. x86) are defined |
c6a6cdaa | 4004 | too conservatively. So we use the secondary memory only if there |
4005 | is no any alternative without reloads. */ | |
4006 | use_sec_mem_p = false; | |
4007 | if (! alt_p) | |
4008 | use_sec_mem_p = true; | |
4009 | else if (sec_mem_p) | |
4010 | { | |
4011 | for (i = 0; i < n_operands; i++) | |
4012 | if (! goal_alt_win[i] && ! goal_alt_match_win[i]) | |
4013 | break; | |
4014 | use_sec_mem_p = i < n_operands; | |
4015 | } | |
4016 | ||
4017 | if (use_sec_mem_p) | |
4018 | { | |
ec4ec95a | 4019 | int in = -1, out = -1; |
e0420317 | 4020 | rtx new_reg, src, dest, rld; |
3754d046 | 4021 | machine_mode sec_mode, rld_mode; |
c6a6cdaa | 4022 | |
ec4ec95a | 4023 | lra_assert (curr_insn_set != NULL_RTX && sec_mem_p); |
4024 | dest = SET_DEST (curr_insn_set); | |
4025 | src = SET_SRC (curr_insn_set); | |
4026 | for (i = 0; i < n_operands; i++) | |
4027 | if (*curr_id->operand_loc[i] == dest) | |
4028 | out = i; | |
4029 | else if (*curr_id->operand_loc[i] == src) | |
4030 | in = i; | |
4031 | for (i = 0; i < curr_static_id->n_dups; i++) | |
4032 | if (out < 0 && *curr_id->dup_loc[i] == dest) | |
4033 | out = curr_static_id->dup_num[i]; | |
4034 | else if (in < 0 && *curr_id->dup_loc[i] == src) | |
4035 | in = curr_static_id->dup_num[i]; | |
4036 | lra_assert (out >= 0 && in >= 0 | |
4037 | && curr_static_id->operand[out].type == OP_OUT | |
4038 | && curr_static_id->operand[in].type == OP_IN); | |
974534ab | 4039 | rld = partial_subreg_p (GET_MODE (src), GET_MODE (dest)) ? src : dest; |
c47331e3 | 4040 | rld_mode = GET_MODE (rld); |
1041f930 | 4041 | sec_mode = targetm.secondary_memory_needed_mode (rld_mode); |
c6a6cdaa | 4042 | new_reg = lra_create_new_reg (sec_mode, NULL_RTX, |
4043 | NO_REGS, "secondary"); | |
4044 | /* If the mode is changed, it should be wider. */ | |
974534ab | 4045 | lra_assert (!partial_subreg_p (sec_mode, rld_mode)); |
e0420317 | 4046 | if (sec_mode != rld_mode) |
4047 | { | |
4048 | /* If the target says specifically to use another mode for | |
f4d3c071 | 4049 | secondary memory moves we cannot reuse the original |
e0420317 | 4050 | insn. */ |
cc0dc61b | 4051 | after = emit_spill_move (false, new_reg, dest); |
7f836b57 | 4052 | lra_process_new_insns (curr_insn, NULL, after, |
cc0dc61b | 4053 | "Inserting the sec. move"); |
4054 | /* We may have non null BEFORE here (e.g. after address | |
4055 | processing. */ | |
4056 | push_to_sequence (before); | |
4057 | before = emit_spill_move (true, new_reg, src); | |
4058 | emit_insn (before); | |
4059 | before = get_insns (); | |
4060 | end_sequence (); | |
7f836b57 | 4061 | lra_process_new_insns (curr_insn, before, NULL, "Changing on"); |
cc0dc61b | 4062 | lra_set_insn_deleted (curr_insn); |
4063 | } | |
e0420317 | 4064 | else if (dest == rld) |
cc0dc61b | 4065 | { |
ec4ec95a | 4066 | *curr_id->operand_loc[out] = new_reg; |
4067 | lra_update_dup (curr_id, out); | |
c47331e3 | 4068 | after = emit_spill_move (false, new_reg, dest); |
7f836b57 | 4069 | lra_process_new_insns (curr_insn, NULL, after, |
c47331e3 | 4070 | "Inserting the sec. move"); |
4071 | } | |
4072 | else | |
4073 | { | |
ec4ec95a | 4074 | *curr_id->operand_loc[in] = new_reg; |
4075 | lra_update_dup (curr_id, in); | |
cc0dc61b | 4076 | /* See comments above. */ |
4077 | push_to_sequence (before); | |
c47331e3 | 4078 | before = emit_spill_move (true, new_reg, src); |
cc0dc61b | 4079 | emit_insn (before); |
4080 | before = get_insns (); | |
4081 | end_sequence (); | |
7f836b57 | 4082 | lra_process_new_insns (curr_insn, before, NULL, |
c47331e3 | 4083 | "Inserting the sec. move"); |
4084 | } | |
4085 | lra_update_insn_regno_info (curr_insn); | |
c6a6cdaa | 4086 | return true; |
4087 | } | |
c6a6cdaa | 4088 | |
4089 | lra_assert (goal_alt_number >= 0); | |
4090 | lra_set_used_insn_alternative (curr_insn, goal_alt_number); | |
4091 | ||
4092 | if (lra_dump_file != NULL) | |
4093 | { | |
4094 | const char *p; | |
4095 | ||
4096 | fprintf (lra_dump_file, " Choosing alt %d in insn %u:", | |
4097 | goal_alt_number, INSN_UID (curr_insn)); | |
4098 | for (i = 0; i < n_operands; i++) | |
4099 | { | |
4100 | p = (curr_static_id->operand_alternative | |
4101 | [goal_alt_number * n_operands + i].constraint); | |
4102 | if (*p == '\0') | |
4103 | continue; | |
4104 | fprintf (lra_dump_file, " (%d) ", i); | |
4105 | for (; *p != '\0' && *p != ',' && *p != '#'; p++) | |
4106 | fputc (*p, lra_dump_file); | |
4107 | } | |
273c330a | 4108 | if (INSN_CODE (curr_insn) >= 0 |
4109 | && (p = get_insn_name (INSN_CODE (curr_insn))) != NULL) | |
4110 | fprintf (lra_dump_file, " {%s}", p); | |
a4686d0a | 4111 | if (maybe_ne (curr_id->sp_offset, 0)) |
4112 | { | |
4113 | fprintf (lra_dump_file, " (sp_off="); | |
4114 | print_dec (curr_id->sp_offset, lra_dump_file); | |
4115 | fprintf (lra_dump_file, ")"); | |
4116 | } | |
4117 | fprintf (lra_dump_file, "\n"); | |
c6a6cdaa | 4118 | } |
4119 | ||
4120 | /* Right now, for any pair of operands I and J that are required to | |
4121 | match, with J < I, goal_alt_matches[I] is J. Add I to | |
4122 | goal_alt_matched[J]. */ | |
1a8f8886 | 4123 | |
c6a6cdaa | 4124 | for (i = 0; i < n_operands; i++) |
4125 | if ((j = goal_alt_matches[i]) >= 0) | |
4126 | { | |
4127 | for (k = 0; goal_alt_matched[j][k] >= 0; k++) | |
4128 | ; | |
4129 | /* We allow matching one output operand and several input | |
4130 | operands. */ | |
4131 | lra_assert (k == 0 | |
4132 | || (curr_static_id->operand[j].type == OP_OUT | |
4133 | && curr_static_id->operand[i].type == OP_IN | |
4134 | && (curr_static_id->operand | |
4135 | [goal_alt_matched[j][0]].type == OP_IN))); | |
4136 | goal_alt_matched[j][k] = i; | |
4137 | goal_alt_matched[j][k + 1] = -1; | |
4138 | } | |
1a8f8886 | 4139 | |
c6a6cdaa | 4140 | for (i = 0; i < n_operands; i++) |
4141 | goal_alt_win[i] |= goal_alt_match_win[i]; | |
1a8f8886 | 4142 | |
c6a6cdaa | 4143 | /* Any constants that aren't allowed and can't be reloaded into |
4144 | registers are here changed into memory references. */ | |
4145 | for (i = 0; i < n_operands; i++) | |
4146 | if (goal_alt_win[i]) | |
4147 | { | |
4148 | int regno; | |
4149 | enum reg_class new_class; | |
4150 | rtx reg = *curr_id->operand_loc[i]; | |
4151 | ||
4152 | if (GET_CODE (reg) == SUBREG) | |
4153 | reg = SUBREG_REG (reg); | |
1a8f8886 | 4154 | |
c6a6cdaa | 4155 | if (REG_P (reg) && (regno = REGNO (reg)) >= FIRST_PSEUDO_REGISTER) |
4156 | { | |
4157 | bool ok_p = in_class_p (reg, goal_alt[i], &new_class); | |
4158 | ||
4159 | if (new_class != NO_REGS && get_reg_class (regno) != new_class) | |
4160 | { | |
4161 | lra_assert (ok_p); | |
7619e612 | 4162 | lra_change_class (regno, new_class, " Change to", true); |
c6a6cdaa | 4163 | } |
4164 | } | |
4165 | } | |
4166 | else | |
4167 | { | |
4168 | const char *constraint; | |
4169 | char c; | |
4170 | rtx op = *curr_id->operand_loc[i]; | |
4171 | rtx subreg = NULL_RTX; | |
3754d046 | 4172 | machine_mode mode = curr_operand_mode[i]; |
1a8f8886 | 4173 | |
c6a6cdaa | 4174 | if (GET_CODE (op) == SUBREG) |
4175 | { | |
4176 | subreg = op; | |
4177 | op = SUBREG_REG (op); | |
4178 | mode = GET_MODE (op); | |
4179 | } | |
1a8f8886 | 4180 | |
c6a6cdaa | 4181 | if (CONST_POOL_OK_P (mode, op) |
4182 | && ((targetm.preferred_reload_class | |
4183 | (op, (enum reg_class) goal_alt[i]) == NO_REGS) | |
4184 | || no_input_reloads_p)) | |
4185 | { | |
4186 | rtx tem = force_const_mem (mode, op); | |
1a8f8886 | 4187 | |
c6a6cdaa | 4188 | change_p = true; |
4189 | if (subreg != NULL_RTX) | |
4190 | tem = gen_rtx_SUBREG (mode, tem, SUBREG_BYTE (subreg)); | |
1a8f8886 | 4191 | |
c6a6cdaa | 4192 | *curr_id->operand_loc[i] = tem; |
4193 | lra_update_dup (curr_id, i); | |
497ba60f | 4194 | process_address (i, false, &before, &after); |
1a8f8886 | 4195 | |
c6a6cdaa | 4196 | /* If the alternative accepts constant pool refs directly |
4197 | there will be no reload needed at all. */ | |
4198 | if (subreg != NULL_RTX) | |
4199 | continue; | |
4200 | /* Skip alternatives before the one requested. */ | |
4201 | constraint = (curr_static_id->operand_alternative | |
4202 | [goal_alt_number * n_operands + i].constraint); | |
4203 | for (; | |
4204 | (c = *constraint) && c != ',' && c != '#'; | |
4205 | constraint += CONSTRAINT_LEN (c, constraint)) | |
4206 | { | |
79bc09fb | 4207 | enum constraint_num cn = lookup_constraint (constraint); |
6b3b345a | 4208 | if ((insn_extra_memory_constraint (cn) |
4209 | || insn_extra_special_memory_constraint (cn)) | |
79bc09fb | 4210 | && satisfies_memory_constraint_p (tem, cn)) |
c6a6cdaa | 4211 | break; |
c6a6cdaa | 4212 | } |
4213 | if (c == '\0' || c == ',' || c == '#') | |
4214 | continue; | |
1a8f8886 | 4215 | |
c6a6cdaa | 4216 | goal_alt_win[i] = true; |
4217 | } | |
4218 | } | |
1a8f8886 | 4219 | |
dd083a02 | 4220 | n_outputs = 0; |
4221 | outputs[0] = -1; | |
c6a6cdaa | 4222 | for (i = 0; i < n_operands; i++) |
4223 | { | |
1f3a048a | 4224 | int regno; |
4225 | bool optional_p = false; | |
c6a6cdaa | 4226 | rtx old, new_reg; |
4227 | rtx op = *curr_id->operand_loc[i]; | |
4228 | ||
4229 | if (goal_alt_win[i]) | |
4230 | { | |
4231 | if (goal_alt[i] == NO_REGS | |
4232 | && REG_P (op) | |
4233 | /* When we assign NO_REGS it means that we will not | |
4234 | assign a hard register to the scratch pseudo by | |
4235 | assigment pass and the scratch pseudo will be | |
4236 | spilled. Spilled scratch pseudos are transformed | |
4237 | back to scratches at the LRA end. */ | |
c2b94990 | 4238 | && lra_former_scratch_operand_p (curr_insn, i) |
4239 | && lra_former_scratch_p (REGNO (op))) | |
f7c98bb1 | 4240 | { |
4241 | int regno = REGNO (op); | |
7619e612 | 4242 | lra_change_class (regno, NO_REGS, " Change to", true); |
f7c98bb1 | 4243 | if (lra_get_regno_hard_regno (regno) >= 0) |
4244 | /* We don't have to mark all insn affected by the | |
4245 | spilled pseudo as there is only one such insn, the | |
4246 | current one. */ | |
4247 | reg_renumber[regno] = -1; | |
c2b94990 | 4248 | lra_assert (bitmap_single_bit_set_p |
4249 | (&lra_reg_info[REGNO (op)].insn_bitmap)); | |
f7c98bb1 | 4250 | } |
1f3a048a | 4251 | /* We can do an optional reload. If the pseudo got a hard |
4252 | reg, we might improve the code through inheritance. If | |
4253 | it does not get a hard register we coalesce memory/memory | |
4254 | moves later. Ignore move insns to avoid cycling. */ | |
267200f3 | 4255 | if (! lra_simple_p |
1f3a048a | 4256 | && lra_undo_inheritance_iter < LRA_MAX_INHERITANCE_PASSES |
4257 | && goal_alt[i] != NO_REGS && REG_P (op) | |
4258 | && (regno = REGNO (op)) >= FIRST_PSEUDO_REGISTER | |
7619e612 | 4259 | && regno < new_regno_start |
267200f3 | 4260 | && ! lra_former_scratch_p (regno) |
1f3a048a | 4261 | && reg_renumber[regno] < 0 |
25cd984c | 4262 | /* Check that the optional reload pseudo will be able to |
4263 | hold given mode value. */ | |
4264 | && ! (prohibited_class_reg_set_mode_p | |
4265 | (goal_alt[i], reg_class_contents[goal_alt[i]], | |
4266 | PSEUDO_REGNO_MODE (regno))) | |
1f3a048a | 4267 | && (curr_insn_set == NULL_RTX |
267200f3 | 4268 | || !((REG_P (SET_SRC (curr_insn_set)) |
4269 | || MEM_P (SET_SRC (curr_insn_set)) | |
4270 | || GET_CODE (SET_SRC (curr_insn_set)) == SUBREG) | |
4271 | && (REG_P (SET_DEST (curr_insn_set)) | |
4272 | || MEM_P (SET_DEST (curr_insn_set)) | |
4273 | || GET_CODE (SET_DEST (curr_insn_set)) == SUBREG)))) | |
1f3a048a | 4274 | optional_p = true; |
74fde7b5 | 4275 | else if (goal_alt_matched[i][0] != -1 |
4276 | && curr_static_id->operand[i].type == OP_OUT | |
4277 | && (curr_static_id->operand_alternative | |
4b2731eb | 4278 | [goal_alt_number * n_operands + i].earlyclobber) |
4279 | && REG_P (op)) | |
74fde7b5 | 4280 | { |
4b2731eb | 4281 | for (j = 0; goal_alt_matched[i][j] != -1; j++) |
4282 | { | |
4283 | rtx op2 = *curr_id->operand_loc[goal_alt_matched[i][j]]; | |
4284 | ||
4285 | if (REG_P (op2) && REGNO (op) != REGNO (op2)) | |
4286 | break; | |
4287 | } | |
4288 | if (goal_alt_matched[i][j] != -1) | |
4289 | { | |
4290 | /* Generate reloads for different output and matched | |
4291 | input registers. This is the easiest way to avoid | |
4292 | creation of non-existing register conflicts in | |
4293 | lra-lives.c. */ | |
4294 | match_reload (i, goal_alt_matched[i], outputs, goal_alt[i], &before, | |
4295 | &after, TRUE); | |
4296 | outputs[n_outputs++] = i; | |
4297 | outputs[n_outputs] = -1; | |
4298 | } | |
74fde7b5 | 4299 | continue; |
4300 | } | |
1f3a048a | 4301 | else |
4302 | continue; | |
c6a6cdaa | 4303 | } |
1a8f8886 | 4304 | |
c6a6cdaa | 4305 | /* Operands that match previous ones have already been handled. */ |
4306 | if (goal_alt_matches[i] >= 0) | |
4307 | continue; | |
4308 | ||
4309 | /* We should not have an operand with a non-offsettable address | |
4310 | appearing where an offsettable address will do. It also may | |
4311 | be a case when the address should be special in other words | |
4312 | not a general one (e.g. it needs no index reg). */ | |
4313 | if (goal_alt_matched[i][0] == -1 && goal_alt_offmemok[i] && MEM_P (op)) | |
4314 | { | |
4315 | enum reg_class rclass; | |
4316 | rtx *loc = &XEXP (op, 0); | |
4317 | enum rtx_code code = GET_CODE (*loc); | |
4318 | ||
4319 | push_to_sequence (before); | |
4320 | rclass = base_reg_class (GET_MODE (op), MEM_ADDR_SPACE (op), | |
4321 | MEM, SCRATCH); | |
4322 | if (GET_RTX_CLASS (code) == RTX_AUTOINC) | |
4323 | new_reg = emit_inc (rclass, *loc, *loc, | |
4324 | /* This value does not matter for MODIFY. */ | |
4325 | GET_MODE_SIZE (GET_MODE (op))); | |
6cadc8f7 | 4326 | else if (get_reload_reg (OP_IN, Pmode, *loc, rclass, FALSE, |
c6a6cdaa | 4327 | "offsetable address", &new_reg)) |
27137b2a | 4328 | { |
4329 | rtx addr = *loc; | |
4330 | enum rtx_code code = GET_CODE (addr); | |
4331 | ||
4332 | if (code == AND && CONST_INT_P (XEXP (addr, 1))) | |
4333 | /* (and ... (const_int -X)) is used to align to X bytes. */ | |
4334 | addr = XEXP (*loc, 0); | |
4335 | lra_emit_move (new_reg, addr); | |
4336 | if (addr != *loc) | |
4337 | emit_move_insn (new_reg, gen_rtx_AND (GET_MODE (new_reg), new_reg, XEXP (*loc, 1))); | |
4338 | } | |
c6a6cdaa | 4339 | before = get_insns (); |
4340 | end_sequence (); | |
4341 | *loc = new_reg; | |
4342 | lra_update_dup (curr_id, i); | |
4343 | } | |
4344 | else if (goal_alt_matched[i][0] == -1) | |
4345 | { | |
3754d046 | 4346 | machine_mode mode; |
c6a6cdaa | 4347 | rtx reg, *loc; |
9edf7ea8 | 4348 | int hard_regno; |
c6a6cdaa | 4349 | enum op_type type = curr_static_id->operand[i].type; |
4350 | ||
4351 | loc = curr_id->operand_loc[i]; | |
4352 | mode = curr_operand_mode[i]; | |
4353 | if (GET_CODE (*loc) == SUBREG) | |
4354 | { | |
4355 | reg = SUBREG_REG (*loc); | |
9edf7ea8 | 4356 | poly_int64 byte = SUBREG_BYTE (*loc); |
c6a6cdaa | 4357 | if (REG_P (reg) |
5cbb8e6b | 4358 | /* Strict_low_part requires reloading the register and not |
4359 | just the subreg. Likewise for a strict subreg no wider | |
4360 | than a word for WORD_REGISTER_OPERATIONS targets. */ | |
c6a6cdaa | 4361 | && (curr_static_id->operand[i].strict_low |
d0257d43 | 4362 | || (!paradoxical_subreg_p (mode, GET_MODE (reg)) |
c6a6cdaa | 4363 | && (hard_regno |
4364 | = get_try_hard_regno (REGNO (reg))) >= 0 | |
4365 | && (simplify_subreg_regno | |
4366 | (hard_regno, | |
4367 | GET_MODE (reg), byte, mode) < 0) | |
4368 | && (goal_alt[i] == NO_REGS | |
4369 | || (simplify_subreg_regno | |
4370 | (ira_class_hard_regs[goal_alt[i]][0], | |
5cbb8e6b | 4371 | GET_MODE (reg), byte, mode) >= 0))) |
3cedfe34 | 4372 | || (partial_subreg_p (mode, GET_MODE (reg)) |
52acb7ae | 4373 | && known_le (GET_MODE_SIZE (GET_MODE (reg)), |
4374 | UNITS_PER_WORD) | |
5cbb8e6b | 4375 | && WORD_REGISTER_OPERATIONS))) |
c6a6cdaa | 4376 | { |
55996ba4 | 4377 | /* An OP_INOUT is required when reloading a subreg of a |
4378 | mode wider than a word to ensure that data beyond the | |
4379 | word being reloaded is preserved. Also automatically | |
4380 | ensure that strict_low_part reloads are made into | |
4381 | OP_INOUT which should already be true from the backend | |
4382 | constraints. */ | |
4383 | if (type == OP_OUT | |
4384 | && (curr_static_id->operand[i].strict_low | |
9f2c0e68 | 4385 | || read_modify_subreg_p (*loc))) |
90f51e67 | 4386 | type = OP_INOUT; |
c6a6cdaa | 4387 | loc = &SUBREG_REG (*loc); |
4388 | mode = GET_MODE (*loc); | |
4389 | } | |
4390 | } | |
4391 | old = *loc; | |
6cadc8f7 | 4392 | if (get_reload_reg (type, mode, old, goal_alt[i], |
4393 | loc != curr_id->operand_loc[i], "", &new_reg) | |
c6a6cdaa | 4394 | && type != OP_OUT) |
4395 | { | |
4396 | push_to_sequence (before); | |
4397 | lra_emit_move (new_reg, old); | |
4398 | before = get_insns (); | |
4399 | end_sequence (); | |
4400 | } | |
4401 | *loc = new_reg; | |
4402 | if (type != OP_IN | |
4403 | && find_reg_note (curr_insn, REG_UNUSED, old) == NULL_RTX) | |
4404 | { | |
4405 | start_sequence (); | |
4406 | lra_emit_move (type == OP_INOUT ? copy_rtx (old) : old, new_reg); | |
4407 | emit_insn (after); | |
4408 | after = get_insns (); | |
4409 | end_sequence (); | |
4410 | *loc = new_reg; | |
4411 | } | |
4412 | for (j = 0; j < goal_alt_dont_inherit_ops_num; j++) | |
4413 | if (goal_alt_dont_inherit_ops[j] == i) | |
4414 | { | |
4415 | lra_set_regno_unique_value (REGNO (new_reg)); | |
4416 | break; | |
4417 | } | |
4418 | lra_update_dup (curr_id, i); | |
4419 | } | |
4420 | else if (curr_static_id->operand[i].type == OP_IN | |
4421 | && (curr_static_id->operand[goal_alt_matched[i][0]].type | |
b8b2688e | 4422 | == OP_OUT |
4423 | || (curr_static_id->operand[goal_alt_matched[i][0]].type | |
4424 | == OP_INOUT | |
4425 | && (operands_match_p | |
4426 | (*curr_id->operand_loc[i], | |
4427 | *curr_id->operand_loc[goal_alt_matched[i][0]], | |
4428 | -1))))) | |
c6a6cdaa | 4429 | { |
aa3ce8ba | 4430 | /* generate reloads for input and matched outputs. */ |
4431 | match_inputs[0] = i; | |
4432 | match_inputs[1] = -1; | |
dd083a02 | 4433 | match_reload (goal_alt_matched[i][0], match_inputs, outputs, |
72460f4d | 4434 | goal_alt[i], &before, &after, |
4435 | curr_static_id->operand_alternative | |
4436 | [goal_alt_number * n_operands + goal_alt_matched[i][0]] | |
4437 | .earlyclobber); | |
c6a6cdaa | 4438 | } |
b8b2688e | 4439 | else if ((curr_static_id->operand[i].type == OP_OUT |
4440 | || (curr_static_id->operand[i].type == OP_INOUT | |
4441 | && (operands_match_p | |
4442 | (*curr_id->operand_loc[i], | |
4443 | *curr_id->operand_loc[goal_alt_matched[i][0]], | |
4444 | -1)))) | |
c6a6cdaa | 4445 | && (curr_static_id->operand[goal_alt_matched[i][0]].type |
b8b2688e | 4446 | == OP_IN)) |
aa3ce8ba | 4447 | /* Generate reloads for output and matched inputs. */ |
dd083a02 | 4448 | match_reload (i, goal_alt_matched[i], outputs, goal_alt[i], &before, |
4449 | &after, curr_static_id->operand_alternative | |
4450 | [goal_alt_number * n_operands + i].earlyclobber); | |
aa3ce8ba | 4451 | else if (curr_static_id->operand[i].type == OP_IN |
4452 | && (curr_static_id->operand[goal_alt_matched[i][0]].type | |
4453 | == OP_IN)) | |
4454 | { | |
4455 | /* Generate reloads for matched inputs. */ | |
4456 | match_inputs[0] = i; | |
4457 | for (j = 0; (k = goal_alt_matched[i][j]) >= 0; j++) | |
4458 | match_inputs[j + 1] = k; | |
4459 | match_inputs[j + 1] = -1; | |
dd083a02 | 4460 | match_reload (-1, match_inputs, outputs, goal_alt[i], &before, |
4461 | &after, false); | |
aa3ce8ba | 4462 | } |
c6a6cdaa | 4463 | else |
4464 | /* We must generate code in any case when function | |
4465 | process_alt_operands decides that it is possible. */ | |
4466 | gcc_unreachable (); | |
dd083a02 | 4467 | |
4468 | /* Memorise processed outputs so that output remaining to be processed | |
4469 | can avoid using the same register value (see match_reload). */ | |
4470 | if (curr_static_id->operand[i].type == OP_OUT) | |
4471 | { | |
4472 | outputs[n_outputs++] = i; | |
4473 | outputs[n_outputs] = -1; | |
4474 | } | |
4475 | ||
1f3a048a | 4476 | if (optional_p) |
4477 | { | |
ab4ea053 | 4478 | rtx reg = op; |
4479 | ||
4480 | lra_assert (REG_P (reg)); | |
4481 | regno = REGNO (reg); | |
1f3a048a | 4482 | op = *curr_id->operand_loc[i]; /* Substitution. */ |
4483 | if (GET_CODE (op) == SUBREG) | |
4484 | op = SUBREG_REG (op); | |
4485 | gcc_assert (REG_P (op) && (int) REGNO (op) >= new_regno_start); | |
4486 | bitmap_set_bit (&lra_optional_reload_pseudos, REGNO (op)); | |
ab4ea053 | 4487 | lra_reg_info[REGNO (op)].restore_rtx = reg; |
1f3a048a | 4488 | if (lra_dump_file != NULL) |
4489 | fprintf (lra_dump_file, | |
4490 | " Making reload reg %d for reg %d optional\n", | |
4491 | REGNO (op), regno); | |
4492 | } | |
c6a6cdaa | 4493 | } |
4494 | if (before != NULL_RTX || after != NULL_RTX | |
4495 | || max_regno_before != max_reg_num ()) | |
4496 | change_p = true; | |
4497 | if (change_p) | |
4498 | { | |
4499 | lra_update_operator_dups (curr_id); | |
4500 | /* Something changes -- process the insn. */ | |
4501 | lra_update_insn_regno_info (curr_insn); | |
4502 | } | |
4503 | lra_process_new_insns (curr_insn, before, after, "Inserting insn reload"); | |
4504 | return change_p; | |
4505 | } | |
4506 | ||
497ba60f | 4507 | /* Return true if INSN satisfies all constraints. In other words, no |
4508 | reload insns are needed. */ | |
4509 | bool | |
4510 | lra_constrain_insn (rtx_insn *insn) | |
4511 | { | |
4512 | int saved_new_regno_start = new_regno_start; | |
4513 | int saved_new_insn_uid_start = new_insn_uid_start; | |
4514 | bool change_p; | |
4515 | ||
4516 | curr_insn = insn; | |
4517 | curr_id = lra_get_insn_recog_data (curr_insn); | |
4518 | curr_static_id = curr_id->insn_static_data; | |
4519 | new_insn_uid_start = get_max_uid (); | |
4520 | new_regno_start = max_reg_num (); | |
4521 | change_p = curr_insn_transform (true); | |
4522 | new_regno_start = saved_new_regno_start; | |
4523 | new_insn_uid_start = saved_new_insn_uid_start; | |
4524 | return ! change_p; | |
4525 | } | |
4526 | ||
c6a6cdaa | 4527 | /* Return true if X is in LIST. */ |
4528 | static bool | |
4529 | in_list_p (rtx x, rtx list) | |
4530 | { | |
4531 | for (; list != NULL_RTX; list = XEXP (list, 1)) | |
4532 | if (XEXP (list, 0) == x) | |
4533 | return true; | |
4534 | return false; | |
4535 | } | |
4536 | ||
4537 | /* Return true if X contains an allocatable hard register (if | |
4538 | HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */ | |
4539 | static bool | |
4540 | contains_reg_p (rtx x, bool hard_reg_p, bool spilled_p) | |
4541 | { | |
4542 | int i, j; | |
4543 | const char *fmt; | |
4544 | enum rtx_code code; | |
4545 | ||
4546 | code = GET_CODE (x); | |
4547 | if (REG_P (x)) | |
4548 | { | |
4549 | int regno = REGNO (x); | |
4550 | HARD_REG_SET alloc_regs; | |
4551 | ||
4552 | if (hard_reg_p) | |
4553 | { | |
4554 | if (regno >= FIRST_PSEUDO_REGISTER) | |
4555 | regno = lra_get_regno_hard_regno (regno); | |
4556 | if (regno < 0) | |
4557 | return false; | |
fb3190fc | 4558 | alloc_regs = ~lra_no_alloc_regs; |
c6a6cdaa | 4559 | return overlaps_hard_reg_set_p (alloc_regs, GET_MODE (x), regno); |
4560 | } | |
4561 | else | |
4562 | { | |
4563 | if (regno < FIRST_PSEUDO_REGISTER) | |
4564 | return false; | |
4565 | if (! spilled_p) | |
4566 | return true; | |
4567 | return lra_get_regno_hard_regno (regno) < 0; | |
4568 | } | |
4569 | } | |
4570 | fmt = GET_RTX_FORMAT (code); | |
4571 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
4572 | { | |
4573 | if (fmt[i] == 'e') | |
4574 | { | |
4575 | if (contains_reg_p (XEXP (x, i), hard_reg_p, spilled_p)) | |
4576 | return true; | |
4577 | } | |
4578 | else if (fmt[i] == 'E') | |
4579 | { | |
4580 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
4581 | if (contains_reg_p (XVECEXP (x, i, j), hard_reg_p, spilled_p)) | |
4582 | return true; | |
4583 | } | |
4584 | } | |
4585 | return false; | |
4586 | } | |
4587 | ||
d596f8db | 4588 | /* Process all regs in location *LOC and change them on equivalent |
4589 | substitution. Return true if any change was done. */ | |
c6a6cdaa | 4590 | static bool |
d596f8db | 4591 | loc_equivalence_change_p (rtx *loc) |
c6a6cdaa | 4592 | { |
4593 | rtx subst, reg, x = *loc; | |
4594 | bool result = false; | |
4595 | enum rtx_code code = GET_CODE (x); | |
4596 | const char *fmt; | |
4597 | int i, j; | |
4598 | ||
4599 | if (code == SUBREG) | |
4600 | { | |
4601 | reg = SUBREG_REG (x); | |
3b3a5e5f | 4602 | if ((subst = get_equiv_with_elimination (reg, curr_insn)) != reg |
c6a6cdaa | 4603 | && GET_MODE (subst) == VOIDmode) |
4604 | { | |
4605 | /* We cannot reload debug location. Simplify subreg here | |
4606 | while we know the inner mode. */ | |
4607 | *loc = simplify_gen_subreg (GET_MODE (x), subst, | |
4608 | GET_MODE (reg), SUBREG_BYTE (x)); | |
4609 | return true; | |
4610 | } | |
4611 | } | |
3b3a5e5f | 4612 | if (code == REG && (subst = get_equiv_with_elimination (x, curr_insn)) != x) |
c6a6cdaa | 4613 | { |
4614 | *loc = subst; | |
4615 | return true; | |
4616 | } | |
4617 | ||
4618 | /* Scan all the operand sub-expressions. */ | |
4619 | fmt = GET_RTX_FORMAT (code); | |
4620 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
4621 | { | |
4622 | if (fmt[i] == 'e') | |
d596f8db | 4623 | result = loc_equivalence_change_p (&XEXP (x, i)) || result; |
c6a6cdaa | 4624 | else if (fmt[i] == 'E') |
4625 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
4626 | result | |
d596f8db | 4627 | = loc_equivalence_change_p (&XVECEXP (x, i, j)) || result; |
c6a6cdaa | 4628 | } |
4629 | return result; | |
4630 | } | |
4631 | ||
136e5c8e | 4632 | /* Similar to loc_equivalence_change_p, but for use as |
61cd3e57 | 4633 | simplify_replace_fn_rtx callback. DATA is insn for which the |
4634 | elimination is done. If it null we don't do the elimination. */ | |
136e5c8e | 4635 | static rtx |
61cd3e57 | 4636 | loc_equivalence_callback (rtx loc, const_rtx, void *data) |
136e5c8e | 4637 | { |
4638 | if (!REG_P (loc)) | |
4639 | return NULL_RTX; | |
4640 | ||
61cd3e57 | 4641 | rtx subst = (data == NULL |
7f836b57 | 4642 | ? get_equiv (loc) : get_equiv_with_elimination (loc, (rtx_insn *) data)); |
136e5c8e | 4643 | if (subst != loc) |
4644 | return subst; | |
4645 | ||
4646 | return NULL_RTX; | |
4647 | } | |
4648 | ||
c6a6cdaa | 4649 | /* Maximum number of generated reload insns per an insn. It is for |
4650 | preventing this pass cycling in a bug case. */ | |
4651 | #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS | |
4652 | ||
4653 | /* The current iteration number of this LRA pass. */ | |
4654 | int lra_constraint_iter; | |
4655 | ||
c6a6cdaa | 4656 | /* True if we substituted equiv which needs checking register |
4657 | allocation correctness because the equivalent value contains | |
4658 | allocatable hard registers or when we restore multi-register | |
4659 | pseudo. */ | |
4660 | bool lra_risky_transformations_p; | |
4661 | ||
4662 | /* Return true if REGNO is referenced in more than one block. */ | |
4663 | static bool | |
4664 | multi_block_pseudo_p (int regno) | |
4665 | { | |
4666 | basic_block bb = NULL; | |
4667 | unsigned int uid; | |
4668 | bitmap_iterator bi; | |
1a8f8886 | 4669 | |
c6a6cdaa | 4670 | if (regno < FIRST_PSEUDO_REGISTER) |
4671 | return false; | |
1a8f8886 | 4672 | |
c6a6cdaa | 4673 | EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi) |
4674 | if (bb == NULL) | |
4675 | bb = BLOCK_FOR_INSN (lra_insn_recog_data[uid]->insn); | |
4676 | else if (BLOCK_FOR_INSN (lra_insn_recog_data[uid]->insn) != bb) | |
4677 | return true; | |
4678 | return false; | |
4679 | } | |
4680 | ||
7a438292 | 4681 | /* Return true if LIST contains a deleted insn. */ |
4682 | static bool | |
382f116f | 4683 | contains_deleted_insn_p (rtx_insn_list *list) |
7a438292 | 4684 | { |
382f116f | 4685 | for (; list != NULL_RTX; list = list->next ()) |
4686 | if (NOTE_P (list->insn ()) | |
4687 | && NOTE_KIND (list->insn ()) == NOTE_INSN_DELETED) | |
7a438292 | 4688 | return true; |
4689 | return false; | |
4690 | } | |
4691 | ||
c6a6cdaa | 4692 | /* Return true if X contains a pseudo dying in INSN. */ |
4693 | static bool | |
c265d2aa | 4694 | dead_pseudo_p (rtx x, rtx_insn *insn) |
c6a6cdaa | 4695 | { |
4696 | int i, j; | |
4697 | const char *fmt; | |
4698 | enum rtx_code code; | |
4699 | ||
4700 | if (REG_P (x)) | |
4701 | return (insn != NULL_RTX | |
4702 | && find_regno_note (insn, REG_DEAD, REGNO (x)) != NULL_RTX); | |
4703 | code = GET_CODE (x); | |
4704 | fmt = GET_RTX_FORMAT (code); | |
4705 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
4706 | { | |
4707 | if (fmt[i] == 'e') | |
4708 | { | |
4709 | if (dead_pseudo_p (XEXP (x, i), insn)) | |
4710 | return true; | |
4711 | } | |
4712 | else if (fmt[i] == 'E') | |
4713 | { | |
4714 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
4715 | if (dead_pseudo_p (XVECEXP (x, i, j), insn)) | |
4716 | return true; | |
4717 | } | |
4718 | } | |
4719 | return false; | |
4720 | } | |
4721 | ||
4722 | /* Return true if INSN contains a dying pseudo in INSN right hand | |
4723 | side. */ | |
4724 | static bool | |
50fc2d35 | 4725 | insn_rhs_dead_pseudo_p (rtx_insn *insn) |
c6a6cdaa | 4726 | { |
4727 | rtx set = single_set (insn); | |
4728 | ||
4729 | gcc_assert (set != NULL); | |
4730 | return dead_pseudo_p (SET_SRC (set), insn); | |
4731 | } | |
4732 | ||
4733 | /* Return true if any init insn of REGNO contains a dying pseudo in | |
4734 | insn right hand side. */ | |
4735 | static bool | |
4736 | init_insn_rhs_dead_pseudo_p (int regno) | |
4737 | { | |
382f116f | 4738 | rtx_insn_list *insns = ira_reg_equiv[regno].init_insns; |
c6a6cdaa | 4739 | |
4740 | if (insns == NULL) | |
4741 | return false; | |
382f116f | 4742 | for (; insns != NULL_RTX; insns = insns->next ()) |
4743 | if (insn_rhs_dead_pseudo_p (insns->insn ())) | |
c6a6cdaa | 4744 | return true; |
4745 | return false; | |
4746 | } | |
4747 | ||
691cfda4 | 4748 | /* Return TRUE if REGNO has a reverse equivalence. The equivalence is |
4749 | reverse only if we have one init insn with given REGNO as a | |
4750 | source. */ | |
4751 | static bool | |
4752 | reverse_equiv_p (int regno) | |
4753 | { | |
382f116f | 4754 | rtx_insn_list *insns = ira_reg_equiv[regno].init_insns; |
4755 | rtx set; | |
691cfda4 | 4756 | |
382f116f | 4757 | if (insns == NULL) |
691cfda4 | 4758 | return false; |
382f116f | 4759 | if (! INSN_P (insns->insn ()) |
4760 | || insns->next () != NULL) | |
691cfda4 | 4761 | return false; |
382f116f | 4762 | if ((set = single_set (insns->insn ())) == NULL_RTX) |
691cfda4 | 4763 | return false; |
4764 | return REG_P (SET_SRC (set)) && (int) REGNO (SET_SRC (set)) == regno; | |
4765 | } | |
4766 | ||
4767 | /* Return TRUE if REGNO was reloaded in an equivalence init insn. We | |
4768 | call this function only for non-reverse equivalence. */ | |
4769 | static bool | |
4770 | contains_reloaded_insn_p (int regno) | |
4771 | { | |
4772 | rtx set; | |
382f116f | 4773 | rtx_insn_list *list = ira_reg_equiv[regno].init_insns; |
691cfda4 | 4774 | |
382f116f | 4775 | for (; list != NULL; list = list->next ()) |
4776 | if ((set = single_set (list->insn ())) == NULL_RTX | |
691cfda4 | 4777 | || ! REG_P (SET_DEST (set)) |
4778 | || (int) REGNO (SET_DEST (set)) != regno) | |
4779 | return true; | |
4780 | return false; | |
4781 | } | |
4782 | ||
c6a6cdaa | 4783 | /* Entry function of LRA constraint pass. Return true if the |
4784 | constraint pass did change the code. */ | |
4785 | bool | |
4786 | lra_constraints (bool first_p) | |
4787 | { | |
4788 | bool changed_p; | |
4789 | int i, hard_regno, new_insns_num; | |
f7b7100e | 4790 | unsigned int min_len, new_min_len, uid; |
4791 | rtx set, x, reg, dest_reg; | |
c6a6cdaa | 4792 | basic_block last_bb; |
f7b7100e | 4793 | bitmap_iterator bi; |
c6a6cdaa | 4794 | |
4795 | lra_constraint_iter++; | |
4796 | if (lra_dump_file != NULL) | |
4797 | fprintf (lra_dump_file, "\n********** Local #%d: **********\n\n", | |
4798 | lra_constraint_iter); | |
c6a6cdaa | 4799 | changed_p = false; |
a9d8ab38 | 4800 | if (pic_offset_table_rtx |
4801 | && REGNO (pic_offset_table_rtx) >= FIRST_PSEUDO_REGISTER) | |
4802 | lra_risky_transformations_p = true; | |
4803 | else | |
9628978f | 4804 | /* On the first iteration we should check IRA assignment |
4805 | correctness. In rare cases, the assignments can be wrong as | |
8ae81042 | 4806 | early clobbers operands are ignored in IRA or usages of |
4807 | paradoxical sub-registers are not taken into account by | |
4808 | IRA. */ | |
9628978f | 4809 | lra_risky_transformations_p = first_p; |
c6a6cdaa | 4810 | new_insn_uid_start = get_max_uid (); |
4811 | new_regno_start = first_p ? lra_constraint_new_regno_start : max_reg_num (); | |
3b3a5e5f | 4812 | /* Mark used hard regs for target stack size calulations. */ |
4813 | for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++) | |
4814 | if (lra_reg_info[i].nrefs != 0 | |
4815 | && (hard_regno = lra_get_regno_hard_regno (i)) >= 0) | |
4816 | { | |
4817 | int j, nregs; | |
4818 | ||
92d2aec3 | 4819 | nregs = hard_regno_nregs (hard_regno, lra_reg_info[i].biggest_mode); |
3b3a5e5f | 4820 | for (j = 0; j < nregs; j++) |
4821 | df_set_regs_ever_live (hard_regno + j, true); | |
4822 | } | |
4823 | /* Do elimination before the equivalence processing as we can spill | |
4824 | some pseudos during elimination. */ | |
4825 | lra_eliminate (false, first_p); | |
f6708c36 | 4826 | auto_bitmap equiv_insn_bitmap (®_obstack); |
c6a6cdaa | 4827 | for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++) |
4828 | if (lra_reg_info[i].nrefs != 0) | |
4829 | { | |
4830 | ira_reg_equiv[i].profitable_p = true; | |
f7b7100e | 4831 | reg = regno_reg_rtx[i]; |
3b3a5e5f | 4832 | if (lra_get_regno_hard_regno (i) < 0 && (x = get_equiv (reg)) != reg) |
c6a6cdaa | 4833 | { |
4834 | bool pseudo_p = contains_reg_p (x, false, false); | |
c6a6cdaa | 4835 | |
f4d3c071 | 4836 | /* After RTL transformation, we cannot guarantee that |
7a438292 | 4837 | pseudo in the substitution was not reloaded which might |
4838 | make equivalence invalid. For example, in reverse | |
4839 | equiv of p0 | |
4840 | ||
4841 | p0 <- ... | |
4842 | ... | |
4843 | equiv_mem <- p0 | |
4844 | ||
4845 | the memory address register was reloaded before the 2nd | |
4846 | insn. */ | |
4847 | if ((! first_p && pseudo_p) | |
4848 | /* We don't use DF for compilation speed sake. So it | |
4849 | is problematic to update live info when we use an | |
4850 | equivalence containing pseudos in more than one | |
4851 | BB. */ | |
4852 | || (pseudo_p && multi_block_pseudo_p (i)) | |
4853 | /* If an init insn was deleted for some reason, cancel | |
4854 | the equiv. We could update the equiv insns after | |
4855 | transformations including an equiv insn deletion | |
4856 | but it is not worthy as such cases are extremely | |
4857 | rare. */ | |
4858 | || contains_deleted_insn_p (ira_reg_equiv[i].init_insns) | |
c6a6cdaa | 4859 | /* If it is not a reverse equivalence, we check that a |
4860 | pseudo in rhs of the init insn is not dying in the | |
4861 | insn. Otherwise, the live info at the beginning of | |
4862 | the corresponding BB might be wrong after we | |
4863 | removed the insn. When the equiv can be a | |
4864 | constant, the right hand side of the init insn can | |
4865 | be a pseudo. */ | |
691cfda4 | 4866 | || (! reverse_equiv_p (i) |
4867 | && (init_insn_rhs_dead_pseudo_p (i) | |
4868 | /* If we reloaded the pseudo in an equivalence | |
f4d3c071 | 4869 | init insn, we cannot remove the equiv init |
691cfda4 | 4870 | insns and the init insns might write into |
4871 | const memory in this case. */ | |
4872 | || contains_reloaded_insn_p (i))) | |
fc8a0f60 | 4873 | /* Prevent access beyond equivalent memory for |
4874 | paradoxical subregs. */ | |
4875 | || (MEM_P (x) | |
52acb7ae | 4876 | && maybe_gt (GET_MODE_SIZE (lra_reg_info[i].biggest_mode), |
4877 | GET_MODE_SIZE (GET_MODE (x)))) | |
a9d8ab38 | 4878 | || (pic_offset_table_rtx |
4879 | && ((CONST_POOL_OK_P (PSEUDO_REGNO_MODE (i), x) | |
4880 | && (targetm.preferred_reload_class | |
4881 | (x, lra_get_allocno_class (i)) == NO_REGS)) | |
bf9df576 | 4882 | || contains_symbol_ref_p (x)))) |
c6a6cdaa | 4883 | ira_reg_equiv[i].defined_p = false; |
c6a6cdaa | 4884 | if (contains_reg_p (x, false, true)) |
4885 | ira_reg_equiv[i].profitable_p = false; | |
3b3a5e5f | 4886 | if (get_equiv (reg) != reg) |
f6708c36 | 4887 | bitmap_ior_into (equiv_insn_bitmap, &lra_reg_info[i].insn_bitmap); |
c6a6cdaa | 4888 | } |
4889 | } | |
61cd3e57 | 4890 | for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++) |
4891 | update_equiv (i); | |
f7b7100e | 4892 | /* We should add all insns containing pseudos which should be |
4893 | substituted by their equivalences. */ | |
f6708c36 | 4894 | EXECUTE_IF_SET_IN_BITMAP (equiv_insn_bitmap, 0, uid, bi) |
f7b7100e | 4895 | lra_push_insn_by_uid (uid); |
c6a6cdaa | 4896 | min_len = lra_insn_stack_length (); |
4897 | new_insns_num = 0; | |
4898 | last_bb = NULL; | |
4899 | changed_p = false; | |
4900 | while ((new_min_len = lra_insn_stack_length ()) != 0) | |
4901 | { | |
4902 | curr_insn = lra_pop_insn (); | |
4903 | --new_min_len; | |
1a8f8886 | 4904 | curr_bb = BLOCK_FOR_INSN (curr_insn); |
c6a6cdaa | 4905 | if (curr_bb != last_bb) |
4906 | { | |
4907 | last_bb = curr_bb; | |
4908 | bb_reload_num = lra_curr_reload_num; | |
4909 | } | |
4910 | if (min_len > new_min_len) | |
4911 | { | |
4912 | min_len = new_min_len; | |
4913 | new_insns_num = 0; | |
4914 | } | |
4915 | if (new_insns_num > MAX_RELOAD_INSNS_NUMBER) | |
4916 | internal_error | |
85b9be9b | 4917 | ("maximum number of generated reload insns per insn achieved (%d)", |
c6a6cdaa | 4918 | MAX_RELOAD_INSNS_NUMBER); |
4919 | new_insns_num++; | |
4920 | if (DEBUG_INSN_P (curr_insn)) | |
4921 | { | |
4922 | /* We need to check equivalence in debug insn and change | |
4923 | pseudo to the equivalent value if necessary. */ | |
4924 | curr_id = lra_get_insn_recog_data (curr_insn); | |
f6708c36 | 4925 | if (bitmap_bit_p (equiv_insn_bitmap, INSN_UID (curr_insn))) |
e717b69a | 4926 | { |
136e5c8e | 4927 | rtx old = *curr_id->operand_loc[0]; |
4928 | *curr_id->operand_loc[0] | |
4929 | = simplify_replace_fn_rtx (old, NULL_RTX, | |
61cd3e57 | 4930 | loc_equivalence_callback, curr_insn); |
136e5c8e | 4931 | if (old != *curr_id->operand_loc[0]) |
4932 | { | |
4933 | lra_update_insn_regno_info (curr_insn); | |
4934 | changed_p = true; | |
4935 | } | |
e717b69a | 4936 | } |
c6a6cdaa | 4937 | } |
4938 | else if (INSN_P (curr_insn)) | |
4939 | { | |
4940 | if ((set = single_set (curr_insn)) != NULL_RTX) | |
4941 | { | |
4942 | dest_reg = SET_DEST (set); | |
4943 | /* The equivalence pseudo could be set up as SUBREG in a | |
4944 | case when it is a call restore insn in a mode | |
4945 | different from the pseudo mode. */ | |
4946 | if (GET_CODE (dest_reg) == SUBREG) | |
4947 | dest_reg = SUBREG_REG (dest_reg); | |
4948 | if ((REG_P (dest_reg) | |
3b3a5e5f | 4949 | && (x = get_equiv (dest_reg)) != dest_reg |
c6a6cdaa | 4950 | /* Remove insns which set up a pseudo whose value |
f4d3c071 | 4951 | cannot be changed. Such insns might be not in |
c6a6cdaa | 4952 | init_insns because we don't update equiv data |
4953 | during insn transformations. | |
c625778b | 4954 | |
c6a6cdaa | 4955 | As an example, let suppose that a pseudo got |
4956 | hard register and on the 1st pass was not | |
4957 | changed to equivalent constant. We generate an | |
4958 | additional insn setting up the pseudo because of | |
4959 | secondary memory movement. Then the pseudo is | |
4960 | spilled and we use the equiv constant. In this | |
4961 | case we should remove the additional insn and | |
e454a550 | 4962 | this insn is not init_insns list. */ |
c6a6cdaa | 4963 | && (! MEM_P (x) || MEM_READONLY_P (x) |
e454a550 | 4964 | /* Check that this is actually an insn setting |
4965 | up the equivalence. */ | |
c6a6cdaa | 4966 | || in_list_p (curr_insn, |
4967 | ira_reg_equiv | |
4968 | [REGNO (dest_reg)].init_insns))) | |
3b3a5e5f | 4969 | || (((x = get_equiv (SET_SRC (set))) != SET_SRC (set)) |
c6a6cdaa | 4970 | && in_list_p (curr_insn, |
4971 | ira_reg_equiv | |
4972 | [REGNO (SET_SRC (set))].init_insns))) | |
4973 | { | |
4974 | /* This is equiv init insn of pseudo which did not get a | |
4975 | hard register -- remove the insn. */ | |
4976 | if (lra_dump_file != NULL) | |
4977 | { | |
4978 | fprintf (lra_dump_file, | |
4979 | " Removing equiv init insn %i (freq=%d)\n", | |
4980 | INSN_UID (curr_insn), | |
e374deeb | 4981 | REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn))); |
6dde9719 | 4982 | dump_insn_slim (lra_dump_file, curr_insn); |
c6a6cdaa | 4983 | } |
4984 | if (contains_reg_p (x, true, false)) | |
4985 | lra_risky_transformations_p = true; | |
4986 | lra_set_insn_deleted (curr_insn); | |
4987 | continue; | |
4988 | } | |
4989 | } | |
4990 | curr_id = lra_get_insn_recog_data (curr_insn); | |
4991 | curr_static_id = curr_id->insn_static_data; | |
4992 | init_curr_insn_input_reloads (); | |
4993 | init_curr_operand_mode (); | |
497ba60f | 4994 | if (curr_insn_transform (false)) |
c6a6cdaa | 4995 | changed_p = true; |
d596f8db | 4996 | /* Check non-transformed insns too for equiv change as USE |
4997 | or CLOBBER don't need reloads but can contain pseudos | |
4998 | being changed on their equivalences. */ | |
f6708c36 | 4999 | else if (bitmap_bit_p (equiv_insn_bitmap, INSN_UID (curr_insn)) |
d596f8db | 5000 | && loc_equivalence_change_p (&PATTERN (curr_insn))) |
5001 | { | |
5002 | lra_update_insn_regno_info (curr_insn); | |
5003 | changed_p = true; | |
5004 | } | |
c6a6cdaa | 5005 | } |
5006 | } | |
f6708c36 | 5007 | |
c6a6cdaa | 5008 | /* If we used a new hard regno, changed_p should be true because the |
5009 | hard reg is assigned to a new pseudo. */ | |
382ecba7 | 5010 | if (flag_checking && !changed_p) |
c6a6cdaa | 5011 | { |
5012 | for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++) | |
5013 | if (lra_reg_info[i].nrefs != 0 | |
5014 | && (hard_regno = lra_get_regno_hard_regno (i)) >= 0) | |
5015 | { | |
92d2aec3 | 5016 | int j, nregs = hard_regno_nregs (hard_regno, |
5017 | PSEUDO_REGNO_MODE (i)); | |
1a8f8886 | 5018 | |
c6a6cdaa | 5019 | for (j = 0; j < nregs; j++) |
5020 | lra_assert (df_regs_ever_live_p (hard_regno + j)); | |
5021 | } | |
5022 | } | |
c6a6cdaa | 5023 | return changed_p; |
5024 | } | |
5025 | ||
ab4ea053 | 5026 | static void initiate_invariants (void); |
5027 | static void finish_invariants (void); | |
5028 | ||
c6a6cdaa | 5029 | /* Initiate the LRA constraint pass. It is done once per |
5030 | function. */ | |
5031 | void | |
5032 | lra_constraints_init (void) | |
5033 | { | |
ab4ea053 | 5034 | initiate_invariants (); |
c6a6cdaa | 5035 | } |
5036 | ||
5037 | /* Finalize the LRA constraint pass. It is done once per | |
5038 | function. */ | |
5039 | void | |
5040 | lra_constraints_finish (void) | |
5041 | { | |
ab4ea053 | 5042 | finish_invariants (); |
5043 | } | |
5044 | ||
5045 | \f | |
5046 | ||
5047 | /* Structure describes invariants for ineheritance. */ | |
1cda36f6 | 5048 | struct lra_invariant |
ab4ea053 | 5049 | { |
5050 | /* The order number of the invariant. */ | |
5051 | int num; | |
5052 | /* The invariant RTX. */ | |
5053 | rtx invariant_rtx; | |
5054 | /* The origin insn of the invariant. */ | |
5055 | rtx_insn *insn; | |
5056 | }; | |
5057 | ||
1cda36f6 | 5058 | typedef lra_invariant invariant_t; |
ab4ea053 | 5059 | typedef invariant_t *invariant_ptr_t; |
5060 | typedef const invariant_t *const_invariant_ptr_t; | |
5061 | ||
5062 | /* Pointer to the inheritance invariants. */ | |
5063 | static vec<invariant_ptr_t> invariants; | |
5064 | ||
5065 | /* Allocation pool for the invariants. */ | |
1cda36f6 | 5066 | static object_allocator<lra_invariant> *invariants_pool; |
ab4ea053 | 5067 | |
5068 | /* Hash table for the invariants. */ | |
5069 | static htab_t invariant_table; | |
5070 | ||
5071 | /* Hash function for INVARIANT. */ | |
5072 | static hashval_t | |
5073 | invariant_hash (const void *invariant) | |
5074 | { | |
5075 | rtx inv = ((const_invariant_ptr_t) invariant)->invariant_rtx; | |
5076 | return lra_rtx_hash (inv); | |
5077 | } | |
5078 | ||
5079 | /* Equal function for invariants INVARIANT1 and INVARIANT2. */ | |
5080 | static int | |
5081 | invariant_eq_p (const void *invariant1, const void *invariant2) | |
5082 | { | |
5083 | rtx inv1 = ((const_invariant_ptr_t) invariant1)->invariant_rtx; | |
5084 | rtx inv2 = ((const_invariant_ptr_t) invariant2)->invariant_rtx; | |
5085 | ||
5086 | return rtx_equal_p (inv1, inv2); | |
5087 | } | |
5088 | ||
5089 | /* Insert INVARIANT_RTX into the table if it is not there yet. Return | |
5090 | invariant which is in the table. */ | |
5091 | static invariant_ptr_t | |
5092 | insert_invariant (rtx invariant_rtx) | |
5093 | { | |
5094 | void **entry_ptr; | |
5095 | invariant_t invariant; | |
5096 | invariant_ptr_t invariant_ptr; | |
5097 | ||
5098 | invariant.invariant_rtx = invariant_rtx; | |
5099 | entry_ptr = htab_find_slot (invariant_table, &invariant, INSERT); | |
5100 | if (*entry_ptr == NULL) | |
5101 | { | |
5102 | invariant_ptr = invariants_pool->allocate (); | |
5103 | invariant_ptr->invariant_rtx = invariant_rtx; | |
5104 | invariant_ptr->insn = NULL; | |
5105 | invariants.safe_push (invariant_ptr); | |
5106 | *entry_ptr = (void *) invariant_ptr; | |
5107 | } | |
5108 | return (invariant_ptr_t) *entry_ptr; | |
5109 | } | |
5110 | ||
5111 | /* Initiate the invariant table. */ | |
5112 | static void | |
5113 | initiate_invariants (void) | |
5114 | { | |
5115 | invariants.create (100); | |
1cda36f6 | 5116 | invariants_pool |
5117 | = new object_allocator<lra_invariant> ("Inheritance invariants"); | |
ab4ea053 | 5118 | invariant_table = htab_create (100, invariant_hash, invariant_eq_p, NULL); |
5119 | } | |
5120 | ||
5121 | /* Finish the invariant table. */ | |
5122 | static void | |
5123 | finish_invariants (void) | |
5124 | { | |
5125 | htab_delete (invariant_table); | |
5126 | delete invariants_pool; | |
5127 | invariants.release (); | |
5128 | } | |
5129 | ||
5130 | /* Make the invariant table empty. */ | |
5131 | static void | |
5132 | clear_invariants (void) | |
5133 | { | |
5134 | htab_empty (invariant_table); | |
5135 | invariants_pool->release (); | |
5136 | invariants.truncate (0); | |
c6a6cdaa | 5137 | } |
5138 | ||
5139 | \f | |
5140 | ||
5141 | /* This page contains code to do inheritance/split | |
5142 | transformations. */ | |
5143 | ||
5144 | /* Number of reloads passed so far in current EBB. */ | |
5145 | static int reloads_num; | |
5146 | ||
5147 | /* Number of calls passed so far in current EBB. */ | |
5148 | static int calls_num; | |
5149 | ||
2f9fa72f | 5150 | /* Index ID is the CALLS_NUM associated the last call we saw with |
5151 | ABI identifier ID. */ | |
5152 | static int last_call_for_abi[NUM_ABI_IDS]; | |
5153 | ||
5154 | /* Which registers have been fully or partially clobbered by a call | |
5155 | since they were last used. */ | |
5156 | static HARD_REG_SET full_and_partial_call_clobbers; | |
5157 | ||
c6a6cdaa | 5158 | /* Current reload pseudo check for validity of elements in |
5159 | USAGE_INSNS. */ | |
5160 | static int curr_usage_insns_check; | |
5161 | ||
5162 | /* Info about last usage of registers in EBB to do inheritance/split | |
5163 | transformation. Inheritance transformation is done from a spilled | |
5164 | pseudo and split transformations from a hard register or a pseudo | |
5165 | assigned to a hard register. */ | |
5166 | struct usage_insns | |
5167 | { | |
5168 | /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member | |
5169 | value INSNS is valid. The insns is chain of optional debug insns | |
cc0dc61b | 5170 | and a finishing non-debug insn using the corresponding reg. The |
5171 | value is also used to mark the registers which are set up in the | |
5172 | current insn. The negated insn uid is used for this. */ | |
c6a6cdaa | 5173 | int check; |
5174 | /* Value of global reloads_num at the last insn in INSNS. */ | |
5175 | int reloads_num; | |
5176 | /* Value of global reloads_nums at the last insn in INSNS. */ | |
5177 | int calls_num; | |
5178 | /* It can be true only for splitting. And it means that the restore | |
5179 | insn should be put after insn given by the following member. */ | |
5180 | bool after_p; | |
5181 | /* Next insns in the current EBB which use the original reg and the | |
5182 | original reg value is not changed between the current insn and | |
5183 | the next insns. In order words, e.g. for inheritance, if we need | |
5184 | to use the original reg value again in the next insns we can try | |
5185 | to use the value in a hard register from a reload insn of the | |
5186 | current insn. */ | |
5187 | rtx insns; | |
5188 | }; | |
5189 | ||
5190 | /* Map: regno -> corresponding pseudo usage insns. */ | |
5191 | static struct usage_insns *usage_insns; | |
5192 | ||
5193 | static void | |
f9a00e9e | 5194 | setup_next_usage_insn (int regno, rtx insn, int reloads_num, bool after_p) |
c6a6cdaa | 5195 | { |
5196 | usage_insns[regno].check = curr_usage_insns_check; | |
5197 | usage_insns[regno].insns = insn; | |
5198 | usage_insns[regno].reloads_num = reloads_num; | |
5199 | usage_insns[regno].calls_num = calls_num; | |
5200 | usage_insns[regno].after_p = after_p; | |
2f9fa72f | 5201 | if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] >= 0) |
5202 | remove_from_hard_reg_set (&full_and_partial_call_clobbers, | |
5203 | PSEUDO_REGNO_MODE (regno), | |
5204 | reg_renumber[regno]); | |
c6a6cdaa | 5205 | } |
5206 | ||
5207 | /* The function is used to form list REGNO usages which consists of | |
5208 | optional debug insns finished by a non-debug insn using REGNO. | |
5209 | RELOADS_NUM is current number of reload insns processed so far. */ | |
5210 | static void | |
06743455 | 5211 | add_next_usage_insn (int regno, rtx_insn *insn, int reloads_num) |
c6a6cdaa | 5212 | { |
5213 | rtx next_usage_insns; | |
1a8f8886 | 5214 | |
c6a6cdaa | 5215 | if (usage_insns[regno].check == curr_usage_insns_check |
5216 | && (next_usage_insns = usage_insns[regno].insns) != NULL_RTX | |
5217 | && DEBUG_INSN_P (insn)) | |
5218 | { | |
5219 | /* Check that we did not add the debug insn yet. */ | |
5220 | if (next_usage_insns != insn | |
5221 | && (GET_CODE (next_usage_insns) != INSN_LIST | |
5222 | || XEXP (next_usage_insns, 0) != insn)) | |
5223 | usage_insns[regno].insns = gen_rtx_INSN_LIST (VOIDmode, insn, | |
5224 | next_usage_insns); | |
5225 | } | |
5226 | else if (NONDEBUG_INSN_P (insn)) | |
5227 | setup_next_usage_insn (regno, insn, reloads_num, false); | |
5228 | else | |
5229 | usage_insns[regno].check = 0; | |
5230 | } | |
1a8f8886 | 5231 | |
5bb0e0fd | 5232 | /* Return first non-debug insn in list USAGE_INSNS. */ |
50fc2d35 | 5233 | static rtx_insn * |
5bb0e0fd | 5234 | skip_usage_debug_insns (rtx usage_insns) |
5235 | { | |
5236 | rtx insn; | |
5237 | ||
5238 | /* Skip debug insns. */ | |
5239 | for (insn = usage_insns; | |
5240 | insn != NULL_RTX && GET_CODE (insn) == INSN_LIST; | |
5241 | insn = XEXP (insn, 1)) | |
5242 | ; | |
50fc2d35 | 5243 | return safe_as_a <rtx_insn *> (insn); |
5bb0e0fd | 5244 | } |
5245 | ||
5246 | /* Return true if we need secondary memory moves for insn in | |
5247 | USAGE_INSNS after inserting inherited pseudo of class INHER_CL | |
5248 | into the insn. */ | |
5249 | static bool | |
acb7fe1f | 5250 | check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED, |
5251 | rtx usage_insns ATTRIBUTE_UNUSED) | |
5bb0e0fd | 5252 | { |
50fc2d35 | 5253 | rtx_insn *insn; |
5254 | rtx set, dest; | |
5bb0e0fd | 5255 | enum reg_class cl; |
5256 | ||
5257 | if (inher_cl == ALL_REGS | |
5258 | || (insn = skip_usage_debug_insns (usage_insns)) == NULL_RTX) | |
5259 | return false; | |
5260 | lra_assert (INSN_P (insn)); | |
5261 | if ((set = single_set (insn)) == NULL_RTX || ! REG_P (SET_DEST (set))) | |
5262 | return false; | |
5263 | dest = SET_DEST (set); | |
5264 | if (! REG_P (dest)) | |
5265 | return false; | |
5266 | lra_assert (inher_cl != NO_REGS); | |
5267 | cl = get_reg_class (REGNO (dest)); | |
5268 | return (cl != NO_REGS && cl != ALL_REGS | |
c836e75b | 5269 | && targetm.secondary_memory_needed (GET_MODE (dest), inher_cl, cl)); |
5bb0e0fd | 5270 | } |
5271 | ||
c6a6cdaa | 5272 | /* Registers involved in inheritance/split in the current EBB |
5273 | (inheritance/split pseudos and original registers). */ | |
5274 | static bitmap_head check_only_regs; | |
5275 | ||
f4d3c071 | 5276 | /* Reload pseudos cannot be involded in invariant inheritance in the |
ab4ea053 | 5277 | current EBB. */ |
5278 | static bitmap_head invalid_invariant_regs; | |
5279 | ||
c6a6cdaa | 5280 | /* Do inheritance transformations for insn INSN, which defines (if |
5281 | DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which | |
5282 | instruction in the EBB next uses ORIGINAL_REGNO; it has the same | |
5283 | form as the "insns" field of usage_insns. Return true if we | |
5284 | succeed in such transformation. | |
5285 | ||
5286 | The transformations look like: | |
5287 | ||
5288 | p <- ... i <- ... | |
5289 | ... p <- i (new insn) | |
5290 | ... => | |
5291 | <- ... p ... <- ... i ... | |
5292 | or | |
5293 | ... i <- p (new insn) | |
5294 | <- ... p ... <- ... i ... | |
5295 | ... => | |
5296 | <- ... p ... <- ... i ... | |
5297 | where p is a spilled original pseudo and i is a new inheritance pseudo. | |
1a8f8886 | 5298 | |
5299 | ||
c6a6cdaa | 5300 | The inheritance pseudo has the smallest class of two classes CL and |
5301 | class of ORIGINAL REGNO. */ | |
5302 | static bool | |
5303 | inherit_reload_reg (bool def_p, int original_regno, | |
7f836b57 | 5304 | enum reg_class cl, rtx_insn *insn, rtx next_usage_insns) |
c6a6cdaa | 5305 | { |
77a00b11 | 5306 | if (optimize_function_for_size_p (cfun)) |
5307 | return false; | |
5308 | ||
c6a6cdaa | 5309 | enum reg_class rclass = lra_get_allocno_class (original_regno); |
5310 | rtx original_reg = regno_reg_rtx[original_regno]; | |
7f836b57 | 5311 | rtx new_reg, usage_insn; |
5312 | rtx_insn *new_insns; | |
c6a6cdaa | 5313 | |
5314 | lra_assert (! usage_insns[original_regno].after_p); | |
5315 | if (lra_dump_file != NULL) | |
5316 | fprintf (lra_dump_file, | |
5bb0e0fd | 5317 | " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n"); |
c6a6cdaa | 5318 | if (! ira_reg_classes_intersect_p[cl][rclass]) |
5319 | { | |
5320 | if (lra_dump_file != NULL) | |
5321 | { | |
5322 | fprintf (lra_dump_file, | |
5bb0e0fd | 5323 | " Rejecting inheritance for %d " |
c6a6cdaa | 5324 | "because of disjoint classes %s and %s\n", |
5325 | original_regno, reg_class_names[cl], | |
5326 | reg_class_names[rclass]); | |
5327 | fprintf (lra_dump_file, | |
5bb0e0fd | 5328 | " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); |
c6a6cdaa | 5329 | } |
5330 | return false; | |
5331 | } | |
5332 | if ((ira_class_subset_p[cl][rclass] && cl != rclass) | |
5333 | /* We don't use a subset of two classes because it can be | |
5334 | NO_REGS. This transformation is still profitable in most | |
5335 | cases even if the classes are not intersected as register | |
5336 | move is probably cheaper than a memory load. */ | |
5337 | || ira_class_hard_regs_num[cl] < ira_class_hard_regs_num[rclass]) | |
5338 | { | |
5339 | if (lra_dump_file != NULL) | |
5340 | fprintf (lra_dump_file, " Use smallest class of %s and %s\n", | |
5341 | reg_class_names[cl], reg_class_names[rclass]); | |
1a8f8886 | 5342 | |
c6a6cdaa | 5343 | rclass = cl; |
5344 | } | |
c47331e3 | 5345 | if (check_secondary_memory_needed_p (rclass, next_usage_insns)) |
5bb0e0fd | 5346 | { |
5347 | /* Reject inheritance resulting in secondary memory moves. | |
5348 | Otherwise, there is a danger in LRA cycling. Also such | |
5349 | transformation will be unprofitable. */ | |
5350 | if (lra_dump_file != NULL) | |
5351 | { | |
50fc2d35 | 5352 | rtx_insn *insn = skip_usage_debug_insns (next_usage_insns); |
5bb0e0fd | 5353 | rtx set = single_set (insn); |
5354 | ||
5355 | lra_assert (set != NULL_RTX); | |
5356 | ||
5357 | rtx dest = SET_DEST (set); | |
5358 | ||
5359 | lra_assert (REG_P (dest)); | |
5360 | fprintf (lra_dump_file, | |
5361 | " Rejecting inheritance for insn %d(%s)<-%d(%s) " | |
5362 | "as secondary mem is needed\n", | |
5363 | REGNO (dest), reg_class_names[get_reg_class (REGNO (dest))], | |
c47331e3 | 5364 | original_regno, reg_class_names[rclass]); |
5bb0e0fd | 5365 | fprintf (lra_dump_file, |
5366 | " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); | |
5367 | } | |
5368 | return false; | |
5369 | } | |
c6a6cdaa | 5370 | new_reg = lra_create_new_reg (GET_MODE (original_reg), original_reg, |
5371 | rclass, "inheritance"); | |
5372 | start_sequence (); | |
5373 | if (def_p) | |
ef0231e9 | 5374 | lra_emit_move (original_reg, new_reg); |
c6a6cdaa | 5375 | else |
ef0231e9 | 5376 | lra_emit_move (new_reg, original_reg); |
c6a6cdaa | 5377 | new_insns = get_insns (); |
5378 | end_sequence (); | |
5379 | if (NEXT_INSN (new_insns) != NULL_RTX) | |
5380 | { | |
5381 | if (lra_dump_file != NULL) | |
5382 | { | |
5383 | fprintf (lra_dump_file, | |
5bb0e0fd | 5384 | " Rejecting inheritance %d->%d " |
c6a6cdaa | 5385 | "as it results in 2 or more insns:\n", |
5386 | original_regno, REGNO (new_reg)); | |
4cd001d5 | 5387 | dump_rtl_slim (lra_dump_file, new_insns, NULL, -1, 0); |
c6a6cdaa | 5388 | fprintf (lra_dump_file, |
5389 | " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); | |
5390 | } | |
5391 | return false; | |
5392 | } | |
06072e79 | 5393 | lra_substitute_pseudo_within_insn (insn, original_regno, new_reg, false); |
c6a6cdaa | 5394 | lra_update_insn_regno_info (insn); |
5395 | if (! def_p) | |
5396 | /* We now have a new usage insn for original regno. */ | |
5397 | setup_next_usage_insn (original_regno, new_insns, reloads_num, false); | |
5398 | if (lra_dump_file != NULL) | |
5bb0e0fd | 5399 | fprintf (lra_dump_file, " Original reg change %d->%d (bb%d):\n", |
c6a6cdaa | 5400 | original_regno, REGNO (new_reg), BLOCK_FOR_INSN (insn)->index); |
ab4ea053 | 5401 | lra_reg_info[REGNO (new_reg)].restore_rtx = regno_reg_rtx[original_regno]; |
c6a6cdaa | 5402 | bitmap_set_bit (&check_only_regs, REGNO (new_reg)); |
5403 | bitmap_set_bit (&check_only_regs, original_regno); | |
5404 | bitmap_set_bit (&lra_inheritance_pseudos, REGNO (new_reg)); | |
5405 | if (def_p) | |
7f836b57 | 5406 | lra_process_new_insns (insn, NULL, new_insns, |
c6a6cdaa | 5407 | "Add original<-inheritance"); |
5408 | else | |
7f836b57 | 5409 | lra_process_new_insns (insn, new_insns, NULL, |
c6a6cdaa | 5410 | "Add inheritance<-original"); |
5411 | while (next_usage_insns != NULL_RTX) | |
5412 | { | |
5413 | if (GET_CODE (next_usage_insns) != INSN_LIST) | |
5414 | { | |
5415 | usage_insn = next_usage_insns; | |
5416 | lra_assert (NONDEBUG_INSN_P (usage_insn)); | |
5417 | next_usage_insns = NULL; | |
5418 | } | |
5419 | else | |
5420 | { | |
5421 | usage_insn = XEXP (next_usage_insns, 0); | |
5422 | lra_assert (DEBUG_INSN_P (usage_insn)); | |
5423 | next_usage_insns = XEXP (next_usage_insns, 1); | |
5424 | } | |
d686eece | 5425 | lra_substitute_pseudo (&usage_insn, original_regno, new_reg, false, |
5426 | DEBUG_INSN_P (usage_insn)); | |
7f836b57 | 5427 | lra_update_insn_regno_info (as_a <rtx_insn *> (usage_insn)); |
c6a6cdaa | 5428 | if (lra_dump_file != NULL) |
5429 | { | |
90567983 | 5430 | basic_block bb = BLOCK_FOR_INSN (usage_insn); |
c6a6cdaa | 5431 | fprintf (lra_dump_file, |
5432 | " Inheritance reuse change %d->%d (bb%d):\n", | |
5433 | original_regno, REGNO (new_reg), | |
90567983 | 5434 | bb ? bb->index : -1); |
f9a00e9e | 5435 | dump_insn_slim (lra_dump_file, as_a <rtx_insn *> (usage_insn)); |
c6a6cdaa | 5436 | } |
5437 | } | |
5438 | if (lra_dump_file != NULL) | |
5439 | fprintf (lra_dump_file, | |
5440 | " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); | |
5441 | return true; | |
5442 | } | |
5443 | ||
5444 | /* Return true if we need a caller save/restore for pseudo REGNO which | |
5445 | was assigned to a hard register. */ | |
5446 | static inline bool | |
5447 | need_for_call_save_p (int regno) | |
5448 | { | |
5449 | lra_assert (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] >= 0); | |
2f9fa72f | 5450 | if (usage_insns[regno].calls_num < calls_num) |
5451 | { | |
5452 | unsigned int abis = 0; | |
5453 | for (unsigned int i = 0; i < NUM_ABI_IDS; ++i) | |
5454 | if (last_call_for_abi[i] > usage_insns[regno].calls_num) | |
5455 | abis |= 1 << i; | |
5456 | gcc_assert (abis); | |
5457 | if (call_clobbered_in_region_p (abis, full_and_partial_call_clobbers, | |
5458 | PSEUDO_REGNO_MODE (regno), | |
5459 | reg_renumber[regno])) | |
5460 | return true; | |
5461 | } | |
5462 | return false; | |
c6a6cdaa | 5463 | } |
5464 | ||
75de4aa2 | 5465 | /* Global registers occurring in the current EBB. */ |
c6a6cdaa | 5466 | static bitmap_head ebb_global_regs; |
5467 | ||
5468 | /* Return true if we need a split for hard register REGNO or pseudo | |
5469 | REGNO which was assigned to a hard register. | |
5470 | POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be | |
5471 | used for reloads since the EBB end. It is an approximation of the | |
5472 | used hard registers in the split range. The exact value would | |
5473 | require expensive calculations. If we were aggressive with | |
5474 | splitting because of the approximation, the split pseudo will save | |
5475 | the same hard register assignment and will be removed in the undo | |
5476 | pass. We still need the approximation because too aggressive | |
5477 | splitting would result in too inaccurate cost calculation in the | |
5478 | assignment pass because of too many generated moves which will be | |
5479 | probably removed in the undo pass. */ | |
5480 | static inline bool | |
5481 | need_for_split_p (HARD_REG_SET potential_reload_hard_regs, int regno) | |
5482 | { | |
5483 | int hard_regno = regno < FIRST_PSEUDO_REGISTER ? regno : reg_renumber[regno]; | |
5484 | ||
5485 | lra_assert (hard_regno >= 0); | |
5486 | return ((TEST_HARD_REG_BIT (potential_reload_hard_regs, hard_regno) | |
5487 | /* Don't split eliminable hard registers, otherwise we can | |
5488 | split hard registers like hard frame pointer, which | |
5489 | lives on BB start/end according to DF-infrastructure, | |
5490 | when there is a pseudo assigned to the register and | |
5491 | living in the same BB. */ | |
5492 | && (regno >= FIRST_PSEUDO_REGISTER | |
5493 | || ! TEST_HARD_REG_BIT (eliminable_regset, hard_regno)) | |
5494 | && ! TEST_HARD_REG_BIT (lra_no_alloc_regs, hard_regno) | |
0157439c | 5495 | /* Don't split call clobbered hard regs living through |
5496 | calls, otherwise we might have a check problem in the | |
5497 | assign sub-pass as in the most cases (exception is a | |
5498 | situation when lra_risky_transformations_p value is | |
5499 | true) the assign pass assumes that all pseudos living | |
5500 | through calls are assigned to call saved hard regs. */ | |
5501 | && (regno >= FIRST_PSEUDO_REGISTER | |
2f9fa72f | 5502 | || !TEST_HARD_REG_BIT (full_and_partial_call_clobbers, regno)) |
c6a6cdaa | 5503 | /* We need at least 2 reloads to make pseudo splitting |
5504 | profitable. We should provide hard regno splitting in | |
5505 | any case to solve 1st insn scheduling problem when | |
5506 | moving hard register definition up might result in | |
5507 | impossibility to find hard register for reload pseudo of | |
5508 | small register class. */ | |
5509 | && (usage_insns[regno].reloads_num | |
7eec3701 | 5510 | + (regno < FIRST_PSEUDO_REGISTER ? 0 : 3) < reloads_num) |
c6a6cdaa | 5511 | && (regno < FIRST_PSEUDO_REGISTER |
5512 | /* For short living pseudos, spilling + inheritance can | |
5513 | be considered a substitution for splitting. | |
5514 | Therefore we do not splitting for local pseudos. It | |
5515 | decreases also aggressiveness of splitting. The | |
5516 | minimal number of references is chosen taking into | |
5517 | account that for 2 references splitting has no sense | |
5518 | as we can just spill the pseudo. */ | |
5519 | || (regno >= FIRST_PSEUDO_REGISTER | |
5520 | && lra_reg_info[regno].nrefs > 3 | |
5521 | && bitmap_bit_p (&ebb_global_regs, regno)))) | |
5522 | || (regno >= FIRST_PSEUDO_REGISTER && need_for_call_save_p (regno))); | |
5523 | } | |
5524 | ||
5525 | /* Return class for the split pseudo created from original pseudo with | |
5526 | ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We | |
5527 | choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and | |
5528 | results in no secondary memory movements. */ | |
5529 | static enum reg_class | |
5530 | choose_split_class (enum reg_class allocno_class, | |
5531 | int hard_regno ATTRIBUTE_UNUSED, | |
3754d046 | 5532 | machine_mode mode ATTRIBUTE_UNUSED) |
c6a6cdaa | 5533 | { |
c6a6cdaa | 5534 | int i; |
5535 | enum reg_class cl, best_cl = NO_REGS; | |
d810a474 | 5536 | enum reg_class hard_reg_class ATTRIBUTE_UNUSED |
5537 | = REGNO_REG_CLASS (hard_regno); | |
1a8f8886 | 5538 | |
c836e75b | 5539 | if (! targetm.secondary_memory_needed (mode, allocno_class, allocno_class) |
c6a6cdaa | 5540 | && TEST_HARD_REG_BIT (reg_class_contents[allocno_class], hard_regno)) |
5541 | return allocno_class; | |
5542 | for (i = 0; | |
5543 | (cl = reg_class_subclasses[allocno_class][i]) != LIM_REG_CLASSES; | |
5544 | i++) | |
c836e75b | 5545 | if (! targetm.secondary_memory_needed (mode, cl, hard_reg_class) |
5546 | && ! targetm.secondary_memory_needed (mode, hard_reg_class, cl) | |
c6a6cdaa | 5547 | && TEST_HARD_REG_BIT (reg_class_contents[cl], hard_regno) |
5548 | && (best_cl == NO_REGS | |
5549 | || ira_class_hard_regs_num[best_cl] < ira_class_hard_regs_num[cl])) | |
5550 | best_cl = cl; | |
5551 | return best_cl; | |
c6a6cdaa | 5552 | } |
5553 | ||
cc39a634 | 5554 | /* Copy any equivalence information from ORIGINAL_REGNO to NEW_REGNO. |
5555 | It only makes sense to call this function if NEW_REGNO is always | |
5556 | equal to ORIGINAL_REGNO. */ | |
5557 | ||
5558 | static void | |
5559 | lra_copy_reg_equiv (unsigned int new_regno, unsigned int original_regno) | |
5560 | { | |
5561 | if (!ira_reg_equiv[original_regno].defined_p) | |
5562 | return; | |
5563 | ||
5564 | ira_expand_reg_equiv (); | |
5565 | ira_reg_equiv[new_regno].defined_p = true; | |
5566 | if (ira_reg_equiv[original_regno].memory) | |
5567 | ira_reg_equiv[new_regno].memory | |
5568 | = copy_rtx (ira_reg_equiv[original_regno].memory); | |
5569 | if (ira_reg_equiv[original_regno].constant) | |
5570 | ira_reg_equiv[new_regno].constant | |
5571 | = copy_rtx (ira_reg_equiv[original_regno].constant); | |
5572 | if (ira_reg_equiv[original_regno].invariant) | |
5573 | ira_reg_equiv[new_regno].invariant | |
5574 | = copy_rtx (ira_reg_equiv[original_regno].invariant); | |
5575 | } | |
5576 | ||
c6a6cdaa | 5577 | /* Do split transformations for insn INSN, which defines or uses |
5578 | ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in | |
5579 | the EBB next uses ORIGINAL_REGNO; it has the same form as the | |
6a4bc24e | 5580 | "insns" field of usage_insns. If TO is not NULL, we don't use |
7fe7987e | 5581 | usage_insns, we put restore insns after TO insn. It is a case when |
5582 | we call it from lra_split_hard_reg_for, outside the inheritance | |
5583 | pass. | |
c6a6cdaa | 5584 | |
5585 | The transformations look like: | |
5586 | ||
5587 | p <- ... p <- ... | |
5588 | ... s <- p (new insn -- save) | |
5589 | ... => | |
5590 | ... p <- s (new insn -- restore) | |
5591 | <- ... p ... <- ... p ... | |
5592 | or | |
5593 | <- ... p ... <- ... p ... | |
5594 | ... s <- p (new insn -- save) | |
5595 | ... => | |
5596 | ... p <- s (new insn -- restore) | |
5597 | <- ... p ... <- ... p ... | |
5598 | ||
5599 | where p is an original pseudo got a hard register or a hard | |
5600 | register and s is a new split pseudo. The save is put before INSN | |
5601 | if BEFORE_P is true. Return true if we succeed in such | |
5602 | transformation. */ | |
5603 | static bool | |
7f836b57 | 5604 | split_reg (bool before_p, int original_regno, rtx_insn *insn, |
6a4bc24e | 5605 | rtx next_usage_insns, rtx_insn *to) |
c6a6cdaa | 5606 | { |
5607 | enum reg_class rclass; | |
5608 | rtx original_reg; | |
74855d08 | 5609 | int hard_regno, nregs; |
7f836b57 | 5610 | rtx new_reg, usage_insn; |
5611 | rtx_insn *restore, *save; | |
c6a6cdaa | 5612 | bool after_p; |
5613 | bool call_save_p; | |
e947f9c3 | 5614 | machine_mode mode; |
c6a6cdaa | 5615 | |
5616 | if (original_regno < FIRST_PSEUDO_REGISTER) | |
5617 | { | |
5618 | rclass = ira_allocno_class_translate[REGNO_REG_CLASS (original_regno)]; | |
5619 | hard_regno = original_regno; | |
5620 | call_save_p = false; | |
74855d08 | 5621 | nregs = 1; |
e947f9c3 | 5622 | mode = lra_reg_info[hard_regno].biggest_mode; |
5623 | machine_mode reg_rtx_mode = GET_MODE (regno_reg_rtx[hard_regno]); | |
e7142ce1 | 5624 | /* A reg can have a biggest_mode of VOIDmode if it was only ever seen |
5625 | as part of a multi-word register. In that case, or if the biggest | |
5626 | mode was larger than a register, just use the reg_rtx. Otherwise, | |
5627 | limit the size to that of the biggest access in the function. */ | |
5628 | if (mode == VOIDmode | |
d0257d43 | 5629 | || paradoxical_subreg_p (mode, reg_rtx_mode)) |
e947f9c3 | 5630 | { |
5631 | original_reg = regno_reg_rtx[hard_regno]; | |
5632 | mode = reg_rtx_mode; | |
5633 | } | |
5634 | else | |
5635 | original_reg = gen_rtx_REG (mode, hard_regno); | |
c6a6cdaa | 5636 | } |
5637 | else | |
5638 | { | |
e947f9c3 | 5639 | mode = PSEUDO_REGNO_MODE (original_regno); |
c6a6cdaa | 5640 | hard_regno = reg_renumber[original_regno]; |
92d2aec3 | 5641 | nregs = hard_regno_nregs (hard_regno, mode); |
c6a6cdaa | 5642 | rclass = lra_get_allocno_class (original_regno); |
5643 | original_reg = regno_reg_rtx[original_regno]; | |
5644 | call_save_p = need_for_call_save_p (original_regno); | |
5645 | } | |
c6a6cdaa | 5646 | lra_assert (hard_regno >= 0); |
5647 | if (lra_dump_file != NULL) | |
5648 | fprintf (lra_dump_file, | |
5649 | " ((((((((((((((((((((((((((((((((((((((((((((((((\n"); | |
e947f9c3 | 5650 | |
c6a6cdaa | 5651 | if (call_save_p) |
5652 | { | |
34575461 | 5653 | mode = HARD_REGNO_CALLER_SAVE_MODE (hard_regno, |
92d2aec3 | 5654 | hard_regno_nregs (hard_regno, mode), |
34575461 | 5655 | mode); |
5656 | new_reg = lra_create_new_reg (mode, NULL_RTX, NO_REGS, "save"); | |
c6a6cdaa | 5657 | } |
5658 | else | |
5659 | { | |
e947f9c3 | 5660 | rclass = choose_split_class (rclass, hard_regno, mode); |
c6a6cdaa | 5661 | if (rclass == NO_REGS) |
5662 | { | |
5663 | if (lra_dump_file != NULL) | |
5664 | { | |
5665 | fprintf (lra_dump_file, | |
5666 | " Rejecting split of %d(%s): " | |
5667 | "no good reg class for %d(%s)\n", | |
5668 | original_regno, | |
5669 | reg_class_names[lra_get_allocno_class (original_regno)], | |
5670 | hard_regno, | |
5671 | reg_class_names[REGNO_REG_CLASS (hard_regno)]); | |
5672 | fprintf | |
5673 | (lra_dump_file, | |
5674 | " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); | |
5675 | } | |
5676 | return false; | |
5677 | } | |
4f031018 | 5678 | /* Split_if_necessary can split hard registers used as part of a |
5679 | multi-register mode but splits each register individually. The | |
5680 | mode used for each independent register may not be supported | |
5681 | so reject the split. Splitting the wider mode should theoretically | |
5682 | be possible but is not implemented. */ | |
b395382f | 5683 | if (!targetm.hard_regno_mode_ok (hard_regno, mode)) |
4f031018 | 5684 | { |
5685 | if (lra_dump_file != NULL) | |
5686 | { | |
5687 | fprintf (lra_dump_file, | |
5688 | " Rejecting split of %d(%s): unsuitable mode %s\n", | |
5689 | original_regno, | |
5690 | reg_class_names[lra_get_allocno_class (original_regno)], | |
5691 | GET_MODE_NAME (mode)); | |
5692 | fprintf | |
5693 | (lra_dump_file, | |
5694 | " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); | |
5695 | } | |
5696 | return false; | |
5697 | } | |
e947f9c3 | 5698 | new_reg = lra_create_new_reg (mode, original_reg, rclass, "split"); |
c6a6cdaa | 5699 | reg_renumber[REGNO (new_reg)] = hard_regno; |
5700 | } | |
cc39a634 | 5701 | int new_regno = REGNO (new_reg); |
c6a6cdaa | 5702 | save = emit_spill_move (true, new_reg, original_reg); |
52793acd | 5703 | if (NEXT_INSN (save) != NULL_RTX && !call_save_p) |
c6a6cdaa | 5704 | { |
c6a6cdaa | 5705 | if (lra_dump_file != NULL) |
5706 | { | |
5707 | fprintf | |
5708 | (lra_dump_file, | |
52793acd | 5709 | " Rejecting split %d->%d resulting in > 2 save insns:\n", |
cc39a634 | 5710 | original_regno, new_regno); |
4cd001d5 | 5711 | dump_rtl_slim (lra_dump_file, save, NULL, -1, 0); |
c6a6cdaa | 5712 | fprintf (lra_dump_file, |
5713 | " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); | |
5714 | } | |
5715 | return false; | |
5716 | } | |
5717 | restore = emit_spill_move (false, new_reg, original_reg); | |
52793acd | 5718 | if (NEXT_INSN (restore) != NULL_RTX && !call_save_p) |
c6a6cdaa | 5719 | { |
c6a6cdaa | 5720 | if (lra_dump_file != NULL) |
5721 | { | |
5722 | fprintf (lra_dump_file, | |
5723 | " Rejecting split %d->%d " | |
52793acd | 5724 | "resulting in > 2 restore insns:\n", |
cc39a634 | 5725 | original_regno, new_regno); |
4cd001d5 | 5726 | dump_rtl_slim (lra_dump_file, restore, NULL, -1, 0); |
c6a6cdaa | 5727 | fprintf (lra_dump_file, |
5728 | " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); | |
5729 | } | |
5730 | return false; | |
5731 | } | |
cc39a634 | 5732 | /* Transfer equivalence information to the spill register, so that |
5733 | if we fail to allocate the spill register, we have the option of | |
5734 | rematerializing the original value instead of spilling to the stack. */ | |
5735 | if (!HARD_REGISTER_NUM_P (original_regno) | |
5736 | && mode == PSEUDO_REGNO_MODE (original_regno)) | |
5737 | lra_copy_reg_equiv (new_regno, original_regno); | |
cc39a634 | 5738 | lra_reg_info[new_regno].restore_rtx = regno_reg_rtx[original_regno]; |
cc39a634 | 5739 | bitmap_set_bit (&lra_split_regs, new_regno); |
6a4bc24e | 5740 | if (to != NULL) |
c6a6cdaa | 5741 | { |
7fe7987e | 5742 | lra_assert (next_usage_insns == NULL); |
6a4bc24e | 5743 | usage_insn = to; |
5744 | after_p = TRUE; | |
5745 | } | |
5746 | else | |
5747 | { | |
7fe7987e | 5748 | /* We need check_only_regs only inside the inheritance pass. */ |
5749 | bitmap_set_bit (&check_only_regs, new_regno); | |
5750 | bitmap_set_bit (&check_only_regs, original_regno); | |
6a4bc24e | 5751 | after_p = usage_insns[original_regno].after_p; |
5752 | for (;;) | |
b12c2c48 | 5753 | { |
6a4bc24e | 5754 | if (GET_CODE (next_usage_insns) != INSN_LIST) |
5755 | { | |
5756 | usage_insn = next_usage_insns; | |
5757 | break; | |
5758 | } | |
5759 | usage_insn = XEXP (next_usage_insns, 0); | |
5760 | lra_assert (DEBUG_INSN_P (usage_insn)); | |
5761 | next_usage_insns = XEXP (next_usage_insns, 1); | |
5762 | lra_substitute_pseudo (&usage_insn, original_regno, new_reg, false, | |
5763 | true); | |
5764 | lra_update_insn_regno_info (as_a <rtx_insn *> (usage_insn)); | |
5765 | if (lra_dump_file != NULL) | |
5766 | { | |
5767 | fprintf (lra_dump_file, " Split reuse change %d->%d:\n", | |
5768 | original_regno, new_regno); | |
5769 | dump_insn_slim (lra_dump_file, as_a <rtx_insn *> (usage_insn)); | |
5770 | } | |
c6a6cdaa | 5771 | } |
5772 | } | |
5773 | lra_assert (NOTE_P (usage_insn) || NONDEBUG_INSN_P (usage_insn)); | |
5774 | lra_assert (usage_insn != insn || (after_p && before_p)); | |
7f836b57 | 5775 | lra_process_new_insns (as_a <rtx_insn *> (usage_insn), |
5776 | after_p ? NULL : restore, | |
5777 | after_p ? restore : NULL, | |
c6a6cdaa | 5778 | call_save_p |
5779 | ? "Add reg<-save" : "Add reg<-split"); | |
7f836b57 | 5780 | lra_process_new_insns (insn, before_p ? save : NULL, |
5781 | before_p ? NULL : save, | |
c6a6cdaa | 5782 | call_save_p |
5783 | ? "Add save<-reg" : "Add split<-reg"); | |
74855d08 | 5784 | if (nregs > 1) |
5785 | /* If we are trying to split multi-register. We should check | |
5786 | conflicts on the next assignment sub-pass. IRA can allocate on | |
5787 | sub-register levels, LRA do this on pseudos level right now and | |
5788 | this discrepancy may create allocation conflicts after | |
5789 | splitting. */ | |
5790 | lra_risky_transformations_p = true; | |
c6a6cdaa | 5791 | if (lra_dump_file != NULL) |
5792 | fprintf (lra_dump_file, | |
5793 | " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); | |
5794 | return true; | |
5795 | } | |
5796 | ||
6a4bc24e | 5797 | /* Split a hard reg for reload pseudo REGNO having RCLASS and living |
5798 | in the range [FROM, TO]. Return true if did a split. Otherwise, | |
5799 | return false. */ | |
5800 | bool | |
5801 | spill_hard_reg_in_range (int regno, enum reg_class rclass, rtx_insn *from, rtx_insn *to) | |
5802 | { | |
5803 | int i, hard_regno; | |
5804 | int rclass_size; | |
5805 | rtx_insn *insn; | |
eaefe34f | 5806 | unsigned int uid; |
5807 | bitmap_iterator bi; | |
5808 | HARD_REG_SET ignore; | |
6a4bc24e | 5809 | |
5810 | lra_assert (from != NULL && to != NULL); | |
eaefe34f | 5811 | CLEAR_HARD_REG_SET (ignore); |
5812 | EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi) | |
5813 | { | |
5814 | lra_insn_recog_data_t id = lra_insn_recog_data[uid]; | |
5815 | struct lra_static_insn_data *static_id = id->insn_static_data; | |
5816 | struct lra_insn_reg *reg; | |
5817 | ||
5818 | for (reg = id->regs; reg != NULL; reg = reg->next) | |
c1031b5a | 5819 | if (reg->regno < FIRST_PSEUDO_REGISTER) |
eaefe34f | 5820 | SET_HARD_REG_BIT (ignore, reg->regno); |
5821 | for (reg = static_id->hard_regs; reg != NULL; reg = reg->next) | |
5822 | SET_HARD_REG_BIT (ignore, reg->regno); | |
5823 | } | |
6a4bc24e | 5824 | rclass_size = ira_class_hard_regs_num[rclass]; |
5825 | for (i = 0; i < rclass_size; i++) | |
5826 | { | |
5827 | hard_regno = ira_class_hard_regs[rclass][i]; | |
eaefe34f | 5828 | if (! TEST_HARD_REG_BIT (lra_reg_info[regno].conflict_hard_regs, hard_regno) |
5829 | || TEST_HARD_REG_BIT (ignore, hard_regno)) | |
6a4bc24e | 5830 | continue; |
5831 | for (insn = from; insn != NEXT_INSN (to); insn = NEXT_INSN (insn)) | |
730ba3b8 | 5832 | { |
6f7735c6 | 5833 | struct lra_static_insn_data *static_id; |
730ba3b8 | 5834 | struct lra_insn_reg *reg; |
5835 | ||
6f7735c6 | 5836 | if (!INSN_P (insn)) |
5837 | continue; | |
5838 | if (bitmap_bit_p (&lra_reg_info[hard_regno].insn_bitmap, | |
5839 | INSN_UID (insn))) | |
730ba3b8 | 5840 | break; |
6f7735c6 | 5841 | static_id = lra_get_insn_recog_data (insn)->insn_static_data; |
730ba3b8 | 5842 | for (reg = static_id->hard_regs; reg != NULL; reg = reg->next) |
5843 | if (reg->regno == hard_regno) | |
5844 | break; | |
5845 | if (reg != NULL) | |
5846 | break; | |
5847 | } | |
6a4bc24e | 5848 | if (insn != NEXT_INSN (to)) |
5849 | continue; | |
5850 | if (split_reg (TRUE, hard_regno, from, NULL, to)) | |
5851 | return true; | |
5852 | } | |
5853 | return false; | |
5854 | } | |
5855 | ||
c6a6cdaa | 5856 | /* Recognize that we need a split transformation for insn INSN, which |
5857 | defines or uses REGNO in its insn biggest MODE (we use it only if | |
5858 | REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains | |
5859 | hard registers which might be used for reloads since the EBB end. | |
5860 | Put the save before INSN if BEFORE_P is true. MAX_UID is maximla | |
5861 | uid before starting INSN processing. Return true if we succeed in | |
5862 | such transformation. */ | |
5863 | static bool | |
3754d046 | 5864 | split_if_necessary (int regno, machine_mode mode, |
c6a6cdaa | 5865 | HARD_REG_SET potential_reload_hard_regs, |
7f836b57 | 5866 | bool before_p, rtx_insn *insn, int max_uid) |
c6a6cdaa | 5867 | { |
5868 | bool res = false; | |
5869 | int i, nregs = 1; | |
5870 | rtx next_usage_insns; | |
5871 | ||
5872 | if (regno < FIRST_PSEUDO_REGISTER) | |
92d2aec3 | 5873 | nregs = hard_regno_nregs (regno, mode); |
c6a6cdaa | 5874 | for (i = 0; i < nregs; i++) |
5875 | if (usage_insns[regno + i].check == curr_usage_insns_check | |
5876 | && (next_usage_insns = usage_insns[regno + i].insns) != NULL_RTX | |
5877 | /* To avoid processing the register twice or more. */ | |
5878 | && ((GET_CODE (next_usage_insns) != INSN_LIST | |
5879 | && INSN_UID (next_usage_insns) < max_uid) | |
5880 | || (GET_CODE (next_usage_insns) == INSN_LIST | |
5881 | && (INSN_UID (XEXP (next_usage_insns, 0)) < max_uid))) | |
5882 | && need_for_split_p (potential_reload_hard_regs, regno + i) | |
6a4bc24e | 5883 | && split_reg (before_p, regno + i, insn, next_usage_insns, NULL)) |
c6a6cdaa | 5884 | res = true; |
5885 | return res; | |
5886 | } | |
5887 | ||
ab4ea053 | 5888 | /* Return TRUE if rtx X is considered as an invariant for |
5889 | inheritance. */ | |
5890 | static bool | |
5891 | invariant_p (const_rtx x) | |
5892 | { | |
5893 | machine_mode mode; | |
5894 | const char *fmt; | |
5895 | enum rtx_code code; | |
5896 | int i, j; | |
5897 | ||
00d7c794 | 5898 | if (side_effects_p (x)) |
5899 | return false; | |
5900 | ||
ab4ea053 | 5901 | code = GET_CODE (x); |
5902 | mode = GET_MODE (x); | |
5903 | if (code == SUBREG) | |
5904 | { | |
5905 | x = SUBREG_REG (x); | |
5906 | code = GET_CODE (x); | |
081c1d32 | 5907 | mode = wider_subreg_mode (mode, GET_MODE (x)); |
ab4ea053 | 5908 | } |
5909 | ||
5910 | if (MEM_P (x)) | |
5911 | return false; | |
5912 | ||
5913 | if (REG_P (x)) | |
5914 | { | |
5915 | int i, nregs, regno = REGNO (x); | |
5916 | ||
5917 | if (regno >= FIRST_PSEUDO_REGISTER || regno == STACK_POINTER_REGNUM | |
5918 | || TEST_HARD_REG_BIT (eliminable_regset, regno) | |
5919 | || GET_MODE_CLASS (GET_MODE (x)) == MODE_CC) | |
5920 | return false; | |
92d2aec3 | 5921 | nregs = hard_regno_nregs (regno, mode); |
ab4ea053 | 5922 | for (i = 0; i < nregs; i++) |
5923 | if (! fixed_regs[regno + i] | |
5924 | /* A hard register may be clobbered in the current insn | |
5925 | but we can ignore this case because if the hard | |
5926 | register is used it should be set somewhere after the | |
5927 | clobber. */ | |
5928 | || bitmap_bit_p (&invalid_invariant_regs, regno + i)) | |
5929 | return false; | |
5930 | } | |
5931 | fmt = GET_RTX_FORMAT (code); | |
5932 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
5933 | { | |
5934 | if (fmt[i] == 'e') | |
5935 | { | |
5936 | if (! invariant_p (XEXP (x, i))) | |
5937 | return false; | |
5938 | } | |
5939 | else if (fmt[i] == 'E') | |
5940 | { | |
5941 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
5942 | if (! invariant_p (XVECEXP (x, i, j))) | |
5943 | return false; | |
5944 | } | |
5945 | } | |
5946 | return true; | |
5947 | } | |
5948 | ||
5949 | /* We have 'dest_reg <- invariant'. Let us try to make an invariant | |
5950 | inheritance transformation (using dest_reg instead invariant in a | |
5951 | subsequent insn). */ | |
5952 | static bool | |
5953 | process_invariant_for_inheritance (rtx dst_reg, rtx invariant_rtx) | |
5954 | { | |
5955 | invariant_ptr_t invariant_ptr; | |
5956 | rtx_insn *insn, *new_insns; | |
5957 | rtx insn_set, insn_reg, new_reg; | |
5958 | int insn_regno; | |
5959 | bool succ_p = false; | |
5960 | int dst_regno = REGNO (dst_reg); | |
582adad1 | 5961 | machine_mode dst_mode = GET_MODE (dst_reg); |
ab4ea053 | 5962 | enum reg_class cl = lra_get_allocno_class (dst_regno), insn_reg_cl; |
5963 | ||
5964 | invariant_ptr = insert_invariant (invariant_rtx); | |
5965 | if ((insn = invariant_ptr->insn) != NULL_RTX) | |
5966 | { | |
5967 | /* We have a subsequent insn using the invariant. */ | |
5968 | insn_set = single_set (insn); | |
5969 | lra_assert (insn_set != NULL); | |
5970 | insn_reg = SET_DEST (insn_set); | |
5971 | lra_assert (REG_P (insn_reg)); | |
5972 | insn_regno = REGNO (insn_reg); | |
5973 | insn_reg_cl = lra_get_allocno_class (insn_regno); | |
5974 | ||
5975 | if (dst_mode == GET_MODE (insn_reg) | |
5976 | /* We should consider only result move reg insns which are | |
5977 | cheap. */ | |
5978 | && targetm.register_move_cost (dst_mode, cl, insn_reg_cl) == 2 | |
5979 | && targetm.register_move_cost (dst_mode, cl, cl) == 2) | |
5980 | { | |
5981 | if (lra_dump_file != NULL) | |
5982 | fprintf (lra_dump_file, | |
5983 | " [[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[\n"); | |
5984 | new_reg = lra_create_new_reg (dst_mode, dst_reg, | |
5985 | cl, "invariant inheritance"); | |
5986 | bitmap_set_bit (&lra_inheritance_pseudos, REGNO (new_reg)); | |
5987 | bitmap_set_bit (&check_only_regs, REGNO (new_reg)); | |
fee93b91 | 5988 | lra_reg_info[REGNO (new_reg)].restore_rtx = PATTERN (insn); |
ab4ea053 | 5989 | start_sequence (); |
5990 | lra_emit_move (new_reg, dst_reg); | |
5991 | new_insns = get_insns (); | |
5992 | end_sequence (); | |
5993 | lra_process_new_insns (curr_insn, NULL, new_insns, | |
5994 | "Add invariant inheritance<-original"); | |
5995 | start_sequence (); | |
5996 | lra_emit_move (SET_DEST (insn_set), new_reg); | |
5997 | new_insns = get_insns (); | |
5998 | end_sequence (); | |
5999 | lra_process_new_insns (insn, NULL, new_insns, | |
6000 | "Changing reload<-inheritance"); | |
6001 | lra_set_insn_deleted (insn); | |
6002 | succ_p = true; | |
6003 | if (lra_dump_file != NULL) | |
6004 | { | |
6005 | fprintf (lra_dump_file, | |
6006 | " Invariant inheritance reuse change %d (bb%d):\n", | |
6007 | REGNO (new_reg), BLOCK_FOR_INSN (insn)->index); | |
6008 | dump_insn_slim (lra_dump_file, insn); | |
6009 | fprintf (lra_dump_file, | |
6010 | " ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]\n"); | |
6011 | } | |
6012 | } | |
6013 | } | |
6014 | invariant_ptr->insn = curr_insn; | |
6015 | return succ_p; | |
6016 | } | |
6017 | ||
c6a6cdaa | 6018 | /* Check only registers living at the current program point in the |
6019 | current EBB. */ | |
6020 | static bitmap_head live_regs; | |
6021 | ||
6022 | /* Update live info in EBB given by its HEAD and TAIL insns after | |
6023 | inheritance/split transformation. The function removes dead moves | |
6024 | too. */ | |
6025 | static void | |
7f836b57 | 6026 | update_ebb_live_info (rtx_insn *head, rtx_insn *tail) |
c6a6cdaa | 6027 | { |
6028 | unsigned int j; | |
7eec3701 | 6029 | int i, regno; |
c6a6cdaa | 6030 | bool live_p; |
7f836b57 | 6031 | rtx_insn *prev_insn; |
6032 | rtx set; | |
c6a6cdaa | 6033 | bool remove_p; |
6034 | basic_block last_bb, prev_bb, curr_bb; | |
6035 | bitmap_iterator bi; | |
6036 | struct lra_insn_reg *reg; | |
6037 | edge e; | |
6038 | edge_iterator ei; | |
6039 | ||
1a8f8886 | 6040 | last_bb = BLOCK_FOR_INSN (tail); |
c6a6cdaa | 6041 | prev_bb = NULL; |
6042 | for (curr_insn = tail; | |
6043 | curr_insn != PREV_INSN (head); | |
6044 | curr_insn = prev_insn) | |
6045 | { | |
6046 | prev_insn = PREV_INSN (curr_insn); | |
76d77f1e | 6047 | /* We need to process empty blocks too. They contain |
6048 | NOTE_INSN_BASIC_BLOCK referring for the basic block. */ | |
6049 | if (NOTE_P (curr_insn) && NOTE_KIND (curr_insn) != NOTE_INSN_BASIC_BLOCK) | |
6050 | continue; | |
c6a6cdaa | 6051 | curr_bb = BLOCK_FOR_INSN (curr_insn); |
6052 | if (curr_bb != prev_bb) | |
6053 | { | |
6054 | if (prev_bb != NULL) | |
6055 | { | |
6056 | /* Update df_get_live_in (prev_bb): */ | |
6057 | EXECUTE_IF_SET_IN_BITMAP (&check_only_regs, 0, j, bi) | |
6058 | if (bitmap_bit_p (&live_regs, j)) | |
6059 | bitmap_set_bit (df_get_live_in (prev_bb), j); | |
6060 | else | |
6061 | bitmap_clear_bit (df_get_live_in (prev_bb), j); | |
6062 | } | |
6063 | if (curr_bb != last_bb) | |
6064 | { | |
6065 | /* Update df_get_live_out (curr_bb): */ | |
6066 | EXECUTE_IF_SET_IN_BITMAP (&check_only_regs, 0, j, bi) | |
6067 | { | |
6068 | live_p = bitmap_bit_p (&live_regs, j); | |
6069 | if (! live_p) | |
6070 | FOR_EACH_EDGE (e, ei, curr_bb->succs) | |
6071 | if (bitmap_bit_p (df_get_live_in (e->dest), j)) | |
6072 | { | |
6073 | live_p = true; | |
6074 | break; | |
6075 | } | |
6076 | if (live_p) | |
6077 | bitmap_set_bit (df_get_live_out (curr_bb), j); | |
6078 | else | |
6079 | bitmap_clear_bit (df_get_live_out (curr_bb), j); | |
6080 | } | |
6081 | } | |
6082 | prev_bb = curr_bb; | |
6083 | bitmap_and (&live_regs, &check_only_regs, df_get_live_out (curr_bb)); | |
6084 | } | |
0f31edc8 | 6085 | if (! NONDEBUG_INSN_P (curr_insn)) |
c6a6cdaa | 6086 | continue; |
6087 | curr_id = lra_get_insn_recog_data (curr_insn); | |
7eec3701 | 6088 | curr_static_id = curr_id->insn_static_data; |
c6a6cdaa | 6089 | remove_p = false; |
5c819ea0 | 6090 | if ((set = single_set (curr_insn)) != NULL_RTX |
6091 | && REG_P (SET_DEST (set)) | |
c6a6cdaa | 6092 | && (regno = REGNO (SET_DEST (set))) >= FIRST_PSEUDO_REGISTER |
5c819ea0 | 6093 | && SET_DEST (set) != pic_offset_table_rtx |
c6a6cdaa | 6094 | && bitmap_bit_p (&check_only_regs, regno) |
6095 | && ! bitmap_bit_p (&live_regs, regno)) | |
6096 | remove_p = true; | |
6097 | /* See which defined values die here. */ | |
6098 | for (reg = curr_id->regs; reg != NULL; reg = reg->next) | |
6099 | if (reg->type == OP_OUT && ! reg->subreg_p) | |
6100 | bitmap_clear_bit (&live_regs, reg->regno); | |
7eec3701 | 6101 | for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next) |
6102 | if (reg->type == OP_OUT && ! reg->subreg_p) | |
6103 | bitmap_clear_bit (&live_regs, reg->regno); | |
853a01d6 | 6104 | if (curr_id->arg_hard_regs != NULL) |
6105 | /* Make clobbered argument hard registers die. */ | |
6106 | for (i = 0; (regno = curr_id->arg_hard_regs[i]) >= 0; i++) | |
6107 | if (regno >= FIRST_PSEUDO_REGISTER) | |
6108 | bitmap_clear_bit (&live_regs, regno - FIRST_PSEUDO_REGISTER); | |
c6a6cdaa | 6109 | /* Mark each used value as live. */ |
6110 | for (reg = curr_id->regs; reg != NULL; reg = reg->next) | |
53d78539 | 6111 | if (reg->type != OP_OUT |
c6a6cdaa | 6112 | && bitmap_bit_p (&check_only_regs, reg->regno)) |
6113 | bitmap_set_bit (&live_regs, reg->regno); | |
7eec3701 | 6114 | for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next) |
6115 | if (reg->type != OP_OUT | |
6116 | && bitmap_bit_p (&check_only_regs, reg->regno)) | |
6117 | bitmap_set_bit (&live_regs, reg->regno); | |
6118 | if (curr_id->arg_hard_regs != NULL) | |
853a01d6 | 6119 | /* Make used argument hard registers live. */ |
7eec3701 | 6120 | for (i = 0; (regno = curr_id->arg_hard_regs[i]) >= 0; i++) |
853a01d6 | 6121 | if (regno < FIRST_PSEUDO_REGISTER |
6122 | && bitmap_bit_p (&check_only_regs, regno)) | |
7eec3701 | 6123 | bitmap_set_bit (&live_regs, regno); |
c6a6cdaa | 6124 | /* It is quite important to remove dead move insns because it |
6125 | means removing dead store. We don't need to process them for | |
6126 | constraints. */ | |
6127 | if (remove_p) | |
6128 | { | |
6129 | if (lra_dump_file != NULL) | |
6130 | { | |
6131 | fprintf (lra_dump_file, " Removing dead insn:\n "); | |
6dde9719 | 6132 | dump_insn_slim (lra_dump_file, curr_insn); |
c6a6cdaa | 6133 | } |
6134 | lra_set_insn_deleted (curr_insn); | |
6135 | } | |
6136 | } | |
6137 | } | |
6138 | ||
6139 | /* The structure describes info to do an inheritance for the current | |
6140 | insn. We need to collect such info first before doing the | |
6141 | transformations because the transformations change the insn | |
6142 | internal representation. */ | |
6143 | struct to_inherit | |
6144 | { | |
6145 | /* Original regno. */ | |
6146 | int regno; | |
6147 | /* Subsequent insns which can inherit original reg value. */ | |
6148 | rtx insns; | |
6149 | }; | |
6150 | ||
6151 | /* Array containing all info for doing inheritance from the current | |
6152 | insn. */ | |
6153 | static struct to_inherit to_inherit[LRA_MAX_INSN_RELOADS]; | |
6154 | ||
6155 | /* Number elements in the previous array. */ | |
6156 | static int to_inherit_num; | |
6157 | ||
6158 | /* Add inheritance info REGNO and INSNS. Their meaning is described in | |
6159 | structure to_inherit. */ | |
6160 | static void | |
6161 | add_to_inherit (int regno, rtx insns) | |
6162 | { | |
6163 | int i; | |
6164 | ||
6165 | for (i = 0; i < to_inherit_num; i++) | |
6166 | if (to_inherit[i].regno == regno) | |
6167 | return; | |
6168 | lra_assert (to_inherit_num < LRA_MAX_INSN_RELOADS); | |
6169 | to_inherit[to_inherit_num].regno = regno; | |
6170 | to_inherit[to_inherit_num++].insns = insns; | |
6171 | } | |
6172 | ||
6173 | /* Return the last non-debug insn in basic block BB, or the block begin | |
6174 | note if none. */ | |
7f836b57 | 6175 | static rtx_insn * |
c6a6cdaa | 6176 | get_last_insertion_point (basic_block bb) |
6177 | { | |
7f836b57 | 6178 | rtx_insn *insn; |
c6a6cdaa | 6179 | |
6180 | FOR_BB_INSNS_REVERSE (bb, insn) | |
6181 | if (NONDEBUG_INSN_P (insn) || NOTE_INSN_BASIC_BLOCK_P (insn)) | |
6182 | return insn; | |
6183 | gcc_unreachable (); | |
6184 | } | |
6185 | ||
6186 | /* Set up RES by registers living on edges FROM except the edge (FROM, | |
6187 | TO) or by registers set up in a jump insn in BB FROM. */ | |
6188 | static void | |
6189 | get_live_on_other_edges (basic_block from, basic_block to, bitmap res) | |
6190 | { | |
7f836b57 | 6191 | rtx_insn *last; |
c6a6cdaa | 6192 | struct lra_insn_reg *reg; |
6193 | edge e; | |
6194 | edge_iterator ei; | |
6195 | ||
6196 | lra_assert (to != NULL); | |
6197 | bitmap_clear (res); | |
6198 | FOR_EACH_EDGE (e, ei, from->succs) | |
6199 | if (e->dest != to) | |
6200 | bitmap_ior_into (res, df_get_live_in (e->dest)); | |
6201 | last = get_last_insertion_point (from); | |
6202 | if (! JUMP_P (last)) | |
6203 | return; | |
6204 | curr_id = lra_get_insn_recog_data (last); | |
6205 | for (reg = curr_id->regs; reg != NULL; reg = reg->next) | |
6206 | if (reg->type != OP_IN) | |
6207 | bitmap_set_bit (res, reg->regno); | |
6208 | } | |
1a8f8886 | 6209 | |
c6a6cdaa | 6210 | /* Used as a temporary results of some bitmap calculations. */ |
6211 | static bitmap_head temp_bitmap; | |
6212 | ||
7eec3701 | 6213 | /* We split for reloads of small class of hard regs. The following |
6214 | defines how many hard regs the class should have to be qualified as | |
6215 | small. The code is mostly oriented to x86/x86-64 architecture | |
6216 | where some insns need to use only specific register or pair of | |
6217 | registers and these register can live in RTL explicitly, e.g. for | |
6218 | parameter passing. */ | |
6219 | static const int max_small_class_regs_num = 2; | |
6220 | ||
c6a6cdaa | 6221 | /* Do inheritance/split transformations in EBB starting with HEAD and |
6222 | finishing on TAIL. We process EBB insns in the reverse order. | |
6223 | Return true if we did any inheritance/split transformation in the | |
6224 | EBB. | |
6225 | ||
6226 | We should avoid excessive splitting which results in worse code | |
6227 | because of inaccurate cost calculations for spilling new split | |
6228 | pseudos in such case. To achieve this we do splitting only if | |
6229 | register pressure is high in given basic block and there are reload | |
6230 | pseudos requiring hard registers. We could do more register | |
6231 | pressure calculations at any given program point to avoid necessary | |
6232 | splitting even more but it is to expensive and the current approach | |
6233 | works well enough. */ | |
6234 | static bool | |
7f836b57 | 6235 | inherit_in_ebb (rtx_insn *head, rtx_insn *tail) |
c6a6cdaa | 6236 | { |
6237 | int i, src_regno, dst_regno, nregs; | |
422470c1 | 6238 | bool change_p, succ_p, update_reloads_num_p; |
7f836b57 | 6239 | rtx_insn *prev_insn, *last_insn; |
ab4ea053 | 6240 | rtx next_usage_insns, curr_set; |
c6a6cdaa | 6241 | enum reg_class cl; |
6242 | struct lra_insn_reg *reg; | |
6243 | basic_block last_processed_bb, curr_bb = NULL; | |
6244 | HARD_REG_SET potential_reload_hard_regs, live_hard_regs; | |
6245 | bitmap to_process; | |
6246 | unsigned int j; | |
6247 | bitmap_iterator bi; | |
6248 | bool head_p, after_p; | |
6249 | ||
6250 | change_p = false; | |
6251 | curr_usage_insns_check++; | |
ab4ea053 | 6252 | clear_invariants (); |
c6a6cdaa | 6253 | reloads_num = calls_num = 0; |
2f9fa72f | 6254 | for (unsigned int i = 0; i < NUM_ABI_IDS; ++i) |
6255 | last_call_for_abi[i] = 0; | |
6256 | CLEAR_HARD_REG_SET (full_and_partial_call_clobbers); | |
c6a6cdaa | 6257 | bitmap_clear (&check_only_regs); |
ab4ea053 | 6258 | bitmap_clear (&invalid_invariant_regs); |
c6a6cdaa | 6259 | last_processed_bb = NULL; |
6260 | CLEAR_HARD_REG_SET (potential_reload_hard_regs); | |
247f191e | 6261 | live_hard_regs = eliminable_regset | lra_no_alloc_regs; |
c6a6cdaa | 6262 | /* We don't process new insns generated in the loop. */ |
6263 | for (curr_insn = tail; curr_insn != PREV_INSN (head); curr_insn = prev_insn) | |
6264 | { | |
6265 | prev_insn = PREV_INSN (curr_insn); | |
6266 | if (BLOCK_FOR_INSN (curr_insn) != NULL) | |
6267 | curr_bb = BLOCK_FOR_INSN (curr_insn); | |
6268 | if (last_processed_bb != curr_bb) | |
6269 | { | |
6270 | /* We are at the end of BB. Add qualified living | |
6271 | pseudos for potential splitting. */ | |
6272 | to_process = df_get_live_out (curr_bb); | |
6273 | if (last_processed_bb != NULL) | |
1a8f8886 | 6274 | { |
c6a6cdaa | 6275 | /* We are somewhere in the middle of EBB. */ |
6276 | get_live_on_other_edges (curr_bb, last_processed_bb, | |
6277 | &temp_bitmap); | |
6278 | to_process = &temp_bitmap; | |
6279 | } | |
6280 | last_processed_bb = curr_bb; | |
6281 | last_insn = get_last_insertion_point (curr_bb); | |
6282 | after_p = (! JUMP_P (last_insn) | |
6283 | && (! CALL_P (last_insn) | |
6284 | || (find_reg_note (last_insn, | |
6285 | REG_NORETURN, NULL_RTX) == NULL_RTX | |
6286 | && ! SIBLING_CALL_P (last_insn)))); | |
c6a6cdaa | 6287 | CLEAR_HARD_REG_SET (potential_reload_hard_regs); |
6288 | EXECUTE_IF_SET_IN_BITMAP (to_process, 0, j, bi) | |
6289 | { | |
6290 | if ((int) j >= lra_constraint_new_regno_start) | |
6291 | break; | |
6292 | if (j < FIRST_PSEUDO_REGISTER || reg_renumber[j] >= 0) | |
6293 | { | |
6294 | if (j < FIRST_PSEUDO_REGISTER) | |
6295 | SET_HARD_REG_BIT (live_hard_regs, j); | |
6296 | else | |
6297 | add_to_hard_reg_set (&live_hard_regs, | |
6298 | PSEUDO_REGNO_MODE (j), | |
6299 | reg_renumber[j]); | |
6300 | setup_next_usage_insn (j, last_insn, reloads_num, after_p); | |
6301 | } | |
6302 | } | |
6303 | } | |
6304 | src_regno = dst_regno = -1; | |
ab4ea053 | 6305 | curr_set = single_set (curr_insn); |
6306 | if (curr_set != NULL_RTX && REG_P (SET_DEST (curr_set))) | |
6307 | dst_regno = REGNO (SET_DEST (curr_set)); | |
6308 | if (curr_set != NULL_RTX && REG_P (SET_SRC (curr_set))) | |
6309 | src_regno = REGNO (SET_SRC (curr_set)); | |
422470c1 | 6310 | update_reloads_num_p = true; |
c6a6cdaa | 6311 | if (src_regno < lra_constraint_new_regno_start |
6312 | && src_regno >= FIRST_PSEUDO_REGISTER | |
6313 | && reg_renumber[src_regno] < 0 | |
6314 | && dst_regno >= lra_constraint_new_regno_start | |
6315 | && (cl = lra_get_allocno_class (dst_regno)) != NO_REGS) | |
6316 | { | |
6317 | /* 'reload_pseudo <- original_pseudo'. */ | |
7eec3701 | 6318 | if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num) |
6319 | reloads_num++; | |
422470c1 | 6320 | update_reloads_num_p = false; |
c6a6cdaa | 6321 | succ_p = false; |
6322 | if (usage_insns[src_regno].check == curr_usage_insns_check | |
6323 | && (next_usage_insns = usage_insns[src_regno].insns) != NULL_RTX) | |
6324 | succ_p = inherit_reload_reg (false, src_regno, cl, | |
6325 | curr_insn, next_usage_insns); | |
6326 | if (succ_p) | |
6327 | change_p = true; | |
6328 | else | |
6329 | setup_next_usage_insn (src_regno, curr_insn, reloads_num, false); | |
6330 | if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs)) | |
247f191e | 6331 | potential_reload_hard_regs |= reg_class_contents[cl]; |
c6a6cdaa | 6332 | } |
ab4ea053 | 6333 | else if (src_regno < 0 |
6334 | && dst_regno >= lra_constraint_new_regno_start | |
6335 | && invariant_p (SET_SRC (curr_set)) | |
6336 | && (cl = lra_get_allocno_class (dst_regno)) != NO_REGS | |
6526e1b6 | 6337 | && ! bitmap_bit_p (&invalid_invariant_regs, dst_regno) |
6338 | && ! bitmap_bit_p (&invalid_invariant_regs, | |
6339 | ORIGINAL_REGNO(regno_reg_rtx[dst_regno]))) | |
ab4ea053 | 6340 | { |
6341 | /* 'reload_pseudo <- invariant'. */ | |
6342 | if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num) | |
6343 | reloads_num++; | |
6344 | update_reloads_num_p = false; | |
6345 | if (process_invariant_for_inheritance (SET_DEST (curr_set), SET_SRC (curr_set))) | |
6346 | change_p = true; | |
6347 | if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs)) | |
247f191e | 6348 | potential_reload_hard_regs |= reg_class_contents[cl]; |
ab4ea053 | 6349 | } |
c6a6cdaa | 6350 | else if (src_regno >= lra_constraint_new_regno_start |
6351 | && dst_regno < lra_constraint_new_regno_start | |
6352 | && dst_regno >= FIRST_PSEUDO_REGISTER | |
6353 | && reg_renumber[dst_regno] < 0 | |
6354 | && (cl = lra_get_allocno_class (src_regno)) != NO_REGS | |
6355 | && usage_insns[dst_regno].check == curr_usage_insns_check | |
6356 | && (next_usage_insns | |
6357 | = usage_insns[dst_regno].insns) != NULL_RTX) | |
6358 | { | |
7eec3701 | 6359 | if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num) |
6360 | reloads_num++; | |
422470c1 | 6361 | update_reloads_num_p = false; |
c6a6cdaa | 6362 | /* 'original_pseudo <- reload_pseudo'. */ |
6363 | if (! JUMP_P (curr_insn) | |
6364 | && inherit_reload_reg (true, dst_regno, cl, | |
6365 | curr_insn, next_usage_insns)) | |
6366 | change_p = true; | |
6367 | /* Invalidate. */ | |
6368 | usage_insns[dst_regno].check = 0; | |
6369 | if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs)) | |
247f191e | 6370 | potential_reload_hard_regs |= reg_class_contents[cl]; |
c6a6cdaa | 6371 | } |
6372 | else if (INSN_P (curr_insn)) | |
6373 | { | |
bf63c98f | 6374 | int iter; |
c6a6cdaa | 6375 | int max_uid = get_max_uid (); |
6376 | ||
6377 | curr_id = lra_get_insn_recog_data (curr_insn); | |
bf63c98f | 6378 | curr_static_id = curr_id->insn_static_data; |
c6a6cdaa | 6379 | to_inherit_num = 0; |
6380 | /* Process insn definitions. */ | |
bf63c98f | 6381 | for (iter = 0; iter < 2; iter++) |
6382 | for (reg = iter == 0 ? curr_id->regs : curr_static_id->hard_regs; | |
6383 | reg != NULL; | |
6384 | reg = reg->next) | |
6385 | if (reg->type != OP_IN | |
6386 | && (dst_regno = reg->regno) < lra_constraint_new_regno_start) | |
6387 | { | |
6388 | if (dst_regno >= FIRST_PSEUDO_REGISTER && reg->type == OP_OUT | |
6389 | && reg_renumber[dst_regno] < 0 && ! reg->subreg_p | |
6390 | && usage_insns[dst_regno].check == curr_usage_insns_check | |
6391 | && (next_usage_insns | |
6392 | = usage_insns[dst_regno].insns) != NULL_RTX) | |
6393 | { | |
6394 | struct lra_insn_reg *r; | |
6395 | ||
6396 | for (r = curr_id->regs; r != NULL; r = r->next) | |
6397 | if (r->type != OP_OUT && r->regno == dst_regno) | |
6398 | break; | |
6399 | /* Don't do inheritance if the pseudo is also | |
6400 | used in the insn. */ | |
6401 | if (r == NULL) | |
f4d3c071 | 6402 | /* We cannot do inheritance right now |
bf63c98f | 6403 | because the current insn reg info (chain |
6404 | regs) can change after that. */ | |
6405 | add_to_inherit (dst_regno, next_usage_insns); | |
6406 | } | |
f4d3c071 | 6407 | /* We cannot process one reg twice here because of |
bf63c98f | 6408 | usage_insns invalidation. */ |
6409 | if ((dst_regno < FIRST_PSEUDO_REGISTER | |
6410 | || reg_renumber[dst_regno] >= 0) | |
0157439c | 6411 | && ! reg->subreg_p && reg->type != OP_IN) |
bf63c98f | 6412 | { |
6413 | HARD_REG_SET s; | |
6414 | ||
6415 | if (split_if_necessary (dst_regno, reg->biggest_mode, | |
6416 | potential_reload_hard_regs, | |
6417 | false, curr_insn, max_uid)) | |
6418 | change_p = true; | |
6419 | CLEAR_HARD_REG_SET (s); | |
6420 | if (dst_regno < FIRST_PSEUDO_REGISTER) | |
6421 | add_to_hard_reg_set (&s, reg->biggest_mode, dst_regno); | |
6422 | else | |
6423 | add_to_hard_reg_set (&s, PSEUDO_REGNO_MODE (dst_regno), | |
6424 | reg_renumber[dst_regno]); | |
9cfad810 | 6425 | live_hard_regs &= ~s; |
6426 | potential_reload_hard_regs &= ~s; | |
bf63c98f | 6427 | } |
6428 | /* We should invalidate potential inheritance or | |
6429 | splitting for the current insn usages to the next | |
6430 | usage insns (see code below) as the output pseudo | |
6431 | prevents this. */ | |
6432 | if ((dst_regno >= FIRST_PSEUDO_REGISTER | |
6433 | && reg_renumber[dst_regno] < 0) | |
6434 | || (reg->type == OP_OUT && ! reg->subreg_p | |
6435 | && (dst_regno < FIRST_PSEUDO_REGISTER | |
6436 | || reg_renumber[dst_regno] >= 0))) | |
6437 | { | |
6438 | /* Invalidate and mark definitions. */ | |
6439 | if (dst_regno >= FIRST_PSEUDO_REGISTER) | |
6440 | usage_insns[dst_regno].check = -(int) INSN_UID (curr_insn); | |
6441 | else | |
6442 | { | |
92d2aec3 | 6443 | nregs = hard_regno_nregs (dst_regno, |
6444 | reg->biggest_mode); | |
bf63c98f | 6445 | for (i = 0; i < nregs; i++) |
6446 | usage_insns[dst_regno + i].check | |
6447 | = -(int) INSN_UID (curr_insn); | |
6448 | } | |
6449 | } | |
6450 | } | |
853a01d6 | 6451 | /* Process clobbered call regs. */ |
6452 | if (curr_id->arg_hard_regs != NULL) | |
6453 | for (i = 0; (dst_regno = curr_id->arg_hard_regs[i]) >= 0; i++) | |
6454 | if (dst_regno >= FIRST_PSEUDO_REGISTER) | |
6455 | usage_insns[dst_regno - FIRST_PSEUDO_REGISTER].check | |
6456 | = -(int) INSN_UID (curr_insn); | |
c6a6cdaa | 6457 | if (! JUMP_P (curr_insn)) |
6458 | for (i = 0; i < to_inherit_num; i++) | |
6459 | if (inherit_reload_reg (true, to_inherit[i].regno, | |
6460 | ALL_REGS, curr_insn, | |
6461 | to_inherit[i].insns)) | |
6462 | change_p = true; | |
6463 | if (CALL_P (curr_insn)) | |
6464 | { | |
7f836b57 | 6465 | rtx cheap, pat, dest; |
6466 | rtx_insn *restore; | |
c6a6cdaa | 6467 | int regno, hard_regno; |
6468 | ||
6469 | calls_num++; | |
2f9fa72f | 6470 | function_abi callee_abi = insn_callee_abi (curr_insn); |
6471 | last_call_for_abi[callee_abi.id ()] = calls_num; | |
6472 | full_and_partial_call_clobbers | |
6473 | |= callee_abi.full_and_partial_reg_clobbers (); | |
c6a6cdaa | 6474 | if ((cheap = find_reg_note (curr_insn, |
6475 | REG_RETURNED, NULL_RTX)) != NULL_RTX | |
6476 | && ((cheap = XEXP (cheap, 0)), true) | |
6477 | && (regno = REGNO (cheap)) >= FIRST_PSEUDO_REGISTER | |
6478 | && (hard_regno = reg_renumber[regno]) >= 0 | |
2fa8212b | 6479 | && usage_insns[regno].check == curr_usage_insns_check |
c6a6cdaa | 6480 | /* If there are pending saves/restores, the |
6481 | optimization is not worth. */ | |
6482 | && usage_insns[regno].calls_num == calls_num - 1 | |
2f9fa72f | 6483 | && callee_abi.clobbers_reg_p (GET_MODE (cheap), hard_regno)) |
c6a6cdaa | 6484 | { |
6485 | /* Restore the pseudo from the call result as | |
6486 | REG_RETURNED note says that the pseudo value is | |
6487 | in the call result and the pseudo is an argument | |
6488 | of the call. */ | |
6489 | pat = PATTERN (curr_insn); | |
6490 | if (GET_CODE (pat) == PARALLEL) | |
6491 | pat = XVECEXP (pat, 0, 0); | |
6492 | dest = SET_DEST (pat); | |
e88cf7af | 6493 | /* For multiple return values dest is PARALLEL. |
6494 | Currently we handle only single return value case. */ | |
6495 | if (REG_P (dest)) | |
6496 | { | |
6497 | start_sequence (); | |
6498 | emit_move_insn (cheap, copy_rtx (dest)); | |
6499 | restore = get_insns (); | |
6500 | end_sequence (); | |
6501 | lra_process_new_insns (curr_insn, NULL, restore, | |
6502 | "Inserting call parameter restore"); | |
6503 | /* We don't need to save/restore of the pseudo from | |
6504 | this call. */ | |
6505 | usage_insns[regno].calls_num = calls_num; | |
2f9fa72f | 6506 | remove_from_hard_reg_set |
6507 | (&full_and_partial_call_clobbers, | |
6508 | GET_MODE (cheap), hard_regno); | |
e88cf7af | 6509 | bitmap_set_bit (&check_only_regs, regno); |
6510 | } | |
c6a6cdaa | 6511 | } |
6512 | } | |
6513 | to_inherit_num = 0; | |
6514 | /* Process insn usages. */ | |
bf63c98f | 6515 | for (iter = 0; iter < 2; iter++) |
6516 | for (reg = iter == 0 ? curr_id->regs : curr_static_id->hard_regs; | |
6517 | reg != NULL; | |
6518 | reg = reg->next) | |
6519 | if ((reg->type != OP_OUT | |
6520 | || (reg->type == OP_OUT && reg->subreg_p)) | |
6521 | && (src_regno = reg->regno) < lra_constraint_new_regno_start) | |
6522 | { | |
6523 | if (src_regno >= FIRST_PSEUDO_REGISTER | |
6524 | && reg_renumber[src_regno] < 0 && reg->type == OP_IN) | |
6525 | { | |
6526 | if (usage_insns[src_regno].check == curr_usage_insns_check | |
6527 | && (next_usage_insns | |
6528 | = usage_insns[src_regno].insns) != NULL_RTX | |
6529 | && NONDEBUG_INSN_P (curr_insn)) | |
6530 | add_to_inherit (src_regno, next_usage_insns); | |
6531 | else if (usage_insns[src_regno].check | |
6532 | != -(int) INSN_UID (curr_insn)) | |
6533 | /* Add usages but only if the reg is not set up | |
6534 | in the same insn. */ | |
6535 | add_next_usage_insn (src_regno, curr_insn, reloads_num); | |
6536 | } | |
6537 | else if (src_regno < FIRST_PSEUDO_REGISTER | |
6538 | || reg_renumber[src_regno] >= 0) | |
6539 | { | |
6540 | bool before_p; | |
9ed997be | 6541 | rtx_insn *use_insn = curr_insn; |
bf63c98f | 6542 | |
6543 | before_p = (JUMP_P (curr_insn) | |
6544 | || (CALL_P (curr_insn) && reg->type == OP_IN)); | |
6545 | if (NONDEBUG_INSN_P (curr_insn) | |
7eec3701 | 6546 | && (! JUMP_P (curr_insn) || reg->type == OP_IN) |
bf63c98f | 6547 | && split_if_necessary (src_regno, reg->biggest_mode, |
6548 | potential_reload_hard_regs, | |
6549 | before_p, curr_insn, max_uid)) | |
6550 | { | |
6551 | if (reg->subreg_p) | |
6552 | lra_risky_transformations_p = true; | |
6553 | change_p = true; | |
7eec3701 | 6554 | /* Invalidate. */ |
bf63c98f | 6555 | usage_insns[src_regno].check = 0; |
6556 | if (before_p) | |
6557 | use_insn = PREV_INSN (curr_insn); | |
6558 | } | |
6559 | if (NONDEBUG_INSN_P (curr_insn)) | |
6560 | { | |
6561 | if (src_regno < FIRST_PSEUDO_REGISTER) | |
6562 | add_to_hard_reg_set (&live_hard_regs, | |
6563 | reg->biggest_mode, src_regno); | |
6564 | else | |
6565 | add_to_hard_reg_set (&live_hard_regs, | |
6566 | PSEUDO_REGNO_MODE (src_regno), | |
6567 | reg_renumber[src_regno]); | |
6568 | } | |
fbaab486 | 6569 | if (src_regno >= FIRST_PSEUDO_REGISTER) |
6570 | add_next_usage_insn (src_regno, use_insn, reloads_num); | |
6571 | else | |
6572 | { | |
6573 | for (i = 0; i < hard_regno_nregs (src_regno, reg->biggest_mode); i++) | |
6574 | add_next_usage_insn (src_regno + i, use_insn, reloads_num); | |
6575 | } | |
bf63c98f | 6576 | } |
6577 | } | |
853a01d6 | 6578 | /* Process used call regs. */ |
422470c1 | 6579 | if (curr_id->arg_hard_regs != NULL) |
6580 | for (i = 0; (src_regno = curr_id->arg_hard_regs[i]) >= 0; i++) | |
6581 | if (src_regno < FIRST_PSEUDO_REGISTER) | |
6582 | { | |
6583 | SET_HARD_REG_BIT (live_hard_regs, src_regno); | |
6584 | add_next_usage_insn (src_regno, curr_insn, reloads_num); | |
6585 | } | |
c6a6cdaa | 6586 | for (i = 0; i < to_inherit_num; i++) |
6587 | { | |
6588 | src_regno = to_inherit[i].regno; | |
6589 | if (inherit_reload_reg (false, src_regno, ALL_REGS, | |
6590 | curr_insn, to_inherit[i].insns)) | |
6591 | change_p = true; | |
6592 | else | |
6593 | setup_next_usage_insn (src_regno, curr_insn, reloads_num, false); | |
6594 | } | |
6595 | } | |
422470c1 | 6596 | if (update_reloads_num_p |
ab4ea053 | 6597 | && NONDEBUG_INSN_P (curr_insn) && curr_set != NULL_RTX) |
422470c1 | 6598 | { |
6599 | int regno = -1; | |
ab4ea053 | 6600 | if ((REG_P (SET_DEST (curr_set)) |
6601 | && (regno = REGNO (SET_DEST (curr_set))) >= lra_constraint_new_regno_start | |
422470c1 | 6602 | && reg_renumber[regno] < 0 |
6603 | && (cl = lra_get_allocno_class (regno)) != NO_REGS) | |
ab4ea053 | 6604 | || (REG_P (SET_SRC (curr_set)) |
6605 | && (regno = REGNO (SET_SRC (curr_set))) >= lra_constraint_new_regno_start | |
422470c1 | 6606 | && reg_renumber[regno] < 0 |
6607 | && (cl = lra_get_allocno_class (regno)) != NO_REGS)) | |
6608 | { | |
7eec3701 | 6609 | if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num) |
6610 | reloads_num++; | |
422470c1 | 6611 | if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs)) |
247f191e | 6612 | potential_reload_hard_regs |= reg_class_contents[cl]; |
422470c1 | 6613 | } |
6614 | } | |
ab4ea053 | 6615 | if (NONDEBUG_INSN_P (curr_insn)) |
6616 | { | |
6617 | int regno; | |
6618 | ||
6619 | /* Invalidate invariants with changed regs. */ | |
6620 | curr_id = lra_get_insn_recog_data (curr_insn); | |
6621 | for (reg = curr_id->regs; reg != NULL; reg = reg->next) | |
6622 | if (reg->type != OP_IN) | |
6526e1b6 | 6623 | { |
6624 | bitmap_set_bit (&invalid_invariant_regs, reg->regno); | |
6625 | bitmap_set_bit (&invalid_invariant_regs, | |
6626 | ORIGINAL_REGNO (regno_reg_rtx[reg->regno])); | |
6627 | } | |
ab4ea053 | 6628 | curr_static_id = curr_id->insn_static_data; |
6629 | for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next) | |
6630 | if (reg->type != OP_IN) | |
6631 | bitmap_set_bit (&invalid_invariant_regs, reg->regno); | |
6632 | if (curr_id->arg_hard_regs != NULL) | |
6633 | for (i = 0; (regno = curr_id->arg_hard_regs[i]) >= 0; i++) | |
6526e1b6 | 6634 | if (regno >= FIRST_PSEUDO_REGISTER) |
ab4ea053 | 6635 | bitmap_set_bit (&invalid_invariant_regs, |
6526e1b6 | 6636 | regno - FIRST_PSEUDO_REGISTER); |
ab4ea053 | 6637 | } |
c6a6cdaa | 6638 | /* We reached the start of the current basic block. */ |
6639 | if (prev_insn == NULL_RTX || prev_insn == PREV_INSN (head) | |
6640 | || BLOCK_FOR_INSN (prev_insn) != curr_bb) | |
6641 | { | |
6642 | /* We reached the beginning of the current block -- do | |
6643 | rest of spliting in the current BB. */ | |
6644 | to_process = df_get_live_in (curr_bb); | |
6645 | if (BLOCK_FOR_INSN (head) != curr_bb) | |
1a8f8886 | 6646 | { |
c6a6cdaa | 6647 | /* We are somewhere in the middle of EBB. */ |
6648 | get_live_on_other_edges (EDGE_PRED (curr_bb, 0)->src, | |
6649 | curr_bb, &temp_bitmap); | |
6650 | to_process = &temp_bitmap; | |
6651 | } | |
6652 | head_p = true; | |
6653 | EXECUTE_IF_SET_IN_BITMAP (to_process, 0, j, bi) | |
6654 | { | |
6655 | if ((int) j >= lra_constraint_new_regno_start) | |
6656 | break; | |
6657 | if (((int) j < FIRST_PSEUDO_REGISTER || reg_renumber[j] >= 0) | |
6658 | && usage_insns[j].check == curr_usage_insns_check | |
6659 | && (next_usage_insns = usage_insns[j].insns) != NULL_RTX) | |
6660 | { | |
6661 | if (need_for_split_p (potential_reload_hard_regs, j)) | |
6662 | { | |
6663 | if (lra_dump_file != NULL && head_p) | |
6664 | { | |
6665 | fprintf (lra_dump_file, | |
6666 | " ----------------------------------\n"); | |
6667 | head_p = false; | |
6668 | } | |
6669 | if (split_reg (false, j, bb_note (curr_bb), | |
6a4bc24e | 6670 | next_usage_insns, NULL)) |
c6a6cdaa | 6671 | change_p = true; |
6672 | } | |
6673 | usage_insns[j].check = 0; | |
6674 | } | |
6675 | } | |
6676 | } | |
6677 | } | |
6678 | return change_p; | |
6679 | } | |
6680 | ||
6681 | /* This value affects EBB forming. If probability of edge from EBB to | |
6682 | a BB is not greater than the following value, we don't add the BB | |
1a8f8886 | 6683 | to EBB. */ |
4b69081d | 6684 | #define EBB_PROBABILITY_CUTOFF \ |
6685 | ((REG_BR_PROB_BASE * LRA_INHERITANCE_EBB_PROBABILITY_CUTOFF) / 100) | |
c6a6cdaa | 6686 | |
6687 | /* Current number of inheritance/split iteration. */ | |
6688 | int lra_inheritance_iter; | |
6689 | ||
6690 | /* Entry function for inheritance/split pass. */ | |
6691 | void | |
6692 | lra_inheritance (void) | |
6693 | { | |
6694 | int i; | |
6695 | basic_block bb, start_bb; | |
6696 | edge e; | |
6697 | ||
c6a6cdaa | 6698 | lra_inheritance_iter++; |
47f6add2 | 6699 | if (lra_inheritance_iter > LRA_MAX_INHERITANCE_PASSES) |
7b184c47 | 6700 | return; |
6701 | timevar_push (TV_LRA_INHERITANCE); | |
c6a6cdaa | 6702 | if (lra_dump_file != NULL) |
6703 | fprintf (lra_dump_file, "\n********** Inheritance #%d: **********\n\n", | |
6704 | lra_inheritance_iter); | |
6705 | curr_usage_insns_check = 0; | |
6706 | usage_insns = XNEWVEC (struct usage_insns, lra_constraint_new_regno_start); | |
6707 | for (i = 0; i < lra_constraint_new_regno_start; i++) | |
6708 | usage_insns[i].check = 0; | |
6709 | bitmap_initialize (&check_only_regs, ®_obstack); | |
ab4ea053 | 6710 | bitmap_initialize (&invalid_invariant_regs, ®_obstack); |
c6a6cdaa | 6711 | bitmap_initialize (&live_regs, ®_obstack); |
6712 | bitmap_initialize (&temp_bitmap, ®_obstack); | |
6713 | bitmap_initialize (&ebb_global_regs, ®_obstack); | |
fc00614f | 6714 | FOR_EACH_BB_FN (bb, cfun) |
c6a6cdaa | 6715 | { |
6716 | start_bb = bb; | |
6717 | if (lra_dump_file != NULL) | |
6718 | fprintf (lra_dump_file, "EBB"); | |
6719 | /* Form a EBB starting with BB. */ | |
6720 | bitmap_clear (&ebb_global_regs); | |
6721 | bitmap_ior_into (&ebb_global_regs, df_get_live_in (bb)); | |
6722 | for (;;) | |
6723 | { | |
6724 | if (lra_dump_file != NULL) | |
6725 | fprintf (lra_dump_file, " %d", bb->index); | |
34154e27 | 6726 | if (bb->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun) |
6727 | || LABEL_P (BB_HEAD (bb->next_bb))) | |
c6a6cdaa | 6728 | break; |
6729 | e = find_fallthru_edge (bb->succs); | |
6730 | if (! e) | |
6731 | break; | |
720cfc43 | 6732 | if (e->probability.initialized_p () |
6733 | && e->probability.to_reg_br_prob_base () < EBB_PROBABILITY_CUTOFF) | |
c6a6cdaa | 6734 | break; |
6735 | bb = bb->next_bb; | |
6736 | } | |
6737 | bitmap_ior_into (&ebb_global_regs, df_get_live_out (bb)); | |
6738 | if (lra_dump_file != NULL) | |
6739 | fprintf (lra_dump_file, "\n"); | |
6740 | if (inherit_in_ebb (BB_HEAD (start_bb), BB_END (bb))) | |
6741 | /* Remember that the EBB head and tail can change in | |
6742 | inherit_in_ebb. */ | |
6743 | update_ebb_live_info (BB_HEAD (start_bb), BB_END (bb)); | |
6744 | } | |
7da7f1c6 | 6745 | bitmap_release (&ebb_global_regs); |
6746 | bitmap_release (&temp_bitmap); | |
6747 | bitmap_release (&live_regs); | |
6748 | bitmap_release (&invalid_invariant_regs); | |
6749 | bitmap_release (&check_only_regs); | |
c6a6cdaa | 6750 | free (usage_insns); |
6751 | ||
6752 | timevar_pop (TV_LRA_INHERITANCE); | |
6753 | } | |
6754 | ||
6755 | \f | |
6756 | ||
6757 | /* This page contains code to undo failed inheritance/split | |
6758 | transformations. */ | |
6759 | ||
6760 | /* Current number of iteration undoing inheritance/split. */ | |
6761 | int lra_undo_inheritance_iter; | |
6762 | ||
6763 | /* Fix BB live info LIVE after removing pseudos created on pass doing | |
6764 | inheritance/split which are REMOVED_PSEUDOS. */ | |
6765 | static void | |
6766 | fix_bb_live_info (bitmap live, bitmap removed_pseudos) | |
6767 | { | |
6768 | unsigned int regno; | |
6769 | bitmap_iterator bi; | |
6770 | ||
6771 | EXECUTE_IF_SET_IN_BITMAP (removed_pseudos, 0, regno, bi) | |
ab4ea053 | 6772 | if (bitmap_clear_bit (live, regno) |
6773 | && REG_P (lra_reg_info[regno].restore_rtx)) | |
6774 | bitmap_set_bit (live, REGNO (lra_reg_info[regno].restore_rtx)); | |
c6a6cdaa | 6775 | } |
6776 | ||
6777 | /* Return regno of the (subreg of) REG. Otherwise, return a negative | |
6778 | number. */ | |
6779 | static int | |
6780 | get_regno (rtx reg) | |
6781 | { | |
6782 | if (GET_CODE (reg) == SUBREG) | |
6783 | reg = SUBREG_REG (reg); | |
6784 | if (REG_P (reg)) | |
6785 | return REGNO (reg); | |
6786 | return -1; | |
6787 | } | |
6788 | ||
02ffd664 | 6789 | /* Delete a move INSN with destination reg DREGNO and a previous |
6790 | clobber insn with the same regno. The inheritance/split code can | |
6791 | generate moves with preceding clobber and when we delete such moves | |
6792 | we should delete the clobber insn too to keep the correct life | |
6793 | info. */ | |
6794 | static void | |
6795 | delete_move_and_clobber (rtx_insn *insn, int dregno) | |
6796 | { | |
6797 | rtx_insn *prev_insn = PREV_INSN (insn); | |
6798 | ||
6799 | lra_set_insn_deleted (insn); | |
2b3c633f | 6800 | lra_assert (dregno >= 0); |
02ffd664 | 6801 | if (prev_insn != NULL && NONDEBUG_INSN_P (prev_insn) |
6802 | && GET_CODE (PATTERN (prev_insn)) == CLOBBER | |
6803 | && dregno == get_regno (XEXP (PATTERN (prev_insn), 0))) | |
6804 | lra_set_insn_deleted (prev_insn); | |
6805 | } | |
6806 | ||
c6a6cdaa | 6807 | /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and |
6808 | return true if we did any change. The undo transformations for | |
6809 | inheritance looks like | |
6810 | i <- i2 | |
6811 | p <- i => p <- i2 | |
6812 | or removing | |
6813 | p <- i, i <- p, and i <- i3 | |
6814 | where p is original pseudo from which inheritance pseudo i was | |
6815 | created, i and i3 are removed inheritance pseudos, i2 is another | |
6816 | not removed inheritance pseudo. All split pseudos or other | |
6817 | occurrences of removed inheritance pseudos are changed on the | |
6818 | corresponding original pseudos. | |
6819 | ||
6820 | The function also schedules insns changed and created during | |
6821 | inheritance/split pass for processing by the subsequent constraint | |
6822 | pass. */ | |
6823 | static bool | |
6824 | remove_inheritance_pseudos (bitmap remove_pseudos) | |
6825 | { | |
6826 | basic_block bb; | |
ab4ea053 | 6827 | int regno, sregno, prev_sregno, dregno; |
6828 | rtx restore_rtx; | |
7f836b57 | 6829 | rtx set, prev_set; |
6830 | rtx_insn *prev_insn; | |
c6a6cdaa | 6831 | bool change_p, done_p; |
6832 | ||
6833 | change_p = ! bitmap_empty_p (remove_pseudos); | |
f4d3c071 | 6834 | /* We cannot finish the function right away if CHANGE_P is true |
c6a6cdaa | 6835 | because we need to marks insns affected by previous |
6836 | inheritance/split pass for processing by the subsequent | |
6837 | constraint pass. */ | |
fc00614f | 6838 | FOR_EACH_BB_FN (bb, cfun) |
c6a6cdaa | 6839 | { |
6840 | fix_bb_live_info (df_get_live_in (bb), remove_pseudos); | |
6841 | fix_bb_live_info (df_get_live_out (bb), remove_pseudos); | |
6842 | FOR_BB_INSNS_REVERSE (bb, curr_insn) | |
6843 | { | |
6844 | if (! INSN_P (curr_insn)) | |
6845 | continue; | |
6846 | done_p = false; | |
6847 | sregno = dregno = -1; | |
6848 | if (change_p && NONDEBUG_INSN_P (curr_insn) | |
6849 | && (set = single_set (curr_insn)) != NULL_RTX) | |
6850 | { | |
6851 | dregno = get_regno (SET_DEST (set)); | |
6852 | sregno = get_regno (SET_SRC (set)); | |
6853 | } | |
1a8f8886 | 6854 | |
c6a6cdaa | 6855 | if (sregno >= 0 && dregno >= 0) |
6856 | { | |
ab4ea053 | 6857 | if (bitmap_bit_p (remove_pseudos, dregno) |
6858 | && ! REG_P (lra_reg_info[dregno].restore_rtx)) | |
6859 | { | |
6860 | /* invariant inheritance pseudo <- original pseudo */ | |
6861 | if (lra_dump_file != NULL) | |
6862 | { | |
6863 | fprintf (lra_dump_file, " Removing invariant inheritance:\n"); | |
6864 | dump_insn_slim (lra_dump_file, curr_insn); | |
6865 | fprintf (lra_dump_file, "\n"); | |
6866 | } | |
6867 | delete_move_and_clobber (curr_insn, dregno); | |
6868 | done_p = true; | |
6869 | } | |
6870 | else if (bitmap_bit_p (remove_pseudos, sregno) | |
6871 | && ! REG_P (lra_reg_info[sregno].restore_rtx)) | |
6872 | { | |
6873 | /* reload pseudo <- invariant inheritance pseudo */ | |
6874 | start_sequence (); | |
f4d3c071 | 6875 | /* We cannot just change the source. It might be |
ab4ea053 | 6876 | an insn different from the move. */ |
fee93b91 | 6877 | emit_insn (lra_reg_info[sregno].restore_rtx); |
ab4ea053 | 6878 | rtx_insn *new_insns = get_insns (); |
6879 | end_sequence (); | |
fee93b91 | 6880 | lra_assert (single_set (new_insns) != NULL |
6881 | && SET_DEST (set) == SET_DEST (single_set (new_insns))); | |
ab4ea053 | 6882 | lra_process_new_insns (curr_insn, NULL, new_insns, |
6883 | "Changing reload<-invariant inheritance"); | |
6884 | delete_move_and_clobber (curr_insn, dregno); | |
6885 | done_p = true; | |
6886 | } | |
6887 | else if ((bitmap_bit_p (remove_pseudos, sregno) | |
6888 | && (get_regno (lra_reg_info[sregno].restore_rtx) == dregno | |
6889 | || (bitmap_bit_p (remove_pseudos, dregno) | |
6890 | && get_regno (lra_reg_info[sregno].restore_rtx) >= 0 | |
6891 | && (get_regno (lra_reg_info[sregno].restore_rtx) | |
6892 | == get_regno (lra_reg_info[dregno].restore_rtx))))) | |
c6a6cdaa | 6893 | || (bitmap_bit_p (remove_pseudos, dregno) |
ab4ea053 | 6894 | && get_regno (lra_reg_info[dregno].restore_rtx) == sregno)) |
c6a6cdaa | 6895 | /* One of the following cases: |
6896 | original <- removed inheritance pseudo | |
6897 | removed inherit pseudo <- another removed inherit pseudo | |
6898 | removed inherit pseudo <- original pseudo | |
6899 | Or | |
6900 | removed_split_pseudo <- original_reg | |
6901 | original_reg <- removed_split_pseudo */ | |
6902 | { | |
6903 | if (lra_dump_file != NULL) | |
6904 | { | |
6905 | fprintf (lra_dump_file, " Removing %s:\n", | |
6906 | bitmap_bit_p (&lra_split_regs, sregno) | |
6907 | || bitmap_bit_p (&lra_split_regs, dregno) | |
6908 | ? "split" : "inheritance"); | |
6dde9719 | 6909 | dump_insn_slim (lra_dump_file, curr_insn); |
c6a6cdaa | 6910 | } |
02ffd664 | 6911 | delete_move_and_clobber (curr_insn, dregno); |
c6a6cdaa | 6912 | done_p = true; |
6913 | } | |
6914 | else if (bitmap_bit_p (remove_pseudos, sregno) | |
6915 | && bitmap_bit_p (&lra_inheritance_pseudos, sregno)) | |
6916 | { | |
6917 | /* Search the following pattern: | |
6918 | inherit_or_split_pseudo1 <- inherit_or_split_pseudo2 | |
6919 | original_pseudo <- inherit_or_split_pseudo1 | |
6920 | where the 2nd insn is the current insn and | |
6921 | inherit_or_split_pseudo2 is not removed. If it is found, | |
6922 | change the current insn onto: | |
6923 | original_pseudo <- inherit_or_split_pseudo2. */ | |
6924 | for (prev_insn = PREV_INSN (curr_insn); | |
6925 | prev_insn != NULL_RTX && ! NONDEBUG_INSN_P (prev_insn); | |
6926 | prev_insn = PREV_INSN (prev_insn)) | |
6927 | ; | |
6928 | if (prev_insn != NULL_RTX && BLOCK_FOR_INSN (prev_insn) == bb | |
6929 | && (prev_set = single_set (prev_insn)) != NULL_RTX | |
6930 | /* There should be no subregs in insn we are | |
6931 | searching because only the original reg might | |
6932 | be in subreg when we changed the mode of | |
6933 | load/store for splitting. */ | |
6934 | && REG_P (SET_DEST (prev_set)) | |
6935 | && REG_P (SET_SRC (prev_set)) | |
6936 | && (int) REGNO (SET_DEST (prev_set)) == sregno | |
6937 | && ((prev_sregno = REGNO (SET_SRC (prev_set))) | |
6938 | >= FIRST_PSEUDO_REGISTER) | |
ab4ea053 | 6939 | && (lra_reg_info[prev_sregno].restore_rtx == NULL_RTX |
6940 | || | |
6941 | /* As we consider chain of inheritance or | |
6942 | splitting described in above comment we should | |
6943 | check that sregno and prev_sregno were | |
6944 | inheritance/split pseudos created from the | |
6945 | same original regno. */ | |
6946 | (get_regno (lra_reg_info[sregno].restore_rtx) >= 0 | |
6947 | && (get_regno (lra_reg_info[sregno].restore_rtx) | |
6948 | == get_regno (lra_reg_info[prev_sregno].restore_rtx)))) | |
c6a6cdaa | 6949 | && ! bitmap_bit_p (remove_pseudos, prev_sregno)) |
6950 | { | |
6951 | lra_assert (GET_MODE (SET_SRC (prev_set)) | |
6952 | == GET_MODE (regno_reg_rtx[sregno])); | |
2b69ec1c | 6953 | /* Although we have a single set, the insn can |
6954 | contain more one sregno register occurrence | |
6955 | as a source. Change all occurrences. */ | |
6956 | lra_substitute_pseudo_within_insn (curr_insn, sregno, | |
6957 | SET_SRC (prev_set), | |
6958 | false); | |
ef76edc2 | 6959 | /* As we are finishing with processing the insn |
6960 | here, check the destination too as it might | |
6961 | inheritance pseudo for another pseudo. */ | |
6962 | if (bitmap_bit_p (remove_pseudos, dregno) | |
6963 | && bitmap_bit_p (&lra_inheritance_pseudos, dregno) | |
ab4ea053 | 6964 | && (restore_rtx |
6965 | = lra_reg_info[dregno].restore_rtx) != NULL_RTX) | |
ef76edc2 | 6966 | { |
6967 | if (GET_CODE (SET_DEST (set)) == SUBREG) | |
ab4ea053 | 6968 | SUBREG_REG (SET_DEST (set)) = restore_rtx; |
ef76edc2 | 6969 | else |
ab4ea053 | 6970 | SET_DEST (set) = restore_rtx; |
ef76edc2 | 6971 | } |
c6a6cdaa | 6972 | lra_push_insn_and_update_insn_regno_info (curr_insn); |
6973 | lra_set_used_insn_alternative_by_uid | |
71d47a14 | 6974 | (INSN_UID (curr_insn), LRA_UNKNOWN_ALT); |
c6a6cdaa | 6975 | done_p = true; |
6976 | if (lra_dump_file != NULL) | |
6977 | { | |
6978 | fprintf (lra_dump_file, " Change reload insn:\n"); | |
6dde9719 | 6979 | dump_insn_slim (lra_dump_file, curr_insn); |
c6a6cdaa | 6980 | } |
6981 | } | |
6982 | } | |
6983 | } | |
6984 | if (! done_p) | |
6985 | { | |
6986 | struct lra_insn_reg *reg; | |
6987 | bool restored_regs_p = false; | |
6988 | bool kept_regs_p = false; | |
6989 | ||
6990 | curr_id = lra_get_insn_recog_data (curr_insn); | |
6991 | for (reg = curr_id->regs; reg != NULL; reg = reg->next) | |
6992 | { | |
6993 | regno = reg->regno; | |
ab4ea053 | 6994 | restore_rtx = lra_reg_info[regno].restore_rtx; |
6995 | if (restore_rtx != NULL_RTX) | |
c6a6cdaa | 6996 | { |
6997 | if (change_p && bitmap_bit_p (remove_pseudos, regno)) | |
6998 | { | |
06072e79 | 6999 | lra_substitute_pseudo_within_insn |
ab4ea053 | 7000 | (curr_insn, regno, restore_rtx, false); |
c6a6cdaa | 7001 | restored_regs_p = true; |
7002 | } | |
7003 | else | |
7004 | kept_regs_p = true; | |
7005 | } | |
7006 | } | |
7007 | if (NONDEBUG_INSN_P (curr_insn) && kept_regs_p) | |
7008 | { | |
7009 | /* The instruction has changed since the previous | |
7010 | constraints pass. */ | |
7011 | lra_push_insn_and_update_insn_regno_info (curr_insn); | |
7012 | lra_set_used_insn_alternative_by_uid | |
71d47a14 | 7013 | (INSN_UID (curr_insn), LRA_UNKNOWN_ALT); |
c6a6cdaa | 7014 | } |
7015 | else if (restored_regs_p) | |
7016 | /* The instruction has been restored to the form that | |
7017 | it had during the previous constraints pass. */ | |
7018 | lra_update_insn_regno_info (curr_insn); | |
7019 | if (restored_regs_p && lra_dump_file != NULL) | |
7020 | { | |
7021 | fprintf (lra_dump_file, " Insn after restoring regs:\n"); | |
6dde9719 | 7022 | dump_insn_slim (lra_dump_file, curr_insn); |
c6a6cdaa | 7023 | } |
7024 | } | |
7025 | } | |
7026 | } | |
7027 | return change_p; | |
7028 | } | |
7029 | ||
1f3a048a | 7030 | /* If optional reload pseudos failed to get a hard register or was not |
7031 | inherited, it is better to remove optional reloads. We do this | |
7032 | transformation after undoing inheritance to figure out necessity to | |
7033 | remove optional reloads easier. Return true if we do any | |
7034 | change. */ | |
7035 | static bool | |
7036 | undo_optional_reloads (void) | |
7037 | { | |
267200f3 | 7038 | bool change_p, keep_p; |
1f3a048a | 7039 | unsigned int regno, uid; |
7040 | bitmap_iterator bi, bi2; | |
7f836b57 | 7041 | rtx_insn *insn; |
7042 | rtx set, src, dest; | |
f6708c36 | 7043 | auto_bitmap removed_optional_reload_pseudos (®_obstack); |
1f3a048a | 7044 | |
f6708c36 | 7045 | bitmap_copy (removed_optional_reload_pseudos, &lra_optional_reload_pseudos); |
1f3a048a | 7046 | EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos, 0, regno, bi) |
0c4735d1 | 7047 | { |
7048 | keep_p = false; | |
95563487 | 7049 | /* Keep optional reloads from previous subpasses. */ |
ab4ea053 | 7050 | if (lra_reg_info[regno].restore_rtx == NULL_RTX |
95563487 | 7051 | /* If the original pseudo changed its allocation, just |
7052 | removing the optional pseudo is dangerous as the original | |
7053 | pseudo will have longer live range. */ | |
ab4ea053 | 7054 | || reg_renumber[REGNO (lra_reg_info[regno].restore_rtx)] >= 0) |
0c4735d1 | 7055 | keep_p = true; |
7056 | else if (reg_renumber[regno] >= 0) | |
7057 | EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi2) | |
267200f3 | 7058 | { |
0c4735d1 | 7059 | insn = lra_insn_recog_data[uid]->insn; |
7060 | if ((set = single_set (insn)) == NULL_RTX) | |
7061 | continue; | |
7062 | src = SET_SRC (set); | |
7063 | dest = SET_DEST (set); | |
7064 | if (! REG_P (src) || ! REG_P (dest)) | |
7065 | continue; | |
7066 | if (REGNO (dest) == regno | |
7067 | /* Ignore insn for optional reloads itself. */ | |
ab4ea053 | 7068 | && REGNO (lra_reg_info[regno].restore_rtx) != REGNO (src) |
0c4735d1 | 7069 | /* Check only inheritance on last inheritance pass. */ |
7070 | && (int) REGNO (src) >= new_regno_start | |
7071 | /* Check that the optional reload was inherited. */ | |
7072 | && bitmap_bit_p (&lra_inheritance_pseudos, REGNO (src))) | |
7073 | { | |
7074 | keep_p = true; | |
7075 | break; | |
7076 | } | |
267200f3 | 7077 | } |
0c4735d1 | 7078 | if (keep_p) |
7079 | { | |
f6708c36 | 7080 | bitmap_clear_bit (removed_optional_reload_pseudos, regno); |
0c4735d1 | 7081 | if (lra_dump_file != NULL) |
7082 | fprintf (lra_dump_file, "Keep optional reload reg %d\n", regno); | |
7083 | } | |
7084 | } | |
f6708c36 | 7085 | change_p = ! bitmap_empty_p (removed_optional_reload_pseudos); |
7086 | auto_bitmap insn_bitmap (®_obstack); | |
7087 | EXECUTE_IF_SET_IN_BITMAP (removed_optional_reload_pseudos, 0, regno, bi) | |
1f3a048a | 7088 | { |
7089 | if (lra_dump_file != NULL) | |
7090 | fprintf (lra_dump_file, "Remove optional reload reg %d\n", regno); | |
f6708c36 | 7091 | bitmap_copy (insn_bitmap, &lra_reg_info[regno].insn_bitmap); |
7092 | EXECUTE_IF_SET_IN_BITMAP (insn_bitmap, 0, uid, bi2) | |
1f3a048a | 7093 | { |
7094 | insn = lra_insn_recog_data[uid]->insn; | |
7095 | if ((set = single_set (insn)) != NULL_RTX) | |
7096 | { | |
7097 | src = SET_SRC (set); | |
7098 | dest = SET_DEST (set); | |
7099 | if (REG_P (src) && REG_P (dest) | |
7100 | && ((REGNO (src) == regno | |
ab4ea053 | 7101 | && (REGNO (lra_reg_info[regno].restore_rtx) |
7102 | == REGNO (dest))) | |
1f3a048a | 7103 | || (REGNO (dest) == regno |
ab4ea053 | 7104 | && (REGNO (lra_reg_info[regno].restore_rtx) |
7105 | == REGNO (src))))) | |
1f3a048a | 7106 | { |
7107 | if (lra_dump_file != NULL) | |
7108 | { | |
7109 | fprintf (lra_dump_file, " Deleting move %u\n", | |
7110 | INSN_UID (insn)); | |
7111 | dump_insn_slim (lra_dump_file, insn); | |
7112 | } | |
02ffd664 | 7113 | delete_move_and_clobber (insn, REGNO (dest)); |
1f3a048a | 7114 | continue; |
7115 | } | |
7116 | /* We should not worry about generation memory-memory | |
7117 | moves here as if the corresponding inheritance did | |
7118 | not work (inheritance pseudo did not get a hard reg), | |
7119 | we remove the inheritance pseudo and the optional | |
7120 | reload. */ | |
7121 | } | |
06072e79 | 7122 | lra_substitute_pseudo_within_insn |
ab4ea053 | 7123 | (insn, regno, lra_reg_info[regno].restore_rtx, false); |
1f3a048a | 7124 | lra_update_insn_regno_info (insn); |
7125 | if (lra_dump_file != NULL) | |
7126 | { | |
7127 | fprintf (lra_dump_file, | |
7128 | " Restoring original insn:\n"); | |
7129 | dump_insn_slim (lra_dump_file, insn); | |
7130 | } | |
7131 | } | |
7132 | } | |
7133 | /* Clear restore_regnos. */ | |
7134 | EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos, 0, regno, bi) | |
ab4ea053 | 7135 | lra_reg_info[regno].restore_rtx = NULL_RTX; |
1f3a048a | 7136 | return change_p; |
7137 | } | |
7138 | ||
c6a6cdaa | 7139 | /* Entry function for undoing inheritance/split transformation. Return true |
7140 | if we did any RTL change in this pass. */ | |
7141 | bool | |
7142 | lra_undo_inheritance (void) | |
7143 | { | |
7144 | unsigned int regno; | |
ab4ea053 | 7145 | int hard_regno; |
c6a6cdaa | 7146 | int n_all_inherit, n_inherit, n_all_split, n_split; |
ab4ea053 | 7147 | rtx restore_rtx; |
c6a6cdaa | 7148 | bitmap_iterator bi; |
7149 | bool change_p; | |
7150 | ||
7151 | lra_undo_inheritance_iter++; | |
47f6add2 | 7152 | if (lra_undo_inheritance_iter > LRA_MAX_INHERITANCE_PASSES) |
7b184c47 | 7153 | return false; |
c6a6cdaa | 7154 | if (lra_dump_file != NULL) |
7155 | fprintf (lra_dump_file, | |
7156 | "\n********** Undoing inheritance #%d: **********\n\n", | |
7157 | lra_undo_inheritance_iter); | |
f6708c36 | 7158 | auto_bitmap remove_pseudos (®_obstack); |
c6a6cdaa | 7159 | n_inherit = n_all_inherit = 0; |
7160 | EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos, 0, regno, bi) | |
ab4ea053 | 7161 | if (lra_reg_info[regno].restore_rtx != NULL_RTX) |
c6a6cdaa | 7162 | { |
7163 | n_all_inherit++; | |
267200f3 | 7164 | if (reg_renumber[regno] < 0 |
7165 | /* If the original pseudo changed its allocation, just | |
7166 | removing inheritance is dangerous as for changing | |
7167 | allocation we used shorter live-ranges. */ | |
ab4ea053 | 7168 | && (! REG_P (lra_reg_info[regno].restore_rtx) |
7169 | || reg_renumber[REGNO (lra_reg_info[regno].restore_rtx)] < 0)) | |
f6708c36 | 7170 | bitmap_set_bit (remove_pseudos, regno); |
c6a6cdaa | 7171 | else |
7172 | n_inherit++; | |
7173 | } | |
7174 | if (lra_dump_file != NULL && n_all_inherit != 0) | |
7175 | fprintf (lra_dump_file, "Inherit %d out of %d (%.2f%%)\n", | |
7176 | n_inherit, n_all_inherit, | |
7177 | (double) n_inherit / n_all_inherit * 100); | |
7178 | n_split = n_all_split = 0; | |
7179 | EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs, 0, regno, bi) | |
ab4ea053 | 7180 | if ((restore_rtx = lra_reg_info[regno].restore_rtx) != NULL_RTX) |
c6a6cdaa | 7181 | { |
ab4ea053 | 7182 | int restore_regno = REGNO (restore_rtx); |
7183 | ||
c6a6cdaa | 7184 | n_all_split++; |
7185 | hard_regno = (restore_regno >= FIRST_PSEUDO_REGISTER | |
7186 | ? reg_renumber[restore_regno] : restore_regno); | |
7187 | if (hard_regno < 0 || reg_renumber[regno] == hard_regno) | |
f6708c36 | 7188 | bitmap_set_bit (remove_pseudos, regno); |
c6a6cdaa | 7189 | else |
7190 | { | |
7191 | n_split++; | |
7192 | if (lra_dump_file != NULL) | |
7193 | fprintf (lra_dump_file, " Keep split r%d (orig=r%d)\n", | |
7194 | regno, restore_regno); | |
7195 | } | |
7196 | } | |
7197 | if (lra_dump_file != NULL && n_all_split != 0) | |
7198 | fprintf (lra_dump_file, "Split %d out of %d (%.2f%%)\n", | |
7199 | n_split, n_all_split, | |
7200 | (double) n_split / n_all_split * 100); | |
f6708c36 | 7201 | change_p = remove_inheritance_pseudos (remove_pseudos); |
c6a6cdaa | 7202 | /* Clear restore_regnos. */ |
7203 | EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos, 0, regno, bi) | |
ab4ea053 | 7204 | lra_reg_info[regno].restore_rtx = NULL_RTX; |
c6a6cdaa | 7205 | EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs, 0, regno, bi) |
ab4ea053 | 7206 | lra_reg_info[regno].restore_rtx = NULL_RTX; |
1f3a048a | 7207 | change_p = undo_optional_reloads () || change_p; |
c6a6cdaa | 7208 | return change_p; |
7209 | } |