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c6a6cdaa | 1 | /* Code for RTL transformations to satisfy insn constraints. |
fbd26352 | 2 | Copyright (C) 2010-2019 Free Software Foundation, Inc. |
c6a6cdaa | 3 | Contributed by Vladimir Makarov <vmakarov@redhat.com>. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it under | |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 3, or (at your option) any later | |
10 | version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | ||
22 | /* This file contains code for 3 passes: constraint pass, | |
23 | inheritance/split pass, and pass for undoing failed inheritance and | |
24 | split. | |
25 | ||
26 | The major goal of constraint pass is to transform RTL to satisfy | |
27 | insn and address constraints by: | |
28 | o choosing insn alternatives; | |
29 | o generating *reload insns* (or reloads in brief) and *reload | |
30 | pseudos* which will get necessary hard registers later; | |
31 | o substituting pseudos with equivalent values and removing the | |
32 | instructions that initialized those pseudos. | |
33 | ||
34 | The constraint pass has biggest and most complicated code in LRA. | |
35 | There are a lot of important details like: | |
36 | o reuse of input reload pseudos to simplify reload pseudo | |
37 | allocations; | |
38 | o some heuristics to choose insn alternative to improve the | |
39 | inheritance; | |
40 | o early clobbers etc. | |
41 | ||
42 | The pass is mimicking former reload pass in alternative choosing | |
43 | because the reload pass is oriented to current machine description | |
44 | model. It might be changed if the machine description model is | |
45 | changed. | |
46 | ||
47 | There is special code for preventing all LRA and this pass cycling | |
48 | in case of bugs. | |
49 | ||
50 | On the first iteration of the pass we process every instruction and | |
51 | choose an alternative for each one. On subsequent iterations we try | |
52 | to avoid reprocessing instructions if we can be sure that the old | |
53 | choice is still valid. | |
54 | ||
55 | The inheritance/spilt pass is to transform code to achieve | |
56 | ineheritance and live range splitting. It is done on backward | |
57 | traversal of EBBs. | |
58 | ||
59 | The inheritance optimization goal is to reuse values in hard | |
60 | registers. There is analogous optimization in old reload pass. The | |
61 | inheritance is achieved by following transformation: | |
62 | ||
63 | reload_p1 <- p reload_p1 <- p | |
64 | ... new_p <- reload_p1 | |
65 | ... => ... | |
66 | reload_p2 <- p reload_p2 <- new_p | |
67 | ||
68 | where p is spilled and not changed between the insns. Reload_p1 is | |
69 | also called *original pseudo* and new_p is called *inheritance | |
70 | pseudo*. | |
71 | ||
72 | The subsequent assignment pass will try to assign the same (or | |
73 | another if it is not possible) hard register to new_p as to | |
74 | reload_p1 or reload_p2. | |
75 | ||
76 | If the assignment pass fails to assign a hard register to new_p, | |
77 | this file will undo the inheritance and restore the original code. | |
78 | This is because implementing the above sequence with a spilled | |
79 | new_p would make the code much worse. The inheritance is done in | |
80 | EBB scope. The above is just a simplified example to get an idea | |
81 | of the inheritance as the inheritance is also done for non-reload | |
82 | insns. | |
83 | ||
84 | Splitting (transformation) is also done in EBB scope on the same | |
85 | pass as the inheritance: | |
86 | ||
87 | r <- ... or ... <- r r <- ... or ... <- r | |
88 | ... s <- r (new insn -- save) | |
1a8f8886 | 89 | ... => |
c6a6cdaa | 90 | ... r <- s (new insn -- restore) |
91 | ... <- r ... <- r | |
92 | ||
93 | The *split pseudo* s is assigned to the hard register of the | |
94 | original pseudo or hard register r. | |
95 | ||
96 | Splitting is done: | |
97 | o In EBBs with high register pressure for global pseudos (living | |
98 | in at least 2 BBs) and assigned to hard registers when there | |
99 | are more one reloads needing the hard registers; | |
100 | o for pseudos needing save/restore code around calls. | |
101 | ||
102 | If the split pseudo still has the same hard register as the | |
103 | original pseudo after the subsequent assignment pass or the | |
104 | original pseudo was split, the opposite transformation is done on | |
105 | the same pass for undoing inheritance. */ | |
106 | ||
107 | #undef REG_OK_STRICT | |
108 | ||
109 | #include "config.h" | |
110 | #include "system.h" | |
111 | #include "coretypes.h" | |
9ef16211 | 112 | #include "backend.h" |
7c29e30e | 113 | #include "target.h" |
c6a6cdaa | 114 | #include "rtl.h" |
7c29e30e | 115 | #include "tree.h" |
116 | #include "predict.h" | |
9ef16211 | 117 | #include "df.h" |
ad7b10a2 | 118 | #include "memmodel.h" |
c6a6cdaa | 119 | #include "tm_p.h" |
7c29e30e | 120 | #include "expmed.h" |
121 | #include "optabs.h" | |
c6a6cdaa | 122 | #include "regs.h" |
7c29e30e | 123 | #include "ira.h" |
c6a6cdaa | 124 | #include "recog.h" |
125 | #include "output.h" | |
126 | #include "addresses.h" | |
c6a6cdaa | 127 | #include "expr.h" |
94ea8568 | 128 | #include "cfgrtl.h" |
c6a6cdaa | 129 | #include "rtl-error.h" |
4b69081d | 130 | #include "params.h" |
9ef16211 | 131 | #include "lra.h" |
c6a6cdaa | 132 | #include "lra-int.h" |
397881d3 | 133 | #include "print-rtl.h" |
c6a6cdaa | 134 | |
135 | /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current | |
136 | insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted | |
137 | reload insns. */ | |
138 | static int bb_reload_num; | |
139 | ||
ea99c7a1 | 140 | /* The current insn being processed and corresponding its single set |
141 | (NULL otherwise), its data (basic block, the insn data, the insn | |
142 | static data, and the mode of each operand). */ | |
7f836b57 | 143 | static rtx_insn *curr_insn; |
ea99c7a1 | 144 | static rtx curr_insn_set; |
c6a6cdaa | 145 | static basic_block curr_bb; |
146 | static lra_insn_recog_data_t curr_id; | |
147 | static struct lra_static_insn_data *curr_static_id; | |
3754d046 | 148 | static machine_mode curr_operand_mode[MAX_RECOG_OPERANDS]; |
1aae95ec | 149 | /* Mode of the register substituted by its equivalence with VOIDmode |
150 | (e.g. constant) and whose subreg is given operand of the current | |
151 | insn. VOIDmode in all other cases. */ | |
152 | static machine_mode original_subreg_reg_mode[MAX_RECOG_OPERANDS]; | |
c6a6cdaa | 153 | |
154 | \f | |
155 | ||
156 | /* Start numbers for new registers and insns at the current constraints | |
157 | pass start. */ | |
158 | static int new_regno_start; | |
159 | static int new_insn_uid_start; | |
160 | ||
1efe9e9d | 161 | /* If LOC is nonnull, strip any outer subreg from it. */ |
162 | static inline rtx * | |
163 | strip_subreg (rtx *loc) | |
164 | { | |
165 | return loc && GET_CODE (*loc) == SUBREG ? &SUBREG_REG (*loc) : loc; | |
166 | } | |
167 | ||
c6a6cdaa | 168 | /* Return hard regno of REGNO or if it is was not assigned to a hard |
169 | register, use a hard register from its allocno class. */ | |
170 | static int | |
171 | get_try_hard_regno (int regno) | |
172 | { | |
173 | int hard_regno; | |
174 | enum reg_class rclass; | |
175 | ||
176 | if ((hard_regno = regno) >= FIRST_PSEUDO_REGISTER) | |
177 | hard_regno = lra_get_regno_hard_regno (regno); | |
178 | if (hard_regno >= 0) | |
179 | return hard_regno; | |
180 | rclass = lra_get_allocno_class (regno); | |
181 | if (rclass == NO_REGS) | |
182 | return -1; | |
183 | return ira_class_hard_regs[rclass][0]; | |
184 | } | |
185 | ||
9731eaaf | 186 | /* Return the hard regno of X after removing its subreg. If X is not |
187 | a register or a subreg of a register, return -1. If X is a pseudo, | |
331a9ecc | 188 | use its assignment. If FINAL_P return the final hard regno which will |
189 | be after elimination. */ | |
c6a6cdaa | 190 | static int |
331a9ecc | 191 | get_hard_regno (rtx x, bool final_p) |
c6a6cdaa | 192 | { |
193 | rtx reg; | |
331a9ecc | 194 | int hard_regno; |
c6a6cdaa | 195 | |
196 | reg = x; | |
9731eaaf | 197 | if (SUBREG_P (x)) |
c6a6cdaa | 198 | reg = SUBREG_REG (x); |
199 | if (! REG_P (reg)) | |
200 | return -1; | |
9731eaaf | 201 | if (! HARD_REGISTER_NUM_P (hard_regno = REGNO (reg))) |
c6a6cdaa | 202 | hard_regno = lra_get_regno_hard_regno (hard_regno); |
203 | if (hard_regno < 0) | |
204 | return -1; | |
331a9ecc | 205 | if (final_p) |
206 | hard_regno = lra_get_elimination_hard_regno (hard_regno); | |
9731eaaf | 207 | if (SUBREG_P (x)) |
331a9ecc | 208 | hard_regno += subreg_regno_offset (hard_regno, GET_MODE (reg), |
209 | SUBREG_BYTE (x), GET_MODE (x)); | |
210 | return hard_regno; | |
c6a6cdaa | 211 | } |
212 | ||
213 | /* If REGNO is a hard register or has been allocated a hard register, | |
214 | return the class of that register. If REGNO is a reload pseudo | |
215 | created by the current constraints pass, return its allocno class. | |
216 | Return NO_REGS otherwise. */ | |
217 | static enum reg_class | |
218 | get_reg_class (int regno) | |
219 | { | |
220 | int hard_regno; | |
221 | ||
331a9ecc | 222 | if (! HARD_REGISTER_NUM_P (hard_regno = regno)) |
c6a6cdaa | 223 | hard_regno = lra_get_regno_hard_regno (regno); |
224 | if (hard_regno >= 0) | |
225 | { | |
331a9ecc | 226 | hard_regno = lra_get_elimination_hard_regno (hard_regno); |
c6a6cdaa | 227 | return REGNO_REG_CLASS (hard_regno); |
228 | } | |
229 | if (regno >= new_regno_start) | |
230 | return lra_get_allocno_class (regno); | |
231 | return NO_REGS; | |
232 | } | |
233 | ||
234 | /* Return true if REG satisfies (or will satisfy) reg class constraint | |
235 | CL. Use elimination first if REG is a hard register. If REG is a | |
236 | reload pseudo created by this constraints pass, assume that it will | |
237 | be allocated a hard register from its allocno class, but allow that | |
238 | class to be narrowed to CL if it is currently a superset of CL. | |
239 | ||
240 | If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of | |
241 | REGNO (reg), or NO_REGS if no change in its class was needed. */ | |
242 | static bool | |
243 | in_class_p (rtx reg, enum reg_class cl, enum reg_class *new_class) | |
244 | { | |
245 | enum reg_class rclass, common_class; | |
3754d046 | 246 | machine_mode reg_mode; |
c6a6cdaa | 247 | int class_size, hard_regno, nregs, i, j; |
248 | int regno = REGNO (reg); | |
1a8f8886 | 249 | |
c6a6cdaa | 250 | if (new_class != NULL) |
251 | *new_class = NO_REGS; | |
252 | if (regno < FIRST_PSEUDO_REGISTER) | |
253 | { | |
254 | rtx final_reg = reg; | |
255 | rtx *final_loc = &final_reg; | |
1a8f8886 | 256 | |
c6a6cdaa | 257 | lra_eliminate_reg_if_possible (final_loc); |
258 | return TEST_HARD_REG_BIT (reg_class_contents[cl], REGNO (*final_loc)); | |
259 | } | |
260 | reg_mode = GET_MODE (reg); | |
261 | rclass = get_reg_class (regno); | |
262 | if (regno < new_regno_start | |
263 | /* Do not allow the constraints for reload instructions to | |
264 | influence the classes of new pseudos. These reloads are | |
265 | typically moves that have many alternatives, and restricting | |
266 | reload pseudos for one alternative may lead to situations | |
267 | where other reload pseudos are no longer allocatable. */ | |
7619e612 | 268 | || (INSN_UID (curr_insn) >= new_insn_uid_start |
269 | && curr_insn_set != NULL | |
58f94f4a | 270 | && ((OBJECT_P (SET_SRC (curr_insn_set)) |
271 | && ! CONSTANT_P (SET_SRC (curr_insn_set))) | |
7619e612 | 272 | || (GET_CODE (SET_SRC (curr_insn_set)) == SUBREG |
58f94f4a | 273 | && OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set))) |
274 | && ! CONSTANT_P (SUBREG_REG (SET_SRC (curr_insn_set))))))) | |
c6a6cdaa | 275 | /* When we don't know what class will be used finally for reload |
276 | pseudos, we use ALL_REGS. */ | |
277 | return ((regno >= new_regno_start && rclass == ALL_REGS) | |
278 | || (rclass != NO_REGS && ira_class_subset_p[rclass][cl] | |
279 | && ! hard_reg_set_subset_p (reg_class_contents[cl], | |
280 | lra_no_alloc_regs))); | |
281 | else | |
282 | { | |
283 | common_class = ira_reg_class_subset[rclass][cl]; | |
284 | if (new_class != NULL) | |
285 | *new_class = common_class; | |
286 | if (hard_reg_set_subset_p (reg_class_contents[common_class], | |
287 | lra_no_alloc_regs)) | |
288 | return false; | |
289 | /* Check that there are enough allocatable regs. */ | |
290 | class_size = ira_class_hard_regs_num[common_class]; | |
291 | for (i = 0; i < class_size; i++) | |
292 | { | |
293 | hard_regno = ira_class_hard_regs[common_class][i]; | |
92d2aec3 | 294 | nregs = hard_regno_nregs (hard_regno, reg_mode); |
c6a6cdaa | 295 | if (nregs == 1) |
296 | return true; | |
297 | for (j = 0; j < nregs; j++) | |
68132dc4 | 298 | if (TEST_HARD_REG_BIT (lra_no_alloc_regs, hard_regno + j) |
299 | || ! TEST_HARD_REG_BIT (reg_class_contents[common_class], | |
300 | hard_regno + j)) | |
c6a6cdaa | 301 | break; |
302 | if (j >= nregs) | |
303 | return true; | |
304 | } | |
305 | return false; | |
306 | } | |
307 | } | |
308 | ||
309 | /* Return true if REGNO satisfies a memory constraint. */ | |
310 | static bool | |
311 | in_mem_p (int regno) | |
312 | { | |
313 | return get_reg_class (regno) == NO_REGS; | |
314 | } | |
315 | ||
67e22af9 | 316 | /* Return 1 if ADDR is a valid memory address for mode MODE in address |
317 | space AS, and check that each pseudo has the proper kind of hard | |
318 | reg. */ | |
319 | static int | |
3754d046 | 320 | valid_address_p (machine_mode mode ATTRIBUTE_UNUSED, |
67e22af9 | 321 | rtx addr, addr_space_t as) |
322 | { | |
323 | #ifdef GO_IF_LEGITIMATE_ADDRESS | |
324 | lra_assert (ADDR_SPACE_GENERIC_P (as)); | |
325 | GO_IF_LEGITIMATE_ADDRESS (mode, addr, win); | |
326 | return 0; | |
327 | ||
328 | win: | |
329 | return 1; | |
330 | #else | |
331 | return targetm.addr_space.legitimate_address_p (mode, addr, 0, as); | |
332 | #endif | |
333 | } | |
334 | ||
335 | namespace { | |
336 | /* Temporarily eliminates registers in an address (for the lifetime of | |
337 | the object). */ | |
338 | class address_eliminator { | |
339 | public: | |
340 | address_eliminator (struct address_info *ad); | |
341 | ~address_eliminator (); | |
342 | ||
343 | private: | |
344 | struct address_info *m_ad; | |
345 | rtx *m_base_loc; | |
346 | rtx m_base_reg; | |
347 | rtx *m_index_loc; | |
348 | rtx m_index_reg; | |
349 | }; | |
350 | } | |
351 | ||
352 | address_eliminator::address_eliminator (struct address_info *ad) | |
353 | : m_ad (ad), | |
354 | m_base_loc (strip_subreg (ad->base_term)), | |
355 | m_base_reg (NULL_RTX), | |
356 | m_index_loc (strip_subreg (ad->index_term)), | |
357 | m_index_reg (NULL_RTX) | |
358 | { | |
359 | if (m_base_loc != NULL) | |
360 | { | |
361 | m_base_reg = *m_base_loc; | |
6dc6c0a7 | 362 | /* If we have non-legitimate address which is decomposed not in |
363 | the way we expected, don't do elimination here. In such case | |
364 | the address will be reloaded and elimination will be done in | |
365 | reload insn finally. */ | |
366 | if (REG_P (m_base_reg)) | |
367 | lra_eliminate_reg_if_possible (m_base_loc); | |
67e22af9 | 368 | if (m_ad->base_term2 != NULL) |
369 | *m_ad->base_term2 = *m_ad->base_term; | |
370 | } | |
371 | if (m_index_loc != NULL) | |
372 | { | |
373 | m_index_reg = *m_index_loc; | |
6dc6c0a7 | 374 | if (REG_P (m_index_reg)) |
375 | lra_eliminate_reg_if_possible (m_index_loc); | |
67e22af9 | 376 | } |
377 | } | |
378 | ||
379 | address_eliminator::~address_eliminator () | |
380 | { | |
381 | if (m_base_loc && *m_base_loc != m_base_reg) | |
382 | { | |
383 | *m_base_loc = m_base_reg; | |
384 | if (m_ad->base_term2 != NULL) | |
385 | *m_ad->base_term2 = *m_ad->base_term; | |
386 | } | |
387 | if (m_index_loc && *m_index_loc != m_index_reg) | |
388 | *m_index_loc = m_index_reg; | |
389 | } | |
390 | ||
391 | /* Return true if the eliminated form of AD is a legitimate target address. */ | |
392 | static bool | |
393 | valid_address_p (struct address_info *ad) | |
394 | { | |
395 | address_eliminator eliminator (ad); | |
396 | return valid_address_p (ad->mode, *ad->outer, ad->as); | |
397 | } | |
398 | ||
67e22af9 | 399 | /* Return true if the eliminated form of memory reference OP satisfies |
6b3b345a | 400 | extra (special) memory constraint CONSTRAINT. */ |
67e22af9 | 401 | static bool |
79bc09fb | 402 | satisfies_memory_constraint_p (rtx op, enum constraint_num constraint) |
67e22af9 | 403 | { |
404 | struct address_info ad; | |
405 | ||
406 | decompose_mem_address (&ad, op); | |
407 | address_eliminator eliminator (&ad); | |
79bc09fb | 408 | return constraint_satisfied_p (op, constraint); |
67e22af9 | 409 | } |
410 | ||
411 | /* Return true if the eliminated form of address AD satisfies extra | |
412 | address constraint CONSTRAINT. */ | |
413 | static bool | |
414 | satisfies_address_constraint_p (struct address_info *ad, | |
79bc09fb | 415 | enum constraint_num constraint) |
67e22af9 | 416 | { |
417 | address_eliminator eliminator (ad); | |
79bc09fb | 418 | return constraint_satisfied_p (*ad->outer, constraint); |
67e22af9 | 419 | } |
420 | ||
421 | /* Return true if the eliminated form of address OP satisfies extra | |
422 | address constraint CONSTRAINT. */ | |
423 | static bool | |
79bc09fb | 424 | satisfies_address_constraint_p (rtx op, enum constraint_num constraint) |
67e22af9 | 425 | { |
426 | struct address_info ad; | |
427 | ||
428 | decompose_lea_address (&ad, &op); | |
429 | return satisfies_address_constraint_p (&ad, constraint); | |
430 | } | |
67e22af9 | 431 | |
61cd3e57 | 432 | /* Initiate equivalences for LRA. As we keep original equivalences |
433 | before any elimination, we need to make copies otherwise any change | |
434 | in insns might change the equivalences. */ | |
435 | void | |
436 | lra_init_equiv (void) | |
437 | { | |
438 | ira_expand_reg_equiv (); | |
439 | for (int i = FIRST_PSEUDO_REGISTER; i < max_reg_num (); i++) | |
440 | { | |
441 | rtx res; | |
442 | ||
443 | if ((res = ira_reg_equiv[i].memory) != NULL_RTX) | |
444 | ira_reg_equiv[i].memory = copy_rtx (res); | |
445 | if ((res = ira_reg_equiv[i].invariant) != NULL_RTX) | |
446 | ira_reg_equiv[i].invariant = copy_rtx (res); | |
447 | } | |
448 | } | |
449 | ||
450 | static rtx loc_equivalence_callback (rtx, const_rtx, void *); | |
451 | ||
452 | /* Update equivalence for REGNO. We need to this as the equivalence | |
453 | might contain other pseudos which are changed by their | |
454 | equivalences. */ | |
455 | static void | |
456 | update_equiv (int regno) | |
457 | { | |
458 | rtx x; | |
459 | ||
460 | if ((x = ira_reg_equiv[regno].memory) != NULL_RTX) | |
461 | ira_reg_equiv[regno].memory | |
462 | = simplify_replace_fn_rtx (x, NULL_RTX, loc_equivalence_callback, | |
463 | NULL_RTX); | |
464 | if ((x = ira_reg_equiv[regno].invariant) != NULL_RTX) | |
465 | ira_reg_equiv[regno].invariant | |
466 | = simplify_replace_fn_rtx (x, NULL_RTX, loc_equivalence_callback, | |
467 | NULL_RTX); | |
468 | } | |
469 | ||
c6a6cdaa | 470 | /* If we have decided to substitute X with another value, return that |
471 | value, otherwise return X. */ | |
472 | static rtx | |
3b3a5e5f | 473 | get_equiv (rtx x) |
c6a6cdaa | 474 | { |
475 | int regno; | |
476 | rtx res; | |
477 | ||
478 | if (! REG_P (x) || (regno = REGNO (x)) < FIRST_PSEUDO_REGISTER | |
479 | || ! ira_reg_equiv[regno].defined_p | |
480 | || ! ira_reg_equiv[regno].profitable_p | |
481 | || lra_get_regno_hard_regno (regno) >= 0) | |
482 | return x; | |
483 | if ((res = ira_reg_equiv[regno].memory) != NULL_RTX) | |
f4447329 | 484 | { |
485 | if (targetm.cannot_substitute_mem_equiv_p (res)) | |
486 | return x; | |
487 | return res; | |
488 | } | |
c6a6cdaa | 489 | if ((res = ira_reg_equiv[regno].constant) != NULL_RTX) |
490 | return res; | |
491 | if ((res = ira_reg_equiv[regno].invariant) != NULL_RTX) | |
492 | return res; | |
493 | gcc_unreachable (); | |
494 | } | |
495 | ||
3b3a5e5f | 496 | /* If we have decided to substitute X with the equivalent value, |
497 | return that value after elimination for INSN, otherwise return | |
498 | X. */ | |
499 | static rtx | |
7f836b57 | 500 | get_equiv_with_elimination (rtx x, rtx_insn *insn) |
3b3a5e5f | 501 | { |
502 | rtx res = get_equiv (x); | |
503 | ||
504 | if (x == res || CONSTANT_P (res)) | |
505 | return res; | |
497ba60f | 506 | return lra_eliminate_regs_1 (insn, res, GET_MODE (res), |
99535fab | 507 | false, false, 0, true); |
3b3a5e5f | 508 | } |
509 | ||
c6a6cdaa | 510 | /* Set up curr_operand_mode. */ |
511 | static void | |
512 | init_curr_operand_mode (void) | |
513 | { | |
514 | int nop = curr_static_id->n_operands; | |
515 | for (int i = 0; i < nop; i++) | |
516 | { | |
3754d046 | 517 | machine_mode mode = GET_MODE (*curr_id->operand_loc[i]); |
c6a6cdaa | 518 | if (mode == VOIDmode) |
519 | { | |
520 | /* The .md mode for address operands is the mode of the | |
521 | addressed value rather than the mode of the address itself. */ | |
522 | if (curr_id->icode >= 0 && curr_static_id->operand[i].is_address) | |
523 | mode = Pmode; | |
524 | else | |
525 | mode = curr_static_id->operand[i].mode; | |
526 | } | |
527 | curr_operand_mode[i] = mode; | |
528 | } | |
529 | } | |
530 | ||
531 | \f | |
532 | ||
533 | /* The page contains code to reuse input reloads. */ | |
534 | ||
535 | /* Structure describes input reload of the current insns. */ | |
536 | struct input_reload | |
537 | { | |
bd13359a | 538 | /* True for input reload of matched operands. */ |
539 | bool match_p; | |
c6a6cdaa | 540 | /* Reloaded value. */ |
541 | rtx input; | |
542 | /* Reload pseudo used. */ | |
543 | rtx reg; | |
544 | }; | |
545 | ||
546 | /* The number of elements in the following array. */ | |
547 | static int curr_insn_input_reloads_num; | |
548 | /* Array containing info about input reloads. It is used to find the | |
549 | same input reload and reuse the reload pseudo in this case. */ | |
550 | static struct input_reload curr_insn_input_reloads[LRA_MAX_INSN_RELOADS]; | |
551 | ||
552 | /* Initiate data concerning reuse of input reloads for the current | |
553 | insn. */ | |
554 | static void | |
555 | init_curr_insn_input_reloads (void) | |
556 | { | |
557 | curr_insn_input_reloads_num = 0; | |
558 | } | |
559 | ||
c6a6cdaa | 560 | /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already |
6cadc8f7 | 561 | created input reload pseudo (only if TYPE is not OP_OUT). Don't |
562 | reuse pseudo if IN_SUBREG_P is true and the reused pseudo should be | |
563 | wrapped up in SUBREG. The result pseudo is returned through | |
564 | RESULT_REG. Return TRUE if we created a new pseudo, FALSE if we | |
565 | reused the already created input reload pseudo. Use TITLE to | |
566 | describe new registers for debug purposes. */ | |
c6a6cdaa | 567 | static bool |
3754d046 | 568 | get_reload_reg (enum op_type type, machine_mode mode, rtx original, |
6cadc8f7 | 569 | enum reg_class rclass, bool in_subreg_p, |
570 | const char *title, rtx *result_reg) | |
c6a6cdaa | 571 | { |
572 | int i, regno; | |
573 | enum reg_class new_class; | |
bd13359a | 574 | bool unique_p = false; |
c6a6cdaa | 575 | |
576 | if (type == OP_OUT) | |
577 | { | |
578 | *result_reg | |
579 | = lra_create_new_reg_with_unique_value (mode, original, rclass, title); | |
580 | return true; | |
581 | } | |
85276115 | 582 | /* Prevent reuse value of expression with side effects, |
583 | e.g. volatile memory. */ | |
584 | if (! side_effects_p (original)) | |
585 | for (i = 0; i < curr_insn_input_reloads_num; i++) | |
bd13359a | 586 | { |
587 | if (! curr_insn_input_reloads[i].match_p | |
588 | && rtx_equal_p (curr_insn_input_reloads[i].input, original) | |
589 | && in_class_p (curr_insn_input_reloads[i].reg, rclass, &new_class)) | |
590 | { | |
591 | rtx reg = curr_insn_input_reloads[i].reg; | |
592 | regno = REGNO (reg); | |
593 | /* If input is equal to original and both are VOIDmode, | |
594 | GET_MODE (reg) might be still different from mode. | |
595 | Ensure we don't return *result_reg with wrong mode. */ | |
596 | if (GET_MODE (reg) != mode) | |
597 | { | |
598 | if (in_subreg_p) | |
599 | continue; | |
52acb7ae | 600 | if (maybe_lt (GET_MODE_SIZE (GET_MODE (reg)), |
601 | GET_MODE_SIZE (mode))) | |
bd13359a | 602 | continue; |
603 | reg = lowpart_subreg (mode, reg, GET_MODE (reg)); | |
604 | if (reg == NULL_RTX || GET_CODE (reg) != SUBREG) | |
605 | continue; | |
606 | } | |
607 | *result_reg = reg; | |
608 | if (lra_dump_file != NULL) | |
609 | { | |
610 | fprintf (lra_dump_file, " Reuse r%d for reload ", regno); | |
611 | dump_value_slim (lra_dump_file, original, 1); | |
612 | } | |
613 | if (new_class != lra_get_allocno_class (regno)) | |
614 | lra_change_class (regno, new_class, ", change to", false); | |
615 | if (lra_dump_file != NULL) | |
616 | fprintf (lra_dump_file, "\n"); | |
617 | return false; | |
618 | } | |
619 | /* If we have an input reload with a different mode, make sure it | |
620 | will get a different hard reg. */ | |
621 | else if (REG_P (original) | |
622 | && REG_P (curr_insn_input_reloads[i].input) | |
623 | && REGNO (original) == REGNO (curr_insn_input_reloads[i].input) | |
624 | && (GET_MODE (original) | |
625 | != GET_MODE (curr_insn_input_reloads[i].input))) | |
626 | unique_p = true; | |
627 | } | |
628 | *result_reg = (unique_p | |
629 | ? lra_create_new_reg_with_unique_value | |
630 | : lra_create_new_reg) (mode, original, rclass, title); | |
c6a6cdaa | 631 | lra_assert (curr_insn_input_reloads_num < LRA_MAX_INSN_RELOADS); |
632 | curr_insn_input_reloads[curr_insn_input_reloads_num].input = original; | |
bd13359a | 633 | curr_insn_input_reloads[curr_insn_input_reloads_num].match_p = false; |
c6a6cdaa | 634 | curr_insn_input_reloads[curr_insn_input_reloads_num++].reg = *result_reg; |
635 | return true; | |
636 | } | |
637 | ||
638 | \f | |
c6a6cdaa | 639 | /* The page contains major code to choose the current insn alternative |
640 | and generate reloads for it. */ | |
641 | ||
642 | /* Return the offset from REGNO of the least significant register | |
643 | in (reg:MODE REGNO). | |
644 | ||
645 | This function is used to tell whether two registers satisfy | |
646 | a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if: | |
647 | ||
648 | REGNO1 + lra_constraint_offset (REGNO1, MODE1) | |
649 | == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */ | |
650 | int | |
3754d046 | 651 | lra_constraint_offset (int regno, machine_mode mode) |
c6a6cdaa | 652 | { |
653 | lra_assert (regno < FIRST_PSEUDO_REGISTER); | |
8974b7a3 | 654 | |
655 | scalar_int_mode int_mode; | |
656 | if (WORDS_BIG_ENDIAN | |
657 | && is_a <scalar_int_mode> (mode, &int_mode) | |
658 | && GET_MODE_SIZE (int_mode) > UNITS_PER_WORD) | |
92d2aec3 | 659 | return hard_regno_nregs (regno, mode) - 1; |
c6a6cdaa | 660 | return 0; |
661 | } | |
662 | ||
663 | /* Like rtx_equal_p except that it allows a REG and a SUBREG to match | |
664 | if they are the same hard reg, and has special hacks for | |
665 | auto-increment and auto-decrement. This is specifically intended for | |
666 | process_alt_operands to use in determining whether two operands | |
667 | match. X is the operand whose number is the lower of the two. | |
668 | ||
669 | It is supposed that X is the output operand and Y is the input | |
670 | operand. Y_HARD_REGNO is the final hard regno of register Y or | |
671 | register in subreg Y as we know it now. Otherwise, it is a | |
672 | negative value. */ | |
673 | static bool | |
674 | operands_match_p (rtx x, rtx y, int y_hard_regno) | |
675 | { | |
676 | int i; | |
677 | RTX_CODE code = GET_CODE (x); | |
678 | const char *fmt; | |
679 | ||
680 | if (x == y) | |
681 | return true; | |
682 | if ((code == REG || (code == SUBREG && REG_P (SUBREG_REG (x)))) | |
683 | && (REG_P (y) || (GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y))))) | |
684 | { | |
685 | int j; | |
1a8f8886 | 686 | |
331a9ecc | 687 | i = get_hard_regno (x, false); |
c6a6cdaa | 688 | if (i < 0) |
689 | goto slow; | |
690 | ||
691 | if ((j = y_hard_regno) < 0) | |
692 | goto slow; | |
693 | ||
694 | i += lra_constraint_offset (i, GET_MODE (x)); | |
695 | j += lra_constraint_offset (j, GET_MODE (y)); | |
696 | ||
697 | return i == j; | |
698 | } | |
699 | ||
700 | /* If two operands must match, because they are really a single | |
701 | operand of an assembler insn, then two post-increments are invalid | |
702 | because the assembler insn would increment only once. On the | |
703 | other hand, a post-increment matches ordinary indexing if the | |
704 | post-increment is the output operand. */ | |
705 | if (code == POST_DEC || code == POST_INC || code == POST_MODIFY) | |
706 | return operands_match_p (XEXP (x, 0), y, y_hard_regno); | |
707 | ||
708 | /* Two pre-increments are invalid because the assembler insn would | |
709 | increment only once. On the other hand, a pre-increment matches | |
710 | ordinary indexing if the pre-increment is the input operand. */ | |
711 | if (GET_CODE (y) == PRE_DEC || GET_CODE (y) == PRE_INC | |
712 | || GET_CODE (y) == PRE_MODIFY) | |
713 | return operands_match_p (x, XEXP (y, 0), -1); | |
1a8f8886 | 714 | |
c6a6cdaa | 715 | slow: |
716 | ||
15183fd2 | 717 | if (code == REG && REG_P (y)) |
718 | return REGNO (x) == REGNO (y); | |
719 | ||
c6a6cdaa | 720 | if (code == REG && GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y)) |
721 | && x == SUBREG_REG (y)) | |
722 | return true; | |
723 | if (GET_CODE (y) == REG && code == SUBREG && REG_P (SUBREG_REG (x)) | |
724 | && SUBREG_REG (x) == y) | |
725 | return true; | |
726 | ||
727 | /* Now we have disposed of all the cases in which different rtx | |
728 | codes can match. */ | |
729 | if (code != GET_CODE (y)) | |
730 | return false; | |
731 | ||
732 | /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */ | |
733 | if (GET_MODE (x) != GET_MODE (y)) | |
734 | return false; | |
735 | ||
736 | switch (code) | |
737 | { | |
738 | CASE_CONST_UNIQUE: | |
739 | return false; | |
740 | ||
741 | case LABEL_REF: | |
c7799456 | 742 | return label_ref_label (x) == label_ref_label (y); |
c6a6cdaa | 743 | case SYMBOL_REF: |
744 | return XSTR (x, 0) == XSTR (y, 0); | |
745 | ||
746 | default: | |
747 | break; | |
748 | } | |
749 | ||
750 | /* Compare the elements. If any pair of corresponding elements fail | |
751 | to match, return false for the whole things. */ | |
752 | ||
753 | fmt = GET_RTX_FORMAT (code); | |
754 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
755 | { | |
756 | int val, j; | |
757 | switch (fmt[i]) | |
758 | { | |
759 | case 'w': | |
760 | if (XWINT (x, i) != XWINT (y, i)) | |
761 | return false; | |
762 | break; | |
763 | ||
764 | case 'i': | |
765 | if (XINT (x, i) != XINT (y, i)) | |
766 | return false; | |
767 | break; | |
768 | ||
9edf7ea8 | 769 | case 'p': |
770 | if (maybe_ne (SUBREG_BYTE (x), SUBREG_BYTE (y))) | |
771 | return false; | |
772 | break; | |
773 | ||
c6a6cdaa | 774 | case 'e': |
775 | val = operands_match_p (XEXP (x, i), XEXP (y, i), -1); | |
776 | if (val == 0) | |
777 | return false; | |
778 | break; | |
779 | ||
780 | case '0': | |
781 | break; | |
782 | ||
783 | case 'E': | |
784 | if (XVECLEN (x, i) != XVECLEN (y, i)) | |
785 | return false; | |
786 | for (j = XVECLEN (x, i) - 1; j >= 0; --j) | |
787 | { | |
788 | val = operands_match_p (XVECEXP (x, i, j), XVECEXP (y, i, j), -1); | |
789 | if (val == 0) | |
790 | return false; | |
791 | } | |
792 | break; | |
793 | ||
794 | /* It is believed that rtx's at this level will never | |
795 | contain anything but integers and other rtx's, except for | |
796 | within LABEL_REFs and SYMBOL_REFs. */ | |
797 | default: | |
798 | gcc_unreachable (); | |
799 | } | |
800 | } | |
801 | return true; | |
802 | } | |
803 | ||
804 | /* True if X is a constant that can be forced into the constant pool. | |
805 | MODE is the mode of the operand, or VOIDmode if not known. */ | |
806 | #define CONST_POOL_OK_P(MODE, X) \ | |
807 | ((MODE) != VOIDmode \ | |
808 | && CONSTANT_P (X) \ | |
809 | && GET_CODE (X) != HIGH \ | |
52acb7ae | 810 | && GET_MODE_SIZE (MODE).is_constant () \ |
c6a6cdaa | 811 | && !targetm.cannot_force_const_mem (MODE, X)) |
812 | ||
813 | /* True if C is a non-empty register class that has too few registers | |
814 | to be safely used as a reload target class. */ | |
4f428208 | 815 | #define SMALL_REGISTER_CLASS_P(C) \ |
816 | (ira_class_hard_regs_num [(C)] == 1 \ | |
817 | || (ira_class_hard_regs_num [(C)] >= 1 \ | |
818 | && targetm.class_likely_spilled_p (C))) | |
c6a6cdaa | 819 | |
820 | /* If REG is a reload pseudo, try to make its class satisfying CL. */ | |
821 | static void | |
822 | narrow_reload_pseudo_class (rtx reg, enum reg_class cl) | |
823 | { | |
824 | enum reg_class rclass; | |
825 | ||
826 | /* Do not make more accurate class from reloads generated. They are | |
827 | mostly moves with a lot of constraints. Making more accurate | |
828 | class may results in very narrow class and impossibility of find | |
829 | registers for several reloads of one insn. */ | |
830 | if (INSN_UID (curr_insn) >= new_insn_uid_start) | |
831 | return; | |
832 | if (GET_CODE (reg) == SUBREG) | |
833 | reg = SUBREG_REG (reg); | |
834 | if (! REG_P (reg) || (int) REGNO (reg) < new_regno_start) | |
835 | return; | |
836 | if (in_class_p (reg, cl, &rclass) && rclass != cl) | |
7619e612 | 837 | lra_change_class (REGNO (reg), rclass, " Change to", true); |
c6a6cdaa | 838 | } |
839 | ||
f64b137f | 840 | /* Searches X for any reference to a reg with the same value as REGNO, |
841 | returning the rtx of the reference found if any. Otherwise, | |
842 | returns NULL_RTX. */ | |
843 | static rtx | |
844 | regno_val_use_in (unsigned int regno, rtx x) | |
845 | { | |
846 | const char *fmt; | |
847 | int i, j; | |
848 | rtx tem; | |
849 | ||
850 | if (REG_P (x) && lra_reg_info[REGNO (x)].val == lra_reg_info[regno].val) | |
851 | return x; | |
852 | ||
853 | fmt = GET_RTX_FORMAT (GET_CODE (x)); | |
854 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) | |
855 | { | |
856 | if (fmt[i] == 'e') | |
857 | { | |
858 | if ((tem = regno_val_use_in (regno, XEXP (x, i)))) | |
859 | return tem; | |
860 | } | |
861 | else if (fmt[i] == 'E') | |
862 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
863 | if ((tem = regno_val_use_in (regno , XVECEXP (x, i, j)))) | |
864 | return tem; | |
865 | } | |
866 | ||
867 | return NULL_RTX; | |
868 | } | |
869 | ||
099c19e2 | 870 | /* Return true if all current insn non-output operands except INS (it |
871 | has a negaitve end marker) do not use pseudos with the same value | |
872 | as REGNO. */ | |
873 | static bool | |
874 | check_conflict_input_operands (int regno, signed char *ins) | |
875 | { | |
876 | int in; | |
877 | int n_operands = curr_static_id->n_operands; | |
878 | ||
879 | for (int nop = 0; nop < n_operands; nop++) | |
880 | if (! curr_static_id->operand[nop].is_operator | |
881 | && curr_static_id->operand[nop].type != OP_OUT) | |
882 | { | |
883 | for (int i = 0; (in = ins[i]) >= 0; i++) | |
884 | if (in == nop) | |
885 | break; | |
886 | if (in < 0 | |
887 | && regno_val_use_in (regno, *curr_id->operand_loc[nop]) != NULL_RTX) | |
888 | return false; | |
889 | } | |
890 | return true; | |
891 | } | |
892 | ||
c6a6cdaa | 893 | /* Generate reloads for matching OUT and INS (array of input operand |
dd083a02 | 894 | numbers with end marker -1) with reg class GOAL_CLASS, considering |
895 | output operands OUTS (similar array to INS) needing to be in different | |
896 | registers. Add input and output reloads correspondingly to the lists | |
897 | *BEFORE and *AFTER. OUT might be negative. In this case we generate | |
898 | input reloads for matched input operands INS. EARLY_CLOBBER_P is a flag | |
899 | that the output operand is early clobbered for chosen alternative. */ | |
c6a6cdaa | 900 | static void |
dd083a02 | 901 | match_reload (signed char out, signed char *ins, signed char *outs, |
902 | enum reg_class goal_class, rtx_insn **before, | |
903 | rtx_insn **after, bool early_clobber_p) | |
c6a6cdaa | 904 | { |
dd083a02 | 905 | bool out_conflict; |
c6a6cdaa | 906 | int i, in; |
9ed997be | 907 | rtx new_in_reg, new_out_reg, reg; |
3754d046 | 908 | machine_mode inmode, outmode; |
c6a6cdaa | 909 | rtx in_rtx = *curr_id->operand_loc[ins[0]]; |
aa3ce8ba | 910 | rtx out_rtx = out < 0 ? in_rtx : *curr_id->operand_loc[out]; |
c6a6cdaa | 911 | |
c6a6cdaa | 912 | inmode = curr_operand_mode[ins[0]]; |
aa3ce8ba | 913 | outmode = out < 0 ? inmode : curr_operand_mode[out]; |
c6a6cdaa | 914 | push_to_sequence (*before); |
915 | if (inmode != outmode) | |
916 | { | |
e23bf764 | 917 | /* process_alt_operands has already checked that the mode sizes |
918 | are ordered. */ | |
974534ab | 919 | if (partial_subreg_p (outmode, inmode)) |
c6a6cdaa | 920 | { |
921 | reg = new_in_reg | |
922 | = lra_create_new_reg_with_unique_value (inmode, in_rtx, | |
923 | goal_class, ""); | |
9346305f | 924 | new_out_reg = gen_lowpart_SUBREG (outmode, reg); |
ea99c7a1 | 925 | LRA_SUBREG_P (new_out_reg) = 1; |
ad6dc746 | 926 | /* If the input reg is dying here, we can use the same hard |
edfb1d8f | 927 | register for REG and IN_RTX. We do it only for original |
928 | pseudos as reload pseudos can die although original | |
929 | pseudos still live where reload pseudos dies. */ | |
930 | if (REG_P (in_rtx) && (int) REGNO (in_rtx) < lra_new_regno_start | |
099c19e2 | 931 | && find_regno_note (curr_insn, REG_DEAD, REGNO (in_rtx)) |
932 | && (!early_clobber_p | |
933 | || check_conflict_input_operands(REGNO (in_rtx), ins))) | |
a1064490 | 934 | lra_assign_reg_val (REGNO (in_rtx), REGNO (reg)); |
c6a6cdaa | 935 | } |
936 | else | |
937 | { | |
938 | reg = new_out_reg | |
939 | = lra_create_new_reg_with_unique_value (outmode, out_rtx, | |
940 | goal_class, ""); | |
9346305f | 941 | new_in_reg = gen_lowpart_SUBREG (inmode, reg); |
c6a6cdaa | 942 | /* NEW_IN_REG is non-paradoxical subreg. We don't want |
943 | NEW_OUT_REG living above. We add clobber clause for | |
ae72d5b2 | 944 | this. This is just a temporary clobber. We can remove |
945 | it at the end of LRA work. */ | |
9ed997be | 946 | rtx_insn *clobber = emit_clobber (new_out_reg); |
ae72d5b2 | 947 | LRA_TEMP_CLOBBER_P (PATTERN (clobber)) = 1; |
ea99c7a1 | 948 | LRA_SUBREG_P (new_in_reg) = 1; |
ad6dc746 | 949 | if (GET_CODE (in_rtx) == SUBREG) |
950 | { | |
951 | rtx subreg_reg = SUBREG_REG (in_rtx); | |
952 | ||
953 | /* If SUBREG_REG is dying here and sub-registers IN_RTX | |
954 | and NEW_IN_REG are similar, we can use the same hard | |
955 | register for REG and SUBREG_REG. */ | |
edfb1d8f | 956 | if (REG_P (subreg_reg) |
957 | && (int) REGNO (subreg_reg) < lra_new_regno_start | |
958 | && GET_MODE (subreg_reg) == outmode | |
9edf7ea8 | 959 | && known_eq (SUBREG_BYTE (in_rtx), SUBREG_BYTE (new_in_reg)) |
099c19e2 | 960 | && find_regno_note (curr_insn, REG_DEAD, REGNO (subreg_reg)) |
961 | && (! early_clobber_p | |
962 | || check_conflict_input_operands (REGNO (subreg_reg), | |
963 | ins))) | |
a1064490 | 964 | lra_assign_reg_val (REGNO (subreg_reg), REGNO (reg)); |
ad6dc746 | 965 | } |
c6a6cdaa | 966 | } |
967 | } | |
968 | else | |
969 | { | |
970 | /* Pseudos have values -- see comments for lra_reg_info. | |
971 | Different pseudos with the same value do not conflict even if | |
972 | they live in the same place. When we create a pseudo we | |
973 | assign value of original pseudo (if any) from which we | |
974 | created the new pseudo. If we create the pseudo from the | |
0af99ebf | 975 | input pseudo, the new pseudo will have no conflict with the |
976 | input pseudo which is wrong when the input pseudo lives after | |
977 | the insn and as the new pseudo value is changed by the insn | |
978 | output. Therefore we create the new pseudo from the output | |
979 | except the case when we have single matched dying input | |
980 | pseudo. | |
1a8f8886 | 981 | |
c6a6cdaa | 982 | We cannot reuse the current output register because we might |
983 | have a situation like "a <- a op b", where the constraints | |
984 | force the second input operand ("b") to match the output | |
985 | operand ("a"). "b" must then be copied into a new register | |
72460f4d | 986 | so that it doesn't clobber the current value of "a". |
987 | ||
f4d3c071 | 988 | We cannot use the same value if the output pseudo is |
72460f4d | 989 | early clobbered or the input pseudo is mentioned in the |
990 | output, e.g. as an address part in memory, because | |
991 | output reload will actually extend the pseudo liveness. | |
992 | We don't care about eliminable hard regs here as we are | |
993 | interesting only in pseudos. */ | |
1a8f8886 | 994 | |
dd083a02 | 995 | /* Matching input's register value is the same as one of the other |
996 | output operand. Output operands in a parallel insn must be in | |
997 | different registers. */ | |
998 | out_conflict = false; | |
999 | if (REG_P (in_rtx)) | |
1000 | { | |
1001 | for (i = 0; outs[i] >= 0; i++) | |
1002 | { | |
1003 | rtx other_out_rtx = *curr_id->operand_loc[outs[i]]; | |
1004 | if (REG_P (other_out_rtx) | |
1005 | && (regno_val_use_in (REGNO (in_rtx), other_out_rtx) | |
1006 | != NULL_RTX)) | |
1007 | { | |
1008 | out_conflict = true; | |
1009 | break; | |
1010 | } | |
1011 | } | |
1012 | } | |
1013 | ||
c6a6cdaa | 1014 | new_in_reg = new_out_reg |
72460f4d | 1015 | = (! early_clobber_p && ins[1] < 0 && REG_P (in_rtx) |
0af99ebf | 1016 | && (int) REGNO (in_rtx) < lra_new_regno_start |
1017 | && find_regno_note (curr_insn, REG_DEAD, REGNO (in_rtx)) | |
099c19e2 | 1018 | && (! early_clobber_p |
1019 | || check_conflict_input_operands (REGNO (in_rtx), ins)) | |
f64b137f | 1020 | && (out < 0 |
1021 | || regno_val_use_in (REGNO (in_rtx), out_rtx) == NULL_RTX) | |
dd083a02 | 1022 | && !out_conflict |
0af99ebf | 1023 | ? lra_create_new_reg (inmode, in_rtx, goal_class, "") |
1024 | : lra_create_new_reg_with_unique_value (outmode, out_rtx, | |
1025 | goal_class, "")); | |
c6a6cdaa | 1026 | } |
aa3ce8ba | 1027 | /* In operand can be got from transformations before processing insn |
1028 | constraints. One example of such transformations is subreg | |
1029 | reloading (see function simplify_operand_subreg). The new | |
1030 | pseudos created by the transformations might have inaccurate | |
c6a6cdaa | 1031 | class (ALL_REGS) and we should make their classes more |
1032 | accurate. */ | |
1033 | narrow_reload_pseudo_class (in_rtx, goal_class); | |
c6a6cdaa | 1034 | lra_emit_move (copy_rtx (new_in_reg), in_rtx); |
1035 | *before = get_insns (); | |
1036 | end_sequence (); | |
bd13359a | 1037 | /* Add the new pseudo to consider values of subsequent input reload |
1038 | pseudos. */ | |
1039 | lra_assert (curr_insn_input_reloads_num < LRA_MAX_INSN_RELOADS); | |
1040 | curr_insn_input_reloads[curr_insn_input_reloads_num].input = in_rtx; | |
1041 | curr_insn_input_reloads[curr_insn_input_reloads_num].match_p = true; | |
1042 | curr_insn_input_reloads[curr_insn_input_reloads_num++].reg = new_in_reg; | |
c6a6cdaa | 1043 | for (i = 0; (in = ins[i]) >= 0; i++) |
1044 | { | |
1045 | lra_assert | |
1046 | (GET_MODE (*curr_id->operand_loc[in]) == VOIDmode | |
1047 | || GET_MODE (new_in_reg) == GET_MODE (*curr_id->operand_loc[in])); | |
1048 | *curr_id->operand_loc[in] = new_in_reg; | |
1049 | } | |
1050 | lra_update_dups (curr_id, ins); | |
aa3ce8ba | 1051 | if (out < 0) |
1052 | return; | |
1053 | /* See a comment for the input operand above. */ | |
1054 | narrow_reload_pseudo_class (out_rtx, goal_class); | |
c6a6cdaa | 1055 | if (find_reg_note (curr_insn, REG_UNUSED, out_rtx) == NULL_RTX) |
1056 | { | |
1057 | start_sequence (); | |
1058 | lra_emit_move (out_rtx, copy_rtx (new_out_reg)); | |
1059 | emit_insn (*after); | |
1060 | *after = get_insns (); | |
1061 | end_sequence (); | |
1062 | } | |
1063 | *curr_id->operand_loc[out] = new_out_reg; | |
1064 | lra_update_dup (curr_id, out); | |
1065 | } | |
1066 | ||
1067 | /* Return register class which is union of all reg classes in insn | |
1068 | constraint alternative string starting with P. */ | |
1069 | static enum reg_class | |
1070 | reg_class_from_constraints (const char *p) | |
1071 | { | |
1072 | int c, len; | |
1073 | enum reg_class op_class = NO_REGS; | |
1074 | ||
1075 | do | |
1076 | switch ((c = *p, len = CONSTRAINT_LEN (c, p)), c) | |
1077 | { | |
1078 | case '#': | |
1079 | case ',': | |
1080 | return op_class; | |
1081 | ||
c6a6cdaa | 1082 | case 'g': |
c6a6cdaa | 1083 | op_class = reg_class_subunion[op_class][GENERAL_REGS]; |
1084 | break; | |
1a8f8886 | 1085 | |
c6a6cdaa | 1086 | default: |
79bc09fb | 1087 | enum constraint_num cn = lookup_constraint (p); |
1088 | enum reg_class cl = reg_class_for_constraint (cn); | |
1089 | if (cl == NO_REGS) | |
c6a6cdaa | 1090 | { |
79bc09fb | 1091 | if (insn_extra_address_constraint (cn)) |
c6a6cdaa | 1092 | op_class |
1093 | = (reg_class_subunion | |
1094 | [op_class][base_reg_class (VOIDmode, ADDR_SPACE_GENERIC, | |
1095 | ADDRESS, SCRATCH)]); | |
c6a6cdaa | 1096 | break; |
1097 | } | |
1a8f8886 | 1098 | |
79bc09fb | 1099 | op_class = reg_class_subunion[op_class][cl]; |
1100 | break; | |
c6a6cdaa | 1101 | } |
1102 | while ((p += len), c); | |
1103 | return op_class; | |
1104 | } | |
1105 | ||
1106 | /* If OP is a register, return the class of the register as per | |
1107 | get_reg_class, otherwise return NO_REGS. */ | |
1108 | static inline enum reg_class | |
1109 | get_op_class (rtx op) | |
1110 | { | |
1111 | return REG_P (op) ? get_reg_class (REGNO (op)) : NO_REGS; | |
1112 | } | |
1113 | ||
1114 | /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo | |
1115 | otherwise. If modes of MEM_PSEUDO and VAL are different, use | |
1116 | SUBREG for VAL to make them equal. */ | |
7f836b57 | 1117 | static rtx_insn * |
c6a6cdaa | 1118 | emit_spill_move (bool to_p, rtx mem_pseudo, rtx val) |
1119 | { | |
1120 | if (GET_MODE (mem_pseudo) != GET_MODE (val)) | |
ea99c7a1 | 1121 | { |
34575461 | 1122 | /* Usually size of mem_pseudo is greater than val size but in |
1123 | rare cases it can be less as it can be defined by target | |
1124 | dependent macro HARD_REGNO_CALLER_SAVE_MODE. */ | |
cc0dc61b | 1125 | if (! MEM_P (val)) |
1126 | { | |
05856efc | 1127 | val = gen_lowpart_SUBREG (GET_MODE (mem_pseudo), |
1128 | GET_CODE (val) == SUBREG | |
1129 | ? SUBREG_REG (val) : val); | |
cc0dc61b | 1130 | LRA_SUBREG_P (val) = 1; |
1131 | } | |
1132 | else | |
1133 | { | |
1134 | mem_pseudo = gen_lowpart_SUBREG (GET_MODE (val), mem_pseudo); | |
1135 | LRA_SUBREG_P (mem_pseudo) = 1; | |
1136 | } | |
ea99c7a1 | 1137 | } |
f9a00e9e | 1138 | return to_p ? gen_move_insn (mem_pseudo, val) |
1139 | : gen_move_insn (val, mem_pseudo); | |
c6a6cdaa | 1140 | } |
1141 | ||
1142 | /* Process a special case insn (register move), return true if we | |
ea99c7a1 | 1143 | don't need to process it anymore. INSN should be a single set |
c836e75b | 1144 | insn. Set up that RTL was changed through CHANGE_P and that hook |
1145 | TARGET_SECONDARY_MEMORY_NEEDED says to use secondary memory through | |
ea99c7a1 | 1146 | SEC_MEM_P. */ |
c6a6cdaa | 1147 | static bool |
ea99c7a1 | 1148 | check_and_process_move (bool *change_p, bool *sec_mem_p ATTRIBUTE_UNUSED) |
c6a6cdaa | 1149 | { |
1150 | int sregno, dregno; | |
28323099 | 1151 | rtx dest, src, dreg, sreg, new_reg, scratch_reg; |
7f836b57 | 1152 | rtx_insn *before; |
c6a6cdaa | 1153 | enum reg_class dclass, sclass, secondary_class; |
c6a6cdaa | 1154 | secondary_reload_info sri; |
1155 | ||
ea99c7a1 | 1156 | lra_assert (curr_insn_set != NULL_RTX); |
1157 | dreg = dest = SET_DEST (curr_insn_set); | |
1158 | sreg = src = SET_SRC (curr_insn_set); | |
c6a6cdaa | 1159 | if (GET_CODE (dest) == SUBREG) |
1160 | dreg = SUBREG_REG (dest); | |
1161 | if (GET_CODE (src) == SUBREG) | |
1162 | sreg = SUBREG_REG (src); | |
cc0dc61b | 1163 | if (! (REG_P (dreg) || MEM_P (dreg)) || ! (REG_P (sreg) || MEM_P (sreg))) |
c6a6cdaa | 1164 | return false; |
1165 | sclass = dclass = NO_REGS; | |
c6a6cdaa | 1166 | if (REG_P (dreg)) |
1167 | dclass = get_reg_class (REGNO (dreg)); | |
68e1f2b7 | 1168 | gcc_assert (dclass < LIM_REG_CLASSES); |
c6a6cdaa | 1169 | if (dclass == ALL_REGS) |
1170 | /* ALL_REGS is used for new pseudos created by transformations | |
1171 | like reload of SUBREG_REG (see function | |
1172 | simplify_operand_subreg). We don't know their class yet. We | |
1173 | should figure out the class from processing the insn | |
1174 | constraints not in this fast path function. Even if ALL_REGS | |
1175 | were a right class for the pseudo, secondary_... hooks usually | |
1176 | are not define for ALL_REGS. */ | |
1177 | return false; | |
c6a6cdaa | 1178 | if (REG_P (sreg)) |
1179 | sclass = get_reg_class (REGNO (sreg)); | |
68e1f2b7 | 1180 | gcc_assert (sclass < LIM_REG_CLASSES); |
c6a6cdaa | 1181 | if (sclass == ALL_REGS) |
1182 | /* See comments above. */ | |
1183 | return false; | |
cc0dc61b | 1184 | if (sclass == NO_REGS && dclass == NO_REGS) |
1185 | return false; | |
c836e75b | 1186 | if (targetm.secondary_memory_needed (GET_MODE (src), sclass, dclass) |
cc0dc61b | 1187 | && ((sclass != NO_REGS && dclass != NO_REGS) |
1041f930 | 1188 | || (GET_MODE (src) |
1189 | != targetm.secondary_memory_needed_mode (GET_MODE (src))))) | |
c6a6cdaa | 1190 | { |
1191 | *sec_mem_p = true; | |
1192 | return false; | |
1193 | } | |
cc0dc61b | 1194 | if (! REG_P (dreg) || ! REG_P (sreg)) |
1195 | return false; | |
c6a6cdaa | 1196 | sri.prev_sri = NULL; |
1197 | sri.icode = CODE_FOR_nothing; | |
1198 | sri.extra_cost = 0; | |
1199 | secondary_class = NO_REGS; | |
1200 | /* Set up hard register for a reload pseudo for hook | |
1201 | secondary_reload because some targets just ignore unassigned | |
1202 | pseudos in the hook. */ | |
1203 | if (dclass != NO_REGS && lra_get_regno_hard_regno (REGNO (dreg)) < 0) | |
1204 | { | |
1205 | dregno = REGNO (dreg); | |
1206 | reg_renumber[dregno] = ira_class_hard_regs[dclass][0]; | |
1207 | } | |
1208 | else | |
1209 | dregno = -1; | |
1210 | if (sclass != NO_REGS && lra_get_regno_hard_regno (REGNO (sreg)) < 0) | |
1211 | { | |
1212 | sregno = REGNO (sreg); | |
1213 | reg_renumber[sregno] = ira_class_hard_regs[sclass][0]; | |
1214 | } | |
1215 | else | |
1216 | sregno = -1; | |
1217 | if (sclass != NO_REGS) | |
1218 | secondary_class | |
1219 | = (enum reg_class) targetm.secondary_reload (false, dest, | |
1220 | (reg_class_t) sclass, | |
1221 | GET_MODE (src), &sri); | |
1222 | if (sclass == NO_REGS | |
1223 | || ((secondary_class != NO_REGS || sri.icode != CODE_FOR_nothing) | |
1224 | && dclass != NO_REGS)) | |
1225 | { | |
c6a6cdaa | 1226 | enum reg_class old_sclass = secondary_class; |
1227 | secondary_reload_info old_sri = sri; | |
c6a6cdaa | 1228 | |
1229 | sri.prev_sri = NULL; | |
1230 | sri.icode = CODE_FOR_nothing; | |
1231 | sri.extra_cost = 0; | |
1232 | secondary_class | |
28323099 | 1233 | = (enum reg_class) targetm.secondary_reload (true, src, |
c6a6cdaa | 1234 | (reg_class_t) dclass, |
28323099 | 1235 | GET_MODE (src), &sri); |
c6a6cdaa | 1236 | /* Check the target hook consistency. */ |
1237 | lra_assert | |
1238 | ((secondary_class == NO_REGS && sri.icode == CODE_FOR_nothing) | |
1239 | || (old_sclass == NO_REGS && old_sri.icode == CODE_FOR_nothing) | |
1240 | || (secondary_class == old_sclass && sri.icode == old_sri.icode)); | |
1241 | } | |
1242 | if (sregno >= 0) | |
1243 | reg_renumber [sregno] = -1; | |
1244 | if (dregno >= 0) | |
1245 | reg_renumber [dregno] = -1; | |
1246 | if (secondary_class == NO_REGS && sri.icode == CODE_FOR_nothing) | |
1247 | return false; | |
1248 | *change_p = true; | |
1249 | new_reg = NULL_RTX; | |
1250 | if (secondary_class != NO_REGS) | |
28323099 | 1251 | new_reg = lra_create_new_reg_with_unique_value (GET_MODE (src), NULL_RTX, |
c6a6cdaa | 1252 | secondary_class, |
1253 | "secondary"); | |
1254 | start_sequence (); | |
c6a6cdaa | 1255 | if (sri.icode == CODE_FOR_nothing) |
28323099 | 1256 | lra_emit_move (new_reg, src); |
c6a6cdaa | 1257 | else |
1258 | { | |
1259 | enum reg_class scratch_class; | |
1260 | ||
1261 | scratch_class = (reg_class_from_constraints | |
1262 | (insn_data[sri.icode].operand[2].constraint)); | |
1263 | scratch_reg = (lra_create_new_reg_with_unique_value | |
1264 | (insn_data[sri.icode].operand[2].mode, NULL_RTX, | |
1265 | scratch_class, "scratch")); | |
1266 | emit_insn (GEN_FCN (sri.icode) (new_reg != NULL_RTX ? new_reg : dest, | |
28323099 | 1267 | src, scratch_reg)); |
c6a6cdaa | 1268 | } |
1269 | before = get_insns (); | |
1270 | end_sequence (); | |
7f836b57 | 1271 | lra_process_new_insns (curr_insn, before, NULL, "Inserting the move"); |
c6a6cdaa | 1272 | if (new_reg != NULL_RTX) |
28323099 | 1273 | SET_SRC (curr_insn_set) = new_reg; |
c6a6cdaa | 1274 | else |
1275 | { | |
1276 | if (lra_dump_file != NULL) | |
1277 | { | |
1278 | fprintf (lra_dump_file, "Deleting move %u\n", INSN_UID (curr_insn)); | |
6dde9719 | 1279 | dump_insn_slim (lra_dump_file, curr_insn); |
c6a6cdaa | 1280 | } |
1281 | lra_set_insn_deleted (curr_insn); | |
1282 | return true; | |
1283 | } | |
1284 | return false; | |
1285 | } | |
1286 | ||
1287 | /* The following data describe the result of process_alt_operands. | |
1288 | The data are used in curr_insn_transform to generate reloads. */ | |
1289 | ||
1290 | /* The chosen reg classes which should be used for the corresponding | |
1291 | operands. */ | |
1292 | static enum reg_class goal_alt[MAX_RECOG_OPERANDS]; | |
1293 | /* True if the operand should be the same as another operand and that | |
1294 | other operand does not need a reload. */ | |
1295 | static bool goal_alt_match_win[MAX_RECOG_OPERANDS]; | |
1296 | /* True if the operand does not need a reload. */ | |
1297 | static bool goal_alt_win[MAX_RECOG_OPERANDS]; | |
1298 | /* True if the operand can be offsetable memory. */ | |
1299 | static bool goal_alt_offmemok[MAX_RECOG_OPERANDS]; | |
1300 | /* The number of an operand to which given operand can be matched to. */ | |
1301 | static int goal_alt_matches[MAX_RECOG_OPERANDS]; | |
1302 | /* The number of elements in the following array. */ | |
1303 | static int goal_alt_dont_inherit_ops_num; | |
1304 | /* Numbers of operands whose reload pseudos should not be inherited. */ | |
1305 | static int goal_alt_dont_inherit_ops[MAX_RECOG_OPERANDS]; | |
1306 | /* True if the insn commutative operands should be swapped. */ | |
1307 | static bool goal_alt_swapped; | |
1308 | /* The chosen insn alternative. */ | |
1309 | static int goal_alt_number; | |
1310 | ||
003000a4 | 1311 | /* True if the corresponding operand is the result of an equivalence |
1312 | substitution. */ | |
1313 | static bool equiv_substition_p[MAX_RECOG_OPERANDS]; | |
1314 | ||
c6a6cdaa | 1315 | /* The following five variables are used to choose the best insn |
1316 | alternative. They reflect final characteristics of the best | |
1317 | alternative. */ | |
1318 | ||
1319 | /* Number of necessary reloads and overall cost reflecting the | |
1320 | previous value and other unpleasantness of the best alternative. */ | |
1321 | static int best_losers, best_overall; | |
c6a6cdaa | 1322 | /* Overall number hard registers used for reloads. For example, on |
1323 | some targets we need 2 general registers to reload DFmode and only | |
1324 | one floating point register. */ | |
1325 | static int best_reload_nregs; | |
1326 | /* Overall number reflecting distances of previous reloading the same | |
1327 | value. The distances are counted from the current BB start. It is | |
1328 | used to improve inheritance chances. */ | |
1329 | static int best_reload_sum; | |
1330 | ||
1331 | /* True if the current insn should have no correspondingly input or | |
1332 | output reloads. */ | |
1333 | static bool no_input_reloads_p, no_output_reloads_p; | |
1334 | ||
1335 | /* True if we swapped the commutative operands in the current | |
1336 | insn. */ | |
1337 | static int curr_swapped; | |
1338 | ||
497ba60f | 1339 | /* if CHECK_ONLY_P is false, arrange for address element *LOC to be a |
1340 | register of class CL. Add any input reloads to list BEFORE. AFTER | |
1341 | is nonnull if *LOC is an automodified value; handle that case by | |
1342 | adding the required output reloads to list AFTER. Return true if | |
1343 | the RTL was changed. | |
1344 | ||
1345 | if CHECK_ONLY_P is true, check that the *LOC is a correct address | |
1346 | register. Return false if the address register is correct. */ | |
c6a6cdaa | 1347 | static bool |
497ba60f | 1348 | process_addr_reg (rtx *loc, bool check_only_p, rtx_insn **before, rtx_insn **after, |
7f836b57 | 1349 | enum reg_class cl) |
c6a6cdaa | 1350 | { |
1351 | int regno; | |
1352 | enum reg_class rclass, new_class; | |
1efe9e9d | 1353 | rtx reg; |
c6a6cdaa | 1354 | rtx new_reg; |
3754d046 | 1355 | machine_mode mode; |
6cadc8f7 | 1356 | bool subreg_p, before_p = false; |
c6a6cdaa | 1357 | |
6cadc8f7 | 1358 | subreg_p = GET_CODE (*loc) == SUBREG; |
1359 | if (subreg_p) | |
4fe01ba9 | 1360 | { |
1361 | reg = SUBREG_REG (*loc); | |
1362 | mode = GET_MODE (reg); | |
1363 | ||
1364 | /* For mode with size bigger than ptr_mode, there unlikely to be "mov" | |
1365 | between two registers with different classes, but there normally will | |
1366 | be "mov" which transfers element of vector register into the general | |
1367 | register, and this normally will be a subreg which should be reloaded | |
1368 | as a whole. This is particularly likely to be triggered when | |
1369 | -fno-split-wide-types specified. */ | |
2e9acae0 | 1370 | if (!REG_P (reg) |
1371 | || in_class_p (reg, cl, &new_class) | |
52acb7ae | 1372 | || known_le (GET_MODE_SIZE (mode), GET_MODE_SIZE (ptr_mode))) |
4fe01ba9 | 1373 | loc = &SUBREG_REG (*loc); |
1374 | } | |
1375 | ||
1efe9e9d | 1376 | reg = *loc; |
c6a6cdaa | 1377 | mode = GET_MODE (reg); |
1378 | if (! REG_P (reg)) | |
1379 | { | |
497ba60f | 1380 | if (check_only_p) |
1381 | return true; | |
c6a6cdaa | 1382 | /* Always reload memory in an address even if the target supports |
1383 | such addresses. */ | |
1384 | new_reg = lra_create_new_reg_with_unique_value (mode, reg, cl, "address"); | |
1385 | before_p = true; | |
1386 | } | |
1387 | else | |
1388 | { | |
1389 | regno = REGNO (reg); | |
1390 | rclass = get_reg_class (regno); | |
497ba60f | 1391 | if (! check_only_p |
1392 | && (*loc = get_equiv_with_elimination (reg, curr_insn)) != reg) | |
c6a6cdaa | 1393 | { |
1394 | if (lra_dump_file != NULL) | |
1395 | { | |
1396 | fprintf (lra_dump_file, | |
1397 | "Changing pseudo %d in address of insn %u on equiv ", | |
1398 | REGNO (reg), INSN_UID (curr_insn)); | |
6dde9719 | 1399 | dump_value_slim (lra_dump_file, *loc, 1); |
c6a6cdaa | 1400 | fprintf (lra_dump_file, "\n"); |
1401 | } | |
1402 | *loc = copy_rtx (*loc); | |
1403 | } | |
1404 | if (*loc != reg || ! in_class_p (reg, cl, &new_class)) | |
1405 | { | |
497ba60f | 1406 | if (check_only_p) |
1407 | return true; | |
c6a6cdaa | 1408 | reg = *loc; |
1409 | if (get_reload_reg (after == NULL ? OP_IN : OP_INOUT, | |
6cadc8f7 | 1410 | mode, reg, cl, subreg_p, "address", &new_reg)) |
c6a6cdaa | 1411 | before_p = true; |
1412 | } | |
1413 | else if (new_class != NO_REGS && rclass != new_class) | |
1414 | { | |
497ba60f | 1415 | if (check_only_p) |
1416 | return true; | |
7619e612 | 1417 | lra_change_class (regno, new_class, " Change to", true); |
c6a6cdaa | 1418 | return false; |
1419 | } | |
1420 | else | |
1421 | return false; | |
1422 | } | |
1423 | if (before_p) | |
1424 | { | |
1425 | push_to_sequence (*before); | |
1426 | lra_emit_move (new_reg, reg); | |
1427 | *before = get_insns (); | |
1428 | end_sequence (); | |
1429 | } | |
1430 | *loc = new_reg; | |
1431 | if (after != NULL) | |
1432 | { | |
1433 | start_sequence (); | |
c8f7cecf | 1434 | lra_emit_move (before_p ? copy_rtx (reg) : reg, new_reg); |
c6a6cdaa | 1435 | emit_insn (*after); |
1436 | *after = get_insns (); | |
1437 | end_sequence (); | |
1438 | } | |
1439 | return true; | |
1440 | } | |
1441 | ||
c5334148 | 1442 | /* Insert move insn in simplify_operand_subreg. BEFORE returns |
1443 | the insn to be inserted before curr insn. AFTER returns the | |
1444 | the insn to be inserted after curr insn. ORIGREG and NEWREG | |
1445 | are the original reg and new reg for reload. */ | |
1446 | static void | |
7f836b57 | 1447 | insert_move_for_subreg (rtx_insn **before, rtx_insn **after, rtx origreg, |
1448 | rtx newreg) | |
c5334148 | 1449 | { |
1450 | if (before) | |
1451 | { | |
1452 | push_to_sequence (*before); | |
1453 | lra_emit_move (newreg, origreg); | |
1454 | *before = get_insns (); | |
1455 | end_sequence (); | |
1456 | } | |
1457 | if (after) | |
1458 | { | |
1459 | start_sequence (); | |
1460 | lra_emit_move (origreg, newreg); | |
1461 | emit_insn (*after); | |
1462 | *after = get_insns (); | |
1463 | end_sequence (); | |
1464 | } | |
1465 | } | |
1466 | ||
3754d046 | 1467 | static int valid_address_p (machine_mode mode, rtx addr, addr_space_t as); |
856bd6f2 | 1468 | static bool process_address (int, bool, rtx_insn **, rtx_insn **); |
1a68e833 | 1469 | |
c6a6cdaa | 1470 | /* Make reloads for subreg in operand NOP with internal subreg mode |
1471 | REG_MODE, add new reloads for further processing. Return true if | |
1aae95ec | 1472 | any change was done. */ |
c6a6cdaa | 1473 | static bool |
3754d046 | 1474 | simplify_operand_subreg (int nop, machine_mode reg_mode) |
c6a6cdaa | 1475 | { |
1476 | int hard_regno; | |
7f836b57 | 1477 | rtx_insn *before, *after; |
1aae95ec | 1478 | machine_mode mode, innermode; |
c6a6cdaa | 1479 | rtx reg, new_reg; |
1480 | rtx operand = *curr_id->operand_loc[nop]; | |
c5334148 | 1481 | enum reg_class regclass; |
1482 | enum op_type type; | |
c6a6cdaa | 1483 | |
7f836b57 | 1484 | before = after = NULL; |
c6a6cdaa | 1485 | |
1486 | if (GET_CODE (operand) != SUBREG) | |
1487 | return false; | |
1a8f8886 | 1488 | |
c6a6cdaa | 1489 | mode = GET_MODE (operand); |
1490 | reg = SUBREG_REG (operand); | |
1aae95ec | 1491 | innermode = GET_MODE (reg); |
c5334148 | 1492 | type = curr_static_id->operand[nop].type; |
2d2b78a1 | 1493 | if (MEM_P (reg)) |
1a68e833 | 1494 | { |
856bd6f2 | 1495 | const bool addr_was_valid |
1496 | = valid_address_p (innermode, XEXP (reg, 0), MEM_ADDR_SPACE (reg)); | |
1a68e833 | 1497 | alter_subreg (curr_id->operand_loc[nop], false); |
856bd6f2 | 1498 | rtx subst = *curr_id->operand_loc[nop]; |
1a68e833 | 1499 | lra_assert (MEM_P (subst)); |
3143c7ef | 1500 | const bool addr_is_valid = valid_address_p (GET_MODE (subst), |
1501 | XEXP (subst, 0), | |
1502 | MEM_ADDR_SPACE (subst)); | |
856bd6f2 | 1503 | if (!addr_was_valid |
3143c7ef | 1504 | || addr_is_valid |
2d2b78a1 | 1505 | || ((get_constraint_type (lookup_constraint |
1506 | (curr_static_id->operand[nop].constraint)) | |
1507 | != CT_SPECIAL_MEMORY) | |
1508 | /* We still can reload address and if the address is | |
1509 | valid, we can remove subreg without reloading its | |
1510 | inner memory. */ | |
1511 | && valid_address_p (GET_MODE (subst), | |
1512 | regno_reg_rtx | |
1513 | [ira_class_hard_regs | |
1514 | [base_reg_class (GET_MODE (subst), | |
1515 | MEM_ADDR_SPACE (subst), | |
1516 | ADDRESS, SCRATCH)][0]], | |
1517 | MEM_ADDR_SPACE (subst)))) | |
1518 | { | |
856bd6f2 | 1519 | /* If we change the address for a paradoxical subreg of memory, the |
b0f26d5e | 1520 | new address might violate the necessary alignment or the access |
1521 | might be slow; take this into consideration. We need not worry | |
856bd6f2 | 1522 | about accesses beyond allocated memory for paradoxical memory |
2d2b78a1 | 1523 | subregs as we don't substitute such equiv memory (see processing |
1524 | equivalences in function lra_constraints) and because for spilled | |
1525 | pseudos we allocate stack memory enough for the biggest | |
8d7a5013 | 1526 | corresponding paradoxical subreg. |
1527 | ||
1528 | However, do not blindly simplify a (subreg (mem ...)) for | |
1529 | WORD_REGISTER_OPERATIONS targets as this may lead to loading junk | |
1530 | data into a register when the inner is narrower than outer or | |
1531 | missing important data from memory when the inner is wider than | |
1532 | outer. This rule only applies to modes that are no wider than | |
3143c7ef | 1533 | a word. |
1534 | ||
1535 | If valid memory becomes invalid after subreg elimination | |
c2041c0a | 1536 | and address might be different we still have to reload |
1537 | memory. | |
3143c7ef | 1538 | */ |
c2041c0a | 1539 | if ((! addr_was_valid |
1540 | || addr_is_valid | |
1541 | || known_eq (GET_MODE_SIZE (mode), GET_MODE_SIZE (innermode))) | |
3143c7ef | 1542 | && !(maybe_ne (GET_MODE_PRECISION (mode), |
1543 | GET_MODE_PRECISION (innermode)) | |
1544 | && known_le (GET_MODE_SIZE (mode), UNITS_PER_WORD) | |
1545 | && known_le (GET_MODE_SIZE (innermode), UNITS_PER_WORD) | |
1546 | && WORD_REGISTER_OPERATIONS) | |
8d7a5013 | 1547 | && (!(MEM_ALIGN (subst) < GET_MODE_ALIGNMENT (mode) |
dfdced85 | 1548 | && targetm.slow_unaligned_access (mode, MEM_ALIGN (subst))) |
8d7a5013 | 1549 | || (MEM_ALIGN (reg) < GET_MODE_ALIGNMENT (innermode) |
dfdced85 | 1550 | && targetm.slow_unaligned_access (innermode, |
1551 | MEM_ALIGN (reg))))) | |
2d2b78a1 | 1552 | return true; |
1553 | ||
856bd6f2 | 1554 | *curr_id->operand_loc[nop] = operand; |
1555 | ||
1556 | /* But if the address was not valid, we cannot reload the MEM without | |
1557 | reloading the address first. */ | |
1558 | if (!addr_was_valid) | |
1559 | process_address (nop, false, &before, &after); | |
1560 | ||
2d2b78a1 | 1561 | /* INNERMODE is fast, MODE slow. Reload the mem in INNERMODE. */ |
1562 | enum reg_class rclass | |
1563 | = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS); | |
856bd6f2 | 1564 | if (get_reload_reg (curr_static_id->operand[nop].type, innermode, |
3143c7ef | 1565 | reg, rclass, TRUE, "slow/invalid mem", &new_reg)) |
2d2b78a1 | 1566 | { |
1567 | bool insert_before, insert_after; | |
1568 | bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg)); | |
1569 | ||
1570 | insert_before = (type != OP_OUT | |
974534ab | 1571 | || partial_subreg_p (mode, innermode)); |
2d2b78a1 | 1572 | insert_after = type != OP_IN; |
1573 | insert_move_for_subreg (insert_before ? &before : NULL, | |
1574 | insert_after ? &after : NULL, | |
1575 | reg, new_reg); | |
1576 | } | |
2d2b78a1 | 1577 | SUBREG_REG (operand) = new_reg; |
1578 | ||
1579 | /* Convert to MODE. */ | |
1580 | reg = operand; | |
856bd6f2 | 1581 | rclass |
1582 | = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS); | |
2d2b78a1 | 1583 | if (get_reload_reg (curr_static_id->operand[nop].type, mode, reg, |
3143c7ef | 1584 | rclass, TRUE, "slow/invalid mem", &new_reg)) |
2d2b78a1 | 1585 | { |
1586 | bool insert_before, insert_after; | |
1587 | bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg)); | |
1588 | ||
1589 | insert_before = type != OP_OUT; | |
1590 | insert_after = type != OP_IN; | |
1591 | insert_move_for_subreg (insert_before ? &before : NULL, | |
1592 | insert_after ? &after : NULL, | |
1593 | reg, new_reg); | |
1594 | } | |
1595 | *curr_id->operand_loc[nop] = new_reg; | |
1596 | lra_process_new_insns (curr_insn, before, after, | |
3143c7ef | 1597 | "Inserting slow/invalid mem reload"); |
2d2b78a1 | 1598 | return true; |
1599 | } | |
401bd0c8 | 1600 | |
1a68e833 | 1601 | /* If the address was valid and became invalid, prefer to reload |
1602 | the memory. Typical case is when the index scale should | |
1603 | correspond the memory. */ | |
2d2b78a1 | 1604 | *curr_id->operand_loc[nop] = operand; |
483f7b77 | 1605 | /* Do not return false here as the MEM_P (reg) will be processed |
1606 | later in this function. */ | |
1a68e833 | 1607 | } |
1608 | else if (REG_P (reg) && REGNO (reg) < FIRST_PSEUDO_REGISTER) | |
c6a6cdaa | 1609 | { |
1610 | alter_subreg (curr_id->operand_loc[nop], false); | |
1611 | return true; | |
1612 | } | |
1aae95ec | 1613 | else if (CONSTANT_P (reg)) |
1614 | { | |
1615 | /* Try to simplify subreg of constant. It is usually result of | |
1616 | equivalence substitution. */ | |
1617 | if (innermode == VOIDmode | |
1618 | && (innermode = original_subreg_reg_mode[nop]) == VOIDmode) | |
1619 | innermode = curr_static_id->operand[nop].mode; | |
1620 | if ((new_reg = simplify_subreg (mode, reg, innermode, | |
1621 | SUBREG_BYTE (operand))) != NULL_RTX) | |
1622 | { | |
1623 | *curr_id->operand_loc[nop] = new_reg; | |
1624 | return true; | |
1625 | } | |
1626 | } | |
c6a6cdaa | 1627 | /* Put constant into memory when we have mixed modes. It generates |
1628 | a better code in most cases as it does not need a secondary | |
1629 | reload memory. It also prevents LRA looping when LRA is using | |
1630 | secondary reload memory again and again. */ | |
1631 | if (CONSTANT_P (reg) && CONST_POOL_OK_P (reg_mode, reg) | |
1632 | && SCALAR_INT_MODE_P (reg_mode) != SCALAR_INT_MODE_P (mode)) | |
1633 | { | |
1634 | SUBREG_REG (operand) = force_const_mem (reg_mode, reg); | |
1635 | alter_subreg (curr_id->operand_loc[nop], false); | |
1636 | return true; | |
1637 | } | |
1638 | /* Force a reload of the SUBREG_REG if this is a constant or PLUS or | |
1639 | if there may be a problem accessing OPERAND in the outer | |
1640 | mode. */ | |
1641 | if ((REG_P (reg) | |
1642 | && REGNO (reg) >= FIRST_PSEUDO_REGISTER | |
1643 | && (hard_regno = lra_get_regno_hard_regno (REGNO (reg))) >= 0 | |
1644 | /* Don't reload paradoxical subregs because we could be looping | |
1645 | having repeatedly final regno out of hard regs range. */ | |
92d2aec3 | 1646 | && (hard_regno_nregs (hard_regno, innermode) |
1647 | >= hard_regno_nregs (hard_regno, mode)) | |
1aae95ec | 1648 | && simplify_subreg_regno (hard_regno, innermode, |
ea99c7a1 | 1649 | SUBREG_BYTE (operand), mode) < 0 |
1650 | /* Don't reload subreg for matching reload. It is actually | |
1651 | valid subreg in LRA. */ | |
1652 | && ! LRA_SUBREG_P (operand)) | |
c6a6cdaa | 1653 | || CONSTANT_P (reg) || GET_CODE (reg) == PLUS || MEM_P (reg)) |
1654 | { | |
9c8190ea | 1655 | enum reg_class rclass; |
1656 | ||
6ba9136f | 1657 | if (REG_P (reg)) |
1658 | /* There is a big probability that we will get the same class | |
9c8190ea | 1659 | for the new pseudo and we will get the same insn which |
1660 | means infinite looping. So spill the new pseudo. */ | |
1661 | rclass = NO_REGS; | |
1662 | else | |
1663 | /* The class will be defined later in curr_insn_transform. */ | |
1664 | rclass | |
1665 | = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS); | |
c6a6cdaa | 1666 | |
4aa54340 | 1667 | if (get_reload_reg (curr_static_id->operand[nop].type, reg_mode, reg, |
6cadc8f7 | 1668 | rclass, TRUE, "subreg reg", &new_reg)) |
c6a6cdaa | 1669 | { |
c5334148 | 1670 | bool insert_before, insert_after; |
1f3a048a | 1671 | bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg)); |
c5334148 | 1672 | |
1673 | insert_before = (type != OP_OUT | |
9f2c0e68 | 1674 | || read_modify_subreg_p (operand)); |
c5334148 | 1675 | insert_after = (type != OP_IN); |
1676 | insert_move_for_subreg (insert_before ? &before : NULL, | |
1677 | insert_after ? &after : NULL, | |
1678 | reg, new_reg); | |
c6a6cdaa | 1679 | } |
1680 | SUBREG_REG (operand) = new_reg; | |
1681 | lra_process_new_insns (curr_insn, before, after, | |
1682 | "Inserting subreg reload"); | |
1683 | return true; | |
1684 | } | |
c5334148 | 1685 | /* Force a reload for a paradoxical subreg. For paradoxical subreg, |
1686 | IRA allocates hardreg to the inner pseudo reg according to its mode | |
1687 | instead of the outermode, so the size of the hardreg may not be enough | |
1688 | to contain the outermode operand, in that case we may need to insert | |
1689 | reload for the reg. For the following two types of paradoxical subreg, | |
1690 | we need to insert reload: | |
1691 | 1. If the op_type is OP_IN, and the hardreg could not be paired with | |
1692 | other hardreg to contain the outermode operand | |
1693 | (checked by in_hard_reg_set_p), we need to insert the reload. | |
1694 | 2. If the op_type is OP_OUT or OP_INOUT. | |
1695 | ||
1696 | Here is a paradoxical subreg example showing how the reload is generated: | |
1697 | ||
1698 | (insn 5 4 7 2 (set (reg:TI 106 [ __comp ]) | |
1699 | (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64} | |
1700 | ||
1701 | In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example | |
1702 | here, if reg107 is assigned to hardreg R15, because R15 is the last | |
1703 | hardreg, compiler cannot find another hardreg to pair with R15 to | |
1704 | contain TImode data. So we insert a TImode reload reg180 for it. | |
1705 | After reload is inserted: | |
1706 | ||
1707 | (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0) | |
1708 | (reg:DI 107 [ __comp ])) -1 | |
1709 | (insn 5 4 7 2 (set (reg:TI 106 [ __comp ]) | |
1710 | (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64} | |
1711 | ||
1712 | Two reload hard registers will be allocated to reg180 to save TImode data | |
4b6df2e8 | 1713 | in LRA_assign. |
1714 | ||
1715 | For LRA pseudos this should normally be handled by the biggest_mode | |
1716 | mechanism. However, it's possible for new uses of an LRA pseudo | |
1717 | to be introduced after we've allocated it, such as when undoing | |
1718 | inheritance, and the allocated register might not then be appropriate | |
1719 | for the new uses. */ | |
c5334148 | 1720 | else if (REG_P (reg) |
1721 | && REGNO (reg) >= FIRST_PSEUDO_REGISTER | |
1722 | && (hard_regno = lra_get_regno_hard_regno (REGNO (reg))) >= 0 | |
92d2aec3 | 1723 | && (hard_regno_nregs (hard_regno, innermode) |
1724 | < hard_regno_nregs (hard_regno, mode)) | |
c5334148 | 1725 | && (regclass = lra_get_allocno_class (REGNO (reg))) |
1726 | && (type != OP_IN | |
1727 | || !in_hard_reg_set_p (reg_class_contents[regclass], | |
4b6df2e8 | 1728 | mode, hard_regno) |
1729 | || overlaps_hard_reg_set_p (lra_no_alloc_regs, | |
1730 | mode, hard_regno))) | |
c5334148 | 1731 | { |
1732 | /* The class will be defined later in curr_insn_transform. */ | |
1733 | enum reg_class rclass | |
1734 | = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS); | |
1735 | ||
1736 | if (get_reload_reg (curr_static_id->operand[nop].type, mode, reg, | |
6cadc8f7 | 1737 | rclass, TRUE, "paradoxical subreg", &new_reg)) |
c5334148 | 1738 | { |
1739 | rtx subreg; | |
1740 | bool insert_before, insert_after; | |
1741 | ||
1742 | PUT_MODE (new_reg, mode); | |
48a08d24 | 1743 | subreg = gen_lowpart_SUBREG (innermode, new_reg); |
c5334148 | 1744 | bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg)); |
1745 | ||
1746 | insert_before = (type != OP_OUT); | |
1747 | insert_after = (type != OP_IN); | |
1748 | insert_move_for_subreg (insert_before ? &before : NULL, | |
1749 | insert_after ? &after : NULL, | |
1750 | reg, subreg); | |
1751 | } | |
1752 | SUBREG_REG (operand) = new_reg; | |
1753 | lra_process_new_insns (curr_insn, before, after, | |
1754 | "Inserting paradoxical subreg reload"); | |
1755 | return true; | |
1756 | } | |
c6a6cdaa | 1757 | return false; |
1758 | } | |
1759 | ||
1760 | /* Return TRUE if X refers for a hard register from SET. */ | |
1761 | static bool | |
1762 | uses_hard_regs_p (rtx x, HARD_REG_SET set) | |
1763 | { | |
1764 | int i, j, x_hard_regno; | |
3754d046 | 1765 | machine_mode mode; |
c6a6cdaa | 1766 | const char *fmt; |
1767 | enum rtx_code code; | |
1768 | ||
1769 | if (x == NULL_RTX) | |
1770 | return false; | |
1771 | code = GET_CODE (x); | |
1772 | mode = GET_MODE (x); | |
3a7d0e9f | 1773 | |
c6a6cdaa | 1774 | if (code == SUBREG) |
1775 | { | |
3a7d0e9f | 1776 | /* For all SUBREGs we want to check whether the full multi-register |
1777 | overlaps the set. For normal SUBREGs this means 'get_hard_regno' of | |
1778 | the inner register, for paradoxical SUBREGs this means the | |
1779 | 'get_hard_regno' of the full SUBREG and for complete SUBREGs either is | |
1780 | fine. Use the wider mode for all cases. */ | |
1781 | rtx subreg = SUBREG_REG (x); | |
081c1d32 | 1782 | mode = wider_subreg_mode (x); |
3a7d0e9f | 1783 | if (mode == GET_MODE (subreg)) |
1784 | { | |
1785 | x = subreg; | |
1786 | code = GET_CODE (x); | |
1787 | } | |
c6a6cdaa | 1788 | } |
1a8f8886 | 1789 | |
3a7d0e9f | 1790 | if (REG_P (x) || SUBREG_P (x)) |
c6a6cdaa | 1791 | { |
331a9ecc | 1792 | x_hard_regno = get_hard_regno (x, true); |
c6a6cdaa | 1793 | return (x_hard_regno >= 0 |
1794 | && overlaps_hard_reg_set_p (set, mode, x_hard_regno)); | |
1795 | } | |
1796 | if (MEM_P (x)) | |
1797 | { | |
1efe9e9d | 1798 | struct address_info ad; |
c6a6cdaa | 1799 | |
1efe9e9d | 1800 | decompose_mem_address (&ad, x); |
1801 | if (ad.base_term != NULL && uses_hard_regs_p (*ad.base_term, set)) | |
1802 | return true; | |
1803 | if (ad.index_term != NULL && uses_hard_regs_p (*ad.index_term, set)) | |
1804 | return true; | |
c6a6cdaa | 1805 | } |
1806 | fmt = GET_RTX_FORMAT (code); | |
1807 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1808 | { | |
1809 | if (fmt[i] == 'e') | |
1810 | { | |
1811 | if (uses_hard_regs_p (XEXP (x, i), set)) | |
1812 | return true; | |
1813 | } | |
1814 | else if (fmt[i] == 'E') | |
1815 | { | |
1816 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
1817 | if (uses_hard_regs_p (XVECEXP (x, i, j), set)) | |
1818 | return true; | |
1819 | } | |
1820 | } | |
1821 | return false; | |
1822 | } | |
1823 | ||
1824 | /* Return true if OP is a spilled pseudo. */ | |
1825 | static inline bool | |
1826 | spilled_pseudo_p (rtx op) | |
1827 | { | |
1828 | return (REG_P (op) | |
1829 | && REGNO (op) >= FIRST_PSEUDO_REGISTER && in_mem_p (REGNO (op))); | |
1830 | } | |
1831 | ||
1832 | /* Return true if X is a general constant. */ | |
1833 | static inline bool | |
1834 | general_constant_p (rtx x) | |
1835 | { | |
1836 | return CONSTANT_P (x) && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (x)); | |
1837 | } | |
1838 | ||
ea99c7a1 | 1839 | static bool |
1840 | reg_in_class_p (rtx reg, enum reg_class cl) | |
1841 | { | |
1842 | if (cl == NO_REGS) | |
1843 | return get_reg_class (REGNO (reg)) == NO_REGS; | |
1844 | return in_class_p (reg, cl, NULL); | |
1845 | } | |
1846 | ||
25cd984c | 1847 | /* Return true if SET of RCLASS contains no hard regs which can be |
1848 | used in MODE. */ | |
1849 | static bool | |
1850 | prohibited_class_reg_set_mode_p (enum reg_class rclass, | |
1851 | HARD_REG_SET &set, | |
582adad1 | 1852 | machine_mode mode) |
25cd984c | 1853 | { |
1854 | HARD_REG_SET temp; | |
1855 | ||
e6ea917c | 1856 | lra_assert (hard_reg_set_subset_p (reg_class_contents[rclass], set)); |
25cd984c | 1857 | COPY_HARD_REG_SET (temp, set); |
1858 | AND_COMPL_HARD_REG_SET (temp, lra_no_alloc_regs); | |
1859 | return (hard_reg_set_subset_p | |
1860 | (temp, ira_prohibited_class_mode_regs[rclass][mode])); | |
1861 | } | |
1862 | ||
8afaf3bf | 1863 | |
1864 | /* Used to check validity info about small class input operands. It | |
1865 | should be incremented at start of processing an insn | |
1866 | alternative. */ | |
1867 | static unsigned int curr_small_class_check = 0; | |
1868 | ||
8df3e7a5 | 1869 | /* Update number of used inputs of class OP_CLASS for operand NOP |
1870 | of alternative NALT. Return true if we have more such class operands | |
1871 | than the number of available regs. */ | |
8afaf3bf | 1872 | static bool |
8df3e7a5 | 1873 | update_and_check_small_class_inputs (int nop, int nalt, |
1874 | enum reg_class op_class) | |
8afaf3bf | 1875 | { |
1876 | static unsigned int small_class_check[LIM_REG_CLASSES]; | |
1877 | static int small_class_input_nums[LIM_REG_CLASSES]; | |
1878 | ||
1879 | if (SMALL_REGISTER_CLASS_P (op_class) | |
1880 | /* We are interesting in classes became small because of fixing | |
1881 | some hard regs, e.g. by an user through GCC options. */ | |
1882 | && hard_reg_set_intersect_p (reg_class_contents[op_class], | |
1883 | ira_no_alloc_regs) | |
1884 | && (curr_static_id->operand[nop].type != OP_OUT | |
8df3e7a5 | 1885 | || TEST_BIT (curr_static_id->operand[nop].early_clobber_alts, nalt))) |
8afaf3bf | 1886 | { |
1887 | if (small_class_check[op_class] == curr_small_class_check) | |
1888 | small_class_input_nums[op_class]++; | |
1889 | else | |
1890 | { | |
1891 | small_class_check[op_class] = curr_small_class_check; | |
1892 | small_class_input_nums[op_class] = 1; | |
1893 | } | |
1894 | if (small_class_input_nums[op_class] > ira_class_hard_regs_num[op_class]) | |
1895 | return true; | |
1896 | } | |
1897 | return false; | |
1898 | } | |
1899 | ||
c6a6cdaa | 1900 | /* Major function to choose the current insn alternative and what |
1901 | operands should be reloaded and how. If ONLY_ALTERNATIVE is not | |
1902 | negative we should consider only this alternative. Return false if | |
f4d3c071 | 1903 | we cannot choose the alternative or find how to reload the |
c6a6cdaa | 1904 | operands. */ |
1905 | static bool | |
1906 | process_alt_operands (int only_alternative) | |
1907 | { | |
1908 | bool ok_p = false; | |
273c330a | 1909 | int nop, overall, nalt; |
c6a6cdaa | 1910 | int n_alternatives = curr_static_id->n_alternatives; |
1911 | int n_operands = curr_static_id->n_operands; | |
1912 | /* LOSERS counts the operands that don't fit this alternative and | |
1913 | would require loading. */ | |
1914 | int losers; | |
eb70a065 | 1915 | int addr_losers; |
c6a6cdaa | 1916 | /* REJECT is a count of how undesirable this alternative says it is |
1917 | if any reloading is required. If the alternative matches exactly | |
1918 | then REJECT is ignored, but otherwise it gets this much counted | |
1919 | against it in addition to the reloading needed. */ | |
1920 | int reject; | |
eb70a065 | 1921 | /* This is defined by '!' or '?' alternative constraint and added to |
1922 | reject. But in some cases it can be ignored. */ | |
1923 | int static_reject; | |
ed6272f7 | 1924 | int op_reject; |
c6a6cdaa | 1925 | /* The number of elements in the following array. */ |
1926 | int early_clobbered_regs_num; | |
1927 | /* Numbers of operands which are early clobber registers. */ | |
1928 | int early_clobbered_nops[MAX_RECOG_OPERANDS]; | |
1929 | enum reg_class curr_alt[MAX_RECOG_OPERANDS]; | |
1930 | HARD_REG_SET curr_alt_set[MAX_RECOG_OPERANDS]; | |
1931 | bool curr_alt_match_win[MAX_RECOG_OPERANDS]; | |
1932 | bool curr_alt_win[MAX_RECOG_OPERANDS]; | |
1933 | bool curr_alt_offmemok[MAX_RECOG_OPERANDS]; | |
1934 | int curr_alt_matches[MAX_RECOG_OPERANDS]; | |
1935 | /* The number of elements in the following array. */ | |
1936 | int curr_alt_dont_inherit_ops_num; | |
1937 | /* Numbers of operands whose reload pseudos should not be inherited. */ | |
1938 | int curr_alt_dont_inherit_ops[MAX_RECOG_OPERANDS]; | |
1939 | rtx op; | |
1940 | /* The register when the operand is a subreg of register, otherwise the | |
1941 | operand itself. */ | |
1942 | rtx no_subreg_reg_operand[MAX_RECOG_OPERANDS]; | |
1943 | /* The register if the operand is a register or subreg of register, | |
1944 | otherwise NULL. */ | |
1945 | rtx operand_reg[MAX_RECOG_OPERANDS]; | |
1946 | int hard_regno[MAX_RECOG_OPERANDS]; | |
3754d046 | 1947 | machine_mode biggest_mode[MAX_RECOG_OPERANDS]; |
c6a6cdaa | 1948 | int reload_nregs, reload_sum; |
1949 | bool costly_p; | |
1950 | enum reg_class cl; | |
1951 | ||
1952 | /* Calculate some data common for all alternatives to speed up the | |
1953 | function. */ | |
1954 | for (nop = 0; nop < n_operands; nop++) | |
1955 | { | |
0244be31 | 1956 | rtx reg; |
1957 | ||
c6a6cdaa | 1958 | op = no_subreg_reg_operand[nop] = *curr_id->operand_loc[nop]; |
1959 | /* The real hard regno of the operand after the allocation. */ | |
331a9ecc | 1960 | hard_regno[nop] = get_hard_regno (op, true); |
1a8f8886 | 1961 | |
0244be31 | 1962 | operand_reg[nop] = reg = op; |
1963 | biggest_mode[nop] = GET_MODE (op); | |
1964 | if (GET_CODE (op) == SUBREG) | |
c6a6cdaa | 1965 | { |
081c1d32 | 1966 | biggest_mode[nop] = wider_subreg_mode (op); |
0244be31 | 1967 | operand_reg[nop] = reg = SUBREG_REG (op); |
c6a6cdaa | 1968 | } |
0244be31 | 1969 | if (! REG_P (reg)) |
c6a6cdaa | 1970 | operand_reg[nop] = NULL_RTX; |
0244be31 | 1971 | else if (REGNO (reg) >= FIRST_PSEUDO_REGISTER |
1972 | || ((int) REGNO (reg) | |
1973 | == lra_get_elimination_hard_regno (REGNO (reg)))) | |
1974 | no_subreg_reg_operand[nop] = reg; | |
1975 | else | |
1976 | operand_reg[nop] = no_subreg_reg_operand[nop] | |
1977 | /* Just use natural mode for elimination result. It should | |
1978 | be enough for extra constraints hooks. */ | |
1979 | = regno_reg_rtx[hard_regno[nop]]; | |
c6a6cdaa | 1980 | } |
1981 | ||
1982 | /* The constraints are made of several alternatives. Each operand's | |
1983 | constraint looks like foo,bar,... with commas separating the | |
1984 | alternatives. The first alternatives for all operands go | |
1985 | together, the second alternatives go together, etc. | |
1986 | ||
1987 | First loop over alternatives. */ | |
e1a797ad | 1988 | alternative_mask preferred = curr_id->preferred_alternatives; |
d2b854bc | 1989 | if (only_alternative >= 0) |
e1a797ad | 1990 | preferred &= ALTERNATIVE_BIT (only_alternative); |
d2b854bc | 1991 | |
c6a6cdaa | 1992 | for (nalt = 0; nalt < n_alternatives; nalt++) |
1993 | { | |
1994 | /* Loop over operands for one constraint alternative. */ | |
e1a797ad | 1995 | if (!TEST_BIT (preferred, nalt)) |
c6a6cdaa | 1996 | continue; |
1997 | ||
3dfcf76a | 1998 | bool matching_early_clobber[MAX_RECOG_OPERANDS]; |
8afaf3bf | 1999 | curr_small_class_check++; |
eb70a065 | 2000 | overall = losers = addr_losers = 0; |
2001 | static_reject = reject = reload_nregs = reload_sum = 0; | |
c6a6cdaa | 2002 | for (nop = 0; nop < n_operands; nop++) |
34575461 | 2003 | { |
2004 | int inc = (curr_static_id | |
2005 | ->operand_alternative[nalt * n_operands + nop].reject); | |
2006 | if (lra_dump_file != NULL && inc != 0) | |
2007 | fprintf (lra_dump_file, | |
2008 | " Staticly defined alt reject+=%d\n", inc); | |
eb70a065 | 2009 | static_reject += inc; |
3dfcf76a | 2010 | matching_early_clobber[nop] = 0; |
34575461 | 2011 | } |
eb70a065 | 2012 | reject += static_reject; |
c6a6cdaa | 2013 | early_clobbered_regs_num = 0; |
2014 | ||
2015 | for (nop = 0; nop < n_operands; nop++) | |
2016 | { | |
2017 | const char *p; | |
2018 | char *end; | |
2019 | int len, c, m, i, opalt_num, this_alternative_matches; | |
2020 | bool win, did_match, offmemok, early_clobber_p; | |
2021 | /* false => this operand can be reloaded somehow for this | |
2022 | alternative. */ | |
2023 | bool badop; | |
2024 | /* true => this operand can be reloaded if the alternative | |
2025 | allows regs. */ | |
2026 | bool winreg; | |
2027 | /* True if a constant forced into memory would be OK for | |
2028 | this operand. */ | |
2029 | bool constmemok; | |
2030 | enum reg_class this_alternative, this_costly_alternative; | |
2031 | HARD_REG_SET this_alternative_set, this_costly_alternative_set; | |
2032 | bool this_alternative_match_win, this_alternative_win; | |
2033 | bool this_alternative_offmemok; | |
2b1732ad | 2034 | bool scratch_p; |
3754d046 | 2035 | machine_mode mode; |
79bc09fb | 2036 | enum constraint_num cn; |
c6a6cdaa | 2037 | |
2038 | opalt_num = nalt * n_operands + nop; | |
2039 | if (curr_static_id->operand_alternative[opalt_num].anything_ok) | |
2040 | { | |
2041 | /* Fast track for no constraints at all. */ | |
2042 | curr_alt[nop] = NO_REGS; | |
2043 | CLEAR_HARD_REG_SET (curr_alt_set[nop]); | |
2044 | curr_alt_win[nop] = true; | |
2045 | curr_alt_match_win[nop] = false; | |
2046 | curr_alt_offmemok[nop] = false; | |
2047 | curr_alt_matches[nop] = -1; | |
2048 | continue; | |
2049 | } | |
1a8f8886 | 2050 | |
c6a6cdaa | 2051 | op = no_subreg_reg_operand[nop]; |
2052 | mode = curr_operand_mode[nop]; | |
2053 | ||
2054 | win = did_match = winreg = offmemok = constmemok = false; | |
2055 | badop = true; | |
1a8f8886 | 2056 | |
c6a6cdaa | 2057 | early_clobber_p = false; |
2058 | p = curr_static_id->operand_alternative[opalt_num].constraint; | |
1a8f8886 | 2059 | |
c6a6cdaa | 2060 | this_costly_alternative = this_alternative = NO_REGS; |
2061 | /* We update set of possible hard regs besides its class | |
2062 | because reg class might be inaccurate. For example, | |
2063 | union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM | |
2064 | is translated in HI_REGS because classes are merged by | |
2065 | pairs and there is no accurate intermediate class. */ | |
2066 | CLEAR_HARD_REG_SET (this_alternative_set); | |
2067 | CLEAR_HARD_REG_SET (this_costly_alternative_set); | |
2068 | this_alternative_win = false; | |
2069 | this_alternative_match_win = false; | |
2070 | this_alternative_offmemok = false; | |
2071 | this_alternative_matches = -1; | |
1a8f8886 | 2072 | |
c6a6cdaa | 2073 | /* An empty constraint should be excluded by the fast |
2074 | track. */ | |
2075 | lra_assert (*p != 0 && *p != ','); | |
1a8f8886 | 2076 | |
ed6272f7 | 2077 | op_reject = 0; |
c6a6cdaa | 2078 | /* Scan this alternative's specs for this operand; set WIN |
2079 | if the operand fits any letter in this alternative. | |
2080 | Otherwise, clear BADOP if this operand could fit some | |
2081 | letter after reloads, or set WINREG if this operand could | |
2082 | fit after reloads provided the constraint allows some | |
2083 | registers. */ | |
2084 | costly_p = false; | |
2085 | do | |
2086 | { | |
2087 | switch ((c = *p, len = CONSTRAINT_LEN (c, p)), c) | |
2088 | { | |
2089 | case '\0': | |
2090 | len = 0; | |
2091 | break; | |
2092 | case ',': | |
2093 | c = '\0'; | |
2094 | break; | |
1a8f8886 | 2095 | |
c6a6cdaa | 2096 | case '&': |
2097 | early_clobber_p = true; | |
2098 | break; | |
1a8f8886 | 2099 | |
ed6272f7 | 2100 | case '$': |
2101 | op_reject += LRA_MAX_REJECT; | |
2102 | break; | |
2103 | case '^': | |
2104 | op_reject += LRA_LOSER_COST_FACTOR; | |
2105 | break; | |
2106 | ||
c6a6cdaa | 2107 | case '#': |
2108 | /* Ignore rest of this alternative. */ | |
2109 | c = '\0'; | |
2110 | break; | |
1a8f8886 | 2111 | |
c6a6cdaa | 2112 | case '0': case '1': case '2': case '3': case '4': |
2113 | case '5': case '6': case '7': case '8': case '9': | |
2114 | { | |
2115 | int m_hregno; | |
2116 | bool match_p; | |
1a8f8886 | 2117 | |
c6a6cdaa | 2118 | m = strtoul (p, &end, 10); |
2119 | p = end; | |
2120 | len = 0; | |
2121 | lra_assert (nop > m); | |
1a8f8886 | 2122 | |
e23bf764 | 2123 | /* Reject matches if we don't know which operand is |
2124 | bigger. This situation would arguably be a bug in | |
2125 | an .md pattern, but could also occur in a user asm. */ | |
2126 | if (!ordered_p (GET_MODE_SIZE (biggest_mode[m]), | |
2127 | GET_MODE_SIZE (biggest_mode[nop]))) | |
2128 | break; | |
2129 | ||
529fdbd1 | 2130 | /* Don't match wrong asm insn operands for proper |
2131 | diagnostic later. */ | |
2132 | if (INSN_CODE (curr_insn) < 0 | |
2133 | && (curr_operand_mode[m] == BLKmode | |
2134 | || curr_operand_mode[nop] == BLKmode) | |
2135 | && curr_operand_mode[m] != curr_operand_mode[nop]) | |
2136 | break; | |
2137 | ||
331a9ecc | 2138 | m_hregno = get_hard_regno (*curr_id->operand_loc[m], false); |
c6a6cdaa | 2139 | /* We are supposed to match a previous operand. |
2140 | If we do, we win if that one did. If we do | |
2141 | not, count both of the operands as losers. | |
2142 | (This is too conservative, since most of the | |
2143 | time only a single reload insn will be needed | |
2144 | to make the two operands win. As a result, | |
2145 | this alternative may be rejected when it is | |
2146 | actually desirable.) */ | |
2147 | match_p = false; | |
2148 | if (operands_match_p (*curr_id->operand_loc[nop], | |
2149 | *curr_id->operand_loc[m], m_hregno)) | |
2150 | { | |
2151 | /* We should reject matching of an early | |
2152 | clobber operand if the matching operand is | |
2153 | not dying in the insn. */ | |
8df3e7a5 | 2154 | if (!TEST_BIT (curr_static_id->operand[m] |
2155 | .early_clobber_alts, nalt) | |
c6a6cdaa | 2156 | || operand_reg[nop] == NULL_RTX |
2157 | || (find_regno_note (curr_insn, REG_DEAD, | |
89c2edcf | 2158 | REGNO (op)) |
2159 | || REGNO (op) == REGNO (operand_reg[m]))) | |
c6a6cdaa | 2160 | match_p = true; |
2161 | } | |
2162 | if (match_p) | |
2163 | { | |
2164 | /* If we are matching a non-offsettable | |
2165 | address where an offsettable address was | |
2166 | expected, then we must reject this | |
2167 | combination, because we can't reload | |
2168 | it. */ | |
2169 | if (curr_alt_offmemok[m] | |
2170 | && MEM_P (*curr_id->operand_loc[m]) | |
2171 | && curr_alt[m] == NO_REGS && ! curr_alt_win[m]) | |
2172 | continue; | |
c6a6cdaa | 2173 | } |
2174 | else | |
2175 | { | |
85d69302 | 2176 | /* If the operands do not match and one |
2177 | operand is INOUT, we can not match them. | |
2178 | Try other possibilities, e.g. other | |
2179 | alternatives or commutative operand | |
2180 | exchange. */ | |
2181 | if (curr_static_id->operand[nop].type == OP_INOUT | |
2182 | || curr_static_id->operand[m].type == OP_INOUT) | |
2183 | break; | |
b782636f | 2184 | /* Operands don't match. If the operands are |
c2930418 | 2185 | different user defined explicit hard |
2186 | registers, then we cannot make them match | |
2187 | when one is early clobber operand. */ | |
b782636f | 2188 | if ((REG_P (*curr_id->operand_loc[nop]) |
2189 | || SUBREG_P (*curr_id->operand_loc[nop])) | |
2190 | && (REG_P (*curr_id->operand_loc[m]) | |
2191 | || SUBREG_P (*curr_id->operand_loc[m]))) | |
2192 | { | |
2193 | rtx nop_reg = *curr_id->operand_loc[nop]; | |
2194 | if (SUBREG_P (nop_reg)) | |
2195 | nop_reg = SUBREG_REG (nop_reg); | |
2196 | rtx m_reg = *curr_id->operand_loc[m]; | |
2197 | if (SUBREG_P (m_reg)) | |
2198 | m_reg = SUBREG_REG (m_reg); | |
2199 | ||
2200 | if (REG_P (nop_reg) | |
2201 | && HARD_REGISTER_P (nop_reg) | |
2202 | && REG_USERVAR_P (nop_reg) | |
2203 | && REG_P (m_reg) | |
2204 | && HARD_REGISTER_P (m_reg) | |
2205 | && REG_USERVAR_P (m_reg)) | |
c2930418 | 2206 | { |
2207 | int i; | |
2208 | ||
2209 | for (i = 0; i < early_clobbered_regs_num; i++) | |
2210 | if (m == early_clobbered_nops[i]) | |
2211 | break; | |
2212 | if (i < early_clobbered_regs_num | |
2213 | || early_clobber_p) | |
2214 | break; | |
2215 | } | |
b782636f | 2216 | } |
b782636f | 2217 | /* Both operands must allow a reload register, |
2218 | otherwise we cannot make them match. */ | |
c6a6cdaa | 2219 | if (curr_alt[m] == NO_REGS) |
2220 | break; | |
2221 | /* Retroactively mark the operand we had to | |
2222 | match as a loser, if it wasn't already and | |
2223 | it wasn't matched to a register constraint | |
2224 | (e.g it might be matched by memory). */ | |
2225 | if (curr_alt_win[m] | |
2226 | && (operand_reg[m] == NULL_RTX | |
2227 | || hard_regno[m] < 0)) | |
2228 | { | |
2229 | losers++; | |
2230 | reload_nregs | |
2231 | += (ira_reg_class_max_nregs[curr_alt[m]] | |
2232 | [GET_MODE (*curr_id->operand_loc[m])]); | |
2233 | } | |
1a8f8886 | 2234 | |
53f1eb5d | 2235 | /* Prefer matching earlyclobber alternative as |
2236 | it results in less hard regs required for | |
2237 | the insn than a non-matching earlyclobber | |
2238 | alternative. */ | |
8df3e7a5 | 2239 | if (TEST_BIT (curr_static_id->operand[m] |
2240 | .early_clobber_alts, nalt)) | |
53f1eb5d | 2241 | { |
2242 | if (lra_dump_file != NULL) | |
2243 | fprintf | |
2244 | (lra_dump_file, | |
2245 | " %d Matching earlyclobber alt:" | |
2246 | " reject--\n", | |
2247 | nop); | |
3dfcf76a | 2248 | if (!matching_early_clobber[m]) |
2249 | { | |
2250 | reject--; | |
2251 | matching_early_clobber[m] = 1; | |
2252 | } | |
53f1eb5d | 2253 | } |
2254 | /* Otherwise we prefer no matching | |
2255 | alternatives because it gives more freedom | |
2256 | in RA. */ | |
2257 | else if (operand_reg[nop] == NULL_RTX | |
2258 | || (find_regno_note (curr_insn, REG_DEAD, | |
2259 | REGNO (operand_reg[nop])) | |
2260 | == NULL_RTX)) | |
34575461 | 2261 | { |
2262 | if (lra_dump_file != NULL) | |
2263 | fprintf | |
2264 | (lra_dump_file, | |
2265 | " %d Matching alt: reject+=2\n", | |
2266 | nop); | |
2267 | reject += 2; | |
2268 | } | |
c6a6cdaa | 2269 | } |
2270 | /* If we have to reload this operand and some | |
2271 | previous operand also had to match the same | |
2272 | thing as this operand, we don't know how to do | |
2273 | that. */ | |
2274 | if (!match_p || !curr_alt_win[m]) | |
2275 | { | |
2276 | for (i = 0; i < nop; i++) | |
2277 | if (curr_alt_matches[i] == m) | |
2278 | break; | |
2279 | if (i < nop) | |
2280 | break; | |
2281 | } | |
2282 | else | |
2283 | did_match = true; | |
1a8f8886 | 2284 | |
7ceb795f | 2285 | this_alternative_matches = m; |
c6a6cdaa | 2286 | /* This can be fixed with reloads if the operand |
2287 | we are supposed to match can be fixed with | |
2288 | reloads. */ | |
2289 | badop = false; | |
2290 | this_alternative = curr_alt[m]; | |
2291 | COPY_HARD_REG_SET (this_alternative_set, curr_alt_set[m]); | |
4b3aba76 | 2292 | winreg = this_alternative != NO_REGS; |
c6a6cdaa | 2293 | break; |
2294 | } | |
1a8f8886 | 2295 | |
c6a6cdaa | 2296 | case 'g': |
2297 | if (MEM_P (op) | |
2298 | || general_constant_p (op) | |
2299 | || spilled_pseudo_p (op)) | |
2300 | win = true; | |
79bc09fb | 2301 | cl = GENERAL_REGS; |
c6a6cdaa | 2302 | goto reg; |
1a8f8886 | 2303 | |
c6a6cdaa | 2304 | default: |
79bc09fb | 2305 | cn = lookup_constraint (p); |
2306 | switch (get_constraint_type (cn)) | |
c6a6cdaa | 2307 | { |
79bc09fb | 2308 | case CT_REGISTER: |
2309 | cl = reg_class_for_constraint (cn); | |
2310 | if (cl != NO_REGS) | |
2311 | goto reg; | |
2312 | break; | |
1a8f8886 | 2313 | |
4e67d0bf | 2314 | case CT_CONST_INT: |
2315 | if (CONST_INT_P (op) | |
2316 | && insn_const_int_ok_for_constraint (INTVAL (op), cn)) | |
2317 | win = true; | |
2318 | break; | |
2319 | ||
79bc09fb | 2320 | case CT_MEMORY: |
2321 | if (MEM_P (op) | |
2322 | && satisfies_memory_constraint_p (op, cn)) | |
2323 | win = true; | |
2324 | else if (spilled_pseudo_p (op)) | |
2325 | win = true; | |
2326 | ||
2327 | /* If we didn't already win, we can reload constants | |
2328 | via force_const_mem or put the pseudo value into | |
2329 | memory, or make other memory by reloading the | |
2330 | address like for 'o'. */ | |
2331 | if (CONST_POOL_OK_P (mode, op) | |
003000a4 | 2332 | || MEM_P (op) || REG_P (op) |
2333 | /* We can restore the equiv insn by a | |
2334 | reload. */ | |
2335 | || equiv_substition_p[nop]) | |
79bc09fb | 2336 | badop = false; |
2337 | constmemok = true; | |
2338 | offmemok = true; | |
2339 | break; | |
2340 | ||
2341 | case CT_ADDRESS: | |
afca8a73 | 2342 | /* An asm operand with an address constraint |
2343 | that doesn't satisfy address_operand has | |
2344 | is_address cleared, so that we don't try to | |
2345 | make a non-address fit. */ | |
2346 | if (!curr_static_id->operand[nop].is_address) | |
2347 | break; | |
79bc09fb | 2348 | /* If we didn't already win, we can reload the address |
2349 | into a base register. */ | |
2350 | if (satisfies_address_constraint_p (op, cn)) | |
2351 | win = true; | |
2352 | cl = base_reg_class (VOIDmode, ADDR_SPACE_GENERIC, | |
2353 | ADDRESS, SCRATCH); | |
2354 | badop = false; | |
2355 | goto reg; | |
2356 | ||
2357 | case CT_FIXED_FORM: | |
2358 | if (constraint_satisfied_p (op, cn)) | |
c6a6cdaa | 2359 | win = true; |
c6a6cdaa | 2360 | break; |
6b3b345a | 2361 | |
2362 | case CT_SPECIAL_MEMORY: | |
2363 | if (MEM_P (op) | |
2364 | && satisfies_memory_constraint_p (op, cn)) | |
2365 | win = true; | |
2366 | else if (spilled_pseudo_p (op)) | |
2367 | win = true; | |
2368 | break; | |
c6a6cdaa | 2369 | } |
79bc09fb | 2370 | break; |
1a8f8886 | 2371 | |
79bc09fb | 2372 | reg: |
fcf9e045 | 2373 | if (mode == BLKmode) |
2374 | break; | |
c6a6cdaa | 2375 | this_alternative = reg_class_subunion[this_alternative][cl]; |
2376 | IOR_HARD_REG_SET (this_alternative_set, | |
2377 | reg_class_contents[cl]); | |
2378 | if (costly_p) | |
2379 | { | |
2380 | this_costly_alternative | |
2381 | = reg_class_subunion[this_costly_alternative][cl]; | |
2382 | IOR_HARD_REG_SET (this_costly_alternative_set, | |
2383 | reg_class_contents[cl]); | |
2384 | } | |
c6a6cdaa | 2385 | winreg = true; |
2386 | if (REG_P (op)) | |
2387 | { | |
2388 | if (hard_regno[nop] >= 0 | |
2389 | && in_hard_reg_set_p (this_alternative_set, | |
2390 | mode, hard_regno[nop])) | |
2391 | win = true; | |
2392 | else if (hard_regno[nop] < 0 | |
2393 | && in_class_p (op, this_alternative, NULL)) | |
2394 | win = true; | |
2395 | } | |
2396 | break; | |
2397 | } | |
2398 | if (c != ' ' && c != '\t') | |
2399 | costly_p = c == '*'; | |
2400 | } | |
2401 | while ((p += len), c); | |
1a8f8886 | 2402 | |
2b1732ad | 2403 | scratch_p = (operand_reg[nop] != NULL_RTX |
2404 | && lra_former_scratch_p (REGNO (operand_reg[nop]))); | |
c6a6cdaa | 2405 | /* Record which operands fit this alternative. */ |
2406 | if (win) | |
2407 | { | |
2408 | this_alternative_win = true; | |
2409 | if (operand_reg[nop] != NULL_RTX) | |
2410 | { | |
2411 | if (hard_regno[nop] >= 0) | |
2412 | { | |
2413 | if (in_hard_reg_set_p (this_costly_alternative_set, | |
2414 | mode, hard_regno[nop])) | |
34575461 | 2415 | { |
2416 | if (lra_dump_file != NULL) | |
2417 | fprintf (lra_dump_file, | |
2418 | " %d Costly set: reject++\n", | |
2419 | nop); | |
2420 | reject++; | |
2421 | } | |
c6a6cdaa | 2422 | } |
2423 | else | |
2424 | { | |
2b1732ad | 2425 | /* Prefer won reg to spilled pseudo under other |
2426 | equal conditions for possibe inheritance. */ | |
2427 | if (! scratch_p) | |
2428 | { | |
2429 | if (lra_dump_file != NULL) | |
2430 | fprintf | |
2431 | (lra_dump_file, | |
2432 | " %d Non pseudo reload: reject++\n", | |
2433 | nop); | |
2434 | reject++; | |
2435 | } | |
c6a6cdaa | 2436 | if (in_class_p (operand_reg[nop], |
2437 | this_costly_alternative, NULL)) | |
34575461 | 2438 | { |
2439 | if (lra_dump_file != NULL) | |
2440 | fprintf | |
2441 | (lra_dump_file, | |
2442 | " %d Non pseudo costly reload:" | |
2443 | " reject++\n", | |
2444 | nop); | |
2445 | reject++; | |
2446 | } | |
c6a6cdaa | 2447 | } |
67cf9b55 | 2448 | /* We simulate the behavior of old reload here. |
c6a6cdaa | 2449 | Although scratches need hard registers and it |
2450 | might result in spilling other pseudos, no reload | |
2451 | insns are generated for the scratches. So it | |
2452 | might cost something but probably less than old | |
2453 | reload pass believes. */ | |
2b1732ad | 2454 | if (scratch_p) |
34575461 | 2455 | { |
2456 | if (lra_dump_file != NULL) | |
2457 | fprintf (lra_dump_file, | |
2b1732ad | 2458 | " %d Scratch win: reject+=2\n", |
34575461 | 2459 | nop); |
2b1732ad | 2460 | reject += 2; |
34575461 | 2461 | } |
c6a6cdaa | 2462 | } |
2463 | } | |
2464 | else if (did_match) | |
2465 | this_alternative_match_win = true; | |
2466 | else | |
2467 | { | |
2468 | int const_to_mem = 0; | |
2469 | bool no_regs_p; | |
2470 | ||
ed6272f7 | 2471 | reject += op_reject; |
3b3a5e5f | 2472 | /* Never do output reload of stack pointer. It makes |
2473 | impossible to do elimination when SP is changed in | |
2474 | RTL. */ | |
2475 | if (op == stack_pointer_rtx && ! frame_pointer_needed | |
2476 | && curr_static_id->operand[nop].type != OP_IN) | |
2477 | goto fail; | |
2478 | ||
aa46b107 | 2479 | /* If this alternative asks for a specific reg class, see if there |
2480 | is at least one allocatable register in that class. */ | |
c6a6cdaa | 2481 | no_regs_p |
2482 | = (this_alternative == NO_REGS | |
2483 | || (hard_reg_set_subset_p | |
2484 | (reg_class_contents[this_alternative], | |
2485 | lra_no_alloc_regs))); | |
aa46b107 | 2486 | |
2487 | /* For asms, verify that the class for this alternative is possible | |
2488 | for the mode that is specified. */ | |
1524bcdc | 2489 | if (!no_regs_p && INSN_CODE (curr_insn) < 0) |
aa46b107 | 2490 | { |
2491 | int i; | |
2492 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
b395382f | 2493 | if (targetm.hard_regno_mode_ok (i, mode) |
b3d446cb | 2494 | && in_hard_reg_set_p (reg_class_contents[this_alternative], |
2495 | mode, i)) | |
aa46b107 | 2496 | break; |
2497 | if (i == FIRST_PSEUDO_REGISTER) | |
2498 | winreg = false; | |
2499 | } | |
2500 | ||
c6a6cdaa | 2501 | /* If this operand accepts a register, and if the |
2502 | register class has at least one allocatable register, | |
2503 | then this operand can be reloaded. */ | |
2504 | if (winreg && !no_regs_p) | |
2505 | badop = false; | |
1a8f8886 | 2506 | |
c6a6cdaa | 2507 | if (badop) |
b3d446cb | 2508 | { |
2509 | if (lra_dump_file != NULL) | |
2510 | fprintf (lra_dump_file, | |
2511 | " alt=%d: Bad operand -- refuse\n", | |
2512 | nalt); | |
2513 | goto fail; | |
2514 | } | |
c6a6cdaa | 2515 | |
a2ebcb84 | 2516 | if (this_alternative != NO_REGS) |
2517 | { | |
2518 | HARD_REG_SET available_regs; | |
2519 | ||
2520 | COPY_HARD_REG_SET (available_regs, | |
2521 | reg_class_contents[this_alternative]); | |
2522 | AND_COMPL_HARD_REG_SET | |
2523 | (available_regs, | |
2524 | ira_prohibited_class_mode_regs[this_alternative][mode]); | |
2525 | AND_COMPL_HARD_REG_SET (available_regs, lra_no_alloc_regs); | |
2526 | if (hard_reg_set_empty_p (available_regs)) | |
2527 | { | |
2528 | /* There are no hard regs holding a value of given | |
2529 | mode. */ | |
2530 | if (offmemok) | |
2531 | { | |
2532 | this_alternative = NO_REGS; | |
2533 | if (lra_dump_file != NULL) | |
2534 | fprintf (lra_dump_file, | |
2535 | " %d Using memory because of" | |
2536 | " a bad mode: reject+=2\n", | |
2537 | nop); | |
2538 | reject += 2; | |
2539 | } | |
2540 | else | |
2541 | { | |
2542 | if (lra_dump_file != NULL) | |
2543 | fprintf (lra_dump_file, | |
2544 | " alt=%d: Wrong mode -- refuse\n", | |
2545 | nalt); | |
2546 | goto fail; | |
2547 | } | |
2548 | } | |
2549 | } | |
2550 | ||
77a00b11 | 2551 | /* If not assigned pseudo has a class which a subset of |
2552 | required reg class, it is a less costly alternative | |
2553 | as the pseudo still can get a hard reg of necessary | |
2554 | class. */ | |
2555 | if (! no_regs_p && REG_P (op) && hard_regno[nop] < 0 | |
2556 | && (cl = get_reg_class (REGNO (op))) != NO_REGS | |
2557 | && ira_class_subset_p[this_alternative][cl]) | |
2558 | { | |
2559 | if (lra_dump_file != NULL) | |
2560 | fprintf | |
2561 | (lra_dump_file, | |
2562 | " %d Super set class reg: reject-=3\n", nop); | |
2563 | reject -= 3; | |
2564 | } | |
2565 | ||
c6a6cdaa | 2566 | this_alternative_offmemok = offmemok; |
2567 | if (this_costly_alternative != NO_REGS) | |
34575461 | 2568 | { |
2569 | if (lra_dump_file != NULL) | |
2570 | fprintf (lra_dump_file, | |
2571 | " %d Costly loser: reject++\n", nop); | |
2572 | reject++; | |
2573 | } | |
c6a6cdaa | 2574 | /* If the operand is dying, has a matching constraint, |
2575 | and satisfies constraints of the matched operand | |
53f1eb5d | 2576 | which failed to satisfy the own constraints, most probably |
4f428208 | 2577 | the reload for this operand will be gone. */ |
2578 | if (this_alternative_matches >= 0 | |
2579 | && !curr_alt_win[this_alternative_matches] | |
2580 | && REG_P (op) | |
2581 | && find_regno_note (curr_insn, REG_DEAD, REGNO (op)) | |
2582 | && (hard_regno[nop] >= 0 | |
2583 | ? in_hard_reg_set_p (this_alternative_set, | |
2584 | mode, hard_regno[nop]) | |
2585 | : in_class_p (op, this_alternative, NULL))) | |
2586 | { | |
2587 | if (lra_dump_file != NULL) | |
2588 | fprintf | |
2589 | (lra_dump_file, | |
2590 | " %d Dying matched operand reload: reject++\n", | |
2591 | nop); | |
2592 | reject++; | |
2593 | } | |
2594 | else | |
2e620dc7 | 2595 | { |
92dfb77d | 2596 | /* Strict_low_part requires to reload the register |
2597 | not the sub-register. In this case we should | |
2598 | check that a final reload hard reg can hold the | |
2599 | value mode. */ | |
2e620dc7 | 2600 | if (curr_static_id->operand[nop].strict_low |
2601 | && REG_P (op) | |
2602 | && hard_regno[nop] < 0 | |
2603 | && GET_CODE (*curr_id->operand_loc[nop]) == SUBREG | |
2604 | && ira_class_hard_regs_num[this_alternative] > 0 | |
b395382f | 2605 | && (!targetm.hard_regno_mode_ok |
2606 | (ira_class_hard_regs[this_alternative][0], | |
2607 | GET_MODE (*curr_id->operand_loc[nop])))) | |
b3d446cb | 2608 | { |
2609 | if (lra_dump_file != NULL) | |
2610 | fprintf | |
2611 | (lra_dump_file, | |
2612 | " alt=%d: Strict low subreg reload -- refuse\n", | |
2613 | nalt); | |
2614 | goto fail; | |
2615 | } | |
2e620dc7 | 2616 | losers++; |
2617 | } | |
c6a6cdaa | 2618 | if (operand_reg[nop] != NULL_RTX |
2619 | /* Output operands and matched input operands are | |
2620 | not inherited. The following conditions do not | |
2621 | exactly describe the previous statement but they | |
2622 | are pretty close. */ | |
2623 | && curr_static_id->operand[nop].type != OP_OUT | |
2624 | && (this_alternative_matches < 0 | |
2625 | || curr_static_id->operand[nop].type != OP_IN)) | |
2626 | { | |
2627 | int last_reload = (lra_reg_info[ORIGINAL_REGNO | |
2628 | (operand_reg[nop])] | |
2629 | .last_reload); | |
2630 | ||
92b64c52 | 2631 | /* The value of reload_sum has sense only if we |
2632 | process insns in their order. It happens only on | |
2633 | the first constraints sub-pass when we do most of | |
2634 | reload work. */ | |
2635 | if (lra_constraint_iter == 1 && last_reload > bb_reload_num) | |
c6a6cdaa | 2636 | reload_sum += last_reload - bb_reload_num; |
2637 | } | |
2638 | /* If this is a constant that is reloaded into the | |
2639 | desired class by copying it to memory first, count | |
2640 | that as another reload. This is consistent with | |
2641 | other code and is required to avoid choosing another | |
2642 | alternative when the constant is moved into memory. | |
2643 | Note that the test here is precisely the same as in | |
2644 | the code below that calls force_const_mem. */ | |
2645 | if (CONST_POOL_OK_P (mode, op) | |
2646 | && ((targetm.preferred_reload_class | |
2647 | (op, this_alternative) == NO_REGS) | |
2648 | || no_input_reloads_p)) | |
2649 | { | |
2650 | const_to_mem = 1; | |
2651 | if (! no_regs_p) | |
2652 | losers++; | |
2653 | } | |
1a8f8886 | 2654 | |
c6a6cdaa | 2655 | /* Alternative loses if it requires a type of reload not |
2656 | permitted for this insn. We can always reload | |
2657 | objects with a REG_UNUSED note. */ | |
2658 | if ((curr_static_id->operand[nop].type != OP_IN | |
2659 | && no_output_reloads_p | |
2660 | && ! find_reg_note (curr_insn, REG_UNUSED, op)) | |
2661 | || (curr_static_id->operand[nop].type != OP_OUT | |
b3d446cb | 2662 | && no_input_reloads_p && ! const_to_mem) |
2663 | || (this_alternative_matches >= 0 | |
fe5cb3e1 | 2664 | && (no_input_reloads_p |
2665 | || (no_output_reloads_p | |
2666 | && (curr_static_id->operand | |
2667 | [this_alternative_matches].type != OP_IN) | |
2668 | && ! find_reg_note (curr_insn, REG_UNUSED, | |
2669 | no_subreg_reg_operand | |
2670 | [this_alternative_matches]))))) | |
b3d446cb | 2671 | { |
2672 | if (lra_dump_file != NULL) | |
2673 | fprintf | |
2674 | (lra_dump_file, | |
2675 | " alt=%d: No input/otput reload -- refuse\n", | |
2676 | nalt); | |
2677 | goto fail; | |
2678 | } | |
1a8f8886 | 2679 | |
f4d3c071 | 2680 | /* Alternative loses if it required class pseudo cannot |
2e19c420 | 2681 | hold value of required mode. Such insns can be |
2bd08537 | 2682 | described by insn definitions with mode iterators. */ |
2e19c420 | 2683 | if (GET_MODE (*curr_id->operand_loc[nop]) != VOIDmode |
2684 | && ! hard_reg_set_empty_p (this_alternative_set) | |
2bd08537 | 2685 | /* It is common practice for constraints to use a |
2686 | class which does not have actually enough regs to | |
2687 | hold the value (e.g. x86 AREG for mode requiring | |
2688 | more one general reg). Therefore we have 2 | |
07c11f2b | 2689 | conditions to check that the reload pseudo cannot |
2690 | hold the mode value. */ | |
b395382f | 2691 | && (!targetm.hard_regno_mode_ok |
2692 | (ira_class_hard_regs[this_alternative][0], | |
2693 | GET_MODE (*curr_id->operand_loc[nop]))) | |
2bd08537 | 2694 | /* The above condition is not enough as the first |
2695 | reg in ira_class_hard_regs can be not aligned for | |
2696 | multi-words mode values. */ | |
25cd984c | 2697 | && (prohibited_class_reg_set_mode_p |
2698 | (this_alternative, this_alternative_set, | |
2699 | GET_MODE (*curr_id->operand_loc[nop])))) | |
2700 | { | |
2701 | if (lra_dump_file != NULL) | |
2702 | fprintf (lra_dump_file, | |
2703 | " alt=%d: reload pseudo for op %d " | |
000969f9 | 2704 | "cannot hold the mode value -- refuse\n", |
25cd984c | 2705 | nalt, nop); |
2706 | goto fail; | |
2e19c420 | 2707 | } |
2708 | ||
4b3aba76 | 2709 | /* Check strong discouragement of reload of non-constant |
2710 | into class THIS_ALTERNATIVE. */ | |
2711 | if (! CONSTANT_P (op) && ! no_regs_p | |
2712 | && (targetm.preferred_reload_class | |
2713 | (op, this_alternative) == NO_REGS | |
2714 | || (curr_static_id->operand[nop].type == OP_OUT | |
2715 | && (targetm.preferred_output_reload_class | |
2716 | (op, this_alternative) == NO_REGS)))) | |
34575461 | 2717 | { |
2718 | if (lra_dump_file != NULL) | |
2719 | fprintf (lra_dump_file, | |
2720 | " %d Non-prefered reload: reject+=%d\n", | |
2721 | nop, LRA_MAX_REJECT); | |
2722 | reject += LRA_MAX_REJECT; | |
2723 | } | |
1a8f8886 | 2724 | |
0178c26e | 2725 | if (! (MEM_P (op) && offmemok) |
2726 | && ! (const_to_mem && constmemok)) | |
c6a6cdaa | 2727 | { |
2728 | /* We prefer to reload pseudos over reloading other | |
2729 | things, since such reloads may be able to be | |
2730 | eliminated later. So bump REJECT in other cases. | |
2731 | Don't do this in the case where we are forcing a | |
2732 | constant into memory and it will then win since | |
2733 | we don't want to have a different alternative | |
2734 | match then. */ | |
2735 | if (! (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER)) | |
34575461 | 2736 | { |
2737 | if (lra_dump_file != NULL) | |
2738 | fprintf | |
2739 | (lra_dump_file, | |
2740 | " %d Non-pseudo reload: reject+=2\n", | |
2741 | nop); | |
2742 | reject += 2; | |
2743 | } | |
1a8f8886 | 2744 | |
c6a6cdaa | 2745 | if (! no_regs_p) |
2746 | reload_nregs | |
2747 | += ira_reg_class_max_nregs[this_alternative][mode]; | |
273c330a | 2748 | |
2749 | if (SMALL_REGISTER_CLASS_P (this_alternative)) | |
34575461 | 2750 | { |
2751 | if (lra_dump_file != NULL) | |
2752 | fprintf | |
2753 | (lra_dump_file, | |
2754 | " %d Small class reload: reject+=%d\n", | |
2755 | nop, LRA_LOSER_COST_FACTOR / 2); | |
2756 | reject += LRA_LOSER_COST_FACTOR / 2; | |
2757 | } | |
c6a6cdaa | 2758 | } |
2759 | ||
70892847 | 2760 | /* We are trying to spill pseudo into memory. It is |
2761 | usually more costly than moving to a hard register | |
2762 | although it might takes the same number of | |
b02d1ebc | 2763 | reloads. |
2764 | ||
2765 | Non-pseudo spill may happen also. Suppose a target allows both | |
2766 | register and memory in the operand constraint alternatives, | |
2767 | then it's typical that an eliminable register has a substition | |
2768 | of "base + offset" which can either be reloaded by a simple | |
2769 | "new_reg <= base + offset" which will match the register | |
2770 | constraint, or a similar reg addition followed by further spill | |
2771 | to and reload from memory which will match the memory | |
2772 | constraint, but this memory spill will be much more costly | |
2773 | usually. | |
2774 | ||
2775 | Code below increases the reject for both pseudo and non-pseudo | |
2776 | spill. */ | |
21b32b46 | 2777 | if (no_regs_p |
2778 | && !(MEM_P (op) && offmemok) | |
2779 | && !(REG_P (op) && hard_regno[nop] < 0)) | |
34575461 | 2780 | { |
2781 | if (lra_dump_file != NULL) | |
2782 | fprintf | |
2783 | (lra_dump_file, | |
b02d1ebc | 2784 | " %d Spill %spseudo into memory: reject+=3\n", |
2785 | nop, REG_P (op) ? "" : "Non-"); | |
34575461 | 2786 | reject += 3; |
c2d1c3eb | 2787 | if (VECTOR_MODE_P (mode)) |
2788 | { | |
2789 | /* Spilling vectors into memory is usually more | |
2790 | costly as they contain big values. */ | |
2791 | if (lra_dump_file != NULL) | |
2792 | fprintf | |
2793 | (lra_dump_file, | |
2794 | " %d Spill vector pseudo: reject+=2\n", | |
2795 | nop); | |
2796 | reject += 2; | |
2797 | } | |
34575461 | 2798 | } |
70892847 | 2799 | |
9cd589b8 | 2800 | /* When we use an operand requiring memory in given |
2801 | alternative, the insn should write *and* read the | |
2802 | value to/from memory it is costly in comparison with | |
2803 | an insn alternative which does not use memory | |
2804 | (e.g. register or immediate operand). We exclude | |
2805 | memory operand for such case as we can satisfy the | |
2806 | memory constraints by reloading address. */ | |
2807 | if (no_regs_p && offmemok && !MEM_P (op)) | |
8afaf3bf | 2808 | { |
2809 | if (lra_dump_file != NULL) | |
2810 | fprintf | |
2811 | (lra_dump_file, | |
2812 | " Using memory insn operand %d: reject+=3\n", | |
2813 | nop); | |
2814 | reject += 3; | |
2815 | } | |
2816 | ||
2590979b | 2817 | /* If reload requires moving value through secondary |
2818 | memory, it will need one more insn at least. */ | |
2819 | if (this_alternative != NO_REGS | |
2820 | && REG_P (op) && (cl = get_reg_class (REGNO (op))) != NO_REGS | |
2821 | && ((curr_static_id->operand[nop].type != OP_OUT | |
c836e75b | 2822 | && targetm.secondary_memory_needed (GET_MODE (op), cl, |
2823 | this_alternative)) | |
2590979b | 2824 | || (curr_static_id->operand[nop].type != OP_IN |
c836e75b | 2825 | && (targetm.secondary_memory_needed |
2826 | (GET_MODE (op), this_alternative, cl))))) | |
2590979b | 2827 | losers++; |
c836e75b | 2828 | |
eb70a065 | 2829 | if (MEM_P (op) && offmemok) |
2830 | addr_losers++; | |
67f1426f | 2831 | else |
44cafa9a | 2832 | { |
67f1426f | 2833 | /* Input reloads can be inherited more often than |
2834 | output reloads can be removed, so penalize output | |
2835 | reloads. */ | |
2836 | if (!REG_P (op) || curr_static_id->operand[nop].type != OP_IN) | |
2837 | { | |
2838 | if (lra_dump_file != NULL) | |
2839 | fprintf | |
2840 | (lra_dump_file, | |
2841 | " %d Non input pseudo reload: reject++\n", | |
2842 | nop); | |
2843 | reject++; | |
2844 | } | |
2845 | ||
2846 | if (curr_static_id->operand[nop].type == OP_INOUT) | |
2847 | { | |
2848 | if (lra_dump_file != NULL) | |
2849 | fprintf | |
2850 | (lra_dump_file, | |
2851 | " %d Input/Output reload: reject+=%d\n", | |
2852 | nop, LRA_LOSER_COST_FACTOR); | |
2853 | reject += LRA_LOSER_COST_FACTOR; | |
2854 | } | |
44cafa9a | 2855 | } |
c6a6cdaa | 2856 | } |
1a8f8886 | 2857 | |
2b1732ad | 2858 | if (early_clobber_p && ! scratch_p) |
34575461 | 2859 | { |
2860 | if (lra_dump_file != NULL) | |
2861 | fprintf (lra_dump_file, | |
2862 | " %d Early clobber: reject++\n", nop); | |
2863 | reject++; | |
2864 | } | |
c6a6cdaa | 2865 | /* ??? We check early clobbers after processing all operands |
2866 | (see loop below) and there we update the costs more. | |
2867 | Should we update the cost (may be approximately) here | |
2868 | because of early clobber register reloads or it is a rare | |
2869 | or non-important thing to be worth to do it. */ | |
eb70a065 | 2870 | overall = (losers * LRA_LOSER_COST_FACTOR + reject |
2871 | - (addr_losers == losers ? static_reject : 0)); | |
c6a6cdaa | 2872 | if ((best_losers == 0 || losers != 0) && best_overall < overall) |
f7c98bb1 | 2873 | { |
2874 | if (lra_dump_file != NULL) | |
2875 | fprintf (lra_dump_file, | |
34575461 | 2876 | " alt=%d,overall=%d,losers=%d -- refuse\n", |
f7c98bb1 | 2877 | nalt, overall, losers); |
2878 | goto fail; | |
2879 | } | |
c6a6cdaa | 2880 | |
8df3e7a5 | 2881 | if (update_and_check_small_class_inputs (nop, nalt, |
2882 | this_alternative)) | |
8afaf3bf | 2883 | { |
2884 | if (lra_dump_file != NULL) | |
2885 | fprintf (lra_dump_file, | |
2886 | " alt=%d, not enough small class regs -- refuse\n", | |
2887 | nalt); | |
2888 | goto fail; | |
2889 | } | |
c6a6cdaa | 2890 | curr_alt[nop] = this_alternative; |
2891 | COPY_HARD_REG_SET (curr_alt_set[nop], this_alternative_set); | |
2892 | curr_alt_win[nop] = this_alternative_win; | |
2893 | curr_alt_match_win[nop] = this_alternative_match_win; | |
2894 | curr_alt_offmemok[nop] = this_alternative_offmemok; | |
2895 | curr_alt_matches[nop] = this_alternative_matches; | |
1a8f8886 | 2896 | |
c6a6cdaa | 2897 | if (this_alternative_matches >= 0 |
2898 | && !did_match && !this_alternative_win) | |
2899 | curr_alt_win[this_alternative_matches] = false; | |
1a8f8886 | 2900 | |
c6a6cdaa | 2901 | if (early_clobber_p && operand_reg[nop] != NULL_RTX) |
2902 | early_clobbered_nops[early_clobbered_regs_num++] = nop; | |
2903 | } | |
eb70a065 | 2904 | |
ea99c7a1 | 2905 | if (curr_insn_set != NULL_RTX && n_operands == 2 |
2906 | /* Prevent processing non-move insns. */ | |
2907 | && (GET_CODE (SET_SRC (curr_insn_set)) == SUBREG | |
2908 | || SET_SRC (curr_insn_set) == no_subreg_reg_operand[1]) | |
2909 | && ((! curr_alt_win[0] && ! curr_alt_win[1] | |
2910 | && REG_P (no_subreg_reg_operand[0]) | |
2911 | && REG_P (no_subreg_reg_operand[1]) | |
2912 | && (reg_in_class_p (no_subreg_reg_operand[0], curr_alt[1]) | |
2913 | || reg_in_class_p (no_subreg_reg_operand[1], curr_alt[0]))) | |
2914 | || (! curr_alt_win[0] && curr_alt_win[1] | |
2915 | && REG_P (no_subreg_reg_operand[1]) | |
eb70a065 | 2916 | /* Check that we reload memory not the memory |
2917 | address. */ | |
9782b2bc | 2918 | && ! (curr_alt_offmemok[0] |
2919 | && MEM_P (no_subreg_reg_operand[0])) | |
ea99c7a1 | 2920 | && reg_in_class_p (no_subreg_reg_operand[1], curr_alt[0])) |
2921 | || (curr_alt_win[0] && ! curr_alt_win[1] | |
2922 | && REG_P (no_subreg_reg_operand[0]) | |
eb70a065 | 2923 | /* Check that we reload memory not the memory |
2924 | address. */ | |
9782b2bc | 2925 | && ! (curr_alt_offmemok[1] |
2926 | && MEM_P (no_subreg_reg_operand[1])) | |
ea99c7a1 | 2927 | && reg_in_class_p (no_subreg_reg_operand[0], curr_alt[1]) |
2928 | && (! CONST_POOL_OK_P (curr_operand_mode[1], | |
2929 | no_subreg_reg_operand[1]) | |
2930 | || (targetm.preferred_reload_class | |
2931 | (no_subreg_reg_operand[1], | |
2932 | (enum reg_class) curr_alt[1]) != NO_REGS)) | |
2933 | /* If it is a result of recent elimination in move | |
2934 | insn we can transform it into an add still by | |
2935 | using this alternative. */ | |
69f0f127 | 2936 | && GET_CODE (no_subreg_reg_operand[1]) != PLUS |
2937 | /* Likewise if the source has been replaced with an | |
2938 | equivalent value. This only happens once -- the reload | |
2939 | will use the equivalent value instead of the register it | |
2940 | replaces -- so there should be no danger of cycling. */ | |
2941 | && !equiv_substition_p[1]))) | |
34575461 | 2942 | { |
2943 | /* We have a move insn and a new reload insn will be similar | |
9782b2bc | 2944 | to the current insn. We should avoid such situation as |
2945 | it results in LRA cycling. */ | |
2946 | if (lra_dump_file != NULL) | |
2947 | fprintf (lra_dump_file, | |
2948 | " Cycle danger: overall += LRA_MAX_REJECT\n"); | |
34575461 | 2949 | overall += LRA_MAX_REJECT; |
2950 | } | |
c6a6cdaa | 2951 | ok_p = true; |
2952 | curr_alt_dont_inherit_ops_num = 0; | |
2953 | for (nop = 0; nop < early_clobbered_regs_num; nop++) | |
2954 | { | |
8c3a9b39 | 2955 | int i, j, clobbered_hard_regno, first_conflict_j, last_conflict_j; |
c6a6cdaa | 2956 | HARD_REG_SET temp_set; |
2957 | ||
2958 | i = early_clobbered_nops[nop]; | |
2959 | if ((! curr_alt_win[i] && ! curr_alt_match_win[i]) | |
2960 | || hard_regno[i] < 0) | |
2961 | continue; | |
89c2edcf | 2962 | lra_assert (operand_reg[i] != NULL_RTX); |
c6a6cdaa | 2963 | clobbered_hard_regno = hard_regno[i]; |
2964 | CLEAR_HARD_REG_SET (temp_set); | |
2965 | add_to_hard_reg_set (&temp_set, biggest_mode[i], clobbered_hard_regno); | |
8c3a9b39 | 2966 | first_conflict_j = last_conflict_j = -1; |
c6a6cdaa | 2967 | for (j = 0; j < n_operands; j++) |
2968 | if (j == i | |
2969 | /* We don't want process insides of match_operator and | |
2970 | match_parallel because otherwise we would process | |
2971 | their operands once again generating a wrong | |
2972 | code. */ | |
2973 | || curr_static_id->operand[j].is_operator) | |
2974 | continue; | |
2975 | else if ((curr_alt_matches[j] == i && curr_alt_match_win[j]) | |
2976 | || (curr_alt_matches[i] == j && curr_alt_match_win[i])) | |
2977 | continue; | |
89c2edcf | 2978 | /* If we don't reload j-th operand, check conflicts. */ |
2979 | else if ((curr_alt_win[j] || curr_alt_match_win[j]) | |
2980 | && uses_hard_regs_p (*curr_id->operand_loc[j], temp_set)) | |
8c3a9b39 | 2981 | { |
2982 | if (first_conflict_j < 0) | |
2983 | first_conflict_j = j; | |
2984 | last_conflict_j = j; | |
b782636f | 2985 | /* Both the earlyclobber operand and conflicting operand |
2986 | cannot both be user defined hard registers. */ | |
2987 | if (HARD_REGISTER_P (operand_reg[i]) | |
2988 | && REG_USERVAR_P (operand_reg[i]) | |
2989 | && operand_reg[j] != NULL_RTX | |
2990 | && HARD_REGISTER_P (operand_reg[j]) | |
2991 | && REG_USERVAR_P (operand_reg[j])) | |
2992 | fatal_insn ("unable to generate reloads for " | |
2993 | "impossible constraints:", curr_insn); | |
8c3a9b39 | 2994 | } |
2995 | if (last_conflict_j < 0) | |
c6a6cdaa | 2996 | continue; |
b782636f | 2997 | |
2998 | /* If an earlyclobber operand conflicts with another non-matching | |
2999 | operand (ie, they have been assigned the same hard register), | |
3000 | then it is better to reload the other operand, as there may | |
3001 | exist yet another operand with a matching constraint associated | |
3002 | with the earlyclobber operand. However, if one of the operands | |
3003 | is an explicit use of a hard register, then we must reload the | |
3004 | other non-hard register operand. */ | |
3005 | if (HARD_REGISTER_P (operand_reg[i]) | |
3006 | || (first_conflict_j == last_conflict_j | |
3007 | && operand_reg[last_conflict_j] != NULL_RTX | |
3008 | && !curr_alt_match_win[last_conflict_j] | |
3009 | && !HARD_REGISTER_P (operand_reg[last_conflict_j]))) | |
89c2edcf | 3010 | { |
8c3a9b39 | 3011 | curr_alt_win[last_conflict_j] = false; |
3012 | curr_alt_dont_inherit_ops[curr_alt_dont_inherit_ops_num++] | |
3013 | = last_conflict_j; | |
89c2edcf | 3014 | losers++; |
34575461 | 3015 | if (lra_dump_file != NULL) |
3016 | fprintf | |
3017 | (lra_dump_file, | |
3018 | " %d Conflict early clobber reload: reject--\n", | |
3019 | i); | |
89c2edcf | 3020 | } |
c6a6cdaa | 3021 | else |
3022 | { | |
89c2edcf | 3023 | /* We need to reload early clobbered register and the |
3024 | matched registers. */ | |
3025 | for (j = 0; j < n_operands; j++) | |
3026 | if (curr_alt_matches[j] == i) | |
3027 | { | |
3028 | curr_alt_match_win[j] = false; | |
3029 | losers++; | |
3030 | overall += LRA_LOSER_COST_FACTOR; | |
3031 | } | |
3032 | if (! curr_alt_match_win[i]) | |
3033 | curr_alt_dont_inherit_ops[curr_alt_dont_inherit_ops_num++] = i; | |
3034 | else | |
3035 | { | |
3036 | /* Remember pseudos used for match reloads are never | |
3037 | inherited. */ | |
3038 | lra_assert (curr_alt_matches[i] >= 0); | |
3039 | curr_alt_win[curr_alt_matches[i]] = false; | |
3040 | } | |
3041 | curr_alt_win[i] = curr_alt_match_win[i] = false; | |
3042 | losers++; | |
34575461 | 3043 | if (lra_dump_file != NULL) |
3044 | fprintf | |
3045 | (lra_dump_file, | |
19efce70 | 3046 | " %d Matched conflict early clobber reloads: " |
34575461 | 3047 | "reject--\n", |
3048 | i); | |
3dfcf76a | 3049 | } |
3050 | /* Early clobber was already reflected in REJECT. */ | |
3051 | if (!matching_early_clobber[i]) | |
3052 | { | |
3053 | lra_assert (reject > 0); | |
f7c98bb1 | 3054 | reject--; |
3dfcf76a | 3055 | matching_early_clobber[i] = 1; |
c6a6cdaa | 3056 | } |
3dfcf76a | 3057 | overall += LRA_LOSER_COST_FACTOR - 1; |
c6a6cdaa | 3058 | } |
f7c98bb1 | 3059 | if (lra_dump_file != NULL) |
273c330a | 3060 | fprintf (lra_dump_file, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n", |
3061 | nalt, overall, losers, reload_nregs); | |
f7c98bb1 | 3062 | |
c6a6cdaa | 3063 | /* If this alternative can be made to work by reloading, and it |
3064 | needs less reloading than the others checked so far, record | |
3065 | it as the chosen goal for reloading. */ | |
3066 | if ((best_losers != 0 && losers == 0) | |
3067 | || (((best_losers == 0 && losers == 0) | |
3068 | || (best_losers != 0 && losers != 0)) | |
3069 | && (best_overall > overall | |
3070 | || (best_overall == overall | |
3071 | /* If the cost of the reloads is the same, | |
3072 | prefer alternative which requires minimal | |
273c330a | 3073 | number of reload regs. */ |
3074 | && (reload_nregs < best_reload_nregs | |
3075 | || (reload_nregs == best_reload_nregs | |
04dda2a2 | 3076 | && (best_reload_sum < reload_sum |
3077 | || (best_reload_sum == reload_sum | |
3078 | && nalt < goal_alt_number)))))))) | |
c6a6cdaa | 3079 | { |
3080 | for (nop = 0; nop < n_operands; nop++) | |
3081 | { | |
3082 | goal_alt_win[nop] = curr_alt_win[nop]; | |
3083 | goal_alt_match_win[nop] = curr_alt_match_win[nop]; | |
3084 | goal_alt_matches[nop] = curr_alt_matches[nop]; | |
3085 | goal_alt[nop] = curr_alt[nop]; | |
3086 | goal_alt_offmemok[nop] = curr_alt_offmemok[nop]; | |
3087 | } | |
3088 | goal_alt_dont_inherit_ops_num = curr_alt_dont_inherit_ops_num; | |
3089 | for (nop = 0; nop < curr_alt_dont_inherit_ops_num; nop++) | |
3090 | goal_alt_dont_inherit_ops[nop] = curr_alt_dont_inherit_ops[nop]; | |
3091 | goal_alt_swapped = curr_swapped; | |
3092 | best_overall = overall; | |
3093 | best_losers = losers; | |
c6a6cdaa | 3094 | best_reload_nregs = reload_nregs; |
3095 | best_reload_sum = reload_sum; | |
3096 | goal_alt_number = nalt; | |
3097 | } | |
3098 | if (losers == 0) | |
3099 | /* Everything is satisfied. Do not process alternatives | |
1a8f8886 | 3100 | anymore. */ |
c6a6cdaa | 3101 | break; |
3102 | fail: | |
3103 | ; | |
3104 | } | |
3105 | return ok_p; | |
3106 | } | |
3107 | ||
d03288b6 | 3108 | /* Make reload base reg from address AD. */ |
3109 | static rtx | |
3110 | base_to_reg (struct address_info *ad) | |
3111 | { | |
3112 | enum reg_class cl; | |
3113 | int code = -1; | |
3114 | rtx new_inner = NULL_RTX; | |
3115 | rtx new_reg = NULL_RTX; | |
57c26b3a | 3116 | rtx_insn *insn; |
3117 | rtx_insn *last_insn = get_last_insn(); | |
d03288b6 | 3118 | |
0508f466 | 3119 | lra_assert (ad->disp == ad->disp_term); |
d03288b6 | 3120 | cl = base_reg_class (ad->mode, ad->as, ad->base_outer_code, |
3121 | get_index_code (ad)); | |
0508f466 | 3122 | new_reg = lra_create_new_reg (GET_MODE (*ad->base), NULL_RTX, |
d03288b6 | 3123 | cl, "base"); |
3124 | new_inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), new_reg, | |
3125 | ad->disp_term == NULL | |
0508f466 | 3126 | ? const0_rtx |
d03288b6 | 3127 | : *ad->disp_term); |
3128 | if (!valid_address_p (ad->mode, new_inner, ad->as)) | |
3129 | return NULL_RTX; | |
0508f466 | 3130 | insn = emit_insn (gen_rtx_SET (new_reg, *ad->base)); |
d03288b6 | 3131 | code = recog_memoized (insn); |
3132 | if (code < 0) | |
3133 | { | |
3134 | delete_insns_since (last_insn); | |
3135 | return NULL_RTX; | |
3136 | } | |
3137 | ||
3138 | return new_inner; | |
3139 | } | |
3140 | ||
6cc181b3 | 3141 | /* Make reload base reg + DISP from address AD. Return the new pseudo. */ |
c6a6cdaa | 3142 | static rtx |
6cc181b3 | 3143 | base_plus_disp_to_reg (struct address_info *ad, rtx disp) |
c6a6cdaa | 3144 | { |
3145 | enum reg_class cl; | |
3146 | rtx new_reg; | |
3147 | ||
6cc181b3 | 3148 | lra_assert (ad->base == ad->base_term); |
1efe9e9d | 3149 | cl = base_reg_class (ad->mode, ad->as, ad->base_outer_code, |
3150 | get_index_code (ad)); | |
3151 | new_reg = lra_create_new_reg (GET_MODE (*ad->base_term), NULL_RTX, | |
3152 | cl, "base + disp"); | |
6cc181b3 | 3153 | lra_emit_add (new_reg, *ad->base_term, disp); |
c6a6cdaa | 3154 | return new_reg; |
3155 | } | |
3156 | ||
28f7a2af | 3157 | /* Make reload of index part of address AD. Return the new |
3158 | pseudo. */ | |
3159 | static rtx | |
3160 | index_part_to_reg (struct address_info *ad) | |
3161 | { | |
3162 | rtx new_reg; | |
3163 | ||
3164 | new_reg = lra_create_new_reg (GET_MODE (*ad->index), NULL_RTX, | |
3165 | INDEX_REG_CLASS, "index term"); | |
3166 | expand_mult (GET_MODE (*ad->index), *ad->index_term, | |
3167 | GEN_INT (get_index_scale (ad)), new_reg, 1); | |
3168 | return new_reg; | |
3169 | } | |
3170 | ||
1efe9e9d | 3171 | /* Return true if we can add a displacement to address AD, even if that |
3172 | makes the address invalid. The fix-up code requires any new address | |
3173 | to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */ | |
809320f0 | 3174 | static bool |
1efe9e9d | 3175 | can_add_disp_p (struct address_info *ad) |
809320f0 | 3176 | { |
1efe9e9d | 3177 | return (!ad->autoinc_p |
3178 | && ad->segment == NULL | |
3179 | && ad->base == ad->base_term | |
3180 | && ad->disp == ad->disp_term); | |
809320f0 | 3181 | } |
3182 | ||
1efe9e9d | 3183 | /* Make equiv substitution in address AD. Return true if a substitution |
3184 | was made. */ | |
c6a6cdaa | 3185 | static bool |
1efe9e9d | 3186 | equiv_address_substitution (struct address_info *ad) |
c6a6cdaa | 3187 | { |
1efe9e9d | 3188 | rtx base_reg, new_base_reg, index_reg, new_index_reg, *base_term, *index_term; |
a4686d0a | 3189 | poly_int64 disp; |
3190 | HOST_WIDE_INT scale; | |
c6a6cdaa | 3191 | bool change_p; |
3192 | ||
1efe9e9d | 3193 | base_term = strip_subreg (ad->base_term); |
3194 | if (base_term == NULL) | |
c6a6cdaa | 3195 | base_reg = new_base_reg = NULL_RTX; |
3196 | else | |
3197 | { | |
1efe9e9d | 3198 | base_reg = *base_term; |
3b3a5e5f | 3199 | new_base_reg = get_equiv_with_elimination (base_reg, curr_insn); |
c6a6cdaa | 3200 | } |
1efe9e9d | 3201 | index_term = strip_subreg (ad->index_term); |
3202 | if (index_term == NULL) | |
c6a6cdaa | 3203 | index_reg = new_index_reg = NULL_RTX; |
3204 | else | |
3205 | { | |
1efe9e9d | 3206 | index_reg = *index_term; |
3b3a5e5f | 3207 | new_index_reg = get_equiv_with_elimination (index_reg, curr_insn); |
c6a6cdaa | 3208 | } |
3209 | if (base_reg == new_base_reg && index_reg == new_index_reg) | |
3210 | return false; | |
3211 | disp = 0; | |
3212 | change_p = false; | |
3213 | if (lra_dump_file != NULL) | |
3214 | { | |
3215 | fprintf (lra_dump_file, "Changing address in insn %d ", | |
3216 | INSN_UID (curr_insn)); | |
6dde9719 | 3217 | dump_value_slim (lra_dump_file, *ad->outer, 1); |
c6a6cdaa | 3218 | } |
3219 | if (base_reg != new_base_reg) | |
3220 | { | |
a4686d0a | 3221 | poly_int64 offset; |
c6a6cdaa | 3222 | if (REG_P (new_base_reg)) |
3223 | { | |
1efe9e9d | 3224 | *base_term = new_base_reg; |
c6a6cdaa | 3225 | change_p = true; |
3226 | } | |
3227 | else if (GET_CODE (new_base_reg) == PLUS | |
3228 | && REG_P (XEXP (new_base_reg, 0)) | |
a4686d0a | 3229 | && poly_int_rtx_p (XEXP (new_base_reg, 1), &offset) |
1efe9e9d | 3230 | && can_add_disp_p (ad)) |
c6a6cdaa | 3231 | { |
a4686d0a | 3232 | disp += offset; |
1efe9e9d | 3233 | *base_term = XEXP (new_base_reg, 0); |
c6a6cdaa | 3234 | change_p = true; |
3235 | } | |
1efe9e9d | 3236 | if (ad->base_term2 != NULL) |
3237 | *ad->base_term2 = *ad->base_term; | |
c6a6cdaa | 3238 | } |
c6a6cdaa | 3239 | if (index_reg != new_index_reg) |
3240 | { | |
a4686d0a | 3241 | poly_int64 offset; |
c6a6cdaa | 3242 | if (REG_P (new_index_reg)) |
3243 | { | |
1efe9e9d | 3244 | *index_term = new_index_reg; |
c6a6cdaa | 3245 | change_p = true; |
3246 | } | |
3247 | else if (GET_CODE (new_index_reg) == PLUS | |
3248 | && REG_P (XEXP (new_index_reg, 0)) | |
a4686d0a | 3249 | && poly_int_rtx_p (XEXP (new_index_reg, 1), &offset) |
1efe9e9d | 3250 | && can_add_disp_p (ad) |
809320f0 | 3251 | && (scale = get_index_scale (ad))) |
c6a6cdaa | 3252 | { |
a4686d0a | 3253 | disp += offset * scale; |
1efe9e9d | 3254 | *index_term = XEXP (new_index_reg, 0); |
c6a6cdaa | 3255 | change_p = true; |
3256 | } | |
3257 | } | |
a4686d0a | 3258 | if (maybe_ne (disp, 0)) |
c6a6cdaa | 3259 | { |
1efe9e9d | 3260 | if (ad->disp != NULL) |
3261 | *ad->disp = plus_constant (GET_MODE (*ad->inner), *ad->disp, disp); | |
c6a6cdaa | 3262 | else |
3263 | { | |
1efe9e9d | 3264 | *ad->inner = plus_constant (GET_MODE (*ad->inner), *ad->inner, disp); |
3265 | update_address (ad); | |
c6a6cdaa | 3266 | } |
3267 | change_p = true; | |
3268 | } | |
3269 | if (lra_dump_file != NULL) | |
3270 | { | |
3271 | if (! change_p) | |
3272 | fprintf (lra_dump_file, " -- no change\n"); | |
3273 | else | |
3274 | { | |
3275 | fprintf (lra_dump_file, " on equiv "); | |
6dde9719 | 3276 | dump_value_slim (lra_dump_file, *ad->outer, 1); |
c6a6cdaa | 3277 | fprintf (lra_dump_file, "\n"); |
3278 | } | |
3279 | } | |
3280 | return change_p; | |
3281 | } | |
3282 | ||
497ba60f | 3283 | /* Major function to make reloads for an address in operand NOP or |
3284 | check its correctness (If CHECK_ONLY_P is true). The supported | |
3285 | cases are: | |
d9b69682 | 3286 | |
c625778b | 3287 | 1) an address that existed before LRA started, at which point it |
3288 | must have been valid. These addresses are subject to elimination | |
3289 | and may have become invalid due to the elimination offset being out | |
3290 | of range. | |
d9b69682 | 3291 | |
c625778b | 3292 | 2) an address created by forcing a constant to memory |
3293 | (force_const_to_mem). The initial form of these addresses might | |
3294 | not be valid, and it is this function's job to make them valid. | |
d9b69682 | 3295 | |
3296 | 3) a frame address formed from a register and a (possibly zero) | |
c625778b | 3297 | constant offset. As above, these addresses might not be valid and |
3298 | this function must make them so. | |
d9b69682 | 3299 | |
3300 | Add reloads to the lists *BEFORE and *AFTER. We might need to add | |
c6a6cdaa | 3301 | reloads to *AFTER because of inc/dec, {pre, post} modify in the |
dcd5393f | 3302 | address. Return true for any RTL change. |
3303 | ||
3304 | The function is a helper function which does not produce all | |
497ba60f | 3305 | transformations (when CHECK_ONLY_P is false) which can be |
3306 | necessary. It does just basic steps. To do all necessary | |
3307 | transformations use function process_address. */ | |
c6a6cdaa | 3308 | static bool |
497ba60f | 3309 | process_address_1 (int nop, bool check_only_p, |
3310 | rtx_insn **before, rtx_insn **after) | |
c6a6cdaa | 3311 | { |
1efe9e9d | 3312 | struct address_info ad; |
3313 | rtx new_reg; | |
72234ee9 | 3314 | HOST_WIDE_INT scale; |
c6a6cdaa | 3315 | rtx op = *curr_id->operand_loc[nop]; |
3316 | const char *constraint = curr_static_id->operand[nop].constraint; | |
79bc09fb | 3317 | enum constraint_num cn = lookup_constraint (constraint); |
497ba60f | 3318 | bool change_p = false; |
c6a6cdaa | 3319 | |
556c2dd1 | 3320 | if (MEM_P (op) |
3321 | && GET_MODE (op) == BLKmode | |
3322 | && GET_CODE (XEXP (op, 0)) == SCRATCH) | |
3323 | return false; | |
3324 | ||
afca8a73 | 3325 | if (insn_extra_address_constraint (cn) |
3326 | /* When we find an asm operand with an address constraint that | |
3327 | doesn't satisfy address_operand to begin with, we clear | |
3328 | is_address, so that we don't try to make a non-address fit. | |
3329 | If the asm statement got this far, it's because other | |
3330 | constraints are available, and we'll use them, disregarding | |
3331 | the unsatisfiable address ones. */ | |
3332 | && curr_static_id->operand[nop].is_address) | |
1efe9e9d | 3333 | decompose_lea_address (&ad, curr_id->operand_loc[nop]); |
efd3cce2 | 3334 | /* Do not attempt to decompose arbitrary addresses generated by combine |
3335 | for asm operands with loose constraints, e.g 'X'. */ | |
3336 | else if (MEM_P (op) | |
5e0f6ab6 | 3337 | && !(INSN_CODE (curr_insn) < 0 |
3338 | && get_constraint_type (cn) == CT_FIXED_FORM | |
efd3cce2 | 3339 | && constraint_satisfied_p (op, cn))) |
1efe9e9d | 3340 | decompose_mem_address (&ad, op); |
c6a6cdaa | 3341 | else if (GET_CODE (op) == SUBREG |
3342 | && MEM_P (SUBREG_REG (op))) | |
1efe9e9d | 3343 | decompose_mem_address (&ad, SUBREG_REG (op)); |
c6a6cdaa | 3344 | else |
3345 | return false; | |
382efce6 | 3346 | /* If INDEX_REG_CLASS is assigned to base_term already and isn't to |
3347 | index_term, swap them so to avoid assigning INDEX_REG_CLASS to both | |
3348 | when INDEX_REG_CLASS is a single register class. */ | |
3349 | if (ad.base_term != NULL | |
3350 | && ad.index_term != NULL | |
3351 | && ira_class_hard_regs_num[INDEX_REG_CLASS] == 1 | |
3352 | && REG_P (*ad.base_term) | |
3353 | && REG_P (*ad.index_term) | |
3354 | && in_class_p (*ad.base_term, INDEX_REG_CLASS, NULL) | |
3355 | && ! in_class_p (*ad.index_term, INDEX_REG_CLASS, NULL)) | |
3356 | { | |
3357 | std::swap (ad.base, ad.index); | |
3358 | std::swap (ad.base_term, ad.index_term); | |
3359 | } | |
497ba60f | 3360 | if (! check_only_p) |
3361 | change_p = equiv_address_substitution (&ad); | |
1efe9e9d | 3362 | if (ad.base_term != NULL |
c6a6cdaa | 3363 | && (process_addr_reg |
497ba60f | 3364 | (ad.base_term, check_only_p, before, |
1efe9e9d | 3365 | (ad.autoinc_p |
3366 | && !(REG_P (*ad.base_term) | |
3367 | && find_regno_note (curr_insn, REG_DEAD, | |
3368 | REGNO (*ad.base_term)) != NULL_RTX) | |
c6a6cdaa | 3369 | ? after : NULL), |
1efe9e9d | 3370 | base_reg_class (ad.mode, ad.as, ad.base_outer_code, |
3371 | get_index_code (&ad))))) | |
c6a6cdaa | 3372 | { |
3373 | change_p = true; | |
1efe9e9d | 3374 | if (ad.base_term2 != NULL) |
3375 | *ad.base_term2 = *ad.base_term; | |
c6a6cdaa | 3376 | } |
1efe9e9d | 3377 | if (ad.index_term != NULL |
497ba60f | 3378 | && process_addr_reg (ad.index_term, check_only_p, |
3379 | before, NULL, INDEX_REG_CLASS)) | |
c6a6cdaa | 3380 | change_p = true; |
3381 | ||
79bc09fb | 3382 | /* Target hooks sometimes don't treat extra-constraint addresses as |
3383 | legitimate address_operands, so handle them specially. */ | |
69449463 | 3384 | if (insn_extra_address_constraint (cn) |
79bc09fb | 3385 | && satisfies_address_constraint_p (&ad, cn)) |
ea99c7a1 | 3386 | return change_p; |
ea99c7a1 | 3387 | |
497ba60f | 3388 | if (check_only_p) |
3389 | return change_p; | |
3390 | ||
1efe9e9d | 3391 | /* There are three cases where the shape of *AD.INNER may now be invalid: |
d9b69682 | 3392 | |
3393 | 1) the original address was valid, but either elimination or | |
c625778b | 3394 | equiv_address_substitution was applied and that made |
3395 | the address invalid. | |
d9b69682 | 3396 | |
3397 | 2) the address is an invalid symbolic address created by | |
c625778b | 3398 | force_const_to_mem. |
d9b69682 | 3399 | |
3400 | 3) the address is a frame address with an invalid offset. | |
3401 | ||
d03288b6 | 3402 | 4) the address is a frame address with an invalid base. |
3403 | ||
ea99c7a1 | 3404 | All these cases involve a non-autoinc address, so there is no |
3405 | point revalidating other types. */ | |
3406 | if (ad.autoinc_p || valid_address_p (&ad)) | |
c6a6cdaa | 3407 | return change_p; |
3408 | ||
d9b69682 | 3409 | /* Any index existed before LRA started, so we can assume that the |
3410 | presence and shape of the index is valid. */ | |
c6a6cdaa | 3411 | push_to_sequence (*before); |
ea99c7a1 | 3412 | lra_assert (ad.disp == ad.disp_term); |
1efe9e9d | 3413 | if (ad.base == NULL) |
c6a6cdaa | 3414 | { |
1efe9e9d | 3415 | if (ad.index == NULL) |
c6a6cdaa | 3416 | { |
401bd0c8 | 3417 | rtx_insn *insn; |
3418 | rtx_insn *last = get_last_insn (); | |
c6a6cdaa | 3419 | int code = -1; |
1efe9e9d | 3420 | enum reg_class cl = base_reg_class (ad.mode, ad.as, |
3421 | SCRATCH, SCRATCH); | |
ea99c7a1 | 3422 | rtx addr = *ad.inner; |
1efe9e9d | 3423 | |
ea99c7a1 | 3424 | new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "addr"); |
6cc3d6ec | 3425 | if (HAVE_lo_sum) |
3426 | { | |
6cc3d6ec | 3427 | /* addr => lo_sum (new_base, addr), case (2) above. */ |
3428 | insn = emit_insn (gen_rtx_SET | |
3429 | (new_reg, | |
3430 | gen_rtx_HIGH (Pmode, copy_rtx (addr)))); | |
3431 | code = recog_memoized (insn); | |
3432 | if (code >= 0) | |
3433 | { | |
3434 | *ad.inner = gen_rtx_LO_SUM (Pmode, new_reg, addr); | |
3435 | if (! valid_address_p (ad.mode, *ad.outer, ad.as)) | |
3436 | { | |
3437 | /* Try to put lo_sum into register. */ | |
3438 | insn = emit_insn (gen_rtx_SET | |
3439 | (new_reg, | |
3440 | gen_rtx_LO_SUM (Pmode, new_reg, addr))); | |
3441 | code = recog_memoized (insn); | |
3442 | if (code >= 0) | |
3443 | { | |
3444 | *ad.inner = new_reg; | |
3445 | if (! valid_address_p (ad.mode, *ad.outer, ad.as)) | |
3446 | { | |
3447 | *ad.inner = addr; | |
3448 | code = -1; | |
3449 | } | |
3450 | } | |
3451 | ||
3452 | } | |
3453 | } | |
3454 | if (code < 0) | |
3455 | delete_insns_since (last); | |
3456 | } | |
3457 | ||
c6a6cdaa | 3458 | if (code < 0) |
3459 | { | |
ea99c7a1 | 3460 | /* addr => new_base, case (2) above. */ |
3461 | lra_emit_move (new_reg, addr); | |
401bd0c8 | 3462 | |
3463 | for (insn = last == NULL_RTX ? get_insns () : NEXT_INSN (last); | |
3464 | insn != NULL_RTX; | |
3465 | insn = NEXT_INSN (insn)) | |
3466 | if (recog_memoized (insn) < 0) | |
3467 | break; | |
3468 | if (insn != NULL_RTX) | |
3469 | { | |
3470 | /* Do nothing if we cannot generate right insns. | |
67cf9b55 | 3471 | This is analogous to reload pass behavior. */ |
401bd0c8 | 3472 | delete_insns_since (last); |
3473 | end_sequence (); | |
3474 | return false; | |
3475 | } | |
ea99c7a1 | 3476 | *ad.inner = new_reg; |
c6a6cdaa | 3477 | } |
3478 | } | |
3479 | else | |
3480 | { | |
d9b69682 | 3481 | /* index * scale + disp => new base + index * scale, |
3482 | case (1) above. */ | |
1efe9e9d | 3483 | enum reg_class cl = base_reg_class (ad.mode, ad.as, PLUS, |
3484 | GET_CODE (*ad.index)); | |
c6a6cdaa | 3485 | |
3486 | lra_assert (INDEX_REG_CLASS != NO_REGS); | |
3487 | new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "disp"); | |
1efe9e9d | 3488 | lra_emit_move (new_reg, *ad.disp); |
3489 | *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), | |
3490 | new_reg, *ad.index); | |
c6a6cdaa | 3491 | } |
3492 | } | |
1efe9e9d | 3493 | else if (ad.index == NULL) |
c6a6cdaa | 3494 | { |
c625778b | 3495 | int regno; |
3496 | enum reg_class cl; | |
7f836b57 | 3497 | rtx set; |
3498 | rtx_insn *insns, *last_insn; | |
d03288b6 | 3499 | /* Try to reload base into register only if the base is invalid |
3500 | for the address but with valid offset, case (4) above. */ | |
3501 | start_sequence (); | |
3502 | new_reg = base_to_reg (&ad); | |
3503 | ||
d9b69682 | 3504 | /* base + disp => new base, cases (1) and (3) above. */ |
c6a6cdaa | 3505 | /* Another option would be to reload the displacement into an |
3506 | index register. However, postreload has code to optimize | |
3507 | address reloads that have the same base and different | |
3508 | displacements, so reloading into an index register would | |
3509 | not necessarily be a win. */ | |
d03288b6 | 3510 | if (new_reg == NULL_RTX) |
6cc181b3 | 3511 | { |
3512 | /* See if the target can split the displacement into a | |
3513 | legitimate new displacement from a local anchor. */ | |
3514 | gcc_assert (ad.disp == ad.disp_term); | |
3515 | poly_int64 orig_offset; | |
3516 | rtx offset1, offset2; | |
3517 | if (poly_int_rtx_p (*ad.disp, &orig_offset) | |
3518 | && targetm.legitimize_address_displacement (&offset1, &offset2, | |
3519 | orig_offset, | |
3520 | ad.mode)) | |
3521 | { | |
3522 | new_reg = base_plus_disp_to_reg (&ad, offset1); | |
3523 | new_reg = gen_rtx_PLUS (GET_MODE (new_reg), new_reg, offset2); | |
3524 | } | |
3525 | else | |
3526 | new_reg = base_plus_disp_to_reg (&ad, *ad.disp); | |
3527 | } | |
c625778b | 3528 | insns = get_insns (); |
3529 | last_insn = get_last_insn (); | |
3530 | /* If we generated at least two insns, try last insn source as | |
3531 | an address. If we succeed, we generate one less insn. */ | |
6cc181b3 | 3532 | if (REG_P (new_reg) |
3533 | && last_insn != insns | |
3534 | && (set = single_set (last_insn)) != NULL_RTX | |
c625778b | 3535 | && GET_CODE (SET_SRC (set)) == PLUS |
3536 | && REG_P (XEXP (SET_SRC (set), 0)) | |
3537 | && CONSTANT_P (XEXP (SET_SRC (set), 1))) | |
3538 | { | |
3539 | *ad.inner = SET_SRC (set); | |
3540 | if (valid_address_p (ad.mode, *ad.outer, ad.as)) | |
3541 | { | |
3542 | *ad.base_term = XEXP (SET_SRC (set), 0); | |
3543 | *ad.disp_term = XEXP (SET_SRC (set), 1); | |
3544 | cl = base_reg_class (ad.mode, ad.as, ad.base_outer_code, | |
3545 | get_index_code (&ad)); | |
3546 | regno = REGNO (*ad.base_term); | |
3547 | if (regno >= FIRST_PSEUDO_REGISTER | |
3548 | && cl != lra_get_allocno_class (regno)) | |
7619e612 | 3549 | lra_change_class (regno, cl, " Change to", true); |
c625778b | 3550 | new_reg = SET_SRC (set); |
3551 | delete_insns_since (PREV_INSN (last_insn)); | |
3552 | } | |
3553 | } | |
3554 | end_sequence (); | |
3555 | emit_insn (insns); | |
1efe9e9d | 3556 | *ad.inner = new_reg; |
c6a6cdaa | 3557 | } |
28f7a2af | 3558 | else if (ad.disp_term != NULL) |
c6a6cdaa | 3559 | { |
d9b69682 | 3560 | /* base + scale * index + disp => new base + scale * index, |
3561 | case (1) above. */ | |
6cc181b3 | 3562 | gcc_assert (ad.disp == ad.disp_term); |
3563 | new_reg = base_plus_disp_to_reg (&ad, *ad.disp); | |
1efe9e9d | 3564 | *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), |
3565 | new_reg, *ad.index); | |
c6a6cdaa | 3566 | } |
72234ee9 | 3567 | else if ((scale = get_index_scale (&ad)) == 1) |
bbf73e27 | 3568 | { |
3569 | /* The last transformation to one reg will be made in | |
3570 | curr_insn_transform function. */ | |
3571 | end_sequence (); | |
3572 | return false; | |
3573 | } | |
72234ee9 | 3574 | else if (scale != 0) |
28f7a2af | 3575 | { |
3576 | /* base + scale * index => base + new_reg, | |
3577 | case (1) above. | |
3578 | Index part of address may become invalid. For example, we | |
3579 | changed pseudo on the equivalent memory and a subreg of the | |
3580 | pseudo onto the memory of different mode for which the scale is | |
3581 | prohibitted. */ | |
3582 | new_reg = index_part_to_reg (&ad); | |
3583 | *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), | |
3584 | *ad.base_term, new_reg); | |
3585 | } | |
72234ee9 | 3586 | else |
3587 | { | |
3588 | enum reg_class cl = base_reg_class (ad.mode, ad.as, | |
3589 | SCRATCH, SCRATCH); | |
3590 | rtx addr = *ad.inner; | |
3591 | ||
3592 | new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "addr"); | |
3593 | /* addr => new_base. */ | |
3594 | lra_emit_move (new_reg, addr); | |
3595 | *ad.inner = new_reg; | |
3596 | } | |
c6a6cdaa | 3597 | *before = get_insns (); |
3598 | end_sequence (); | |
3599 | return true; | |
3600 | } | |
3601 | ||
497ba60f | 3602 | /* If CHECK_ONLY_P is false, do address reloads until it is necessary. |
3603 | Use process_address_1 as a helper function. Return true for any | |
3604 | RTL changes. | |
3605 | ||
3606 | If CHECK_ONLY_P is true, just check address correctness. Return | |
3607 | false if the address correct. */ | |
dcd5393f | 3608 | static bool |
497ba60f | 3609 | process_address (int nop, bool check_only_p, |
3610 | rtx_insn **before, rtx_insn **after) | |
dcd5393f | 3611 | { |
3612 | bool res = false; | |
3613 | ||
497ba60f | 3614 | while (process_address_1 (nop, check_only_p, before, after)) |
3615 | { | |
3616 | if (check_only_p) | |
3617 | return true; | |
3618 | res = true; | |
3619 | } | |
dcd5393f | 3620 | return res; |
3621 | } | |
3622 | ||
c6a6cdaa | 3623 | /* Emit insns to reload VALUE into a new register. VALUE is an |
3624 | auto-increment or auto-decrement RTX whose operand is a register or | |
3625 | memory location; so reloading involves incrementing that location. | |
3626 | IN is either identical to VALUE, or some cheaper place to reload | |
3627 | value being incremented/decremented from. | |
3628 | ||
3629 | INC_AMOUNT is the number to increment or decrement by (always | |
3630 | positive and ignored for POST_MODIFY/PRE_MODIFY). | |
3631 | ||
3632 | Return pseudo containing the result. */ | |
3633 | static rtx | |
3173f31b | 3634 | emit_inc (enum reg_class new_rclass, rtx in, rtx value, poly_int64 inc_amount) |
c6a6cdaa | 3635 | { |
3636 | /* REG or MEM to be copied and incremented. */ | |
3637 | rtx incloc = XEXP (value, 0); | |
3638 | /* Nonzero if increment after copying. */ | |
3639 | int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC | |
3640 | || GET_CODE (value) == POST_MODIFY); | |
7f836b57 | 3641 | rtx_insn *last; |
c6a6cdaa | 3642 | rtx inc; |
ed3e6e5d | 3643 | rtx_insn *add_insn; |
c6a6cdaa | 3644 | int code; |
3645 | rtx real_in = in == value ? incloc : in; | |
3646 | rtx result; | |
3647 | bool plus_p = true; | |
3648 | ||
3649 | if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY) | |
3650 | { | |
3651 | lra_assert (GET_CODE (XEXP (value, 1)) == PLUS | |
3652 | || GET_CODE (XEXP (value, 1)) == MINUS); | |
3653 | lra_assert (rtx_equal_p (XEXP (XEXP (value, 1), 0), XEXP (value, 0))); | |
3654 | plus_p = GET_CODE (XEXP (value, 1)) == PLUS; | |
3655 | inc = XEXP (XEXP (value, 1), 1); | |
3656 | } | |
3657 | else | |
3658 | { | |
3659 | if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC) | |
3660 | inc_amount = -inc_amount; | |
3661 | ||
3173f31b | 3662 | inc = gen_int_mode (inc_amount, GET_MODE (value)); |
c6a6cdaa | 3663 | } |
3664 | ||
3665 | if (! post && REG_P (incloc)) | |
3666 | result = incloc; | |
3667 | else | |
3668 | result = lra_create_new_reg (GET_MODE (value), value, new_rclass, | |
3669 | "INC/DEC result"); | |
3670 | ||
3671 | if (real_in != result) | |
3672 | { | |
3673 | /* First copy the location to the result register. */ | |
3674 | lra_assert (REG_P (result)); | |
3675 | emit_insn (gen_move_insn (result, real_in)); | |
3676 | } | |
3677 | ||
3678 | /* We suppose that there are insns to add/sub with the constant | |
3679 | increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the | |
3680 | old reload worked with this assumption. If the assumption | |
3681 | becomes wrong, we should use approach in function | |
3682 | base_plus_disp_to_reg. */ | |
3683 | if (in == value) | |
3684 | { | |
3685 | /* See if we can directly increment INCLOC. */ | |
3686 | last = get_last_insn (); | |
3687 | add_insn = emit_insn (plus_p | |
3688 | ? gen_add2_insn (incloc, inc) | |
3689 | : gen_sub2_insn (incloc, inc)); | |
3690 | ||
3691 | code = recog_memoized (add_insn); | |
3692 | if (code >= 0) | |
3693 | { | |
3694 | if (! post && result != incloc) | |
3695 | emit_insn (gen_move_insn (result, incloc)); | |
3696 | return result; | |
3697 | } | |
3698 | delete_insns_since (last); | |
3699 | } | |
3700 | ||
3701 | /* If couldn't do the increment directly, must increment in RESULT. | |
3702 | The way we do this depends on whether this is pre- or | |
3703 | post-increment. For pre-increment, copy INCLOC to the reload | |
3704 | register, increment it there, then save back. */ | |
3705 | if (! post) | |
3706 | { | |
3707 | if (real_in != result) | |
3708 | emit_insn (gen_move_insn (result, real_in)); | |
3709 | if (plus_p) | |
3710 | emit_insn (gen_add2_insn (result, inc)); | |
3711 | else | |
3712 | emit_insn (gen_sub2_insn (result, inc)); | |
3713 | if (result != incloc) | |
3714 | emit_insn (gen_move_insn (incloc, result)); | |
3715 | } | |
3716 | else | |
3717 | { | |
3718 | /* Post-increment. | |
3719 | ||
3720 | Because this might be a jump insn or a compare, and because | |
3721 | RESULT may not be available after the insn in an input | |
3722 | reload, we must do the incrementing before the insn being | |
3723 | reloaded for. | |
3724 | ||
3725 | We have already copied IN to RESULT. Increment the copy in | |
3726 | RESULT, save that back, then decrement RESULT so it has | |
3727 | the original value. */ | |
3728 | if (plus_p) | |
3729 | emit_insn (gen_add2_insn (result, inc)); | |
3730 | else | |
3731 | emit_insn (gen_sub2_insn (result, inc)); | |
3732 | emit_insn (gen_move_insn (incloc, result)); | |
3733 | /* Restore non-modified value for the result. We prefer this | |
3734 | way because it does not require an additional hard | |
3735 | register. */ | |
3736 | if (plus_p) | |
3737 | { | |
a4686d0a | 3738 | poly_int64 offset; |
3739 | if (poly_int_rtx_p (inc, &offset)) | |
d11aedc7 | 3740 | emit_insn (gen_add2_insn (result, |
a4686d0a | 3741 | gen_int_mode (-offset, |
d11aedc7 | 3742 | GET_MODE (result)))); |
c6a6cdaa | 3743 | else |
3744 | emit_insn (gen_sub2_insn (result, inc)); | |
3745 | } | |
3746 | else | |
3747 | emit_insn (gen_add2_insn (result, inc)); | |
3748 | } | |
3749 | return result; | |
3750 | } | |
3751 | ||
ea99c7a1 | 3752 | /* Return true if the current move insn does not need processing as we |
3753 | already know that it satisfies its constraints. */ | |
3754 | static bool | |
3755 | simple_move_p (void) | |
3756 | { | |
3757 | rtx dest, src; | |
3758 | enum reg_class dclass, sclass; | |
3759 | ||
3760 | lra_assert (curr_insn_set != NULL_RTX); | |
3761 | dest = SET_DEST (curr_insn_set); | |
3762 | src = SET_SRC (curr_insn_set); | |
532322d3 | 3763 | |
3764 | /* If the instruction has multiple sets we need to process it even if it | |
3765 | is single_set. This can happen if one or more of the SETs are dead. | |
3766 | See PR73650. */ | |
3767 | if (multiple_sets (curr_insn)) | |
3768 | return false; | |
3769 | ||
ea99c7a1 | 3770 | return ((dclass = get_op_class (dest)) != NO_REGS |
3771 | && (sclass = get_op_class (src)) != NO_REGS | |
3772 | /* The backend guarantees that register moves of cost 2 | |
3773 | never need reloads. */ | |
06d288a6 | 3774 | && targetm.register_move_cost (GET_MODE (src), sclass, dclass) == 2); |
ea99c7a1 | 3775 | } |
3776 | ||
c6a6cdaa | 3777 | /* Swap operands NOP and NOP + 1. */ |
3778 | static inline void | |
3779 | swap_operands (int nop) | |
3780 | { | |
dfcf26a5 | 3781 | std::swap (curr_operand_mode[nop], curr_operand_mode[nop + 1]); |
3782 | std::swap (original_subreg_reg_mode[nop], original_subreg_reg_mode[nop + 1]); | |
3783 | std::swap (*curr_id->operand_loc[nop], *curr_id->operand_loc[nop + 1]); | |
003000a4 | 3784 | std::swap (equiv_substition_p[nop], equiv_substition_p[nop + 1]); |
c6a6cdaa | 3785 | /* Swap the duplicates too. */ |
3786 | lra_update_dup (curr_id, nop); | |
3787 | lra_update_dup (curr_id, nop + 1); | |
3788 | } | |
3789 | ||
3790 | /* Main entry point of the constraint code: search the body of the | |
3791 | current insn to choose the best alternative. It is mimicking insn | |
3792 | alternative cost calculation model of former reload pass. That is | |
3793 | because machine descriptions were written to use this model. This | |
3794 | model can be changed in future. Make commutative operand exchange | |
3795 | if it is chosen. | |
3796 | ||
497ba60f | 3797 | if CHECK_ONLY_P is false, do RTL changes to satisfy the |
3798 | constraints. Return true if any change happened during function | |
3799 | call. | |
3800 | ||
3801 | If CHECK_ONLY_P is true then don't do any transformation. Just | |
3802 | check that the insn satisfies all constraints. If the insn does | |
3803 | not satisfy any constraint, return true. */ | |
c6a6cdaa | 3804 | static bool |
497ba60f | 3805 | curr_insn_transform (bool check_only_p) |
c6a6cdaa | 3806 | { |
3807 | int i, j, k; | |
3808 | int n_operands; | |
3809 | int n_alternatives; | |
dd083a02 | 3810 | int n_outputs; |
c6a6cdaa | 3811 | int commutative; |
3812 | signed char goal_alt_matched[MAX_RECOG_OPERANDS][MAX_RECOG_OPERANDS]; | |
aa3ce8ba | 3813 | signed char match_inputs[MAX_RECOG_OPERANDS + 1]; |
dd083a02 | 3814 | signed char outputs[MAX_RECOG_OPERANDS + 1]; |
7f836b57 | 3815 | rtx_insn *before, *after; |
c6a6cdaa | 3816 | bool alt_p = false; |
3817 | /* Flag that the insn has been changed through a transformation. */ | |
3818 | bool change_p; | |
3819 | bool sec_mem_p; | |
c6a6cdaa | 3820 | bool use_sec_mem_p; |
c6a6cdaa | 3821 | int max_regno_before; |
3822 | int reused_alternative_num; | |
3823 | ||
ea99c7a1 | 3824 | curr_insn_set = single_set (curr_insn); |
3825 | if (curr_insn_set != NULL_RTX && simple_move_p ()) | |
71d47a14 | 3826 | { |
3827 | /* We assume that the corresponding insn alternative has no | |
3828 | earlier clobbers. If it is not the case, don't define move | |
3829 | cost equal to 2 for the corresponding register classes. */ | |
3830 | lra_set_used_insn_alternative (curr_insn, LRA_NON_CLOBBERED_ALT); | |
3831 | return false; | |
3832 | } | |
ea99c7a1 | 3833 | |
c6a6cdaa | 3834 | no_input_reloads_p = no_output_reloads_p = false; |
3835 | goal_alt_number = -1; | |
ea99c7a1 | 3836 | change_p = sec_mem_p = false; |
c6a6cdaa | 3837 | /* JUMP_INSNs and CALL_INSNs are not allowed to have any output |
3838 | reloads; neither are insns that SET cc0. Insns that use CC0 are | |
3839 | not allowed to have any input reloads. */ | |
3840 | if (JUMP_P (curr_insn) || CALL_P (curr_insn)) | |
3841 | no_output_reloads_p = true; | |
3842 | ||
ff900b8e | 3843 | if (HAVE_cc0 && reg_referenced_p (cc0_rtx, PATTERN (curr_insn))) |
c6a6cdaa | 3844 | no_input_reloads_p = true; |
ff900b8e | 3845 | if (HAVE_cc0 && reg_set_p (cc0_rtx, PATTERN (curr_insn))) |
c6a6cdaa | 3846 | no_output_reloads_p = true; |
c6a6cdaa | 3847 | |
3848 | n_operands = curr_static_id->n_operands; | |
3849 | n_alternatives = curr_static_id->n_alternatives; | |
3850 | ||
3851 | /* Just return "no reloads" if insn has no operands with | |
3852 | constraints. */ | |
3853 | if (n_operands == 0 || n_alternatives == 0) | |
3854 | return false; | |
3855 | ||
3856 | max_regno_before = max_reg_num (); | |
3857 | ||
3858 | for (i = 0; i < n_operands; i++) | |
3859 | { | |
3860 | goal_alt_matched[i][0] = -1; | |
3861 | goal_alt_matches[i] = -1; | |
3862 | } | |
3863 | ||
3864 | commutative = curr_static_id->commutative; | |
3865 | ||
3866 | /* Now see what we need for pseudos that didn't get hard regs or got | |
3867 | the wrong kind of hard reg. For this, we must consider all the | |
3868 | operands together against the register constraints. */ | |
3869 | ||
4b3aba76 | 3870 | best_losers = best_overall = INT_MAX; |
273c330a | 3871 | best_reload_sum = 0; |
c6a6cdaa | 3872 | |
3873 | curr_swapped = false; | |
3874 | goal_alt_swapped = false; | |
3875 | ||
497ba60f | 3876 | if (! check_only_p) |
3877 | /* Make equivalence substitution and memory subreg elimination | |
3878 | before address processing because an address legitimacy can | |
3879 | depend on memory mode. */ | |
3880 | for (i = 0; i < n_operands; i++) | |
3881 | { | |
af121a86 | 3882 | rtx op, subst, old; |
497ba60f | 3883 | bool op_change_p = false; |
af121a86 | 3884 | |
3885 | if (curr_static_id->operand[i].is_operator) | |
3886 | continue; | |
497ba60f | 3887 | |
af121a86 | 3888 | old = op = *curr_id->operand_loc[i]; |
497ba60f | 3889 | if (GET_CODE (old) == SUBREG) |
3890 | old = SUBREG_REG (old); | |
3891 | subst = get_equiv_with_elimination (old, curr_insn); | |
1aae95ec | 3892 | original_subreg_reg_mode[i] = VOIDmode; |
003000a4 | 3893 | equiv_substition_p[i] = false; |
497ba60f | 3894 | if (subst != old) |
3895 | { | |
003000a4 | 3896 | equiv_substition_p[i] = true; |
497ba60f | 3897 | subst = copy_rtx (subst); |
3898 | lra_assert (REG_P (old)); | |
1aae95ec | 3899 | if (GET_CODE (op) != SUBREG) |
497ba60f | 3900 | *curr_id->operand_loc[i] = subst; |
1aae95ec | 3901 | else |
3902 | { | |
3903 | SUBREG_REG (op) = subst; | |
3904 | if (GET_MODE (subst) == VOIDmode) | |
3905 | original_subreg_reg_mode[i] = GET_MODE (old); | |
3906 | } | |
497ba60f | 3907 | if (lra_dump_file != NULL) |
3908 | { | |
3909 | fprintf (lra_dump_file, | |
3910 | "Changing pseudo %d in operand %i of insn %u on equiv ", | |
3911 | REGNO (old), i, INSN_UID (curr_insn)); | |
3912 | dump_value_slim (lra_dump_file, subst, 1); | |
1aae95ec | 3913 | fprintf (lra_dump_file, "\n"); |
497ba60f | 3914 | } |
3915 | op_change_p = change_p = true; | |
3916 | } | |
3917 | if (simplify_operand_subreg (i, GET_MODE (old)) || op_change_p) | |
3918 | { | |
3919 | change_p = true; | |
3920 | lra_update_dup (curr_id, i); | |
3921 | } | |
3922 | } | |
c6a6cdaa | 3923 | |
3924 | /* Reload address registers and displacements. We do it before | |
3925 | finding an alternative because of memory constraints. */ | |
7f836b57 | 3926 | before = after = NULL; |
c6a6cdaa | 3927 | for (i = 0; i < n_operands; i++) |
3928 | if (! curr_static_id->operand[i].is_operator | |
497ba60f | 3929 | && process_address (i, check_only_p, &before, &after)) |
c6a6cdaa | 3930 | { |
497ba60f | 3931 | if (check_only_p) |
3932 | return true; | |
c6a6cdaa | 3933 | change_p = true; |
3934 | lra_update_dup (curr_id, i); | |
3935 | } | |
dcd5393f | 3936 | |
c6a6cdaa | 3937 | if (change_p) |
3938 | /* If we've changed the instruction then any alternative that | |
3939 | we chose previously may no longer be valid. */ | |
71d47a14 | 3940 | lra_set_used_insn_alternative (curr_insn, LRA_UNKNOWN_ALT); |
c6a6cdaa | 3941 | |
497ba60f | 3942 | if (! check_only_p && curr_insn_set != NULL_RTX |
ea99c7a1 | 3943 | && check_and_process_move (&change_p, &sec_mem_p)) |
3944 | return change_p; | |
3945 | ||
c6a6cdaa | 3946 | try_swapped: |
3947 | ||
71d47a14 | 3948 | reused_alternative_num = check_only_p ? LRA_UNKNOWN_ALT : curr_id->used_insn_alternative; |
c6a6cdaa | 3949 | if (lra_dump_file != NULL && reused_alternative_num >= 0) |
3950 | fprintf (lra_dump_file, "Reusing alternative %d for insn #%u\n", | |
3951 | reused_alternative_num, INSN_UID (curr_insn)); | |
3952 | ||
3953 | if (process_alt_operands (reused_alternative_num)) | |
3954 | alt_p = true; | |
3955 | ||
497ba60f | 3956 | if (check_only_p) |
3957 | return ! alt_p || best_losers != 0; | |
3958 | ||
c6a6cdaa | 3959 | /* If insn is commutative (it's safe to exchange a certain pair of |
3960 | operands) then we need to try each alternative twice, the second | |
3961 | time matching those two operands as if we had exchanged them. To | |
3962 | do this, really exchange them in operands. | |
3963 | ||
3964 | If we have just tried the alternatives the second time, return | |
3965 | operands to normal and drop through. */ | |
3966 | ||
3967 | if (reused_alternative_num < 0 && commutative >= 0) | |
3968 | { | |
3969 | curr_swapped = !curr_swapped; | |
3970 | if (curr_swapped) | |
3971 | { | |
3972 | swap_operands (commutative); | |
3973 | goto try_swapped; | |
3974 | } | |
3975 | else | |
3976 | swap_operands (commutative); | |
3977 | } | |
3978 | ||
c6a6cdaa | 3979 | if (! alt_p && ! sec_mem_p) |
3980 | { | |
3981 | /* No alternative works with reloads?? */ | |
3982 | if (INSN_CODE (curr_insn) >= 0) | |
3983 | fatal_insn ("unable to generate reloads for:", curr_insn); | |
3984 | error_for_asm (curr_insn, | |
3985 | "inconsistent operand constraints in an %<asm%>"); | |
3923c63e | 3986 | lra_asm_error_p = true; |
127e79a7 | 3987 | /* Avoid further trouble with this insn. Don't generate use |
3988 | pattern here as we could use the insn SP offset. */ | |
3989 | lra_set_insn_deleted (curr_insn); | |
c6a6cdaa | 3990 | return true; |
3991 | } | |
3992 | ||
3993 | /* If the best alternative is with operands 1 and 2 swapped, swap | |
3994 | them. Update the operand numbers of any reloads already | |
3995 | pushed. */ | |
3996 | ||
3997 | if (goal_alt_swapped) | |
3998 | { | |
3999 | if (lra_dump_file != NULL) | |
4000 | fprintf (lra_dump_file, " Commutative operand exchange in insn %u\n", | |
4001 | INSN_UID (curr_insn)); | |
4002 | ||
4003 | /* Swap the duplicates too. */ | |
4004 | swap_operands (commutative); | |
4005 | change_p = true; | |
4006 | } | |
4007 | ||
c836e75b | 4008 | /* Some targets' TARGET_SECONDARY_MEMORY_NEEDED (e.g. x86) are defined |
c6a6cdaa | 4009 | too conservatively. So we use the secondary memory only if there |
4010 | is no any alternative without reloads. */ | |
4011 | use_sec_mem_p = false; | |
4012 | if (! alt_p) | |
4013 | use_sec_mem_p = true; | |
4014 | else if (sec_mem_p) | |
4015 | { | |
4016 | for (i = 0; i < n_operands; i++) | |
4017 | if (! goal_alt_win[i] && ! goal_alt_match_win[i]) | |
4018 | break; | |
4019 | use_sec_mem_p = i < n_operands; | |
4020 | } | |
4021 | ||
4022 | if (use_sec_mem_p) | |
4023 | { | |
ec4ec95a | 4024 | int in = -1, out = -1; |
e0420317 | 4025 | rtx new_reg, src, dest, rld; |
3754d046 | 4026 | machine_mode sec_mode, rld_mode; |
c6a6cdaa | 4027 | |
ec4ec95a | 4028 | lra_assert (curr_insn_set != NULL_RTX && sec_mem_p); |
4029 | dest = SET_DEST (curr_insn_set); | |
4030 | src = SET_SRC (curr_insn_set); | |
4031 | for (i = 0; i < n_operands; i++) | |
4032 | if (*curr_id->operand_loc[i] == dest) | |
4033 | out = i; | |
4034 | else if (*curr_id->operand_loc[i] == src) | |
4035 | in = i; | |
4036 | for (i = 0; i < curr_static_id->n_dups; i++) | |
4037 | if (out < 0 && *curr_id->dup_loc[i] == dest) | |
4038 | out = curr_static_id->dup_num[i]; | |
4039 | else if (in < 0 && *curr_id->dup_loc[i] == src) | |
4040 | in = curr_static_id->dup_num[i]; | |
4041 | lra_assert (out >= 0 && in >= 0 | |
4042 | && curr_static_id->operand[out].type == OP_OUT | |
4043 | && curr_static_id->operand[in].type == OP_IN); | |
974534ab | 4044 | rld = partial_subreg_p (GET_MODE (src), GET_MODE (dest)) ? src : dest; |
c47331e3 | 4045 | rld_mode = GET_MODE (rld); |
1041f930 | 4046 | sec_mode = targetm.secondary_memory_needed_mode (rld_mode); |
c6a6cdaa | 4047 | new_reg = lra_create_new_reg (sec_mode, NULL_RTX, |
4048 | NO_REGS, "secondary"); | |
4049 | /* If the mode is changed, it should be wider. */ | |
974534ab | 4050 | lra_assert (!partial_subreg_p (sec_mode, rld_mode)); |
e0420317 | 4051 | if (sec_mode != rld_mode) |
4052 | { | |
4053 | /* If the target says specifically to use another mode for | |
f4d3c071 | 4054 | secondary memory moves we cannot reuse the original |
e0420317 | 4055 | insn. */ |
cc0dc61b | 4056 | after = emit_spill_move (false, new_reg, dest); |
7f836b57 | 4057 | lra_process_new_insns (curr_insn, NULL, after, |
cc0dc61b | 4058 | "Inserting the sec. move"); |
4059 | /* We may have non null BEFORE here (e.g. after address | |
4060 | processing. */ | |
4061 | push_to_sequence (before); | |
4062 | before = emit_spill_move (true, new_reg, src); | |
4063 | emit_insn (before); | |
4064 | before = get_insns (); | |
4065 | end_sequence (); | |
7f836b57 | 4066 | lra_process_new_insns (curr_insn, before, NULL, "Changing on"); |
cc0dc61b | 4067 | lra_set_insn_deleted (curr_insn); |
4068 | } | |
e0420317 | 4069 | else if (dest == rld) |
cc0dc61b | 4070 | { |
ec4ec95a | 4071 | *curr_id->operand_loc[out] = new_reg; |
4072 | lra_update_dup (curr_id, out); | |
c47331e3 | 4073 | after = emit_spill_move (false, new_reg, dest); |
7f836b57 | 4074 | lra_process_new_insns (curr_insn, NULL, after, |
c47331e3 | 4075 | "Inserting the sec. move"); |
4076 | } | |
4077 | else | |
4078 | { | |
ec4ec95a | 4079 | *curr_id->operand_loc[in] = new_reg; |
4080 | lra_update_dup (curr_id, in); | |
cc0dc61b | 4081 | /* See comments above. */ |
4082 | push_to_sequence (before); | |
c47331e3 | 4083 | before = emit_spill_move (true, new_reg, src); |
cc0dc61b | 4084 | emit_insn (before); |
4085 | before = get_insns (); | |
4086 | end_sequence (); | |
7f836b57 | 4087 | lra_process_new_insns (curr_insn, before, NULL, |
c47331e3 | 4088 | "Inserting the sec. move"); |
4089 | } | |
4090 | lra_update_insn_regno_info (curr_insn); | |
c6a6cdaa | 4091 | return true; |
4092 | } | |
c6a6cdaa | 4093 | |
4094 | lra_assert (goal_alt_number >= 0); | |
4095 | lra_set_used_insn_alternative (curr_insn, goal_alt_number); | |
4096 | ||
4097 | if (lra_dump_file != NULL) | |
4098 | { | |
4099 | const char *p; | |
4100 | ||
4101 | fprintf (lra_dump_file, " Choosing alt %d in insn %u:", | |
4102 | goal_alt_number, INSN_UID (curr_insn)); | |
4103 | for (i = 0; i < n_operands; i++) | |
4104 | { | |
4105 | p = (curr_static_id->operand_alternative | |
4106 | [goal_alt_number * n_operands + i].constraint); | |
4107 | if (*p == '\0') | |
4108 | continue; | |
4109 | fprintf (lra_dump_file, " (%d) ", i); | |
4110 | for (; *p != '\0' && *p != ',' && *p != '#'; p++) | |
4111 | fputc (*p, lra_dump_file); | |
4112 | } | |
273c330a | 4113 | if (INSN_CODE (curr_insn) >= 0 |
4114 | && (p = get_insn_name (INSN_CODE (curr_insn))) != NULL) | |
4115 | fprintf (lra_dump_file, " {%s}", p); | |
a4686d0a | 4116 | if (maybe_ne (curr_id->sp_offset, 0)) |
4117 | { | |
4118 | fprintf (lra_dump_file, " (sp_off="); | |
4119 | print_dec (curr_id->sp_offset, lra_dump_file); | |
4120 | fprintf (lra_dump_file, ")"); | |
4121 | } | |
4122 | fprintf (lra_dump_file, "\n"); | |
c6a6cdaa | 4123 | } |
4124 | ||
4125 | /* Right now, for any pair of operands I and J that are required to | |
4126 | match, with J < I, goal_alt_matches[I] is J. Add I to | |
4127 | goal_alt_matched[J]. */ | |
1a8f8886 | 4128 | |
c6a6cdaa | 4129 | for (i = 0; i < n_operands; i++) |
4130 | if ((j = goal_alt_matches[i]) >= 0) | |
4131 | { | |
4132 | for (k = 0; goal_alt_matched[j][k] >= 0; k++) | |
4133 | ; | |
4134 | /* We allow matching one output operand and several input | |
4135 | operands. */ | |
4136 | lra_assert (k == 0 | |
4137 | || (curr_static_id->operand[j].type == OP_OUT | |
4138 | && curr_static_id->operand[i].type == OP_IN | |
4139 | && (curr_static_id->operand | |
4140 | [goal_alt_matched[j][0]].type == OP_IN))); | |
4141 | goal_alt_matched[j][k] = i; | |
4142 | goal_alt_matched[j][k + 1] = -1; | |
4143 | } | |
1a8f8886 | 4144 | |
c6a6cdaa | 4145 | for (i = 0; i < n_operands; i++) |
4146 | goal_alt_win[i] |= goal_alt_match_win[i]; | |
1a8f8886 | 4147 | |
c6a6cdaa | 4148 | /* Any constants that aren't allowed and can't be reloaded into |
4149 | registers are here changed into memory references. */ | |
4150 | for (i = 0; i < n_operands; i++) | |
4151 | if (goal_alt_win[i]) | |
4152 | { | |
4153 | int regno; | |
4154 | enum reg_class new_class; | |
4155 | rtx reg = *curr_id->operand_loc[i]; | |
4156 | ||
4157 | if (GET_CODE (reg) == SUBREG) | |
4158 | reg = SUBREG_REG (reg); | |
1a8f8886 | 4159 | |
c6a6cdaa | 4160 | if (REG_P (reg) && (regno = REGNO (reg)) >= FIRST_PSEUDO_REGISTER) |
4161 | { | |
4162 | bool ok_p = in_class_p (reg, goal_alt[i], &new_class); | |
4163 | ||
4164 | if (new_class != NO_REGS && get_reg_class (regno) != new_class) | |
4165 | { | |
4166 | lra_assert (ok_p); | |
7619e612 | 4167 | lra_change_class (regno, new_class, " Change to", true); |
c6a6cdaa | 4168 | } |
4169 | } | |
4170 | } | |
4171 | else | |
4172 | { | |
4173 | const char *constraint; | |
4174 | char c; | |
4175 | rtx op = *curr_id->operand_loc[i]; | |
4176 | rtx subreg = NULL_RTX; | |
3754d046 | 4177 | machine_mode mode = curr_operand_mode[i]; |
1a8f8886 | 4178 | |
c6a6cdaa | 4179 | if (GET_CODE (op) == SUBREG) |
4180 | { | |
4181 | subreg = op; | |
4182 | op = SUBREG_REG (op); | |
4183 | mode = GET_MODE (op); | |
4184 | } | |
1a8f8886 | 4185 | |
c6a6cdaa | 4186 | if (CONST_POOL_OK_P (mode, op) |
4187 | && ((targetm.preferred_reload_class | |
4188 | (op, (enum reg_class) goal_alt[i]) == NO_REGS) | |
4189 | || no_input_reloads_p)) | |
4190 | { | |
4191 | rtx tem = force_const_mem (mode, op); | |
1a8f8886 | 4192 | |
c6a6cdaa | 4193 | change_p = true; |
4194 | if (subreg != NULL_RTX) | |
4195 | tem = gen_rtx_SUBREG (mode, tem, SUBREG_BYTE (subreg)); | |
1a8f8886 | 4196 | |
c6a6cdaa | 4197 | *curr_id->operand_loc[i] = tem; |
4198 | lra_update_dup (curr_id, i); | |
497ba60f | 4199 | process_address (i, false, &before, &after); |
1a8f8886 | 4200 | |
c6a6cdaa | 4201 | /* If the alternative accepts constant pool refs directly |
4202 | there will be no reload needed at all. */ | |
4203 | if (subreg != NULL_RTX) | |
4204 | continue; | |
4205 | /* Skip alternatives before the one requested. */ | |
4206 | constraint = (curr_static_id->operand_alternative | |
4207 | [goal_alt_number * n_operands + i].constraint); | |
4208 | for (; | |
4209 | (c = *constraint) && c != ',' && c != '#'; | |
4210 | constraint += CONSTRAINT_LEN (c, constraint)) | |
4211 | { | |
79bc09fb | 4212 | enum constraint_num cn = lookup_constraint (constraint); |
6b3b345a | 4213 | if ((insn_extra_memory_constraint (cn) |
4214 | || insn_extra_special_memory_constraint (cn)) | |
79bc09fb | 4215 | && satisfies_memory_constraint_p (tem, cn)) |
c6a6cdaa | 4216 | break; |
c6a6cdaa | 4217 | } |
4218 | if (c == '\0' || c == ',' || c == '#') | |
4219 | continue; | |
1a8f8886 | 4220 | |
c6a6cdaa | 4221 | goal_alt_win[i] = true; |
4222 | } | |
4223 | } | |
1a8f8886 | 4224 | |
dd083a02 | 4225 | n_outputs = 0; |
4226 | outputs[0] = -1; | |
c6a6cdaa | 4227 | for (i = 0; i < n_operands; i++) |
4228 | { | |
1f3a048a | 4229 | int regno; |
4230 | bool optional_p = false; | |
c6a6cdaa | 4231 | rtx old, new_reg; |
4232 | rtx op = *curr_id->operand_loc[i]; | |
4233 | ||
4234 | if (goal_alt_win[i]) | |
4235 | { | |
4236 | if (goal_alt[i] == NO_REGS | |
4237 | && REG_P (op) | |
4238 | /* When we assign NO_REGS it means that we will not | |
4239 | assign a hard register to the scratch pseudo by | |
4240 | assigment pass and the scratch pseudo will be | |
4241 | spilled. Spilled scratch pseudos are transformed | |
4242 | back to scratches at the LRA end. */ | |
c2b94990 | 4243 | && lra_former_scratch_operand_p (curr_insn, i) |
4244 | && lra_former_scratch_p (REGNO (op))) | |
f7c98bb1 | 4245 | { |
4246 | int regno = REGNO (op); | |
7619e612 | 4247 | lra_change_class (regno, NO_REGS, " Change to", true); |
f7c98bb1 | 4248 | if (lra_get_regno_hard_regno (regno) >= 0) |
4249 | /* We don't have to mark all insn affected by the | |
4250 | spilled pseudo as there is only one such insn, the | |
4251 | current one. */ | |
4252 | reg_renumber[regno] = -1; | |
c2b94990 | 4253 | lra_assert (bitmap_single_bit_set_p |
4254 | (&lra_reg_info[REGNO (op)].insn_bitmap)); | |
f7c98bb1 | 4255 | } |
1f3a048a | 4256 | /* We can do an optional reload. If the pseudo got a hard |
4257 | reg, we might improve the code through inheritance. If | |
4258 | it does not get a hard register we coalesce memory/memory | |
4259 | moves later. Ignore move insns to avoid cycling. */ | |
267200f3 | 4260 | if (! lra_simple_p |
1f3a048a | 4261 | && lra_undo_inheritance_iter < LRA_MAX_INHERITANCE_PASSES |
4262 | && goal_alt[i] != NO_REGS && REG_P (op) | |
4263 | && (regno = REGNO (op)) >= FIRST_PSEUDO_REGISTER | |
7619e612 | 4264 | && regno < new_regno_start |
267200f3 | 4265 | && ! lra_former_scratch_p (regno) |
1f3a048a | 4266 | && reg_renumber[regno] < 0 |
25cd984c | 4267 | /* Check that the optional reload pseudo will be able to |
4268 | hold given mode value. */ | |
4269 | && ! (prohibited_class_reg_set_mode_p | |
4270 | (goal_alt[i], reg_class_contents[goal_alt[i]], | |
4271 | PSEUDO_REGNO_MODE (regno))) | |
1f3a048a | 4272 | && (curr_insn_set == NULL_RTX |
267200f3 | 4273 | || !((REG_P (SET_SRC (curr_insn_set)) |
4274 | || MEM_P (SET_SRC (curr_insn_set)) | |
4275 | || GET_CODE (SET_SRC (curr_insn_set)) == SUBREG) | |
4276 | && (REG_P (SET_DEST (curr_insn_set)) | |
4277 | || MEM_P (SET_DEST (curr_insn_set)) | |
4278 | || GET_CODE (SET_DEST (curr_insn_set)) == SUBREG)))) | |
1f3a048a | 4279 | optional_p = true; |
74fde7b5 | 4280 | else if (goal_alt_matched[i][0] != -1 |
4281 | && curr_static_id->operand[i].type == OP_OUT | |
4282 | && (curr_static_id->operand_alternative | |
4b2731eb | 4283 | [goal_alt_number * n_operands + i].earlyclobber) |
4284 | && REG_P (op)) | |
74fde7b5 | 4285 | { |
4b2731eb | 4286 | for (j = 0; goal_alt_matched[i][j] != -1; j++) |
4287 | { | |
4288 | rtx op2 = *curr_id->operand_loc[goal_alt_matched[i][j]]; | |
4289 | ||
4290 | if (REG_P (op2) && REGNO (op) != REGNO (op2)) | |
4291 | break; | |
4292 | } | |
4293 | if (goal_alt_matched[i][j] != -1) | |
4294 | { | |
4295 | /* Generate reloads for different output and matched | |
4296 | input registers. This is the easiest way to avoid | |
4297 | creation of non-existing register conflicts in | |
4298 | lra-lives.c. */ | |
4299 | match_reload (i, goal_alt_matched[i], outputs, goal_alt[i], &before, | |
4300 | &after, TRUE); | |
4301 | outputs[n_outputs++] = i; | |
4302 | outputs[n_outputs] = -1; | |
4303 | } | |
74fde7b5 | 4304 | continue; |
4305 | } | |
1f3a048a | 4306 | else |
4307 | continue; | |
c6a6cdaa | 4308 | } |
1a8f8886 | 4309 | |
c6a6cdaa | 4310 | /* Operands that match previous ones have already been handled. */ |
4311 | if (goal_alt_matches[i] >= 0) | |
4312 | continue; | |
4313 | ||
4314 | /* We should not have an operand with a non-offsettable address | |
4315 | appearing where an offsettable address will do. It also may | |
4316 | be a case when the address should be special in other words | |
4317 | not a general one (e.g. it needs no index reg). */ | |
4318 | if (goal_alt_matched[i][0] == -1 && goal_alt_offmemok[i] && MEM_P (op)) | |
4319 | { | |
4320 | enum reg_class rclass; | |
4321 | rtx *loc = &XEXP (op, 0); | |
4322 | enum rtx_code code = GET_CODE (*loc); | |
4323 | ||
4324 | push_to_sequence (before); | |
4325 | rclass = base_reg_class (GET_MODE (op), MEM_ADDR_SPACE (op), | |
4326 | MEM, SCRATCH); | |
4327 | if (GET_RTX_CLASS (code) == RTX_AUTOINC) | |
4328 | new_reg = emit_inc (rclass, *loc, *loc, | |
4329 | /* This value does not matter for MODIFY. */ | |
4330 | GET_MODE_SIZE (GET_MODE (op))); | |
6cadc8f7 | 4331 | else if (get_reload_reg (OP_IN, Pmode, *loc, rclass, FALSE, |
c6a6cdaa | 4332 | "offsetable address", &new_reg)) |
27137b2a | 4333 | { |
4334 | rtx addr = *loc; | |
4335 | enum rtx_code code = GET_CODE (addr); | |
4336 | ||
4337 | if (code == AND && CONST_INT_P (XEXP (addr, 1))) | |
4338 | /* (and ... (const_int -X)) is used to align to X bytes. */ | |
4339 | addr = XEXP (*loc, 0); | |
4340 | lra_emit_move (new_reg, addr); | |
4341 | if (addr != *loc) | |
4342 | emit_move_insn (new_reg, gen_rtx_AND (GET_MODE (new_reg), new_reg, XEXP (*loc, 1))); | |
4343 | } | |
c6a6cdaa | 4344 | before = get_insns (); |
4345 | end_sequence (); | |
4346 | *loc = new_reg; | |
4347 | lra_update_dup (curr_id, i); | |
4348 | } | |
4349 | else if (goal_alt_matched[i][0] == -1) | |
4350 | { | |
3754d046 | 4351 | machine_mode mode; |
c6a6cdaa | 4352 | rtx reg, *loc; |
9edf7ea8 | 4353 | int hard_regno; |
c6a6cdaa | 4354 | enum op_type type = curr_static_id->operand[i].type; |
4355 | ||
4356 | loc = curr_id->operand_loc[i]; | |
4357 | mode = curr_operand_mode[i]; | |
4358 | if (GET_CODE (*loc) == SUBREG) | |
4359 | { | |
4360 | reg = SUBREG_REG (*loc); | |
9edf7ea8 | 4361 | poly_int64 byte = SUBREG_BYTE (*loc); |
c6a6cdaa | 4362 | if (REG_P (reg) |
5cbb8e6b | 4363 | /* Strict_low_part requires reloading the register and not |
4364 | just the subreg. Likewise for a strict subreg no wider | |
4365 | than a word for WORD_REGISTER_OPERATIONS targets. */ | |
c6a6cdaa | 4366 | && (curr_static_id->operand[i].strict_low |
d0257d43 | 4367 | || (!paradoxical_subreg_p (mode, GET_MODE (reg)) |
c6a6cdaa | 4368 | && (hard_regno |
4369 | = get_try_hard_regno (REGNO (reg))) >= 0 | |
4370 | && (simplify_subreg_regno | |
4371 | (hard_regno, | |
4372 | GET_MODE (reg), byte, mode) < 0) | |
4373 | && (goal_alt[i] == NO_REGS | |
4374 | || (simplify_subreg_regno | |
4375 | (ira_class_hard_regs[goal_alt[i]][0], | |
5cbb8e6b | 4376 | GET_MODE (reg), byte, mode) >= 0))) |
3cedfe34 | 4377 | || (partial_subreg_p (mode, GET_MODE (reg)) |
52acb7ae | 4378 | && known_le (GET_MODE_SIZE (GET_MODE (reg)), |
4379 | UNITS_PER_WORD) | |
5cbb8e6b | 4380 | && WORD_REGISTER_OPERATIONS))) |
c6a6cdaa | 4381 | { |
55996ba4 | 4382 | /* An OP_INOUT is required when reloading a subreg of a |
4383 | mode wider than a word to ensure that data beyond the | |
4384 | word being reloaded is preserved. Also automatically | |
4385 | ensure that strict_low_part reloads are made into | |
4386 | OP_INOUT which should already be true from the backend | |
4387 | constraints. */ | |
4388 | if (type == OP_OUT | |
4389 | && (curr_static_id->operand[i].strict_low | |
9f2c0e68 | 4390 | || read_modify_subreg_p (*loc))) |
90f51e67 | 4391 | type = OP_INOUT; |
c6a6cdaa | 4392 | loc = &SUBREG_REG (*loc); |
4393 | mode = GET_MODE (*loc); | |
4394 | } | |
4395 | } | |
4396 | old = *loc; | |
6cadc8f7 | 4397 | if (get_reload_reg (type, mode, old, goal_alt[i], |
4398 | loc != curr_id->operand_loc[i], "", &new_reg) | |
c6a6cdaa | 4399 | && type != OP_OUT) |
4400 | { | |
4401 | push_to_sequence (before); | |
4402 | lra_emit_move (new_reg, old); | |
4403 | before = get_insns (); | |
4404 | end_sequence (); | |
4405 | } | |
4406 | *loc = new_reg; | |
4407 | if (type != OP_IN | |
4408 | && find_reg_note (curr_insn, REG_UNUSED, old) == NULL_RTX) | |
4409 | { | |
4410 | start_sequence (); | |
4411 | lra_emit_move (type == OP_INOUT ? copy_rtx (old) : old, new_reg); | |
4412 | emit_insn (after); | |
4413 | after = get_insns (); | |
4414 | end_sequence (); | |
4415 | *loc = new_reg; | |
4416 | } | |
4417 | for (j = 0; j < goal_alt_dont_inherit_ops_num; j++) | |
4418 | if (goal_alt_dont_inherit_ops[j] == i) | |
4419 | { | |
4420 | lra_set_regno_unique_value (REGNO (new_reg)); | |
4421 | break; | |
4422 | } | |
4423 | lra_update_dup (curr_id, i); | |
4424 | } | |
4425 | else if (curr_static_id->operand[i].type == OP_IN | |
4426 | && (curr_static_id->operand[goal_alt_matched[i][0]].type | |
b8b2688e | 4427 | == OP_OUT |
4428 | || (curr_static_id->operand[goal_alt_matched[i][0]].type | |
4429 | == OP_INOUT | |
4430 | && (operands_match_p | |
4431 | (*curr_id->operand_loc[i], | |
4432 | *curr_id->operand_loc[goal_alt_matched[i][0]], | |
4433 | -1))))) | |
c6a6cdaa | 4434 | { |
aa3ce8ba | 4435 | /* generate reloads for input and matched outputs. */ |
4436 | match_inputs[0] = i; | |
4437 | match_inputs[1] = -1; | |
dd083a02 | 4438 | match_reload (goal_alt_matched[i][0], match_inputs, outputs, |
72460f4d | 4439 | goal_alt[i], &before, &after, |
4440 | curr_static_id->operand_alternative | |
4441 | [goal_alt_number * n_operands + goal_alt_matched[i][0]] | |
4442 | .earlyclobber); | |
c6a6cdaa | 4443 | } |
b8b2688e | 4444 | else if ((curr_static_id->operand[i].type == OP_OUT |
4445 | || (curr_static_id->operand[i].type == OP_INOUT | |
4446 | && (operands_match_p | |
4447 | (*curr_id->operand_loc[i], | |
4448 | *curr_id->operand_loc[goal_alt_matched[i][0]], | |
4449 | -1)))) | |
c6a6cdaa | 4450 | && (curr_static_id->operand[goal_alt_matched[i][0]].type |
b8b2688e | 4451 | == OP_IN)) |
aa3ce8ba | 4452 | /* Generate reloads for output and matched inputs. */ |
dd083a02 | 4453 | match_reload (i, goal_alt_matched[i], outputs, goal_alt[i], &before, |
4454 | &after, curr_static_id->operand_alternative | |
4455 | [goal_alt_number * n_operands + i].earlyclobber); | |
aa3ce8ba | 4456 | else if (curr_static_id->operand[i].type == OP_IN |
4457 | && (curr_static_id->operand[goal_alt_matched[i][0]].type | |
4458 | == OP_IN)) | |
4459 | { | |
4460 | /* Generate reloads for matched inputs. */ | |
4461 | match_inputs[0] = i; | |
4462 | for (j = 0; (k = goal_alt_matched[i][j]) >= 0; j++) | |
4463 | match_inputs[j + 1] = k; | |
4464 | match_inputs[j + 1] = -1; | |
dd083a02 | 4465 | match_reload (-1, match_inputs, outputs, goal_alt[i], &before, |
4466 | &after, false); | |
aa3ce8ba | 4467 | } |
c6a6cdaa | 4468 | else |
4469 | /* We must generate code in any case when function | |
4470 | process_alt_operands decides that it is possible. */ | |
4471 | gcc_unreachable (); | |
dd083a02 | 4472 | |
4473 | /* Memorise processed outputs so that output remaining to be processed | |
4474 | can avoid using the same register value (see match_reload). */ | |
4475 | if (curr_static_id->operand[i].type == OP_OUT) | |
4476 | { | |
4477 | outputs[n_outputs++] = i; | |
4478 | outputs[n_outputs] = -1; | |
4479 | } | |
4480 | ||
1f3a048a | 4481 | if (optional_p) |
4482 | { | |
ab4ea053 | 4483 | rtx reg = op; |
4484 | ||
4485 | lra_assert (REG_P (reg)); | |
4486 | regno = REGNO (reg); | |
1f3a048a | 4487 | op = *curr_id->operand_loc[i]; /* Substitution. */ |
4488 | if (GET_CODE (op) == SUBREG) | |
4489 | op = SUBREG_REG (op); | |
4490 | gcc_assert (REG_P (op) && (int) REGNO (op) >= new_regno_start); | |
4491 | bitmap_set_bit (&lra_optional_reload_pseudos, REGNO (op)); | |
ab4ea053 | 4492 | lra_reg_info[REGNO (op)].restore_rtx = reg; |
1f3a048a | 4493 | if (lra_dump_file != NULL) |
4494 | fprintf (lra_dump_file, | |
4495 | " Making reload reg %d for reg %d optional\n", | |
4496 | REGNO (op), regno); | |
4497 | } | |
c6a6cdaa | 4498 | } |
4499 | if (before != NULL_RTX || after != NULL_RTX | |
4500 | || max_regno_before != max_reg_num ()) | |
4501 | change_p = true; | |
4502 | if (change_p) | |
4503 | { | |
4504 | lra_update_operator_dups (curr_id); | |
4505 | /* Something changes -- process the insn. */ | |
4506 | lra_update_insn_regno_info (curr_insn); | |
4507 | } | |
4508 | lra_process_new_insns (curr_insn, before, after, "Inserting insn reload"); | |
4509 | return change_p; | |
4510 | } | |
4511 | ||
497ba60f | 4512 | /* Return true if INSN satisfies all constraints. In other words, no |
4513 | reload insns are needed. */ | |
4514 | bool | |
4515 | lra_constrain_insn (rtx_insn *insn) | |
4516 | { | |
4517 | int saved_new_regno_start = new_regno_start; | |
4518 | int saved_new_insn_uid_start = new_insn_uid_start; | |
4519 | bool change_p; | |
4520 | ||
4521 | curr_insn = insn; | |
4522 | curr_id = lra_get_insn_recog_data (curr_insn); | |
4523 | curr_static_id = curr_id->insn_static_data; | |
4524 | new_insn_uid_start = get_max_uid (); | |
4525 | new_regno_start = max_reg_num (); | |
4526 | change_p = curr_insn_transform (true); | |
4527 | new_regno_start = saved_new_regno_start; | |
4528 | new_insn_uid_start = saved_new_insn_uid_start; | |
4529 | return ! change_p; | |
4530 | } | |
4531 | ||
c6a6cdaa | 4532 | /* Return true if X is in LIST. */ |
4533 | static bool | |
4534 | in_list_p (rtx x, rtx list) | |
4535 | { | |
4536 | for (; list != NULL_RTX; list = XEXP (list, 1)) | |
4537 | if (XEXP (list, 0) == x) | |
4538 | return true; | |
4539 | return false; | |
4540 | } | |
4541 | ||
4542 | /* Return true if X contains an allocatable hard register (if | |
4543 | HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */ | |
4544 | static bool | |
4545 | contains_reg_p (rtx x, bool hard_reg_p, bool spilled_p) | |
4546 | { | |
4547 | int i, j; | |
4548 | const char *fmt; | |
4549 | enum rtx_code code; | |
4550 | ||
4551 | code = GET_CODE (x); | |
4552 | if (REG_P (x)) | |
4553 | { | |
4554 | int regno = REGNO (x); | |
4555 | HARD_REG_SET alloc_regs; | |
4556 | ||
4557 | if (hard_reg_p) | |
4558 | { | |
4559 | if (regno >= FIRST_PSEUDO_REGISTER) | |
4560 | regno = lra_get_regno_hard_regno (regno); | |
4561 | if (regno < 0) | |
4562 | return false; | |
4563 | COMPL_HARD_REG_SET (alloc_regs, lra_no_alloc_regs); | |
4564 | return overlaps_hard_reg_set_p (alloc_regs, GET_MODE (x), regno); | |
4565 | } | |
4566 | else | |
4567 | { | |
4568 | if (regno < FIRST_PSEUDO_REGISTER) | |
4569 | return false; | |
4570 | if (! spilled_p) | |
4571 | return true; | |
4572 | return lra_get_regno_hard_regno (regno) < 0; | |
4573 | } | |
4574 | } | |
4575 | fmt = GET_RTX_FORMAT (code); | |
4576 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
4577 | { | |
4578 | if (fmt[i] == 'e') | |
4579 | { | |
4580 | if (contains_reg_p (XEXP (x, i), hard_reg_p, spilled_p)) | |
4581 | return true; | |
4582 | } | |
4583 | else if (fmt[i] == 'E') | |
4584 | { | |
4585 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
4586 | if (contains_reg_p (XVECEXP (x, i, j), hard_reg_p, spilled_p)) | |
4587 | return true; | |
4588 | } | |
4589 | } | |
4590 | return false; | |
4591 | } | |
4592 | ||
d596f8db | 4593 | /* Process all regs in location *LOC and change them on equivalent |
4594 | substitution. Return true if any change was done. */ | |
c6a6cdaa | 4595 | static bool |
d596f8db | 4596 | loc_equivalence_change_p (rtx *loc) |
c6a6cdaa | 4597 | { |
4598 | rtx subst, reg, x = *loc; | |
4599 | bool result = false; | |
4600 | enum rtx_code code = GET_CODE (x); | |
4601 | const char *fmt; | |
4602 | int i, j; | |
4603 | ||
4604 | if (code == SUBREG) | |
4605 | { | |
4606 | reg = SUBREG_REG (x); | |
3b3a5e5f | 4607 | if ((subst = get_equiv_with_elimination (reg, curr_insn)) != reg |
c6a6cdaa | 4608 | && GET_MODE (subst) == VOIDmode) |
4609 | { | |
4610 | /* We cannot reload debug location. Simplify subreg here | |
4611 | while we know the inner mode. */ | |
4612 | *loc = simplify_gen_subreg (GET_MODE (x), subst, | |
4613 | GET_MODE (reg), SUBREG_BYTE (x)); | |
4614 | return true; | |
4615 | } | |
4616 | } | |
3b3a5e5f | 4617 | if (code == REG && (subst = get_equiv_with_elimination (x, curr_insn)) != x) |
c6a6cdaa | 4618 | { |
4619 | *loc = subst; | |
4620 | return true; | |
4621 | } | |
4622 | ||
4623 | /* Scan all the operand sub-expressions. */ | |
4624 | fmt = GET_RTX_FORMAT (code); | |
4625 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
4626 | { | |
4627 | if (fmt[i] == 'e') | |
d596f8db | 4628 | result = loc_equivalence_change_p (&XEXP (x, i)) || result; |
c6a6cdaa | 4629 | else if (fmt[i] == 'E') |
4630 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
4631 | result | |
d596f8db | 4632 | = loc_equivalence_change_p (&XVECEXP (x, i, j)) || result; |
c6a6cdaa | 4633 | } |
4634 | return result; | |
4635 | } | |
4636 | ||
136e5c8e | 4637 | /* Similar to loc_equivalence_change_p, but for use as |
61cd3e57 | 4638 | simplify_replace_fn_rtx callback. DATA is insn for which the |
4639 | elimination is done. If it null we don't do the elimination. */ | |
136e5c8e | 4640 | static rtx |
61cd3e57 | 4641 | loc_equivalence_callback (rtx loc, const_rtx, void *data) |
136e5c8e | 4642 | { |
4643 | if (!REG_P (loc)) | |
4644 | return NULL_RTX; | |
4645 | ||
61cd3e57 | 4646 | rtx subst = (data == NULL |
7f836b57 | 4647 | ? get_equiv (loc) : get_equiv_with_elimination (loc, (rtx_insn *) data)); |
136e5c8e | 4648 | if (subst != loc) |
4649 | return subst; | |
4650 | ||
4651 | return NULL_RTX; | |
4652 | } | |
4653 | ||
c6a6cdaa | 4654 | /* Maximum number of generated reload insns per an insn. It is for |
4655 | preventing this pass cycling in a bug case. */ | |
4656 | #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS | |
4657 | ||
4658 | /* The current iteration number of this LRA pass. */ | |
4659 | int lra_constraint_iter; | |
4660 | ||
c6a6cdaa | 4661 | /* True if we substituted equiv which needs checking register |
4662 | allocation correctness because the equivalent value contains | |
4663 | allocatable hard registers or when we restore multi-register | |
4664 | pseudo. */ | |
4665 | bool lra_risky_transformations_p; | |
4666 | ||
4667 | /* Return true if REGNO is referenced in more than one block. */ | |
4668 | static bool | |
4669 | multi_block_pseudo_p (int regno) | |
4670 | { | |
4671 | basic_block bb = NULL; | |
4672 | unsigned int uid; | |
4673 | bitmap_iterator bi; | |
1a8f8886 | 4674 | |
c6a6cdaa | 4675 | if (regno < FIRST_PSEUDO_REGISTER) |
4676 | return false; | |
1a8f8886 | 4677 | |
c6a6cdaa | 4678 | EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi) |
4679 | if (bb == NULL) | |
4680 | bb = BLOCK_FOR_INSN (lra_insn_recog_data[uid]->insn); | |
4681 | else if (BLOCK_FOR_INSN (lra_insn_recog_data[uid]->insn) != bb) | |
4682 | return true; | |
4683 | return false; | |
4684 | } | |
4685 | ||
7a438292 | 4686 | /* Return true if LIST contains a deleted insn. */ |
4687 | static bool | |
382f116f | 4688 | contains_deleted_insn_p (rtx_insn_list *list) |
7a438292 | 4689 | { |
382f116f | 4690 | for (; list != NULL_RTX; list = list->next ()) |
4691 | if (NOTE_P (list->insn ()) | |
4692 | && NOTE_KIND (list->insn ()) == NOTE_INSN_DELETED) | |
7a438292 | 4693 | return true; |
4694 | return false; | |
4695 | } | |
4696 | ||
c6a6cdaa | 4697 | /* Return true if X contains a pseudo dying in INSN. */ |
4698 | static bool | |
c265d2aa | 4699 | dead_pseudo_p (rtx x, rtx_insn *insn) |
c6a6cdaa | 4700 | { |
4701 | int i, j; | |
4702 | const char *fmt; | |
4703 | enum rtx_code code; | |
4704 | ||
4705 | if (REG_P (x)) | |
4706 | return (insn != NULL_RTX | |
4707 | && find_regno_note (insn, REG_DEAD, REGNO (x)) != NULL_RTX); | |
4708 | code = GET_CODE (x); | |
4709 | fmt = GET_RTX_FORMAT (code); | |
4710 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
4711 | { | |
4712 | if (fmt[i] == 'e') | |
4713 | { | |
4714 | if (dead_pseudo_p (XEXP (x, i), insn)) | |
4715 | return true; | |
4716 | } | |
4717 | else if (fmt[i] == 'E') | |
4718 | { | |
4719 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
4720 | if (dead_pseudo_p (XVECEXP (x, i, j), insn)) | |
4721 | return true; | |
4722 | } | |
4723 | } | |
4724 | return false; | |
4725 | } | |
4726 | ||
4727 | /* Return true if INSN contains a dying pseudo in INSN right hand | |
4728 | side. */ | |
4729 | static bool | |
50fc2d35 | 4730 | insn_rhs_dead_pseudo_p (rtx_insn *insn) |
c6a6cdaa | 4731 | { |
4732 | rtx set = single_set (insn); | |
4733 | ||
4734 | gcc_assert (set != NULL); | |
4735 | return dead_pseudo_p (SET_SRC (set), insn); | |
4736 | } | |
4737 | ||
4738 | /* Return true if any init insn of REGNO contains a dying pseudo in | |
4739 | insn right hand side. */ | |
4740 | static bool | |
4741 | init_insn_rhs_dead_pseudo_p (int regno) | |
4742 | { | |
382f116f | 4743 | rtx_insn_list *insns = ira_reg_equiv[regno].init_insns; |
c6a6cdaa | 4744 | |
4745 | if (insns == NULL) | |
4746 | return false; | |
382f116f | 4747 | for (; insns != NULL_RTX; insns = insns->next ()) |
4748 | if (insn_rhs_dead_pseudo_p (insns->insn ())) | |
c6a6cdaa | 4749 | return true; |
4750 | return false; | |
4751 | } | |
4752 | ||
691cfda4 | 4753 | /* Return TRUE if REGNO has a reverse equivalence. The equivalence is |
4754 | reverse only if we have one init insn with given REGNO as a | |
4755 | source. */ | |
4756 | static bool | |
4757 | reverse_equiv_p (int regno) | |
4758 | { | |
382f116f | 4759 | rtx_insn_list *insns = ira_reg_equiv[regno].init_insns; |
4760 | rtx set; | |
691cfda4 | 4761 | |
382f116f | 4762 | if (insns == NULL) |
691cfda4 | 4763 | return false; |
382f116f | 4764 | if (! INSN_P (insns->insn ()) |
4765 | || insns->next () != NULL) | |
691cfda4 | 4766 | return false; |
382f116f | 4767 | if ((set = single_set (insns->insn ())) == NULL_RTX) |
691cfda4 | 4768 | return false; |
4769 | return REG_P (SET_SRC (set)) && (int) REGNO (SET_SRC (set)) == regno; | |
4770 | } | |
4771 | ||
4772 | /* Return TRUE if REGNO was reloaded in an equivalence init insn. We | |
4773 | call this function only for non-reverse equivalence. */ | |
4774 | static bool | |
4775 | contains_reloaded_insn_p (int regno) | |
4776 | { | |
4777 | rtx set; | |
382f116f | 4778 | rtx_insn_list *list = ira_reg_equiv[regno].init_insns; |
691cfda4 | 4779 | |
382f116f | 4780 | for (; list != NULL; list = list->next ()) |
4781 | if ((set = single_set (list->insn ())) == NULL_RTX | |
691cfda4 | 4782 | || ! REG_P (SET_DEST (set)) |
4783 | || (int) REGNO (SET_DEST (set)) != regno) | |
4784 | return true; | |
4785 | return false; | |
4786 | } | |
4787 | ||
c6a6cdaa | 4788 | /* Entry function of LRA constraint pass. Return true if the |
4789 | constraint pass did change the code. */ | |
4790 | bool | |
4791 | lra_constraints (bool first_p) | |
4792 | { | |
4793 | bool changed_p; | |
4794 | int i, hard_regno, new_insns_num; | |
f7b7100e | 4795 | unsigned int min_len, new_min_len, uid; |
4796 | rtx set, x, reg, dest_reg; | |
c6a6cdaa | 4797 | basic_block last_bb; |
f7b7100e | 4798 | bitmap_iterator bi; |
c6a6cdaa | 4799 | |
4800 | lra_constraint_iter++; | |
4801 | if (lra_dump_file != NULL) | |
4802 | fprintf (lra_dump_file, "\n********** Local #%d: **********\n\n", | |
4803 | lra_constraint_iter); | |
c6a6cdaa | 4804 | changed_p = false; |
a9d8ab38 | 4805 | if (pic_offset_table_rtx |
4806 | && REGNO (pic_offset_table_rtx) >= FIRST_PSEUDO_REGISTER) | |
4807 | lra_risky_transformations_p = true; | |
4808 | else | |
9628978f | 4809 | /* On the first iteration we should check IRA assignment |
4810 | correctness. In rare cases, the assignments can be wrong as | |
8ae81042 | 4811 | early clobbers operands are ignored in IRA or usages of |
4812 | paradoxical sub-registers are not taken into account by | |
4813 | IRA. */ | |
9628978f | 4814 | lra_risky_transformations_p = first_p; |
c6a6cdaa | 4815 | new_insn_uid_start = get_max_uid (); |
4816 | new_regno_start = first_p ? lra_constraint_new_regno_start : max_reg_num (); | |
3b3a5e5f | 4817 | /* Mark used hard regs for target stack size calulations. */ |
4818 | for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++) | |
4819 | if (lra_reg_info[i].nrefs != 0 | |
4820 | && (hard_regno = lra_get_regno_hard_regno (i)) >= 0) | |
4821 | { | |
4822 | int j, nregs; | |
4823 | ||
92d2aec3 | 4824 | nregs = hard_regno_nregs (hard_regno, lra_reg_info[i].biggest_mode); |
3b3a5e5f | 4825 | for (j = 0; j < nregs; j++) |
4826 | df_set_regs_ever_live (hard_regno + j, true); | |
4827 | } | |
4828 | /* Do elimination before the equivalence processing as we can spill | |
4829 | some pseudos during elimination. */ | |
4830 | lra_eliminate (false, first_p); | |
f6708c36 | 4831 | auto_bitmap equiv_insn_bitmap (®_obstack); |
c6a6cdaa | 4832 | for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++) |
4833 | if (lra_reg_info[i].nrefs != 0) | |
4834 | { | |
4835 | ira_reg_equiv[i].profitable_p = true; | |
f7b7100e | 4836 | reg = regno_reg_rtx[i]; |
3b3a5e5f | 4837 | if (lra_get_regno_hard_regno (i) < 0 && (x = get_equiv (reg)) != reg) |
c6a6cdaa | 4838 | { |
4839 | bool pseudo_p = contains_reg_p (x, false, false); | |
c6a6cdaa | 4840 | |
f4d3c071 | 4841 | /* After RTL transformation, we cannot guarantee that |
7a438292 | 4842 | pseudo in the substitution was not reloaded which might |
4843 | make equivalence invalid. For example, in reverse | |
4844 | equiv of p0 | |
4845 | ||
4846 | p0 <- ... | |
4847 | ... | |
4848 | equiv_mem <- p0 | |
4849 | ||
4850 | the memory address register was reloaded before the 2nd | |
4851 | insn. */ | |
4852 | if ((! first_p && pseudo_p) | |
4853 | /* We don't use DF for compilation speed sake. So it | |
4854 | is problematic to update live info when we use an | |
4855 | equivalence containing pseudos in more than one | |
4856 | BB. */ | |
4857 | || (pseudo_p && multi_block_pseudo_p (i)) | |
4858 | /* If an init insn was deleted for some reason, cancel | |
4859 | the equiv. We could update the equiv insns after | |
4860 | transformations including an equiv insn deletion | |
4861 | but it is not worthy as such cases are extremely | |
4862 | rare. */ | |
4863 | || contains_deleted_insn_p (ira_reg_equiv[i].init_insns) | |
c6a6cdaa | 4864 | /* If it is not a reverse equivalence, we check that a |
4865 | pseudo in rhs of the init insn is not dying in the | |
4866 | insn. Otherwise, the live info at the beginning of | |
4867 | the corresponding BB might be wrong after we | |
4868 | removed the insn. When the equiv can be a | |
4869 | constant, the right hand side of the init insn can | |
4870 | be a pseudo. */ | |
691cfda4 | 4871 | || (! reverse_equiv_p (i) |
4872 | && (init_insn_rhs_dead_pseudo_p (i) | |
4873 | /* If we reloaded the pseudo in an equivalence | |
f4d3c071 | 4874 | init insn, we cannot remove the equiv init |
691cfda4 | 4875 | insns and the init insns might write into |
4876 | const memory in this case. */ | |
4877 | || contains_reloaded_insn_p (i))) | |
fc8a0f60 | 4878 | /* Prevent access beyond equivalent memory for |
4879 | paradoxical subregs. */ | |
4880 | || (MEM_P (x) | |
52acb7ae | 4881 | && maybe_gt (GET_MODE_SIZE (lra_reg_info[i].biggest_mode), |
4882 | GET_MODE_SIZE (GET_MODE (x)))) | |
a9d8ab38 | 4883 | || (pic_offset_table_rtx |
4884 | && ((CONST_POOL_OK_P (PSEUDO_REGNO_MODE (i), x) | |
4885 | && (targetm.preferred_reload_class | |
4886 | (x, lra_get_allocno_class (i)) == NO_REGS)) | |
bf9df576 | 4887 | || contains_symbol_ref_p (x)))) |
c6a6cdaa | 4888 | ira_reg_equiv[i].defined_p = false; |
c6a6cdaa | 4889 | if (contains_reg_p (x, false, true)) |
4890 | ira_reg_equiv[i].profitable_p = false; | |
3b3a5e5f | 4891 | if (get_equiv (reg) != reg) |
f6708c36 | 4892 | bitmap_ior_into (equiv_insn_bitmap, &lra_reg_info[i].insn_bitmap); |
c6a6cdaa | 4893 | } |
4894 | } | |
61cd3e57 | 4895 | for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++) |
4896 | update_equiv (i); | |
f7b7100e | 4897 | /* We should add all insns containing pseudos which should be |
4898 | substituted by their equivalences. */ | |
f6708c36 | 4899 | EXECUTE_IF_SET_IN_BITMAP (equiv_insn_bitmap, 0, uid, bi) |
f7b7100e | 4900 | lra_push_insn_by_uid (uid); |
c6a6cdaa | 4901 | min_len = lra_insn_stack_length (); |
4902 | new_insns_num = 0; | |
4903 | last_bb = NULL; | |
4904 | changed_p = false; | |
4905 | while ((new_min_len = lra_insn_stack_length ()) != 0) | |
4906 | { | |
4907 | curr_insn = lra_pop_insn (); | |
4908 | --new_min_len; | |
1a8f8886 | 4909 | curr_bb = BLOCK_FOR_INSN (curr_insn); |
c6a6cdaa | 4910 | if (curr_bb != last_bb) |
4911 | { | |
4912 | last_bb = curr_bb; | |
4913 | bb_reload_num = lra_curr_reload_num; | |
4914 | } | |
4915 | if (min_len > new_min_len) | |
4916 | { | |
4917 | min_len = new_min_len; | |
4918 | new_insns_num = 0; | |
4919 | } | |
4920 | if (new_insns_num > MAX_RELOAD_INSNS_NUMBER) | |
4921 | internal_error | |
85b9be9b | 4922 | ("maximum number of generated reload insns per insn achieved (%d)", |
c6a6cdaa | 4923 | MAX_RELOAD_INSNS_NUMBER); |
4924 | new_insns_num++; | |
4925 | if (DEBUG_INSN_P (curr_insn)) | |
4926 | { | |
4927 | /* We need to check equivalence in debug insn and change | |
4928 | pseudo to the equivalent value if necessary. */ | |
4929 | curr_id = lra_get_insn_recog_data (curr_insn); | |
f6708c36 | 4930 | if (bitmap_bit_p (equiv_insn_bitmap, INSN_UID (curr_insn))) |
e717b69a | 4931 | { |
136e5c8e | 4932 | rtx old = *curr_id->operand_loc[0]; |
4933 | *curr_id->operand_loc[0] | |
4934 | = simplify_replace_fn_rtx (old, NULL_RTX, | |
61cd3e57 | 4935 | loc_equivalence_callback, curr_insn); |
136e5c8e | 4936 | if (old != *curr_id->operand_loc[0]) |
4937 | { | |
4938 | lra_update_insn_regno_info (curr_insn); | |
4939 | changed_p = true; | |
4940 | } | |
e717b69a | 4941 | } |
c6a6cdaa | 4942 | } |
4943 | else if (INSN_P (curr_insn)) | |
4944 | { | |
4945 | if ((set = single_set (curr_insn)) != NULL_RTX) | |
4946 | { | |
4947 | dest_reg = SET_DEST (set); | |
4948 | /* The equivalence pseudo could be set up as SUBREG in a | |
4949 | case when it is a call restore insn in a mode | |
4950 | different from the pseudo mode. */ | |
4951 | if (GET_CODE (dest_reg) == SUBREG) | |
4952 | dest_reg = SUBREG_REG (dest_reg); | |
4953 | if ((REG_P (dest_reg) | |
3b3a5e5f | 4954 | && (x = get_equiv (dest_reg)) != dest_reg |
c6a6cdaa | 4955 | /* Remove insns which set up a pseudo whose value |
f4d3c071 | 4956 | cannot be changed. Such insns might be not in |
c6a6cdaa | 4957 | init_insns because we don't update equiv data |
4958 | during insn transformations. | |
c625778b | 4959 | |
c6a6cdaa | 4960 | As an example, let suppose that a pseudo got |
4961 | hard register and on the 1st pass was not | |
4962 | changed to equivalent constant. We generate an | |
4963 | additional insn setting up the pseudo because of | |
4964 | secondary memory movement. Then the pseudo is | |
4965 | spilled and we use the equiv constant. In this | |
4966 | case we should remove the additional insn and | |
e454a550 | 4967 | this insn is not init_insns list. */ |
c6a6cdaa | 4968 | && (! MEM_P (x) || MEM_READONLY_P (x) |
e454a550 | 4969 | /* Check that this is actually an insn setting |
4970 | up the equivalence. */ | |
c6a6cdaa | 4971 | || in_list_p (curr_insn, |
4972 | ira_reg_equiv | |
4973 | [REGNO (dest_reg)].init_insns))) | |
3b3a5e5f | 4974 | || (((x = get_equiv (SET_SRC (set))) != SET_SRC (set)) |
c6a6cdaa | 4975 | && in_list_p (curr_insn, |
4976 | ira_reg_equiv | |
4977 | [REGNO (SET_SRC (set))].init_insns))) | |
4978 | { | |
4979 | /* This is equiv init insn of pseudo which did not get a | |
4980 | hard register -- remove the insn. */ | |
4981 | if (lra_dump_file != NULL) | |
4982 | { | |
4983 | fprintf (lra_dump_file, | |
4984 | " Removing equiv init insn %i (freq=%d)\n", | |
4985 | INSN_UID (curr_insn), | |
e374deeb | 4986 | REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn))); |
6dde9719 | 4987 | dump_insn_slim (lra_dump_file, curr_insn); |
c6a6cdaa | 4988 | } |
4989 | if (contains_reg_p (x, true, false)) | |
4990 | lra_risky_transformations_p = true; | |
4991 | lra_set_insn_deleted (curr_insn); | |
4992 | continue; | |
4993 | } | |
4994 | } | |
4995 | curr_id = lra_get_insn_recog_data (curr_insn); | |
4996 | curr_static_id = curr_id->insn_static_data; | |
4997 | init_curr_insn_input_reloads (); | |
4998 | init_curr_operand_mode (); | |
497ba60f | 4999 | if (curr_insn_transform (false)) |
c6a6cdaa | 5000 | changed_p = true; |
d596f8db | 5001 | /* Check non-transformed insns too for equiv change as USE |
5002 | or CLOBBER don't need reloads but can contain pseudos | |
5003 | being changed on their equivalences. */ | |
f6708c36 | 5004 | else if (bitmap_bit_p (equiv_insn_bitmap, INSN_UID (curr_insn)) |
d596f8db | 5005 | && loc_equivalence_change_p (&PATTERN (curr_insn))) |
5006 | { | |
5007 | lra_update_insn_regno_info (curr_insn); | |
5008 | changed_p = true; | |
5009 | } | |
c6a6cdaa | 5010 | } |
5011 | } | |
f6708c36 | 5012 | |
c6a6cdaa | 5013 | /* If we used a new hard regno, changed_p should be true because the |
5014 | hard reg is assigned to a new pseudo. */ | |
382ecba7 | 5015 | if (flag_checking && !changed_p) |
c6a6cdaa | 5016 | { |
5017 | for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++) | |
5018 | if (lra_reg_info[i].nrefs != 0 | |
5019 | && (hard_regno = lra_get_regno_hard_regno (i)) >= 0) | |
5020 | { | |
92d2aec3 | 5021 | int j, nregs = hard_regno_nregs (hard_regno, |
5022 | PSEUDO_REGNO_MODE (i)); | |
1a8f8886 | 5023 | |
c6a6cdaa | 5024 | for (j = 0; j < nregs; j++) |
5025 | lra_assert (df_regs_ever_live_p (hard_regno + j)); | |
5026 | } | |
5027 | } | |
c6a6cdaa | 5028 | return changed_p; |
5029 | } | |
5030 | ||
ab4ea053 | 5031 | static void initiate_invariants (void); |
5032 | static void finish_invariants (void); | |
5033 | ||
c6a6cdaa | 5034 | /* Initiate the LRA constraint pass. It is done once per |
5035 | function. */ | |
5036 | void | |
5037 | lra_constraints_init (void) | |
5038 | { | |
ab4ea053 | 5039 | initiate_invariants (); |
c6a6cdaa | 5040 | } |
5041 | ||
5042 | /* Finalize the LRA constraint pass. It is done once per | |
5043 | function. */ | |
5044 | void | |
5045 | lra_constraints_finish (void) | |
5046 | { | |
ab4ea053 | 5047 | finish_invariants (); |
5048 | } | |
5049 | ||
5050 | \f | |
5051 | ||
5052 | /* Structure describes invariants for ineheritance. */ | |
1cda36f6 | 5053 | struct lra_invariant |
ab4ea053 | 5054 | { |
5055 | /* The order number of the invariant. */ | |
5056 | int num; | |
5057 | /* The invariant RTX. */ | |
5058 | rtx invariant_rtx; | |
5059 | /* The origin insn of the invariant. */ | |
5060 | rtx_insn *insn; | |
5061 | }; | |
5062 | ||
1cda36f6 | 5063 | typedef lra_invariant invariant_t; |
ab4ea053 | 5064 | typedef invariant_t *invariant_ptr_t; |
5065 | typedef const invariant_t *const_invariant_ptr_t; | |
5066 | ||
5067 | /* Pointer to the inheritance invariants. */ | |
5068 | static vec<invariant_ptr_t> invariants; | |
5069 | ||
5070 | /* Allocation pool for the invariants. */ | |
1cda36f6 | 5071 | static object_allocator<lra_invariant> *invariants_pool; |
ab4ea053 | 5072 | |
5073 | /* Hash table for the invariants. */ | |
5074 | static htab_t invariant_table; | |
5075 | ||
5076 | /* Hash function for INVARIANT. */ | |
5077 | static hashval_t | |
5078 | invariant_hash (const void *invariant) | |
5079 | { | |
5080 | rtx inv = ((const_invariant_ptr_t) invariant)->invariant_rtx; | |
5081 | return lra_rtx_hash (inv); | |
5082 | } | |
5083 | ||
5084 | /* Equal function for invariants INVARIANT1 and INVARIANT2. */ | |
5085 | static int | |
5086 | invariant_eq_p (const void *invariant1, const void *invariant2) | |
5087 | { | |
5088 | rtx inv1 = ((const_invariant_ptr_t) invariant1)->invariant_rtx; | |
5089 | rtx inv2 = ((const_invariant_ptr_t) invariant2)->invariant_rtx; | |
5090 | ||
5091 | return rtx_equal_p (inv1, inv2); | |
5092 | } | |
5093 | ||
5094 | /* Insert INVARIANT_RTX into the table if it is not there yet. Return | |
5095 | invariant which is in the table. */ | |
5096 | static invariant_ptr_t | |
5097 | insert_invariant (rtx invariant_rtx) | |
5098 | { | |
5099 | void **entry_ptr; | |
5100 | invariant_t invariant; | |
5101 | invariant_ptr_t invariant_ptr; | |
5102 | ||
5103 | invariant.invariant_rtx = invariant_rtx; | |
5104 | entry_ptr = htab_find_slot (invariant_table, &invariant, INSERT); | |
5105 | if (*entry_ptr == NULL) | |
5106 | { | |
5107 | invariant_ptr = invariants_pool->allocate (); | |
5108 | invariant_ptr->invariant_rtx = invariant_rtx; | |
5109 | invariant_ptr->insn = NULL; | |
5110 | invariants.safe_push (invariant_ptr); | |
5111 | *entry_ptr = (void *) invariant_ptr; | |
5112 | } | |
5113 | return (invariant_ptr_t) *entry_ptr; | |
5114 | } | |
5115 | ||
5116 | /* Initiate the invariant table. */ | |
5117 | static void | |
5118 | initiate_invariants (void) | |
5119 | { | |
5120 | invariants.create (100); | |
1cda36f6 | 5121 | invariants_pool |
5122 | = new object_allocator<lra_invariant> ("Inheritance invariants"); | |
ab4ea053 | 5123 | invariant_table = htab_create (100, invariant_hash, invariant_eq_p, NULL); |
5124 | } | |
5125 | ||
5126 | /* Finish the invariant table. */ | |
5127 | static void | |
5128 | finish_invariants (void) | |
5129 | { | |
5130 | htab_delete (invariant_table); | |
5131 | delete invariants_pool; | |
5132 | invariants.release (); | |
5133 | } | |
5134 | ||
5135 | /* Make the invariant table empty. */ | |
5136 | static void | |
5137 | clear_invariants (void) | |
5138 | { | |
5139 | htab_empty (invariant_table); | |
5140 | invariants_pool->release (); | |
5141 | invariants.truncate (0); | |
c6a6cdaa | 5142 | } |
5143 | ||
5144 | \f | |
5145 | ||
5146 | /* This page contains code to do inheritance/split | |
5147 | transformations. */ | |
5148 | ||
5149 | /* Number of reloads passed so far in current EBB. */ | |
5150 | static int reloads_num; | |
5151 | ||
5152 | /* Number of calls passed so far in current EBB. */ | |
5153 | static int calls_num; | |
5154 | ||
5155 | /* Current reload pseudo check for validity of elements in | |
5156 | USAGE_INSNS. */ | |
5157 | static int curr_usage_insns_check; | |
5158 | ||
5159 | /* Info about last usage of registers in EBB to do inheritance/split | |
5160 | transformation. Inheritance transformation is done from a spilled | |
5161 | pseudo and split transformations from a hard register or a pseudo | |
5162 | assigned to a hard register. */ | |
5163 | struct usage_insns | |
5164 | { | |
5165 | /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member | |
5166 | value INSNS is valid. The insns is chain of optional debug insns | |
cc0dc61b | 5167 | and a finishing non-debug insn using the corresponding reg. The |
5168 | value is also used to mark the registers which are set up in the | |
5169 | current insn. The negated insn uid is used for this. */ | |
c6a6cdaa | 5170 | int check; |
5171 | /* Value of global reloads_num at the last insn in INSNS. */ | |
5172 | int reloads_num; | |
5173 | /* Value of global reloads_nums at the last insn in INSNS. */ | |
5174 | int calls_num; | |
5175 | /* It can be true only for splitting. And it means that the restore | |
5176 | insn should be put after insn given by the following member. */ | |
5177 | bool after_p; | |
5178 | /* Next insns in the current EBB which use the original reg and the | |
5179 | original reg value is not changed between the current insn and | |
5180 | the next insns. In order words, e.g. for inheritance, if we need | |
5181 | to use the original reg value again in the next insns we can try | |
5182 | to use the value in a hard register from a reload insn of the | |
5183 | current insn. */ | |
5184 | rtx insns; | |
5185 | }; | |
5186 | ||
5187 | /* Map: regno -> corresponding pseudo usage insns. */ | |
5188 | static struct usage_insns *usage_insns; | |
5189 | ||
5190 | static void | |
f9a00e9e | 5191 | setup_next_usage_insn (int regno, rtx insn, int reloads_num, bool after_p) |
c6a6cdaa | 5192 | { |
5193 | usage_insns[regno].check = curr_usage_insns_check; | |
5194 | usage_insns[regno].insns = insn; | |
5195 | usage_insns[regno].reloads_num = reloads_num; | |
5196 | usage_insns[regno].calls_num = calls_num; | |
5197 | usage_insns[regno].after_p = after_p; | |
5198 | } | |
5199 | ||
5200 | /* The function is used to form list REGNO usages which consists of | |
5201 | optional debug insns finished by a non-debug insn using REGNO. | |
5202 | RELOADS_NUM is current number of reload insns processed so far. */ | |
5203 | static void | |
06743455 | 5204 | add_next_usage_insn (int regno, rtx_insn *insn, int reloads_num) |
c6a6cdaa | 5205 | { |
5206 | rtx next_usage_insns; | |
1a8f8886 | 5207 | |
c6a6cdaa | 5208 | if (usage_insns[regno].check == curr_usage_insns_check |
5209 | && (next_usage_insns = usage_insns[regno].insns) != NULL_RTX | |
5210 | && DEBUG_INSN_P (insn)) | |
5211 | { | |
5212 | /* Check that we did not add the debug insn yet. */ | |
5213 | if (next_usage_insns != insn | |
5214 | && (GET_CODE (next_usage_insns) != INSN_LIST | |
5215 | || XEXP (next_usage_insns, 0) != insn)) | |
5216 | usage_insns[regno].insns = gen_rtx_INSN_LIST (VOIDmode, insn, | |
5217 | next_usage_insns); | |
5218 | } | |
5219 | else if (NONDEBUG_INSN_P (insn)) | |
5220 | setup_next_usage_insn (regno, insn, reloads_num, false); | |
5221 | else | |
5222 | usage_insns[regno].check = 0; | |
5223 | } | |
1a8f8886 | 5224 | |
5bb0e0fd | 5225 | /* Return first non-debug insn in list USAGE_INSNS. */ |
50fc2d35 | 5226 | static rtx_insn * |
5bb0e0fd | 5227 | skip_usage_debug_insns (rtx usage_insns) |
5228 | { | |
5229 | rtx insn; | |
5230 | ||
5231 | /* Skip debug insns. */ | |
5232 | for (insn = usage_insns; | |
5233 | insn != NULL_RTX && GET_CODE (insn) == INSN_LIST; | |
5234 | insn = XEXP (insn, 1)) | |
5235 | ; | |
50fc2d35 | 5236 | return safe_as_a <rtx_insn *> (insn); |
5bb0e0fd | 5237 | } |
5238 | ||
5239 | /* Return true if we need secondary memory moves for insn in | |
5240 | USAGE_INSNS after inserting inherited pseudo of class INHER_CL | |
5241 | into the insn. */ | |
5242 | static bool | |
acb7fe1f | 5243 | check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED, |
5244 | rtx usage_insns ATTRIBUTE_UNUSED) | |
5bb0e0fd | 5245 | { |
50fc2d35 | 5246 | rtx_insn *insn; |
5247 | rtx set, dest; | |
5bb0e0fd | 5248 | enum reg_class cl; |
5249 | ||
5250 | if (inher_cl == ALL_REGS | |
5251 | || (insn = skip_usage_debug_insns (usage_insns)) == NULL_RTX) | |
5252 | return false; | |
5253 | lra_assert (INSN_P (insn)); | |
5254 | if ((set = single_set (insn)) == NULL_RTX || ! REG_P (SET_DEST (set))) | |
5255 | return false; | |
5256 | dest = SET_DEST (set); | |
5257 | if (! REG_P (dest)) | |
5258 | return false; | |
5259 | lra_assert (inher_cl != NO_REGS); | |
5260 | cl = get_reg_class (REGNO (dest)); | |
5261 | return (cl != NO_REGS && cl != ALL_REGS | |
c836e75b | 5262 | && targetm.secondary_memory_needed (GET_MODE (dest), inher_cl, cl)); |
5bb0e0fd | 5263 | } |
5264 | ||
c6a6cdaa | 5265 | /* Registers involved in inheritance/split in the current EBB |
5266 | (inheritance/split pseudos and original registers). */ | |
5267 | static bitmap_head check_only_regs; | |
5268 | ||
f4d3c071 | 5269 | /* Reload pseudos cannot be involded in invariant inheritance in the |
ab4ea053 | 5270 | current EBB. */ |
5271 | static bitmap_head invalid_invariant_regs; | |
5272 | ||
c6a6cdaa | 5273 | /* Do inheritance transformations for insn INSN, which defines (if |
5274 | DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which | |
5275 | instruction in the EBB next uses ORIGINAL_REGNO; it has the same | |
5276 | form as the "insns" field of usage_insns. Return true if we | |
5277 | succeed in such transformation. | |
5278 | ||
5279 | The transformations look like: | |
5280 | ||
5281 | p <- ... i <- ... | |
5282 | ... p <- i (new insn) | |
5283 | ... => | |
5284 | <- ... p ... <- ... i ... | |
5285 | or | |
5286 | ... i <- p (new insn) | |
5287 | <- ... p ... <- ... i ... | |
5288 | ... => | |
5289 | <- ... p ... <- ... i ... | |
5290 | where p is a spilled original pseudo and i is a new inheritance pseudo. | |
1a8f8886 | 5291 | |
5292 | ||
c6a6cdaa | 5293 | The inheritance pseudo has the smallest class of two classes CL and |
5294 | class of ORIGINAL REGNO. */ | |
5295 | static bool | |
5296 | inherit_reload_reg (bool def_p, int original_regno, | |
7f836b57 | 5297 | enum reg_class cl, rtx_insn *insn, rtx next_usage_insns) |
c6a6cdaa | 5298 | { |
77a00b11 | 5299 | if (optimize_function_for_size_p (cfun)) |
5300 | return false; | |
5301 | ||
c6a6cdaa | 5302 | enum reg_class rclass = lra_get_allocno_class (original_regno); |
5303 | rtx original_reg = regno_reg_rtx[original_regno]; | |
7f836b57 | 5304 | rtx new_reg, usage_insn; |
5305 | rtx_insn *new_insns; | |
c6a6cdaa | 5306 | |
5307 | lra_assert (! usage_insns[original_regno].after_p); | |
5308 | if (lra_dump_file != NULL) | |
5309 | fprintf (lra_dump_file, | |
5bb0e0fd | 5310 | " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n"); |
c6a6cdaa | 5311 | if (! ira_reg_classes_intersect_p[cl][rclass]) |
5312 | { | |
5313 | if (lra_dump_file != NULL) | |
5314 | { | |
5315 | fprintf (lra_dump_file, | |
5bb0e0fd | 5316 | " Rejecting inheritance for %d " |
c6a6cdaa | 5317 | "because of disjoint classes %s and %s\n", |
5318 | original_regno, reg_class_names[cl], | |
5319 | reg_class_names[rclass]); | |
5320 | fprintf (lra_dump_file, | |
5bb0e0fd | 5321 | " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); |
c6a6cdaa | 5322 | } |
5323 | return false; | |
5324 | } | |
5325 | if ((ira_class_subset_p[cl][rclass] && cl != rclass) | |
5326 | /* We don't use a subset of two classes because it can be | |
5327 | NO_REGS. This transformation is still profitable in most | |
5328 | cases even if the classes are not intersected as register | |
5329 | move is probably cheaper than a memory load. */ | |
5330 | || ira_class_hard_regs_num[cl] < ira_class_hard_regs_num[rclass]) | |
5331 | { | |
5332 | if (lra_dump_file != NULL) | |
5333 | fprintf (lra_dump_file, " Use smallest class of %s and %s\n", | |
5334 | reg_class_names[cl], reg_class_names[rclass]); | |
1a8f8886 | 5335 | |
c6a6cdaa | 5336 | rclass = cl; |
5337 | } | |
c47331e3 | 5338 | if (check_secondary_memory_needed_p (rclass, next_usage_insns)) |
5bb0e0fd | 5339 | { |
5340 | /* Reject inheritance resulting in secondary memory moves. | |
5341 | Otherwise, there is a danger in LRA cycling. Also such | |
5342 | transformation will be unprofitable. */ | |
5343 | if (lra_dump_file != NULL) | |
5344 | { | |
50fc2d35 | 5345 | rtx_insn *insn = skip_usage_debug_insns (next_usage_insns); |
5bb0e0fd | 5346 | rtx set = single_set (insn); |
5347 | ||
5348 | lra_assert (set != NULL_RTX); | |
5349 | ||
5350 | rtx dest = SET_DEST (set); | |
5351 | ||
5352 | lra_assert (REG_P (dest)); | |
5353 | fprintf (lra_dump_file, | |
5354 | " Rejecting inheritance for insn %d(%s)<-%d(%s) " | |
5355 | "as secondary mem is needed\n", | |
5356 | REGNO (dest), reg_class_names[get_reg_class (REGNO (dest))], | |
c47331e3 | 5357 | original_regno, reg_class_names[rclass]); |
5bb0e0fd | 5358 | fprintf (lra_dump_file, |
5359 | " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); | |
5360 | } | |
5361 | return false; | |
5362 | } | |
c6a6cdaa | 5363 | new_reg = lra_create_new_reg (GET_MODE (original_reg), original_reg, |
5364 | rclass, "inheritance"); | |
5365 | start_sequence (); | |
5366 | if (def_p) | |
ef0231e9 | 5367 | lra_emit_move (original_reg, new_reg); |
c6a6cdaa | 5368 | else |
ef0231e9 | 5369 | lra_emit_move (new_reg, original_reg); |
c6a6cdaa | 5370 | new_insns = get_insns (); |
5371 | end_sequence (); | |
5372 | if (NEXT_INSN (new_insns) != NULL_RTX) | |
5373 | { | |
5374 | if (lra_dump_file != NULL) | |
5375 | { | |
5376 | fprintf (lra_dump_file, | |
5bb0e0fd | 5377 | " Rejecting inheritance %d->%d " |
c6a6cdaa | 5378 | "as it results in 2 or more insns:\n", |
5379 | original_regno, REGNO (new_reg)); | |
4cd001d5 | 5380 | dump_rtl_slim (lra_dump_file, new_insns, NULL, -1, 0); |
c6a6cdaa | 5381 | fprintf (lra_dump_file, |
5382 | " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); | |
5383 | } | |
5384 | return false; | |
5385 | } | |
06072e79 | 5386 | lra_substitute_pseudo_within_insn (insn, original_regno, new_reg, false); |
c6a6cdaa | 5387 | lra_update_insn_regno_info (insn); |
5388 | if (! def_p) | |
5389 | /* We now have a new usage insn for original regno. */ | |
5390 | setup_next_usage_insn (original_regno, new_insns, reloads_num, false); | |
5391 | if (lra_dump_file != NULL) | |
5bb0e0fd | 5392 | fprintf (lra_dump_file, " Original reg change %d->%d (bb%d):\n", |
c6a6cdaa | 5393 | original_regno, REGNO (new_reg), BLOCK_FOR_INSN (insn)->index); |
ab4ea053 | 5394 | lra_reg_info[REGNO (new_reg)].restore_rtx = regno_reg_rtx[original_regno]; |
c6a6cdaa | 5395 | bitmap_set_bit (&check_only_regs, REGNO (new_reg)); |
5396 | bitmap_set_bit (&check_only_regs, original_regno); | |
5397 | bitmap_set_bit (&lra_inheritance_pseudos, REGNO (new_reg)); | |
5398 | if (def_p) | |
7f836b57 | 5399 | lra_process_new_insns (insn, NULL, new_insns, |
c6a6cdaa | 5400 | "Add original<-inheritance"); |
5401 | else | |
7f836b57 | 5402 | lra_process_new_insns (insn, new_insns, NULL, |
c6a6cdaa | 5403 | "Add inheritance<-original"); |
5404 | while (next_usage_insns != NULL_RTX) | |
5405 | { | |
5406 | if (GET_CODE (next_usage_insns) != INSN_LIST) | |
5407 | { | |
5408 | usage_insn = next_usage_insns; | |
5409 | lra_assert (NONDEBUG_INSN_P (usage_insn)); | |
5410 | next_usage_insns = NULL; | |
5411 | } | |
5412 | else | |
5413 | { | |
5414 | usage_insn = XEXP (next_usage_insns, 0); | |
5415 | lra_assert (DEBUG_INSN_P (usage_insn)); | |
5416 | next_usage_insns = XEXP (next_usage_insns, 1); | |
5417 | } | |
d686eece | 5418 | lra_substitute_pseudo (&usage_insn, original_regno, new_reg, false, |
5419 | DEBUG_INSN_P (usage_insn)); | |
7f836b57 | 5420 | lra_update_insn_regno_info (as_a <rtx_insn *> (usage_insn)); |
c6a6cdaa | 5421 | if (lra_dump_file != NULL) |
5422 | { | |
90567983 | 5423 | basic_block bb = BLOCK_FOR_INSN (usage_insn); |
c6a6cdaa | 5424 | fprintf (lra_dump_file, |
5425 | " Inheritance reuse change %d->%d (bb%d):\n", | |
5426 | original_regno, REGNO (new_reg), | |
90567983 | 5427 | bb ? bb->index : -1); |
f9a00e9e | 5428 | dump_insn_slim (lra_dump_file, as_a <rtx_insn *> (usage_insn)); |
c6a6cdaa | 5429 | } |
5430 | } | |
5431 | if (lra_dump_file != NULL) | |
5432 | fprintf (lra_dump_file, | |
5433 | " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); | |
5434 | return true; | |
5435 | } | |
5436 | ||
5437 | /* Return true if we need a caller save/restore for pseudo REGNO which | |
5438 | was assigned to a hard register. */ | |
5439 | static inline bool | |
5440 | need_for_call_save_p (int regno) | |
5441 | { | |
5442 | lra_assert (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] >= 0); | |
5443 | return (usage_insns[regno].calls_num < calls_num | |
5444 | && (overlaps_hard_reg_set_p | |
fcf56aaf | 5445 | ((flag_ipa_ra && |
f2cc6708 | 5446 | ! hard_reg_set_empty_p (lra_reg_info[regno].actual_call_used_reg_set)) |
5447 | ? lra_reg_info[regno].actual_call_used_reg_set | |
5448 | : call_used_reg_set, | |
a766a8b0 | 5449 | PSEUDO_REGNO_MODE (regno), reg_renumber[regno]) |
5da94e60 | 5450 | || (targetm.hard_regno_call_part_clobbered |
5c62f29a | 5451 | (lra_reg_info[regno].call_insn, |
5452 | reg_renumber[regno], PSEUDO_REGNO_MODE (regno))))); | |
c6a6cdaa | 5453 | } |
5454 | ||
75de4aa2 | 5455 | /* Global registers occurring in the current EBB. */ |
c6a6cdaa | 5456 | static bitmap_head ebb_global_regs; |
5457 | ||
5458 | /* Return true if we need a split for hard register REGNO or pseudo | |
5459 | REGNO which was assigned to a hard register. | |
5460 | POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be | |
5461 | used for reloads since the EBB end. It is an approximation of the | |
5462 | used hard registers in the split range. The exact value would | |
5463 | require expensive calculations. If we were aggressive with | |
5464 | splitting because of the approximation, the split pseudo will save | |
5465 | the same hard register assignment and will be removed in the undo | |
5466 | pass. We still need the approximation because too aggressive | |
5467 | splitting would result in too inaccurate cost calculation in the | |
5468 | assignment pass because of too many generated moves which will be | |
5469 | probably removed in the undo pass. */ | |
5470 | static inline bool | |
5471 | need_for_split_p (HARD_REG_SET potential_reload_hard_regs, int regno) | |
5472 | { | |
5473 | int hard_regno = regno < FIRST_PSEUDO_REGISTER ? regno : reg_renumber[regno]; | |
5474 | ||
5475 | lra_assert (hard_regno >= 0); | |
5476 | return ((TEST_HARD_REG_BIT (potential_reload_hard_regs, hard_regno) | |
5477 | /* Don't split eliminable hard registers, otherwise we can | |
5478 | split hard registers like hard frame pointer, which | |
5479 | lives on BB start/end according to DF-infrastructure, | |
5480 | when there is a pseudo assigned to the register and | |
5481 | living in the same BB. */ | |
5482 | && (regno >= FIRST_PSEUDO_REGISTER | |
5483 | || ! TEST_HARD_REG_BIT (eliminable_regset, hard_regno)) | |
5484 | && ! TEST_HARD_REG_BIT (lra_no_alloc_regs, hard_regno) | |
0157439c | 5485 | /* Don't split call clobbered hard regs living through |
5486 | calls, otherwise we might have a check problem in the | |
5487 | assign sub-pass as in the most cases (exception is a | |
5488 | situation when lra_risky_transformations_p value is | |
5489 | true) the assign pass assumes that all pseudos living | |
5490 | through calls are assigned to call saved hard regs. */ | |
5491 | && (regno >= FIRST_PSEUDO_REGISTER | |
5492 | || ! TEST_HARD_REG_BIT (call_used_reg_set, regno) | |
5493 | || usage_insns[regno].calls_num == calls_num) | |
c6a6cdaa | 5494 | /* We need at least 2 reloads to make pseudo splitting |
5495 | profitable. We should provide hard regno splitting in | |
5496 | any case to solve 1st insn scheduling problem when | |
5497 | moving hard register definition up might result in | |
5498 | impossibility to find hard register for reload pseudo of | |
5499 | small register class. */ | |
5500 | && (usage_insns[regno].reloads_num | |
7eec3701 | 5501 | + (regno < FIRST_PSEUDO_REGISTER ? 0 : 3) < reloads_num) |
c6a6cdaa | 5502 | && (regno < FIRST_PSEUDO_REGISTER |
5503 | /* For short living pseudos, spilling + inheritance can | |
5504 | be considered a substitution for splitting. | |
5505 | Therefore we do not splitting for local pseudos. It | |
5506 | decreases also aggressiveness of splitting. The | |
5507 | minimal number of references is chosen taking into | |
5508 | account that for 2 references splitting has no sense | |
5509 | as we can just spill the pseudo. */ | |
5510 | || (regno >= FIRST_PSEUDO_REGISTER | |
5511 | && lra_reg_info[regno].nrefs > 3 | |
5512 | && bitmap_bit_p (&ebb_global_regs, regno)))) | |
5513 | || (regno >= FIRST_PSEUDO_REGISTER && need_for_call_save_p (regno))); | |
5514 | } | |
5515 | ||
5516 | /* Return class for the split pseudo created from original pseudo with | |
5517 | ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We | |
5518 | choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and | |
5519 | results in no secondary memory movements. */ | |
5520 | static enum reg_class | |
5521 | choose_split_class (enum reg_class allocno_class, | |
5522 | int hard_regno ATTRIBUTE_UNUSED, | |
3754d046 | 5523 | machine_mode mode ATTRIBUTE_UNUSED) |
c6a6cdaa | 5524 | { |
c6a6cdaa | 5525 | int i; |
5526 | enum reg_class cl, best_cl = NO_REGS; | |
d810a474 | 5527 | enum reg_class hard_reg_class ATTRIBUTE_UNUSED |
5528 | = REGNO_REG_CLASS (hard_regno); | |
1a8f8886 | 5529 | |
c836e75b | 5530 | if (! targetm.secondary_memory_needed (mode, allocno_class, allocno_class) |
c6a6cdaa | 5531 | && TEST_HARD_REG_BIT (reg_class_contents[allocno_class], hard_regno)) |
5532 | return allocno_class; | |
5533 | for (i = 0; | |
5534 | (cl = reg_class_subclasses[allocno_class][i]) != LIM_REG_CLASSES; | |
5535 | i++) | |
c836e75b | 5536 | if (! targetm.secondary_memory_needed (mode, cl, hard_reg_class) |
5537 | && ! targetm.secondary_memory_needed (mode, hard_reg_class, cl) | |
c6a6cdaa | 5538 | && TEST_HARD_REG_BIT (reg_class_contents[cl], hard_regno) |
5539 | && (best_cl == NO_REGS | |
5540 | || ira_class_hard_regs_num[best_cl] < ira_class_hard_regs_num[cl])) | |
5541 | best_cl = cl; | |
5542 | return best_cl; | |
c6a6cdaa | 5543 | } |
5544 | ||
cc39a634 | 5545 | /* Copy any equivalence information from ORIGINAL_REGNO to NEW_REGNO. |
5546 | It only makes sense to call this function if NEW_REGNO is always | |
5547 | equal to ORIGINAL_REGNO. */ | |
5548 | ||
5549 | static void | |
5550 | lra_copy_reg_equiv (unsigned int new_regno, unsigned int original_regno) | |
5551 | { | |
5552 | if (!ira_reg_equiv[original_regno].defined_p) | |
5553 | return; | |
5554 | ||
5555 | ira_expand_reg_equiv (); | |
5556 | ira_reg_equiv[new_regno].defined_p = true; | |
5557 | if (ira_reg_equiv[original_regno].memory) | |
5558 | ira_reg_equiv[new_regno].memory | |
5559 | = copy_rtx (ira_reg_equiv[original_regno].memory); | |
5560 | if (ira_reg_equiv[original_regno].constant) | |
5561 | ira_reg_equiv[new_regno].constant | |
5562 | = copy_rtx (ira_reg_equiv[original_regno].constant); | |
5563 | if (ira_reg_equiv[original_regno].invariant) | |
5564 | ira_reg_equiv[new_regno].invariant | |
5565 | = copy_rtx (ira_reg_equiv[original_regno].invariant); | |
5566 | } | |
5567 | ||
c6a6cdaa | 5568 | /* Do split transformations for insn INSN, which defines or uses |
5569 | ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in | |
5570 | the EBB next uses ORIGINAL_REGNO; it has the same form as the | |
6a4bc24e | 5571 | "insns" field of usage_insns. If TO is not NULL, we don't use |
7fe7987e | 5572 | usage_insns, we put restore insns after TO insn. It is a case when |
5573 | we call it from lra_split_hard_reg_for, outside the inheritance | |
5574 | pass. | |
c6a6cdaa | 5575 | |
5576 | The transformations look like: | |
5577 | ||
5578 | p <- ... p <- ... | |
5579 | ... s <- p (new insn -- save) | |
5580 | ... => | |
5581 | ... p <- s (new insn -- restore) | |
5582 | <- ... p ... <- ... p ... | |
5583 | or | |
5584 | <- ... p ... <- ... p ... | |
5585 | ... s <- p (new insn -- save) | |
5586 | ... => | |
5587 | ... p <- s (new insn -- restore) | |
5588 | <- ... p ... <- ... p ... | |
5589 | ||
5590 | where p is an original pseudo got a hard register or a hard | |
5591 | register and s is a new split pseudo. The save is put before INSN | |
5592 | if BEFORE_P is true. Return true if we succeed in such | |
5593 | transformation. */ | |
5594 | static bool | |
7f836b57 | 5595 | split_reg (bool before_p, int original_regno, rtx_insn *insn, |
6a4bc24e | 5596 | rtx next_usage_insns, rtx_insn *to) |
c6a6cdaa | 5597 | { |
5598 | enum reg_class rclass; | |
5599 | rtx original_reg; | |
74855d08 | 5600 | int hard_regno, nregs; |
7f836b57 | 5601 | rtx new_reg, usage_insn; |
5602 | rtx_insn *restore, *save; | |
c6a6cdaa | 5603 | bool after_p; |
5604 | bool call_save_p; | |
e947f9c3 | 5605 | machine_mode mode; |
c6a6cdaa | 5606 | |
5607 | if (original_regno < FIRST_PSEUDO_REGISTER) | |
5608 | { | |
5609 | rclass = ira_allocno_class_translate[REGNO_REG_CLASS (original_regno)]; | |
5610 | hard_regno = original_regno; | |
5611 | call_save_p = false; | |
74855d08 | 5612 | nregs = 1; |
e947f9c3 | 5613 | mode = lra_reg_info[hard_regno].biggest_mode; |
5614 | machine_mode reg_rtx_mode = GET_MODE (regno_reg_rtx[hard_regno]); | |
e7142ce1 | 5615 | /* A reg can have a biggest_mode of VOIDmode if it was only ever seen |
5616 | as part of a multi-word register. In that case, or if the biggest | |
5617 | mode was larger than a register, just use the reg_rtx. Otherwise, | |
5618 | limit the size to that of the biggest access in the function. */ | |
5619 | if (mode == VOIDmode | |
d0257d43 | 5620 | || paradoxical_subreg_p (mode, reg_rtx_mode)) |
e947f9c3 | 5621 | { |
5622 | original_reg = regno_reg_rtx[hard_regno]; | |
5623 | mode = reg_rtx_mode; | |
5624 | } | |
5625 | else | |
5626 | original_reg = gen_rtx_REG (mode, hard_regno); | |
c6a6cdaa | 5627 | } |
5628 | else | |
5629 | { | |
e947f9c3 | 5630 | mode = PSEUDO_REGNO_MODE (original_regno); |
c6a6cdaa | 5631 | hard_regno = reg_renumber[original_regno]; |
92d2aec3 | 5632 | nregs = hard_regno_nregs (hard_regno, mode); |
c6a6cdaa | 5633 | rclass = lra_get_allocno_class (original_regno); |
5634 | original_reg = regno_reg_rtx[original_regno]; | |
5635 | call_save_p = need_for_call_save_p (original_regno); | |
5636 | } | |
c6a6cdaa | 5637 | lra_assert (hard_regno >= 0); |
5638 | if (lra_dump_file != NULL) | |
5639 | fprintf (lra_dump_file, | |
5640 | " ((((((((((((((((((((((((((((((((((((((((((((((((\n"); | |
e947f9c3 | 5641 | |
c6a6cdaa | 5642 | if (call_save_p) |
5643 | { | |
34575461 | 5644 | mode = HARD_REGNO_CALLER_SAVE_MODE (hard_regno, |
92d2aec3 | 5645 | hard_regno_nregs (hard_regno, mode), |
34575461 | 5646 | mode); |
5647 | new_reg = lra_create_new_reg (mode, NULL_RTX, NO_REGS, "save"); | |
c6a6cdaa | 5648 | } |
5649 | else | |
5650 | { | |
e947f9c3 | 5651 | rclass = choose_split_class (rclass, hard_regno, mode); |
c6a6cdaa | 5652 | if (rclass == NO_REGS) |
5653 | { | |
5654 | if (lra_dump_file != NULL) | |
5655 | { | |
5656 | fprintf (lra_dump_file, | |
5657 | " Rejecting split of %d(%s): " | |
5658 | "no good reg class for %d(%s)\n", | |
5659 | original_regno, | |
5660 | reg_class_names[lra_get_allocno_class (original_regno)], | |
5661 | hard_regno, | |
5662 | reg_class_names[REGNO_REG_CLASS (hard_regno)]); | |
5663 | fprintf | |
5664 | (lra_dump_file, | |
5665 | " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); | |
5666 | } | |
5667 | return false; | |
5668 | } | |
4f031018 | 5669 | /* Split_if_necessary can split hard registers used as part of a |
5670 | multi-register mode but splits each register individually. The | |
5671 | mode used for each independent register may not be supported | |
5672 | so reject the split. Splitting the wider mode should theoretically | |
5673 | be possible but is not implemented. */ | |
b395382f | 5674 | if (!targetm.hard_regno_mode_ok (hard_regno, mode)) |
4f031018 | 5675 | { |
5676 | if (lra_dump_file != NULL) | |
5677 | { | |
5678 | fprintf (lra_dump_file, | |
5679 | " Rejecting split of %d(%s): unsuitable mode %s\n", | |
5680 | original_regno, | |
5681 | reg_class_names[lra_get_allocno_class (original_regno)], | |
5682 | GET_MODE_NAME (mode)); | |
5683 | fprintf | |
5684 | (lra_dump_file, | |
5685 | " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); | |
5686 | } | |
5687 | return false; | |
5688 | } | |
e947f9c3 | 5689 | new_reg = lra_create_new_reg (mode, original_reg, rclass, "split"); |
c6a6cdaa | 5690 | reg_renumber[REGNO (new_reg)] = hard_regno; |
5691 | } | |
cc39a634 | 5692 | int new_regno = REGNO (new_reg); |
c6a6cdaa | 5693 | save = emit_spill_move (true, new_reg, original_reg); |
52793acd | 5694 | if (NEXT_INSN (save) != NULL_RTX && !call_save_p) |
c6a6cdaa | 5695 | { |
c6a6cdaa | 5696 | if (lra_dump_file != NULL) |
5697 | { | |
5698 | fprintf | |
5699 | (lra_dump_file, | |
52793acd | 5700 | " Rejecting split %d->%d resulting in > 2 save insns:\n", |
cc39a634 | 5701 | original_regno, new_regno); |
4cd001d5 | 5702 | dump_rtl_slim (lra_dump_file, save, NULL, -1, 0); |
c6a6cdaa | 5703 | fprintf (lra_dump_file, |
5704 | " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); | |
5705 | } | |
5706 | return false; | |
5707 | } | |
5708 | restore = emit_spill_move (false, new_reg, original_reg); | |
52793acd | 5709 | if (NEXT_INSN (restore) != NULL_RTX && !call_save_p) |
c6a6cdaa | 5710 | { |
c6a6cdaa | 5711 | if (lra_dump_file != NULL) |
5712 | { | |
5713 | fprintf (lra_dump_file, | |
5714 | " Rejecting split %d->%d " | |
52793acd | 5715 | "resulting in > 2 restore insns:\n", |
cc39a634 | 5716 | original_regno, new_regno); |
4cd001d5 | 5717 | dump_rtl_slim (lra_dump_file, restore, NULL, -1, 0); |
c6a6cdaa | 5718 | fprintf (lra_dump_file, |
5719 | " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); | |
5720 | } | |
5721 | return false; | |
5722 | } | |
cc39a634 | 5723 | /* Transfer equivalence information to the spill register, so that |
5724 | if we fail to allocate the spill register, we have the option of | |
5725 | rematerializing the original value instead of spilling to the stack. */ | |
5726 | if (!HARD_REGISTER_NUM_P (original_regno) | |
5727 | && mode == PSEUDO_REGNO_MODE (original_regno)) | |
5728 | lra_copy_reg_equiv (new_regno, original_regno); | |
cc39a634 | 5729 | lra_reg_info[new_regno].restore_rtx = regno_reg_rtx[original_regno]; |
cc39a634 | 5730 | bitmap_set_bit (&lra_split_regs, new_regno); |
6a4bc24e | 5731 | if (to != NULL) |
c6a6cdaa | 5732 | { |
7fe7987e | 5733 | lra_assert (next_usage_insns == NULL); |
6a4bc24e | 5734 | usage_insn = to; |
5735 | after_p = TRUE; | |
5736 | } | |
5737 | else | |
5738 | { | |
7fe7987e | 5739 | /* We need check_only_regs only inside the inheritance pass. */ |
5740 | bitmap_set_bit (&check_only_regs, new_regno); | |
5741 | bitmap_set_bit (&check_only_regs, original_regno); | |
6a4bc24e | 5742 | after_p = usage_insns[original_regno].after_p; |
5743 | for (;;) | |
b12c2c48 | 5744 | { |
6a4bc24e | 5745 | if (GET_CODE (next_usage_insns) != INSN_LIST) |
5746 | { | |
5747 | usage_insn = next_usage_insns; | |
5748 | break; | |
5749 | } | |
5750 | usage_insn = XEXP (next_usage_insns, 0); | |
5751 | lra_assert (DEBUG_INSN_P (usage_insn)); | |
5752 | next_usage_insns = XEXP (next_usage_insns, 1); | |
5753 | lra_substitute_pseudo (&usage_insn, original_regno, new_reg, false, | |
5754 | true); | |
5755 | lra_update_insn_regno_info (as_a <rtx_insn *> (usage_insn)); | |
5756 | if (lra_dump_file != NULL) | |
5757 | { | |
5758 | fprintf (lra_dump_file, " Split reuse change %d->%d:\n", | |
5759 | original_regno, new_regno); | |
5760 | dump_insn_slim (lra_dump_file, as_a <rtx_insn *> (usage_insn)); | |
5761 | } | |
c6a6cdaa | 5762 | } |
5763 | } | |
5764 | lra_assert (NOTE_P (usage_insn) || NONDEBUG_INSN_P (usage_insn)); | |
5765 | lra_assert (usage_insn != insn || (after_p && before_p)); | |
7f836b57 | 5766 | lra_process_new_insns (as_a <rtx_insn *> (usage_insn), |
5767 | after_p ? NULL : restore, | |
5768 | after_p ? restore : NULL, | |
c6a6cdaa | 5769 | call_save_p |
5770 | ? "Add reg<-save" : "Add reg<-split"); | |
7f836b57 | 5771 | lra_process_new_insns (insn, before_p ? save : NULL, |
5772 | before_p ? NULL : save, | |
c6a6cdaa | 5773 | call_save_p |
5774 | ? "Add save<-reg" : "Add split<-reg"); | |
74855d08 | 5775 | if (nregs > 1) |
5776 | /* If we are trying to split multi-register. We should check | |
5777 | conflicts on the next assignment sub-pass. IRA can allocate on | |
5778 | sub-register levels, LRA do this on pseudos level right now and | |
5779 | this discrepancy may create allocation conflicts after | |
5780 | splitting. */ | |
5781 | lra_risky_transformations_p = true; | |
c6a6cdaa | 5782 | if (lra_dump_file != NULL) |
5783 | fprintf (lra_dump_file, | |
5784 | " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); | |
5785 | return true; | |
5786 | } | |
5787 | ||
6a4bc24e | 5788 | /* Split a hard reg for reload pseudo REGNO having RCLASS and living |
5789 | in the range [FROM, TO]. Return true if did a split. Otherwise, | |
5790 | return false. */ | |
5791 | bool | |
5792 | spill_hard_reg_in_range (int regno, enum reg_class rclass, rtx_insn *from, rtx_insn *to) | |
5793 | { | |
5794 | int i, hard_regno; | |
5795 | int rclass_size; | |
5796 | rtx_insn *insn; | |
eaefe34f | 5797 | unsigned int uid; |
5798 | bitmap_iterator bi; | |
5799 | HARD_REG_SET ignore; | |
6a4bc24e | 5800 | |
5801 | lra_assert (from != NULL && to != NULL); | |
eaefe34f | 5802 | CLEAR_HARD_REG_SET (ignore); |
5803 | EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi) | |
5804 | { | |
5805 | lra_insn_recog_data_t id = lra_insn_recog_data[uid]; | |
5806 | struct lra_static_insn_data *static_id = id->insn_static_data; | |
5807 | struct lra_insn_reg *reg; | |
5808 | ||
5809 | for (reg = id->regs; reg != NULL; reg = reg->next) | |
c1031b5a | 5810 | if (reg->regno < FIRST_PSEUDO_REGISTER) |
eaefe34f | 5811 | SET_HARD_REG_BIT (ignore, reg->regno); |
5812 | for (reg = static_id->hard_regs; reg != NULL; reg = reg->next) | |
5813 | SET_HARD_REG_BIT (ignore, reg->regno); | |
5814 | } | |
6a4bc24e | 5815 | rclass_size = ira_class_hard_regs_num[rclass]; |
5816 | for (i = 0; i < rclass_size; i++) | |
5817 | { | |
5818 | hard_regno = ira_class_hard_regs[rclass][i]; | |
eaefe34f | 5819 | if (! TEST_HARD_REG_BIT (lra_reg_info[regno].conflict_hard_regs, hard_regno) |
5820 | || TEST_HARD_REG_BIT (ignore, hard_regno)) | |
6a4bc24e | 5821 | continue; |
5822 | for (insn = from; insn != NEXT_INSN (to); insn = NEXT_INSN (insn)) | |
730ba3b8 | 5823 | { |
6f7735c6 | 5824 | struct lra_static_insn_data *static_id; |
730ba3b8 | 5825 | struct lra_insn_reg *reg; |
5826 | ||
6f7735c6 | 5827 | if (!INSN_P (insn)) |
5828 | continue; | |
5829 | if (bitmap_bit_p (&lra_reg_info[hard_regno].insn_bitmap, | |
5830 | INSN_UID (insn))) | |
730ba3b8 | 5831 | break; |
6f7735c6 | 5832 | static_id = lra_get_insn_recog_data (insn)->insn_static_data; |
730ba3b8 | 5833 | for (reg = static_id->hard_regs; reg != NULL; reg = reg->next) |
5834 | if (reg->regno == hard_regno) | |
5835 | break; | |
5836 | if (reg != NULL) | |
5837 | break; | |
5838 | } | |
6a4bc24e | 5839 | if (insn != NEXT_INSN (to)) |
5840 | continue; | |
5841 | if (split_reg (TRUE, hard_regno, from, NULL, to)) | |
5842 | return true; | |
5843 | } | |
5844 | return false; | |
5845 | } | |
5846 | ||
c6a6cdaa | 5847 | /* Recognize that we need a split transformation for insn INSN, which |
5848 | defines or uses REGNO in its insn biggest MODE (we use it only if | |
5849 | REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains | |
5850 | hard registers which might be used for reloads since the EBB end. | |
5851 | Put the save before INSN if BEFORE_P is true. MAX_UID is maximla | |
5852 | uid before starting INSN processing. Return true if we succeed in | |
5853 | such transformation. */ | |
5854 | static bool | |
3754d046 | 5855 | split_if_necessary (int regno, machine_mode mode, |
c6a6cdaa | 5856 | HARD_REG_SET potential_reload_hard_regs, |
7f836b57 | 5857 | bool before_p, rtx_insn *insn, int max_uid) |
c6a6cdaa | 5858 | { |
5859 | bool res = false; | |
5860 | int i, nregs = 1; | |
5861 | rtx next_usage_insns; | |
5862 | ||
5863 | if (regno < FIRST_PSEUDO_REGISTER) | |
92d2aec3 | 5864 | nregs = hard_regno_nregs (regno, mode); |
c6a6cdaa | 5865 | for (i = 0; i < nregs; i++) |
5866 | if (usage_insns[regno + i].check == curr_usage_insns_check | |
5867 | && (next_usage_insns = usage_insns[regno + i].insns) != NULL_RTX | |
5868 | /* To avoid processing the register twice or more. */ | |
5869 | && ((GET_CODE (next_usage_insns) != INSN_LIST | |
5870 | && INSN_UID (next_usage_insns) < max_uid) | |
5871 | || (GET_CODE (next_usage_insns) == INSN_LIST | |
5872 | && (INSN_UID (XEXP (next_usage_insns, 0)) < max_uid))) | |
5873 | && need_for_split_p (potential_reload_hard_regs, regno + i) | |
6a4bc24e | 5874 | && split_reg (before_p, regno + i, insn, next_usage_insns, NULL)) |
c6a6cdaa | 5875 | res = true; |
5876 | return res; | |
5877 | } | |
5878 | ||
ab4ea053 | 5879 | /* Return TRUE if rtx X is considered as an invariant for |
5880 | inheritance. */ | |
5881 | static bool | |
5882 | invariant_p (const_rtx x) | |
5883 | { | |
5884 | machine_mode mode; | |
5885 | const char *fmt; | |
5886 | enum rtx_code code; | |
5887 | int i, j; | |
5888 | ||
00d7c794 | 5889 | if (side_effects_p (x)) |
5890 | return false; | |
5891 | ||
ab4ea053 | 5892 | code = GET_CODE (x); |
5893 | mode = GET_MODE (x); | |
5894 | if (code == SUBREG) | |
5895 | { | |
5896 | x = SUBREG_REG (x); | |
5897 | code = GET_CODE (x); | |
081c1d32 | 5898 | mode = wider_subreg_mode (mode, GET_MODE (x)); |
ab4ea053 | 5899 | } |
5900 | ||
5901 | if (MEM_P (x)) | |
5902 | return false; | |
5903 | ||
5904 | if (REG_P (x)) | |
5905 | { | |
5906 | int i, nregs, regno = REGNO (x); | |
5907 | ||
5908 | if (regno >= FIRST_PSEUDO_REGISTER || regno == STACK_POINTER_REGNUM | |
5909 | || TEST_HARD_REG_BIT (eliminable_regset, regno) | |
5910 | || GET_MODE_CLASS (GET_MODE (x)) == MODE_CC) | |
5911 | return false; | |
92d2aec3 | 5912 | nregs = hard_regno_nregs (regno, mode); |
ab4ea053 | 5913 | for (i = 0; i < nregs; i++) |
5914 | if (! fixed_regs[regno + i] | |
5915 | /* A hard register may be clobbered in the current insn | |
5916 | but we can ignore this case because if the hard | |
5917 | register is used it should be set somewhere after the | |
5918 | clobber. */ | |
5919 | || bitmap_bit_p (&invalid_invariant_regs, regno + i)) | |
5920 | return false; | |
5921 | } | |
5922 | fmt = GET_RTX_FORMAT (code); | |
5923 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
5924 | { | |
5925 | if (fmt[i] == 'e') | |
5926 | { | |
5927 | if (! invariant_p (XEXP (x, i))) | |
5928 | return false; | |
5929 | } | |
5930 | else if (fmt[i] == 'E') | |
5931 | { | |
5932 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
5933 | if (! invariant_p (XVECEXP (x, i, j))) | |
5934 | return false; | |
5935 | } | |
5936 | } | |
5937 | return true; | |
5938 | } | |
5939 | ||
5940 | /* We have 'dest_reg <- invariant'. Let us try to make an invariant | |
5941 | inheritance transformation (using dest_reg instead invariant in a | |
5942 | subsequent insn). */ | |
5943 | static bool | |
5944 | process_invariant_for_inheritance (rtx dst_reg, rtx invariant_rtx) | |
5945 | { | |
5946 | invariant_ptr_t invariant_ptr; | |
5947 | rtx_insn *insn, *new_insns; | |
5948 | rtx insn_set, insn_reg, new_reg; | |
5949 | int insn_regno; | |
5950 | bool succ_p = false; | |
5951 | int dst_regno = REGNO (dst_reg); | |
582adad1 | 5952 | machine_mode dst_mode = GET_MODE (dst_reg); |
ab4ea053 | 5953 | enum reg_class cl = lra_get_allocno_class (dst_regno), insn_reg_cl; |
5954 | ||
5955 | invariant_ptr = insert_invariant (invariant_rtx); | |
5956 | if ((insn = invariant_ptr->insn) != NULL_RTX) | |
5957 | { | |
5958 | /* We have a subsequent insn using the invariant. */ | |
5959 | insn_set = single_set (insn); | |
5960 | lra_assert (insn_set != NULL); | |
5961 | insn_reg = SET_DEST (insn_set); | |
5962 | lra_assert (REG_P (insn_reg)); | |
5963 | insn_regno = REGNO (insn_reg); | |
5964 | insn_reg_cl = lra_get_allocno_class (insn_regno); | |
5965 | ||
5966 | if (dst_mode == GET_MODE (insn_reg) | |
5967 | /* We should consider only result move reg insns which are | |
5968 | cheap. */ | |
5969 | && targetm.register_move_cost (dst_mode, cl, insn_reg_cl) == 2 | |
5970 | && targetm.register_move_cost (dst_mode, cl, cl) == 2) | |
5971 | { | |
5972 | if (lra_dump_file != NULL) | |
5973 | fprintf (lra_dump_file, | |
5974 | " [[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[\n"); | |
5975 | new_reg = lra_create_new_reg (dst_mode, dst_reg, | |
5976 | cl, "invariant inheritance"); | |
5977 | bitmap_set_bit (&lra_inheritance_pseudos, REGNO (new_reg)); | |
5978 | bitmap_set_bit (&check_only_regs, REGNO (new_reg)); | |
fee93b91 | 5979 | lra_reg_info[REGNO (new_reg)].restore_rtx = PATTERN (insn); |
ab4ea053 | 5980 | start_sequence (); |
5981 | lra_emit_move (new_reg, dst_reg); | |
5982 | new_insns = get_insns (); | |
5983 | end_sequence (); | |
5984 | lra_process_new_insns (curr_insn, NULL, new_insns, | |
5985 | "Add invariant inheritance<-original"); | |
5986 | start_sequence (); | |
5987 | lra_emit_move (SET_DEST (insn_set), new_reg); | |
5988 | new_insns = get_insns (); | |
5989 | end_sequence (); | |
5990 | lra_process_new_insns (insn, NULL, new_insns, | |
5991 | "Changing reload<-inheritance"); | |
5992 | lra_set_insn_deleted (insn); | |
5993 | succ_p = true; | |
5994 | if (lra_dump_file != NULL) | |
5995 | { | |
5996 | fprintf (lra_dump_file, | |
5997 | " Invariant inheritance reuse change %d (bb%d):\n", | |
5998 | REGNO (new_reg), BLOCK_FOR_INSN (insn)->index); | |
5999 | dump_insn_slim (lra_dump_file, insn); | |
6000 | fprintf (lra_dump_file, | |
6001 | " ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]\n"); | |
6002 | } | |
6003 | } | |
6004 | } | |
6005 | invariant_ptr->insn = curr_insn; | |
6006 | return succ_p; | |
6007 | } | |
6008 | ||
c6a6cdaa | 6009 | /* Check only registers living at the current program point in the |
6010 | current EBB. */ | |
6011 | static bitmap_head live_regs; | |
6012 | ||
6013 | /* Update live info in EBB given by its HEAD and TAIL insns after | |
6014 | inheritance/split transformation. The function removes dead moves | |
6015 | too. */ | |
6016 | static void | |
7f836b57 | 6017 | update_ebb_live_info (rtx_insn *head, rtx_insn *tail) |
c6a6cdaa | 6018 | { |
6019 | unsigned int j; | |
7eec3701 | 6020 | int i, regno; |
c6a6cdaa | 6021 | bool live_p; |
7f836b57 | 6022 | rtx_insn *prev_insn; |
6023 | rtx set; | |
c6a6cdaa | 6024 | bool remove_p; |
6025 | basic_block last_bb, prev_bb, curr_bb; | |
6026 | bitmap_iterator bi; | |
6027 | struct lra_insn_reg *reg; | |
6028 | edge e; | |
6029 | edge_iterator ei; | |
6030 | ||
1a8f8886 | 6031 | last_bb = BLOCK_FOR_INSN (tail); |
c6a6cdaa | 6032 | prev_bb = NULL; |
6033 | for (curr_insn = tail; | |
6034 | curr_insn != PREV_INSN (head); | |
6035 | curr_insn = prev_insn) | |
6036 | { | |
6037 | prev_insn = PREV_INSN (curr_insn); | |
76d77f1e | 6038 | /* We need to process empty blocks too. They contain |
6039 | NOTE_INSN_BASIC_BLOCK referring for the basic block. */ | |
6040 | if (NOTE_P (curr_insn) && NOTE_KIND (curr_insn) != NOTE_INSN_BASIC_BLOCK) | |
6041 | continue; | |
c6a6cdaa | 6042 | curr_bb = BLOCK_FOR_INSN (curr_insn); |
6043 | if (curr_bb != prev_bb) | |
6044 | { | |
6045 | if (prev_bb != NULL) | |
6046 | { | |
6047 | /* Update df_get_live_in (prev_bb): */ | |
6048 | EXECUTE_IF_SET_IN_BITMAP (&check_only_regs, 0, j, bi) | |
6049 | if (bitmap_bit_p (&live_regs, j)) | |
6050 | bitmap_set_bit (df_get_live_in (prev_bb), j); | |
6051 | else | |
6052 | bitmap_clear_bit (df_get_live_in (prev_bb), j); | |
6053 | } | |
6054 | if (curr_bb != last_bb) | |
6055 | { | |
6056 | /* Update df_get_live_out (curr_bb): */ | |
6057 | EXECUTE_IF_SET_IN_BITMAP (&check_only_regs, 0, j, bi) | |
6058 | { | |
6059 | live_p = bitmap_bit_p (&live_regs, j); | |
6060 | if (! live_p) | |
6061 | FOR_EACH_EDGE (e, ei, curr_bb->succs) | |
6062 | if (bitmap_bit_p (df_get_live_in (e->dest), j)) | |
6063 | { | |
6064 | live_p = true; | |
6065 | break; | |
6066 | } | |
6067 | if (live_p) | |
6068 | bitmap_set_bit (df_get_live_out (curr_bb), j); | |
6069 | else | |
6070 | bitmap_clear_bit (df_get_live_out (curr_bb), j); | |
6071 | } | |
6072 | } | |
6073 | prev_bb = curr_bb; | |
6074 | bitmap_and (&live_regs, &check_only_regs, df_get_live_out (curr_bb)); | |
6075 | } | |
0f31edc8 | 6076 | if (! NONDEBUG_INSN_P (curr_insn)) |
c6a6cdaa | 6077 | continue; |
6078 | curr_id = lra_get_insn_recog_data (curr_insn); | |
7eec3701 | 6079 | curr_static_id = curr_id->insn_static_data; |
c6a6cdaa | 6080 | remove_p = false; |
5c819ea0 | 6081 | if ((set = single_set (curr_insn)) != NULL_RTX |
6082 | && REG_P (SET_DEST (set)) | |
c6a6cdaa | 6083 | && (regno = REGNO (SET_DEST (set))) >= FIRST_PSEUDO_REGISTER |
5c819ea0 | 6084 | && SET_DEST (set) != pic_offset_table_rtx |
c6a6cdaa | 6085 | && bitmap_bit_p (&check_only_regs, regno) |
6086 | && ! bitmap_bit_p (&live_regs, regno)) | |
6087 | remove_p = true; | |
6088 | /* See which defined values die here. */ | |
6089 | for (reg = curr_id->regs; reg != NULL; reg = reg->next) | |
6090 | if (reg->type == OP_OUT && ! reg->subreg_p) | |
6091 | bitmap_clear_bit (&live_regs, reg->regno); | |
7eec3701 | 6092 | for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next) |
6093 | if (reg->type == OP_OUT && ! reg->subreg_p) | |
6094 | bitmap_clear_bit (&live_regs, reg->regno); | |
853a01d6 | 6095 | if (curr_id->arg_hard_regs != NULL) |
6096 | /* Make clobbered argument hard registers die. */ | |
6097 | for (i = 0; (regno = curr_id->arg_hard_regs[i]) >= 0; i++) | |
6098 | if (regno >= FIRST_PSEUDO_REGISTER) | |
6099 | bitmap_clear_bit (&live_regs, regno - FIRST_PSEUDO_REGISTER); | |
c6a6cdaa | 6100 | /* Mark each used value as live. */ |
6101 | for (reg = curr_id->regs; reg != NULL; reg = reg->next) | |
53d78539 | 6102 | if (reg->type != OP_OUT |
c6a6cdaa | 6103 | && bitmap_bit_p (&check_only_regs, reg->regno)) |
6104 | bitmap_set_bit (&live_regs, reg->regno); | |
7eec3701 | 6105 | for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next) |
6106 | if (reg->type != OP_OUT | |
6107 | && bitmap_bit_p (&check_only_regs, reg->regno)) | |
6108 | bitmap_set_bit (&live_regs, reg->regno); | |
6109 | if (curr_id->arg_hard_regs != NULL) | |
853a01d6 | 6110 | /* Make used argument hard registers live. */ |
7eec3701 | 6111 | for (i = 0; (regno = curr_id->arg_hard_regs[i]) >= 0; i++) |
853a01d6 | 6112 | if (regno < FIRST_PSEUDO_REGISTER |
6113 | && bitmap_bit_p (&check_only_regs, regno)) | |
7eec3701 | 6114 | bitmap_set_bit (&live_regs, regno); |
c6a6cdaa | 6115 | /* It is quite important to remove dead move insns because it |
6116 | means removing dead store. We don't need to process them for | |
6117 | constraints. */ | |
6118 | if (remove_p) | |
6119 | { | |
6120 | if (lra_dump_file != NULL) | |
6121 | { | |
6122 | fprintf (lra_dump_file, " Removing dead insn:\n "); | |
6dde9719 | 6123 | dump_insn_slim (lra_dump_file, curr_insn); |
c6a6cdaa | 6124 | } |
6125 | lra_set_insn_deleted (curr_insn); | |
6126 | } | |
6127 | } | |
6128 | } | |
6129 | ||
6130 | /* The structure describes info to do an inheritance for the current | |
6131 | insn. We need to collect such info first before doing the | |
6132 | transformations because the transformations change the insn | |
6133 | internal representation. */ | |
6134 | struct to_inherit | |
6135 | { | |
6136 | /* Original regno. */ | |
6137 | int regno; | |
6138 | /* Subsequent insns which can inherit original reg value. */ | |
6139 | rtx insns; | |
6140 | }; | |
6141 | ||
6142 | /* Array containing all info for doing inheritance from the current | |
6143 | insn. */ | |
6144 | static struct to_inherit to_inherit[LRA_MAX_INSN_RELOADS]; | |
6145 | ||
6146 | /* Number elements in the previous array. */ | |
6147 | static int to_inherit_num; | |
6148 | ||
6149 | /* Add inheritance info REGNO and INSNS. Their meaning is described in | |
6150 | structure to_inherit. */ | |
6151 | static void | |
6152 | add_to_inherit (int regno, rtx insns) | |
6153 | { | |
6154 | int i; | |
6155 | ||
6156 | for (i = 0; i < to_inherit_num; i++) | |
6157 | if (to_inherit[i].regno == regno) | |
6158 | return; | |
6159 | lra_assert (to_inherit_num < LRA_MAX_INSN_RELOADS); | |
6160 | to_inherit[to_inherit_num].regno = regno; | |
6161 | to_inherit[to_inherit_num++].insns = insns; | |
6162 | } | |
6163 | ||
6164 | /* Return the last non-debug insn in basic block BB, or the block begin | |
6165 | note if none. */ | |
7f836b57 | 6166 | static rtx_insn * |
c6a6cdaa | 6167 | get_last_insertion_point (basic_block bb) |
6168 | { | |
7f836b57 | 6169 | rtx_insn *insn; |
c6a6cdaa | 6170 | |
6171 | FOR_BB_INSNS_REVERSE (bb, insn) | |
6172 | if (NONDEBUG_INSN_P (insn) || NOTE_INSN_BASIC_BLOCK_P (insn)) | |
6173 | return insn; | |
6174 | gcc_unreachable (); | |
6175 | } | |
6176 | ||
6177 | /* Set up RES by registers living on edges FROM except the edge (FROM, | |
6178 | TO) or by registers set up in a jump insn in BB FROM. */ | |
6179 | static void | |
6180 | get_live_on_other_edges (basic_block from, basic_block to, bitmap res) | |
6181 | { | |
7f836b57 | 6182 | rtx_insn *last; |
c6a6cdaa | 6183 | struct lra_insn_reg *reg; |
6184 | edge e; | |
6185 | edge_iterator ei; | |
6186 | ||
6187 | lra_assert (to != NULL); | |
6188 | bitmap_clear (res); | |
6189 | FOR_EACH_EDGE (e, ei, from->succs) | |
6190 | if (e->dest != to) | |
6191 | bitmap_ior_into (res, df_get_live_in (e->dest)); | |
6192 | last = get_last_insertion_point (from); | |
6193 | if (! JUMP_P (last)) | |
6194 | return; | |
6195 | curr_id = lra_get_insn_recog_data (last); | |
6196 | for (reg = curr_id->regs; reg != NULL; reg = reg->next) | |
6197 | if (reg->type != OP_IN) | |
6198 | bitmap_set_bit (res, reg->regno); | |
6199 | } | |
1a8f8886 | 6200 | |
c6a6cdaa | 6201 | /* Used as a temporary results of some bitmap calculations. */ |
6202 | static bitmap_head temp_bitmap; | |
6203 | ||
7eec3701 | 6204 | /* We split for reloads of small class of hard regs. The following |
6205 | defines how many hard regs the class should have to be qualified as | |
6206 | small. The code is mostly oriented to x86/x86-64 architecture | |
6207 | where some insns need to use only specific register or pair of | |
6208 | registers and these register can live in RTL explicitly, e.g. for | |
6209 | parameter passing. */ | |
6210 | static const int max_small_class_regs_num = 2; | |
6211 | ||
c6a6cdaa | 6212 | /* Do inheritance/split transformations in EBB starting with HEAD and |
6213 | finishing on TAIL. We process EBB insns in the reverse order. | |
6214 | Return true if we did any inheritance/split transformation in the | |
6215 | EBB. | |
6216 | ||
6217 | We should avoid excessive splitting which results in worse code | |
6218 | because of inaccurate cost calculations for spilling new split | |
6219 | pseudos in such case. To achieve this we do splitting only if | |
6220 | register pressure is high in given basic block and there are reload | |
6221 | pseudos requiring hard registers. We could do more register | |
6222 | pressure calculations at any given program point to avoid necessary | |
6223 | splitting even more but it is to expensive and the current approach | |
6224 | works well enough. */ | |
6225 | static bool | |
7f836b57 | 6226 | inherit_in_ebb (rtx_insn *head, rtx_insn *tail) |
c6a6cdaa | 6227 | { |
6228 | int i, src_regno, dst_regno, nregs; | |
422470c1 | 6229 | bool change_p, succ_p, update_reloads_num_p; |
7f836b57 | 6230 | rtx_insn *prev_insn, *last_insn; |
ab4ea053 | 6231 | rtx next_usage_insns, curr_set; |
c6a6cdaa | 6232 | enum reg_class cl; |
6233 | struct lra_insn_reg *reg; | |
6234 | basic_block last_processed_bb, curr_bb = NULL; | |
6235 | HARD_REG_SET potential_reload_hard_regs, live_hard_regs; | |
6236 | bitmap to_process; | |
6237 | unsigned int j; | |
6238 | bitmap_iterator bi; | |
6239 | bool head_p, after_p; | |
6240 | ||
6241 | change_p = false; | |
6242 | curr_usage_insns_check++; | |
ab4ea053 | 6243 | clear_invariants (); |
c6a6cdaa | 6244 | reloads_num = calls_num = 0; |
6245 | bitmap_clear (&check_only_regs); | |
ab4ea053 | 6246 | bitmap_clear (&invalid_invariant_regs); |
c6a6cdaa | 6247 | last_processed_bb = NULL; |
6248 | CLEAR_HARD_REG_SET (potential_reload_hard_regs); | |
7eec3701 | 6249 | COPY_HARD_REG_SET (live_hard_regs, eliminable_regset); |
6250 | IOR_HARD_REG_SET (live_hard_regs, lra_no_alloc_regs); | |
c6a6cdaa | 6251 | /* We don't process new insns generated in the loop. */ |
6252 | for (curr_insn = tail; curr_insn != PREV_INSN (head); curr_insn = prev_insn) | |
6253 | { | |
6254 | prev_insn = PREV_INSN (curr_insn); | |
6255 | if (BLOCK_FOR_INSN (curr_insn) != NULL) | |
6256 | curr_bb = BLOCK_FOR_INSN (curr_insn); | |
6257 | if (last_processed_bb != curr_bb) | |
6258 | { | |
6259 | /* We are at the end of BB. Add qualified living | |
6260 | pseudos for potential splitting. */ | |
6261 | to_process = df_get_live_out (curr_bb); | |
6262 | if (last_processed_bb != NULL) | |
1a8f8886 | 6263 | { |
c6a6cdaa | 6264 | /* We are somewhere in the middle of EBB. */ |
6265 | get_live_on_other_edges (curr_bb, last_processed_bb, | |
6266 | &temp_bitmap); | |
6267 | to_process = &temp_bitmap; | |
6268 | } | |
6269 | last_processed_bb = curr_bb; | |
6270 | last_insn = get_last_insertion_point (curr_bb); | |
6271 | after_p = (! JUMP_P (last_insn) | |
6272 | && (! CALL_P (last_insn) | |
6273 | || (find_reg_note (last_insn, | |
6274 | REG_NORETURN, NULL_RTX) == NULL_RTX | |
6275 | && ! SIBLING_CALL_P (last_insn)))); | |
c6a6cdaa | 6276 | CLEAR_HARD_REG_SET (potential_reload_hard_regs); |
6277 | EXECUTE_IF_SET_IN_BITMAP (to_process, 0, j, bi) | |
6278 | { | |
6279 | if ((int) j >= lra_constraint_new_regno_start) | |
6280 | break; | |
6281 | if (j < FIRST_PSEUDO_REGISTER || reg_renumber[j] >= 0) | |
6282 | { | |
6283 | if (j < FIRST_PSEUDO_REGISTER) | |
6284 | SET_HARD_REG_BIT (live_hard_regs, j); | |
6285 | else | |
6286 | add_to_hard_reg_set (&live_hard_regs, | |
6287 | PSEUDO_REGNO_MODE (j), | |
6288 | reg_renumber[j]); | |
6289 | setup_next_usage_insn (j, last_insn, reloads_num, after_p); | |
6290 | } | |
6291 | } | |
6292 | } | |
6293 | src_regno = dst_regno = -1; | |
ab4ea053 | 6294 | curr_set = single_set (curr_insn); |
6295 | if (curr_set != NULL_RTX && REG_P (SET_DEST (curr_set))) | |
6296 | dst_regno = REGNO (SET_DEST (curr_set)); | |
6297 | if (curr_set != NULL_RTX && REG_P (SET_SRC (curr_set))) | |
6298 | src_regno = REGNO (SET_SRC (curr_set)); | |
422470c1 | 6299 | update_reloads_num_p = true; |
c6a6cdaa | 6300 | if (src_regno < lra_constraint_new_regno_start |
6301 | && src_regno >= FIRST_PSEUDO_REGISTER | |
6302 | && reg_renumber[src_regno] < 0 | |
6303 | && dst_regno >= lra_constraint_new_regno_start | |
6304 | && (cl = lra_get_allocno_class (dst_regno)) != NO_REGS) | |
6305 | { | |
6306 | /* 'reload_pseudo <- original_pseudo'. */ | |
7eec3701 | 6307 | if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num) |
6308 | reloads_num++; | |
422470c1 | 6309 | update_reloads_num_p = false; |
c6a6cdaa | 6310 | succ_p = false; |
6311 | if (usage_insns[src_regno].check == curr_usage_insns_check | |
6312 | && (next_usage_insns = usage_insns[src_regno].insns) != NULL_RTX) | |
6313 | succ_p = inherit_reload_reg (false, src_regno, cl, | |
6314 | curr_insn, next_usage_insns); | |
6315 | if (succ_p) | |
6316 | change_p = true; | |
6317 | else | |
6318 | setup_next_usage_insn (src_regno, curr_insn, reloads_num, false); | |
6319 | if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs)) | |
6320 | IOR_HARD_REG_SET (potential_reload_hard_regs, | |
6321 | reg_class_contents[cl]); | |
6322 | } | |
ab4ea053 | 6323 | else if (src_regno < 0 |
6324 | && dst_regno >= lra_constraint_new_regno_start | |
6325 | && invariant_p (SET_SRC (curr_set)) | |
6326 | && (cl = lra_get_allocno_class (dst_regno)) != NO_REGS | |
6526e1b6 | 6327 | && ! bitmap_bit_p (&invalid_invariant_regs, dst_regno) |
6328 | && ! bitmap_bit_p (&invalid_invariant_regs, | |
6329 | ORIGINAL_REGNO(regno_reg_rtx[dst_regno]))) | |
ab4ea053 | 6330 | { |
6331 | /* 'reload_pseudo <- invariant'. */ | |
6332 | if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num) | |
6333 | reloads_num++; | |
6334 | update_reloads_num_p = false; | |
6335 | if (process_invariant_for_inheritance (SET_DEST (curr_set), SET_SRC (curr_set))) | |
6336 | change_p = true; | |
6337 | if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs)) | |
6338 | IOR_HARD_REG_SET (potential_reload_hard_regs, | |
6339 | reg_class_contents[cl]); | |
6340 | } | |
c6a6cdaa | 6341 | else if (src_regno >= lra_constraint_new_regno_start |
6342 | && dst_regno < lra_constraint_new_regno_start | |
6343 | && dst_regno >= FIRST_PSEUDO_REGISTER | |
6344 | && reg_renumber[dst_regno] < 0 | |
6345 | && (cl = lra_get_allocno_class (src_regno)) != NO_REGS | |
6346 | && usage_insns[dst_regno].check == curr_usage_insns_check | |
6347 | && (next_usage_insns | |
6348 | = usage_insns[dst_regno].insns) != NULL_RTX) | |
6349 | { | |
7eec3701 | 6350 | if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num) |
6351 | reloads_num++; | |
422470c1 | 6352 | update_reloads_num_p = false; |
c6a6cdaa | 6353 | /* 'original_pseudo <- reload_pseudo'. */ |
6354 | if (! JUMP_P (curr_insn) | |
6355 | && inherit_reload_reg (true, dst_regno, cl, | |
6356 | curr_insn, next_usage_insns)) | |
6357 | change_p = true; | |
6358 | /* Invalidate. */ | |
6359 | usage_insns[dst_regno].check = 0; | |
6360 | if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs)) | |
6361 | IOR_HARD_REG_SET (potential_reload_hard_regs, | |
6362 | reg_class_contents[cl]); | |
6363 | } | |
6364 | else if (INSN_P (curr_insn)) | |
6365 | { | |
bf63c98f | 6366 | int iter; |
c6a6cdaa | 6367 | int max_uid = get_max_uid (); |
6368 | ||
6369 | curr_id = lra_get_insn_recog_data (curr_insn); | |
bf63c98f | 6370 | curr_static_id = curr_id->insn_static_data; |
c6a6cdaa | 6371 | to_inherit_num = 0; |
6372 | /* Process insn definitions. */ | |
bf63c98f | 6373 | for (iter = 0; iter < 2; iter++) |
6374 | for (reg = iter == 0 ? curr_id->regs : curr_static_id->hard_regs; | |
6375 | reg != NULL; | |
6376 | reg = reg->next) | |
6377 | if (reg->type != OP_IN | |
6378 | && (dst_regno = reg->regno) < lra_constraint_new_regno_start) | |
6379 | { | |
6380 | if (dst_regno >= FIRST_PSEUDO_REGISTER && reg->type == OP_OUT | |
6381 | && reg_renumber[dst_regno] < 0 && ! reg->subreg_p | |
6382 | && usage_insns[dst_regno].check == curr_usage_insns_check | |
6383 | && (next_usage_insns | |
6384 | = usage_insns[dst_regno].insns) != NULL_RTX) | |
6385 | { | |
6386 | struct lra_insn_reg *r; | |
6387 | ||
6388 | for (r = curr_id->regs; r != NULL; r = r->next) | |
6389 | if (r->type != OP_OUT && r->regno == dst_regno) | |
6390 | break; | |
6391 | /* Don't do inheritance if the pseudo is also | |
6392 | used in the insn. */ | |
6393 | if (r == NULL) | |
f4d3c071 | 6394 | /* We cannot do inheritance right now |
bf63c98f | 6395 | because the current insn reg info (chain |
6396 | regs) can change after that. */ | |
6397 | add_to_inherit (dst_regno, next_usage_insns); | |
6398 | } | |
f4d3c071 | 6399 | /* We cannot process one reg twice here because of |
bf63c98f | 6400 | usage_insns invalidation. */ |
6401 | if ((dst_regno < FIRST_PSEUDO_REGISTER | |
6402 | || reg_renumber[dst_regno] >= 0) | |
0157439c | 6403 | && ! reg->subreg_p && reg->type != OP_IN) |
bf63c98f | 6404 | { |
6405 | HARD_REG_SET s; | |
6406 | ||
6407 | if (split_if_necessary (dst_regno, reg->biggest_mode, | |
6408 | potential_reload_hard_regs, | |
6409 | false, curr_insn, max_uid)) | |
6410 | change_p = true; | |
6411 | CLEAR_HARD_REG_SET (s); | |
6412 | if (dst_regno < FIRST_PSEUDO_REGISTER) | |
6413 | add_to_hard_reg_set (&s, reg->biggest_mode, dst_regno); | |
6414 | else | |
6415 | add_to_hard_reg_set (&s, PSEUDO_REGNO_MODE (dst_regno), | |
6416 | reg_renumber[dst_regno]); | |
6417 | AND_COMPL_HARD_REG_SET (live_hard_regs, s); | |
68d3038f | 6418 | AND_COMPL_HARD_REG_SET (potential_reload_hard_regs, s); |
bf63c98f | 6419 | } |
6420 | /* We should invalidate potential inheritance or | |
6421 | splitting for the current insn usages to the next | |
6422 | usage insns (see code below) as the output pseudo | |
6423 | prevents this. */ | |
6424 | if ((dst_regno >= FIRST_PSEUDO_REGISTER | |
6425 | && reg_renumber[dst_regno] < 0) | |
6426 | || (reg->type == OP_OUT && ! reg->subreg_p | |
6427 | && (dst_regno < FIRST_PSEUDO_REGISTER | |
6428 | || reg_renumber[dst_regno] >= 0))) | |
6429 | { | |
6430 | /* Invalidate and mark definitions. */ | |
6431 | if (dst_regno >= FIRST_PSEUDO_REGISTER) | |
6432 | usage_insns[dst_regno].check = -(int) INSN_UID (curr_insn); | |
6433 | else | |
6434 | { | |
92d2aec3 | 6435 | nregs = hard_regno_nregs (dst_regno, |
6436 | reg->biggest_mode); | |
bf63c98f | 6437 | for (i = 0; i < nregs; i++) |
6438 | usage_insns[dst_regno + i].check | |
6439 | = -(int) INSN_UID (curr_insn); | |
6440 | } | |
6441 | } | |
6442 | } | |
853a01d6 | 6443 | /* Process clobbered call regs. */ |
6444 | if (curr_id->arg_hard_regs != NULL) | |
6445 | for (i = 0; (dst_regno = curr_id->arg_hard_regs[i]) >= 0; i++) | |
6446 | if (dst_regno >= FIRST_PSEUDO_REGISTER) | |
6447 | usage_insns[dst_regno - FIRST_PSEUDO_REGISTER].check | |
6448 | = -(int) INSN_UID (curr_insn); | |
c6a6cdaa | 6449 | if (! JUMP_P (curr_insn)) |
6450 | for (i = 0; i < to_inherit_num; i++) | |
6451 | if (inherit_reload_reg (true, to_inherit[i].regno, | |
6452 | ALL_REGS, curr_insn, | |
6453 | to_inherit[i].insns)) | |
6454 | change_p = true; | |
6455 | if (CALL_P (curr_insn)) | |
6456 | { | |
7f836b57 | 6457 | rtx cheap, pat, dest; |
6458 | rtx_insn *restore; | |
c6a6cdaa | 6459 | int regno, hard_regno; |
6460 | ||
6461 | calls_num++; | |
6462 | if ((cheap = find_reg_note (curr_insn, | |
6463 | REG_RETURNED, NULL_RTX)) != NULL_RTX | |
6464 | && ((cheap = XEXP (cheap, 0)), true) | |
6465 | && (regno = REGNO (cheap)) >= FIRST_PSEUDO_REGISTER | |
6466 | && (hard_regno = reg_renumber[regno]) >= 0 | |
2fa8212b | 6467 | && usage_insns[regno].check == curr_usage_insns_check |
c6a6cdaa | 6468 | /* If there are pending saves/restores, the |
6469 | optimization is not worth. */ | |
6470 | && usage_insns[regno].calls_num == calls_num - 1 | |
6471 | && TEST_HARD_REG_BIT (call_used_reg_set, hard_regno)) | |
6472 | { | |
6473 | /* Restore the pseudo from the call result as | |
6474 | REG_RETURNED note says that the pseudo value is | |
6475 | in the call result and the pseudo is an argument | |
6476 | of the call. */ | |
6477 | pat = PATTERN (curr_insn); | |
6478 | if (GET_CODE (pat) == PARALLEL) | |
6479 | pat = XVECEXP (pat, 0, 0); | |
6480 | dest = SET_DEST (pat); | |
e88cf7af | 6481 | /* For multiple return values dest is PARALLEL. |
6482 | Currently we handle only single return value case. */ | |
6483 | if (REG_P (dest)) | |
6484 | { | |
6485 | start_sequence (); | |
6486 | emit_move_insn (cheap, copy_rtx (dest)); | |
6487 | restore = get_insns (); | |
6488 | end_sequence (); | |
6489 | lra_process_new_insns (curr_insn, NULL, restore, | |
6490 | "Inserting call parameter restore"); | |
6491 | /* We don't need to save/restore of the pseudo from | |
6492 | this call. */ | |
6493 | usage_insns[regno].calls_num = calls_num; | |
6494 | bitmap_set_bit (&check_only_regs, regno); | |
6495 | } | |
c6a6cdaa | 6496 | } |
6497 | } | |
6498 | to_inherit_num = 0; | |
6499 | /* Process insn usages. */ | |
bf63c98f | 6500 | for (iter = 0; iter < 2; iter++) |
6501 | for (reg = iter == 0 ? curr_id->regs : curr_static_id->hard_regs; | |
6502 | reg != NULL; | |
6503 | reg = reg->next) | |
6504 | if ((reg->type != OP_OUT | |
6505 | || (reg->type == OP_OUT && reg->subreg_p)) | |
6506 | && (src_regno = reg->regno) < lra_constraint_new_regno_start) | |
6507 | { | |
6508 | if (src_regno >= FIRST_PSEUDO_REGISTER | |
6509 | && reg_renumber[src_regno] < 0 && reg->type == OP_IN) | |
6510 | { | |
6511 | if (usage_insns[src_regno].check == curr_usage_insns_check | |
6512 | && (next_usage_insns | |
6513 | = usage_insns[src_regno].insns) != NULL_RTX | |
6514 | && NONDEBUG_INSN_P (curr_insn)) | |
6515 | add_to_inherit (src_regno, next_usage_insns); | |
6516 | else if (usage_insns[src_regno].check | |
6517 | != -(int) INSN_UID (curr_insn)) | |
6518 | /* Add usages but only if the reg is not set up | |
6519 | in the same insn. */ | |
6520 | add_next_usage_insn (src_regno, curr_insn, reloads_num); | |
6521 | } | |
6522 | else if (src_regno < FIRST_PSEUDO_REGISTER | |
6523 | || reg_renumber[src_regno] >= 0) | |
6524 | { | |
6525 | bool before_p; | |
9ed997be | 6526 | rtx_insn *use_insn = curr_insn; |
bf63c98f | 6527 | |
6528 | before_p = (JUMP_P (curr_insn) | |
6529 | || (CALL_P (curr_insn) && reg->type == OP_IN)); | |
6530 | if (NONDEBUG_INSN_P (curr_insn) | |
7eec3701 | 6531 | && (! JUMP_P (curr_insn) || reg->type == OP_IN) |
bf63c98f | 6532 | && split_if_necessary (src_regno, reg->biggest_mode, |
6533 | potential_reload_hard_regs, | |
6534 | before_p, curr_insn, max_uid)) | |
6535 | { | |
6536 | if (reg->subreg_p) | |
6537 | lra_risky_transformations_p = true; | |
6538 | change_p = true; | |
7eec3701 | 6539 | /* Invalidate. */ |
bf63c98f | 6540 | usage_insns[src_regno].check = 0; |
6541 | if (before_p) | |
6542 | use_insn = PREV_INSN (curr_insn); | |
6543 | } | |
6544 | if (NONDEBUG_INSN_P (curr_insn)) | |
6545 | { | |
6546 | if (src_regno < FIRST_PSEUDO_REGISTER) | |
6547 | add_to_hard_reg_set (&live_hard_regs, | |
6548 | reg->biggest_mode, src_regno); | |
6549 | else | |
6550 | add_to_hard_reg_set (&live_hard_regs, | |
6551 | PSEUDO_REGNO_MODE (src_regno), | |
6552 | reg_renumber[src_regno]); | |
6553 | } | |
fbaab486 | 6554 | if (src_regno >= FIRST_PSEUDO_REGISTER) |
6555 | add_next_usage_insn (src_regno, use_insn, reloads_num); | |
6556 | else | |
6557 | { | |
6558 | for (i = 0; i < hard_regno_nregs (src_regno, reg->biggest_mode); i++) | |
6559 | add_next_usage_insn (src_regno + i, use_insn, reloads_num); | |
6560 | } | |
bf63c98f | 6561 | } |
6562 | } | |
853a01d6 | 6563 | /* Process used call regs. */ |
422470c1 | 6564 | if (curr_id->arg_hard_regs != NULL) |
6565 | for (i = 0; (src_regno = curr_id->arg_hard_regs[i]) >= 0; i++) | |
6566 | if (src_regno < FIRST_PSEUDO_REGISTER) | |
6567 | { | |
6568 | SET_HARD_REG_BIT (live_hard_regs, src_regno); | |
6569 | add_next_usage_insn (src_regno, curr_insn, reloads_num); | |
6570 | } | |
c6a6cdaa | 6571 | for (i = 0; i < to_inherit_num; i++) |
6572 | { | |
6573 | src_regno = to_inherit[i].regno; | |
6574 | if (inherit_reload_reg (false, src_regno, ALL_REGS, | |
6575 | curr_insn, to_inherit[i].insns)) | |
6576 | change_p = true; | |
6577 | else | |
6578 | setup_next_usage_insn (src_regno, curr_insn, reloads_num, false); | |
6579 | } | |
6580 | } | |
422470c1 | 6581 | if (update_reloads_num_p |
ab4ea053 | 6582 | && NONDEBUG_INSN_P (curr_insn) && curr_set != NULL_RTX) |
422470c1 | 6583 | { |
6584 | int regno = -1; | |
ab4ea053 | 6585 | if ((REG_P (SET_DEST (curr_set)) |
6586 | && (regno = REGNO (SET_DEST (curr_set))) >= lra_constraint_new_regno_start | |
422470c1 | 6587 | && reg_renumber[regno] < 0 |
6588 | && (cl = lra_get_allocno_class (regno)) != NO_REGS) | |
ab4ea053 | 6589 | || (REG_P (SET_SRC (curr_set)) |
6590 | && (regno = REGNO (SET_SRC (curr_set))) >= lra_constraint_new_regno_start | |
422470c1 | 6591 | && reg_renumber[regno] < 0 |
6592 | && (cl = lra_get_allocno_class (regno)) != NO_REGS)) | |
6593 | { | |
7eec3701 | 6594 | if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num) |
6595 | reloads_num++; | |
422470c1 | 6596 | if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs)) |
6597 | IOR_HARD_REG_SET (potential_reload_hard_regs, | |
6598 | reg_class_contents[cl]); | |
6599 | } | |
6600 | } | |
ab4ea053 | 6601 | if (NONDEBUG_INSN_P (curr_insn)) |
6602 | { | |
6603 | int regno; | |
6604 | ||
6605 | /* Invalidate invariants with changed regs. */ | |
6606 | curr_id = lra_get_insn_recog_data (curr_insn); | |
6607 | for (reg = curr_id->regs; reg != NULL; reg = reg->next) | |
6608 | if (reg->type != OP_IN) | |
6526e1b6 | 6609 | { |
6610 | bitmap_set_bit (&invalid_invariant_regs, reg->regno); | |
6611 | bitmap_set_bit (&invalid_invariant_regs, | |
6612 | ORIGINAL_REGNO (regno_reg_rtx[reg->regno])); | |
6613 | } | |
ab4ea053 | 6614 | curr_static_id = curr_id->insn_static_data; |
6615 | for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next) | |
6616 | if (reg->type != OP_IN) | |
6617 | bitmap_set_bit (&invalid_invariant_regs, reg->regno); | |
6618 | if (curr_id->arg_hard_regs != NULL) | |
6619 | for (i = 0; (regno = curr_id->arg_hard_regs[i]) >= 0; i++) | |
6526e1b6 | 6620 | if (regno >= FIRST_PSEUDO_REGISTER) |
ab4ea053 | 6621 | bitmap_set_bit (&invalid_invariant_regs, |
6526e1b6 | 6622 | regno - FIRST_PSEUDO_REGISTER); |
ab4ea053 | 6623 | } |
c6a6cdaa | 6624 | /* We reached the start of the current basic block. */ |
6625 | if (prev_insn == NULL_RTX || prev_insn == PREV_INSN (head) | |
6626 | || BLOCK_FOR_INSN (prev_insn) != curr_bb) | |
6627 | { | |
6628 | /* We reached the beginning of the current block -- do | |
6629 | rest of spliting in the current BB. */ | |
6630 | to_process = df_get_live_in (curr_bb); | |
6631 | if (BLOCK_FOR_INSN (head) != curr_bb) | |
1a8f8886 | 6632 | { |
c6a6cdaa | 6633 | /* We are somewhere in the middle of EBB. */ |
6634 | get_live_on_other_edges (EDGE_PRED (curr_bb, 0)->src, | |
6635 | curr_bb, &temp_bitmap); | |
6636 | to_process = &temp_bitmap; | |
6637 | } | |
6638 | head_p = true; | |
6639 | EXECUTE_IF_SET_IN_BITMAP (to_process, 0, j, bi) | |
6640 | { | |
6641 | if ((int) j >= lra_constraint_new_regno_start) | |
6642 | break; | |
6643 | if (((int) j < FIRST_PSEUDO_REGISTER || reg_renumber[j] >= 0) | |
6644 | && usage_insns[j].check == curr_usage_insns_check | |
6645 | && (next_usage_insns = usage_insns[j].insns) != NULL_RTX) | |
6646 | { | |
6647 | if (need_for_split_p (potential_reload_hard_regs, j)) | |
6648 | { | |
6649 | if (lra_dump_file != NULL && head_p) | |
6650 | { | |
6651 | fprintf (lra_dump_file, | |
6652 | " ----------------------------------\n"); | |
6653 | head_p = false; | |
6654 | } | |
6655 | if (split_reg (false, j, bb_note (curr_bb), | |
6a4bc24e | 6656 | next_usage_insns, NULL)) |
c6a6cdaa | 6657 | change_p = true; |
6658 | } | |
6659 | usage_insns[j].check = 0; | |
6660 | } | |
6661 | } | |
6662 | } | |
6663 | } | |
6664 | return change_p; | |
6665 | } | |
6666 | ||
6667 | /* This value affects EBB forming. If probability of edge from EBB to | |
6668 | a BB is not greater than the following value, we don't add the BB | |
1a8f8886 | 6669 | to EBB. */ |
4b69081d | 6670 | #define EBB_PROBABILITY_CUTOFF \ |
6671 | ((REG_BR_PROB_BASE * LRA_INHERITANCE_EBB_PROBABILITY_CUTOFF) / 100) | |
c6a6cdaa | 6672 | |
6673 | /* Current number of inheritance/split iteration. */ | |
6674 | int lra_inheritance_iter; | |
6675 | ||
6676 | /* Entry function for inheritance/split pass. */ | |
6677 | void | |
6678 | lra_inheritance (void) | |
6679 | { | |
6680 | int i; | |
6681 | basic_block bb, start_bb; | |
6682 | edge e; | |
6683 | ||
c6a6cdaa | 6684 | lra_inheritance_iter++; |
47f6add2 | 6685 | if (lra_inheritance_iter > LRA_MAX_INHERITANCE_PASSES) |
7b184c47 | 6686 | return; |
6687 | timevar_push (TV_LRA_INHERITANCE); | |
c6a6cdaa | 6688 | if (lra_dump_file != NULL) |
6689 | fprintf (lra_dump_file, "\n********** Inheritance #%d: **********\n\n", | |
6690 | lra_inheritance_iter); | |
6691 | curr_usage_insns_check = 0; | |
6692 | usage_insns = XNEWVEC (struct usage_insns, lra_constraint_new_regno_start); | |
6693 | for (i = 0; i < lra_constraint_new_regno_start; i++) | |
6694 | usage_insns[i].check = 0; | |
6695 | bitmap_initialize (&check_only_regs, ®_obstack); | |
ab4ea053 | 6696 | bitmap_initialize (&invalid_invariant_regs, ®_obstack); |
c6a6cdaa | 6697 | bitmap_initialize (&live_regs, ®_obstack); |
6698 | bitmap_initialize (&temp_bitmap, ®_obstack); | |
6699 | bitmap_initialize (&ebb_global_regs, ®_obstack); | |
fc00614f | 6700 | FOR_EACH_BB_FN (bb, cfun) |
c6a6cdaa | 6701 | { |
6702 | start_bb = bb; | |
6703 | if (lra_dump_file != NULL) | |
6704 | fprintf (lra_dump_file, "EBB"); | |
6705 | /* Form a EBB starting with BB. */ | |
6706 | bitmap_clear (&ebb_global_regs); | |
6707 | bitmap_ior_into (&ebb_global_regs, df_get_live_in (bb)); | |
6708 | for (;;) | |
6709 | { | |
6710 | if (lra_dump_file != NULL) | |
6711 | fprintf (lra_dump_file, " %d", bb->index); | |
34154e27 | 6712 | if (bb->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun) |
6713 | || LABEL_P (BB_HEAD (bb->next_bb))) | |
c6a6cdaa | 6714 | break; |
6715 | e = find_fallthru_edge (bb->succs); | |
6716 | if (! e) | |
6717 | break; | |
720cfc43 | 6718 | if (e->probability.initialized_p () |
6719 | && e->probability.to_reg_br_prob_base () < EBB_PROBABILITY_CUTOFF) | |
c6a6cdaa | 6720 | break; |
6721 | bb = bb->next_bb; | |
6722 | } | |
6723 | bitmap_ior_into (&ebb_global_regs, df_get_live_out (bb)); | |
6724 | if (lra_dump_file != NULL) | |
6725 | fprintf (lra_dump_file, "\n"); | |
6726 | if (inherit_in_ebb (BB_HEAD (start_bb), BB_END (bb))) | |
6727 | /* Remember that the EBB head and tail can change in | |
6728 | inherit_in_ebb. */ | |
6729 | update_ebb_live_info (BB_HEAD (start_bb), BB_END (bb)); | |
6730 | } | |
7da7f1c6 | 6731 | bitmap_release (&ebb_global_regs); |
6732 | bitmap_release (&temp_bitmap); | |
6733 | bitmap_release (&live_regs); | |
6734 | bitmap_release (&invalid_invariant_regs); | |
6735 | bitmap_release (&check_only_regs); | |
c6a6cdaa | 6736 | free (usage_insns); |
6737 | ||
6738 | timevar_pop (TV_LRA_INHERITANCE); | |
6739 | } | |
6740 | ||
6741 | \f | |
6742 | ||
6743 | /* This page contains code to undo failed inheritance/split | |
6744 | transformations. */ | |
6745 | ||
6746 | /* Current number of iteration undoing inheritance/split. */ | |
6747 | int lra_undo_inheritance_iter; | |
6748 | ||
6749 | /* Fix BB live info LIVE after removing pseudos created on pass doing | |
6750 | inheritance/split which are REMOVED_PSEUDOS. */ | |
6751 | static void | |
6752 | fix_bb_live_info (bitmap live, bitmap removed_pseudos) | |
6753 | { | |
6754 | unsigned int regno; | |
6755 | bitmap_iterator bi; | |
6756 | ||
6757 | EXECUTE_IF_SET_IN_BITMAP (removed_pseudos, 0, regno, bi) | |
ab4ea053 | 6758 | if (bitmap_clear_bit (live, regno) |
6759 | && REG_P (lra_reg_info[regno].restore_rtx)) | |
6760 | bitmap_set_bit (live, REGNO (lra_reg_info[regno].restore_rtx)); | |
c6a6cdaa | 6761 | } |
6762 | ||
6763 | /* Return regno of the (subreg of) REG. Otherwise, return a negative | |
6764 | number. */ | |
6765 | static int | |
6766 | get_regno (rtx reg) | |
6767 | { | |
6768 | if (GET_CODE (reg) == SUBREG) | |
6769 | reg = SUBREG_REG (reg); | |
6770 | if (REG_P (reg)) | |
6771 | return REGNO (reg); | |
6772 | return -1; | |
6773 | } | |
6774 | ||
02ffd664 | 6775 | /* Delete a move INSN with destination reg DREGNO and a previous |
6776 | clobber insn with the same regno. The inheritance/split code can | |
6777 | generate moves with preceding clobber and when we delete such moves | |
6778 | we should delete the clobber insn too to keep the correct life | |
6779 | info. */ | |
6780 | static void | |
6781 | delete_move_and_clobber (rtx_insn *insn, int dregno) | |
6782 | { | |
6783 | rtx_insn *prev_insn = PREV_INSN (insn); | |
6784 | ||
6785 | lra_set_insn_deleted (insn); | |
2b3c633f | 6786 | lra_assert (dregno >= 0); |
02ffd664 | 6787 | if (prev_insn != NULL && NONDEBUG_INSN_P (prev_insn) |
6788 | && GET_CODE (PATTERN (prev_insn)) == CLOBBER | |
6789 | && dregno == get_regno (XEXP (PATTERN (prev_insn), 0))) | |
6790 | lra_set_insn_deleted (prev_insn); | |
6791 | } | |
6792 | ||
c6a6cdaa | 6793 | /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and |
6794 | return true if we did any change. The undo transformations for | |
6795 | inheritance looks like | |
6796 | i <- i2 | |
6797 | p <- i => p <- i2 | |
6798 | or removing | |
6799 | p <- i, i <- p, and i <- i3 | |
6800 | where p is original pseudo from which inheritance pseudo i was | |
6801 | created, i and i3 are removed inheritance pseudos, i2 is another | |
6802 | not removed inheritance pseudo. All split pseudos or other | |
6803 | occurrences of removed inheritance pseudos are changed on the | |
6804 | corresponding original pseudos. | |
6805 | ||
6806 | The function also schedules insns changed and created during | |
6807 | inheritance/split pass for processing by the subsequent constraint | |
6808 | pass. */ | |
6809 | static bool | |
6810 | remove_inheritance_pseudos (bitmap remove_pseudos) | |
6811 | { | |
6812 | basic_block bb; | |
ab4ea053 | 6813 | int regno, sregno, prev_sregno, dregno; |
6814 | rtx restore_rtx; | |
7f836b57 | 6815 | rtx set, prev_set; |
6816 | rtx_insn *prev_insn; | |
c6a6cdaa | 6817 | bool change_p, done_p; |
6818 | ||
6819 | change_p = ! bitmap_empty_p (remove_pseudos); | |
f4d3c071 | 6820 | /* We cannot finish the function right away if CHANGE_P is true |
c6a6cdaa | 6821 | because we need to marks insns affected by previous |
6822 | inheritance/split pass for processing by the subsequent | |
6823 | constraint pass. */ | |
fc00614f | 6824 | FOR_EACH_BB_FN (bb, cfun) |
c6a6cdaa | 6825 | { |
6826 | fix_bb_live_info (df_get_live_in (bb), remove_pseudos); | |
6827 | fix_bb_live_info (df_get_live_out (bb), remove_pseudos); | |
6828 | FOR_BB_INSNS_REVERSE (bb, curr_insn) | |
6829 | { | |
6830 | if (! INSN_P (curr_insn)) | |
6831 | continue; | |
6832 | done_p = false; | |
6833 | sregno = dregno = -1; | |
6834 | if (change_p && NONDEBUG_INSN_P (curr_insn) | |
6835 | && (set = single_set (curr_insn)) != NULL_RTX) | |
6836 | { | |
6837 | dregno = get_regno (SET_DEST (set)); | |
6838 | sregno = get_regno (SET_SRC (set)); | |
6839 | } | |
1a8f8886 | 6840 | |
c6a6cdaa | 6841 | if (sregno >= 0 && dregno >= 0) |
6842 | { | |
ab4ea053 | 6843 | if (bitmap_bit_p (remove_pseudos, dregno) |
6844 | && ! REG_P (lra_reg_info[dregno].restore_rtx)) | |
6845 | { | |
6846 | /* invariant inheritance pseudo <- original pseudo */ | |
6847 | if (lra_dump_file != NULL) | |
6848 | { | |
6849 | fprintf (lra_dump_file, " Removing invariant inheritance:\n"); | |
6850 | dump_insn_slim (lra_dump_file, curr_insn); | |
6851 | fprintf (lra_dump_file, "\n"); | |
6852 | } | |
6853 | delete_move_and_clobber (curr_insn, dregno); | |
6854 | done_p = true; | |
6855 | } | |
6856 | else if (bitmap_bit_p (remove_pseudos, sregno) | |
6857 | && ! REG_P (lra_reg_info[sregno].restore_rtx)) | |
6858 | { | |
6859 | /* reload pseudo <- invariant inheritance pseudo */ | |
6860 | start_sequence (); | |
f4d3c071 | 6861 | /* We cannot just change the source. It might be |
ab4ea053 | 6862 | an insn different from the move. */ |
fee93b91 | 6863 | emit_insn (lra_reg_info[sregno].restore_rtx); |
ab4ea053 | 6864 | rtx_insn *new_insns = get_insns (); |
6865 | end_sequence (); | |
fee93b91 | 6866 | lra_assert (single_set (new_insns) != NULL |
6867 | && SET_DEST (set) == SET_DEST (single_set (new_insns))); | |
ab4ea053 | 6868 | lra_process_new_insns (curr_insn, NULL, new_insns, |
6869 | "Changing reload<-invariant inheritance"); | |
6870 | delete_move_and_clobber (curr_insn, dregno); | |
6871 | done_p = true; | |
6872 | } | |
6873 | else if ((bitmap_bit_p (remove_pseudos, sregno) | |
6874 | && (get_regno (lra_reg_info[sregno].restore_rtx) == dregno | |
6875 | || (bitmap_bit_p (remove_pseudos, dregno) | |
6876 | && get_regno (lra_reg_info[sregno].restore_rtx) >= 0 | |
6877 | && (get_regno (lra_reg_info[sregno].restore_rtx) | |
6878 | == get_regno (lra_reg_info[dregno].restore_rtx))))) | |
c6a6cdaa | 6879 | || (bitmap_bit_p (remove_pseudos, dregno) |
ab4ea053 | 6880 | && get_regno (lra_reg_info[dregno].restore_rtx) == sregno)) |
c6a6cdaa | 6881 | /* One of the following cases: |
6882 | original <- removed inheritance pseudo | |
6883 | removed inherit pseudo <- another removed inherit pseudo | |
6884 | removed inherit pseudo <- original pseudo | |
6885 | Or | |
6886 | removed_split_pseudo <- original_reg | |
6887 | original_reg <- removed_split_pseudo */ | |
6888 | { | |
6889 | if (lra_dump_file != NULL) | |
6890 | { | |
6891 | fprintf (lra_dump_file, " Removing %s:\n", | |
6892 | bitmap_bit_p (&lra_split_regs, sregno) | |
6893 | || bitmap_bit_p (&lra_split_regs, dregno) | |
6894 | ? "split" : "inheritance"); | |
6dde9719 | 6895 | dump_insn_slim (lra_dump_file, curr_insn); |
c6a6cdaa | 6896 | } |
02ffd664 | 6897 | delete_move_and_clobber (curr_insn, dregno); |
c6a6cdaa | 6898 | done_p = true; |
6899 | } | |
6900 | else if (bitmap_bit_p (remove_pseudos, sregno) | |
6901 | && bitmap_bit_p (&lra_inheritance_pseudos, sregno)) | |
6902 | { | |
6903 | /* Search the following pattern: | |
6904 | inherit_or_split_pseudo1 <- inherit_or_split_pseudo2 | |
6905 | original_pseudo <- inherit_or_split_pseudo1 | |
6906 | where the 2nd insn is the current insn and | |
6907 | inherit_or_split_pseudo2 is not removed. If it is found, | |
6908 | change the current insn onto: | |
6909 | original_pseudo <- inherit_or_split_pseudo2. */ | |
6910 | for (prev_insn = PREV_INSN (curr_insn); | |
6911 | prev_insn != NULL_RTX && ! NONDEBUG_INSN_P (prev_insn); | |
6912 | prev_insn = PREV_INSN (prev_insn)) | |
6913 | ; | |
6914 | if (prev_insn != NULL_RTX && BLOCK_FOR_INSN (prev_insn) == bb | |
6915 | && (prev_set = single_set (prev_insn)) != NULL_RTX | |
6916 | /* There should be no subregs in insn we are | |
6917 | searching because only the original reg might | |
6918 | be in subreg when we changed the mode of | |
6919 | load/store for splitting. */ | |
6920 | && REG_P (SET_DEST (prev_set)) | |
6921 | && REG_P (SET_SRC (prev_set)) | |
6922 | && (int) REGNO (SET_DEST (prev_set)) == sregno | |
6923 | && ((prev_sregno = REGNO (SET_SRC (prev_set))) | |
6924 | >= FIRST_PSEUDO_REGISTER) | |
ab4ea053 | 6925 | && (lra_reg_info[prev_sregno].restore_rtx == NULL_RTX |
6926 | || | |
6927 | /* As we consider chain of inheritance or | |
6928 | splitting described in above comment we should | |
6929 | check that sregno and prev_sregno were | |
6930 | inheritance/split pseudos created from the | |
6931 | same original regno. */ | |
6932 | (get_regno (lra_reg_info[sregno].restore_rtx) >= 0 | |
6933 | && (get_regno (lra_reg_info[sregno].restore_rtx) | |
6934 | == get_regno (lra_reg_info[prev_sregno].restore_rtx)))) | |
c6a6cdaa | 6935 | && ! bitmap_bit_p (remove_pseudos, prev_sregno)) |
6936 | { | |
6937 | lra_assert (GET_MODE (SET_SRC (prev_set)) | |
6938 | == GET_MODE (regno_reg_rtx[sregno])); | |
2b69ec1c | 6939 | /* Although we have a single set, the insn can |
6940 | contain more one sregno register occurrence | |
6941 | as a source. Change all occurrences. */ | |
6942 | lra_substitute_pseudo_within_insn (curr_insn, sregno, | |
6943 | SET_SRC (prev_set), | |
6944 | false); | |
ef76edc2 | 6945 | /* As we are finishing with processing the insn |
6946 | here, check the destination too as it might | |
6947 | inheritance pseudo for another pseudo. */ | |
6948 | if (bitmap_bit_p (remove_pseudos, dregno) | |
6949 | && bitmap_bit_p (&lra_inheritance_pseudos, dregno) | |
ab4ea053 | 6950 | && (restore_rtx |
6951 | = lra_reg_info[dregno].restore_rtx) != NULL_RTX) | |
ef76edc2 | 6952 | { |
6953 | if (GET_CODE (SET_DEST (set)) == SUBREG) | |
ab4ea053 | 6954 | SUBREG_REG (SET_DEST (set)) = restore_rtx; |
ef76edc2 | 6955 | else |
ab4ea053 | 6956 | SET_DEST (set) = restore_rtx; |
ef76edc2 | 6957 | } |
c6a6cdaa | 6958 | lra_push_insn_and_update_insn_regno_info (curr_insn); |
6959 | lra_set_used_insn_alternative_by_uid | |
71d47a14 | 6960 | (INSN_UID (curr_insn), LRA_UNKNOWN_ALT); |
c6a6cdaa | 6961 | done_p = true; |
6962 | if (lra_dump_file != NULL) | |
6963 | { | |
6964 | fprintf (lra_dump_file, " Change reload insn:\n"); | |
6dde9719 | 6965 | dump_insn_slim (lra_dump_file, curr_insn); |
c6a6cdaa | 6966 | } |
6967 | } | |
6968 | } | |
6969 | } | |
6970 | if (! done_p) | |
6971 | { | |
6972 | struct lra_insn_reg *reg; | |
6973 | bool restored_regs_p = false; | |
6974 | bool kept_regs_p = false; | |
6975 | ||
6976 | curr_id = lra_get_insn_recog_data (curr_insn); | |
6977 | for (reg = curr_id->regs; reg != NULL; reg = reg->next) | |
6978 | { | |
6979 | regno = reg->regno; | |
ab4ea053 | 6980 | restore_rtx = lra_reg_info[regno].restore_rtx; |
6981 | if (restore_rtx != NULL_RTX) | |
c6a6cdaa | 6982 | { |
6983 | if (change_p && bitmap_bit_p (remove_pseudos, regno)) | |
6984 | { | |
06072e79 | 6985 | lra_substitute_pseudo_within_insn |
ab4ea053 | 6986 | (curr_insn, regno, restore_rtx, false); |
c6a6cdaa | 6987 | restored_regs_p = true; |
6988 | } | |
6989 | else | |
6990 | kept_regs_p = true; | |
6991 | } | |
6992 | } | |
6993 | if (NONDEBUG_INSN_P (curr_insn) && kept_regs_p) | |
6994 | { | |
6995 | /* The instruction has changed since the previous | |
6996 | constraints pass. */ | |
6997 | lra_push_insn_and_update_insn_regno_info (curr_insn); | |
6998 | lra_set_used_insn_alternative_by_uid | |
71d47a14 | 6999 | (INSN_UID (curr_insn), LRA_UNKNOWN_ALT); |
c6a6cdaa | 7000 | } |
7001 | else if (restored_regs_p) | |
7002 | /* The instruction has been restored to the form that | |
7003 | it had during the previous constraints pass. */ | |
7004 | lra_update_insn_regno_info (curr_insn); | |
7005 | if (restored_regs_p && lra_dump_file != NULL) | |
7006 | { | |
7007 | fprintf (lra_dump_file, " Insn after restoring regs:\n"); | |
6dde9719 | 7008 | dump_insn_slim (lra_dump_file, curr_insn); |
c6a6cdaa | 7009 | } |
7010 | } | |
7011 | } | |
7012 | } | |
7013 | return change_p; | |
7014 | } | |
7015 | ||
1f3a048a | 7016 | /* If optional reload pseudos failed to get a hard register or was not |
7017 | inherited, it is better to remove optional reloads. We do this | |
7018 | transformation after undoing inheritance to figure out necessity to | |
7019 | remove optional reloads easier. Return true if we do any | |
7020 | change. */ | |
7021 | static bool | |
7022 | undo_optional_reloads (void) | |
7023 | { | |
267200f3 | 7024 | bool change_p, keep_p; |
1f3a048a | 7025 | unsigned int regno, uid; |
7026 | bitmap_iterator bi, bi2; | |
7f836b57 | 7027 | rtx_insn *insn; |
7028 | rtx set, src, dest; | |
f6708c36 | 7029 | auto_bitmap removed_optional_reload_pseudos (®_obstack); |
1f3a048a | 7030 | |
f6708c36 | 7031 | bitmap_copy (removed_optional_reload_pseudos, &lra_optional_reload_pseudos); |
1f3a048a | 7032 | EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos, 0, regno, bi) |
0c4735d1 | 7033 | { |
7034 | keep_p = false; | |
95563487 | 7035 | /* Keep optional reloads from previous subpasses. */ |
ab4ea053 | 7036 | if (lra_reg_info[regno].restore_rtx == NULL_RTX |
95563487 | 7037 | /* If the original pseudo changed its allocation, just |
7038 | removing the optional pseudo is dangerous as the original | |
7039 | pseudo will have longer live range. */ | |
ab4ea053 | 7040 | || reg_renumber[REGNO (lra_reg_info[regno].restore_rtx)] >= 0) |
0c4735d1 | 7041 | keep_p = true; |
7042 | else if (reg_renumber[regno] >= 0) | |
7043 | EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi2) | |
267200f3 | 7044 | { |
0c4735d1 | 7045 | insn = lra_insn_recog_data[uid]->insn; |
7046 | if ((set = single_set (insn)) == NULL_RTX) | |
7047 | continue; | |
7048 | src = SET_SRC (set); | |
7049 | dest = SET_DEST (set); | |
7050 | if (! REG_P (src) || ! REG_P (dest)) | |
7051 | continue; | |
7052 | if (REGNO (dest) == regno | |
7053 | /* Ignore insn for optional reloads itself. */ | |
ab4ea053 | 7054 | && REGNO (lra_reg_info[regno].restore_rtx) != REGNO (src) |
0c4735d1 | 7055 | /* Check only inheritance on last inheritance pass. */ |
7056 | && (int) REGNO (src) >= new_regno_start | |
7057 | /* Check that the optional reload was inherited. */ | |
7058 | && bitmap_bit_p (&lra_inheritance_pseudos, REGNO (src))) | |
7059 | { | |
7060 | keep_p = true; | |
7061 | break; | |
7062 | } | |
267200f3 | 7063 | } |
0c4735d1 | 7064 | if (keep_p) |
7065 | { | |
f6708c36 | 7066 | bitmap_clear_bit (removed_optional_reload_pseudos, regno); |
0c4735d1 | 7067 | if (lra_dump_file != NULL) |
7068 | fprintf (lra_dump_file, "Keep optional reload reg %d\n", regno); | |
7069 | } | |
7070 | } | |
f6708c36 | 7071 | change_p = ! bitmap_empty_p (removed_optional_reload_pseudos); |
7072 | auto_bitmap insn_bitmap (®_obstack); | |
7073 | EXECUTE_IF_SET_IN_BITMAP (removed_optional_reload_pseudos, 0, regno, bi) | |
1f3a048a | 7074 | { |
7075 | if (lra_dump_file != NULL) | |
7076 | fprintf (lra_dump_file, "Remove optional reload reg %d\n", regno); | |
f6708c36 | 7077 | bitmap_copy (insn_bitmap, &lra_reg_info[regno].insn_bitmap); |
7078 | EXECUTE_IF_SET_IN_BITMAP (insn_bitmap, 0, uid, bi2) | |
1f3a048a | 7079 | { |
7080 | insn = lra_insn_recog_data[uid]->insn; | |
7081 | if ((set = single_set (insn)) != NULL_RTX) | |
7082 | { | |
7083 | src = SET_SRC (set); | |
7084 | dest = SET_DEST (set); | |
7085 | if (REG_P (src) && REG_P (dest) | |
7086 | && ((REGNO (src) == regno | |
ab4ea053 | 7087 | && (REGNO (lra_reg_info[regno].restore_rtx) |
7088 | == REGNO (dest))) | |
1f3a048a | 7089 | || (REGNO (dest) == regno |
ab4ea053 | 7090 | && (REGNO (lra_reg_info[regno].restore_rtx) |
7091 | == REGNO (src))))) | |
1f3a048a | 7092 | { |
7093 | if (lra_dump_file != NULL) | |
7094 | { | |
7095 | fprintf (lra_dump_file, " Deleting move %u\n", | |
7096 | INSN_UID (insn)); | |
7097 | dump_insn_slim (lra_dump_file, insn); | |
7098 | } | |
02ffd664 | 7099 | delete_move_and_clobber (insn, REGNO (dest)); |
1f3a048a | 7100 | continue; |
7101 | } | |
7102 | /* We should not worry about generation memory-memory | |
7103 | moves here as if the corresponding inheritance did | |
7104 | not work (inheritance pseudo did not get a hard reg), | |
7105 | we remove the inheritance pseudo and the optional | |
7106 | reload. */ | |
7107 | } | |
06072e79 | 7108 | lra_substitute_pseudo_within_insn |
ab4ea053 | 7109 | (insn, regno, lra_reg_info[regno].restore_rtx, false); |
1f3a048a | 7110 | lra_update_insn_regno_info (insn); |
7111 | if (lra_dump_file != NULL) | |
7112 | { | |
7113 | fprintf (lra_dump_file, | |
7114 | " Restoring original insn:\n"); | |
7115 | dump_insn_slim (lra_dump_file, insn); | |
7116 | } | |
7117 | } | |
7118 | } | |
7119 | /* Clear restore_regnos. */ | |
7120 | EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos, 0, regno, bi) | |
ab4ea053 | 7121 | lra_reg_info[regno].restore_rtx = NULL_RTX; |
1f3a048a | 7122 | return change_p; |
7123 | } | |
7124 | ||
c6a6cdaa | 7125 | /* Entry function for undoing inheritance/split transformation. Return true |
7126 | if we did any RTL change in this pass. */ | |
7127 | bool | |
7128 | lra_undo_inheritance (void) | |
7129 | { | |
7130 | unsigned int regno; | |
ab4ea053 | 7131 | int hard_regno; |
c6a6cdaa | 7132 | int n_all_inherit, n_inherit, n_all_split, n_split; |
ab4ea053 | 7133 | rtx restore_rtx; |
c6a6cdaa | 7134 | bitmap_iterator bi; |
7135 | bool change_p; | |
7136 | ||
7137 | lra_undo_inheritance_iter++; | |
47f6add2 | 7138 | if (lra_undo_inheritance_iter > LRA_MAX_INHERITANCE_PASSES) |
7b184c47 | 7139 | return false; |
c6a6cdaa | 7140 | if (lra_dump_file != NULL) |
7141 | fprintf (lra_dump_file, | |
7142 | "\n********** Undoing inheritance #%d: **********\n\n", | |
7143 | lra_undo_inheritance_iter); | |
f6708c36 | 7144 | auto_bitmap remove_pseudos (®_obstack); |
c6a6cdaa | 7145 | n_inherit = n_all_inherit = 0; |
7146 | EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos, 0, regno, bi) | |
ab4ea053 | 7147 | if (lra_reg_info[regno].restore_rtx != NULL_RTX) |
c6a6cdaa | 7148 | { |
7149 | n_all_inherit++; | |
267200f3 | 7150 | if (reg_renumber[regno] < 0 |
7151 | /* If the original pseudo changed its allocation, just | |
7152 | removing inheritance is dangerous as for changing | |
7153 | allocation we used shorter live-ranges. */ | |
ab4ea053 | 7154 | && (! REG_P (lra_reg_info[regno].restore_rtx) |
7155 | || reg_renumber[REGNO (lra_reg_info[regno].restore_rtx)] < 0)) | |
f6708c36 | 7156 | bitmap_set_bit (remove_pseudos, regno); |
c6a6cdaa | 7157 | else |
7158 | n_inherit++; | |
7159 | } | |
7160 | if (lra_dump_file != NULL && n_all_inherit != 0) | |
7161 | fprintf (lra_dump_file, "Inherit %d out of %d (%.2f%%)\n", | |
7162 | n_inherit, n_all_inherit, | |
7163 | (double) n_inherit / n_all_inherit * 100); | |
7164 | n_split = n_all_split = 0; | |
7165 | EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs, 0, regno, bi) | |
ab4ea053 | 7166 | if ((restore_rtx = lra_reg_info[regno].restore_rtx) != NULL_RTX) |
c6a6cdaa | 7167 | { |
ab4ea053 | 7168 | int restore_regno = REGNO (restore_rtx); |
7169 | ||
c6a6cdaa | 7170 | n_all_split++; |
7171 | hard_regno = (restore_regno >= FIRST_PSEUDO_REGISTER | |
7172 | ? reg_renumber[restore_regno] : restore_regno); | |
7173 | if (hard_regno < 0 || reg_renumber[regno] == hard_regno) | |
f6708c36 | 7174 | bitmap_set_bit (remove_pseudos, regno); |
c6a6cdaa | 7175 | else |
7176 | { | |
7177 | n_split++; | |
7178 | if (lra_dump_file != NULL) | |
7179 | fprintf (lra_dump_file, " Keep split r%d (orig=r%d)\n", | |
7180 | regno, restore_regno); | |
7181 | } | |
7182 | } | |
7183 | if (lra_dump_file != NULL && n_all_split != 0) | |
7184 | fprintf (lra_dump_file, "Split %d out of %d (%.2f%%)\n", | |
7185 | n_split, n_all_split, | |
7186 | (double) n_split / n_all_split * 100); | |
f6708c36 | 7187 | change_p = remove_inheritance_pseudos (remove_pseudos); |
c6a6cdaa | 7188 | /* Clear restore_regnos. */ |
7189 | EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos, 0, regno, bi) | |
ab4ea053 | 7190 | lra_reg_info[regno].restore_rtx = NULL_RTX; |
c6a6cdaa | 7191 | EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs, 0, regno, bi) |
ab4ea053 | 7192 | lra_reg_info[regno].restore_rtx = NULL_RTX; |
1f3a048a | 7193 | change_p = undo_optional_reloads () || change_p; |
c6a6cdaa | 7194 | return change_p; |
7195 | } |