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55a2c322 | 1 | /* Code for RTL transformations to satisfy insn constraints. |
d1e082c2 | 2 | Copyright (C) 2010-2013 Free Software Foundation, Inc. |
55a2c322 VM |
3 | Contributed by Vladimir Makarov <vmakarov@redhat.com>. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it under | |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 3, or (at your option) any later | |
10 | version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | ||
22 | /* This file contains code for 3 passes: constraint pass, | |
23 | inheritance/split pass, and pass for undoing failed inheritance and | |
24 | split. | |
25 | ||
26 | The major goal of constraint pass is to transform RTL to satisfy | |
27 | insn and address constraints by: | |
28 | o choosing insn alternatives; | |
29 | o generating *reload insns* (or reloads in brief) and *reload | |
30 | pseudos* which will get necessary hard registers later; | |
31 | o substituting pseudos with equivalent values and removing the | |
32 | instructions that initialized those pseudos. | |
33 | ||
34 | The constraint pass has biggest and most complicated code in LRA. | |
35 | There are a lot of important details like: | |
36 | o reuse of input reload pseudos to simplify reload pseudo | |
37 | allocations; | |
38 | o some heuristics to choose insn alternative to improve the | |
39 | inheritance; | |
40 | o early clobbers etc. | |
41 | ||
42 | The pass is mimicking former reload pass in alternative choosing | |
43 | because the reload pass is oriented to current machine description | |
44 | model. It might be changed if the machine description model is | |
45 | changed. | |
46 | ||
47 | There is special code for preventing all LRA and this pass cycling | |
48 | in case of bugs. | |
49 | ||
50 | On the first iteration of the pass we process every instruction and | |
51 | choose an alternative for each one. On subsequent iterations we try | |
52 | to avoid reprocessing instructions if we can be sure that the old | |
53 | choice is still valid. | |
54 | ||
55 | The inheritance/spilt pass is to transform code to achieve | |
56 | ineheritance and live range splitting. It is done on backward | |
57 | traversal of EBBs. | |
58 | ||
59 | The inheritance optimization goal is to reuse values in hard | |
60 | registers. There is analogous optimization in old reload pass. The | |
61 | inheritance is achieved by following transformation: | |
62 | ||
63 | reload_p1 <- p reload_p1 <- p | |
64 | ... new_p <- reload_p1 | |
65 | ... => ... | |
66 | reload_p2 <- p reload_p2 <- new_p | |
67 | ||
68 | where p is spilled and not changed between the insns. Reload_p1 is | |
69 | also called *original pseudo* and new_p is called *inheritance | |
70 | pseudo*. | |
71 | ||
72 | The subsequent assignment pass will try to assign the same (or | |
73 | another if it is not possible) hard register to new_p as to | |
74 | reload_p1 or reload_p2. | |
75 | ||
76 | If the assignment pass fails to assign a hard register to new_p, | |
77 | this file will undo the inheritance and restore the original code. | |
78 | This is because implementing the above sequence with a spilled | |
79 | new_p would make the code much worse. The inheritance is done in | |
80 | EBB scope. The above is just a simplified example to get an idea | |
81 | of the inheritance as the inheritance is also done for non-reload | |
82 | insns. | |
83 | ||
84 | Splitting (transformation) is also done in EBB scope on the same | |
85 | pass as the inheritance: | |
86 | ||
87 | r <- ... or ... <- r r <- ... or ... <- r | |
88 | ... s <- r (new insn -- save) | |
f4eafc30 | 89 | ... => |
55a2c322 VM |
90 | ... r <- s (new insn -- restore) |
91 | ... <- r ... <- r | |
92 | ||
93 | The *split pseudo* s is assigned to the hard register of the | |
94 | original pseudo or hard register r. | |
95 | ||
96 | Splitting is done: | |
97 | o In EBBs with high register pressure for global pseudos (living | |
98 | in at least 2 BBs) and assigned to hard registers when there | |
99 | are more one reloads needing the hard registers; | |
100 | o for pseudos needing save/restore code around calls. | |
101 | ||
102 | If the split pseudo still has the same hard register as the | |
103 | original pseudo after the subsequent assignment pass or the | |
104 | original pseudo was split, the opposite transformation is done on | |
105 | the same pass for undoing inheritance. */ | |
106 | ||
107 | #undef REG_OK_STRICT | |
108 | ||
109 | #include "config.h" | |
110 | #include "system.h" | |
111 | #include "coretypes.h" | |
112 | #include "tm.h" | |
113 | #include "hard-reg-set.h" | |
114 | #include "rtl.h" | |
115 | #include "tm_p.h" | |
116 | #include "regs.h" | |
117 | #include "insn-config.h" | |
118 | #include "insn-codes.h" | |
119 | #include "recog.h" | |
120 | #include "output.h" | |
121 | #include "addresses.h" | |
122 | #include "target.h" | |
123 | #include "function.h" | |
124 | #include "expr.h" | |
125 | #include "basic-block.h" | |
126 | #include "except.h" | |
127 | #include "optabs.h" | |
128 | #include "df.h" | |
129 | #include "ira.h" | |
130 | #include "rtl-error.h" | |
131 | #include "lra-int.h" | |
132 | ||
133 | /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current | |
134 | insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted | |
135 | reload insns. */ | |
136 | static int bb_reload_num; | |
137 | ||
2c62cbaa VM |
138 | /* The current insn being processed and corresponding its single set |
139 | (NULL otherwise), its data (basic block, the insn data, the insn | |
140 | static data, and the mode of each operand). */ | |
55a2c322 | 141 | static rtx curr_insn; |
2c62cbaa | 142 | static rtx curr_insn_set; |
55a2c322 VM |
143 | static basic_block curr_bb; |
144 | static lra_insn_recog_data_t curr_id; | |
145 | static struct lra_static_insn_data *curr_static_id; | |
146 | static enum machine_mode curr_operand_mode[MAX_RECOG_OPERANDS]; | |
147 | ||
148 | \f | |
149 | ||
150 | /* Start numbers for new registers and insns at the current constraints | |
151 | pass start. */ | |
152 | static int new_regno_start; | |
153 | static int new_insn_uid_start; | |
154 | ||
277f65de RS |
155 | /* If LOC is nonnull, strip any outer subreg from it. */ |
156 | static inline rtx * | |
157 | strip_subreg (rtx *loc) | |
158 | { | |
159 | return loc && GET_CODE (*loc) == SUBREG ? &SUBREG_REG (*loc) : loc; | |
160 | } | |
161 | ||
55a2c322 VM |
162 | /* Return hard regno of REGNO or if it is was not assigned to a hard |
163 | register, use a hard register from its allocno class. */ | |
164 | static int | |
165 | get_try_hard_regno (int regno) | |
166 | { | |
167 | int hard_regno; | |
168 | enum reg_class rclass; | |
169 | ||
170 | if ((hard_regno = regno) >= FIRST_PSEUDO_REGISTER) | |
171 | hard_regno = lra_get_regno_hard_regno (regno); | |
172 | if (hard_regno >= 0) | |
173 | return hard_regno; | |
174 | rclass = lra_get_allocno_class (regno); | |
175 | if (rclass == NO_REGS) | |
176 | return -1; | |
177 | return ira_class_hard_regs[rclass][0]; | |
178 | } | |
179 | ||
180 | /* Return final hard regno (plus offset) which will be after | |
181 | elimination. We do this for matching constraints because the final | |
182 | hard regno could have a different class. */ | |
183 | static int | |
184 | get_final_hard_regno (int hard_regno, int offset) | |
185 | { | |
186 | if (hard_regno < 0) | |
187 | return hard_regno; | |
188 | hard_regno = lra_get_elimination_hard_regno (hard_regno); | |
189 | return hard_regno + offset; | |
190 | } | |
191 | ||
192 | /* Return hard regno of X after removing subreg and making | |
193 | elimination. If X is not a register or subreg of register, return | |
194 | -1. For pseudo use its assignment. */ | |
195 | static int | |
196 | get_hard_regno (rtx x) | |
197 | { | |
198 | rtx reg; | |
199 | int offset, hard_regno; | |
200 | ||
201 | reg = x; | |
202 | if (GET_CODE (x) == SUBREG) | |
203 | reg = SUBREG_REG (x); | |
204 | if (! REG_P (reg)) | |
205 | return -1; | |
206 | if ((hard_regno = REGNO (reg)) >= FIRST_PSEUDO_REGISTER) | |
207 | hard_regno = lra_get_regno_hard_regno (hard_regno); | |
208 | if (hard_regno < 0) | |
209 | return -1; | |
210 | offset = 0; | |
211 | if (GET_CODE (x) == SUBREG) | |
212 | offset += subreg_regno_offset (hard_regno, GET_MODE (reg), | |
213 | SUBREG_BYTE (x), GET_MODE (x)); | |
214 | return get_final_hard_regno (hard_regno, offset); | |
215 | } | |
216 | ||
217 | /* If REGNO is a hard register or has been allocated a hard register, | |
218 | return the class of that register. If REGNO is a reload pseudo | |
219 | created by the current constraints pass, return its allocno class. | |
220 | Return NO_REGS otherwise. */ | |
221 | static enum reg_class | |
222 | get_reg_class (int regno) | |
223 | { | |
224 | int hard_regno; | |
225 | ||
226 | if ((hard_regno = regno) >= FIRST_PSEUDO_REGISTER) | |
227 | hard_regno = lra_get_regno_hard_regno (regno); | |
228 | if (hard_regno >= 0) | |
229 | { | |
230 | hard_regno = get_final_hard_regno (hard_regno, 0); | |
231 | return REGNO_REG_CLASS (hard_regno); | |
232 | } | |
233 | if (regno >= new_regno_start) | |
234 | return lra_get_allocno_class (regno); | |
235 | return NO_REGS; | |
236 | } | |
237 | ||
238 | /* Return true if REG satisfies (or will satisfy) reg class constraint | |
239 | CL. Use elimination first if REG is a hard register. If REG is a | |
240 | reload pseudo created by this constraints pass, assume that it will | |
241 | be allocated a hard register from its allocno class, but allow that | |
242 | class to be narrowed to CL if it is currently a superset of CL. | |
243 | ||
244 | If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of | |
245 | REGNO (reg), or NO_REGS if no change in its class was needed. */ | |
246 | static bool | |
247 | in_class_p (rtx reg, enum reg_class cl, enum reg_class *new_class) | |
248 | { | |
249 | enum reg_class rclass, common_class; | |
250 | enum machine_mode reg_mode; | |
251 | int class_size, hard_regno, nregs, i, j; | |
252 | int regno = REGNO (reg); | |
f4eafc30 | 253 | |
55a2c322 VM |
254 | if (new_class != NULL) |
255 | *new_class = NO_REGS; | |
256 | if (regno < FIRST_PSEUDO_REGISTER) | |
257 | { | |
258 | rtx final_reg = reg; | |
259 | rtx *final_loc = &final_reg; | |
f4eafc30 | 260 | |
55a2c322 VM |
261 | lra_eliminate_reg_if_possible (final_loc); |
262 | return TEST_HARD_REG_BIT (reg_class_contents[cl], REGNO (*final_loc)); | |
263 | } | |
264 | reg_mode = GET_MODE (reg); | |
265 | rclass = get_reg_class (regno); | |
266 | if (regno < new_regno_start | |
267 | /* Do not allow the constraints for reload instructions to | |
268 | influence the classes of new pseudos. These reloads are | |
269 | typically moves that have many alternatives, and restricting | |
270 | reload pseudos for one alternative may lead to situations | |
271 | where other reload pseudos are no longer allocatable. */ | |
272 | || INSN_UID (curr_insn) >= new_insn_uid_start) | |
273 | /* When we don't know what class will be used finally for reload | |
274 | pseudos, we use ALL_REGS. */ | |
275 | return ((regno >= new_regno_start && rclass == ALL_REGS) | |
276 | || (rclass != NO_REGS && ira_class_subset_p[rclass][cl] | |
277 | && ! hard_reg_set_subset_p (reg_class_contents[cl], | |
278 | lra_no_alloc_regs))); | |
279 | else | |
280 | { | |
281 | common_class = ira_reg_class_subset[rclass][cl]; | |
282 | if (new_class != NULL) | |
283 | *new_class = common_class; | |
284 | if (hard_reg_set_subset_p (reg_class_contents[common_class], | |
285 | lra_no_alloc_regs)) | |
286 | return false; | |
287 | /* Check that there are enough allocatable regs. */ | |
288 | class_size = ira_class_hard_regs_num[common_class]; | |
289 | for (i = 0; i < class_size; i++) | |
290 | { | |
291 | hard_regno = ira_class_hard_regs[common_class][i]; | |
292 | nregs = hard_regno_nregs[hard_regno][reg_mode]; | |
293 | if (nregs == 1) | |
294 | return true; | |
295 | for (j = 0; j < nregs; j++) | |
f421c426 VM |
296 | if (TEST_HARD_REG_BIT (lra_no_alloc_regs, hard_regno + j) |
297 | || ! TEST_HARD_REG_BIT (reg_class_contents[common_class], | |
298 | hard_regno + j)) | |
55a2c322 VM |
299 | break; |
300 | if (j >= nregs) | |
301 | return true; | |
302 | } | |
303 | return false; | |
304 | } | |
305 | } | |
306 | ||
307 | /* Return true if REGNO satisfies a memory constraint. */ | |
308 | static bool | |
309 | in_mem_p (int regno) | |
310 | { | |
311 | return get_reg_class (regno) == NO_REGS; | |
312 | } | |
313 | ||
314 | /* If we have decided to substitute X with another value, return that | |
315 | value, otherwise return X. */ | |
316 | static rtx | |
317 | get_equiv_substitution (rtx x) | |
318 | { | |
319 | int regno; | |
320 | rtx res; | |
321 | ||
322 | if (! REG_P (x) || (regno = REGNO (x)) < FIRST_PSEUDO_REGISTER | |
323 | || ! ira_reg_equiv[regno].defined_p | |
324 | || ! ira_reg_equiv[regno].profitable_p | |
325 | || lra_get_regno_hard_regno (regno) >= 0) | |
326 | return x; | |
327 | if ((res = ira_reg_equiv[regno].memory) != NULL_RTX) | |
328 | return res; | |
329 | if ((res = ira_reg_equiv[regno].constant) != NULL_RTX) | |
330 | return res; | |
331 | if ((res = ira_reg_equiv[regno].invariant) != NULL_RTX) | |
332 | return res; | |
333 | gcc_unreachable (); | |
334 | } | |
335 | ||
336 | /* Set up curr_operand_mode. */ | |
337 | static void | |
338 | init_curr_operand_mode (void) | |
339 | { | |
340 | int nop = curr_static_id->n_operands; | |
341 | for (int i = 0; i < nop; i++) | |
342 | { | |
343 | enum machine_mode mode = GET_MODE (*curr_id->operand_loc[i]); | |
344 | if (mode == VOIDmode) | |
345 | { | |
346 | /* The .md mode for address operands is the mode of the | |
347 | addressed value rather than the mode of the address itself. */ | |
348 | if (curr_id->icode >= 0 && curr_static_id->operand[i].is_address) | |
349 | mode = Pmode; | |
350 | else | |
351 | mode = curr_static_id->operand[i].mode; | |
352 | } | |
353 | curr_operand_mode[i] = mode; | |
354 | } | |
355 | } | |
356 | ||
357 | \f | |
358 | ||
359 | /* The page contains code to reuse input reloads. */ | |
360 | ||
361 | /* Structure describes input reload of the current insns. */ | |
362 | struct input_reload | |
363 | { | |
364 | /* Reloaded value. */ | |
365 | rtx input; | |
366 | /* Reload pseudo used. */ | |
367 | rtx reg; | |
368 | }; | |
369 | ||
370 | /* The number of elements in the following array. */ | |
371 | static int curr_insn_input_reloads_num; | |
372 | /* Array containing info about input reloads. It is used to find the | |
373 | same input reload and reuse the reload pseudo in this case. */ | |
374 | static struct input_reload curr_insn_input_reloads[LRA_MAX_INSN_RELOADS]; | |
375 | ||
376 | /* Initiate data concerning reuse of input reloads for the current | |
377 | insn. */ | |
378 | static void | |
379 | init_curr_insn_input_reloads (void) | |
380 | { | |
381 | curr_insn_input_reloads_num = 0; | |
382 | } | |
383 | ||
384 | /* Change class of pseudo REGNO to NEW_CLASS. Print info about it | |
385 | using TITLE. Output a new line if NL_P. */ | |
386 | static void | |
387 | change_class (int regno, enum reg_class new_class, | |
388 | const char *title, bool nl_p) | |
389 | { | |
390 | lra_assert (regno >= FIRST_PSEUDO_REGISTER); | |
391 | if (lra_dump_file != NULL) | |
392 | fprintf (lra_dump_file, "%s to class %s for r%d", | |
393 | title, reg_class_names[new_class], regno); | |
394 | setup_reg_classes (regno, new_class, NO_REGS, new_class); | |
395 | if (lra_dump_file != NULL && nl_p) | |
396 | fprintf (lra_dump_file, "\n"); | |
397 | } | |
398 | ||
399 | /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already | |
400 | created input reload pseudo (only if TYPE is not OP_OUT). The | |
401 | result pseudo is returned through RESULT_REG. Return TRUE if we | |
402 | created a new pseudo, FALSE if we reused the already created input | |
403 | reload pseudo. Use TITLE to describe new registers for debug | |
404 | purposes. */ | |
405 | static bool | |
406 | get_reload_reg (enum op_type type, enum machine_mode mode, rtx original, | |
407 | enum reg_class rclass, const char *title, rtx *result_reg) | |
408 | { | |
409 | int i, regno; | |
410 | enum reg_class new_class; | |
411 | ||
412 | if (type == OP_OUT) | |
413 | { | |
414 | *result_reg | |
415 | = lra_create_new_reg_with_unique_value (mode, original, rclass, title); | |
416 | return true; | |
417 | } | |
73cca0cc VM |
418 | /* Prevent reuse value of expression with side effects, |
419 | e.g. volatile memory. */ | |
420 | if (! side_effects_p (original)) | |
421 | for (i = 0; i < curr_insn_input_reloads_num; i++) | |
422 | if (rtx_equal_p (curr_insn_input_reloads[i].input, original) | |
423 | && in_class_p (curr_insn_input_reloads[i].reg, rclass, &new_class)) | |
424 | { | |
5df81313 JJ |
425 | rtx reg = curr_insn_input_reloads[i].reg; |
426 | regno = REGNO (reg); | |
427 | /* If input is equal to original and both are VOIDmode, | |
428 | GET_MODE (reg) might be still different from mode. | |
429 | Ensure we don't return *result_reg with wrong mode. */ | |
430 | if (GET_MODE (reg) != mode) | |
431 | { | |
432 | if (GET_MODE_SIZE (GET_MODE (reg)) < GET_MODE_SIZE (mode)) | |
433 | continue; | |
434 | reg = lowpart_subreg (mode, reg, GET_MODE (reg)); | |
435 | if (reg == NULL_RTX || GET_CODE (reg) != SUBREG) | |
436 | continue; | |
437 | } | |
438 | *result_reg = reg; | |
73cca0cc VM |
439 | if (lra_dump_file != NULL) |
440 | { | |
441 | fprintf (lra_dump_file, " Reuse r%d for reload ", regno); | |
442 | dump_value_slim (lra_dump_file, original, 1); | |
443 | } | |
444 | if (new_class != lra_get_allocno_class (regno)) | |
445 | change_class (regno, new_class, ", change", false); | |
446 | if (lra_dump_file != NULL) | |
447 | fprintf (lra_dump_file, "\n"); | |
448 | return false; | |
449 | } | |
55a2c322 VM |
450 | *result_reg = lra_create_new_reg (mode, original, rclass, title); |
451 | lra_assert (curr_insn_input_reloads_num < LRA_MAX_INSN_RELOADS); | |
452 | curr_insn_input_reloads[curr_insn_input_reloads_num].input = original; | |
453 | curr_insn_input_reloads[curr_insn_input_reloads_num++].reg = *result_reg; | |
454 | return true; | |
455 | } | |
456 | ||
457 | \f | |
458 | ||
459 | /* The page contains code to extract memory address parts. */ | |
460 | ||
55a2c322 VM |
461 | /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudos. */ |
462 | static inline bool | |
463 | ok_for_index_p_nonstrict (rtx reg) | |
464 | { | |
465 | unsigned regno = REGNO (reg); | |
f4eafc30 | 466 | |
55a2c322 VM |
467 | return regno >= FIRST_PSEUDO_REGISTER || REGNO_OK_FOR_INDEX_P (regno); |
468 | } | |
469 | ||
470 | /* A version of regno_ok_for_base_p for use here, when all pseudos | |
471 | should count as OK. Arguments as for regno_ok_for_base_p. */ | |
472 | static inline bool | |
473 | ok_for_base_p_nonstrict (rtx reg, enum machine_mode mode, addr_space_t as, | |
474 | enum rtx_code outer_code, enum rtx_code index_code) | |
475 | { | |
476 | unsigned regno = REGNO (reg); | |
477 | ||
478 | if (regno >= FIRST_PSEUDO_REGISTER) | |
479 | return true; | |
480 | return ok_for_base_p_1 (regno, mode, as, outer_code, index_code); | |
481 | } | |
482 | ||
55a2c322 VM |
483 | \f |
484 | ||
485 | /* The page contains major code to choose the current insn alternative | |
486 | and generate reloads for it. */ | |
487 | ||
488 | /* Return the offset from REGNO of the least significant register | |
489 | in (reg:MODE REGNO). | |
490 | ||
491 | This function is used to tell whether two registers satisfy | |
492 | a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if: | |
493 | ||
494 | REGNO1 + lra_constraint_offset (REGNO1, MODE1) | |
495 | == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */ | |
496 | int | |
497 | lra_constraint_offset (int regno, enum machine_mode mode) | |
498 | { | |
499 | lra_assert (regno < FIRST_PSEUDO_REGISTER); | |
500 | if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (mode) > UNITS_PER_WORD | |
501 | && SCALAR_INT_MODE_P (mode)) | |
502 | return hard_regno_nregs[regno][mode] - 1; | |
503 | return 0; | |
504 | } | |
505 | ||
506 | /* Like rtx_equal_p except that it allows a REG and a SUBREG to match | |
507 | if they are the same hard reg, and has special hacks for | |
508 | auto-increment and auto-decrement. This is specifically intended for | |
509 | process_alt_operands to use in determining whether two operands | |
510 | match. X is the operand whose number is the lower of the two. | |
511 | ||
512 | It is supposed that X is the output operand and Y is the input | |
513 | operand. Y_HARD_REGNO is the final hard regno of register Y or | |
514 | register in subreg Y as we know it now. Otherwise, it is a | |
515 | negative value. */ | |
516 | static bool | |
517 | operands_match_p (rtx x, rtx y, int y_hard_regno) | |
518 | { | |
519 | int i; | |
520 | RTX_CODE code = GET_CODE (x); | |
521 | const char *fmt; | |
522 | ||
523 | if (x == y) | |
524 | return true; | |
525 | if ((code == REG || (code == SUBREG && REG_P (SUBREG_REG (x)))) | |
526 | && (REG_P (y) || (GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y))))) | |
527 | { | |
528 | int j; | |
f4eafc30 | 529 | |
55a2c322 VM |
530 | i = get_hard_regno (x); |
531 | if (i < 0) | |
532 | goto slow; | |
533 | ||
534 | if ((j = y_hard_regno) < 0) | |
535 | goto slow; | |
536 | ||
537 | i += lra_constraint_offset (i, GET_MODE (x)); | |
538 | j += lra_constraint_offset (j, GET_MODE (y)); | |
539 | ||
540 | return i == j; | |
541 | } | |
542 | ||
543 | /* If two operands must match, because they are really a single | |
544 | operand of an assembler insn, then two post-increments are invalid | |
545 | because the assembler insn would increment only once. On the | |
546 | other hand, a post-increment matches ordinary indexing if the | |
547 | post-increment is the output operand. */ | |
548 | if (code == POST_DEC || code == POST_INC || code == POST_MODIFY) | |
549 | return operands_match_p (XEXP (x, 0), y, y_hard_regno); | |
550 | ||
551 | /* Two pre-increments are invalid because the assembler insn would | |
552 | increment only once. On the other hand, a pre-increment matches | |
553 | ordinary indexing if the pre-increment is the input operand. */ | |
554 | if (GET_CODE (y) == PRE_DEC || GET_CODE (y) == PRE_INC | |
555 | || GET_CODE (y) == PRE_MODIFY) | |
556 | return operands_match_p (x, XEXP (y, 0), -1); | |
f4eafc30 | 557 | |
55a2c322 VM |
558 | slow: |
559 | ||
560 | if (code == REG && GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y)) | |
561 | && x == SUBREG_REG (y)) | |
562 | return true; | |
563 | if (GET_CODE (y) == REG && code == SUBREG && REG_P (SUBREG_REG (x)) | |
564 | && SUBREG_REG (x) == y) | |
565 | return true; | |
566 | ||
567 | /* Now we have disposed of all the cases in which different rtx | |
568 | codes can match. */ | |
569 | if (code != GET_CODE (y)) | |
570 | return false; | |
571 | ||
572 | /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */ | |
573 | if (GET_MODE (x) != GET_MODE (y)) | |
574 | return false; | |
575 | ||
576 | switch (code) | |
577 | { | |
578 | CASE_CONST_UNIQUE: | |
579 | return false; | |
580 | ||
581 | case LABEL_REF: | |
582 | return XEXP (x, 0) == XEXP (y, 0); | |
583 | case SYMBOL_REF: | |
584 | return XSTR (x, 0) == XSTR (y, 0); | |
585 | ||
586 | default: | |
587 | break; | |
588 | } | |
589 | ||
590 | /* Compare the elements. If any pair of corresponding elements fail | |
591 | to match, return false for the whole things. */ | |
592 | ||
593 | fmt = GET_RTX_FORMAT (code); | |
594 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
595 | { | |
596 | int val, j; | |
597 | switch (fmt[i]) | |
598 | { | |
599 | case 'w': | |
600 | if (XWINT (x, i) != XWINT (y, i)) | |
601 | return false; | |
602 | break; | |
603 | ||
604 | case 'i': | |
605 | if (XINT (x, i) != XINT (y, i)) | |
606 | return false; | |
607 | break; | |
608 | ||
609 | case 'e': | |
610 | val = operands_match_p (XEXP (x, i), XEXP (y, i), -1); | |
611 | if (val == 0) | |
612 | return false; | |
613 | break; | |
614 | ||
615 | case '0': | |
616 | break; | |
617 | ||
618 | case 'E': | |
619 | if (XVECLEN (x, i) != XVECLEN (y, i)) | |
620 | return false; | |
621 | for (j = XVECLEN (x, i) - 1; j >= 0; --j) | |
622 | { | |
623 | val = operands_match_p (XVECEXP (x, i, j), XVECEXP (y, i, j), -1); | |
624 | if (val == 0) | |
625 | return false; | |
626 | } | |
627 | break; | |
628 | ||
629 | /* It is believed that rtx's at this level will never | |
630 | contain anything but integers and other rtx's, except for | |
631 | within LABEL_REFs and SYMBOL_REFs. */ | |
632 | default: | |
633 | gcc_unreachable (); | |
634 | } | |
635 | } | |
636 | return true; | |
637 | } | |
638 | ||
639 | /* True if X is a constant that can be forced into the constant pool. | |
640 | MODE is the mode of the operand, or VOIDmode if not known. */ | |
641 | #define CONST_POOL_OK_P(MODE, X) \ | |
642 | ((MODE) != VOIDmode \ | |
643 | && CONSTANT_P (X) \ | |
644 | && GET_CODE (X) != HIGH \ | |
645 | && !targetm.cannot_force_const_mem (MODE, X)) | |
646 | ||
647 | /* True if C is a non-empty register class that has too few registers | |
648 | to be safely used as a reload target class. */ | |
649 | #define SMALL_REGISTER_CLASS_P(C) \ | |
650 | (reg_class_size [(C)] == 1 \ | |
651 | || (reg_class_size [(C)] >= 1 && targetm.class_likely_spilled_p (C))) | |
652 | ||
653 | /* If REG is a reload pseudo, try to make its class satisfying CL. */ | |
654 | static void | |
655 | narrow_reload_pseudo_class (rtx reg, enum reg_class cl) | |
656 | { | |
657 | enum reg_class rclass; | |
658 | ||
659 | /* Do not make more accurate class from reloads generated. They are | |
660 | mostly moves with a lot of constraints. Making more accurate | |
661 | class may results in very narrow class and impossibility of find | |
662 | registers for several reloads of one insn. */ | |
663 | if (INSN_UID (curr_insn) >= new_insn_uid_start) | |
664 | return; | |
665 | if (GET_CODE (reg) == SUBREG) | |
666 | reg = SUBREG_REG (reg); | |
667 | if (! REG_P (reg) || (int) REGNO (reg) < new_regno_start) | |
668 | return; | |
669 | if (in_class_p (reg, cl, &rclass) && rclass != cl) | |
670 | change_class (REGNO (reg), rclass, " Change", true); | |
671 | } | |
672 | ||
673 | /* Generate reloads for matching OUT and INS (array of input operand | |
674 | numbers with end marker -1) with reg class GOAL_CLASS. Add input | |
511dcace VM |
675 | and output reloads correspondingly to the lists *BEFORE and *AFTER. |
676 | OUT might be negative. In this case we generate input reloads for | |
677 | matched input operands INS. */ | |
55a2c322 VM |
678 | static void |
679 | match_reload (signed char out, signed char *ins, enum reg_class goal_class, | |
680 | rtx *before, rtx *after) | |
681 | { | |
682 | int i, in; | |
c5cd5a7e | 683 | rtx new_in_reg, new_out_reg, reg, clobber; |
55a2c322 VM |
684 | enum machine_mode inmode, outmode; |
685 | rtx in_rtx = *curr_id->operand_loc[ins[0]]; | |
511dcace | 686 | rtx out_rtx = out < 0 ? in_rtx : *curr_id->operand_loc[out]; |
55a2c322 | 687 | |
55a2c322 | 688 | inmode = curr_operand_mode[ins[0]]; |
511dcace | 689 | outmode = out < 0 ? inmode : curr_operand_mode[out]; |
55a2c322 VM |
690 | push_to_sequence (*before); |
691 | if (inmode != outmode) | |
692 | { | |
693 | if (GET_MODE_SIZE (inmode) > GET_MODE_SIZE (outmode)) | |
694 | { | |
695 | reg = new_in_reg | |
696 | = lra_create_new_reg_with_unique_value (inmode, in_rtx, | |
697 | goal_class, ""); | |
698 | if (SCALAR_INT_MODE_P (inmode)) | |
699 | new_out_reg = gen_lowpart_SUBREG (outmode, reg); | |
700 | else | |
701 | new_out_reg = gen_rtx_SUBREG (outmode, reg, 0); | |
2c62cbaa | 702 | LRA_SUBREG_P (new_out_reg) = 1; |
350c0fe7 | 703 | /* If the input reg is dying here, we can use the same hard |
f681cf95 VM |
704 | register for REG and IN_RTX. We do it only for original |
705 | pseudos as reload pseudos can die although original | |
706 | pseudos still live where reload pseudos dies. */ | |
707 | if (REG_P (in_rtx) && (int) REGNO (in_rtx) < lra_new_regno_start | |
350c0fe7 | 708 | && find_regno_note (curr_insn, REG_DEAD, REGNO (in_rtx))) |
d70a81dd | 709 | lra_assign_reg_val (REGNO (in_rtx), REGNO (reg)); |
55a2c322 VM |
710 | } |
711 | else | |
712 | { | |
713 | reg = new_out_reg | |
714 | = lra_create_new_reg_with_unique_value (outmode, out_rtx, | |
715 | goal_class, ""); | |
716 | if (SCALAR_INT_MODE_P (outmode)) | |
717 | new_in_reg = gen_lowpart_SUBREG (inmode, reg); | |
718 | else | |
719 | new_in_reg = gen_rtx_SUBREG (inmode, reg, 0); | |
720 | /* NEW_IN_REG is non-paradoxical subreg. We don't want | |
721 | NEW_OUT_REG living above. We add clobber clause for | |
c5cd5a7e VM |
722 | this. This is just a temporary clobber. We can remove |
723 | it at the end of LRA work. */ | |
724 | clobber = emit_clobber (new_out_reg); | |
725 | LRA_TEMP_CLOBBER_P (PATTERN (clobber)) = 1; | |
2c62cbaa | 726 | LRA_SUBREG_P (new_in_reg) = 1; |
350c0fe7 VM |
727 | if (GET_CODE (in_rtx) == SUBREG) |
728 | { | |
729 | rtx subreg_reg = SUBREG_REG (in_rtx); | |
730 | ||
731 | /* If SUBREG_REG is dying here and sub-registers IN_RTX | |
732 | and NEW_IN_REG are similar, we can use the same hard | |
733 | register for REG and SUBREG_REG. */ | |
f681cf95 VM |
734 | if (REG_P (subreg_reg) |
735 | && (int) REGNO (subreg_reg) < lra_new_regno_start | |
736 | && GET_MODE (subreg_reg) == outmode | |
350c0fe7 VM |
737 | && SUBREG_BYTE (in_rtx) == SUBREG_BYTE (new_in_reg) |
738 | && find_regno_note (curr_insn, REG_DEAD, REGNO (subreg_reg))) | |
d70a81dd | 739 | lra_assign_reg_val (REGNO (subreg_reg), REGNO (reg)); |
350c0fe7 | 740 | } |
55a2c322 VM |
741 | } |
742 | } | |
743 | else | |
744 | { | |
745 | /* Pseudos have values -- see comments for lra_reg_info. | |
746 | Different pseudos with the same value do not conflict even if | |
747 | they live in the same place. When we create a pseudo we | |
748 | assign value of original pseudo (if any) from which we | |
749 | created the new pseudo. If we create the pseudo from the | |
750 | input pseudo, the new pseudo will no conflict with the input | |
751 | pseudo which is wrong when the input pseudo lives after the | |
752 | insn and as the new pseudo value is changed by the insn | |
753 | output. Therefore we create the new pseudo from the output. | |
f4eafc30 | 754 | |
55a2c322 VM |
755 | We cannot reuse the current output register because we might |
756 | have a situation like "a <- a op b", where the constraints | |
757 | force the second input operand ("b") to match the output | |
758 | operand ("a"). "b" must then be copied into a new register | |
759 | so that it doesn't clobber the current value of "a". */ | |
f4eafc30 | 760 | |
55a2c322 VM |
761 | new_in_reg = new_out_reg |
762 | = lra_create_new_reg_with_unique_value (outmode, out_rtx, | |
763 | goal_class, ""); | |
764 | } | |
511dcace VM |
765 | /* In operand can be got from transformations before processing insn |
766 | constraints. One example of such transformations is subreg | |
767 | reloading (see function simplify_operand_subreg). The new | |
768 | pseudos created by the transformations might have inaccurate | |
55a2c322 VM |
769 | class (ALL_REGS) and we should make their classes more |
770 | accurate. */ | |
771 | narrow_reload_pseudo_class (in_rtx, goal_class); | |
55a2c322 VM |
772 | lra_emit_move (copy_rtx (new_in_reg), in_rtx); |
773 | *before = get_insns (); | |
774 | end_sequence (); | |
775 | for (i = 0; (in = ins[i]) >= 0; i++) | |
776 | { | |
777 | lra_assert | |
778 | (GET_MODE (*curr_id->operand_loc[in]) == VOIDmode | |
779 | || GET_MODE (new_in_reg) == GET_MODE (*curr_id->operand_loc[in])); | |
780 | *curr_id->operand_loc[in] = new_in_reg; | |
781 | } | |
782 | lra_update_dups (curr_id, ins); | |
511dcace VM |
783 | if (out < 0) |
784 | return; | |
785 | /* See a comment for the input operand above. */ | |
786 | narrow_reload_pseudo_class (out_rtx, goal_class); | |
55a2c322 VM |
787 | if (find_reg_note (curr_insn, REG_UNUSED, out_rtx) == NULL_RTX) |
788 | { | |
789 | start_sequence (); | |
790 | lra_emit_move (out_rtx, copy_rtx (new_out_reg)); | |
791 | emit_insn (*after); | |
792 | *after = get_insns (); | |
793 | end_sequence (); | |
794 | } | |
795 | *curr_id->operand_loc[out] = new_out_reg; | |
796 | lra_update_dup (curr_id, out); | |
797 | } | |
798 | ||
799 | /* Return register class which is union of all reg classes in insn | |
800 | constraint alternative string starting with P. */ | |
801 | static enum reg_class | |
802 | reg_class_from_constraints (const char *p) | |
803 | { | |
804 | int c, len; | |
805 | enum reg_class op_class = NO_REGS; | |
806 | ||
807 | do | |
808 | switch ((c = *p, len = CONSTRAINT_LEN (c, p)), c) | |
809 | { | |
810 | case '#': | |
811 | case ',': | |
812 | return op_class; | |
813 | ||
814 | case 'p': | |
815 | op_class = (reg_class_subunion | |
816 | [op_class][base_reg_class (VOIDmode, ADDR_SPACE_GENERIC, | |
817 | ADDRESS, SCRATCH)]); | |
818 | break; | |
f4eafc30 | 819 | |
55a2c322 VM |
820 | case 'g': |
821 | case 'r': | |
822 | op_class = reg_class_subunion[op_class][GENERAL_REGS]; | |
823 | break; | |
f4eafc30 | 824 | |
55a2c322 VM |
825 | default: |
826 | if (REG_CLASS_FROM_CONSTRAINT (c, p) == NO_REGS) | |
827 | { | |
828 | #ifdef EXTRA_CONSTRAINT_STR | |
829 | if (EXTRA_ADDRESS_CONSTRAINT (c, p)) | |
830 | op_class | |
831 | = (reg_class_subunion | |
832 | [op_class][base_reg_class (VOIDmode, ADDR_SPACE_GENERIC, | |
833 | ADDRESS, SCRATCH)]); | |
834 | #endif | |
835 | break; | |
836 | } | |
f4eafc30 | 837 | |
55a2c322 VM |
838 | op_class |
839 | = reg_class_subunion[op_class][REG_CLASS_FROM_CONSTRAINT (c, p)]; | |
840 | break; | |
841 | } | |
842 | while ((p += len), c); | |
843 | return op_class; | |
844 | } | |
845 | ||
846 | /* If OP is a register, return the class of the register as per | |
847 | get_reg_class, otherwise return NO_REGS. */ | |
848 | static inline enum reg_class | |
849 | get_op_class (rtx op) | |
850 | { | |
851 | return REG_P (op) ? get_reg_class (REGNO (op)) : NO_REGS; | |
852 | } | |
853 | ||
854 | /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo | |
855 | otherwise. If modes of MEM_PSEUDO and VAL are different, use | |
856 | SUBREG for VAL to make them equal. */ | |
857 | static rtx | |
858 | emit_spill_move (bool to_p, rtx mem_pseudo, rtx val) | |
859 | { | |
860 | if (GET_MODE (mem_pseudo) != GET_MODE (val)) | |
2c62cbaa | 861 | { |
1ccd4874 VM |
862 | lra_assert (GET_MODE_SIZE (GET_MODE (mem_pseudo)) |
863 | >= GET_MODE_SIZE (GET_MODE (val))); | |
864 | if (! MEM_P (val)) | |
865 | { | |
866 | val = gen_rtx_SUBREG (GET_MODE (mem_pseudo), | |
867 | GET_CODE (val) == SUBREG ? SUBREG_REG (val) : val, | |
868 | 0); | |
869 | LRA_SUBREG_P (val) = 1; | |
870 | } | |
871 | else | |
872 | { | |
873 | mem_pseudo = gen_lowpart_SUBREG (GET_MODE (val), mem_pseudo); | |
874 | LRA_SUBREG_P (mem_pseudo) = 1; | |
875 | } | |
2c62cbaa | 876 | } |
55a2c322 | 877 | return (to_p |
0ae24cc8 VM |
878 | ? gen_move_insn (mem_pseudo, val) |
879 | : gen_move_insn (val, mem_pseudo)); | |
55a2c322 VM |
880 | } |
881 | ||
882 | /* Process a special case insn (register move), return true if we | |
2c62cbaa VM |
883 | don't need to process it anymore. INSN should be a single set |
884 | insn. Set up that RTL was changed through CHANGE_P and macro | |
885 | SECONDARY_MEMORY_NEEDED says to use secondary memory through | |
886 | SEC_MEM_P. */ | |
55a2c322 | 887 | static bool |
2c62cbaa | 888 | check_and_process_move (bool *change_p, bool *sec_mem_p ATTRIBUTE_UNUSED) |
55a2c322 VM |
889 | { |
890 | int sregno, dregno; | |
2c62cbaa | 891 | rtx dest, src, dreg, sreg, old_sreg, new_reg, before, scratch_reg; |
55a2c322 VM |
892 | enum reg_class dclass, sclass, secondary_class; |
893 | enum machine_mode sreg_mode; | |
894 | secondary_reload_info sri; | |
895 | ||
2c62cbaa VM |
896 | lra_assert (curr_insn_set != NULL_RTX); |
897 | dreg = dest = SET_DEST (curr_insn_set); | |
898 | sreg = src = SET_SRC (curr_insn_set); | |
55a2c322 VM |
899 | if (GET_CODE (dest) == SUBREG) |
900 | dreg = SUBREG_REG (dest); | |
901 | if (GET_CODE (src) == SUBREG) | |
902 | sreg = SUBREG_REG (src); | |
1ccd4874 | 903 | if (! (REG_P (dreg) || MEM_P (dreg)) || ! (REG_P (sreg) || MEM_P (sreg))) |
55a2c322 VM |
904 | return false; |
905 | sclass = dclass = NO_REGS; | |
55a2c322 VM |
906 | if (REG_P (dreg)) |
907 | dclass = get_reg_class (REGNO (dreg)); | |
908 | if (dclass == ALL_REGS) | |
909 | /* ALL_REGS is used for new pseudos created by transformations | |
910 | like reload of SUBREG_REG (see function | |
911 | simplify_operand_subreg). We don't know their class yet. We | |
912 | should figure out the class from processing the insn | |
913 | constraints not in this fast path function. Even if ALL_REGS | |
914 | were a right class for the pseudo, secondary_... hooks usually | |
915 | are not define for ALL_REGS. */ | |
916 | return false; | |
917 | sreg_mode = GET_MODE (sreg); | |
918 | old_sreg = sreg; | |
55a2c322 VM |
919 | if (REG_P (sreg)) |
920 | sclass = get_reg_class (REGNO (sreg)); | |
921 | if (sclass == ALL_REGS) | |
922 | /* See comments above. */ | |
923 | return false; | |
1ccd4874 VM |
924 | if (sclass == NO_REGS && dclass == NO_REGS) |
925 | return false; | |
55a2c322 | 926 | #ifdef SECONDARY_MEMORY_NEEDED |
1ccd4874 VM |
927 | if (SECONDARY_MEMORY_NEEDED (sclass, dclass, GET_MODE (src)) |
928 | #ifdef SECONDARY_MEMORY_NEEDED_MODE | |
929 | && ((sclass != NO_REGS && dclass != NO_REGS) | |
930 | || GET_MODE (src) != SECONDARY_MEMORY_NEEDED_MODE (GET_MODE (src))) | |
931 | #endif | |
932 | ) | |
55a2c322 VM |
933 | { |
934 | *sec_mem_p = true; | |
935 | return false; | |
936 | } | |
937 | #endif | |
1ccd4874 VM |
938 | if (! REG_P (dreg) || ! REG_P (sreg)) |
939 | return false; | |
55a2c322 VM |
940 | sri.prev_sri = NULL; |
941 | sri.icode = CODE_FOR_nothing; | |
942 | sri.extra_cost = 0; | |
943 | secondary_class = NO_REGS; | |
944 | /* Set up hard register for a reload pseudo for hook | |
945 | secondary_reload because some targets just ignore unassigned | |
946 | pseudos in the hook. */ | |
947 | if (dclass != NO_REGS && lra_get_regno_hard_regno (REGNO (dreg)) < 0) | |
948 | { | |
949 | dregno = REGNO (dreg); | |
950 | reg_renumber[dregno] = ira_class_hard_regs[dclass][0]; | |
951 | } | |
952 | else | |
953 | dregno = -1; | |
954 | if (sclass != NO_REGS && lra_get_regno_hard_regno (REGNO (sreg)) < 0) | |
955 | { | |
956 | sregno = REGNO (sreg); | |
957 | reg_renumber[sregno] = ira_class_hard_regs[sclass][0]; | |
958 | } | |
959 | else | |
960 | sregno = -1; | |
961 | if (sclass != NO_REGS) | |
962 | secondary_class | |
963 | = (enum reg_class) targetm.secondary_reload (false, dest, | |
964 | (reg_class_t) sclass, | |
965 | GET_MODE (src), &sri); | |
966 | if (sclass == NO_REGS | |
967 | || ((secondary_class != NO_REGS || sri.icode != CODE_FOR_nothing) | |
968 | && dclass != NO_REGS)) | |
969 | { | |
55a2c322 VM |
970 | enum reg_class old_sclass = secondary_class; |
971 | secondary_reload_info old_sri = sri; | |
55a2c322 VM |
972 | |
973 | sri.prev_sri = NULL; | |
974 | sri.icode = CODE_FOR_nothing; | |
975 | sri.extra_cost = 0; | |
976 | secondary_class | |
977 | = (enum reg_class) targetm.secondary_reload (true, sreg, | |
978 | (reg_class_t) dclass, | |
979 | sreg_mode, &sri); | |
980 | /* Check the target hook consistency. */ | |
981 | lra_assert | |
982 | ((secondary_class == NO_REGS && sri.icode == CODE_FOR_nothing) | |
983 | || (old_sclass == NO_REGS && old_sri.icode == CODE_FOR_nothing) | |
984 | || (secondary_class == old_sclass && sri.icode == old_sri.icode)); | |
985 | } | |
986 | if (sregno >= 0) | |
987 | reg_renumber [sregno] = -1; | |
988 | if (dregno >= 0) | |
989 | reg_renumber [dregno] = -1; | |
990 | if (secondary_class == NO_REGS && sri.icode == CODE_FOR_nothing) | |
991 | return false; | |
992 | *change_p = true; | |
993 | new_reg = NULL_RTX; | |
994 | if (secondary_class != NO_REGS) | |
995 | new_reg = lra_create_new_reg_with_unique_value (sreg_mode, NULL_RTX, | |
996 | secondary_class, | |
997 | "secondary"); | |
998 | start_sequence (); | |
999 | if (old_sreg != sreg) | |
1000 | sreg = copy_rtx (sreg); | |
1001 | if (sri.icode == CODE_FOR_nothing) | |
1002 | lra_emit_move (new_reg, sreg); | |
1003 | else | |
1004 | { | |
1005 | enum reg_class scratch_class; | |
1006 | ||
1007 | scratch_class = (reg_class_from_constraints | |
1008 | (insn_data[sri.icode].operand[2].constraint)); | |
1009 | scratch_reg = (lra_create_new_reg_with_unique_value | |
1010 | (insn_data[sri.icode].operand[2].mode, NULL_RTX, | |
1011 | scratch_class, "scratch")); | |
1012 | emit_insn (GEN_FCN (sri.icode) (new_reg != NULL_RTX ? new_reg : dest, | |
1013 | sreg, scratch_reg)); | |
1014 | } | |
1015 | before = get_insns (); | |
1016 | end_sequence (); | |
1017 | lra_process_new_insns (curr_insn, before, NULL_RTX, "Inserting the move"); | |
1018 | if (new_reg != NULL_RTX) | |
1019 | { | |
1020 | if (GET_CODE (src) == SUBREG) | |
1021 | SUBREG_REG (src) = new_reg; | |
1022 | else | |
2c62cbaa | 1023 | SET_SRC (curr_insn_set) = new_reg; |
55a2c322 VM |
1024 | } |
1025 | else | |
1026 | { | |
1027 | if (lra_dump_file != NULL) | |
1028 | { | |
1029 | fprintf (lra_dump_file, "Deleting move %u\n", INSN_UID (curr_insn)); | |
cfbeaedf | 1030 | dump_insn_slim (lra_dump_file, curr_insn); |
55a2c322 VM |
1031 | } |
1032 | lra_set_insn_deleted (curr_insn); | |
1033 | return true; | |
1034 | } | |
1035 | return false; | |
1036 | } | |
1037 | ||
1038 | /* The following data describe the result of process_alt_operands. | |
1039 | The data are used in curr_insn_transform to generate reloads. */ | |
1040 | ||
1041 | /* The chosen reg classes which should be used for the corresponding | |
1042 | operands. */ | |
1043 | static enum reg_class goal_alt[MAX_RECOG_OPERANDS]; | |
1044 | /* True if the operand should be the same as another operand and that | |
1045 | other operand does not need a reload. */ | |
1046 | static bool goal_alt_match_win[MAX_RECOG_OPERANDS]; | |
1047 | /* True if the operand does not need a reload. */ | |
1048 | static bool goal_alt_win[MAX_RECOG_OPERANDS]; | |
1049 | /* True if the operand can be offsetable memory. */ | |
1050 | static bool goal_alt_offmemok[MAX_RECOG_OPERANDS]; | |
1051 | /* The number of an operand to which given operand can be matched to. */ | |
1052 | static int goal_alt_matches[MAX_RECOG_OPERANDS]; | |
1053 | /* The number of elements in the following array. */ | |
1054 | static int goal_alt_dont_inherit_ops_num; | |
1055 | /* Numbers of operands whose reload pseudos should not be inherited. */ | |
1056 | static int goal_alt_dont_inherit_ops[MAX_RECOG_OPERANDS]; | |
1057 | /* True if the insn commutative operands should be swapped. */ | |
1058 | static bool goal_alt_swapped; | |
1059 | /* The chosen insn alternative. */ | |
1060 | static int goal_alt_number; | |
1061 | ||
1062 | /* The following five variables are used to choose the best insn | |
1063 | alternative. They reflect final characteristics of the best | |
1064 | alternative. */ | |
1065 | ||
1066 | /* Number of necessary reloads and overall cost reflecting the | |
1067 | previous value and other unpleasantness of the best alternative. */ | |
1068 | static int best_losers, best_overall; | |
55a2c322 VM |
1069 | /* Overall number hard registers used for reloads. For example, on |
1070 | some targets we need 2 general registers to reload DFmode and only | |
1071 | one floating point register. */ | |
1072 | static int best_reload_nregs; | |
1073 | /* Overall number reflecting distances of previous reloading the same | |
1074 | value. The distances are counted from the current BB start. It is | |
1075 | used to improve inheritance chances. */ | |
1076 | static int best_reload_sum; | |
1077 | ||
1078 | /* True if the current insn should have no correspondingly input or | |
1079 | output reloads. */ | |
1080 | static bool no_input_reloads_p, no_output_reloads_p; | |
1081 | ||
1082 | /* True if we swapped the commutative operands in the current | |
1083 | insn. */ | |
1084 | static int curr_swapped; | |
1085 | ||
1086 | /* Arrange for address element *LOC to be a register of class CL. | |
1087 | Add any input reloads to list BEFORE. AFTER is nonnull if *LOC is an | |
1088 | automodified value; handle that case by adding the required output | |
1089 | reloads to list AFTER. Return true if the RTL was changed. */ | |
1090 | static bool | |
1091 | process_addr_reg (rtx *loc, rtx *before, rtx *after, enum reg_class cl) | |
1092 | { | |
1093 | int regno; | |
1094 | enum reg_class rclass, new_class; | |
277f65de | 1095 | rtx reg; |
55a2c322 VM |
1096 | rtx new_reg; |
1097 | enum machine_mode mode; | |
1098 | bool before_p = false; | |
1099 | ||
277f65de RS |
1100 | loc = strip_subreg (loc); |
1101 | reg = *loc; | |
55a2c322 VM |
1102 | mode = GET_MODE (reg); |
1103 | if (! REG_P (reg)) | |
1104 | { | |
1105 | /* Always reload memory in an address even if the target supports | |
1106 | such addresses. */ | |
1107 | new_reg = lra_create_new_reg_with_unique_value (mode, reg, cl, "address"); | |
1108 | before_p = true; | |
1109 | } | |
1110 | else | |
1111 | { | |
1112 | regno = REGNO (reg); | |
1113 | rclass = get_reg_class (regno); | |
1114 | if ((*loc = get_equiv_substitution (reg)) != reg) | |
1115 | { | |
1116 | if (lra_dump_file != NULL) | |
1117 | { | |
1118 | fprintf (lra_dump_file, | |
1119 | "Changing pseudo %d in address of insn %u on equiv ", | |
1120 | REGNO (reg), INSN_UID (curr_insn)); | |
cfbeaedf | 1121 | dump_value_slim (lra_dump_file, *loc, 1); |
55a2c322 VM |
1122 | fprintf (lra_dump_file, "\n"); |
1123 | } | |
1124 | *loc = copy_rtx (*loc); | |
1125 | } | |
1126 | if (*loc != reg || ! in_class_p (reg, cl, &new_class)) | |
1127 | { | |
1128 | reg = *loc; | |
1129 | if (get_reload_reg (after == NULL ? OP_IN : OP_INOUT, | |
1130 | mode, reg, cl, "address", &new_reg)) | |
1131 | before_p = true; | |
1132 | } | |
1133 | else if (new_class != NO_REGS && rclass != new_class) | |
1134 | { | |
1135 | change_class (regno, new_class, " Change", true); | |
1136 | return false; | |
1137 | } | |
1138 | else | |
1139 | return false; | |
1140 | } | |
1141 | if (before_p) | |
1142 | { | |
1143 | push_to_sequence (*before); | |
1144 | lra_emit_move (new_reg, reg); | |
1145 | *before = get_insns (); | |
1146 | end_sequence (); | |
1147 | } | |
1148 | *loc = new_reg; | |
1149 | if (after != NULL) | |
1150 | { | |
1151 | start_sequence (); | |
1152 | lra_emit_move (reg, new_reg); | |
1153 | emit_insn (*after); | |
1154 | *after = get_insns (); | |
1155 | end_sequence (); | |
1156 | } | |
1157 | return true; | |
1158 | } | |
1159 | ||
55a2c322 VM |
1160 | /* Make reloads for subreg in operand NOP with internal subreg mode |
1161 | REG_MODE, add new reloads for further processing. Return true if | |
1162 | any reload was generated. */ | |
1163 | static bool | |
1164 | simplify_operand_subreg (int nop, enum machine_mode reg_mode) | |
1165 | { | |
1166 | int hard_regno; | |
1167 | rtx before, after; | |
1168 | enum machine_mode mode; | |
1169 | rtx reg, new_reg; | |
1170 | rtx operand = *curr_id->operand_loc[nop]; | |
1171 | ||
1172 | before = after = NULL_RTX; | |
1173 | ||
1174 | if (GET_CODE (operand) != SUBREG) | |
1175 | return false; | |
f4eafc30 | 1176 | |
55a2c322 VM |
1177 | mode = GET_MODE (operand); |
1178 | reg = SUBREG_REG (operand); | |
1179 | /* If we change address for paradoxical subreg of memory, the | |
1180 | address might violate the necessary alignment or the access might | |
b28ece32 VM |
1181 | be slow. So take this into consideration. We should not worry |
1182 | about access beyond allocated memory for paradoxical memory | |
1183 | subregs as we don't substitute such equiv memory (see processing | |
1184 | equivalences in function lra_constraints) and because for spilled | |
1185 | pseudos we allocate stack memory enough for the biggest | |
1186 | corresponding paradoxical subreg. */ | |
55a2c322 | 1187 | if ((MEM_P (reg) |
08e931f3 | 1188 | && (! SLOW_UNALIGNED_ACCESS (mode, MEM_ALIGN (reg)) |
55a2c322 VM |
1189 | || MEM_ALIGN (reg) >= GET_MODE_ALIGNMENT (mode))) |
1190 | || (REG_P (reg) && REGNO (reg) < FIRST_PSEUDO_REGISTER)) | |
1191 | { | |
1192 | alter_subreg (curr_id->operand_loc[nop], false); | |
1193 | return true; | |
1194 | } | |
1195 | /* Put constant into memory when we have mixed modes. It generates | |
1196 | a better code in most cases as it does not need a secondary | |
1197 | reload memory. It also prevents LRA looping when LRA is using | |
1198 | secondary reload memory again and again. */ | |
1199 | if (CONSTANT_P (reg) && CONST_POOL_OK_P (reg_mode, reg) | |
1200 | && SCALAR_INT_MODE_P (reg_mode) != SCALAR_INT_MODE_P (mode)) | |
1201 | { | |
1202 | SUBREG_REG (operand) = force_const_mem (reg_mode, reg); | |
1203 | alter_subreg (curr_id->operand_loc[nop], false); | |
1204 | return true; | |
1205 | } | |
1206 | /* Force a reload of the SUBREG_REG if this is a constant or PLUS or | |
1207 | if there may be a problem accessing OPERAND in the outer | |
1208 | mode. */ | |
1209 | if ((REG_P (reg) | |
1210 | && REGNO (reg) >= FIRST_PSEUDO_REGISTER | |
1211 | && (hard_regno = lra_get_regno_hard_regno (REGNO (reg))) >= 0 | |
1212 | /* Don't reload paradoxical subregs because we could be looping | |
1213 | having repeatedly final regno out of hard regs range. */ | |
1214 | && (hard_regno_nregs[hard_regno][GET_MODE (reg)] | |
1215 | >= hard_regno_nregs[hard_regno][mode]) | |
1216 | && simplify_subreg_regno (hard_regno, GET_MODE (reg), | |
2c62cbaa VM |
1217 | SUBREG_BYTE (operand), mode) < 0 |
1218 | /* Don't reload subreg for matching reload. It is actually | |
1219 | valid subreg in LRA. */ | |
1220 | && ! LRA_SUBREG_P (operand)) | |
55a2c322 VM |
1221 | || CONSTANT_P (reg) || GET_CODE (reg) == PLUS || MEM_P (reg)) |
1222 | { | |
1223 | enum op_type type = curr_static_id->operand[nop].type; | |
1224 | /* The class will be defined later in curr_insn_transform. */ | |
1225 | enum reg_class rclass | |
1226 | = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS); | |
1227 | ||
25bb0bb5 VM |
1228 | if (get_reload_reg (curr_static_id->operand[nop].type, reg_mode, reg, |
1229 | rclass, "subreg reg", &new_reg)) | |
55a2c322 | 1230 | { |
25bb0bb5 VM |
1231 | bitmap_set_bit (&lra_optional_reload_pseudos, REGNO (new_reg)); |
1232 | if (type != OP_OUT | |
1233 | || GET_MODE_SIZE (GET_MODE (reg)) > GET_MODE_SIZE (mode)) | |
1234 | { | |
1235 | push_to_sequence (before); | |
1236 | lra_emit_move (new_reg, reg); | |
1237 | before = get_insns (); | |
1238 | end_sequence (); | |
1239 | } | |
1240 | if (type != OP_IN) | |
1241 | { | |
1242 | start_sequence (); | |
1243 | lra_emit_move (reg, new_reg); | |
1244 | emit_insn (after); | |
1245 | after = get_insns (); | |
1246 | end_sequence (); | |
1247 | } | |
55a2c322 VM |
1248 | } |
1249 | SUBREG_REG (operand) = new_reg; | |
1250 | lra_process_new_insns (curr_insn, before, after, | |
1251 | "Inserting subreg reload"); | |
1252 | return true; | |
1253 | } | |
1254 | return false; | |
1255 | } | |
1256 | ||
1257 | /* Return TRUE if X refers for a hard register from SET. */ | |
1258 | static bool | |
1259 | uses_hard_regs_p (rtx x, HARD_REG_SET set) | |
1260 | { | |
1261 | int i, j, x_hard_regno; | |
1262 | enum machine_mode mode; | |
1263 | const char *fmt; | |
1264 | enum rtx_code code; | |
1265 | ||
1266 | if (x == NULL_RTX) | |
1267 | return false; | |
1268 | code = GET_CODE (x); | |
1269 | mode = GET_MODE (x); | |
1270 | if (code == SUBREG) | |
1271 | { | |
1272 | x = SUBREG_REG (x); | |
1273 | code = GET_CODE (x); | |
1274 | if (GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (mode)) | |
1275 | mode = GET_MODE (x); | |
1276 | } | |
f4eafc30 | 1277 | |
55a2c322 VM |
1278 | if (REG_P (x)) |
1279 | { | |
1280 | x_hard_regno = get_hard_regno (x); | |
1281 | return (x_hard_regno >= 0 | |
1282 | && overlaps_hard_reg_set_p (set, mode, x_hard_regno)); | |
1283 | } | |
1284 | if (MEM_P (x)) | |
1285 | { | |
277f65de | 1286 | struct address_info ad; |
55a2c322 | 1287 | |
277f65de RS |
1288 | decompose_mem_address (&ad, x); |
1289 | if (ad.base_term != NULL && uses_hard_regs_p (*ad.base_term, set)) | |
1290 | return true; | |
1291 | if (ad.index_term != NULL && uses_hard_regs_p (*ad.index_term, set)) | |
1292 | return true; | |
55a2c322 VM |
1293 | } |
1294 | fmt = GET_RTX_FORMAT (code); | |
1295 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1296 | { | |
1297 | if (fmt[i] == 'e') | |
1298 | { | |
1299 | if (uses_hard_regs_p (XEXP (x, i), set)) | |
1300 | return true; | |
1301 | } | |
1302 | else if (fmt[i] == 'E') | |
1303 | { | |
1304 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
1305 | if (uses_hard_regs_p (XVECEXP (x, i, j), set)) | |
1306 | return true; | |
1307 | } | |
1308 | } | |
1309 | return false; | |
1310 | } | |
1311 | ||
1312 | /* Return true if OP is a spilled pseudo. */ | |
1313 | static inline bool | |
1314 | spilled_pseudo_p (rtx op) | |
1315 | { | |
1316 | return (REG_P (op) | |
1317 | && REGNO (op) >= FIRST_PSEUDO_REGISTER && in_mem_p (REGNO (op))); | |
1318 | } | |
1319 | ||
1320 | /* Return true if X is a general constant. */ | |
1321 | static inline bool | |
1322 | general_constant_p (rtx x) | |
1323 | { | |
1324 | return CONSTANT_P (x) && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (x)); | |
1325 | } | |
1326 | ||
2c62cbaa VM |
1327 | static bool |
1328 | reg_in_class_p (rtx reg, enum reg_class cl) | |
1329 | { | |
1330 | if (cl == NO_REGS) | |
1331 | return get_reg_class (REGNO (reg)) == NO_REGS; | |
1332 | return in_class_p (reg, cl, NULL); | |
1333 | } | |
1334 | ||
55a2c322 VM |
1335 | /* Major function to choose the current insn alternative and what |
1336 | operands should be reloaded and how. If ONLY_ALTERNATIVE is not | |
1337 | negative we should consider only this alternative. Return false if | |
1338 | we can not choose the alternative or find how to reload the | |
1339 | operands. */ | |
1340 | static bool | |
1341 | process_alt_operands (int only_alternative) | |
1342 | { | |
1343 | bool ok_p = false; | |
36ff9dfb | 1344 | int nop, overall, nalt; |
55a2c322 VM |
1345 | int n_alternatives = curr_static_id->n_alternatives; |
1346 | int n_operands = curr_static_id->n_operands; | |
1347 | /* LOSERS counts the operands that don't fit this alternative and | |
1348 | would require loading. */ | |
1349 | int losers; | |
1350 | /* REJECT is a count of how undesirable this alternative says it is | |
1351 | if any reloading is required. If the alternative matches exactly | |
1352 | then REJECT is ignored, but otherwise it gets this much counted | |
1353 | against it in addition to the reloading needed. */ | |
1354 | int reject; | |
1355 | /* The number of elements in the following array. */ | |
1356 | int early_clobbered_regs_num; | |
1357 | /* Numbers of operands which are early clobber registers. */ | |
1358 | int early_clobbered_nops[MAX_RECOG_OPERANDS]; | |
1359 | enum reg_class curr_alt[MAX_RECOG_OPERANDS]; | |
1360 | HARD_REG_SET curr_alt_set[MAX_RECOG_OPERANDS]; | |
1361 | bool curr_alt_match_win[MAX_RECOG_OPERANDS]; | |
1362 | bool curr_alt_win[MAX_RECOG_OPERANDS]; | |
1363 | bool curr_alt_offmemok[MAX_RECOG_OPERANDS]; | |
1364 | int curr_alt_matches[MAX_RECOG_OPERANDS]; | |
1365 | /* The number of elements in the following array. */ | |
1366 | int curr_alt_dont_inherit_ops_num; | |
1367 | /* Numbers of operands whose reload pseudos should not be inherited. */ | |
1368 | int curr_alt_dont_inherit_ops[MAX_RECOG_OPERANDS]; | |
1369 | rtx op; | |
1370 | /* The register when the operand is a subreg of register, otherwise the | |
1371 | operand itself. */ | |
1372 | rtx no_subreg_reg_operand[MAX_RECOG_OPERANDS]; | |
1373 | /* The register if the operand is a register or subreg of register, | |
1374 | otherwise NULL. */ | |
1375 | rtx operand_reg[MAX_RECOG_OPERANDS]; | |
1376 | int hard_regno[MAX_RECOG_OPERANDS]; | |
1377 | enum machine_mode biggest_mode[MAX_RECOG_OPERANDS]; | |
1378 | int reload_nregs, reload_sum; | |
1379 | bool costly_p; | |
1380 | enum reg_class cl; | |
1381 | ||
1382 | /* Calculate some data common for all alternatives to speed up the | |
1383 | function. */ | |
1384 | for (nop = 0; nop < n_operands; nop++) | |
1385 | { | |
1386 | op = no_subreg_reg_operand[nop] = *curr_id->operand_loc[nop]; | |
1387 | /* The real hard regno of the operand after the allocation. */ | |
1388 | hard_regno[nop] = get_hard_regno (op); | |
f4eafc30 | 1389 | |
55a2c322 VM |
1390 | operand_reg[nop] = op; |
1391 | biggest_mode[nop] = GET_MODE (operand_reg[nop]); | |
1392 | if (GET_CODE (operand_reg[nop]) == SUBREG) | |
1393 | { | |
1394 | operand_reg[nop] = SUBREG_REG (operand_reg[nop]); | |
1395 | if (GET_MODE_SIZE (biggest_mode[nop]) | |
1396 | < GET_MODE_SIZE (GET_MODE (operand_reg[nop]))) | |
1397 | biggest_mode[nop] = GET_MODE (operand_reg[nop]); | |
1398 | } | |
1399 | if (REG_P (operand_reg[nop])) | |
1400 | no_subreg_reg_operand[nop] = operand_reg[nop]; | |
1401 | else | |
1402 | operand_reg[nop] = NULL_RTX; | |
1403 | } | |
1404 | ||
1405 | /* The constraints are made of several alternatives. Each operand's | |
1406 | constraint looks like foo,bar,... with commas separating the | |
1407 | alternatives. The first alternatives for all operands go | |
1408 | together, the second alternatives go together, etc. | |
1409 | ||
1410 | First loop over alternatives. */ | |
1411 | for (nalt = 0; nalt < n_alternatives; nalt++) | |
1412 | { | |
1413 | /* Loop over operands for one constraint alternative. */ | |
2c62cbaa | 1414 | #if HAVE_ATTR_enabled |
55a2c322 VM |
1415 | if (curr_id->alternative_enabled_p != NULL |
1416 | && ! curr_id->alternative_enabled_p[nalt]) | |
1417 | continue; | |
1418 | #endif | |
1419 | ||
1420 | if (only_alternative >= 0 && nalt != only_alternative) | |
1421 | continue; | |
1422 | ||
36ff9dfb | 1423 | |
55a2c322 VM |
1424 | overall = losers = reject = reload_nregs = reload_sum = 0; |
1425 | for (nop = 0; nop < n_operands; nop++) | |
1426 | reject += (curr_static_id | |
1427 | ->operand_alternative[nalt * n_operands + nop].reject); | |
1428 | early_clobbered_regs_num = 0; | |
1429 | ||
1430 | for (nop = 0; nop < n_operands; nop++) | |
1431 | { | |
1432 | const char *p; | |
1433 | char *end; | |
1434 | int len, c, m, i, opalt_num, this_alternative_matches; | |
1435 | bool win, did_match, offmemok, early_clobber_p; | |
1436 | /* false => this operand can be reloaded somehow for this | |
1437 | alternative. */ | |
1438 | bool badop; | |
1439 | /* true => this operand can be reloaded if the alternative | |
1440 | allows regs. */ | |
1441 | bool winreg; | |
1442 | /* True if a constant forced into memory would be OK for | |
1443 | this operand. */ | |
1444 | bool constmemok; | |
1445 | enum reg_class this_alternative, this_costly_alternative; | |
1446 | HARD_REG_SET this_alternative_set, this_costly_alternative_set; | |
1447 | bool this_alternative_match_win, this_alternative_win; | |
1448 | bool this_alternative_offmemok; | |
1449 | enum machine_mode mode; | |
1450 | ||
1451 | opalt_num = nalt * n_operands + nop; | |
1452 | if (curr_static_id->operand_alternative[opalt_num].anything_ok) | |
1453 | { | |
1454 | /* Fast track for no constraints at all. */ | |
1455 | curr_alt[nop] = NO_REGS; | |
1456 | CLEAR_HARD_REG_SET (curr_alt_set[nop]); | |
1457 | curr_alt_win[nop] = true; | |
1458 | curr_alt_match_win[nop] = false; | |
1459 | curr_alt_offmemok[nop] = false; | |
1460 | curr_alt_matches[nop] = -1; | |
1461 | continue; | |
1462 | } | |
f4eafc30 | 1463 | |
55a2c322 VM |
1464 | op = no_subreg_reg_operand[nop]; |
1465 | mode = curr_operand_mode[nop]; | |
1466 | ||
1467 | win = did_match = winreg = offmemok = constmemok = false; | |
1468 | badop = true; | |
f4eafc30 | 1469 | |
55a2c322 VM |
1470 | early_clobber_p = false; |
1471 | p = curr_static_id->operand_alternative[opalt_num].constraint; | |
f4eafc30 | 1472 | |
55a2c322 VM |
1473 | this_costly_alternative = this_alternative = NO_REGS; |
1474 | /* We update set of possible hard regs besides its class | |
1475 | because reg class might be inaccurate. For example, | |
1476 | union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM | |
1477 | is translated in HI_REGS because classes are merged by | |
1478 | pairs and there is no accurate intermediate class. */ | |
1479 | CLEAR_HARD_REG_SET (this_alternative_set); | |
1480 | CLEAR_HARD_REG_SET (this_costly_alternative_set); | |
1481 | this_alternative_win = false; | |
1482 | this_alternative_match_win = false; | |
1483 | this_alternative_offmemok = false; | |
1484 | this_alternative_matches = -1; | |
f4eafc30 | 1485 | |
55a2c322 VM |
1486 | /* An empty constraint should be excluded by the fast |
1487 | track. */ | |
1488 | lra_assert (*p != 0 && *p != ','); | |
f4eafc30 | 1489 | |
55a2c322 VM |
1490 | /* Scan this alternative's specs for this operand; set WIN |
1491 | if the operand fits any letter in this alternative. | |
1492 | Otherwise, clear BADOP if this operand could fit some | |
1493 | letter after reloads, or set WINREG if this operand could | |
1494 | fit after reloads provided the constraint allows some | |
1495 | registers. */ | |
1496 | costly_p = false; | |
1497 | do | |
1498 | { | |
1499 | switch ((c = *p, len = CONSTRAINT_LEN (c, p)), c) | |
1500 | { | |
1501 | case '\0': | |
1502 | len = 0; | |
1503 | break; | |
1504 | case ',': | |
1505 | c = '\0'; | |
1506 | break; | |
f4eafc30 | 1507 | |
55a2c322 VM |
1508 | case '=': case '+': case '?': case '*': case '!': |
1509 | case ' ': case '\t': | |
1510 | break; | |
f4eafc30 | 1511 | |
55a2c322 VM |
1512 | case '%': |
1513 | /* We only support one commutative marker, the first | |
1514 | one. We already set commutative above. */ | |
1515 | break; | |
f4eafc30 | 1516 | |
55a2c322 VM |
1517 | case '&': |
1518 | early_clobber_p = true; | |
1519 | break; | |
f4eafc30 | 1520 | |
55a2c322 VM |
1521 | case '#': |
1522 | /* Ignore rest of this alternative. */ | |
1523 | c = '\0'; | |
1524 | break; | |
f4eafc30 | 1525 | |
55a2c322 VM |
1526 | case '0': case '1': case '2': case '3': case '4': |
1527 | case '5': case '6': case '7': case '8': case '9': | |
1528 | { | |
1529 | int m_hregno; | |
1530 | bool match_p; | |
f4eafc30 | 1531 | |
55a2c322 VM |
1532 | m = strtoul (p, &end, 10); |
1533 | p = end; | |
1534 | len = 0; | |
1535 | lra_assert (nop > m); | |
f4eafc30 | 1536 | |
55a2c322 VM |
1537 | this_alternative_matches = m; |
1538 | m_hregno = get_hard_regno (*curr_id->operand_loc[m]); | |
1539 | /* We are supposed to match a previous operand. | |
1540 | If we do, we win if that one did. If we do | |
1541 | not, count both of the operands as losers. | |
1542 | (This is too conservative, since most of the | |
1543 | time only a single reload insn will be needed | |
1544 | to make the two operands win. As a result, | |
1545 | this alternative may be rejected when it is | |
1546 | actually desirable.) */ | |
1547 | match_p = false; | |
1548 | if (operands_match_p (*curr_id->operand_loc[nop], | |
1549 | *curr_id->operand_loc[m], m_hregno)) | |
1550 | { | |
1551 | /* We should reject matching of an early | |
1552 | clobber operand if the matching operand is | |
1553 | not dying in the insn. */ | |
1554 | if (! curr_static_id->operand[m].early_clobber | |
1555 | || operand_reg[nop] == NULL_RTX | |
1556 | || (find_regno_note (curr_insn, REG_DEAD, | |
1c86bd80 VM |
1557 | REGNO (op)) |
1558 | || REGNO (op) == REGNO (operand_reg[m]))) | |
55a2c322 VM |
1559 | match_p = true; |
1560 | } | |
1561 | if (match_p) | |
1562 | { | |
1563 | /* If we are matching a non-offsettable | |
1564 | address where an offsettable address was | |
1565 | expected, then we must reject this | |
1566 | combination, because we can't reload | |
1567 | it. */ | |
1568 | if (curr_alt_offmemok[m] | |
1569 | && MEM_P (*curr_id->operand_loc[m]) | |
1570 | && curr_alt[m] == NO_REGS && ! curr_alt_win[m]) | |
1571 | continue; | |
f4eafc30 | 1572 | |
55a2c322 VM |
1573 | } |
1574 | else | |
1575 | { | |
1576 | /* Operands don't match. Both operands must | |
1577 | allow a reload register, otherwise we | |
1578 | cannot make them match. */ | |
1579 | if (curr_alt[m] == NO_REGS) | |
1580 | break; | |
1581 | /* Retroactively mark the operand we had to | |
1582 | match as a loser, if it wasn't already and | |
1583 | it wasn't matched to a register constraint | |
1584 | (e.g it might be matched by memory). */ | |
1585 | if (curr_alt_win[m] | |
1586 | && (operand_reg[m] == NULL_RTX | |
1587 | || hard_regno[m] < 0)) | |
1588 | { | |
1589 | losers++; | |
1590 | reload_nregs | |
1591 | += (ira_reg_class_max_nregs[curr_alt[m]] | |
1592 | [GET_MODE (*curr_id->operand_loc[m])]); | |
1593 | } | |
f4eafc30 | 1594 | |
55a2c322 VM |
1595 | /* We prefer no matching alternatives because |
1596 | it gives more freedom in RA. */ | |
1597 | if (operand_reg[nop] == NULL_RTX | |
1598 | || (find_regno_note (curr_insn, REG_DEAD, | |
1599 | REGNO (operand_reg[nop])) | |
1600 | == NULL_RTX)) | |
1601 | reject += 2; | |
1602 | } | |
1603 | /* If we have to reload this operand and some | |
1604 | previous operand also had to match the same | |
1605 | thing as this operand, we don't know how to do | |
1606 | that. */ | |
1607 | if (!match_p || !curr_alt_win[m]) | |
1608 | { | |
1609 | for (i = 0; i < nop; i++) | |
1610 | if (curr_alt_matches[i] == m) | |
1611 | break; | |
1612 | if (i < nop) | |
1613 | break; | |
1614 | } | |
1615 | else | |
1616 | did_match = true; | |
f4eafc30 | 1617 | |
55a2c322 VM |
1618 | /* This can be fixed with reloads if the operand |
1619 | we are supposed to match can be fixed with | |
1620 | reloads. */ | |
1621 | badop = false; | |
1622 | this_alternative = curr_alt[m]; | |
1623 | COPY_HARD_REG_SET (this_alternative_set, curr_alt_set[m]); | |
821b7577 | 1624 | winreg = this_alternative != NO_REGS; |
55a2c322 VM |
1625 | break; |
1626 | } | |
f4eafc30 | 1627 | |
55a2c322 VM |
1628 | case 'p': |
1629 | cl = base_reg_class (VOIDmode, ADDR_SPACE_GENERIC, | |
1630 | ADDRESS, SCRATCH); | |
1631 | this_alternative = reg_class_subunion[this_alternative][cl]; | |
1632 | IOR_HARD_REG_SET (this_alternative_set, | |
1633 | reg_class_contents[cl]); | |
1634 | if (costly_p) | |
1635 | { | |
1636 | this_costly_alternative | |
1637 | = reg_class_subunion[this_costly_alternative][cl]; | |
1638 | IOR_HARD_REG_SET (this_costly_alternative_set, | |
1639 | reg_class_contents[cl]); | |
1640 | } | |
1641 | win = true; | |
1642 | badop = false; | |
1643 | break; | |
f4eafc30 | 1644 | |
55a2c322 VM |
1645 | case TARGET_MEM_CONSTRAINT: |
1646 | if (MEM_P (op) || spilled_pseudo_p (op)) | |
1647 | win = true; | |
1bdc4b11 VM |
1648 | /* We can put constant or pseudo value into memory |
1649 | to satisfy the constraint. */ | |
1650 | if (CONST_POOL_OK_P (mode, op) || REG_P (op)) | |
55a2c322 VM |
1651 | badop = false; |
1652 | constmemok = true; | |
1653 | break; | |
f4eafc30 | 1654 | |
55a2c322 VM |
1655 | case '<': |
1656 | if (MEM_P (op) | |
1657 | && (GET_CODE (XEXP (op, 0)) == PRE_DEC | |
1658 | || GET_CODE (XEXP (op, 0)) == POST_DEC)) | |
1659 | win = true; | |
1660 | break; | |
f4eafc30 | 1661 | |
55a2c322 VM |
1662 | case '>': |
1663 | if (MEM_P (op) | |
1664 | && (GET_CODE (XEXP (op, 0)) == PRE_INC | |
1665 | || GET_CODE (XEXP (op, 0)) == POST_INC)) | |
1666 | win = true; | |
1667 | break; | |
f4eafc30 | 1668 | |
55a2c322 VM |
1669 | /* Memory op whose address is not offsettable. */ |
1670 | case 'V': | |
1671 | if (MEM_P (op) | |
1672 | && ! offsettable_nonstrict_memref_p (op)) | |
1673 | win = true; | |
1674 | break; | |
f4eafc30 | 1675 | |
55a2c322 VM |
1676 | /* Memory operand whose address is offsettable. */ |
1677 | case 'o': | |
1678 | if ((MEM_P (op) | |
1679 | && offsettable_nonstrict_memref_p (op)) | |
1680 | || spilled_pseudo_p (op)) | |
1681 | win = true; | |
1bdc4b11 VM |
1682 | /* We can put constant or pseudo value into memory |
1683 | or make memory address offsetable to satisfy the | |
1684 | constraint. */ | |
1685 | if (CONST_POOL_OK_P (mode, op) || MEM_P (op) || REG_P (op)) | |
55a2c322 VM |
1686 | badop = false; |
1687 | constmemok = true; | |
1688 | offmemok = true; | |
1689 | break; | |
f4eafc30 | 1690 | |
55a2c322 VM |
1691 | case 'E': |
1692 | case 'F': | |
1693 | if (GET_CODE (op) == CONST_DOUBLE | |
1694 | || (GET_CODE (op) == CONST_VECTOR | |
1695 | && (GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT))) | |
1696 | win = true; | |
1697 | break; | |
f4eafc30 | 1698 | |
55a2c322 VM |
1699 | case 'G': |
1700 | case 'H': | |
5a107a0f | 1701 | if (CONST_DOUBLE_AS_FLOAT_P (op) |
55a2c322 VM |
1702 | && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, c, p)) |
1703 | win = true; | |
1704 | break; | |
f4eafc30 | 1705 | |
55a2c322 | 1706 | case 's': |
5a107a0f | 1707 | if (CONST_SCALAR_INT_P (op)) |
55a2c322 | 1708 | break; |
1bdc4b11 | 1709 | |
55a2c322 VM |
1710 | case 'i': |
1711 | if (general_constant_p (op)) | |
1712 | win = true; | |
1713 | break; | |
f4eafc30 | 1714 | |
55a2c322 | 1715 | case 'n': |
5a107a0f | 1716 | if (CONST_SCALAR_INT_P (op)) |
55a2c322 VM |
1717 | win = true; |
1718 | break; | |
f4eafc30 | 1719 | |
55a2c322 VM |
1720 | case 'I': |
1721 | case 'J': | |
1722 | case 'K': | |
1723 | case 'L': | |
1724 | case 'M': | |
1725 | case 'N': | |
1726 | case 'O': | |
1727 | case 'P': | |
1728 | if (CONST_INT_P (op) | |
1729 | && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), c, p)) | |
1730 | win = true; | |
1731 | break; | |
f4eafc30 | 1732 | |
55a2c322 VM |
1733 | case 'X': |
1734 | /* This constraint should be excluded by the fast | |
1735 | track. */ | |
1736 | gcc_unreachable (); | |
1737 | break; | |
f4eafc30 | 1738 | |
55a2c322 VM |
1739 | case 'g': |
1740 | if (MEM_P (op) | |
1741 | || general_constant_p (op) | |
1742 | || spilled_pseudo_p (op)) | |
1743 | win = true; | |
1744 | /* Drop through into 'r' case. */ | |
f4eafc30 | 1745 | |
55a2c322 VM |
1746 | case 'r': |
1747 | this_alternative | |
1748 | = reg_class_subunion[this_alternative][GENERAL_REGS]; | |
1749 | IOR_HARD_REG_SET (this_alternative_set, | |
1750 | reg_class_contents[GENERAL_REGS]); | |
1751 | if (costly_p) | |
1752 | { | |
1753 | this_costly_alternative | |
1754 | = (reg_class_subunion | |
1755 | [this_costly_alternative][GENERAL_REGS]); | |
1756 | IOR_HARD_REG_SET (this_costly_alternative_set, | |
1757 | reg_class_contents[GENERAL_REGS]); | |
1758 | } | |
1759 | goto reg; | |
f4eafc30 | 1760 | |
55a2c322 VM |
1761 | default: |
1762 | if (REG_CLASS_FROM_CONSTRAINT (c, p) == NO_REGS) | |
1763 | { | |
1764 | #ifdef EXTRA_CONSTRAINT_STR | |
1765 | if (EXTRA_MEMORY_CONSTRAINT (c, p)) | |
1766 | { | |
1767 | if (EXTRA_CONSTRAINT_STR (op, c, p)) | |
1768 | win = true; | |
1769 | else if (spilled_pseudo_p (op)) | |
1770 | win = true; | |
f4eafc30 | 1771 | |
55a2c322 | 1772 | /* If we didn't already win, we can reload |
1bdc4b11 VM |
1773 | constants via force_const_mem or put the |
1774 | pseudo value into memory, or make other | |
1775 | memory by reloading the address like for | |
55a2c322 | 1776 | 'o'. */ |
1bdc4b11 VM |
1777 | if (CONST_POOL_OK_P (mode, op) |
1778 | || MEM_P (op) || REG_P (op)) | |
55a2c322 VM |
1779 | badop = false; |
1780 | constmemok = true; | |
1781 | offmemok = true; | |
1782 | break; | |
1783 | } | |
1784 | if (EXTRA_ADDRESS_CONSTRAINT (c, p)) | |
1785 | { | |
1786 | if (EXTRA_CONSTRAINT_STR (op, c, p)) | |
1787 | win = true; | |
f4eafc30 | 1788 | |
55a2c322 VM |
1789 | /* If we didn't already win, we can reload |
1790 | the address into a base register. */ | |
1791 | cl = base_reg_class (VOIDmode, ADDR_SPACE_GENERIC, | |
1792 | ADDRESS, SCRATCH); | |
1793 | this_alternative | |
1794 | = reg_class_subunion[this_alternative][cl]; | |
1795 | IOR_HARD_REG_SET (this_alternative_set, | |
1796 | reg_class_contents[cl]); | |
1797 | if (costly_p) | |
1798 | { | |
1799 | this_costly_alternative | |
1800 | = (reg_class_subunion | |
1801 | [this_costly_alternative][cl]); | |
1802 | IOR_HARD_REG_SET (this_costly_alternative_set, | |
1803 | reg_class_contents[cl]); | |
1804 | } | |
1805 | badop = false; | |
1806 | break; | |
1807 | } | |
f4eafc30 | 1808 | |
55a2c322 VM |
1809 | if (EXTRA_CONSTRAINT_STR (op, c, p)) |
1810 | win = true; | |
1811 | #endif | |
1812 | break; | |
1813 | } | |
f4eafc30 | 1814 | |
55a2c322 VM |
1815 | cl = REG_CLASS_FROM_CONSTRAINT (c, p); |
1816 | this_alternative = reg_class_subunion[this_alternative][cl]; | |
1817 | IOR_HARD_REG_SET (this_alternative_set, | |
1818 | reg_class_contents[cl]); | |
1819 | if (costly_p) | |
1820 | { | |
1821 | this_costly_alternative | |
1822 | = reg_class_subunion[this_costly_alternative][cl]; | |
1823 | IOR_HARD_REG_SET (this_costly_alternative_set, | |
1824 | reg_class_contents[cl]); | |
1825 | } | |
1826 | reg: | |
1827 | if (mode == BLKmode) | |
1828 | break; | |
1829 | winreg = true; | |
1830 | if (REG_P (op)) | |
1831 | { | |
1832 | if (hard_regno[nop] >= 0 | |
1833 | && in_hard_reg_set_p (this_alternative_set, | |
1834 | mode, hard_regno[nop])) | |
1835 | win = true; | |
1836 | else if (hard_regno[nop] < 0 | |
1837 | && in_class_p (op, this_alternative, NULL)) | |
1838 | win = true; | |
1839 | } | |
1840 | break; | |
1841 | } | |
1842 | if (c != ' ' && c != '\t') | |
1843 | costly_p = c == '*'; | |
1844 | } | |
1845 | while ((p += len), c); | |
f4eafc30 | 1846 | |
55a2c322 VM |
1847 | /* Record which operands fit this alternative. */ |
1848 | if (win) | |
1849 | { | |
1850 | this_alternative_win = true; | |
1851 | if (operand_reg[nop] != NULL_RTX) | |
1852 | { | |
1853 | if (hard_regno[nop] >= 0) | |
1854 | { | |
1855 | if (in_hard_reg_set_p (this_costly_alternative_set, | |
1856 | mode, hard_regno[nop])) | |
1857 | reject++; | |
1858 | } | |
1859 | else | |
1860 | { | |
1861 | /* Prefer won reg to spilled pseudo under other equal | |
1862 | conditions. */ | |
1863 | reject++; | |
1864 | if (in_class_p (operand_reg[nop], | |
1865 | this_costly_alternative, NULL)) | |
1866 | reject++; | |
1867 | } | |
1868 | /* We simulate the behaviour of old reload here. | |
1869 | Although scratches need hard registers and it | |
1870 | might result in spilling other pseudos, no reload | |
1871 | insns are generated for the scratches. So it | |
1872 | might cost something but probably less than old | |
1873 | reload pass believes. */ | |
1874 | if (lra_former_scratch_p (REGNO (operand_reg[nop]))) | |
821b7577 | 1875 | reject += LRA_LOSER_COST_FACTOR; |
55a2c322 VM |
1876 | } |
1877 | } | |
1878 | else if (did_match) | |
1879 | this_alternative_match_win = true; | |
1880 | else | |
1881 | { | |
1882 | int const_to_mem = 0; | |
1883 | bool no_regs_p; | |
1884 | ||
e86c0101 SB |
1885 | /* If this alternative asks for a specific reg class, see if there |
1886 | is at least one allocatable register in that class. */ | |
55a2c322 VM |
1887 | no_regs_p |
1888 | = (this_alternative == NO_REGS | |
1889 | || (hard_reg_set_subset_p | |
1890 | (reg_class_contents[this_alternative], | |
1891 | lra_no_alloc_regs))); | |
e86c0101 SB |
1892 | |
1893 | /* For asms, verify that the class for this alternative is possible | |
1894 | for the mode that is specified. */ | |
1895 | if (!no_regs_p && REG_P (op) && INSN_CODE (curr_insn) < 0) | |
1896 | { | |
1897 | int i; | |
1898 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1899 | if (HARD_REGNO_MODE_OK (i, mode) | |
1900 | && in_hard_reg_set_p (reg_class_contents[this_alternative], mode, i)) | |
1901 | break; | |
1902 | if (i == FIRST_PSEUDO_REGISTER) | |
1903 | winreg = false; | |
1904 | } | |
1905 | ||
55a2c322 VM |
1906 | /* If this operand accepts a register, and if the |
1907 | register class has at least one allocatable register, | |
1908 | then this operand can be reloaded. */ | |
1909 | if (winreg && !no_regs_p) | |
1910 | badop = false; | |
f4eafc30 | 1911 | |
55a2c322 VM |
1912 | if (badop) |
1913 | goto fail; | |
1914 | ||
1915 | this_alternative_offmemok = offmemok; | |
1916 | if (this_costly_alternative != NO_REGS) | |
1917 | reject++; | |
1918 | /* If the operand is dying, has a matching constraint, | |
1919 | and satisfies constraints of the matched operand | |
1920 | which failed to satisfy the own constraints, we do | |
1921 | not need to generate a reload insn for this | |
1922 | operand. */ | |
1923 | if (!(this_alternative_matches >= 0 | |
1924 | && !curr_alt_win[this_alternative_matches] | |
1925 | && REG_P (op) | |
1926 | && find_regno_note (curr_insn, REG_DEAD, REGNO (op)) | |
1927 | && (hard_regno[nop] >= 0 | |
1928 | ? in_hard_reg_set_p (this_alternative_set, | |
1929 | mode, hard_regno[nop]) | |
1930 | : in_class_p (op, this_alternative, NULL)))) | |
027ece11 | 1931 | { |
5306401f VM |
1932 | /* Strict_low_part requires to reload the register |
1933 | not the sub-register. In this case we should | |
1934 | check that a final reload hard reg can hold the | |
1935 | value mode. */ | |
027ece11 VM |
1936 | if (curr_static_id->operand[nop].strict_low |
1937 | && REG_P (op) | |
1938 | && hard_regno[nop] < 0 | |
1939 | && GET_CODE (*curr_id->operand_loc[nop]) == SUBREG | |
1940 | && ira_class_hard_regs_num[this_alternative] > 0 | |
1941 | && ! HARD_REGNO_MODE_OK (ira_class_hard_regs | |
1942 | [this_alternative][0], | |
1943 | GET_MODE (op))) | |
1944 | goto fail; | |
1945 | losers++; | |
1946 | } | |
55a2c322 VM |
1947 | if (operand_reg[nop] != NULL_RTX |
1948 | /* Output operands and matched input operands are | |
1949 | not inherited. The following conditions do not | |
1950 | exactly describe the previous statement but they | |
1951 | are pretty close. */ | |
1952 | && curr_static_id->operand[nop].type != OP_OUT | |
1953 | && (this_alternative_matches < 0 | |
1954 | || curr_static_id->operand[nop].type != OP_IN)) | |
1955 | { | |
1956 | int last_reload = (lra_reg_info[ORIGINAL_REGNO | |
1957 | (operand_reg[nop])] | |
1958 | .last_reload); | |
1959 | ||
1960 | if (last_reload > bb_reload_num) | |
1961 | reload_sum += last_reload - bb_reload_num; | |
1962 | } | |
1963 | /* If this is a constant that is reloaded into the | |
1964 | desired class by copying it to memory first, count | |
1965 | that as another reload. This is consistent with | |
1966 | other code and is required to avoid choosing another | |
1967 | alternative when the constant is moved into memory. | |
1968 | Note that the test here is precisely the same as in | |
1969 | the code below that calls force_const_mem. */ | |
1970 | if (CONST_POOL_OK_P (mode, op) | |
1971 | && ((targetm.preferred_reload_class | |
1972 | (op, this_alternative) == NO_REGS) | |
1973 | || no_input_reloads_p)) | |
1974 | { | |
1975 | const_to_mem = 1; | |
1976 | if (! no_regs_p) | |
1977 | losers++; | |
1978 | } | |
f4eafc30 | 1979 | |
55a2c322 VM |
1980 | /* Alternative loses if it requires a type of reload not |
1981 | permitted for this insn. We can always reload | |
1982 | objects with a REG_UNUSED note. */ | |
1983 | if ((curr_static_id->operand[nop].type != OP_IN | |
1984 | && no_output_reloads_p | |
1985 | && ! find_reg_note (curr_insn, REG_UNUSED, op)) | |
1986 | || (curr_static_id->operand[nop].type != OP_OUT | |
1987 | && no_input_reloads_p && ! const_to_mem)) | |
1988 | goto fail; | |
f4eafc30 | 1989 | |
821b7577 VM |
1990 | /* Check strong discouragement of reload of non-constant |
1991 | into class THIS_ALTERNATIVE. */ | |
1992 | if (! CONSTANT_P (op) && ! no_regs_p | |
1993 | && (targetm.preferred_reload_class | |
1994 | (op, this_alternative) == NO_REGS | |
1995 | || (curr_static_id->operand[nop].type == OP_OUT | |
1996 | && (targetm.preferred_output_reload_class | |
1997 | (op, this_alternative) == NO_REGS)))) | |
1998 | reject += LRA_MAX_REJECT; | |
f4eafc30 | 1999 | |
682303da VM |
2000 | if (MEM_P (op) && offmemok) |
2001 | { | |
2002 | /* If we know offset and this non-offsetable memory, | |
2003 | something wrong with this memory and it is better | |
2004 | to try other memory possibilities. */ | |
2005 | if (MEM_OFFSET_KNOWN_P (op)) | |
2006 | reject += LRA_MAX_REJECT; | |
2007 | } | |
2008 | else if (! (const_to_mem && constmemok)) | |
55a2c322 VM |
2009 | { |
2010 | /* We prefer to reload pseudos over reloading other | |
2011 | things, since such reloads may be able to be | |
2012 | eliminated later. So bump REJECT in other cases. | |
2013 | Don't do this in the case where we are forcing a | |
2014 | constant into memory and it will then win since | |
2015 | we don't want to have a different alternative | |
2016 | match then. */ | |
2017 | if (! (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER)) | |
2018 | reject += 2; | |
f4eafc30 | 2019 | |
55a2c322 VM |
2020 | if (! no_regs_p) |
2021 | reload_nregs | |
2022 | += ira_reg_class_max_nregs[this_alternative][mode]; | |
36ff9dfb VM |
2023 | |
2024 | if (SMALL_REGISTER_CLASS_P (this_alternative)) | |
2025 | reject += LRA_LOSER_COST_FACTOR / 2; | |
55a2c322 VM |
2026 | } |
2027 | ||
1bdc4b11 VM |
2028 | /* We are trying to spill pseudo into memory. It is |
2029 | usually more costly than moving to a hard register | |
2030 | although it might takes the same number of | |
2031 | reloads. */ | |
2032 | if (no_regs_p && REG_P (op)) | |
deca73f5 | 2033 | reject += 2; |
1bdc4b11 | 2034 | |
7100b561 UB |
2035 | #ifdef SECONDARY_MEMORY_NEEDED |
2036 | /* If reload requires moving value through secondary | |
2037 | memory, it will need one more insn at least. */ | |
2038 | if (this_alternative != NO_REGS | |
2039 | && REG_P (op) && (cl = get_reg_class (REGNO (op))) != NO_REGS | |
2040 | && ((curr_static_id->operand[nop].type != OP_OUT | |
2041 | && SECONDARY_MEMORY_NEEDED (cl, this_alternative, | |
2042 | GET_MODE (op))) | |
2043 | || (curr_static_id->operand[nop].type != OP_IN | |
2044 | && SECONDARY_MEMORY_NEEDED (this_alternative, cl, | |
2045 | GET_MODE (op))))) | |
2046 | losers++; | |
2047 | #endif | |
55a2c322 VM |
2048 | /* Input reloads can be inherited more often than output |
2049 | reloads can be removed, so penalize output | |
2050 | reloads. */ | |
2051 | if (!REG_P (op) || curr_static_id->operand[nop].type != OP_IN) | |
2052 | reject++; | |
36ff9dfb | 2053 | |
55a2c322 | 2054 | } |
f4eafc30 | 2055 | |
55a2c322 VM |
2056 | if (early_clobber_p) |
2057 | reject++; | |
2058 | /* ??? We check early clobbers after processing all operands | |
2059 | (see loop below) and there we update the costs more. | |
2060 | Should we update the cost (may be approximately) here | |
2061 | because of early clobber register reloads or it is a rare | |
2062 | or non-important thing to be worth to do it. */ | |
821b7577 | 2063 | overall = losers * LRA_LOSER_COST_FACTOR + reject; |
55a2c322 | 2064 | if ((best_losers == 0 || losers != 0) && best_overall < overall) |
deca73f5 VM |
2065 | { |
2066 | if (lra_dump_file != NULL) | |
2067 | fprintf (lra_dump_file, | |
2068 | " alt=%d,overall=%d,losers=%d -- reject\n", | |
2069 | nalt, overall, losers); | |
2070 | goto fail; | |
2071 | } | |
55a2c322 VM |
2072 | |
2073 | curr_alt[nop] = this_alternative; | |
2074 | COPY_HARD_REG_SET (curr_alt_set[nop], this_alternative_set); | |
2075 | curr_alt_win[nop] = this_alternative_win; | |
2076 | curr_alt_match_win[nop] = this_alternative_match_win; | |
2077 | curr_alt_offmemok[nop] = this_alternative_offmemok; | |
2078 | curr_alt_matches[nop] = this_alternative_matches; | |
f4eafc30 | 2079 | |
55a2c322 VM |
2080 | if (this_alternative_matches >= 0 |
2081 | && !did_match && !this_alternative_win) | |
2082 | curr_alt_win[this_alternative_matches] = false; | |
f4eafc30 | 2083 | |
55a2c322 VM |
2084 | if (early_clobber_p && operand_reg[nop] != NULL_RTX) |
2085 | early_clobbered_nops[early_clobbered_regs_num++] = nop; | |
2086 | } | |
2c62cbaa VM |
2087 | if (curr_insn_set != NULL_RTX && n_operands == 2 |
2088 | /* Prevent processing non-move insns. */ | |
2089 | && (GET_CODE (SET_SRC (curr_insn_set)) == SUBREG | |
2090 | || SET_SRC (curr_insn_set) == no_subreg_reg_operand[1]) | |
2091 | && ((! curr_alt_win[0] && ! curr_alt_win[1] | |
2092 | && REG_P (no_subreg_reg_operand[0]) | |
2093 | && REG_P (no_subreg_reg_operand[1]) | |
2094 | && (reg_in_class_p (no_subreg_reg_operand[0], curr_alt[1]) | |
2095 | || reg_in_class_p (no_subreg_reg_operand[1], curr_alt[0]))) | |
2096 | || (! curr_alt_win[0] && curr_alt_win[1] | |
2097 | && REG_P (no_subreg_reg_operand[1]) | |
2098 | && reg_in_class_p (no_subreg_reg_operand[1], curr_alt[0])) | |
2099 | || (curr_alt_win[0] && ! curr_alt_win[1] | |
2100 | && REG_P (no_subreg_reg_operand[0]) | |
2101 | && reg_in_class_p (no_subreg_reg_operand[0], curr_alt[1]) | |
2102 | && (! CONST_POOL_OK_P (curr_operand_mode[1], | |
2103 | no_subreg_reg_operand[1]) | |
2104 | || (targetm.preferred_reload_class | |
2105 | (no_subreg_reg_operand[1], | |
2106 | (enum reg_class) curr_alt[1]) != NO_REGS)) | |
2107 | /* If it is a result of recent elimination in move | |
2108 | insn we can transform it into an add still by | |
2109 | using this alternative. */ | |
2110 | && GET_CODE (no_subreg_reg_operand[1]) != PLUS))) | |
2111 | /* We have a move insn and a new reload insn will be similar | |
2112 | to the current insn. We should avoid such situation as it | |
2113 | results in LRA cycling. */ | |
2114 | overall += LRA_MAX_REJECT; | |
55a2c322 VM |
2115 | ok_p = true; |
2116 | curr_alt_dont_inherit_ops_num = 0; | |
2117 | for (nop = 0; nop < early_clobbered_regs_num; nop++) | |
2118 | { | |
2194f7a2 | 2119 | int i, j, clobbered_hard_regno, first_conflict_j, last_conflict_j; |
55a2c322 VM |
2120 | HARD_REG_SET temp_set; |
2121 | ||
2122 | i = early_clobbered_nops[nop]; | |
2123 | if ((! curr_alt_win[i] && ! curr_alt_match_win[i]) | |
2124 | || hard_regno[i] < 0) | |
2125 | continue; | |
1c86bd80 | 2126 | lra_assert (operand_reg[i] != NULL_RTX); |
55a2c322 VM |
2127 | clobbered_hard_regno = hard_regno[i]; |
2128 | CLEAR_HARD_REG_SET (temp_set); | |
2129 | add_to_hard_reg_set (&temp_set, biggest_mode[i], clobbered_hard_regno); | |
2194f7a2 | 2130 | first_conflict_j = last_conflict_j = -1; |
55a2c322 VM |
2131 | for (j = 0; j < n_operands; j++) |
2132 | if (j == i | |
2133 | /* We don't want process insides of match_operator and | |
2134 | match_parallel because otherwise we would process | |
2135 | their operands once again generating a wrong | |
2136 | code. */ | |
2137 | || curr_static_id->operand[j].is_operator) | |
2138 | continue; | |
2139 | else if ((curr_alt_matches[j] == i && curr_alt_match_win[j]) | |
2140 | || (curr_alt_matches[i] == j && curr_alt_match_win[i])) | |
2141 | continue; | |
1c86bd80 VM |
2142 | /* If we don't reload j-th operand, check conflicts. */ |
2143 | else if ((curr_alt_win[j] || curr_alt_match_win[j]) | |
2144 | && uses_hard_regs_p (*curr_id->operand_loc[j], temp_set)) | |
2194f7a2 VM |
2145 | { |
2146 | if (first_conflict_j < 0) | |
2147 | first_conflict_j = j; | |
2148 | last_conflict_j = j; | |
2149 | } | |
2150 | if (last_conflict_j < 0) | |
55a2c322 | 2151 | continue; |
1c86bd80 VM |
2152 | /* If earlyclobber operand conflicts with another |
2153 | non-matching operand which is actually the same register | |
2154 | as the earlyclobber operand, it is better to reload the | |
2155 | another operand as an operand matching the earlyclobber | |
2156 | operand can be also the same. */ | |
2194f7a2 VM |
2157 | if (first_conflict_j == last_conflict_j |
2158 | && operand_reg[last_conflict_j] | |
2159 | != NULL_RTX && ! curr_alt_match_win[last_conflict_j] | |
2160 | && REGNO (operand_reg[i]) == REGNO (operand_reg[last_conflict_j])) | |
1c86bd80 | 2161 | { |
2194f7a2 VM |
2162 | curr_alt_win[last_conflict_j] = false; |
2163 | curr_alt_dont_inherit_ops[curr_alt_dont_inherit_ops_num++] | |
2164 | = last_conflict_j; | |
1c86bd80 | 2165 | losers++; |
deca73f5 VM |
2166 | /* Early clobber was already reflected in REJECT. */ |
2167 | lra_assert (reject > 0); | |
2168 | reject--; | |
2169 | overall += LRA_LOSER_COST_FACTOR - 1; | |
1c86bd80 | 2170 | } |
55a2c322 VM |
2171 | else |
2172 | { | |
1c86bd80 VM |
2173 | /* We need to reload early clobbered register and the |
2174 | matched registers. */ | |
2175 | for (j = 0; j < n_operands; j++) | |
2176 | if (curr_alt_matches[j] == i) | |
2177 | { | |
2178 | curr_alt_match_win[j] = false; | |
2179 | losers++; | |
2180 | overall += LRA_LOSER_COST_FACTOR; | |
2181 | } | |
2182 | if (! curr_alt_match_win[i]) | |
2183 | curr_alt_dont_inherit_ops[curr_alt_dont_inherit_ops_num++] = i; | |
2184 | else | |
2185 | { | |
2186 | /* Remember pseudos used for match reloads are never | |
2187 | inherited. */ | |
2188 | lra_assert (curr_alt_matches[i] >= 0); | |
2189 | curr_alt_win[curr_alt_matches[i]] = false; | |
2190 | } | |
2191 | curr_alt_win[i] = curr_alt_match_win[i] = false; | |
2192 | losers++; | |
deca73f5 VM |
2193 | /* Early clobber was already reflected in REJECT. */ |
2194 | lra_assert (reject > 0); | |
2195 | reject--; | |
2196 | overall += LRA_LOSER_COST_FACTOR - 1; | |
55a2c322 | 2197 | } |
55a2c322 | 2198 | } |
deca73f5 | 2199 | if (lra_dump_file != NULL) |
36ff9dfb VM |
2200 | fprintf (lra_dump_file, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n", |
2201 | nalt, overall, losers, reload_nregs); | |
deca73f5 | 2202 | |
55a2c322 VM |
2203 | /* If this alternative can be made to work by reloading, and it |
2204 | needs less reloading than the others checked so far, record | |
2205 | it as the chosen goal for reloading. */ | |
2206 | if ((best_losers != 0 && losers == 0) | |
2207 | || (((best_losers == 0 && losers == 0) | |
2208 | || (best_losers != 0 && losers != 0)) | |
2209 | && (best_overall > overall | |
2210 | || (best_overall == overall | |
2211 | /* If the cost of the reloads is the same, | |
2212 | prefer alternative which requires minimal | |
36ff9dfb VM |
2213 | number of reload regs. */ |
2214 | && (reload_nregs < best_reload_nregs | |
2215 | || (reload_nregs == best_reload_nregs | |
f15feaf9 VM |
2216 | && (best_reload_sum < reload_sum |
2217 | || (best_reload_sum == reload_sum | |
2218 | && nalt < goal_alt_number)))))))) | |
55a2c322 VM |
2219 | { |
2220 | for (nop = 0; nop < n_operands; nop++) | |
2221 | { | |
2222 | goal_alt_win[nop] = curr_alt_win[nop]; | |
2223 | goal_alt_match_win[nop] = curr_alt_match_win[nop]; | |
2224 | goal_alt_matches[nop] = curr_alt_matches[nop]; | |
2225 | goal_alt[nop] = curr_alt[nop]; | |
2226 | goal_alt_offmemok[nop] = curr_alt_offmemok[nop]; | |
2227 | } | |
2228 | goal_alt_dont_inherit_ops_num = curr_alt_dont_inherit_ops_num; | |
2229 | for (nop = 0; nop < curr_alt_dont_inherit_ops_num; nop++) | |
2230 | goal_alt_dont_inherit_ops[nop] = curr_alt_dont_inherit_ops[nop]; | |
2231 | goal_alt_swapped = curr_swapped; | |
2232 | best_overall = overall; | |
2233 | best_losers = losers; | |
55a2c322 VM |
2234 | best_reload_nregs = reload_nregs; |
2235 | best_reload_sum = reload_sum; | |
2236 | goal_alt_number = nalt; | |
2237 | } | |
2238 | if (losers == 0) | |
2239 | /* Everything is satisfied. Do not process alternatives | |
f4eafc30 | 2240 | anymore. */ |
55a2c322 VM |
2241 | break; |
2242 | fail: | |
2243 | ; | |
2244 | } | |
2245 | return ok_p; | |
2246 | } | |
2247 | ||
2248 | /* Return 1 if ADDR is a valid memory address for mode MODE in address | |
2249 | space AS, and check that each pseudo has the proper kind of hard | |
2250 | reg. */ | |
2251 | static int | |
2252 | valid_address_p (enum machine_mode mode ATTRIBUTE_UNUSED, | |
2253 | rtx addr, addr_space_t as) | |
2254 | { | |
2255 | #ifdef GO_IF_LEGITIMATE_ADDRESS | |
2256 | lra_assert (ADDR_SPACE_GENERIC_P (as)); | |
2257 | GO_IF_LEGITIMATE_ADDRESS (mode, addr, win); | |
2258 | return 0; | |
f4eafc30 | 2259 | |
55a2c322 VM |
2260 | win: |
2261 | return 1; | |
2262 | #else | |
2263 | return targetm.addr_space.legitimate_address_p (mode, addr, 0, as); | |
2264 | #endif | |
2265 | } | |
2266 | ||
277f65de | 2267 | /* Return whether address AD is valid. */ |
8bf9b489 RS |
2268 | |
2269 | static bool | |
277f65de | 2270 | valid_address_p (struct address_info *ad) |
8bf9b489 RS |
2271 | { |
2272 | /* Some ports do not check displacements for eliminable registers, | |
2273 | so we replace them temporarily with the elimination target. */ | |
2274 | rtx saved_base_reg = NULL_RTX; | |
2275 | rtx saved_index_reg = NULL_RTX; | |
277f65de RS |
2276 | rtx *base_term = strip_subreg (ad->base_term); |
2277 | rtx *index_term = strip_subreg (ad->index_term); | |
2278 | if (base_term != NULL) | |
8bf9b489 | 2279 | { |
277f65de RS |
2280 | saved_base_reg = *base_term; |
2281 | lra_eliminate_reg_if_possible (base_term); | |
2282 | if (ad->base_term2 != NULL) | |
2283 | *ad->base_term2 = *ad->base_term; | |
8bf9b489 | 2284 | } |
277f65de | 2285 | if (index_term != NULL) |
8bf9b489 | 2286 | { |
277f65de RS |
2287 | saved_index_reg = *index_term; |
2288 | lra_eliminate_reg_if_possible (index_term); | |
8bf9b489 | 2289 | } |
277f65de | 2290 | bool ok_p = valid_address_p (ad->mode, *ad->outer, ad->as); |
8bf9b489 RS |
2291 | if (saved_base_reg != NULL_RTX) |
2292 | { | |
277f65de RS |
2293 | *base_term = saved_base_reg; |
2294 | if (ad->base_term2 != NULL) | |
2295 | *ad->base_term2 = *ad->base_term; | |
8bf9b489 RS |
2296 | } |
2297 | if (saved_index_reg != NULL_RTX) | |
277f65de | 2298 | *index_term = saved_index_reg; |
8bf9b489 RS |
2299 | return ok_p; |
2300 | } | |
2301 | ||
277f65de | 2302 | /* Make reload base reg + disp from address AD. Return the new pseudo. */ |
55a2c322 | 2303 | static rtx |
277f65de | 2304 | base_plus_disp_to_reg (struct address_info *ad) |
55a2c322 VM |
2305 | { |
2306 | enum reg_class cl; | |
2307 | rtx new_reg; | |
2308 | ||
277f65de RS |
2309 | lra_assert (ad->base == ad->base_term && ad->disp == ad->disp_term); |
2310 | cl = base_reg_class (ad->mode, ad->as, ad->base_outer_code, | |
2311 | get_index_code (ad)); | |
2312 | new_reg = lra_create_new_reg (GET_MODE (*ad->base_term), NULL_RTX, | |
2313 | cl, "base + disp"); | |
2314 | lra_emit_add (new_reg, *ad->base_term, *ad->disp_term); | |
55a2c322 VM |
2315 | return new_reg; |
2316 | } | |
2317 | ||
277f65de RS |
2318 | /* Return true if we can add a displacement to address AD, even if that |
2319 | makes the address invalid. The fix-up code requires any new address | |
2320 | to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */ | |
02ea4bf4 | 2321 | static bool |
277f65de | 2322 | can_add_disp_p (struct address_info *ad) |
02ea4bf4 | 2323 | { |
277f65de RS |
2324 | return (!ad->autoinc_p |
2325 | && ad->segment == NULL | |
2326 | && ad->base == ad->base_term | |
2327 | && ad->disp == ad->disp_term); | |
02ea4bf4 RS |
2328 | } |
2329 | ||
277f65de RS |
2330 | /* Make equiv substitution in address AD. Return true if a substitution |
2331 | was made. */ | |
55a2c322 | 2332 | static bool |
277f65de | 2333 | equiv_address_substitution (struct address_info *ad) |
55a2c322 | 2334 | { |
277f65de | 2335 | rtx base_reg, new_base_reg, index_reg, new_index_reg, *base_term, *index_term; |
55a2c322 VM |
2336 | HOST_WIDE_INT disp, scale; |
2337 | bool change_p; | |
2338 | ||
277f65de RS |
2339 | base_term = strip_subreg (ad->base_term); |
2340 | if (base_term == NULL) | |
55a2c322 VM |
2341 | base_reg = new_base_reg = NULL_RTX; |
2342 | else | |
2343 | { | |
277f65de | 2344 | base_reg = *base_term; |
55a2c322 VM |
2345 | new_base_reg = get_equiv_substitution (base_reg); |
2346 | } | |
277f65de RS |
2347 | index_term = strip_subreg (ad->index_term); |
2348 | if (index_term == NULL) | |
55a2c322 VM |
2349 | index_reg = new_index_reg = NULL_RTX; |
2350 | else | |
2351 | { | |
277f65de | 2352 | index_reg = *index_term; |
55a2c322 VM |
2353 | new_index_reg = get_equiv_substitution (index_reg); |
2354 | } | |
2355 | if (base_reg == new_base_reg && index_reg == new_index_reg) | |
2356 | return false; | |
2357 | disp = 0; | |
2358 | change_p = false; | |
2359 | if (lra_dump_file != NULL) | |
2360 | { | |
2361 | fprintf (lra_dump_file, "Changing address in insn %d ", | |
2362 | INSN_UID (curr_insn)); | |
cfbeaedf | 2363 | dump_value_slim (lra_dump_file, *ad->outer, 1); |
55a2c322 VM |
2364 | } |
2365 | if (base_reg != new_base_reg) | |
2366 | { | |
2367 | if (REG_P (new_base_reg)) | |
2368 | { | |
277f65de | 2369 | *base_term = new_base_reg; |
55a2c322 VM |
2370 | change_p = true; |
2371 | } | |
2372 | else if (GET_CODE (new_base_reg) == PLUS | |
2373 | && REG_P (XEXP (new_base_reg, 0)) | |
02ea4bf4 | 2374 | && CONST_INT_P (XEXP (new_base_reg, 1)) |
277f65de | 2375 | && can_add_disp_p (ad)) |
55a2c322 VM |
2376 | { |
2377 | disp += INTVAL (XEXP (new_base_reg, 1)); | |
277f65de | 2378 | *base_term = XEXP (new_base_reg, 0); |
55a2c322 VM |
2379 | change_p = true; |
2380 | } | |
277f65de RS |
2381 | if (ad->base_term2 != NULL) |
2382 | *ad->base_term2 = *ad->base_term; | |
55a2c322 | 2383 | } |
55a2c322 VM |
2384 | if (index_reg != new_index_reg) |
2385 | { | |
2386 | if (REG_P (new_index_reg)) | |
2387 | { | |
277f65de | 2388 | *index_term = new_index_reg; |
55a2c322 VM |
2389 | change_p = true; |
2390 | } | |
2391 | else if (GET_CODE (new_index_reg) == PLUS | |
2392 | && REG_P (XEXP (new_index_reg, 0)) | |
02ea4bf4 | 2393 | && CONST_INT_P (XEXP (new_index_reg, 1)) |
277f65de | 2394 | && can_add_disp_p (ad) |
02ea4bf4 | 2395 | && (scale = get_index_scale (ad))) |
55a2c322 VM |
2396 | { |
2397 | disp += INTVAL (XEXP (new_index_reg, 1)) * scale; | |
277f65de | 2398 | *index_term = XEXP (new_index_reg, 0); |
55a2c322 VM |
2399 | change_p = true; |
2400 | } | |
2401 | } | |
2402 | if (disp != 0) | |
2403 | { | |
277f65de RS |
2404 | if (ad->disp != NULL) |
2405 | *ad->disp = plus_constant (GET_MODE (*ad->inner), *ad->disp, disp); | |
55a2c322 VM |
2406 | else |
2407 | { | |
277f65de RS |
2408 | *ad->inner = plus_constant (GET_MODE (*ad->inner), *ad->inner, disp); |
2409 | update_address (ad); | |
55a2c322 VM |
2410 | } |
2411 | change_p = true; | |
2412 | } | |
2413 | if (lra_dump_file != NULL) | |
2414 | { | |
2415 | if (! change_p) | |
2416 | fprintf (lra_dump_file, " -- no change\n"); | |
2417 | else | |
2418 | { | |
2419 | fprintf (lra_dump_file, " on equiv "); | |
cfbeaedf | 2420 | dump_value_slim (lra_dump_file, *ad->outer, 1); |
55a2c322 VM |
2421 | fprintf (lra_dump_file, "\n"); |
2422 | } | |
2423 | } | |
2424 | return change_p; | |
2425 | } | |
2426 | ||
bd3d34d4 RS |
2427 | /* Major function to make reloads for an address in operand NOP. |
2428 | The supported cases are: | |
2429 | ||
5a107a0f VM |
2430 | 1) an address that existed before LRA started, at which point it |
2431 | must have been valid. These addresses are subject to elimination | |
2432 | and may have become invalid due to the elimination offset being out | |
2433 | of range. | |
bd3d34d4 | 2434 | |
5a107a0f VM |
2435 | 2) an address created by forcing a constant to memory |
2436 | (force_const_to_mem). The initial form of these addresses might | |
2437 | not be valid, and it is this function's job to make them valid. | |
bd3d34d4 RS |
2438 | |
2439 | 3) a frame address formed from a register and a (possibly zero) | |
5a107a0f VM |
2440 | constant offset. As above, these addresses might not be valid and |
2441 | this function must make them so. | |
bd3d34d4 RS |
2442 | |
2443 | Add reloads to the lists *BEFORE and *AFTER. We might need to add | |
55a2c322 VM |
2444 | reloads to *AFTER because of inc/dec, {pre, post} modify in the |
2445 | address. Return true for any RTL change. */ | |
2446 | static bool | |
2447 | process_address (int nop, rtx *before, rtx *after) | |
2448 | { | |
277f65de RS |
2449 | struct address_info ad; |
2450 | rtx new_reg; | |
55a2c322 VM |
2451 | rtx op = *curr_id->operand_loc[nop]; |
2452 | const char *constraint = curr_static_id->operand[nop].constraint; | |
2453 | bool change_p; | |
55a2c322 VM |
2454 | |
2455 | if (constraint[0] == 'p' | |
2456 | || EXTRA_ADDRESS_CONSTRAINT (constraint[0], constraint)) | |
277f65de | 2457 | decompose_lea_address (&ad, curr_id->operand_loc[nop]); |
55a2c322 | 2458 | else if (MEM_P (op)) |
277f65de | 2459 | decompose_mem_address (&ad, op); |
55a2c322 VM |
2460 | else if (GET_CODE (op) == SUBREG |
2461 | && MEM_P (SUBREG_REG (op))) | |
277f65de | 2462 | decompose_mem_address (&ad, SUBREG_REG (op)); |
55a2c322 VM |
2463 | else |
2464 | return false; | |
277f65de RS |
2465 | change_p = equiv_address_substitution (&ad); |
2466 | if (ad.base_term != NULL | |
55a2c322 | 2467 | && (process_addr_reg |
277f65de RS |
2468 | (ad.base_term, before, |
2469 | (ad.autoinc_p | |
2470 | && !(REG_P (*ad.base_term) | |
2471 | && find_regno_note (curr_insn, REG_DEAD, | |
2472 | REGNO (*ad.base_term)) != NULL_RTX) | |
55a2c322 | 2473 | ? after : NULL), |
277f65de RS |
2474 | base_reg_class (ad.mode, ad.as, ad.base_outer_code, |
2475 | get_index_code (&ad))))) | |
55a2c322 VM |
2476 | { |
2477 | change_p = true; | |
277f65de RS |
2478 | if (ad.base_term2 != NULL) |
2479 | *ad.base_term2 = *ad.base_term; | |
55a2c322 | 2480 | } |
277f65de RS |
2481 | if (ad.index_term != NULL |
2482 | && process_addr_reg (ad.index_term, before, NULL, INDEX_REG_CLASS)) | |
55a2c322 VM |
2483 | change_p = true; |
2484 | ||
2c62cbaa VM |
2485 | #ifdef EXTRA_CONSTRAINT_STR |
2486 | /* Target hooks sometimes reject extra constraint addresses -- use | |
2487 | EXTRA_CONSTRAINT_STR for the validation. */ | |
2488 | if (constraint[0] != 'p' | |
2489 | && EXTRA_ADDRESS_CONSTRAINT (constraint[0], constraint) | |
2490 | && EXTRA_CONSTRAINT_STR (op, constraint[0], constraint)) | |
2491 | return change_p; | |
2492 | #endif | |
2493 | ||
277f65de | 2494 | /* There are three cases where the shape of *AD.INNER may now be invalid: |
bd3d34d4 RS |
2495 | |
2496 | 1) the original address was valid, but either elimination or | |
5a107a0f VM |
2497 | equiv_address_substitution was applied and that made |
2498 | the address invalid. | |
bd3d34d4 RS |
2499 | |
2500 | 2) the address is an invalid symbolic address created by | |
5a107a0f | 2501 | force_const_to_mem. |
bd3d34d4 RS |
2502 | |
2503 | 3) the address is a frame address with an invalid offset. | |
2504 | ||
2c62cbaa VM |
2505 | All these cases involve a non-autoinc address, so there is no |
2506 | point revalidating other types. */ | |
2507 | if (ad.autoinc_p || valid_address_p (&ad)) | |
55a2c322 VM |
2508 | return change_p; |
2509 | ||
bd3d34d4 RS |
2510 | /* Any index existed before LRA started, so we can assume that the |
2511 | presence and shape of the index is valid. */ | |
55a2c322 | 2512 | push_to_sequence (*before); |
2c62cbaa | 2513 | lra_assert (ad.disp == ad.disp_term); |
277f65de | 2514 | if (ad.base == NULL) |
55a2c322 | 2515 | { |
277f65de | 2516 | if (ad.index == NULL) |
55a2c322 VM |
2517 | { |
2518 | int code = -1; | |
277f65de RS |
2519 | enum reg_class cl = base_reg_class (ad.mode, ad.as, |
2520 | SCRATCH, SCRATCH); | |
2c62cbaa | 2521 | rtx addr = *ad.inner; |
277f65de | 2522 | |
2c62cbaa | 2523 | new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "addr"); |
55a2c322 VM |
2524 | #ifdef HAVE_lo_sum |
2525 | { | |
2526 | rtx insn; | |
2527 | rtx last = get_last_insn (); | |
2528 | ||
2c62cbaa | 2529 | /* addr => lo_sum (new_base, addr), case (2) above. */ |
55a2c322 VM |
2530 | insn = emit_insn (gen_rtx_SET |
2531 | (VOIDmode, new_reg, | |
2c62cbaa | 2532 | gen_rtx_HIGH (Pmode, copy_rtx (addr)))); |
55a2c322 VM |
2533 | code = recog_memoized (insn); |
2534 | if (code >= 0) | |
2535 | { | |
2c62cbaa | 2536 | *ad.inner = gen_rtx_LO_SUM (Pmode, new_reg, addr); |
277f65de | 2537 | if (! valid_address_p (ad.mode, *ad.outer, ad.as)) |
55a2c322 | 2538 | { |
2c62cbaa VM |
2539 | /* Try to put lo_sum into register. */ |
2540 | insn = emit_insn (gen_rtx_SET | |
2541 | (VOIDmode, new_reg, | |
2542 | gen_rtx_LO_SUM (Pmode, new_reg, addr))); | |
2543 | code = recog_memoized (insn); | |
2544 | if (code >= 0) | |
2545 | { | |
2546 | *ad.inner = new_reg; | |
2547 | if (! valid_address_p (ad.mode, *ad.outer, ad.as)) | |
2548 | { | |
2549 | *ad.inner = addr; | |
2550 | code = -1; | |
2551 | } | |
2552 | } | |
2553 | ||
55a2c322 VM |
2554 | } |
2555 | } | |
2556 | if (code < 0) | |
2557 | delete_insns_since (last); | |
2558 | } | |
2559 | #endif | |
2560 | if (code < 0) | |
2561 | { | |
2c62cbaa VM |
2562 | /* addr => new_base, case (2) above. */ |
2563 | lra_emit_move (new_reg, addr); | |
2564 | *ad.inner = new_reg; | |
55a2c322 VM |
2565 | } |
2566 | } | |
2567 | else | |
2568 | { | |
bd3d34d4 RS |
2569 | /* index * scale + disp => new base + index * scale, |
2570 | case (1) above. */ | |
277f65de RS |
2571 | enum reg_class cl = base_reg_class (ad.mode, ad.as, PLUS, |
2572 | GET_CODE (*ad.index)); | |
55a2c322 VM |
2573 | |
2574 | lra_assert (INDEX_REG_CLASS != NO_REGS); | |
2575 | new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "disp"); | |
277f65de RS |
2576 | lra_emit_move (new_reg, *ad.disp); |
2577 | *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), | |
2578 | new_reg, *ad.index); | |
55a2c322 VM |
2579 | } |
2580 | } | |
277f65de | 2581 | else if (ad.index == NULL) |
55a2c322 | 2582 | { |
5a107a0f VM |
2583 | int regno; |
2584 | enum reg_class cl; | |
2585 | rtx set, insns, last_insn; | |
bd3d34d4 | 2586 | /* base + disp => new base, cases (1) and (3) above. */ |
55a2c322 VM |
2587 | /* Another option would be to reload the displacement into an |
2588 | index register. However, postreload has code to optimize | |
2589 | address reloads that have the same base and different | |
2590 | displacements, so reloading into an index register would | |
2591 | not necessarily be a win. */ | |
5a107a0f | 2592 | start_sequence (); |
277f65de | 2593 | new_reg = base_plus_disp_to_reg (&ad); |
5a107a0f VM |
2594 | insns = get_insns (); |
2595 | last_insn = get_last_insn (); | |
2596 | /* If we generated at least two insns, try last insn source as | |
2597 | an address. If we succeed, we generate one less insn. */ | |
2598 | if (last_insn != insns && (set = single_set (last_insn)) != NULL_RTX | |
2599 | && GET_CODE (SET_SRC (set)) == PLUS | |
2600 | && REG_P (XEXP (SET_SRC (set), 0)) | |
2601 | && CONSTANT_P (XEXP (SET_SRC (set), 1))) | |
2602 | { | |
2603 | *ad.inner = SET_SRC (set); | |
2604 | if (valid_address_p (ad.mode, *ad.outer, ad.as)) | |
2605 | { | |
2606 | *ad.base_term = XEXP (SET_SRC (set), 0); | |
2607 | *ad.disp_term = XEXP (SET_SRC (set), 1); | |
2608 | cl = base_reg_class (ad.mode, ad.as, ad.base_outer_code, | |
2609 | get_index_code (&ad)); | |
2610 | regno = REGNO (*ad.base_term); | |
2611 | if (regno >= FIRST_PSEUDO_REGISTER | |
2612 | && cl != lra_get_allocno_class (regno)) | |
2613 | change_class (regno, cl, " Change", true); | |
2614 | new_reg = SET_SRC (set); | |
2615 | delete_insns_since (PREV_INSN (last_insn)); | |
2616 | } | |
2617 | } | |
2618 | end_sequence (); | |
2619 | emit_insn (insns); | |
277f65de | 2620 | *ad.inner = new_reg; |
55a2c322 VM |
2621 | } |
2622 | else | |
2623 | { | |
bd3d34d4 RS |
2624 | /* base + scale * index + disp => new base + scale * index, |
2625 | case (1) above. */ | |
277f65de RS |
2626 | new_reg = base_plus_disp_to_reg (&ad); |
2627 | *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), | |
2628 | new_reg, *ad.index); | |
55a2c322 VM |
2629 | } |
2630 | *before = get_insns (); | |
2631 | end_sequence (); | |
2632 | return true; | |
2633 | } | |
2634 | ||
2635 | /* Emit insns to reload VALUE into a new register. VALUE is an | |
2636 | auto-increment or auto-decrement RTX whose operand is a register or | |
2637 | memory location; so reloading involves incrementing that location. | |
2638 | IN is either identical to VALUE, or some cheaper place to reload | |
2639 | value being incremented/decremented from. | |
2640 | ||
2641 | INC_AMOUNT is the number to increment or decrement by (always | |
2642 | positive and ignored for POST_MODIFY/PRE_MODIFY). | |
2643 | ||
2644 | Return pseudo containing the result. */ | |
2645 | static rtx | |
2646 | emit_inc (enum reg_class new_rclass, rtx in, rtx value, int inc_amount) | |
2647 | { | |
2648 | /* REG or MEM to be copied and incremented. */ | |
2649 | rtx incloc = XEXP (value, 0); | |
2650 | /* Nonzero if increment after copying. */ | |
2651 | int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC | |
2652 | || GET_CODE (value) == POST_MODIFY); | |
2653 | rtx last; | |
2654 | rtx inc; | |
2655 | rtx add_insn; | |
2656 | int code; | |
2657 | rtx real_in = in == value ? incloc : in; | |
2658 | rtx result; | |
2659 | bool plus_p = true; | |
2660 | ||
2661 | if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY) | |
2662 | { | |
2663 | lra_assert (GET_CODE (XEXP (value, 1)) == PLUS | |
2664 | || GET_CODE (XEXP (value, 1)) == MINUS); | |
2665 | lra_assert (rtx_equal_p (XEXP (XEXP (value, 1), 0), XEXP (value, 0))); | |
2666 | plus_p = GET_CODE (XEXP (value, 1)) == PLUS; | |
2667 | inc = XEXP (XEXP (value, 1), 1); | |
2668 | } | |
2669 | else | |
2670 | { | |
2671 | if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC) | |
2672 | inc_amount = -inc_amount; | |
2673 | ||
2674 | inc = GEN_INT (inc_amount); | |
2675 | } | |
2676 | ||
2677 | if (! post && REG_P (incloc)) | |
2678 | result = incloc; | |
2679 | else | |
2680 | result = lra_create_new_reg (GET_MODE (value), value, new_rclass, | |
2681 | "INC/DEC result"); | |
2682 | ||
2683 | if (real_in != result) | |
2684 | { | |
2685 | /* First copy the location to the result register. */ | |
2686 | lra_assert (REG_P (result)); | |
2687 | emit_insn (gen_move_insn (result, real_in)); | |
2688 | } | |
2689 | ||
2690 | /* We suppose that there are insns to add/sub with the constant | |
2691 | increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the | |
2692 | old reload worked with this assumption. If the assumption | |
2693 | becomes wrong, we should use approach in function | |
2694 | base_plus_disp_to_reg. */ | |
2695 | if (in == value) | |
2696 | { | |
2697 | /* See if we can directly increment INCLOC. */ | |
2698 | last = get_last_insn (); | |
2699 | add_insn = emit_insn (plus_p | |
2700 | ? gen_add2_insn (incloc, inc) | |
2701 | : gen_sub2_insn (incloc, inc)); | |
2702 | ||
2703 | code = recog_memoized (add_insn); | |
2704 | if (code >= 0) | |
2705 | { | |
2706 | if (! post && result != incloc) | |
2707 | emit_insn (gen_move_insn (result, incloc)); | |
2708 | return result; | |
2709 | } | |
2710 | delete_insns_since (last); | |
2711 | } | |
2712 | ||
2713 | /* If couldn't do the increment directly, must increment in RESULT. | |
2714 | The way we do this depends on whether this is pre- or | |
2715 | post-increment. For pre-increment, copy INCLOC to the reload | |
2716 | register, increment it there, then save back. */ | |
2717 | if (! post) | |
2718 | { | |
2719 | if (real_in != result) | |
2720 | emit_insn (gen_move_insn (result, real_in)); | |
2721 | if (plus_p) | |
2722 | emit_insn (gen_add2_insn (result, inc)); | |
2723 | else | |
2724 | emit_insn (gen_sub2_insn (result, inc)); | |
2725 | if (result != incloc) | |
2726 | emit_insn (gen_move_insn (incloc, result)); | |
2727 | } | |
2728 | else | |
2729 | { | |
2730 | /* Post-increment. | |
2731 | ||
2732 | Because this might be a jump insn or a compare, and because | |
2733 | RESULT may not be available after the insn in an input | |
2734 | reload, we must do the incrementing before the insn being | |
2735 | reloaded for. | |
2736 | ||
2737 | We have already copied IN to RESULT. Increment the copy in | |
2738 | RESULT, save that back, then decrement RESULT so it has | |
2739 | the original value. */ | |
2740 | if (plus_p) | |
2741 | emit_insn (gen_add2_insn (result, inc)); | |
2742 | else | |
2743 | emit_insn (gen_sub2_insn (result, inc)); | |
2744 | emit_insn (gen_move_insn (incloc, result)); | |
2745 | /* Restore non-modified value for the result. We prefer this | |
2746 | way because it does not require an additional hard | |
2747 | register. */ | |
2748 | if (plus_p) | |
2749 | { | |
2750 | if (CONST_INT_P (inc)) | |
2751 | emit_insn (gen_add2_insn (result, GEN_INT (-INTVAL (inc)))); | |
2752 | else | |
2753 | emit_insn (gen_sub2_insn (result, inc)); | |
2754 | } | |
2755 | else | |
2756 | emit_insn (gen_add2_insn (result, inc)); | |
2757 | } | |
2758 | return result; | |
2759 | } | |
2760 | ||
2c62cbaa VM |
2761 | /* Return true if the current move insn does not need processing as we |
2762 | already know that it satisfies its constraints. */ | |
2763 | static bool | |
2764 | simple_move_p (void) | |
2765 | { | |
2766 | rtx dest, src; | |
2767 | enum reg_class dclass, sclass; | |
2768 | ||
2769 | lra_assert (curr_insn_set != NULL_RTX); | |
2770 | dest = SET_DEST (curr_insn_set); | |
2771 | src = SET_SRC (curr_insn_set); | |
2772 | return ((dclass = get_op_class (dest)) != NO_REGS | |
2773 | && (sclass = get_op_class (src)) != NO_REGS | |
2774 | /* The backend guarantees that register moves of cost 2 | |
2775 | never need reloads. */ | |
2776 | && targetm.register_move_cost (GET_MODE (src), dclass, sclass) == 2); | |
2777 | } | |
2778 | ||
55a2c322 VM |
2779 | /* Swap operands NOP and NOP + 1. */ |
2780 | static inline void | |
2781 | swap_operands (int nop) | |
2782 | { | |
2783 | enum machine_mode mode = curr_operand_mode[nop]; | |
2784 | curr_operand_mode[nop] = curr_operand_mode[nop + 1]; | |
2785 | curr_operand_mode[nop + 1] = mode; | |
2786 | rtx x = *curr_id->operand_loc[nop]; | |
2787 | *curr_id->operand_loc[nop] = *curr_id->operand_loc[nop + 1]; | |
2788 | *curr_id->operand_loc[nop + 1] = x; | |
2789 | /* Swap the duplicates too. */ | |
2790 | lra_update_dup (curr_id, nop); | |
2791 | lra_update_dup (curr_id, nop + 1); | |
2792 | } | |
2793 | ||
2794 | /* Main entry point of the constraint code: search the body of the | |
2795 | current insn to choose the best alternative. It is mimicking insn | |
2796 | alternative cost calculation model of former reload pass. That is | |
2797 | because machine descriptions were written to use this model. This | |
2798 | model can be changed in future. Make commutative operand exchange | |
2799 | if it is chosen. | |
2800 | ||
2801 | Return true if some RTL changes happened during function call. */ | |
2802 | static bool | |
2803 | curr_insn_transform (void) | |
2804 | { | |
2805 | int i, j, k; | |
2806 | int n_operands; | |
2807 | int n_alternatives; | |
2808 | int commutative; | |
2809 | signed char goal_alt_matched[MAX_RECOG_OPERANDS][MAX_RECOG_OPERANDS]; | |
511dcace | 2810 | signed char match_inputs[MAX_RECOG_OPERANDS + 1]; |
55a2c322 VM |
2811 | rtx before, after; |
2812 | bool alt_p = false; | |
2813 | /* Flag that the insn has been changed through a transformation. */ | |
2814 | bool change_p; | |
2815 | bool sec_mem_p; | |
2816 | #ifdef SECONDARY_MEMORY_NEEDED | |
2817 | bool use_sec_mem_p; | |
2818 | #endif | |
2819 | int max_regno_before; | |
2820 | int reused_alternative_num; | |
2821 | ||
2c62cbaa VM |
2822 | curr_insn_set = single_set (curr_insn); |
2823 | if (curr_insn_set != NULL_RTX && simple_move_p ()) | |
2824 | return false; | |
2825 | ||
55a2c322 VM |
2826 | no_input_reloads_p = no_output_reloads_p = false; |
2827 | goal_alt_number = -1; | |
2c62cbaa | 2828 | change_p = sec_mem_p = false; |
55a2c322 VM |
2829 | /* JUMP_INSNs and CALL_INSNs are not allowed to have any output |
2830 | reloads; neither are insns that SET cc0. Insns that use CC0 are | |
2831 | not allowed to have any input reloads. */ | |
2832 | if (JUMP_P (curr_insn) || CALL_P (curr_insn)) | |
2833 | no_output_reloads_p = true; | |
2834 | ||
2835 | #ifdef HAVE_cc0 | |
2836 | if (reg_referenced_p (cc0_rtx, PATTERN (curr_insn))) | |
2837 | no_input_reloads_p = true; | |
2838 | if (reg_set_p (cc0_rtx, PATTERN (curr_insn))) | |
2839 | no_output_reloads_p = true; | |
2840 | #endif | |
2841 | ||
2842 | n_operands = curr_static_id->n_operands; | |
2843 | n_alternatives = curr_static_id->n_alternatives; | |
2844 | ||
2845 | /* Just return "no reloads" if insn has no operands with | |
2846 | constraints. */ | |
2847 | if (n_operands == 0 || n_alternatives == 0) | |
2848 | return false; | |
2849 | ||
2850 | max_regno_before = max_reg_num (); | |
2851 | ||
2852 | for (i = 0; i < n_operands; i++) | |
2853 | { | |
2854 | goal_alt_matched[i][0] = -1; | |
2855 | goal_alt_matches[i] = -1; | |
2856 | } | |
2857 | ||
2858 | commutative = curr_static_id->commutative; | |
2859 | ||
2860 | /* Now see what we need for pseudos that didn't get hard regs or got | |
2861 | the wrong kind of hard reg. For this, we must consider all the | |
2862 | operands together against the register constraints. */ | |
2863 | ||
821b7577 | 2864 | best_losers = best_overall = INT_MAX; |
36ff9dfb | 2865 | best_reload_sum = 0; |
55a2c322 VM |
2866 | |
2867 | curr_swapped = false; | |
2868 | goal_alt_swapped = false; | |
2869 | ||
2870 | /* Make equivalence substitution and memory subreg elimination | |
2871 | before address processing because an address legitimacy can | |
2872 | depend on memory mode. */ | |
2873 | for (i = 0; i < n_operands; i++) | |
2874 | { | |
2875 | rtx op = *curr_id->operand_loc[i]; | |
2876 | rtx subst, old = op; | |
2877 | bool op_change_p = false; | |
2878 | ||
2879 | if (GET_CODE (old) == SUBREG) | |
2880 | old = SUBREG_REG (old); | |
2881 | subst = get_equiv_substitution (old); | |
2882 | if (subst != old) | |
2883 | { | |
2884 | subst = copy_rtx (subst); | |
2885 | lra_assert (REG_P (old)); | |
2886 | if (GET_CODE (op) == SUBREG) | |
2887 | SUBREG_REG (op) = subst; | |
2888 | else | |
2889 | *curr_id->operand_loc[i] = subst; | |
2890 | if (lra_dump_file != NULL) | |
2891 | { | |
2892 | fprintf (lra_dump_file, | |
2893 | "Changing pseudo %d in operand %i of insn %u on equiv ", | |
2894 | REGNO (old), i, INSN_UID (curr_insn)); | |
cfbeaedf | 2895 | dump_value_slim (lra_dump_file, subst, 1); |
55a2c322 VM |
2896 | fprintf (lra_dump_file, "\n"); |
2897 | } | |
2898 | op_change_p = change_p = true; | |
2899 | } | |
2900 | if (simplify_operand_subreg (i, GET_MODE (old)) || op_change_p) | |
2901 | { | |
2902 | change_p = true; | |
2903 | lra_update_dup (curr_id, i); | |
2904 | } | |
2905 | } | |
2906 | ||
2907 | /* Reload address registers and displacements. We do it before | |
2908 | finding an alternative because of memory constraints. */ | |
2909 | before = after = NULL_RTX; | |
2910 | for (i = 0; i < n_operands; i++) | |
2911 | if (! curr_static_id->operand[i].is_operator | |
2912 | && process_address (i, &before, &after)) | |
2913 | { | |
2914 | change_p = true; | |
2915 | lra_update_dup (curr_id, i); | |
2916 | } | |
f4eafc30 | 2917 | |
55a2c322 VM |
2918 | if (change_p) |
2919 | /* If we've changed the instruction then any alternative that | |
2920 | we chose previously may no longer be valid. */ | |
2921 | lra_set_used_insn_alternative (curr_insn, -1); | |
2922 | ||
2c62cbaa VM |
2923 | if (curr_insn_set != NULL_RTX |
2924 | && check_and_process_move (&change_p, &sec_mem_p)) | |
2925 | return change_p; | |
2926 | ||
55a2c322 VM |
2927 | try_swapped: |
2928 | ||
2929 | reused_alternative_num = curr_id->used_insn_alternative; | |
2930 | if (lra_dump_file != NULL && reused_alternative_num >= 0) | |
2931 | fprintf (lra_dump_file, "Reusing alternative %d for insn #%u\n", | |
2932 | reused_alternative_num, INSN_UID (curr_insn)); | |
2933 | ||
2934 | if (process_alt_operands (reused_alternative_num)) | |
2935 | alt_p = true; | |
2936 | ||
2937 | /* If insn is commutative (it's safe to exchange a certain pair of | |
2938 | operands) then we need to try each alternative twice, the second | |
2939 | time matching those two operands as if we had exchanged them. To | |
2940 | do this, really exchange them in operands. | |
2941 | ||
2942 | If we have just tried the alternatives the second time, return | |
2943 | operands to normal and drop through. */ | |
2944 | ||
2945 | if (reused_alternative_num < 0 && commutative >= 0) | |
2946 | { | |
2947 | curr_swapped = !curr_swapped; | |
2948 | if (curr_swapped) | |
2949 | { | |
2950 | swap_operands (commutative); | |
2951 | goto try_swapped; | |
2952 | } | |
2953 | else | |
2954 | swap_operands (commutative); | |
2955 | } | |
2956 | ||
55a2c322 VM |
2957 | if (! alt_p && ! sec_mem_p) |
2958 | { | |
2959 | /* No alternative works with reloads?? */ | |
2960 | if (INSN_CODE (curr_insn) >= 0) | |
2961 | fatal_insn ("unable to generate reloads for:", curr_insn); | |
2962 | error_for_asm (curr_insn, | |
2963 | "inconsistent operand constraints in an %<asm%>"); | |
2964 | /* Avoid further trouble with this insn. */ | |
2965 | PATTERN (curr_insn) = gen_rtx_USE (VOIDmode, const0_rtx); | |
2966 | lra_invalidate_insn_data (curr_insn); | |
2967 | return true; | |
2968 | } | |
2969 | ||
2970 | /* If the best alternative is with operands 1 and 2 swapped, swap | |
2971 | them. Update the operand numbers of any reloads already | |
2972 | pushed. */ | |
2973 | ||
2974 | if (goal_alt_swapped) | |
2975 | { | |
2976 | if (lra_dump_file != NULL) | |
2977 | fprintf (lra_dump_file, " Commutative operand exchange in insn %u\n", | |
2978 | INSN_UID (curr_insn)); | |
2979 | ||
2980 | /* Swap the duplicates too. */ | |
2981 | swap_operands (commutative); | |
2982 | change_p = true; | |
2983 | } | |
2984 | ||
2985 | #ifdef SECONDARY_MEMORY_NEEDED | |
2986 | /* Some target macros SECONDARY_MEMORY_NEEDED (e.g. x86) are defined | |
2987 | too conservatively. So we use the secondary memory only if there | |
2988 | is no any alternative without reloads. */ | |
2989 | use_sec_mem_p = false; | |
2990 | if (! alt_p) | |
2991 | use_sec_mem_p = true; | |
2992 | else if (sec_mem_p) | |
2993 | { | |
2994 | for (i = 0; i < n_operands; i++) | |
2995 | if (! goal_alt_win[i] && ! goal_alt_match_win[i]) | |
2996 | break; | |
2997 | use_sec_mem_p = i < n_operands; | |
2998 | } | |
2999 | ||
3000 | if (use_sec_mem_p) | |
3001 | { | |
89d56d79 | 3002 | rtx new_reg, src, dest, rld; |
66aa7879 | 3003 | enum machine_mode sec_mode, rld_mode; |
55a2c322 VM |
3004 | |
3005 | lra_assert (sec_mem_p); | |
66aa7879 VM |
3006 | lra_assert (curr_static_id->operand[0].type == OP_OUT |
3007 | && curr_static_id->operand[1].type == OP_IN); | |
3008 | dest = *curr_id->operand_loc[0]; | |
3009 | src = *curr_id->operand_loc[1]; | |
3010 | rld = (GET_MODE_SIZE (GET_MODE (dest)) <= GET_MODE_SIZE (GET_MODE (src)) | |
3011 | ? dest : src); | |
3012 | rld_mode = GET_MODE (rld); | |
55a2c322 | 3013 | #ifdef SECONDARY_MEMORY_NEEDED_MODE |
66aa7879 | 3014 | sec_mode = SECONDARY_MEMORY_NEEDED_MODE (rld_mode); |
55a2c322 | 3015 | #else |
66aa7879 | 3016 | sec_mode = rld_mode; |
55a2c322 VM |
3017 | #endif |
3018 | new_reg = lra_create_new_reg (sec_mode, NULL_RTX, | |
3019 | NO_REGS, "secondary"); | |
3020 | /* If the mode is changed, it should be wider. */ | |
66aa7879 | 3021 | lra_assert (GET_MODE_SIZE (sec_mode) >= GET_MODE_SIZE (rld_mode)); |
89d56d79 VM |
3022 | if (sec_mode != rld_mode) |
3023 | { | |
3024 | /* If the target says specifically to use another mode for | |
3025 | secondary memory moves we can not reuse the original | |
3026 | insn. */ | |
1ccd4874 VM |
3027 | after = emit_spill_move (false, new_reg, dest); |
3028 | lra_process_new_insns (curr_insn, NULL_RTX, after, | |
3029 | "Inserting the sec. move"); | |
3030 | /* We may have non null BEFORE here (e.g. after address | |
3031 | processing. */ | |
3032 | push_to_sequence (before); | |
3033 | before = emit_spill_move (true, new_reg, src); | |
3034 | emit_insn (before); | |
3035 | before = get_insns (); | |
3036 | end_sequence (); | |
3037 | lra_process_new_insns (curr_insn, before, NULL_RTX, "Changing on"); | |
3038 | lra_set_insn_deleted (curr_insn); | |
3039 | } | |
89d56d79 | 3040 | else if (dest == rld) |
1ccd4874 VM |
3041 | { |
3042 | *curr_id->operand_loc[0] = new_reg; | |
66aa7879 VM |
3043 | after = emit_spill_move (false, new_reg, dest); |
3044 | lra_process_new_insns (curr_insn, NULL_RTX, after, | |
3045 | "Inserting the sec. move"); | |
3046 | } | |
3047 | else | |
3048 | { | |
89d56d79 | 3049 | *curr_id->operand_loc[1] = new_reg; |
1ccd4874 VM |
3050 | /* See comments above. */ |
3051 | push_to_sequence (before); | |
66aa7879 | 3052 | before = emit_spill_move (true, new_reg, src); |
1ccd4874 VM |
3053 | emit_insn (before); |
3054 | before = get_insns (); | |
3055 | end_sequence (); | |
66aa7879 VM |
3056 | lra_process_new_insns (curr_insn, before, NULL_RTX, |
3057 | "Inserting the sec. move"); | |
3058 | } | |
3059 | lra_update_insn_regno_info (curr_insn); | |
55a2c322 VM |
3060 | return true; |
3061 | } | |
3062 | #endif | |
3063 | ||
3064 | lra_assert (goal_alt_number >= 0); | |
3065 | lra_set_used_insn_alternative (curr_insn, goal_alt_number); | |
3066 | ||
3067 | if (lra_dump_file != NULL) | |
3068 | { | |
3069 | const char *p; | |
3070 | ||
3071 | fprintf (lra_dump_file, " Choosing alt %d in insn %u:", | |
3072 | goal_alt_number, INSN_UID (curr_insn)); | |
3073 | for (i = 0; i < n_operands; i++) | |
3074 | { | |
3075 | p = (curr_static_id->operand_alternative | |
3076 | [goal_alt_number * n_operands + i].constraint); | |
3077 | if (*p == '\0') | |
3078 | continue; | |
3079 | fprintf (lra_dump_file, " (%d) ", i); | |
3080 | for (; *p != '\0' && *p != ',' && *p != '#'; p++) | |
3081 | fputc (*p, lra_dump_file); | |
3082 | } | |
36ff9dfb VM |
3083 | if (INSN_CODE (curr_insn) >= 0 |
3084 | && (p = get_insn_name (INSN_CODE (curr_insn))) != NULL) | |
3085 | fprintf (lra_dump_file, " {%s}", p); | |
3086 | fprintf (lra_dump_file, "\n"); | |
55a2c322 VM |
3087 | } |
3088 | ||
3089 | /* Right now, for any pair of operands I and J that are required to | |
3090 | match, with J < I, goal_alt_matches[I] is J. Add I to | |
3091 | goal_alt_matched[J]. */ | |
f4eafc30 | 3092 | |
55a2c322 VM |
3093 | for (i = 0; i < n_operands; i++) |
3094 | if ((j = goal_alt_matches[i]) >= 0) | |
3095 | { | |
3096 | for (k = 0; goal_alt_matched[j][k] >= 0; k++) | |
3097 | ; | |
3098 | /* We allow matching one output operand and several input | |
3099 | operands. */ | |
3100 | lra_assert (k == 0 | |
3101 | || (curr_static_id->operand[j].type == OP_OUT | |
3102 | && curr_static_id->operand[i].type == OP_IN | |
3103 | && (curr_static_id->operand | |
3104 | [goal_alt_matched[j][0]].type == OP_IN))); | |
3105 | goal_alt_matched[j][k] = i; | |
3106 | goal_alt_matched[j][k + 1] = -1; | |
3107 | } | |
f4eafc30 | 3108 | |
55a2c322 VM |
3109 | for (i = 0; i < n_operands; i++) |
3110 | goal_alt_win[i] |= goal_alt_match_win[i]; | |
f4eafc30 | 3111 | |
55a2c322 VM |
3112 | /* Any constants that aren't allowed and can't be reloaded into |
3113 | registers are here changed into memory references. */ | |
3114 | for (i = 0; i < n_operands; i++) | |
3115 | if (goal_alt_win[i]) | |
3116 | { | |
3117 | int regno; | |
3118 | enum reg_class new_class; | |
3119 | rtx reg = *curr_id->operand_loc[i]; | |
3120 | ||
3121 | if (GET_CODE (reg) == SUBREG) | |
3122 | reg = SUBREG_REG (reg); | |
f4eafc30 | 3123 | |
55a2c322 VM |
3124 | if (REG_P (reg) && (regno = REGNO (reg)) >= FIRST_PSEUDO_REGISTER) |
3125 | { | |
3126 | bool ok_p = in_class_p (reg, goal_alt[i], &new_class); | |
3127 | ||
3128 | if (new_class != NO_REGS && get_reg_class (regno) != new_class) | |
3129 | { | |
3130 | lra_assert (ok_p); | |
3131 | change_class (regno, new_class, " Change", true); | |
3132 | } | |
3133 | } | |
3134 | } | |
3135 | else | |
3136 | { | |
3137 | const char *constraint; | |
3138 | char c; | |
3139 | rtx op = *curr_id->operand_loc[i]; | |
3140 | rtx subreg = NULL_RTX; | |
3141 | enum machine_mode mode = curr_operand_mode[i]; | |
f4eafc30 | 3142 | |
55a2c322 VM |
3143 | if (GET_CODE (op) == SUBREG) |
3144 | { | |
3145 | subreg = op; | |
3146 | op = SUBREG_REG (op); | |
3147 | mode = GET_MODE (op); | |
3148 | } | |
f4eafc30 | 3149 | |
55a2c322 VM |
3150 | if (CONST_POOL_OK_P (mode, op) |
3151 | && ((targetm.preferred_reload_class | |
3152 | (op, (enum reg_class) goal_alt[i]) == NO_REGS) | |
3153 | || no_input_reloads_p)) | |
3154 | { | |
3155 | rtx tem = force_const_mem (mode, op); | |
f4eafc30 | 3156 | |
55a2c322 VM |
3157 | change_p = true; |
3158 | if (subreg != NULL_RTX) | |
3159 | tem = gen_rtx_SUBREG (mode, tem, SUBREG_BYTE (subreg)); | |
f4eafc30 | 3160 | |
55a2c322 VM |
3161 | *curr_id->operand_loc[i] = tem; |
3162 | lra_update_dup (curr_id, i); | |
3163 | process_address (i, &before, &after); | |
f4eafc30 | 3164 | |
55a2c322 VM |
3165 | /* If the alternative accepts constant pool refs directly |
3166 | there will be no reload needed at all. */ | |
3167 | if (subreg != NULL_RTX) | |
3168 | continue; | |
3169 | /* Skip alternatives before the one requested. */ | |
3170 | constraint = (curr_static_id->operand_alternative | |
3171 | [goal_alt_number * n_operands + i].constraint); | |
3172 | for (; | |
3173 | (c = *constraint) && c != ',' && c != '#'; | |
3174 | constraint += CONSTRAINT_LEN (c, constraint)) | |
3175 | { | |
3176 | if (c == TARGET_MEM_CONSTRAINT || c == 'o') | |
3177 | break; | |
3178 | #ifdef EXTRA_CONSTRAINT_STR | |
3179 | if (EXTRA_MEMORY_CONSTRAINT (c, constraint) | |
3180 | && EXTRA_CONSTRAINT_STR (tem, c, constraint)) | |
3181 | break; | |
3182 | #endif | |
3183 | } | |
3184 | if (c == '\0' || c == ',' || c == '#') | |
3185 | continue; | |
f4eafc30 | 3186 | |
55a2c322 VM |
3187 | goal_alt_win[i] = true; |
3188 | } | |
3189 | } | |
f4eafc30 | 3190 | |
55a2c322 VM |
3191 | for (i = 0; i < n_operands; i++) |
3192 | { | |
3193 | rtx old, new_reg; | |
3194 | rtx op = *curr_id->operand_loc[i]; | |
3195 | ||
3196 | if (goal_alt_win[i]) | |
3197 | { | |
3198 | if (goal_alt[i] == NO_REGS | |
3199 | && REG_P (op) | |
3200 | /* When we assign NO_REGS it means that we will not | |
3201 | assign a hard register to the scratch pseudo by | |
3202 | assigment pass and the scratch pseudo will be | |
3203 | spilled. Spilled scratch pseudos are transformed | |
3204 | back to scratches at the LRA end. */ | |
3205 | && lra_former_scratch_operand_p (curr_insn, i)) | |
deca73f5 VM |
3206 | { |
3207 | int regno = REGNO (op); | |
3208 | change_class (regno, NO_REGS, " Change", true); | |
3209 | if (lra_get_regno_hard_regno (regno) >= 0) | |
3210 | /* We don't have to mark all insn affected by the | |
3211 | spilled pseudo as there is only one such insn, the | |
3212 | current one. */ | |
3213 | reg_renumber[regno] = -1; | |
3214 | } | |
55a2c322 VM |
3215 | continue; |
3216 | } | |
f4eafc30 | 3217 | |
55a2c322 VM |
3218 | /* Operands that match previous ones have already been handled. */ |
3219 | if (goal_alt_matches[i] >= 0) | |
3220 | continue; | |
3221 | ||
3222 | /* We should not have an operand with a non-offsettable address | |
3223 | appearing where an offsettable address will do. It also may | |
3224 | be a case when the address should be special in other words | |
3225 | not a general one (e.g. it needs no index reg). */ | |
3226 | if (goal_alt_matched[i][0] == -1 && goal_alt_offmemok[i] && MEM_P (op)) | |
3227 | { | |
3228 | enum reg_class rclass; | |
3229 | rtx *loc = &XEXP (op, 0); | |
3230 | enum rtx_code code = GET_CODE (*loc); | |
3231 | ||
3232 | push_to_sequence (before); | |
3233 | rclass = base_reg_class (GET_MODE (op), MEM_ADDR_SPACE (op), | |
3234 | MEM, SCRATCH); | |
3235 | if (GET_RTX_CLASS (code) == RTX_AUTOINC) | |
3236 | new_reg = emit_inc (rclass, *loc, *loc, | |
3237 | /* This value does not matter for MODIFY. */ | |
3238 | GET_MODE_SIZE (GET_MODE (op))); | |
3239 | else if (get_reload_reg (OP_IN, Pmode, *loc, rclass, | |
3240 | "offsetable address", &new_reg)) | |
3241 | lra_emit_move (new_reg, *loc); | |
3242 | before = get_insns (); | |
3243 | end_sequence (); | |
3244 | *loc = new_reg; | |
3245 | lra_update_dup (curr_id, i); | |
3246 | } | |
3247 | else if (goal_alt_matched[i][0] == -1) | |
3248 | { | |
3249 | enum machine_mode mode; | |
3250 | rtx reg, *loc; | |
3251 | int hard_regno, byte; | |
3252 | enum op_type type = curr_static_id->operand[i].type; | |
3253 | ||
3254 | loc = curr_id->operand_loc[i]; | |
3255 | mode = curr_operand_mode[i]; | |
3256 | if (GET_CODE (*loc) == SUBREG) | |
3257 | { | |
3258 | reg = SUBREG_REG (*loc); | |
3259 | byte = SUBREG_BYTE (*loc); | |
3260 | if (REG_P (reg) | |
3261 | /* Strict_low_part requires reload the register not | |
3262 | the sub-register. */ | |
3263 | && (curr_static_id->operand[i].strict_low | |
3264 | || (GET_MODE_SIZE (mode) | |
3265 | <= GET_MODE_SIZE (GET_MODE (reg)) | |
3266 | && (hard_regno | |
3267 | = get_try_hard_regno (REGNO (reg))) >= 0 | |
3268 | && (simplify_subreg_regno | |
3269 | (hard_regno, | |
3270 | GET_MODE (reg), byte, mode) < 0) | |
3271 | && (goal_alt[i] == NO_REGS | |
3272 | || (simplify_subreg_regno | |
3273 | (ira_class_hard_regs[goal_alt[i]][0], | |
3274 | GET_MODE (reg), byte, mode) >= 0))))) | |
3275 | { | |
3276 | loc = &SUBREG_REG (*loc); | |
3277 | mode = GET_MODE (*loc); | |
3278 | } | |
3279 | } | |
3280 | old = *loc; | |
3281 | if (get_reload_reg (type, mode, old, goal_alt[i], "", &new_reg) | |
3282 | && type != OP_OUT) | |
3283 | { | |
3284 | push_to_sequence (before); | |
3285 | lra_emit_move (new_reg, old); | |
3286 | before = get_insns (); | |
3287 | end_sequence (); | |
3288 | } | |
3289 | *loc = new_reg; | |
3290 | if (type != OP_IN | |
3291 | && find_reg_note (curr_insn, REG_UNUSED, old) == NULL_RTX) | |
3292 | { | |
3293 | start_sequence (); | |
3294 | lra_emit_move (type == OP_INOUT ? copy_rtx (old) : old, new_reg); | |
3295 | emit_insn (after); | |
3296 | after = get_insns (); | |
3297 | end_sequence (); | |
3298 | *loc = new_reg; | |
3299 | } | |
3300 | for (j = 0; j < goal_alt_dont_inherit_ops_num; j++) | |
3301 | if (goal_alt_dont_inherit_ops[j] == i) | |
3302 | { | |
3303 | lra_set_regno_unique_value (REGNO (new_reg)); | |
3304 | break; | |
3305 | } | |
3306 | lra_update_dup (curr_id, i); | |
3307 | } | |
3308 | else if (curr_static_id->operand[i].type == OP_IN | |
3309 | && (curr_static_id->operand[goal_alt_matched[i][0]].type | |
3310 | == OP_OUT)) | |
3311 | { | |
511dcace VM |
3312 | /* generate reloads for input and matched outputs. */ |
3313 | match_inputs[0] = i; | |
3314 | match_inputs[1] = -1; | |
3315 | match_reload (goal_alt_matched[i][0], match_inputs, | |
55a2c322 VM |
3316 | goal_alt[i], &before, &after); |
3317 | } | |
3318 | else if (curr_static_id->operand[i].type == OP_OUT | |
3319 | && (curr_static_id->operand[goal_alt_matched[i][0]].type | |
3320 | == OP_IN)) | |
511dcace | 3321 | /* Generate reloads for output and matched inputs. */ |
55a2c322 | 3322 | match_reload (i, goal_alt_matched[i], goal_alt[i], &before, &after); |
511dcace VM |
3323 | else if (curr_static_id->operand[i].type == OP_IN |
3324 | && (curr_static_id->operand[goal_alt_matched[i][0]].type | |
3325 | == OP_IN)) | |
3326 | { | |
3327 | /* Generate reloads for matched inputs. */ | |
3328 | match_inputs[0] = i; | |
3329 | for (j = 0; (k = goal_alt_matched[i][j]) >= 0; j++) | |
3330 | match_inputs[j + 1] = k; | |
3331 | match_inputs[j + 1] = -1; | |
3332 | match_reload (-1, match_inputs, goal_alt[i], &before, &after); | |
3333 | } | |
55a2c322 VM |
3334 | else |
3335 | /* We must generate code in any case when function | |
3336 | process_alt_operands decides that it is possible. */ | |
3337 | gcc_unreachable (); | |
3338 | } | |
3339 | if (before != NULL_RTX || after != NULL_RTX | |
3340 | || max_regno_before != max_reg_num ()) | |
3341 | change_p = true; | |
3342 | if (change_p) | |
3343 | { | |
3344 | lra_update_operator_dups (curr_id); | |
3345 | /* Something changes -- process the insn. */ | |
3346 | lra_update_insn_regno_info (curr_insn); | |
3347 | } | |
3348 | lra_process_new_insns (curr_insn, before, after, "Inserting insn reload"); | |
3349 | return change_p; | |
3350 | } | |
3351 | ||
3352 | /* Return true if X is in LIST. */ | |
3353 | static bool | |
3354 | in_list_p (rtx x, rtx list) | |
3355 | { | |
3356 | for (; list != NULL_RTX; list = XEXP (list, 1)) | |
3357 | if (XEXP (list, 0) == x) | |
3358 | return true; | |
3359 | return false; | |
3360 | } | |
3361 | ||
3362 | /* Return true if X contains an allocatable hard register (if | |
3363 | HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */ | |
3364 | static bool | |
3365 | contains_reg_p (rtx x, bool hard_reg_p, bool spilled_p) | |
3366 | { | |
3367 | int i, j; | |
3368 | const char *fmt; | |
3369 | enum rtx_code code; | |
3370 | ||
3371 | code = GET_CODE (x); | |
3372 | if (REG_P (x)) | |
3373 | { | |
3374 | int regno = REGNO (x); | |
3375 | HARD_REG_SET alloc_regs; | |
3376 | ||
3377 | if (hard_reg_p) | |
3378 | { | |
3379 | if (regno >= FIRST_PSEUDO_REGISTER) | |
3380 | regno = lra_get_regno_hard_regno (regno); | |
3381 | if (regno < 0) | |
3382 | return false; | |
3383 | COMPL_HARD_REG_SET (alloc_regs, lra_no_alloc_regs); | |
3384 | return overlaps_hard_reg_set_p (alloc_regs, GET_MODE (x), regno); | |
3385 | } | |
3386 | else | |
3387 | { | |
3388 | if (regno < FIRST_PSEUDO_REGISTER) | |
3389 | return false; | |
3390 | if (! spilled_p) | |
3391 | return true; | |
3392 | return lra_get_regno_hard_regno (regno) < 0; | |
3393 | } | |
3394 | } | |
3395 | fmt = GET_RTX_FORMAT (code); | |
3396 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3397 | { | |
3398 | if (fmt[i] == 'e') | |
3399 | { | |
3400 | if (contains_reg_p (XEXP (x, i), hard_reg_p, spilled_p)) | |
3401 | return true; | |
3402 | } | |
3403 | else if (fmt[i] == 'E') | |
3404 | { | |
3405 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
3406 | if (contains_reg_p (XVECEXP (x, i, j), hard_reg_p, spilled_p)) | |
3407 | return true; | |
3408 | } | |
3409 | } | |
3410 | return false; | |
3411 | } | |
3412 | ||
28430b2e VM |
3413 | /* Process all regs in location *LOC and change them on equivalent |
3414 | substitution. Return true if any change was done. */ | |
55a2c322 | 3415 | static bool |
28430b2e | 3416 | loc_equivalence_change_p (rtx *loc) |
55a2c322 VM |
3417 | { |
3418 | rtx subst, reg, x = *loc; | |
3419 | bool result = false; | |
3420 | enum rtx_code code = GET_CODE (x); | |
3421 | const char *fmt; | |
3422 | int i, j; | |
3423 | ||
3424 | if (code == SUBREG) | |
3425 | { | |
3426 | reg = SUBREG_REG (x); | |
3427 | if ((subst = get_equiv_substitution (reg)) != reg | |
3428 | && GET_MODE (subst) == VOIDmode) | |
3429 | { | |
3430 | /* We cannot reload debug location. Simplify subreg here | |
3431 | while we know the inner mode. */ | |
3432 | *loc = simplify_gen_subreg (GET_MODE (x), subst, | |
3433 | GET_MODE (reg), SUBREG_BYTE (x)); | |
3434 | return true; | |
3435 | } | |
3436 | } | |
3437 | if (code == REG && (subst = get_equiv_substitution (x)) != x) | |
3438 | { | |
3439 | *loc = subst; | |
3440 | return true; | |
3441 | } | |
3442 | ||
3443 | /* Scan all the operand sub-expressions. */ | |
3444 | fmt = GET_RTX_FORMAT (code); | |
3445 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3446 | { | |
3447 | if (fmt[i] == 'e') | |
28430b2e | 3448 | result = loc_equivalence_change_p (&XEXP (x, i)) || result; |
55a2c322 VM |
3449 | else if (fmt[i] == 'E') |
3450 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
3451 | result | |
28430b2e | 3452 | = loc_equivalence_change_p (&XVECEXP (x, i, j)) || result; |
55a2c322 VM |
3453 | } |
3454 | return result; | |
3455 | } | |
3456 | ||
d0608e59 JJ |
3457 | /* Similar to loc_equivalence_change_p, but for use as |
3458 | simplify_replace_fn_rtx callback. */ | |
3459 | static rtx | |
3460 | loc_equivalence_callback (rtx loc, const_rtx, void *) | |
3461 | { | |
3462 | if (!REG_P (loc)) | |
3463 | return NULL_RTX; | |
3464 | ||
3465 | rtx subst = get_equiv_substitution (loc); | |
3466 | if (subst != loc) | |
3467 | return subst; | |
3468 | ||
3469 | return NULL_RTX; | |
3470 | } | |
3471 | ||
55a2c322 VM |
3472 | /* Maximum number of generated reload insns per an insn. It is for |
3473 | preventing this pass cycling in a bug case. */ | |
3474 | #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS | |
3475 | ||
3476 | /* The current iteration number of this LRA pass. */ | |
3477 | int lra_constraint_iter; | |
3478 | ||
3479 | /* The current iteration number of this LRA pass after the last spill | |
3480 | pass. */ | |
3481 | int lra_constraint_iter_after_spill; | |
3482 | ||
3483 | /* True if we substituted equiv which needs checking register | |
3484 | allocation correctness because the equivalent value contains | |
3485 | allocatable hard registers or when we restore multi-register | |
3486 | pseudo. */ | |
3487 | bool lra_risky_transformations_p; | |
3488 | ||
3489 | /* Return true if REGNO is referenced in more than one block. */ | |
3490 | static bool | |
3491 | multi_block_pseudo_p (int regno) | |
3492 | { | |
3493 | basic_block bb = NULL; | |
3494 | unsigned int uid; | |
3495 | bitmap_iterator bi; | |
f4eafc30 | 3496 | |
55a2c322 VM |
3497 | if (regno < FIRST_PSEUDO_REGISTER) |
3498 | return false; | |
f4eafc30 | 3499 | |
55a2c322 VM |
3500 | EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi) |
3501 | if (bb == NULL) | |
3502 | bb = BLOCK_FOR_INSN (lra_insn_recog_data[uid]->insn); | |
3503 | else if (BLOCK_FOR_INSN (lra_insn_recog_data[uid]->insn) != bb) | |
3504 | return true; | |
3505 | return false; | |
3506 | } | |
3507 | ||
1966c91b VM |
3508 | /* Return true if LIST contains a deleted insn. */ |
3509 | static bool | |
3510 | contains_deleted_insn_p (rtx list) | |
3511 | { | |
3512 | for (; list != NULL_RTX; list = XEXP (list, 1)) | |
3513 | if (NOTE_P (XEXP (list, 0)) | |
3514 | && NOTE_KIND (XEXP (list, 0)) == NOTE_INSN_DELETED) | |
3515 | return true; | |
3516 | return false; | |
3517 | } | |
3518 | ||
55a2c322 VM |
3519 | /* Return true if X contains a pseudo dying in INSN. */ |
3520 | static bool | |
3521 | dead_pseudo_p (rtx x, rtx insn) | |
3522 | { | |
3523 | int i, j; | |
3524 | const char *fmt; | |
3525 | enum rtx_code code; | |
3526 | ||
3527 | if (REG_P (x)) | |
3528 | return (insn != NULL_RTX | |
3529 | && find_regno_note (insn, REG_DEAD, REGNO (x)) != NULL_RTX); | |
3530 | code = GET_CODE (x); | |
3531 | fmt = GET_RTX_FORMAT (code); | |
3532 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3533 | { | |
3534 | if (fmt[i] == 'e') | |
3535 | { | |
3536 | if (dead_pseudo_p (XEXP (x, i), insn)) | |
3537 | return true; | |
3538 | } | |
3539 | else if (fmt[i] == 'E') | |
3540 | { | |
3541 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
3542 | if (dead_pseudo_p (XVECEXP (x, i, j), insn)) | |
3543 | return true; | |
3544 | } | |
3545 | } | |
3546 | return false; | |
3547 | } | |
3548 | ||
3549 | /* Return true if INSN contains a dying pseudo in INSN right hand | |
3550 | side. */ | |
3551 | static bool | |
3552 | insn_rhs_dead_pseudo_p (rtx insn) | |
3553 | { | |
3554 | rtx set = single_set (insn); | |
3555 | ||
3556 | gcc_assert (set != NULL); | |
3557 | return dead_pseudo_p (SET_SRC (set), insn); | |
3558 | } | |
3559 | ||
3560 | /* Return true if any init insn of REGNO contains a dying pseudo in | |
3561 | insn right hand side. */ | |
3562 | static bool | |
3563 | init_insn_rhs_dead_pseudo_p (int regno) | |
3564 | { | |
3565 | rtx insns = ira_reg_equiv[regno].init_insns; | |
3566 | ||
3567 | if (insns == NULL) | |
3568 | return false; | |
3569 | if (INSN_P (insns)) | |
3570 | return insn_rhs_dead_pseudo_p (insns); | |
3571 | for (; insns != NULL_RTX; insns = XEXP (insns, 1)) | |
3572 | if (insn_rhs_dead_pseudo_p (XEXP (insns, 0))) | |
3573 | return true; | |
3574 | return false; | |
3575 | } | |
3576 | ||
3577 | /* Entry function of LRA constraint pass. Return true if the | |
3578 | constraint pass did change the code. */ | |
3579 | bool | |
3580 | lra_constraints (bool first_p) | |
3581 | { | |
3582 | bool changed_p; | |
3583 | int i, hard_regno, new_insns_num; | |
6cd1dd26 VM |
3584 | unsigned int min_len, new_min_len, uid; |
3585 | rtx set, x, reg, dest_reg; | |
55a2c322 | 3586 | basic_block last_bb; |
6cd1dd26 VM |
3587 | bitmap_head equiv_insn_bitmap; |
3588 | bitmap_iterator bi; | |
55a2c322 VM |
3589 | |
3590 | lra_constraint_iter++; | |
3591 | if (lra_dump_file != NULL) | |
3592 | fprintf (lra_dump_file, "\n********** Local #%d: **********\n\n", | |
3593 | lra_constraint_iter); | |
3594 | lra_constraint_iter_after_spill++; | |
8e3a4869 | 3595 | if (lra_constraint_iter_after_spill > LRA_MAX_CONSTRAINT_ITERATION_NUMBER) |
55a2c322 VM |
3596 | internal_error |
3597 | ("Maximum number of LRA constraint passes is achieved (%d)\n", | |
8e3a4869 | 3598 | LRA_MAX_CONSTRAINT_ITERATION_NUMBER); |
55a2c322 VM |
3599 | changed_p = false; |
3600 | lra_risky_transformations_p = false; | |
3601 | new_insn_uid_start = get_max_uid (); | |
3602 | new_regno_start = first_p ? lra_constraint_new_regno_start : max_reg_num (); | |
6cd1dd26 | 3603 | bitmap_initialize (&equiv_insn_bitmap, ®_obstack); |
55a2c322 VM |
3604 | for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++) |
3605 | if (lra_reg_info[i].nrefs != 0) | |
3606 | { | |
3607 | ira_reg_equiv[i].profitable_p = true; | |
6cd1dd26 | 3608 | reg = regno_reg_rtx[i]; |
55a2c322 VM |
3609 | if ((hard_regno = lra_get_regno_hard_regno (i)) >= 0) |
3610 | { | |
9011b0f6 | 3611 | int j, nregs; |
f4eafc30 | 3612 | |
9011b0f6 | 3613 | nregs = hard_regno_nregs[hard_regno][lra_reg_info[i].biggest_mode]; |
55a2c322 VM |
3614 | for (j = 0; j < nregs; j++) |
3615 | df_set_regs_ever_live (hard_regno + j, true); | |
3616 | } | |
6cd1dd26 | 3617 | else if ((x = get_equiv_substitution (reg)) != reg) |
55a2c322 VM |
3618 | { |
3619 | bool pseudo_p = contains_reg_p (x, false, false); | |
5a107a0f | 3620 | rtx set, insns; |
55a2c322 | 3621 | |
1966c91b VM |
3622 | /* After RTL transformation, we can not guarantee that |
3623 | pseudo in the substitution was not reloaded which might | |
3624 | make equivalence invalid. For example, in reverse | |
3625 | equiv of p0 | |
3626 | ||
3627 | p0 <- ... | |
3628 | ... | |
3629 | equiv_mem <- p0 | |
3630 | ||
3631 | the memory address register was reloaded before the 2nd | |
3632 | insn. */ | |
3633 | if ((! first_p && pseudo_p) | |
3634 | /* We don't use DF for compilation speed sake. So it | |
3635 | is problematic to update live info when we use an | |
3636 | equivalence containing pseudos in more than one | |
3637 | BB. */ | |
3638 | || (pseudo_p && multi_block_pseudo_p (i)) | |
3639 | /* If an init insn was deleted for some reason, cancel | |
3640 | the equiv. We could update the equiv insns after | |
3641 | transformations including an equiv insn deletion | |
3642 | but it is not worthy as such cases are extremely | |
3643 | rare. */ | |
3644 | || contains_deleted_insn_p (ira_reg_equiv[i].init_insns) | |
55a2c322 VM |
3645 | /* If it is not a reverse equivalence, we check that a |
3646 | pseudo in rhs of the init insn is not dying in the | |
3647 | insn. Otherwise, the live info at the beginning of | |
3648 | the corresponding BB might be wrong after we | |
3649 | removed the insn. When the equiv can be a | |
3650 | constant, the right hand side of the init insn can | |
3651 | be a pseudo. */ | |
5a107a0f VM |
3652 | || (! ((insns = ira_reg_equiv[i].init_insns) != NULL_RTX |
3653 | && INSN_P (XEXP (insns, 0)) | |
3654 | && XEXP (insns, 1) == NULL_RTX | |
3655 | && (set = single_set (XEXP (insns, 0))) != NULL_RTX | |
3656 | && REG_P (SET_SRC (set)) | |
3657 | && (int) REGNO (SET_SRC (set)) == i) | |
b28ece32 VM |
3658 | && init_insn_rhs_dead_pseudo_p (i)) |
3659 | /* Prevent access beyond equivalent memory for | |
3660 | paradoxical subregs. */ | |
3661 | || (MEM_P (x) | |
3662 | && (GET_MODE_SIZE (lra_reg_info[i].biggest_mode) | |
3663 | > GET_MODE_SIZE (GET_MODE (x))))) | |
55a2c322 | 3664 | ira_reg_equiv[i].defined_p = false; |
55a2c322 VM |
3665 | if (contains_reg_p (x, false, true)) |
3666 | ira_reg_equiv[i].profitable_p = false; | |
6cd1dd26 VM |
3667 | if (get_equiv_substitution (reg) != reg) |
3668 | bitmap_ior_into (&equiv_insn_bitmap, &lra_reg_info[i].insn_bitmap); | |
55a2c322 VM |
3669 | } |
3670 | } | |
6cd1dd26 VM |
3671 | /* We should add all insns containing pseudos which should be |
3672 | substituted by their equivalences. */ | |
3673 | EXECUTE_IF_SET_IN_BITMAP (&equiv_insn_bitmap, 0, uid, bi) | |
3674 | lra_push_insn_by_uid (uid); | |
55a2c322 VM |
3675 | lra_eliminate (false); |
3676 | min_len = lra_insn_stack_length (); | |
3677 | new_insns_num = 0; | |
3678 | last_bb = NULL; | |
3679 | changed_p = false; | |
3680 | while ((new_min_len = lra_insn_stack_length ()) != 0) | |
3681 | { | |
3682 | curr_insn = lra_pop_insn (); | |
3683 | --new_min_len; | |
f4eafc30 | 3684 | curr_bb = BLOCK_FOR_INSN (curr_insn); |
55a2c322 VM |
3685 | if (curr_bb != last_bb) |
3686 | { | |
3687 | last_bb = curr_bb; | |
3688 | bb_reload_num = lra_curr_reload_num; | |
3689 | } | |
3690 | if (min_len > new_min_len) | |
3691 | { | |
3692 | min_len = new_min_len; | |
3693 | new_insns_num = 0; | |
3694 | } | |
3695 | if (new_insns_num > MAX_RELOAD_INSNS_NUMBER) | |
3696 | internal_error | |
3697 | ("Max. number of generated reload insns per insn is achieved (%d)\n", | |
3698 | MAX_RELOAD_INSNS_NUMBER); | |
3699 | new_insns_num++; | |
3700 | if (DEBUG_INSN_P (curr_insn)) | |
3701 | { | |
3702 | /* We need to check equivalence in debug insn and change | |
3703 | pseudo to the equivalent value if necessary. */ | |
3704 | curr_id = lra_get_insn_recog_data (curr_insn); | |
d0608e59 | 3705 | if (bitmap_bit_p (&equiv_insn_bitmap, INSN_UID (curr_insn))) |
4d64ce5c | 3706 | { |
d0608e59 JJ |
3707 | rtx old = *curr_id->operand_loc[0]; |
3708 | *curr_id->operand_loc[0] | |
3709 | = simplify_replace_fn_rtx (old, NULL_RTX, | |
3710 | loc_equivalence_callback, NULL); | |
3711 | if (old != *curr_id->operand_loc[0]) | |
3712 | { | |
3713 | lra_update_insn_regno_info (curr_insn); | |
3714 | changed_p = true; | |
3715 | } | |
4d64ce5c | 3716 | } |
55a2c322 VM |
3717 | } |
3718 | else if (INSN_P (curr_insn)) | |
3719 | { | |
3720 | if ((set = single_set (curr_insn)) != NULL_RTX) | |
3721 | { | |
3722 | dest_reg = SET_DEST (set); | |
3723 | /* The equivalence pseudo could be set up as SUBREG in a | |
3724 | case when it is a call restore insn in a mode | |
3725 | different from the pseudo mode. */ | |
3726 | if (GET_CODE (dest_reg) == SUBREG) | |
3727 | dest_reg = SUBREG_REG (dest_reg); | |
3728 | if ((REG_P (dest_reg) | |
3729 | && (x = get_equiv_substitution (dest_reg)) != dest_reg | |
5a107a0f VM |
3730 | /* Check that this is actually an insn setting up |
3731 | the equivalence. */ | |
3732 | && (in_list_p (curr_insn, | |
3733 | ira_reg_equiv | |
3734 | [REGNO (dest_reg)].init_insns) | |
3735 | /* Init insns may contain not all insns setting | |
3736 | up equivalence as we have live range | |
3737 | splitting. So here we use another condition | |
3738 | to check insn setting up the equivalence | |
3739 | which should be removed, e.g. in case when | |
3740 | the equivalence is a constant. */ | |
3741 | || ! MEM_P (x)) | |
55a2c322 VM |
3742 | /* Remove insns which set up a pseudo whose value |
3743 | can not be changed. Such insns might be not in | |
3744 | init_insns because we don't update equiv data | |
3745 | during insn transformations. | |
5a107a0f | 3746 | |
55a2c322 VM |
3747 | As an example, let suppose that a pseudo got |
3748 | hard register and on the 1st pass was not | |
3749 | changed to equivalent constant. We generate an | |
3750 | additional insn setting up the pseudo because of | |
3751 | secondary memory movement. Then the pseudo is | |
3752 | spilled and we use the equiv constant. In this | |
3753 | case we should remove the additional insn and | |
3754 | this insn is not init_insns list. */ | |
3755 | && (! MEM_P (x) || MEM_READONLY_P (x) | |
3756 | || in_list_p (curr_insn, | |
3757 | ira_reg_equiv | |
3758 | [REGNO (dest_reg)].init_insns))) | |
3759 | || (((x = get_equiv_substitution (SET_SRC (set))) | |
3760 | != SET_SRC (set)) | |
3761 | && in_list_p (curr_insn, | |
3762 | ira_reg_equiv | |
3763 | [REGNO (SET_SRC (set))].init_insns))) | |
3764 | { | |
3765 | /* This is equiv init insn of pseudo which did not get a | |
3766 | hard register -- remove the insn. */ | |
3767 | if (lra_dump_file != NULL) | |
3768 | { | |
3769 | fprintf (lra_dump_file, | |
3770 | " Removing equiv init insn %i (freq=%d)\n", | |
3771 | INSN_UID (curr_insn), | |
3772 | BLOCK_FOR_INSN (curr_insn)->frequency); | |
cfbeaedf | 3773 | dump_insn_slim (lra_dump_file, curr_insn); |
55a2c322 VM |
3774 | } |
3775 | if (contains_reg_p (x, true, false)) | |
3776 | lra_risky_transformations_p = true; | |
3777 | lra_set_insn_deleted (curr_insn); | |
3778 | continue; | |
3779 | } | |
3780 | } | |
3781 | curr_id = lra_get_insn_recog_data (curr_insn); | |
3782 | curr_static_id = curr_id->insn_static_data; | |
3783 | init_curr_insn_input_reloads (); | |
3784 | init_curr_operand_mode (); | |
3785 | if (curr_insn_transform ()) | |
3786 | changed_p = true; | |
28430b2e VM |
3787 | /* Check non-transformed insns too for equiv change as USE |
3788 | or CLOBBER don't need reloads but can contain pseudos | |
3789 | being changed on their equivalences. */ | |
3790 | else if (bitmap_bit_p (&equiv_insn_bitmap, INSN_UID (curr_insn)) | |
3791 | && loc_equivalence_change_p (&PATTERN (curr_insn))) | |
3792 | { | |
3793 | lra_update_insn_regno_info (curr_insn); | |
3794 | changed_p = true; | |
3795 | } | |
55a2c322 VM |
3796 | } |
3797 | } | |
28430b2e | 3798 | bitmap_clear (&equiv_insn_bitmap); |
55a2c322 VM |
3799 | /* If we used a new hard regno, changed_p should be true because the |
3800 | hard reg is assigned to a new pseudo. */ | |
3801 | #ifdef ENABLE_CHECKING | |
3802 | if (! changed_p) | |
3803 | { | |
3804 | for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++) | |
3805 | if (lra_reg_info[i].nrefs != 0 | |
3806 | && (hard_regno = lra_get_regno_hard_regno (i)) >= 0) | |
3807 | { | |
3808 | int j, nregs = hard_regno_nregs[hard_regno][PSEUDO_REGNO_MODE (i)]; | |
f4eafc30 | 3809 | |
55a2c322 VM |
3810 | for (j = 0; j < nregs; j++) |
3811 | lra_assert (df_regs_ever_live_p (hard_regno + j)); | |
3812 | } | |
3813 | } | |
3814 | #endif | |
3815 | return changed_p; | |
3816 | } | |
3817 | ||
3818 | /* Initiate the LRA constraint pass. It is done once per | |
3819 | function. */ | |
3820 | void | |
3821 | lra_constraints_init (void) | |
3822 | { | |
3823 | } | |
3824 | ||
3825 | /* Finalize the LRA constraint pass. It is done once per | |
3826 | function. */ | |
3827 | void | |
3828 | lra_constraints_finish (void) | |
3829 | { | |
3830 | } | |
3831 | ||
3832 | \f | |
3833 | ||
3834 | /* This page contains code to do inheritance/split | |
3835 | transformations. */ | |
3836 | ||
3837 | /* Number of reloads passed so far in current EBB. */ | |
3838 | static int reloads_num; | |
3839 | ||
3840 | /* Number of calls passed so far in current EBB. */ | |
3841 | static int calls_num; | |
3842 | ||
3843 | /* Current reload pseudo check for validity of elements in | |
3844 | USAGE_INSNS. */ | |
3845 | static int curr_usage_insns_check; | |
3846 | ||
3847 | /* Info about last usage of registers in EBB to do inheritance/split | |
3848 | transformation. Inheritance transformation is done from a spilled | |
3849 | pseudo and split transformations from a hard register or a pseudo | |
3850 | assigned to a hard register. */ | |
3851 | struct usage_insns | |
3852 | { | |
3853 | /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member | |
3854 | value INSNS is valid. The insns is chain of optional debug insns | |
1ccd4874 VM |
3855 | and a finishing non-debug insn using the corresponding reg. The |
3856 | value is also used to mark the registers which are set up in the | |
3857 | current insn. The negated insn uid is used for this. */ | |
55a2c322 VM |
3858 | int check; |
3859 | /* Value of global reloads_num at the last insn in INSNS. */ | |
3860 | int reloads_num; | |
3861 | /* Value of global reloads_nums at the last insn in INSNS. */ | |
3862 | int calls_num; | |
3863 | /* It can be true only for splitting. And it means that the restore | |
3864 | insn should be put after insn given by the following member. */ | |
3865 | bool after_p; | |
3866 | /* Next insns in the current EBB which use the original reg and the | |
3867 | original reg value is not changed between the current insn and | |
3868 | the next insns. In order words, e.g. for inheritance, if we need | |
3869 | to use the original reg value again in the next insns we can try | |
3870 | to use the value in a hard register from a reload insn of the | |
3871 | current insn. */ | |
3872 | rtx insns; | |
3873 | }; | |
3874 | ||
3875 | /* Map: regno -> corresponding pseudo usage insns. */ | |
3876 | static struct usage_insns *usage_insns; | |
3877 | ||
3878 | static void | |
3879 | setup_next_usage_insn (int regno, rtx insn, int reloads_num, bool after_p) | |
3880 | { | |
3881 | usage_insns[regno].check = curr_usage_insns_check; | |
3882 | usage_insns[regno].insns = insn; | |
3883 | usage_insns[regno].reloads_num = reloads_num; | |
3884 | usage_insns[regno].calls_num = calls_num; | |
3885 | usage_insns[regno].after_p = after_p; | |
3886 | } | |
3887 | ||
3888 | /* The function is used to form list REGNO usages which consists of | |
3889 | optional debug insns finished by a non-debug insn using REGNO. | |
3890 | RELOADS_NUM is current number of reload insns processed so far. */ | |
3891 | static void | |
3892 | add_next_usage_insn (int regno, rtx insn, int reloads_num) | |
3893 | { | |
3894 | rtx next_usage_insns; | |
f4eafc30 | 3895 | |
55a2c322 VM |
3896 | if (usage_insns[regno].check == curr_usage_insns_check |
3897 | && (next_usage_insns = usage_insns[regno].insns) != NULL_RTX | |
3898 | && DEBUG_INSN_P (insn)) | |
3899 | { | |
3900 | /* Check that we did not add the debug insn yet. */ | |
3901 | if (next_usage_insns != insn | |
3902 | && (GET_CODE (next_usage_insns) != INSN_LIST | |
3903 | || XEXP (next_usage_insns, 0) != insn)) | |
3904 | usage_insns[regno].insns = gen_rtx_INSN_LIST (VOIDmode, insn, | |
3905 | next_usage_insns); | |
3906 | } | |
3907 | else if (NONDEBUG_INSN_P (insn)) | |
3908 | setup_next_usage_insn (regno, insn, reloads_num, false); | |
3909 | else | |
3910 | usage_insns[regno].check = 0; | |
3911 | } | |
f4eafc30 | 3912 | |
55a2c322 VM |
3913 | /* Replace all references to register OLD_REGNO in *LOC with pseudo |
3914 | register NEW_REG. Return true if any change was made. */ | |
3915 | static bool | |
3916 | substitute_pseudo (rtx *loc, int old_regno, rtx new_reg) | |
3917 | { | |
3918 | rtx x = *loc; | |
3919 | bool result = false; | |
3920 | enum rtx_code code; | |
3921 | const char *fmt; | |
3922 | int i, j; | |
3923 | ||
3924 | if (x == NULL_RTX) | |
3925 | return false; | |
3926 | ||
3927 | code = GET_CODE (x); | |
3928 | if (code == REG && (int) REGNO (x) == old_regno) | |
3929 | { | |
3930 | enum machine_mode mode = GET_MODE (*loc); | |
3931 | enum machine_mode inner_mode = GET_MODE (new_reg); | |
3932 | ||
3933 | if (mode != inner_mode) | |
3934 | { | |
3935 | if (GET_MODE_SIZE (mode) >= GET_MODE_SIZE (inner_mode) | |
3936 | || ! SCALAR_INT_MODE_P (inner_mode)) | |
3937 | new_reg = gen_rtx_SUBREG (mode, new_reg, 0); | |
3938 | else | |
3939 | new_reg = gen_lowpart_SUBREG (mode, new_reg); | |
3940 | } | |
3941 | *loc = new_reg; | |
3942 | return true; | |
3943 | } | |
3944 | ||
3945 | /* Scan all the operand sub-expressions. */ | |
3946 | fmt = GET_RTX_FORMAT (code); | |
3947 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3948 | { | |
3949 | if (fmt[i] == 'e') | |
3950 | { | |
3951 | if (substitute_pseudo (&XEXP (x, i), old_regno, new_reg)) | |
3952 | result = true; | |
3953 | } | |
3954 | else if (fmt[i] == 'E') | |
3955 | { | |
3956 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
3957 | if (substitute_pseudo (&XVECEXP (x, i, j), old_regno, new_reg)) | |
3958 | result = true; | |
3959 | } | |
3960 | } | |
3961 | return result; | |
3962 | } | |
3963 | ||
bc3591eb VM |
3964 | /* Return first non-debug insn in list USAGE_INSNS. */ |
3965 | static rtx | |
3966 | skip_usage_debug_insns (rtx usage_insns) | |
3967 | { | |
3968 | rtx insn; | |
3969 | ||
3970 | /* Skip debug insns. */ | |
3971 | for (insn = usage_insns; | |
3972 | insn != NULL_RTX && GET_CODE (insn) == INSN_LIST; | |
3973 | insn = XEXP (insn, 1)) | |
3974 | ; | |
3975 | return insn; | |
3976 | } | |
3977 | ||
3978 | /* Return true if we need secondary memory moves for insn in | |
3979 | USAGE_INSNS after inserting inherited pseudo of class INHER_CL | |
3980 | into the insn. */ | |
3981 | static bool | |
fbebbadd JR |
3982 | check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED, |
3983 | rtx usage_insns ATTRIBUTE_UNUSED) | |
bc3591eb VM |
3984 | { |
3985 | #ifndef SECONDARY_MEMORY_NEEDED | |
3986 | return false; | |
3987 | #else | |
3988 | rtx insn, set, dest; | |
3989 | enum reg_class cl; | |
3990 | ||
3991 | if (inher_cl == ALL_REGS | |
3992 | || (insn = skip_usage_debug_insns (usage_insns)) == NULL_RTX) | |
3993 | return false; | |
3994 | lra_assert (INSN_P (insn)); | |
3995 | if ((set = single_set (insn)) == NULL_RTX || ! REG_P (SET_DEST (set))) | |
3996 | return false; | |
3997 | dest = SET_DEST (set); | |
3998 | if (! REG_P (dest)) | |
3999 | return false; | |
4000 | lra_assert (inher_cl != NO_REGS); | |
4001 | cl = get_reg_class (REGNO (dest)); | |
4002 | return (cl != NO_REGS && cl != ALL_REGS | |
4003 | && SECONDARY_MEMORY_NEEDED (inher_cl, cl, GET_MODE (dest))); | |
4004 | #endif | |
4005 | } | |
4006 | ||
55a2c322 VM |
4007 | /* Registers involved in inheritance/split in the current EBB |
4008 | (inheritance/split pseudos and original registers). */ | |
4009 | static bitmap_head check_only_regs; | |
4010 | ||
4011 | /* Do inheritance transformations for insn INSN, which defines (if | |
4012 | DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which | |
4013 | instruction in the EBB next uses ORIGINAL_REGNO; it has the same | |
4014 | form as the "insns" field of usage_insns. Return true if we | |
4015 | succeed in such transformation. | |
4016 | ||
4017 | The transformations look like: | |
4018 | ||
4019 | p <- ... i <- ... | |
4020 | ... p <- i (new insn) | |
4021 | ... => | |
4022 | <- ... p ... <- ... i ... | |
4023 | or | |
4024 | ... i <- p (new insn) | |
4025 | <- ... p ... <- ... i ... | |
4026 | ... => | |
4027 | <- ... p ... <- ... i ... | |
4028 | where p is a spilled original pseudo and i is a new inheritance pseudo. | |
f4eafc30 L |
4029 | |
4030 | ||
55a2c322 VM |
4031 | The inheritance pseudo has the smallest class of two classes CL and |
4032 | class of ORIGINAL REGNO. */ | |
4033 | static bool | |
4034 | inherit_reload_reg (bool def_p, int original_regno, | |
4035 | enum reg_class cl, rtx insn, rtx next_usage_insns) | |
4036 | { | |
4037 | enum reg_class rclass = lra_get_allocno_class (original_regno); | |
4038 | rtx original_reg = regno_reg_rtx[original_regno]; | |
4039 | rtx new_reg, new_insns, usage_insn; | |
4040 | ||
4041 | lra_assert (! usage_insns[original_regno].after_p); | |
4042 | if (lra_dump_file != NULL) | |
4043 | fprintf (lra_dump_file, | |
bc3591eb | 4044 | " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n"); |
55a2c322 VM |
4045 | if (! ira_reg_classes_intersect_p[cl][rclass]) |
4046 | { | |
4047 | if (lra_dump_file != NULL) | |
4048 | { | |
4049 | fprintf (lra_dump_file, | |
bc3591eb | 4050 | " Rejecting inheritance for %d " |
55a2c322 VM |
4051 | "because of disjoint classes %s and %s\n", |
4052 | original_regno, reg_class_names[cl], | |
4053 | reg_class_names[rclass]); | |
4054 | fprintf (lra_dump_file, | |
bc3591eb | 4055 | " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); |
55a2c322 VM |
4056 | } |
4057 | return false; | |
4058 | } | |
4059 | if ((ira_class_subset_p[cl][rclass] && cl != rclass) | |
4060 | /* We don't use a subset of two classes because it can be | |
4061 | NO_REGS. This transformation is still profitable in most | |
4062 | cases even if the classes are not intersected as register | |
4063 | move is probably cheaper than a memory load. */ | |
4064 | || ira_class_hard_regs_num[cl] < ira_class_hard_regs_num[rclass]) | |
4065 | { | |
4066 | if (lra_dump_file != NULL) | |
4067 | fprintf (lra_dump_file, " Use smallest class of %s and %s\n", | |
4068 | reg_class_names[cl], reg_class_names[rclass]); | |
f4eafc30 | 4069 | |
55a2c322 VM |
4070 | rclass = cl; |
4071 | } | |
66aa7879 | 4072 | if (check_secondary_memory_needed_p (rclass, next_usage_insns)) |
bc3591eb VM |
4073 | { |
4074 | /* Reject inheritance resulting in secondary memory moves. | |
4075 | Otherwise, there is a danger in LRA cycling. Also such | |
4076 | transformation will be unprofitable. */ | |
4077 | if (lra_dump_file != NULL) | |
4078 | { | |
4079 | rtx insn = skip_usage_debug_insns (next_usage_insns); | |
4080 | rtx set = single_set (insn); | |
4081 | ||
4082 | lra_assert (set != NULL_RTX); | |
4083 | ||
4084 | rtx dest = SET_DEST (set); | |
4085 | ||
4086 | lra_assert (REG_P (dest)); | |
4087 | fprintf (lra_dump_file, | |
4088 | " Rejecting inheritance for insn %d(%s)<-%d(%s) " | |
4089 | "as secondary mem is needed\n", | |
4090 | REGNO (dest), reg_class_names[get_reg_class (REGNO (dest))], | |
66aa7879 | 4091 | original_regno, reg_class_names[rclass]); |
bc3591eb VM |
4092 | fprintf (lra_dump_file, |
4093 | " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); | |
4094 | } | |
4095 | return false; | |
4096 | } | |
55a2c322 VM |
4097 | new_reg = lra_create_new_reg (GET_MODE (original_reg), original_reg, |
4098 | rclass, "inheritance"); | |
4099 | start_sequence (); | |
4100 | if (def_p) | |
4101 | emit_move_insn (original_reg, new_reg); | |
4102 | else | |
4103 | emit_move_insn (new_reg, original_reg); | |
4104 | new_insns = get_insns (); | |
4105 | end_sequence (); | |
4106 | if (NEXT_INSN (new_insns) != NULL_RTX) | |
4107 | { | |
4108 | if (lra_dump_file != NULL) | |
4109 | { | |
4110 | fprintf (lra_dump_file, | |
bc3591eb | 4111 | " Rejecting inheritance %d->%d " |
55a2c322 VM |
4112 | "as it results in 2 or more insns:\n", |
4113 | original_regno, REGNO (new_reg)); | |
cfbeaedf | 4114 | dump_rtl_slim (lra_dump_file, new_insns, NULL_RTX, -1, 0); |
55a2c322 VM |
4115 | fprintf (lra_dump_file, |
4116 | " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); | |
4117 | } | |
4118 | return false; | |
4119 | } | |
4120 | substitute_pseudo (&insn, original_regno, new_reg); | |
4121 | lra_update_insn_regno_info (insn); | |
4122 | if (! def_p) | |
4123 | /* We now have a new usage insn for original regno. */ | |
4124 | setup_next_usage_insn (original_regno, new_insns, reloads_num, false); | |
4125 | if (lra_dump_file != NULL) | |
bc3591eb | 4126 | fprintf (lra_dump_file, " Original reg change %d->%d (bb%d):\n", |
55a2c322 VM |
4127 | original_regno, REGNO (new_reg), BLOCK_FOR_INSN (insn)->index); |
4128 | lra_reg_info[REGNO (new_reg)].restore_regno = original_regno; | |
4129 | bitmap_set_bit (&check_only_regs, REGNO (new_reg)); | |
4130 | bitmap_set_bit (&check_only_regs, original_regno); | |
4131 | bitmap_set_bit (&lra_inheritance_pseudos, REGNO (new_reg)); | |
4132 | if (def_p) | |
4133 | lra_process_new_insns (insn, NULL_RTX, new_insns, | |
4134 | "Add original<-inheritance"); | |
4135 | else | |
4136 | lra_process_new_insns (insn, new_insns, NULL_RTX, | |
4137 | "Add inheritance<-original"); | |
4138 | while (next_usage_insns != NULL_RTX) | |
4139 | { | |
4140 | if (GET_CODE (next_usage_insns) != INSN_LIST) | |
4141 | { | |
4142 | usage_insn = next_usage_insns; | |
4143 | lra_assert (NONDEBUG_INSN_P (usage_insn)); | |
4144 | next_usage_insns = NULL; | |
4145 | } | |
4146 | else | |
4147 | { | |
4148 | usage_insn = XEXP (next_usage_insns, 0); | |
4149 | lra_assert (DEBUG_INSN_P (usage_insn)); | |
4150 | next_usage_insns = XEXP (next_usage_insns, 1); | |
4151 | } | |
4152 | substitute_pseudo (&usage_insn, original_regno, new_reg); | |
4153 | lra_update_insn_regno_info (usage_insn); | |
4154 | if (lra_dump_file != NULL) | |
4155 | { | |
4156 | fprintf (lra_dump_file, | |
4157 | " Inheritance reuse change %d->%d (bb%d):\n", | |
4158 | original_regno, REGNO (new_reg), | |
4159 | BLOCK_FOR_INSN (usage_insn)->index); | |
cfbeaedf | 4160 | dump_insn_slim (lra_dump_file, usage_insn); |
55a2c322 VM |
4161 | } |
4162 | } | |
4163 | if (lra_dump_file != NULL) | |
4164 | fprintf (lra_dump_file, | |
4165 | " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); | |
4166 | return true; | |
4167 | } | |
4168 | ||
4169 | /* Return true if we need a caller save/restore for pseudo REGNO which | |
4170 | was assigned to a hard register. */ | |
4171 | static inline bool | |
4172 | need_for_call_save_p (int regno) | |
4173 | { | |
4174 | lra_assert (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] >= 0); | |
4175 | return (usage_insns[regno].calls_num < calls_num | |
4176 | && (overlaps_hard_reg_set_p | |
4177 | (call_used_reg_set, | |
4178 | PSEUDO_REGNO_MODE (regno), reg_renumber[regno]))); | |
4179 | } | |
4180 | ||
4181 | /* Global registers occuring in the current EBB. */ | |
4182 | static bitmap_head ebb_global_regs; | |
4183 | ||
4184 | /* Return true if we need a split for hard register REGNO or pseudo | |
4185 | REGNO which was assigned to a hard register. | |
4186 | POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be | |
4187 | used for reloads since the EBB end. It is an approximation of the | |
4188 | used hard registers in the split range. The exact value would | |
4189 | require expensive calculations. If we were aggressive with | |
4190 | splitting because of the approximation, the split pseudo will save | |
4191 | the same hard register assignment and will be removed in the undo | |
4192 | pass. We still need the approximation because too aggressive | |
4193 | splitting would result in too inaccurate cost calculation in the | |
4194 | assignment pass because of too many generated moves which will be | |
4195 | probably removed in the undo pass. */ | |
4196 | static inline bool | |
4197 | need_for_split_p (HARD_REG_SET potential_reload_hard_regs, int regno) | |
4198 | { | |
4199 | int hard_regno = regno < FIRST_PSEUDO_REGISTER ? regno : reg_renumber[regno]; | |
4200 | ||
4201 | lra_assert (hard_regno >= 0); | |
4202 | return ((TEST_HARD_REG_BIT (potential_reload_hard_regs, hard_regno) | |
4203 | /* Don't split eliminable hard registers, otherwise we can | |
4204 | split hard registers like hard frame pointer, which | |
4205 | lives on BB start/end according to DF-infrastructure, | |
4206 | when there is a pseudo assigned to the register and | |
4207 | living in the same BB. */ | |
4208 | && (regno >= FIRST_PSEUDO_REGISTER | |
4209 | || ! TEST_HARD_REG_BIT (eliminable_regset, hard_regno)) | |
4210 | && ! TEST_HARD_REG_BIT (lra_no_alloc_regs, hard_regno) | |
4211 | /* We need at least 2 reloads to make pseudo splitting | |
4212 | profitable. We should provide hard regno splitting in | |
4213 | any case to solve 1st insn scheduling problem when | |
4214 | moving hard register definition up might result in | |
4215 | impossibility to find hard register for reload pseudo of | |
4216 | small register class. */ | |
4217 | && (usage_insns[regno].reloads_num | |
4218 | + (regno < FIRST_PSEUDO_REGISTER ? 0 : 2) < reloads_num) | |
4219 | && (regno < FIRST_PSEUDO_REGISTER | |
4220 | /* For short living pseudos, spilling + inheritance can | |
4221 | be considered a substitution for splitting. | |
4222 | Therefore we do not splitting for local pseudos. It | |
4223 | decreases also aggressiveness of splitting. The | |
4224 | minimal number of references is chosen taking into | |
4225 | account that for 2 references splitting has no sense | |
4226 | as we can just spill the pseudo. */ | |
4227 | || (regno >= FIRST_PSEUDO_REGISTER | |
4228 | && lra_reg_info[regno].nrefs > 3 | |
4229 | && bitmap_bit_p (&ebb_global_regs, regno)))) | |
4230 | || (regno >= FIRST_PSEUDO_REGISTER && need_for_call_save_p (regno))); | |
4231 | } | |
4232 | ||
4233 | /* Return class for the split pseudo created from original pseudo with | |
4234 | ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We | |
4235 | choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and | |
4236 | results in no secondary memory movements. */ | |
4237 | static enum reg_class | |
4238 | choose_split_class (enum reg_class allocno_class, | |
4239 | int hard_regno ATTRIBUTE_UNUSED, | |
4240 | enum machine_mode mode ATTRIBUTE_UNUSED) | |
4241 | { | |
4242 | #ifndef SECONDARY_MEMORY_NEEDED | |
4243 | return allocno_class; | |
4244 | #else | |
4245 | int i; | |
4246 | enum reg_class cl, best_cl = NO_REGS; | |
ef4dbe49 JR |
4247 | enum reg_class hard_reg_class ATTRIBUTE_UNUSED |
4248 | = REGNO_REG_CLASS (hard_regno); | |
f4eafc30 | 4249 | |
55a2c322 VM |
4250 | if (! SECONDARY_MEMORY_NEEDED (allocno_class, allocno_class, mode) |
4251 | && TEST_HARD_REG_BIT (reg_class_contents[allocno_class], hard_regno)) | |
4252 | return allocno_class; | |
4253 | for (i = 0; | |
4254 | (cl = reg_class_subclasses[allocno_class][i]) != LIM_REG_CLASSES; | |
4255 | i++) | |
4256 | if (! SECONDARY_MEMORY_NEEDED (cl, hard_reg_class, mode) | |
4257 | && ! SECONDARY_MEMORY_NEEDED (hard_reg_class, cl, mode) | |
4258 | && TEST_HARD_REG_BIT (reg_class_contents[cl], hard_regno) | |
4259 | && (best_cl == NO_REGS | |
4260 | || ira_class_hard_regs_num[best_cl] < ira_class_hard_regs_num[cl])) | |
4261 | best_cl = cl; | |
4262 | return best_cl; | |
4263 | #endif | |
4264 | } | |
4265 | ||
4266 | /* Do split transformations for insn INSN, which defines or uses | |
4267 | ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in | |
4268 | the EBB next uses ORIGINAL_REGNO; it has the same form as the | |
4269 | "insns" field of usage_insns. | |
4270 | ||
4271 | The transformations look like: | |
4272 | ||
4273 | p <- ... p <- ... | |
4274 | ... s <- p (new insn -- save) | |
4275 | ... => | |
4276 | ... p <- s (new insn -- restore) | |
4277 | <- ... p ... <- ... p ... | |
4278 | or | |
4279 | <- ... p ... <- ... p ... | |
4280 | ... s <- p (new insn -- save) | |
4281 | ... => | |
4282 | ... p <- s (new insn -- restore) | |
4283 | <- ... p ... <- ... p ... | |
4284 | ||
4285 | where p is an original pseudo got a hard register or a hard | |
4286 | register and s is a new split pseudo. The save is put before INSN | |
4287 | if BEFORE_P is true. Return true if we succeed in such | |
4288 | transformation. */ | |
4289 | static bool | |
4290 | split_reg (bool before_p, int original_regno, rtx insn, rtx next_usage_insns) | |
4291 | { | |
4292 | enum reg_class rclass; | |
4293 | rtx original_reg; | |
77bce07c | 4294 | int hard_regno, nregs; |
55a2c322 VM |
4295 | rtx new_reg, save, restore, usage_insn; |
4296 | bool after_p; | |
4297 | bool call_save_p; | |
4298 | ||
4299 | if (original_regno < FIRST_PSEUDO_REGISTER) | |
4300 | { | |
4301 | rclass = ira_allocno_class_translate[REGNO_REG_CLASS (original_regno)]; | |
4302 | hard_regno = original_regno; | |
4303 | call_save_p = false; | |
77bce07c | 4304 | nregs = 1; |
55a2c322 VM |
4305 | } |
4306 | else | |
4307 | { | |
4308 | hard_regno = reg_renumber[original_regno]; | |
77bce07c | 4309 | nregs = hard_regno_nregs[hard_regno][PSEUDO_REGNO_MODE (original_regno)]; |
55a2c322 VM |
4310 | rclass = lra_get_allocno_class (original_regno); |
4311 | original_reg = regno_reg_rtx[original_regno]; | |
4312 | call_save_p = need_for_call_save_p (original_regno); | |
4313 | } | |
4314 | original_reg = regno_reg_rtx[original_regno]; | |
4315 | lra_assert (hard_regno >= 0); | |
4316 | if (lra_dump_file != NULL) | |
4317 | fprintf (lra_dump_file, | |
4318 | " ((((((((((((((((((((((((((((((((((((((((((((((((\n"); | |
4319 | if (call_save_p) | |
4320 | { | |
4321 | enum machine_mode sec_mode; | |
f4eafc30 | 4322 | |
55a2c322 VM |
4323 | #ifdef SECONDARY_MEMORY_NEEDED_MODE |
4324 | sec_mode = SECONDARY_MEMORY_NEEDED_MODE (GET_MODE (original_reg)); | |
4325 | #else | |
4326 | sec_mode = GET_MODE (original_reg); | |
4327 | #endif | |
4328 | new_reg = lra_create_new_reg (sec_mode, NULL_RTX, | |
4329 | NO_REGS, "save"); | |
4330 | } | |
4331 | else | |
4332 | { | |
4333 | rclass = choose_split_class (rclass, hard_regno, | |
4334 | GET_MODE (original_reg)); | |
4335 | if (rclass == NO_REGS) | |
4336 | { | |
4337 | if (lra_dump_file != NULL) | |
4338 | { | |
4339 | fprintf (lra_dump_file, | |
4340 | " Rejecting split of %d(%s): " | |
4341 | "no good reg class for %d(%s)\n", | |
4342 | original_regno, | |
4343 | reg_class_names[lra_get_allocno_class (original_regno)], | |
4344 | hard_regno, | |
4345 | reg_class_names[REGNO_REG_CLASS (hard_regno)]); | |
4346 | fprintf | |
4347 | (lra_dump_file, | |
4348 | " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); | |
4349 | } | |
4350 | return false; | |
4351 | } | |
4352 | new_reg = lra_create_new_reg (GET_MODE (original_reg), original_reg, | |
4353 | rclass, "split"); | |
4354 | reg_renumber[REGNO (new_reg)] = hard_regno; | |
4355 | } | |
4356 | save = emit_spill_move (true, new_reg, original_reg); | |
4357 | if (NEXT_INSN (save) != NULL_RTX) | |
4358 | { | |
4359 | lra_assert (! call_save_p); | |
4360 | if (lra_dump_file != NULL) | |
4361 | { | |
4362 | fprintf | |
4363 | (lra_dump_file, | |
4364 | " Rejecting split %d->%d resulting in > 2 %s save insns:\n", | |
4365 | original_regno, REGNO (new_reg), call_save_p ? "call" : ""); | |
cfbeaedf | 4366 | dump_rtl_slim (lra_dump_file, save, NULL_RTX, -1, 0); |
55a2c322 VM |
4367 | fprintf (lra_dump_file, |
4368 | " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); | |
4369 | } | |
4370 | return false; | |
4371 | } | |
4372 | restore = emit_spill_move (false, new_reg, original_reg); | |
4373 | if (NEXT_INSN (restore) != NULL_RTX) | |
4374 | { | |
4375 | lra_assert (! call_save_p); | |
4376 | if (lra_dump_file != NULL) | |
4377 | { | |
4378 | fprintf (lra_dump_file, | |
4379 | " Rejecting split %d->%d " | |
4380 | "resulting in > 2 %s restore insns:\n", | |
4381 | original_regno, REGNO (new_reg), call_save_p ? "call" : ""); | |
cfbeaedf | 4382 | dump_rtl_slim (lra_dump_file, restore, NULL_RTX, -1, 0); |
55a2c322 VM |
4383 | fprintf (lra_dump_file, |
4384 | " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); | |
4385 | } | |
4386 | return false; | |
4387 | } | |
4388 | after_p = usage_insns[original_regno].after_p; | |
4389 | lra_reg_info[REGNO (new_reg)].restore_regno = original_regno; | |
4390 | bitmap_set_bit (&check_only_regs, REGNO (new_reg)); | |
4391 | bitmap_set_bit (&check_only_regs, original_regno); | |
4392 | bitmap_set_bit (&lra_split_regs, REGNO (new_reg)); | |
4393 | for (;;) | |
4394 | { | |
4395 | if (GET_CODE (next_usage_insns) != INSN_LIST) | |
4396 | { | |
4397 | usage_insn = next_usage_insns; | |
4398 | break; | |
4399 | } | |
4400 | usage_insn = XEXP (next_usage_insns, 0); | |
4401 | lra_assert (DEBUG_INSN_P (usage_insn)); | |
4402 | next_usage_insns = XEXP (next_usage_insns, 1); | |
4403 | substitute_pseudo (&usage_insn, original_regno, new_reg); | |
4404 | lra_update_insn_regno_info (usage_insn); | |
4405 | if (lra_dump_file != NULL) | |
4406 | { | |
4407 | fprintf (lra_dump_file, " Split reuse change %d->%d:\n", | |
4408 | original_regno, REGNO (new_reg)); | |
cfbeaedf | 4409 | dump_insn_slim (lra_dump_file, usage_insn); |
55a2c322 VM |
4410 | } |
4411 | } | |
4412 | lra_assert (NOTE_P (usage_insn) || NONDEBUG_INSN_P (usage_insn)); | |
4413 | lra_assert (usage_insn != insn || (after_p && before_p)); | |
4414 | lra_process_new_insns (usage_insn, after_p ? NULL_RTX : restore, | |
4415 | after_p ? restore : NULL_RTX, | |
4416 | call_save_p | |
4417 | ? "Add reg<-save" : "Add reg<-split"); | |
4418 | lra_process_new_insns (insn, before_p ? save : NULL_RTX, | |
4419 | before_p ? NULL_RTX : save, | |
4420 | call_save_p | |
4421 | ? "Add save<-reg" : "Add split<-reg"); | |
77bce07c VM |
4422 | if (nregs > 1) |
4423 | /* If we are trying to split multi-register. We should check | |
4424 | conflicts on the next assignment sub-pass. IRA can allocate on | |
4425 | sub-register levels, LRA do this on pseudos level right now and | |
4426 | this discrepancy may create allocation conflicts after | |
4427 | splitting. */ | |
4428 | lra_risky_transformations_p = true; | |
55a2c322 VM |
4429 | if (lra_dump_file != NULL) |
4430 | fprintf (lra_dump_file, | |
4431 | " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); | |
4432 | return true; | |
4433 | } | |
4434 | ||
4435 | /* Recognize that we need a split transformation for insn INSN, which | |
4436 | defines or uses REGNO in its insn biggest MODE (we use it only if | |
4437 | REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains | |
4438 | hard registers which might be used for reloads since the EBB end. | |
4439 | Put the save before INSN if BEFORE_P is true. MAX_UID is maximla | |
4440 | uid before starting INSN processing. Return true if we succeed in | |
4441 | such transformation. */ | |
4442 | static bool | |
4443 | split_if_necessary (int regno, enum machine_mode mode, | |
4444 | HARD_REG_SET potential_reload_hard_regs, | |
4445 | bool before_p, rtx insn, int max_uid) | |
4446 | { | |
4447 | bool res = false; | |
4448 | int i, nregs = 1; | |
4449 | rtx next_usage_insns; | |
4450 | ||
4451 | if (regno < FIRST_PSEUDO_REGISTER) | |
4452 | nregs = hard_regno_nregs[regno][mode]; | |
4453 | for (i = 0; i < nregs; i++) | |
4454 | if (usage_insns[regno + i].check == curr_usage_insns_check | |
4455 | && (next_usage_insns = usage_insns[regno + i].insns) != NULL_RTX | |
4456 | /* To avoid processing the register twice or more. */ | |
4457 | && ((GET_CODE (next_usage_insns) != INSN_LIST | |
4458 | && INSN_UID (next_usage_insns) < max_uid) | |
4459 | || (GET_CODE (next_usage_insns) == INSN_LIST | |
4460 | && (INSN_UID (XEXP (next_usage_insns, 0)) < max_uid))) | |
4461 | && need_for_split_p (potential_reload_hard_regs, regno + i) | |
4462 | && split_reg (before_p, regno + i, insn, next_usage_insns)) | |
4463 | res = true; | |
4464 | return res; | |
4465 | } | |
4466 | ||
4467 | /* Check only registers living at the current program point in the | |
4468 | current EBB. */ | |
4469 | static bitmap_head live_regs; | |
4470 | ||
4471 | /* Update live info in EBB given by its HEAD and TAIL insns after | |
4472 | inheritance/split transformation. The function removes dead moves | |
4473 | too. */ | |
4474 | static void | |
4475 | update_ebb_live_info (rtx head, rtx tail) | |
4476 | { | |
4477 | unsigned int j; | |
4478 | int regno; | |
4479 | bool live_p; | |
4480 | rtx prev_insn, set; | |
4481 | bool remove_p; | |
4482 | basic_block last_bb, prev_bb, curr_bb; | |
4483 | bitmap_iterator bi; | |
4484 | struct lra_insn_reg *reg; | |
4485 | edge e; | |
4486 | edge_iterator ei; | |
4487 | ||
f4eafc30 | 4488 | last_bb = BLOCK_FOR_INSN (tail); |
55a2c322 VM |
4489 | prev_bb = NULL; |
4490 | for (curr_insn = tail; | |
4491 | curr_insn != PREV_INSN (head); | |
4492 | curr_insn = prev_insn) | |
4493 | { | |
4494 | prev_insn = PREV_INSN (curr_insn); | |
911598e3 VM |
4495 | /* We need to process empty blocks too. They contain |
4496 | NOTE_INSN_BASIC_BLOCK referring for the basic block. */ | |
4497 | if (NOTE_P (curr_insn) && NOTE_KIND (curr_insn) != NOTE_INSN_BASIC_BLOCK) | |
4498 | continue; | |
55a2c322 VM |
4499 | curr_bb = BLOCK_FOR_INSN (curr_insn); |
4500 | if (curr_bb != prev_bb) | |
4501 | { | |
4502 | if (prev_bb != NULL) | |
4503 | { | |
4504 | /* Update df_get_live_in (prev_bb): */ | |
4505 | EXECUTE_IF_SET_IN_BITMAP (&check_only_regs, 0, j, bi) | |
4506 | if (bitmap_bit_p (&live_regs, j)) | |
4507 | bitmap_set_bit (df_get_live_in (prev_bb), j); | |
4508 | else | |
4509 | bitmap_clear_bit (df_get_live_in (prev_bb), j); | |
4510 | } | |
4511 | if (curr_bb != last_bb) | |
4512 | { | |
4513 | /* Update df_get_live_out (curr_bb): */ | |
4514 | EXECUTE_IF_SET_IN_BITMAP (&check_only_regs, 0, j, bi) | |
4515 | { | |
4516 | live_p = bitmap_bit_p (&live_regs, j); | |
4517 | if (! live_p) | |
4518 | FOR_EACH_EDGE (e, ei, curr_bb->succs) | |
4519 | if (bitmap_bit_p (df_get_live_in (e->dest), j)) | |
4520 | { | |
4521 | live_p = true; | |
4522 | break; | |
4523 | } | |
4524 | if (live_p) | |
4525 | bitmap_set_bit (df_get_live_out (curr_bb), j); | |
4526 | else | |
4527 | bitmap_clear_bit (df_get_live_out (curr_bb), j); | |
4528 | } | |
4529 | } | |
4530 | prev_bb = curr_bb; | |
4531 | bitmap_and (&live_regs, &check_only_regs, df_get_live_out (curr_bb)); | |
4532 | } | |
44b94bdb | 4533 | if (! NONDEBUG_INSN_P (curr_insn)) |
55a2c322 VM |
4534 | continue; |
4535 | curr_id = lra_get_insn_recog_data (curr_insn); | |
4536 | remove_p = false; | |
4537 | if ((set = single_set (curr_insn)) != NULL_RTX && REG_P (SET_DEST (set)) | |
4538 | && (regno = REGNO (SET_DEST (set))) >= FIRST_PSEUDO_REGISTER | |
4539 | && bitmap_bit_p (&check_only_regs, regno) | |
4540 | && ! bitmap_bit_p (&live_regs, regno)) | |
4541 | remove_p = true; | |
4542 | /* See which defined values die here. */ | |
4543 | for (reg = curr_id->regs; reg != NULL; reg = reg->next) | |
4544 | if (reg->type == OP_OUT && ! reg->subreg_p) | |
4545 | bitmap_clear_bit (&live_regs, reg->regno); | |
4546 | /* Mark each used value as live. */ | |
4547 | for (reg = curr_id->regs; reg != NULL; reg = reg->next) | |
4548 | if (reg->type == OP_IN | |
4549 | && bitmap_bit_p (&check_only_regs, reg->regno)) | |
4550 | bitmap_set_bit (&live_regs, reg->regno); | |
4551 | /* It is quite important to remove dead move insns because it | |
4552 | means removing dead store. We don't need to process them for | |
4553 | constraints. */ | |
4554 | if (remove_p) | |
4555 | { | |
4556 | if (lra_dump_file != NULL) | |
4557 | { | |
4558 | fprintf (lra_dump_file, " Removing dead insn:\n "); | |
cfbeaedf | 4559 | dump_insn_slim (lra_dump_file, curr_insn); |
55a2c322 VM |
4560 | } |
4561 | lra_set_insn_deleted (curr_insn); | |
4562 | } | |
4563 | } | |
4564 | } | |
4565 | ||
4566 | /* The structure describes info to do an inheritance for the current | |
4567 | insn. We need to collect such info first before doing the | |
4568 | transformations because the transformations change the insn | |
4569 | internal representation. */ | |
4570 | struct to_inherit | |
4571 | { | |
4572 | /* Original regno. */ | |
4573 | int regno; | |
4574 | /* Subsequent insns which can inherit original reg value. */ | |
4575 | rtx insns; | |
4576 | }; | |
4577 | ||
4578 | /* Array containing all info for doing inheritance from the current | |
4579 | insn. */ | |
4580 | static struct to_inherit to_inherit[LRA_MAX_INSN_RELOADS]; | |
4581 | ||
4582 | /* Number elements in the previous array. */ | |
4583 | static int to_inherit_num; | |
4584 | ||
4585 | /* Add inheritance info REGNO and INSNS. Their meaning is described in | |
4586 | structure to_inherit. */ | |
4587 | static void | |
4588 | add_to_inherit (int regno, rtx insns) | |
4589 | { | |
4590 | int i; | |
4591 | ||
4592 | for (i = 0; i < to_inherit_num; i++) | |
4593 | if (to_inherit[i].regno == regno) | |
4594 | return; | |
4595 | lra_assert (to_inherit_num < LRA_MAX_INSN_RELOADS); | |
4596 | to_inherit[to_inherit_num].regno = regno; | |
4597 | to_inherit[to_inherit_num++].insns = insns; | |
4598 | } | |
4599 | ||
4600 | /* Return the last non-debug insn in basic block BB, or the block begin | |
4601 | note if none. */ | |
4602 | static rtx | |
4603 | get_last_insertion_point (basic_block bb) | |
4604 | { | |
4605 | rtx insn; | |
4606 | ||
4607 | FOR_BB_INSNS_REVERSE (bb, insn) | |
4608 | if (NONDEBUG_INSN_P (insn) || NOTE_INSN_BASIC_BLOCK_P (insn)) | |
4609 | return insn; | |
4610 | gcc_unreachable (); | |
4611 | } | |
4612 | ||
4613 | /* Set up RES by registers living on edges FROM except the edge (FROM, | |
4614 | TO) or by registers set up in a jump insn in BB FROM. */ | |
4615 | static void | |
4616 | get_live_on_other_edges (basic_block from, basic_block to, bitmap res) | |
4617 | { | |
4618 | rtx last; | |
4619 | struct lra_insn_reg *reg; | |
4620 | edge e; | |
4621 | edge_iterator ei; | |
4622 | ||
4623 | lra_assert (to != NULL); | |
4624 | bitmap_clear (res); | |
4625 | FOR_EACH_EDGE (e, ei, from->succs) | |
4626 | if (e->dest != to) | |
4627 | bitmap_ior_into (res, df_get_live_in (e->dest)); | |
4628 | last = get_last_insertion_point (from); | |
4629 | if (! JUMP_P (last)) | |
4630 | return; | |
4631 | curr_id = lra_get_insn_recog_data (last); | |
4632 | for (reg = curr_id->regs; reg != NULL; reg = reg->next) | |
4633 | if (reg->type != OP_IN) | |
4634 | bitmap_set_bit (res, reg->regno); | |
4635 | } | |
f4eafc30 | 4636 | |
55a2c322 VM |
4637 | /* Used as a temporary results of some bitmap calculations. */ |
4638 | static bitmap_head temp_bitmap; | |
4639 | ||
4640 | /* Do inheritance/split transformations in EBB starting with HEAD and | |
4641 | finishing on TAIL. We process EBB insns in the reverse order. | |
4642 | Return true if we did any inheritance/split transformation in the | |
4643 | EBB. | |
4644 | ||
4645 | We should avoid excessive splitting which results in worse code | |
4646 | because of inaccurate cost calculations for spilling new split | |
4647 | pseudos in such case. To achieve this we do splitting only if | |
4648 | register pressure is high in given basic block and there are reload | |
4649 | pseudos requiring hard registers. We could do more register | |
4650 | pressure calculations at any given program point to avoid necessary | |
4651 | splitting even more but it is to expensive and the current approach | |
4652 | works well enough. */ | |
4653 | static bool | |
4654 | inherit_in_ebb (rtx head, rtx tail) | |
4655 | { | |
4656 | int i, src_regno, dst_regno, nregs; | |
4657 | bool change_p, succ_p; | |
4658 | rtx prev_insn, next_usage_insns, set, last_insn; | |
4659 | enum reg_class cl; | |
4660 | struct lra_insn_reg *reg; | |
4661 | basic_block last_processed_bb, curr_bb = NULL; | |
4662 | HARD_REG_SET potential_reload_hard_regs, live_hard_regs; | |
4663 | bitmap to_process; | |
4664 | unsigned int j; | |
4665 | bitmap_iterator bi; | |
4666 | bool head_p, after_p; | |
4667 | ||
4668 | change_p = false; | |
4669 | curr_usage_insns_check++; | |
4670 | reloads_num = calls_num = 0; | |
4671 | bitmap_clear (&check_only_regs); | |
4672 | last_processed_bb = NULL; | |
4673 | CLEAR_HARD_REG_SET (potential_reload_hard_regs); | |
4674 | CLEAR_HARD_REG_SET (live_hard_regs); | |
4675 | /* We don't process new insns generated in the loop. */ | |
4676 | for (curr_insn = tail; curr_insn != PREV_INSN (head); curr_insn = prev_insn) | |
4677 | { | |
4678 | prev_insn = PREV_INSN (curr_insn); | |
4679 | if (BLOCK_FOR_INSN (curr_insn) != NULL) | |
4680 | curr_bb = BLOCK_FOR_INSN (curr_insn); | |
4681 | if (last_processed_bb != curr_bb) | |
4682 | { | |
4683 | /* We are at the end of BB. Add qualified living | |
4684 | pseudos for potential splitting. */ | |
4685 | to_process = df_get_live_out (curr_bb); | |
4686 | if (last_processed_bb != NULL) | |
f4eafc30 | 4687 | { |
55a2c322 VM |
4688 | /* We are somewhere in the middle of EBB. */ |
4689 | get_live_on_other_edges (curr_bb, last_processed_bb, | |
4690 | &temp_bitmap); | |
4691 | to_process = &temp_bitmap; | |
4692 | } | |
4693 | last_processed_bb = curr_bb; | |
4694 | last_insn = get_last_insertion_point (curr_bb); | |
4695 | after_p = (! JUMP_P (last_insn) | |
4696 | && (! CALL_P (last_insn) | |
4697 | || (find_reg_note (last_insn, | |
4698 | REG_NORETURN, NULL_RTX) == NULL_RTX | |
4699 | && ! SIBLING_CALL_P (last_insn)))); | |
4700 | REG_SET_TO_HARD_REG_SET (live_hard_regs, df_get_live_out (curr_bb)); | |
4701 | IOR_HARD_REG_SET (live_hard_regs, eliminable_regset); | |
4702 | IOR_HARD_REG_SET (live_hard_regs, lra_no_alloc_regs); | |
4703 | CLEAR_HARD_REG_SET (potential_reload_hard_regs); | |
4704 | EXECUTE_IF_SET_IN_BITMAP (to_process, 0, j, bi) | |
4705 | { | |
4706 | if ((int) j >= lra_constraint_new_regno_start) | |
4707 | break; | |
4708 | if (j < FIRST_PSEUDO_REGISTER || reg_renumber[j] >= 0) | |
4709 | { | |
4710 | if (j < FIRST_PSEUDO_REGISTER) | |
4711 | SET_HARD_REG_BIT (live_hard_regs, j); | |
4712 | else | |
4713 | add_to_hard_reg_set (&live_hard_regs, | |
4714 | PSEUDO_REGNO_MODE (j), | |
4715 | reg_renumber[j]); | |
4716 | setup_next_usage_insn (j, last_insn, reloads_num, after_p); | |
4717 | } | |
4718 | } | |
4719 | } | |
4720 | src_regno = dst_regno = -1; | |
4721 | if (NONDEBUG_INSN_P (curr_insn) | |
4722 | && (set = single_set (curr_insn)) != NULL_RTX | |
4723 | && REG_P (SET_DEST (set)) && REG_P (SET_SRC (set))) | |
4724 | { | |
4725 | src_regno = REGNO (SET_SRC (set)); | |
4726 | dst_regno = REGNO (SET_DEST (set)); | |
4727 | } | |
4728 | if (src_regno < lra_constraint_new_regno_start | |
4729 | && src_regno >= FIRST_PSEUDO_REGISTER | |
4730 | && reg_renumber[src_regno] < 0 | |
4731 | && dst_regno >= lra_constraint_new_regno_start | |
4732 | && (cl = lra_get_allocno_class (dst_regno)) != NO_REGS) | |
4733 | { | |
4734 | /* 'reload_pseudo <- original_pseudo'. */ | |
4735 | reloads_num++; | |
4736 | succ_p = false; | |
4737 | if (usage_insns[src_regno].check == curr_usage_insns_check | |
4738 | && (next_usage_insns = usage_insns[src_regno].insns) != NULL_RTX) | |
4739 | succ_p = inherit_reload_reg (false, src_regno, cl, | |
4740 | curr_insn, next_usage_insns); | |
4741 | if (succ_p) | |
4742 | change_p = true; | |
4743 | else | |
4744 | setup_next_usage_insn (src_regno, curr_insn, reloads_num, false); | |
4745 | if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs)) | |
4746 | IOR_HARD_REG_SET (potential_reload_hard_regs, | |
4747 | reg_class_contents[cl]); | |
4748 | } | |
4749 | else if (src_regno >= lra_constraint_new_regno_start | |
4750 | && dst_regno < lra_constraint_new_regno_start | |
4751 | && dst_regno >= FIRST_PSEUDO_REGISTER | |
4752 | && reg_renumber[dst_regno] < 0 | |
4753 | && (cl = lra_get_allocno_class (src_regno)) != NO_REGS | |
4754 | && usage_insns[dst_regno].check == curr_usage_insns_check | |
4755 | && (next_usage_insns | |
4756 | = usage_insns[dst_regno].insns) != NULL_RTX) | |
4757 | { | |
4758 | reloads_num++; | |
4759 | /* 'original_pseudo <- reload_pseudo'. */ | |
4760 | if (! JUMP_P (curr_insn) | |
4761 | && inherit_reload_reg (true, dst_regno, cl, | |
4762 | curr_insn, next_usage_insns)) | |
4763 | change_p = true; | |
4764 | /* Invalidate. */ | |
4765 | usage_insns[dst_regno].check = 0; | |
4766 | if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs)) | |
4767 | IOR_HARD_REG_SET (potential_reload_hard_regs, | |
4768 | reg_class_contents[cl]); | |
4769 | } | |
4770 | else if (INSN_P (curr_insn)) | |
4771 | { | |
4772 | int max_uid = get_max_uid (); | |
4773 | ||
4774 | curr_id = lra_get_insn_recog_data (curr_insn); | |
4775 | to_inherit_num = 0; | |
4776 | /* Process insn definitions. */ | |
4777 | for (reg = curr_id->regs; reg != NULL; reg = reg->next) | |
4778 | if (reg->type != OP_IN | |
4779 | && (dst_regno = reg->regno) < lra_constraint_new_regno_start) | |
4780 | { | |
4781 | if (dst_regno >= FIRST_PSEUDO_REGISTER && reg->type == OP_OUT | |
4782 | && reg_renumber[dst_regno] < 0 && ! reg->subreg_p | |
4783 | && usage_insns[dst_regno].check == curr_usage_insns_check | |
4784 | && (next_usage_insns | |
4785 | = usage_insns[dst_regno].insns) != NULL_RTX) | |
4786 | { | |
4787 | struct lra_insn_reg *r; | |
f4eafc30 | 4788 | |
55a2c322 VM |
4789 | for (r = curr_id->regs; r != NULL; r = r->next) |
4790 | if (r->type != OP_OUT && r->regno == dst_regno) | |
4791 | break; | |
4792 | /* Don't do inheritance if the pseudo is also | |
4793 | used in the insn. */ | |
4794 | if (r == NULL) | |
4795 | /* We can not do inheritance right now | |
4796 | because the current insn reg info (chain | |
4797 | regs) can change after that. */ | |
4798 | add_to_inherit (dst_regno, next_usage_insns); | |
4799 | } | |
4800 | /* We can not process one reg twice here because of | |
4801 | usage_insns invalidation. */ | |
4802 | if ((dst_regno < FIRST_PSEUDO_REGISTER | |
4803 | || reg_renumber[dst_regno] >= 0) | |
4804 | && ! reg->subreg_p && reg->type == OP_OUT) | |
4805 | { | |
4806 | HARD_REG_SET s; | |
f4eafc30 | 4807 | |
55a2c322 VM |
4808 | if (split_if_necessary (dst_regno, reg->biggest_mode, |
4809 | potential_reload_hard_regs, | |
4810 | false, curr_insn, max_uid)) | |
4811 | change_p = true; | |
4812 | CLEAR_HARD_REG_SET (s); | |
4813 | if (dst_regno < FIRST_PSEUDO_REGISTER) | |
4814 | add_to_hard_reg_set (&s, reg->biggest_mode, dst_regno); | |
4815 | else | |
4816 | add_to_hard_reg_set (&s, PSEUDO_REGNO_MODE (dst_regno), | |
4817 | reg_renumber[dst_regno]); | |
4818 | AND_COMPL_HARD_REG_SET (live_hard_regs, s); | |
4819 | } | |
4820 | /* We should invalidate potential inheritance or | |
4821 | splitting for the current insn usages to the next | |
4822 | usage insns (see code below) as the output pseudo | |
4823 | prevents this. */ | |
4824 | if ((dst_regno >= FIRST_PSEUDO_REGISTER | |
4825 | && reg_renumber[dst_regno] < 0) | |
4826 | || (reg->type == OP_OUT && ! reg->subreg_p | |
4827 | && (dst_regno < FIRST_PSEUDO_REGISTER | |
4828 | || reg_renumber[dst_regno] >= 0))) | |
4829 | { | |
1ccd4874 | 4830 | /* Invalidate and mark definitions. */ |
55a2c322 | 4831 | if (dst_regno >= FIRST_PSEUDO_REGISTER) |
1ccd4874 | 4832 | usage_insns[dst_regno].check = -(int) INSN_UID (curr_insn); |
55a2c322 VM |
4833 | else |
4834 | { | |
4835 | nregs = hard_regno_nregs[dst_regno][reg->biggest_mode]; | |
4836 | for (i = 0; i < nregs; i++) | |
1ccd4874 VM |
4837 | usage_insns[dst_regno + i].check |
4838 | = -(int) INSN_UID (curr_insn); | |
55a2c322 VM |
4839 | } |
4840 | } | |
4841 | } | |
4842 | if (! JUMP_P (curr_insn)) | |
4843 | for (i = 0; i < to_inherit_num; i++) | |
4844 | if (inherit_reload_reg (true, to_inherit[i].regno, | |
4845 | ALL_REGS, curr_insn, | |
4846 | to_inherit[i].insns)) | |
4847 | change_p = true; | |
4848 | if (CALL_P (curr_insn)) | |
4849 | { | |
4850 | rtx cheap, pat, dest, restore; | |
4851 | int regno, hard_regno; | |
4852 | ||
4853 | calls_num++; | |
4854 | if ((cheap = find_reg_note (curr_insn, | |
4855 | REG_RETURNED, NULL_RTX)) != NULL_RTX | |
4856 | && ((cheap = XEXP (cheap, 0)), true) | |
4857 | && (regno = REGNO (cheap)) >= FIRST_PSEUDO_REGISTER | |
4858 | && (hard_regno = reg_renumber[regno]) >= 0 | |
4859 | /* If there are pending saves/restores, the | |
4860 | optimization is not worth. */ | |
4861 | && usage_insns[regno].calls_num == calls_num - 1 | |
4862 | && TEST_HARD_REG_BIT (call_used_reg_set, hard_regno)) | |
4863 | { | |
4864 | /* Restore the pseudo from the call result as | |
4865 | REG_RETURNED note says that the pseudo value is | |
4866 | in the call result and the pseudo is an argument | |
4867 | of the call. */ | |
4868 | pat = PATTERN (curr_insn); | |
4869 | if (GET_CODE (pat) == PARALLEL) | |
4870 | pat = XVECEXP (pat, 0, 0); | |
4871 | dest = SET_DEST (pat); | |
4872 | start_sequence (); | |
4873 | emit_move_insn (cheap, copy_rtx (dest)); | |
4874 | restore = get_insns (); | |
4875 | end_sequence (); | |
4876 | lra_process_new_insns (curr_insn, NULL, restore, | |
4877 | "Inserting call parameter restore"); | |
4878 | /* We don't need to save/restore of the pseudo from | |
4879 | this call. */ | |
4880 | usage_insns[regno].calls_num = calls_num; | |
4881 | bitmap_set_bit (&check_only_regs, regno); | |
4882 | } | |
4883 | } | |
4884 | to_inherit_num = 0; | |
4885 | /* Process insn usages. */ | |
4886 | for (reg = curr_id->regs; reg != NULL; reg = reg->next) | |
4887 | if ((reg->type != OP_OUT | |
4888 | || (reg->type == OP_OUT && reg->subreg_p)) | |
4889 | && (src_regno = reg->regno) < lra_constraint_new_regno_start) | |
4890 | { | |
4891 | if (src_regno >= FIRST_PSEUDO_REGISTER | |
4892 | && reg_renumber[src_regno] < 0 && reg->type == OP_IN) | |
4893 | { | |
4894 | if (usage_insns[src_regno].check == curr_usage_insns_check | |
4895 | && (next_usage_insns | |
4896 | = usage_insns[src_regno].insns) != NULL_RTX | |
4897 | && NONDEBUG_INSN_P (curr_insn)) | |
4898 | add_to_inherit (src_regno, next_usage_insns); | |
1ccd4874 VM |
4899 | else if (usage_insns[src_regno].check |
4900 | != -(int) INSN_UID (curr_insn)) | |
4901 | /* Add usages but only if the reg is not set up | |
4902 | in the same insn. */ | |
55a2c322 VM |
4903 | add_next_usage_insn (src_regno, curr_insn, reloads_num); |
4904 | } | |
4905 | else if (src_regno < FIRST_PSEUDO_REGISTER | |
4906 | || reg_renumber[src_regno] >= 0) | |
4907 | { | |
4908 | bool before_p; | |
4909 | rtx use_insn = curr_insn; | |
4910 | ||
4911 | before_p = (JUMP_P (curr_insn) | |
4912 | || (CALL_P (curr_insn) && reg->type == OP_IN)); | |
4913 | if (NONDEBUG_INSN_P (curr_insn) | |
4914 | && split_if_necessary (src_regno, reg->biggest_mode, | |
4915 | potential_reload_hard_regs, | |
4916 | before_p, curr_insn, max_uid)) | |
4917 | { | |
4918 | if (reg->subreg_p) | |
4919 | lra_risky_transformations_p = true; | |
4920 | change_p = true; | |
4921 | /* Invalidate. */ | |
4922 | usage_insns[src_regno].check = 0; | |
4923 | if (before_p) | |
4924 | use_insn = PREV_INSN (curr_insn); | |
4925 | } | |
4926 | if (NONDEBUG_INSN_P (curr_insn)) | |
4927 | { | |
4928 | if (src_regno < FIRST_PSEUDO_REGISTER) | |
4929 | add_to_hard_reg_set (&live_hard_regs, | |
4930 | reg->biggest_mode, src_regno); | |
4931 | else | |
4932 | add_to_hard_reg_set (&live_hard_regs, | |
4933 | PSEUDO_REGNO_MODE (src_regno), | |
4934 | reg_renumber[src_regno]); | |
4935 | } | |
4936 | add_next_usage_insn (src_regno, use_insn, reloads_num); | |
4937 | } | |
4938 | } | |
4939 | for (i = 0; i < to_inherit_num; i++) | |
4940 | { | |
4941 | src_regno = to_inherit[i].regno; | |
4942 | if (inherit_reload_reg (false, src_regno, ALL_REGS, | |
4943 | curr_insn, to_inherit[i].insns)) | |
4944 | change_p = true; | |
4945 | else | |
4946 | setup_next_usage_insn (src_regno, curr_insn, reloads_num, false); | |
4947 | } | |
4948 | } | |
4949 | /* We reached the start of the current basic block. */ | |
4950 | if (prev_insn == NULL_RTX || prev_insn == PREV_INSN (head) | |
4951 | || BLOCK_FOR_INSN (prev_insn) != curr_bb) | |
4952 | { | |
4953 | /* We reached the beginning of the current block -- do | |
4954 | rest of spliting in the current BB. */ | |
4955 | to_process = df_get_live_in (curr_bb); | |
4956 | if (BLOCK_FOR_INSN (head) != curr_bb) | |
f4eafc30 | 4957 | { |
55a2c322 VM |
4958 | /* We are somewhere in the middle of EBB. */ |
4959 | get_live_on_other_edges (EDGE_PRED (curr_bb, 0)->src, | |
4960 | curr_bb, &temp_bitmap); | |
4961 | to_process = &temp_bitmap; | |
4962 | } | |
4963 | head_p = true; | |
4964 | EXECUTE_IF_SET_IN_BITMAP (to_process, 0, j, bi) | |
4965 | { | |
4966 | if ((int) j >= lra_constraint_new_regno_start) | |
4967 | break; | |
4968 | if (((int) j < FIRST_PSEUDO_REGISTER || reg_renumber[j] >= 0) | |
4969 | && usage_insns[j].check == curr_usage_insns_check | |
4970 | && (next_usage_insns = usage_insns[j].insns) != NULL_RTX) | |
4971 | { | |
4972 | if (need_for_split_p (potential_reload_hard_regs, j)) | |
4973 | { | |
4974 | if (lra_dump_file != NULL && head_p) | |
4975 | { | |
4976 | fprintf (lra_dump_file, | |
4977 | " ----------------------------------\n"); | |
4978 | head_p = false; | |
4979 | } | |
4980 | if (split_reg (false, j, bb_note (curr_bb), | |
4981 | next_usage_insns)) | |
4982 | change_p = true; | |
4983 | } | |
4984 | usage_insns[j].check = 0; | |
4985 | } | |
4986 | } | |
4987 | } | |
4988 | } | |
4989 | return change_p; | |
4990 | } | |
4991 | ||
4992 | /* This value affects EBB forming. If probability of edge from EBB to | |
4993 | a BB is not greater than the following value, we don't add the BB | |
f4eafc30 | 4994 | to EBB. */ |
2c62cbaa | 4995 | #define EBB_PROBABILITY_CUTOFF ((REG_BR_PROB_BASE * 50) / 100) |
55a2c322 VM |
4996 | |
4997 | /* Current number of inheritance/split iteration. */ | |
4998 | int lra_inheritance_iter; | |
4999 | ||
5000 | /* Entry function for inheritance/split pass. */ | |
5001 | void | |
5002 | lra_inheritance (void) | |
5003 | { | |
5004 | int i; | |
5005 | basic_block bb, start_bb; | |
5006 | edge e; | |
5007 | ||
55a2c322 | 5008 | lra_inheritance_iter++; |
8e3a4869 | 5009 | if (lra_inheritance_iter > LRA_MAX_INHERITANCE_PASSES) |
e731262b VM |
5010 | return; |
5011 | timevar_push (TV_LRA_INHERITANCE); | |
55a2c322 VM |
5012 | if (lra_dump_file != NULL) |
5013 | fprintf (lra_dump_file, "\n********** Inheritance #%d: **********\n\n", | |
5014 | lra_inheritance_iter); | |
5015 | curr_usage_insns_check = 0; | |
5016 | usage_insns = XNEWVEC (struct usage_insns, lra_constraint_new_regno_start); | |
5017 | for (i = 0; i < lra_constraint_new_regno_start; i++) | |
5018 | usage_insns[i].check = 0; | |
5019 | bitmap_initialize (&check_only_regs, ®_obstack); | |
5020 | bitmap_initialize (&live_regs, ®_obstack); | |
5021 | bitmap_initialize (&temp_bitmap, ®_obstack); | |
5022 | bitmap_initialize (&ebb_global_regs, ®_obstack); | |
5023 | FOR_EACH_BB (bb) | |
5024 | { | |
5025 | start_bb = bb; | |
5026 | if (lra_dump_file != NULL) | |
5027 | fprintf (lra_dump_file, "EBB"); | |
5028 | /* Form a EBB starting with BB. */ | |
5029 | bitmap_clear (&ebb_global_regs); | |
5030 | bitmap_ior_into (&ebb_global_regs, df_get_live_in (bb)); | |
5031 | for (;;) | |
5032 | { | |
5033 | if (lra_dump_file != NULL) | |
5034 | fprintf (lra_dump_file, " %d", bb->index); | |
5035 | if (bb->next_bb == EXIT_BLOCK_PTR || LABEL_P (BB_HEAD (bb->next_bb))) | |
5036 | break; | |
5037 | e = find_fallthru_edge (bb->succs); | |
5038 | if (! e) | |
5039 | break; | |
5040 | if (e->probability <= EBB_PROBABILITY_CUTOFF) | |
5041 | break; | |
5042 | bb = bb->next_bb; | |
5043 | } | |
5044 | bitmap_ior_into (&ebb_global_regs, df_get_live_out (bb)); | |
5045 | if (lra_dump_file != NULL) | |
5046 | fprintf (lra_dump_file, "\n"); | |
5047 | if (inherit_in_ebb (BB_HEAD (start_bb), BB_END (bb))) | |
5048 | /* Remember that the EBB head and tail can change in | |
5049 | inherit_in_ebb. */ | |
5050 | update_ebb_live_info (BB_HEAD (start_bb), BB_END (bb)); | |
5051 | } | |
5052 | bitmap_clear (&ebb_global_regs); | |
5053 | bitmap_clear (&temp_bitmap); | |
5054 | bitmap_clear (&live_regs); | |
5055 | bitmap_clear (&check_only_regs); | |
5056 | free (usage_insns); | |
5057 | ||
5058 | timevar_pop (TV_LRA_INHERITANCE); | |
5059 | } | |
5060 | ||
5061 | \f | |
5062 | ||
5063 | /* This page contains code to undo failed inheritance/split | |
5064 | transformations. */ | |
5065 | ||
5066 | /* Current number of iteration undoing inheritance/split. */ | |
5067 | int lra_undo_inheritance_iter; | |
5068 | ||
5069 | /* Fix BB live info LIVE after removing pseudos created on pass doing | |
5070 | inheritance/split which are REMOVED_PSEUDOS. */ | |
5071 | static void | |
5072 | fix_bb_live_info (bitmap live, bitmap removed_pseudos) | |
5073 | { | |
5074 | unsigned int regno; | |
5075 | bitmap_iterator bi; | |
5076 | ||
5077 | EXECUTE_IF_SET_IN_BITMAP (removed_pseudos, 0, regno, bi) | |
5078 | if (bitmap_clear_bit (live, regno)) | |
5079 | bitmap_set_bit (live, lra_reg_info[regno].restore_regno); | |
5080 | } | |
5081 | ||
5082 | /* Return regno of the (subreg of) REG. Otherwise, return a negative | |
5083 | number. */ | |
5084 | static int | |
5085 | get_regno (rtx reg) | |
5086 | { | |
5087 | if (GET_CODE (reg) == SUBREG) | |
5088 | reg = SUBREG_REG (reg); | |
5089 | if (REG_P (reg)) | |
5090 | return REGNO (reg); | |
5091 | return -1; | |
5092 | } | |
5093 | ||
5094 | /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and | |
5095 | return true if we did any change. The undo transformations for | |
5096 | inheritance looks like | |
5097 | i <- i2 | |
5098 | p <- i => p <- i2 | |
5099 | or removing | |
5100 | p <- i, i <- p, and i <- i3 | |
5101 | where p is original pseudo from which inheritance pseudo i was | |
5102 | created, i and i3 are removed inheritance pseudos, i2 is another | |
5103 | not removed inheritance pseudo. All split pseudos or other | |
5104 | occurrences of removed inheritance pseudos are changed on the | |
5105 | corresponding original pseudos. | |
5106 | ||
5107 | The function also schedules insns changed and created during | |
5108 | inheritance/split pass for processing by the subsequent constraint | |
5109 | pass. */ | |
5110 | static bool | |
5111 | remove_inheritance_pseudos (bitmap remove_pseudos) | |
5112 | { | |
5113 | basic_block bb; | |
5114 | int regno, sregno, prev_sregno, dregno, restore_regno; | |
5115 | rtx set, prev_set, prev_insn; | |
5116 | bool change_p, done_p; | |
5117 | ||
5118 | change_p = ! bitmap_empty_p (remove_pseudos); | |
5119 | /* We can not finish the function right away if CHANGE_P is true | |
5120 | because we need to marks insns affected by previous | |
5121 | inheritance/split pass for processing by the subsequent | |
5122 | constraint pass. */ | |
5123 | FOR_EACH_BB (bb) | |
5124 | { | |
5125 | fix_bb_live_info (df_get_live_in (bb), remove_pseudos); | |
5126 | fix_bb_live_info (df_get_live_out (bb), remove_pseudos); | |
5127 | FOR_BB_INSNS_REVERSE (bb, curr_insn) | |
5128 | { | |
5129 | if (! INSN_P (curr_insn)) | |
5130 | continue; | |
5131 | done_p = false; | |
5132 | sregno = dregno = -1; | |
5133 | if (change_p && NONDEBUG_INSN_P (curr_insn) | |
5134 | && (set = single_set (curr_insn)) != NULL_RTX) | |
5135 | { | |
5136 | dregno = get_regno (SET_DEST (set)); | |
5137 | sregno = get_regno (SET_SRC (set)); | |
5138 | } | |
f4eafc30 | 5139 | |
55a2c322 VM |
5140 | if (sregno >= 0 && dregno >= 0) |
5141 | { | |
5142 | if ((bitmap_bit_p (remove_pseudos, sregno) | |
5143 | && (lra_reg_info[sregno].restore_regno == dregno | |
5144 | || (bitmap_bit_p (remove_pseudos, dregno) | |
5145 | && (lra_reg_info[sregno].restore_regno | |
5146 | == lra_reg_info[dregno].restore_regno)))) | |
5147 | || (bitmap_bit_p (remove_pseudos, dregno) | |
5148 | && lra_reg_info[dregno].restore_regno == sregno)) | |
5149 | /* One of the following cases: | |
5150 | original <- removed inheritance pseudo | |
5151 | removed inherit pseudo <- another removed inherit pseudo | |
5152 | removed inherit pseudo <- original pseudo | |
5153 | Or | |
5154 | removed_split_pseudo <- original_reg | |
5155 | original_reg <- removed_split_pseudo */ | |
5156 | { | |
5157 | if (lra_dump_file != NULL) | |
5158 | { | |
5159 | fprintf (lra_dump_file, " Removing %s:\n", | |
5160 | bitmap_bit_p (&lra_split_regs, sregno) | |
5161 | || bitmap_bit_p (&lra_split_regs, dregno) | |
5162 | ? "split" : "inheritance"); | |
cfbeaedf | 5163 | dump_insn_slim (lra_dump_file, curr_insn); |
55a2c322 VM |
5164 | } |
5165 | lra_set_insn_deleted (curr_insn); | |
5166 | done_p = true; | |
5167 | } | |
5168 | else if (bitmap_bit_p (remove_pseudos, sregno) | |
5169 | && bitmap_bit_p (&lra_inheritance_pseudos, sregno)) | |
5170 | { | |
5171 | /* Search the following pattern: | |
5172 | inherit_or_split_pseudo1 <- inherit_or_split_pseudo2 | |
5173 | original_pseudo <- inherit_or_split_pseudo1 | |
5174 | where the 2nd insn is the current insn and | |
5175 | inherit_or_split_pseudo2 is not removed. If it is found, | |
5176 | change the current insn onto: | |
5177 | original_pseudo <- inherit_or_split_pseudo2. */ | |
5178 | for (prev_insn = PREV_INSN (curr_insn); | |
5179 | prev_insn != NULL_RTX && ! NONDEBUG_INSN_P (prev_insn); | |
5180 | prev_insn = PREV_INSN (prev_insn)) | |
5181 | ; | |
5182 | if (prev_insn != NULL_RTX && BLOCK_FOR_INSN (prev_insn) == bb | |
5183 | && (prev_set = single_set (prev_insn)) != NULL_RTX | |
5184 | /* There should be no subregs in insn we are | |
5185 | searching because only the original reg might | |
5186 | be in subreg when we changed the mode of | |
5187 | load/store for splitting. */ | |
5188 | && REG_P (SET_DEST (prev_set)) | |
5189 | && REG_P (SET_SRC (prev_set)) | |
5190 | && (int) REGNO (SET_DEST (prev_set)) == sregno | |
5191 | && ((prev_sregno = REGNO (SET_SRC (prev_set))) | |
5192 | >= FIRST_PSEUDO_REGISTER) | |
5193 | /* As we consider chain of inheritance or | |
5194 | splitting described in above comment we should | |
5195 | check that sregno and prev_sregno were | |
5196 | inheritance/split pseudos created from the | |
5197 | same original regno. */ | |
5198 | && (lra_reg_info[sregno].restore_regno | |
5199 | == lra_reg_info[prev_sregno].restore_regno) | |
5200 | && ! bitmap_bit_p (remove_pseudos, prev_sregno)) | |
5201 | { | |
5202 | lra_assert (GET_MODE (SET_SRC (prev_set)) | |
5203 | == GET_MODE (regno_reg_rtx[sregno])); | |
5204 | if (GET_CODE (SET_SRC (set)) == SUBREG) | |
5205 | SUBREG_REG (SET_SRC (set)) = SET_SRC (prev_set); | |
5206 | else | |
5207 | SET_SRC (set) = SET_SRC (prev_set); | |
5208 | lra_push_insn_and_update_insn_regno_info (curr_insn); | |
5209 | lra_set_used_insn_alternative_by_uid | |
5210 | (INSN_UID (curr_insn), -1); | |
5211 | done_p = true; | |
5212 | if (lra_dump_file != NULL) | |
5213 | { | |
5214 | fprintf (lra_dump_file, " Change reload insn:\n"); | |
cfbeaedf | 5215 | dump_insn_slim (lra_dump_file, curr_insn); |
55a2c322 VM |
5216 | } |
5217 | } | |
5218 | } | |
5219 | } | |
5220 | if (! done_p) | |
5221 | { | |
5222 | struct lra_insn_reg *reg; | |
5223 | bool restored_regs_p = false; | |
5224 | bool kept_regs_p = false; | |
5225 | ||
5226 | curr_id = lra_get_insn_recog_data (curr_insn); | |
5227 | for (reg = curr_id->regs; reg != NULL; reg = reg->next) | |
5228 | { | |
5229 | regno = reg->regno; | |
5230 | restore_regno = lra_reg_info[regno].restore_regno; | |
5231 | if (restore_regno >= 0) | |
5232 | { | |
5233 | if (change_p && bitmap_bit_p (remove_pseudos, regno)) | |
5234 | { | |
5235 | substitute_pseudo (&curr_insn, regno, | |
5236 | regno_reg_rtx[restore_regno]); | |
5237 | restored_regs_p = true; | |
5238 | } | |
5239 | else | |
5240 | kept_regs_p = true; | |
5241 | } | |
5242 | } | |
5243 | if (NONDEBUG_INSN_P (curr_insn) && kept_regs_p) | |
5244 | { | |
5245 | /* The instruction has changed since the previous | |
5246 | constraints pass. */ | |
5247 | lra_push_insn_and_update_insn_regno_info (curr_insn); | |
5248 | lra_set_used_insn_alternative_by_uid | |
5249 | (INSN_UID (curr_insn), -1); | |
5250 | } | |
5251 | else if (restored_regs_p) | |
5252 | /* The instruction has been restored to the form that | |
5253 | it had during the previous constraints pass. */ | |
5254 | lra_update_insn_regno_info (curr_insn); | |
5255 | if (restored_regs_p && lra_dump_file != NULL) | |
5256 | { | |
5257 | fprintf (lra_dump_file, " Insn after restoring regs:\n"); | |
cfbeaedf | 5258 | dump_insn_slim (lra_dump_file, curr_insn); |
55a2c322 VM |
5259 | } |
5260 | } | |
5261 | } | |
5262 | } | |
5263 | return change_p; | |
5264 | } | |
5265 | ||
5266 | /* Entry function for undoing inheritance/split transformation. Return true | |
5267 | if we did any RTL change in this pass. */ | |
5268 | bool | |
5269 | lra_undo_inheritance (void) | |
5270 | { | |
5271 | unsigned int regno; | |
5272 | int restore_regno, hard_regno; | |
5273 | int n_all_inherit, n_inherit, n_all_split, n_split; | |
5274 | bitmap_head remove_pseudos; | |
5275 | bitmap_iterator bi; | |
5276 | bool change_p; | |
5277 | ||
5278 | lra_undo_inheritance_iter++; | |
8e3a4869 | 5279 | if (lra_undo_inheritance_iter > LRA_MAX_INHERITANCE_PASSES) |
e731262b | 5280 | return false; |
55a2c322 VM |
5281 | if (lra_dump_file != NULL) |
5282 | fprintf (lra_dump_file, | |
5283 | "\n********** Undoing inheritance #%d: **********\n\n", | |
5284 | lra_undo_inheritance_iter); | |
5285 | bitmap_initialize (&remove_pseudos, ®_obstack); | |
5286 | n_inherit = n_all_inherit = 0; | |
5287 | EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos, 0, regno, bi) | |
5288 | if (lra_reg_info[regno].restore_regno >= 0) | |
5289 | { | |
5290 | n_all_inherit++; | |
5291 | if (reg_renumber[regno] < 0) | |
5292 | bitmap_set_bit (&remove_pseudos, regno); | |
5293 | else | |
5294 | n_inherit++; | |
5295 | } | |
5296 | if (lra_dump_file != NULL && n_all_inherit != 0) | |
5297 | fprintf (lra_dump_file, "Inherit %d out of %d (%.2f%%)\n", | |
5298 | n_inherit, n_all_inherit, | |
5299 | (double) n_inherit / n_all_inherit * 100); | |
5300 | n_split = n_all_split = 0; | |
5301 | EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs, 0, regno, bi) | |
5302 | if ((restore_regno = lra_reg_info[regno].restore_regno) >= 0) | |
5303 | { | |
5304 | n_all_split++; | |
5305 | hard_regno = (restore_regno >= FIRST_PSEUDO_REGISTER | |
5306 | ? reg_renumber[restore_regno] : restore_regno); | |
5307 | if (hard_regno < 0 || reg_renumber[regno] == hard_regno) | |
5308 | bitmap_set_bit (&remove_pseudos, regno); | |
5309 | else | |
5310 | { | |
5311 | n_split++; | |
5312 | if (lra_dump_file != NULL) | |
5313 | fprintf (lra_dump_file, " Keep split r%d (orig=r%d)\n", | |
5314 | regno, restore_regno); | |
5315 | } | |
5316 | } | |
5317 | if (lra_dump_file != NULL && n_all_split != 0) | |
5318 | fprintf (lra_dump_file, "Split %d out of %d (%.2f%%)\n", | |
5319 | n_split, n_all_split, | |
5320 | (double) n_split / n_all_split * 100); | |
5321 | change_p = remove_inheritance_pseudos (&remove_pseudos); | |
5322 | bitmap_clear (&remove_pseudos); | |
5323 | /* Clear restore_regnos. */ | |
5324 | EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos, 0, regno, bi) | |
5325 | lra_reg_info[regno].restore_regno = -1; | |
5326 | EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs, 0, regno, bi) | |
5327 | lra_reg_info[regno].restore_regno = -1; | |
5328 | return change_p; | |
5329 | } |