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55a2c322 | 1 | /* Code for RTL transformations to satisfy insn constraints. |
99dee823 | 2 | Copyright (C) 2010-2021 Free Software Foundation, Inc. |
55a2c322 VM |
3 | Contributed by Vladimir Makarov <vmakarov@redhat.com>. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it under | |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 3, or (at your option) any later | |
10 | version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | ||
22 | /* This file contains code for 3 passes: constraint pass, | |
23 | inheritance/split pass, and pass for undoing failed inheritance and | |
24 | split. | |
25 | ||
26 | The major goal of constraint pass is to transform RTL to satisfy | |
27 | insn and address constraints by: | |
28 | o choosing insn alternatives; | |
29 | o generating *reload insns* (or reloads in brief) and *reload | |
30 | pseudos* which will get necessary hard registers later; | |
31 | o substituting pseudos with equivalent values and removing the | |
32 | instructions that initialized those pseudos. | |
33 | ||
34 | The constraint pass has biggest and most complicated code in LRA. | |
35 | There are a lot of important details like: | |
36 | o reuse of input reload pseudos to simplify reload pseudo | |
37 | allocations; | |
38 | o some heuristics to choose insn alternative to improve the | |
39 | inheritance; | |
40 | o early clobbers etc. | |
41 | ||
42 | The pass is mimicking former reload pass in alternative choosing | |
43 | because the reload pass is oriented to current machine description | |
44 | model. It might be changed if the machine description model is | |
45 | changed. | |
46 | ||
47 | There is special code for preventing all LRA and this pass cycling | |
48 | in case of bugs. | |
49 | ||
50 | On the first iteration of the pass we process every instruction and | |
51 | choose an alternative for each one. On subsequent iterations we try | |
52 | to avoid reprocessing instructions if we can be sure that the old | |
53 | choice is still valid. | |
54 | ||
55 | The inheritance/spilt pass is to transform code to achieve | |
56 | ineheritance and live range splitting. It is done on backward | |
57 | traversal of EBBs. | |
58 | ||
59 | The inheritance optimization goal is to reuse values in hard | |
60 | registers. There is analogous optimization in old reload pass. The | |
61 | inheritance is achieved by following transformation: | |
62 | ||
63 | reload_p1 <- p reload_p1 <- p | |
64 | ... new_p <- reload_p1 | |
65 | ... => ... | |
66 | reload_p2 <- p reload_p2 <- new_p | |
67 | ||
68 | where p is spilled and not changed between the insns. Reload_p1 is | |
69 | also called *original pseudo* and new_p is called *inheritance | |
70 | pseudo*. | |
71 | ||
72 | The subsequent assignment pass will try to assign the same (or | |
73 | another if it is not possible) hard register to new_p as to | |
74 | reload_p1 or reload_p2. | |
75 | ||
76 | If the assignment pass fails to assign a hard register to new_p, | |
77 | this file will undo the inheritance and restore the original code. | |
78 | This is because implementing the above sequence with a spilled | |
79 | new_p would make the code much worse. The inheritance is done in | |
80 | EBB scope. The above is just a simplified example to get an idea | |
81 | of the inheritance as the inheritance is also done for non-reload | |
82 | insns. | |
83 | ||
84 | Splitting (transformation) is also done in EBB scope on the same | |
85 | pass as the inheritance: | |
86 | ||
87 | r <- ... or ... <- r r <- ... or ... <- r | |
88 | ... s <- r (new insn -- save) | |
f4eafc30 | 89 | ... => |
55a2c322 VM |
90 | ... r <- s (new insn -- restore) |
91 | ... <- r ... <- r | |
92 | ||
93 | The *split pseudo* s is assigned to the hard register of the | |
94 | original pseudo or hard register r. | |
95 | ||
96 | Splitting is done: | |
97 | o In EBBs with high register pressure for global pseudos (living | |
98 | in at least 2 BBs) and assigned to hard registers when there | |
99 | are more one reloads needing the hard registers; | |
100 | o for pseudos needing save/restore code around calls. | |
101 | ||
102 | If the split pseudo still has the same hard register as the | |
103 | original pseudo after the subsequent assignment pass or the | |
104 | original pseudo was split, the opposite transformation is done on | |
105 | the same pass for undoing inheritance. */ | |
106 | ||
107 | #undef REG_OK_STRICT | |
108 | ||
109 | #include "config.h" | |
110 | #include "system.h" | |
111 | #include "coretypes.h" | |
c7131fb2 | 112 | #include "backend.h" |
957060b5 | 113 | #include "target.h" |
55a2c322 | 114 | #include "rtl.h" |
957060b5 AM |
115 | #include "tree.h" |
116 | #include "predict.h" | |
c7131fb2 | 117 | #include "df.h" |
4d0cdd0c | 118 | #include "memmodel.h" |
55a2c322 | 119 | #include "tm_p.h" |
957060b5 AM |
120 | #include "expmed.h" |
121 | #include "optabs.h" | |
55a2c322 | 122 | #include "regs.h" |
957060b5 | 123 | #include "ira.h" |
55a2c322 VM |
124 | #include "recog.h" |
125 | #include "output.h" | |
126 | #include "addresses.h" | |
55a2c322 | 127 | #include "expr.h" |
60393bbc | 128 | #include "cfgrtl.h" |
55a2c322 | 129 | #include "rtl-error.h" |
c7131fb2 | 130 | #include "lra.h" |
55a2c322 | 131 | #include "lra-int.h" |
013a8899 | 132 | #include "print-rtl.h" |
6ee2cc70 | 133 | #include "function-abi.h" |
6b3034ea | 134 | #include "rtl-iter.h" |
55a2c322 VM |
135 | |
136 | /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current | |
137 | insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted | |
138 | reload insns. */ | |
139 | static int bb_reload_num; | |
140 | ||
2c62cbaa VM |
141 | /* The current insn being processed and corresponding its single set |
142 | (NULL otherwise), its data (basic block, the insn data, the insn | |
143 | static data, and the mode of each operand). */ | |
cfa434f6 | 144 | static rtx_insn *curr_insn; |
2c62cbaa | 145 | static rtx curr_insn_set; |
55a2c322 VM |
146 | static basic_block curr_bb; |
147 | static lra_insn_recog_data_t curr_id; | |
148 | static struct lra_static_insn_data *curr_static_id; | |
ef4bddc2 | 149 | static machine_mode curr_operand_mode[MAX_RECOG_OPERANDS]; |
895ff86f VM |
150 | /* Mode of the register substituted by its equivalence with VOIDmode |
151 | (e.g. constant) and whose subreg is given operand of the current | |
152 | insn. VOIDmode in all other cases. */ | |
153 | static machine_mode original_subreg_reg_mode[MAX_RECOG_OPERANDS]; | |
55a2c322 VM |
154 | |
155 | \f | |
156 | ||
157 | /* Start numbers for new registers and insns at the current constraints | |
158 | pass start. */ | |
159 | static int new_regno_start; | |
160 | static int new_insn_uid_start; | |
161 | ||
277f65de RS |
162 | /* If LOC is nonnull, strip any outer subreg from it. */ |
163 | static inline rtx * | |
164 | strip_subreg (rtx *loc) | |
165 | { | |
166 | return loc && GET_CODE (*loc) == SUBREG ? &SUBREG_REG (*loc) : loc; | |
167 | } | |
168 | ||
55a2c322 VM |
169 | /* Return hard regno of REGNO or if it is was not assigned to a hard |
170 | register, use a hard register from its allocno class. */ | |
171 | static int | |
172 | get_try_hard_regno (int regno) | |
173 | { | |
174 | int hard_regno; | |
175 | enum reg_class rclass; | |
176 | ||
177 | if ((hard_regno = regno) >= FIRST_PSEUDO_REGISTER) | |
178 | hard_regno = lra_get_regno_hard_regno (regno); | |
179 | if (hard_regno >= 0) | |
180 | return hard_regno; | |
181 | rclass = lra_get_allocno_class (regno); | |
182 | if (rclass == NO_REGS) | |
183 | return -1; | |
184 | return ira_class_hard_regs[rclass][0]; | |
185 | } | |
186 | ||
9d0a9bb4 PB |
187 | /* Return the hard regno of X after removing its subreg. If X is not |
188 | a register or a subreg of a register, return -1. If X is a pseudo, | |
1686923c BE |
189 | use its assignment. If FINAL_P return the final hard regno which will |
190 | be after elimination. */ | |
55a2c322 | 191 | static int |
1686923c | 192 | get_hard_regno (rtx x, bool final_p) |
55a2c322 VM |
193 | { |
194 | rtx reg; | |
1686923c | 195 | int hard_regno; |
55a2c322 VM |
196 | |
197 | reg = x; | |
9d0a9bb4 | 198 | if (SUBREG_P (x)) |
55a2c322 VM |
199 | reg = SUBREG_REG (x); |
200 | if (! REG_P (reg)) | |
201 | return -1; | |
9d0a9bb4 | 202 | if (! HARD_REGISTER_NUM_P (hard_regno = REGNO (reg))) |
55a2c322 VM |
203 | hard_regno = lra_get_regno_hard_regno (hard_regno); |
204 | if (hard_regno < 0) | |
205 | return -1; | |
1686923c BE |
206 | if (final_p) |
207 | hard_regno = lra_get_elimination_hard_regno (hard_regno); | |
9d0a9bb4 | 208 | if (SUBREG_P (x)) |
1686923c BE |
209 | hard_regno += subreg_regno_offset (hard_regno, GET_MODE (reg), |
210 | SUBREG_BYTE (x), GET_MODE (x)); | |
211 | return hard_regno; | |
55a2c322 VM |
212 | } |
213 | ||
214 | /* If REGNO is a hard register or has been allocated a hard register, | |
215 | return the class of that register. If REGNO is a reload pseudo | |
216 | created by the current constraints pass, return its allocno class. | |
217 | Return NO_REGS otherwise. */ | |
218 | static enum reg_class | |
219 | get_reg_class (int regno) | |
220 | { | |
221 | int hard_regno; | |
222 | ||
1686923c | 223 | if (! HARD_REGISTER_NUM_P (hard_regno = regno)) |
55a2c322 VM |
224 | hard_regno = lra_get_regno_hard_regno (regno); |
225 | if (hard_regno >= 0) | |
226 | { | |
1686923c | 227 | hard_regno = lra_get_elimination_hard_regno (hard_regno); |
55a2c322 VM |
228 | return REGNO_REG_CLASS (hard_regno); |
229 | } | |
230 | if (regno >= new_regno_start) | |
231 | return lra_get_allocno_class (regno); | |
232 | return NO_REGS; | |
233 | } | |
234 | ||
235 | /* Return true if REG satisfies (or will satisfy) reg class constraint | |
236 | CL. Use elimination first if REG is a hard register. If REG is a | |
237 | reload pseudo created by this constraints pass, assume that it will | |
238 | be allocated a hard register from its allocno class, but allow that | |
6001db79 RS |
239 | class to be narrowed to CL if it is currently a superset of CL and |
240 | if either: | |
241 | ||
242 | - ALLOW_ALL_RELOAD_CLASS_CHANGES_P is true or | |
243 | - the instruction we're processing is not a reload move. | |
55a2c322 VM |
244 | |
245 | If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of | |
246 | REGNO (reg), or NO_REGS if no change in its class was needed. */ | |
247 | static bool | |
6001db79 RS |
248 | in_class_p (rtx reg, enum reg_class cl, enum reg_class *new_class, |
249 | bool allow_all_reload_class_changes_p = false) | |
55a2c322 VM |
250 | { |
251 | enum reg_class rclass, common_class; | |
ef4bddc2 | 252 | machine_mode reg_mode; |
7f9f83ef | 253 | rtx src; |
55a2c322 VM |
254 | int class_size, hard_regno, nregs, i, j; |
255 | int regno = REGNO (reg); | |
f4eafc30 | 256 | |
55a2c322 VM |
257 | if (new_class != NULL) |
258 | *new_class = NO_REGS; | |
259 | if (regno < FIRST_PSEUDO_REGISTER) | |
260 | { | |
261 | rtx final_reg = reg; | |
262 | rtx *final_loc = &final_reg; | |
f4eafc30 | 263 | |
55a2c322 VM |
264 | lra_eliminate_reg_if_possible (final_loc); |
265 | return TEST_HARD_REG_BIT (reg_class_contents[cl], REGNO (*final_loc)); | |
266 | } | |
267 | reg_mode = GET_MODE (reg); | |
268 | rclass = get_reg_class (regno); | |
7f9f83ef | 269 | src = curr_insn_set != NULL ? SET_SRC (curr_insn_set) : NULL; |
55a2c322 VM |
270 | if (regno < new_regno_start |
271 | /* Do not allow the constraints for reload instructions to | |
272 | influence the classes of new pseudos. These reloads are | |
273 | typically moves that have many alternatives, and restricting | |
274 | reload pseudos for one alternative may lead to situations | |
275 | where other reload pseudos are no longer allocatable. */ | |
6001db79 RS |
276 | || (!allow_all_reload_class_changes_p |
277 | && INSN_UID (curr_insn) >= new_insn_uid_start | |
7f9f83ef VM |
278 | && src != NULL |
279 | && ((REG_P (src) || MEM_P (src)) | |
280 | || (GET_CODE (src) == SUBREG | |
281 | && (REG_P (SUBREG_REG (src)) || MEM_P (SUBREG_REG (src))))))) | |
55a2c322 VM |
282 | /* When we don't know what class will be used finally for reload |
283 | pseudos, we use ALL_REGS. */ | |
284 | return ((regno >= new_regno_start && rclass == ALL_REGS) | |
285 | || (rclass != NO_REGS && ira_class_subset_p[rclass][cl] | |
286 | && ! hard_reg_set_subset_p (reg_class_contents[cl], | |
287 | lra_no_alloc_regs))); | |
288 | else | |
289 | { | |
290 | common_class = ira_reg_class_subset[rclass][cl]; | |
291 | if (new_class != NULL) | |
292 | *new_class = common_class; | |
293 | if (hard_reg_set_subset_p (reg_class_contents[common_class], | |
294 | lra_no_alloc_regs)) | |
295 | return false; | |
296 | /* Check that there are enough allocatable regs. */ | |
297 | class_size = ira_class_hard_regs_num[common_class]; | |
298 | for (i = 0; i < class_size; i++) | |
299 | { | |
300 | hard_regno = ira_class_hard_regs[common_class][i]; | |
ad474626 | 301 | nregs = hard_regno_nregs (hard_regno, reg_mode); |
55a2c322 VM |
302 | if (nregs == 1) |
303 | return true; | |
304 | for (j = 0; j < nregs; j++) | |
f421c426 VM |
305 | if (TEST_HARD_REG_BIT (lra_no_alloc_regs, hard_regno + j) |
306 | || ! TEST_HARD_REG_BIT (reg_class_contents[common_class], | |
307 | hard_regno + j)) | |
55a2c322 VM |
308 | break; |
309 | if (j >= nregs) | |
310 | return true; | |
311 | } | |
312 | return false; | |
313 | } | |
314 | } | |
315 | ||
316 | /* Return true if REGNO satisfies a memory constraint. */ | |
317 | static bool | |
318 | in_mem_p (int regno) | |
319 | { | |
320 | return get_reg_class (regno) == NO_REGS; | |
321 | } | |
322 | ||
a953491e RS |
323 | /* Return 1 if ADDR is a valid memory address for mode MODE in address |
324 | space AS, and check that each pseudo has the proper kind of hard | |
325 | reg. */ | |
326 | static int | |
ef4bddc2 | 327 | valid_address_p (machine_mode mode ATTRIBUTE_UNUSED, |
a953491e RS |
328 | rtx addr, addr_space_t as) |
329 | { | |
330 | #ifdef GO_IF_LEGITIMATE_ADDRESS | |
331 | lra_assert (ADDR_SPACE_GENERIC_P (as)); | |
332 | GO_IF_LEGITIMATE_ADDRESS (mode, addr, win); | |
333 | return 0; | |
334 | ||
335 | win: | |
336 | return 1; | |
337 | #else | |
338 | return targetm.addr_space.legitimate_address_p (mode, addr, 0, as); | |
339 | #endif | |
340 | } | |
341 | ||
342 | namespace { | |
343 | /* Temporarily eliminates registers in an address (for the lifetime of | |
344 | the object). */ | |
345 | class address_eliminator { | |
346 | public: | |
347 | address_eliminator (struct address_info *ad); | |
348 | ~address_eliminator (); | |
349 | ||
350 | private: | |
351 | struct address_info *m_ad; | |
352 | rtx *m_base_loc; | |
353 | rtx m_base_reg; | |
354 | rtx *m_index_loc; | |
355 | rtx m_index_reg; | |
356 | }; | |
357 | } | |
358 | ||
359 | address_eliminator::address_eliminator (struct address_info *ad) | |
360 | : m_ad (ad), | |
361 | m_base_loc (strip_subreg (ad->base_term)), | |
362 | m_base_reg (NULL_RTX), | |
363 | m_index_loc (strip_subreg (ad->index_term)), | |
364 | m_index_reg (NULL_RTX) | |
365 | { | |
366 | if (m_base_loc != NULL) | |
367 | { | |
368 | m_base_reg = *m_base_loc; | |
9cb95c07 VM |
369 | /* If we have non-legitimate address which is decomposed not in |
370 | the way we expected, don't do elimination here. In such case | |
371 | the address will be reloaded and elimination will be done in | |
372 | reload insn finally. */ | |
373 | if (REG_P (m_base_reg)) | |
374 | lra_eliminate_reg_if_possible (m_base_loc); | |
a953491e RS |
375 | if (m_ad->base_term2 != NULL) |
376 | *m_ad->base_term2 = *m_ad->base_term; | |
377 | } | |
378 | if (m_index_loc != NULL) | |
379 | { | |
380 | m_index_reg = *m_index_loc; | |
9cb95c07 VM |
381 | if (REG_P (m_index_reg)) |
382 | lra_eliminate_reg_if_possible (m_index_loc); | |
a953491e RS |
383 | } |
384 | } | |
385 | ||
386 | address_eliminator::~address_eliminator () | |
387 | { | |
388 | if (m_base_loc && *m_base_loc != m_base_reg) | |
389 | { | |
390 | *m_base_loc = m_base_reg; | |
391 | if (m_ad->base_term2 != NULL) | |
392 | *m_ad->base_term2 = *m_ad->base_term; | |
393 | } | |
394 | if (m_index_loc && *m_index_loc != m_index_reg) | |
395 | *m_index_loc = m_index_reg; | |
396 | } | |
397 | ||
1aeffdce RS |
398 | /* Return true if the eliminated form of AD is a legitimate target address. |
399 | If OP is a MEM, AD is the address within OP, otherwise OP should be | |
400 | ignored. CONSTRAINT is one constraint that the operand may need | |
401 | to meet. */ | |
a953491e | 402 | static bool |
1aeffdce RS |
403 | valid_address_p (rtx op, struct address_info *ad, |
404 | enum constraint_num constraint) | |
a953491e RS |
405 | { |
406 | address_eliminator eliminator (ad); | |
1aeffdce RS |
407 | |
408 | /* Allow a memory OP if it matches CONSTRAINT, even if CONSTRAINT is more | |
db8b3e14 | 409 | forgiving than "m". |
410 | Need to extract memory from op for special memory constraint, | |
411 | i.e. bcst_mem_operand in i386 backend. */ | |
412 | if (MEM_P (extract_mem_from_operand (op)) | |
02f2dc44 | 413 | && insn_extra_relaxed_memory_constraint (constraint) |
1aeffdce RS |
414 | && constraint_satisfied_p (op, constraint)) |
415 | return true; | |
416 | ||
a953491e RS |
417 | return valid_address_p (ad->mode, *ad->outer, ad->as); |
418 | } | |
419 | ||
4de7b010 | 420 | /* For special_memory_operand, it could be false for MEM_P (op), |
421 | i.e. bcst_mem_operand in i386 backend. | |
422 | Extract and return real memory operand or op. */ | |
423 | rtx | |
424 | extract_mem_from_operand (rtx op) | |
425 | { | |
426 | for (rtx x = op;; x = XEXP (x, 0)) | |
427 | { | |
428 | if (MEM_P (x)) | |
429 | return x; | |
430 | if (GET_RTX_LENGTH (GET_CODE (x)) != 1 | |
431 | || GET_RTX_FORMAT (GET_CODE (x))[0] != 'e') | |
432 | break; | |
433 | } | |
434 | return op; | |
435 | } | |
436 | ||
a953491e | 437 | /* Return true if the eliminated form of memory reference OP satisfies |
9eb1ca69 | 438 | extra (special) memory constraint CONSTRAINT. */ |
a953491e | 439 | static bool |
777e635f | 440 | satisfies_memory_constraint_p (rtx op, enum constraint_num constraint) |
a953491e RS |
441 | { |
442 | struct address_info ad; | |
4de7b010 | 443 | rtx mem = extract_mem_from_operand (op); |
444 | if (!MEM_P (mem)) | |
445 | return false; | |
a953491e | 446 | |
4de7b010 | 447 | decompose_mem_address (&ad, mem); |
a953491e | 448 | address_eliminator eliminator (&ad); |
777e635f | 449 | return constraint_satisfied_p (op, constraint); |
a953491e RS |
450 | } |
451 | ||
452 | /* Return true if the eliminated form of address AD satisfies extra | |
453 | address constraint CONSTRAINT. */ | |
454 | static bool | |
455 | satisfies_address_constraint_p (struct address_info *ad, | |
777e635f | 456 | enum constraint_num constraint) |
a953491e RS |
457 | { |
458 | address_eliminator eliminator (ad); | |
777e635f | 459 | return constraint_satisfied_p (*ad->outer, constraint); |
a953491e RS |
460 | } |
461 | ||
462 | /* Return true if the eliminated form of address OP satisfies extra | |
463 | address constraint CONSTRAINT. */ | |
464 | static bool | |
777e635f | 465 | satisfies_address_constraint_p (rtx op, enum constraint_num constraint) |
a953491e RS |
466 | { |
467 | struct address_info ad; | |
468 | ||
469 | decompose_lea_address (&ad, &op); | |
470 | return satisfies_address_constraint_p (&ad, constraint); | |
471 | } | |
a953491e | 472 | |
4c2b2d79 VM |
473 | /* Initiate equivalences for LRA. As we keep original equivalences |
474 | before any elimination, we need to make copies otherwise any change | |
475 | in insns might change the equivalences. */ | |
476 | void | |
477 | lra_init_equiv (void) | |
478 | { | |
479 | ira_expand_reg_equiv (); | |
480 | for (int i = FIRST_PSEUDO_REGISTER; i < max_reg_num (); i++) | |
481 | { | |
482 | rtx res; | |
483 | ||
484 | if ((res = ira_reg_equiv[i].memory) != NULL_RTX) | |
485 | ira_reg_equiv[i].memory = copy_rtx (res); | |
486 | if ((res = ira_reg_equiv[i].invariant) != NULL_RTX) | |
487 | ira_reg_equiv[i].invariant = copy_rtx (res); | |
488 | } | |
489 | } | |
490 | ||
491 | static rtx loc_equivalence_callback (rtx, const_rtx, void *); | |
492 | ||
493 | /* Update equivalence for REGNO. We need to this as the equivalence | |
494 | might contain other pseudos which are changed by their | |
495 | equivalences. */ | |
496 | static void | |
497 | update_equiv (int regno) | |
498 | { | |
499 | rtx x; | |
500 | ||
501 | if ((x = ira_reg_equiv[regno].memory) != NULL_RTX) | |
502 | ira_reg_equiv[regno].memory | |
503 | = simplify_replace_fn_rtx (x, NULL_RTX, loc_equivalence_callback, | |
504 | NULL_RTX); | |
505 | if ((x = ira_reg_equiv[regno].invariant) != NULL_RTX) | |
506 | ira_reg_equiv[regno].invariant | |
507 | = simplify_replace_fn_rtx (x, NULL_RTX, loc_equivalence_callback, | |
508 | NULL_RTX); | |
509 | } | |
510 | ||
55a2c322 VM |
511 | /* If we have decided to substitute X with another value, return that |
512 | value, otherwise return X. */ | |
513 | static rtx | |
8d49e7ef | 514 | get_equiv (rtx x) |
55a2c322 VM |
515 | { |
516 | int regno; | |
517 | rtx res; | |
518 | ||
519 | if (! REG_P (x) || (regno = REGNO (x)) < FIRST_PSEUDO_REGISTER | |
520 | || ! ira_reg_equiv[regno].defined_p | |
521 | || ! ira_reg_equiv[regno].profitable_p | |
522 | || lra_get_regno_hard_regno (regno) >= 0) | |
523 | return x; | |
524 | if ((res = ira_reg_equiv[regno].memory) != NULL_RTX) | |
d6220b11 KK |
525 | { |
526 | if (targetm.cannot_substitute_mem_equiv_p (res)) | |
527 | return x; | |
528 | return res; | |
529 | } | |
55a2c322 VM |
530 | if ((res = ira_reg_equiv[regno].constant) != NULL_RTX) |
531 | return res; | |
532 | if ((res = ira_reg_equiv[regno].invariant) != NULL_RTX) | |
533 | return res; | |
534 | gcc_unreachable (); | |
535 | } | |
536 | ||
8d49e7ef VM |
537 | /* If we have decided to substitute X with the equivalent value, |
538 | return that value after elimination for INSN, otherwise return | |
539 | X. */ | |
540 | static rtx | |
cfa434f6 | 541 | get_equiv_with_elimination (rtx x, rtx_insn *insn) |
8d49e7ef VM |
542 | { |
543 | rtx res = get_equiv (x); | |
544 | ||
545 | if (x == res || CONSTANT_P (res)) | |
546 | return res; | |
d9cf932c | 547 | return lra_eliminate_regs_1 (insn, res, GET_MODE (res), |
a6af1bf9 | 548 | false, false, 0, true); |
8d49e7ef VM |
549 | } |
550 | ||
55a2c322 VM |
551 | /* Set up curr_operand_mode. */ |
552 | static void | |
553 | init_curr_operand_mode (void) | |
554 | { | |
555 | int nop = curr_static_id->n_operands; | |
556 | for (int i = 0; i < nop; i++) | |
557 | { | |
ef4bddc2 | 558 | machine_mode mode = GET_MODE (*curr_id->operand_loc[i]); |
55a2c322 VM |
559 | if (mode == VOIDmode) |
560 | { | |
561 | /* The .md mode for address operands is the mode of the | |
562 | addressed value rather than the mode of the address itself. */ | |
563 | if (curr_id->icode >= 0 && curr_static_id->operand[i].is_address) | |
564 | mode = Pmode; | |
565 | else | |
566 | mode = curr_static_id->operand[i].mode; | |
567 | } | |
568 | curr_operand_mode[i] = mode; | |
569 | } | |
570 | } | |
571 | ||
572 | \f | |
573 | ||
574 | /* The page contains code to reuse input reloads. */ | |
575 | ||
576 | /* Structure describes input reload of the current insns. */ | |
577 | struct input_reload | |
578 | { | |
3f156a6c VM |
579 | /* True for input reload of matched operands. */ |
580 | bool match_p; | |
55a2c322 VM |
581 | /* Reloaded value. */ |
582 | rtx input; | |
583 | /* Reload pseudo used. */ | |
584 | rtx reg; | |
585 | }; | |
586 | ||
587 | /* The number of elements in the following array. */ | |
588 | static int curr_insn_input_reloads_num; | |
589 | /* Array containing info about input reloads. It is used to find the | |
590 | same input reload and reuse the reload pseudo in this case. */ | |
591 | static struct input_reload curr_insn_input_reloads[LRA_MAX_INSN_RELOADS]; | |
592 | ||
593 | /* Initiate data concerning reuse of input reloads for the current | |
594 | insn. */ | |
595 | static void | |
596 | init_curr_insn_input_reloads (void) | |
597 | { | |
598 | curr_insn_input_reloads_num = 0; | |
599 | } | |
600 | ||
6b3034ea AC |
601 | /* The canonical form of an rtx inside a MEM is not necessarily the same as the |
602 | canonical form of the rtx outside the MEM. Fix this up in the case that | |
603 | we're reloading an address (and therefore pulling it outside a MEM). */ | |
604 | static rtx | |
605 | canonicalize_reload_addr (rtx addr) | |
606 | { | |
607 | subrtx_var_iterator::array_type array; | |
608 | FOR_EACH_SUBRTX_VAR (iter, array, addr, NONCONST) | |
609 | { | |
610 | rtx x = *iter; | |
611 | if (GET_CODE (x) == MULT && CONST_INT_P (XEXP (x, 1))) | |
612 | { | |
613 | const HOST_WIDE_INT ci = INTVAL (XEXP (x, 1)); | |
614 | const int pwr2 = exact_log2 (ci); | |
615 | if (pwr2 > 0) | |
616 | { | |
617 | /* Rewrite this to use a shift instead, which is canonical when | |
618 | outside of a MEM. */ | |
619 | PUT_CODE (x, ASHIFT); | |
620 | XEXP (x, 1) = GEN_INT (pwr2); | |
621 | } | |
622 | } | |
623 | } | |
624 | ||
625 | return addr; | |
626 | } | |
627 | ||
6001db79 RS |
628 | /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse an existing |
629 | reload pseudo. Don't reuse an existing reload pseudo if IN_SUBREG_P | |
630 | is true and the reused pseudo should be wrapped up in a SUBREG. | |
631 | The result pseudo is returned through RESULT_REG. Return TRUE if we | |
632 | created a new pseudo, FALSE if we reused an existing reload pseudo. | |
633 | Use TITLE to describe new registers for debug purposes. */ | |
55a2c322 | 634 | static bool |
ef4bddc2 | 635 | get_reload_reg (enum op_type type, machine_mode mode, rtx original, |
95921002 VM |
636 | enum reg_class rclass, bool in_subreg_p, |
637 | const char *title, rtx *result_reg) | |
55a2c322 VM |
638 | { |
639 | int i, regno; | |
640 | enum reg_class new_class; | |
3f156a6c | 641 | bool unique_p = false; |
55a2c322 VM |
642 | |
643 | if (type == OP_OUT) | |
644 | { | |
6001db79 RS |
645 | /* Output reload registers tend to start out with a conservative |
646 | choice of register class. Usually this is ALL_REGS, although | |
647 | a target might narrow it (for performance reasons) through | |
648 | targetm.preferred_reload_class. It's therefore quite common | |
649 | for a reload instruction to require a more restrictive class | |
650 | than the class that was originally assigned to the reload register. | |
651 | ||
652 | In these situations, it's more efficient to refine the choice | |
653 | of register class rather than create a second reload register. | |
654 | This also helps to avoid cycling for registers that are only | |
655 | used by reload instructions. */ | |
656 | if (REG_P (original) | |
657 | && (int) REGNO (original) >= new_regno_start | |
658 | && INSN_UID (curr_insn) >= new_insn_uid_start | |
659 | && in_class_p (original, rclass, &new_class, true)) | |
660 | { | |
661 | unsigned int regno = REGNO (original); | |
662 | if (lra_dump_file != NULL) | |
663 | { | |
664 | fprintf (lra_dump_file, " Reuse r%d for output ", regno); | |
665 | dump_value_slim (lra_dump_file, original, 1); | |
666 | } | |
667 | if (new_class != lra_get_allocno_class (regno)) | |
668 | lra_change_class (regno, new_class, ", change to", false); | |
669 | if (lra_dump_file != NULL) | |
670 | fprintf (lra_dump_file, "\n"); | |
671 | *result_reg = original; | |
672 | return false; | |
673 | } | |
55a2c322 VM |
674 | *result_reg |
675 | = lra_create_new_reg_with_unique_value (mode, original, rclass, title); | |
676 | return true; | |
677 | } | |
73cca0cc VM |
678 | /* Prevent reuse value of expression with side effects, |
679 | e.g. volatile memory. */ | |
680 | if (! side_effects_p (original)) | |
681 | for (i = 0; i < curr_insn_input_reloads_num; i++) | |
3f156a6c VM |
682 | { |
683 | if (! curr_insn_input_reloads[i].match_p | |
684 | && rtx_equal_p (curr_insn_input_reloads[i].input, original) | |
685 | && in_class_p (curr_insn_input_reloads[i].reg, rclass, &new_class)) | |
686 | { | |
687 | rtx reg = curr_insn_input_reloads[i].reg; | |
688 | regno = REGNO (reg); | |
689 | /* If input is equal to original and both are VOIDmode, | |
690 | GET_MODE (reg) might be still different from mode. | |
691 | Ensure we don't return *result_reg with wrong mode. */ | |
692 | if (GET_MODE (reg) != mode) | |
693 | { | |
694 | if (in_subreg_p) | |
695 | continue; | |
cf098191 RS |
696 | if (maybe_lt (GET_MODE_SIZE (GET_MODE (reg)), |
697 | GET_MODE_SIZE (mode))) | |
3f156a6c VM |
698 | continue; |
699 | reg = lowpart_subreg (mode, reg, GET_MODE (reg)); | |
700 | if (reg == NULL_RTX || GET_CODE (reg) != SUBREG) | |
701 | continue; | |
702 | } | |
703 | *result_reg = reg; | |
704 | if (lra_dump_file != NULL) | |
705 | { | |
706 | fprintf (lra_dump_file, " Reuse r%d for reload ", regno); | |
707 | dump_value_slim (lra_dump_file, original, 1); | |
708 | } | |
709 | if (new_class != lra_get_allocno_class (regno)) | |
710 | lra_change_class (regno, new_class, ", change to", false); | |
711 | if (lra_dump_file != NULL) | |
712 | fprintf (lra_dump_file, "\n"); | |
713 | return false; | |
714 | } | |
715 | /* If we have an input reload with a different mode, make sure it | |
716 | will get a different hard reg. */ | |
717 | else if (REG_P (original) | |
718 | && REG_P (curr_insn_input_reloads[i].input) | |
719 | && REGNO (original) == REGNO (curr_insn_input_reloads[i].input) | |
720 | && (GET_MODE (original) | |
721 | != GET_MODE (curr_insn_input_reloads[i].input))) | |
722 | unique_p = true; | |
723 | } | |
724 | *result_reg = (unique_p | |
725 | ? lra_create_new_reg_with_unique_value | |
726 | : lra_create_new_reg) (mode, original, rclass, title); | |
55a2c322 VM |
727 | lra_assert (curr_insn_input_reloads_num < LRA_MAX_INSN_RELOADS); |
728 | curr_insn_input_reloads[curr_insn_input_reloads_num].input = original; | |
3f156a6c | 729 | curr_insn_input_reloads[curr_insn_input_reloads_num].match_p = false; |
55a2c322 VM |
730 | curr_insn_input_reloads[curr_insn_input_reloads_num++].reg = *result_reg; |
731 | return true; | |
732 | } | |
733 | ||
734 | \f | |
55a2c322 VM |
735 | /* The page contains major code to choose the current insn alternative |
736 | and generate reloads for it. */ | |
737 | ||
738 | /* Return the offset from REGNO of the least significant register | |
739 | in (reg:MODE REGNO). | |
740 | ||
741 | This function is used to tell whether two registers satisfy | |
742 | a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if: | |
743 | ||
744 | REGNO1 + lra_constraint_offset (REGNO1, MODE1) | |
745 | == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */ | |
746 | int | |
ef4bddc2 | 747 | lra_constraint_offset (int regno, machine_mode mode) |
55a2c322 VM |
748 | { |
749 | lra_assert (regno < FIRST_PSEUDO_REGISTER); | |
b0567726 RS |
750 | |
751 | scalar_int_mode int_mode; | |
752 | if (WORDS_BIG_ENDIAN | |
753 | && is_a <scalar_int_mode> (mode, &int_mode) | |
754 | && GET_MODE_SIZE (int_mode) > UNITS_PER_WORD) | |
ad474626 | 755 | return hard_regno_nregs (regno, mode) - 1; |
55a2c322 VM |
756 | return 0; |
757 | } | |
758 | ||
759 | /* Like rtx_equal_p except that it allows a REG and a SUBREG to match | |
760 | if they are the same hard reg, and has special hacks for | |
761 | auto-increment and auto-decrement. This is specifically intended for | |
762 | process_alt_operands to use in determining whether two operands | |
763 | match. X is the operand whose number is the lower of the two. | |
764 | ||
765 | It is supposed that X is the output operand and Y is the input | |
766 | operand. Y_HARD_REGNO is the final hard regno of register Y or | |
767 | register in subreg Y as we know it now. Otherwise, it is a | |
768 | negative value. */ | |
769 | static bool | |
770 | operands_match_p (rtx x, rtx y, int y_hard_regno) | |
771 | { | |
772 | int i; | |
773 | RTX_CODE code = GET_CODE (x); | |
774 | const char *fmt; | |
775 | ||
776 | if (x == y) | |
777 | return true; | |
778 | if ((code == REG || (code == SUBREG && REG_P (SUBREG_REG (x)))) | |
779 | && (REG_P (y) || (GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y))))) | |
780 | { | |
781 | int j; | |
f4eafc30 | 782 | |
1686923c | 783 | i = get_hard_regno (x, false); |
55a2c322 VM |
784 | if (i < 0) |
785 | goto slow; | |
786 | ||
787 | if ((j = y_hard_regno) < 0) | |
788 | goto slow; | |
789 | ||
790 | i += lra_constraint_offset (i, GET_MODE (x)); | |
791 | j += lra_constraint_offset (j, GET_MODE (y)); | |
792 | ||
793 | return i == j; | |
794 | } | |
795 | ||
796 | /* If two operands must match, because they are really a single | |
797 | operand of an assembler insn, then two post-increments are invalid | |
798 | because the assembler insn would increment only once. On the | |
799 | other hand, a post-increment matches ordinary indexing if the | |
800 | post-increment is the output operand. */ | |
801 | if (code == POST_DEC || code == POST_INC || code == POST_MODIFY) | |
802 | return operands_match_p (XEXP (x, 0), y, y_hard_regno); | |
803 | ||
804 | /* Two pre-increments are invalid because the assembler insn would | |
805 | increment only once. On the other hand, a pre-increment matches | |
806 | ordinary indexing if the pre-increment is the input operand. */ | |
807 | if (GET_CODE (y) == PRE_DEC || GET_CODE (y) == PRE_INC | |
808 | || GET_CODE (y) == PRE_MODIFY) | |
809 | return operands_match_p (x, XEXP (y, 0), -1); | |
f4eafc30 | 810 | |
55a2c322 VM |
811 | slow: |
812 | ||
9fccb335 RS |
813 | if (code == REG && REG_P (y)) |
814 | return REGNO (x) == REGNO (y); | |
815 | ||
55a2c322 VM |
816 | if (code == REG && GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y)) |
817 | && x == SUBREG_REG (y)) | |
818 | return true; | |
819 | if (GET_CODE (y) == REG && code == SUBREG && REG_P (SUBREG_REG (x)) | |
820 | && SUBREG_REG (x) == y) | |
821 | return true; | |
822 | ||
823 | /* Now we have disposed of all the cases in which different rtx | |
824 | codes can match. */ | |
825 | if (code != GET_CODE (y)) | |
826 | return false; | |
827 | ||
828 | /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */ | |
829 | if (GET_MODE (x) != GET_MODE (y)) | |
830 | return false; | |
831 | ||
832 | switch (code) | |
833 | { | |
834 | CASE_CONST_UNIQUE: | |
835 | return false; | |
836 | ||
a87d3f96 RS |
837 | case CONST_VECTOR: |
838 | if (!same_vector_encodings_p (x, y)) | |
839 | return false; | |
840 | break; | |
841 | ||
55a2c322 | 842 | case LABEL_REF: |
04a121a7 | 843 | return label_ref_label (x) == label_ref_label (y); |
55a2c322 VM |
844 | case SYMBOL_REF: |
845 | return XSTR (x, 0) == XSTR (y, 0); | |
846 | ||
847 | default: | |
848 | break; | |
849 | } | |
850 | ||
851 | /* Compare the elements. If any pair of corresponding elements fail | |
852 | to match, return false for the whole things. */ | |
853 | ||
854 | fmt = GET_RTX_FORMAT (code); | |
855 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
856 | { | |
857 | int val, j; | |
858 | switch (fmt[i]) | |
859 | { | |
860 | case 'w': | |
861 | if (XWINT (x, i) != XWINT (y, i)) | |
862 | return false; | |
863 | break; | |
864 | ||
865 | case 'i': | |
866 | if (XINT (x, i) != XINT (y, i)) | |
867 | return false; | |
868 | break; | |
869 | ||
91914e56 RS |
870 | case 'p': |
871 | if (maybe_ne (SUBREG_BYTE (x), SUBREG_BYTE (y))) | |
872 | return false; | |
873 | break; | |
874 | ||
55a2c322 VM |
875 | case 'e': |
876 | val = operands_match_p (XEXP (x, i), XEXP (y, i), -1); | |
877 | if (val == 0) | |
878 | return false; | |
879 | break; | |
880 | ||
881 | case '0': | |
882 | break; | |
883 | ||
884 | case 'E': | |
885 | if (XVECLEN (x, i) != XVECLEN (y, i)) | |
886 | return false; | |
887 | for (j = XVECLEN (x, i) - 1; j >= 0; --j) | |
888 | { | |
889 | val = operands_match_p (XVECEXP (x, i, j), XVECEXP (y, i, j), -1); | |
890 | if (val == 0) | |
891 | return false; | |
892 | } | |
893 | break; | |
894 | ||
895 | /* It is believed that rtx's at this level will never | |
896 | contain anything but integers and other rtx's, except for | |
897 | within LABEL_REFs and SYMBOL_REFs. */ | |
898 | default: | |
899 | gcc_unreachable (); | |
900 | } | |
901 | } | |
902 | return true; | |
903 | } | |
904 | ||
905 | /* True if X is a constant that can be forced into the constant pool. | |
906 | MODE is the mode of the operand, or VOIDmode if not known. */ | |
907 | #define CONST_POOL_OK_P(MODE, X) \ | |
908 | ((MODE) != VOIDmode \ | |
909 | && CONSTANT_P (X) \ | |
910 | && GET_CODE (X) != HIGH \ | |
cf098191 | 911 | && GET_MODE_SIZE (MODE).is_constant () \ |
55a2c322 VM |
912 | && !targetm.cannot_force_const_mem (MODE, X)) |
913 | ||
914 | /* True if C is a non-empty register class that has too few registers | |
915 | to be safely used as a reload target class. */ | |
a9711f36 VM |
916 | #define SMALL_REGISTER_CLASS_P(C) \ |
917 | (ira_class_hard_regs_num [(C)] == 1 \ | |
918 | || (ira_class_hard_regs_num [(C)] >= 1 \ | |
919 | && targetm.class_likely_spilled_p (C))) | |
55a2c322 VM |
920 | |
921 | /* If REG is a reload pseudo, try to make its class satisfying CL. */ | |
922 | static void | |
923 | narrow_reload_pseudo_class (rtx reg, enum reg_class cl) | |
924 | { | |
925 | enum reg_class rclass; | |
926 | ||
927 | /* Do not make more accurate class from reloads generated. They are | |
928 | mostly moves with a lot of constraints. Making more accurate | |
929 | class may results in very narrow class and impossibility of find | |
930 | registers for several reloads of one insn. */ | |
931 | if (INSN_UID (curr_insn) >= new_insn_uid_start) | |
932 | return; | |
933 | if (GET_CODE (reg) == SUBREG) | |
934 | reg = SUBREG_REG (reg); | |
935 | if (! REG_P (reg) || (int) REGNO (reg) < new_regno_start) | |
936 | return; | |
937 | if (in_class_p (reg, cl, &rclass) && rclass != cl) | |
a2d0d374 | 938 | lra_change_class (REGNO (reg), rclass, " Change to", true); |
55a2c322 VM |
939 | } |
940 | ||
4be9717c VM |
941 | /* Searches X for any reference to a reg with the same value as REGNO, |
942 | returning the rtx of the reference found if any. Otherwise, | |
943 | returns NULL_RTX. */ | |
944 | static rtx | |
945 | regno_val_use_in (unsigned int regno, rtx x) | |
946 | { | |
947 | const char *fmt; | |
948 | int i, j; | |
949 | rtx tem; | |
950 | ||
951 | if (REG_P (x) && lra_reg_info[REGNO (x)].val == lra_reg_info[regno].val) | |
952 | return x; | |
953 | ||
954 | fmt = GET_RTX_FORMAT (GET_CODE (x)); | |
955 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) | |
956 | { | |
957 | if (fmt[i] == 'e') | |
958 | { | |
959 | if ((tem = regno_val_use_in (regno, XEXP (x, i)))) | |
960 | return tem; | |
961 | } | |
962 | else if (fmt[i] == 'E') | |
963 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
964 | if ((tem = regno_val_use_in (regno , XVECEXP (x, i, j)))) | |
965 | return tem; | |
966 | } | |
967 | ||
968 | return NULL_RTX; | |
969 | } | |
970 | ||
d8321b33 VM |
971 | /* Return true if all current insn non-output operands except INS (it |
972 | has a negaitve end marker) do not use pseudos with the same value | |
973 | as REGNO. */ | |
974 | static bool | |
975 | check_conflict_input_operands (int regno, signed char *ins) | |
976 | { | |
977 | int in; | |
978 | int n_operands = curr_static_id->n_operands; | |
979 | ||
980 | for (int nop = 0; nop < n_operands; nop++) | |
981 | if (! curr_static_id->operand[nop].is_operator | |
982 | && curr_static_id->operand[nop].type != OP_OUT) | |
983 | { | |
984 | for (int i = 0; (in = ins[i]) >= 0; i++) | |
985 | if (in == nop) | |
986 | break; | |
987 | if (in < 0 | |
988 | && regno_val_use_in (regno, *curr_id->operand_loc[nop]) != NULL_RTX) | |
989 | return false; | |
990 | } | |
991 | return true; | |
992 | } | |
993 | ||
55a2c322 | 994 | /* Generate reloads for matching OUT and INS (array of input operand |
aefae0f1 TP |
995 | numbers with end marker -1) with reg class GOAL_CLASS, considering |
996 | output operands OUTS (similar array to INS) needing to be in different | |
997 | registers. Add input and output reloads correspondingly to the lists | |
998 | *BEFORE and *AFTER. OUT might be negative. In this case we generate | |
999 | input reloads for matched input operands INS. EARLY_CLOBBER_P is a flag | |
1000 | that the output operand is early clobbered for chosen alternative. */ | |
55a2c322 | 1001 | static void |
aefae0f1 TP |
1002 | match_reload (signed char out, signed char *ins, signed char *outs, |
1003 | enum reg_class goal_class, rtx_insn **before, | |
1004 | rtx_insn **after, bool early_clobber_p) | |
55a2c322 | 1005 | { |
aefae0f1 | 1006 | bool out_conflict; |
55a2c322 | 1007 | int i, in; |
e67d1102 | 1008 | rtx new_in_reg, new_out_reg, reg; |
ef4bddc2 | 1009 | machine_mode inmode, outmode; |
55a2c322 | 1010 | rtx in_rtx = *curr_id->operand_loc[ins[0]]; |
511dcace | 1011 | rtx out_rtx = out < 0 ? in_rtx : *curr_id->operand_loc[out]; |
55a2c322 | 1012 | |
55a2c322 | 1013 | inmode = curr_operand_mode[ins[0]]; |
511dcace | 1014 | outmode = out < 0 ? inmode : curr_operand_mode[out]; |
55a2c322 VM |
1015 | push_to_sequence (*before); |
1016 | if (inmode != outmode) | |
1017 | { | |
00224b1a RS |
1018 | /* process_alt_operands has already checked that the mode sizes |
1019 | are ordered. */ | |
bd4288c0 | 1020 | if (partial_subreg_p (outmode, inmode)) |
55a2c322 VM |
1021 | { |
1022 | reg = new_in_reg | |
1023 | = lra_create_new_reg_with_unique_value (inmode, in_rtx, | |
1024 | goal_class, ""); | |
98a05c03 | 1025 | new_out_reg = gen_lowpart_SUBREG (outmode, reg); |
2c62cbaa | 1026 | LRA_SUBREG_P (new_out_reg) = 1; |
350c0fe7 | 1027 | /* If the input reg is dying here, we can use the same hard |
f681cf95 VM |
1028 | register for REG and IN_RTX. We do it only for original |
1029 | pseudos as reload pseudos can die although original | |
1030 | pseudos still live where reload pseudos dies. */ | |
1031 | if (REG_P (in_rtx) && (int) REGNO (in_rtx) < lra_new_regno_start | |
d8321b33 VM |
1032 | && find_regno_note (curr_insn, REG_DEAD, REGNO (in_rtx)) |
1033 | && (!early_clobber_p | |
1034 | || check_conflict_input_operands(REGNO (in_rtx), ins))) | |
d70a81dd | 1035 | lra_assign_reg_val (REGNO (in_rtx), REGNO (reg)); |
55a2c322 VM |
1036 | } |
1037 | else | |
1038 | { | |
1039 | reg = new_out_reg | |
1040 | = lra_create_new_reg_with_unique_value (outmode, out_rtx, | |
1041 | goal_class, ""); | |
98a05c03 | 1042 | new_in_reg = gen_lowpart_SUBREG (inmode, reg); |
55a2c322 VM |
1043 | /* NEW_IN_REG is non-paradoxical subreg. We don't want |
1044 | NEW_OUT_REG living above. We add clobber clause for | |
c5cd5a7e VM |
1045 | this. This is just a temporary clobber. We can remove |
1046 | it at the end of LRA work. */ | |
e67d1102 | 1047 | rtx_insn *clobber = emit_clobber (new_out_reg); |
c5cd5a7e | 1048 | LRA_TEMP_CLOBBER_P (PATTERN (clobber)) = 1; |
2c62cbaa | 1049 | LRA_SUBREG_P (new_in_reg) = 1; |
350c0fe7 VM |
1050 | if (GET_CODE (in_rtx) == SUBREG) |
1051 | { | |
1052 | rtx subreg_reg = SUBREG_REG (in_rtx); | |
1053 | ||
1054 | /* If SUBREG_REG is dying here and sub-registers IN_RTX | |
1055 | and NEW_IN_REG are similar, we can use the same hard | |
1056 | register for REG and SUBREG_REG. */ | |
f681cf95 VM |
1057 | if (REG_P (subreg_reg) |
1058 | && (int) REGNO (subreg_reg) < lra_new_regno_start | |
1059 | && GET_MODE (subreg_reg) == outmode | |
91914e56 | 1060 | && known_eq (SUBREG_BYTE (in_rtx), SUBREG_BYTE (new_in_reg)) |
d8321b33 VM |
1061 | && find_regno_note (curr_insn, REG_DEAD, REGNO (subreg_reg)) |
1062 | && (! early_clobber_p | |
1063 | || check_conflict_input_operands (REGNO (subreg_reg), | |
1064 | ins))) | |
d70a81dd | 1065 | lra_assign_reg_val (REGNO (subreg_reg), REGNO (reg)); |
350c0fe7 | 1066 | } |
55a2c322 VM |
1067 | } |
1068 | } | |
1069 | else | |
1070 | { | |
1071 | /* Pseudos have values -- see comments for lra_reg_info. | |
1072 | Different pseudos with the same value do not conflict even if | |
1073 | they live in the same place. When we create a pseudo we | |
1074 | assign value of original pseudo (if any) from which we | |
1075 | created the new pseudo. If we create the pseudo from the | |
3363daad VM |
1076 | input pseudo, the new pseudo will have no conflict with the |
1077 | input pseudo which is wrong when the input pseudo lives after | |
1078 | the insn and as the new pseudo value is changed by the insn | |
1079 | output. Therefore we create the new pseudo from the output | |
1080 | except the case when we have single matched dying input | |
1081 | pseudo. | |
f4eafc30 | 1082 | |
55a2c322 VM |
1083 | We cannot reuse the current output register because we might |
1084 | have a situation like "a <- a op b", where the constraints | |
1085 | force the second input operand ("b") to match the output | |
1086 | operand ("a"). "b" must then be copied into a new register | |
599e1cf8 VM |
1087 | so that it doesn't clobber the current value of "a". |
1088 | ||
67914693 | 1089 | We cannot use the same value if the output pseudo is |
599e1cf8 VM |
1090 | early clobbered or the input pseudo is mentioned in the |
1091 | output, e.g. as an address part in memory, because | |
1092 | output reload will actually extend the pseudo liveness. | |
1093 | We don't care about eliminable hard regs here as we are | |
1094 | interesting only in pseudos. */ | |
f4eafc30 | 1095 | |
aefae0f1 TP |
1096 | /* Matching input's register value is the same as one of the other |
1097 | output operand. Output operands in a parallel insn must be in | |
1098 | different registers. */ | |
1099 | out_conflict = false; | |
1100 | if (REG_P (in_rtx)) | |
1101 | { | |
1102 | for (i = 0; outs[i] >= 0; i++) | |
1103 | { | |
1104 | rtx other_out_rtx = *curr_id->operand_loc[outs[i]]; | |
1105 | if (REG_P (other_out_rtx) | |
1106 | && (regno_val_use_in (REGNO (in_rtx), other_out_rtx) | |
1107 | != NULL_RTX)) | |
1108 | { | |
1109 | out_conflict = true; | |
1110 | break; | |
1111 | } | |
1112 | } | |
1113 | } | |
1114 | ||
55a2c322 | 1115 | new_in_reg = new_out_reg |
599e1cf8 | 1116 | = (! early_clobber_p && ins[1] < 0 && REG_P (in_rtx) |
3363daad VM |
1117 | && (int) REGNO (in_rtx) < lra_new_regno_start |
1118 | && find_regno_note (curr_insn, REG_DEAD, REGNO (in_rtx)) | |
d8321b33 VM |
1119 | && (! early_clobber_p |
1120 | || check_conflict_input_operands (REGNO (in_rtx), ins)) | |
4be9717c VM |
1121 | && (out < 0 |
1122 | || regno_val_use_in (REGNO (in_rtx), out_rtx) == NULL_RTX) | |
aefae0f1 | 1123 | && !out_conflict |
3363daad VM |
1124 | ? lra_create_new_reg (inmode, in_rtx, goal_class, "") |
1125 | : lra_create_new_reg_with_unique_value (outmode, out_rtx, | |
1126 | goal_class, "")); | |
55a2c322 | 1127 | } |
511dcace VM |
1128 | /* In operand can be got from transformations before processing insn |
1129 | constraints. One example of such transformations is subreg | |
1130 | reloading (see function simplify_operand_subreg). The new | |
1131 | pseudos created by the transformations might have inaccurate | |
55a2c322 VM |
1132 | class (ALL_REGS) and we should make their classes more |
1133 | accurate. */ | |
1134 | narrow_reload_pseudo_class (in_rtx, goal_class); | |
55a2c322 VM |
1135 | lra_emit_move (copy_rtx (new_in_reg), in_rtx); |
1136 | *before = get_insns (); | |
1137 | end_sequence (); | |
3f156a6c VM |
1138 | /* Add the new pseudo to consider values of subsequent input reload |
1139 | pseudos. */ | |
1140 | lra_assert (curr_insn_input_reloads_num < LRA_MAX_INSN_RELOADS); | |
1141 | curr_insn_input_reloads[curr_insn_input_reloads_num].input = in_rtx; | |
1142 | curr_insn_input_reloads[curr_insn_input_reloads_num].match_p = true; | |
1143 | curr_insn_input_reloads[curr_insn_input_reloads_num++].reg = new_in_reg; | |
55a2c322 | 1144 | for (i = 0; (in = ins[i]) >= 0; i++) |
60257913 VM |
1145 | if (GET_MODE (*curr_id->operand_loc[in]) == VOIDmode |
1146 | || GET_MODE (new_in_reg) == GET_MODE (*curr_id->operand_loc[in])) | |
55a2c322 | 1147 | *curr_id->operand_loc[in] = new_in_reg; |
60257913 VM |
1148 | else |
1149 | { | |
1150 | lra_assert | |
1151 | (GET_MODE (new_out_reg) == GET_MODE (*curr_id->operand_loc[in])); | |
1152 | *curr_id->operand_loc[in] = new_out_reg; | |
1153 | } | |
55a2c322 | 1154 | lra_update_dups (curr_id, ins); |
511dcace VM |
1155 | if (out < 0) |
1156 | return; | |
1157 | /* See a comment for the input operand above. */ | |
1158 | narrow_reload_pseudo_class (out_rtx, goal_class); | |
55a2c322 VM |
1159 | if (find_reg_note (curr_insn, REG_UNUSED, out_rtx) == NULL_RTX) |
1160 | { | |
bb37ad8c | 1161 | reg = SUBREG_P (out_rtx) ? SUBREG_REG (out_rtx) : out_rtx; |
55a2c322 | 1162 | start_sequence (); |
bb37ad8c VM |
1163 | /* If we had strict_low_part, use it also in reload to keep other |
1164 | parts unchanged but do it only for regs as strict_low_part | |
1165 | has no sense for memory and probably there is no insn pattern | |
1166 | to match the reload insn in memory case. */ | |
1167 | if (out >= 0 && curr_static_id->operand[out].strict_low && REG_P (reg)) | |
5261cf8c | 1168 | out_rtx = gen_rtx_STRICT_LOW_PART (VOIDmode, out_rtx); |
55a2c322 VM |
1169 | lra_emit_move (out_rtx, copy_rtx (new_out_reg)); |
1170 | emit_insn (*after); | |
1171 | *after = get_insns (); | |
1172 | end_sequence (); | |
1173 | } | |
1174 | *curr_id->operand_loc[out] = new_out_reg; | |
1175 | lra_update_dup (curr_id, out); | |
1176 | } | |
1177 | ||
1178 | /* Return register class which is union of all reg classes in insn | |
1179 | constraint alternative string starting with P. */ | |
1180 | static enum reg_class | |
1181 | reg_class_from_constraints (const char *p) | |
1182 | { | |
1183 | int c, len; | |
1184 | enum reg_class op_class = NO_REGS; | |
1185 | ||
1186 | do | |
1187 | switch ((c = *p, len = CONSTRAINT_LEN (c, p)), c) | |
1188 | { | |
1189 | case '#': | |
1190 | case ',': | |
1191 | return op_class; | |
1192 | ||
55a2c322 | 1193 | case 'g': |
55a2c322 VM |
1194 | op_class = reg_class_subunion[op_class][GENERAL_REGS]; |
1195 | break; | |
f4eafc30 | 1196 | |
55a2c322 | 1197 | default: |
777e635f RS |
1198 | enum constraint_num cn = lookup_constraint (p); |
1199 | enum reg_class cl = reg_class_for_constraint (cn); | |
1200 | if (cl == NO_REGS) | |
55a2c322 | 1201 | { |
777e635f | 1202 | if (insn_extra_address_constraint (cn)) |
55a2c322 VM |
1203 | op_class |
1204 | = (reg_class_subunion | |
1205 | [op_class][base_reg_class (VOIDmode, ADDR_SPACE_GENERIC, | |
1206 | ADDRESS, SCRATCH)]); | |
55a2c322 VM |
1207 | break; |
1208 | } | |
f4eafc30 | 1209 | |
777e635f RS |
1210 | op_class = reg_class_subunion[op_class][cl]; |
1211 | break; | |
55a2c322 VM |
1212 | } |
1213 | while ((p += len), c); | |
1214 | return op_class; | |
1215 | } | |
1216 | ||
1217 | /* If OP is a register, return the class of the register as per | |
1218 | get_reg_class, otherwise return NO_REGS. */ | |
1219 | static inline enum reg_class | |
1220 | get_op_class (rtx op) | |
1221 | { | |
1222 | return REG_P (op) ? get_reg_class (REGNO (op)) : NO_REGS; | |
1223 | } | |
1224 | ||
1225 | /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo | |
1226 | otherwise. If modes of MEM_PSEUDO and VAL are different, use | |
1227 | SUBREG for VAL to make them equal. */ | |
cfa434f6 | 1228 | static rtx_insn * |
55a2c322 VM |
1229 | emit_spill_move (bool to_p, rtx mem_pseudo, rtx val) |
1230 | { | |
1231 | if (GET_MODE (mem_pseudo) != GET_MODE (val)) | |
2c62cbaa | 1232 | { |
cb1cca12 VM |
1233 | /* Usually size of mem_pseudo is greater than val size but in |
1234 | rare cases it can be less as it can be defined by target | |
1235 | dependent macro HARD_REGNO_CALLER_SAVE_MODE. */ | |
1ccd4874 VM |
1236 | if (! MEM_P (val)) |
1237 | { | |
54b84aa9 EB |
1238 | val = gen_lowpart_SUBREG (GET_MODE (mem_pseudo), |
1239 | GET_CODE (val) == SUBREG | |
1240 | ? SUBREG_REG (val) : val); | |
1ccd4874 VM |
1241 | LRA_SUBREG_P (val) = 1; |
1242 | } | |
1243 | else | |
1244 | { | |
1245 | mem_pseudo = gen_lowpart_SUBREG (GET_MODE (val), mem_pseudo); | |
1246 | LRA_SUBREG_P (mem_pseudo) = 1; | |
1247 | } | |
2c62cbaa | 1248 | } |
1476d1bd MM |
1249 | return to_p ? gen_move_insn (mem_pseudo, val) |
1250 | : gen_move_insn (val, mem_pseudo); | |
55a2c322 VM |
1251 | } |
1252 | ||
1253 | /* Process a special case insn (register move), return true if we | |
2c62cbaa | 1254 | don't need to process it anymore. INSN should be a single set |
f15643d4 RS |
1255 | insn. Set up that RTL was changed through CHANGE_P and that hook |
1256 | TARGET_SECONDARY_MEMORY_NEEDED says to use secondary memory through | |
2c62cbaa | 1257 | SEC_MEM_P. */ |
55a2c322 | 1258 | static bool |
2c62cbaa | 1259 | check_and_process_move (bool *change_p, bool *sec_mem_p ATTRIBUTE_UNUSED) |
55a2c322 VM |
1260 | { |
1261 | int sregno, dregno; | |
ef0006eb | 1262 | rtx dest, src, dreg, sreg, new_reg, scratch_reg; |
cfa434f6 | 1263 | rtx_insn *before; |
55a2c322 | 1264 | enum reg_class dclass, sclass, secondary_class; |
55a2c322 VM |
1265 | secondary_reload_info sri; |
1266 | ||
2c62cbaa VM |
1267 | lra_assert (curr_insn_set != NULL_RTX); |
1268 | dreg = dest = SET_DEST (curr_insn_set); | |
1269 | sreg = src = SET_SRC (curr_insn_set); | |
55a2c322 VM |
1270 | if (GET_CODE (dest) == SUBREG) |
1271 | dreg = SUBREG_REG (dest); | |
1272 | if (GET_CODE (src) == SUBREG) | |
1273 | sreg = SUBREG_REG (src); | |
1ccd4874 | 1274 | if (! (REG_P (dreg) || MEM_P (dreg)) || ! (REG_P (sreg) || MEM_P (sreg))) |
55a2c322 VM |
1275 | return false; |
1276 | sclass = dclass = NO_REGS; | |
55a2c322 VM |
1277 | if (REG_P (dreg)) |
1278 | dclass = get_reg_class (REGNO (dreg)); | |
48855443 | 1279 | gcc_assert (dclass < LIM_REG_CLASSES); |
55a2c322 VM |
1280 | if (dclass == ALL_REGS) |
1281 | /* ALL_REGS is used for new pseudos created by transformations | |
1282 | like reload of SUBREG_REG (see function | |
1283 | simplify_operand_subreg). We don't know their class yet. We | |
1284 | should figure out the class from processing the insn | |
1285 | constraints not in this fast path function. Even if ALL_REGS | |
1286 | were a right class for the pseudo, secondary_... hooks usually | |
1287 | are not define for ALL_REGS. */ | |
1288 | return false; | |
55a2c322 VM |
1289 | if (REG_P (sreg)) |
1290 | sclass = get_reg_class (REGNO (sreg)); | |
48855443 | 1291 | gcc_assert (sclass < LIM_REG_CLASSES); |
55a2c322 VM |
1292 | if (sclass == ALL_REGS) |
1293 | /* See comments above. */ | |
1294 | return false; | |
1ccd4874 VM |
1295 | if (sclass == NO_REGS && dclass == NO_REGS) |
1296 | return false; | |
f15643d4 | 1297 | if (targetm.secondary_memory_needed (GET_MODE (src), sclass, dclass) |
1ccd4874 | 1298 | && ((sclass != NO_REGS && dclass != NO_REGS) |
94e23f53 RS |
1299 | || (GET_MODE (src) |
1300 | != targetm.secondary_memory_needed_mode (GET_MODE (src))))) | |
55a2c322 VM |
1301 | { |
1302 | *sec_mem_p = true; | |
1303 | return false; | |
1304 | } | |
1ccd4874 VM |
1305 | if (! REG_P (dreg) || ! REG_P (sreg)) |
1306 | return false; | |
55a2c322 VM |
1307 | sri.prev_sri = NULL; |
1308 | sri.icode = CODE_FOR_nothing; | |
1309 | sri.extra_cost = 0; | |
1310 | secondary_class = NO_REGS; | |
1311 | /* Set up hard register for a reload pseudo for hook | |
1312 | secondary_reload because some targets just ignore unassigned | |
1313 | pseudos in the hook. */ | |
1314 | if (dclass != NO_REGS && lra_get_regno_hard_regno (REGNO (dreg)) < 0) | |
1315 | { | |
1316 | dregno = REGNO (dreg); | |
1317 | reg_renumber[dregno] = ira_class_hard_regs[dclass][0]; | |
1318 | } | |
1319 | else | |
1320 | dregno = -1; | |
1321 | if (sclass != NO_REGS && lra_get_regno_hard_regno (REGNO (sreg)) < 0) | |
1322 | { | |
1323 | sregno = REGNO (sreg); | |
1324 | reg_renumber[sregno] = ira_class_hard_regs[sclass][0]; | |
1325 | } | |
1326 | else | |
1327 | sregno = -1; | |
1328 | if (sclass != NO_REGS) | |
1329 | secondary_class | |
1330 | = (enum reg_class) targetm.secondary_reload (false, dest, | |
1331 | (reg_class_t) sclass, | |
1332 | GET_MODE (src), &sri); | |
1333 | if (sclass == NO_REGS | |
1334 | || ((secondary_class != NO_REGS || sri.icode != CODE_FOR_nothing) | |
1335 | && dclass != NO_REGS)) | |
1336 | { | |
55a2c322 VM |
1337 | enum reg_class old_sclass = secondary_class; |
1338 | secondary_reload_info old_sri = sri; | |
55a2c322 VM |
1339 | |
1340 | sri.prev_sri = NULL; | |
1341 | sri.icode = CODE_FOR_nothing; | |
1342 | sri.extra_cost = 0; | |
1343 | secondary_class | |
ef0006eb | 1344 | = (enum reg_class) targetm.secondary_reload (true, src, |
55a2c322 | 1345 | (reg_class_t) dclass, |
ef0006eb | 1346 | GET_MODE (src), &sri); |
55a2c322 VM |
1347 | /* Check the target hook consistency. */ |
1348 | lra_assert | |
1349 | ((secondary_class == NO_REGS && sri.icode == CODE_FOR_nothing) | |
1350 | || (old_sclass == NO_REGS && old_sri.icode == CODE_FOR_nothing) | |
1351 | || (secondary_class == old_sclass && sri.icode == old_sri.icode)); | |
1352 | } | |
1353 | if (sregno >= 0) | |
1354 | reg_renumber [sregno] = -1; | |
1355 | if (dregno >= 0) | |
1356 | reg_renumber [dregno] = -1; | |
1357 | if (secondary_class == NO_REGS && sri.icode == CODE_FOR_nothing) | |
1358 | return false; | |
1359 | *change_p = true; | |
1360 | new_reg = NULL_RTX; | |
1361 | if (secondary_class != NO_REGS) | |
ef0006eb | 1362 | new_reg = lra_create_new_reg_with_unique_value (GET_MODE (src), NULL_RTX, |
55a2c322 VM |
1363 | secondary_class, |
1364 | "secondary"); | |
1365 | start_sequence (); | |
55a2c322 | 1366 | if (sri.icode == CODE_FOR_nothing) |
ef0006eb | 1367 | lra_emit_move (new_reg, src); |
55a2c322 VM |
1368 | else |
1369 | { | |
1370 | enum reg_class scratch_class; | |
1371 | ||
1372 | scratch_class = (reg_class_from_constraints | |
1373 | (insn_data[sri.icode].operand[2].constraint)); | |
1374 | scratch_reg = (lra_create_new_reg_with_unique_value | |
1375 | (insn_data[sri.icode].operand[2].mode, NULL_RTX, | |
1376 | scratch_class, "scratch")); | |
1377 | emit_insn (GEN_FCN (sri.icode) (new_reg != NULL_RTX ? new_reg : dest, | |
ef0006eb | 1378 | src, scratch_reg)); |
55a2c322 VM |
1379 | } |
1380 | before = get_insns (); | |
1381 | end_sequence (); | |
cfa434f6 | 1382 | lra_process_new_insns (curr_insn, before, NULL, "Inserting the move"); |
55a2c322 | 1383 | if (new_reg != NULL_RTX) |
ef0006eb | 1384 | SET_SRC (curr_insn_set) = new_reg; |
55a2c322 VM |
1385 | else |
1386 | { | |
1387 | if (lra_dump_file != NULL) | |
1388 | { | |
1389 | fprintf (lra_dump_file, "Deleting move %u\n", INSN_UID (curr_insn)); | |
cfbeaedf | 1390 | dump_insn_slim (lra_dump_file, curr_insn); |
55a2c322 VM |
1391 | } |
1392 | lra_set_insn_deleted (curr_insn); | |
1393 | return true; | |
1394 | } | |
1395 | return false; | |
1396 | } | |
1397 | ||
1398 | /* The following data describe the result of process_alt_operands. | |
1399 | The data are used in curr_insn_transform to generate reloads. */ | |
1400 | ||
1401 | /* The chosen reg classes which should be used for the corresponding | |
1402 | operands. */ | |
1403 | static enum reg_class goal_alt[MAX_RECOG_OPERANDS]; | |
1404 | /* True if the operand should be the same as another operand and that | |
1405 | other operand does not need a reload. */ | |
1406 | static bool goal_alt_match_win[MAX_RECOG_OPERANDS]; | |
1407 | /* True if the operand does not need a reload. */ | |
1408 | static bool goal_alt_win[MAX_RECOG_OPERANDS]; | |
1409 | /* True if the operand can be offsetable memory. */ | |
1410 | static bool goal_alt_offmemok[MAX_RECOG_OPERANDS]; | |
1411 | /* The number of an operand to which given operand can be matched to. */ | |
1412 | static int goal_alt_matches[MAX_RECOG_OPERANDS]; | |
1413 | /* The number of elements in the following array. */ | |
1414 | static int goal_alt_dont_inherit_ops_num; | |
1415 | /* Numbers of operands whose reload pseudos should not be inherited. */ | |
1416 | static int goal_alt_dont_inherit_ops[MAX_RECOG_OPERANDS]; | |
1417 | /* True if the insn commutative operands should be swapped. */ | |
1418 | static bool goal_alt_swapped; | |
1419 | /* The chosen insn alternative. */ | |
1420 | static int goal_alt_number; | |
1421 | ||
987b67f1 VM |
1422 | /* True if the corresponding operand is the result of an equivalence |
1423 | substitution. */ | |
1424 | static bool equiv_substition_p[MAX_RECOG_OPERANDS]; | |
1425 | ||
55a2c322 VM |
1426 | /* The following five variables are used to choose the best insn |
1427 | alternative. They reflect final characteristics of the best | |
1428 | alternative. */ | |
1429 | ||
1430 | /* Number of necessary reloads and overall cost reflecting the | |
1431 | previous value and other unpleasantness of the best alternative. */ | |
1432 | static int best_losers, best_overall; | |
55a2c322 VM |
1433 | /* Overall number hard registers used for reloads. For example, on |
1434 | some targets we need 2 general registers to reload DFmode and only | |
1435 | one floating point register. */ | |
1436 | static int best_reload_nregs; | |
1437 | /* Overall number reflecting distances of previous reloading the same | |
1438 | value. The distances are counted from the current BB start. It is | |
1439 | used to improve inheritance chances. */ | |
1440 | static int best_reload_sum; | |
1441 | ||
1442 | /* True if the current insn should have no correspondingly input or | |
1443 | output reloads. */ | |
1444 | static bool no_input_reloads_p, no_output_reloads_p; | |
1445 | ||
1446 | /* True if we swapped the commutative operands in the current | |
1447 | insn. */ | |
1448 | static int curr_swapped; | |
1449 | ||
d9cf932c VM |
1450 | /* if CHECK_ONLY_P is false, arrange for address element *LOC to be a |
1451 | register of class CL. Add any input reloads to list BEFORE. AFTER | |
1452 | is nonnull if *LOC is an automodified value; handle that case by | |
1453 | adding the required output reloads to list AFTER. Return true if | |
1454 | the RTL was changed. | |
1455 | ||
1456 | if CHECK_ONLY_P is true, check that the *LOC is a correct address | |
1457 | register. Return false if the address register is correct. */ | |
55a2c322 | 1458 | static bool |
d9cf932c | 1459 | process_addr_reg (rtx *loc, bool check_only_p, rtx_insn **before, rtx_insn **after, |
cfa434f6 | 1460 | enum reg_class cl) |
55a2c322 VM |
1461 | { |
1462 | int regno; | |
1463 | enum reg_class rclass, new_class; | |
277f65de | 1464 | rtx reg; |
55a2c322 | 1465 | rtx new_reg; |
ef4bddc2 | 1466 | machine_mode mode; |
95921002 | 1467 | bool subreg_p, before_p = false; |
55a2c322 | 1468 | |
95921002 VM |
1469 | subreg_p = GET_CODE (*loc) == SUBREG; |
1470 | if (subreg_p) | |
ada2eb68 JW |
1471 | { |
1472 | reg = SUBREG_REG (*loc); | |
1473 | mode = GET_MODE (reg); | |
1474 | ||
1475 | /* For mode with size bigger than ptr_mode, there unlikely to be "mov" | |
1476 | between two registers with different classes, but there normally will | |
1477 | be "mov" which transfers element of vector register into the general | |
1478 | register, and this normally will be a subreg which should be reloaded | |
1479 | as a whole. This is particularly likely to be triggered when | |
1480 | -fno-split-wide-types specified. */ | |
3c11e1af JW |
1481 | if (!REG_P (reg) |
1482 | || in_class_p (reg, cl, &new_class) | |
cf098191 | 1483 | || known_le (GET_MODE_SIZE (mode), GET_MODE_SIZE (ptr_mode))) |
ada2eb68 JW |
1484 | loc = &SUBREG_REG (*loc); |
1485 | } | |
1486 | ||
277f65de | 1487 | reg = *loc; |
55a2c322 VM |
1488 | mode = GET_MODE (reg); |
1489 | if (! REG_P (reg)) | |
1490 | { | |
d9cf932c VM |
1491 | if (check_only_p) |
1492 | return true; | |
55a2c322 VM |
1493 | /* Always reload memory in an address even if the target supports |
1494 | such addresses. */ | |
1495 | new_reg = lra_create_new_reg_with_unique_value (mode, reg, cl, "address"); | |
1496 | before_p = true; | |
1497 | } | |
1498 | else | |
1499 | { | |
1500 | regno = REGNO (reg); | |
1501 | rclass = get_reg_class (regno); | |
d9cf932c VM |
1502 | if (! check_only_p |
1503 | && (*loc = get_equiv_with_elimination (reg, curr_insn)) != reg) | |
55a2c322 VM |
1504 | { |
1505 | if (lra_dump_file != NULL) | |
1506 | { | |
1507 | fprintf (lra_dump_file, | |
1508 | "Changing pseudo %d in address of insn %u on equiv ", | |
1509 | REGNO (reg), INSN_UID (curr_insn)); | |
cfbeaedf | 1510 | dump_value_slim (lra_dump_file, *loc, 1); |
55a2c322 VM |
1511 | fprintf (lra_dump_file, "\n"); |
1512 | } | |
1513 | *loc = copy_rtx (*loc); | |
1514 | } | |
1515 | if (*loc != reg || ! in_class_p (reg, cl, &new_class)) | |
1516 | { | |
d9cf932c VM |
1517 | if (check_only_p) |
1518 | return true; | |
55a2c322 VM |
1519 | reg = *loc; |
1520 | if (get_reload_reg (after == NULL ? OP_IN : OP_INOUT, | |
95921002 | 1521 | mode, reg, cl, subreg_p, "address", &new_reg)) |
55a2c322 VM |
1522 | before_p = true; |
1523 | } | |
1524 | else if (new_class != NO_REGS && rclass != new_class) | |
1525 | { | |
d9cf932c VM |
1526 | if (check_only_p) |
1527 | return true; | |
a2d0d374 | 1528 | lra_change_class (regno, new_class, " Change to", true); |
55a2c322 VM |
1529 | return false; |
1530 | } | |
1531 | else | |
1532 | return false; | |
1533 | } | |
1534 | if (before_p) | |
1535 | { | |
1536 | push_to_sequence (*before); | |
1537 | lra_emit_move (new_reg, reg); | |
1538 | *before = get_insns (); | |
1539 | end_sequence (); | |
1540 | } | |
1541 | *loc = new_reg; | |
1542 | if (after != NULL) | |
1543 | { | |
1544 | start_sequence (); | |
9a9fe2b4 | 1545 | lra_emit_move (before_p ? copy_rtx (reg) : reg, new_reg); |
55a2c322 VM |
1546 | emit_insn (*after); |
1547 | *after = get_insns (); | |
1548 | end_sequence (); | |
1549 | } | |
1550 | return true; | |
1551 | } | |
1552 | ||
4f0bee4c WM |
1553 | /* Insert move insn in simplify_operand_subreg. BEFORE returns |
1554 | the insn to be inserted before curr insn. AFTER returns the | |
1555 | the insn to be inserted after curr insn. ORIGREG and NEWREG | |
1556 | are the original reg and new reg for reload. */ | |
1557 | static void | |
cfa434f6 DM |
1558 | insert_move_for_subreg (rtx_insn **before, rtx_insn **after, rtx origreg, |
1559 | rtx newreg) | |
4f0bee4c WM |
1560 | { |
1561 | if (before) | |
1562 | { | |
1563 | push_to_sequence (*before); | |
1564 | lra_emit_move (newreg, origreg); | |
1565 | *before = get_insns (); | |
1566 | end_sequence (); | |
1567 | } | |
1568 | if (after) | |
1569 | { | |
1570 | start_sequence (); | |
1571 | lra_emit_move (origreg, newreg); | |
1572 | emit_insn (*after); | |
1573 | *after = get_insns (); | |
1574 | end_sequence (); | |
1575 | } | |
1576 | } | |
1577 | ||
ef4bddc2 | 1578 | static int valid_address_p (machine_mode mode, rtx addr, addr_space_t as); |
ab5d2233 | 1579 | static bool process_address (int, bool, rtx_insn **, rtx_insn **); |
ba38538f | 1580 | |
55a2c322 VM |
1581 | /* Make reloads for subreg in operand NOP with internal subreg mode |
1582 | REG_MODE, add new reloads for further processing. Return true if | |
895ff86f | 1583 | any change was done. */ |
55a2c322 | 1584 | static bool |
ef4bddc2 | 1585 | simplify_operand_subreg (int nop, machine_mode reg_mode) |
55a2c322 | 1586 | { |
497498c8 | 1587 | int hard_regno, inner_hard_regno; |
cfa434f6 | 1588 | rtx_insn *before, *after; |
895ff86f | 1589 | machine_mode mode, innermode; |
55a2c322 VM |
1590 | rtx reg, new_reg; |
1591 | rtx operand = *curr_id->operand_loc[nop]; | |
4f0bee4c WM |
1592 | enum reg_class regclass; |
1593 | enum op_type type; | |
55a2c322 | 1594 | |
cfa434f6 | 1595 | before = after = NULL; |
55a2c322 VM |
1596 | |
1597 | if (GET_CODE (operand) != SUBREG) | |
1598 | return false; | |
f4eafc30 | 1599 | |
55a2c322 VM |
1600 | mode = GET_MODE (operand); |
1601 | reg = SUBREG_REG (operand); | |
895ff86f | 1602 | innermode = GET_MODE (reg); |
4f0bee4c | 1603 | type = curr_static_id->operand[nop].type; |
2e186411 | 1604 | if (MEM_P (reg)) |
ba38538f | 1605 | { |
ab5d2233 EB |
1606 | const bool addr_was_valid |
1607 | = valid_address_p (innermode, XEXP (reg, 0), MEM_ADDR_SPACE (reg)); | |
ba38538f | 1608 | alter_subreg (curr_id->operand_loc[nop], false); |
ab5d2233 | 1609 | rtx subst = *curr_id->operand_loc[nop]; |
ba38538f | 1610 | lra_assert (MEM_P (subst)); |
8eaff6ef VM |
1611 | const bool addr_is_valid = valid_address_p (GET_MODE (subst), |
1612 | XEXP (subst, 0), | |
1613 | MEM_ADDR_SPACE (subst)); | |
ab5d2233 | 1614 | if (!addr_was_valid |
8eaff6ef | 1615 | || addr_is_valid |
2e186411 AM |
1616 | || ((get_constraint_type (lookup_constraint |
1617 | (curr_static_id->operand[nop].constraint)) | |
1618 | != CT_SPECIAL_MEMORY) | |
1619 | /* We still can reload address and if the address is | |
1620 | valid, we can remove subreg without reloading its | |
1621 | inner memory. */ | |
1622 | && valid_address_p (GET_MODE (subst), | |
1623 | regno_reg_rtx | |
1624 | [ira_class_hard_regs | |
1625 | [base_reg_class (GET_MODE (subst), | |
1626 | MEM_ADDR_SPACE (subst), | |
1627 | ADDRESS, SCRATCH)][0]], | |
1628 | MEM_ADDR_SPACE (subst)))) | |
1629 | { | |
ab5d2233 | 1630 | /* If we change the address for a paradoxical subreg of memory, the |
849fccf8 EB |
1631 | new address might violate the necessary alignment or the access |
1632 | might be slow; take this into consideration. We need not worry | |
ab5d2233 | 1633 | about accesses beyond allocated memory for paradoxical memory |
2e186411 AM |
1634 | subregs as we don't substitute such equiv memory (see processing |
1635 | equivalences in function lra_constraints) and because for spilled | |
1636 | pseudos we allocate stack memory enough for the biggest | |
198075e1 MF |
1637 | corresponding paradoxical subreg. |
1638 | ||
1639 | However, do not blindly simplify a (subreg (mem ...)) for | |
1640 | WORD_REGISTER_OPERATIONS targets as this may lead to loading junk | |
1641 | data into a register when the inner is narrower than outer or | |
1642 | missing important data from memory when the inner is wider than | |
1643 | outer. This rule only applies to modes that are no wider than | |
8eaff6ef VM |
1644 | a word. |
1645 | ||
1646 | If valid memory becomes invalid after subreg elimination | |
f8dc3fb2 VM |
1647 | and address might be different we still have to reload |
1648 | memory. | |
8eaff6ef | 1649 | */ |
f8dc3fb2 VM |
1650 | if ((! addr_was_valid |
1651 | || addr_is_valid | |
1652 | || known_eq (GET_MODE_SIZE (mode), GET_MODE_SIZE (innermode))) | |
8eaff6ef VM |
1653 | && !(maybe_ne (GET_MODE_PRECISION (mode), |
1654 | GET_MODE_PRECISION (innermode)) | |
1655 | && known_le (GET_MODE_SIZE (mode), UNITS_PER_WORD) | |
1656 | && known_le (GET_MODE_SIZE (innermode), UNITS_PER_WORD) | |
1657 | && WORD_REGISTER_OPERATIONS) | |
198075e1 | 1658 | && (!(MEM_ALIGN (subst) < GET_MODE_ALIGNMENT (mode) |
e0bd6c9f | 1659 | && targetm.slow_unaligned_access (mode, MEM_ALIGN (subst))) |
198075e1 | 1660 | || (MEM_ALIGN (reg) < GET_MODE_ALIGNMENT (innermode) |
e0bd6c9f RS |
1661 | && targetm.slow_unaligned_access (innermode, |
1662 | MEM_ALIGN (reg))))) | |
2e186411 AM |
1663 | return true; |
1664 | ||
ab5d2233 EB |
1665 | *curr_id->operand_loc[nop] = operand; |
1666 | ||
1667 | /* But if the address was not valid, we cannot reload the MEM without | |
1668 | reloading the address first. */ | |
1669 | if (!addr_was_valid) | |
1670 | process_address (nop, false, &before, &after); | |
1671 | ||
2e186411 AM |
1672 | /* INNERMODE is fast, MODE slow. Reload the mem in INNERMODE. */ |
1673 | enum reg_class rclass | |
1674 | = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS); | |
ab5d2233 | 1675 | if (get_reload_reg (curr_static_id->operand[nop].type, innermode, |
8eaff6ef | 1676 | reg, rclass, TRUE, "slow/invalid mem", &new_reg)) |
2e186411 AM |
1677 | { |
1678 | bool insert_before, insert_after; | |
1679 | bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg)); | |
1680 | ||
1681 | insert_before = (type != OP_OUT | |
bd4288c0 | 1682 | || partial_subreg_p (mode, innermode)); |
2e186411 AM |
1683 | insert_after = type != OP_IN; |
1684 | insert_move_for_subreg (insert_before ? &before : NULL, | |
1685 | insert_after ? &after : NULL, | |
1686 | reg, new_reg); | |
1687 | } | |
2e186411 AM |
1688 | SUBREG_REG (operand) = new_reg; |
1689 | ||
1690 | /* Convert to MODE. */ | |
1691 | reg = operand; | |
ab5d2233 EB |
1692 | rclass |
1693 | = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS); | |
2e186411 | 1694 | if (get_reload_reg (curr_static_id->operand[nop].type, mode, reg, |
8eaff6ef | 1695 | rclass, TRUE, "slow/invalid mem", &new_reg)) |
2e186411 AM |
1696 | { |
1697 | bool insert_before, insert_after; | |
1698 | bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg)); | |
1699 | ||
1700 | insert_before = type != OP_OUT; | |
1701 | insert_after = type != OP_IN; | |
1702 | insert_move_for_subreg (insert_before ? &before : NULL, | |
1703 | insert_after ? &after : NULL, | |
1704 | reg, new_reg); | |
1705 | } | |
1706 | *curr_id->operand_loc[nop] = new_reg; | |
1707 | lra_process_new_insns (curr_insn, before, after, | |
8eaff6ef | 1708 | "Inserting slow/invalid mem reload"); |
2e186411 AM |
1709 | return true; |
1710 | } | |
95831c01 | 1711 | |
ba38538f VM |
1712 | /* If the address was valid and became invalid, prefer to reload |
1713 | the memory. Typical case is when the index scale should | |
1714 | correspond the memory. */ | |
2e186411 | 1715 | *curr_id->operand_loc[nop] = operand; |
77850e96 MF |
1716 | /* Do not return false here as the MEM_P (reg) will be processed |
1717 | later in this function. */ | |
ba38538f VM |
1718 | } |
1719 | else if (REG_P (reg) && REGNO (reg) < FIRST_PSEUDO_REGISTER) | |
55a2c322 VM |
1720 | { |
1721 | alter_subreg (curr_id->operand_loc[nop], false); | |
1722 | return true; | |
1723 | } | |
895ff86f VM |
1724 | else if (CONSTANT_P (reg)) |
1725 | { | |
1726 | /* Try to simplify subreg of constant. It is usually result of | |
1727 | equivalence substitution. */ | |
1728 | if (innermode == VOIDmode | |
1729 | && (innermode = original_subreg_reg_mode[nop]) == VOIDmode) | |
1730 | innermode = curr_static_id->operand[nop].mode; | |
1731 | if ((new_reg = simplify_subreg (mode, reg, innermode, | |
1732 | SUBREG_BYTE (operand))) != NULL_RTX) | |
1733 | { | |
1734 | *curr_id->operand_loc[nop] = new_reg; | |
1735 | return true; | |
1736 | } | |
1737 | } | |
55a2c322 VM |
1738 | /* Put constant into memory when we have mixed modes. It generates |
1739 | a better code in most cases as it does not need a secondary | |
1740 | reload memory. It also prevents LRA looping when LRA is using | |
1741 | secondary reload memory again and again. */ | |
1742 | if (CONSTANT_P (reg) && CONST_POOL_OK_P (reg_mode, reg) | |
1743 | && SCALAR_INT_MODE_P (reg_mode) != SCALAR_INT_MODE_P (mode)) | |
1744 | { | |
1745 | SUBREG_REG (operand) = force_const_mem (reg_mode, reg); | |
1746 | alter_subreg (curr_id->operand_loc[nop], false); | |
1747 | return true; | |
1748 | } | |
1749 | /* Force a reload of the SUBREG_REG if this is a constant or PLUS or | |
1750 | if there may be a problem accessing OPERAND in the outer | |
1751 | mode. */ | |
1752 | if ((REG_P (reg) | |
1753 | && REGNO (reg) >= FIRST_PSEUDO_REGISTER | |
1754 | && (hard_regno = lra_get_regno_hard_regno (REGNO (reg))) >= 0 | |
1755 | /* Don't reload paradoxical subregs because we could be looping | |
1756 | having repeatedly final regno out of hard regs range. */ | |
ad474626 RS |
1757 | && (hard_regno_nregs (hard_regno, innermode) |
1758 | >= hard_regno_nregs (hard_regno, mode)) | |
895ff86f | 1759 | && simplify_subreg_regno (hard_regno, innermode, |
2c62cbaa VM |
1760 | SUBREG_BYTE (operand), mode) < 0 |
1761 | /* Don't reload subreg for matching reload. It is actually | |
1762 | valid subreg in LRA. */ | |
1763 | && ! LRA_SUBREG_P (operand)) | |
55a2c322 VM |
1764 | || CONSTANT_P (reg) || GET_CODE (reg) == PLUS || MEM_P (reg)) |
1765 | { | |
6e23f296 VM |
1766 | enum reg_class rclass; |
1767 | ||
7613fa50 VM |
1768 | if (REG_P (reg)) |
1769 | /* There is a big probability that we will get the same class | |
6e23f296 VM |
1770 | for the new pseudo and we will get the same insn which |
1771 | means infinite looping. So spill the new pseudo. */ | |
1772 | rclass = NO_REGS; | |
1773 | else | |
1774 | /* The class will be defined later in curr_insn_transform. */ | |
1775 | rclass | |
1776 | = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS); | |
55a2c322 | 1777 | |
25bb0bb5 | 1778 | if (get_reload_reg (curr_static_id->operand[nop].type, reg_mode, reg, |
95921002 | 1779 | rclass, TRUE, "subreg reg", &new_reg)) |
55a2c322 | 1780 | { |
4f0bee4c | 1781 | bool insert_before, insert_after; |
2b778c9d | 1782 | bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg)); |
4f0bee4c WM |
1783 | |
1784 | insert_before = (type != OP_OUT | |
9eaf97d6 | 1785 | || read_modify_subreg_p (operand)); |
4f0bee4c WM |
1786 | insert_after = (type != OP_IN); |
1787 | insert_move_for_subreg (insert_before ? &before : NULL, | |
1788 | insert_after ? &after : NULL, | |
1789 | reg, new_reg); | |
55a2c322 VM |
1790 | } |
1791 | SUBREG_REG (operand) = new_reg; | |
1792 | lra_process_new_insns (curr_insn, before, after, | |
1793 | "Inserting subreg reload"); | |
1794 | return true; | |
1795 | } | |
4f0bee4c WM |
1796 | /* Force a reload for a paradoxical subreg. For paradoxical subreg, |
1797 | IRA allocates hardreg to the inner pseudo reg according to its mode | |
1798 | instead of the outermode, so the size of the hardreg may not be enough | |
1799 | to contain the outermode operand, in that case we may need to insert | |
1800 | reload for the reg. For the following two types of paradoxical subreg, | |
1801 | we need to insert reload: | |
1802 | 1. If the op_type is OP_IN, and the hardreg could not be paired with | |
1803 | other hardreg to contain the outermode operand | |
1804 | (checked by in_hard_reg_set_p), we need to insert the reload. | |
1805 | 2. If the op_type is OP_OUT or OP_INOUT. | |
1806 | ||
1807 | Here is a paradoxical subreg example showing how the reload is generated: | |
1808 | ||
1809 | (insn 5 4 7 2 (set (reg:TI 106 [ __comp ]) | |
1810 | (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64} | |
1811 | ||
1812 | In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example | |
1813 | here, if reg107 is assigned to hardreg R15, because R15 is the last | |
1814 | hardreg, compiler cannot find another hardreg to pair with R15 to | |
1815 | contain TImode data. So we insert a TImode reload reg180 for it. | |
1816 | After reload is inserted: | |
1817 | ||
1818 | (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0) | |
1819 | (reg:DI 107 [ __comp ])) -1 | |
1820 | (insn 5 4 7 2 (set (reg:TI 106 [ __comp ]) | |
1821 | (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64} | |
1822 | ||
1823 | Two reload hard registers will be allocated to reg180 to save TImode data | |
8fd96632 RS |
1824 | in LRA_assign. |
1825 | ||
1826 | For LRA pseudos this should normally be handled by the biggest_mode | |
1827 | mechanism. However, it's possible for new uses of an LRA pseudo | |
1828 | to be introduced after we've allocated it, such as when undoing | |
1829 | inheritance, and the allocated register might not then be appropriate | |
1830 | for the new uses. */ | |
4f0bee4c WM |
1831 | else if (REG_P (reg) |
1832 | && REGNO (reg) >= FIRST_PSEUDO_REGISTER | |
497498c8 RS |
1833 | && paradoxical_subreg_p (operand) |
1834 | && (inner_hard_regno = lra_get_regno_hard_regno (REGNO (reg))) >= 0 | |
1835 | && ((hard_regno | |
1836 | = simplify_subreg_regno (inner_hard_regno, innermode, | |
1837 | SUBREG_BYTE (operand), mode)) < 0 | |
1838 | || ((hard_regno_nregs (inner_hard_regno, innermode) | |
1839 | < hard_regno_nregs (hard_regno, mode)) | |
1840 | && (regclass = lra_get_allocno_class (REGNO (reg))) | |
1841 | && (type != OP_IN | |
1842 | || !in_hard_reg_set_p (reg_class_contents[regclass], | |
1843 | mode, hard_regno) | |
1844 | || overlaps_hard_reg_set_p (lra_no_alloc_regs, | |
1845 | mode, hard_regno))))) | |
4f0bee4c WM |
1846 | { |
1847 | /* The class will be defined later in curr_insn_transform. */ | |
1848 | enum reg_class rclass | |
1849 | = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS); | |
1850 | ||
1851 | if (get_reload_reg (curr_static_id->operand[nop].type, mode, reg, | |
95921002 | 1852 | rclass, TRUE, "paradoxical subreg", &new_reg)) |
4f0bee4c WM |
1853 | { |
1854 | rtx subreg; | |
1855 | bool insert_before, insert_after; | |
1856 | ||
1857 | PUT_MODE (new_reg, mode); | |
ea09f50d | 1858 | subreg = gen_lowpart_SUBREG (innermode, new_reg); |
4f0bee4c WM |
1859 | bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg)); |
1860 | ||
1861 | insert_before = (type != OP_OUT); | |
1862 | insert_after = (type != OP_IN); | |
1863 | insert_move_for_subreg (insert_before ? &before : NULL, | |
1864 | insert_after ? &after : NULL, | |
1865 | reg, subreg); | |
1866 | } | |
1867 | SUBREG_REG (operand) = new_reg; | |
1868 | lra_process_new_insns (curr_insn, before, after, | |
1869 | "Inserting paradoxical subreg reload"); | |
1870 | return true; | |
1871 | } | |
55a2c322 VM |
1872 | return false; |
1873 | } | |
1874 | ||
1875 | /* Return TRUE if X refers for a hard register from SET. */ | |
1876 | static bool | |
1877 | uses_hard_regs_p (rtx x, HARD_REG_SET set) | |
1878 | { | |
1879 | int i, j, x_hard_regno; | |
ef4bddc2 | 1880 | machine_mode mode; |
55a2c322 VM |
1881 | const char *fmt; |
1882 | enum rtx_code code; | |
1883 | ||
1884 | if (x == NULL_RTX) | |
1885 | return false; | |
1886 | code = GET_CODE (x); | |
1887 | mode = GET_MODE (x); | |
145d4e1a | 1888 | |
55a2c322 VM |
1889 | if (code == SUBREG) |
1890 | { | |
145d4e1a AV |
1891 | /* For all SUBREGs we want to check whether the full multi-register |
1892 | overlaps the set. For normal SUBREGs this means 'get_hard_regno' of | |
1893 | the inner register, for paradoxical SUBREGs this means the | |
1894 | 'get_hard_regno' of the full SUBREG and for complete SUBREGs either is | |
1895 | fine. Use the wider mode for all cases. */ | |
1896 | rtx subreg = SUBREG_REG (x); | |
bd5a2c67 | 1897 | mode = wider_subreg_mode (x); |
145d4e1a AV |
1898 | if (mode == GET_MODE (subreg)) |
1899 | { | |
1900 | x = subreg; | |
1901 | code = GET_CODE (x); | |
1902 | } | |
55a2c322 | 1903 | } |
f4eafc30 | 1904 | |
145d4e1a | 1905 | if (REG_P (x) || SUBREG_P (x)) |
55a2c322 | 1906 | { |
1686923c | 1907 | x_hard_regno = get_hard_regno (x, true); |
55a2c322 VM |
1908 | return (x_hard_regno >= 0 |
1909 | && overlaps_hard_reg_set_p (set, mode, x_hard_regno)); | |
1910 | } | |
55a2c322 VM |
1911 | fmt = GET_RTX_FORMAT (code); |
1912 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1913 | { | |
1914 | if (fmt[i] == 'e') | |
1915 | { | |
1916 | if (uses_hard_regs_p (XEXP (x, i), set)) | |
1917 | return true; | |
1918 | } | |
1919 | else if (fmt[i] == 'E') | |
1920 | { | |
1921 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
1922 | if (uses_hard_regs_p (XVECEXP (x, i, j), set)) | |
1923 | return true; | |
1924 | } | |
1925 | } | |
1926 | return false; | |
1927 | } | |
1928 | ||
1929 | /* Return true if OP is a spilled pseudo. */ | |
1930 | static inline bool | |
1931 | spilled_pseudo_p (rtx op) | |
1932 | { | |
1933 | return (REG_P (op) | |
1934 | && REGNO (op) >= FIRST_PSEUDO_REGISTER && in_mem_p (REGNO (op))); | |
1935 | } | |
1936 | ||
1937 | /* Return true if X is a general constant. */ | |
1938 | static inline bool | |
1939 | general_constant_p (rtx x) | |
1940 | { | |
1941 | return CONSTANT_P (x) && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (x)); | |
1942 | } | |
1943 | ||
2c62cbaa VM |
1944 | static bool |
1945 | reg_in_class_p (rtx reg, enum reg_class cl) | |
1946 | { | |
1947 | if (cl == NO_REGS) | |
1948 | return get_reg_class (REGNO (reg)) == NO_REGS; | |
1949 | return in_class_p (reg, cl, NULL); | |
1950 | } | |
1951 | ||
3c954213 VM |
1952 | /* Return true if SET of RCLASS contains no hard regs which can be |
1953 | used in MODE. */ | |
1954 | static bool | |
1955 | prohibited_class_reg_set_mode_p (enum reg_class rclass, | |
1956 | HARD_REG_SET &set, | |
b8506a8a | 1957 | machine_mode mode) |
3c954213 VM |
1958 | { |
1959 | HARD_REG_SET temp; | |
1960 | ||
c07ad89a | 1961 | lra_assert (hard_reg_set_subset_p (reg_class_contents[rclass], set)); |
d15e5131 | 1962 | temp = set & ~lra_no_alloc_regs; |
3c954213 VM |
1963 | return (hard_reg_set_subset_p |
1964 | (temp, ira_prohibited_class_mode_regs[rclass][mode])); | |
1965 | } | |
1966 | ||
9b195552 VM |
1967 | |
1968 | /* Used to check validity info about small class input operands. It | |
1969 | should be incremented at start of processing an insn | |
1970 | alternative. */ | |
1971 | static unsigned int curr_small_class_check = 0; | |
1972 | ||
a25f3e8e RS |
1973 | /* Update number of used inputs of class OP_CLASS for operand NOP |
1974 | of alternative NALT. Return true if we have more such class operands | |
1975 | than the number of available regs. */ | |
9b195552 | 1976 | static bool |
a25f3e8e RS |
1977 | update_and_check_small_class_inputs (int nop, int nalt, |
1978 | enum reg_class op_class) | |
9b195552 VM |
1979 | { |
1980 | static unsigned int small_class_check[LIM_REG_CLASSES]; | |
1981 | static int small_class_input_nums[LIM_REG_CLASSES]; | |
1982 | ||
1983 | if (SMALL_REGISTER_CLASS_P (op_class) | |
1984 | /* We are interesting in classes became small because of fixing | |
1985 | some hard regs, e.g. by an user through GCC options. */ | |
1986 | && hard_reg_set_intersect_p (reg_class_contents[op_class], | |
1987 | ira_no_alloc_regs) | |
1988 | && (curr_static_id->operand[nop].type != OP_OUT | |
a25f3e8e | 1989 | || TEST_BIT (curr_static_id->operand[nop].early_clobber_alts, nalt))) |
9b195552 VM |
1990 | { |
1991 | if (small_class_check[op_class] == curr_small_class_check) | |
1992 | small_class_input_nums[op_class]++; | |
1993 | else | |
1994 | { | |
1995 | small_class_check[op_class] = curr_small_class_check; | |
1996 | small_class_input_nums[op_class] = 1; | |
1997 | } | |
1998 | if (small_class_input_nums[op_class] > ira_class_hard_regs_num[op_class]) | |
1999 | return true; | |
2000 | } | |
2001 | return false; | |
2002 | } | |
2003 | ||
55a2c322 VM |
2004 | /* Major function to choose the current insn alternative and what |
2005 | operands should be reloaded and how. If ONLY_ALTERNATIVE is not | |
2006 | negative we should consider only this alternative. Return false if | |
67914693 | 2007 | we cannot choose the alternative or find how to reload the |
55a2c322 VM |
2008 | operands. */ |
2009 | static bool | |
2010 | process_alt_operands (int only_alternative) | |
2011 | { | |
2012 | bool ok_p = false; | |
36ff9dfb | 2013 | int nop, overall, nalt; |
55a2c322 VM |
2014 | int n_alternatives = curr_static_id->n_alternatives; |
2015 | int n_operands = curr_static_id->n_operands; | |
2016 | /* LOSERS counts the operands that don't fit this alternative and | |
2017 | would require loading. */ | |
2018 | int losers; | |
feca7b89 | 2019 | int addr_losers; |
55a2c322 VM |
2020 | /* REJECT is a count of how undesirable this alternative says it is |
2021 | if any reloading is required. If the alternative matches exactly | |
2022 | then REJECT is ignored, but otherwise it gets this much counted | |
2023 | against it in addition to the reloading needed. */ | |
2024 | int reject; | |
feca7b89 VM |
2025 | /* This is defined by '!' or '?' alternative constraint and added to |
2026 | reject. But in some cases it can be ignored. */ | |
2027 | int static_reject; | |
d1457701 | 2028 | int op_reject; |
55a2c322 VM |
2029 | /* The number of elements in the following array. */ |
2030 | int early_clobbered_regs_num; | |
2031 | /* Numbers of operands which are early clobber registers. */ | |
2032 | int early_clobbered_nops[MAX_RECOG_OPERANDS]; | |
2033 | enum reg_class curr_alt[MAX_RECOG_OPERANDS]; | |
2034 | HARD_REG_SET curr_alt_set[MAX_RECOG_OPERANDS]; | |
2035 | bool curr_alt_match_win[MAX_RECOG_OPERANDS]; | |
2036 | bool curr_alt_win[MAX_RECOG_OPERANDS]; | |
2037 | bool curr_alt_offmemok[MAX_RECOG_OPERANDS]; | |
2038 | int curr_alt_matches[MAX_RECOG_OPERANDS]; | |
2039 | /* The number of elements in the following array. */ | |
2040 | int curr_alt_dont_inherit_ops_num; | |
2041 | /* Numbers of operands whose reload pseudos should not be inherited. */ | |
2042 | int curr_alt_dont_inherit_ops[MAX_RECOG_OPERANDS]; | |
2043 | rtx op; | |
2044 | /* The register when the operand is a subreg of register, otherwise the | |
2045 | operand itself. */ | |
2046 | rtx no_subreg_reg_operand[MAX_RECOG_OPERANDS]; | |
2047 | /* The register if the operand is a register or subreg of register, | |
2048 | otherwise NULL. */ | |
2049 | rtx operand_reg[MAX_RECOG_OPERANDS]; | |
2050 | int hard_regno[MAX_RECOG_OPERANDS]; | |
ef4bddc2 | 2051 | machine_mode biggest_mode[MAX_RECOG_OPERANDS]; |
55a2c322 VM |
2052 | int reload_nregs, reload_sum; |
2053 | bool costly_p; | |
2054 | enum reg_class cl; | |
2055 | ||
2056 | /* Calculate some data common for all alternatives to speed up the | |
2057 | function. */ | |
2058 | for (nop = 0; nop < n_operands; nop++) | |
2059 | { | |
7214306b VM |
2060 | rtx reg; |
2061 | ||
55a2c322 VM |
2062 | op = no_subreg_reg_operand[nop] = *curr_id->operand_loc[nop]; |
2063 | /* The real hard regno of the operand after the allocation. */ | |
1686923c | 2064 | hard_regno[nop] = get_hard_regno (op, true); |
f4eafc30 | 2065 | |
7214306b VM |
2066 | operand_reg[nop] = reg = op; |
2067 | biggest_mode[nop] = GET_MODE (op); | |
2068 | if (GET_CODE (op) == SUBREG) | |
55a2c322 | 2069 | { |
bd5a2c67 | 2070 | biggest_mode[nop] = wider_subreg_mode (op); |
7214306b | 2071 | operand_reg[nop] = reg = SUBREG_REG (op); |
55a2c322 | 2072 | } |
7214306b | 2073 | if (! REG_P (reg)) |
55a2c322 | 2074 | operand_reg[nop] = NULL_RTX; |
7214306b VM |
2075 | else if (REGNO (reg) >= FIRST_PSEUDO_REGISTER |
2076 | || ((int) REGNO (reg) | |
2077 | == lra_get_elimination_hard_regno (REGNO (reg)))) | |
2078 | no_subreg_reg_operand[nop] = reg; | |
2079 | else | |
2080 | operand_reg[nop] = no_subreg_reg_operand[nop] | |
2081 | /* Just use natural mode for elimination result. It should | |
2082 | be enough for extra constraints hooks. */ | |
2083 | = regno_reg_rtx[hard_regno[nop]]; | |
55a2c322 VM |
2084 | } |
2085 | ||
2086 | /* The constraints are made of several alternatives. Each operand's | |
2087 | constraint looks like foo,bar,... with commas separating the | |
2088 | alternatives. The first alternatives for all operands go | |
2089 | together, the second alternatives go together, etc. | |
2090 | ||
2091 | First loop over alternatives. */ | |
9840b2fa | 2092 | alternative_mask preferred = curr_id->preferred_alternatives; |
4cc8d9d2 | 2093 | if (only_alternative >= 0) |
9840b2fa | 2094 | preferred &= ALTERNATIVE_BIT (only_alternative); |
4cc8d9d2 | 2095 | |
55a2c322 VM |
2096 | for (nalt = 0; nalt < n_alternatives; nalt++) |
2097 | { | |
2098 | /* Loop over operands for one constraint alternative. */ | |
9840b2fa | 2099 | if (!TEST_BIT (preferred, nalt)) |
55a2c322 VM |
2100 | continue; |
2101 | ||
dbe7895c | 2102 | bool matching_early_clobber[MAX_RECOG_OPERANDS]; |
9b195552 | 2103 | curr_small_class_check++; |
feca7b89 VM |
2104 | overall = losers = addr_losers = 0; |
2105 | static_reject = reject = reload_nregs = reload_sum = 0; | |
55a2c322 | 2106 | for (nop = 0; nop < n_operands; nop++) |
cb1cca12 VM |
2107 | { |
2108 | int inc = (curr_static_id | |
2109 | ->operand_alternative[nalt * n_operands + nop].reject); | |
2110 | if (lra_dump_file != NULL && inc != 0) | |
2111 | fprintf (lra_dump_file, | |
2112 | " Staticly defined alt reject+=%d\n", inc); | |
feca7b89 | 2113 | static_reject += inc; |
dbe7895c | 2114 | matching_early_clobber[nop] = 0; |
cb1cca12 | 2115 | } |
feca7b89 | 2116 | reject += static_reject; |
55a2c322 VM |
2117 | early_clobbered_regs_num = 0; |
2118 | ||
2119 | for (nop = 0; nop < n_operands; nop++) | |
2120 | { | |
2121 | const char *p; | |
2122 | char *end; | |
2123 | int len, c, m, i, opalt_num, this_alternative_matches; | |
2124 | bool win, did_match, offmemok, early_clobber_p; | |
2125 | /* false => this operand can be reloaded somehow for this | |
2126 | alternative. */ | |
2127 | bool badop; | |
2128 | /* true => this operand can be reloaded if the alternative | |
2129 | allows regs. */ | |
2130 | bool winreg; | |
2131 | /* True if a constant forced into memory would be OK for | |
2132 | this operand. */ | |
2133 | bool constmemok; | |
2134 | enum reg_class this_alternative, this_costly_alternative; | |
2135 | HARD_REG_SET this_alternative_set, this_costly_alternative_set; | |
2136 | bool this_alternative_match_win, this_alternative_win; | |
2137 | bool this_alternative_offmemok; | |
80f466c4 | 2138 | bool scratch_p; |
ef4bddc2 | 2139 | machine_mode mode; |
777e635f | 2140 | enum constraint_num cn; |
55a2c322 VM |
2141 | |
2142 | opalt_num = nalt * n_operands + nop; | |
2143 | if (curr_static_id->operand_alternative[opalt_num].anything_ok) | |
2144 | { | |
2145 | /* Fast track for no constraints at all. */ | |
2146 | curr_alt[nop] = NO_REGS; | |
2147 | CLEAR_HARD_REG_SET (curr_alt_set[nop]); | |
2148 | curr_alt_win[nop] = true; | |
2149 | curr_alt_match_win[nop] = false; | |
2150 | curr_alt_offmemok[nop] = false; | |
2151 | curr_alt_matches[nop] = -1; | |
2152 | continue; | |
2153 | } | |
f4eafc30 | 2154 | |
55a2c322 VM |
2155 | op = no_subreg_reg_operand[nop]; |
2156 | mode = curr_operand_mode[nop]; | |
2157 | ||
2158 | win = did_match = winreg = offmemok = constmemok = false; | |
2159 | badop = true; | |
f4eafc30 | 2160 | |
55a2c322 VM |
2161 | early_clobber_p = false; |
2162 | p = curr_static_id->operand_alternative[opalt_num].constraint; | |
f4eafc30 | 2163 | |
55a2c322 VM |
2164 | this_costly_alternative = this_alternative = NO_REGS; |
2165 | /* We update set of possible hard regs besides its class | |
2166 | because reg class might be inaccurate. For example, | |
2167 | union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM | |
2168 | is translated in HI_REGS because classes are merged by | |
2169 | pairs and there is no accurate intermediate class. */ | |
2170 | CLEAR_HARD_REG_SET (this_alternative_set); | |
2171 | CLEAR_HARD_REG_SET (this_costly_alternative_set); | |
2172 | this_alternative_win = false; | |
2173 | this_alternative_match_win = false; | |
2174 | this_alternative_offmemok = false; | |
2175 | this_alternative_matches = -1; | |
f4eafc30 | 2176 | |
55a2c322 VM |
2177 | /* An empty constraint should be excluded by the fast |
2178 | track. */ | |
2179 | lra_assert (*p != 0 && *p != ','); | |
f4eafc30 | 2180 | |
d1457701 | 2181 | op_reject = 0; |
55a2c322 VM |
2182 | /* Scan this alternative's specs for this operand; set WIN |
2183 | if the operand fits any letter in this alternative. | |
2184 | Otherwise, clear BADOP if this operand could fit some | |
2185 | letter after reloads, or set WINREG if this operand could | |
2186 | fit after reloads provided the constraint allows some | |
2187 | registers. */ | |
2188 | costly_p = false; | |
2189 | do | |
2190 | { | |
2191 | switch ((c = *p, len = CONSTRAINT_LEN (c, p)), c) | |
2192 | { | |
2193 | case '\0': | |
2194 | len = 0; | |
2195 | break; | |
2196 | case ',': | |
2197 | c = '\0'; | |
2198 | break; | |
f4eafc30 | 2199 | |
55a2c322 VM |
2200 | case '&': |
2201 | early_clobber_p = true; | |
2202 | break; | |
f4eafc30 | 2203 | |
d1457701 VM |
2204 | case '$': |
2205 | op_reject += LRA_MAX_REJECT; | |
2206 | break; | |
2207 | case '^': | |
2208 | op_reject += LRA_LOSER_COST_FACTOR; | |
2209 | break; | |
2210 | ||
55a2c322 VM |
2211 | case '#': |
2212 | /* Ignore rest of this alternative. */ | |
2213 | c = '\0'; | |
2214 | break; | |
f4eafc30 | 2215 | |
55a2c322 VM |
2216 | case '0': case '1': case '2': case '3': case '4': |
2217 | case '5': case '6': case '7': case '8': case '9': | |
2218 | { | |
2219 | int m_hregno; | |
2220 | bool match_p; | |
f4eafc30 | 2221 | |
55a2c322 VM |
2222 | m = strtoul (p, &end, 10); |
2223 | p = end; | |
2224 | len = 0; | |
2225 | lra_assert (nop > m); | |
f4eafc30 | 2226 | |
00224b1a RS |
2227 | /* Reject matches if we don't know which operand is |
2228 | bigger. This situation would arguably be a bug in | |
2229 | an .md pattern, but could also occur in a user asm. */ | |
2230 | if (!ordered_p (GET_MODE_SIZE (biggest_mode[m]), | |
2231 | GET_MODE_SIZE (biggest_mode[nop]))) | |
2232 | break; | |
2233 | ||
a426543a VM |
2234 | /* Don't match wrong asm insn operands for proper |
2235 | diagnostic later. */ | |
2236 | if (INSN_CODE (curr_insn) < 0 | |
2237 | && (curr_operand_mode[m] == BLKmode | |
2238 | || curr_operand_mode[nop] == BLKmode) | |
2239 | && curr_operand_mode[m] != curr_operand_mode[nop]) | |
2240 | break; | |
2241 | ||
1686923c | 2242 | m_hregno = get_hard_regno (*curr_id->operand_loc[m], false); |
55a2c322 VM |
2243 | /* We are supposed to match a previous operand. |
2244 | If we do, we win if that one did. If we do | |
2245 | not, count both of the operands as losers. | |
2246 | (This is too conservative, since most of the | |
2247 | time only a single reload insn will be needed | |
2248 | to make the two operands win. As a result, | |
2249 | this alternative may be rejected when it is | |
2250 | actually desirable.) */ | |
2251 | match_p = false; | |
2252 | if (operands_match_p (*curr_id->operand_loc[nop], | |
2253 | *curr_id->operand_loc[m], m_hregno)) | |
2254 | { | |
2255 | /* We should reject matching of an early | |
2256 | clobber operand if the matching operand is | |
2257 | not dying in the insn. */ | |
a25f3e8e RS |
2258 | if (!TEST_BIT (curr_static_id->operand[m] |
2259 | .early_clobber_alts, nalt) | |
55a2c322 VM |
2260 | || operand_reg[nop] == NULL_RTX |
2261 | || (find_regno_note (curr_insn, REG_DEAD, | |
1c86bd80 VM |
2262 | REGNO (op)) |
2263 | || REGNO (op) == REGNO (operand_reg[m]))) | |
55a2c322 VM |
2264 | match_p = true; |
2265 | } | |
2266 | if (match_p) | |
2267 | { | |
2268 | /* If we are matching a non-offsettable | |
2269 | address where an offsettable address was | |
2270 | expected, then we must reject this | |
2271 | combination, because we can't reload | |
2272 | it. */ | |
2273 | if (curr_alt_offmemok[m] | |
2274 | && MEM_P (*curr_id->operand_loc[m]) | |
2275 | && curr_alt[m] == NO_REGS && ! curr_alt_win[m]) | |
2276 | continue; | |
55a2c322 VM |
2277 | } |
2278 | else | |
2279 | { | |
9f41de41 VM |
2280 | /* If the operands do not match and one |
2281 | operand is INOUT, we can not match them. | |
2282 | Try other possibilities, e.g. other | |
2283 | alternatives or commutative operand | |
2284 | exchange. */ | |
2285 | if (curr_static_id->operand[nop].type == OP_INOUT | |
2286 | || curr_static_id->operand[m].type == OP_INOUT) | |
2287 | break; | |
2f0b80c7 | 2288 | /* Operands don't match. If the operands are |
613caed2 VM |
2289 | different user defined explicit hard |
2290 | registers, then we cannot make them match | |
2291 | when one is early clobber operand. */ | |
2f0b80c7 PB |
2292 | if ((REG_P (*curr_id->operand_loc[nop]) |
2293 | || SUBREG_P (*curr_id->operand_loc[nop])) | |
2294 | && (REG_P (*curr_id->operand_loc[m]) | |
2295 | || SUBREG_P (*curr_id->operand_loc[m]))) | |
2296 | { | |
2297 | rtx nop_reg = *curr_id->operand_loc[nop]; | |
2298 | if (SUBREG_P (nop_reg)) | |
2299 | nop_reg = SUBREG_REG (nop_reg); | |
2300 | rtx m_reg = *curr_id->operand_loc[m]; | |
2301 | if (SUBREG_P (m_reg)) | |
2302 | m_reg = SUBREG_REG (m_reg); | |
2303 | ||
2304 | if (REG_P (nop_reg) | |
2305 | && HARD_REGISTER_P (nop_reg) | |
2306 | && REG_USERVAR_P (nop_reg) | |
2307 | && REG_P (m_reg) | |
2308 | && HARD_REGISTER_P (m_reg) | |
2309 | && REG_USERVAR_P (m_reg)) | |
613caed2 VM |
2310 | { |
2311 | int i; | |
2312 | ||
2313 | for (i = 0; i < early_clobbered_regs_num; i++) | |
2314 | if (m == early_clobbered_nops[i]) | |
2315 | break; | |
2316 | if (i < early_clobbered_regs_num | |
2317 | || early_clobber_p) | |
2318 | break; | |
2319 | } | |
2f0b80c7 | 2320 | } |
2f0b80c7 PB |
2321 | /* Both operands must allow a reload register, |
2322 | otherwise we cannot make them match. */ | |
55a2c322 VM |
2323 | if (curr_alt[m] == NO_REGS) |
2324 | break; | |
2325 | /* Retroactively mark the operand we had to | |
2326 | match as a loser, if it wasn't already and | |
2327 | it wasn't matched to a register constraint | |
2328 | (e.g it might be matched by memory). */ | |
2329 | if (curr_alt_win[m] | |
2330 | && (operand_reg[m] == NULL_RTX | |
2331 | || hard_regno[m] < 0)) | |
2332 | { | |
2333 | losers++; | |
2334 | reload_nregs | |
2335 | += (ira_reg_class_max_nregs[curr_alt[m]] | |
2336 | [GET_MODE (*curr_id->operand_loc[m])]); | |
2337 | } | |
f4eafc30 | 2338 | |
f4581282 VM |
2339 | /* Prefer matching earlyclobber alternative as |
2340 | it results in less hard regs required for | |
2341 | the insn than a non-matching earlyclobber | |
2342 | alternative. */ | |
a25f3e8e RS |
2343 | if (TEST_BIT (curr_static_id->operand[m] |
2344 | .early_clobber_alts, nalt)) | |
f4581282 VM |
2345 | { |
2346 | if (lra_dump_file != NULL) | |
2347 | fprintf | |
2348 | (lra_dump_file, | |
2349 | " %d Matching earlyclobber alt:" | |
2350 | " reject--\n", | |
2351 | nop); | |
dbe7895c AS |
2352 | if (!matching_early_clobber[m]) |
2353 | { | |
2354 | reject--; | |
2355 | matching_early_clobber[m] = 1; | |
2356 | } | |
f4581282 VM |
2357 | } |
2358 | /* Otherwise we prefer no matching | |
2359 | alternatives because it gives more freedom | |
2360 | in RA. */ | |
2361 | else if (operand_reg[nop] == NULL_RTX | |
2362 | || (find_regno_note (curr_insn, REG_DEAD, | |
2363 | REGNO (operand_reg[nop])) | |
2364 | == NULL_RTX)) | |
cb1cca12 VM |
2365 | { |
2366 | if (lra_dump_file != NULL) | |
2367 | fprintf | |
2368 | (lra_dump_file, | |
2369 | " %d Matching alt: reject+=2\n", | |
2370 | nop); | |
2371 | reject += 2; | |
2372 | } | |
55a2c322 VM |
2373 | } |
2374 | /* If we have to reload this operand and some | |
2375 | previous operand also had to match the same | |
2376 | thing as this operand, we don't know how to do | |
2377 | that. */ | |
2378 | if (!match_p || !curr_alt_win[m]) | |
2379 | { | |
2380 | for (i = 0; i < nop; i++) | |
2381 | if (curr_alt_matches[i] == m) | |
2382 | break; | |
2383 | if (i < nop) | |
2384 | break; | |
2385 | } | |
2386 | else | |
2387 | did_match = true; | |
f4eafc30 | 2388 | |
28ed1460 | 2389 | this_alternative_matches = m; |
55a2c322 VM |
2390 | /* This can be fixed with reloads if the operand |
2391 | we are supposed to match can be fixed with | |
2392 | reloads. */ | |
2393 | badop = false; | |
2394 | this_alternative = curr_alt[m]; | |
6576d245 | 2395 | this_alternative_set = curr_alt_set[m]; |
821b7577 | 2396 | winreg = this_alternative != NO_REGS; |
55a2c322 VM |
2397 | break; |
2398 | } | |
f4eafc30 | 2399 | |
55a2c322 VM |
2400 | case 'g': |
2401 | if (MEM_P (op) | |
2402 | || general_constant_p (op) | |
2403 | || spilled_pseudo_p (op)) | |
2404 | win = true; | |
777e635f | 2405 | cl = GENERAL_REGS; |
55a2c322 | 2406 | goto reg; |
f4eafc30 | 2407 | |
55a2c322 | 2408 | default: |
777e635f RS |
2409 | cn = lookup_constraint (p); |
2410 | switch (get_constraint_type (cn)) | |
55a2c322 | 2411 | { |
777e635f RS |
2412 | case CT_REGISTER: |
2413 | cl = reg_class_for_constraint (cn); | |
2414 | if (cl != NO_REGS) | |
2415 | goto reg; | |
2416 | break; | |
f4eafc30 | 2417 | |
d9c35eee RS |
2418 | case CT_CONST_INT: |
2419 | if (CONST_INT_P (op) | |
2420 | && insn_const_int_ok_for_constraint (INTVAL (op), cn)) | |
2421 | win = true; | |
2422 | break; | |
2423 | ||
777e635f | 2424 | case CT_MEMORY: |
0d37e2d3 | 2425 | case CT_RELAXED_MEMORY: |
2e0aa43f | 2426 | if (MEM_P (op) |
2427 | && satisfies_memory_constraint_p (op, cn)) | |
777e635f RS |
2428 | win = true; |
2429 | else if (spilled_pseudo_p (op)) | |
2430 | win = true; | |
2431 | ||
2432 | /* If we didn't already win, we can reload constants | |
2433 | via force_const_mem or put the pseudo value into | |
2434 | memory, or make other memory by reloading the | |
2435 | address like for 'o'. */ | |
2436 | if (CONST_POOL_OK_P (mode, op) | |
987b67f1 VM |
2437 | || MEM_P (op) || REG_P (op) |
2438 | /* We can restore the equiv insn by a | |
2439 | reload. */ | |
2440 | || equiv_substition_p[nop]) | |
777e635f RS |
2441 | badop = false; |
2442 | constmemok = true; | |
2443 | offmemok = true; | |
2444 | break; | |
2445 | ||
2446 | case CT_ADDRESS: | |
998fd141 AO |
2447 | /* An asm operand with an address constraint |
2448 | that doesn't satisfy address_operand has | |
2449 | is_address cleared, so that we don't try to | |
2450 | make a non-address fit. */ | |
2451 | if (!curr_static_id->operand[nop].is_address) | |
2452 | break; | |
777e635f RS |
2453 | /* If we didn't already win, we can reload the address |
2454 | into a base register. */ | |
2455 | if (satisfies_address_constraint_p (op, cn)) | |
2456 | win = true; | |
2457 | cl = base_reg_class (VOIDmode, ADDR_SPACE_GENERIC, | |
2458 | ADDRESS, SCRATCH); | |
2459 | badop = false; | |
2460 | goto reg; | |
2461 | ||
2462 | case CT_FIXED_FORM: | |
2463 | if (constraint_satisfied_p (op, cn)) | |
55a2c322 | 2464 | win = true; |
55a2c322 | 2465 | break; |
9eb1ca69 VM |
2466 | |
2467 | case CT_SPECIAL_MEMORY: | |
4de7b010 | 2468 | if (satisfies_memory_constraint_p (op, cn)) |
9eb1ca69 VM |
2469 | win = true; |
2470 | else if (spilled_pseudo_p (op)) | |
2471 | win = true; | |
2472 | break; | |
55a2c322 | 2473 | } |
777e635f | 2474 | break; |
f4eafc30 | 2475 | |
777e635f | 2476 | reg: |
a5b821e4 JJ |
2477 | if (mode == BLKmode) |
2478 | break; | |
55a2c322 | 2479 | this_alternative = reg_class_subunion[this_alternative][cl]; |
44942965 | 2480 | this_alternative_set |= reg_class_contents[cl]; |
55a2c322 VM |
2481 | if (costly_p) |
2482 | { | |
2483 | this_costly_alternative | |
2484 | = reg_class_subunion[this_costly_alternative][cl]; | |
44942965 | 2485 | this_costly_alternative_set |= reg_class_contents[cl]; |
55a2c322 | 2486 | } |
55a2c322 VM |
2487 | winreg = true; |
2488 | if (REG_P (op)) | |
2489 | { | |
2490 | if (hard_regno[nop] >= 0 | |
2491 | && in_hard_reg_set_p (this_alternative_set, | |
2492 | mode, hard_regno[nop])) | |
2493 | win = true; | |
2494 | else if (hard_regno[nop] < 0 | |
2495 | && in_class_p (op, this_alternative, NULL)) | |
2496 | win = true; | |
2497 | } | |
2498 | break; | |
2499 | } | |
2500 | if (c != ' ' && c != '\t') | |
2501 | costly_p = c == '*'; | |
2502 | } | |
2503 | while ((p += len), c); | |
f4eafc30 | 2504 | |
80f466c4 | 2505 | scratch_p = (operand_reg[nop] != NULL_RTX |
44fbc9c6 | 2506 | && ira_former_scratch_p (REGNO (operand_reg[nop]))); |
55a2c322 VM |
2507 | /* Record which operands fit this alternative. */ |
2508 | if (win) | |
2509 | { | |
2510 | this_alternative_win = true; | |
2511 | if (operand_reg[nop] != NULL_RTX) | |
2512 | { | |
2513 | if (hard_regno[nop] >= 0) | |
2514 | { | |
2515 | if (in_hard_reg_set_p (this_costly_alternative_set, | |
2516 | mode, hard_regno[nop])) | |
cb1cca12 VM |
2517 | { |
2518 | if (lra_dump_file != NULL) | |
2519 | fprintf (lra_dump_file, | |
2520 | " %d Costly set: reject++\n", | |
2521 | nop); | |
2522 | reject++; | |
2523 | } | |
55a2c322 VM |
2524 | } |
2525 | else | |
2526 | { | |
80f466c4 VM |
2527 | /* Prefer won reg to spilled pseudo under other |
2528 | equal conditions for possibe inheritance. */ | |
2529 | if (! scratch_p) | |
2530 | { | |
2531 | if (lra_dump_file != NULL) | |
2532 | fprintf | |
2533 | (lra_dump_file, | |
2534 | " %d Non pseudo reload: reject++\n", | |
2535 | nop); | |
2536 | reject++; | |
2537 | } | |
55a2c322 VM |
2538 | if (in_class_p (operand_reg[nop], |
2539 | this_costly_alternative, NULL)) | |
cb1cca12 VM |
2540 | { |
2541 | if (lra_dump_file != NULL) | |
2542 | fprintf | |
2543 | (lra_dump_file, | |
2544 | " %d Non pseudo costly reload:" | |
2545 | " reject++\n", | |
2546 | nop); | |
2547 | reject++; | |
2548 | } | |
55a2c322 | 2549 | } |
9c582551 | 2550 | /* We simulate the behavior of old reload here. |
55a2c322 VM |
2551 | Although scratches need hard registers and it |
2552 | might result in spilling other pseudos, no reload | |
2553 | insns are generated for the scratches. So it | |
2554 | might cost something but probably less than old | |
2555 | reload pass believes. */ | |
80f466c4 | 2556 | if (scratch_p) |
cb1cca12 VM |
2557 | { |
2558 | if (lra_dump_file != NULL) | |
2559 | fprintf (lra_dump_file, | |
80f466c4 | 2560 | " %d Scratch win: reject+=2\n", |
cb1cca12 | 2561 | nop); |
80f466c4 | 2562 | reject += 2; |
cb1cca12 | 2563 | } |
55a2c322 VM |
2564 | } |
2565 | } | |
2566 | else if (did_match) | |
2567 | this_alternative_match_win = true; | |
2568 | else | |
2569 | { | |
2570 | int const_to_mem = 0; | |
2571 | bool no_regs_p; | |
2572 | ||
d1457701 | 2573 | reject += op_reject; |
8d49e7ef VM |
2574 | /* Never do output reload of stack pointer. It makes |
2575 | impossible to do elimination when SP is changed in | |
2576 | RTL. */ | |
2577 | if (op == stack_pointer_rtx && ! frame_pointer_needed | |
2578 | && curr_static_id->operand[nop].type != OP_IN) | |
2579 | goto fail; | |
2580 | ||
e86c0101 SB |
2581 | /* If this alternative asks for a specific reg class, see if there |
2582 | is at least one allocatable register in that class. */ | |
55a2c322 VM |
2583 | no_regs_p |
2584 | = (this_alternative == NO_REGS | |
2585 | || (hard_reg_set_subset_p | |
2586 | (reg_class_contents[this_alternative], | |
2587 | lra_no_alloc_regs))); | |
e86c0101 SB |
2588 | |
2589 | /* For asms, verify that the class for this alternative is possible | |
2590 | for the mode that is specified. */ | |
ecee672b | 2591 | if (!no_regs_p && INSN_CODE (curr_insn) < 0) |
e86c0101 SB |
2592 | { |
2593 | int i; | |
2594 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
f939c3e6 | 2595 | if (targetm.hard_regno_mode_ok (i, mode) |
8f21260c VM |
2596 | && in_hard_reg_set_p (reg_class_contents[this_alternative], |
2597 | mode, i)) | |
e86c0101 SB |
2598 | break; |
2599 | if (i == FIRST_PSEUDO_REGISTER) | |
2600 | winreg = false; | |
2601 | } | |
2602 | ||
55a2c322 VM |
2603 | /* If this operand accepts a register, and if the |
2604 | register class has at least one allocatable register, | |
2605 | then this operand can be reloaded. */ | |
2606 | if (winreg && !no_regs_p) | |
2607 | badop = false; | |
f4eafc30 | 2608 | |
55a2c322 | 2609 | if (badop) |
8f21260c VM |
2610 | { |
2611 | if (lra_dump_file != NULL) | |
2612 | fprintf (lra_dump_file, | |
2613 | " alt=%d: Bad operand -- refuse\n", | |
2614 | nalt); | |
2615 | goto fail; | |
2616 | } | |
55a2c322 | 2617 | |
d13835b6 VM |
2618 | if (this_alternative != NO_REGS) |
2619 | { | |
d15e5131 RS |
2620 | HARD_REG_SET available_regs |
2621 | = (reg_class_contents[this_alternative] | |
2622 | & ~((ira_prohibited_class_mode_regs | |
2623 | [this_alternative][mode]) | |
2624 | | lra_no_alloc_regs)); | |
d13835b6 VM |
2625 | if (hard_reg_set_empty_p (available_regs)) |
2626 | { | |
2627 | /* There are no hard regs holding a value of given | |
2628 | mode. */ | |
2629 | if (offmemok) | |
2630 | { | |
2631 | this_alternative = NO_REGS; | |
2632 | if (lra_dump_file != NULL) | |
2633 | fprintf (lra_dump_file, | |
2634 | " %d Using memory because of" | |
2635 | " a bad mode: reject+=2\n", | |
2636 | nop); | |
2637 | reject += 2; | |
2638 | } | |
2639 | else | |
2640 | { | |
2641 | if (lra_dump_file != NULL) | |
2642 | fprintf (lra_dump_file, | |
2643 | " alt=%d: Wrong mode -- refuse\n", | |
2644 | nalt); | |
2645 | goto fail; | |
2646 | } | |
2647 | } | |
2648 | } | |
2649 | ||
2ae577fd VM |
2650 | /* If not assigned pseudo has a class which a subset of |
2651 | required reg class, it is a less costly alternative | |
2652 | as the pseudo still can get a hard reg of necessary | |
2653 | class. */ | |
2654 | if (! no_regs_p && REG_P (op) && hard_regno[nop] < 0 | |
2655 | && (cl = get_reg_class (REGNO (op))) != NO_REGS | |
2656 | && ira_class_subset_p[this_alternative][cl]) | |
2657 | { | |
2658 | if (lra_dump_file != NULL) | |
2659 | fprintf | |
2660 | (lra_dump_file, | |
2661 | " %d Super set class reg: reject-=3\n", nop); | |
2662 | reject -= 3; | |
2663 | } | |
2664 | ||
55a2c322 VM |
2665 | this_alternative_offmemok = offmemok; |
2666 | if (this_costly_alternative != NO_REGS) | |
cb1cca12 VM |
2667 | { |
2668 | if (lra_dump_file != NULL) | |
2669 | fprintf (lra_dump_file, | |
2670 | " %d Costly loser: reject++\n", nop); | |
2671 | reject++; | |
2672 | } | |
55a2c322 VM |
2673 | /* If the operand is dying, has a matching constraint, |
2674 | and satisfies constraints of the matched operand | |
f4581282 | 2675 | which failed to satisfy the own constraints, most probably |
a9711f36 VM |
2676 | the reload for this operand will be gone. */ |
2677 | if (this_alternative_matches >= 0 | |
2678 | && !curr_alt_win[this_alternative_matches] | |
2679 | && REG_P (op) | |
2680 | && find_regno_note (curr_insn, REG_DEAD, REGNO (op)) | |
2681 | && (hard_regno[nop] >= 0 | |
2682 | ? in_hard_reg_set_p (this_alternative_set, | |
2683 | mode, hard_regno[nop]) | |
2684 | : in_class_p (op, this_alternative, NULL))) | |
2685 | { | |
2686 | if (lra_dump_file != NULL) | |
2687 | fprintf | |
2688 | (lra_dump_file, | |
2689 | " %d Dying matched operand reload: reject++\n", | |
2690 | nop); | |
2691 | reject++; | |
2692 | } | |
2693 | else | |
027ece11 | 2694 | { |
5306401f VM |
2695 | /* Strict_low_part requires to reload the register |
2696 | not the sub-register. In this case we should | |
2697 | check that a final reload hard reg can hold the | |
2698 | value mode. */ | |
027ece11 VM |
2699 | if (curr_static_id->operand[nop].strict_low |
2700 | && REG_P (op) | |
2701 | && hard_regno[nop] < 0 | |
2702 | && GET_CODE (*curr_id->operand_loc[nop]) == SUBREG | |
2703 | && ira_class_hard_regs_num[this_alternative] > 0 | |
f939c3e6 RS |
2704 | && (!targetm.hard_regno_mode_ok |
2705 | (ira_class_hard_regs[this_alternative][0], | |
2706 | GET_MODE (*curr_id->operand_loc[nop])))) | |
8f21260c VM |
2707 | { |
2708 | if (lra_dump_file != NULL) | |
2709 | fprintf | |
2710 | (lra_dump_file, | |
2711 | " alt=%d: Strict low subreg reload -- refuse\n", | |
2712 | nalt); | |
2713 | goto fail; | |
2714 | } | |
027ece11 VM |
2715 | losers++; |
2716 | } | |
55a2c322 VM |
2717 | if (operand_reg[nop] != NULL_RTX |
2718 | /* Output operands and matched input operands are | |
2719 | not inherited. The following conditions do not | |
2720 | exactly describe the previous statement but they | |
2721 | are pretty close. */ | |
2722 | && curr_static_id->operand[nop].type != OP_OUT | |
2723 | && (this_alternative_matches < 0 | |
2724 | || curr_static_id->operand[nop].type != OP_IN)) | |
2725 | { | |
2726 | int last_reload = (lra_reg_info[ORIGINAL_REGNO | |
2727 | (operand_reg[nop])] | |
2728 | .last_reload); | |
2729 | ||
6334f3e9 VM |
2730 | /* The value of reload_sum has sense only if we |
2731 | process insns in their order. It happens only on | |
2732 | the first constraints sub-pass when we do most of | |
2733 | reload work. */ | |
2734 | if (lra_constraint_iter == 1 && last_reload > bb_reload_num) | |
55a2c322 VM |
2735 | reload_sum += last_reload - bb_reload_num; |
2736 | } | |
2737 | /* If this is a constant that is reloaded into the | |
2738 | desired class by copying it to memory first, count | |
2739 | that as another reload. This is consistent with | |
2740 | other code and is required to avoid choosing another | |
2741 | alternative when the constant is moved into memory. | |
2742 | Note that the test here is precisely the same as in | |
2743 | the code below that calls force_const_mem. */ | |
2744 | if (CONST_POOL_OK_P (mode, op) | |
2745 | && ((targetm.preferred_reload_class | |
2746 | (op, this_alternative) == NO_REGS) | |
2747 | || no_input_reloads_p)) | |
2748 | { | |
2749 | const_to_mem = 1; | |
2750 | if (! no_regs_p) | |
2751 | losers++; | |
2752 | } | |
f4eafc30 | 2753 | |
55a2c322 VM |
2754 | /* Alternative loses if it requires a type of reload not |
2755 | permitted for this insn. We can always reload | |
2756 | objects with a REG_UNUSED note. */ | |
2757 | if ((curr_static_id->operand[nop].type != OP_IN | |
2758 | && no_output_reloads_p | |
2759 | && ! find_reg_note (curr_insn, REG_UNUSED, op)) | |
2760 | || (curr_static_id->operand[nop].type != OP_OUT | |
8f21260c VM |
2761 | && no_input_reloads_p && ! const_to_mem) |
2762 | || (this_alternative_matches >= 0 | |
9102dadd VM |
2763 | && (no_input_reloads_p |
2764 | || (no_output_reloads_p | |
2765 | && (curr_static_id->operand | |
2766 | [this_alternative_matches].type != OP_IN) | |
2767 | && ! find_reg_note (curr_insn, REG_UNUSED, | |
2768 | no_subreg_reg_operand | |
2769 | [this_alternative_matches]))))) | |
8f21260c VM |
2770 | { |
2771 | if (lra_dump_file != NULL) | |
2772 | fprintf | |
2773 | (lra_dump_file, | |
2774 | " alt=%d: No input/otput reload -- refuse\n", | |
2775 | nalt); | |
2776 | goto fail; | |
2777 | } | |
f4eafc30 | 2778 | |
67914693 | 2779 | /* Alternative loses if it required class pseudo cannot |
f66af4aa | 2780 | hold value of required mode. Such insns can be |
7b6e0c54 | 2781 | described by insn definitions with mode iterators. */ |
f66af4aa VM |
2782 | if (GET_MODE (*curr_id->operand_loc[nop]) != VOIDmode |
2783 | && ! hard_reg_set_empty_p (this_alternative_set) | |
7b6e0c54 VM |
2784 | /* It is common practice for constraints to use a |
2785 | class which does not have actually enough regs to | |
2786 | hold the value (e.g. x86 AREG for mode requiring | |
2787 | more one general reg). Therefore we have 2 | |
155ed511 SL |
2788 | conditions to check that the reload pseudo cannot |
2789 | hold the mode value. */ | |
f939c3e6 RS |
2790 | && (!targetm.hard_regno_mode_ok |
2791 | (ira_class_hard_regs[this_alternative][0], | |
2792 | GET_MODE (*curr_id->operand_loc[nop]))) | |
7b6e0c54 VM |
2793 | /* The above condition is not enough as the first |
2794 | reg in ira_class_hard_regs can be not aligned for | |
2795 | multi-words mode values. */ | |
3c954213 VM |
2796 | && (prohibited_class_reg_set_mode_p |
2797 | (this_alternative, this_alternative_set, | |
2798 | GET_MODE (*curr_id->operand_loc[nop])))) | |
2799 | { | |
2800 | if (lra_dump_file != NULL) | |
2801 | fprintf (lra_dump_file, | |
2802 | " alt=%d: reload pseudo for op %d " | |
0d7bac69 | 2803 | "cannot hold the mode value -- refuse\n", |
3c954213 VM |
2804 | nalt, nop); |
2805 | goto fail; | |
f66af4aa VM |
2806 | } |
2807 | ||
821b7577 VM |
2808 | /* Check strong discouragement of reload of non-constant |
2809 | into class THIS_ALTERNATIVE. */ | |
2810 | if (! CONSTANT_P (op) && ! no_regs_p | |
2811 | && (targetm.preferred_reload_class | |
2812 | (op, this_alternative) == NO_REGS | |
2813 | || (curr_static_id->operand[nop].type == OP_OUT | |
2814 | && (targetm.preferred_output_reload_class | |
2815 | (op, this_alternative) == NO_REGS)))) | |
cb1cca12 | 2816 | { |
a8a728aa VM |
2817 | if (offmemok && REG_P (op)) |
2818 | { | |
2819 | if (lra_dump_file != NULL) | |
2820 | fprintf | |
2821 | (lra_dump_file, | |
2822 | " %d Spill pseudo into memory: reject+=3\n", | |
2823 | nop); | |
2824 | reject += 3; | |
2825 | } | |
2826 | else | |
2827 | { | |
2828 | if (lra_dump_file != NULL) | |
2829 | fprintf | |
2830 | (lra_dump_file, | |
2831 | " %d Non-prefered reload: reject+=%d\n", | |
2832 | nop, LRA_MAX_REJECT); | |
2833 | reject += LRA_MAX_REJECT; | |
2834 | } | |
cb1cca12 | 2835 | } |
f4eafc30 | 2836 | |
ed52a84e VM |
2837 | if (! (MEM_P (op) && offmemok) |
2838 | && ! (const_to_mem && constmemok)) | |
55a2c322 VM |
2839 | { |
2840 | /* We prefer to reload pseudos over reloading other | |
2841 | things, since such reloads may be able to be | |
2842 | eliminated later. So bump REJECT in other cases. | |
2843 | Don't do this in the case where we are forcing a | |
2844 | constant into memory and it will then win since | |
2845 | we don't want to have a different alternative | |
2846 | match then. */ | |
2847 | if (! (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER)) | |
cb1cca12 VM |
2848 | { |
2849 | if (lra_dump_file != NULL) | |
2850 | fprintf | |
2851 | (lra_dump_file, | |
2852 | " %d Non-pseudo reload: reject+=2\n", | |
2853 | nop); | |
2854 | reject += 2; | |
2855 | } | |
f4eafc30 | 2856 | |
55a2c322 VM |
2857 | if (! no_regs_p) |
2858 | reload_nregs | |
2859 | += ira_reg_class_max_nregs[this_alternative][mode]; | |
36ff9dfb VM |
2860 | |
2861 | if (SMALL_REGISTER_CLASS_P (this_alternative)) | |
cb1cca12 VM |
2862 | { |
2863 | if (lra_dump_file != NULL) | |
2864 | fprintf | |
2865 | (lra_dump_file, | |
2866 | " %d Small class reload: reject+=%d\n", | |
2867 | nop, LRA_LOSER_COST_FACTOR / 2); | |
2868 | reject += LRA_LOSER_COST_FACTOR / 2; | |
2869 | } | |
55a2c322 VM |
2870 | } |
2871 | ||
1bdc4b11 VM |
2872 | /* We are trying to spill pseudo into memory. It is |
2873 | usually more costly than moving to a hard register | |
2874 | although it might takes the same number of | |
5f225ef4 VM |
2875 | reloads. |
2876 | ||
2877 | Non-pseudo spill may happen also. Suppose a target allows both | |
2878 | register and memory in the operand constraint alternatives, | |
2879 | then it's typical that an eliminable register has a substition | |
2880 | of "base + offset" which can either be reloaded by a simple | |
2881 | "new_reg <= base + offset" which will match the register | |
2882 | constraint, or a similar reg addition followed by further spill | |
2883 | to and reload from memory which will match the memory | |
2884 | constraint, but this memory spill will be much more costly | |
2885 | usually. | |
2886 | ||
2887 | Code below increases the reject for both pseudo and non-pseudo | |
2888 | spill. */ | |
10406801 JW |
2889 | if (no_regs_p |
2890 | && !(MEM_P (op) && offmemok) | |
2891 | && !(REG_P (op) && hard_regno[nop] < 0)) | |
cb1cca12 VM |
2892 | { |
2893 | if (lra_dump_file != NULL) | |
2894 | fprintf | |
2895 | (lra_dump_file, | |
5f225ef4 VM |
2896 | " %d Spill %spseudo into memory: reject+=3\n", |
2897 | nop, REG_P (op) ? "" : "Non-"); | |
cb1cca12 | 2898 | reject += 3; |
7891065a VM |
2899 | if (VECTOR_MODE_P (mode)) |
2900 | { | |
2901 | /* Spilling vectors into memory is usually more | |
2902 | costly as they contain big values. */ | |
2903 | if (lra_dump_file != NULL) | |
2904 | fprintf | |
2905 | (lra_dump_file, | |
2906 | " %d Spill vector pseudo: reject+=2\n", | |
2907 | nop); | |
2908 | reject += 2; | |
2909 | } | |
cb1cca12 | 2910 | } |
1bdc4b11 | 2911 | |
4796d8f6 VM |
2912 | /* When we use an operand requiring memory in given |
2913 | alternative, the insn should write *and* read the | |
2914 | value to/from memory it is costly in comparison with | |
2915 | an insn alternative which does not use memory | |
2916 | (e.g. register or immediate operand). We exclude | |
2917 | memory operand for such case as we can satisfy the | |
2918 | memory constraints by reloading address. */ | |
2919 | if (no_regs_p && offmemok && !MEM_P (op)) | |
9b195552 VM |
2920 | { |
2921 | if (lra_dump_file != NULL) | |
2922 | fprintf | |
2923 | (lra_dump_file, | |
2924 | " Using memory insn operand %d: reject+=3\n", | |
2925 | nop); | |
2926 | reject += 3; | |
2927 | } | |
2928 | ||
7100b561 UB |
2929 | /* If reload requires moving value through secondary |
2930 | memory, it will need one more insn at least. */ | |
2931 | if (this_alternative != NO_REGS | |
2932 | && REG_P (op) && (cl = get_reg_class (REGNO (op))) != NO_REGS | |
2933 | && ((curr_static_id->operand[nop].type != OP_OUT | |
f15643d4 RS |
2934 | && targetm.secondary_memory_needed (GET_MODE (op), cl, |
2935 | this_alternative)) | |
7100b561 | 2936 | || (curr_static_id->operand[nop].type != OP_IN |
f15643d4 RS |
2937 | && (targetm.secondary_memory_needed |
2938 | (GET_MODE (op), this_alternative, cl))))) | |
7100b561 | 2939 | losers++; |
f15643d4 | 2940 | |
feca7b89 VM |
2941 | if (MEM_P (op) && offmemok) |
2942 | addr_losers++; | |
82396b8c | 2943 | else |
8b8e41e5 | 2944 | { |
82396b8c VM |
2945 | /* Input reloads can be inherited more often than |
2946 | output reloads can be removed, so penalize output | |
2947 | reloads. */ | |
2948 | if (!REG_P (op) || curr_static_id->operand[nop].type != OP_IN) | |
2949 | { | |
2950 | if (lra_dump_file != NULL) | |
2951 | fprintf | |
2952 | (lra_dump_file, | |
2953 | " %d Non input pseudo reload: reject++\n", | |
2954 | nop); | |
2955 | reject++; | |
2956 | } | |
2957 | ||
2958 | if (curr_static_id->operand[nop].type == OP_INOUT) | |
2959 | { | |
2960 | if (lra_dump_file != NULL) | |
2961 | fprintf | |
2962 | (lra_dump_file, | |
2963 | " %d Input/Output reload: reject+=%d\n", | |
2964 | nop, LRA_LOSER_COST_FACTOR); | |
2965 | reject += LRA_LOSER_COST_FACTOR; | |
2966 | } | |
8b8e41e5 | 2967 | } |
55a2c322 | 2968 | } |
f4eafc30 | 2969 | |
80f466c4 | 2970 | if (early_clobber_p && ! scratch_p) |
cb1cca12 VM |
2971 | { |
2972 | if (lra_dump_file != NULL) | |
2973 | fprintf (lra_dump_file, | |
2974 | " %d Early clobber: reject++\n", nop); | |
2975 | reject++; | |
2976 | } | |
55a2c322 VM |
2977 | /* ??? We check early clobbers after processing all operands |
2978 | (see loop below) and there we update the costs more. | |
2979 | Should we update the cost (may be approximately) here | |
2980 | because of early clobber register reloads or it is a rare | |
2981 | or non-important thing to be worth to do it. */ | |
feca7b89 VM |
2982 | overall = (losers * LRA_LOSER_COST_FACTOR + reject |
2983 | - (addr_losers == losers ? static_reject : 0)); | |
55a2c322 | 2984 | if ((best_losers == 0 || losers != 0) && best_overall < overall) |
deca73f5 VM |
2985 | { |
2986 | if (lra_dump_file != NULL) | |
2987 | fprintf (lra_dump_file, | |
cb1cca12 | 2988 | " alt=%d,overall=%d,losers=%d -- refuse\n", |
deca73f5 VM |
2989 | nalt, overall, losers); |
2990 | goto fail; | |
2991 | } | |
55a2c322 | 2992 | |
a25f3e8e RS |
2993 | if (update_and_check_small_class_inputs (nop, nalt, |
2994 | this_alternative)) | |
9b195552 VM |
2995 | { |
2996 | if (lra_dump_file != NULL) | |
2997 | fprintf (lra_dump_file, | |
2998 | " alt=%d, not enough small class regs -- refuse\n", | |
2999 | nalt); | |
3000 | goto fail; | |
3001 | } | |
55a2c322 | 3002 | curr_alt[nop] = this_alternative; |
6576d245 | 3003 | curr_alt_set[nop] = this_alternative_set; |
55a2c322 VM |
3004 | curr_alt_win[nop] = this_alternative_win; |
3005 | curr_alt_match_win[nop] = this_alternative_match_win; | |
3006 | curr_alt_offmemok[nop] = this_alternative_offmemok; | |
3007 | curr_alt_matches[nop] = this_alternative_matches; | |
f4eafc30 | 3008 | |
55a2c322 VM |
3009 | if (this_alternative_matches >= 0 |
3010 | && !did_match && !this_alternative_win) | |
3011 | curr_alt_win[this_alternative_matches] = false; | |
f4eafc30 | 3012 | |
55a2c322 VM |
3013 | if (early_clobber_p && operand_reg[nop] != NULL_RTX) |
3014 | early_clobbered_nops[early_clobbered_regs_num++] = nop; | |
3015 | } | |
feca7b89 | 3016 | |
2c62cbaa VM |
3017 | if (curr_insn_set != NULL_RTX && n_operands == 2 |
3018 | /* Prevent processing non-move insns. */ | |
3019 | && (GET_CODE (SET_SRC (curr_insn_set)) == SUBREG | |
3020 | || SET_SRC (curr_insn_set) == no_subreg_reg_operand[1]) | |
3021 | && ((! curr_alt_win[0] && ! curr_alt_win[1] | |
3022 | && REG_P (no_subreg_reg_operand[0]) | |
3023 | && REG_P (no_subreg_reg_operand[1]) | |
3024 | && (reg_in_class_p (no_subreg_reg_operand[0], curr_alt[1]) | |
3025 | || reg_in_class_p (no_subreg_reg_operand[1], curr_alt[0]))) | |
3026 | || (! curr_alt_win[0] && curr_alt_win[1] | |
3027 | && REG_P (no_subreg_reg_operand[1]) | |
feca7b89 VM |
3028 | /* Check that we reload memory not the memory |
3029 | address. */ | |
9125b9fc VM |
3030 | && ! (curr_alt_offmemok[0] |
3031 | && MEM_P (no_subreg_reg_operand[0])) | |
2c62cbaa VM |
3032 | && reg_in_class_p (no_subreg_reg_operand[1], curr_alt[0])) |
3033 | || (curr_alt_win[0] && ! curr_alt_win[1] | |
3034 | && REG_P (no_subreg_reg_operand[0]) | |
feca7b89 VM |
3035 | /* Check that we reload memory not the memory |
3036 | address. */ | |
9125b9fc VM |
3037 | && ! (curr_alt_offmemok[1] |
3038 | && MEM_P (no_subreg_reg_operand[1])) | |
2c62cbaa VM |
3039 | && reg_in_class_p (no_subreg_reg_operand[0], curr_alt[1]) |
3040 | && (! CONST_POOL_OK_P (curr_operand_mode[1], | |
3041 | no_subreg_reg_operand[1]) | |
3042 | || (targetm.preferred_reload_class | |
3043 | (no_subreg_reg_operand[1], | |
3044 | (enum reg_class) curr_alt[1]) != NO_REGS)) | |
3045 | /* If it is a result of recent elimination in move | |
3046 | insn we can transform it into an add still by | |
3047 | using this alternative. */ | |
b4c96972 RS |
3048 | && GET_CODE (no_subreg_reg_operand[1]) != PLUS |
3049 | /* Likewise if the source has been replaced with an | |
3050 | equivalent value. This only happens once -- the reload | |
3051 | will use the equivalent value instead of the register it | |
3052 | replaces -- so there should be no danger of cycling. */ | |
3053 | && !equiv_substition_p[1]))) | |
cb1cca12 VM |
3054 | { |
3055 | /* We have a move insn and a new reload insn will be similar | |
9125b9fc VM |
3056 | to the current insn. We should avoid such situation as |
3057 | it results in LRA cycling. */ | |
3058 | if (lra_dump_file != NULL) | |
3059 | fprintf (lra_dump_file, | |
3060 | " Cycle danger: overall += LRA_MAX_REJECT\n"); | |
cb1cca12 VM |
3061 | overall += LRA_MAX_REJECT; |
3062 | } | |
55a2c322 VM |
3063 | ok_p = true; |
3064 | curr_alt_dont_inherit_ops_num = 0; | |
3065 | for (nop = 0; nop < early_clobbered_regs_num; nop++) | |
3066 | { | |
2194f7a2 | 3067 | int i, j, clobbered_hard_regno, first_conflict_j, last_conflict_j; |
55a2c322 VM |
3068 | HARD_REG_SET temp_set; |
3069 | ||
3070 | i = early_clobbered_nops[nop]; | |
3071 | if ((! curr_alt_win[i] && ! curr_alt_match_win[i]) | |
3072 | || hard_regno[i] < 0) | |
3073 | continue; | |
1c86bd80 | 3074 | lra_assert (operand_reg[i] != NULL_RTX); |
55a2c322 VM |
3075 | clobbered_hard_regno = hard_regno[i]; |
3076 | CLEAR_HARD_REG_SET (temp_set); | |
3077 | add_to_hard_reg_set (&temp_set, biggest_mode[i], clobbered_hard_regno); | |
2194f7a2 | 3078 | first_conflict_j = last_conflict_j = -1; |
55a2c322 VM |
3079 | for (j = 0; j < n_operands; j++) |
3080 | if (j == i | |
3081 | /* We don't want process insides of match_operator and | |
3082 | match_parallel because otherwise we would process | |
3083 | their operands once again generating a wrong | |
3084 | code. */ | |
3085 | || curr_static_id->operand[j].is_operator) | |
3086 | continue; | |
3087 | else if ((curr_alt_matches[j] == i && curr_alt_match_win[j]) | |
3088 | || (curr_alt_matches[i] == j && curr_alt_match_win[i])) | |
3089 | continue; | |
1c86bd80 VM |
3090 | /* If we don't reload j-th operand, check conflicts. */ |
3091 | else if ((curr_alt_win[j] || curr_alt_match_win[j]) | |
3092 | && uses_hard_regs_p (*curr_id->operand_loc[j], temp_set)) | |
2194f7a2 VM |
3093 | { |
3094 | if (first_conflict_j < 0) | |
3095 | first_conflict_j = j; | |
3096 | last_conflict_j = j; | |
2f0b80c7 PB |
3097 | /* Both the earlyclobber operand and conflicting operand |
3098 | cannot both be user defined hard registers. */ | |
3099 | if (HARD_REGISTER_P (operand_reg[i]) | |
3100 | && REG_USERVAR_P (operand_reg[i]) | |
3101 | && operand_reg[j] != NULL_RTX | |
3102 | && HARD_REGISTER_P (operand_reg[j]) | |
3103 | && REG_USERVAR_P (operand_reg[j])) | |
eb69a49c JJ |
3104 | { |
3105 | /* For asm, let curr_insn_transform diagnose it. */ | |
3106 | if (INSN_CODE (curr_insn) < 0) | |
3107 | return false; | |
3108 | fatal_insn ("unable to generate reloads for " | |
3109 | "impossible constraints:", curr_insn); | |
3110 | } | |
2194f7a2 VM |
3111 | } |
3112 | if (last_conflict_j < 0) | |
55a2c322 | 3113 | continue; |
2f0b80c7 PB |
3114 | |
3115 | /* If an earlyclobber operand conflicts with another non-matching | |
3116 | operand (ie, they have been assigned the same hard register), | |
3117 | then it is better to reload the other operand, as there may | |
3118 | exist yet another operand with a matching constraint associated | |
3119 | with the earlyclobber operand. However, if one of the operands | |
3120 | is an explicit use of a hard register, then we must reload the | |
3121 | other non-hard register operand. */ | |
3122 | if (HARD_REGISTER_P (operand_reg[i]) | |
3123 | || (first_conflict_j == last_conflict_j | |
3124 | && operand_reg[last_conflict_j] != NULL_RTX | |
3125 | && !curr_alt_match_win[last_conflict_j] | |
3126 | && !HARD_REGISTER_P (operand_reg[last_conflict_j]))) | |
1c86bd80 | 3127 | { |
2194f7a2 VM |
3128 | curr_alt_win[last_conflict_j] = false; |
3129 | curr_alt_dont_inherit_ops[curr_alt_dont_inherit_ops_num++] | |
3130 | = last_conflict_j; | |
1c86bd80 | 3131 | losers++; |
cb1cca12 VM |
3132 | if (lra_dump_file != NULL) |
3133 | fprintf | |
3134 | (lra_dump_file, | |
3135 | " %d Conflict early clobber reload: reject--\n", | |
3136 | i); | |
1c86bd80 | 3137 | } |
55a2c322 VM |
3138 | else |
3139 | { | |
1c86bd80 VM |
3140 | /* We need to reload early clobbered register and the |
3141 | matched registers. */ | |
3142 | for (j = 0; j < n_operands; j++) | |
3143 | if (curr_alt_matches[j] == i) | |
3144 | { | |
3145 | curr_alt_match_win[j] = false; | |
3146 | losers++; | |
3147 | overall += LRA_LOSER_COST_FACTOR; | |
3148 | } | |
3149 | if (! curr_alt_match_win[i]) | |
3150 | curr_alt_dont_inherit_ops[curr_alt_dont_inherit_ops_num++] = i; | |
3151 | else | |
3152 | { | |
3153 | /* Remember pseudos used for match reloads are never | |
3154 | inherited. */ | |
3155 | lra_assert (curr_alt_matches[i] >= 0); | |
3156 | curr_alt_win[curr_alt_matches[i]] = false; | |
3157 | } | |
3158 | curr_alt_win[i] = curr_alt_match_win[i] = false; | |
3159 | losers++; | |
cb1cca12 VM |
3160 | if (lra_dump_file != NULL) |
3161 | fprintf | |
3162 | (lra_dump_file, | |
aa326bfb | 3163 | " %d Matched conflict early clobber reloads: " |
cb1cca12 VM |
3164 | "reject--\n", |
3165 | i); | |
dbe7895c AS |
3166 | } |
3167 | /* Early clobber was already reflected in REJECT. */ | |
3168 | if (!matching_early_clobber[i]) | |
3169 | { | |
3170 | lra_assert (reject > 0); | |
deca73f5 | 3171 | reject--; |
dbe7895c | 3172 | matching_early_clobber[i] = 1; |
55a2c322 | 3173 | } |
dbe7895c | 3174 | overall += LRA_LOSER_COST_FACTOR - 1; |
55a2c322 | 3175 | } |
deca73f5 | 3176 | if (lra_dump_file != NULL) |
36ff9dfb VM |
3177 | fprintf (lra_dump_file, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n", |
3178 | nalt, overall, losers, reload_nregs); | |
deca73f5 | 3179 | |
55a2c322 VM |
3180 | /* If this alternative can be made to work by reloading, and it |
3181 | needs less reloading than the others checked so far, record | |
3182 | it as the chosen goal for reloading. */ | |
3183 | if ((best_losers != 0 && losers == 0) | |
3184 | || (((best_losers == 0 && losers == 0) | |
3185 | || (best_losers != 0 && losers != 0)) | |
3186 | && (best_overall > overall | |
3187 | || (best_overall == overall | |
3188 | /* If the cost of the reloads is the same, | |
3189 | prefer alternative which requires minimal | |
36ff9dfb VM |
3190 | number of reload regs. */ |
3191 | && (reload_nregs < best_reload_nregs | |
3192 | || (reload_nregs == best_reload_nregs | |
f15feaf9 VM |
3193 | && (best_reload_sum < reload_sum |
3194 | || (best_reload_sum == reload_sum | |
3195 | && nalt < goal_alt_number)))))))) | |
55a2c322 VM |
3196 | { |
3197 | for (nop = 0; nop < n_operands; nop++) | |
3198 | { | |
3199 | goal_alt_win[nop] = curr_alt_win[nop]; | |
3200 | goal_alt_match_win[nop] = curr_alt_match_win[nop]; | |
3201 | goal_alt_matches[nop] = curr_alt_matches[nop]; | |
3202 | goal_alt[nop] = curr_alt[nop]; | |
3203 | goal_alt_offmemok[nop] = curr_alt_offmemok[nop]; | |
3204 | } | |
3205 | goal_alt_dont_inherit_ops_num = curr_alt_dont_inherit_ops_num; | |
3206 | for (nop = 0; nop < curr_alt_dont_inherit_ops_num; nop++) | |
3207 | goal_alt_dont_inherit_ops[nop] = curr_alt_dont_inherit_ops[nop]; | |
3208 | goal_alt_swapped = curr_swapped; | |
3209 | best_overall = overall; | |
3210 | best_losers = losers; | |
55a2c322 VM |
3211 | best_reload_nregs = reload_nregs; |
3212 | best_reload_sum = reload_sum; | |
3213 | goal_alt_number = nalt; | |
3214 | } | |
3215 | if (losers == 0) | |
3216 | /* Everything is satisfied. Do not process alternatives | |
f4eafc30 | 3217 | anymore. */ |
55a2c322 VM |
3218 | break; |
3219 | fail: | |
3220 | ; | |
3221 | } | |
3222 | return ok_p; | |
3223 | } | |
3224 | ||
c31d2d11 RS |
3225 | /* Make reload base reg from address AD. */ |
3226 | static rtx | |
3227 | base_to_reg (struct address_info *ad) | |
3228 | { | |
3229 | enum reg_class cl; | |
3230 | int code = -1; | |
3231 | rtx new_inner = NULL_RTX; | |
3232 | rtx new_reg = NULL_RTX; | |
fee3e72c DM |
3233 | rtx_insn *insn; |
3234 | rtx_insn *last_insn = get_last_insn(); | |
c31d2d11 | 3235 | |
0a001dcb | 3236 | lra_assert (ad->disp == ad->disp_term); |
c31d2d11 RS |
3237 | cl = base_reg_class (ad->mode, ad->as, ad->base_outer_code, |
3238 | get_index_code (ad)); | |
0a001dcb | 3239 | new_reg = lra_create_new_reg (GET_MODE (*ad->base), NULL_RTX, |
c31d2d11 RS |
3240 | cl, "base"); |
3241 | new_inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), new_reg, | |
3242 | ad->disp_term == NULL | |
0a001dcb | 3243 | ? const0_rtx |
c31d2d11 RS |
3244 | : *ad->disp_term); |
3245 | if (!valid_address_p (ad->mode, new_inner, ad->as)) | |
3246 | return NULL_RTX; | |
0a001dcb | 3247 | insn = emit_insn (gen_rtx_SET (new_reg, *ad->base)); |
c31d2d11 RS |
3248 | code = recog_memoized (insn); |
3249 | if (code < 0) | |
3250 | { | |
3251 | delete_insns_since (last_insn); | |
3252 | return NULL_RTX; | |
3253 | } | |
3254 | ||
3255 | return new_inner; | |
3256 | } | |
3257 | ||
9005477f | 3258 | /* Make reload base reg + DISP from address AD. Return the new pseudo. */ |
55a2c322 | 3259 | static rtx |
9005477f | 3260 | base_plus_disp_to_reg (struct address_info *ad, rtx disp) |
55a2c322 VM |
3261 | { |
3262 | enum reg_class cl; | |
3263 | rtx new_reg; | |
3264 | ||
9005477f | 3265 | lra_assert (ad->base == ad->base_term); |
277f65de RS |
3266 | cl = base_reg_class (ad->mode, ad->as, ad->base_outer_code, |
3267 | get_index_code (ad)); | |
3268 | new_reg = lra_create_new_reg (GET_MODE (*ad->base_term), NULL_RTX, | |
3269 | cl, "base + disp"); | |
9005477f | 3270 | lra_emit_add (new_reg, *ad->base_term, disp); |
55a2c322 VM |
3271 | return new_reg; |
3272 | } | |
3273 | ||
6e071b1e VM |
3274 | /* Make reload of index part of address AD. Return the new |
3275 | pseudo. */ | |
3276 | static rtx | |
3277 | index_part_to_reg (struct address_info *ad) | |
3278 | { | |
3279 | rtx new_reg; | |
3280 | ||
3281 | new_reg = lra_create_new_reg (GET_MODE (*ad->index), NULL_RTX, | |
3282 | INDEX_REG_CLASS, "index term"); | |
3283 | expand_mult (GET_MODE (*ad->index), *ad->index_term, | |
3284 | GEN_INT (get_index_scale (ad)), new_reg, 1); | |
3285 | return new_reg; | |
3286 | } | |
3287 | ||
277f65de RS |
3288 | /* Return true if we can add a displacement to address AD, even if that |
3289 | makes the address invalid. The fix-up code requires any new address | |
3290 | to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */ | |
02ea4bf4 | 3291 | static bool |
277f65de | 3292 | can_add_disp_p (struct address_info *ad) |
02ea4bf4 | 3293 | { |
277f65de RS |
3294 | return (!ad->autoinc_p |
3295 | && ad->segment == NULL | |
3296 | && ad->base == ad->base_term | |
3297 | && ad->disp == ad->disp_term); | |
02ea4bf4 RS |
3298 | } |
3299 | ||
277f65de RS |
3300 | /* Make equiv substitution in address AD. Return true if a substitution |
3301 | was made. */ | |
55a2c322 | 3302 | static bool |
277f65de | 3303 | equiv_address_substitution (struct address_info *ad) |
55a2c322 | 3304 | { |
277f65de | 3305 | rtx base_reg, new_base_reg, index_reg, new_index_reg, *base_term, *index_term; |
73ca989c RS |
3306 | poly_int64 disp; |
3307 | HOST_WIDE_INT scale; | |
55a2c322 VM |
3308 | bool change_p; |
3309 | ||
277f65de RS |
3310 | base_term = strip_subreg (ad->base_term); |
3311 | if (base_term == NULL) | |
55a2c322 VM |
3312 | base_reg = new_base_reg = NULL_RTX; |
3313 | else | |
3314 | { | |
277f65de | 3315 | base_reg = *base_term; |
8d49e7ef | 3316 | new_base_reg = get_equiv_with_elimination (base_reg, curr_insn); |
55a2c322 | 3317 | } |
277f65de RS |
3318 | index_term = strip_subreg (ad->index_term); |
3319 | if (index_term == NULL) | |
55a2c322 VM |
3320 | index_reg = new_index_reg = NULL_RTX; |
3321 | else | |
3322 | { | |
277f65de | 3323 | index_reg = *index_term; |
8d49e7ef | 3324 | new_index_reg = get_equiv_with_elimination (index_reg, curr_insn); |
55a2c322 VM |
3325 | } |
3326 | if (base_reg == new_base_reg && index_reg == new_index_reg) | |
3327 | return false; | |
3328 | disp = 0; | |
3329 | change_p = false; | |
3330 | if (lra_dump_file != NULL) | |
3331 | { | |
3332 | fprintf (lra_dump_file, "Changing address in insn %d ", | |
3333 | INSN_UID (curr_insn)); | |
cfbeaedf | 3334 | dump_value_slim (lra_dump_file, *ad->outer, 1); |
55a2c322 VM |
3335 | } |
3336 | if (base_reg != new_base_reg) | |
3337 | { | |
73ca989c | 3338 | poly_int64 offset; |
55a2c322 VM |
3339 | if (REG_P (new_base_reg)) |
3340 | { | |
277f65de | 3341 | *base_term = new_base_reg; |
55a2c322 VM |
3342 | change_p = true; |
3343 | } | |
3344 | else if (GET_CODE (new_base_reg) == PLUS | |
3345 | && REG_P (XEXP (new_base_reg, 0)) | |
73ca989c | 3346 | && poly_int_rtx_p (XEXP (new_base_reg, 1), &offset) |
277f65de | 3347 | && can_add_disp_p (ad)) |
55a2c322 | 3348 | { |
73ca989c | 3349 | disp += offset; |
277f65de | 3350 | *base_term = XEXP (new_base_reg, 0); |
55a2c322 VM |
3351 | change_p = true; |
3352 | } | |
277f65de RS |
3353 | if (ad->base_term2 != NULL) |
3354 | *ad->base_term2 = *ad->base_term; | |
55a2c322 | 3355 | } |
55a2c322 VM |
3356 | if (index_reg != new_index_reg) |
3357 | { | |
73ca989c | 3358 | poly_int64 offset; |
55a2c322 VM |
3359 | if (REG_P (new_index_reg)) |
3360 | { | |
277f65de | 3361 | *index_term = new_index_reg; |
55a2c322 VM |
3362 | change_p = true; |
3363 | } | |
3364 | else if (GET_CODE (new_index_reg) == PLUS | |
3365 | && REG_P (XEXP (new_index_reg, 0)) | |
73ca989c | 3366 | && poly_int_rtx_p (XEXP (new_index_reg, 1), &offset) |
277f65de | 3367 | && can_add_disp_p (ad) |
02ea4bf4 | 3368 | && (scale = get_index_scale (ad))) |
55a2c322 | 3369 | { |
73ca989c | 3370 | disp += offset * scale; |
277f65de | 3371 | *index_term = XEXP (new_index_reg, 0); |
55a2c322 VM |
3372 | change_p = true; |
3373 | } | |
3374 | } | |
73ca989c | 3375 | if (maybe_ne (disp, 0)) |
55a2c322 | 3376 | { |
277f65de RS |
3377 | if (ad->disp != NULL) |
3378 | *ad->disp = plus_constant (GET_MODE (*ad->inner), *ad->disp, disp); | |
55a2c322 VM |
3379 | else |
3380 | { | |
277f65de RS |
3381 | *ad->inner = plus_constant (GET_MODE (*ad->inner), *ad->inner, disp); |
3382 | update_address (ad); | |
55a2c322 VM |
3383 | } |
3384 | change_p = true; | |
3385 | } | |
3386 | if (lra_dump_file != NULL) | |
3387 | { | |
3388 | if (! change_p) | |
3389 | fprintf (lra_dump_file, " -- no change\n"); | |
3390 | else | |
3391 | { | |
3392 | fprintf (lra_dump_file, " on equiv "); | |
cfbeaedf | 3393 | dump_value_slim (lra_dump_file, *ad->outer, 1); |
55a2c322 VM |
3394 | fprintf (lra_dump_file, "\n"); |
3395 | } | |
3396 | } | |
3397 | return change_p; | |
3398 | } | |
3399 | ||
04b4828c VM |
3400 | /* Skip all modifiers and whitespaces in constraint STR and return the |
3401 | result. */ | |
3402 | static const char * | |
8bf983c7 | 3403 | skip_constraint_modifiers (const char *str) |
04b4828c VM |
3404 | { |
3405 | for (;;str++) | |
3406 | switch (*str) | |
3407 | { | |
8bf983c7 | 3408 | case '+': case '&' : case '=': case '*': case ' ': case '\t': |
04b4828c VM |
3409 | case '$': case '^' : case '%': case '?': case '!': |
3410 | break; | |
3411 | default: return str; | |
3412 | } | |
3413 | } | |
3414 | ||
d9cf932c VM |
3415 | /* Major function to make reloads for an address in operand NOP or |
3416 | check its correctness (If CHECK_ONLY_P is true). The supported | |
3417 | cases are: | |
bd3d34d4 | 3418 | |
5a107a0f VM |
3419 | 1) an address that existed before LRA started, at which point it |
3420 | must have been valid. These addresses are subject to elimination | |
3421 | and may have become invalid due to the elimination offset being out | |
3422 | of range. | |
bd3d34d4 | 3423 | |
5a107a0f VM |
3424 | 2) an address created by forcing a constant to memory |
3425 | (force_const_to_mem). The initial form of these addresses might | |
3426 | not be valid, and it is this function's job to make them valid. | |
bd3d34d4 RS |
3427 | |
3428 | 3) a frame address formed from a register and a (possibly zero) | |
5a107a0f VM |
3429 | constant offset. As above, these addresses might not be valid and |
3430 | this function must make them so. | |
bd3d34d4 RS |
3431 | |
3432 | Add reloads to the lists *BEFORE and *AFTER. We might need to add | |
55a2c322 | 3433 | reloads to *AFTER because of inc/dec, {pre, post} modify in the |
cc8849a1 VM |
3434 | address. Return true for any RTL change. |
3435 | ||
3436 | The function is a helper function which does not produce all | |
d9cf932c VM |
3437 | transformations (when CHECK_ONLY_P is false) which can be |
3438 | necessary. It does just basic steps. To do all necessary | |
3439 | transformations use function process_address. */ | |
55a2c322 | 3440 | static bool |
d9cf932c VM |
3441 | process_address_1 (int nop, bool check_only_p, |
3442 | rtx_insn **before, rtx_insn **after) | |
55a2c322 | 3443 | { |
277f65de RS |
3444 | struct address_info ad; |
3445 | rtx new_reg; | |
bc2fc1f3 | 3446 | HOST_WIDE_INT scale; |
55a2c322 | 3447 | rtx op = *curr_id->operand_loc[nop]; |
db8b3e14 | 3448 | rtx mem = extract_mem_from_operand (op); |
04b4828c VM |
3449 | const char *constraint; |
3450 | enum constraint_num cn; | |
d9cf932c | 3451 | bool change_p = false; |
55a2c322 | 3452 | |
db8b3e14 | 3453 | if (MEM_P (mem) |
3454 | && GET_MODE (mem) == BLKmode | |
3455 | && GET_CODE (XEXP (mem, 0)) == SCRATCH) | |
823bb054 SB |
3456 | return false; |
3457 | ||
04b4828c | 3458 | constraint |
8bf983c7 | 3459 | = skip_constraint_modifiers (curr_static_id->operand[nop].constraint); |
fb5d9e83 VM |
3460 | if (IN_RANGE (constraint[0], '0', '9')) |
3461 | { | |
3462 | char *end; | |
3463 | unsigned long dup = strtoul (constraint, &end, 10); | |
3464 | constraint | |
8bf983c7 | 3465 | = skip_constraint_modifiers (curr_static_id->operand[dup].constraint); |
fb5d9e83 | 3466 | } |
d81019db VM |
3467 | cn = lookup_constraint (*constraint == '\0' ? "X" : constraint); |
3468 | /* If we have several alternatives or/and several constraints in an | |
3469 | alternative and we can not say at this stage what constraint will be used, | |
3470 | use unknown constraint. The exception is an address constraint. If | |
3471 | operand has one address constraint, probably all others constraints are | |
3472 | address ones. */ | |
8bf983c7 VM |
3473 | if (constraint[0] != '\0' && get_constraint_type (cn) != CT_ADDRESS |
3474 | && *skip_constraint_modifiers (constraint | |
3475 | + CONSTRAINT_LEN (constraint[0], | |
3476 | constraint)) != '\0') | |
a4670f58 | 3477 | cn = CONSTRAINT__UNKNOWN; |
998fd141 AO |
3478 | if (insn_extra_address_constraint (cn) |
3479 | /* When we find an asm operand with an address constraint that | |
3480 | doesn't satisfy address_operand to begin with, we clear | |
3481 | is_address, so that we don't try to make a non-address fit. | |
3482 | If the asm statement got this far, it's because other | |
3483 | constraints are available, and we'll use them, disregarding | |
3484 | the unsatisfiable address ones. */ | |
3485 | && curr_static_id->operand[nop].is_address) | |
277f65de | 3486 | decompose_lea_address (&ad, curr_id->operand_loc[nop]); |
164f0634 | 3487 | /* Do not attempt to decompose arbitrary addresses generated by combine |
db8b3e14 | 3488 | for asm operands with loose constraints, e.g 'X'. |
3489 | Need to extract memory from op for special memory constraint, | |
3490 | i.e. bcst_mem_operand in i386 backend. */ | |
3491 | else if (MEM_P (mem) | |
a81a0bfa | 3492 | && !(INSN_CODE (curr_insn) < 0 |
d38bbb85 VM |
3493 | && get_constraint_type (cn) == CT_FIXED_FORM |
3494 | && constraint_satisfied_p (op, cn))) | |
db8b3e14 | 3495 | decompose_mem_address (&ad, mem); |
55a2c322 VM |
3496 | else if (GET_CODE (op) == SUBREG |
3497 | && MEM_P (SUBREG_REG (op))) | |
277f65de | 3498 | decompose_mem_address (&ad, SUBREG_REG (op)); |
55a2c322 VM |
3499 | else |
3500 | return false; | |
70712859 KK |
3501 | /* If INDEX_REG_CLASS is assigned to base_term already and isn't to |
3502 | index_term, swap them so to avoid assigning INDEX_REG_CLASS to both | |
3503 | when INDEX_REG_CLASS is a single register class. */ | |
3504 | if (ad.base_term != NULL | |
3505 | && ad.index_term != NULL | |
3506 | && ira_class_hard_regs_num[INDEX_REG_CLASS] == 1 | |
3507 | && REG_P (*ad.base_term) | |
3508 | && REG_P (*ad.index_term) | |
3509 | && in_class_p (*ad.base_term, INDEX_REG_CLASS, NULL) | |
3510 | && ! in_class_p (*ad.index_term, INDEX_REG_CLASS, NULL)) | |
3511 | { | |
3512 | std::swap (ad.base, ad.index); | |
3513 | std::swap (ad.base_term, ad.index_term); | |
3514 | } | |
d9cf932c VM |
3515 | if (! check_only_p) |
3516 | change_p = equiv_address_substitution (&ad); | |
277f65de | 3517 | if (ad.base_term != NULL |
55a2c322 | 3518 | && (process_addr_reg |
d9cf932c | 3519 | (ad.base_term, check_only_p, before, |
277f65de RS |
3520 | (ad.autoinc_p |
3521 | && !(REG_P (*ad.base_term) | |
3522 | && find_regno_note (curr_insn, REG_DEAD, | |
3523 | REGNO (*ad.base_term)) != NULL_RTX) | |
55a2c322 | 3524 | ? after : NULL), |
277f65de RS |
3525 | base_reg_class (ad.mode, ad.as, ad.base_outer_code, |
3526 | get_index_code (&ad))))) | |
55a2c322 VM |
3527 | { |
3528 | change_p = true; | |
277f65de RS |
3529 | if (ad.base_term2 != NULL) |
3530 | *ad.base_term2 = *ad.base_term; | |
55a2c322 | 3531 | } |
277f65de | 3532 | if (ad.index_term != NULL |
d9cf932c VM |
3533 | && process_addr_reg (ad.index_term, check_only_p, |
3534 | before, NULL, INDEX_REG_CLASS)) | |
55a2c322 VM |
3535 | change_p = true; |
3536 | ||
777e635f RS |
3537 | /* Target hooks sometimes don't treat extra-constraint addresses as |
3538 | legitimate address_operands, so handle them specially. */ | |
8677664e | 3539 | if (insn_extra_address_constraint (cn) |
777e635f | 3540 | && satisfies_address_constraint_p (&ad, cn)) |
2c62cbaa | 3541 | return change_p; |
2c62cbaa | 3542 | |
d9cf932c VM |
3543 | if (check_only_p) |
3544 | return change_p; | |
3545 | ||
277f65de | 3546 | /* There are three cases where the shape of *AD.INNER may now be invalid: |
bd3d34d4 RS |
3547 | |
3548 | 1) the original address was valid, but either elimination or | |
5a107a0f VM |
3549 | equiv_address_substitution was applied and that made |
3550 | the address invalid. | |
bd3d34d4 RS |
3551 | |
3552 | 2) the address is an invalid symbolic address created by | |
5a107a0f | 3553 | force_const_to_mem. |
bd3d34d4 RS |
3554 | |
3555 | 3) the address is a frame address with an invalid offset. | |
3556 | ||
c31d2d11 RS |
3557 | 4) the address is a frame address with an invalid base. |
3558 | ||
2c62cbaa VM |
3559 | All these cases involve a non-autoinc address, so there is no |
3560 | point revalidating other types. */ | |
1aeffdce | 3561 | if (ad.autoinc_p || valid_address_p (op, &ad, cn)) |
55a2c322 VM |
3562 | return change_p; |
3563 | ||
bd3d34d4 RS |
3564 | /* Any index existed before LRA started, so we can assume that the |
3565 | presence and shape of the index is valid. */ | |
55a2c322 | 3566 | push_to_sequence (*before); |
2c62cbaa | 3567 | lra_assert (ad.disp == ad.disp_term); |
277f65de | 3568 | if (ad.base == NULL) |
55a2c322 | 3569 | { |
277f65de | 3570 | if (ad.index == NULL) |
55a2c322 | 3571 | { |
95831c01 VM |
3572 | rtx_insn *insn; |
3573 | rtx_insn *last = get_last_insn (); | |
55a2c322 | 3574 | int code = -1; |
277f65de RS |
3575 | enum reg_class cl = base_reg_class (ad.mode, ad.as, |
3576 | SCRATCH, SCRATCH); | |
2c62cbaa | 3577 | rtx addr = *ad.inner; |
277f65de | 3578 | |
2c62cbaa | 3579 | new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "addr"); |
d0b2266a TS |
3580 | if (HAVE_lo_sum) |
3581 | { | |
d0b2266a TS |
3582 | /* addr => lo_sum (new_base, addr), case (2) above. */ |
3583 | insn = emit_insn (gen_rtx_SET | |
3584 | (new_reg, | |
3585 | gen_rtx_HIGH (Pmode, copy_rtx (addr)))); | |
3586 | code = recog_memoized (insn); | |
3587 | if (code >= 0) | |
3588 | { | |
3589 | *ad.inner = gen_rtx_LO_SUM (Pmode, new_reg, addr); | |
1aeffdce | 3590 | if (!valid_address_p (op, &ad, cn)) |
d0b2266a TS |
3591 | { |
3592 | /* Try to put lo_sum into register. */ | |
3593 | insn = emit_insn (gen_rtx_SET | |
3594 | (new_reg, | |
3595 | gen_rtx_LO_SUM (Pmode, new_reg, addr))); | |
3596 | code = recog_memoized (insn); | |
3597 | if (code >= 0) | |
3598 | { | |
3599 | *ad.inner = new_reg; | |
1aeffdce | 3600 | if (!valid_address_p (op, &ad, cn)) |
d0b2266a TS |
3601 | { |
3602 | *ad.inner = addr; | |
3603 | code = -1; | |
3604 | } | |
3605 | } | |
3606 | ||
3607 | } | |
3608 | } | |
3609 | if (code < 0) | |
3610 | delete_insns_since (last); | |
3611 | } | |
3612 | ||
55a2c322 VM |
3613 | if (code < 0) |
3614 | { | |
2c62cbaa VM |
3615 | /* addr => new_base, case (2) above. */ |
3616 | lra_emit_move (new_reg, addr); | |
95831c01 VM |
3617 | |
3618 | for (insn = last == NULL_RTX ? get_insns () : NEXT_INSN (last); | |
3619 | insn != NULL_RTX; | |
3620 | insn = NEXT_INSN (insn)) | |
3621 | if (recog_memoized (insn) < 0) | |
3622 | break; | |
3623 | if (insn != NULL_RTX) | |
3624 | { | |
3625 | /* Do nothing if we cannot generate right insns. | |
9c582551 | 3626 | This is analogous to reload pass behavior. */ |
95831c01 VM |
3627 | delete_insns_since (last); |
3628 | end_sequence (); | |
3629 | return false; | |
3630 | } | |
2c62cbaa | 3631 | *ad.inner = new_reg; |
55a2c322 VM |
3632 | } |
3633 | } | |
3634 | else | |
3635 | { | |
bd3d34d4 RS |
3636 | /* index * scale + disp => new base + index * scale, |
3637 | case (1) above. */ | |
277f65de RS |
3638 | enum reg_class cl = base_reg_class (ad.mode, ad.as, PLUS, |
3639 | GET_CODE (*ad.index)); | |
55a2c322 VM |
3640 | |
3641 | lra_assert (INDEX_REG_CLASS != NO_REGS); | |
3642 | new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "disp"); | |
277f65de RS |
3643 | lra_emit_move (new_reg, *ad.disp); |
3644 | *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), | |
3645 | new_reg, *ad.index); | |
55a2c322 VM |
3646 | } |
3647 | } | |
277f65de | 3648 | else if (ad.index == NULL) |
55a2c322 | 3649 | { |
5a107a0f VM |
3650 | int regno; |
3651 | enum reg_class cl; | |
cfa434f6 DM |
3652 | rtx set; |
3653 | rtx_insn *insns, *last_insn; | |
c31d2d11 RS |
3654 | /* Try to reload base into register only if the base is invalid |
3655 | for the address but with valid offset, case (4) above. */ | |
3656 | start_sequence (); | |
3657 | new_reg = base_to_reg (&ad); | |
3658 | ||
bd3d34d4 | 3659 | /* base + disp => new base, cases (1) and (3) above. */ |
55a2c322 VM |
3660 | /* Another option would be to reload the displacement into an |
3661 | index register. However, postreload has code to optimize | |
3662 | address reloads that have the same base and different | |
3663 | displacements, so reloading into an index register would | |
3664 | not necessarily be a win. */ | |
c31d2d11 | 3665 | if (new_reg == NULL_RTX) |
9005477f RS |
3666 | { |
3667 | /* See if the target can split the displacement into a | |
3668 | legitimate new displacement from a local anchor. */ | |
3669 | gcc_assert (ad.disp == ad.disp_term); | |
3670 | poly_int64 orig_offset; | |
3671 | rtx offset1, offset2; | |
3672 | if (poly_int_rtx_p (*ad.disp, &orig_offset) | |
3673 | && targetm.legitimize_address_displacement (&offset1, &offset2, | |
3674 | orig_offset, | |
3675 | ad.mode)) | |
3676 | { | |
3677 | new_reg = base_plus_disp_to_reg (&ad, offset1); | |
3678 | new_reg = gen_rtx_PLUS (GET_MODE (new_reg), new_reg, offset2); | |
3679 | } | |
3680 | else | |
3681 | new_reg = base_plus_disp_to_reg (&ad, *ad.disp); | |
3682 | } | |
5a107a0f VM |
3683 | insns = get_insns (); |
3684 | last_insn = get_last_insn (); | |
3685 | /* If we generated at least two insns, try last insn source as | |
3686 | an address. If we succeed, we generate one less insn. */ | |
9005477f RS |
3687 | if (REG_P (new_reg) |
3688 | && last_insn != insns | |
3689 | && (set = single_set (last_insn)) != NULL_RTX | |
5a107a0f VM |
3690 | && GET_CODE (SET_SRC (set)) == PLUS |
3691 | && REG_P (XEXP (SET_SRC (set), 0)) | |
3692 | && CONSTANT_P (XEXP (SET_SRC (set), 1))) | |
3693 | { | |
3694 | *ad.inner = SET_SRC (set); | |
1aeffdce | 3695 | if (valid_address_p (op, &ad, cn)) |
5a107a0f VM |
3696 | { |
3697 | *ad.base_term = XEXP (SET_SRC (set), 0); | |
3698 | *ad.disp_term = XEXP (SET_SRC (set), 1); | |
3699 | cl = base_reg_class (ad.mode, ad.as, ad.base_outer_code, | |
3700 | get_index_code (&ad)); | |
3701 | regno = REGNO (*ad.base_term); | |
3702 | if (regno >= FIRST_PSEUDO_REGISTER | |
3703 | && cl != lra_get_allocno_class (regno)) | |
a2d0d374 | 3704 | lra_change_class (regno, cl, " Change to", true); |
5a107a0f VM |
3705 | new_reg = SET_SRC (set); |
3706 | delete_insns_since (PREV_INSN (last_insn)); | |
3707 | } | |
3708 | } | |
3709 | end_sequence (); | |
3710 | emit_insn (insns); | |
277f65de | 3711 | *ad.inner = new_reg; |
55a2c322 | 3712 | } |
6e071b1e | 3713 | else if (ad.disp_term != NULL) |
55a2c322 | 3714 | { |
bd3d34d4 RS |
3715 | /* base + scale * index + disp => new base + scale * index, |
3716 | case (1) above. */ | |
9005477f RS |
3717 | gcc_assert (ad.disp == ad.disp_term); |
3718 | new_reg = base_plus_disp_to_reg (&ad, *ad.disp); | |
277f65de RS |
3719 | *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), |
3720 | new_reg, *ad.index); | |
55a2c322 | 3721 | } |
bc2fc1f3 | 3722 | else if ((scale = get_index_scale (&ad)) == 1) |
5a770e01 VM |
3723 | { |
3724 | /* The last transformation to one reg will be made in | |
3725 | curr_insn_transform function. */ | |
3726 | end_sequence (); | |
3727 | return false; | |
3728 | } | |
bc2fc1f3 | 3729 | else if (scale != 0) |
6e071b1e VM |
3730 | { |
3731 | /* base + scale * index => base + new_reg, | |
3732 | case (1) above. | |
3733 | Index part of address may become invalid. For example, we | |
3734 | changed pseudo on the equivalent memory and a subreg of the | |
3735 | pseudo onto the memory of different mode for which the scale is | |
3736 | prohibitted. */ | |
3737 | new_reg = index_part_to_reg (&ad); | |
3738 | *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), | |
3739 | *ad.base_term, new_reg); | |
3740 | } | |
bc2fc1f3 VM |
3741 | else |
3742 | { | |
3743 | enum reg_class cl = base_reg_class (ad.mode, ad.as, | |
3744 | SCRATCH, SCRATCH); | |
3745 | rtx addr = *ad.inner; | |
3746 | ||
3747 | new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "addr"); | |
3748 | /* addr => new_base. */ | |
3749 | lra_emit_move (new_reg, addr); | |
3750 | *ad.inner = new_reg; | |
3751 | } | |
55a2c322 VM |
3752 | *before = get_insns (); |
3753 | end_sequence (); | |
3754 | return true; | |
3755 | } | |
3756 | ||
d9cf932c VM |
3757 | /* If CHECK_ONLY_P is false, do address reloads until it is necessary. |
3758 | Use process_address_1 as a helper function. Return true for any | |
3759 | RTL changes. | |
3760 | ||
3761 | If CHECK_ONLY_P is true, just check address correctness. Return | |
3762 | false if the address correct. */ | |
cc8849a1 | 3763 | static bool |
d9cf932c VM |
3764 | process_address (int nop, bool check_only_p, |
3765 | rtx_insn **before, rtx_insn **after) | |
cc8849a1 VM |
3766 | { |
3767 | bool res = false; | |
3768 | ||
d9cf932c VM |
3769 | while (process_address_1 (nop, check_only_p, before, after)) |
3770 | { | |
3771 | if (check_only_p) | |
3772 | return true; | |
3773 | res = true; | |
3774 | } | |
cc8849a1 VM |
3775 | return res; |
3776 | } | |
3777 | ||
55a2c322 VM |
3778 | /* Emit insns to reload VALUE into a new register. VALUE is an |
3779 | auto-increment or auto-decrement RTX whose operand is a register or | |
3780 | memory location; so reloading involves incrementing that location. | |
3781 | IN is either identical to VALUE, or some cheaper place to reload | |
3782 | value being incremented/decremented from. | |
3783 | ||
3784 | INC_AMOUNT is the number to increment or decrement by (always | |
3785 | positive and ignored for POST_MODIFY/PRE_MODIFY). | |
3786 | ||
3787 | Return pseudo containing the result. */ | |
3788 | static rtx | |
31ae0e43 | 3789 | emit_inc (enum reg_class new_rclass, rtx in, rtx value, poly_int64 inc_amount) |
55a2c322 VM |
3790 | { |
3791 | /* REG or MEM to be copied and incremented. */ | |
3792 | rtx incloc = XEXP (value, 0); | |
3793 | /* Nonzero if increment after copying. */ | |
3794 | int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC | |
3795 | || GET_CODE (value) == POST_MODIFY); | |
cfa434f6 | 3796 | rtx_insn *last; |
55a2c322 | 3797 | rtx inc; |
647d790d | 3798 | rtx_insn *add_insn; |
55a2c322 VM |
3799 | int code; |
3800 | rtx real_in = in == value ? incloc : in; | |
3801 | rtx result; | |
3802 | bool plus_p = true; | |
3803 | ||
3804 | if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY) | |
3805 | { | |
3806 | lra_assert (GET_CODE (XEXP (value, 1)) == PLUS | |
3807 | || GET_CODE (XEXP (value, 1)) == MINUS); | |
3808 | lra_assert (rtx_equal_p (XEXP (XEXP (value, 1), 0), XEXP (value, 0))); | |
3809 | plus_p = GET_CODE (XEXP (value, 1)) == PLUS; | |
3810 | inc = XEXP (XEXP (value, 1), 1); | |
3811 | } | |
3812 | else | |
3813 | { | |
3814 | if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC) | |
3815 | inc_amount = -inc_amount; | |
3816 | ||
31ae0e43 | 3817 | inc = gen_int_mode (inc_amount, GET_MODE (value)); |
55a2c322 VM |
3818 | } |
3819 | ||
3820 | if (! post && REG_P (incloc)) | |
3821 | result = incloc; | |
3822 | else | |
3823 | result = lra_create_new_reg (GET_MODE (value), value, new_rclass, | |
3824 | "INC/DEC result"); | |
3825 | ||
3826 | if (real_in != result) | |
3827 | { | |
3828 | /* First copy the location to the result register. */ | |
3829 | lra_assert (REG_P (result)); | |
3830 | emit_insn (gen_move_insn (result, real_in)); | |
3831 | } | |
3832 | ||
3833 | /* We suppose that there are insns to add/sub with the constant | |
3834 | increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the | |
3835 | old reload worked with this assumption. If the assumption | |
3836 | becomes wrong, we should use approach in function | |
3837 | base_plus_disp_to_reg. */ | |
3838 | if (in == value) | |
3839 | { | |
3840 | /* See if we can directly increment INCLOC. */ | |
3841 | last = get_last_insn (); | |
3842 | add_insn = emit_insn (plus_p | |
3843 | ? gen_add2_insn (incloc, inc) | |
3844 | : gen_sub2_insn (incloc, inc)); | |
3845 | ||
3846 | code = recog_memoized (add_insn); | |
3847 | if (code >= 0) | |
3848 | { | |
3849 | if (! post && result != incloc) | |
3850 | emit_insn (gen_move_insn (result, incloc)); | |
3851 | return result; | |
3852 | } | |
3853 | delete_insns_since (last); | |
3854 | } | |
3855 | ||
3856 | /* If couldn't do the increment directly, must increment in RESULT. | |
3857 | The way we do this depends on whether this is pre- or | |
3858 | post-increment. For pre-increment, copy INCLOC to the reload | |
3859 | register, increment it there, then save back. */ | |
3860 | if (! post) | |
3861 | { | |
3862 | if (real_in != result) | |
3863 | emit_insn (gen_move_insn (result, real_in)); | |
3864 | if (plus_p) | |
3865 | emit_insn (gen_add2_insn (result, inc)); | |
3866 | else | |
3867 | emit_insn (gen_sub2_insn (result, inc)); | |
3868 | if (result != incloc) | |
3869 | emit_insn (gen_move_insn (incloc, result)); | |
3870 | } | |
3871 | else | |
3872 | { | |
3873 | /* Post-increment. | |
3874 | ||
3875 | Because this might be a jump insn or a compare, and because | |
3876 | RESULT may not be available after the insn in an input | |
3877 | reload, we must do the incrementing before the insn being | |
3878 | reloaded for. | |
3879 | ||
3880 | We have already copied IN to RESULT. Increment the copy in | |
3881 | RESULT, save that back, then decrement RESULT so it has | |
3882 | the original value. */ | |
3883 | if (plus_p) | |
3884 | emit_insn (gen_add2_insn (result, inc)); | |
3885 | else | |
3886 | emit_insn (gen_sub2_insn (result, inc)); | |
3887 | emit_insn (gen_move_insn (incloc, result)); | |
3888 | /* Restore non-modified value for the result. We prefer this | |
3889 | way because it does not require an additional hard | |
3890 | register. */ | |
3891 | if (plus_p) | |
3892 | { | |
73ca989c RS |
3893 | poly_int64 offset; |
3894 | if (poly_int_rtx_p (inc, &offset)) | |
69db2d57 | 3895 | emit_insn (gen_add2_insn (result, |
73ca989c | 3896 | gen_int_mode (-offset, |
69db2d57 | 3897 | GET_MODE (result)))); |
55a2c322 VM |
3898 | else |
3899 | emit_insn (gen_sub2_insn (result, inc)); | |
3900 | } | |
3901 | else | |
3902 | emit_insn (gen_add2_insn (result, inc)); | |
3903 | } | |
3904 | return result; | |
3905 | } | |
3906 | ||
2c62cbaa VM |
3907 | /* Return true if the current move insn does not need processing as we |
3908 | already know that it satisfies its constraints. */ | |
3909 | static bool | |
3910 | simple_move_p (void) | |
3911 | { | |
3912 | rtx dest, src; | |
3913 | enum reg_class dclass, sclass; | |
3914 | ||
3915 | lra_assert (curr_insn_set != NULL_RTX); | |
3916 | dest = SET_DEST (curr_insn_set); | |
3917 | src = SET_SRC (curr_insn_set); | |
2008be40 SB |
3918 | |
3919 | /* If the instruction has multiple sets we need to process it even if it | |
3920 | is single_set. This can happen if one or more of the SETs are dead. | |
3921 | See PR73650. */ | |
3922 | if (multiple_sets (curr_insn)) | |
3923 | return false; | |
3924 | ||
2c62cbaa VM |
3925 | return ((dclass = get_op_class (dest)) != NO_REGS |
3926 | && (sclass = get_op_class (src)) != NO_REGS | |
3927 | /* The backend guarantees that register moves of cost 2 | |
3928 | never need reloads. */ | |
03b9b5ce | 3929 | && targetm.register_move_cost (GET_MODE (src), sclass, dclass) == 2); |
2c62cbaa VM |
3930 | } |
3931 | ||
55a2c322 VM |
3932 | /* Swap operands NOP and NOP + 1. */ |
3933 | static inline void | |
3934 | swap_operands (int nop) | |
3935 | { | |
fab27f52 MM |
3936 | std::swap (curr_operand_mode[nop], curr_operand_mode[nop + 1]); |
3937 | std::swap (original_subreg_reg_mode[nop], original_subreg_reg_mode[nop + 1]); | |
3938 | std::swap (*curr_id->operand_loc[nop], *curr_id->operand_loc[nop + 1]); | |
987b67f1 | 3939 | std::swap (equiv_substition_p[nop], equiv_substition_p[nop + 1]); |
55a2c322 VM |
3940 | /* Swap the duplicates too. */ |
3941 | lra_update_dup (curr_id, nop); | |
3942 | lra_update_dup (curr_id, nop + 1); | |
3943 | } | |
3944 | ||
3945 | /* Main entry point of the constraint code: search the body of the | |
3946 | current insn to choose the best alternative. It is mimicking insn | |
3947 | alternative cost calculation model of former reload pass. That is | |
3948 | because machine descriptions were written to use this model. This | |
3949 | model can be changed in future. Make commutative operand exchange | |
3950 | if it is chosen. | |
3951 | ||
d9cf932c VM |
3952 | if CHECK_ONLY_P is false, do RTL changes to satisfy the |
3953 | constraints. Return true if any change happened during function | |
3954 | call. | |
3955 | ||
3956 | If CHECK_ONLY_P is true then don't do any transformation. Just | |
3957 | check that the insn satisfies all constraints. If the insn does | |
3958 | not satisfy any constraint, return true. */ | |
55a2c322 | 3959 | static bool |
d9cf932c | 3960 | curr_insn_transform (bool check_only_p) |
55a2c322 VM |
3961 | { |
3962 | int i, j, k; | |
3963 | int n_operands; | |
3964 | int n_alternatives; | |
aefae0f1 | 3965 | int n_outputs; |
55a2c322 VM |
3966 | int commutative; |
3967 | signed char goal_alt_matched[MAX_RECOG_OPERANDS][MAX_RECOG_OPERANDS]; | |
511dcace | 3968 | signed char match_inputs[MAX_RECOG_OPERANDS + 1]; |
aefae0f1 | 3969 | signed char outputs[MAX_RECOG_OPERANDS + 1]; |
cfa434f6 | 3970 | rtx_insn *before, *after; |
55a2c322 VM |
3971 | bool alt_p = false; |
3972 | /* Flag that the insn has been changed through a transformation. */ | |
3973 | bool change_p; | |
3974 | bool sec_mem_p; | |
55a2c322 | 3975 | bool use_sec_mem_p; |
55a2c322 VM |
3976 | int max_regno_before; |
3977 | int reused_alternative_num; | |
3978 | ||
2c62cbaa VM |
3979 | curr_insn_set = single_set (curr_insn); |
3980 | if (curr_insn_set != NULL_RTX && simple_move_p ()) | |
7874b7c5 VM |
3981 | { |
3982 | /* We assume that the corresponding insn alternative has no | |
3983 | earlier clobbers. If it is not the case, don't define move | |
3984 | cost equal to 2 for the corresponding register classes. */ | |
3985 | lra_set_used_insn_alternative (curr_insn, LRA_NON_CLOBBERED_ALT); | |
3986 | return false; | |
3987 | } | |
2c62cbaa | 3988 | |
55a2c322 VM |
3989 | no_input_reloads_p = no_output_reloads_p = false; |
3990 | goal_alt_number = -1; | |
2c62cbaa | 3991 | change_p = sec_mem_p = false; |
e3b3b596 VM |
3992 | /* CALL_INSNs are not allowed to have any output reloads; neither |
3993 | are insns that SET cc0. Insns that use CC0 are not allowed to | |
3994 | have any input reloads. */ | |
3995 | if (CALL_P (curr_insn)) | |
55a2c322 VM |
3996 | no_output_reloads_p = true; |
3997 | ||
058eb3b0 | 3998 | if (HAVE_cc0 && reg_referenced_p (cc0_rtx, PATTERN (curr_insn))) |
55a2c322 | 3999 | no_input_reloads_p = true; |
058eb3b0 | 4000 | if (HAVE_cc0 && reg_set_p (cc0_rtx, PATTERN (curr_insn))) |
55a2c322 | 4001 | no_output_reloads_p = true; |
55a2c322 VM |
4002 | |
4003 | n_operands = curr_static_id->n_operands; | |
4004 | n_alternatives = curr_static_id->n_alternatives; | |
4005 | ||
4006 | /* Just return "no reloads" if insn has no operands with | |
4007 | constraints. */ | |
4008 | if (n_operands == 0 || n_alternatives == 0) | |
4009 | return false; | |
4010 | ||
4011 | max_regno_before = max_reg_num (); | |
4012 | ||
4013 | for (i = 0; i < n_operands; i++) | |
4014 | { | |
4015 | goal_alt_matched[i][0] = -1; | |
4016 | goal_alt_matches[i] = -1; | |
4017 | } | |
4018 | ||
4019 | commutative = curr_static_id->commutative; | |
4020 | ||
4021 | /* Now see what we need for pseudos that didn't get hard regs or got | |
4022 | the wrong kind of hard reg. For this, we must consider all the | |
4023 | operands together against the register constraints. */ | |
4024 | ||
821b7577 | 4025 | best_losers = best_overall = INT_MAX; |
36ff9dfb | 4026 | best_reload_sum = 0; |
55a2c322 VM |
4027 | |
4028 | curr_swapped = false; | |
4029 | goal_alt_swapped = false; | |
4030 | ||
d9cf932c VM |
4031 | if (! check_only_p) |
4032 | /* Make equivalence substitution and memory subreg elimination | |
4033 | before address processing because an address legitimacy can | |
4034 | depend on memory mode. */ | |
4035 | for (i = 0; i < n_operands; i++) | |
4036 | { | |
0b87be09 | 4037 | rtx op, subst, old; |
d9cf932c | 4038 | bool op_change_p = false; |
0b87be09 VM |
4039 | |
4040 | if (curr_static_id->operand[i].is_operator) | |
4041 | continue; | |
d9cf932c | 4042 | |
0b87be09 | 4043 | old = op = *curr_id->operand_loc[i]; |
d9cf932c VM |
4044 | if (GET_CODE (old) == SUBREG) |
4045 | old = SUBREG_REG (old); | |
4046 | subst = get_equiv_with_elimination (old, curr_insn); | |
895ff86f | 4047 | original_subreg_reg_mode[i] = VOIDmode; |
987b67f1 | 4048 | equiv_substition_p[i] = false; |
d9cf932c VM |
4049 | if (subst != old) |
4050 | { | |
987b67f1 | 4051 | equiv_substition_p[i] = true; |
d9cf932c VM |
4052 | subst = copy_rtx (subst); |
4053 | lra_assert (REG_P (old)); | |
895ff86f | 4054 | if (GET_CODE (op) != SUBREG) |
d9cf932c | 4055 | *curr_id->operand_loc[i] = subst; |
895ff86f VM |
4056 | else |
4057 | { | |
4058 | SUBREG_REG (op) = subst; | |
4059 | if (GET_MODE (subst) == VOIDmode) | |
4060 | original_subreg_reg_mode[i] = GET_MODE (old); | |
4061 | } | |
d9cf932c VM |
4062 | if (lra_dump_file != NULL) |
4063 | { | |
4064 | fprintf (lra_dump_file, | |
4065 | "Changing pseudo %d in operand %i of insn %u on equiv ", | |
4066 | REGNO (old), i, INSN_UID (curr_insn)); | |
4067 | dump_value_slim (lra_dump_file, subst, 1); | |
895ff86f | 4068 | fprintf (lra_dump_file, "\n"); |
d9cf932c VM |
4069 | } |
4070 | op_change_p = change_p = true; | |
4071 | } | |
4072 | if (simplify_operand_subreg (i, GET_MODE (old)) || op_change_p) | |
4073 | { | |
4074 | change_p = true; | |
4075 | lra_update_dup (curr_id, i); | |
4076 | } | |
4077 | } | |
55a2c322 VM |
4078 | |
4079 | /* Reload address registers and displacements. We do it before | |
4080 | finding an alternative because of memory constraints. */ | |
cfa434f6 | 4081 | before = after = NULL; |
55a2c322 VM |
4082 | for (i = 0; i < n_operands; i++) |
4083 | if (! curr_static_id->operand[i].is_operator | |
d9cf932c | 4084 | && process_address (i, check_only_p, &before, &after)) |
55a2c322 | 4085 | { |
d9cf932c VM |
4086 | if (check_only_p) |
4087 | return true; | |
55a2c322 VM |
4088 | change_p = true; |
4089 | lra_update_dup (curr_id, i); | |
4090 | } | |
cc8849a1 | 4091 | |
55a2c322 VM |
4092 | if (change_p) |
4093 | /* If we've changed the instruction then any alternative that | |
4094 | we chose previously may no longer be valid. */ | |
7874b7c5 | 4095 | lra_set_used_insn_alternative (curr_insn, LRA_UNKNOWN_ALT); |
55a2c322 | 4096 | |
d9cf932c | 4097 | if (! check_only_p && curr_insn_set != NULL_RTX |
2c62cbaa VM |
4098 | && check_and_process_move (&change_p, &sec_mem_p)) |
4099 | return change_p; | |
4100 | ||
55a2c322 VM |
4101 | try_swapped: |
4102 | ||
7874b7c5 | 4103 | reused_alternative_num = check_only_p ? LRA_UNKNOWN_ALT : curr_id->used_insn_alternative; |
55a2c322 VM |
4104 | if (lra_dump_file != NULL && reused_alternative_num >= 0) |
4105 | fprintf (lra_dump_file, "Reusing alternative %d for insn #%u\n", | |
4106 | reused_alternative_num, INSN_UID (curr_insn)); | |
4107 | ||
4108 | if (process_alt_operands (reused_alternative_num)) | |
4109 | alt_p = true; | |
4110 | ||
d9cf932c VM |
4111 | if (check_only_p) |
4112 | return ! alt_p || best_losers != 0; | |
4113 | ||
55a2c322 VM |
4114 | /* If insn is commutative (it's safe to exchange a certain pair of |
4115 | operands) then we need to try each alternative twice, the second | |
4116 | time matching those two operands as if we had exchanged them. To | |
4117 | do this, really exchange them in operands. | |
4118 | ||
4119 | If we have just tried the alternatives the second time, return | |
4120 | operands to normal and drop through. */ | |
4121 | ||
4122 | if (reused_alternative_num < 0 && commutative >= 0) | |
4123 | { | |
4124 | curr_swapped = !curr_swapped; | |
4125 | if (curr_swapped) | |
4126 | { | |
4127 | swap_operands (commutative); | |
4128 | goto try_swapped; | |
4129 | } | |
4130 | else | |
4131 | swap_operands (commutative); | |
4132 | } | |
4133 | ||
55a2c322 VM |
4134 | if (! alt_p && ! sec_mem_p) |
4135 | { | |
4136 | /* No alternative works with reloads?? */ | |
4137 | if (INSN_CODE (curr_insn) >= 0) | |
4138 | fatal_insn ("unable to generate reloads for:", curr_insn); | |
4139 | error_for_asm (curr_insn, | |
4140 | "inconsistent operand constraints in an %<asm%>"); | |
11067dee | 4141 | lra_asm_error_p = true; |
2f2709e6 VM |
4142 | if (! JUMP_P (curr_insn)) |
4143 | { | |
4144 | /* Avoid further trouble with this insn. Don't generate use | |
4145 | pattern here as we could use the insn SP offset. */ | |
4146 | lra_set_insn_deleted (curr_insn); | |
4147 | } | |
4148 | else | |
4149 | { | |
4150 | lra_invalidate_insn_data (curr_insn); | |
4151 | ira_nullify_asm_goto (curr_insn); | |
4152 | lra_update_insn_regno_info (curr_insn); | |
4153 | } | |
55a2c322 VM |
4154 | return true; |
4155 | } | |
4156 | ||
4157 | /* If the best alternative is with operands 1 and 2 swapped, swap | |
4158 | them. Update the operand numbers of any reloads already | |
4159 | pushed. */ | |
4160 | ||
4161 | if (goal_alt_swapped) | |
4162 | { | |
4163 | if (lra_dump_file != NULL) | |
4164 | fprintf (lra_dump_file, " Commutative operand exchange in insn %u\n", | |
4165 | INSN_UID (curr_insn)); | |
4166 | ||
4167 | /* Swap the duplicates too. */ | |
4168 | swap_operands (commutative); | |
4169 | change_p = true; | |
4170 | } | |
4171 | ||
f15643d4 | 4172 | /* Some targets' TARGET_SECONDARY_MEMORY_NEEDED (e.g. x86) are defined |
55a2c322 VM |
4173 | too conservatively. So we use the secondary memory only if there |
4174 | is no any alternative without reloads. */ | |
4175 | use_sec_mem_p = false; | |
4176 | if (! alt_p) | |
4177 | use_sec_mem_p = true; | |
4178 | else if (sec_mem_p) | |
4179 | { | |
4180 | for (i = 0; i < n_operands; i++) | |
4181 | if (! goal_alt_win[i] && ! goal_alt_match_win[i]) | |
4182 | break; | |
4183 | use_sec_mem_p = i < n_operands; | |
4184 | } | |
4185 | ||
4186 | if (use_sec_mem_p) | |
4187 | { | |
e03dd765 | 4188 | int in = -1, out = -1; |
89d56d79 | 4189 | rtx new_reg, src, dest, rld; |
ef4bddc2 | 4190 | machine_mode sec_mode, rld_mode; |
55a2c322 | 4191 | |
e03dd765 VM |
4192 | lra_assert (curr_insn_set != NULL_RTX && sec_mem_p); |
4193 | dest = SET_DEST (curr_insn_set); | |
4194 | src = SET_SRC (curr_insn_set); | |
4195 | for (i = 0; i < n_operands; i++) | |
4196 | if (*curr_id->operand_loc[i] == dest) | |
4197 | out = i; | |
4198 | else if (*curr_id->operand_loc[i] == src) | |
4199 | in = i; | |
4200 | for (i = 0; i < curr_static_id->n_dups; i++) | |
4201 | if (out < 0 && *curr_id->dup_loc[i] == dest) | |
4202 | out = curr_static_id->dup_num[i]; | |
4203 | else if (in < 0 && *curr_id->dup_loc[i] == src) | |
4204 | in = curr_static_id->dup_num[i]; | |
4205 | lra_assert (out >= 0 && in >= 0 | |
4206 | && curr_static_id->operand[out].type == OP_OUT | |
4207 | && curr_static_id->operand[in].type == OP_IN); | |
bd4288c0 | 4208 | rld = partial_subreg_p (GET_MODE (src), GET_MODE (dest)) ? src : dest; |
66aa7879 | 4209 | rld_mode = GET_MODE (rld); |
94e23f53 | 4210 | sec_mode = targetm.secondary_memory_needed_mode (rld_mode); |
55a2c322 VM |
4211 | new_reg = lra_create_new_reg (sec_mode, NULL_RTX, |
4212 | NO_REGS, "secondary"); | |
4213 | /* If the mode is changed, it should be wider. */ | |
bd4288c0 | 4214 | lra_assert (!partial_subreg_p (sec_mode, rld_mode)); |
89d56d79 VM |
4215 | if (sec_mode != rld_mode) |
4216 | { | |
4217 | /* If the target says specifically to use another mode for | |
67914693 | 4218 | secondary memory moves we cannot reuse the original |
89d56d79 | 4219 | insn. */ |
1ccd4874 | 4220 | after = emit_spill_move (false, new_reg, dest); |
cfa434f6 | 4221 | lra_process_new_insns (curr_insn, NULL, after, |
1ccd4874 VM |
4222 | "Inserting the sec. move"); |
4223 | /* We may have non null BEFORE here (e.g. after address | |
4224 | processing. */ | |
4225 | push_to_sequence (before); | |
4226 | before = emit_spill_move (true, new_reg, src); | |
4227 | emit_insn (before); | |
4228 | before = get_insns (); | |
4229 | end_sequence (); | |
cfa434f6 | 4230 | lra_process_new_insns (curr_insn, before, NULL, "Changing on"); |
1ccd4874 VM |
4231 | lra_set_insn_deleted (curr_insn); |
4232 | } | |
89d56d79 | 4233 | else if (dest == rld) |
1ccd4874 | 4234 | { |
e03dd765 VM |
4235 | *curr_id->operand_loc[out] = new_reg; |
4236 | lra_update_dup (curr_id, out); | |
66aa7879 | 4237 | after = emit_spill_move (false, new_reg, dest); |
cfa434f6 | 4238 | lra_process_new_insns (curr_insn, NULL, after, |
66aa7879 VM |
4239 | "Inserting the sec. move"); |
4240 | } | |
4241 | else | |
4242 | { | |
e03dd765 VM |
4243 | *curr_id->operand_loc[in] = new_reg; |
4244 | lra_update_dup (curr_id, in); | |
1ccd4874 VM |
4245 | /* See comments above. */ |
4246 | push_to_sequence (before); | |
66aa7879 | 4247 | before = emit_spill_move (true, new_reg, src); |
1ccd4874 VM |
4248 | emit_insn (before); |
4249 | before = get_insns (); | |
4250 | end_sequence (); | |
cfa434f6 | 4251 | lra_process_new_insns (curr_insn, before, NULL, |
66aa7879 VM |
4252 | "Inserting the sec. move"); |
4253 | } | |
4254 | lra_update_insn_regno_info (curr_insn); | |
55a2c322 VM |
4255 | return true; |
4256 | } | |
55a2c322 VM |
4257 | |
4258 | lra_assert (goal_alt_number >= 0); | |
4259 | lra_set_used_insn_alternative (curr_insn, goal_alt_number); | |
4260 | ||
4261 | if (lra_dump_file != NULL) | |
4262 | { | |
4263 | const char *p; | |
4264 | ||
4265 | fprintf (lra_dump_file, " Choosing alt %d in insn %u:", | |
4266 | goal_alt_number, INSN_UID (curr_insn)); | |
4267 | for (i = 0; i < n_operands; i++) | |
4268 | { | |
4269 | p = (curr_static_id->operand_alternative | |
4270 | [goal_alt_number * n_operands + i].constraint); | |
4271 | if (*p == '\0') | |
4272 | continue; | |
4273 | fprintf (lra_dump_file, " (%d) ", i); | |
4274 | for (; *p != '\0' && *p != ',' && *p != '#'; p++) | |
4275 | fputc (*p, lra_dump_file); | |
4276 | } | |
36ff9dfb VM |
4277 | if (INSN_CODE (curr_insn) >= 0 |
4278 | && (p = get_insn_name (INSN_CODE (curr_insn))) != NULL) | |
4279 | fprintf (lra_dump_file, " {%s}", p); | |
73ca989c RS |
4280 | if (maybe_ne (curr_id->sp_offset, 0)) |
4281 | { | |
4282 | fprintf (lra_dump_file, " (sp_off="); | |
4283 | print_dec (curr_id->sp_offset, lra_dump_file); | |
4284 | fprintf (lra_dump_file, ")"); | |
4285 | } | |
4286 | fprintf (lra_dump_file, "\n"); | |
55a2c322 VM |
4287 | } |
4288 | ||
4289 | /* Right now, for any pair of operands I and J that are required to | |
4290 | match, with J < I, goal_alt_matches[I] is J. Add I to | |
4291 | goal_alt_matched[J]. */ | |
f4eafc30 | 4292 | |
55a2c322 VM |
4293 | for (i = 0; i < n_operands; i++) |
4294 | if ((j = goal_alt_matches[i]) >= 0) | |
4295 | { | |
4296 | for (k = 0; goal_alt_matched[j][k] >= 0; k++) | |
4297 | ; | |
4298 | /* We allow matching one output operand and several input | |
4299 | operands. */ | |
4300 | lra_assert (k == 0 | |
4301 | || (curr_static_id->operand[j].type == OP_OUT | |
4302 | && curr_static_id->operand[i].type == OP_IN | |
4303 | && (curr_static_id->operand | |
4304 | [goal_alt_matched[j][0]].type == OP_IN))); | |
4305 | goal_alt_matched[j][k] = i; | |
4306 | goal_alt_matched[j][k + 1] = -1; | |
4307 | } | |
f4eafc30 | 4308 | |
55a2c322 VM |
4309 | for (i = 0; i < n_operands; i++) |
4310 | goal_alt_win[i] |= goal_alt_match_win[i]; | |
f4eafc30 | 4311 | |
55a2c322 VM |
4312 | /* Any constants that aren't allowed and can't be reloaded into |
4313 | registers are here changed into memory references. */ | |
4314 | for (i = 0; i < n_operands; i++) | |
4315 | if (goal_alt_win[i]) | |
4316 | { | |
4317 | int regno; | |
4318 | enum reg_class new_class; | |
4319 | rtx reg = *curr_id->operand_loc[i]; | |
4320 | ||
4321 | if (GET_CODE (reg) == SUBREG) | |
4322 | reg = SUBREG_REG (reg); | |
f4eafc30 | 4323 | |
55a2c322 VM |
4324 | if (REG_P (reg) && (regno = REGNO (reg)) >= FIRST_PSEUDO_REGISTER) |
4325 | { | |
4326 | bool ok_p = in_class_p (reg, goal_alt[i], &new_class); | |
4327 | ||
4328 | if (new_class != NO_REGS && get_reg_class (regno) != new_class) | |
4329 | { | |
4330 | lra_assert (ok_p); | |
a2d0d374 | 4331 | lra_change_class (regno, new_class, " Change to", true); |
55a2c322 VM |
4332 | } |
4333 | } | |
4334 | } | |
4335 | else | |
4336 | { | |
4337 | const char *constraint; | |
4338 | char c; | |
4339 | rtx op = *curr_id->operand_loc[i]; | |
4340 | rtx subreg = NULL_RTX; | |
ef4bddc2 | 4341 | machine_mode mode = curr_operand_mode[i]; |
f4eafc30 | 4342 | |
55a2c322 VM |
4343 | if (GET_CODE (op) == SUBREG) |
4344 | { | |
4345 | subreg = op; | |
4346 | op = SUBREG_REG (op); | |
4347 | mode = GET_MODE (op); | |
4348 | } | |
f4eafc30 | 4349 | |
55a2c322 VM |
4350 | if (CONST_POOL_OK_P (mode, op) |
4351 | && ((targetm.preferred_reload_class | |
4352 | (op, (enum reg_class) goal_alt[i]) == NO_REGS) | |
4353 | || no_input_reloads_p)) | |
4354 | { | |
4355 | rtx tem = force_const_mem (mode, op); | |
f4eafc30 | 4356 | |
55a2c322 VM |
4357 | change_p = true; |
4358 | if (subreg != NULL_RTX) | |
4359 | tem = gen_rtx_SUBREG (mode, tem, SUBREG_BYTE (subreg)); | |
f4eafc30 | 4360 | |
55a2c322 VM |
4361 | *curr_id->operand_loc[i] = tem; |
4362 | lra_update_dup (curr_id, i); | |
d9cf932c | 4363 | process_address (i, false, &before, &after); |
f4eafc30 | 4364 | |
55a2c322 VM |
4365 | /* If the alternative accepts constant pool refs directly |
4366 | there will be no reload needed at all. */ | |
4367 | if (subreg != NULL_RTX) | |
4368 | continue; | |
4369 | /* Skip alternatives before the one requested. */ | |
4370 | constraint = (curr_static_id->operand_alternative | |
4371 | [goal_alt_number * n_operands + i].constraint); | |
4372 | for (; | |
4373 | (c = *constraint) && c != ',' && c != '#'; | |
4374 | constraint += CONSTRAINT_LEN (c, constraint)) | |
4375 | { | |
777e635f | 4376 | enum constraint_num cn = lookup_constraint (constraint); |
9eb1ca69 | 4377 | if ((insn_extra_memory_constraint (cn) |
02f2dc44 VM |
4378 | || insn_extra_special_memory_constraint (cn) |
4379 | || insn_extra_relaxed_memory_constraint (cn)) | |
777e635f | 4380 | && satisfies_memory_constraint_p (tem, cn)) |
55a2c322 | 4381 | break; |
55a2c322 VM |
4382 | } |
4383 | if (c == '\0' || c == ',' || c == '#') | |
4384 | continue; | |
f4eafc30 | 4385 | |
55a2c322 VM |
4386 | goal_alt_win[i] = true; |
4387 | } | |
4388 | } | |
f4eafc30 | 4389 | |
aefae0f1 TP |
4390 | n_outputs = 0; |
4391 | outputs[0] = -1; | |
55a2c322 VM |
4392 | for (i = 0; i < n_operands; i++) |
4393 | { | |
2b778c9d VM |
4394 | int regno; |
4395 | bool optional_p = false; | |
55a2c322 VM |
4396 | rtx old, new_reg; |
4397 | rtx op = *curr_id->operand_loc[i]; | |
4398 | ||
4399 | if (goal_alt_win[i]) | |
4400 | { | |
4401 | if (goal_alt[i] == NO_REGS | |
4402 | && REG_P (op) | |
4403 | /* When we assign NO_REGS it means that we will not | |
4404 | assign a hard register to the scratch pseudo by | |
4405 | assigment pass and the scratch pseudo will be | |
4406 | spilled. Spilled scratch pseudos are transformed | |
4407 | back to scratches at the LRA end. */ | |
44fbc9c6 VM |
4408 | && ira_former_scratch_operand_p (curr_insn, i) |
4409 | && ira_former_scratch_p (REGNO (op))) | |
deca73f5 VM |
4410 | { |
4411 | int regno = REGNO (op); | |
a2d0d374 | 4412 | lra_change_class (regno, NO_REGS, " Change to", true); |
deca73f5 VM |
4413 | if (lra_get_regno_hard_regno (regno) >= 0) |
4414 | /* We don't have to mark all insn affected by the | |
4415 | spilled pseudo as there is only one such insn, the | |
4416 | current one. */ | |
4417 | reg_renumber[regno] = -1; | |
6c051d60 VM |
4418 | lra_assert (bitmap_single_bit_set_p |
4419 | (&lra_reg_info[REGNO (op)].insn_bitmap)); | |
deca73f5 | 4420 | } |
2b778c9d VM |
4421 | /* We can do an optional reload. If the pseudo got a hard |
4422 | reg, we might improve the code through inheritance. If | |
4423 | it does not get a hard register we coalesce memory/memory | |
4424 | moves later. Ignore move insns to avoid cycling. */ | |
b0681c9e | 4425 | if (! lra_simple_p |
2b778c9d VM |
4426 | && lra_undo_inheritance_iter < LRA_MAX_INHERITANCE_PASSES |
4427 | && goal_alt[i] != NO_REGS && REG_P (op) | |
4428 | && (regno = REGNO (op)) >= FIRST_PSEUDO_REGISTER | |
a2d0d374 | 4429 | && regno < new_regno_start |
44fbc9c6 | 4430 | && ! ira_former_scratch_p (regno) |
2b778c9d | 4431 | && reg_renumber[regno] < 0 |
3c954213 VM |
4432 | /* Check that the optional reload pseudo will be able to |
4433 | hold given mode value. */ | |
4434 | && ! (prohibited_class_reg_set_mode_p | |
4435 | (goal_alt[i], reg_class_contents[goal_alt[i]], | |
4436 | PSEUDO_REGNO_MODE (regno))) | |
2b778c9d | 4437 | && (curr_insn_set == NULL_RTX |
b0681c9e VM |
4438 | || !((REG_P (SET_SRC (curr_insn_set)) |
4439 | || MEM_P (SET_SRC (curr_insn_set)) | |
4440 | || GET_CODE (SET_SRC (curr_insn_set)) == SUBREG) | |
4441 | && (REG_P (SET_DEST (curr_insn_set)) | |
4442 | || MEM_P (SET_DEST (curr_insn_set)) | |
4443 | || GET_CODE (SET_DEST (curr_insn_set)) == SUBREG)))) | |
2b778c9d | 4444 | optional_p = true; |
c07a0a22 VM |
4445 | else if (goal_alt_matched[i][0] != -1 |
4446 | && curr_static_id->operand[i].type == OP_OUT | |
4447 | && (curr_static_id->operand_alternative | |
33163a62 VM |
4448 | [goal_alt_number * n_operands + i].earlyclobber) |
4449 | && REG_P (op)) | |
c07a0a22 | 4450 | { |
33163a62 VM |
4451 | for (j = 0; goal_alt_matched[i][j] != -1; j++) |
4452 | { | |
4453 | rtx op2 = *curr_id->operand_loc[goal_alt_matched[i][j]]; | |
4454 | ||
4455 | if (REG_P (op2) && REGNO (op) != REGNO (op2)) | |
4456 | break; | |
4457 | } | |
4458 | if (goal_alt_matched[i][j] != -1) | |
4459 | { | |
4460 | /* Generate reloads for different output and matched | |
4461 | input registers. This is the easiest way to avoid | |
4462 | creation of non-existing register conflicts in | |
4463 | lra-lives.c. */ | |
4464 | match_reload (i, goal_alt_matched[i], outputs, goal_alt[i], &before, | |
4465 | &after, TRUE); | |
4466 | outputs[n_outputs++] = i; | |
4467 | outputs[n_outputs] = -1; | |
4468 | } | |
c07a0a22 VM |
4469 | continue; |
4470 | } | |
2b778c9d VM |
4471 | else |
4472 | continue; | |
55a2c322 | 4473 | } |
f4eafc30 | 4474 | |
55a2c322 VM |
4475 | /* Operands that match previous ones have already been handled. */ |
4476 | if (goal_alt_matches[i] >= 0) | |
4477 | continue; | |
4478 | ||
4479 | /* We should not have an operand with a non-offsettable address | |
4480 | appearing where an offsettable address will do. It also may | |
4481 | be a case when the address should be special in other words | |
4482 | not a general one (e.g. it needs no index reg). */ | |
4483 | if (goal_alt_matched[i][0] == -1 && goal_alt_offmemok[i] && MEM_P (op)) | |
4484 | { | |
4485 | enum reg_class rclass; | |
4486 | rtx *loc = &XEXP (op, 0); | |
4487 | enum rtx_code code = GET_CODE (*loc); | |
4488 | ||
4489 | push_to_sequence (before); | |
4490 | rclass = base_reg_class (GET_MODE (op), MEM_ADDR_SPACE (op), | |
4491 | MEM, SCRATCH); | |
4492 | if (GET_RTX_CLASS (code) == RTX_AUTOINC) | |
4493 | new_reg = emit_inc (rclass, *loc, *loc, | |
4494 | /* This value does not matter for MODIFY. */ | |
4495 | GET_MODE_SIZE (GET_MODE (op))); | |
95921002 | 4496 | else if (get_reload_reg (OP_IN, Pmode, *loc, rclass, FALSE, |
55a2c322 | 4497 | "offsetable address", &new_reg)) |
634c3ff0 VM |
4498 | { |
4499 | rtx addr = *loc; | |
4500 | enum rtx_code code = GET_CODE (addr); | |
6b3034ea AC |
4501 | bool align_p = false; |
4502 | ||
634c3ff0 | 4503 | if (code == AND && CONST_INT_P (XEXP (addr, 1))) |
6b3034ea AC |
4504 | { |
4505 | /* (and ... (const_int -X)) is used to align to X bytes. */ | |
4506 | align_p = true; | |
4507 | addr = XEXP (*loc, 0); | |
4508 | } | |
4509 | else | |
4510 | addr = canonicalize_reload_addr (addr); | |
4511 | ||
634c3ff0 | 4512 | lra_emit_move (new_reg, addr); |
6b3034ea | 4513 | if (align_p) |
634c3ff0 VM |
4514 | emit_move_insn (new_reg, gen_rtx_AND (GET_MODE (new_reg), new_reg, XEXP (*loc, 1))); |
4515 | } | |
55a2c322 VM |
4516 | before = get_insns (); |
4517 | end_sequence (); | |
4518 | *loc = new_reg; | |
4519 | lra_update_dup (curr_id, i); | |
4520 | } | |
4521 | else if (goal_alt_matched[i][0] == -1) | |
4522 | { | |
ef4bddc2 | 4523 | machine_mode mode; |
55a2c322 | 4524 | rtx reg, *loc; |
91914e56 | 4525 | int hard_regno; |
55a2c322 VM |
4526 | enum op_type type = curr_static_id->operand[i].type; |
4527 | ||
4528 | loc = curr_id->operand_loc[i]; | |
4529 | mode = curr_operand_mode[i]; | |
4530 | if (GET_CODE (*loc) == SUBREG) | |
4531 | { | |
4532 | reg = SUBREG_REG (*loc); | |
91914e56 | 4533 | poly_int64 byte = SUBREG_BYTE (*loc); |
55a2c322 | 4534 | if (REG_P (reg) |
8e02e8a0 MF |
4535 | /* Strict_low_part requires reloading the register and not |
4536 | just the subreg. Likewise for a strict subreg no wider | |
4537 | than a word for WORD_REGISTER_OPERATIONS targets. */ | |
55a2c322 | 4538 | && (curr_static_id->operand[i].strict_low |
03a95621 | 4539 | || (!paradoxical_subreg_p (mode, GET_MODE (reg)) |
55a2c322 VM |
4540 | && (hard_regno |
4541 | = get_try_hard_regno (REGNO (reg))) >= 0 | |
4542 | && (simplify_subreg_regno | |
4543 | (hard_regno, | |
4544 | GET_MODE (reg), byte, mode) < 0) | |
4545 | && (goal_alt[i] == NO_REGS | |
4546 | || (simplify_subreg_regno | |
4547 | (ira_class_hard_regs[goal_alt[i]][0], | |
8e02e8a0 | 4548 | GET_MODE (reg), byte, mode) >= 0))) |
e5f83886 | 4549 | || (partial_subreg_p (mode, GET_MODE (reg)) |
cf098191 RS |
4550 | && known_le (GET_MODE_SIZE (GET_MODE (reg)), |
4551 | UNITS_PER_WORD) | |
8e02e8a0 | 4552 | && WORD_REGISTER_OPERATIONS))) |
55a2c322 | 4553 | { |
62cdb862 MF |
4554 | /* An OP_INOUT is required when reloading a subreg of a |
4555 | mode wider than a word to ensure that data beyond the | |
4556 | word being reloaded is preserved. Also automatically | |
4557 | ensure that strict_low_part reloads are made into | |
4558 | OP_INOUT which should already be true from the backend | |
4559 | constraints. */ | |
4560 | if (type == OP_OUT | |
4561 | && (curr_static_id->operand[i].strict_low | |
9eaf97d6 | 4562 | || read_modify_subreg_p (*loc))) |
8b8e23de | 4563 | type = OP_INOUT; |
55a2c322 VM |
4564 | loc = &SUBREG_REG (*loc); |
4565 | mode = GET_MODE (*loc); | |
4566 | } | |
4567 | } | |
4568 | old = *loc; | |
95921002 VM |
4569 | if (get_reload_reg (type, mode, old, goal_alt[i], |
4570 | loc != curr_id->operand_loc[i], "", &new_reg) | |
55a2c322 VM |
4571 | && type != OP_OUT) |
4572 | { | |
4573 | push_to_sequence (before); | |
4574 | lra_emit_move (new_reg, old); | |
4575 | before = get_insns (); | |
4576 | end_sequence (); | |
4577 | } | |
4578 | *loc = new_reg; | |
4579 | if (type != OP_IN | |
4580 | && find_reg_note (curr_insn, REG_UNUSED, old) == NULL_RTX) | |
4581 | { | |
4582 | start_sequence (); | |
4583 | lra_emit_move (type == OP_INOUT ? copy_rtx (old) : old, new_reg); | |
4584 | emit_insn (after); | |
4585 | after = get_insns (); | |
4586 | end_sequence (); | |
4587 | *loc = new_reg; | |
4588 | } | |
4589 | for (j = 0; j < goal_alt_dont_inherit_ops_num; j++) | |
4590 | if (goal_alt_dont_inherit_ops[j] == i) | |
4591 | { | |
4592 | lra_set_regno_unique_value (REGNO (new_reg)); | |
4593 | break; | |
4594 | } | |
4595 | lra_update_dup (curr_id, i); | |
4596 | } | |
4597 | else if (curr_static_id->operand[i].type == OP_IN | |
4598 | && (curr_static_id->operand[goal_alt_matched[i][0]].type | |
57d69a63 VM |
4599 | == OP_OUT |
4600 | || (curr_static_id->operand[goal_alt_matched[i][0]].type | |
4601 | == OP_INOUT | |
4602 | && (operands_match_p | |
4603 | (*curr_id->operand_loc[i], | |
4604 | *curr_id->operand_loc[goal_alt_matched[i][0]], | |
4605 | -1))))) | |
55a2c322 | 4606 | { |
511dcace VM |
4607 | /* generate reloads for input and matched outputs. */ |
4608 | match_inputs[0] = i; | |
4609 | match_inputs[1] = -1; | |
aefae0f1 | 4610 | match_reload (goal_alt_matched[i][0], match_inputs, outputs, |
599e1cf8 VM |
4611 | goal_alt[i], &before, &after, |
4612 | curr_static_id->operand_alternative | |
4613 | [goal_alt_number * n_operands + goal_alt_matched[i][0]] | |
4614 | .earlyclobber); | |
55a2c322 | 4615 | } |
57d69a63 VM |
4616 | else if ((curr_static_id->operand[i].type == OP_OUT |
4617 | || (curr_static_id->operand[i].type == OP_INOUT | |
4618 | && (operands_match_p | |
4619 | (*curr_id->operand_loc[i], | |
4620 | *curr_id->operand_loc[goal_alt_matched[i][0]], | |
4621 | -1)))) | |
55a2c322 | 4622 | && (curr_static_id->operand[goal_alt_matched[i][0]].type |
57d69a63 | 4623 | == OP_IN)) |
511dcace | 4624 | /* Generate reloads for output and matched inputs. */ |
aefae0f1 TP |
4625 | match_reload (i, goal_alt_matched[i], outputs, goal_alt[i], &before, |
4626 | &after, curr_static_id->operand_alternative | |
4627 | [goal_alt_number * n_operands + i].earlyclobber); | |
511dcace VM |
4628 | else if (curr_static_id->operand[i].type == OP_IN |
4629 | && (curr_static_id->operand[goal_alt_matched[i][0]].type | |
4630 | == OP_IN)) | |
4631 | { | |
4632 | /* Generate reloads for matched inputs. */ | |
4633 | match_inputs[0] = i; | |
4634 | for (j = 0; (k = goal_alt_matched[i][j]) >= 0; j++) | |
4635 | match_inputs[j + 1] = k; | |
4636 | match_inputs[j + 1] = -1; | |
aefae0f1 TP |
4637 | match_reload (-1, match_inputs, outputs, goal_alt[i], &before, |
4638 | &after, false); | |
511dcace | 4639 | } |
55a2c322 VM |
4640 | else |
4641 | /* We must generate code in any case when function | |
4642 | process_alt_operands decides that it is possible. */ | |
4643 | gcc_unreachable (); | |
aefae0f1 TP |
4644 | |
4645 | /* Memorise processed outputs so that output remaining to be processed | |
4646 | can avoid using the same register value (see match_reload). */ | |
4647 | if (curr_static_id->operand[i].type == OP_OUT) | |
4648 | { | |
4649 | outputs[n_outputs++] = i; | |
4650 | outputs[n_outputs] = -1; | |
4651 | } | |
4652 | ||
2b778c9d VM |
4653 | if (optional_p) |
4654 | { | |
8a8330b7 VM |
4655 | rtx reg = op; |
4656 | ||
4657 | lra_assert (REG_P (reg)); | |
4658 | regno = REGNO (reg); | |
2b778c9d VM |
4659 | op = *curr_id->operand_loc[i]; /* Substitution. */ |
4660 | if (GET_CODE (op) == SUBREG) | |
4661 | op = SUBREG_REG (op); | |
4662 | gcc_assert (REG_P (op) && (int) REGNO (op) >= new_regno_start); | |
4663 | bitmap_set_bit (&lra_optional_reload_pseudos, REGNO (op)); | |
8a8330b7 | 4664 | lra_reg_info[REGNO (op)].restore_rtx = reg; |
2b778c9d VM |
4665 | if (lra_dump_file != NULL) |
4666 | fprintf (lra_dump_file, | |
4667 | " Making reload reg %d for reg %d optional\n", | |
4668 | REGNO (op), regno); | |
4669 | } | |
55a2c322 VM |
4670 | } |
4671 | if (before != NULL_RTX || after != NULL_RTX | |
4672 | || max_regno_before != max_reg_num ()) | |
4673 | change_p = true; | |
4674 | if (change_p) | |
4675 | { | |
4676 | lra_update_operator_dups (curr_id); | |
4677 | /* Something changes -- process the insn. */ | |
4678 | lra_update_insn_regno_info (curr_insn); | |
4679 | } | |
4680 | lra_process_new_insns (curr_insn, before, after, "Inserting insn reload"); | |
4681 | return change_p; | |
4682 | } | |
4683 | ||
d9cf932c VM |
4684 | /* Return true if INSN satisfies all constraints. In other words, no |
4685 | reload insns are needed. */ | |
4686 | bool | |
4687 | lra_constrain_insn (rtx_insn *insn) | |
4688 | { | |
4689 | int saved_new_regno_start = new_regno_start; | |
4690 | int saved_new_insn_uid_start = new_insn_uid_start; | |
4691 | bool change_p; | |
4692 | ||
4693 | curr_insn = insn; | |
4694 | curr_id = lra_get_insn_recog_data (curr_insn); | |
4695 | curr_static_id = curr_id->insn_static_data; | |
4696 | new_insn_uid_start = get_max_uid (); | |
4697 | new_regno_start = max_reg_num (); | |
4698 | change_p = curr_insn_transform (true); | |
4699 | new_regno_start = saved_new_regno_start; | |
4700 | new_insn_uid_start = saved_new_insn_uid_start; | |
4701 | return ! change_p; | |
4702 | } | |
4703 | ||
55a2c322 VM |
4704 | /* Return true if X is in LIST. */ |
4705 | static bool | |
4706 | in_list_p (rtx x, rtx list) | |
4707 | { | |
4708 | for (; list != NULL_RTX; list = XEXP (list, 1)) | |
4709 | if (XEXP (list, 0) == x) | |
4710 | return true; | |
4711 | return false; | |
4712 | } | |
4713 | ||
4714 | /* Return true if X contains an allocatable hard register (if | |
4715 | HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */ | |
4716 | static bool | |
4717 | contains_reg_p (rtx x, bool hard_reg_p, bool spilled_p) | |
4718 | { | |
4719 | int i, j; | |
4720 | const char *fmt; | |
4721 | enum rtx_code code; | |
4722 | ||
4723 | code = GET_CODE (x); | |
4724 | if (REG_P (x)) | |
4725 | { | |
4726 | int regno = REGNO (x); | |
4727 | HARD_REG_SET alloc_regs; | |
4728 | ||
4729 | if (hard_reg_p) | |
4730 | { | |
4731 | if (regno >= FIRST_PSEUDO_REGISTER) | |
4732 | regno = lra_get_regno_hard_regno (regno); | |
4733 | if (regno < 0) | |
4734 | return false; | |
50b3f54d | 4735 | alloc_regs = ~lra_no_alloc_regs; |
55a2c322 VM |
4736 | return overlaps_hard_reg_set_p (alloc_regs, GET_MODE (x), regno); |
4737 | } | |
4738 | else | |
4739 | { | |
4740 | if (regno < FIRST_PSEUDO_REGISTER) | |
4741 | return false; | |
4742 | if (! spilled_p) | |
4743 | return true; | |
4744 | return lra_get_regno_hard_regno (regno) < 0; | |
4745 | } | |
4746 | } | |
4747 | fmt = GET_RTX_FORMAT (code); | |
4748 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
4749 | { | |
4750 | if (fmt[i] == 'e') | |
4751 | { | |
4752 | if (contains_reg_p (XEXP (x, i), hard_reg_p, spilled_p)) | |
4753 | return true; | |
4754 | } | |
4755 | else if (fmt[i] == 'E') | |
4756 | { | |
4757 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
4758 | if (contains_reg_p (XVECEXP (x, i, j), hard_reg_p, spilled_p)) | |
4759 | return true; | |
4760 | } | |
4761 | } | |
4762 | return false; | |
4763 | } | |
4764 | ||
28430b2e VM |
4765 | /* Process all regs in location *LOC and change them on equivalent |
4766 | substitution. Return true if any change was done. */ | |
55a2c322 | 4767 | static bool |
28430b2e | 4768 | loc_equivalence_change_p (rtx *loc) |
55a2c322 VM |
4769 | { |
4770 | rtx subst, reg, x = *loc; | |
4771 | bool result = false; | |
4772 | enum rtx_code code = GET_CODE (x); | |
4773 | const char *fmt; | |
4774 | int i, j; | |
4775 | ||
4776 | if (code == SUBREG) | |
4777 | { | |
4778 | reg = SUBREG_REG (x); | |
8d49e7ef | 4779 | if ((subst = get_equiv_with_elimination (reg, curr_insn)) != reg |
55a2c322 VM |
4780 | && GET_MODE (subst) == VOIDmode) |
4781 | { | |
4782 | /* We cannot reload debug location. Simplify subreg here | |
4783 | while we know the inner mode. */ | |
4784 | *loc = simplify_gen_subreg (GET_MODE (x), subst, | |
4785 | GET_MODE (reg), SUBREG_BYTE (x)); | |
4786 | return true; | |
4787 | } | |
4788 | } | |
8d49e7ef | 4789 | if (code == REG && (subst = get_equiv_with_elimination (x, curr_insn)) != x) |
55a2c322 VM |
4790 | { |
4791 | *loc = subst; | |
4792 | return true; | |
4793 | } | |
4794 | ||
4795 | /* Scan all the operand sub-expressions. */ | |
4796 | fmt = GET_RTX_FORMAT (code); | |
4797 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
4798 | { | |
4799 | if (fmt[i] == 'e') | |
28430b2e | 4800 | result = loc_equivalence_change_p (&XEXP (x, i)) || result; |
55a2c322 VM |
4801 | else if (fmt[i] == 'E') |
4802 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
4803 | result | |
28430b2e | 4804 | = loc_equivalence_change_p (&XVECEXP (x, i, j)) || result; |
55a2c322 VM |
4805 | } |
4806 | return result; | |
4807 | } | |
4808 | ||
d0608e59 | 4809 | /* Similar to loc_equivalence_change_p, but for use as |
4c2b2d79 VM |
4810 | simplify_replace_fn_rtx callback. DATA is insn for which the |
4811 | elimination is done. If it null we don't do the elimination. */ | |
d0608e59 | 4812 | static rtx |
4c2b2d79 | 4813 | loc_equivalence_callback (rtx loc, const_rtx, void *data) |
d0608e59 JJ |
4814 | { |
4815 | if (!REG_P (loc)) | |
4816 | return NULL_RTX; | |
4817 | ||
4c2b2d79 | 4818 | rtx subst = (data == NULL |
cfa434f6 | 4819 | ? get_equiv (loc) : get_equiv_with_elimination (loc, (rtx_insn *) data)); |
d0608e59 JJ |
4820 | if (subst != loc) |
4821 | return subst; | |
4822 | ||
4823 | return NULL_RTX; | |
4824 | } | |
4825 | ||
55a2c322 VM |
4826 | /* Maximum number of generated reload insns per an insn. It is for |
4827 | preventing this pass cycling in a bug case. */ | |
4828 | #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS | |
4829 | ||
4830 | /* The current iteration number of this LRA pass. */ | |
4831 | int lra_constraint_iter; | |
4832 | ||
7436a1c6 VM |
4833 | /* True if we should during assignment sub-pass check assignment |
4834 | correctness for all pseudos and spill some of them to correct | |
4835 | conflicts. It can be necessary when we substitute equiv which | |
4836 | needs checking register allocation correctness because the | |
4837 | equivalent value contains allocatable hard registers, or when we | |
4838 | restore multi-register pseudo, or when we change the insn code and | |
4839 | its operand became INOUT operand when it was IN one before. */ | |
4840 | bool check_and_force_assignment_correctness_p; | |
55a2c322 VM |
4841 | |
4842 | /* Return true if REGNO is referenced in more than one block. */ | |
4843 | static bool | |
4844 | multi_block_pseudo_p (int regno) | |
4845 | { | |
4846 | basic_block bb = NULL; | |
4847 | unsigned int uid; | |
4848 | bitmap_iterator bi; | |
f4eafc30 | 4849 | |
55a2c322 VM |
4850 | if (regno < FIRST_PSEUDO_REGISTER) |
4851 | return false; | |
f4eafc30 | 4852 | |
4839de55 PP |
4853 | EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi) |
4854 | if (bb == NULL) | |
4855 | bb = BLOCK_FOR_INSN (lra_insn_recog_data[uid]->insn); | |
4856 | else if (BLOCK_FOR_INSN (lra_insn_recog_data[uid]->insn) != bb) | |
4857 | return true; | |
4858 | return false; | |
55a2c322 VM |
4859 | } |
4860 | ||
1966c91b VM |
4861 | /* Return true if LIST contains a deleted insn. */ |
4862 | static bool | |
0cc97fc5 | 4863 | contains_deleted_insn_p (rtx_insn_list *list) |
1966c91b | 4864 | { |
0cc97fc5 DM |
4865 | for (; list != NULL_RTX; list = list->next ()) |
4866 | if (NOTE_P (list->insn ()) | |
4867 | && NOTE_KIND (list->insn ()) == NOTE_INSN_DELETED) | |
1966c91b VM |
4868 | return true; |
4869 | return false; | |
4870 | } | |
4871 | ||
55a2c322 VM |
4872 | /* Return true if X contains a pseudo dying in INSN. */ |
4873 | static bool | |
605780f6 | 4874 | dead_pseudo_p (rtx x, rtx_insn *insn) |
55a2c322 VM |
4875 | { |
4876 | int i, j; | |
4877 | const char *fmt; | |
4878 | enum rtx_code code; | |
4879 | ||
4880 | if (REG_P (x)) | |
4881 | return (insn != NULL_RTX | |
4882 | && find_regno_note (insn, REG_DEAD, REGNO (x)) != NULL_RTX); | |
4883 | code = GET_CODE (x); | |
4884 | fmt = GET_RTX_FORMAT (code); | |
4885 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
4886 | { | |
4887 | if (fmt[i] == 'e') | |
4888 | { | |
4889 | if (dead_pseudo_p (XEXP (x, i), insn)) | |
4890 | return true; | |
4891 | } | |
4892 | else if (fmt[i] == 'E') | |
4893 | { | |
4894 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
4895 | if (dead_pseudo_p (XVECEXP (x, i, j), insn)) | |
4896 | return true; | |
4897 | } | |
4898 | } | |
4899 | return false; | |
4900 | } | |
4901 | ||
4902 | /* Return true if INSN contains a dying pseudo in INSN right hand | |
4903 | side. */ | |
4904 | static bool | |
e8a54173 | 4905 | insn_rhs_dead_pseudo_p (rtx_insn *insn) |
55a2c322 VM |
4906 | { |
4907 | rtx set = single_set (insn); | |
4908 | ||
4909 | gcc_assert (set != NULL); | |
4910 | return dead_pseudo_p (SET_SRC (set), insn); | |
4911 | } | |
4912 | ||
4913 | /* Return true if any init insn of REGNO contains a dying pseudo in | |
4914 | insn right hand side. */ | |
4915 | static bool | |
4916 | init_insn_rhs_dead_pseudo_p (int regno) | |
4917 | { | |
0cc97fc5 | 4918 | rtx_insn_list *insns = ira_reg_equiv[regno].init_insns; |
55a2c322 VM |
4919 | |
4920 | if (insns == NULL) | |
4921 | return false; | |
0cc97fc5 DM |
4922 | for (; insns != NULL_RTX; insns = insns->next ()) |
4923 | if (insn_rhs_dead_pseudo_p (insns->insn ())) | |
55a2c322 VM |
4924 | return true; |
4925 | return false; | |
4926 | } | |
4927 | ||
01e54ef8 VM |
4928 | /* Return TRUE if REGNO has a reverse equivalence. The equivalence is |
4929 | reverse only if we have one init insn with given REGNO as a | |
4930 | source. */ | |
4931 | static bool | |
4932 | reverse_equiv_p (int regno) | |
4933 | { | |
0cc97fc5 DM |
4934 | rtx_insn_list *insns = ira_reg_equiv[regno].init_insns; |
4935 | rtx set; | |
01e54ef8 | 4936 | |
0cc97fc5 | 4937 | if (insns == NULL) |
01e54ef8 | 4938 | return false; |
0cc97fc5 DM |
4939 | if (! INSN_P (insns->insn ()) |
4940 | || insns->next () != NULL) | |
01e54ef8 | 4941 | return false; |
0cc97fc5 | 4942 | if ((set = single_set (insns->insn ())) == NULL_RTX) |
01e54ef8 VM |
4943 | return false; |
4944 | return REG_P (SET_SRC (set)) && (int) REGNO (SET_SRC (set)) == regno; | |
4945 | } | |
4946 | ||
4947 | /* Return TRUE if REGNO was reloaded in an equivalence init insn. We | |
4948 | call this function only for non-reverse equivalence. */ | |
4949 | static bool | |
4950 | contains_reloaded_insn_p (int regno) | |
4951 | { | |
4952 | rtx set; | |
0cc97fc5 | 4953 | rtx_insn_list *list = ira_reg_equiv[regno].init_insns; |
01e54ef8 | 4954 | |
0cc97fc5 DM |
4955 | for (; list != NULL; list = list->next ()) |
4956 | if ((set = single_set (list->insn ())) == NULL_RTX | |
01e54ef8 VM |
4957 | || ! REG_P (SET_DEST (set)) |
4958 | || (int) REGNO (SET_DEST (set)) != regno) | |
4959 | return true; | |
4960 | return false; | |
4961 | } | |
4962 | ||
55a2c322 VM |
4963 | /* Entry function of LRA constraint pass. Return true if the |
4964 | constraint pass did change the code. */ | |
4965 | bool | |
4966 | lra_constraints (bool first_p) | |
4967 | { | |
4968 | bool changed_p; | |
4969 | int i, hard_regno, new_insns_num; | |
6cd1dd26 VM |
4970 | unsigned int min_len, new_min_len, uid; |
4971 | rtx set, x, reg, dest_reg; | |
55a2c322 | 4972 | basic_block last_bb; |
6cd1dd26 | 4973 | bitmap_iterator bi; |
55a2c322 VM |
4974 | |
4975 | lra_constraint_iter++; | |
4976 | if (lra_dump_file != NULL) | |
4977 | fprintf (lra_dump_file, "\n********** Local #%d: **********\n\n", | |
4978 | lra_constraint_iter); | |
55a2c322 | 4979 | changed_p = false; |
bcb21886 KY |
4980 | if (pic_offset_table_rtx |
4981 | && REGNO (pic_offset_table_rtx) >= FIRST_PSEUDO_REGISTER) | |
7436a1c6 VM |
4982 | check_and_force_assignment_correctness_p = true; |
4983 | else if (first_p) | |
15961e4a VM |
4984 | /* On the first iteration we should check IRA assignment |
4985 | correctness. In rare cases, the assignments can be wrong as | |
7e4d17a8 VM |
4986 | early clobbers operands are ignored in IRA or usages of |
4987 | paradoxical sub-registers are not taken into account by | |
4988 | IRA. */ | |
7436a1c6 | 4989 | check_and_force_assignment_correctness_p = true; |
55a2c322 VM |
4990 | new_insn_uid_start = get_max_uid (); |
4991 | new_regno_start = first_p ? lra_constraint_new_regno_start : max_reg_num (); | |
8d49e7ef VM |
4992 | /* Mark used hard regs for target stack size calulations. */ |
4993 | for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++) | |
4994 | if (lra_reg_info[i].nrefs != 0 | |
4995 | && (hard_regno = lra_get_regno_hard_regno (i)) >= 0) | |
4996 | { | |
4997 | int j, nregs; | |
4998 | ||
ad474626 | 4999 | nregs = hard_regno_nregs (hard_regno, lra_reg_info[i].biggest_mode); |
8d49e7ef VM |
5000 | for (j = 0; j < nregs; j++) |
5001 | df_set_regs_ever_live (hard_regno + j, true); | |
5002 | } | |
5003 | /* Do elimination before the equivalence processing as we can spill | |
5004 | some pseudos during elimination. */ | |
5005 | lra_eliminate (false, first_p); | |
d648b5ff | 5006 | auto_bitmap equiv_insn_bitmap (®_obstack); |
55a2c322 VM |
5007 | for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++) |
5008 | if (lra_reg_info[i].nrefs != 0) | |
5009 | { | |
5010 | ira_reg_equiv[i].profitable_p = true; | |
6cd1dd26 | 5011 | reg = regno_reg_rtx[i]; |
8d49e7ef | 5012 | if (lra_get_regno_hard_regno (i) < 0 && (x = get_equiv (reg)) != reg) |
55a2c322 VM |
5013 | { |
5014 | bool pseudo_p = contains_reg_p (x, false, false); | |
55a2c322 | 5015 | |
67914693 | 5016 | /* After RTL transformation, we cannot guarantee that |
1966c91b VM |
5017 | pseudo in the substitution was not reloaded which might |
5018 | make equivalence invalid. For example, in reverse | |
5019 | equiv of p0 | |
5020 | ||
5021 | p0 <- ... | |
5022 | ... | |
5023 | equiv_mem <- p0 | |
5024 | ||
5025 | the memory address register was reloaded before the 2nd | |
5026 | insn. */ | |
5027 | if ((! first_p && pseudo_p) | |
5028 | /* We don't use DF for compilation speed sake. So it | |
5029 | is problematic to update live info when we use an | |
5030 | equivalence containing pseudos in more than one | |
5031 | BB. */ | |
5032 | || (pseudo_p && multi_block_pseudo_p (i)) | |
5033 | /* If an init insn was deleted for some reason, cancel | |
5034 | the equiv. We could update the equiv insns after | |
5035 | transformations including an equiv insn deletion | |
5036 | but it is not worthy as such cases are extremely | |
5037 | rare. */ | |
5038 | || contains_deleted_insn_p (ira_reg_equiv[i].init_insns) | |
55a2c322 VM |
5039 | /* If it is not a reverse equivalence, we check that a |
5040 | pseudo in rhs of the init insn is not dying in the | |
5041 | insn. Otherwise, the live info at the beginning of | |
5042 | the corresponding BB might be wrong after we | |
5043 | removed the insn. When the equiv can be a | |
5044 | constant, the right hand side of the init insn can | |
5045 | be a pseudo. */ | |
01e54ef8 VM |
5046 | || (! reverse_equiv_p (i) |
5047 | && (init_insn_rhs_dead_pseudo_p (i) | |
5048 | /* If we reloaded the pseudo in an equivalence | |
67914693 | 5049 | init insn, we cannot remove the equiv init |
01e54ef8 VM |
5050 | insns and the init insns might write into |
5051 | const memory in this case. */ | |
5052 | || contains_reloaded_insn_p (i))) | |
b28ece32 VM |
5053 | /* Prevent access beyond equivalent memory for |
5054 | paradoxical subregs. */ | |
5055 | || (MEM_P (x) | |
cf098191 RS |
5056 | && maybe_gt (GET_MODE_SIZE (lra_reg_info[i].biggest_mode), |
5057 | GET_MODE_SIZE (GET_MODE (x)))) | |
bcb21886 KY |
5058 | || (pic_offset_table_rtx |
5059 | && ((CONST_POOL_OK_P (PSEUDO_REGNO_MODE (i), x) | |
5060 | && (targetm.preferred_reload_class | |
5061 | (x, lra_get_allocno_class (i)) == NO_REGS)) | |
b81a2f0d | 5062 | || contains_symbol_ref_p (x)))) |
55a2c322 | 5063 | ira_reg_equiv[i].defined_p = false; |
55a2c322 VM |
5064 | if (contains_reg_p (x, false, true)) |
5065 | ira_reg_equiv[i].profitable_p = false; | |
8d49e7ef | 5066 | if (get_equiv (reg) != reg) |
d648b5ff | 5067 | bitmap_ior_into (equiv_insn_bitmap, &lra_reg_info[i].insn_bitmap); |
55a2c322 VM |
5068 | } |
5069 | } | |
4c2b2d79 VM |
5070 | for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++) |
5071 | update_equiv (i); | |
6cd1dd26 VM |
5072 | /* We should add all insns containing pseudos which should be |
5073 | substituted by their equivalences. */ | |
d648b5ff | 5074 | EXECUTE_IF_SET_IN_BITMAP (equiv_insn_bitmap, 0, uid, bi) |
6cd1dd26 | 5075 | lra_push_insn_by_uid (uid); |
55a2c322 VM |
5076 | min_len = lra_insn_stack_length (); |
5077 | new_insns_num = 0; | |
5078 | last_bb = NULL; | |
5079 | changed_p = false; | |
5080 | while ((new_min_len = lra_insn_stack_length ()) != 0) | |
5081 | { | |
5082 | curr_insn = lra_pop_insn (); | |
5083 | --new_min_len; | |
f4eafc30 | 5084 | curr_bb = BLOCK_FOR_INSN (curr_insn); |
55a2c322 VM |
5085 | if (curr_bb != last_bb) |
5086 | { | |
5087 | last_bb = curr_bb; | |
5088 | bb_reload_num = lra_curr_reload_num; | |
5089 | } | |
5090 | if (min_len > new_min_len) | |
5091 | { | |
5092 | min_len = new_min_len; | |
5093 | new_insns_num = 0; | |
5094 | } | |
5095 | if (new_insns_num > MAX_RELOAD_INSNS_NUMBER) | |
5096 | internal_error | |
a9c697b8 | 5097 | ("maximum number of generated reload insns per insn achieved (%d)", |
55a2c322 VM |
5098 | MAX_RELOAD_INSNS_NUMBER); |
5099 | new_insns_num++; | |
5100 | if (DEBUG_INSN_P (curr_insn)) | |
5101 | { | |
5102 | /* We need to check equivalence in debug insn and change | |
5103 | pseudo to the equivalent value if necessary. */ | |
5104 | curr_id = lra_get_insn_recog_data (curr_insn); | |
d648b5ff | 5105 | if (bitmap_bit_p (equiv_insn_bitmap, INSN_UID (curr_insn))) |
4d64ce5c | 5106 | { |
d0608e59 JJ |
5107 | rtx old = *curr_id->operand_loc[0]; |
5108 | *curr_id->operand_loc[0] | |
5109 | = simplify_replace_fn_rtx (old, NULL_RTX, | |
4c2b2d79 | 5110 | loc_equivalence_callback, curr_insn); |
d0608e59 JJ |
5111 | if (old != *curr_id->operand_loc[0]) |
5112 | { | |
5113 | lra_update_insn_regno_info (curr_insn); | |
5114 | changed_p = true; | |
5115 | } | |
4d64ce5c | 5116 | } |
55a2c322 VM |
5117 | } |
5118 | else if (INSN_P (curr_insn)) | |
5119 | { | |
5120 | if ((set = single_set (curr_insn)) != NULL_RTX) | |
5121 | { | |
5122 | dest_reg = SET_DEST (set); | |
5123 | /* The equivalence pseudo could be set up as SUBREG in a | |
5124 | case when it is a call restore insn in a mode | |
5125 | different from the pseudo mode. */ | |
5126 | if (GET_CODE (dest_reg) == SUBREG) | |
5127 | dest_reg = SUBREG_REG (dest_reg); | |
5128 | if ((REG_P (dest_reg) | |
8d49e7ef | 5129 | && (x = get_equiv (dest_reg)) != dest_reg |
55a2c322 | 5130 | /* Remove insns which set up a pseudo whose value |
67914693 | 5131 | cannot be changed. Such insns might be not in |
55a2c322 VM |
5132 | init_insns because we don't update equiv data |
5133 | during insn transformations. | |
5a107a0f | 5134 | |
55a2c322 VM |
5135 | As an example, let suppose that a pseudo got |
5136 | hard register and on the 1st pass was not | |
5137 | changed to equivalent constant. We generate an | |
5138 | additional insn setting up the pseudo because of | |
5139 | secondary memory movement. Then the pseudo is | |
5140 | spilled and we use the equiv constant. In this | |
5141 | case we should remove the additional insn and | |
f6937e32 | 5142 | this insn is not init_insns list. */ |
55a2c322 | 5143 | && (! MEM_P (x) || MEM_READONLY_P (x) |
f6937e32 VM |
5144 | /* Check that this is actually an insn setting |
5145 | up the equivalence. */ | |
55a2c322 VM |
5146 | || in_list_p (curr_insn, |
5147 | ira_reg_equiv | |
5148 | [REGNO (dest_reg)].init_insns))) | |
8d49e7ef | 5149 | || (((x = get_equiv (SET_SRC (set))) != SET_SRC (set)) |
55a2c322 VM |
5150 | && in_list_p (curr_insn, |
5151 | ira_reg_equiv | |
5152 | [REGNO (SET_SRC (set))].init_insns))) | |
5153 | { | |
5154 | /* This is equiv init insn of pseudo which did not get a | |
5155 | hard register -- remove the insn. */ | |
5156 | if (lra_dump_file != NULL) | |
5157 | { | |
5158 | fprintf (lra_dump_file, | |
5159 | " Removing equiv init insn %i (freq=%d)\n", | |
5160 | INSN_UID (curr_insn), | |
fef37404 | 5161 | REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn))); |
cfbeaedf | 5162 | dump_insn_slim (lra_dump_file, curr_insn); |
55a2c322 VM |
5163 | } |
5164 | if (contains_reg_p (x, true, false)) | |
7436a1c6 | 5165 | check_and_force_assignment_correctness_p = true; |
55a2c322 VM |
5166 | lra_set_insn_deleted (curr_insn); |
5167 | continue; | |
5168 | } | |
5169 | } | |
5170 | curr_id = lra_get_insn_recog_data (curr_insn); | |
5171 | curr_static_id = curr_id->insn_static_data; | |
5172 | init_curr_insn_input_reloads (); | |
5173 | init_curr_operand_mode (); | |
d9cf932c | 5174 | if (curr_insn_transform (false)) |
55a2c322 | 5175 | changed_p = true; |
28430b2e VM |
5176 | /* Check non-transformed insns too for equiv change as USE |
5177 | or CLOBBER don't need reloads but can contain pseudos | |
5178 | being changed on their equivalences. */ | |
d648b5ff | 5179 | else if (bitmap_bit_p (equiv_insn_bitmap, INSN_UID (curr_insn)) |
28430b2e VM |
5180 | && loc_equivalence_change_p (&PATTERN (curr_insn))) |
5181 | { | |
5182 | lra_update_insn_regno_info (curr_insn); | |
5183 | changed_p = true; | |
5184 | } | |
55a2c322 VM |
5185 | } |
5186 | } | |
d648b5ff | 5187 | |
55a2c322 VM |
5188 | /* If we used a new hard regno, changed_p should be true because the |
5189 | hard reg is assigned to a new pseudo. */ | |
b2b29377 | 5190 | if (flag_checking && !changed_p) |
55a2c322 VM |
5191 | { |
5192 | for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++) | |
5193 | if (lra_reg_info[i].nrefs != 0 | |
5194 | && (hard_regno = lra_get_regno_hard_regno (i)) >= 0) | |
5195 | { | |
ad474626 RS |
5196 | int j, nregs = hard_regno_nregs (hard_regno, |
5197 | PSEUDO_REGNO_MODE (i)); | |
f4eafc30 | 5198 | |
55a2c322 VM |
5199 | for (j = 0; j < nregs; j++) |
5200 | lra_assert (df_regs_ever_live_p (hard_regno + j)); | |
5201 | } | |
5202 | } | |
55a2c322 VM |
5203 | return changed_p; |
5204 | } | |
5205 | ||
8a8330b7 VM |
5206 | static void initiate_invariants (void); |
5207 | static void finish_invariants (void); | |
5208 | ||
55a2c322 VM |
5209 | /* Initiate the LRA constraint pass. It is done once per |
5210 | function. */ | |
5211 | void | |
5212 | lra_constraints_init (void) | |
5213 | { | |
8a8330b7 | 5214 | initiate_invariants (); |
55a2c322 VM |
5215 | } |
5216 | ||
5217 | /* Finalize the LRA constraint pass. It is done once per | |
5218 | function. */ | |
5219 | void | |
5220 | lra_constraints_finish (void) | |
5221 | { | |
8a8330b7 VM |
5222 | finish_invariants (); |
5223 | } | |
5224 | ||
5225 | \f | |
5226 | ||
5227 | /* Structure describes invariants for ineheritance. */ | |
eb0f8780 | 5228 | struct lra_invariant |
8a8330b7 VM |
5229 | { |
5230 | /* The order number of the invariant. */ | |
5231 | int num; | |
5232 | /* The invariant RTX. */ | |
5233 | rtx invariant_rtx; | |
5234 | /* The origin insn of the invariant. */ | |
5235 | rtx_insn *insn; | |
5236 | }; | |
5237 | ||
eb0f8780 | 5238 | typedef lra_invariant invariant_t; |
8a8330b7 VM |
5239 | typedef invariant_t *invariant_ptr_t; |
5240 | typedef const invariant_t *const_invariant_ptr_t; | |
5241 | ||
5242 | /* Pointer to the inheritance invariants. */ | |
5243 | static vec<invariant_ptr_t> invariants; | |
5244 | ||
5245 | /* Allocation pool for the invariants. */ | |
eb0f8780 | 5246 | static object_allocator<lra_invariant> *invariants_pool; |
8a8330b7 VM |
5247 | |
5248 | /* Hash table for the invariants. */ | |
5249 | static htab_t invariant_table; | |
5250 | ||
5251 | /* Hash function for INVARIANT. */ | |
5252 | static hashval_t | |
5253 | invariant_hash (const void *invariant) | |
5254 | { | |
5255 | rtx inv = ((const_invariant_ptr_t) invariant)->invariant_rtx; | |
5256 | return lra_rtx_hash (inv); | |
5257 | } | |
5258 | ||
5259 | /* Equal function for invariants INVARIANT1 and INVARIANT2. */ | |
5260 | static int | |
5261 | invariant_eq_p (const void *invariant1, const void *invariant2) | |
5262 | { | |
5263 | rtx inv1 = ((const_invariant_ptr_t) invariant1)->invariant_rtx; | |
5264 | rtx inv2 = ((const_invariant_ptr_t) invariant2)->invariant_rtx; | |
5265 | ||
5266 | return rtx_equal_p (inv1, inv2); | |
5267 | } | |
5268 | ||
5269 | /* Insert INVARIANT_RTX into the table if it is not there yet. Return | |
5270 | invariant which is in the table. */ | |
5271 | static invariant_ptr_t | |
5272 | insert_invariant (rtx invariant_rtx) | |
5273 | { | |
5274 | void **entry_ptr; | |
5275 | invariant_t invariant; | |
5276 | invariant_ptr_t invariant_ptr; | |
5277 | ||
5278 | invariant.invariant_rtx = invariant_rtx; | |
5279 | entry_ptr = htab_find_slot (invariant_table, &invariant, INSERT); | |
5280 | if (*entry_ptr == NULL) | |
5281 | { | |
5282 | invariant_ptr = invariants_pool->allocate (); | |
5283 | invariant_ptr->invariant_rtx = invariant_rtx; | |
5284 | invariant_ptr->insn = NULL; | |
5285 | invariants.safe_push (invariant_ptr); | |
5286 | *entry_ptr = (void *) invariant_ptr; | |
5287 | } | |
5288 | return (invariant_ptr_t) *entry_ptr; | |
5289 | } | |
5290 | ||
5291 | /* Initiate the invariant table. */ | |
5292 | static void | |
5293 | initiate_invariants (void) | |
5294 | { | |
5295 | invariants.create (100); | |
eb0f8780 ML |
5296 | invariants_pool |
5297 | = new object_allocator<lra_invariant> ("Inheritance invariants"); | |
8a8330b7 VM |
5298 | invariant_table = htab_create (100, invariant_hash, invariant_eq_p, NULL); |
5299 | } | |
5300 | ||
5301 | /* Finish the invariant table. */ | |
5302 | static void | |
5303 | finish_invariants (void) | |
5304 | { | |
5305 | htab_delete (invariant_table); | |
5306 | delete invariants_pool; | |
5307 | invariants.release (); | |
5308 | } | |
5309 | ||
5310 | /* Make the invariant table empty. */ | |
5311 | static void | |
5312 | clear_invariants (void) | |
5313 | { | |
5314 | htab_empty (invariant_table); | |
5315 | invariants_pool->release (); | |
5316 | invariants.truncate (0); | |
55a2c322 VM |
5317 | } |
5318 | ||
5319 | \f | |
5320 | ||
5321 | /* This page contains code to do inheritance/split | |
5322 | transformations. */ | |
5323 | ||
5324 | /* Number of reloads passed so far in current EBB. */ | |
5325 | static int reloads_num; | |
5326 | ||
5327 | /* Number of calls passed so far in current EBB. */ | |
5328 | static int calls_num; | |
5329 | ||
a1e6ee38 RS |
5330 | /* Index ID is the CALLS_NUM associated the last call we saw with |
5331 | ABI identifier ID. */ | |
5332 | static int last_call_for_abi[NUM_ABI_IDS]; | |
5333 | ||
5334 | /* Which registers have been fully or partially clobbered by a call | |
5335 | since they were last used. */ | |
5336 | static HARD_REG_SET full_and_partial_call_clobbers; | |
5337 | ||
55a2c322 VM |
5338 | /* Current reload pseudo check for validity of elements in |
5339 | USAGE_INSNS. */ | |
5340 | static int curr_usage_insns_check; | |
5341 | ||
5342 | /* Info about last usage of registers in EBB to do inheritance/split | |
5343 | transformation. Inheritance transformation is done from a spilled | |
5344 | pseudo and split transformations from a hard register or a pseudo | |
5345 | assigned to a hard register. */ | |
5346 | struct usage_insns | |
5347 | { | |
5348 | /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member | |
5349 | value INSNS is valid. The insns is chain of optional debug insns | |
1ccd4874 VM |
5350 | and a finishing non-debug insn using the corresponding reg. The |
5351 | value is also used to mark the registers which are set up in the | |
5352 | current insn. The negated insn uid is used for this. */ | |
55a2c322 VM |
5353 | int check; |
5354 | /* Value of global reloads_num at the last insn in INSNS. */ | |
5355 | int reloads_num; | |
5356 | /* Value of global reloads_nums at the last insn in INSNS. */ | |
5357 | int calls_num; | |
5358 | /* It can be true only for splitting. And it means that the restore | |
5359 | insn should be put after insn given by the following member. */ | |
5360 | bool after_p; | |
5361 | /* Next insns in the current EBB which use the original reg and the | |
5362 | original reg value is not changed between the current insn and | |
5363 | the next insns. In order words, e.g. for inheritance, if we need | |
5364 | to use the original reg value again in the next insns we can try | |
5365 | to use the value in a hard register from a reload insn of the | |
5366 | current insn. */ | |
5367 | rtx insns; | |
5368 | }; | |
5369 | ||
5370 | /* Map: regno -> corresponding pseudo usage insns. */ | |
5371 | static struct usage_insns *usage_insns; | |
5372 | ||
5373 | static void | |
1476d1bd | 5374 | setup_next_usage_insn (int regno, rtx insn, int reloads_num, bool after_p) |
55a2c322 VM |
5375 | { |
5376 | usage_insns[regno].check = curr_usage_insns_check; | |
5377 | usage_insns[regno].insns = insn; | |
5378 | usage_insns[regno].reloads_num = reloads_num; | |
5379 | usage_insns[regno].calls_num = calls_num; | |
5380 | usage_insns[regno].after_p = after_p; | |
a1e6ee38 RS |
5381 | if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] >= 0) |
5382 | remove_from_hard_reg_set (&full_and_partial_call_clobbers, | |
5383 | PSEUDO_REGNO_MODE (regno), | |
5384 | reg_renumber[regno]); | |
55a2c322 VM |
5385 | } |
5386 | ||
5387 | /* The function is used to form list REGNO usages which consists of | |
5388 | optional debug insns finished by a non-debug insn using REGNO. | |
5389 | RELOADS_NUM is current number of reload insns processed so far. */ | |
5390 | static void | |
767dc529 | 5391 | add_next_usage_insn (int regno, rtx_insn *insn, int reloads_num) |
55a2c322 VM |
5392 | { |
5393 | rtx next_usage_insns; | |
f4eafc30 | 5394 | |
55a2c322 VM |
5395 | if (usage_insns[regno].check == curr_usage_insns_check |
5396 | && (next_usage_insns = usage_insns[regno].insns) != NULL_RTX | |
5397 | && DEBUG_INSN_P (insn)) | |
5398 | { | |
5399 | /* Check that we did not add the debug insn yet. */ | |
5400 | if (next_usage_insns != insn | |
5401 | && (GET_CODE (next_usage_insns) != INSN_LIST | |
5402 | || XEXP (next_usage_insns, 0) != insn)) | |
5403 | usage_insns[regno].insns = gen_rtx_INSN_LIST (VOIDmode, insn, | |
5404 | next_usage_insns); | |
5405 | } | |
5406 | else if (NONDEBUG_INSN_P (insn)) | |
5407 | setup_next_usage_insn (regno, insn, reloads_num, false); | |
5408 | else | |
5409 | usage_insns[regno].check = 0; | |
5410 | } | |
f4eafc30 | 5411 | |
bc3591eb | 5412 | /* Return first non-debug insn in list USAGE_INSNS. */ |
e8a54173 | 5413 | static rtx_insn * |
bc3591eb VM |
5414 | skip_usage_debug_insns (rtx usage_insns) |
5415 | { | |
5416 | rtx insn; | |
5417 | ||
5418 | /* Skip debug insns. */ | |
5419 | for (insn = usage_insns; | |
5420 | insn != NULL_RTX && GET_CODE (insn) == INSN_LIST; | |
5421 | insn = XEXP (insn, 1)) | |
5422 | ; | |
e8a54173 | 5423 | return safe_as_a <rtx_insn *> (insn); |
bc3591eb VM |
5424 | } |
5425 | ||
5426 | /* Return true if we need secondary memory moves for insn in | |
5427 | USAGE_INSNS after inserting inherited pseudo of class INHER_CL | |
5428 | into the insn. */ | |
5429 | static bool | |
fbebbadd JR |
5430 | check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED, |
5431 | rtx usage_insns ATTRIBUTE_UNUSED) | |
bc3591eb | 5432 | { |
e8a54173 DM |
5433 | rtx_insn *insn; |
5434 | rtx set, dest; | |
bc3591eb VM |
5435 | enum reg_class cl; |
5436 | ||
5437 | if (inher_cl == ALL_REGS | |
5438 | || (insn = skip_usage_debug_insns (usage_insns)) == NULL_RTX) | |
5439 | return false; | |
5440 | lra_assert (INSN_P (insn)); | |
5441 | if ((set = single_set (insn)) == NULL_RTX || ! REG_P (SET_DEST (set))) | |
5442 | return false; | |
5443 | dest = SET_DEST (set); | |
5444 | if (! REG_P (dest)) | |
5445 | return false; | |
5446 | lra_assert (inher_cl != NO_REGS); | |
5447 | cl = get_reg_class (REGNO (dest)); | |
5448 | return (cl != NO_REGS && cl != ALL_REGS | |
f15643d4 | 5449 | && targetm.secondary_memory_needed (GET_MODE (dest), inher_cl, cl)); |
bc3591eb VM |
5450 | } |
5451 | ||
55a2c322 VM |
5452 | /* Registers involved in inheritance/split in the current EBB |
5453 | (inheritance/split pseudos and original registers). */ | |
5454 | static bitmap_head check_only_regs; | |
5455 | ||
67914693 | 5456 | /* Reload pseudos cannot be involded in invariant inheritance in the |
8a8330b7 VM |
5457 | current EBB. */ |
5458 | static bitmap_head invalid_invariant_regs; | |
5459 | ||
55a2c322 VM |
5460 | /* Do inheritance transformations for insn INSN, which defines (if |
5461 | DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which | |
5462 | instruction in the EBB next uses ORIGINAL_REGNO; it has the same | |
5463 | form as the "insns" field of usage_insns. Return true if we | |
5464 | succeed in such transformation. | |
5465 | ||
5466 | The transformations look like: | |
5467 | ||
5468 | p <- ... i <- ... | |
5469 | ... p <- i (new insn) | |
5470 | ... => | |
5471 | <- ... p ... <- ... i ... | |
5472 | or | |
5473 | ... i <- p (new insn) | |
5474 | <- ... p ... <- ... i ... | |
5475 | ... => | |
5476 | <- ... p ... <- ... i ... | |
5477 | where p is a spilled original pseudo and i is a new inheritance pseudo. | |
f4eafc30 L |
5478 | |
5479 | ||
55a2c322 VM |
5480 | The inheritance pseudo has the smallest class of two classes CL and |
5481 | class of ORIGINAL REGNO. */ | |
5482 | static bool | |
5483 | inherit_reload_reg (bool def_p, int original_regno, | |
cfa434f6 | 5484 | enum reg_class cl, rtx_insn *insn, rtx next_usage_insns) |
55a2c322 | 5485 | { |
2ae577fd VM |
5486 | if (optimize_function_for_size_p (cfun)) |
5487 | return false; | |
5488 | ||
55a2c322 VM |
5489 | enum reg_class rclass = lra_get_allocno_class (original_regno); |
5490 | rtx original_reg = regno_reg_rtx[original_regno]; | |
cfa434f6 DM |
5491 | rtx new_reg, usage_insn; |
5492 | rtx_insn *new_insns; | |
55a2c322 VM |
5493 | |
5494 | lra_assert (! usage_insns[original_regno].after_p); | |
5495 | if (lra_dump_file != NULL) | |
5496 | fprintf (lra_dump_file, | |
bc3591eb | 5497 | " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n"); |
55a2c322 VM |
5498 | if (! ira_reg_classes_intersect_p[cl][rclass]) |
5499 | { | |
5500 | if (lra_dump_file != NULL) | |
5501 | { | |
5502 | fprintf (lra_dump_file, | |
bc3591eb | 5503 | " Rejecting inheritance for %d " |
55a2c322 VM |
5504 | "because of disjoint classes %s and %s\n", |
5505 | original_regno, reg_class_names[cl], | |
5506 | reg_class_names[rclass]); | |
5507 | fprintf (lra_dump_file, | |
bc3591eb | 5508 | " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); |
55a2c322 VM |
5509 | } |
5510 | return false; | |
5511 | } | |
5512 | if ((ira_class_subset_p[cl][rclass] && cl != rclass) | |
5513 | /* We don't use a subset of two classes because it can be | |
5514 | NO_REGS. This transformation is still profitable in most | |
5515 | cases even if the classes are not intersected as register | |
5516 | move is probably cheaper than a memory load. */ | |
5517 | || ira_class_hard_regs_num[cl] < ira_class_hard_regs_num[rclass]) | |
5518 | { | |
5519 | if (lra_dump_file != NULL) | |
5520 | fprintf (lra_dump_file, " Use smallest class of %s and %s\n", | |
5521 | reg_class_names[cl], reg_class_names[rclass]); | |
f4eafc30 | 5522 | |
55a2c322 VM |
5523 | rclass = cl; |
5524 | } | |
66aa7879 | 5525 | if (check_secondary_memory_needed_p (rclass, next_usage_insns)) |
bc3591eb VM |
5526 | { |
5527 | /* Reject inheritance resulting in secondary memory moves. | |
5528 | Otherwise, there is a danger in LRA cycling. Also such | |
5529 | transformation will be unprofitable. */ | |
5530 | if (lra_dump_file != NULL) | |
5531 | { | |
e8a54173 | 5532 | rtx_insn *insn = skip_usage_debug_insns (next_usage_insns); |
bc3591eb VM |
5533 | rtx set = single_set (insn); |
5534 | ||
5535 | lra_assert (set != NULL_RTX); | |
5536 | ||
5537 | rtx dest = SET_DEST (set); | |
5538 | ||
5539 | lra_assert (REG_P (dest)); | |
5540 | fprintf (lra_dump_file, | |
5541 | " Rejecting inheritance for insn %d(%s)<-%d(%s) " | |
5542 | "as secondary mem is needed\n", | |
5543 | REGNO (dest), reg_class_names[get_reg_class (REGNO (dest))], | |
66aa7879 | 5544 | original_regno, reg_class_names[rclass]); |
bc3591eb VM |
5545 | fprintf (lra_dump_file, |
5546 | " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); | |
5547 | } | |
5548 | return false; | |
5549 | } | |
55a2c322 VM |
5550 | new_reg = lra_create_new_reg (GET_MODE (original_reg), original_reg, |
5551 | rclass, "inheritance"); | |
5552 | start_sequence (); | |
5553 | if (def_p) | |
a810ee82 | 5554 | lra_emit_move (original_reg, new_reg); |
55a2c322 | 5555 | else |
a810ee82 | 5556 | lra_emit_move (new_reg, original_reg); |
55a2c322 VM |
5557 | new_insns = get_insns (); |
5558 | end_sequence (); | |
5559 | if (NEXT_INSN (new_insns) != NULL_RTX) | |
5560 | { | |
5561 | if (lra_dump_file != NULL) | |
5562 | { | |
5563 | fprintf (lra_dump_file, | |
bc3591eb | 5564 | " Rejecting inheritance %d->%d " |
55a2c322 VM |
5565 | "as it results in 2 or more insns:\n", |
5566 | original_regno, REGNO (new_reg)); | |
dc01c3d1 | 5567 | dump_rtl_slim (lra_dump_file, new_insns, NULL, -1, 0); |
55a2c322 VM |
5568 | fprintf (lra_dump_file, |
5569 | " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); | |
5570 | } | |
5571 | return false; | |
5572 | } | |
ef87312e | 5573 | lra_substitute_pseudo_within_insn (insn, original_regno, new_reg, false); |
55a2c322 VM |
5574 | lra_update_insn_regno_info (insn); |
5575 | if (! def_p) | |
5576 | /* We now have a new usage insn for original regno. */ | |
5577 | setup_next_usage_insn (original_regno, new_insns, reloads_num, false); | |
5578 | if (lra_dump_file != NULL) | |
bc3591eb | 5579 | fprintf (lra_dump_file, " Original reg change %d->%d (bb%d):\n", |
55a2c322 | 5580 | original_regno, REGNO (new_reg), BLOCK_FOR_INSN (insn)->index); |
8a8330b7 | 5581 | lra_reg_info[REGNO (new_reg)].restore_rtx = regno_reg_rtx[original_regno]; |
55a2c322 VM |
5582 | bitmap_set_bit (&check_only_regs, REGNO (new_reg)); |
5583 | bitmap_set_bit (&check_only_regs, original_regno); | |
5584 | bitmap_set_bit (&lra_inheritance_pseudos, REGNO (new_reg)); | |
5585 | if (def_p) | |
cfa434f6 | 5586 | lra_process_new_insns (insn, NULL, new_insns, |
55a2c322 VM |
5587 | "Add original<-inheritance"); |
5588 | else | |
cfa434f6 | 5589 | lra_process_new_insns (insn, new_insns, NULL, |
55a2c322 VM |
5590 | "Add inheritance<-original"); |
5591 | while (next_usage_insns != NULL_RTX) | |
5592 | { | |
5593 | if (GET_CODE (next_usage_insns) != INSN_LIST) | |
5594 | { | |
5595 | usage_insn = next_usage_insns; | |
5596 | lra_assert (NONDEBUG_INSN_P (usage_insn)); | |
5597 | next_usage_insns = NULL; | |
5598 | } | |
5599 | else | |
5600 | { | |
5601 | usage_insn = XEXP (next_usage_insns, 0); | |
5602 | lra_assert (DEBUG_INSN_P (usage_insn)); | |
5603 | next_usage_insns = XEXP (next_usage_insns, 1); | |
5604 | } | |
33006d53 JJ |
5605 | lra_substitute_pseudo (&usage_insn, original_regno, new_reg, false, |
5606 | DEBUG_INSN_P (usage_insn)); | |
cfa434f6 | 5607 | lra_update_insn_regno_info (as_a <rtx_insn *> (usage_insn)); |
55a2c322 VM |
5608 | if (lra_dump_file != NULL) |
5609 | { | |
96a95ac1 | 5610 | basic_block bb = BLOCK_FOR_INSN (usage_insn); |
55a2c322 VM |
5611 | fprintf (lra_dump_file, |
5612 | " Inheritance reuse change %d->%d (bb%d):\n", | |
5613 | original_regno, REGNO (new_reg), | |
96a95ac1 | 5614 | bb ? bb->index : -1); |
1476d1bd | 5615 | dump_insn_slim (lra_dump_file, as_a <rtx_insn *> (usage_insn)); |
55a2c322 VM |
5616 | } |
5617 | } | |
5618 | if (lra_dump_file != NULL) | |
5619 | fprintf (lra_dump_file, | |
5620 | " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); | |
5621 | return true; | |
5622 | } | |
5623 | ||
5624 | /* Return true if we need a caller save/restore for pseudo REGNO which | |
5625 | was assigned to a hard register. */ | |
5626 | static inline bool | |
5627 | need_for_call_save_p (int regno) | |
5628 | { | |
5629 | lra_assert (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] >= 0); | |
a1e6ee38 RS |
5630 | if (usage_insns[regno].calls_num < calls_num) |
5631 | { | |
5632 | unsigned int abis = 0; | |
5633 | for (unsigned int i = 0; i < NUM_ABI_IDS; ++i) | |
5634 | if (last_call_for_abi[i] > usage_insns[regno].calls_num) | |
5635 | abis |= 1 << i; | |
5636 | gcc_assert (abis); | |
5637 | if (call_clobbered_in_region_p (abis, full_and_partial_call_clobbers, | |
5638 | PSEUDO_REGNO_MODE (regno), | |
5639 | reg_renumber[regno])) | |
5640 | return true; | |
5641 | } | |
5642 | return false; | |
55a2c322 VM |
5643 | } |
5644 | ||
1aa95df7 | 5645 | /* Global registers occurring in the current EBB. */ |
55a2c322 VM |
5646 | static bitmap_head ebb_global_regs; |
5647 | ||
5648 | /* Return true if we need a split for hard register REGNO or pseudo | |
5649 | REGNO which was assigned to a hard register. | |
5650 | POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be | |
5651 | used for reloads since the EBB end. It is an approximation of the | |
5652 | used hard registers in the split range. The exact value would | |
5653 | require expensive calculations. If we were aggressive with | |
5654 | splitting because of the approximation, the split pseudo will save | |
5655 | the same hard register assignment and will be removed in the undo | |
5656 | pass. We still need the approximation because too aggressive | |
5657 | splitting would result in too inaccurate cost calculation in the | |
5658 | assignment pass because of too many generated moves which will be | |
5659 | probably removed in the undo pass. */ | |
5660 | static inline bool | |
5661 | need_for_split_p (HARD_REG_SET potential_reload_hard_regs, int regno) | |
5662 | { | |
5663 | int hard_regno = regno < FIRST_PSEUDO_REGISTER ? regno : reg_renumber[regno]; | |
5664 | ||
5665 | lra_assert (hard_regno >= 0); | |
5666 | return ((TEST_HARD_REG_BIT (potential_reload_hard_regs, hard_regno) | |
5667 | /* Don't split eliminable hard registers, otherwise we can | |
5668 | split hard registers like hard frame pointer, which | |
5669 | lives on BB start/end according to DF-infrastructure, | |
5670 | when there is a pseudo assigned to the register and | |
5671 | living in the same BB. */ | |
5672 | && (regno >= FIRST_PSEUDO_REGISTER | |
5673 | || ! TEST_HARD_REG_BIT (eliminable_regset, hard_regno)) | |
5674 | && ! TEST_HARD_REG_BIT (lra_no_alloc_regs, hard_regno) | |
e32e4c4a VM |
5675 | /* Don't split call clobbered hard regs living through |
5676 | calls, otherwise we might have a check problem in the | |
5677 | assign sub-pass as in the most cases (exception is a | |
7436a1c6 | 5678 | situation when check_and_force_assignment_correctness_p value is |
e32e4c4a VM |
5679 | true) the assign pass assumes that all pseudos living |
5680 | through calls are assigned to call saved hard regs. */ | |
5681 | && (regno >= FIRST_PSEUDO_REGISTER | |
a1e6ee38 | 5682 | || !TEST_HARD_REG_BIT (full_and_partial_call_clobbers, regno)) |
55a2c322 VM |
5683 | /* We need at least 2 reloads to make pseudo splitting |
5684 | profitable. We should provide hard regno splitting in | |
5685 | any case to solve 1st insn scheduling problem when | |
5686 | moving hard register definition up might result in | |
5687 | impossibility to find hard register for reload pseudo of | |
5688 | small register class. */ | |
5689 | && (usage_insns[regno].reloads_num | |
8e9d68a9 | 5690 | + (regno < FIRST_PSEUDO_REGISTER ? 0 : 3) < reloads_num) |
55a2c322 VM |
5691 | && (regno < FIRST_PSEUDO_REGISTER |
5692 | /* For short living pseudos, spilling + inheritance can | |
5693 | be considered a substitution for splitting. | |
5694 | Therefore we do not splitting for local pseudos. It | |
5695 | decreases also aggressiveness of splitting. The | |
5696 | minimal number of references is chosen taking into | |
5697 | account that for 2 references splitting has no sense | |
5698 | as we can just spill the pseudo. */ | |
5699 | || (regno >= FIRST_PSEUDO_REGISTER | |
5700 | && lra_reg_info[regno].nrefs > 3 | |
5701 | && bitmap_bit_p (&ebb_global_regs, regno)))) | |
5702 | || (regno >= FIRST_PSEUDO_REGISTER && need_for_call_save_p (regno))); | |
5703 | } | |
5704 | ||
5705 | /* Return class for the split pseudo created from original pseudo with | |
5706 | ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We | |
5707 | choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and | |
5708 | results in no secondary memory movements. */ | |
5709 | static enum reg_class | |
5710 | choose_split_class (enum reg_class allocno_class, | |
5711 | int hard_regno ATTRIBUTE_UNUSED, | |
ef4bddc2 | 5712 | machine_mode mode ATTRIBUTE_UNUSED) |
55a2c322 | 5713 | { |
55a2c322 VM |
5714 | int i; |
5715 | enum reg_class cl, best_cl = NO_REGS; | |
ef4dbe49 JR |
5716 | enum reg_class hard_reg_class ATTRIBUTE_UNUSED |
5717 | = REGNO_REG_CLASS (hard_regno); | |
f4eafc30 | 5718 | |
f15643d4 | 5719 | if (! targetm.secondary_memory_needed (mode, allocno_class, allocno_class) |
55a2c322 VM |
5720 | && TEST_HARD_REG_BIT (reg_class_contents[allocno_class], hard_regno)) |
5721 | return allocno_class; | |
5722 | for (i = 0; | |
5723 | (cl = reg_class_subclasses[allocno_class][i]) != LIM_REG_CLASSES; | |
5724 | i++) | |
f15643d4 RS |
5725 | if (! targetm.secondary_memory_needed (mode, cl, hard_reg_class) |
5726 | && ! targetm.secondary_memory_needed (mode, hard_reg_class, cl) | |
55a2c322 VM |
5727 | && TEST_HARD_REG_BIT (reg_class_contents[cl], hard_regno) |
5728 | && (best_cl == NO_REGS | |
5729 | || ira_class_hard_regs_num[best_cl] < ira_class_hard_regs_num[cl])) | |
5730 | best_cl = cl; | |
5731 | return best_cl; | |
55a2c322 VM |
5732 | } |
5733 | ||
8ffa3150 RS |
5734 | /* Copy any equivalence information from ORIGINAL_REGNO to NEW_REGNO. |
5735 | It only makes sense to call this function if NEW_REGNO is always | |
5736 | equal to ORIGINAL_REGNO. */ | |
5737 | ||
5738 | static void | |
5739 | lra_copy_reg_equiv (unsigned int new_regno, unsigned int original_regno) | |
5740 | { | |
5741 | if (!ira_reg_equiv[original_regno].defined_p) | |
5742 | return; | |
5743 | ||
5744 | ira_expand_reg_equiv (); | |
5745 | ira_reg_equiv[new_regno].defined_p = true; | |
5746 | if (ira_reg_equiv[original_regno].memory) | |
5747 | ira_reg_equiv[new_regno].memory | |
5748 | = copy_rtx (ira_reg_equiv[original_regno].memory); | |
5749 | if (ira_reg_equiv[original_regno].constant) | |
5750 | ira_reg_equiv[new_regno].constant | |
5751 | = copy_rtx (ira_reg_equiv[original_regno].constant); | |
5752 | if (ira_reg_equiv[original_regno].invariant) | |
5753 | ira_reg_equiv[new_regno].invariant | |
5754 | = copy_rtx (ira_reg_equiv[original_regno].invariant); | |
5755 | } | |
5756 | ||
55a2c322 VM |
5757 | /* Do split transformations for insn INSN, which defines or uses |
5758 | ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in | |
5759 | the EBB next uses ORIGINAL_REGNO; it has the same form as the | |
6027ea4c | 5760 | "insns" field of usage_insns. If TO is not NULL, we don't use |
037586dd VM |
5761 | usage_insns, we put restore insns after TO insn. It is a case when |
5762 | we call it from lra_split_hard_reg_for, outside the inheritance | |
5763 | pass. | |
55a2c322 VM |
5764 | |
5765 | The transformations look like: | |
5766 | ||
5767 | p <- ... p <- ... | |
5768 | ... s <- p (new insn -- save) | |
5769 | ... => | |
5770 | ... p <- s (new insn -- restore) | |
5771 | <- ... p ... <- ... p ... | |
5772 | or | |
5773 | <- ... p ... <- ... p ... | |
5774 | ... s <- p (new insn -- save) | |
5775 | ... => | |
5776 | ... p <- s (new insn -- restore) | |
5777 | <- ... p ... <- ... p ... | |
5778 | ||
5779 | where p is an original pseudo got a hard register or a hard | |
5780 | register and s is a new split pseudo. The save is put before INSN | |
5781 | if BEFORE_P is true. Return true if we succeed in such | |
5782 | transformation. */ | |
5783 | static bool | |
cfa434f6 | 5784 | split_reg (bool before_p, int original_regno, rtx_insn *insn, |
6027ea4c | 5785 | rtx next_usage_insns, rtx_insn *to) |
55a2c322 VM |
5786 | { |
5787 | enum reg_class rclass; | |
5788 | rtx original_reg; | |
77bce07c | 5789 | int hard_regno, nregs; |
cfa434f6 DM |
5790 | rtx new_reg, usage_insn; |
5791 | rtx_insn *restore, *save; | |
55a2c322 VM |
5792 | bool after_p; |
5793 | bool call_save_p; | |
3cbf012a | 5794 | machine_mode mode; |
55a2c322 VM |
5795 | |
5796 | if (original_regno < FIRST_PSEUDO_REGISTER) | |
5797 | { | |
5798 | rclass = ira_allocno_class_translate[REGNO_REG_CLASS (original_regno)]; | |
5799 | hard_regno = original_regno; | |
5800 | call_save_p = false; | |
77bce07c | 5801 | nregs = 1; |
3cbf012a BS |
5802 | mode = lra_reg_info[hard_regno].biggest_mode; |
5803 | machine_mode reg_rtx_mode = GET_MODE (regno_reg_rtx[hard_regno]); | |
4bbd51af | 5804 | /* A reg can have a biggest_mode of VOIDmode if it was only ever seen as |
f99f64f6 VM |
5805 | part of a multi-word register. In that case, just use the reg_rtx |
5806 | mode. Do the same also if the biggest mode was larger than a register | |
5807 | or we can not compare the modes. Otherwise, limit the size to that of | |
5808 | the biggest access in the function. */ | |
5809 | if (mode == VOIDmode | |
5810 | || !ordered_p (GET_MODE_PRECISION (mode), | |
5811 | GET_MODE_PRECISION (reg_rtx_mode)) | |
5812 | || paradoxical_subreg_p (mode, reg_rtx_mode)) | |
3cbf012a BS |
5813 | { |
5814 | original_reg = regno_reg_rtx[hard_regno]; | |
5815 | mode = reg_rtx_mode; | |
5816 | } | |
5817 | else | |
5818 | original_reg = gen_rtx_REG (mode, hard_regno); | |
55a2c322 VM |
5819 | } |
5820 | else | |
5821 | { | |
3cbf012a | 5822 | mode = PSEUDO_REGNO_MODE (original_regno); |
55a2c322 | 5823 | hard_regno = reg_renumber[original_regno]; |
ad474626 | 5824 | nregs = hard_regno_nregs (hard_regno, mode); |
55a2c322 VM |
5825 | rclass = lra_get_allocno_class (original_regno); |
5826 | original_reg = regno_reg_rtx[original_regno]; | |
5827 | call_save_p = need_for_call_save_p (original_regno); | |
5828 | } | |
55a2c322 VM |
5829 | lra_assert (hard_regno >= 0); |
5830 | if (lra_dump_file != NULL) | |
5831 | fprintf (lra_dump_file, | |
5832 | " ((((((((((((((((((((((((((((((((((((((((((((((((\n"); | |
3cbf012a | 5833 | |
55a2c322 VM |
5834 | if (call_save_p) |
5835 | { | |
cb1cca12 | 5836 | mode = HARD_REGNO_CALLER_SAVE_MODE (hard_regno, |
ad474626 | 5837 | hard_regno_nregs (hard_regno, mode), |
cb1cca12 VM |
5838 | mode); |
5839 | new_reg = lra_create_new_reg (mode, NULL_RTX, NO_REGS, "save"); | |
55a2c322 VM |
5840 | } |
5841 | else | |
5842 | { | |
3cbf012a | 5843 | rclass = choose_split_class (rclass, hard_regno, mode); |
55a2c322 VM |
5844 | if (rclass == NO_REGS) |
5845 | { | |
5846 | if (lra_dump_file != NULL) | |
5847 | { | |
5848 | fprintf (lra_dump_file, | |
5849 | " Rejecting split of %d(%s): " | |
5850 | "no good reg class for %d(%s)\n", | |
5851 | original_regno, | |
5852 | reg_class_names[lra_get_allocno_class (original_regno)], | |
5853 | hard_regno, | |
5854 | reg_class_names[REGNO_REG_CLASS (hard_regno)]); | |
5855 | fprintf | |
5856 | (lra_dump_file, | |
5857 | " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); | |
5858 | } | |
5859 | return false; | |
5860 | } | |
1b51df94 MF |
5861 | /* Split_if_necessary can split hard registers used as part of a |
5862 | multi-register mode but splits each register individually. The | |
5863 | mode used for each independent register may not be supported | |
5864 | so reject the split. Splitting the wider mode should theoretically | |
5865 | be possible but is not implemented. */ | |
f939c3e6 | 5866 | if (!targetm.hard_regno_mode_ok (hard_regno, mode)) |
1b51df94 MF |
5867 | { |
5868 | if (lra_dump_file != NULL) | |
5869 | { | |
5870 | fprintf (lra_dump_file, | |
5871 | " Rejecting split of %d(%s): unsuitable mode %s\n", | |
5872 | original_regno, | |
5873 | reg_class_names[lra_get_allocno_class (original_regno)], | |
5874 | GET_MODE_NAME (mode)); | |
5875 | fprintf | |
5876 | (lra_dump_file, | |
5877 | " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); | |
5878 | } | |
5879 | return false; | |
5880 | } | |
3cbf012a | 5881 | new_reg = lra_create_new_reg (mode, original_reg, rclass, "split"); |
55a2c322 VM |
5882 | reg_renumber[REGNO (new_reg)] = hard_regno; |
5883 | } | |
8ffa3150 | 5884 | int new_regno = REGNO (new_reg); |
55a2c322 | 5885 | save = emit_spill_move (true, new_reg, original_reg); |
c61fe0cc | 5886 | if (NEXT_INSN (save) != NULL_RTX && !call_save_p) |
55a2c322 | 5887 | { |
55a2c322 VM |
5888 | if (lra_dump_file != NULL) |
5889 | { | |
5890 | fprintf | |
5891 | (lra_dump_file, | |
c61fe0cc | 5892 | " Rejecting split %d->%d resulting in > 2 save insns:\n", |
8ffa3150 | 5893 | original_regno, new_regno); |
dc01c3d1 | 5894 | dump_rtl_slim (lra_dump_file, save, NULL, -1, 0); |
55a2c322 VM |
5895 | fprintf (lra_dump_file, |
5896 | " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); | |
5897 | } | |
5898 | return false; | |
5899 | } | |
5900 | restore = emit_spill_move (false, new_reg, original_reg); | |
c61fe0cc | 5901 | if (NEXT_INSN (restore) != NULL_RTX && !call_save_p) |
55a2c322 | 5902 | { |
55a2c322 VM |
5903 | if (lra_dump_file != NULL) |
5904 | { | |
5905 | fprintf (lra_dump_file, | |
5906 | " Rejecting split %d->%d " | |
c61fe0cc | 5907 | "resulting in > 2 restore insns:\n", |
8ffa3150 | 5908 | original_regno, new_regno); |
dc01c3d1 | 5909 | dump_rtl_slim (lra_dump_file, restore, NULL, -1, 0); |
55a2c322 VM |
5910 | fprintf (lra_dump_file, |
5911 | " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); | |
5912 | } | |
5913 | return false; | |
5914 | } | |
8ffa3150 RS |
5915 | /* Transfer equivalence information to the spill register, so that |
5916 | if we fail to allocate the spill register, we have the option of | |
5917 | rematerializing the original value instead of spilling to the stack. */ | |
5918 | if (!HARD_REGISTER_NUM_P (original_regno) | |
5919 | && mode == PSEUDO_REGNO_MODE (original_regno)) | |
5920 | lra_copy_reg_equiv (new_regno, original_regno); | |
8ffa3150 | 5921 | lra_reg_info[new_regno].restore_rtx = regno_reg_rtx[original_regno]; |
8ffa3150 | 5922 | bitmap_set_bit (&lra_split_regs, new_regno); |
6027ea4c | 5923 | if (to != NULL) |
55a2c322 | 5924 | { |
037586dd | 5925 | lra_assert (next_usage_insns == NULL); |
6027ea4c VM |
5926 | usage_insn = to; |
5927 | after_p = TRUE; | |
5928 | } | |
5929 | else | |
5930 | { | |
037586dd VM |
5931 | /* We need check_only_regs only inside the inheritance pass. */ |
5932 | bitmap_set_bit (&check_only_regs, new_regno); | |
5933 | bitmap_set_bit (&check_only_regs, original_regno); | |
6027ea4c VM |
5934 | after_p = usage_insns[original_regno].after_p; |
5935 | for (;;) | |
b3231b65 | 5936 | { |
6027ea4c VM |
5937 | if (GET_CODE (next_usage_insns) != INSN_LIST) |
5938 | { | |
5939 | usage_insn = next_usage_insns; | |
5940 | break; | |
5941 | } | |
5942 | usage_insn = XEXP (next_usage_insns, 0); | |
5943 | lra_assert (DEBUG_INSN_P (usage_insn)); | |
5944 | next_usage_insns = XEXP (next_usage_insns, 1); | |
5945 | lra_substitute_pseudo (&usage_insn, original_regno, new_reg, false, | |
5946 | true); | |
5947 | lra_update_insn_regno_info (as_a <rtx_insn *> (usage_insn)); | |
5948 | if (lra_dump_file != NULL) | |
5949 | { | |
5950 | fprintf (lra_dump_file, " Split reuse change %d->%d:\n", | |
5951 | original_regno, new_regno); | |
5952 | dump_insn_slim (lra_dump_file, as_a <rtx_insn *> (usage_insn)); | |
5953 | } | |
55a2c322 VM |
5954 | } |
5955 | } | |
5956 | lra_assert (NOTE_P (usage_insn) || NONDEBUG_INSN_P (usage_insn)); | |
5957 | lra_assert (usage_insn != insn || (after_p && before_p)); | |
cfa434f6 DM |
5958 | lra_process_new_insns (as_a <rtx_insn *> (usage_insn), |
5959 | after_p ? NULL : restore, | |
5960 | after_p ? restore : NULL, | |
55a2c322 VM |
5961 | call_save_p |
5962 | ? "Add reg<-save" : "Add reg<-split"); | |
cfa434f6 DM |
5963 | lra_process_new_insns (insn, before_p ? save : NULL, |
5964 | before_p ? NULL : save, | |
55a2c322 VM |
5965 | call_save_p |
5966 | ? "Add save<-reg" : "Add split<-reg"); | |
77bce07c VM |
5967 | if (nregs > 1) |
5968 | /* If we are trying to split multi-register. We should check | |
5969 | conflicts on the next assignment sub-pass. IRA can allocate on | |
5970 | sub-register levels, LRA do this on pseudos level right now and | |
5971 | this discrepancy may create allocation conflicts after | |
5972 | splitting. */ | |
7436a1c6 | 5973 | check_and_force_assignment_correctness_p = true; |
55a2c322 VM |
5974 | if (lra_dump_file != NULL) |
5975 | fprintf (lra_dump_file, | |
5976 | " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); | |
5977 | return true; | |
5978 | } | |
5979 | ||
6027ea4c VM |
5980 | /* Split a hard reg for reload pseudo REGNO having RCLASS and living |
5981 | in the range [FROM, TO]. Return true if did a split. Otherwise, | |
5982 | return false. */ | |
5983 | bool | |
5984 | spill_hard_reg_in_range (int regno, enum reg_class rclass, rtx_insn *from, rtx_insn *to) | |
5985 | { | |
5986 | int i, hard_regno; | |
5987 | int rclass_size; | |
5988 | rtx_insn *insn; | |
7293e3f5 VM |
5989 | unsigned int uid; |
5990 | bitmap_iterator bi; | |
5991 | HARD_REG_SET ignore; | |
6027ea4c VM |
5992 | |
5993 | lra_assert (from != NULL && to != NULL); | |
7293e3f5 VM |
5994 | CLEAR_HARD_REG_SET (ignore); |
5995 | EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi) | |
5996 | { | |
5997 | lra_insn_recog_data_t id = lra_insn_recog_data[uid]; | |
5998 | struct lra_static_insn_data *static_id = id->insn_static_data; | |
5999 | struct lra_insn_reg *reg; | |
6000 | ||
6001 | for (reg = id->regs; reg != NULL; reg = reg->next) | |
65e87462 | 6002 | if (reg->regno < FIRST_PSEUDO_REGISTER) |
7293e3f5 VM |
6003 | SET_HARD_REG_BIT (ignore, reg->regno); |
6004 | for (reg = static_id->hard_regs; reg != NULL; reg = reg->next) | |
6005 | SET_HARD_REG_BIT (ignore, reg->regno); | |
6006 | } | |
6027ea4c VM |
6007 | rclass_size = ira_class_hard_regs_num[rclass]; |
6008 | for (i = 0; i < rclass_size; i++) | |
6009 | { | |
6010 | hard_regno = ira_class_hard_regs[rclass][i]; | |
7293e3f5 VM |
6011 | if (! TEST_HARD_REG_BIT (lra_reg_info[regno].conflict_hard_regs, hard_regno) |
6012 | || TEST_HARD_REG_BIT (ignore, hard_regno)) | |
6027ea4c VM |
6013 | continue; |
6014 | for (insn = from; insn != NEXT_INSN (to); insn = NEXT_INSN (insn)) | |
dc843a85 | 6015 | { |
3664a0f1 | 6016 | struct lra_static_insn_data *static_id; |
dc843a85 IL |
6017 | struct lra_insn_reg *reg; |
6018 | ||
3664a0f1 IL |
6019 | if (!INSN_P (insn)) |
6020 | continue; | |
6021 | if (bitmap_bit_p (&lra_reg_info[hard_regno].insn_bitmap, | |
6022 | INSN_UID (insn))) | |
dc843a85 | 6023 | break; |
3664a0f1 | 6024 | static_id = lra_get_insn_recog_data (insn)->insn_static_data; |
dc843a85 IL |
6025 | for (reg = static_id->hard_regs; reg != NULL; reg = reg->next) |
6026 | if (reg->regno == hard_regno) | |
6027 | break; | |
6028 | if (reg != NULL) | |
6029 | break; | |
6030 | } | |
6027ea4c VM |
6031 | if (insn != NEXT_INSN (to)) |
6032 | continue; | |
6033 | if (split_reg (TRUE, hard_regno, from, NULL, to)) | |
6034 | return true; | |
6035 | } | |
6036 | return false; | |
6037 | } | |
6038 | ||
55a2c322 VM |
6039 | /* Recognize that we need a split transformation for insn INSN, which |
6040 | defines or uses REGNO in its insn biggest MODE (we use it only if | |
6041 | REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains | |
6042 | hard registers which might be used for reloads since the EBB end. | |
6043 | Put the save before INSN if BEFORE_P is true. MAX_UID is maximla | |
6044 | uid before starting INSN processing. Return true if we succeed in | |
6045 | such transformation. */ | |
6046 | static bool | |
ef4bddc2 | 6047 | split_if_necessary (int regno, machine_mode mode, |
55a2c322 | 6048 | HARD_REG_SET potential_reload_hard_regs, |
cfa434f6 | 6049 | bool before_p, rtx_insn *insn, int max_uid) |
55a2c322 VM |
6050 | { |
6051 | bool res = false; | |
6052 | int i, nregs = 1; | |
6053 | rtx next_usage_insns; | |
6054 | ||
6055 | if (regno < FIRST_PSEUDO_REGISTER) | |
ad474626 | 6056 | nregs = hard_regno_nregs (regno, mode); |
55a2c322 VM |
6057 | for (i = 0; i < nregs; i++) |
6058 | if (usage_insns[regno + i].check == curr_usage_insns_check | |
6059 | && (next_usage_insns = usage_insns[regno + i].insns) != NULL_RTX | |
6060 | /* To avoid processing the register twice or more. */ | |
6061 | && ((GET_CODE (next_usage_insns) != INSN_LIST | |
6062 | && INSN_UID (next_usage_insns) < max_uid) | |
6063 | || (GET_CODE (next_usage_insns) == INSN_LIST | |
6064 | && (INSN_UID (XEXP (next_usage_insns, 0)) < max_uid))) | |
6065 | && need_for_split_p (potential_reload_hard_regs, regno + i) | |
6027ea4c | 6066 | && split_reg (before_p, regno + i, insn, next_usage_insns, NULL)) |
55a2c322 VM |
6067 | res = true; |
6068 | return res; | |
6069 | } | |
6070 | ||
8a8330b7 VM |
6071 | /* Return TRUE if rtx X is considered as an invariant for |
6072 | inheritance. */ | |
6073 | static bool | |
6074 | invariant_p (const_rtx x) | |
6075 | { | |
6076 | machine_mode mode; | |
6077 | const char *fmt; | |
6078 | enum rtx_code code; | |
6079 | int i, j; | |
6080 | ||
850b8aa3 SB |
6081 | if (side_effects_p (x)) |
6082 | return false; | |
6083 | ||
8a8330b7 VM |
6084 | code = GET_CODE (x); |
6085 | mode = GET_MODE (x); | |
6086 | if (code == SUBREG) | |
6087 | { | |
6088 | x = SUBREG_REG (x); | |
6089 | code = GET_CODE (x); | |
bd5a2c67 | 6090 | mode = wider_subreg_mode (mode, GET_MODE (x)); |
8a8330b7 VM |
6091 | } |
6092 | ||
6093 | if (MEM_P (x)) | |
6094 | return false; | |
6095 | ||
6096 | if (REG_P (x)) | |
6097 | { | |
6098 | int i, nregs, regno = REGNO (x); | |
6099 | ||
6100 | if (regno >= FIRST_PSEUDO_REGISTER || regno == STACK_POINTER_REGNUM | |
6101 | || TEST_HARD_REG_BIT (eliminable_regset, regno) | |
6102 | || GET_MODE_CLASS (GET_MODE (x)) == MODE_CC) | |
6103 | return false; | |
ad474626 | 6104 | nregs = hard_regno_nregs (regno, mode); |
8a8330b7 VM |
6105 | for (i = 0; i < nregs; i++) |
6106 | if (! fixed_regs[regno + i] | |
6107 | /* A hard register may be clobbered in the current insn | |
6108 | but we can ignore this case because if the hard | |
6109 | register is used it should be set somewhere after the | |
6110 | clobber. */ | |
6111 | || bitmap_bit_p (&invalid_invariant_regs, regno + i)) | |
6112 | return false; | |
6113 | } | |
6114 | fmt = GET_RTX_FORMAT (code); | |
6115 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
6116 | { | |
6117 | if (fmt[i] == 'e') | |
6118 | { | |
6119 | if (! invariant_p (XEXP (x, i))) | |
6120 | return false; | |
6121 | } | |
6122 | else if (fmt[i] == 'E') | |
6123 | { | |
6124 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
6125 | if (! invariant_p (XVECEXP (x, i, j))) | |
6126 | return false; | |
6127 | } | |
6128 | } | |
6129 | return true; | |
6130 | } | |
6131 | ||
6132 | /* We have 'dest_reg <- invariant'. Let us try to make an invariant | |
6133 | inheritance transformation (using dest_reg instead invariant in a | |
6134 | subsequent insn). */ | |
6135 | static bool | |
6136 | process_invariant_for_inheritance (rtx dst_reg, rtx invariant_rtx) | |
6137 | { | |
6138 | invariant_ptr_t invariant_ptr; | |
6139 | rtx_insn *insn, *new_insns; | |
6140 | rtx insn_set, insn_reg, new_reg; | |
6141 | int insn_regno; | |
6142 | bool succ_p = false; | |
6143 | int dst_regno = REGNO (dst_reg); | |
b8506a8a | 6144 | machine_mode dst_mode = GET_MODE (dst_reg); |
8a8330b7 VM |
6145 | enum reg_class cl = lra_get_allocno_class (dst_regno), insn_reg_cl; |
6146 | ||
6147 | invariant_ptr = insert_invariant (invariant_rtx); | |
6148 | if ((insn = invariant_ptr->insn) != NULL_RTX) | |
6149 | { | |
6150 | /* We have a subsequent insn using the invariant. */ | |
6151 | insn_set = single_set (insn); | |
6152 | lra_assert (insn_set != NULL); | |
6153 | insn_reg = SET_DEST (insn_set); | |
6154 | lra_assert (REG_P (insn_reg)); | |
6155 | insn_regno = REGNO (insn_reg); | |
6156 | insn_reg_cl = lra_get_allocno_class (insn_regno); | |
6157 | ||
6158 | if (dst_mode == GET_MODE (insn_reg) | |
6159 | /* We should consider only result move reg insns which are | |
6160 | cheap. */ | |
6161 | && targetm.register_move_cost (dst_mode, cl, insn_reg_cl) == 2 | |
6162 | && targetm.register_move_cost (dst_mode, cl, cl) == 2) | |
6163 | { | |
6164 | if (lra_dump_file != NULL) | |
6165 | fprintf (lra_dump_file, | |
6166 | " [[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[\n"); | |
6167 | new_reg = lra_create_new_reg (dst_mode, dst_reg, | |
6168 | cl, "invariant inheritance"); | |
6169 | bitmap_set_bit (&lra_inheritance_pseudos, REGNO (new_reg)); | |
6170 | bitmap_set_bit (&check_only_regs, REGNO (new_reg)); | |
b10d44ef | 6171 | lra_reg_info[REGNO (new_reg)].restore_rtx = PATTERN (insn); |
8a8330b7 VM |
6172 | start_sequence (); |
6173 | lra_emit_move (new_reg, dst_reg); | |
6174 | new_insns = get_insns (); | |
6175 | end_sequence (); | |
6176 | lra_process_new_insns (curr_insn, NULL, new_insns, | |
6177 | "Add invariant inheritance<-original"); | |
6178 | start_sequence (); | |
6179 | lra_emit_move (SET_DEST (insn_set), new_reg); | |
6180 | new_insns = get_insns (); | |
6181 | end_sequence (); | |
6182 | lra_process_new_insns (insn, NULL, new_insns, | |
6183 | "Changing reload<-inheritance"); | |
6184 | lra_set_insn_deleted (insn); | |
6185 | succ_p = true; | |
6186 | if (lra_dump_file != NULL) | |
6187 | { | |
6188 | fprintf (lra_dump_file, | |
6189 | " Invariant inheritance reuse change %d (bb%d):\n", | |
6190 | REGNO (new_reg), BLOCK_FOR_INSN (insn)->index); | |
6191 | dump_insn_slim (lra_dump_file, insn); | |
6192 | fprintf (lra_dump_file, | |
6193 | " ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]\n"); | |
6194 | } | |
6195 | } | |
6196 | } | |
6197 | invariant_ptr->insn = curr_insn; | |
6198 | return succ_p; | |
6199 | } | |
6200 | ||
55a2c322 VM |
6201 | /* Check only registers living at the current program point in the |
6202 | current EBB. */ | |
6203 | static bitmap_head live_regs; | |
6204 | ||
6205 | /* Update live info in EBB given by its HEAD and TAIL insns after | |
6206 | inheritance/split transformation. The function removes dead moves | |
6207 | too. */ | |
6208 | static void | |
cfa434f6 | 6209 | update_ebb_live_info (rtx_insn *head, rtx_insn *tail) |
55a2c322 VM |
6210 | { |
6211 | unsigned int j; | |
8e9d68a9 | 6212 | int i, regno; |
55a2c322 | 6213 | bool live_p; |
cfa434f6 DM |
6214 | rtx_insn *prev_insn; |
6215 | rtx set; | |
55a2c322 VM |
6216 | bool remove_p; |
6217 | basic_block last_bb, prev_bb, curr_bb; | |
6218 | bitmap_iterator bi; | |
6219 | struct lra_insn_reg *reg; | |
6220 | edge e; | |
6221 | edge_iterator ei; | |
6222 | ||
f4eafc30 | 6223 | last_bb = BLOCK_FOR_INSN (tail); |
55a2c322 VM |
6224 | prev_bb = NULL; |
6225 | for (curr_insn = tail; | |
6226 | curr_insn != PREV_INSN (head); | |
6227 | curr_insn = prev_insn) | |
6228 | { | |
6229 | prev_insn = PREV_INSN (curr_insn); | |
911598e3 VM |
6230 | /* We need to process empty blocks too. They contain |
6231 | NOTE_INSN_BASIC_BLOCK referring for the basic block. */ | |
6232 | if (NOTE_P (curr_insn) && NOTE_KIND (curr_insn) != NOTE_INSN_BASIC_BLOCK) | |
6233 | continue; | |
55a2c322 VM |
6234 | curr_bb = BLOCK_FOR_INSN (curr_insn); |
6235 | if (curr_bb != prev_bb) | |
6236 | { | |
6237 | if (prev_bb != NULL) | |
6238 | { | |
6239 | /* Update df_get_live_in (prev_bb): */ | |
6240 | EXECUTE_IF_SET_IN_BITMAP (&check_only_regs, 0, j, bi) | |
6241 | if (bitmap_bit_p (&live_regs, j)) | |
6242 | bitmap_set_bit (df_get_live_in (prev_bb), j); | |
6243 | else | |
6244 | bitmap_clear_bit (df_get_live_in (prev_bb), j); | |
6245 | } | |
6246 | if (curr_bb != last_bb) | |
6247 | { | |
6248 | /* Update df_get_live_out (curr_bb): */ | |
6249 | EXECUTE_IF_SET_IN_BITMAP (&check_only_regs, 0, j, bi) | |
6250 | { | |
6251 | live_p = bitmap_bit_p (&live_regs, j); | |
6252 | if (! live_p) | |
6253 | FOR_EACH_EDGE (e, ei, curr_bb->succs) | |
6254 | if (bitmap_bit_p (df_get_live_in (e->dest), j)) | |
6255 | { | |
6256 | live_p = true; | |
6257 | break; | |
6258 | } | |
6259 | if (live_p) | |
6260 | bitmap_set_bit (df_get_live_out (curr_bb), j); | |
6261 | else | |
6262 | bitmap_clear_bit (df_get_live_out (curr_bb), j); | |
6263 | } | |
6264 | } | |
6265 | prev_bb = curr_bb; | |
6266 | bitmap_and (&live_regs, &check_only_regs, df_get_live_out (curr_bb)); | |
6267 | } | |
44b94bdb | 6268 | if (! NONDEBUG_INSN_P (curr_insn)) |
55a2c322 VM |
6269 | continue; |
6270 | curr_id = lra_get_insn_recog_data (curr_insn); | |
8e9d68a9 | 6271 | curr_static_id = curr_id->insn_static_data; |
55a2c322 | 6272 | remove_p = false; |
53250f44 BS |
6273 | if ((set = single_set (curr_insn)) != NULL_RTX |
6274 | && REG_P (SET_DEST (set)) | |
55a2c322 | 6275 | && (regno = REGNO (SET_DEST (set))) >= FIRST_PSEUDO_REGISTER |
53250f44 | 6276 | && SET_DEST (set) != pic_offset_table_rtx |
55a2c322 VM |
6277 | && bitmap_bit_p (&check_only_regs, regno) |
6278 | && ! bitmap_bit_p (&live_regs, regno)) | |
6279 | remove_p = true; | |
6280 | /* See which defined values die here. */ | |
6281 | for (reg = curr_id->regs; reg != NULL; reg = reg->next) | |
6282 | if (reg->type == OP_OUT && ! reg->subreg_p) | |
6283 | bitmap_clear_bit (&live_regs, reg->regno); | |
8e9d68a9 VM |
6284 | for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next) |
6285 | if (reg->type == OP_OUT && ! reg->subreg_p) | |
6286 | bitmap_clear_bit (&live_regs, reg->regno); | |
9d86e84e VM |
6287 | if (curr_id->arg_hard_regs != NULL) |
6288 | /* Make clobbered argument hard registers die. */ | |
6289 | for (i = 0; (regno = curr_id->arg_hard_regs[i]) >= 0; i++) | |
6290 | if (regno >= FIRST_PSEUDO_REGISTER) | |
6291 | bitmap_clear_bit (&live_regs, regno - FIRST_PSEUDO_REGISTER); | |
55a2c322 VM |
6292 | /* Mark each used value as live. */ |
6293 | for (reg = curr_id->regs; reg != NULL; reg = reg->next) | |
d89ae27c | 6294 | if (reg->type != OP_OUT |
55a2c322 VM |
6295 | && bitmap_bit_p (&check_only_regs, reg->regno)) |
6296 | bitmap_set_bit (&live_regs, reg->regno); | |
8e9d68a9 VM |
6297 | for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next) |
6298 | if (reg->type != OP_OUT | |
6299 | && bitmap_bit_p (&check_only_regs, reg->regno)) | |
6300 | bitmap_set_bit (&live_regs, reg->regno); | |
6301 | if (curr_id->arg_hard_regs != NULL) | |
9d86e84e | 6302 | /* Make used argument hard registers live. */ |
8e9d68a9 | 6303 | for (i = 0; (regno = curr_id->arg_hard_regs[i]) >= 0; i++) |
9d86e84e VM |
6304 | if (regno < FIRST_PSEUDO_REGISTER |
6305 | && bitmap_bit_p (&check_only_regs, regno)) | |
8e9d68a9 | 6306 | bitmap_set_bit (&live_regs, regno); |
55a2c322 VM |
6307 | /* It is quite important to remove dead move insns because it |
6308 | means removing dead store. We don't need to process them for | |
6309 | constraints. */ | |
6310 | if (remove_p) | |
6311 | { | |
6312 | if (lra_dump_file != NULL) | |
6313 | { | |
6314 | fprintf (lra_dump_file, " Removing dead insn:\n "); | |
cfbeaedf | 6315 | dump_insn_slim (lra_dump_file, curr_insn); |
55a2c322 VM |
6316 | } |
6317 | lra_set_insn_deleted (curr_insn); | |
6318 | } | |
6319 | } | |
6320 | } | |
6321 | ||
6322 | /* The structure describes info to do an inheritance for the current | |
6323 | insn. We need to collect such info first before doing the | |
6324 | transformations because the transformations change the insn | |
6325 | internal representation. */ | |
6326 | struct to_inherit | |
6327 | { | |
6328 | /* Original regno. */ | |
6329 | int regno; | |
6330 | /* Subsequent insns which can inherit original reg value. */ | |
6331 | rtx insns; | |
6332 | }; | |
6333 | ||
6334 | /* Array containing all info for doing inheritance from the current | |
6335 | insn. */ | |
6336 | static struct to_inherit to_inherit[LRA_MAX_INSN_RELOADS]; | |
6337 | ||
6338 | /* Number elements in the previous array. */ | |
6339 | static int to_inherit_num; | |
6340 | ||
6341 | /* Add inheritance info REGNO and INSNS. Their meaning is described in | |
6342 | structure to_inherit. */ | |
6343 | static void | |
6344 | add_to_inherit (int regno, rtx insns) | |
6345 | { | |
6346 | int i; | |
6347 | ||
6348 | for (i = 0; i < to_inherit_num; i++) | |
6349 | if (to_inherit[i].regno == regno) | |
6350 | return; | |
6351 | lra_assert (to_inherit_num < LRA_MAX_INSN_RELOADS); | |
6352 | to_inherit[to_inherit_num].regno = regno; | |
6353 | to_inherit[to_inherit_num++].insns = insns; | |
6354 | } | |
6355 | ||
6356 | /* Return the last non-debug insn in basic block BB, or the block begin | |
6357 | note if none. */ | |
cfa434f6 | 6358 | static rtx_insn * |
55a2c322 VM |
6359 | get_last_insertion_point (basic_block bb) |
6360 | { | |
cfa434f6 | 6361 | rtx_insn *insn; |
55a2c322 VM |
6362 | |
6363 | FOR_BB_INSNS_REVERSE (bb, insn) | |
6364 | if (NONDEBUG_INSN_P (insn) || NOTE_INSN_BASIC_BLOCK_P (insn)) | |
6365 | return insn; | |
6366 | gcc_unreachable (); | |
6367 | } | |
6368 | ||
6369 | /* Set up RES by registers living on edges FROM except the edge (FROM, | |
6370 | TO) or by registers set up in a jump insn in BB FROM. */ | |
6371 | static void | |
6372 | get_live_on_other_edges (basic_block from, basic_block to, bitmap res) | |
6373 | { | |
cfa434f6 | 6374 | rtx_insn *last; |
55a2c322 VM |
6375 | struct lra_insn_reg *reg; |
6376 | edge e; | |
6377 | edge_iterator ei; | |
6378 | ||
6379 | lra_assert (to != NULL); | |
6380 | bitmap_clear (res); | |
6381 | FOR_EACH_EDGE (e, ei, from->succs) | |
6382 | if (e->dest != to) | |
6383 | bitmap_ior_into (res, df_get_live_in (e->dest)); | |
6384 | last = get_last_insertion_point (from); | |
6385 | if (! JUMP_P (last)) | |
6386 | return; | |
6387 | curr_id = lra_get_insn_recog_data (last); | |
6388 | for (reg = curr_id->regs; reg != NULL; reg = reg->next) | |
6389 | if (reg->type != OP_IN) | |
6390 | bitmap_set_bit (res, reg->regno); | |
6391 | } | |
f4eafc30 | 6392 | |
55a2c322 VM |
6393 | /* Used as a temporary results of some bitmap calculations. */ |
6394 | static bitmap_head temp_bitmap; | |
6395 | ||
8e9d68a9 VM |
6396 | /* We split for reloads of small class of hard regs. The following |
6397 | defines how many hard regs the class should have to be qualified as | |
6398 | small. The code is mostly oriented to x86/x86-64 architecture | |
6399 | where some insns need to use only specific register or pair of | |
6400 | registers and these register can live in RTL explicitly, e.g. for | |
6401 | parameter passing. */ | |
6402 | static const int max_small_class_regs_num = 2; | |
6403 | ||
55a2c322 VM |
6404 | /* Do inheritance/split transformations in EBB starting with HEAD and |
6405 | finishing on TAIL. We process EBB insns in the reverse order. | |
6406 | Return true if we did any inheritance/split transformation in the | |
6407 | EBB. | |
6408 | ||
6409 | We should avoid excessive splitting which results in worse code | |
6410 | because of inaccurate cost calculations for spilling new split | |
6411 | pseudos in such case. To achieve this we do splitting only if | |
6412 | register pressure is high in given basic block and there are reload | |
6413 | pseudos requiring hard registers. We could do more register | |
6414 | pressure calculations at any given program point to avoid necessary | |
6415 | splitting even more but it is to expensive and the current approach | |
6416 | works well enough. */ | |
6417 | static bool | |
cfa434f6 | 6418 | inherit_in_ebb (rtx_insn *head, rtx_insn *tail) |
55a2c322 VM |
6419 | { |
6420 | int i, src_regno, dst_regno, nregs; | |
df2980be | 6421 | bool change_p, succ_p, update_reloads_num_p; |
cfa434f6 | 6422 | rtx_insn *prev_insn, *last_insn; |
8a8330b7 | 6423 | rtx next_usage_insns, curr_set; |
55a2c322 VM |
6424 | enum reg_class cl; |
6425 | struct lra_insn_reg *reg; | |
6426 | basic_block last_processed_bb, curr_bb = NULL; | |
6427 | HARD_REG_SET potential_reload_hard_regs, live_hard_regs; | |
6428 | bitmap to_process; | |
6429 | unsigned int j; | |
6430 | bitmap_iterator bi; | |
6431 | bool head_p, after_p; | |
6432 | ||
6433 | change_p = false; | |
6434 | curr_usage_insns_check++; | |
8a8330b7 | 6435 | clear_invariants (); |
55a2c322 | 6436 | reloads_num = calls_num = 0; |
a1e6ee38 RS |
6437 | for (unsigned int i = 0; i < NUM_ABI_IDS; ++i) |
6438 | last_call_for_abi[i] = 0; | |
6439 | CLEAR_HARD_REG_SET (full_and_partial_call_clobbers); | |
55a2c322 | 6440 | bitmap_clear (&check_only_regs); |
8a8330b7 | 6441 | bitmap_clear (&invalid_invariant_regs); |
55a2c322 VM |
6442 | last_processed_bb = NULL; |
6443 | CLEAR_HARD_REG_SET (potential_reload_hard_regs); | |
44942965 | 6444 | live_hard_regs = eliminable_regset | lra_no_alloc_regs; |
55a2c322 VM |
6445 | /* We don't process new insns generated in the loop. */ |
6446 | for (curr_insn = tail; curr_insn != PREV_INSN (head); curr_insn = prev_insn) | |
6447 | { | |
6448 | prev_insn = PREV_INSN (curr_insn); | |
6449 | if (BLOCK_FOR_INSN (curr_insn) != NULL) | |
6450 | curr_bb = BLOCK_FOR_INSN (curr_insn); | |
6451 | if (last_processed_bb != curr_bb) | |
6452 | { | |
6453 | /* We are at the end of BB. Add qualified living | |
6454 | pseudos for potential splitting. */ | |
6455 | to_process = df_get_live_out (curr_bb); | |
6456 | if (last_processed_bb != NULL) | |
f4eafc30 | 6457 | { |
55a2c322 VM |
6458 | /* We are somewhere in the middle of EBB. */ |
6459 | get_live_on_other_edges (curr_bb, last_processed_bb, | |
6460 | &temp_bitmap); | |
6461 | to_process = &temp_bitmap; | |
6462 | } | |
6463 | last_processed_bb = curr_bb; | |
6464 | last_insn = get_last_insertion_point (curr_bb); | |
6465 | after_p = (! JUMP_P (last_insn) | |
6466 | && (! CALL_P (last_insn) | |
6467 | || (find_reg_note (last_insn, | |
6468 | REG_NORETURN, NULL_RTX) == NULL_RTX | |
6469 | && ! SIBLING_CALL_P (last_insn)))); | |
55a2c322 VM |
6470 | CLEAR_HARD_REG_SET (potential_reload_hard_regs); |
6471 | EXECUTE_IF_SET_IN_BITMAP (to_process, 0, j, bi) | |
6472 | { | |
6473 | if ((int) j >= lra_constraint_new_regno_start) | |
6474 | break; | |
6475 | if (j < FIRST_PSEUDO_REGISTER || reg_renumber[j] >= 0) | |
6476 | { | |
6477 | if (j < FIRST_PSEUDO_REGISTER) | |
6478 | SET_HARD_REG_BIT (live_hard_regs, j); | |
6479 | else | |
6480 | add_to_hard_reg_set (&live_hard_regs, | |
6481 | PSEUDO_REGNO_MODE (j), | |
6482 | reg_renumber[j]); | |
6483 | setup_next_usage_insn (j, last_insn, reloads_num, after_p); | |
6484 | } | |
6485 | } | |
6486 | } | |
6487 | src_regno = dst_regno = -1; | |
8a8330b7 VM |
6488 | curr_set = single_set (curr_insn); |
6489 | if (curr_set != NULL_RTX && REG_P (SET_DEST (curr_set))) | |
6490 | dst_regno = REGNO (SET_DEST (curr_set)); | |
6491 | if (curr_set != NULL_RTX && REG_P (SET_SRC (curr_set))) | |
6492 | src_regno = REGNO (SET_SRC (curr_set)); | |
df2980be | 6493 | update_reloads_num_p = true; |
55a2c322 VM |
6494 | if (src_regno < lra_constraint_new_regno_start |
6495 | && src_regno >= FIRST_PSEUDO_REGISTER | |
6496 | && reg_renumber[src_regno] < 0 | |
6497 | && dst_regno >= lra_constraint_new_regno_start | |
6498 | && (cl = lra_get_allocno_class (dst_regno)) != NO_REGS) | |
6499 | { | |
6500 | /* 'reload_pseudo <- original_pseudo'. */ | |
8e9d68a9 VM |
6501 | if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num) |
6502 | reloads_num++; | |
df2980be | 6503 | update_reloads_num_p = false; |
55a2c322 VM |
6504 | succ_p = false; |
6505 | if (usage_insns[src_regno].check == curr_usage_insns_check | |
6506 | && (next_usage_insns = usage_insns[src_regno].insns) != NULL_RTX) | |
6507 | succ_p = inherit_reload_reg (false, src_regno, cl, | |
6508 | curr_insn, next_usage_insns); | |
6509 | if (succ_p) | |
6510 | change_p = true; | |
6511 | else | |
6512 | setup_next_usage_insn (src_regno, curr_insn, reloads_num, false); | |
6513 | if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs)) | |
44942965 | 6514 | potential_reload_hard_regs |= reg_class_contents[cl]; |
55a2c322 | 6515 | } |
8a8330b7 VM |
6516 | else if (src_regno < 0 |
6517 | && dst_regno >= lra_constraint_new_regno_start | |
6518 | && invariant_p (SET_SRC (curr_set)) | |
6519 | && (cl = lra_get_allocno_class (dst_regno)) != NO_REGS | |
f7abdf36 VM |
6520 | && ! bitmap_bit_p (&invalid_invariant_regs, dst_regno) |
6521 | && ! bitmap_bit_p (&invalid_invariant_regs, | |
6522 | ORIGINAL_REGNO(regno_reg_rtx[dst_regno]))) | |
8a8330b7 VM |
6523 | { |
6524 | /* 'reload_pseudo <- invariant'. */ | |
6525 | if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num) | |
6526 | reloads_num++; | |
6527 | update_reloads_num_p = false; | |
6528 | if (process_invariant_for_inheritance (SET_DEST (curr_set), SET_SRC (curr_set))) | |
6529 | change_p = true; | |
6530 | if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs)) | |
44942965 | 6531 | potential_reload_hard_regs |= reg_class_contents[cl]; |
8a8330b7 | 6532 | } |
55a2c322 VM |
6533 | else if (src_regno >= lra_constraint_new_regno_start |
6534 | && dst_regno < lra_constraint_new_regno_start | |
6535 | && dst_regno >= FIRST_PSEUDO_REGISTER | |
6536 | && reg_renumber[dst_regno] < 0 | |
6537 | && (cl = lra_get_allocno_class (src_regno)) != NO_REGS | |
6538 | && usage_insns[dst_regno].check == curr_usage_insns_check | |
6539 | && (next_usage_insns | |
6540 | = usage_insns[dst_regno].insns) != NULL_RTX) | |
6541 | { | |
8e9d68a9 VM |
6542 | if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num) |
6543 | reloads_num++; | |
df2980be | 6544 | update_reloads_num_p = false; |
55a2c322 VM |
6545 | /* 'original_pseudo <- reload_pseudo'. */ |
6546 | if (! JUMP_P (curr_insn) | |
6547 | && inherit_reload_reg (true, dst_regno, cl, | |
6548 | curr_insn, next_usage_insns)) | |
6549 | change_p = true; | |
6550 | /* Invalidate. */ | |
6551 | usage_insns[dst_regno].check = 0; | |
6552 | if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs)) | |
44942965 | 6553 | potential_reload_hard_regs |= reg_class_contents[cl]; |
55a2c322 VM |
6554 | } |
6555 | else if (INSN_P (curr_insn)) | |
6556 | { | |
2f259720 | 6557 | int iter; |
55a2c322 VM |
6558 | int max_uid = get_max_uid (); |
6559 | ||
6560 | curr_id = lra_get_insn_recog_data (curr_insn); | |
2f259720 | 6561 | curr_static_id = curr_id->insn_static_data; |
55a2c322 VM |
6562 | to_inherit_num = 0; |
6563 | /* Process insn definitions. */ | |
2f259720 VM |
6564 | for (iter = 0; iter < 2; iter++) |
6565 | for (reg = iter == 0 ? curr_id->regs : curr_static_id->hard_regs; | |
6566 | reg != NULL; | |
6567 | reg = reg->next) | |
6568 | if (reg->type != OP_IN | |
6569 | && (dst_regno = reg->regno) < lra_constraint_new_regno_start) | |
6570 | { | |
6571 | if (dst_regno >= FIRST_PSEUDO_REGISTER && reg->type == OP_OUT | |
6572 | && reg_renumber[dst_regno] < 0 && ! reg->subreg_p | |
6573 | && usage_insns[dst_regno].check == curr_usage_insns_check | |
6574 | && (next_usage_insns | |
6575 | = usage_insns[dst_regno].insns) != NULL_RTX) | |
6576 | { | |
6577 | struct lra_insn_reg *r; | |
6578 | ||
6579 | for (r = curr_id->regs; r != NULL; r = r->next) | |
6580 | if (r->type != OP_OUT && r->regno == dst_regno) | |
6581 | break; | |
6582 | /* Don't do inheritance if the pseudo is also | |
6583 | used in the insn. */ | |
6584 | if (r == NULL) | |
67914693 | 6585 | /* We cannot do inheritance right now |
2f259720 VM |
6586 | because the current insn reg info (chain |
6587 | regs) can change after that. */ | |
6588 | add_to_inherit (dst_regno, next_usage_insns); | |
6589 | } | |
67914693 | 6590 | /* We cannot process one reg twice here because of |
2f259720 VM |
6591 | usage_insns invalidation. */ |
6592 | if ((dst_regno < FIRST_PSEUDO_REGISTER | |
6593 | || reg_renumber[dst_regno] >= 0) | |
e32e4c4a | 6594 | && ! reg->subreg_p && reg->type != OP_IN) |
2f259720 VM |
6595 | { |
6596 | HARD_REG_SET s; | |
6597 | ||
6598 | if (split_if_necessary (dst_regno, reg->biggest_mode, | |
6599 | potential_reload_hard_regs, | |
6600 | false, curr_insn, max_uid)) | |
6601 | change_p = true; | |
6602 | CLEAR_HARD_REG_SET (s); | |
6603 | if (dst_regno < FIRST_PSEUDO_REGISTER) | |
6604 | add_to_hard_reg_set (&s, reg->biggest_mode, dst_regno); | |
6605 | else | |
6606 | add_to_hard_reg_set (&s, PSEUDO_REGNO_MODE (dst_regno), | |
6607 | reg_renumber[dst_regno]); | |
d15e5131 RS |
6608 | live_hard_regs &= ~s; |
6609 | potential_reload_hard_regs &= ~s; | |
2f259720 VM |
6610 | } |
6611 | /* We should invalidate potential inheritance or | |
6612 | splitting for the current insn usages to the next | |
6613 | usage insns (see code below) as the output pseudo | |
6614 | prevents this. */ | |
6615 | if ((dst_regno >= FIRST_PSEUDO_REGISTER | |
6616 | && reg_renumber[dst_regno] < 0) | |
6617 | || (reg->type == OP_OUT && ! reg->subreg_p | |
6618 | && (dst_regno < FIRST_PSEUDO_REGISTER | |
6619 | || reg_renumber[dst_regno] >= 0))) | |
6620 | { | |
6621 | /* Invalidate and mark definitions. */ | |
6622 | if (dst_regno >= FIRST_PSEUDO_REGISTER) | |
6623 | usage_insns[dst_regno].check = -(int) INSN_UID (curr_insn); | |
6624 | else | |
6625 | { | |
ad474626 RS |
6626 | nregs = hard_regno_nregs (dst_regno, |
6627 | reg->biggest_mode); | |
2f259720 VM |
6628 | for (i = 0; i < nregs; i++) |
6629 | usage_insns[dst_regno + i].check | |
6630 | = -(int) INSN_UID (curr_insn); | |
6631 | } | |
6632 | } | |
6633 | } | |
9d86e84e VM |
6634 | /* Process clobbered call regs. */ |
6635 | if (curr_id->arg_hard_regs != NULL) | |
6636 | for (i = 0; (dst_regno = curr_id->arg_hard_regs[i]) >= 0; i++) | |
6637 | if (dst_regno >= FIRST_PSEUDO_REGISTER) | |
6638 | usage_insns[dst_regno - FIRST_PSEUDO_REGISTER].check | |
6639 | = -(int) INSN_UID (curr_insn); | |
55a2c322 VM |
6640 | if (! JUMP_P (curr_insn)) |
6641 | for (i = 0; i < to_inherit_num; i++) | |
6642 | if (inherit_reload_reg (true, to_inherit[i].regno, | |
6643 | ALL_REGS, curr_insn, | |
6644 | to_inherit[i].insns)) | |
6645 | change_p = true; | |
6646 | if (CALL_P (curr_insn)) | |
6647 | { | |
cfa434f6 DM |
6648 | rtx cheap, pat, dest; |
6649 | rtx_insn *restore; | |
55a2c322 VM |
6650 | int regno, hard_regno; |
6651 | ||
6652 | calls_num++; | |
a1e6ee38 RS |
6653 | function_abi callee_abi = insn_callee_abi (curr_insn); |
6654 | last_call_for_abi[callee_abi.id ()] = calls_num; | |
6655 | full_and_partial_call_clobbers | |
6656 | |= callee_abi.full_and_partial_reg_clobbers (); | |
55a2c322 VM |
6657 | if ((cheap = find_reg_note (curr_insn, |
6658 | REG_RETURNED, NULL_RTX)) != NULL_RTX | |
6659 | && ((cheap = XEXP (cheap, 0)), true) | |
6660 | && (regno = REGNO (cheap)) >= FIRST_PSEUDO_REGISTER | |
6661 | && (hard_regno = reg_renumber[regno]) >= 0 | |
851dac7c | 6662 | && usage_insns[regno].check == curr_usage_insns_check |
55a2c322 VM |
6663 | /* If there are pending saves/restores, the |
6664 | optimization is not worth. */ | |
6665 | && usage_insns[regno].calls_num == calls_num - 1 | |
a1e6ee38 | 6666 | && callee_abi.clobbers_reg_p (GET_MODE (cheap), hard_regno)) |
55a2c322 VM |
6667 | { |
6668 | /* Restore the pseudo from the call result as | |
6669 | REG_RETURNED note says that the pseudo value is | |
6670 | in the call result and the pseudo is an argument | |
6671 | of the call. */ | |
6672 | pat = PATTERN (curr_insn); | |
6673 | if (GET_CODE (pat) == PARALLEL) | |
6674 | pat = XVECEXP (pat, 0, 0); | |
6675 | dest = SET_DEST (pat); | |
54bddf1d IE |
6676 | /* For multiple return values dest is PARALLEL. |
6677 | Currently we handle only single return value case. */ | |
6678 | if (REG_P (dest)) | |
6679 | { | |
6680 | start_sequence (); | |
6681 | emit_move_insn (cheap, copy_rtx (dest)); | |
6682 | restore = get_insns (); | |
6683 | end_sequence (); | |
6684 | lra_process_new_insns (curr_insn, NULL, restore, | |
6685 | "Inserting call parameter restore"); | |
6686 | /* We don't need to save/restore of the pseudo from | |
6687 | this call. */ | |
6688 | usage_insns[regno].calls_num = calls_num; | |
a1e6ee38 RS |
6689 | remove_from_hard_reg_set |
6690 | (&full_and_partial_call_clobbers, | |
6691 | GET_MODE (cheap), hard_regno); | |
54bddf1d IE |
6692 | bitmap_set_bit (&check_only_regs, regno); |
6693 | } | |
55a2c322 VM |
6694 | } |
6695 | } | |
6696 | to_inherit_num = 0; | |
6697 | /* Process insn usages. */ | |
2f259720 VM |
6698 | for (iter = 0; iter < 2; iter++) |
6699 | for (reg = iter == 0 ? curr_id->regs : curr_static_id->hard_regs; | |
6700 | reg != NULL; | |
6701 | reg = reg->next) | |
6702 | if ((reg->type != OP_OUT | |
6703 | || (reg->type == OP_OUT && reg->subreg_p)) | |
6704 | && (src_regno = reg->regno) < lra_constraint_new_regno_start) | |
6705 | { | |
6706 | if (src_regno >= FIRST_PSEUDO_REGISTER | |
6707 | && reg_renumber[src_regno] < 0 && reg->type == OP_IN) | |
6708 | { | |
6709 | if (usage_insns[src_regno].check == curr_usage_insns_check | |
6710 | && (next_usage_insns | |
6711 | = usage_insns[src_regno].insns) != NULL_RTX | |
6712 | && NONDEBUG_INSN_P (curr_insn)) | |
6713 | add_to_inherit (src_regno, next_usage_insns); | |
6714 | else if (usage_insns[src_regno].check | |
6715 | != -(int) INSN_UID (curr_insn)) | |
6716 | /* Add usages but only if the reg is not set up | |
6717 | in the same insn. */ | |
6718 | add_next_usage_insn (src_regno, curr_insn, reloads_num); | |
6719 | } | |
6720 | else if (src_regno < FIRST_PSEUDO_REGISTER | |
6721 | || reg_renumber[src_regno] >= 0) | |
6722 | { | |
6723 | bool before_p; | |
e67d1102 | 6724 | rtx_insn *use_insn = curr_insn; |
2f259720 VM |
6725 | |
6726 | before_p = (JUMP_P (curr_insn) | |
6727 | || (CALL_P (curr_insn) && reg->type == OP_IN)); | |
6728 | if (NONDEBUG_INSN_P (curr_insn) | |
8e9d68a9 | 6729 | && (! JUMP_P (curr_insn) || reg->type == OP_IN) |
2f259720 VM |
6730 | && split_if_necessary (src_regno, reg->biggest_mode, |
6731 | potential_reload_hard_regs, | |
6732 | before_p, curr_insn, max_uid)) | |
6733 | { | |
6734 | if (reg->subreg_p) | |
7436a1c6 | 6735 | check_and_force_assignment_correctness_p = true; |
2f259720 | 6736 | change_p = true; |
8e9d68a9 | 6737 | /* Invalidate. */ |
2f259720 VM |
6738 | usage_insns[src_regno].check = 0; |
6739 | if (before_p) | |
6740 | use_insn = PREV_INSN (curr_insn); | |
6741 | } | |
6742 | if (NONDEBUG_INSN_P (curr_insn)) | |
6743 | { | |
6744 | if (src_regno < FIRST_PSEUDO_REGISTER) | |
6745 | add_to_hard_reg_set (&live_hard_regs, | |
6746 | reg->biggest_mode, src_regno); | |
6747 | else | |
6748 | add_to_hard_reg_set (&live_hard_regs, | |
6749 | PSEUDO_REGNO_MODE (src_regno), | |
6750 | reg_renumber[src_regno]); | |
6751 | } | |
16ba97b9 VM |
6752 | if (src_regno >= FIRST_PSEUDO_REGISTER) |
6753 | add_next_usage_insn (src_regno, use_insn, reloads_num); | |
6754 | else | |
6755 | { | |
6756 | for (i = 0; i < hard_regno_nregs (src_regno, reg->biggest_mode); i++) | |
6757 | add_next_usage_insn (src_regno + i, use_insn, reloads_num); | |
6758 | } | |
2f259720 VM |
6759 | } |
6760 | } | |
9d86e84e | 6761 | /* Process used call regs. */ |
df2980be VM |
6762 | if (curr_id->arg_hard_regs != NULL) |
6763 | for (i = 0; (src_regno = curr_id->arg_hard_regs[i]) >= 0; i++) | |
6764 | if (src_regno < FIRST_PSEUDO_REGISTER) | |
6765 | { | |
6766 | SET_HARD_REG_BIT (live_hard_regs, src_regno); | |
6767 | add_next_usage_insn (src_regno, curr_insn, reloads_num); | |
6768 | } | |
55a2c322 VM |
6769 | for (i = 0; i < to_inherit_num; i++) |
6770 | { | |
6771 | src_regno = to_inherit[i].regno; | |
6772 | if (inherit_reload_reg (false, src_regno, ALL_REGS, | |
6773 | curr_insn, to_inherit[i].insns)) | |
6774 | change_p = true; | |
6775 | else | |
6776 | setup_next_usage_insn (src_regno, curr_insn, reloads_num, false); | |
6777 | } | |
6778 | } | |
df2980be | 6779 | if (update_reloads_num_p |
8a8330b7 | 6780 | && NONDEBUG_INSN_P (curr_insn) && curr_set != NULL_RTX) |
df2980be VM |
6781 | { |
6782 | int regno = -1; | |
8a8330b7 VM |
6783 | if ((REG_P (SET_DEST (curr_set)) |
6784 | && (regno = REGNO (SET_DEST (curr_set))) >= lra_constraint_new_regno_start | |
df2980be VM |
6785 | && reg_renumber[regno] < 0 |
6786 | && (cl = lra_get_allocno_class (regno)) != NO_REGS) | |
8a8330b7 VM |
6787 | || (REG_P (SET_SRC (curr_set)) |
6788 | && (regno = REGNO (SET_SRC (curr_set))) >= lra_constraint_new_regno_start | |
df2980be VM |
6789 | && reg_renumber[regno] < 0 |
6790 | && (cl = lra_get_allocno_class (regno)) != NO_REGS)) | |
6791 | { | |
8e9d68a9 VM |
6792 | if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num) |
6793 | reloads_num++; | |
df2980be | 6794 | if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs)) |
44942965 | 6795 | potential_reload_hard_regs |= reg_class_contents[cl]; |
df2980be VM |
6796 | } |
6797 | } | |
8a8330b7 VM |
6798 | if (NONDEBUG_INSN_P (curr_insn)) |
6799 | { | |
6800 | int regno; | |
6801 | ||
6802 | /* Invalidate invariants with changed regs. */ | |
6803 | curr_id = lra_get_insn_recog_data (curr_insn); | |
6804 | for (reg = curr_id->regs; reg != NULL; reg = reg->next) | |
6805 | if (reg->type != OP_IN) | |
f7abdf36 VM |
6806 | { |
6807 | bitmap_set_bit (&invalid_invariant_regs, reg->regno); | |
6808 | bitmap_set_bit (&invalid_invariant_regs, | |
6809 | ORIGINAL_REGNO (regno_reg_rtx[reg->regno])); | |
6810 | } | |
8a8330b7 VM |
6811 | curr_static_id = curr_id->insn_static_data; |
6812 | for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next) | |
6813 | if (reg->type != OP_IN) | |
6814 | bitmap_set_bit (&invalid_invariant_regs, reg->regno); | |
6815 | if (curr_id->arg_hard_regs != NULL) | |
6816 | for (i = 0; (regno = curr_id->arg_hard_regs[i]) >= 0; i++) | |
f7abdf36 | 6817 | if (regno >= FIRST_PSEUDO_REGISTER) |
8a8330b7 | 6818 | bitmap_set_bit (&invalid_invariant_regs, |
f7abdf36 | 6819 | regno - FIRST_PSEUDO_REGISTER); |
8a8330b7 | 6820 | } |
55a2c322 VM |
6821 | /* We reached the start of the current basic block. */ |
6822 | if (prev_insn == NULL_RTX || prev_insn == PREV_INSN (head) | |
6823 | || BLOCK_FOR_INSN (prev_insn) != curr_bb) | |
6824 | { | |
6825 | /* We reached the beginning of the current block -- do | |
6826 | rest of spliting in the current BB. */ | |
6827 | to_process = df_get_live_in (curr_bb); | |
6828 | if (BLOCK_FOR_INSN (head) != curr_bb) | |
f4eafc30 | 6829 | { |
55a2c322 VM |
6830 | /* We are somewhere in the middle of EBB. */ |
6831 | get_live_on_other_edges (EDGE_PRED (curr_bb, 0)->src, | |
6832 | curr_bb, &temp_bitmap); | |
6833 | to_process = &temp_bitmap; | |
6834 | } | |
6835 | head_p = true; | |
6836 | EXECUTE_IF_SET_IN_BITMAP (to_process, 0, j, bi) | |
6837 | { | |
6838 | if ((int) j >= lra_constraint_new_regno_start) | |
6839 | break; | |
6840 | if (((int) j < FIRST_PSEUDO_REGISTER || reg_renumber[j] >= 0) | |
6841 | && usage_insns[j].check == curr_usage_insns_check | |
6842 | && (next_usage_insns = usage_insns[j].insns) != NULL_RTX) | |
6843 | { | |
6844 | if (need_for_split_p (potential_reload_hard_regs, j)) | |
6845 | { | |
6846 | if (lra_dump_file != NULL && head_p) | |
6847 | { | |
6848 | fprintf (lra_dump_file, | |
6849 | " ----------------------------------\n"); | |
6850 | head_p = false; | |
6851 | } | |
6852 | if (split_reg (false, j, bb_note (curr_bb), | |
6027ea4c | 6853 | next_usage_insns, NULL)) |
55a2c322 VM |
6854 | change_p = true; |
6855 | } | |
6856 | usage_insns[j].check = 0; | |
6857 | } | |
6858 | } | |
6859 | } | |
6860 | } | |
6861 | return change_p; | |
6862 | } | |
6863 | ||
6864 | /* This value affects EBB forming. If probability of edge from EBB to | |
6865 | a BB is not greater than the following value, we don't add the BB | |
f4eafc30 | 6866 | to EBB. */ |
fb8a0e40 | 6867 | #define EBB_PROBABILITY_CUTOFF \ |
028d4092 | 6868 | ((REG_BR_PROB_BASE * param_lra_inheritance_ebb_probability_cutoff) / 100) |
55a2c322 VM |
6869 | |
6870 | /* Current number of inheritance/split iteration. */ | |
6871 | int lra_inheritance_iter; | |
6872 | ||
6873 | /* Entry function for inheritance/split pass. */ | |
6874 | void | |
6875 | lra_inheritance (void) | |
6876 | { | |
6877 | int i; | |
6878 | basic_block bb, start_bb; | |
6879 | edge e; | |
6880 | ||
55a2c322 | 6881 | lra_inheritance_iter++; |
8e3a4869 | 6882 | if (lra_inheritance_iter > LRA_MAX_INHERITANCE_PASSES) |
e731262b VM |
6883 | return; |
6884 | timevar_push (TV_LRA_INHERITANCE); | |
55a2c322 VM |
6885 | if (lra_dump_file != NULL) |
6886 | fprintf (lra_dump_file, "\n********** Inheritance #%d: **********\n\n", | |
6887 | lra_inheritance_iter); | |
6888 | curr_usage_insns_check = 0; | |
6889 | usage_insns = XNEWVEC (struct usage_insns, lra_constraint_new_regno_start); | |
6890 | for (i = 0; i < lra_constraint_new_regno_start; i++) | |
6891 | usage_insns[i].check = 0; | |
6892 | bitmap_initialize (&check_only_regs, ®_obstack); | |
8a8330b7 | 6893 | bitmap_initialize (&invalid_invariant_regs, ®_obstack); |
55a2c322 VM |
6894 | bitmap_initialize (&live_regs, ®_obstack); |
6895 | bitmap_initialize (&temp_bitmap, ®_obstack); | |
6896 | bitmap_initialize (&ebb_global_regs, ®_obstack); | |
11cd3bed | 6897 | FOR_EACH_BB_FN (bb, cfun) |
55a2c322 VM |
6898 | { |
6899 | start_bb = bb; | |
6900 | if (lra_dump_file != NULL) | |
6901 | fprintf (lra_dump_file, "EBB"); | |
6902 | /* Form a EBB starting with BB. */ | |
6903 | bitmap_clear (&ebb_global_regs); | |
6904 | bitmap_ior_into (&ebb_global_regs, df_get_live_in (bb)); | |
6905 | for (;;) | |
6906 | { | |
6907 | if (lra_dump_file != NULL) | |
6908 | fprintf (lra_dump_file, " %d", bb->index); | |
fefa31b5 DM |
6909 | if (bb->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun) |
6910 | || LABEL_P (BB_HEAD (bb->next_bb))) | |
55a2c322 VM |
6911 | break; |
6912 | e = find_fallthru_edge (bb->succs); | |
6913 | if (! e) | |
6914 | break; | |
357067f2 JH |
6915 | if (e->probability.initialized_p () |
6916 | && e->probability.to_reg_br_prob_base () < EBB_PROBABILITY_CUTOFF) | |
55a2c322 VM |
6917 | break; |
6918 | bb = bb->next_bb; | |
6919 | } | |
6920 | bitmap_ior_into (&ebb_global_regs, df_get_live_out (bb)); | |
6921 | if (lra_dump_file != NULL) | |
6922 | fprintf (lra_dump_file, "\n"); | |
6923 | if (inherit_in_ebb (BB_HEAD (start_bb), BB_END (bb))) | |
6924 | /* Remember that the EBB head and tail can change in | |
6925 | inherit_in_ebb. */ | |
6926 | update_ebb_live_info (BB_HEAD (start_bb), BB_END (bb)); | |
6927 | } | |
1c252ef3 RB |
6928 | bitmap_release (&ebb_global_regs); |
6929 | bitmap_release (&temp_bitmap); | |
6930 | bitmap_release (&live_regs); | |
6931 | bitmap_release (&invalid_invariant_regs); | |
6932 | bitmap_release (&check_only_regs); | |
55a2c322 VM |
6933 | free (usage_insns); |
6934 | ||
6935 | timevar_pop (TV_LRA_INHERITANCE); | |
6936 | } | |
6937 | ||
6938 | \f | |
6939 | ||
6940 | /* This page contains code to undo failed inheritance/split | |
6941 | transformations. */ | |
6942 | ||
6943 | /* Current number of iteration undoing inheritance/split. */ | |
6944 | int lra_undo_inheritance_iter; | |
6945 | ||
6946 | /* Fix BB live info LIVE after removing pseudos created on pass doing | |
6947 | inheritance/split which are REMOVED_PSEUDOS. */ | |
6948 | static void | |
6949 | fix_bb_live_info (bitmap live, bitmap removed_pseudos) | |
6950 | { | |
6951 | unsigned int regno; | |
6952 | bitmap_iterator bi; | |
6953 | ||
6954 | EXECUTE_IF_SET_IN_BITMAP (removed_pseudos, 0, regno, bi) | |
8a8330b7 VM |
6955 | if (bitmap_clear_bit (live, regno) |
6956 | && REG_P (lra_reg_info[regno].restore_rtx)) | |
6957 | bitmap_set_bit (live, REGNO (lra_reg_info[regno].restore_rtx)); | |
55a2c322 VM |
6958 | } |
6959 | ||
6960 | /* Return regno of the (subreg of) REG. Otherwise, return a negative | |
6961 | number. */ | |
6962 | static int | |
6963 | get_regno (rtx reg) | |
6964 | { | |
6965 | if (GET_CODE (reg) == SUBREG) | |
6966 | reg = SUBREG_REG (reg); | |
6967 | if (REG_P (reg)) | |
6968 | return REGNO (reg); | |
6969 | return -1; | |
6970 | } | |
6971 | ||
cefe08a4 VM |
6972 | /* Delete a move INSN with destination reg DREGNO and a previous |
6973 | clobber insn with the same regno. The inheritance/split code can | |
6974 | generate moves with preceding clobber and when we delete such moves | |
6975 | we should delete the clobber insn too to keep the correct life | |
6976 | info. */ | |
6977 | static void | |
6978 | delete_move_and_clobber (rtx_insn *insn, int dregno) | |
6979 | { | |
6980 | rtx_insn *prev_insn = PREV_INSN (insn); | |
6981 | ||
6982 | lra_set_insn_deleted (insn); | |
79b57d18 | 6983 | lra_assert (dregno >= 0); |
cefe08a4 VM |
6984 | if (prev_insn != NULL && NONDEBUG_INSN_P (prev_insn) |
6985 | && GET_CODE (PATTERN (prev_insn)) == CLOBBER | |
6986 | && dregno == get_regno (XEXP (PATTERN (prev_insn), 0))) | |
6987 | lra_set_insn_deleted (prev_insn); | |
6988 | } | |
6989 | ||
55a2c322 VM |
6990 | /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and |
6991 | return true if we did any change. The undo transformations for | |
6992 | inheritance looks like | |
6993 | i <- i2 | |
6994 | p <- i => p <- i2 | |
6995 | or removing | |
6996 | p <- i, i <- p, and i <- i3 | |
6997 | where p is original pseudo from which inheritance pseudo i was | |
6998 | created, i and i3 are removed inheritance pseudos, i2 is another | |
6999 | not removed inheritance pseudo. All split pseudos or other | |
7000 | occurrences of removed inheritance pseudos are changed on the | |
7001 | corresponding original pseudos. | |
7002 | ||
7003 | The function also schedules insns changed and created during | |
7004 | inheritance/split pass for processing by the subsequent constraint | |
7005 | pass. */ | |
7006 | static bool | |
7007 | remove_inheritance_pseudos (bitmap remove_pseudos) | |
7008 | { | |
7009 | basic_block bb; | |
8a8330b7 VM |
7010 | int regno, sregno, prev_sregno, dregno; |
7011 | rtx restore_rtx; | |
cfa434f6 DM |
7012 | rtx set, prev_set; |
7013 | rtx_insn *prev_insn; | |
55a2c322 VM |
7014 | bool change_p, done_p; |
7015 | ||
7016 | change_p = ! bitmap_empty_p (remove_pseudos); | |
67914693 | 7017 | /* We cannot finish the function right away if CHANGE_P is true |
55a2c322 VM |
7018 | because we need to marks insns affected by previous |
7019 | inheritance/split pass for processing by the subsequent | |
7020 | constraint pass. */ | |
11cd3bed | 7021 | FOR_EACH_BB_FN (bb, cfun) |
55a2c322 VM |
7022 | { |
7023 | fix_bb_live_info (df_get_live_in (bb), remove_pseudos); | |
7024 | fix_bb_live_info (df_get_live_out (bb), remove_pseudos); | |
7025 | FOR_BB_INSNS_REVERSE (bb, curr_insn) | |
7026 | { | |
7027 | if (! INSN_P (curr_insn)) | |
7028 | continue; | |
7029 | done_p = false; | |
7030 | sregno = dregno = -1; | |
7031 | if (change_p && NONDEBUG_INSN_P (curr_insn) | |
7032 | && (set = single_set (curr_insn)) != NULL_RTX) | |
7033 | { | |
7034 | dregno = get_regno (SET_DEST (set)); | |
7035 | sregno = get_regno (SET_SRC (set)); | |
7036 | } | |
f4eafc30 | 7037 | |
55a2c322 VM |
7038 | if (sregno >= 0 && dregno >= 0) |
7039 | { | |
8a8330b7 VM |
7040 | if (bitmap_bit_p (remove_pseudos, dregno) |
7041 | && ! REG_P (lra_reg_info[dregno].restore_rtx)) | |
7042 | { | |
7043 | /* invariant inheritance pseudo <- original pseudo */ | |
7044 | if (lra_dump_file != NULL) | |
7045 | { | |
7046 | fprintf (lra_dump_file, " Removing invariant inheritance:\n"); | |
7047 | dump_insn_slim (lra_dump_file, curr_insn); | |
7048 | fprintf (lra_dump_file, "\n"); | |
7049 | } | |
7050 | delete_move_and_clobber (curr_insn, dregno); | |
7051 | done_p = true; | |
7052 | } | |
7053 | else if (bitmap_bit_p (remove_pseudos, sregno) | |
7054 | && ! REG_P (lra_reg_info[sregno].restore_rtx)) | |
7055 | { | |
7056 | /* reload pseudo <- invariant inheritance pseudo */ | |
7057 | start_sequence (); | |
67914693 | 7058 | /* We cannot just change the source. It might be |
8a8330b7 | 7059 | an insn different from the move. */ |
b10d44ef | 7060 | emit_insn (lra_reg_info[sregno].restore_rtx); |
8a8330b7 VM |
7061 | rtx_insn *new_insns = get_insns (); |
7062 | end_sequence (); | |
b10d44ef VM |
7063 | lra_assert (single_set (new_insns) != NULL |
7064 | && SET_DEST (set) == SET_DEST (single_set (new_insns))); | |
8a8330b7 VM |
7065 | lra_process_new_insns (curr_insn, NULL, new_insns, |
7066 | "Changing reload<-invariant inheritance"); | |
7067 | delete_move_and_clobber (curr_insn, dregno); | |
7068 | done_p = true; | |
7069 | } | |
7070 | else if ((bitmap_bit_p (remove_pseudos, sregno) | |
7071 | && (get_regno (lra_reg_info[sregno].restore_rtx) == dregno | |
7072 | || (bitmap_bit_p (remove_pseudos, dregno) | |
7073 | && get_regno (lra_reg_info[sregno].restore_rtx) >= 0 | |
7074 | && (get_regno (lra_reg_info[sregno].restore_rtx) | |
7075 | == get_regno (lra_reg_info[dregno].restore_rtx))))) | |
55a2c322 | 7076 | || (bitmap_bit_p (remove_pseudos, dregno) |
8a8330b7 | 7077 | && get_regno (lra_reg_info[dregno].restore_rtx) == sregno)) |
55a2c322 VM |
7078 | /* One of the following cases: |
7079 | original <- removed inheritance pseudo | |
7080 | removed inherit pseudo <- another removed inherit pseudo | |
7081 | removed inherit pseudo <- original pseudo | |
7082 | Or | |
7083 | removed_split_pseudo <- original_reg | |
7084 | original_reg <- removed_split_pseudo */ | |
7085 | { | |
7086 | if (lra_dump_file != NULL) | |
7087 | { | |
7088 | fprintf (lra_dump_file, " Removing %s:\n", | |
7089 | bitmap_bit_p (&lra_split_regs, sregno) | |
7090 | || bitmap_bit_p (&lra_split_regs, dregno) | |
7091 | ? "split" : "inheritance"); | |
cfbeaedf | 7092 | dump_insn_slim (lra_dump_file, curr_insn); |
55a2c322 | 7093 | } |
cefe08a4 | 7094 | delete_move_and_clobber (curr_insn, dregno); |
55a2c322 VM |
7095 | done_p = true; |
7096 | } | |
7097 | else if (bitmap_bit_p (remove_pseudos, sregno) | |
7098 | && bitmap_bit_p (&lra_inheritance_pseudos, sregno)) | |
7099 | { | |
7100 | /* Search the following pattern: | |
7101 | inherit_or_split_pseudo1 <- inherit_or_split_pseudo2 | |
7102 | original_pseudo <- inherit_or_split_pseudo1 | |
7103 | where the 2nd insn is the current insn and | |
7104 | inherit_or_split_pseudo2 is not removed. If it is found, | |
7105 | change the current insn onto: | |
7106 | original_pseudo <- inherit_or_split_pseudo2. */ | |
7107 | for (prev_insn = PREV_INSN (curr_insn); | |
7108 | prev_insn != NULL_RTX && ! NONDEBUG_INSN_P (prev_insn); | |
7109 | prev_insn = PREV_INSN (prev_insn)) | |
7110 | ; | |
7111 | if (prev_insn != NULL_RTX && BLOCK_FOR_INSN (prev_insn) == bb | |
7112 | && (prev_set = single_set (prev_insn)) != NULL_RTX | |
7113 | /* There should be no subregs in insn we are | |
7114 | searching because only the original reg might | |
7115 | be in subreg when we changed the mode of | |
7116 | load/store for splitting. */ | |
7117 | && REG_P (SET_DEST (prev_set)) | |
7118 | && REG_P (SET_SRC (prev_set)) | |
7119 | && (int) REGNO (SET_DEST (prev_set)) == sregno | |
7120 | && ((prev_sregno = REGNO (SET_SRC (prev_set))) | |
7121 | >= FIRST_PSEUDO_REGISTER) | |
8a8330b7 VM |
7122 | && (lra_reg_info[prev_sregno].restore_rtx == NULL_RTX |
7123 | || | |
7124 | /* As we consider chain of inheritance or | |
7125 | splitting described in above comment we should | |
7126 | check that sregno and prev_sregno were | |
7127 | inheritance/split pseudos created from the | |
7128 | same original regno. */ | |
7129 | (get_regno (lra_reg_info[sregno].restore_rtx) >= 0 | |
7130 | && (get_regno (lra_reg_info[sregno].restore_rtx) | |
7131 | == get_regno (lra_reg_info[prev_sregno].restore_rtx)))) | |
55a2c322 VM |
7132 | && ! bitmap_bit_p (remove_pseudos, prev_sregno)) |
7133 | { | |
7134 | lra_assert (GET_MODE (SET_SRC (prev_set)) | |
7135 | == GET_MODE (regno_reg_rtx[sregno])); | |
ef61d1ab AK |
7136 | /* Although we have a single set, the insn can |
7137 | contain more one sregno register occurrence | |
7138 | as a source. Change all occurrences. */ | |
7139 | lra_substitute_pseudo_within_insn (curr_insn, sregno, | |
7140 | SET_SRC (prev_set), | |
7141 | false); | |
12b308fa VM |
7142 | /* As we are finishing with processing the insn |
7143 | here, check the destination too as it might | |
7144 | inheritance pseudo for another pseudo. */ | |
7145 | if (bitmap_bit_p (remove_pseudos, dregno) | |
7146 | && bitmap_bit_p (&lra_inheritance_pseudos, dregno) | |
8a8330b7 VM |
7147 | && (restore_rtx |
7148 | = lra_reg_info[dregno].restore_rtx) != NULL_RTX) | |
12b308fa VM |
7149 | { |
7150 | if (GET_CODE (SET_DEST (set)) == SUBREG) | |
8a8330b7 | 7151 | SUBREG_REG (SET_DEST (set)) = restore_rtx; |
12b308fa | 7152 | else |
8a8330b7 | 7153 | SET_DEST (set) = restore_rtx; |
12b308fa | 7154 | } |
55a2c322 VM |
7155 | lra_push_insn_and_update_insn_regno_info (curr_insn); |
7156 | lra_set_used_insn_alternative_by_uid | |
7874b7c5 | 7157 | (INSN_UID (curr_insn), LRA_UNKNOWN_ALT); |
55a2c322 VM |
7158 | done_p = true; |
7159 | if (lra_dump_file != NULL) | |
7160 | { | |
7161 | fprintf (lra_dump_file, " Change reload insn:\n"); | |
cfbeaedf | 7162 | dump_insn_slim (lra_dump_file, curr_insn); |
55a2c322 VM |
7163 | } |
7164 | } | |
7165 | } | |
7166 | } | |
7167 | if (! done_p) | |
7168 | { | |
7169 | struct lra_insn_reg *reg; | |
7170 | bool restored_regs_p = false; | |
7171 | bool kept_regs_p = false; | |
7172 | ||
7173 | curr_id = lra_get_insn_recog_data (curr_insn); | |
7174 | for (reg = curr_id->regs; reg != NULL; reg = reg->next) | |
7175 | { | |
7176 | regno = reg->regno; | |
8a8330b7 VM |
7177 | restore_rtx = lra_reg_info[regno].restore_rtx; |
7178 | if (restore_rtx != NULL_RTX) | |
55a2c322 VM |
7179 | { |
7180 | if (change_p && bitmap_bit_p (remove_pseudos, regno)) | |
7181 | { | |
ef87312e | 7182 | lra_substitute_pseudo_within_insn |
8a8330b7 | 7183 | (curr_insn, regno, restore_rtx, false); |
55a2c322 VM |
7184 | restored_regs_p = true; |
7185 | } | |
7186 | else | |
7187 | kept_regs_p = true; | |
7188 | } | |
7189 | } | |
7190 | if (NONDEBUG_INSN_P (curr_insn) && kept_regs_p) | |
7191 | { | |
7192 | /* The instruction has changed since the previous | |
7193 | constraints pass. */ | |
7194 | lra_push_insn_and_update_insn_regno_info (curr_insn); | |
7195 | lra_set_used_insn_alternative_by_uid | |
7874b7c5 | 7196 | (INSN_UID (curr_insn), LRA_UNKNOWN_ALT); |
55a2c322 VM |
7197 | } |
7198 | else if (restored_regs_p) | |
7199 | /* The instruction has been restored to the form that | |
7200 | it had during the previous constraints pass. */ | |
7201 | lra_update_insn_regno_info (curr_insn); | |
7202 | if (restored_regs_p && lra_dump_file != NULL) | |
7203 | { | |
7204 | fprintf (lra_dump_file, " Insn after restoring regs:\n"); | |
cfbeaedf | 7205 | dump_insn_slim (lra_dump_file, curr_insn); |
55a2c322 VM |
7206 | } |
7207 | } | |
7208 | } | |
7209 | } | |
7210 | return change_p; | |
7211 | } | |
7212 | ||
2b778c9d VM |
7213 | /* If optional reload pseudos failed to get a hard register or was not |
7214 | inherited, it is better to remove optional reloads. We do this | |
7215 | transformation after undoing inheritance to figure out necessity to | |
7216 | remove optional reloads easier. Return true if we do any | |
7217 | change. */ | |
7218 | static bool | |
7219 | undo_optional_reloads (void) | |
7220 | { | |
b0681c9e | 7221 | bool change_p, keep_p; |
2b778c9d VM |
7222 | unsigned int regno, uid; |
7223 | bitmap_iterator bi, bi2; | |
cfa434f6 DM |
7224 | rtx_insn *insn; |
7225 | rtx set, src, dest; | |
d648b5ff | 7226 | auto_bitmap removed_optional_reload_pseudos (®_obstack); |
2b778c9d | 7227 | |
d648b5ff | 7228 | bitmap_copy (removed_optional_reload_pseudos, &lra_optional_reload_pseudos); |
2b778c9d | 7229 | EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos, 0, regno, bi) |
aa940f7c VM |
7230 | { |
7231 | keep_p = false; | |
080cbf9e | 7232 | /* Keep optional reloads from previous subpasses. */ |
8a8330b7 | 7233 | if (lra_reg_info[regno].restore_rtx == NULL_RTX |
080cbf9e VM |
7234 | /* If the original pseudo changed its allocation, just |
7235 | removing the optional pseudo is dangerous as the original | |
7236 | pseudo will have longer live range. */ | |
8a8330b7 | 7237 | || reg_renumber[REGNO (lra_reg_info[regno].restore_rtx)] >= 0) |
aa940f7c VM |
7238 | keep_p = true; |
7239 | else if (reg_renumber[regno] >= 0) | |
7240 | EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi2) | |
b0681c9e | 7241 | { |
aa940f7c VM |
7242 | insn = lra_insn_recog_data[uid]->insn; |
7243 | if ((set = single_set (insn)) == NULL_RTX) | |
7244 | continue; | |
7245 | src = SET_SRC (set); | |
7246 | dest = SET_DEST (set); | |
7247 | if (! REG_P (src) || ! REG_P (dest)) | |
7248 | continue; | |
7249 | if (REGNO (dest) == regno | |
7250 | /* Ignore insn for optional reloads itself. */ | |
8a8330b7 | 7251 | && REGNO (lra_reg_info[regno].restore_rtx) != REGNO (src) |
aa940f7c VM |
7252 | /* Check only inheritance on last inheritance pass. */ |
7253 | && (int) REGNO (src) >= new_regno_start | |
7254 | /* Check that the optional reload was inherited. */ | |
7255 | && bitmap_bit_p (&lra_inheritance_pseudos, REGNO (src))) | |
7256 | { | |
7257 | keep_p = true; | |
7258 | break; | |
7259 | } | |
b0681c9e | 7260 | } |
aa940f7c VM |
7261 | if (keep_p) |
7262 | { | |
d648b5ff | 7263 | bitmap_clear_bit (removed_optional_reload_pseudos, regno); |
aa940f7c VM |
7264 | if (lra_dump_file != NULL) |
7265 | fprintf (lra_dump_file, "Keep optional reload reg %d\n", regno); | |
7266 | } | |
7267 | } | |
d648b5ff TS |
7268 | change_p = ! bitmap_empty_p (removed_optional_reload_pseudos); |
7269 | auto_bitmap insn_bitmap (®_obstack); | |
7270 | EXECUTE_IF_SET_IN_BITMAP (removed_optional_reload_pseudos, 0, regno, bi) | |
2b778c9d VM |
7271 | { |
7272 | if (lra_dump_file != NULL) | |
7273 | fprintf (lra_dump_file, "Remove optional reload reg %d\n", regno); | |
d648b5ff TS |
7274 | bitmap_copy (insn_bitmap, &lra_reg_info[regno].insn_bitmap); |
7275 | EXECUTE_IF_SET_IN_BITMAP (insn_bitmap, 0, uid, bi2) | |
2b778c9d VM |
7276 | { |
7277 | insn = lra_insn_recog_data[uid]->insn; | |
7278 | if ((set = single_set (insn)) != NULL_RTX) | |
7279 | { | |
7280 | src = SET_SRC (set); | |
7281 | dest = SET_DEST (set); | |
7282 | if (REG_P (src) && REG_P (dest) | |
7283 | && ((REGNO (src) == regno | |
8a8330b7 VM |
7284 | && (REGNO (lra_reg_info[regno].restore_rtx) |
7285 | == REGNO (dest))) | |
2b778c9d | 7286 | || (REGNO (dest) == regno |
8a8330b7 VM |
7287 | && (REGNO (lra_reg_info[regno].restore_rtx) |
7288 | == REGNO (src))))) | |
2b778c9d VM |
7289 | { |
7290 | if (lra_dump_file != NULL) | |
7291 | { | |
7292 | fprintf (lra_dump_file, " Deleting move %u\n", | |
7293 | INSN_UID (insn)); | |
7294 | dump_insn_slim (lra_dump_file, insn); | |
7295 | } | |
cefe08a4 | 7296 | delete_move_and_clobber (insn, REGNO (dest)); |
2b778c9d VM |
7297 | continue; |
7298 | } | |
7299 | /* We should not worry about generation memory-memory | |
7300 | moves here as if the corresponding inheritance did | |
7301 | not work (inheritance pseudo did not get a hard reg), | |
7302 | we remove the inheritance pseudo and the optional | |
7303 | reload. */ | |
7304 | } | |
ef87312e | 7305 | lra_substitute_pseudo_within_insn |
8a8330b7 | 7306 | (insn, regno, lra_reg_info[regno].restore_rtx, false); |
2b778c9d VM |
7307 | lra_update_insn_regno_info (insn); |
7308 | if (lra_dump_file != NULL) | |
7309 | { | |
7310 | fprintf (lra_dump_file, | |
7311 | " Restoring original insn:\n"); | |
7312 | dump_insn_slim (lra_dump_file, insn); | |
7313 | } | |
7314 | } | |
7315 | } | |
7316 | /* Clear restore_regnos. */ | |
7317 | EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos, 0, regno, bi) | |
8a8330b7 | 7318 | lra_reg_info[regno].restore_rtx = NULL_RTX; |
2b778c9d VM |
7319 | return change_p; |
7320 | } | |
7321 | ||
55a2c322 VM |
7322 | /* Entry function for undoing inheritance/split transformation. Return true |
7323 | if we did any RTL change in this pass. */ | |
7324 | bool | |
7325 | lra_undo_inheritance (void) | |
7326 | { | |
7327 | unsigned int regno; | |
8a8330b7 | 7328 | int hard_regno; |
55a2c322 | 7329 | int n_all_inherit, n_inherit, n_all_split, n_split; |
8a8330b7 | 7330 | rtx restore_rtx; |
55a2c322 VM |
7331 | bitmap_iterator bi; |
7332 | bool change_p; | |
7333 | ||
7334 | lra_undo_inheritance_iter++; | |
8e3a4869 | 7335 | if (lra_undo_inheritance_iter > LRA_MAX_INHERITANCE_PASSES) |
e731262b | 7336 | return false; |
55a2c322 VM |
7337 | if (lra_dump_file != NULL) |
7338 | fprintf (lra_dump_file, | |
7339 | "\n********** Undoing inheritance #%d: **********\n\n", | |
7340 | lra_undo_inheritance_iter); | |
d648b5ff | 7341 | auto_bitmap remove_pseudos (®_obstack); |
55a2c322 VM |
7342 | n_inherit = n_all_inherit = 0; |
7343 | EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos, 0, regno, bi) | |
8a8330b7 | 7344 | if (lra_reg_info[regno].restore_rtx != NULL_RTX) |
55a2c322 VM |
7345 | { |
7346 | n_all_inherit++; | |
b0681c9e VM |
7347 | if (reg_renumber[regno] < 0 |
7348 | /* If the original pseudo changed its allocation, just | |
7349 | removing inheritance is dangerous as for changing | |
7350 | allocation we used shorter live-ranges. */ | |
8a8330b7 VM |
7351 | && (! REG_P (lra_reg_info[regno].restore_rtx) |
7352 | || reg_renumber[REGNO (lra_reg_info[regno].restore_rtx)] < 0)) | |
d648b5ff | 7353 | bitmap_set_bit (remove_pseudos, regno); |
55a2c322 VM |
7354 | else |
7355 | n_inherit++; | |
7356 | } | |
7357 | if (lra_dump_file != NULL && n_all_inherit != 0) | |
7358 | fprintf (lra_dump_file, "Inherit %d out of %d (%.2f%%)\n", | |
7359 | n_inherit, n_all_inherit, | |
7360 | (double) n_inherit / n_all_inherit * 100); | |
7361 | n_split = n_all_split = 0; | |
7362 | EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs, 0, regno, bi) | |
8a8330b7 | 7363 | if ((restore_rtx = lra_reg_info[regno].restore_rtx) != NULL_RTX) |
55a2c322 | 7364 | { |
8a8330b7 VM |
7365 | int restore_regno = REGNO (restore_rtx); |
7366 | ||
55a2c322 VM |
7367 | n_all_split++; |
7368 | hard_regno = (restore_regno >= FIRST_PSEUDO_REGISTER | |
7369 | ? reg_renumber[restore_regno] : restore_regno); | |
7370 | if (hard_regno < 0 || reg_renumber[regno] == hard_regno) | |
d648b5ff | 7371 | bitmap_set_bit (remove_pseudos, regno); |
55a2c322 VM |
7372 | else |
7373 | { | |
7374 | n_split++; | |
7375 | if (lra_dump_file != NULL) | |
7376 | fprintf (lra_dump_file, " Keep split r%d (orig=r%d)\n", | |
7377 | regno, restore_regno); | |
7378 | } | |
7379 | } | |
7380 | if (lra_dump_file != NULL && n_all_split != 0) | |
7381 | fprintf (lra_dump_file, "Split %d out of %d (%.2f%%)\n", | |
7382 | n_split, n_all_split, | |
7383 | (double) n_split / n_all_split * 100); | |
d648b5ff | 7384 | change_p = remove_inheritance_pseudos (remove_pseudos); |
55a2c322 VM |
7385 | /* Clear restore_regnos. */ |
7386 | EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos, 0, regno, bi) | |
8a8330b7 | 7387 | lra_reg_info[regno].restore_rtx = NULL_RTX; |
55a2c322 | 7388 | EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs, 0, regno, bi) |
8a8330b7 | 7389 | lra_reg_info[regno].restore_rtx = NULL_RTX; |
2b778c9d | 7390 | change_p = undo_optional_reloads () || change_p; |
55a2c322 VM |
7391 | return change_p; |
7392 | } |