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55a2c322 | 1 | /* Code for RTL transformations to satisfy insn constraints. |
85ec4feb | 2 | Copyright (C) 2010-2018 Free Software Foundation, Inc. |
55a2c322 VM |
3 | Contributed by Vladimir Makarov <vmakarov@redhat.com>. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it under | |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 3, or (at your option) any later | |
10 | version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | ||
22 | /* This file contains code for 3 passes: constraint pass, | |
23 | inheritance/split pass, and pass for undoing failed inheritance and | |
24 | split. | |
25 | ||
26 | The major goal of constraint pass is to transform RTL to satisfy | |
27 | insn and address constraints by: | |
28 | o choosing insn alternatives; | |
29 | o generating *reload insns* (or reloads in brief) and *reload | |
30 | pseudos* which will get necessary hard registers later; | |
31 | o substituting pseudos with equivalent values and removing the | |
32 | instructions that initialized those pseudos. | |
33 | ||
34 | The constraint pass has biggest and most complicated code in LRA. | |
35 | There are a lot of important details like: | |
36 | o reuse of input reload pseudos to simplify reload pseudo | |
37 | allocations; | |
38 | o some heuristics to choose insn alternative to improve the | |
39 | inheritance; | |
40 | o early clobbers etc. | |
41 | ||
42 | The pass is mimicking former reload pass in alternative choosing | |
43 | because the reload pass is oriented to current machine description | |
44 | model. It might be changed if the machine description model is | |
45 | changed. | |
46 | ||
47 | There is special code for preventing all LRA and this pass cycling | |
48 | in case of bugs. | |
49 | ||
50 | On the first iteration of the pass we process every instruction and | |
51 | choose an alternative for each one. On subsequent iterations we try | |
52 | to avoid reprocessing instructions if we can be sure that the old | |
53 | choice is still valid. | |
54 | ||
55 | The inheritance/spilt pass is to transform code to achieve | |
56 | ineheritance and live range splitting. It is done on backward | |
57 | traversal of EBBs. | |
58 | ||
59 | The inheritance optimization goal is to reuse values in hard | |
60 | registers. There is analogous optimization in old reload pass. The | |
61 | inheritance is achieved by following transformation: | |
62 | ||
63 | reload_p1 <- p reload_p1 <- p | |
64 | ... new_p <- reload_p1 | |
65 | ... => ... | |
66 | reload_p2 <- p reload_p2 <- new_p | |
67 | ||
68 | where p is spilled and not changed between the insns. Reload_p1 is | |
69 | also called *original pseudo* and new_p is called *inheritance | |
70 | pseudo*. | |
71 | ||
72 | The subsequent assignment pass will try to assign the same (or | |
73 | another if it is not possible) hard register to new_p as to | |
74 | reload_p1 or reload_p2. | |
75 | ||
76 | If the assignment pass fails to assign a hard register to new_p, | |
77 | this file will undo the inheritance and restore the original code. | |
78 | This is because implementing the above sequence with a spilled | |
79 | new_p would make the code much worse. The inheritance is done in | |
80 | EBB scope. The above is just a simplified example to get an idea | |
81 | of the inheritance as the inheritance is also done for non-reload | |
82 | insns. | |
83 | ||
84 | Splitting (transformation) is also done in EBB scope on the same | |
85 | pass as the inheritance: | |
86 | ||
87 | r <- ... or ... <- r r <- ... or ... <- r | |
88 | ... s <- r (new insn -- save) | |
f4eafc30 | 89 | ... => |
55a2c322 VM |
90 | ... r <- s (new insn -- restore) |
91 | ... <- r ... <- r | |
92 | ||
93 | The *split pseudo* s is assigned to the hard register of the | |
94 | original pseudo or hard register r. | |
95 | ||
96 | Splitting is done: | |
97 | o In EBBs with high register pressure for global pseudos (living | |
98 | in at least 2 BBs) and assigned to hard registers when there | |
99 | are more one reloads needing the hard registers; | |
100 | o for pseudos needing save/restore code around calls. | |
101 | ||
102 | If the split pseudo still has the same hard register as the | |
103 | original pseudo after the subsequent assignment pass or the | |
104 | original pseudo was split, the opposite transformation is done on | |
105 | the same pass for undoing inheritance. */ | |
106 | ||
107 | #undef REG_OK_STRICT | |
108 | ||
109 | #include "config.h" | |
110 | #include "system.h" | |
111 | #include "coretypes.h" | |
c7131fb2 | 112 | #include "backend.h" |
957060b5 | 113 | #include "target.h" |
55a2c322 | 114 | #include "rtl.h" |
957060b5 AM |
115 | #include "tree.h" |
116 | #include "predict.h" | |
c7131fb2 | 117 | #include "df.h" |
4d0cdd0c | 118 | #include "memmodel.h" |
55a2c322 | 119 | #include "tm_p.h" |
957060b5 AM |
120 | #include "expmed.h" |
121 | #include "optabs.h" | |
55a2c322 | 122 | #include "regs.h" |
957060b5 | 123 | #include "ira.h" |
55a2c322 VM |
124 | #include "recog.h" |
125 | #include "output.h" | |
126 | #include "addresses.h" | |
55a2c322 | 127 | #include "expr.h" |
60393bbc | 128 | #include "cfgrtl.h" |
55a2c322 | 129 | #include "rtl-error.h" |
fb8a0e40 | 130 | #include "params.h" |
c7131fb2 | 131 | #include "lra.h" |
55a2c322 | 132 | #include "lra-int.h" |
013a8899 | 133 | #include "print-rtl.h" |
55a2c322 VM |
134 | |
135 | /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current | |
136 | insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted | |
137 | reload insns. */ | |
138 | static int bb_reload_num; | |
139 | ||
2c62cbaa VM |
140 | /* The current insn being processed and corresponding its single set |
141 | (NULL otherwise), its data (basic block, the insn data, the insn | |
142 | static data, and the mode of each operand). */ | |
cfa434f6 | 143 | static rtx_insn *curr_insn; |
2c62cbaa | 144 | static rtx curr_insn_set; |
55a2c322 VM |
145 | static basic_block curr_bb; |
146 | static lra_insn_recog_data_t curr_id; | |
147 | static struct lra_static_insn_data *curr_static_id; | |
ef4bddc2 | 148 | static machine_mode curr_operand_mode[MAX_RECOG_OPERANDS]; |
895ff86f VM |
149 | /* Mode of the register substituted by its equivalence with VOIDmode |
150 | (e.g. constant) and whose subreg is given operand of the current | |
151 | insn. VOIDmode in all other cases. */ | |
152 | static machine_mode original_subreg_reg_mode[MAX_RECOG_OPERANDS]; | |
55a2c322 VM |
153 | |
154 | \f | |
155 | ||
156 | /* Start numbers for new registers and insns at the current constraints | |
157 | pass start. */ | |
158 | static int new_regno_start; | |
159 | static int new_insn_uid_start; | |
160 | ||
277f65de RS |
161 | /* If LOC is nonnull, strip any outer subreg from it. */ |
162 | static inline rtx * | |
163 | strip_subreg (rtx *loc) | |
164 | { | |
165 | return loc && GET_CODE (*loc) == SUBREG ? &SUBREG_REG (*loc) : loc; | |
166 | } | |
167 | ||
55a2c322 VM |
168 | /* Return hard regno of REGNO or if it is was not assigned to a hard |
169 | register, use a hard register from its allocno class. */ | |
170 | static int | |
171 | get_try_hard_regno (int regno) | |
172 | { | |
173 | int hard_regno; | |
174 | enum reg_class rclass; | |
175 | ||
176 | if ((hard_regno = regno) >= FIRST_PSEUDO_REGISTER) | |
177 | hard_regno = lra_get_regno_hard_regno (regno); | |
178 | if (hard_regno >= 0) | |
179 | return hard_regno; | |
180 | rclass = lra_get_allocno_class (regno); | |
181 | if (rclass == NO_REGS) | |
182 | return -1; | |
183 | return ira_class_hard_regs[rclass][0]; | |
184 | } | |
185 | ||
9d0a9bb4 PB |
186 | /* Return the hard regno of X after removing its subreg. If X is not |
187 | a register or a subreg of a register, return -1. If X is a pseudo, | |
1686923c BE |
188 | use its assignment. If FINAL_P return the final hard regno which will |
189 | be after elimination. */ | |
55a2c322 | 190 | static int |
1686923c | 191 | get_hard_regno (rtx x, bool final_p) |
55a2c322 VM |
192 | { |
193 | rtx reg; | |
1686923c | 194 | int hard_regno; |
55a2c322 VM |
195 | |
196 | reg = x; | |
9d0a9bb4 | 197 | if (SUBREG_P (x)) |
55a2c322 VM |
198 | reg = SUBREG_REG (x); |
199 | if (! REG_P (reg)) | |
200 | return -1; | |
9d0a9bb4 | 201 | if (! HARD_REGISTER_NUM_P (hard_regno = REGNO (reg))) |
55a2c322 VM |
202 | hard_regno = lra_get_regno_hard_regno (hard_regno); |
203 | if (hard_regno < 0) | |
204 | return -1; | |
1686923c BE |
205 | if (final_p) |
206 | hard_regno = lra_get_elimination_hard_regno (hard_regno); | |
9d0a9bb4 | 207 | if (SUBREG_P (x)) |
1686923c BE |
208 | hard_regno += subreg_regno_offset (hard_regno, GET_MODE (reg), |
209 | SUBREG_BYTE (x), GET_MODE (x)); | |
210 | return hard_regno; | |
55a2c322 VM |
211 | } |
212 | ||
213 | /* If REGNO is a hard register or has been allocated a hard register, | |
214 | return the class of that register. If REGNO is a reload pseudo | |
215 | created by the current constraints pass, return its allocno class. | |
216 | Return NO_REGS otherwise. */ | |
217 | static enum reg_class | |
218 | get_reg_class (int regno) | |
219 | { | |
220 | int hard_regno; | |
221 | ||
1686923c | 222 | if (! HARD_REGISTER_NUM_P (hard_regno = regno)) |
55a2c322 VM |
223 | hard_regno = lra_get_regno_hard_regno (regno); |
224 | if (hard_regno >= 0) | |
225 | { | |
1686923c | 226 | hard_regno = lra_get_elimination_hard_regno (hard_regno); |
55a2c322 VM |
227 | return REGNO_REG_CLASS (hard_regno); |
228 | } | |
229 | if (regno >= new_regno_start) | |
230 | return lra_get_allocno_class (regno); | |
231 | return NO_REGS; | |
232 | } | |
233 | ||
234 | /* Return true if REG satisfies (or will satisfy) reg class constraint | |
235 | CL. Use elimination first if REG is a hard register. If REG is a | |
236 | reload pseudo created by this constraints pass, assume that it will | |
237 | be allocated a hard register from its allocno class, but allow that | |
238 | class to be narrowed to CL if it is currently a superset of CL. | |
239 | ||
240 | If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of | |
241 | REGNO (reg), or NO_REGS if no change in its class was needed. */ | |
242 | static bool | |
243 | in_class_p (rtx reg, enum reg_class cl, enum reg_class *new_class) | |
244 | { | |
245 | enum reg_class rclass, common_class; | |
ef4bddc2 | 246 | machine_mode reg_mode; |
55a2c322 VM |
247 | int class_size, hard_regno, nregs, i, j; |
248 | int regno = REGNO (reg); | |
f4eafc30 | 249 | |
55a2c322 VM |
250 | if (new_class != NULL) |
251 | *new_class = NO_REGS; | |
252 | if (regno < FIRST_PSEUDO_REGISTER) | |
253 | { | |
254 | rtx final_reg = reg; | |
255 | rtx *final_loc = &final_reg; | |
f4eafc30 | 256 | |
55a2c322 VM |
257 | lra_eliminate_reg_if_possible (final_loc); |
258 | return TEST_HARD_REG_BIT (reg_class_contents[cl], REGNO (*final_loc)); | |
259 | } | |
260 | reg_mode = GET_MODE (reg); | |
261 | rclass = get_reg_class (regno); | |
262 | if (regno < new_regno_start | |
263 | /* Do not allow the constraints for reload instructions to | |
264 | influence the classes of new pseudos. These reloads are | |
265 | typically moves that have many alternatives, and restricting | |
266 | reload pseudos for one alternative may lead to situations | |
267 | where other reload pseudos are no longer allocatable. */ | |
a2d0d374 VM |
268 | || (INSN_UID (curr_insn) >= new_insn_uid_start |
269 | && curr_insn_set != NULL | |
58532ca6 VM |
270 | && ((OBJECT_P (SET_SRC (curr_insn_set)) |
271 | && ! CONSTANT_P (SET_SRC (curr_insn_set))) | |
a2d0d374 | 272 | || (GET_CODE (SET_SRC (curr_insn_set)) == SUBREG |
58532ca6 VM |
273 | && OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set))) |
274 | && ! CONSTANT_P (SUBREG_REG (SET_SRC (curr_insn_set))))))) | |
55a2c322 VM |
275 | /* When we don't know what class will be used finally for reload |
276 | pseudos, we use ALL_REGS. */ | |
277 | return ((regno >= new_regno_start && rclass == ALL_REGS) | |
278 | || (rclass != NO_REGS && ira_class_subset_p[rclass][cl] | |
279 | && ! hard_reg_set_subset_p (reg_class_contents[cl], | |
280 | lra_no_alloc_regs))); | |
281 | else | |
282 | { | |
283 | common_class = ira_reg_class_subset[rclass][cl]; | |
284 | if (new_class != NULL) | |
285 | *new_class = common_class; | |
286 | if (hard_reg_set_subset_p (reg_class_contents[common_class], | |
287 | lra_no_alloc_regs)) | |
288 | return false; | |
289 | /* Check that there are enough allocatable regs. */ | |
290 | class_size = ira_class_hard_regs_num[common_class]; | |
291 | for (i = 0; i < class_size; i++) | |
292 | { | |
293 | hard_regno = ira_class_hard_regs[common_class][i]; | |
ad474626 | 294 | nregs = hard_regno_nregs (hard_regno, reg_mode); |
55a2c322 VM |
295 | if (nregs == 1) |
296 | return true; | |
297 | for (j = 0; j < nregs; j++) | |
f421c426 VM |
298 | if (TEST_HARD_REG_BIT (lra_no_alloc_regs, hard_regno + j) |
299 | || ! TEST_HARD_REG_BIT (reg_class_contents[common_class], | |
300 | hard_regno + j)) | |
55a2c322 VM |
301 | break; |
302 | if (j >= nregs) | |
303 | return true; | |
304 | } | |
305 | return false; | |
306 | } | |
307 | } | |
308 | ||
309 | /* Return true if REGNO satisfies a memory constraint. */ | |
310 | static bool | |
311 | in_mem_p (int regno) | |
312 | { | |
313 | return get_reg_class (regno) == NO_REGS; | |
314 | } | |
315 | ||
a953491e RS |
316 | /* Return 1 if ADDR is a valid memory address for mode MODE in address |
317 | space AS, and check that each pseudo has the proper kind of hard | |
318 | reg. */ | |
319 | static int | |
ef4bddc2 | 320 | valid_address_p (machine_mode mode ATTRIBUTE_UNUSED, |
a953491e RS |
321 | rtx addr, addr_space_t as) |
322 | { | |
323 | #ifdef GO_IF_LEGITIMATE_ADDRESS | |
324 | lra_assert (ADDR_SPACE_GENERIC_P (as)); | |
325 | GO_IF_LEGITIMATE_ADDRESS (mode, addr, win); | |
326 | return 0; | |
327 | ||
328 | win: | |
329 | return 1; | |
330 | #else | |
331 | return targetm.addr_space.legitimate_address_p (mode, addr, 0, as); | |
332 | #endif | |
333 | } | |
334 | ||
335 | namespace { | |
336 | /* Temporarily eliminates registers in an address (for the lifetime of | |
337 | the object). */ | |
338 | class address_eliminator { | |
339 | public: | |
340 | address_eliminator (struct address_info *ad); | |
341 | ~address_eliminator (); | |
342 | ||
343 | private: | |
344 | struct address_info *m_ad; | |
345 | rtx *m_base_loc; | |
346 | rtx m_base_reg; | |
347 | rtx *m_index_loc; | |
348 | rtx m_index_reg; | |
349 | }; | |
350 | } | |
351 | ||
352 | address_eliminator::address_eliminator (struct address_info *ad) | |
353 | : m_ad (ad), | |
354 | m_base_loc (strip_subreg (ad->base_term)), | |
355 | m_base_reg (NULL_RTX), | |
356 | m_index_loc (strip_subreg (ad->index_term)), | |
357 | m_index_reg (NULL_RTX) | |
358 | { | |
359 | if (m_base_loc != NULL) | |
360 | { | |
361 | m_base_reg = *m_base_loc; | |
362 | lra_eliminate_reg_if_possible (m_base_loc); | |
363 | if (m_ad->base_term2 != NULL) | |
364 | *m_ad->base_term2 = *m_ad->base_term; | |
365 | } | |
366 | if (m_index_loc != NULL) | |
367 | { | |
368 | m_index_reg = *m_index_loc; | |
369 | lra_eliminate_reg_if_possible (m_index_loc); | |
370 | } | |
371 | } | |
372 | ||
373 | address_eliminator::~address_eliminator () | |
374 | { | |
375 | if (m_base_loc && *m_base_loc != m_base_reg) | |
376 | { | |
377 | *m_base_loc = m_base_reg; | |
378 | if (m_ad->base_term2 != NULL) | |
379 | *m_ad->base_term2 = *m_ad->base_term; | |
380 | } | |
381 | if (m_index_loc && *m_index_loc != m_index_reg) | |
382 | *m_index_loc = m_index_reg; | |
383 | } | |
384 | ||
385 | /* Return true if the eliminated form of AD is a legitimate target address. */ | |
386 | static bool | |
387 | valid_address_p (struct address_info *ad) | |
388 | { | |
389 | address_eliminator eliminator (ad); | |
390 | return valid_address_p (ad->mode, *ad->outer, ad->as); | |
391 | } | |
392 | ||
a953491e | 393 | /* Return true if the eliminated form of memory reference OP satisfies |
9eb1ca69 | 394 | extra (special) memory constraint CONSTRAINT. */ |
a953491e | 395 | static bool |
777e635f | 396 | satisfies_memory_constraint_p (rtx op, enum constraint_num constraint) |
a953491e RS |
397 | { |
398 | struct address_info ad; | |
399 | ||
400 | decompose_mem_address (&ad, op); | |
401 | address_eliminator eliminator (&ad); | |
777e635f | 402 | return constraint_satisfied_p (op, constraint); |
a953491e RS |
403 | } |
404 | ||
405 | /* Return true if the eliminated form of address AD satisfies extra | |
406 | address constraint CONSTRAINT. */ | |
407 | static bool | |
408 | satisfies_address_constraint_p (struct address_info *ad, | |
777e635f | 409 | enum constraint_num constraint) |
a953491e RS |
410 | { |
411 | address_eliminator eliminator (ad); | |
777e635f | 412 | return constraint_satisfied_p (*ad->outer, constraint); |
a953491e RS |
413 | } |
414 | ||
415 | /* Return true if the eliminated form of address OP satisfies extra | |
416 | address constraint CONSTRAINT. */ | |
417 | static bool | |
777e635f | 418 | satisfies_address_constraint_p (rtx op, enum constraint_num constraint) |
a953491e RS |
419 | { |
420 | struct address_info ad; | |
421 | ||
422 | decompose_lea_address (&ad, &op); | |
423 | return satisfies_address_constraint_p (&ad, constraint); | |
424 | } | |
a953491e | 425 | |
4c2b2d79 VM |
426 | /* Initiate equivalences for LRA. As we keep original equivalences |
427 | before any elimination, we need to make copies otherwise any change | |
428 | in insns might change the equivalences. */ | |
429 | void | |
430 | lra_init_equiv (void) | |
431 | { | |
432 | ira_expand_reg_equiv (); | |
433 | for (int i = FIRST_PSEUDO_REGISTER; i < max_reg_num (); i++) | |
434 | { | |
435 | rtx res; | |
436 | ||
437 | if ((res = ira_reg_equiv[i].memory) != NULL_RTX) | |
438 | ira_reg_equiv[i].memory = copy_rtx (res); | |
439 | if ((res = ira_reg_equiv[i].invariant) != NULL_RTX) | |
440 | ira_reg_equiv[i].invariant = copy_rtx (res); | |
441 | } | |
442 | } | |
443 | ||
444 | static rtx loc_equivalence_callback (rtx, const_rtx, void *); | |
445 | ||
446 | /* Update equivalence for REGNO. We need to this as the equivalence | |
447 | might contain other pseudos which are changed by their | |
448 | equivalences. */ | |
449 | static void | |
450 | update_equiv (int regno) | |
451 | { | |
452 | rtx x; | |
453 | ||
454 | if ((x = ira_reg_equiv[regno].memory) != NULL_RTX) | |
455 | ira_reg_equiv[regno].memory | |
456 | = simplify_replace_fn_rtx (x, NULL_RTX, loc_equivalence_callback, | |
457 | NULL_RTX); | |
458 | if ((x = ira_reg_equiv[regno].invariant) != NULL_RTX) | |
459 | ira_reg_equiv[regno].invariant | |
460 | = simplify_replace_fn_rtx (x, NULL_RTX, loc_equivalence_callback, | |
461 | NULL_RTX); | |
462 | } | |
463 | ||
55a2c322 VM |
464 | /* If we have decided to substitute X with another value, return that |
465 | value, otherwise return X. */ | |
466 | static rtx | |
8d49e7ef | 467 | get_equiv (rtx x) |
55a2c322 VM |
468 | { |
469 | int regno; | |
470 | rtx res; | |
471 | ||
472 | if (! REG_P (x) || (regno = REGNO (x)) < FIRST_PSEUDO_REGISTER | |
473 | || ! ira_reg_equiv[regno].defined_p | |
474 | || ! ira_reg_equiv[regno].profitable_p | |
475 | || lra_get_regno_hard_regno (regno) >= 0) | |
476 | return x; | |
477 | if ((res = ira_reg_equiv[regno].memory) != NULL_RTX) | |
d6220b11 KK |
478 | { |
479 | if (targetm.cannot_substitute_mem_equiv_p (res)) | |
480 | return x; | |
481 | return res; | |
482 | } | |
55a2c322 VM |
483 | if ((res = ira_reg_equiv[regno].constant) != NULL_RTX) |
484 | return res; | |
485 | if ((res = ira_reg_equiv[regno].invariant) != NULL_RTX) | |
486 | return res; | |
487 | gcc_unreachable (); | |
488 | } | |
489 | ||
8d49e7ef VM |
490 | /* If we have decided to substitute X with the equivalent value, |
491 | return that value after elimination for INSN, otherwise return | |
492 | X. */ | |
493 | static rtx | |
cfa434f6 | 494 | get_equiv_with_elimination (rtx x, rtx_insn *insn) |
8d49e7ef VM |
495 | { |
496 | rtx res = get_equiv (x); | |
497 | ||
498 | if (x == res || CONSTANT_P (res)) | |
499 | return res; | |
d9cf932c | 500 | return lra_eliminate_regs_1 (insn, res, GET_MODE (res), |
a6af1bf9 | 501 | false, false, 0, true); |
8d49e7ef VM |
502 | } |
503 | ||
55a2c322 VM |
504 | /* Set up curr_operand_mode. */ |
505 | static void | |
506 | init_curr_operand_mode (void) | |
507 | { | |
508 | int nop = curr_static_id->n_operands; | |
509 | for (int i = 0; i < nop; i++) | |
510 | { | |
ef4bddc2 | 511 | machine_mode mode = GET_MODE (*curr_id->operand_loc[i]); |
55a2c322 VM |
512 | if (mode == VOIDmode) |
513 | { | |
514 | /* The .md mode for address operands is the mode of the | |
515 | addressed value rather than the mode of the address itself. */ | |
516 | if (curr_id->icode >= 0 && curr_static_id->operand[i].is_address) | |
517 | mode = Pmode; | |
518 | else | |
519 | mode = curr_static_id->operand[i].mode; | |
520 | } | |
521 | curr_operand_mode[i] = mode; | |
522 | } | |
523 | } | |
524 | ||
525 | \f | |
526 | ||
527 | /* The page contains code to reuse input reloads. */ | |
528 | ||
529 | /* Structure describes input reload of the current insns. */ | |
530 | struct input_reload | |
531 | { | |
3f156a6c VM |
532 | /* True for input reload of matched operands. */ |
533 | bool match_p; | |
55a2c322 VM |
534 | /* Reloaded value. */ |
535 | rtx input; | |
536 | /* Reload pseudo used. */ | |
537 | rtx reg; | |
538 | }; | |
539 | ||
540 | /* The number of elements in the following array. */ | |
541 | static int curr_insn_input_reloads_num; | |
542 | /* Array containing info about input reloads. It is used to find the | |
543 | same input reload and reuse the reload pseudo in this case. */ | |
544 | static struct input_reload curr_insn_input_reloads[LRA_MAX_INSN_RELOADS]; | |
545 | ||
546 | /* Initiate data concerning reuse of input reloads for the current | |
547 | insn. */ | |
548 | static void | |
549 | init_curr_insn_input_reloads (void) | |
550 | { | |
551 | curr_insn_input_reloads_num = 0; | |
552 | } | |
553 | ||
55a2c322 | 554 | /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already |
95921002 VM |
555 | created input reload pseudo (only if TYPE is not OP_OUT). Don't |
556 | reuse pseudo if IN_SUBREG_P is true and the reused pseudo should be | |
557 | wrapped up in SUBREG. The result pseudo is returned through | |
558 | RESULT_REG. Return TRUE if we created a new pseudo, FALSE if we | |
559 | reused the already created input reload pseudo. Use TITLE to | |
560 | describe new registers for debug purposes. */ | |
55a2c322 | 561 | static bool |
ef4bddc2 | 562 | get_reload_reg (enum op_type type, machine_mode mode, rtx original, |
95921002 VM |
563 | enum reg_class rclass, bool in_subreg_p, |
564 | const char *title, rtx *result_reg) | |
55a2c322 VM |
565 | { |
566 | int i, regno; | |
567 | enum reg_class new_class; | |
3f156a6c | 568 | bool unique_p = false; |
55a2c322 VM |
569 | |
570 | if (type == OP_OUT) | |
571 | { | |
572 | *result_reg | |
573 | = lra_create_new_reg_with_unique_value (mode, original, rclass, title); | |
574 | return true; | |
575 | } | |
73cca0cc VM |
576 | /* Prevent reuse value of expression with side effects, |
577 | e.g. volatile memory. */ | |
578 | if (! side_effects_p (original)) | |
579 | for (i = 0; i < curr_insn_input_reloads_num; i++) | |
3f156a6c VM |
580 | { |
581 | if (! curr_insn_input_reloads[i].match_p | |
582 | && rtx_equal_p (curr_insn_input_reloads[i].input, original) | |
583 | && in_class_p (curr_insn_input_reloads[i].reg, rclass, &new_class)) | |
584 | { | |
585 | rtx reg = curr_insn_input_reloads[i].reg; | |
586 | regno = REGNO (reg); | |
587 | /* If input is equal to original and both are VOIDmode, | |
588 | GET_MODE (reg) might be still different from mode. | |
589 | Ensure we don't return *result_reg with wrong mode. */ | |
590 | if (GET_MODE (reg) != mode) | |
591 | { | |
592 | if (in_subreg_p) | |
593 | continue; | |
cf098191 RS |
594 | if (maybe_lt (GET_MODE_SIZE (GET_MODE (reg)), |
595 | GET_MODE_SIZE (mode))) | |
3f156a6c VM |
596 | continue; |
597 | reg = lowpart_subreg (mode, reg, GET_MODE (reg)); | |
598 | if (reg == NULL_RTX || GET_CODE (reg) != SUBREG) | |
599 | continue; | |
600 | } | |
601 | *result_reg = reg; | |
602 | if (lra_dump_file != NULL) | |
603 | { | |
604 | fprintf (lra_dump_file, " Reuse r%d for reload ", regno); | |
605 | dump_value_slim (lra_dump_file, original, 1); | |
606 | } | |
607 | if (new_class != lra_get_allocno_class (regno)) | |
608 | lra_change_class (regno, new_class, ", change to", false); | |
609 | if (lra_dump_file != NULL) | |
610 | fprintf (lra_dump_file, "\n"); | |
611 | return false; | |
612 | } | |
613 | /* If we have an input reload with a different mode, make sure it | |
614 | will get a different hard reg. */ | |
615 | else if (REG_P (original) | |
616 | && REG_P (curr_insn_input_reloads[i].input) | |
617 | && REGNO (original) == REGNO (curr_insn_input_reloads[i].input) | |
618 | && (GET_MODE (original) | |
619 | != GET_MODE (curr_insn_input_reloads[i].input))) | |
620 | unique_p = true; | |
621 | } | |
622 | *result_reg = (unique_p | |
623 | ? lra_create_new_reg_with_unique_value | |
624 | : lra_create_new_reg) (mode, original, rclass, title); | |
55a2c322 VM |
625 | lra_assert (curr_insn_input_reloads_num < LRA_MAX_INSN_RELOADS); |
626 | curr_insn_input_reloads[curr_insn_input_reloads_num].input = original; | |
3f156a6c | 627 | curr_insn_input_reloads[curr_insn_input_reloads_num].match_p = false; |
55a2c322 VM |
628 | curr_insn_input_reloads[curr_insn_input_reloads_num++].reg = *result_reg; |
629 | return true; | |
630 | } | |
631 | ||
632 | \f | |
55a2c322 VM |
633 | /* The page contains major code to choose the current insn alternative |
634 | and generate reloads for it. */ | |
635 | ||
636 | /* Return the offset from REGNO of the least significant register | |
637 | in (reg:MODE REGNO). | |
638 | ||
639 | This function is used to tell whether two registers satisfy | |
640 | a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if: | |
641 | ||
642 | REGNO1 + lra_constraint_offset (REGNO1, MODE1) | |
643 | == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */ | |
644 | int | |
ef4bddc2 | 645 | lra_constraint_offset (int regno, machine_mode mode) |
55a2c322 VM |
646 | { |
647 | lra_assert (regno < FIRST_PSEUDO_REGISTER); | |
b0567726 RS |
648 | |
649 | scalar_int_mode int_mode; | |
650 | if (WORDS_BIG_ENDIAN | |
651 | && is_a <scalar_int_mode> (mode, &int_mode) | |
652 | && GET_MODE_SIZE (int_mode) > UNITS_PER_WORD) | |
ad474626 | 653 | return hard_regno_nregs (regno, mode) - 1; |
55a2c322 VM |
654 | return 0; |
655 | } | |
656 | ||
657 | /* Like rtx_equal_p except that it allows a REG and a SUBREG to match | |
658 | if they are the same hard reg, and has special hacks for | |
659 | auto-increment and auto-decrement. This is specifically intended for | |
660 | process_alt_operands to use in determining whether two operands | |
661 | match. X is the operand whose number is the lower of the two. | |
662 | ||
663 | It is supposed that X is the output operand and Y is the input | |
664 | operand. Y_HARD_REGNO is the final hard regno of register Y or | |
665 | register in subreg Y as we know it now. Otherwise, it is a | |
666 | negative value. */ | |
667 | static bool | |
668 | operands_match_p (rtx x, rtx y, int y_hard_regno) | |
669 | { | |
670 | int i; | |
671 | RTX_CODE code = GET_CODE (x); | |
672 | const char *fmt; | |
673 | ||
674 | if (x == y) | |
675 | return true; | |
676 | if ((code == REG || (code == SUBREG && REG_P (SUBREG_REG (x)))) | |
677 | && (REG_P (y) || (GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y))))) | |
678 | { | |
679 | int j; | |
f4eafc30 | 680 | |
1686923c | 681 | i = get_hard_regno (x, false); |
55a2c322 VM |
682 | if (i < 0) |
683 | goto slow; | |
684 | ||
685 | if ((j = y_hard_regno) < 0) | |
686 | goto slow; | |
687 | ||
688 | i += lra_constraint_offset (i, GET_MODE (x)); | |
689 | j += lra_constraint_offset (j, GET_MODE (y)); | |
690 | ||
691 | return i == j; | |
692 | } | |
693 | ||
694 | /* If two operands must match, because they are really a single | |
695 | operand of an assembler insn, then two post-increments are invalid | |
696 | because the assembler insn would increment only once. On the | |
697 | other hand, a post-increment matches ordinary indexing if the | |
698 | post-increment is the output operand. */ | |
699 | if (code == POST_DEC || code == POST_INC || code == POST_MODIFY) | |
700 | return operands_match_p (XEXP (x, 0), y, y_hard_regno); | |
701 | ||
702 | /* Two pre-increments are invalid because the assembler insn would | |
703 | increment only once. On the other hand, a pre-increment matches | |
704 | ordinary indexing if the pre-increment is the input operand. */ | |
705 | if (GET_CODE (y) == PRE_DEC || GET_CODE (y) == PRE_INC | |
706 | || GET_CODE (y) == PRE_MODIFY) | |
707 | return operands_match_p (x, XEXP (y, 0), -1); | |
f4eafc30 | 708 | |
55a2c322 VM |
709 | slow: |
710 | ||
9fccb335 RS |
711 | if (code == REG && REG_P (y)) |
712 | return REGNO (x) == REGNO (y); | |
713 | ||
55a2c322 VM |
714 | if (code == REG && GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y)) |
715 | && x == SUBREG_REG (y)) | |
716 | return true; | |
717 | if (GET_CODE (y) == REG && code == SUBREG && REG_P (SUBREG_REG (x)) | |
718 | && SUBREG_REG (x) == y) | |
719 | return true; | |
720 | ||
721 | /* Now we have disposed of all the cases in which different rtx | |
722 | codes can match. */ | |
723 | if (code != GET_CODE (y)) | |
724 | return false; | |
725 | ||
726 | /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */ | |
727 | if (GET_MODE (x) != GET_MODE (y)) | |
728 | return false; | |
729 | ||
730 | switch (code) | |
731 | { | |
732 | CASE_CONST_UNIQUE: | |
733 | return false; | |
734 | ||
735 | case LABEL_REF: | |
04a121a7 | 736 | return label_ref_label (x) == label_ref_label (y); |
55a2c322 VM |
737 | case SYMBOL_REF: |
738 | return XSTR (x, 0) == XSTR (y, 0); | |
739 | ||
740 | default: | |
741 | break; | |
742 | } | |
743 | ||
744 | /* Compare the elements. If any pair of corresponding elements fail | |
745 | to match, return false for the whole things. */ | |
746 | ||
747 | fmt = GET_RTX_FORMAT (code); | |
748 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
749 | { | |
750 | int val, j; | |
751 | switch (fmt[i]) | |
752 | { | |
753 | case 'w': | |
754 | if (XWINT (x, i) != XWINT (y, i)) | |
755 | return false; | |
756 | break; | |
757 | ||
758 | case 'i': | |
759 | if (XINT (x, i) != XINT (y, i)) | |
760 | return false; | |
761 | break; | |
762 | ||
91914e56 RS |
763 | case 'p': |
764 | if (maybe_ne (SUBREG_BYTE (x), SUBREG_BYTE (y))) | |
765 | return false; | |
766 | break; | |
767 | ||
55a2c322 VM |
768 | case 'e': |
769 | val = operands_match_p (XEXP (x, i), XEXP (y, i), -1); | |
770 | if (val == 0) | |
771 | return false; | |
772 | break; | |
773 | ||
774 | case '0': | |
775 | break; | |
776 | ||
777 | case 'E': | |
778 | if (XVECLEN (x, i) != XVECLEN (y, i)) | |
779 | return false; | |
780 | for (j = XVECLEN (x, i) - 1; j >= 0; --j) | |
781 | { | |
782 | val = operands_match_p (XVECEXP (x, i, j), XVECEXP (y, i, j), -1); | |
783 | if (val == 0) | |
784 | return false; | |
785 | } | |
786 | break; | |
787 | ||
788 | /* It is believed that rtx's at this level will never | |
789 | contain anything but integers and other rtx's, except for | |
790 | within LABEL_REFs and SYMBOL_REFs. */ | |
791 | default: | |
792 | gcc_unreachable (); | |
793 | } | |
794 | } | |
795 | return true; | |
796 | } | |
797 | ||
798 | /* True if X is a constant that can be forced into the constant pool. | |
799 | MODE is the mode of the operand, or VOIDmode if not known. */ | |
800 | #define CONST_POOL_OK_P(MODE, X) \ | |
801 | ((MODE) != VOIDmode \ | |
802 | && CONSTANT_P (X) \ | |
803 | && GET_CODE (X) != HIGH \ | |
cf098191 | 804 | && GET_MODE_SIZE (MODE).is_constant () \ |
55a2c322 VM |
805 | && !targetm.cannot_force_const_mem (MODE, X)) |
806 | ||
807 | /* True if C is a non-empty register class that has too few registers | |
808 | to be safely used as a reload target class. */ | |
a9711f36 VM |
809 | #define SMALL_REGISTER_CLASS_P(C) \ |
810 | (ira_class_hard_regs_num [(C)] == 1 \ | |
811 | || (ira_class_hard_regs_num [(C)] >= 1 \ | |
812 | && targetm.class_likely_spilled_p (C))) | |
55a2c322 VM |
813 | |
814 | /* If REG is a reload pseudo, try to make its class satisfying CL. */ | |
815 | static void | |
816 | narrow_reload_pseudo_class (rtx reg, enum reg_class cl) | |
817 | { | |
818 | enum reg_class rclass; | |
819 | ||
820 | /* Do not make more accurate class from reloads generated. They are | |
821 | mostly moves with a lot of constraints. Making more accurate | |
822 | class may results in very narrow class and impossibility of find | |
823 | registers for several reloads of one insn. */ | |
824 | if (INSN_UID (curr_insn) >= new_insn_uid_start) | |
825 | return; | |
826 | if (GET_CODE (reg) == SUBREG) | |
827 | reg = SUBREG_REG (reg); | |
828 | if (! REG_P (reg) || (int) REGNO (reg) < new_regno_start) | |
829 | return; | |
830 | if (in_class_p (reg, cl, &rclass) && rclass != cl) | |
a2d0d374 | 831 | lra_change_class (REGNO (reg), rclass, " Change to", true); |
55a2c322 VM |
832 | } |
833 | ||
4be9717c VM |
834 | /* Searches X for any reference to a reg with the same value as REGNO, |
835 | returning the rtx of the reference found if any. Otherwise, | |
836 | returns NULL_RTX. */ | |
837 | static rtx | |
838 | regno_val_use_in (unsigned int regno, rtx x) | |
839 | { | |
840 | const char *fmt; | |
841 | int i, j; | |
842 | rtx tem; | |
843 | ||
844 | if (REG_P (x) && lra_reg_info[REGNO (x)].val == lra_reg_info[regno].val) | |
845 | return x; | |
846 | ||
847 | fmt = GET_RTX_FORMAT (GET_CODE (x)); | |
848 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) | |
849 | { | |
850 | if (fmt[i] == 'e') | |
851 | { | |
852 | if ((tem = regno_val_use_in (regno, XEXP (x, i)))) | |
853 | return tem; | |
854 | } | |
855 | else if (fmt[i] == 'E') | |
856 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
857 | if ((tem = regno_val_use_in (regno , XVECEXP (x, i, j)))) | |
858 | return tem; | |
859 | } | |
860 | ||
861 | return NULL_RTX; | |
862 | } | |
863 | ||
d8321b33 VM |
864 | /* Return true if all current insn non-output operands except INS (it |
865 | has a negaitve end marker) do not use pseudos with the same value | |
866 | as REGNO. */ | |
867 | static bool | |
868 | check_conflict_input_operands (int regno, signed char *ins) | |
869 | { | |
870 | int in; | |
871 | int n_operands = curr_static_id->n_operands; | |
872 | ||
873 | for (int nop = 0; nop < n_operands; nop++) | |
874 | if (! curr_static_id->operand[nop].is_operator | |
875 | && curr_static_id->operand[nop].type != OP_OUT) | |
876 | { | |
877 | for (int i = 0; (in = ins[i]) >= 0; i++) | |
878 | if (in == nop) | |
879 | break; | |
880 | if (in < 0 | |
881 | && regno_val_use_in (regno, *curr_id->operand_loc[nop]) != NULL_RTX) | |
882 | return false; | |
883 | } | |
884 | return true; | |
885 | } | |
886 | ||
55a2c322 | 887 | /* Generate reloads for matching OUT and INS (array of input operand |
aefae0f1 TP |
888 | numbers with end marker -1) with reg class GOAL_CLASS, considering |
889 | output operands OUTS (similar array to INS) needing to be in different | |
890 | registers. Add input and output reloads correspondingly to the lists | |
891 | *BEFORE and *AFTER. OUT might be negative. In this case we generate | |
892 | input reloads for matched input operands INS. EARLY_CLOBBER_P is a flag | |
893 | that the output operand is early clobbered for chosen alternative. */ | |
55a2c322 | 894 | static void |
aefae0f1 TP |
895 | match_reload (signed char out, signed char *ins, signed char *outs, |
896 | enum reg_class goal_class, rtx_insn **before, | |
897 | rtx_insn **after, bool early_clobber_p) | |
55a2c322 | 898 | { |
aefae0f1 | 899 | bool out_conflict; |
55a2c322 | 900 | int i, in; |
e67d1102 | 901 | rtx new_in_reg, new_out_reg, reg; |
ef4bddc2 | 902 | machine_mode inmode, outmode; |
55a2c322 | 903 | rtx in_rtx = *curr_id->operand_loc[ins[0]]; |
511dcace | 904 | rtx out_rtx = out < 0 ? in_rtx : *curr_id->operand_loc[out]; |
55a2c322 | 905 | |
55a2c322 | 906 | inmode = curr_operand_mode[ins[0]]; |
511dcace | 907 | outmode = out < 0 ? inmode : curr_operand_mode[out]; |
55a2c322 VM |
908 | push_to_sequence (*before); |
909 | if (inmode != outmode) | |
910 | { | |
00224b1a RS |
911 | /* process_alt_operands has already checked that the mode sizes |
912 | are ordered. */ | |
bd4288c0 | 913 | if (partial_subreg_p (outmode, inmode)) |
55a2c322 VM |
914 | { |
915 | reg = new_in_reg | |
916 | = lra_create_new_reg_with_unique_value (inmode, in_rtx, | |
917 | goal_class, ""); | |
98a05c03 | 918 | new_out_reg = gen_lowpart_SUBREG (outmode, reg); |
2c62cbaa | 919 | LRA_SUBREG_P (new_out_reg) = 1; |
350c0fe7 | 920 | /* If the input reg is dying here, we can use the same hard |
f681cf95 VM |
921 | register for REG and IN_RTX. We do it only for original |
922 | pseudos as reload pseudos can die although original | |
923 | pseudos still live where reload pseudos dies. */ | |
924 | if (REG_P (in_rtx) && (int) REGNO (in_rtx) < lra_new_regno_start | |
d8321b33 VM |
925 | && find_regno_note (curr_insn, REG_DEAD, REGNO (in_rtx)) |
926 | && (!early_clobber_p | |
927 | || check_conflict_input_operands(REGNO (in_rtx), ins))) | |
d70a81dd | 928 | lra_assign_reg_val (REGNO (in_rtx), REGNO (reg)); |
55a2c322 VM |
929 | } |
930 | else | |
931 | { | |
932 | reg = new_out_reg | |
933 | = lra_create_new_reg_with_unique_value (outmode, out_rtx, | |
934 | goal_class, ""); | |
98a05c03 | 935 | new_in_reg = gen_lowpart_SUBREG (inmode, reg); |
55a2c322 VM |
936 | /* NEW_IN_REG is non-paradoxical subreg. We don't want |
937 | NEW_OUT_REG living above. We add clobber clause for | |
c5cd5a7e VM |
938 | this. This is just a temporary clobber. We can remove |
939 | it at the end of LRA work. */ | |
e67d1102 | 940 | rtx_insn *clobber = emit_clobber (new_out_reg); |
c5cd5a7e | 941 | LRA_TEMP_CLOBBER_P (PATTERN (clobber)) = 1; |
2c62cbaa | 942 | LRA_SUBREG_P (new_in_reg) = 1; |
350c0fe7 VM |
943 | if (GET_CODE (in_rtx) == SUBREG) |
944 | { | |
945 | rtx subreg_reg = SUBREG_REG (in_rtx); | |
946 | ||
947 | /* If SUBREG_REG is dying here and sub-registers IN_RTX | |
948 | and NEW_IN_REG are similar, we can use the same hard | |
949 | register for REG and SUBREG_REG. */ | |
f681cf95 VM |
950 | if (REG_P (subreg_reg) |
951 | && (int) REGNO (subreg_reg) < lra_new_regno_start | |
952 | && GET_MODE (subreg_reg) == outmode | |
91914e56 | 953 | && known_eq (SUBREG_BYTE (in_rtx), SUBREG_BYTE (new_in_reg)) |
d8321b33 VM |
954 | && find_regno_note (curr_insn, REG_DEAD, REGNO (subreg_reg)) |
955 | && (! early_clobber_p | |
956 | || check_conflict_input_operands (REGNO (subreg_reg), | |
957 | ins))) | |
d70a81dd | 958 | lra_assign_reg_val (REGNO (subreg_reg), REGNO (reg)); |
350c0fe7 | 959 | } |
55a2c322 VM |
960 | } |
961 | } | |
962 | else | |
963 | { | |
964 | /* Pseudos have values -- see comments for lra_reg_info. | |
965 | Different pseudos with the same value do not conflict even if | |
966 | they live in the same place. When we create a pseudo we | |
967 | assign value of original pseudo (if any) from which we | |
968 | created the new pseudo. If we create the pseudo from the | |
3363daad VM |
969 | input pseudo, the new pseudo will have no conflict with the |
970 | input pseudo which is wrong when the input pseudo lives after | |
971 | the insn and as the new pseudo value is changed by the insn | |
972 | output. Therefore we create the new pseudo from the output | |
973 | except the case when we have single matched dying input | |
974 | pseudo. | |
f4eafc30 | 975 | |
55a2c322 VM |
976 | We cannot reuse the current output register because we might |
977 | have a situation like "a <- a op b", where the constraints | |
978 | force the second input operand ("b") to match the output | |
979 | operand ("a"). "b" must then be copied into a new register | |
599e1cf8 VM |
980 | so that it doesn't clobber the current value of "a". |
981 | ||
982 | We can not use the same value if the output pseudo is | |
983 | early clobbered or the input pseudo is mentioned in the | |
984 | output, e.g. as an address part in memory, because | |
985 | output reload will actually extend the pseudo liveness. | |
986 | We don't care about eliminable hard regs here as we are | |
987 | interesting only in pseudos. */ | |
f4eafc30 | 988 | |
aefae0f1 TP |
989 | /* Matching input's register value is the same as one of the other |
990 | output operand. Output operands in a parallel insn must be in | |
991 | different registers. */ | |
992 | out_conflict = false; | |
993 | if (REG_P (in_rtx)) | |
994 | { | |
995 | for (i = 0; outs[i] >= 0; i++) | |
996 | { | |
997 | rtx other_out_rtx = *curr_id->operand_loc[outs[i]]; | |
998 | if (REG_P (other_out_rtx) | |
999 | && (regno_val_use_in (REGNO (in_rtx), other_out_rtx) | |
1000 | != NULL_RTX)) | |
1001 | { | |
1002 | out_conflict = true; | |
1003 | break; | |
1004 | } | |
1005 | } | |
1006 | } | |
1007 | ||
55a2c322 | 1008 | new_in_reg = new_out_reg |
599e1cf8 | 1009 | = (! early_clobber_p && ins[1] < 0 && REG_P (in_rtx) |
3363daad VM |
1010 | && (int) REGNO (in_rtx) < lra_new_regno_start |
1011 | && find_regno_note (curr_insn, REG_DEAD, REGNO (in_rtx)) | |
d8321b33 VM |
1012 | && (! early_clobber_p |
1013 | || check_conflict_input_operands (REGNO (in_rtx), ins)) | |
4be9717c VM |
1014 | && (out < 0 |
1015 | || regno_val_use_in (REGNO (in_rtx), out_rtx) == NULL_RTX) | |
aefae0f1 | 1016 | && !out_conflict |
3363daad VM |
1017 | ? lra_create_new_reg (inmode, in_rtx, goal_class, "") |
1018 | : lra_create_new_reg_with_unique_value (outmode, out_rtx, | |
1019 | goal_class, "")); | |
55a2c322 | 1020 | } |
511dcace VM |
1021 | /* In operand can be got from transformations before processing insn |
1022 | constraints. One example of such transformations is subreg | |
1023 | reloading (see function simplify_operand_subreg). The new | |
1024 | pseudos created by the transformations might have inaccurate | |
55a2c322 VM |
1025 | class (ALL_REGS) and we should make their classes more |
1026 | accurate. */ | |
1027 | narrow_reload_pseudo_class (in_rtx, goal_class); | |
55a2c322 VM |
1028 | lra_emit_move (copy_rtx (new_in_reg), in_rtx); |
1029 | *before = get_insns (); | |
1030 | end_sequence (); | |
3f156a6c VM |
1031 | /* Add the new pseudo to consider values of subsequent input reload |
1032 | pseudos. */ | |
1033 | lra_assert (curr_insn_input_reloads_num < LRA_MAX_INSN_RELOADS); | |
1034 | curr_insn_input_reloads[curr_insn_input_reloads_num].input = in_rtx; | |
1035 | curr_insn_input_reloads[curr_insn_input_reloads_num].match_p = true; | |
1036 | curr_insn_input_reloads[curr_insn_input_reloads_num++].reg = new_in_reg; | |
55a2c322 VM |
1037 | for (i = 0; (in = ins[i]) >= 0; i++) |
1038 | { | |
1039 | lra_assert | |
1040 | (GET_MODE (*curr_id->operand_loc[in]) == VOIDmode | |
1041 | || GET_MODE (new_in_reg) == GET_MODE (*curr_id->operand_loc[in])); | |
1042 | *curr_id->operand_loc[in] = new_in_reg; | |
1043 | } | |
1044 | lra_update_dups (curr_id, ins); | |
511dcace VM |
1045 | if (out < 0) |
1046 | return; | |
1047 | /* See a comment for the input operand above. */ | |
1048 | narrow_reload_pseudo_class (out_rtx, goal_class); | |
55a2c322 VM |
1049 | if (find_reg_note (curr_insn, REG_UNUSED, out_rtx) == NULL_RTX) |
1050 | { | |
1051 | start_sequence (); | |
1052 | lra_emit_move (out_rtx, copy_rtx (new_out_reg)); | |
1053 | emit_insn (*after); | |
1054 | *after = get_insns (); | |
1055 | end_sequence (); | |
1056 | } | |
1057 | *curr_id->operand_loc[out] = new_out_reg; | |
1058 | lra_update_dup (curr_id, out); | |
1059 | } | |
1060 | ||
1061 | /* Return register class which is union of all reg classes in insn | |
1062 | constraint alternative string starting with P. */ | |
1063 | static enum reg_class | |
1064 | reg_class_from_constraints (const char *p) | |
1065 | { | |
1066 | int c, len; | |
1067 | enum reg_class op_class = NO_REGS; | |
1068 | ||
1069 | do | |
1070 | switch ((c = *p, len = CONSTRAINT_LEN (c, p)), c) | |
1071 | { | |
1072 | case '#': | |
1073 | case ',': | |
1074 | return op_class; | |
1075 | ||
55a2c322 | 1076 | case 'g': |
55a2c322 VM |
1077 | op_class = reg_class_subunion[op_class][GENERAL_REGS]; |
1078 | break; | |
f4eafc30 | 1079 | |
55a2c322 | 1080 | default: |
777e635f RS |
1081 | enum constraint_num cn = lookup_constraint (p); |
1082 | enum reg_class cl = reg_class_for_constraint (cn); | |
1083 | if (cl == NO_REGS) | |
55a2c322 | 1084 | { |
777e635f | 1085 | if (insn_extra_address_constraint (cn)) |
55a2c322 VM |
1086 | op_class |
1087 | = (reg_class_subunion | |
1088 | [op_class][base_reg_class (VOIDmode, ADDR_SPACE_GENERIC, | |
1089 | ADDRESS, SCRATCH)]); | |
55a2c322 VM |
1090 | break; |
1091 | } | |
f4eafc30 | 1092 | |
777e635f RS |
1093 | op_class = reg_class_subunion[op_class][cl]; |
1094 | break; | |
55a2c322 VM |
1095 | } |
1096 | while ((p += len), c); | |
1097 | return op_class; | |
1098 | } | |
1099 | ||
1100 | /* If OP is a register, return the class of the register as per | |
1101 | get_reg_class, otherwise return NO_REGS. */ | |
1102 | static inline enum reg_class | |
1103 | get_op_class (rtx op) | |
1104 | { | |
1105 | return REG_P (op) ? get_reg_class (REGNO (op)) : NO_REGS; | |
1106 | } | |
1107 | ||
1108 | /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo | |
1109 | otherwise. If modes of MEM_PSEUDO and VAL are different, use | |
1110 | SUBREG for VAL to make them equal. */ | |
cfa434f6 | 1111 | static rtx_insn * |
55a2c322 VM |
1112 | emit_spill_move (bool to_p, rtx mem_pseudo, rtx val) |
1113 | { | |
1114 | if (GET_MODE (mem_pseudo) != GET_MODE (val)) | |
2c62cbaa | 1115 | { |
cb1cca12 VM |
1116 | /* Usually size of mem_pseudo is greater than val size but in |
1117 | rare cases it can be less as it can be defined by target | |
1118 | dependent macro HARD_REGNO_CALLER_SAVE_MODE. */ | |
1ccd4874 VM |
1119 | if (! MEM_P (val)) |
1120 | { | |
54b84aa9 EB |
1121 | val = gen_lowpart_SUBREG (GET_MODE (mem_pseudo), |
1122 | GET_CODE (val) == SUBREG | |
1123 | ? SUBREG_REG (val) : val); | |
1ccd4874 VM |
1124 | LRA_SUBREG_P (val) = 1; |
1125 | } | |
1126 | else | |
1127 | { | |
1128 | mem_pseudo = gen_lowpart_SUBREG (GET_MODE (val), mem_pseudo); | |
1129 | LRA_SUBREG_P (mem_pseudo) = 1; | |
1130 | } | |
2c62cbaa | 1131 | } |
1476d1bd MM |
1132 | return to_p ? gen_move_insn (mem_pseudo, val) |
1133 | : gen_move_insn (val, mem_pseudo); | |
55a2c322 VM |
1134 | } |
1135 | ||
1136 | /* Process a special case insn (register move), return true if we | |
2c62cbaa | 1137 | don't need to process it anymore. INSN should be a single set |
f15643d4 RS |
1138 | insn. Set up that RTL was changed through CHANGE_P and that hook |
1139 | TARGET_SECONDARY_MEMORY_NEEDED says to use secondary memory through | |
2c62cbaa | 1140 | SEC_MEM_P. */ |
55a2c322 | 1141 | static bool |
2c62cbaa | 1142 | check_and_process_move (bool *change_p, bool *sec_mem_p ATTRIBUTE_UNUSED) |
55a2c322 VM |
1143 | { |
1144 | int sregno, dregno; | |
ef0006eb | 1145 | rtx dest, src, dreg, sreg, new_reg, scratch_reg; |
cfa434f6 | 1146 | rtx_insn *before; |
55a2c322 | 1147 | enum reg_class dclass, sclass, secondary_class; |
55a2c322 VM |
1148 | secondary_reload_info sri; |
1149 | ||
2c62cbaa VM |
1150 | lra_assert (curr_insn_set != NULL_RTX); |
1151 | dreg = dest = SET_DEST (curr_insn_set); | |
1152 | sreg = src = SET_SRC (curr_insn_set); | |
55a2c322 VM |
1153 | if (GET_CODE (dest) == SUBREG) |
1154 | dreg = SUBREG_REG (dest); | |
1155 | if (GET_CODE (src) == SUBREG) | |
1156 | sreg = SUBREG_REG (src); | |
1ccd4874 | 1157 | if (! (REG_P (dreg) || MEM_P (dreg)) || ! (REG_P (sreg) || MEM_P (sreg))) |
55a2c322 VM |
1158 | return false; |
1159 | sclass = dclass = NO_REGS; | |
55a2c322 VM |
1160 | if (REG_P (dreg)) |
1161 | dclass = get_reg_class (REGNO (dreg)); | |
48855443 | 1162 | gcc_assert (dclass < LIM_REG_CLASSES); |
55a2c322 VM |
1163 | if (dclass == ALL_REGS) |
1164 | /* ALL_REGS is used for new pseudos created by transformations | |
1165 | like reload of SUBREG_REG (see function | |
1166 | simplify_operand_subreg). We don't know their class yet. We | |
1167 | should figure out the class from processing the insn | |
1168 | constraints not in this fast path function. Even if ALL_REGS | |
1169 | were a right class for the pseudo, secondary_... hooks usually | |
1170 | are not define for ALL_REGS. */ | |
1171 | return false; | |
55a2c322 VM |
1172 | if (REG_P (sreg)) |
1173 | sclass = get_reg_class (REGNO (sreg)); | |
48855443 | 1174 | gcc_assert (sclass < LIM_REG_CLASSES); |
55a2c322 VM |
1175 | if (sclass == ALL_REGS) |
1176 | /* See comments above. */ | |
1177 | return false; | |
1ccd4874 VM |
1178 | if (sclass == NO_REGS && dclass == NO_REGS) |
1179 | return false; | |
f15643d4 | 1180 | if (targetm.secondary_memory_needed (GET_MODE (src), sclass, dclass) |
1ccd4874 | 1181 | && ((sclass != NO_REGS && dclass != NO_REGS) |
94e23f53 RS |
1182 | || (GET_MODE (src) |
1183 | != targetm.secondary_memory_needed_mode (GET_MODE (src))))) | |
55a2c322 VM |
1184 | { |
1185 | *sec_mem_p = true; | |
1186 | return false; | |
1187 | } | |
1ccd4874 VM |
1188 | if (! REG_P (dreg) || ! REG_P (sreg)) |
1189 | return false; | |
55a2c322 VM |
1190 | sri.prev_sri = NULL; |
1191 | sri.icode = CODE_FOR_nothing; | |
1192 | sri.extra_cost = 0; | |
1193 | secondary_class = NO_REGS; | |
1194 | /* Set up hard register for a reload pseudo for hook | |
1195 | secondary_reload because some targets just ignore unassigned | |
1196 | pseudos in the hook. */ | |
1197 | if (dclass != NO_REGS && lra_get_regno_hard_regno (REGNO (dreg)) < 0) | |
1198 | { | |
1199 | dregno = REGNO (dreg); | |
1200 | reg_renumber[dregno] = ira_class_hard_regs[dclass][0]; | |
1201 | } | |
1202 | else | |
1203 | dregno = -1; | |
1204 | if (sclass != NO_REGS && lra_get_regno_hard_regno (REGNO (sreg)) < 0) | |
1205 | { | |
1206 | sregno = REGNO (sreg); | |
1207 | reg_renumber[sregno] = ira_class_hard_regs[sclass][0]; | |
1208 | } | |
1209 | else | |
1210 | sregno = -1; | |
1211 | if (sclass != NO_REGS) | |
1212 | secondary_class | |
1213 | = (enum reg_class) targetm.secondary_reload (false, dest, | |
1214 | (reg_class_t) sclass, | |
1215 | GET_MODE (src), &sri); | |
1216 | if (sclass == NO_REGS | |
1217 | || ((secondary_class != NO_REGS || sri.icode != CODE_FOR_nothing) | |
1218 | && dclass != NO_REGS)) | |
1219 | { | |
55a2c322 VM |
1220 | enum reg_class old_sclass = secondary_class; |
1221 | secondary_reload_info old_sri = sri; | |
55a2c322 VM |
1222 | |
1223 | sri.prev_sri = NULL; | |
1224 | sri.icode = CODE_FOR_nothing; | |
1225 | sri.extra_cost = 0; | |
1226 | secondary_class | |
ef0006eb | 1227 | = (enum reg_class) targetm.secondary_reload (true, src, |
55a2c322 | 1228 | (reg_class_t) dclass, |
ef0006eb | 1229 | GET_MODE (src), &sri); |
55a2c322 VM |
1230 | /* Check the target hook consistency. */ |
1231 | lra_assert | |
1232 | ((secondary_class == NO_REGS && sri.icode == CODE_FOR_nothing) | |
1233 | || (old_sclass == NO_REGS && old_sri.icode == CODE_FOR_nothing) | |
1234 | || (secondary_class == old_sclass && sri.icode == old_sri.icode)); | |
1235 | } | |
1236 | if (sregno >= 0) | |
1237 | reg_renumber [sregno] = -1; | |
1238 | if (dregno >= 0) | |
1239 | reg_renumber [dregno] = -1; | |
1240 | if (secondary_class == NO_REGS && sri.icode == CODE_FOR_nothing) | |
1241 | return false; | |
1242 | *change_p = true; | |
1243 | new_reg = NULL_RTX; | |
1244 | if (secondary_class != NO_REGS) | |
ef0006eb | 1245 | new_reg = lra_create_new_reg_with_unique_value (GET_MODE (src), NULL_RTX, |
55a2c322 VM |
1246 | secondary_class, |
1247 | "secondary"); | |
1248 | start_sequence (); | |
55a2c322 | 1249 | if (sri.icode == CODE_FOR_nothing) |
ef0006eb | 1250 | lra_emit_move (new_reg, src); |
55a2c322 VM |
1251 | else |
1252 | { | |
1253 | enum reg_class scratch_class; | |
1254 | ||
1255 | scratch_class = (reg_class_from_constraints | |
1256 | (insn_data[sri.icode].operand[2].constraint)); | |
1257 | scratch_reg = (lra_create_new_reg_with_unique_value | |
1258 | (insn_data[sri.icode].operand[2].mode, NULL_RTX, | |
1259 | scratch_class, "scratch")); | |
1260 | emit_insn (GEN_FCN (sri.icode) (new_reg != NULL_RTX ? new_reg : dest, | |
ef0006eb | 1261 | src, scratch_reg)); |
55a2c322 VM |
1262 | } |
1263 | before = get_insns (); | |
1264 | end_sequence (); | |
cfa434f6 | 1265 | lra_process_new_insns (curr_insn, before, NULL, "Inserting the move"); |
55a2c322 | 1266 | if (new_reg != NULL_RTX) |
ef0006eb | 1267 | SET_SRC (curr_insn_set) = new_reg; |
55a2c322 VM |
1268 | else |
1269 | { | |
1270 | if (lra_dump_file != NULL) | |
1271 | { | |
1272 | fprintf (lra_dump_file, "Deleting move %u\n", INSN_UID (curr_insn)); | |
cfbeaedf | 1273 | dump_insn_slim (lra_dump_file, curr_insn); |
55a2c322 VM |
1274 | } |
1275 | lra_set_insn_deleted (curr_insn); | |
1276 | return true; | |
1277 | } | |
1278 | return false; | |
1279 | } | |
1280 | ||
1281 | /* The following data describe the result of process_alt_operands. | |
1282 | The data are used in curr_insn_transform to generate reloads. */ | |
1283 | ||
1284 | /* The chosen reg classes which should be used for the corresponding | |
1285 | operands. */ | |
1286 | static enum reg_class goal_alt[MAX_RECOG_OPERANDS]; | |
1287 | /* True if the operand should be the same as another operand and that | |
1288 | other operand does not need a reload. */ | |
1289 | static bool goal_alt_match_win[MAX_RECOG_OPERANDS]; | |
1290 | /* True if the operand does not need a reload. */ | |
1291 | static bool goal_alt_win[MAX_RECOG_OPERANDS]; | |
1292 | /* True if the operand can be offsetable memory. */ | |
1293 | static bool goal_alt_offmemok[MAX_RECOG_OPERANDS]; | |
1294 | /* The number of an operand to which given operand can be matched to. */ | |
1295 | static int goal_alt_matches[MAX_RECOG_OPERANDS]; | |
1296 | /* The number of elements in the following array. */ | |
1297 | static int goal_alt_dont_inherit_ops_num; | |
1298 | /* Numbers of operands whose reload pseudos should not be inherited. */ | |
1299 | static int goal_alt_dont_inherit_ops[MAX_RECOG_OPERANDS]; | |
1300 | /* True if the insn commutative operands should be swapped. */ | |
1301 | static bool goal_alt_swapped; | |
1302 | /* The chosen insn alternative. */ | |
1303 | static int goal_alt_number; | |
1304 | ||
987b67f1 VM |
1305 | /* True if the corresponding operand is the result of an equivalence |
1306 | substitution. */ | |
1307 | static bool equiv_substition_p[MAX_RECOG_OPERANDS]; | |
1308 | ||
55a2c322 VM |
1309 | /* The following five variables are used to choose the best insn |
1310 | alternative. They reflect final characteristics of the best | |
1311 | alternative. */ | |
1312 | ||
1313 | /* Number of necessary reloads and overall cost reflecting the | |
1314 | previous value and other unpleasantness of the best alternative. */ | |
1315 | static int best_losers, best_overall; | |
55a2c322 VM |
1316 | /* Overall number hard registers used for reloads. For example, on |
1317 | some targets we need 2 general registers to reload DFmode and only | |
1318 | one floating point register. */ | |
1319 | static int best_reload_nregs; | |
1320 | /* Overall number reflecting distances of previous reloading the same | |
1321 | value. The distances are counted from the current BB start. It is | |
1322 | used to improve inheritance chances. */ | |
1323 | static int best_reload_sum; | |
1324 | ||
1325 | /* True if the current insn should have no correspondingly input or | |
1326 | output reloads. */ | |
1327 | static bool no_input_reloads_p, no_output_reloads_p; | |
1328 | ||
1329 | /* True if we swapped the commutative operands in the current | |
1330 | insn. */ | |
1331 | static int curr_swapped; | |
1332 | ||
d9cf932c VM |
1333 | /* if CHECK_ONLY_P is false, arrange for address element *LOC to be a |
1334 | register of class CL. Add any input reloads to list BEFORE. AFTER | |
1335 | is nonnull if *LOC is an automodified value; handle that case by | |
1336 | adding the required output reloads to list AFTER. Return true if | |
1337 | the RTL was changed. | |
1338 | ||
1339 | if CHECK_ONLY_P is true, check that the *LOC is a correct address | |
1340 | register. Return false if the address register is correct. */ | |
55a2c322 | 1341 | static bool |
d9cf932c | 1342 | process_addr_reg (rtx *loc, bool check_only_p, rtx_insn **before, rtx_insn **after, |
cfa434f6 | 1343 | enum reg_class cl) |
55a2c322 VM |
1344 | { |
1345 | int regno; | |
1346 | enum reg_class rclass, new_class; | |
277f65de | 1347 | rtx reg; |
55a2c322 | 1348 | rtx new_reg; |
ef4bddc2 | 1349 | machine_mode mode; |
95921002 | 1350 | bool subreg_p, before_p = false; |
55a2c322 | 1351 | |
95921002 VM |
1352 | subreg_p = GET_CODE (*loc) == SUBREG; |
1353 | if (subreg_p) | |
ada2eb68 JW |
1354 | { |
1355 | reg = SUBREG_REG (*loc); | |
1356 | mode = GET_MODE (reg); | |
1357 | ||
1358 | /* For mode with size bigger than ptr_mode, there unlikely to be "mov" | |
1359 | between two registers with different classes, but there normally will | |
1360 | be "mov" which transfers element of vector register into the general | |
1361 | register, and this normally will be a subreg which should be reloaded | |
1362 | as a whole. This is particularly likely to be triggered when | |
1363 | -fno-split-wide-types specified. */ | |
3c11e1af JW |
1364 | if (!REG_P (reg) |
1365 | || in_class_p (reg, cl, &new_class) | |
cf098191 | 1366 | || known_le (GET_MODE_SIZE (mode), GET_MODE_SIZE (ptr_mode))) |
ada2eb68 JW |
1367 | loc = &SUBREG_REG (*loc); |
1368 | } | |
1369 | ||
277f65de | 1370 | reg = *loc; |
55a2c322 VM |
1371 | mode = GET_MODE (reg); |
1372 | if (! REG_P (reg)) | |
1373 | { | |
d9cf932c VM |
1374 | if (check_only_p) |
1375 | return true; | |
55a2c322 VM |
1376 | /* Always reload memory in an address even if the target supports |
1377 | such addresses. */ | |
1378 | new_reg = lra_create_new_reg_with_unique_value (mode, reg, cl, "address"); | |
1379 | before_p = true; | |
1380 | } | |
1381 | else | |
1382 | { | |
1383 | regno = REGNO (reg); | |
1384 | rclass = get_reg_class (regno); | |
d9cf932c VM |
1385 | if (! check_only_p |
1386 | && (*loc = get_equiv_with_elimination (reg, curr_insn)) != reg) | |
55a2c322 VM |
1387 | { |
1388 | if (lra_dump_file != NULL) | |
1389 | { | |
1390 | fprintf (lra_dump_file, | |
1391 | "Changing pseudo %d in address of insn %u on equiv ", | |
1392 | REGNO (reg), INSN_UID (curr_insn)); | |
cfbeaedf | 1393 | dump_value_slim (lra_dump_file, *loc, 1); |
55a2c322 VM |
1394 | fprintf (lra_dump_file, "\n"); |
1395 | } | |
1396 | *loc = copy_rtx (*loc); | |
1397 | } | |
1398 | if (*loc != reg || ! in_class_p (reg, cl, &new_class)) | |
1399 | { | |
d9cf932c VM |
1400 | if (check_only_p) |
1401 | return true; | |
55a2c322 VM |
1402 | reg = *loc; |
1403 | if (get_reload_reg (after == NULL ? OP_IN : OP_INOUT, | |
95921002 | 1404 | mode, reg, cl, subreg_p, "address", &new_reg)) |
55a2c322 VM |
1405 | before_p = true; |
1406 | } | |
1407 | else if (new_class != NO_REGS && rclass != new_class) | |
1408 | { | |
d9cf932c VM |
1409 | if (check_only_p) |
1410 | return true; | |
a2d0d374 | 1411 | lra_change_class (regno, new_class, " Change to", true); |
55a2c322 VM |
1412 | return false; |
1413 | } | |
1414 | else | |
1415 | return false; | |
1416 | } | |
1417 | if (before_p) | |
1418 | { | |
1419 | push_to_sequence (*before); | |
1420 | lra_emit_move (new_reg, reg); | |
1421 | *before = get_insns (); | |
1422 | end_sequence (); | |
1423 | } | |
1424 | *loc = new_reg; | |
1425 | if (after != NULL) | |
1426 | { | |
1427 | start_sequence (); | |
9a9fe2b4 | 1428 | lra_emit_move (before_p ? copy_rtx (reg) : reg, new_reg); |
55a2c322 VM |
1429 | emit_insn (*after); |
1430 | *after = get_insns (); | |
1431 | end_sequence (); | |
1432 | } | |
1433 | return true; | |
1434 | } | |
1435 | ||
4f0bee4c WM |
1436 | /* Insert move insn in simplify_operand_subreg. BEFORE returns |
1437 | the insn to be inserted before curr insn. AFTER returns the | |
1438 | the insn to be inserted after curr insn. ORIGREG and NEWREG | |
1439 | are the original reg and new reg for reload. */ | |
1440 | static void | |
cfa434f6 DM |
1441 | insert_move_for_subreg (rtx_insn **before, rtx_insn **after, rtx origreg, |
1442 | rtx newreg) | |
4f0bee4c WM |
1443 | { |
1444 | if (before) | |
1445 | { | |
1446 | push_to_sequence (*before); | |
1447 | lra_emit_move (newreg, origreg); | |
1448 | *before = get_insns (); | |
1449 | end_sequence (); | |
1450 | } | |
1451 | if (after) | |
1452 | { | |
1453 | start_sequence (); | |
1454 | lra_emit_move (origreg, newreg); | |
1455 | emit_insn (*after); | |
1456 | *after = get_insns (); | |
1457 | end_sequence (); | |
1458 | } | |
1459 | } | |
1460 | ||
ef4bddc2 | 1461 | static int valid_address_p (machine_mode mode, rtx addr, addr_space_t as); |
ab5d2233 | 1462 | static bool process_address (int, bool, rtx_insn **, rtx_insn **); |
ba38538f | 1463 | |
55a2c322 VM |
1464 | /* Make reloads for subreg in operand NOP with internal subreg mode |
1465 | REG_MODE, add new reloads for further processing. Return true if | |
895ff86f | 1466 | any change was done. */ |
55a2c322 | 1467 | static bool |
ef4bddc2 | 1468 | simplify_operand_subreg (int nop, machine_mode reg_mode) |
55a2c322 VM |
1469 | { |
1470 | int hard_regno; | |
cfa434f6 | 1471 | rtx_insn *before, *after; |
895ff86f | 1472 | machine_mode mode, innermode; |
55a2c322 VM |
1473 | rtx reg, new_reg; |
1474 | rtx operand = *curr_id->operand_loc[nop]; | |
4f0bee4c WM |
1475 | enum reg_class regclass; |
1476 | enum op_type type; | |
55a2c322 | 1477 | |
cfa434f6 | 1478 | before = after = NULL; |
55a2c322 VM |
1479 | |
1480 | if (GET_CODE (operand) != SUBREG) | |
1481 | return false; | |
f4eafc30 | 1482 | |
55a2c322 VM |
1483 | mode = GET_MODE (operand); |
1484 | reg = SUBREG_REG (operand); | |
895ff86f | 1485 | innermode = GET_MODE (reg); |
4f0bee4c | 1486 | type = curr_static_id->operand[nop].type; |
2e186411 | 1487 | if (MEM_P (reg)) |
ba38538f | 1488 | { |
ab5d2233 EB |
1489 | const bool addr_was_valid |
1490 | = valid_address_p (innermode, XEXP (reg, 0), MEM_ADDR_SPACE (reg)); | |
ba38538f | 1491 | alter_subreg (curr_id->operand_loc[nop], false); |
ab5d2233 | 1492 | rtx subst = *curr_id->operand_loc[nop]; |
ba38538f | 1493 | lra_assert (MEM_P (subst)); |
ab5d2233 EB |
1494 | |
1495 | if (!addr_was_valid | |
ba38538f | 1496 | || valid_address_p (GET_MODE (subst), XEXP (subst, 0), |
2e186411 AM |
1497 | MEM_ADDR_SPACE (subst)) |
1498 | || ((get_constraint_type (lookup_constraint | |
1499 | (curr_static_id->operand[nop].constraint)) | |
1500 | != CT_SPECIAL_MEMORY) | |
1501 | /* We still can reload address and if the address is | |
1502 | valid, we can remove subreg without reloading its | |
1503 | inner memory. */ | |
1504 | && valid_address_p (GET_MODE (subst), | |
1505 | regno_reg_rtx | |
1506 | [ira_class_hard_regs | |
1507 | [base_reg_class (GET_MODE (subst), | |
1508 | MEM_ADDR_SPACE (subst), | |
1509 | ADDRESS, SCRATCH)][0]], | |
1510 | MEM_ADDR_SPACE (subst)))) | |
1511 | { | |
ab5d2233 | 1512 | /* If we change the address for a paradoxical subreg of memory, the |
849fccf8 EB |
1513 | new address might violate the necessary alignment or the access |
1514 | might be slow; take this into consideration. We need not worry | |
ab5d2233 | 1515 | about accesses beyond allocated memory for paradoxical memory |
2e186411 AM |
1516 | subregs as we don't substitute such equiv memory (see processing |
1517 | equivalences in function lra_constraints) and because for spilled | |
1518 | pseudos we allocate stack memory enough for the biggest | |
198075e1 MF |
1519 | corresponding paradoxical subreg. |
1520 | ||
1521 | However, do not blindly simplify a (subreg (mem ...)) for | |
1522 | WORD_REGISTER_OPERATIONS targets as this may lead to loading junk | |
1523 | data into a register when the inner is narrower than outer or | |
1524 | missing important data from memory when the inner is wider than | |
1525 | outer. This rule only applies to modes that are no wider than | |
1526 | a word. */ | |
bb94ec76 RS |
1527 | if (!(maybe_ne (GET_MODE_PRECISION (mode), |
1528 | GET_MODE_PRECISION (innermode)) | |
cf098191 RS |
1529 | && known_le (GET_MODE_SIZE (mode), UNITS_PER_WORD) |
1530 | && known_le (GET_MODE_SIZE (innermode), UNITS_PER_WORD) | |
198075e1 MF |
1531 | && WORD_REGISTER_OPERATIONS) |
1532 | && (!(MEM_ALIGN (subst) < GET_MODE_ALIGNMENT (mode) | |
e0bd6c9f | 1533 | && targetm.slow_unaligned_access (mode, MEM_ALIGN (subst))) |
198075e1 | 1534 | || (MEM_ALIGN (reg) < GET_MODE_ALIGNMENT (innermode) |
e0bd6c9f RS |
1535 | && targetm.slow_unaligned_access (innermode, |
1536 | MEM_ALIGN (reg))))) | |
2e186411 AM |
1537 | return true; |
1538 | ||
ab5d2233 EB |
1539 | *curr_id->operand_loc[nop] = operand; |
1540 | ||
1541 | /* But if the address was not valid, we cannot reload the MEM without | |
1542 | reloading the address first. */ | |
1543 | if (!addr_was_valid) | |
1544 | process_address (nop, false, &before, &after); | |
1545 | ||
2e186411 AM |
1546 | /* INNERMODE is fast, MODE slow. Reload the mem in INNERMODE. */ |
1547 | enum reg_class rclass | |
1548 | = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS); | |
ab5d2233 EB |
1549 | if (get_reload_reg (curr_static_id->operand[nop].type, innermode, |
1550 | reg, rclass, TRUE, "slow mem", &new_reg)) | |
2e186411 AM |
1551 | { |
1552 | bool insert_before, insert_after; | |
1553 | bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg)); | |
1554 | ||
1555 | insert_before = (type != OP_OUT | |
bd4288c0 | 1556 | || partial_subreg_p (mode, innermode)); |
2e186411 AM |
1557 | insert_after = type != OP_IN; |
1558 | insert_move_for_subreg (insert_before ? &before : NULL, | |
1559 | insert_after ? &after : NULL, | |
1560 | reg, new_reg); | |
1561 | } | |
2e186411 AM |
1562 | SUBREG_REG (operand) = new_reg; |
1563 | ||
1564 | /* Convert to MODE. */ | |
1565 | reg = operand; | |
ab5d2233 EB |
1566 | rclass |
1567 | = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS); | |
2e186411 AM |
1568 | if (get_reload_reg (curr_static_id->operand[nop].type, mode, reg, |
1569 | rclass, TRUE, "slow mem", &new_reg)) | |
1570 | { | |
1571 | bool insert_before, insert_after; | |
1572 | bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg)); | |
1573 | ||
1574 | insert_before = type != OP_OUT; | |
1575 | insert_after = type != OP_IN; | |
1576 | insert_move_for_subreg (insert_before ? &before : NULL, | |
1577 | insert_after ? &after : NULL, | |
1578 | reg, new_reg); | |
1579 | } | |
1580 | *curr_id->operand_loc[nop] = new_reg; | |
1581 | lra_process_new_insns (curr_insn, before, after, | |
1582 | "Inserting slow mem reload"); | |
1583 | return true; | |
1584 | } | |
95831c01 | 1585 | |
ba38538f VM |
1586 | /* If the address was valid and became invalid, prefer to reload |
1587 | the memory. Typical case is when the index scale should | |
1588 | correspond the memory. */ | |
2e186411 | 1589 | *curr_id->operand_loc[nop] = operand; |
77850e96 MF |
1590 | /* Do not return false here as the MEM_P (reg) will be processed |
1591 | later in this function. */ | |
ba38538f VM |
1592 | } |
1593 | else if (REG_P (reg) && REGNO (reg) < FIRST_PSEUDO_REGISTER) | |
55a2c322 VM |
1594 | { |
1595 | alter_subreg (curr_id->operand_loc[nop], false); | |
1596 | return true; | |
1597 | } | |
895ff86f VM |
1598 | else if (CONSTANT_P (reg)) |
1599 | { | |
1600 | /* Try to simplify subreg of constant. It is usually result of | |
1601 | equivalence substitution. */ | |
1602 | if (innermode == VOIDmode | |
1603 | && (innermode = original_subreg_reg_mode[nop]) == VOIDmode) | |
1604 | innermode = curr_static_id->operand[nop].mode; | |
1605 | if ((new_reg = simplify_subreg (mode, reg, innermode, | |
1606 | SUBREG_BYTE (operand))) != NULL_RTX) | |
1607 | { | |
1608 | *curr_id->operand_loc[nop] = new_reg; | |
1609 | return true; | |
1610 | } | |
1611 | } | |
55a2c322 VM |
1612 | /* Put constant into memory when we have mixed modes. It generates |
1613 | a better code in most cases as it does not need a secondary | |
1614 | reload memory. It also prevents LRA looping when LRA is using | |
1615 | secondary reload memory again and again. */ | |
1616 | if (CONSTANT_P (reg) && CONST_POOL_OK_P (reg_mode, reg) | |
1617 | && SCALAR_INT_MODE_P (reg_mode) != SCALAR_INT_MODE_P (mode)) | |
1618 | { | |
1619 | SUBREG_REG (operand) = force_const_mem (reg_mode, reg); | |
1620 | alter_subreg (curr_id->operand_loc[nop], false); | |
1621 | return true; | |
1622 | } | |
1623 | /* Force a reload of the SUBREG_REG if this is a constant or PLUS or | |
1624 | if there may be a problem accessing OPERAND in the outer | |
1625 | mode. */ | |
1626 | if ((REG_P (reg) | |
1627 | && REGNO (reg) >= FIRST_PSEUDO_REGISTER | |
1628 | && (hard_regno = lra_get_regno_hard_regno (REGNO (reg))) >= 0 | |
1629 | /* Don't reload paradoxical subregs because we could be looping | |
1630 | having repeatedly final regno out of hard regs range. */ | |
ad474626 RS |
1631 | && (hard_regno_nregs (hard_regno, innermode) |
1632 | >= hard_regno_nregs (hard_regno, mode)) | |
895ff86f | 1633 | && simplify_subreg_regno (hard_regno, innermode, |
2c62cbaa VM |
1634 | SUBREG_BYTE (operand), mode) < 0 |
1635 | /* Don't reload subreg for matching reload. It is actually | |
1636 | valid subreg in LRA. */ | |
1637 | && ! LRA_SUBREG_P (operand)) | |
55a2c322 VM |
1638 | || CONSTANT_P (reg) || GET_CODE (reg) == PLUS || MEM_P (reg)) |
1639 | { | |
6e23f296 VM |
1640 | enum reg_class rclass; |
1641 | ||
7613fa50 VM |
1642 | if (REG_P (reg)) |
1643 | /* There is a big probability that we will get the same class | |
6e23f296 VM |
1644 | for the new pseudo and we will get the same insn which |
1645 | means infinite looping. So spill the new pseudo. */ | |
1646 | rclass = NO_REGS; | |
1647 | else | |
1648 | /* The class will be defined later in curr_insn_transform. */ | |
1649 | rclass | |
1650 | = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS); | |
55a2c322 | 1651 | |
25bb0bb5 | 1652 | if (get_reload_reg (curr_static_id->operand[nop].type, reg_mode, reg, |
95921002 | 1653 | rclass, TRUE, "subreg reg", &new_reg)) |
55a2c322 | 1654 | { |
4f0bee4c | 1655 | bool insert_before, insert_after; |
2b778c9d | 1656 | bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg)); |
4f0bee4c WM |
1657 | |
1658 | insert_before = (type != OP_OUT | |
9eaf97d6 | 1659 | || read_modify_subreg_p (operand)); |
4f0bee4c WM |
1660 | insert_after = (type != OP_IN); |
1661 | insert_move_for_subreg (insert_before ? &before : NULL, | |
1662 | insert_after ? &after : NULL, | |
1663 | reg, new_reg); | |
55a2c322 VM |
1664 | } |
1665 | SUBREG_REG (operand) = new_reg; | |
1666 | lra_process_new_insns (curr_insn, before, after, | |
1667 | "Inserting subreg reload"); | |
1668 | return true; | |
1669 | } | |
4f0bee4c WM |
1670 | /* Force a reload for a paradoxical subreg. For paradoxical subreg, |
1671 | IRA allocates hardreg to the inner pseudo reg according to its mode | |
1672 | instead of the outermode, so the size of the hardreg may not be enough | |
1673 | to contain the outermode operand, in that case we may need to insert | |
1674 | reload for the reg. For the following two types of paradoxical subreg, | |
1675 | we need to insert reload: | |
1676 | 1. If the op_type is OP_IN, and the hardreg could not be paired with | |
1677 | other hardreg to contain the outermode operand | |
1678 | (checked by in_hard_reg_set_p), we need to insert the reload. | |
1679 | 2. If the op_type is OP_OUT or OP_INOUT. | |
1680 | ||
1681 | Here is a paradoxical subreg example showing how the reload is generated: | |
1682 | ||
1683 | (insn 5 4 7 2 (set (reg:TI 106 [ __comp ]) | |
1684 | (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64} | |
1685 | ||
1686 | In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example | |
1687 | here, if reg107 is assigned to hardreg R15, because R15 is the last | |
1688 | hardreg, compiler cannot find another hardreg to pair with R15 to | |
1689 | contain TImode data. So we insert a TImode reload reg180 for it. | |
1690 | After reload is inserted: | |
1691 | ||
1692 | (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0) | |
1693 | (reg:DI 107 [ __comp ])) -1 | |
1694 | (insn 5 4 7 2 (set (reg:TI 106 [ __comp ]) | |
1695 | (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64} | |
1696 | ||
1697 | Two reload hard registers will be allocated to reg180 to save TImode data | |
8fd96632 RS |
1698 | in LRA_assign. |
1699 | ||
1700 | For LRA pseudos this should normally be handled by the biggest_mode | |
1701 | mechanism. However, it's possible for new uses of an LRA pseudo | |
1702 | to be introduced after we've allocated it, such as when undoing | |
1703 | inheritance, and the allocated register might not then be appropriate | |
1704 | for the new uses. */ | |
4f0bee4c WM |
1705 | else if (REG_P (reg) |
1706 | && REGNO (reg) >= FIRST_PSEUDO_REGISTER | |
1707 | && (hard_regno = lra_get_regno_hard_regno (REGNO (reg))) >= 0 | |
ad474626 RS |
1708 | && (hard_regno_nregs (hard_regno, innermode) |
1709 | < hard_regno_nregs (hard_regno, mode)) | |
4f0bee4c WM |
1710 | && (regclass = lra_get_allocno_class (REGNO (reg))) |
1711 | && (type != OP_IN | |
1712 | || !in_hard_reg_set_p (reg_class_contents[regclass], | |
8fd96632 RS |
1713 | mode, hard_regno) |
1714 | || overlaps_hard_reg_set_p (lra_no_alloc_regs, | |
1715 | mode, hard_regno))) | |
4f0bee4c WM |
1716 | { |
1717 | /* The class will be defined later in curr_insn_transform. */ | |
1718 | enum reg_class rclass | |
1719 | = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS); | |
1720 | ||
1721 | if (get_reload_reg (curr_static_id->operand[nop].type, mode, reg, | |
95921002 | 1722 | rclass, TRUE, "paradoxical subreg", &new_reg)) |
4f0bee4c WM |
1723 | { |
1724 | rtx subreg; | |
1725 | bool insert_before, insert_after; | |
1726 | ||
1727 | PUT_MODE (new_reg, mode); | |
ea09f50d | 1728 | subreg = gen_lowpart_SUBREG (innermode, new_reg); |
4f0bee4c WM |
1729 | bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg)); |
1730 | ||
1731 | insert_before = (type != OP_OUT); | |
1732 | insert_after = (type != OP_IN); | |
1733 | insert_move_for_subreg (insert_before ? &before : NULL, | |
1734 | insert_after ? &after : NULL, | |
1735 | reg, subreg); | |
1736 | } | |
1737 | SUBREG_REG (operand) = new_reg; | |
1738 | lra_process_new_insns (curr_insn, before, after, | |
1739 | "Inserting paradoxical subreg reload"); | |
1740 | return true; | |
1741 | } | |
55a2c322 VM |
1742 | return false; |
1743 | } | |
1744 | ||
1745 | /* Return TRUE if X refers for a hard register from SET. */ | |
1746 | static bool | |
1747 | uses_hard_regs_p (rtx x, HARD_REG_SET set) | |
1748 | { | |
1749 | int i, j, x_hard_regno; | |
ef4bddc2 | 1750 | machine_mode mode; |
55a2c322 VM |
1751 | const char *fmt; |
1752 | enum rtx_code code; | |
1753 | ||
1754 | if (x == NULL_RTX) | |
1755 | return false; | |
1756 | code = GET_CODE (x); | |
1757 | mode = GET_MODE (x); | |
1758 | if (code == SUBREG) | |
1759 | { | |
bd5a2c67 | 1760 | mode = wider_subreg_mode (x); |
55a2c322 VM |
1761 | x = SUBREG_REG (x); |
1762 | code = GET_CODE (x); | |
55a2c322 | 1763 | } |
f4eafc30 | 1764 | |
55a2c322 VM |
1765 | if (REG_P (x)) |
1766 | { | |
1686923c | 1767 | x_hard_regno = get_hard_regno (x, true); |
55a2c322 VM |
1768 | return (x_hard_regno >= 0 |
1769 | && overlaps_hard_reg_set_p (set, mode, x_hard_regno)); | |
1770 | } | |
1771 | if (MEM_P (x)) | |
1772 | { | |
277f65de | 1773 | struct address_info ad; |
55a2c322 | 1774 | |
277f65de RS |
1775 | decompose_mem_address (&ad, x); |
1776 | if (ad.base_term != NULL && uses_hard_regs_p (*ad.base_term, set)) | |
1777 | return true; | |
1778 | if (ad.index_term != NULL && uses_hard_regs_p (*ad.index_term, set)) | |
1779 | return true; | |
55a2c322 VM |
1780 | } |
1781 | fmt = GET_RTX_FORMAT (code); | |
1782 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1783 | { | |
1784 | if (fmt[i] == 'e') | |
1785 | { | |
1786 | if (uses_hard_regs_p (XEXP (x, i), set)) | |
1787 | return true; | |
1788 | } | |
1789 | else if (fmt[i] == 'E') | |
1790 | { | |
1791 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
1792 | if (uses_hard_regs_p (XVECEXP (x, i, j), set)) | |
1793 | return true; | |
1794 | } | |
1795 | } | |
1796 | return false; | |
1797 | } | |
1798 | ||
1799 | /* Return true if OP is a spilled pseudo. */ | |
1800 | static inline bool | |
1801 | spilled_pseudo_p (rtx op) | |
1802 | { | |
1803 | return (REG_P (op) | |
1804 | && REGNO (op) >= FIRST_PSEUDO_REGISTER && in_mem_p (REGNO (op))); | |
1805 | } | |
1806 | ||
1807 | /* Return true if X is a general constant. */ | |
1808 | static inline bool | |
1809 | general_constant_p (rtx x) | |
1810 | { | |
1811 | return CONSTANT_P (x) && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (x)); | |
1812 | } | |
1813 | ||
2c62cbaa VM |
1814 | static bool |
1815 | reg_in_class_p (rtx reg, enum reg_class cl) | |
1816 | { | |
1817 | if (cl == NO_REGS) | |
1818 | return get_reg_class (REGNO (reg)) == NO_REGS; | |
1819 | return in_class_p (reg, cl, NULL); | |
1820 | } | |
1821 | ||
3c954213 VM |
1822 | /* Return true if SET of RCLASS contains no hard regs which can be |
1823 | used in MODE. */ | |
1824 | static bool | |
1825 | prohibited_class_reg_set_mode_p (enum reg_class rclass, | |
1826 | HARD_REG_SET &set, | |
b8506a8a | 1827 | machine_mode mode) |
3c954213 VM |
1828 | { |
1829 | HARD_REG_SET temp; | |
1830 | ||
c07ad89a | 1831 | lra_assert (hard_reg_set_subset_p (reg_class_contents[rclass], set)); |
3c954213 VM |
1832 | COPY_HARD_REG_SET (temp, set); |
1833 | AND_COMPL_HARD_REG_SET (temp, lra_no_alloc_regs); | |
1834 | return (hard_reg_set_subset_p | |
1835 | (temp, ira_prohibited_class_mode_regs[rclass][mode])); | |
1836 | } | |
1837 | ||
9b195552 VM |
1838 | |
1839 | /* Used to check validity info about small class input operands. It | |
1840 | should be incremented at start of processing an insn | |
1841 | alternative. */ | |
1842 | static unsigned int curr_small_class_check = 0; | |
1843 | ||
1844 | /* Update number of used inputs of class OP_CLASS for operand NOP. | |
1845 | Return true if we have more such class operands than the number of | |
1846 | available regs. */ | |
1847 | static bool | |
1848 | update_and_check_small_class_inputs (int nop, enum reg_class op_class) | |
1849 | { | |
1850 | static unsigned int small_class_check[LIM_REG_CLASSES]; | |
1851 | static int small_class_input_nums[LIM_REG_CLASSES]; | |
1852 | ||
1853 | if (SMALL_REGISTER_CLASS_P (op_class) | |
1854 | /* We are interesting in classes became small because of fixing | |
1855 | some hard regs, e.g. by an user through GCC options. */ | |
1856 | && hard_reg_set_intersect_p (reg_class_contents[op_class], | |
1857 | ira_no_alloc_regs) | |
1858 | && (curr_static_id->operand[nop].type != OP_OUT | |
1859 | || curr_static_id->operand[nop].early_clobber)) | |
1860 | { | |
1861 | if (small_class_check[op_class] == curr_small_class_check) | |
1862 | small_class_input_nums[op_class]++; | |
1863 | else | |
1864 | { | |
1865 | small_class_check[op_class] = curr_small_class_check; | |
1866 | small_class_input_nums[op_class] = 1; | |
1867 | } | |
1868 | if (small_class_input_nums[op_class] > ira_class_hard_regs_num[op_class]) | |
1869 | return true; | |
1870 | } | |
1871 | return false; | |
1872 | } | |
1873 | ||
55a2c322 VM |
1874 | /* Major function to choose the current insn alternative and what |
1875 | operands should be reloaded and how. If ONLY_ALTERNATIVE is not | |
1876 | negative we should consider only this alternative. Return false if | |
1877 | we can not choose the alternative or find how to reload the | |
1878 | operands. */ | |
1879 | static bool | |
1880 | process_alt_operands (int only_alternative) | |
1881 | { | |
1882 | bool ok_p = false; | |
36ff9dfb | 1883 | int nop, overall, nalt; |
55a2c322 VM |
1884 | int n_alternatives = curr_static_id->n_alternatives; |
1885 | int n_operands = curr_static_id->n_operands; | |
1886 | /* LOSERS counts the operands that don't fit this alternative and | |
1887 | would require loading. */ | |
1888 | int losers; | |
feca7b89 | 1889 | int addr_losers; |
55a2c322 VM |
1890 | /* REJECT is a count of how undesirable this alternative says it is |
1891 | if any reloading is required. If the alternative matches exactly | |
1892 | then REJECT is ignored, but otherwise it gets this much counted | |
1893 | against it in addition to the reloading needed. */ | |
1894 | int reject; | |
feca7b89 VM |
1895 | /* This is defined by '!' or '?' alternative constraint and added to |
1896 | reject. But in some cases it can be ignored. */ | |
1897 | int static_reject; | |
d1457701 | 1898 | int op_reject; |
55a2c322 VM |
1899 | /* The number of elements in the following array. */ |
1900 | int early_clobbered_regs_num; | |
1901 | /* Numbers of operands which are early clobber registers. */ | |
1902 | int early_clobbered_nops[MAX_RECOG_OPERANDS]; | |
1903 | enum reg_class curr_alt[MAX_RECOG_OPERANDS]; | |
1904 | HARD_REG_SET curr_alt_set[MAX_RECOG_OPERANDS]; | |
1905 | bool curr_alt_match_win[MAX_RECOG_OPERANDS]; | |
1906 | bool curr_alt_win[MAX_RECOG_OPERANDS]; | |
1907 | bool curr_alt_offmemok[MAX_RECOG_OPERANDS]; | |
1908 | int curr_alt_matches[MAX_RECOG_OPERANDS]; | |
1909 | /* The number of elements in the following array. */ | |
1910 | int curr_alt_dont_inherit_ops_num; | |
1911 | /* Numbers of operands whose reload pseudos should not be inherited. */ | |
1912 | int curr_alt_dont_inherit_ops[MAX_RECOG_OPERANDS]; | |
1913 | rtx op; | |
1914 | /* The register when the operand is a subreg of register, otherwise the | |
1915 | operand itself. */ | |
1916 | rtx no_subreg_reg_operand[MAX_RECOG_OPERANDS]; | |
1917 | /* The register if the operand is a register or subreg of register, | |
1918 | otherwise NULL. */ | |
1919 | rtx operand_reg[MAX_RECOG_OPERANDS]; | |
1920 | int hard_regno[MAX_RECOG_OPERANDS]; | |
ef4bddc2 | 1921 | machine_mode biggest_mode[MAX_RECOG_OPERANDS]; |
55a2c322 VM |
1922 | int reload_nregs, reload_sum; |
1923 | bool costly_p; | |
1924 | enum reg_class cl; | |
1925 | ||
1926 | /* Calculate some data common for all alternatives to speed up the | |
1927 | function. */ | |
1928 | for (nop = 0; nop < n_operands; nop++) | |
1929 | { | |
7214306b VM |
1930 | rtx reg; |
1931 | ||
55a2c322 VM |
1932 | op = no_subreg_reg_operand[nop] = *curr_id->operand_loc[nop]; |
1933 | /* The real hard regno of the operand after the allocation. */ | |
1686923c | 1934 | hard_regno[nop] = get_hard_regno (op, true); |
f4eafc30 | 1935 | |
7214306b VM |
1936 | operand_reg[nop] = reg = op; |
1937 | biggest_mode[nop] = GET_MODE (op); | |
1938 | if (GET_CODE (op) == SUBREG) | |
55a2c322 | 1939 | { |
bd5a2c67 | 1940 | biggest_mode[nop] = wider_subreg_mode (op); |
7214306b | 1941 | operand_reg[nop] = reg = SUBREG_REG (op); |
55a2c322 | 1942 | } |
7214306b | 1943 | if (! REG_P (reg)) |
55a2c322 | 1944 | operand_reg[nop] = NULL_RTX; |
7214306b VM |
1945 | else if (REGNO (reg) >= FIRST_PSEUDO_REGISTER |
1946 | || ((int) REGNO (reg) | |
1947 | == lra_get_elimination_hard_regno (REGNO (reg)))) | |
1948 | no_subreg_reg_operand[nop] = reg; | |
1949 | else | |
1950 | operand_reg[nop] = no_subreg_reg_operand[nop] | |
1951 | /* Just use natural mode for elimination result. It should | |
1952 | be enough for extra constraints hooks. */ | |
1953 | = regno_reg_rtx[hard_regno[nop]]; | |
55a2c322 VM |
1954 | } |
1955 | ||
1956 | /* The constraints are made of several alternatives. Each operand's | |
1957 | constraint looks like foo,bar,... with commas separating the | |
1958 | alternatives. The first alternatives for all operands go | |
1959 | together, the second alternatives go together, etc. | |
1960 | ||
1961 | First loop over alternatives. */ | |
9840b2fa | 1962 | alternative_mask preferred = curr_id->preferred_alternatives; |
4cc8d9d2 | 1963 | if (only_alternative >= 0) |
9840b2fa | 1964 | preferred &= ALTERNATIVE_BIT (only_alternative); |
4cc8d9d2 | 1965 | |
55a2c322 VM |
1966 | for (nalt = 0; nalt < n_alternatives; nalt++) |
1967 | { | |
1968 | /* Loop over operands for one constraint alternative. */ | |
9840b2fa | 1969 | if (!TEST_BIT (preferred, nalt)) |
55a2c322 VM |
1970 | continue; |
1971 | ||
dbe7895c | 1972 | bool matching_early_clobber[MAX_RECOG_OPERANDS]; |
9b195552 | 1973 | curr_small_class_check++; |
feca7b89 VM |
1974 | overall = losers = addr_losers = 0; |
1975 | static_reject = reject = reload_nregs = reload_sum = 0; | |
55a2c322 | 1976 | for (nop = 0; nop < n_operands; nop++) |
cb1cca12 VM |
1977 | { |
1978 | int inc = (curr_static_id | |
1979 | ->operand_alternative[nalt * n_operands + nop].reject); | |
1980 | if (lra_dump_file != NULL && inc != 0) | |
1981 | fprintf (lra_dump_file, | |
1982 | " Staticly defined alt reject+=%d\n", inc); | |
feca7b89 | 1983 | static_reject += inc; |
dbe7895c | 1984 | matching_early_clobber[nop] = 0; |
cb1cca12 | 1985 | } |
feca7b89 | 1986 | reject += static_reject; |
55a2c322 VM |
1987 | early_clobbered_regs_num = 0; |
1988 | ||
1989 | for (nop = 0; nop < n_operands; nop++) | |
1990 | { | |
1991 | const char *p; | |
1992 | char *end; | |
1993 | int len, c, m, i, opalt_num, this_alternative_matches; | |
1994 | bool win, did_match, offmemok, early_clobber_p; | |
1995 | /* false => this operand can be reloaded somehow for this | |
1996 | alternative. */ | |
1997 | bool badop; | |
1998 | /* true => this operand can be reloaded if the alternative | |
1999 | allows regs. */ | |
2000 | bool winreg; | |
2001 | /* True if a constant forced into memory would be OK for | |
2002 | this operand. */ | |
2003 | bool constmemok; | |
2004 | enum reg_class this_alternative, this_costly_alternative; | |
2005 | HARD_REG_SET this_alternative_set, this_costly_alternative_set; | |
2006 | bool this_alternative_match_win, this_alternative_win; | |
2007 | bool this_alternative_offmemok; | |
80f466c4 | 2008 | bool scratch_p; |
ef4bddc2 | 2009 | machine_mode mode; |
777e635f | 2010 | enum constraint_num cn; |
55a2c322 VM |
2011 | |
2012 | opalt_num = nalt * n_operands + nop; | |
2013 | if (curr_static_id->operand_alternative[opalt_num].anything_ok) | |
2014 | { | |
2015 | /* Fast track for no constraints at all. */ | |
2016 | curr_alt[nop] = NO_REGS; | |
2017 | CLEAR_HARD_REG_SET (curr_alt_set[nop]); | |
2018 | curr_alt_win[nop] = true; | |
2019 | curr_alt_match_win[nop] = false; | |
2020 | curr_alt_offmemok[nop] = false; | |
2021 | curr_alt_matches[nop] = -1; | |
2022 | continue; | |
2023 | } | |
f4eafc30 | 2024 | |
55a2c322 VM |
2025 | op = no_subreg_reg_operand[nop]; |
2026 | mode = curr_operand_mode[nop]; | |
2027 | ||
2028 | win = did_match = winreg = offmemok = constmemok = false; | |
2029 | badop = true; | |
f4eafc30 | 2030 | |
55a2c322 VM |
2031 | early_clobber_p = false; |
2032 | p = curr_static_id->operand_alternative[opalt_num].constraint; | |
f4eafc30 | 2033 | |
55a2c322 VM |
2034 | this_costly_alternative = this_alternative = NO_REGS; |
2035 | /* We update set of possible hard regs besides its class | |
2036 | because reg class might be inaccurate. For example, | |
2037 | union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM | |
2038 | is translated in HI_REGS because classes are merged by | |
2039 | pairs and there is no accurate intermediate class. */ | |
2040 | CLEAR_HARD_REG_SET (this_alternative_set); | |
2041 | CLEAR_HARD_REG_SET (this_costly_alternative_set); | |
2042 | this_alternative_win = false; | |
2043 | this_alternative_match_win = false; | |
2044 | this_alternative_offmemok = false; | |
2045 | this_alternative_matches = -1; | |
f4eafc30 | 2046 | |
55a2c322 VM |
2047 | /* An empty constraint should be excluded by the fast |
2048 | track. */ | |
2049 | lra_assert (*p != 0 && *p != ','); | |
f4eafc30 | 2050 | |
d1457701 | 2051 | op_reject = 0; |
55a2c322 VM |
2052 | /* Scan this alternative's specs for this operand; set WIN |
2053 | if the operand fits any letter in this alternative. | |
2054 | Otherwise, clear BADOP if this operand could fit some | |
2055 | letter after reloads, or set WINREG if this operand could | |
2056 | fit after reloads provided the constraint allows some | |
2057 | registers. */ | |
2058 | costly_p = false; | |
2059 | do | |
2060 | { | |
2061 | switch ((c = *p, len = CONSTRAINT_LEN (c, p)), c) | |
2062 | { | |
2063 | case '\0': | |
2064 | len = 0; | |
2065 | break; | |
2066 | case ',': | |
2067 | c = '\0'; | |
2068 | break; | |
f4eafc30 | 2069 | |
55a2c322 VM |
2070 | case '&': |
2071 | early_clobber_p = true; | |
2072 | break; | |
f4eafc30 | 2073 | |
d1457701 VM |
2074 | case '$': |
2075 | op_reject += LRA_MAX_REJECT; | |
2076 | break; | |
2077 | case '^': | |
2078 | op_reject += LRA_LOSER_COST_FACTOR; | |
2079 | break; | |
2080 | ||
55a2c322 VM |
2081 | case '#': |
2082 | /* Ignore rest of this alternative. */ | |
2083 | c = '\0'; | |
2084 | break; | |
f4eafc30 | 2085 | |
55a2c322 VM |
2086 | case '0': case '1': case '2': case '3': case '4': |
2087 | case '5': case '6': case '7': case '8': case '9': | |
2088 | { | |
2089 | int m_hregno; | |
2090 | bool match_p; | |
f4eafc30 | 2091 | |
55a2c322 VM |
2092 | m = strtoul (p, &end, 10); |
2093 | p = end; | |
2094 | len = 0; | |
2095 | lra_assert (nop > m); | |
f4eafc30 | 2096 | |
00224b1a RS |
2097 | /* Reject matches if we don't know which operand is |
2098 | bigger. This situation would arguably be a bug in | |
2099 | an .md pattern, but could also occur in a user asm. */ | |
2100 | if (!ordered_p (GET_MODE_SIZE (biggest_mode[m]), | |
2101 | GET_MODE_SIZE (biggest_mode[nop]))) | |
2102 | break; | |
2103 | ||
a426543a VM |
2104 | /* Don't match wrong asm insn operands for proper |
2105 | diagnostic later. */ | |
2106 | if (INSN_CODE (curr_insn) < 0 | |
2107 | && (curr_operand_mode[m] == BLKmode | |
2108 | || curr_operand_mode[nop] == BLKmode) | |
2109 | && curr_operand_mode[m] != curr_operand_mode[nop]) | |
2110 | break; | |
2111 | ||
1686923c | 2112 | m_hregno = get_hard_regno (*curr_id->operand_loc[m], false); |
55a2c322 VM |
2113 | /* We are supposed to match a previous operand. |
2114 | If we do, we win if that one did. If we do | |
2115 | not, count both of the operands as losers. | |
2116 | (This is too conservative, since most of the | |
2117 | time only a single reload insn will be needed | |
2118 | to make the two operands win. As a result, | |
2119 | this alternative may be rejected when it is | |
2120 | actually desirable.) */ | |
2121 | match_p = false; | |
2122 | if (operands_match_p (*curr_id->operand_loc[nop], | |
2123 | *curr_id->operand_loc[m], m_hregno)) | |
2124 | { | |
2125 | /* We should reject matching of an early | |
2126 | clobber operand if the matching operand is | |
2127 | not dying in the insn. */ | |
2128 | if (! curr_static_id->operand[m].early_clobber | |
2129 | || operand_reg[nop] == NULL_RTX | |
2130 | || (find_regno_note (curr_insn, REG_DEAD, | |
1c86bd80 VM |
2131 | REGNO (op)) |
2132 | || REGNO (op) == REGNO (operand_reg[m]))) | |
55a2c322 VM |
2133 | match_p = true; |
2134 | } | |
2135 | if (match_p) | |
2136 | { | |
2137 | /* If we are matching a non-offsettable | |
2138 | address where an offsettable address was | |
2139 | expected, then we must reject this | |
2140 | combination, because we can't reload | |
2141 | it. */ | |
2142 | if (curr_alt_offmemok[m] | |
2143 | && MEM_P (*curr_id->operand_loc[m]) | |
2144 | && curr_alt[m] == NO_REGS && ! curr_alt_win[m]) | |
2145 | continue; | |
55a2c322 VM |
2146 | } |
2147 | else | |
2148 | { | |
2f0b80c7 PB |
2149 | /* Operands don't match. If the operands are |
2150 | different user defined explicit hard registers, | |
2151 | then we cannot make them match. */ | |
2152 | if ((REG_P (*curr_id->operand_loc[nop]) | |
2153 | || SUBREG_P (*curr_id->operand_loc[nop])) | |
2154 | && (REG_P (*curr_id->operand_loc[m]) | |
2155 | || SUBREG_P (*curr_id->operand_loc[m]))) | |
2156 | { | |
2157 | rtx nop_reg = *curr_id->operand_loc[nop]; | |
2158 | if (SUBREG_P (nop_reg)) | |
2159 | nop_reg = SUBREG_REG (nop_reg); | |
2160 | rtx m_reg = *curr_id->operand_loc[m]; | |
2161 | if (SUBREG_P (m_reg)) | |
2162 | m_reg = SUBREG_REG (m_reg); | |
2163 | ||
2164 | if (REG_P (nop_reg) | |
2165 | && HARD_REGISTER_P (nop_reg) | |
2166 | && REG_USERVAR_P (nop_reg) | |
2167 | && REG_P (m_reg) | |
2168 | && HARD_REGISTER_P (m_reg) | |
2169 | && REG_USERVAR_P (m_reg)) | |
2170 | break; | |
2171 | } | |
2172 | ||
2173 | /* Both operands must allow a reload register, | |
2174 | otherwise we cannot make them match. */ | |
55a2c322 VM |
2175 | if (curr_alt[m] == NO_REGS) |
2176 | break; | |
2177 | /* Retroactively mark the operand we had to | |
2178 | match as a loser, if it wasn't already and | |
2179 | it wasn't matched to a register constraint | |
2180 | (e.g it might be matched by memory). */ | |
2181 | if (curr_alt_win[m] | |
2182 | && (operand_reg[m] == NULL_RTX | |
2183 | || hard_regno[m] < 0)) | |
2184 | { | |
2185 | losers++; | |
2186 | reload_nregs | |
2187 | += (ira_reg_class_max_nregs[curr_alt[m]] | |
2188 | [GET_MODE (*curr_id->operand_loc[m])]); | |
2189 | } | |
f4eafc30 | 2190 | |
f4581282 VM |
2191 | /* Prefer matching earlyclobber alternative as |
2192 | it results in less hard regs required for | |
2193 | the insn than a non-matching earlyclobber | |
2194 | alternative. */ | |
2195 | if (curr_static_id->operand[m].early_clobber) | |
2196 | { | |
2197 | if (lra_dump_file != NULL) | |
2198 | fprintf | |
2199 | (lra_dump_file, | |
2200 | " %d Matching earlyclobber alt:" | |
2201 | " reject--\n", | |
2202 | nop); | |
dbe7895c AS |
2203 | if (!matching_early_clobber[m]) |
2204 | { | |
2205 | reject--; | |
2206 | matching_early_clobber[m] = 1; | |
2207 | } | |
f4581282 VM |
2208 | } |
2209 | /* Otherwise we prefer no matching | |
2210 | alternatives because it gives more freedom | |
2211 | in RA. */ | |
2212 | else if (operand_reg[nop] == NULL_RTX | |
2213 | || (find_regno_note (curr_insn, REG_DEAD, | |
2214 | REGNO (operand_reg[nop])) | |
2215 | == NULL_RTX)) | |
cb1cca12 VM |
2216 | { |
2217 | if (lra_dump_file != NULL) | |
2218 | fprintf | |
2219 | (lra_dump_file, | |
2220 | " %d Matching alt: reject+=2\n", | |
2221 | nop); | |
2222 | reject += 2; | |
2223 | } | |
55a2c322 VM |
2224 | } |
2225 | /* If we have to reload this operand and some | |
2226 | previous operand also had to match the same | |
2227 | thing as this operand, we don't know how to do | |
2228 | that. */ | |
2229 | if (!match_p || !curr_alt_win[m]) | |
2230 | { | |
2231 | for (i = 0; i < nop; i++) | |
2232 | if (curr_alt_matches[i] == m) | |
2233 | break; | |
2234 | if (i < nop) | |
2235 | break; | |
2236 | } | |
2237 | else | |
2238 | did_match = true; | |
f4eafc30 | 2239 | |
28ed1460 | 2240 | this_alternative_matches = m; |
55a2c322 VM |
2241 | /* This can be fixed with reloads if the operand |
2242 | we are supposed to match can be fixed with | |
2243 | reloads. */ | |
2244 | badop = false; | |
2245 | this_alternative = curr_alt[m]; | |
2246 | COPY_HARD_REG_SET (this_alternative_set, curr_alt_set[m]); | |
821b7577 | 2247 | winreg = this_alternative != NO_REGS; |
55a2c322 VM |
2248 | break; |
2249 | } | |
f4eafc30 | 2250 | |
55a2c322 VM |
2251 | case 'g': |
2252 | if (MEM_P (op) | |
2253 | || general_constant_p (op) | |
2254 | || spilled_pseudo_p (op)) | |
2255 | win = true; | |
777e635f | 2256 | cl = GENERAL_REGS; |
55a2c322 | 2257 | goto reg; |
f4eafc30 | 2258 | |
55a2c322 | 2259 | default: |
777e635f RS |
2260 | cn = lookup_constraint (p); |
2261 | switch (get_constraint_type (cn)) | |
55a2c322 | 2262 | { |
777e635f RS |
2263 | case CT_REGISTER: |
2264 | cl = reg_class_for_constraint (cn); | |
2265 | if (cl != NO_REGS) | |
2266 | goto reg; | |
2267 | break; | |
f4eafc30 | 2268 | |
d9c35eee RS |
2269 | case CT_CONST_INT: |
2270 | if (CONST_INT_P (op) | |
2271 | && insn_const_int_ok_for_constraint (INTVAL (op), cn)) | |
2272 | win = true; | |
2273 | break; | |
2274 | ||
777e635f RS |
2275 | case CT_MEMORY: |
2276 | if (MEM_P (op) | |
2277 | && satisfies_memory_constraint_p (op, cn)) | |
2278 | win = true; | |
2279 | else if (spilled_pseudo_p (op)) | |
2280 | win = true; | |
2281 | ||
2282 | /* If we didn't already win, we can reload constants | |
2283 | via force_const_mem or put the pseudo value into | |
2284 | memory, or make other memory by reloading the | |
2285 | address like for 'o'. */ | |
2286 | if (CONST_POOL_OK_P (mode, op) | |
987b67f1 VM |
2287 | || MEM_P (op) || REG_P (op) |
2288 | /* We can restore the equiv insn by a | |
2289 | reload. */ | |
2290 | || equiv_substition_p[nop]) | |
777e635f RS |
2291 | badop = false; |
2292 | constmemok = true; | |
2293 | offmemok = true; | |
2294 | break; | |
2295 | ||
2296 | case CT_ADDRESS: | |
998fd141 AO |
2297 | /* An asm operand with an address constraint |
2298 | that doesn't satisfy address_operand has | |
2299 | is_address cleared, so that we don't try to | |
2300 | make a non-address fit. */ | |
2301 | if (!curr_static_id->operand[nop].is_address) | |
2302 | break; | |
777e635f RS |
2303 | /* If we didn't already win, we can reload the address |
2304 | into a base register. */ | |
2305 | if (satisfies_address_constraint_p (op, cn)) | |
2306 | win = true; | |
2307 | cl = base_reg_class (VOIDmode, ADDR_SPACE_GENERIC, | |
2308 | ADDRESS, SCRATCH); | |
2309 | badop = false; | |
2310 | goto reg; | |
2311 | ||
2312 | case CT_FIXED_FORM: | |
2313 | if (constraint_satisfied_p (op, cn)) | |
55a2c322 | 2314 | win = true; |
55a2c322 | 2315 | break; |
9eb1ca69 VM |
2316 | |
2317 | case CT_SPECIAL_MEMORY: | |
2318 | if (MEM_P (op) | |
2319 | && satisfies_memory_constraint_p (op, cn)) | |
2320 | win = true; | |
2321 | else if (spilled_pseudo_p (op)) | |
2322 | win = true; | |
2323 | break; | |
55a2c322 | 2324 | } |
777e635f | 2325 | break; |
f4eafc30 | 2326 | |
777e635f | 2327 | reg: |
55a2c322 VM |
2328 | this_alternative = reg_class_subunion[this_alternative][cl]; |
2329 | IOR_HARD_REG_SET (this_alternative_set, | |
2330 | reg_class_contents[cl]); | |
2331 | if (costly_p) | |
2332 | { | |
2333 | this_costly_alternative | |
2334 | = reg_class_subunion[this_costly_alternative][cl]; | |
2335 | IOR_HARD_REG_SET (this_costly_alternative_set, | |
2336 | reg_class_contents[cl]); | |
2337 | } | |
55a2c322 VM |
2338 | if (mode == BLKmode) |
2339 | break; | |
2340 | winreg = true; | |
2341 | if (REG_P (op)) | |
2342 | { | |
2343 | if (hard_regno[nop] >= 0 | |
2344 | && in_hard_reg_set_p (this_alternative_set, | |
2345 | mode, hard_regno[nop])) | |
2346 | win = true; | |
2347 | else if (hard_regno[nop] < 0 | |
2348 | && in_class_p (op, this_alternative, NULL)) | |
2349 | win = true; | |
2350 | } | |
2351 | break; | |
2352 | } | |
2353 | if (c != ' ' && c != '\t') | |
2354 | costly_p = c == '*'; | |
2355 | } | |
2356 | while ((p += len), c); | |
f4eafc30 | 2357 | |
80f466c4 VM |
2358 | scratch_p = (operand_reg[nop] != NULL_RTX |
2359 | && lra_former_scratch_p (REGNO (operand_reg[nop]))); | |
55a2c322 VM |
2360 | /* Record which operands fit this alternative. */ |
2361 | if (win) | |
2362 | { | |
2363 | this_alternative_win = true; | |
2364 | if (operand_reg[nop] != NULL_RTX) | |
2365 | { | |
2366 | if (hard_regno[nop] >= 0) | |
2367 | { | |
2368 | if (in_hard_reg_set_p (this_costly_alternative_set, | |
2369 | mode, hard_regno[nop])) | |
cb1cca12 VM |
2370 | { |
2371 | if (lra_dump_file != NULL) | |
2372 | fprintf (lra_dump_file, | |
2373 | " %d Costly set: reject++\n", | |
2374 | nop); | |
2375 | reject++; | |
2376 | } | |
55a2c322 VM |
2377 | } |
2378 | else | |
2379 | { | |
80f466c4 VM |
2380 | /* Prefer won reg to spilled pseudo under other |
2381 | equal conditions for possibe inheritance. */ | |
2382 | if (! scratch_p) | |
2383 | { | |
2384 | if (lra_dump_file != NULL) | |
2385 | fprintf | |
2386 | (lra_dump_file, | |
2387 | " %d Non pseudo reload: reject++\n", | |
2388 | nop); | |
2389 | reject++; | |
2390 | } | |
55a2c322 VM |
2391 | if (in_class_p (operand_reg[nop], |
2392 | this_costly_alternative, NULL)) | |
cb1cca12 VM |
2393 | { |
2394 | if (lra_dump_file != NULL) | |
2395 | fprintf | |
2396 | (lra_dump_file, | |
2397 | " %d Non pseudo costly reload:" | |
2398 | " reject++\n", | |
2399 | nop); | |
2400 | reject++; | |
2401 | } | |
55a2c322 | 2402 | } |
9c582551 | 2403 | /* We simulate the behavior of old reload here. |
55a2c322 VM |
2404 | Although scratches need hard registers and it |
2405 | might result in spilling other pseudos, no reload | |
2406 | insns are generated for the scratches. So it | |
2407 | might cost something but probably less than old | |
2408 | reload pass believes. */ | |
80f466c4 | 2409 | if (scratch_p) |
cb1cca12 VM |
2410 | { |
2411 | if (lra_dump_file != NULL) | |
2412 | fprintf (lra_dump_file, | |
80f466c4 | 2413 | " %d Scratch win: reject+=2\n", |
cb1cca12 | 2414 | nop); |
80f466c4 | 2415 | reject += 2; |
cb1cca12 | 2416 | } |
55a2c322 VM |
2417 | } |
2418 | } | |
2419 | else if (did_match) | |
2420 | this_alternative_match_win = true; | |
2421 | else | |
2422 | { | |
2423 | int const_to_mem = 0; | |
2424 | bool no_regs_p; | |
2425 | ||
d1457701 | 2426 | reject += op_reject; |
8d49e7ef VM |
2427 | /* Never do output reload of stack pointer. It makes |
2428 | impossible to do elimination when SP is changed in | |
2429 | RTL. */ | |
2430 | if (op == stack_pointer_rtx && ! frame_pointer_needed | |
2431 | && curr_static_id->operand[nop].type != OP_IN) | |
2432 | goto fail; | |
2433 | ||
e86c0101 SB |
2434 | /* If this alternative asks for a specific reg class, see if there |
2435 | is at least one allocatable register in that class. */ | |
55a2c322 VM |
2436 | no_regs_p |
2437 | = (this_alternative == NO_REGS | |
2438 | || (hard_reg_set_subset_p | |
2439 | (reg_class_contents[this_alternative], | |
2440 | lra_no_alloc_regs))); | |
e86c0101 SB |
2441 | |
2442 | /* For asms, verify that the class for this alternative is possible | |
2443 | for the mode that is specified. */ | |
ecee672b | 2444 | if (!no_regs_p && INSN_CODE (curr_insn) < 0) |
e86c0101 SB |
2445 | { |
2446 | int i; | |
2447 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
f939c3e6 | 2448 | if (targetm.hard_regno_mode_ok (i, mode) |
8f21260c VM |
2449 | && in_hard_reg_set_p (reg_class_contents[this_alternative], |
2450 | mode, i)) | |
e86c0101 SB |
2451 | break; |
2452 | if (i == FIRST_PSEUDO_REGISTER) | |
2453 | winreg = false; | |
2454 | } | |
2455 | ||
55a2c322 VM |
2456 | /* If this operand accepts a register, and if the |
2457 | register class has at least one allocatable register, | |
2458 | then this operand can be reloaded. */ | |
2459 | if (winreg && !no_regs_p) | |
2460 | badop = false; | |
f4eafc30 | 2461 | |
55a2c322 | 2462 | if (badop) |
8f21260c VM |
2463 | { |
2464 | if (lra_dump_file != NULL) | |
2465 | fprintf (lra_dump_file, | |
2466 | " alt=%d: Bad operand -- refuse\n", | |
2467 | nalt); | |
2468 | goto fail; | |
2469 | } | |
55a2c322 | 2470 | |
d13835b6 VM |
2471 | if (this_alternative != NO_REGS) |
2472 | { | |
2473 | HARD_REG_SET available_regs; | |
2474 | ||
2475 | COPY_HARD_REG_SET (available_regs, | |
2476 | reg_class_contents[this_alternative]); | |
2477 | AND_COMPL_HARD_REG_SET | |
2478 | (available_regs, | |
2479 | ira_prohibited_class_mode_regs[this_alternative][mode]); | |
2480 | AND_COMPL_HARD_REG_SET (available_regs, lra_no_alloc_regs); | |
2481 | if (hard_reg_set_empty_p (available_regs)) | |
2482 | { | |
2483 | /* There are no hard regs holding a value of given | |
2484 | mode. */ | |
2485 | if (offmemok) | |
2486 | { | |
2487 | this_alternative = NO_REGS; | |
2488 | if (lra_dump_file != NULL) | |
2489 | fprintf (lra_dump_file, | |
2490 | " %d Using memory because of" | |
2491 | " a bad mode: reject+=2\n", | |
2492 | nop); | |
2493 | reject += 2; | |
2494 | } | |
2495 | else | |
2496 | { | |
2497 | if (lra_dump_file != NULL) | |
2498 | fprintf (lra_dump_file, | |
2499 | " alt=%d: Wrong mode -- refuse\n", | |
2500 | nalt); | |
2501 | goto fail; | |
2502 | } | |
2503 | } | |
2504 | } | |
2505 | ||
2ae577fd VM |
2506 | /* If not assigned pseudo has a class which a subset of |
2507 | required reg class, it is a less costly alternative | |
2508 | as the pseudo still can get a hard reg of necessary | |
2509 | class. */ | |
2510 | if (! no_regs_p && REG_P (op) && hard_regno[nop] < 0 | |
2511 | && (cl = get_reg_class (REGNO (op))) != NO_REGS | |
2512 | && ira_class_subset_p[this_alternative][cl]) | |
2513 | { | |
2514 | if (lra_dump_file != NULL) | |
2515 | fprintf | |
2516 | (lra_dump_file, | |
2517 | " %d Super set class reg: reject-=3\n", nop); | |
2518 | reject -= 3; | |
2519 | } | |
2520 | ||
55a2c322 VM |
2521 | this_alternative_offmemok = offmemok; |
2522 | if (this_costly_alternative != NO_REGS) | |
cb1cca12 VM |
2523 | { |
2524 | if (lra_dump_file != NULL) | |
2525 | fprintf (lra_dump_file, | |
2526 | " %d Costly loser: reject++\n", nop); | |
2527 | reject++; | |
2528 | } | |
55a2c322 VM |
2529 | /* If the operand is dying, has a matching constraint, |
2530 | and satisfies constraints of the matched operand | |
f4581282 | 2531 | which failed to satisfy the own constraints, most probably |
a9711f36 VM |
2532 | the reload for this operand will be gone. */ |
2533 | if (this_alternative_matches >= 0 | |
2534 | && !curr_alt_win[this_alternative_matches] | |
2535 | && REG_P (op) | |
2536 | && find_regno_note (curr_insn, REG_DEAD, REGNO (op)) | |
2537 | && (hard_regno[nop] >= 0 | |
2538 | ? in_hard_reg_set_p (this_alternative_set, | |
2539 | mode, hard_regno[nop]) | |
2540 | : in_class_p (op, this_alternative, NULL))) | |
2541 | { | |
2542 | if (lra_dump_file != NULL) | |
2543 | fprintf | |
2544 | (lra_dump_file, | |
2545 | " %d Dying matched operand reload: reject++\n", | |
2546 | nop); | |
2547 | reject++; | |
2548 | } | |
2549 | else | |
027ece11 | 2550 | { |
5306401f VM |
2551 | /* Strict_low_part requires to reload the register |
2552 | not the sub-register. In this case we should | |
2553 | check that a final reload hard reg can hold the | |
2554 | value mode. */ | |
027ece11 VM |
2555 | if (curr_static_id->operand[nop].strict_low |
2556 | && REG_P (op) | |
2557 | && hard_regno[nop] < 0 | |
2558 | && GET_CODE (*curr_id->operand_loc[nop]) == SUBREG | |
2559 | && ira_class_hard_regs_num[this_alternative] > 0 | |
f939c3e6 RS |
2560 | && (!targetm.hard_regno_mode_ok |
2561 | (ira_class_hard_regs[this_alternative][0], | |
2562 | GET_MODE (*curr_id->operand_loc[nop])))) | |
8f21260c VM |
2563 | { |
2564 | if (lra_dump_file != NULL) | |
2565 | fprintf | |
2566 | (lra_dump_file, | |
2567 | " alt=%d: Strict low subreg reload -- refuse\n", | |
2568 | nalt); | |
2569 | goto fail; | |
2570 | } | |
027ece11 VM |
2571 | losers++; |
2572 | } | |
55a2c322 VM |
2573 | if (operand_reg[nop] != NULL_RTX |
2574 | /* Output operands and matched input operands are | |
2575 | not inherited. The following conditions do not | |
2576 | exactly describe the previous statement but they | |
2577 | are pretty close. */ | |
2578 | && curr_static_id->operand[nop].type != OP_OUT | |
2579 | && (this_alternative_matches < 0 | |
2580 | || curr_static_id->operand[nop].type != OP_IN)) | |
2581 | { | |
2582 | int last_reload = (lra_reg_info[ORIGINAL_REGNO | |
2583 | (operand_reg[nop])] | |
2584 | .last_reload); | |
2585 | ||
6334f3e9 VM |
2586 | /* The value of reload_sum has sense only if we |
2587 | process insns in their order. It happens only on | |
2588 | the first constraints sub-pass when we do most of | |
2589 | reload work. */ | |
2590 | if (lra_constraint_iter == 1 && last_reload > bb_reload_num) | |
55a2c322 VM |
2591 | reload_sum += last_reload - bb_reload_num; |
2592 | } | |
2593 | /* If this is a constant that is reloaded into the | |
2594 | desired class by copying it to memory first, count | |
2595 | that as another reload. This is consistent with | |
2596 | other code and is required to avoid choosing another | |
2597 | alternative when the constant is moved into memory. | |
2598 | Note that the test here is precisely the same as in | |
2599 | the code below that calls force_const_mem. */ | |
2600 | if (CONST_POOL_OK_P (mode, op) | |
2601 | && ((targetm.preferred_reload_class | |
2602 | (op, this_alternative) == NO_REGS) | |
2603 | || no_input_reloads_p)) | |
2604 | { | |
2605 | const_to_mem = 1; | |
2606 | if (! no_regs_p) | |
2607 | losers++; | |
2608 | } | |
f4eafc30 | 2609 | |
55a2c322 VM |
2610 | /* Alternative loses if it requires a type of reload not |
2611 | permitted for this insn. We can always reload | |
2612 | objects with a REG_UNUSED note. */ | |
2613 | if ((curr_static_id->operand[nop].type != OP_IN | |
2614 | && no_output_reloads_p | |
2615 | && ! find_reg_note (curr_insn, REG_UNUSED, op)) | |
2616 | || (curr_static_id->operand[nop].type != OP_OUT | |
8f21260c VM |
2617 | && no_input_reloads_p && ! const_to_mem) |
2618 | || (this_alternative_matches >= 0 | |
9102dadd VM |
2619 | && (no_input_reloads_p |
2620 | || (no_output_reloads_p | |
2621 | && (curr_static_id->operand | |
2622 | [this_alternative_matches].type != OP_IN) | |
2623 | && ! find_reg_note (curr_insn, REG_UNUSED, | |
2624 | no_subreg_reg_operand | |
2625 | [this_alternative_matches]))))) | |
8f21260c VM |
2626 | { |
2627 | if (lra_dump_file != NULL) | |
2628 | fprintf | |
2629 | (lra_dump_file, | |
2630 | " alt=%d: No input/otput reload -- refuse\n", | |
2631 | nalt); | |
2632 | goto fail; | |
2633 | } | |
f4eafc30 | 2634 | |
f66af4aa VM |
2635 | /* Alternative loses if it required class pseudo can not |
2636 | hold value of required mode. Such insns can be | |
7b6e0c54 | 2637 | described by insn definitions with mode iterators. */ |
f66af4aa VM |
2638 | if (GET_MODE (*curr_id->operand_loc[nop]) != VOIDmode |
2639 | && ! hard_reg_set_empty_p (this_alternative_set) | |
7b6e0c54 VM |
2640 | /* It is common practice for constraints to use a |
2641 | class which does not have actually enough regs to | |
2642 | hold the value (e.g. x86 AREG for mode requiring | |
2643 | more one general reg). Therefore we have 2 | |
2644 | conditions to check that the reload pseudo can | |
2645 | not hold the mode value. */ | |
f939c3e6 RS |
2646 | && (!targetm.hard_regno_mode_ok |
2647 | (ira_class_hard_regs[this_alternative][0], | |
2648 | GET_MODE (*curr_id->operand_loc[nop]))) | |
7b6e0c54 VM |
2649 | /* The above condition is not enough as the first |
2650 | reg in ira_class_hard_regs can be not aligned for | |
2651 | multi-words mode values. */ | |
3c954213 VM |
2652 | && (prohibited_class_reg_set_mode_p |
2653 | (this_alternative, this_alternative_set, | |
2654 | GET_MODE (*curr_id->operand_loc[nop])))) | |
2655 | { | |
2656 | if (lra_dump_file != NULL) | |
2657 | fprintf (lra_dump_file, | |
2658 | " alt=%d: reload pseudo for op %d " | |
2659 | " can not hold the mode value -- refuse\n", | |
2660 | nalt, nop); | |
2661 | goto fail; | |
f66af4aa VM |
2662 | } |
2663 | ||
821b7577 VM |
2664 | /* Check strong discouragement of reload of non-constant |
2665 | into class THIS_ALTERNATIVE. */ | |
2666 | if (! CONSTANT_P (op) && ! no_regs_p | |
2667 | && (targetm.preferred_reload_class | |
2668 | (op, this_alternative) == NO_REGS | |
2669 | || (curr_static_id->operand[nop].type == OP_OUT | |
2670 | && (targetm.preferred_output_reload_class | |
2671 | (op, this_alternative) == NO_REGS)))) | |
cb1cca12 VM |
2672 | { |
2673 | if (lra_dump_file != NULL) | |
2674 | fprintf (lra_dump_file, | |
2675 | " %d Non-prefered reload: reject+=%d\n", | |
2676 | nop, LRA_MAX_REJECT); | |
2677 | reject += LRA_MAX_REJECT; | |
2678 | } | |
f4eafc30 | 2679 | |
ed52a84e VM |
2680 | if (! (MEM_P (op) && offmemok) |
2681 | && ! (const_to_mem && constmemok)) | |
55a2c322 VM |
2682 | { |
2683 | /* We prefer to reload pseudos over reloading other | |
2684 | things, since such reloads may be able to be | |
2685 | eliminated later. So bump REJECT in other cases. | |
2686 | Don't do this in the case where we are forcing a | |
2687 | constant into memory and it will then win since | |
2688 | we don't want to have a different alternative | |
2689 | match then. */ | |
2690 | if (! (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER)) | |
cb1cca12 VM |
2691 | { |
2692 | if (lra_dump_file != NULL) | |
2693 | fprintf | |
2694 | (lra_dump_file, | |
2695 | " %d Non-pseudo reload: reject+=2\n", | |
2696 | nop); | |
2697 | reject += 2; | |
2698 | } | |
f4eafc30 | 2699 | |
55a2c322 VM |
2700 | if (! no_regs_p) |
2701 | reload_nregs | |
2702 | += ira_reg_class_max_nregs[this_alternative][mode]; | |
36ff9dfb VM |
2703 | |
2704 | if (SMALL_REGISTER_CLASS_P (this_alternative)) | |
cb1cca12 VM |
2705 | { |
2706 | if (lra_dump_file != NULL) | |
2707 | fprintf | |
2708 | (lra_dump_file, | |
2709 | " %d Small class reload: reject+=%d\n", | |
2710 | nop, LRA_LOSER_COST_FACTOR / 2); | |
2711 | reject += LRA_LOSER_COST_FACTOR / 2; | |
2712 | } | |
55a2c322 VM |
2713 | } |
2714 | ||
1bdc4b11 VM |
2715 | /* We are trying to spill pseudo into memory. It is |
2716 | usually more costly than moving to a hard register | |
2717 | although it might takes the same number of | |
5f225ef4 VM |
2718 | reloads. |
2719 | ||
2720 | Non-pseudo spill may happen also. Suppose a target allows both | |
2721 | register and memory in the operand constraint alternatives, | |
2722 | then it's typical that an eliminable register has a substition | |
2723 | of "base + offset" which can either be reloaded by a simple | |
2724 | "new_reg <= base + offset" which will match the register | |
2725 | constraint, or a similar reg addition followed by further spill | |
2726 | to and reload from memory which will match the memory | |
2727 | constraint, but this memory spill will be much more costly | |
2728 | usually. | |
2729 | ||
2730 | Code below increases the reject for both pseudo and non-pseudo | |
2731 | spill. */ | |
10406801 JW |
2732 | if (no_regs_p |
2733 | && !(MEM_P (op) && offmemok) | |
2734 | && !(REG_P (op) && hard_regno[nop] < 0)) | |
cb1cca12 VM |
2735 | { |
2736 | if (lra_dump_file != NULL) | |
2737 | fprintf | |
2738 | (lra_dump_file, | |
5f225ef4 VM |
2739 | " %d Spill %spseudo into memory: reject+=3\n", |
2740 | nop, REG_P (op) ? "" : "Non-"); | |
cb1cca12 | 2741 | reject += 3; |
7891065a VM |
2742 | if (VECTOR_MODE_P (mode)) |
2743 | { | |
2744 | /* Spilling vectors into memory is usually more | |
2745 | costly as they contain big values. */ | |
2746 | if (lra_dump_file != NULL) | |
2747 | fprintf | |
2748 | (lra_dump_file, | |
2749 | " %d Spill vector pseudo: reject+=2\n", | |
2750 | nop); | |
2751 | reject += 2; | |
2752 | } | |
cb1cca12 | 2753 | } |
1bdc4b11 | 2754 | |
4796d8f6 VM |
2755 | /* When we use an operand requiring memory in given |
2756 | alternative, the insn should write *and* read the | |
2757 | value to/from memory it is costly in comparison with | |
2758 | an insn alternative which does not use memory | |
2759 | (e.g. register or immediate operand). We exclude | |
2760 | memory operand for such case as we can satisfy the | |
2761 | memory constraints by reloading address. */ | |
2762 | if (no_regs_p && offmemok && !MEM_P (op)) | |
9b195552 VM |
2763 | { |
2764 | if (lra_dump_file != NULL) | |
2765 | fprintf | |
2766 | (lra_dump_file, | |
2767 | " Using memory insn operand %d: reject+=3\n", | |
2768 | nop); | |
2769 | reject += 3; | |
2770 | } | |
2771 | ||
7100b561 UB |
2772 | /* If reload requires moving value through secondary |
2773 | memory, it will need one more insn at least. */ | |
2774 | if (this_alternative != NO_REGS | |
2775 | && REG_P (op) && (cl = get_reg_class (REGNO (op))) != NO_REGS | |
2776 | && ((curr_static_id->operand[nop].type != OP_OUT | |
f15643d4 RS |
2777 | && targetm.secondary_memory_needed (GET_MODE (op), cl, |
2778 | this_alternative)) | |
7100b561 | 2779 | || (curr_static_id->operand[nop].type != OP_IN |
f15643d4 RS |
2780 | && (targetm.secondary_memory_needed |
2781 | (GET_MODE (op), this_alternative, cl))))) | |
7100b561 | 2782 | losers++; |
f15643d4 | 2783 | |
55a2c322 VM |
2784 | /* Input reloads can be inherited more often than output |
2785 | reloads can be removed, so penalize output | |
2786 | reloads. */ | |
2787 | if (!REG_P (op) || curr_static_id->operand[nop].type != OP_IN) | |
cb1cca12 VM |
2788 | { |
2789 | if (lra_dump_file != NULL) | |
2790 | fprintf | |
2791 | (lra_dump_file, | |
2792 | " %d Non input pseudo reload: reject++\n", | |
2793 | nop); | |
2794 | reject++; | |
2795 | } | |
feca7b89 VM |
2796 | |
2797 | if (MEM_P (op) && offmemok) | |
2798 | addr_losers++; | |
8b8e41e5 VM |
2799 | else if (curr_static_id->operand[nop].type == OP_INOUT) |
2800 | { | |
2801 | if (lra_dump_file != NULL) | |
2802 | fprintf | |
2803 | (lra_dump_file, | |
2804 | " %d Input/Output reload: reject+=%d\n", | |
2805 | nop, LRA_LOSER_COST_FACTOR); | |
2806 | reject += LRA_LOSER_COST_FACTOR; | |
2807 | } | |
55a2c322 | 2808 | } |
f4eafc30 | 2809 | |
80f466c4 | 2810 | if (early_clobber_p && ! scratch_p) |
cb1cca12 VM |
2811 | { |
2812 | if (lra_dump_file != NULL) | |
2813 | fprintf (lra_dump_file, | |
2814 | " %d Early clobber: reject++\n", nop); | |
2815 | reject++; | |
2816 | } | |
55a2c322 VM |
2817 | /* ??? We check early clobbers after processing all operands |
2818 | (see loop below) and there we update the costs more. | |
2819 | Should we update the cost (may be approximately) here | |
2820 | because of early clobber register reloads or it is a rare | |
2821 | or non-important thing to be worth to do it. */ | |
feca7b89 VM |
2822 | overall = (losers * LRA_LOSER_COST_FACTOR + reject |
2823 | - (addr_losers == losers ? static_reject : 0)); | |
55a2c322 | 2824 | if ((best_losers == 0 || losers != 0) && best_overall < overall) |
deca73f5 VM |
2825 | { |
2826 | if (lra_dump_file != NULL) | |
2827 | fprintf (lra_dump_file, | |
cb1cca12 | 2828 | " alt=%d,overall=%d,losers=%d -- refuse\n", |
deca73f5 VM |
2829 | nalt, overall, losers); |
2830 | goto fail; | |
2831 | } | |
55a2c322 | 2832 | |
9b195552 VM |
2833 | if (update_and_check_small_class_inputs (nop, this_alternative)) |
2834 | { | |
2835 | if (lra_dump_file != NULL) | |
2836 | fprintf (lra_dump_file, | |
2837 | " alt=%d, not enough small class regs -- refuse\n", | |
2838 | nalt); | |
2839 | goto fail; | |
2840 | } | |
55a2c322 VM |
2841 | curr_alt[nop] = this_alternative; |
2842 | COPY_HARD_REG_SET (curr_alt_set[nop], this_alternative_set); | |
2843 | curr_alt_win[nop] = this_alternative_win; | |
2844 | curr_alt_match_win[nop] = this_alternative_match_win; | |
2845 | curr_alt_offmemok[nop] = this_alternative_offmemok; | |
2846 | curr_alt_matches[nop] = this_alternative_matches; | |
f4eafc30 | 2847 | |
55a2c322 VM |
2848 | if (this_alternative_matches >= 0 |
2849 | && !did_match && !this_alternative_win) | |
2850 | curr_alt_win[this_alternative_matches] = false; | |
f4eafc30 | 2851 | |
55a2c322 VM |
2852 | if (early_clobber_p && operand_reg[nop] != NULL_RTX) |
2853 | early_clobbered_nops[early_clobbered_regs_num++] = nop; | |
2854 | } | |
feca7b89 | 2855 | |
2c62cbaa VM |
2856 | if (curr_insn_set != NULL_RTX && n_operands == 2 |
2857 | /* Prevent processing non-move insns. */ | |
2858 | && (GET_CODE (SET_SRC (curr_insn_set)) == SUBREG | |
2859 | || SET_SRC (curr_insn_set) == no_subreg_reg_operand[1]) | |
2860 | && ((! curr_alt_win[0] && ! curr_alt_win[1] | |
2861 | && REG_P (no_subreg_reg_operand[0]) | |
2862 | && REG_P (no_subreg_reg_operand[1]) | |
2863 | && (reg_in_class_p (no_subreg_reg_operand[0], curr_alt[1]) | |
2864 | || reg_in_class_p (no_subreg_reg_operand[1], curr_alt[0]))) | |
2865 | || (! curr_alt_win[0] && curr_alt_win[1] | |
2866 | && REG_P (no_subreg_reg_operand[1]) | |
feca7b89 VM |
2867 | /* Check that we reload memory not the memory |
2868 | address. */ | |
9125b9fc VM |
2869 | && ! (curr_alt_offmemok[0] |
2870 | && MEM_P (no_subreg_reg_operand[0])) | |
2c62cbaa VM |
2871 | && reg_in_class_p (no_subreg_reg_operand[1], curr_alt[0])) |
2872 | || (curr_alt_win[0] && ! curr_alt_win[1] | |
2873 | && REG_P (no_subreg_reg_operand[0]) | |
feca7b89 VM |
2874 | /* Check that we reload memory not the memory |
2875 | address. */ | |
9125b9fc VM |
2876 | && ! (curr_alt_offmemok[1] |
2877 | && MEM_P (no_subreg_reg_operand[1])) | |
2c62cbaa VM |
2878 | && reg_in_class_p (no_subreg_reg_operand[0], curr_alt[1]) |
2879 | && (! CONST_POOL_OK_P (curr_operand_mode[1], | |
2880 | no_subreg_reg_operand[1]) | |
2881 | || (targetm.preferred_reload_class | |
2882 | (no_subreg_reg_operand[1], | |
2883 | (enum reg_class) curr_alt[1]) != NO_REGS)) | |
2884 | /* If it is a result of recent elimination in move | |
2885 | insn we can transform it into an add still by | |
2886 | using this alternative. */ | |
b4c96972 RS |
2887 | && GET_CODE (no_subreg_reg_operand[1]) != PLUS |
2888 | /* Likewise if the source has been replaced with an | |
2889 | equivalent value. This only happens once -- the reload | |
2890 | will use the equivalent value instead of the register it | |
2891 | replaces -- so there should be no danger of cycling. */ | |
2892 | && !equiv_substition_p[1]))) | |
cb1cca12 VM |
2893 | { |
2894 | /* We have a move insn and a new reload insn will be similar | |
9125b9fc VM |
2895 | to the current insn. We should avoid such situation as |
2896 | it results in LRA cycling. */ | |
2897 | if (lra_dump_file != NULL) | |
2898 | fprintf (lra_dump_file, | |
2899 | " Cycle danger: overall += LRA_MAX_REJECT\n"); | |
cb1cca12 VM |
2900 | overall += LRA_MAX_REJECT; |
2901 | } | |
55a2c322 VM |
2902 | ok_p = true; |
2903 | curr_alt_dont_inherit_ops_num = 0; | |
2904 | for (nop = 0; nop < early_clobbered_regs_num; nop++) | |
2905 | { | |
2194f7a2 | 2906 | int i, j, clobbered_hard_regno, first_conflict_j, last_conflict_j; |
55a2c322 VM |
2907 | HARD_REG_SET temp_set; |
2908 | ||
2909 | i = early_clobbered_nops[nop]; | |
2910 | if ((! curr_alt_win[i] && ! curr_alt_match_win[i]) | |
2911 | || hard_regno[i] < 0) | |
2912 | continue; | |
1c86bd80 | 2913 | lra_assert (operand_reg[i] != NULL_RTX); |
55a2c322 VM |
2914 | clobbered_hard_regno = hard_regno[i]; |
2915 | CLEAR_HARD_REG_SET (temp_set); | |
2916 | add_to_hard_reg_set (&temp_set, biggest_mode[i], clobbered_hard_regno); | |
2194f7a2 | 2917 | first_conflict_j = last_conflict_j = -1; |
55a2c322 VM |
2918 | for (j = 0; j < n_operands; j++) |
2919 | if (j == i | |
2920 | /* We don't want process insides of match_operator and | |
2921 | match_parallel because otherwise we would process | |
2922 | their operands once again generating a wrong | |
2923 | code. */ | |
2924 | || curr_static_id->operand[j].is_operator) | |
2925 | continue; | |
2926 | else if ((curr_alt_matches[j] == i && curr_alt_match_win[j]) | |
2927 | || (curr_alt_matches[i] == j && curr_alt_match_win[i])) | |
2928 | continue; | |
1c86bd80 VM |
2929 | /* If we don't reload j-th operand, check conflicts. */ |
2930 | else if ((curr_alt_win[j] || curr_alt_match_win[j]) | |
2931 | && uses_hard_regs_p (*curr_id->operand_loc[j], temp_set)) | |
2194f7a2 VM |
2932 | { |
2933 | if (first_conflict_j < 0) | |
2934 | first_conflict_j = j; | |
2935 | last_conflict_j = j; | |
2f0b80c7 PB |
2936 | /* Both the earlyclobber operand and conflicting operand |
2937 | cannot both be user defined hard registers. */ | |
2938 | if (HARD_REGISTER_P (operand_reg[i]) | |
2939 | && REG_USERVAR_P (operand_reg[i]) | |
2940 | && operand_reg[j] != NULL_RTX | |
2941 | && HARD_REGISTER_P (operand_reg[j]) | |
2942 | && REG_USERVAR_P (operand_reg[j])) | |
2943 | fatal_insn ("unable to generate reloads for " | |
2944 | "impossible constraints:", curr_insn); | |
2194f7a2 VM |
2945 | } |
2946 | if (last_conflict_j < 0) | |
55a2c322 | 2947 | continue; |
2f0b80c7 PB |
2948 | |
2949 | /* If an earlyclobber operand conflicts with another non-matching | |
2950 | operand (ie, they have been assigned the same hard register), | |
2951 | then it is better to reload the other operand, as there may | |
2952 | exist yet another operand with a matching constraint associated | |
2953 | with the earlyclobber operand. However, if one of the operands | |
2954 | is an explicit use of a hard register, then we must reload the | |
2955 | other non-hard register operand. */ | |
2956 | if (HARD_REGISTER_P (operand_reg[i]) | |
2957 | || (first_conflict_j == last_conflict_j | |
2958 | && operand_reg[last_conflict_j] != NULL_RTX | |
2959 | && !curr_alt_match_win[last_conflict_j] | |
2960 | && !HARD_REGISTER_P (operand_reg[last_conflict_j]))) | |
1c86bd80 | 2961 | { |
2194f7a2 VM |
2962 | curr_alt_win[last_conflict_j] = false; |
2963 | curr_alt_dont_inherit_ops[curr_alt_dont_inherit_ops_num++] | |
2964 | = last_conflict_j; | |
1c86bd80 | 2965 | losers++; |
cb1cca12 VM |
2966 | if (lra_dump_file != NULL) |
2967 | fprintf | |
2968 | (lra_dump_file, | |
2969 | " %d Conflict early clobber reload: reject--\n", | |
2970 | i); | |
1c86bd80 | 2971 | } |
55a2c322 VM |
2972 | else |
2973 | { | |
1c86bd80 VM |
2974 | /* We need to reload early clobbered register and the |
2975 | matched registers. */ | |
2976 | for (j = 0; j < n_operands; j++) | |
2977 | if (curr_alt_matches[j] == i) | |
2978 | { | |
2979 | curr_alt_match_win[j] = false; | |
2980 | losers++; | |
2981 | overall += LRA_LOSER_COST_FACTOR; | |
2982 | } | |
2983 | if (! curr_alt_match_win[i]) | |
2984 | curr_alt_dont_inherit_ops[curr_alt_dont_inherit_ops_num++] = i; | |
2985 | else | |
2986 | { | |
2987 | /* Remember pseudos used for match reloads are never | |
2988 | inherited. */ | |
2989 | lra_assert (curr_alt_matches[i] >= 0); | |
2990 | curr_alt_win[curr_alt_matches[i]] = false; | |
2991 | } | |
2992 | curr_alt_win[i] = curr_alt_match_win[i] = false; | |
2993 | losers++; | |
cb1cca12 VM |
2994 | if (lra_dump_file != NULL) |
2995 | fprintf | |
2996 | (lra_dump_file, | |
aa326bfb | 2997 | " %d Matched conflict early clobber reloads: " |
cb1cca12 VM |
2998 | "reject--\n", |
2999 | i); | |
dbe7895c AS |
3000 | } |
3001 | /* Early clobber was already reflected in REJECT. */ | |
3002 | if (!matching_early_clobber[i]) | |
3003 | { | |
3004 | lra_assert (reject > 0); | |
deca73f5 | 3005 | reject--; |
dbe7895c | 3006 | matching_early_clobber[i] = 1; |
55a2c322 | 3007 | } |
dbe7895c | 3008 | overall += LRA_LOSER_COST_FACTOR - 1; |
55a2c322 | 3009 | } |
deca73f5 | 3010 | if (lra_dump_file != NULL) |
36ff9dfb VM |
3011 | fprintf (lra_dump_file, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n", |
3012 | nalt, overall, losers, reload_nregs); | |
deca73f5 | 3013 | |
55a2c322 VM |
3014 | /* If this alternative can be made to work by reloading, and it |
3015 | needs less reloading than the others checked so far, record | |
3016 | it as the chosen goal for reloading. */ | |
3017 | if ((best_losers != 0 && losers == 0) | |
3018 | || (((best_losers == 0 && losers == 0) | |
3019 | || (best_losers != 0 && losers != 0)) | |
3020 | && (best_overall > overall | |
3021 | || (best_overall == overall | |
3022 | /* If the cost of the reloads is the same, | |
3023 | prefer alternative which requires minimal | |
36ff9dfb VM |
3024 | number of reload regs. */ |
3025 | && (reload_nregs < best_reload_nregs | |
3026 | || (reload_nregs == best_reload_nregs | |
f15feaf9 VM |
3027 | && (best_reload_sum < reload_sum |
3028 | || (best_reload_sum == reload_sum | |
3029 | && nalt < goal_alt_number)))))))) | |
55a2c322 VM |
3030 | { |
3031 | for (nop = 0; nop < n_operands; nop++) | |
3032 | { | |
3033 | goal_alt_win[nop] = curr_alt_win[nop]; | |
3034 | goal_alt_match_win[nop] = curr_alt_match_win[nop]; | |
3035 | goal_alt_matches[nop] = curr_alt_matches[nop]; | |
3036 | goal_alt[nop] = curr_alt[nop]; | |
3037 | goal_alt_offmemok[nop] = curr_alt_offmemok[nop]; | |
3038 | } | |
3039 | goal_alt_dont_inherit_ops_num = curr_alt_dont_inherit_ops_num; | |
3040 | for (nop = 0; nop < curr_alt_dont_inherit_ops_num; nop++) | |
3041 | goal_alt_dont_inherit_ops[nop] = curr_alt_dont_inherit_ops[nop]; | |
3042 | goal_alt_swapped = curr_swapped; | |
3043 | best_overall = overall; | |
3044 | best_losers = losers; | |
55a2c322 VM |
3045 | best_reload_nregs = reload_nregs; |
3046 | best_reload_sum = reload_sum; | |
3047 | goal_alt_number = nalt; | |
3048 | } | |
3049 | if (losers == 0) | |
3050 | /* Everything is satisfied. Do not process alternatives | |
f4eafc30 | 3051 | anymore. */ |
55a2c322 VM |
3052 | break; |
3053 | fail: | |
3054 | ; | |
3055 | } | |
3056 | return ok_p; | |
3057 | } | |
3058 | ||
c31d2d11 RS |
3059 | /* Make reload base reg from address AD. */ |
3060 | static rtx | |
3061 | base_to_reg (struct address_info *ad) | |
3062 | { | |
3063 | enum reg_class cl; | |
3064 | int code = -1; | |
3065 | rtx new_inner = NULL_RTX; | |
3066 | rtx new_reg = NULL_RTX; | |
fee3e72c DM |
3067 | rtx_insn *insn; |
3068 | rtx_insn *last_insn = get_last_insn(); | |
c31d2d11 | 3069 | |
0a001dcb | 3070 | lra_assert (ad->disp == ad->disp_term); |
c31d2d11 RS |
3071 | cl = base_reg_class (ad->mode, ad->as, ad->base_outer_code, |
3072 | get_index_code (ad)); | |
0a001dcb | 3073 | new_reg = lra_create_new_reg (GET_MODE (*ad->base), NULL_RTX, |
c31d2d11 RS |
3074 | cl, "base"); |
3075 | new_inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), new_reg, | |
3076 | ad->disp_term == NULL | |
0a001dcb | 3077 | ? const0_rtx |
c31d2d11 RS |
3078 | : *ad->disp_term); |
3079 | if (!valid_address_p (ad->mode, new_inner, ad->as)) | |
3080 | return NULL_RTX; | |
0a001dcb | 3081 | insn = emit_insn (gen_rtx_SET (new_reg, *ad->base)); |
c31d2d11 RS |
3082 | code = recog_memoized (insn); |
3083 | if (code < 0) | |
3084 | { | |
3085 | delete_insns_since (last_insn); | |
3086 | return NULL_RTX; | |
3087 | } | |
3088 | ||
3089 | return new_inner; | |
3090 | } | |
3091 | ||
9005477f | 3092 | /* Make reload base reg + DISP from address AD. Return the new pseudo. */ |
55a2c322 | 3093 | static rtx |
9005477f | 3094 | base_plus_disp_to_reg (struct address_info *ad, rtx disp) |
55a2c322 VM |
3095 | { |
3096 | enum reg_class cl; | |
3097 | rtx new_reg; | |
3098 | ||
9005477f | 3099 | lra_assert (ad->base == ad->base_term); |
277f65de RS |
3100 | cl = base_reg_class (ad->mode, ad->as, ad->base_outer_code, |
3101 | get_index_code (ad)); | |
3102 | new_reg = lra_create_new_reg (GET_MODE (*ad->base_term), NULL_RTX, | |
3103 | cl, "base + disp"); | |
9005477f | 3104 | lra_emit_add (new_reg, *ad->base_term, disp); |
55a2c322 VM |
3105 | return new_reg; |
3106 | } | |
3107 | ||
6e071b1e VM |
3108 | /* Make reload of index part of address AD. Return the new |
3109 | pseudo. */ | |
3110 | static rtx | |
3111 | index_part_to_reg (struct address_info *ad) | |
3112 | { | |
3113 | rtx new_reg; | |
3114 | ||
3115 | new_reg = lra_create_new_reg (GET_MODE (*ad->index), NULL_RTX, | |
3116 | INDEX_REG_CLASS, "index term"); | |
3117 | expand_mult (GET_MODE (*ad->index), *ad->index_term, | |
3118 | GEN_INT (get_index_scale (ad)), new_reg, 1); | |
3119 | return new_reg; | |
3120 | } | |
3121 | ||
277f65de RS |
3122 | /* Return true if we can add a displacement to address AD, even if that |
3123 | makes the address invalid. The fix-up code requires any new address | |
3124 | to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */ | |
02ea4bf4 | 3125 | static bool |
277f65de | 3126 | can_add_disp_p (struct address_info *ad) |
02ea4bf4 | 3127 | { |
277f65de RS |
3128 | return (!ad->autoinc_p |
3129 | && ad->segment == NULL | |
3130 | && ad->base == ad->base_term | |
3131 | && ad->disp == ad->disp_term); | |
02ea4bf4 RS |
3132 | } |
3133 | ||
277f65de RS |
3134 | /* Make equiv substitution in address AD. Return true if a substitution |
3135 | was made. */ | |
55a2c322 | 3136 | static bool |
277f65de | 3137 | equiv_address_substitution (struct address_info *ad) |
55a2c322 | 3138 | { |
277f65de | 3139 | rtx base_reg, new_base_reg, index_reg, new_index_reg, *base_term, *index_term; |
73ca989c RS |
3140 | poly_int64 disp; |
3141 | HOST_WIDE_INT scale; | |
55a2c322 VM |
3142 | bool change_p; |
3143 | ||
277f65de RS |
3144 | base_term = strip_subreg (ad->base_term); |
3145 | if (base_term == NULL) | |
55a2c322 VM |
3146 | base_reg = new_base_reg = NULL_RTX; |
3147 | else | |
3148 | { | |
277f65de | 3149 | base_reg = *base_term; |
8d49e7ef | 3150 | new_base_reg = get_equiv_with_elimination (base_reg, curr_insn); |
55a2c322 | 3151 | } |
277f65de RS |
3152 | index_term = strip_subreg (ad->index_term); |
3153 | if (index_term == NULL) | |
55a2c322 VM |
3154 | index_reg = new_index_reg = NULL_RTX; |
3155 | else | |
3156 | { | |
277f65de | 3157 | index_reg = *index_term; |
8d49e7ef | 3158 | new_index_reg = get_equiv_with_elimination (index_reg, curr_insn); |
55a2c322 VM |
3159 | } |
3160 | if (base_reg == new_base_reg && index_reg == new_index_reg) | |
3161 | return false; | |
3162 | disp = 0; | |
3163 | change_p = false; | |
3164 | if (lra_dump_file != NULL) | |
3165 | { | |
3166 | fprintf (lra_dump_file, "Changing address in insn %d ", | |
3167 | INSN_UID (curr_insn)); | |
cfbeaedf | 3168 | dump_value_slim (lra_dump_file, *ad->outer, 1); |
55a2c322 VM |
3169 | } |
3170 | if (base_reg != new_base_reg) | |
3171 | { | |
73ca989c | 3172 | poly_int64 offset; |
55a2c322 VM |
3173 | if (REG_P (new_base_reg)) |
3174 | { | |
277f65de | 3175 | *base_term = new_base_reg; |
55a2c322 VM |
3176 | change_p = true; |
3177 | } | |
3178 | else if (GET_CODE (new_base_reg) == PLUS | |
3179 | && REG_P (XEXP (new_base_reg, 0)) | |
73ca989c | 3180 | && poly_int_rtx_p (XEXP (new_base_reg, 1), &offset) |
277f65de | 3181 | && can_add_disp_p (ad)) |
55a2c322 | 3182 | { |
73ca989c | 3183 | disp += offset; |
277f65de | 3184 | *base_term = XEXP (new_base_reg, 0); |
55a2c322 VM |
3185 | change_p = true; |
3186 | } | |
277f65de RS |
3187 | if (ad->base_term2 != NULL) |
3188 | *ad->base_term2 = *ad->base_term; | |
55a2c322 | 3189 | } |
55a2c322 VM |
3190 | if (index_reg != new_index_reg) |
3191 | { | |
73ca989c | 3192 | poly_int64 offset; |
55a2c322 VM |
3193 | if (REG_P (new_index_reg)) |
3194 | { | |
277f65de | 3195 | *index_term = new_index_reg; |
55a2c322 VM |
3196 | change_p = true; |
3197 | } | |
3198 | else if (GET_CODE (new_index_reg) == PLUS | |
3199 | && REG_P (XEXP (new_index_reg, 0)) | |
73ca989c | 3200 | && poly_int_rtx_p (XEXP (new_index_reg, 1), &offset) |
277f65de | 3201 | && can_add_disp_p (ad) |
02ea4bf4 | 3202 | && (scale = get_index_scale (ad))) |
55a2c322 | 3203 | { |
73ca989c | 3204 | disp += offset * scale; |
277f65de | 3205 | *index_term = XEXP (new_index_reg, 0); |
55a2c322 VM |
3206 | change_p = true; |
3207 | } | |
3208 | } | |
73ca989c | 3209 | if (maybe_ne (disp, 0)) |
55a2c322 | 3210 | { |
277f65de RS |
3211 | if (ad->disp != NULL) |
3212 | *ad->disp = plus_constant (GET_MODE (*ad->inner), *ad->disp, disp); | |
55a2c322 VM |
3213 | else |
3214 | { | |
277f65de RS |
3215 | *ad->inner = plus_constant (GET_MODE (*ad->inner), *ad->inner, disp); |
3216 | update_address (ad); | |
55a2c322 VM |
3217 | } |
3218 | change_p = true; | |
3219 | } | |
3220 | if (lra_dump_file != NULL) | |
3221 | { | |
3222 | if (! change_p) | |
3223 | fprintf (lra_dump_file, " -- no change\n"); | |
3224 | else | |
3225 | { | |
3226 | fprintf (lra_dump_file, " on equiv "); | |
cfbeaedf | 3227 | dump_value_slim (lra_dump_file, *ad->outer, 1); |
55a2c322 VM |
3228 | fprintf (lra_dump_file, "\n"); |
3229 | } | |
3230 | } | |
3231 | return change_p; | |
3232 | } | |
3233 | ||
d9cf932c VM |
3234 | /* Major function to make reloads for an address in operand NOP or |
3235 | check its correctness (If CHECK_ONLY_P is true). The supported | |
3236 | cases are: | |
bd3d34d4 | 3237 | |
5a107a0f VM |
3238 | 1) an address that existed before LRA started, at which point it |
3239 | must have been valid. These addresses are subject to elimination | |
3240 | and may have become invalid due to the elimination offset being out | |
3241 | of range. | |
bd3d34d4 | 3242 | |
5a107a0f VM |
3243 | 2) an address created by forcing a constant to memory |
3244 | (force_const_to_mem). The initial form of these addresses might | |
3245 | not be valid, and it is this function's job to make them valid. | |
bd3d34d4 RS |
3246 | |
3247 | 3) a frame address formed from a register and a (possibly zero) | |
5a107a0f VM |
3248 | constant offset. As above, these addresses might not be valid and |
3249 | this function must make them so. | |
bd3d34d4 RS |
3250 | |
3251 | Add reloads to the lists *BEFORE and *AFTER. We might need to add | |
55a2c322 | 3252 | reloads to *AFTER because of inc/dec, {pre, post} modify in the |
cc8849a1 VM |
3253 | address. Return true for any RTL change. |
3254 | ||
3255 | The function is a helper function which does not produce all | |
d9cf932c VM |
3256 | transformations (when CHECK_ONLY_P is false) which can be |
3257 | necessary. It does just basic steps. To do all necessary | |
3258 | transformations use function process_address. */ | |
55a2c322 | 3259 | static bool |
d9cf932c VM |
3260 | process_address_1 (int nop, bool check_only_p, |
3261 | rtx_insn **before, rtx_insn **after) | |
55a2c322 | 3262 | { |
277f65de RS |
3263 | struct address_info ad; |
3264 | rtx new_reg; | |
bc2fc1f3 | 3265 | HOST_WIDE_INT scale; |
55a2c322 VM |
3266 | rtx op = *curr_id->operand_loc[nop]; |
3267 | const char *constraint = curr_static_id->operand[nop].constraint; | |
777e635f | 3268 | enum constraint_num cn = lookup_constraint (constraint); |
d9cf932c | 3269 | bool change_p = false; |
55a2c322 | 3270 | |
823bb054 SB |
3271 | if (MEM_P (op) |
3272 | && GET_MODE (op) == BLKmode | |
3273 | && GET_CODE (XEXP (op, 0)) == SCRATCH) | |
3274 | return false; | |
3275 | ||
998fd141 AO |
3276 | if (insn_extra_address_constraint (cn) |
3277 | /* When we find an asm operand with an address constraint that | |
3278 | doesn't satisfy address_operand to begin with, we clear | |
3279 | is_address, so that we don't try to make a non-address fit. | |
3280 | If the asm statement got this far, it's because other | |
3281 | constraints are available, and we'll use them, disregarding | |
3282 | the unsatisfiable address ones. */ | |
3283 | && curr_static_id->operand[nop].is_address) | |
277f65de | 3284 | decompose_lea_address (&ad, curr_id->operand_loc[nop]); |
164f0634 EB |
3285 | /* Do not attempt to decompose arbitrary addresses generated by combine |
3286 | for asm operands with loose constraints, e.g 'X'. */ | |
3287 | else if (MEM_P (op) | |
a81a0bfa TP |
3288 | && !(INSN_CODE (curr_insn) < 0 |
3289 | && get_constraint_type (cn) == CT_FIXED_FORM | |
164f0634 | 3290 | && constraint_satisfied_p (op, cn))) |
277f65de | 3291 | decompose_mem_address (&ad, op); |
55a2c322 VM |
3292 | else if (GET_CODE (op) == SUBREG |
3293 | && MEM_P (SUBREG_REG (op))) | |
277f65de | 3294 | decompose_mem_address (&ad, SUBREG_REG (op)); |
55a2c322 VM |
3295 | else |
3296 | return false; | |
70712859 KK |
3297 | /* If INDEX_REG_CLASS is assigned to base_term already and isn't to |
3298 | index_term, swap them so to avoid assigning INDEX_REG_CLASS to both | |
3299 | when INDEX_REG_CLASS is a single register class. */ | |
3300 | if (ad.base_term != NULL | |
3301 | && ad.index_term != NULL | |
3302 | && ira_class_hard_regs_num[INDEX_REG_CLASS] == 1 | |
3303 | && REG_P (*ad.base_term) | |
3304 | && REG_P (*ad.index_term) | |
3305 | && in_class_p (*ad.base_term, INDEX_REG_CLASS, NULL) | |
3306 | && ! in_class_p (*ad.index_term, INDEX_REG_CLASS, NULL)) | |
3307 | { | |
3308 | std::swap (ad.base, ad.index); | |
3309 | std::swap (ad.base_term, ad.index_term); | |
3310 | } | |
d9cf932c VM |
3311 | if (! check_only_p) |
3312 | change_p = equiv_address_substitution (&ad); | |
277f65de | 3313 | if (ad.base_term != NULL |
55a2c322 | 3314 | && (process_addr_reg |
d9cf932c | 3315 | (ad.base_term, check_only_p, before, |
277f65de RS |
3316 | (ad.autoinc_p |
3317 | && !(REG_P (*ad.base_term) | |
3318 | && find_regno_note (curr_insn, REG_DEAD, | |
3319 | REGNO (*ad.base_term)) != NULL_RTX) | |
55a2c322 | 3320 | ? after : NULL), |
277f65de RS |
3321 | base_reg_class (ad.mode, ad.as, ad.base_outer_code, |
3322 | get_index_code (&ad))))) | |
55a2c322 VM |
3323 | { |
3324 | change_p = true; | |
277f65de RS |
3325 | if (ad.base_term2 != NULL) |
3326 | *ad.base_term2 = *ad.base_term; | |
55a2c322 | 3327 | } |
277f65de | 3328 | if (ad.index_term != NULL |
d9cf932c VM |
3329 | && process_addr_reg (ad.index_term, check_only_p, |
3330 | before, NULL, INDEX_REG_CLASS)) | |
55a2c322 VM |
3331 | change_p = true; |
3332 | ||
777e635f RS |
3333 | /* Target hooks sometimes don't treat extra-constraint addresses as |
3334 | legitimate address_operands, so handle them specially. */ | |
8677664e | 3335 | if (insn_extra_address_constraint (cn) |
777e635f | 3336 | && satisfies_address_constraint_p (&ad, cn)) |
2c62cbaa | 3337 | return change_p; |
2c62cbaa | 3338 | |
d9cf932c VM |
3339 | if (check_only_p) |
3340 | return change_p; | |
3341 | ||
277f65de | 3342 | /* There are three cases where the shape of *AD.INNER may now be invalid: |
bd3d34d4 RS |
3343 | |
3344 | 1) the original address was valid, but either elimination or | |
5a107a0f VM |
3345 | equiv_address_substitution was applied and that made |
3346 | the address invalid. | |
bd3d34d4 RS |
3347 | |
3348 | 2) the address is an invalid symbolic address created by | |
5a107a0f | 3349 | force_const_to_mem. |
bd3d34d4 RS |
3350 | |
3351 | 3) the address is a frame address with an invalid offset. | |
3352 | ||
c31d2d11 RS |
3353 | 4) the address is a frame address with an invalid base. |
3354 | ||
2c62cbaa VM |
3355 | All these cases involve a non-autoinc address, so there is no |
3356 | point revalidating other types. */ | |
3357 | if (ad.autoinc_p || valid_address_p (&ad)) | |
55a2c322 VM |
3358 | return change_p; |
3359 | ||
bd3d34d4 RS |
3360 | /* Any index existed before LRA started, so we can assume that the |
3361 | presence and shape of the index is valid. */ | |
55a2c322 | 3362 | push_to_sequence (*before); |
2c62cbaa | 3363 | lra_assert (ad.disp == ad.disp_term); |
277f65de | 3364 | if (ad.base == NULL) |
55a2c322 | 3365 | { |
277f65de | 3366 | if (ad.index == NULL) |
55a2c322 | 3367 | { |
95831c01 VM |
3368 | rtx_insn *insn; |
3369 | rtx_insn *last = get_last_insn (); | |
55a2c322 | 3370 | int code = -1; |
277f65de RS |
3371 | enum reg_class cl = base_reg_class (ad.mode, ad.as, |
3372 | SCRATCH, SCRATCH); | |
2c62cbaa | 3373 | rtx addr = *ad.inner; |
277f65de | 3374 | |
2c62cbaa | 3375 | new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "addr"); |
d0b2266a TS |
3376 | if (HAVE_lo_sum) |
3377 | { | |
d0b2266a TS |
3378 | /* addr => lo_sum (new_base, addr), case (2) above. */ |
3379 | insn = emit_insn (gen_rtx_SET | |
3380 | (new_reg, | |
3381 | gen_rtx_HIGH (Pmode, copy_rtx (addr)))); | |
3382 | code = recog_memoized (insn); | |
3383 | if (code >= 0) | |
3384 | { | |
3385 | *ad.inner = gen_rtx_LO_SUM (Pmode, new_reg, addr); | |
3386 | if (! valid_address_p (ad.mode, *ad.outer, ad.as)) | |
3387 | { | |
3388 | /* Try to put lo_sum into register. */ | |
3389 | insn = emit_insn (gen_rtx_SET | |
3390 | (new_reg, | |
3391 | gen_rtx_LO_SUM (Pmode, new_reg, addr))); | |
3392 | code = recog_memoized (insn); | |
3393 | if (code >= 0) | |
3394 | { | |
3395 | *ad.inner = new_reg; | |
3396 | if (! valid_address_p (ad.mode, *ad.outer, ad.as)) | |
3397 | { | |
3398 | *ad.inner = addr; | |
3399 | code = -1; | |
3400 | } | |
3401 | } | |
3402 | ||
3403 | } | |
3404 | } | |
3405 | if (code < 0) | |
3406 | delete_insns_since (last); | |
3407 | } | |
3408 | ||
55a2c322 VM |
3409 | if (code < 0) |
3410 | { | |
2c62cbaa VM |
3411 | /* addr => new_base, case (2) above. */ |
3412 | lra_emit_move (new_reg, addr); | |
95831c01 VM |
3413 | |
3414 | for (insn = last == NULL_RTX ? get_insns () : NEXT_INSN (last); | |
3415 | insn != NULL_RTX; | |
3416 | insn = NEXT_INSN (insn)) | |
3417 | if (recog_memoized (insn) < 0) | |
3418 | break; | |
3419 | if (insn != NULL_RTX) | |
3420 | { | |
3421 | /* Do nothing if we cannot generate right insns. | |
9c582551 | 3422 | This is analogous to reload pass behavior. */ |
95831c01 VM |
3423 | delete_insns_since (last); |
3424 | end_sequence (); | |
3425 | return false; | |
3426 | } | |
2c62cbaa | 3427 | *ad.inner = new_reg; |
55a2c322 VM |
3428 | } |
3429 | } | |
3430 | else | |
3431 | { | |
bd3d34d4 RS |
3432 | /* index * scale + disp => new base + index * scale, |
3433 | case (1) above. */ | |
277f65de RS |
3434 | enum reg_class cl = base_reg_class (ad.mode, ad.as, PLUS, |
3435 | GET_CODE (*ad.index)); | |
55a2c322 VM |
3436 | |
3437 | lra_assert (INDEX_REG_CLASS != NO_REGS); | |
3438 | new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "disp"); | |
277f65de RS |
3439 | lra_emit_move (new_reg, *ad.disp); |
3440 | *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), | |
3441 | new_reg, *ad.index); | |
55a2c322 VM |
3442 | } |
3443 | } | |
277f65de | 3444 | else if (ad.index == NULL) |
55a2c322 | 3445 | { |
5a107a0f VM |
3446 | int regno; |
3447 | enum reg_class cl; | |
cfa434f6 DM |
3448 | rtx set; |
3449 | rtx_insn *insns, *last_insn; | |
c31d2d11 RS |
3450 | /* Try to reload base into register only if the base is invalid |
3451 | for the address but with valid offset, case (4) above. */ | |
3452 | start_sequence (); | |
3453 | new_reg = base_to_reg (&ad); | |
3454 | ||
bd3d34d4 | 3455 | /* base + disp => new base, cases (1) and (3) above. */ |
55a2c322 VM |
3456 | /* Another option would be to reload the displacement into an |
3457 | index register. However, postreload has code to optimize | |
3458 | address reloads that have the same base and different | |
3459 | displacements, so reloading into an index register would | |
3460 | not necessarily be a win. */ | |
c31d2d11 | 3461 | if (new_reg == NULL_RTX) |
9005477f RS |
3462 | { |
3463 | /* See if the target can split the displacement into a | |
3464 | legitimate new displacement from a local anchor. */ | |
3465 | gcc_assert (ad.disp == ad.disp_term); | |
3466 | poly_int64 orig_offset; | |
3467 | rtx offset1, offset2; | |
3468 | if (poly_int_rtx_p (*ad.disp, &orig_offset) | |
3469 | && targetm.legitimize_address_displacement (&offset1, &offset2, | |
3470 | orig_offset, | |
3471 | ad.mode)) | |
3472 | { | |
3473 | new_reg = base_plus_disp_to_reg (&ad, offset1); | |
3474 | new_reg = gen_rtx_PLUS (GET_MODE (new_reg), new_reg, offset2); | |
3475 | } | |
3476 | else | |
3477 | new_reg = base_plus_disp_to_reg (&ad, *ad.disp); | |
3478 | } | |
5a107a0f VM |
3479 | insns = get_insns (); |
3480 | last_insn = get_last_insn (); | |
3481 | /* If we generated at least two insns, try last insn source as | |
3482 | an address. If we succeed, we generate one less insn. */ | |
9005477f RS |
3483 | if (REG_P (new_reg) |
3484 | && last_insn != insns | |
3485 | && (set = single_set (last_insn)) != NULL_RTX | |
5a107a0f VM |
3486 | && GET_CODE (SET_SRC (set)) == PLUS |
3487 | && REG_P (XEXP (SET_SRC (set), 0)) | |
3488 | && CONSTANT_P (XEXP (SET_SRC (set), 1))) | |
3489 | { | |
3490 | *ad.inner = SET_SRC (set); | |
3491 | if (valid_address_p (ad.mode, *ad.outer, ad.as)) | |
3492 | { | |
3493 | *ad.base_term = XEXP (SET_SRC (set), 0); | |
3494 | *ad.disp_term = XEXP (SET_SRC (set), 1); | |
3495 | cl = base_reg_class (ad.mode, ad.as, ad.base_outer_code, | |
3496 | get_index_code (&ad)); | |
3497 | regno = REGNO (*ad.base_term); | |
3498 | if (regno >= FIRST_PSEUDO_REGISTER | |
3499 | && cl != lra_get_allocno_class (regno)) | |
a2d0d374 | 3500 | lra_change_class (regno, cl, " Change to", true); |
5a107a0f VM |
3501 | new_reg = SET_SRC (set); |
3502 | delete_insns_since (PREV_INSN (last_insn)); | |
3503 | } | |
3504 | } | |
3505 | end_sequence (); | |
3506 | emit_insn (insns); | |
277f65de | 3507 | *ad.inner = new_reg; |
55a2c322 | 3508 | } |
6e071b1e | 3509 | else if (ad.disp_term != NULL) |
55a2c322 | 3510 | { |
bd3d34d4 RS |
3511 | /* base + scale * index + disp => new base + scale * index, |
3512 | case (1) above. */ | |
9005477f RS |
3513 | gcc_assert (ad.disp == ad.disp_term); |
3514 | new_reg = base_plus_disp_to_reg (&ad, *ad.disp); | |
277f65de RS |
3515 | *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), |
3516 | new_reg, *ad.index); | |
55a2c322 | 3517 | } |
bc2fc1f3 | 3518 | else if ((scale = get_index_scale (&ad)) == 1) |
5a770e01 VM |
3519 | { |
3520 | /* The last transformation to one reg will be made in | |
3521 | curr_insn_transform function. */ | |
3522 | end_sequence (); | |
3523 | return false; | |
3524 | } | |
bc2fc1f3 | 3525 | else if (scale != 0) |
6e071b1e VM |
3526 | { |
3527 | /* base + scale * index => base + new_reg, | |
3528 | case (1) above. | |
3529 | Index part of address may become invalid. For example, we | |
3530 | changed pseudo on the equivalent memory and a subreg of the | |
3531 | pseudo onto the memory of different mode for which the scale is | |
3532 | prohibitted. */ | |
3533 | new_reg = index_part_to_reg (&ad); | |
3534 | *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), | |
3535 | *ad.base_term, new_reg); | |
3536 | } | |
bc2fc1f3 VM |
3537 | else |
3538 | { | |
3539 | enum reg_class cl = base_reg_class (ad.mode, ad.as, | |
3540 | SCRATCH, SCRATCH); | |
3541 | rtx addr = *ad.inner; | |
3542 | ||
3543 | new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "addr"); | |
3544 | /* addr => new_base. */ | |
3545 | lra_emit_move (new_reg, addr); | |
3546 | *ad.inner = new_reg; | |
3547 | } | |
55a2c322 VM |
3548 | *before = get_insns (); |
3549 | end_sequence (); | |
3550 | return true; | |
3551 | } | |
3552 | ||
d9cf932c VM |
3553 | /* If CHECK_ONLY_P is false, do address reloads until it is necessary. |
3554 | Use process_address_1 as a helper function. Return true for any | |
3555 | RTL changes. | |
3556 | ||
3557 | If CHECK_ONLY_P is true, just check address correctness. Return | |
3558 | false if the address correct. */ | |
cc8849a1 | 3559 | static bool |
d9cf932c VM |
3560 | process_address (int nop, bool check_only_p, |
3561 | rtx_insn **before, rtx_insn **after) | |
cc8849a1 VM |
3562 | { |
3563 | bool res = false; | |
3564 | ||
d9cf932c VM |
3565 | while (process_address_1 (nop, check_only_p, before, after)) |
3566 | { | |
3567 | if (check_only_p) | |
3568 | return true; | |
3569 | res = true; | |
3570 | } | |
cc8849a1 VM |
3571 | return res; |
3572 | } | |
3573 | ||
55a2c322 VM |
3574 | /* Emit insns to reload VALUE into a new register. VALUE is an |
3575 | auto-increment or auto-decrement RTX whose operand is a register or | |
3576 | memory location; so reloading involves incrementing that location. | |
3577 | IN is either identical to VALUE, or some cheaper place to reload | |
3578 | value being incremented/decremented from. | |
3579 | ||
3580 | INC_AMOUNT is the number to increment or decrement by (always | |
3581 | positive and ignored for POST_MODIFY/PRE_MODIFY). | |
3582 | ||
3583 | Return pseudo containing the result. */ | |
3584 | static rtx | |
31ae0e43 | 3585 | emit_inc (enum reg_class new_rclass, rtx in, rtx value, poly_int64 inc_amount) |
55a2c322 VM |
3586 | { |
3587 | /* REG or MEM to be copied and incremented. */ | |
3588 | rtx incloc = XEXP (value, 0); | |
3589 | /* Nonzero if increment after copying. */ | |
3590 | int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC | |
3591 | || GET_CODE (value) == POST_MODIFY); | |
cfa434f6 | 3592 | rtx_insn *last; |
55a2c322 | 3593 | rtx inc; |
647d790d | 3594 | rtx_insn *add_insn; |
55a2c322 VM |
3595 | int code; |
3596 | rtx real_in = in == value ? incloc : in; | |
3597 | rtx result; | |
3598 | bool plus_p = true; | |
3599 | ||
3600 | if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY) | |
3601 | { | |
3602 | lra_assert (GET_CODE (XEXP (value, 1)) == PLUS | |
3603 | || GET_CODE (XEXP (value, 1)) == MINUS); | |
3604 | lra_assert (rtx_equal_p (XEXP (XEXP (value, 1), 0), XEXP (value, 0))); | |
3605 | plus_p = GET_CODE (XEXP (value, 1)) == PLUS; | |
3606 | inc = XEXP (XEXP (value, 1), 1); | |
3607 | } | |
3608 | else | |
3609 | { | |
3610 | if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC) | |
3611 | inc_amount = -inc_amount; | |
3612 | ||
31ae0e43 | 3613 | inc = gen_int_mode (inc_amount, GET_MODE (value)); |
55a2c322 VM |
3614 | } |
3615 | ||
3616 | if (! post && REG_P (incloc)) | |
3617 | result = incloc; | |
3618 | else | |
3619 | result = lra_create_new_reg (GET_MODE (value), value, new_rclass, | |
3620 | "INC/DEC result"); | |
3621 | ||
3622 | if (real_in != result) | |
3623 | { | |
3624 | /* First copy the location to the result register. */ | |
3625 | lra_assert (REG_P (result)); | |
3626 | emit_insn (gen_move_insn (result, real_in)); | |
3627 | } | |
3628 | ||
3629 | /* We suppose that there are insns to add/sub with the constant | |
3630 | increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the | |
3631 | old reload worked with this assumption. If the assumption | |
3632 | becomes wrong, we should use approach in function | |
3633 | base_plus_disp_to_reg. */ | |
3634 | if (in == value) | |
3635 | { | |
3636 | /* See if we can directly increment INCLOC. */ | |
3637 | last = get_last_insn (); | |
3638 | add_insn = emit_insn (plus_p | |
3639 | ? gen_add2_insn (incloc, inc) | |
3640 | : gen_sub2_insn (incloc, inc)); | |
3641 | ||
3642 | code = recog_memoized (add_insn); | |
3643 | if (code >= 0) | |
3644 | { | |
3645 | if (! post && result != incloc) | |
3646 | emit_insn (gen_move_insn (result, incloc)); | |
3647 | return result; | |
3648 | } | |
3649 | delete_insns_since (last); | |
3650 | } | |
3651 | ||
3652 | /* If couldn't do the increment directly, must increment in RESULT. | |
3653 | The way we do this depends on whether this is pre- or | |
3654 | post-increment. For pre-increment, copy INCLOC to the reload | |
3655 | register, increment it there, then save back. */ | |
3656 | if (! post) | |
3657 | { | |
3658 | if (real_in != result) | |
3659 | emit_insn (gen_move_insn (result, real_in)); | |
3660 | if (plus_p) | |
3661 | emit_insn (gen_add2_insn (result, inc)); | |
3662 | else | |
3663 | emit_insn (gen_sub2_insn (result, inc)); | |
3664 | if (result != incloc) | |
3665 | emit_insn (gen_move_insn (incloc, result)); | |
3666 | } | |
3667 | else | |
3668 | { | |
3669 | /* Post-increment. | |
3670 | ||
3671 | Because this might be a jump insn or a compare, and because | |
3672 | RESULT may not be available after the insn in an input | |
3673 | reload, we must do the incrementing before the insn being | |
3674 | reloaded for. | |
3675 | ||
3676 | We have already copied IN to RESULT. Increment the copy in | |
3677 | RESULT, save that back, then decrement RESULT so it has | |
3678 | the original value. */ | |
3679 | if (plus_p) | |
3680 | emit_insn (gen_add2_insn (result, inc)); | |
3681 | else | |
3682 | emit_insn (gen_sub2_insn (result, inc)); | |
3683 | emit_insn (gen_move_insn (incloc, result)); | |
3684 | /* Restore non-modified value for the result. We prefer this | |
3685 | way because it does not require an additional hard | |
3686 | register. */ | |
3687 | if (plus_p) | |
3688 | { | |
73ca989c RS |
3689 | poly_int64 offset; |
3690 | if (poly_int_rtx_p (inc, &offset)) | |
69db2d57 | 3691 | emit_insn (gen_add2_insn (result, |
73ca989c | 3692 | gen_int_mode (-offset, |
69db2d57 | 3693 | GET_MODE (result)))); |
55a2c322 VM |
3694 | else |
3695 | emit_insn (gen_sub2_insn (result, inc)); | |
3696 | } | |
3697 | else | |
3698 | emit_insn (gen_add2_insn (result, inc)); | |
3699 | } | |
3700 | return result; | |
3701 | } | |
3702 | ||
2c62cbaa VM |
3703 | /* Return true if the current move insn does not need processing as we |
3704 | already know that it satisfies its constraints. */ | |
3705 | static bool | |
3706 | simple_move_p (void) | |
3707 | { | |
3708 | rtx dest, src; | |
3709 | enum reg_class dclass, sclass; | |
3710 | ||
3711 | lra_assert (curr_insn_set != NULL_RTX); | |
3712 | dest = SET_DEST (curr_insn_set); | |
3713 | src = SET_SRC (curr_insn_set); | |
2008be40 SB |
3714 | |
3715 | /* If the instruction has multiple sets we need to process it even if it | |
3716 | is single_set. This can happen if one or more of the SETs are dead. | |
3717 | See PR73650. */ | |
3718 | if (multiple_sets (curr_insn)) | |
3719 | return false; | |
3720 | ||
2c62cbaa VM |
3721 | return ((dclass = get_op_class (dest)) != NO_REGS |
3722 | && (sclass = get_op_class (src)) != NO_REGS | |
3723 | /* The backend guarantees that register moves of cost 2 | |
3724 | never need reloads. */ | |
03b9b5ce | 3725 | && targetm.register_move_cost (GET_MODE (src), sclass, dclass) == 2); |
2c62cbaa VM |
3726 | } |
3727 | ||
55a2c322 VM |
3728 | /* Swap operands NOP and NOP + 1. */ |
3729 | static inline void | |
3730 | swap_operands (int nop) | |
3731 | { | |
fab27f52 MM |
3732 | std::swap (curr_operand_mode[nop], curr_operand_mode[nop + 1]); |
3733 | std::swap (original_subreg_reg_mode[nop], original_subreg_reg_mode[nop + 1]); | |
3734 | std::swap (*curr_id->operand_loc[nop], *curr_id->operand_loc[nop + 1]); | |
987b67f1 | 3735 | std::swap (equiv_substition_p[nop], equiv_substition_p[nop + 1]); |
55a2c322 VM |
3736 | /* Swap the duplicates too. */ |
3737 | lra_update_dup (curr_id, nop); | |
3738 | lra_update_dup (curr_id, nop + 1); | |
3739 | } | |
3740 | ||
3741 | /* Main entry point of the constraint code: search the body of the | |
3742 | current insn to choose the best alternative. It is mimicking insn | |
3743 | alternative cost calculation model of former reload pass. That is | |
3744 | because machine descriptions were written to use this model. This | |
3745 | model can be changed in future. Make commutative operand exchange | |
3746 | if it is chosen. | |
3747 | ||
d9cf932c VM |
3748 | if CHECK_ONLY_P is false, do RTL changes to satisfy the |
3749 | constraints. Return true if any change happened during function | |
3750 | call. | |
3751 | ||
3752 | If CHECK_ONLY_P is true then don't do any transformation. Just | |
3753 | check that the insn satisfies all constraints. If the insn does | |
3754 | not satisfy any constraint, return true. */ | |
55a2c322 | 3755 | static bool |
d9cf932c | 3756 | curr_insn_transform (bool check_only_p) |
55a2c322 VM |
3757 | { |
3758 | int i, j, k; | |
3759 | int n_operands; | |
3760 | int n_alternatives; | |
aefae0f1 | 3761 | int n_outputs; |
55a2c322 VM |
3762 | int commutative; |
3763 | signed char goal_alt_matched[MAX_RECOG_OPERANDS][MAX_RECOG_OPERANDS]; | |
511dcace | 3764 | signed char match_inputs[MAX_RECOG_OPERANDS + 1]; |
aefae0f1 | 3765 | signed char outputs[MAX_RECOG_OPERANDS + 1]; |
cfa434f6 | 3766 | rtx_insn *before, *after; |
55a2c322 VM |
3767 | bool alt_p = false; |
3768 | /* Flag that the insn has been changed through a transformation. */ | |
3769 | bool change_p; | |
3770 | bool sec_mem_p; | |
55a2c322 | 3771 | bool use_sec_mem_p; |
55a2c322 VM |
3772 | int max_regno_before; |
3773 | int reused_alternative_num; | |
3774 | ||
2c62cbaa VM |
3775 | curr_insn_set = single_set (curr_insn); |
3776 | if (curr_insn_set != NULL_RTX && simple_move_p ()) | |
7874b7c5 VM |
3777 | { |
3778 | /* We assume that the corresponding insn alternative has no | |
3779 | earlier clobbers. If it is not the case, don't define move | |
3780 | cost equal to 2 for the corresponding register classes. */ | |
3781 | lra_set_used_insn_alternative (curr_insn, LRA_NON_CLOBBERED_ALT); | |
3782 | return false; | |
3783 | } | |
2c62cbaa | 3784 | |
55a2c322 VM |
3785 | no_input_reloads_p = no_output_reloads_p = false; |
3786 | goal_alt_number = -1; | |
2c62cbaa | 3787 | change_p = sec_mem_p = false; |
55a2c322 VM |
3788 | /* JUMP_INSNs and CALL_INSNs are not allowed to have any output |
3789 | reloads; neither are insns that SET cc0. Insns that use CC0 are | |
3790 | not allowed to have any input reloads. */ | |
3791 | if (JUMP_P (curr_insn) || CALL_P (curr_insn)) | |
3792 | no_output_reloads_p = true; | |
3793 | ||
058eb3b0 | 3794 | if (HAVE_cc0 && reg_referenced_p (cc0_rtx, PATTERN (curr_insn))) |
55a2c322 | 3795 | no_input_reloads_p = true; |
058eb3b0 | 3796 | if (HAVE_cc0 && reg_set_p (cc0_rtx, PATTERN (curr_insn))) |
55a2c322 | 3797 | no_output_reloads_p = true; |
55a2c322 VM |
3798 | |
3799 | n_operands = curr_static_id->n_operands; | |
3800 | n_alternatives = curr_static_id->n_alternatives; | |
3801 | ||
3802 | /* Just return "no reloads" if insn has no operands with | |
3803 | constraints. */ | |
3804 | if (n_operands == 0 || n_alternatives == 0) | |
3805 | return false; | |
3806 | ||
3807 | max_regno_before = max_reg_num (); | |
3808 | ||
3809 | for (i = 0; i < n_operands; i++) | |
3810 | { | |
3811 | goal_alt_matched[i][0] = -1; | |
3812 | goal_alt_matches[i] = -1; | |
3813 | } | |
3814 | ||
3815 | commutative = curr_static_id->commutative; | |
3816 | ||
3817 | /* Now see what we need for pseudos that didn't get hard regs or got | |
3818 | the wrong kind of hard reg. For this, we must consider all the | |
3819 | operands together against the register constraints. */ | |
3820 | ||
821b7577 | 3821 | best_losers = best_overall = INT_MAX; |
36ff9dfb | 3822 | best_reload_sum = 0; |
55a2c322 VM |
3823 | |
3824 | curr_swapped = false; | |
3825 | goal_alt_swapped = false; | |
3826 | ||
d9cf932c VM |
3827 | if (! check_only_p) |
3828 | /* Make equivalence substitution and memory subreg elimination | |
3829 | before address processing because an address legitimacy can | |
3830 | depend on memory mode. */ | |
3831 | for (i = 0; i < n_operands; i++) | |
3832 | { | |
0b87be09 | 3833 | rtx op, subst, old; |
d9cf932c | 3834 | bool op_change_p = false; |
0b87be09 VM |
3835 | |
3836 | if (curr_static_id->operand[i].is_operator) | |
3837 | continue; | |
d9cf932c | 3838 | |
0b87be09 | 3839 | old = op = *curr_id->operand_loc[i]; |
d9cf932c VM |
3840 | if (GET_CODE (old) == SUBREG) |
3841 | old = SUBREG_REG (old); | |
3842 | subst = get_equiv_with_elimination (old, curr_insn); | |
895ff86f | 3843 | original_subreg_reg_mode[i] = VOIDmode; |
987b67f1 | 3844 | equiv_substition_p[i] = false; |
d9cf932c VM |
3845 | if (subst != old) |
3846 | { | |
987b67f1 | 3847 | equiv_substition_p[i] = true; |
d9cf932c VM |
3848 | subst = copy_rtx (subst); |
3849 | lra_assert (REG_P (old)); | |
895ff86f | 3850 | if (GET_CODE (op) != SUBREG) |
d9cf932c | 3851 | *curr_id->operand_loc[i] = subst; |
895ff86f VM |
3852 | else |
3853 | { | |
3854 | SUBREG_REG (op) = subst; | |
3855 | if (GET_MODE (subst) == VOIDmode) | |
3856 | original_subreg_reg_mode[i] = GET_MODE (old); | |
3857 | } | |
d9cf932c VM |
3858 | if (lra_dump_file != NULL) |
3859 | { | |
3860 | fprintf (lra_dump_file, | |
3861 | "Changing pseudo %d in operand %i of insn %u on equiv ", | |
3862 | REGNO (old), i, INSN_UID (curr_insn)); | |
3863 | dump_value_slim (lra_dump_file, subst, 1); | |
895ff86f | 3864 | fprintf (lra_dump_file, "\n"); |
d9cf932c VM |
3865 | } |
3866 | op_change_p = change_p = true; | |
3867 | } | |
3868 | if (simplify_operand_subreg (i, GET_MODE (old)) || op_change_p) | |
3869 | { | |
3870 | change_p = true; | |
3871 | lra_update_dup (curr_id, i); | |
3872 | } | |
3873 | } | |
55a2c322 VM |
3874 | |
3875 | /* Reload address registers and displacements. We do it before | |
3876 | finding an alternative because of memory constraints. */ | |
cfa434f6 | 3877 | before = after = NULL; |
55a2c322 VM |
3878 | for (i = 0; i < n_operands; i++) |
3879 | if (! curr_static_id->operand[i].is_operator | |
d9cf932c | 3880 | && process_address (i, check_only_p, &before, &after)) |
55a2c322 | 3881 | { |
d9cf932c VM |
3882 | if (check_only_p) |
3883 | return true; | |
55a2c322 VM |
3884 | change_p = true; |
3885 | lra_update_dup (curr_id, i); | |
3886 | } | |
cc8849a1 | 3887 | |
55a2c322 VM |
3888 | if (change_p) |
3889 | /* If we've changed the instruction then any alternative that | |
3890 | we chose previously may no longer be valid. */ | |
7874b7c5 | 3891 | lra_set_used_insn_alternative (curr_insn, LRA_UNKNOWN_ALT); |
55a2c322 | 3892 | |
d9cf932c | 3893 | if (! check_only_p && curr_insn_set != NULL_RTX |
2c62cbaa VM |
3894 | && check_and_process_move (&change_p, &sec_mem_p)) |
3895 | return change_p; | |
3896 | ||
55a2c322 VM |
3897 | try_swapped: |
3898 | ||
7874b7c5 | 3899 | reused_alternative_num = check_only_p ? LRA_UNKNOWN_ALT : curr_id->used_insn_alternative; |
55a2c322 VM |
3900 | if (lra_dump_file != NULL && reused_alternative_num >= 0) |
3901 | fprintf (lra_dump_file, "Reusing alternative %d for insn #%u\n", | |
3902 | reused_alternative_num, INSN_UID (curr_insn)); | |
3903 | ||
3904 | if (process_alt_operands (reused_alternative_num)) | |
3905 | alt_p = true; | |
3906 | ||
d9cf932c VM |
3907 | if (check_only_p) |
3908 | return ! alt_p || best_losers != 0; | |
3909 | ||
55a2c322 VM |
3910 | /* If insn is commutative (it's safe to exchange a certain pair of |
3911 | operands) then we need to try each alternative twice, the second | |
3912 | time matching those two operands as if we had exchanged them. To | |
3913 | do this, really exchange them in operands. | |
3914 | ||
3915 | If we have just tried the alternatives the second time, return | |
3916 | operands to normal and drop through. */ | |
3917 | ||
3918 | if (reused_alternative_num < 0 && commutative >= 0) | |
3919 | { | |
3920 | curr_swapped = !curr_swapped; | |
3921 | if (curr_swapped) | |
3922 | { | |
3923 | swap_operands (commutative); | |
3924 | goto try_swapped; | |
3925 | } | |
3926 | else | |
3927 | swap_operands (commutative); | |
3928 | } | |
3929 | ||
55a2c322 VM |
3930 | if (! alt_p && ! sec_mem_p) |
3931 | { | |
3932 | /* No alternative works with reloads?? */ | |
3933 | if (INSN_CODE (curr_insn) >= 0) | |
3934 | fatal_insn ("unable to generate reloads for:", curr_insn); | |
3935 | error_for_asm (curr_insn, | |
3936 | "inconsistent operand constraints in an %<asm%>"); | |
8b4aea73 VM |
3937 | /* Avoid further trouble with this insn. Don't generate use |
3938 | pattern here as we could use the insn SP offset. */ | |
3939 | lra_set_insn_deleted (curr_insn); | |
55a2c322 VM |
3940 | return true; |
3941 | } | |
3942 | ||
3943 | /* If the best alternative is with operands 1 and 2 swapped, swap | |
3944 | them. Update the operand numbers of any reloads already | |
3945 | pushed. */ | |
3946 | ||
3947 | if (goal_alt_swapped) | |
3948 | { | |
3949 | if (lra_dump_file != NULL) | |
3950 | fprintf (lra_dump_file, " Commutative operand exchange in insn %u\n", | |
3951 | INSN_UID (curr_insn)); | |
3952 | ||
3953 | /* Swap the duplicates too. */ | |
3954 | swap_operands (commutative); | |
3955 | change_p = true; | |
3956 | } | |
3957 | ||
f15643d4 | 3958 | /* Some targets' TARGET_SECONDARY_MEMORY_NEEDED (e.g. x86) are defined |
55a2c322 VM |
3959 | too conservatively. So we use the secondary memory only if there |
3960 | is no any alternative without reloads. */ | |
3961 | use_sec_mem_p = false; | |
3962 | if (! alt_p) | |
3963 | use_sec_mem_p = true; | |
3964 | else if (sec_mem_p) | |
3965 | { | |
3966 | for (i = 0; i < n_operands; i++) | |
3967 | if (! goal_alt_win[i] && ! goal_alt_match_win[i]) | |
3968 | break; | |
3969 | use_sec_mem_p = i < n_operands; | |
3970 | } | |
3971 | ||
3972 | if (use_sec_mem_p) | |
3973 | { | |
e03dd765 | 3974 | int in = -1, out = -1; |
89d56d79 | 3975 | rtx new_reg, src, dest, rld; |
ef4bddc2 | 3976 | machine_mode sec_mode, rld_mode; |
55a2c322 | 3977 | |
e03dd765 VM |
3978 | lra_assert (curr_insn_set != NULL_RTX && sec_mem_p); |
3979 | dest = SET_DEST (curr_insn_set); | |
3980 | src = SET_SRC (curr_insn_set); | |
3981 | for (i = 0; i < n_operands; i++) | |
3982 | if (*curr_id->operand_loc[i] == dest) | |
3983 | out = i; | |
3984 | else if (*curr_id->operand_loc[i] == src) | |
3985 | in = i; | |
3986 | for (i = 0; i < curr_static_id->n_dups; i++) | |
3987 | if (out < 0 && *curr_id->dup_loc[i] == dest) | |
3988 | out = curr_static_id->dup_num[i]; | |
3989 | else if (in < 0 && *curr_id->dup_loc[i] == src) | |
3990 | in = curr_static_id->dup_num[i]; | |
3991 | lra_assert (out >= 0 && in >= 0 | |
3992 | && curr_static_id->operand[out].type == OP_OUT | |
3993 | && curr_static_id->operand[in].type == OP_IN); | |
bd4288c0 | 3994 | rld = partial_subreg_p (GET_MODE (src), GET_MODE (dest)) ? src : dest; |
66aa7879 | 3995 | rld_mode = GET_MODE (rld); |
94e23f53 | 3996 | sec_mode = targetm.secondary_memory_needed_mode (rld_mode); |
55a2c322 VM |
3997 | new_reg = lra_create_new_reg (sec_mode, NULL_RTX, |
3998 | NO_REGS, "secondary"); | |
3999 | /* If the mode is changed, it should be wider. */ | |
bd4288c0 | 4000 | lra_assert (!partial_subreg_p (sec_mode, rld_mode)); |
89d56d79 VM |
4001 | if (sec_mode != rld_mode) |
4002 | { | |
4003 | /* If the target says specifically to use another mode for | |
4004 | secondary memory moves we can not reuse the original | |
4005 | insn. */ | |
1ccd4874 | 4006 | after = emit_spill_move (false, new_reg, dest); |
cfa434f6 | 4007 | lra_process_new_insns (curr_insn, NULL, after, |
1ccd4874 VM |
4008 | "Inserting the sec. move"); |
4009 | /* We may have non null BEFORE here (e.g. after address | |
4010 | processing. */ | |
4011 | push_to_sequence (before); | |
4012 | before = emit_spill_move (true, new_reg, src); | |
4013 | emit_insn (before); | |
4014 | before = get_insns (); | |
4015 | end_sequence (); | |
cfa434f6 | 4016 | lra_process_new_insns (curr_insn, before, NULL, "Changing on"); |
1ccd4874 VM |
4017 | lra_set_insn_deleted (curr_insn); |
4018 | } | |
89d56d79 | 4019 | else if (dest == rld) |
1ccd4874 | 4020 | { |
e03dd765 VM |
4021 | *curr_id->operand_loc[out] = new_reg; |
4022 | lra_update_dup (curr_id, out); | |
66aa7879 | 4023 | after = emit_spill_move (false, new_reg, dest); |
cfa434f6 | 4024 | lra_process_new_insns (curr_insn, NULL, after, |
66aa7879 VM |
4025 | "Inserting the sec. move"); |
4026 | } | |
4027 | else | |
4028 | { | |
e03dd765 VM |
4029 | *curr_id->operand_loc[in] = new_reg; |
4030 | lra_update_dup (curr_id, in); | |
1ccd4874 VM |
4031 | /* See comments above. */ |
4032 | push_to_sequence (before); | |
66aa7879 | 4033 | before = emit_spill_move (true, new_reg, src); |
1ccd4874 VM |
4034 | emit_insn (before); |
4035 | before = get_insns (); | |
4036 | end_sequence (); | |
cfa434f6 | 4037 | lra_process_new_insns (curr_insn, before, NULL, |
66aa7879 VM |
4038 | "Inserting the sec. move"); |
4039 | } | |
4040 | lra_update_insn_regno_info (curr_insn); | |
55a2c322 VM |
4041 | return true; |
4042 | } | |
55a2c322 VM |
4043 | |
4044 | lra_assert (goal_alt_number >= 0); | |
4045 | lra_set_used_insn_alternative (curr_insn, goal_alt_number); | |
4046 | ||
4047 | if (lra_dump_file != NULL) | |
4048 | { | |
4049 | const char *p; | |
4050 | ||
4051 | fprintf (lra_dump_file, " Choosing alt %d in insn %u:", | |
4052 | goal_alt_number, INSN_UID (curr_insn)); | |
4053 | for (i = 0; i < n_operands; i++) | |
4054 | { | |
4055 | p = (curr_static_id->operand_alternative | |
4056 | [goal_alt_number * n_operands + i].constraint); | |
4057 | if (*p == '\0') | |
4058 | continue; | |
4059 | fprintf (lra_dump_file, " (%d) ", i); | |
4060 | for (; *p != '\0' && *p != ',' && *p != '#'; p++) | |
4061 | fputc (*p, lra_dump_file); | |
4062 | } | |
36ff9dfb VM |
4063 | if (INSN_CODE (curr_insn) >= 0 |
4064 | && (p = get_insn_name (INSN_CODE (curr_insn))) != NULL) | |
4065 | fprintf (lra_dump_file, " {%s}", p); | |
73ca989c RS |
4066 | if (maybe_ne (curr_id->sp_offset, 0)) |
4067 | { | |
4068 | fprintf (lra_dump_file, " (sp_off="); | |
4069 | print_dec (curr_id->sp_offset, lra_dump_file); | |
4070 | fprintf (lra_dump_file, ")"); | |
4071 | } | |
4072 | fprintf (lra_dump_file, "\n"); | |
55a2c322 VM |
4073 | } |
4074 | ||
4075 | /* Right now, for any pair of operands I and J that are required to | |
4076 | match, with J < I, goal_alt_matches[I] is J. Add I to | |
4077 | goal_alt_matched[J]. */ | |
f4eafc30 | 4078 | |
55a2c322 VM |
4079 | for (i = 0; i < n_operands; i++) |
4080 | if ((j = goal_alt_matches[i]) >= 0) | |
4081 | { | |
4082 | for (k = 0; goal_alt_matched[j][k] >= 0; k++) | |
4083 | ; | |
4084 | /* We allow matching one output operand and several input | |
4085 | operands. */ | |
4086 | lra_assert (k == 0 | |
4087 | || (curr_static_id->operand[j].type == OP_OUT | |
4088 | && curr_static_id->operand[i].type == OP_IN | |
4089 | && (curr_static_id->operand | |
4090 | [goal_alt_matched[j][0]].type == OP_IN))); | |
4091 | goal_alt_matched[j][k] = i; | |
4092 | goal_alt_matched[j][k + 1] = -1; | |
4093 | } | |
f4eafc30 | 4094 | |
55a2c322 VM |
4095 | for (i = 0; i < n_operands; i++) |
4096 | goal_alt_win[i] |= goal_alt_match_win[i]; | |
f4eafc30 | 4097 | |
55a2c322 VM |
4098 | /* Any constants that aren't allowed and can't be reloaded into |
4099 | registers are here changed into memory references. */ | |
4100 | for (i = 0; i < n_operands; i++) | |
4101 | if (goal_alt_win[i]) | |
4102 | { | |
4103 | int regno; | |
4104 | enum reg_class new_class; | |
4105 | rtx reg = *curr_id->operand_loc[i]; | |
4106 | ||
4107 | if (GET_CODE (reg) == SUBREG) | |
4108 | reg = SUBREG_REG (reg); | |
f4eafc30 | 4109 | |
55a2c322 VM |
4110 | if (REG_P (reg) && (regno = REGNO (reg)) >= FIRST_PSEUDO_REGISTER) |
4111 | { | |
4112 | bool ok_p = in_class_p (reg, goal_alt[i], &new_class); | |
4113 | ||
4114 | if (new_class != NO_REGS && get_reg_class (regno) != new_class) | |
4115 | { | |
4116 | lra_assert (ok_p); | |
a2d0d374 | 4117 | lra_change_class (regno, new_class, " Change to", true); |
55a2c322 VM |
4118 | } |
4119 | } | |
4120 | } | |
4121 | else | |
4122 | { | |
4123 | const char *constraint; | |
4124 | char c; | |
4125 | rtx op = *curr_id->operand_loc[i]; | |
4126 | rtx subreg = NULL_RTX; | |
ef4bddc2 | 4127 | machine_mode mode = curr_operand_mode[i]; |
f4eafc30 | 4128 | |
55a2c322 VM |
4129 | if (GET_CODE (op) == SUBREG) |
4130 | { | |
4131 | subreg = op; | |
4132 | op = SUBREG_REG (op); | |
4133 | mode = GET_MODE (op); | |
4134 | } | |
f4eafc30 | 4135 | |
55a2c322 VM |
4136 | if (CONST_POOL_OK_P (mode, op) |
4137 | && ((targetm.preferred_reload_class | |
4138 | (op, (enum reg_class) goal_alt[i]) == NO_REGS) | |
4139 | || no_input_reloads_p)) | |
4140 | { | |
4141 | rtx tem = force_const_mem (mode, op); | |
f4eafc30 | 4142 | |
55a2c322 VM |
4143 | change_p = true; |
4144 | if (subreg != NULL_RTX) | |
4145 | tem = gen_rtx_SUBREG (mode, tem, SUBREG_BYTE (subreg)); | |
f4eafc30 | 4146 | |
55a2c322 VM |
4147 | *curr_id->operand_loc[i] = tem; |
4148 | lra_update_dup (curr_id, i); | |
d9cf932c | 4149 | process_address (i, false, &before, &after); |
f4eafc30 | 4150 | |
55a2c322 VM |
4151 | /* If the alternative accepts constant pool refs directly |
4152 | there will be no reload needed at all. */ | |
4153 | if (subreg != NULL_RTX) | |
4154 | continue; | |
4155 | /* Skip alternatives before the one requested. */ | |
4156 | constraint = (curr_static_id->operand_alternative | |
4157 | [goal_alt_number * n_operands + i].constraint); | |
4158 | for (; | |
4159 | (c = *constraint) && c != ',' && c != '#'; | |
4160 | constraint += CONSTRAINT_LEN (c, constraint)) | |
4161 | { | |
777e635f | 4162 | enum constraint_num cn = lookup_constraint (constraint); |
9eb1ca69 VM |
4163 | if ((insn_extra_memory_constraint (cn) |
4164 | || insn_extra_special_memory_constraint (cn)) | |
777e635f | 4165 | && satisfies_memory_constraint_p (tem, cn)) |
55a2c322 | 4166 | break; |
55a2c322 VM |
4167 | } |
4168 | if (c == '\0' || c == ',' || c == '#') | |
4169 | continue; | |
f4eafc30 | 4170 | |
55a2c322 VM |
4171 | goal_alt_win[i] = true; |
4172 | } | |
4173 | } | |
f4eafc30 | 4174 | |
aefae0f1 TP |
4175 | n_outputs = 0; |
4176 | outputs[0] = -1; | |
55a2c322 VM |
4177 | for (i = 0; i < n_operands; i++) |
4178 | { | |
2b778c9d VM |
4179 | int regno; |
4180 | bool optional_p = false; | |
55a2c322 VM |
4181 | rtx old, new_reg; |
4182 | rtx op = *curr_id->operand_loc[i]; | |
4183 | ||
4184 | if (goal_alt_win[i]) | |
4185 | { | |
4186 | if (goal_alt[i] == NO_REGS | |
4187 | && REG_P (op) | |
4188 | /* When we assign NO_REGS it means that we will not | |
4189 | assign a hard register to the scratch pseudo by | |
4190 | assigment pass and the scratch pseudo will be | |
4191 | spilled. Spilled scratch pseudos are transformed | |
4192 | back to scratches at the LRA end. */ | |
6c051d60 VM |
4193 | && lra_former_scratch_operand_p (curr_insn, i) |
4194 | && lra_former_scratch_p (REGNO (op))) | |
deca73f5 VM |
4195 | { |
4196 | int regno = REGNO (op); | |
a2d0d374 | 4197 | lra_change_class (regno, NO_REGS, " Change to", true); |
deca73f5 VM |
4198 | if (lra_get_regno_hard_regno (regno) >= 0) |
4199 | /* We don't have to mark all insn affected by the | |
4200 | spilled pseudo as there is only one such insn, the | |
4201 | current one. */ | |
4202 | reg_renumber[regno] = -1; | |
6c051d60 VM |
4203 | lra_assert (bitmap_single_bit_set_p |
4204 | (&lra_reg_info[REGNO (op)].insn_bitmap)); | |
deca73f5 | 4205 | } |
2b778c9d VM |
4206 | /* We can do an optional reload. If the pseudo got a hard |
4207 | reg, we might improve the code through inheritance. If | |
4208 | it does not get a hard register we coalesce memory/memory | |
4209 | moves later. Ignore move insns to avoid cycling. */ | |
b0681c9e | 4210 | if (! lra_simple_p |
2b778c9d VM |
4211 | && lra_undo_inheritance_iter < LRA_MAX_INHERITANCE_PASSES |
4212 | && goal_alt[i] != NO_REGS && REG_P (op) | |
4213 | && (regno = REGNO (op)) >= FIRST_PSEUDO_REGISTER | |
a2d0d374 | 4214 | && regno < new_regno_start |
b0681c9e | 4215 | && ! lra_former_scratch_p (regno) |
2b778c9d | 4216 | && reg_renumber[regno] < 0 |
3c954213 VM |
4217 | /* Check that the optional reload pseudo will be able to |
4218 | hold given mode value. */ | |
4219 | && ! (prohibited_class_reg_set_mode_p | |
4220 | (goal_alt[i], reg_class_contents[goal_alt[i]], | |
4221 | PSEUDO_REGNO_MODE (regno))) | |
2b778c9d | 4222 | && (curr_insn_set == NULL_RTX |
b0681c9e VM |
4223 | || !((REG_P (SET_SRC (curr_insn_set)) |
4224 | || MEM_P (SET_SRC (curr_insn_set)) | |
4225 | || GET_CODE (SET_SRC (curr_insn_set)) == SUBREG) | |
4226 | && (REG_P (SET_DEST (curr_insn_set)) | |
4227 | || MEM_P (SET_DEST (curr_insn_set)) | |
4228 | || GET_CODE (SET_DEST (curr_insn_set)) == SUBREG)))) | |
2b778c9d VM |
4229 | optional_p = true; |
4230 | else | |
4231 | continue; | |
55a2c322 | 4232 | } |
f4eafc30 | 4233 | |
55a2c322 VM |
4234 | /* Operands that match previous ones have already been handled. */ |
4235 | if (goal_alt_matches[i] >= 0) | |
4236 | continue; | |
4237 | ||
4238 | /* We should not have an operand with a non-offsettable address | |
4239 | appearing where an offsettable address will do. It also may | |
4240 | be a case when the address should be special in other words | |
4241 | not a general one (e.g. it needs no index reg). */ | |
4242 | if (goal_alt_matched[i][0] == -1 && goal_alt_offmemok[i] && MEM_P (op)) | |
4243 | { | |
4244 | enum reg_class rclass; | |
4245 | rtx *loc = &XEXP (op, 0); | |
4246 | enum rtx_code code = GET_CODE (*loc); | |
4247 | ||
4248 | push_to_sequence (before); | |
4249 | rclass = base_reg_class (GET_MODE (op), MEM_ADDR_SPACE (op), | |
4250 | MEM, SCRATCH); | |
4251 | if (GET_RTX_CLASS (code) == RTX_AUTOINC) | |
4252 | new_reg = emit_inc (rclass, *loc, *loc, | |
4253 | /* This value does not matter for MODIFY. */ | |
4254 | GET_MODE_SIZE (GET_MODE (op))); | |
95921002 | 4255 | else if (get_reload_reg (OP_IN, Pmode, *loc, rclass, FALSE, |
55a2c322 | 4256 | "offsetable address", &new_reg)) |
634c3ff0 VM |
4257 | { |
4258 | rtx addr = *loc; | |
4259 | enum rtx_code code = GET_CODE (addr); | |
4260 | ||
4261 | if (code == AND && CONST_INT_P (XEXP (addr, 1))) | |
4262 | /* (and ... (const_int -X)) is used to align to X bytes. */ | |
4263 | addr = XEXP (*loc, 0); | |
4264 | lra_emit_move (new_reg, addr); | |
4265 | if (addr != *loc) | |
4266 | emit_move_insn (new_reg, gen_rtx_AND (GET_MODE (new_reg), new_reg, XEXP (*loc, 1))); | |
4267 | } | |
55a2c322 VM |
4268 | before = get_insns (); |
4269 | end_sequence (); | |
4270 | *loc = new_reg; | |
4271 | lra_update_dup (curr_id, i); | |
4272 | } | |
4273 | else if (goal_alt_matched[i][0] == -1) | |
4274 | { | |
ef4bddc2 | 4275 | machine_mode mode; |
55a2c322 | 4276 | rtx reg, *loc; |
91914e56 | 4277 | int hard_regno; |
55a2c322 VM |
4278 | enum op_type type = curr_static_id->operand[i].type; |
4279 | ||
4280 | loc = curr_id->operand_loc[i]; | |
4281 | mode = curr_operand_mode[i]; | |
4282 | if (GET_CODE (*loc) == SUBREG) | |
4283 | { | |
4284 | reg = SUBREG_REG (*loc); | |
91914e56 | 4285 | poly_int64 byte = SUBREG_BYTE (*loc); |
55a2c322 | 4286 | if (REG_P (reg) |
8e02e8a0 MF |
4287 | /* Strict_low_part requires reloading the register and not |
4288 | just the subreg. Likewise for a strict subreg no wider | |
4289 | than a word for WORD_REGISTER_OPERATIONS targets. */ | |
55a2c322 | 4290 | && (curr_static_id->operand[i].strict_low |
03a95621 | 4291 | || (!paradoxical_subreg_p (mode, GET_MODE (reg)) |
55a2c322 VM |
4292 | && (hard_regno |
4293 | = get_try_hard_regno (REGNO (reg))) >= 0 | |
4294 | && (simplify_subreg_regno | |
4295 | (hard_regno, | |
4296 | GET_MODE (reg), byte, mode) < 0) | |
4297 | && (goal_alt[i] == NO_REGS | |
4298 | || (simplify_subreg_regno | |
4299 | (ira_class_hard_regs[goal_alt[i]][0], | |
8e02e8a0 | 4300 | GET_MODE (reg), byte, mode) >= 0))) |
e5f83886 | 4301 | || (partial_subreg_p (mode, GET_MODE (reg)) |
cf098191 RS |
4302 | && known_le (GET_MODE_SIZE (GET_MODE (reg)), |
4303 | UNITS_PER_WORD) | |
8e02e8a0 | 4304 | && WORD_REGISTER_OPERATIONS))) |
55a2c322 | 4305 | { |
62cdb862 MF |
4306 | /* An OP_INOUT is required when reloading a subreg of a |
4307 | mode wider than a word to ensure that data beyond the | |
4308 | word being reloaded is preserved. Also automatically | |
4309 | ensure that strict_low_part reloads are made into | |
4310 | OP_INOUT which should already be true from the backend | |
4311 | constraints. */ | |
4312 | if (type == OP_OUT | |
4313 | && (curr_static_id->operand[i].strict_low | |
9eaf97d6 | 4314 | || read_modify_subreg_p (*loc))) |
8b8e23de | 4315 | type = OP_INOUT; |
55a2c322 VM |
4316 | loc = &SUBREG_REG (*loc); |
4317 | mode = GET_MODE (*loc); | |
4318 | } | |
4319 | } | |
4320 | old = *loc; | |
95921002 VM |
4321 | if (get_reload_reg (type, mode, old, goal_alt[i], |
4322 | loc != curr_id->operand_loc[i], "", &new_reg) | |
55a2c322 VM |
4323 | && type != OP_OUT) |
4324 | { | |
4325 | push_to_sequence (before); | |
4326 | lra_emit_move (new_reg, old); | |
4327 | before = get_insns (); | |
4328 | end_sequence (); | |
4329 | } | |
4330 | *loc = new_reg; | |
4331 | if (type != OP_IN | |
4332 | && find_reg_note (curr_insn, REG_UNUSED, old) == NULL_RTX) | |
4333 | { | |
4334 | start_sequence (); | |
4335 | lra_emit_move (type == OP_INOUT ? copy_rtx (old) : old, new_reg); | |
4336 | emit_insn (after); | |
4337 | after = get_insns (); | |
4338 | end_sequence (); | |
4339 | *loc = new_reg; | |
4340 | } | |
4341 | for (j = 0; j < goal_alt_dont_inherit_ops_num; j++) | |
4342 | if (goal_alt_dont_inherit_ops[j] == i) | |
4343 | { | |
4344 | lra_set_regno_unique_value (REGNO (new_reg)); | |
4345 | break; | |
4346 | } | |
4347 | lra_update_dup (curr_id, i); | |
4348 | } | |
4349 | else if (curr_static_id->operand[i].type == OP_IN | |
4350 | && (curr_static_id->operand[goal_alt_matched[i][0]].type | |
57d69a63 VM |
4351 | == OP_OUT |
4352 | || (curr_static_id->operand[goal_alt_matched[i][0]].type | |
4353 | == OP_INOUT | |
4354 | && (operands_match_p | |
4355 | (*curr_id->operand_loc[i], | |
4356 | *curr_id->operand_loc[goal_alt_matched[i][0]], | |
4357 | -1))))) | |
55a2c322 | 4358 | { |
511dcace VM |
4359 | /* generate reloads for input and matched outputs. */ |
4360 | match_inputs[0] = i; | |
4361 | match_inputs[1] = -1; | |
aefae0f1 | 4362 | match_reload (goal_alt_matched[i][0], match_inputs, outputs, |
599e1cf8 VM |
4363 | goal_alt[i], &before, &after, |
4364 | curr_static_id->operand_alternative | |
4365 | [goal_alt_number * n_operands + goal_alt_matched[i][0]] | |
4366 | .earlyclobber); | |
55a2c322 | 4367 | } |
57d69a63 VM |
4368 | else if ((curr_static_id->operand[i].type == OP_OUT |
4369 | || (curr_static_id->operand[i].type == OP_INOUT | |
4370 | && (operands_match_p | |
4371 | (*curr_id->operand_loc[i], | |
4372 | *curr_id->operand_loc[goal_alt_matched[i][0]], | |
4373 | -1)))) | |
55a2c322 | 4374 | && (curr_static_id->operand[goal_alt_matched[i][0]].type |
57d69a63 | 4375 | == OP_IN)) |
511dcace | 4376 | /* Generate reloads for output and matched inputs. */ |
aefae0f1 TP |
4377 | match_reload (i, goal_alt_matched[i], outputs, goal_alt[i], &before, |
4378 | &after, curr_static_id->operand_alternative | |
4379 | [goal_alt_number * n_operands + i].earlyclobber); | |
511dcace VM |
4380 | else if (curr_static_id->operand[i].type == OP_IN |
4381 | && (curr_static_id->operand[goal_alt_matched[i][0]].type | |
4382 | == OP_IN)) | |
4383 | { | |
4384 | /* Generate reloads for matched inputs. */ | |
4385 | match_inputs[0] = i; | |
4386 | for (j = 0; (k = goal_alt_matched[i][j]) >= 0; j++) | |
4387 | match_inputs[j + 1] = k; | |
4388 | match_inputs[j + 1] = -1; | |
aefae0f1 TP |
4389 | match_reload (-1, match_inputs, outputs, goal_alt[i], &before, |
4390 | &after, false); | |
511dcace | 4391 | } |
55a2c322 VM |
4392 | else |
4393 | /* We must generate code in any case when function | |
4394 | process_alt_operands decides that it is possible. */ | |
4395 | gcc_unreachable (); | |
aefae0f1 TP |
4396 | |
4397 | /* Memorise processed outputs so that output remaining to be processed | |
4398 | can avoid using the same register value (see match_reload). */ | |
4399 | if (curr_static_id->operand[i].type == OP_OUT) | |
4400 | { | |
4401 | outputs[n_outputs++] = i; | |
4402 | outputs[n_outputs] = -1; | |
4403 | } | |
4404 | ||
2b778c9d VM |
4405 | if (optional_p) |
4406 | { | |
8a8330b7 VM |
4407 | rtx reg = op; |
4408 | ||
4409 | lra_assert (REG_P (reg)); | |
4410 | regno = REGNO (reg); | |
2b778c9d VM |
4411 | op = *curr_id->operand_loc[i]; /* Substitution. */ |
4412 | if (GET_CODE (op) == SUBREG) | |
4413 | op = SUBREG_REG (op); | |
4414 | gcc_assert (REG_P (op) && (int) REGNO (op) >= new_regno_start); | |
4415 | bitmap_set_bit (&lra_optional_reload_pseudos, REGNO (op)); | |
8a8330b7 | 4416 | lra_reg_info[REGNO (op)].restore_rtx = reg; |
2b778c9d VM |
4417 | if (lra_dump_file != NULL) |
4418 | fprintf (lra_dump_file, | |
4419 | " Making reload reg %d for reg %d optional\n", | |
4420 | REGNO (op), regno); | |
4421 | } | |
55a2c322 VM |
4422 | } |
4423 | if (before != NULL_RTX || after != NULL_RTX | |
4424 | || max_regno_before != max_reg_num ()) | |
4425 | change_p = true; | |
4426 | if (change_p) | |
4427 | { | |
4428 | lra_update_operator_dups (curr_id); | |
4429 | /* Something changes -- process the insn. */ | |
4430 | lra_update_insn_regno_info (curr_insn); | |
4431 | } | |
4432 | lra_process_new_insns (curr_insn, before, after, "Inserting insn reload"); | |
4433 | return change_p; | |
4434 | } | |
4435 | ||
d9cf932c VM |
4436 | /* Return true if INSN satisfies all constraints. In other words, no |
4437 | reload insns are needed. */ | |
4438 | bool | |
4439 | lra_constrain_insn (rtx_insn *insn) | |
4440 | { | |
4441 | int saved_new_regno_start = new_regno_start; | |
4442 | int saved_new_insn_uid_start = new_insn_uid_start; | |
4443 | bool change_p; | |
4444 | ||
4445 | curr_insn = insn; | |
4446 | curr_id = lra_get_insn_recog_data (curr_insn); | |
4447 | curr_static_id = curr_id->insn_static_data; | |
4448 | new_insn_uid_start = get_max_uid (); | |
4449 | new_regno_start = max_reg_num (); | |
4450 | change_p = curr_insn_transform (true); | |
4451 | new_regno_start = saved_new_regno_start; | |
4452 | new_insn_uid_start = saved_new_insn_uid_start; | |
4453 | return ! change_p; | |
4454 | } | |
4455 | ||
55a2c322 VM |
4456 | /* Return true if X is in LIST. */ |
4457 | static bool | |
4458 | in_list_p (rtx x, rtx list) | |
4459 | { | |
4460 | for (; list != NULL_RTX; list = XEXP (list, 1)) | |
4461 | if (XEXP (list, 0) == x) | |
4462 | return true; | |
4463 | return false; | |
4464 | } | |
4465 | ||
4466 | /* Return true if X contains an allocatable hard register (if | |
4467 | HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */ | |
4468 | static bool | |
4469 | contains_reg_p (rtx x, bool hard_reg_p, bool spilled_p) | |
4470 | { | |
4471 | int i, j; | |
4472 | const char *fmt; | |
4473 | enum rtx_code code; | |
4474 | ||
4475 | code = GET_CODE (x); | |
4476 | if (REG_P (x)) | |
4477 | { | |
4478 | int regno = REGNO (x); | |
4479 | HARD_REG_SET alloc_regs; | |
4480 | ||
4481 | if (hard_reg_p) | |
4482 | { | |
4483 | if (regno >= FIRST_PSEUDO_REGISTER) | |
4484 | regno = lra_get_regno_hard_regno (regno); | |
4485 | if (regno < 0) | |
4486 | return false; | |
4487 | COMPL_HARD_REG_SET (alloc_regs, lra_no_alloc_regs); | |
4488 | return overlaps_hard_reg_set_p (alloc_regs, GET_MODE (x), regno); | |
4489 | } | |
4490 | else | |
4491 | { | |
4492 | if (regno < FIRST_PSEUDO_REGISTER) | |
4493 | return false; | |
4494 | if (! spilled_p) | |
4495 | return true; | |
4496 | return lra_get_regno_hard_regno (regno) < 0; | |
4497 | } | |
4498 | } | |
4499 | fmt = GET_RTX_FORMAT (code); | |
4500 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
4501 | { | |
4502 | if (fmt[i] == 'e') | |
4503 | { | |
4504 | if (contains_reg_p (XEXP (x, i), hard_reg_p, spilled_p)) | |
4505 | return true; | |
4506 | } | |
4507 | else if (fmt[i] == 'E') | |
4508 | { | |
4509 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
4510 | if (contains_reg_p (XVECEXP (x, i, j), hard_reg_p, spilled_p)) | |
4511 | return true; | |
4512 | } | |
4513 | } | |
4514 | return false; | |
4515 | } | |
4516 | ||
28430b2e VM |
4517 | /* Process all regs in location *LOC and change them on equivalent |
4518 | substitution. Return true if any change was done. */ | |
55a2c322 | 4519 | static bool |
28430b2e | 4520 | loc_equivalence_change_p (rtx *loc) |
55a2c322 VM |
4521 | { |
4522 | rtx subst, reg, x = *loc; | |
4523 | bool result = false; | |
4524 | enum rtx_code code = GET_CODE (x); | |
4525 | const char *fmt; | |
4526 | int i, j; | |
4527 | ||
4528 | if (code == SUBREG) | |
4529 | { | |
4530 | reg = SUBREG_REG (x); | |
8d49e7ef | 4531 | if ((subst = get_equiv_with_elimination (reg, curr_insn)) != reg |
55a2c322 VM |
4532 | && GET_MODE (subst) == VOIDmode) |
4533 | { | |
4534 | /* We cannot reload debug location. Simplify subreg here | |
4535 | while we know the inner mode. */ | |
4536 | *loc = simplify_gen_subreg (GET_MODE (x), subst, | |
4537 | GET_MODE (reg), SUBREG_BYTE (x)); | |
4538 | return true; | |
4539 | } | |
4540 | } | |
8d49e7ef | 4541 | if (code == REG && (subst = get_equiv_with_elimination (x, curr_insn)) != x) |
55a2c322 VM |
4542 | { |
4543 | *loc = subst; | |
4544 | return true; | |
4545 | } | |
4546 | ||
4547 | /* Scan all the operand sub-expressions. */ | |
4548 | fmt = GET_RTX_FORMAT (code); | |
4549 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
4550 | { | |
4551 | if (fmt[i] == 'e') | |
28430b2e | 4552 | result = loc_equivalence_change_p (&XEXP (x, i)) || result; |
55a2c322 VM |
4553 | else if (fmt[i] == 'E') |
4554 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
4555 | result | |
28430b2e | 4556 | = loc_equivalence_change_p (&XVECEXP (x, i, j)) || result; |
55a2c322 VM |
4557 | } |
4558 | return result; | |
4559 | } | |
4560 | ||
d0608e59 | 4561 | /* Similar to loc_equivalence_change_p, but for use as |
4c2b2d79 VM |
4562 | simplify_replace_fn_rtx callback. DATA is insn for which the |
4563 | elimination is done. If it null we don't do the elimination. */ | |
d0608e59 | 4564 | static rtx |
4c2b2d79 | 4565 | loc_equivalence_callback (rtx loc, const_rtx, void *data) |
d0608e59 JJ |
4566 | { |
4567 | if (!REG_P (loc)) | |
4568 | return NULL_RTX; | |
4569 | ||
4c2b2d79 | 4570 | rtx subst = (data == NULL |
cfa434f6 | 4571 | ? get_equiv (loc) : get_equiv_with_elimination (loc, (rtx_insn *) data)); |
d0608e59 JJ |
4572 | if (subst != loc) |
4573 | return subst; | |
4574 | ||
4575 | return NULL_RTX; | |
4576 | } | |
4577 | ||
55a2c322 VM |
4578 | /* Maximum number of generated reload insns per an insn. It is for |
4579 | preventing this pass cycling in a bug case. */ | |
4580 | #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS | |
4581 | ||
4582 | /* The current iteration number of this LRA pass. */ | |
4583 | int lra_constraint_iter; | |
4584 | ||
55a2c322 VM |
4585 | /* True if we substituted equiv which needs checking register |
4586 | allocation correctness because the equivalent value contains | |
4587 | allocatable hard registers or when we restore multi-register | |
4588 | pseudo. */ | |
4589 | bool lra_risky_transformations_p; | |
4590 | ||
4591 | /* Return true if REGNO is referenced in more than one block. */ | |
4592 | static bool | |
4593 | multi_block_pseudo_p (int regno) | |
4594 | { | |
4595 | basic_block bb = NULL; | |
4596 | unsigned int uid; | |
4597 | bitmap_iterator bi; | |
f4eafc30 | 4598 | |
55a2c322 VM |
4599 | if (regno < FIRST_PSEUDO_REGISTER) |
4600 | return false; | |
f4eafc30 | 4601 | |
55a2c322 VM |
4602 | EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi) |
4603 | if (bb == NULL) | |
4604 | bb = BLOCK_FOR_INSN (lra_insn_recog_data[uid]->insn); | |
4605 | else if (BLOCK_FOR_INSN (lra_insn_recog_data[uid]->insn) != bb) | |
4606 | return true; | |
4607 | return false; | |
4608 | } | |
4609 | ||
1966c91b VM |
4610 | /* Return true if LIST contains a deleted insn. */ |
4611 | static bool | |
0cc97fc5 | 4612 | contains_deleted_insn_p (rtx_insn_list *list) |
1966c91b | 4613 | { |
0cc97fc5 DM |
4614 | for (; list != NULL_RTX; list = list->next ()) |
4615 | if (NOTE_P (list->insn ()) | |
4616 | && NOTE_KIND (list->insn ()) == NOTE_INSN_DELETED) | |
1966c91b VM |
4617 | return true; |
4618 | return false; | |
4619 | } | |
4620 | ||
55a2c322 VM |
4621 | /* Return true if X contains a pseudo dying in INSN. */ |
4622 | static bool | |
605780f6 | 4623 | dead_pseudo_p (rtx x, rtx_insn *insn) |
55a2c322 VM |
4624 | { |
4625 | int i, j; | |
4626 | const char *fmt; | |
4627 | enum rtx_code code; | |
4628 | ||
4629 | if (REG_P (x)) | |
4630 | return (insn != NULL_RTX | |
4631 | && find_regno_note (insn, REG_DEAD, REGNO (x)) != NULL_RTX); | |
4632 | code = GET_CODE (x); | |
4633 | fmt = GET_RTX_FORMAT (code); | |
4634 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
4635 | { | |
4636 | if (fmt[i] == 'e') | |
4637 | { | |
4638 | if (dead_pseudo_p (XEXP (x, i), insn)) | |
4639 | return true; | |
4640 | } | |
4641 | else if (fmt[i] == 'E') | |
4642 | { | |
4643 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
4644 | if (dead_pseudo_p (XVECEXP (x, i, j), insn)) | |
4645 | return true; | |
4646 | } | |
4647 | } | |
4648 | return false; | |
4649 | } | |
4650 | ||
4651 | /* Return true if INSN contains a dying pseudo in INSN right hand | |
4652 | side. */ | |
4653 | static bool | |
e8a54173 | 4654 | insn_rhs_dead_pseudo_p (rtx_insn *insn) |
55a2c322 VM |
4655 | { |
4656 | rtx set = single_set (insn); | |
4657 | ||
4658 | gcc_assert (set != NULL); | |
4659 | return dead_pseudo_p (SET_SRC (set), insn); | |
4660 | } | |
4661 | ||
4662 | /* Return true if any init insn of REGNO contains a dying pseudo in | |
4663 | insn right hand side. */ | |
4664 | static bool | |
4665 | init_insn_rhs_dead_pseudo_p (int regno) | |
4666 | { | |
0cc97fc5 | 4667 | rtx_insn_list *insns = ira_reg_equiv[regno].init_insns; |
55a2c322 VM |
4668 | |
4669 | if (insns == NULL) | |
4670 | return false; | |
0cc97fc5 DM |
4671 | for (; insns != NULL_RTX; insns = insns->next ()) |
4672 | if (insn_rhs_dead_pseudo_p (insns->insn ())) | |
55a2c322 VM |
4673 | return true; |
4674 | return false; | |
4675 | } | |
4676 | ||
01e54ef8 VM |
4677 | /* Return TRUE if REGNO has a reverse equivalence. The equivalence is |
4678 | reverse only if we have one init insn with given REGNO as a | |
4679 | source. */ | |
4680 | static bool | |
4681 | reverse_equiv_p (int regno) | |
4682 | { | |
0cc97fc5 DM |
4683 | rtx_insn_list *insns = ira_reg_equiv[regno].init_insns; |
4684 | rtx set; | |
01e54ef8 | 4685 | |
0cc97fc5 | 4686 | if (insns == NULL) |
01e54ef8 | 4687 | return false; |
0cc97fc5 DM |
4688 | if (! INSN_P (insns->insn ()) |
4689 | || insns->next () != NULL) | |
01e54ef8 | 4690 | return false; |
0cc97fc5 | 4691 | if ((set = single_set (insns->insn ())) == NULL_RTX) |
01e54ef8 VM |
4692 | return false; |
4693 | return REG_P (SET_SRC (set)) && (int) REGNO (SET_SRC (set)) == regno; | |
4694 | } | |
4695 | ||
4696 | /* Return TRUE if REGNO was reloaded in an equivalence init insn. We | |
4697 | call this function only for non-reverse equivalence. */ | |
4698 | static bool | |
4699 | contains_reloaded_insn_p (int regno) | |
4700 | { | |
4701 | rtx set; | |
0cc97fc5 | 4702 | rtx_insn_list *list = ira_reg_equiv[regno].init_insns; |
01e54ef8 | 4703 | |
0cc97fc5 DM |
4704 | for (; list != NULL; list = list->next ()) |
4705 | if ((set = single_set (list->insn ())) == NULL_RTX | |
01e54ef8 VM |
4706 | || ! REG_P (SET_DEST (set)) |
4707 | || (int) REGNO (SET_DEST (set)) != regno) | |
4708 | return true; | |
4709 | return false; | |
4710 | } | |
4711 | ||
55a2c322 VM |
4712 | /* Entry function of LRA constraint pass. Return true if the |
4713 | constraint pass did change the code. */ | |
4714 | bool | |
4715 | lra_constraints (bool first_p) | |
4716 | { | |
4717 | bool changed_p; | |
4718 | int i, hard_regno, new_insns_num; | |
6cd1dd26 VM |
4719 | unsigned int min_len, new_min_len, uid; |
4720 | rtx set, x, reg, dest_reg; | |
55a2c322 | 4721 | basic_block last_bb; |
6cd1dd26 | 4722 | bitmap_iterator bi; |
55a2c322 VM |
4723 | |
4724 | lra_constraint_iter++; | |
4725 | if (lra_dump_file != NULL) | |
4726 | fprintf (lra_dump_file, "\n********** Local #%d: **********\n\n", | |
4727 | lra_constraint_iter); | |
55a2c322 | 4728 | changed_p = false; |
bcb21886 KY |
4729 | if (pic_offset_table_rtx |
4730 | && REGNO (pic_offset_table_rtx) >= FIRST_PSEUDO_REGISTER) | |
4731 | lra_risky_transformations_p = true; | |
4732 | else | |
15961e4a VM |
4733 | /* On the first iteration we should check IRA assignment |
4734 | correctness. In rare cases, the assignments can be wrong as | |
4735 | early clobbers operands are ignored in IRA. */ | |
4736 | lra_risky_transformations_p = first_p; | |
55a2c322 VM |
4737 | new_insn_uid_start = get_max_uid (); |
4738 | new_regno_start = first_p ? lra_constraint_new_regno_start : max_reg_num (); | |
8d49e7ef VM |
4739 | /* Mark used hard regs for target stack size calulations. */ |
4740 | for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++) | |
4741 | if (lra_reg_info[i].nrefs != 0 | |
4742 | && (hard_regno = lra_get_regno_hard_regno (i)) >= 0) | |
4743 | { | |
4744 | int j, nregs; | |
4745 | ||
ad474626 | 4746 | nregs = hard_regno_nregs (hard_regno, lra_reg_info[i].biggest_mode); |
8d49e7ef VM |
4747 | for (j = 0; j < nregs; j++) |
4748 | df_set_regs_ever_live (hard_regno + j, true); | |
4749 | } | |
4750 | /* Do elimination before the equivalence processing as we can spill | |
4751 | some pseudos during elimination. */ | |
4752 | lra_eliminate (false, first_p); | |
d648b5ff | 4753 | auto_bitmap equiv_insn_bitmap (®_obstack); |
55a2c322 VM |
4754 | for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++) |
4755 | if (lra_reg_info[i].nrefs != 0) | |
4756 | { | |
4757 | ira_reg_equiv[i].profitable_p = true; | |
6cd1dd26 | 4758 | reg = regno_reg_rtx[i]; |
8d49e7ef | 4759 | if (lra_get_regno_hard_regno (i) < 0 && (x = get_equiv (reg)) != reg) |
55a2c322 VM |
4760 | { |
4761 | bool pseudo_p = contains_reg_p (x, false, false); | |
55a2c322 | 4762 | |
1966c91b VM |
4763 | /* After RTL transformation, we can not guarantee that |
4764 | pseudo in the substitution was not reloaded which might | |
4765 | make equivalence invalid. For example, in reverse | |
4766 | equiv of p0 | |
4767 | ||
4768 | p0 <- ... | |
4769 | ... | |
4770 | equiv_mem <- p0 | |
4771 | ||
4772 | the memory address register was reloaded before the 2nd | |
4773 | insn. */ | |
4774 | if ((! first_p && pseudo_p) | |
4775 | /* We don't use DF for compilation speed sake. So it | |
4776 | is problematic to update live info when we use an | |
4777 | equivalence containing pseudos in more than one | |
4778 | BB. */ | |
4779 | || (pseudo_p && multi_block_pseudo_p (i)) | |
4780 | /* If an init insn was deleted for some reason, cancel | |
4781 | the equiv. We could update the equiv insns after | |
4782 | transformations including an equiv insn deletion | |
4783 | but it is not worthy as such cases are extremely | |
4784 | rare. */ | |
4785 | || contains_deleted_insn_p (ira_reg_equiv[i].init_insns) | |
55a2c322 VM |
4786 | /* If it is not a reverse equivalence, we check that a |
4787 | pseudo in rhs of the init insn is not dying in the | |
4788 | insn. Otherwise, the live info at the beginning of | |
4789 | the corresponding BB might be wrong after we | |
4790 | removed the insn. When the equiv can be a | |
4791 | constant, the right hand side of the init insn can | |
4792 | be a pseudo. */ | |
01e54ef8 VM |
4793 | || (! reverse_equiv_p (i) |
4794 | && (init_insn_rhs_dead_pseudo_p (i) | |
4795 | /* If we reloaded the pseudo in an equivalence | |
4796 | init insn, we can not remove the equiv init | |
4797 | insns and the init insns might write into | |
4798 | const memory in this case. */ | |
4799 | || contains_reloaded_insn_p (i))) | |
b28ece32 VM |
4800 | /* Prevent access beyond equivalent memory for |
4801 | paradoxical subregs. */ | |
4802 | || (MEM_P (x) | |
cf098191 RS |
4803 | && maybe_gt (GET_MODE_SIZE (lra_reg_info[i].biggest_mode), |
4804 | GET_MODE_SIZE (GET_MODE (x)))) | |
bcb21886 KY |
4805 | || (pic_offset_table_rtx |
4806 | && ((CONST_POOL_OK_P (PSEUDO_REGNO_MODE (i), x) | |
4807 | && (targetm.preferred_reload_class | |
4808 | (x, lra_get_allocno_class (i)) == NO_REGS)) | |
b81a2f0d | 4809 | || contains_symbol_ref_p (x)))) |
55a2c322 | 4810 | ira_reg_equiv[i].defined_p = false; |
55a2c322 VM |
4811 | if (contains_reg_p (x, false, true)) |
4812 | ira_reg_equiv[i].profitable_p = false; | |
8d49e7ef | 4813 | if (get_equiv (reg) != reg) |
d648b5ff | 4814 | bitmap_ior_into (equiv_insn_bitmap, &lra_reg_info[i].insn_bitmap); |
55a2c322 VM |
4815 | } |
4816 | } | |
4c2b2d79 VM |
4817 | for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++) |
4818 | update_equiv (i); | |
6cd1dd26 VM |
4819 | /* We should add all insns containing pseudos which should be |
4820 | substituted by their equivalences. */ | |
d648b5ff | 4821 | EXECUTE_IF_SET_IN_BITMAP (equiv_insn_bitmap, 0, uid, bi) |
6cd1dd26 | 4822 | lra_push_insn_by_uid (uid); |
55a2c322 VM |
4823 | min_len = lra_insn_stack_length (); |
4824 | new_insns_num = 0; | |
4825 | last_bb = NULL; | |
4826 | changed_p = false; | |
4827 | while ((new_min_len = lra_insn_stack_length ()) != 0) | |
4828 | { | |
4829 | curr_insn = lra_pop_insn (); | |
4830 | --new_min_len; | |
f4eafc30 | 4831 | curr_bb = BLOCK_FOR_INSN (curr_insn); |
55a2c322 VM |
4832 | if (curr_bb != last_bb) |
4833 | { | |
4834 | last_bb = curr_bb; | |
4835 | bb_reload_num = lra_curr_reload_num; | |
4836 | } | |
4837 | if (min_len > new_min_len) | |
4838 | { | |
4839 | min_len = new_min_len; | |
4840 | new_insns_num = 0; | |
4841 | } | |
4842 | if (new_insns_num > MAX_RELOAD_INSNS_NUMBER) | |
4843 | internal_error | |
4844 | ("Max. number of generated reload insns per insn is achieved (%d)\n", | |
4845 | MAX_RELOAD_INSNS_NUMBER); | |
4846 | new_insns_num++; | |
4847 | if (DEBUG_INSN_P (curr_insn)) | |
4848 | { | |
4849 | /* We need to check equivalence in debug insn and change | |
4850 | pseudo to the equivalent value if necessary. */ | |
4851 | curr_id = lra_get_insn_recog_data (curr_insn); | |
d648b5ff | 4852 | if (bitmap_bit_p (equiv_insn_bitmap, INSN_UID (curr_insn))) |
4d64ce5c | 4853 | { |
d0608e59 JJ |
4854 | rtx old = *curr_id->operand_loc[0]; |
4855 | *curr_id->operand_loc[0] | |
4856 | = simplify_replace_fn_rtx (old, NULL_RTX, | |
4c2b2d79 | 4857 | loc_equivalence_callback, curr_insn); |
d0608e59 JJ |
4858 | if (old != *curr_id->operand_loc[0]) |
4859 | { | |
4860 | lra_update_insn_regno_info (curr_insn); | |
4861 | changed_p = true; | |
4862 | } | |
4d64ce5c | 4863 | } |
55a2c322 VM |
4864 | } |
4865 | else if (INSN_P (curr_insn)) | |
4866 | { | |
4867 | if ((set = single_set (curr_insn)) != NULL_RTX) | |
4868 | { | |
4869 | dest_reg = SET_DEST (set); | |
4870 | /* The equivalence pseudo could be set up as SUBREG in a | |
4871 | case when it is a call restore insn in a mode | |
4872 | different from the pseudo mode. */ | |
4873 | if (GET_CODE (dest_reg) == SUBREG) | |
4874 | dest_reg = SUBREG_REG (dest_reg); | |
4875 | if ((REG_P (dest_reg) | |
8d49e7ef | 4876 | && (x = get_equiv (dest_reg)) != dest_reg |
55a2c322 VM |
4877 | /* Remove insns which set up a pseudo whose value |
4878 | can not be changed. Such insns might be not in | |
4879 | init_insns because we don't update equiv data | |
4880 | during insn transformations. | |
5a107a0f | 4881 | |
55a2c322 VM |
4882 | As an example, let suppose that a pseudo got |
4883 | hard register and on the 1st pass was not | |
4884 | changed to equivalent constant. We generate an | |
4885 | additional insn setting up the pseudo because of | |
4886 | secondary memory movement. Then the pseudo is | |
4887 | spilled and we use the equiv constant. In this | |
4888 | case we should remove the additional insn and | |
f6937e32 | 4889 | this insn is not init_insns list. */ |
55a2c322 | 4890 | && (! MEM_P (x) || MEM_READONLY_P (x) |
f6937e32 VM |
4891 | /* Check that this is actually an insn setting |
4892 | up the equivalence. */ | |
55a2c322 VM |
4893 | || in_list_p (curr_insn, |
4894 | ira_reg_equiv | |
4895 | [REGNO (dest_reg)].init_insns))) | |
8d49e7ef | 4896 | || (((x = get_equiv (SET_SRC (set))) != SET_SRC (set)) |
55a2c322 VM |
4897 | && in_list_p (curr_insn, |
4898 | ira_reg_equiv | |
4899 | [REGNO (SET_SRC (set))].init_insns))) | |
4900 | { | |
4901 | /* This is equiv init insn of pseudo which did not get a | |
4902 | hard register -- remove the insn. */ | |
4903 | if (lra_dump_file != NULL) | |
4904 | { | |
4905 | fprintf (lra_dump_file, | |
4906 | " Removing equiv init insn %i (freq=%d)\n", | |
4907 | INSN_UID (curr_insn), | |
fef37404 | 4908 | REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn))); |
cfbeaedf | 4909 | dump_insn_slim (lra_dump_file, curr_insn); |
55a2c322 VM |
4910 | } |
4911 | if (contains_reg_p (x, true, false)) | |
4912 | lra_risky_transformations_p = true; | |
4913 | lra_set_insn_deleted (curr_insn); | |
4914 | continue; | |
4915 | } | |
4916 | } | |
4917 | curr_id = lra_get_insn_recog_data (curr_insn); | |
4918 | curr_static_id = curr_id->insn_static_data; | |
4919 | init_curr_insn_input_reloads (); | |
4920 | init_curr_operand_mode (); | |
d9cf932c | 4921 | if (curr_insn_transform (false)) |
55a2c322 | 4922 | changed_p = true; |
28430b2e VM |
4923 | /* Check non-transformed insns too for equiv change as USE |
4924 | or CLOBBER don't need reloads but can contain pseudos | |
4925 | being changed on their equivalences. */ | |
d648b5ff | 4926 | else if (bitmap_bit_p (equiv_insn_bitmap, INSN_UID (curr_insn)) |
28430b2e VM |
4927 | && loc_equivalence_change_p (&PATTERN (curr_insn))) |
4928 | { | |
4929 | lra_update_insn_regno_info (curr_insn); | |
4930 | changed_p = true; | |
4931 | } | |
55a2c322 VM |
4932 | } |
4933 | } | |
d648b5ff | 4934 | |
55a2c322 VM |
4935 | /* If we used a new hard regno, changed_p should be true because the |
4936 | hard reg is assigned to a new pseudo. */ | |
b2b29377 | 4937 | if (flag_checking && !changed_p) |
55a2c322 VM |
4938 | { |
4939 | for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++) | |
4940 | if (lra_reg_info[i].nrefs != 0 | |
4941 | && (hard_regno = lra_get_regno_hard_regno (i)) >= 0) | |
4942 | { | |
ad474626 RS |
4943 | int j, nregs = hard_regno_nregs (hard_regno, |
4944 | PSEUDO_REGNO_MODE (i)); | |
f4eafc30 | 4945 | |
55a2c322 VM |
4946 | for (j = 0; j < nregs; j++) |
4947 | lra_assert (df_regs_ever_live_p (hard_regno + j)); | |
4948 | } | |
4949 | } | |
55a2c322 VM |
4950 | return changed_p; |
4951 | } | |
4952 | ||
8a8330b7 VM |
4953 | static void initiate_invariants (void); |
4954 | static void finish_invariants (void); | |
4955 | ||
55a2c322 VM |
4956 | /* Initiate the LRA constraint pass. It is done once per |
4957 | function. */ | |
4958 | void | |
4959 | lra_constraints_init (void) | |
4960 | { | |
8a8330b7 | 4961 | initiate_invariants (); |
55a2c322 VM |
4962 | } |
4963 | ||
4964 | /* Finalize the LRA constraint pass. It is done once per | |
4965 | function. */ | |
4966 | void | |
4967 | lra_constraints_finish (void) | |
4968 | { | |
8a8330b7 VM |
4969 | finish_invariants (); |
4970 | } | |
4971 | ||
4972 | \f | |
4973 | ||
4974 | /* Structure describes invariants for ineheritance. */ | |
eb0f8780 | 4975 | struct lra_invariant |
8a8330b7 VM |
4976 | { |
4977 | /* The order number of the invariant. */ | |
4978 | int num; | |
4979 | /* The invariant RTX. */ | |
4980 | rtx invariant_rtx; | |
4981 | /* The origin insn of the invariant. */ | |
4982 | rtx_insn *insn; | |
4983 | }; | |
4984 | ||
eb0f8780 | 4985 | typedef lra_invariant invariant_t; |
8a8330b7 VM |
4986 | typedef invariant_t *invariant_ptr_t; |
4987 | typedef const invariant_t *const_invariant_ptr_t; | |
4988 | ||
4989 | /* Pointer to the inheritance invariants. */ | |
4990 | static vec<invariant_ptr_t> invariants; | |
4991 | ||
4992 | /* Allocation pool for the invariants. */ | |
eb0f8780 | 4993 | static object_allocator<lra_invariant> *invariants_pool; |
8a8330b7 VM |
4994 | |
4995 | /* Hash table for the invariants. */ | |
4996 | static htab_t invariant_table; | |
4997 | ||
4998 | /* Hash function for INVARIANT. */ | |
4999 | static hashval_t | |
5000 | invariant_hash (const void *invariant) | |
5001 | { | |
5002 | rtx inv = ((const_invariant_ptr_t) invariant)->invariant_rtx; | |
5003 | return lra_rtx_hash (inv); | |
5004 | } | |
5005 | ||
5006 | /* Equal function for invariants INVARIANT1 and INVARIANT2. */ | |
5007 | static int | |
5008 | invariant_eq_p (const void *invariant1, const void *invariant2) | |
5009 | { | |
5010 | rtx inv1 = ((const_invariant_ptr_t) invariant1)->invariant_rtx; | |
5011 | rtx inv2 = ((const_invariant_ptr_t) invariant2)->invariant_rtx; | |
5012 | ||
5013 | return rtx_equal_p (inv1, inv2); | |
5014 | } | |
5015 | ||
5016 | /* Insert INVARIANT_RTX into the table if it is not there yet. Return | |
5017 | invariant which is in the table. */ | |
5018 | static invariant_ptr_t | |
5019 | insert_invariant (rtx invariant_rtx) | |
5020 | { | |
5021 | void **entry_ptr; | |
5022 | invariant_t invariant; | |
5023 | invariant_ptr_t invariant_ptr; | |
5024 | ||
5025 | invariant.invariant_rtx = invariant_rtx; | |
5026 | entry_ptr = htab_find_slot (invariant_table, &invariant, INSERT); | |
5027 | if (*entry_ptr == NULL) | |
5028 | { | |
5029 | invariant_ptr = invariants_pool->allocate (); | |
5030 | invariant_ptr->invariant_rtx = invariant_rtx; | |
5031 | invariant_ptr->insn = NULL; | |
5032 | invariants.safe_push (invariant_ptr); | |
5033 | *entry_ptr = (void *) invariant_ptr; | |
5034 | } | |
5035 | return (invariant_ptr_t) *entry_ptr; | |
5036 | } | |
5037 | ||
5038 | /* Initiate the invariant table. */ | |
5039 | static void | |
5040 | initiate_invariants (void) | |
5041 | { | |
5042 | invariants.create (100); | |
eb0f8780 ML |
5043 | invariants_pool |
5044 | = new object_allocator<lra_invariant> ("Inheritance invariants"); | |
8a8330b7 VM |
5045 | invariant_table = htab_create (100, invariant_hash, invariant_eq_p, NULL); |
5046 | } | |
5047 | ||
5048 | /* Finish the invariant table. */ | |
5049 | static void | |
5050 | finish_invariants (void) | |
5051 | { | |
5052 | htab_delete (invariant_table); | |
5053 | delete invariants_pool; | |
5054 | invariants.release (); | |
5055 | } | |
5056 | ||
5057 | /* Make the invariant table empty. */ | |
5058 | static void | |
5059 | clear_invariants (void) | |
5060 | { | |
5061 | htab_empty (invariant_table); | |
5062 | invariants_pool->release (); | |
5063 | invariants.truncate (0); | |
55a2c322 VM |
5064 | } |
5065 | ||
5066 | \f | |
5067 | ||
5068 | /* This page contains code to do inheritance/split | |
5069 | transformations. */ | |
5070 | ||
5071 | /* Number of reloads passed so far in current EBB. */ | |
5072 | static int reloads_num; | |
5073 | ||
5074 | /* Number of calls passed so far in current EBB. */ | |
5075 | static int calls_num; | |
5076 | ||
5077 | /* Current reload pseudo check for validity of elements in | |
5078 | USAGE_INSNS. */ | |
5079 | static int curr_usage_insns_check; | |
5080 | ||
5081 | /* Info about last usage of registers in EBB to do inheritance/split | |
5082 | transformation. Inheritance transformation is done from a spilled | |
5083 | pseudo and split transformations from a hard register or a pseudo | |
5084 | assigned to a hard register. */ | |
5085 | struct usage_insns | |
5086 | { | |
5087 | /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member | |
5088 | value INSNS is valid. The insns is chain of optional debug insns | |
1ccd4874 VM |
5089 | and a finishing non-debug insn using the corresponding reg. The |
5090 | value is also used to mark the registers which are set up in the | |
5091 | current insn. The negated insn uid is used for this. */ | |
55a2c322 VM |
5092 | int check; |
5093 | /* Value of global reloads_num at the last insn in INSNS. */ | |
5094 | int reloads_num; | |
5095 | /* Value of global reloads_nums at the last insn in INSNS. */ | |
5096 | int calls_num; | |
5097 | /* It can be true only for splitting. And it means that the restore | |
5098 | insn should be put after insn given by the following member. */ | |
5099 | bool after_p; | |
5100 | /* Next insns in the current EBB which use the original reg and the | |
5101 | original reg value is not changed between the current insn and | |
5102 | the next insns. In order words, e.g. for inheritance, if we need | |
5103 | to use the original reg value again in the next insns we can try | |
5104 | to use the value in a hard register from a reload insn of the | |
5105 | current insn. */ | |
5106 | rtx insns; | |
5107 | }; | |
5108 | ||
5109 | /* Map: regno -> corresponding pseudo usage insns. */ | |
5110 | static struct usage_insns *usage_insns; | |
5111 | ||
5112 | static void | |
1476d1bd | 5113 | setup_next_usage_insn (int regno, rtx insn, int reloads_num, bool after_p) |
55a2c322 VM |
5114 | { |
5115 | usage_insns[regno].check = curr_usage_insns_check; | |
5116 | usage_insns[regno].insns = insn; | |
5117 | usage_insns[regno].reloads_num = reloads_num; | |
5118 | usage_insns[regno].calls_num = calls_num; | |
5119 | usage_insns[regno].after_p = after_p; | |
5120 | } | |
5121 | ||
5122 | /* The function is used to form list REGNO usages which consists of | |
5123 | optional debug insns finished by a non-debug insn using REGNO. | |
5124 | RELOADS_NUM is current number of reload insns processed so far. */ | |
5125 | static void | |
767dc529 | 5126 | add_next_usage_insn (int regno, rtx_insn *insn, int reloads_num) |
55a2c322 VM |
5127 | { |
5128 | rtx next_usage_insns; | |
f4eafc30 | 5129 | |
55a2c322 VM |
5130 | if (usage_insns[regno].check == curr_usage_insns_check |
5131 | && (next_usage_insns = usage_insns[regno].insns) != NULL_RTX | |
5132 | && DEBUG_INSN_P (insn)) | |
5133 | { | |
5134 | /* Check that we did not add the debug insn yet. */ | |
5135 | if (next_usage_insns != insn | |
5136 | && (GET_CODE (next_usage_insns) != INSN_LIST | |
5137 | || XEXP (next_usage_insns, 0) != insn)) | |
5138 | usage_insns[regno].insns = gen_rtx_INSN_LIST (VOIDmode, insn, | |
5139 | next_usage_insns); | |
5140 | } | |
5141 | else if (NONDEBUG_INSN_P (insn)) | |
5142 | setup_next_usage_insn (regno, insn, reloads_num, false); | |
5143 | else | |
5144 | usage_insns[regno].check = 0; | |
5145 | } | |
f4eafc30 | 5146 | |
bc3591eb | 5147 | /* Return first non-debug insn in list USAGE_INSNS. */ |
e8a54173 | 5148 | static rtx_insn * |
bc3591eb VM |
5149 | skip_usage_debug_insns (rtx usage_insns) |
5150 | { | |
5151 | rtx insn; | |
5152 | ||
5153 | /* Skip debug insns. */ | |
5154 | for (insn = usage_insns; | |
5155 | insn != NULL_RTX && GET_CODE (insn) == INSN_LIST; | |
5156 | insn = XEXP (insn, 1)) | |
5157 | ; | |
e8a54173 | 5158 | return safe_as_a <rtx_insn *> (insn); |
bc3591eb VM |
5159 | } |
5160 | ||
5161 | /* Return true if we need secondary memory moves for insn in | |
5162 | USAGE_INSNS after inserting inherited pseudo of class INHER_CL | |
5163 | into the insn. */ | |
5164 | static bool | |
fbebbadd JR |
5165 | check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED, |
5166 | rtx usage_insns ATTRIBUTE_UNUSED) | |
bc3591eb | 5167 | { |
e8a54173 DM |
5168 | rtx_insn *insn; |
5169 | rtx set, dest; | |
bc3591eb VM |
5170 | enum reg_class cl; |
5171 | ||
5172 | if (inher_cl == ALL_REGS | |
5173 | || (insn = skip_usage_debug_insns (usage_insns)) == NULL_RTX) | |
5174 | return false; | |
5175 | lra_assert (INSN_P (insn)); | |
5176 | if ((set = single_set (insn)) == NULL_RTX || ! REG_P (SET_DEST (set))) | |
5177 | return false; | |
5178 | dest = SET_DEST (set); | |
5179 | if (! REG_P (dest)) | |
5180 | return false; | |
5181 | lra_assert (inher_cl != NO_REGS); | |
5182 | cl = get_reg_class (REGNO (dest)); | |
5183 | return (cl != NO_REGS && cl != ALL_REGS | |
f15643d4 | 5184 | && targetm.secondary_memory_needed (GET_MODE (dest), inher_cl, cl)); |
bc3591eb VM |
5185 | } |
5186 | ||
55a2c322 VM |
5187 | /* Registers involved in inheritance/split in the current EBB |
5188 | (inheritance/split pseudos and original registers). */ | |
5189 | static bitmap_head check_only_regs; | |
5190 | ||
8a8330b7 VM |
5191 | /* Reload pseudos can not be involded in invariant inheritance in the |
5192 | current EBB. */ | |
5193 | static bitmap_head invalid_invariant_regs; | |
5194 | ||
55a2c322 VM |
5195 | /* Do inheritance transformations for insn INSN, which defines (if |
5196 | DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which | |
5197 | instruction in the EBB next uses ORIGINAL_REGNO; it has the same | |
5198 | form as the "insns" field of usage_insns. Return true if we | |
5199 | succeed in such transformation. | |
5200 | ||
5201 | The transformations look like: | |
5202 | ||
5203 | p <- ... i <- ... | |
5204 | ... p <- i (new insn) | |
5205 | ... => | |
5206 | <- ... p ... <- ... i ... | |
5207 | or | |
5208 | ... i <- p (new insn) | |
5209 | <- ... p ... <- ... i ... | |
5210 | ... => | |
5211 | <- ... p ... <- ... i ... | |
5212 | where p is a spilled original pseudo and i is a new inheritance pseudo. | |
f4eafc30 L |
5213 | |
5214 | ||
55a2c322 VM |
5215 | The inheritance pseudo has the smallest class of two classes CL and |
5216 | class of ORIGINAL REGNO. */ | |
5217 | static bool | |
5218 | inherit_reload_reg (bool def_p, int original_regno, | |
cfa434f6 | 5219 | enum reg_class cl, rtx_insn *insn, rtx next_usage_insns) |
55a2c322 | 5220 | { |
2ae577fd VM |
5221 | if (optimize_function_for_size_p (cfun)) |
5222 | return false; | |
5223 | ||
55a2c322 VM |
5224 | enum reg_class rclass = lra_get_allocno_class (original_regno); |
5225 | rtx original_reg = regno_reg_rtx[original_regno]; | |
cfa434f6 DM |
5226 | rtx new_reg, usage_insn; |
5227 | rtx_insn *new_insns; | |
55a2c322 VM |
5228 | |
5229 | lra_assert (! usage_insns[original_regno].after_p); | |
5230 | if (lra_dump_file != NULL) | |
5231 | fprintf (lra_dump_file, | |
bc3591eb | 5232 | " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n"); |
55a2c322 VM |
5233 | if (! ira_reg_classes_intersect_p[cl][rclass]) |
5234 | { | |
5235 | if (lra_dump_file != NULL) | |
5236 | { | |
5237 | fprintf (lra_dump_file, | |
bc3591eb | 5238 | " Rejecting inheritance for %d " |
55a2c322 VM |
5239 | "because of disjoint classes %s and %s\n", |
5240 | original_regno, reg_class_names[cl], | |
5241 | reg_class_names[rclass]); | |
5242 | fprintf (lra_dump_file, | |
bc3591eb | 5243 | " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); |
55a2c322 VM |
5244 | } |
5245 | return false; | |
5246 | } | |
5247 | if ((ira_class_subset_p[cl][rclass] && cl != rclass) | |
5248 | /* We don't use a subset of two classes because it can be | |
5249 | NO_REGS. This transformation is still profitable in most | |
5250 | cases even if the classes are not intersected as register | |
5251 | move is probably cheaper than a memory load. */ | |
5252 | || ira_class_hard_regs_num[cl] < ira_class_hard_regs_num[rclass]) | |
5253 | { | |
5254 | if (lra_dump_file != NULL) | |
5255 | fprintf (lra_dump_file, " Use smallest class of %s and %s\n", | |
5256 | reg_class_names[cl], reg_class_names[rclass]); | |
f4eafc30 | 5257 | |
55a2c322 VM |
5258 | rclass = cl; |
5259 | } | |
66aa7879 | 5260 | if (check_secondary_memory_needed_p (rclass, next_usage_insns)) |
bc3591eb VM |
5261 | { |
5262 | /* Reject inheritance resulting in secondary memory moves. | |
5263 | Otherwise, there is a danger in LRA cycling. Also such | |
5264 | transformation will be unprofitable. */ | |
5265 | if (lra_dump_file != NULL) | |
5266 | { | |
e8a54173 | 5267 | rtx_insn *insn = skip_usage_debug_insns (next_usage_insns); |
bc3591eb VM |
5268 | rtx set = single_set (insn); |
5269 | ||
5270 | lra_assert (set != NULL_RTX); | |
5271 | ||
5272 | rtx dest = SET_DEST (set); | |
5273 | ||
5274 | lra_assert (REG_P (dest)); | |
5275 | fprintf (lra_dump_file, | |
5276 | " Rejecting inheritance for insn %d(%s)<-%d(%s) " | |
5277 | "as secondary mem is needed\n", | |
5278 | REGNO (dest), reg_class_names[get_reg_class (REGNO (dest))], | |
66aa7879 | 5279 | original_regno, reg_class_names[rclass]); |
bc3591eb VM |
5280 | fprintf (lra_dump_file, |
5281 | " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); | |
5282 | } | |
5283 | return false; | |
5284 | } | |
55a2c322 VM |
5285 | new_reg = lra_create_new_reg (GET_MODE (original_reg), original_reg, |
5286 | rclass, "inheritance"); | |
5287 | start_sequence (); | |
5288 | if (def_p) | |
a810ee82 | 5289 | lra_emit_move (original_reg, new_reg); |
55a2c322 | 5290 | else |
a810ee82 | 5291 | lra_emit_move (new_reg, original_reg); |
55a2c322 VM |
5292 | new_insns = get_insns (); |
5293 | end_sequence (); | |
5294 | if (NEXT_INSN (new_insns) != NULL_RTX) | |
5295 | { | |
5296 | if (lra_dump_file != NULL) | |
5297 | { | |
5298 | fprintf (lra_dump_file, | |
bc3591eb | 5299 | " Rejecting inheritance %d->%d " |
55a2c322 VM |
5300 | "as it results in 2 or more insns:\n", |
5301 | original_regno, REGNO (new_reg)); | |
dc01c3d1 | 5302 | dump_rtl_slim (lra_dump_file, new_insns, NULL, -1, 0); |
55a2c322 VM |
5303 | fprintf (lra_dump_file, |
5304 | " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); | |
5305 | } | |
5306 | return false; | |
5307 | } | |
ef87312e | 5308 | lra_substitute_pseudo_within_insn (insn, original_regno, new_reg, false); |
55a2c322 VM |
5309 | lra_update_insn_regno_info (insn); |
5310 | if (! def_p) | |
5311 | /* We now have a new usage insn for original regno. */ | |
5312 | setup_next_usage_insn (original_regno, new_insns, reloads_num, false); | |
5313 | if (lra_dump_file != NULL) | |
bc3591eb | 5314 | fprintf (lra_dump_file, " Original reg change %d->%d (bb%d):\n", |
55a2c322 | 5315 | original_regno, REGNO (new_reg), BLOCK_FOR_INSN (insn)->index); |
8a8330b7 | 5316 | lra_reg_info[REGNO (new_reg)].restore_rtx = regno_reg_rtx[original_regno]; |
55a2c322 VM |
5317 | bitmap_set_bit (&check_only_regs, REGNO (new_reg)); |
5318 | bitmap_set_bit (&check_only_regs, original_regno); | |
5319 | bitmap_set_bit (&lra_inheritance_pseudos, REGNO (new_reg)); | |
5320 | if (def_p) | |
cfa434f6 | 5321 | lra_process_new_insns (insn, NULL, new_insns, |
55a2c322 VM |
5322 | "Add original<-inheritance"); |
5323 | else | |
cfa434f6 | 5324 | lra_process_new_insns (insn, new_insns, NULL, |
55a2c322 VM |
5325 | "Add inheritance<-original"); |
5326 | while (next_usage_insns != NULL_RTX) | |
5327 | { | |
5328 | if (GET_CODE (next_usage_insns) != INSN_LIST) | |
5329 | { | |
5330 | usage_insn = next_usage_insns; | |
5331 | lra_assert (NONDEBUG_INSN_P (usage_insn)); | |
5332 | next_usage_insns = NULL; | |
5333 | } | |
5334 | else | |
5335 | { | |
5336 | usage_insn = XEXP (next_usage_insns, 0); | |
5337 | lra_assert (DEBUG_INSN_P (usage_insn)); | |
5338 | next_usage_insns = XEXP (next_usage_insns, 1); | |
5339 | } | |
33006d53 JJ |
5340 | lra_substitute_pseudo (&usage_insn, original_regno, new_reg, false, |
5341 | DEBUG_INSN_P (usage_insn)); | |
cfa434f6 | 5342 | lra_update_insn_regno_info (as_a <rtx_insn *> (usage_insn)); |
55a2c322 VM |
5343 | if (lra_dump_file != NULL) |
5344 | { | |
96a95ac1 | 5345 | basic_block bb = BLOCK_FOR_INSN (usage_insn); |
55a2c322 VM |
5346 | fprintf (lra_dump_file, |
5347 | " Inheritance reuse change %d->%d (bb%d):\n", | |
5348 | original_regno, REGNO (new_reg), | |
96a95ac1 | 5349 | bb ? bb->index : -1); |
1476d1bd | 5350 | dump_insn_slim (lra_dump_file, as_a <rtx_insn *> (usage_insn)); |
55a2c322 VM |
5351 | } |
5352 | } | |
5353 | if (lra_dump_file != NULL) | |
5354 | fprintf (lra_dump_file, | |
5355 | " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); | |
5356 | return true; | |
5357 | } | |
5358 | ||
5359 | /* Return true if we need a caller save/restore for pseudo REGNO which | |
5360 | was assigned to a hard register. */ | |
5361 | static inline bool | |
5362 | need_for_call_save_p (int regno) | |
5363 | { | |
5364 | lra_assert (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] >= 0); | |
5365 | return (usage_insns[regno].calls_num < calls_num | |
5366 | && (overlaps_hard_reg_set_p | |
1e288103 | 5367 | ((flag_ipa_ra && |
10e1bdb2 TV |
5368 | ! hard_reg_set_empty_p (lra_reg_info[regno].actual_call_used_reg_set)) |
5369 | ? lra_reg_info[regno].actual_call_used_reg_set | |
5370 | : call_used_reg_set, | |
8a26ad39 | 5371 | PSEUDO_REGNO_MODE (regno), reg_renumber[regno]) |
80ec73f4 RS |
5372 | || (targetm.hard_regno_call_part_clobbered |
5373 | (reg_renumber[regno], PSEUDO_REGNO_MODE (regno))))); | |
55a2c322 VM |
5374 | } |
5375 | ||
1aa95df7 | 5376 | /* Global registers occurring in the current EBB. */ |
55a2c322 VM |
5377 | static bitmap_head ebb_global_regs; |
5378 | ||
5379 | /* Return true if we need a split for hard register REGNO or pseudo | |
5380 | REGNO which was assigned to a hard register. | |
5381 | POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be | |
5382 | used for reloads since the EBB end. It is an approximation of the | |
5383 | used hard registers in the split range. The exact value would | |
5384 | require expensive calculations. If we were aggressive with | |
5385 | splitting because of the approximation, the split pseudo will save | |
5386 | the same hard register assignment and will be removed in the undo | |
5387 | pass. We still need the approximation because too aggressive | |
5388 | splitting would result in too inaccurate cost calculation in the | |
5389 | assignment pass because of too many generated moves which will be | |
5390 | probably removed in the undo pass. */ | |
5391 | static inline bool | |
5392 | need_for_split_p (HARD_REG_SET potential_reload_hard_regs, int regno) | |
5393 | { | |
5394 | int hard_regno = regno < FIRST_PSEUDO_REGISTER ? regno : reg_renumber[regno]; | |
5395 | ||
5396 | lra_assert (hard_regno >= 0); | |
5397 | return ((TEST_HARD_REG_BIT (potential_reload_hard_regs, hard_regno) | |
5398 | /* Don't split eliminable hard registers, otherwise we can | |
5399 | split hard registers like hard frame pointer, which | |
5400 | lives on BB start/end according to DF-infrastructure, | |
5401 | when there is a pseudo assigned to the register and | |
5402 | living in the same BB. */ | |
5403 | && (regno >= FIRST_PSEUDO_REGISTER | |
5404 | || ! TEST_HARD_REG_BIT (eliminable_regset, hard_regno)) | |
5405 | && ! TEST_HARD_REG_BIT (lra_no_alloc_regs, hard_regno) | |
e32e4c4a VM |
5406 | /* Don't split call clobbered hard regs living through |
5407 | calls, otherwise we might have a check problem in the | |
5408 | assign sub-pass as in the most cases (exception is a | |
5409 | situation when lra_risky_transformations_p value is | |
5410 | true) the assign pass assumes that all pseudos living | |
5411 | through calls are assigned to call saved hard regs. */ | |
5412 | && (regno >= FIRST_PSEUDO_REGISTER | |
5413 | || ! TEST_HARD_REG_BIT (call_used_reg_set, regno) | |
5414 | || usage_insns[regno].calls_num == calls_num) | |
55a2c322 VM |
5415 | /* We need at least 2 reloads to make pseudo splitting |
5416 | profitable. We should provide hard regno splitting in | |
5417 | any case to solve 1st insn scheduling problem when | |
5418 | moving hard register definition up might result in | |
5419 | impossibility to find hard register for reload pseudo of | |
5420 | small register class. */ | |
5421 | && (usage_insns[regno].reloads_num | |
8e9d68a9 | 5422 | + (regno < FIRST_PSEUDO_REGISTER ? 0 : 3) < reloads_num) |
55a2c322 VM |
5423 | && (regno < FIRST_PSEUDO_REGISTER |
5424 | /* For short living pseudos, spilling + inheritance can | |
5425 | be considered a substitution for splitting. | |
5426 | Therefore we do not splitting for local pseudos. It | |
5427 | decreases also aggressiveness of splitting. The | |
5428 | minimal number of references is chosen taking into | |
5429 | account that for 2 references splitting has no sense | |
5430 | as we can just spill the pseudo. */ | |
5431 | || (regno >= FIRST_PSEUDO_REGISTER | |
5432 | && lra_reg_info[regno].nrefs > 3 | |
5433 | && bitmap_bit_p (&ebb_global_regs, regno)))) | |
5434 | || (regno >= FIRST_PSEUDO_REGISTER && need_for_call_save_p (regno))); | |
5435 | } | |
5436 | ||
5437 | /* Return class for the split pseudo created from original pseudo with | |
5438 | ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We | |
5439 | choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and | |
5440 | results in no secondary memory movements. */ | |
5441 | static enum reg_class | |
5442 | choose_split_class (enum reg_class allocno_class, | |
5443 | int hard_regno ATTRIBUTE_UNUSED, | |
ef4bddc2 | 5444 | machine_mode mode ATTRIBUTE_UNUSED) |
55a2c322 | 5445 | { |
55a2c322 VM |
5446 | int i; |
5447 | enum reg_class cl, best_cl = NO_REGS; | |
ef4dbe49 JR |
5448 | enum reg_class hard_reg_class ATTRIBUTE_UNUSED |
5449 | = REGNO_REG_CLASS (hard_regno); | |
f4eafc30 | 5450 | |
f15643d4 | 5451 | if (! targetm.secondary_memory_needed (mode, allocno_class, allocno_class) |
55a2c322 VM |
5452 | && TEST_HARD_REG_BIT (reg_class_contents[allocno_class], hard_regno)) |
5453 | return allocno_class; | |
5454 | for (i = 0; | |
5455 | (cl = reg_class_subclasses[allocno_class][i]) != LIM_REG_CLASSES; | |
5456 | i++) | |
f15643d4 RS |
5457 | if (! targetm.secondary_memory_needed (mode, cl, hard_reg_class) |
5458 | && ! targetm.secondary_memory_needed (mode, hard_reg_class, cl) | |
55a2c322 VM |
5459 | && TEST_HARD_REG_BIT (reg_class_contents[cl], hard_regno) |
5460 | && (best_cl == NO_REGS | |
5461 | || ira_class_hard_regs_num[best_cl] < ira_class_hard_regs_num[cl])) | |
5462 | best_cl = cl; | |
5463 | return best_cl; | |
55a2c322 VM |
5464 | } |
5465 | ||
8ffa3150 RS |
5466 | /* Copy any equivalence information from ORIGINAL_REGNO to NEW_REGNO. |
5467 | It only makes sense to call this function if NEW_REGNO is always | |
5468 | equal to ORIGINAL_REGNO. */ | |
5469 | ||
5470 | static void | |
5471 | lra_copy_reg_equiv (unsigned int new_regno, unsigned int original_regno) | |
5472 | { | |
5473 | if (!ira_reg_equiv[original_regno].defined_p) | |
5474 | return; | |
5475 | ||
5476 | ira_expand_reg_equiv (); | |
5477 | ira_reg_equiv[new_regno].defined_p = true; | |
5478 | if (ira_reg_equiv[original_regno].memory) | |
5479 | ira_reg_equiv[new_regno].memory | |
5480 | = copy_rtx (ira_reg_equiv[original_regno].memory); | |
5481 | if (ira_reg_equiv[original_regno].constant) | |
5482 | ira_reg_equiv[new_regno].constant | |
5483 | = copy_rtx (ira_reg_equiv[original_regno].constant); | |
5484 | if (ira_reg_equiv[original_regno].invariant) | |
5485 | ira_reg_equiv[new_regno].invariant | |
5486 | = copy_rtx (ira_reg_equiv[original_regno].invariant); | |
5487 | } | |
5488 | ||
55a2c322 VM |
5489 | /* Do split transformations for insn INSN, which defines or uses |
5490 | ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in | |
5491 | the EBB next uses ORIGINAL_REGNO; it has the same form as the | |
6027ea4c VM |
5492 | "insns" field of usage_insns. If TO is not NULL, we don't use |
5493 | usage_insns, we put restore insns after TO insn. | |
55a2c322 VM |
5494 | |
5495 | The transformations look like: | |
5496 | ||
5497 | p <- ... p <- ... | |
5498 | ... s <- p (new insn -- save) | |
5499 | ... => | |
5500 | ... p <- s (new insn -- restore) | |
5501 | <- ... p ... <- ... p ... | |
5502 | or | |
5503 | <- ... p ... <- ... p ... | |
5504 | ... s <- p (new insn -- save) | |
5505 | ... => | |
5506 | ... p <- s (new insn -- restore) | |
5507 | <- ... p ... <- ... p ... | |
5508 | ||
5509 | where p is an original pseudo got a hard register or a hard | |
5510 | register and s is a new split pseudo. The save is put before INSN | |
5511 | if BEFORE_P is true. Return true if we succeed in such | |
5512 | transformation. */ | |
5513 | static bool | |
cfa434f6 | 5514 | split_reg (bool before_p, int original_regno, rtx_insn *insn, |
6027ea4c | 5515 | rtx next_usage_insns, rtx_insn *to) |
55a2c322 VM |
5516 | { |
5517 | enum reg_class rclass; | |
5518 | rtx original_reg; | |
77bce07c | 5519 | int hard_regno, nregs; |
cfa434f6 DM |
5520 | rtx new_reg, usage_insn; |
5521 | rtx_insn *restore, *save; | |
55a2c322 VM |
5522 | bool after_p; |
5523 | bool call_save_p; | |
3cbf012a | 5524 | machine_mode mode; |
55a2c322 VM |
5525 | |
5526 | if (original_regno < FIRST_PSEUDO_REGISTER) | |
5527 | { | |
5528 | rclass = ira_allocno_class_translate[REGNO_REG_CLASS (original_regno)]; | |
5529 | hard_regno = original_regno; | |
5530 | call_save_p = false; | |
77bce07c | 5531 | nregs = 1; |
3cbf012a BS |
5532 | mode = lra_reg_info[hard_regno].biggest_mode; |
5533 | machine_mode reg_rtx_mode = GET_MODE (regno_reg_rtx[hard_regno]); | |
5c6a601c BS |
5534 | /* A reg can have a biggest_mode of VOIDmode if it was only ever seen |
5535 | as part of a multi-word register. In that case, or if the biggest | |
5536 | mode was larger than a register, just use the reg_rtx. Otherwise, | |
5537 | limit the size to that of the biggest access in the function. */ | |
5538 | if (mode == VOIDmode | |
03a95621 | 5539 | || paradoxical_subreg_p (mode, reg_rtx_mode)) |
3cbf012a BS |
5540 | { |
5541 | original_reg = regno_reg_rtx[hard_regno]; | |
5542 | mode = reg_rtx_mode; | |
5543 | } | |
5544 | else | |
5545 | original_reg = gen_rtx_REG (mode, hard_regno); | |
55a2c322 VM |
5546 | } |
5547 | else | |
5548 | { | |
3cbf012a | 5549 | mode = PSEUDO_REGNO_MODE (original_regno); |
55a2c322 | 5550 | hard_regno = reg_renumber[original_regno]; |
ad474626 | 5551 | nregs = hard_regno_nregs (hard_regno, mode); |
55a2c322 VM |
5552 | rclass = lra_get_allocno_class (original_regno); |
5553 | original_reg = regno_reg_rtx[original_regno]; | |
5554 | call_save_p = need_for_call_save_p (original_regno); | |
5555 | } | |
55a2c322 VM |
5556 | lra_assert (hard_regno >= 0); |
5557 | if (lra_dump_file != NULL) | |
5558 | fprintf (lra_dump_file, | |
5559 | " ((((((((((((((((((((((((((((((((((((((((((((((((\n"); | |
3cbf012a | 5560 | |
55a2c322 VM |
5561 | if (call_save_p) |
5562 | { | |
cb1cca12 | 5563 | mode = HARD_REGNO_CALLER_SAVE_MODE (hard_regno, |
ad474626 | 5564 | hard_regno_nregs (hard_regno, mode), |
cb1cca12 VM |
5565 | mode); |
5566 | new_reg = lra_create_new_reg (mode, NULL_RTX, NO_REGS, "save"); | |
55a2c322 VM |
5567 | } |
5568 | else | |
5569 | { | |
3cbf012a | 5570 | rclass = choose_split_class (rclass, hard_regno, mode); |
55a2c322 VM |
5571 | if (rclass == NO_REGS) |
5572 | { | |
5573 | if (lra_dump_file != NULL) | |
5574 | { | |
5575 | fprintf (lra_dump_file, | |
5576 | " Rejecting split of %d(%s): " | |
5577 | "no good reg class for %d(%s)\n", | |
5578 | original_regno, | |
5579 | reg_class_names[lra_get_allocno_class (original_regno)], | |
5580 | hard_regno, | |
5581 | reg_class_names[REGNO_REG_CLASS (hard_regno)]); | |
5582 | fprintf | |
5583 | (lra_dump_file, | |
5584 | " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); | |
5585 | } | |
5586 | return false; | |
5587 | } | |
1b51df94 MF |
5588 | /* Split_if_necessary can split hard registers used as part of a |
5589 | multi-register mode but splits each register individually. The | |
5590 | mode used for each independent register may not be supported | |
5591 | so reject the split. Splitting the wider mode should theoretically | |
5592 | be possible but is not implemented. */ | |
f939c3e6 | 5593 | if (!targetm.hard_regno_mode_ok (hard_regno, mode)) |
1b51df94 MF |
5594 | { |
5595 | if (lra_dump_file != NULL) | |
5596 | { | |
5597 | fprintf (lra_dump_file, | |
5598 | " Rejecting split of %d(%s): unsuitable mode %s\n", | |
5599 | original_regno, | |
5600 | reg_class_names[lra_get_allocno_class (original_regno)], | |
5601 | GET_MODE_NAME (mode)); | |
5602 | fprintf | |
5603 | (lra_dump_file, | |
5604 | " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); | |
5605 | } | |
5606 | return false; | |
5607 | } | |
3cbf012a | 5608 | new_reg = lra_create_new_reg (mode, original_reg, rclass, "split"); |
55a2c322 VM |
5609 | reg_renumber[REGNO (new_reg)] = hard_regno; |
5610 | } | |
8ffa3150 | 5611 | int new_regno = REGNO (new_reg); |
55a2c322 | 5612 | save = emit_spill_move (true, new_reg, original_reg); |
c61fe0cc | 5613 | if (NEXT_INSN (save) != NULL_RTX && !call_save_p) |
55a2c322 | 5614 | { |
55a2c322 VM |
5615 | if (lra_dump_file != NULL) |
5616 | { | |
5617 | fprintf | |
5618 | (lra_dump_file, | |
c61fe0cc | 5619 | " Rejecting split %d->%d resulting in > 2 save insns:\n", |
8ffa3150 | 5620 | original_regno, new_regno); |
dc01c3d1 | 5621 | dump_rtl_slim (lra_dump_file, save, NULL, -1, 0); |
55a2c322 VM |
5622 | fprintf (lra_dump_file, |
5623 | " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); | |
5624 | } | |
5625 | return false; | |
5626 | } | |
5627 | restore = emit_spill_move (false, new_reg, original_reg); | |
c61fe0cc | 5628 | if (NEXT_INSN (restore) != NULL_RTX && !call_save_p) |
55a2c322 | 5629 | { |
55a2c322 VM |
5630 | if (lra_dump_file != NULL) |
5631 | { | |
5632 | fprintf (lra_dump_file, | |
5633 | " Rejecting split %d->%d " | |
c61fe0cc | 5634 | "resulting in > 2 restore insns:\n", |
8ffa3150 | 5635 | original_regno, new_regno); |
dc01c3d1 | 5636 | dump_rtl_slim (lra_dump_file, restore, NULL, -1, 0); |
55a2c322 VM |
5637 | fprintf (lra_dump_file, |
5638 | " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); | |
5639 | } | |
5640 | return false; | |
5641 | } | |
8ffa3150 RS |
5642 | /* Transfer equivalence information to the spill register, so that |
5643 | if we fail to allocate the spill register, we have the option of | |
5644 | rematerializing the original value instead of spilling to the stack. */ | |
5645 | if (!HARD_REGISTER_NUM_P (original_regno) | |
5646 | && mode == PSEUDO_REGNO_MODE (original_regno)) | |
5647 | lra_copy_reg_equiv (new_regno, original_regno); | |
8ffa3150 RS |
5648 | lra_reg_info[new_regno].restore_rtx = regno_reg_rtx[original_regno]; |
5649 | bitmap_set_bit (&check_only_regs, new_regno); | |
55a2c322 | 5650 | bitmap_set_bit (&check_only_regs, original_regno); |
8ffa3150 | 5651 | bitmap_set_bit (&lra_split_regs, new_regno); |
6027ea4c | 5652 | if (to != NULL) |
55a2c322 | 5653 | { |
6027ea4c VM |
5654 | usage_insn = to; |
5655 | after_p = TRUE; | |
5656 | } | |
5657 | else | |
5658 | { | |
5659 | after_p = usage_insns[original_regno].after_p; | |
5660 | for (;;) | |
b3231b65 | 5661 | { |
6027ea4c VM |
5662 | if (GET_CODE (next_usage_insns) != INSN_LIST) |
5663 | { | |
5664 | usage_insn = next_usage_insns; | |
5665 | break; | |
5666 | } | |
5667 | usage_insn = XEXP (next_usage_insns, 0); | |
5668 | lra_assert (DEBUG_INSN_P (usage_insn)); | |
5669 | next_usage_insns = XEXP (next_usage_insns, 1); | |
5670 | lra_substitute_pseudo (&usage_insn, original_regno, new_reg, false, | |
5671 | true); | |
5672 | lra_update_insn_regno_info (as_a <rtx_insn *> (usage_insn)); | |
5673 | if (lra_dump_file != NULL) | |
5674 | { | |
5675 | fprintf (lra_dump_file, " Split reuse change %d->%d:\n", | |
5676 | original_regno, new_regno); | |
5677 | dump_insn_slim (lra_dump_file, as_a <rtx_insn *> (usage_insn)); | |
5678 | } | |
55a2c322 VM |
5679 | } |
5680 | } | |
5681 | lra_assert (NOTE_P (usage_insn) || NONDEBUG_INSN_P (usage_insn)); | |
5682 | lra_assert (usage_insn != insn || (after_p && before_p)); | |
cfa434f6 DM |
5683 | lra_process_new_insns (as_a <rtx_insn *> (usage_insn), |
5684 | after_p ? NULL : restore, | |
5685 | after_p ? restore : NULL, | |
55a2c322 VM |
5686 | call_save_p |
5687 | ? "Add reg<-save" : "Add reg<-split"); | |
cfa434f6 DM |
5688 | lra_process_new_insns (insn, before_p ? save : NULL, |
5689 | before_p ? NULL : save, | |
55a2c322 VM |
5690 | call_save_p |
5691 | ? "Add save<-reg" : "Add split<-reg"); | |
77bce07c VM |
5692 | if (nregs > 1) |
5693 | /* If we are trying to split multi-register. We should check | |
5694 | conflicts on the next assignment sub-pass. IRA can allocate on | |
5695 | sub-register levels, LRA do this on pseudos level right now and | |
5696 | this discrepancy may create allocation conflicts after | |
5697 | splitting. */ | |
5698 | lra_risky_transformations_p = true; | |
55a2c322 VM |
5699 | if (lra_dump_file != NULL) |
5700 | fprintf (lra_dump_file, | |
5701 | " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); | |
5702 | return true; | |
5703 | } | |
5704 | ||
6027ea4c VM |
5705 | /* Split a hard reg for reload pseudo REGNO having RCLASS and living |
5706 | in the range [FROM, TO]. Return true if did a split. Otherwise, | |
5707 | return false. */ | |
5708 | bool | |
5709 | spill_hard_reg_in_range (int regno, enum reg_class rclass, rtx_insn *from, rtx_insn *to) | |
5710 | { | |
5711 | int i, hard_regno; | |
5712 | int rclass_size; | |
5713 | rtx_insn *insn; | |
7293e3f5 VM |
5714 | unsigned int uid; |
5715 | bitmap_iterator bi; | |
5716 | HARD_REG_SET ignore; | |
6027ea4c VM |
5717 | |
5718 | lra_assert (from != NULL && to != NULL); | |
7293e3f5 VM |
5719 | CLEAR_HARD_REG_SET (ignore); |
5720 | EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi) | |
5721 | { | |
5722 | lra_insn_recog_data_t id = lra_insn_recog_data[uid]; | |
5723 | struct lra_static_insn_data *static_id = id->insn_static_data; | |
5724 | struct lra_insn_reg *reg; | |
5725 | ||
5726 | for (reg = id->regs; reg != NULL; reg = reg->next) | |
65e87462 | 5727 | if (reg->regno < FIRST_PSEUDO_REGISTER) |
7293e3f5 VM |
5728 | SET_HARD_REG_BIT (ignore, reg->regno); |
5729 | for (reg = static_id->hard_regs; reg != NULL; reg = reg->next) | |
5730 | SET_HARD_REG_BIT (ignore, reg->regno); | |
5731 | } | |
6027ea4c VM |
5732 | rclass_size = ira_class_hard_regs_num[rclass]; |
5733 | for (i = 0; i < rclass_size; i++) | |
5734 | { | |
5735 | hard_regno = ira_class_hard_regs[rclass][i]; | |
7293e3f5 VM |
5736 | if (! TEST_HARD_REG_BIT (lra_reg_info[regno].conflict_hard_regs, hard_regno) |
5737 | || TEST_HARD_REG_BIT (ignore, hard_regno)) | |
6027ea4c VM |
5738 | continue; |
5739 | for (insn = from; insn != NEXT_INSN (to); insn = NEXT_INSN (insn)) | |
dc843a85 | 5740 | { |
3664a0f1 | 5741 | struct lra_static_insn_data *static_id; |
dc843a85 IL |
5742 | struct lra_insn_reg *reg; |
5743 | ||
3664a0f1 IL |
5744 | if (!INSN_P (insn)) |
5745 | continue; | |
5746 | if (bitmap_bit_p (&lra_reg_info[hard_regno].insn_bitmap, | |
5747 | INSN_UID (insn))) | |
dc843a85 | 5748 | break; |
3664a0f1 | 5749 | static_id = lra_get_insn_recog_data (insn)->insn_static_data; |
dc843a85 IL |
5750 | for (reg = static_id->hard_regs; reg != NULL; reg = reg->next) |
5751 | if (reg->regno == hard_regno) | |
5752 | break; | |
5753 | if (reg != NULL) | |
5754 | break; | |
5755 | } | |
6027ea4c VM |
5756 | if (insn != NEXT_INSN (to)) |
5757 | continue; | |
5758 | if (split_reg (TRUE, hard_regno, from, NULL, to)) | |
5759 | return true; | |
5760 | } | |
5761 | return false; | |
5762 | } | |
5763 | ||
55a2c322 VM |
5764 | /* Recognize that we need a split transformation for insn INSN, which |
5765 | defines or uses REGNO in its insn biggest MODE (we use it only if | |
5766 | REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains | |
5767 | hard registers which might be used for reloads since the EBB end. | |
5768 | Put the save before INSN if BEFORE_P is true. MAX_UID is maximla | |
5769 | uid before starting INSN processing. Return true if we succeed in | |
5770 | such transformation. */ | |
5771 | static bool | |
ef4bddc2 | 5772 | split_if_necessary (int regno, machine_mode mode, |
55a2c322 | 5773 | HARD_REG_SET potential_reload_hard_regs, |
cfa434f6 | 5774 | bool before_p, rtx_insn *insn, int max_uid) |
55a2c322 VM |
5775 | { |
5776 | bool res = false; | |
5777 | int i, nregs = 1; | |
5778 | rtx next_usage_insns; | |
5779 | ||
5780 | if (regno < FIRST_PSEUDO_REGISTER) | |
ad474626 | 5781 | nregs = hard_regno_nregs (regno, mode); |
55a2c322 VM |
5782 | for (i = 0; i < nregs; i++) |
5783 | if (usage_insns[regno + i].check == curr_usage_insns_check | |
5784 | && (next_usage_insns = usage_insns[regno + i].insns) != NULL_RTX | |
5785 | /* To avoid processing the register twice or more. */ | |
5786 | && ((GET_CODE (next_usage_insns) != INSN_LIST | |
5787 | && INSN_UID (next_usage_insns) < max_uid) | |
5788 | || (GET_CODE (next_usage_insns) == INSN_LIST | |
5789 | && (INSN_UID (XEXP (next_usage_insns, 0)) < max_uid))) | |
5790 | && need_for_split_p (potential_reload_hard_regs, regno + i) | |
6027ea4c | 5791 | && split_reg (before_p, regno + i, insn, next_usage_insns, NULL)) |
55a2c322 VM |
5792 | res = true; |
5793 | return res; | |
5794 | } | |
5795 | ||
8a8330b7 VM |
5796 | /* Return TRUE if rtx X is considered as an invariant for |
5797 | inheritance. */ | |
5798 | static bool | |
5799 | invariant_p (const_rtx x) | |
5800 | { | |
5801 | machine_mode mode; | |
5802 | const char *fmt; | |
5803 | enum rtx_code code; | |
5804 | int i, j; | |
5805 | ||
5806 | code = GET_CODE (x); | |
5807 | mode = GET_MODE (x); | |
5808 | if (code == SUBREG) | |
5809 | { | |
5810 | x = SUBREG_REG (x); | |
5811 | code = GET_CODE (x); | |
bd5a2c67 | 5812 | mode = wider_subreg_mode (mode, GET_MODE (x)); |
8a8330b7 VM |
5813 | } |
5814 | ||
5815 | if (MEM_P (x)) | |
5816 | return false; | |
5817 | ||
5818 | if (REG_P (x)) | |
5819 | { | |
5820 | int i, nregs, regno = REGNO (x); | |
5821 | ||
5822 | if (regno >= FIRST_PSEUDO_REGISTER || regno == STACK_POINTER_REGNUM | |
5823 | || TEST_HARD_REG_BIT (eliminable_regset, regno) | |
5824 | || GET_MODE_CLASS (GET_MODE (x)) == MODE_CC) | |
5825 | return false; | |
ad474626 | 5826 | nregs = hard_regno_nregs (regno, mode); |
8a8330b7 VM |
5827 | for (i = 0; i < nregs; i++) |
5828 | if (! fixed_regs[regno + i] | |
5829 | /* A hard register may be clobbered in the current insn | |
5830 | but we can ignore this case because if the hard | |
5831 | register is used it should be set somewhere after the | |
5832 | clobber. */ | |
5833 | || bitmap_bit_p (&invalid_invariant_regs, regno + i)) | |
5834 | return false; | |
5835 | } | |
5836 | fmt = GET_RTX_FORMAT (code); | |
5837 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
5838 | { | |
5839 | if (fmt[i] == 'e') | |
5840 | { | |
5841 | if (! invariant_p (XEXP (x, i))) | |
5842 | return false; | |
5843 | } | |
5844 | else if (fmt[i] == 'E') | |
5845 | { | |
5846 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
5847 | if (! invariant_p (XVECEXP (x, i, j))) | |
5848 | return false; | |
5849 | } | |
5850 | } | |
5851 | return true; | |
5852 | } | |
5853 | ||
5854 | /* We have 'dest_reg <- invariant'. Let us try to make an invariant | |
5855 | inheritance transformation (using dest_reg instead invariant in a | |
5856 | subsequent insn). */ | |
5857 | static bool | |
5858 | process_invariant_for_inheritance (rtx dst_reg, rtx invariant_rtx) | |
5859 | { | |
5860 | invariant_ptr_t invariant_ptr; | |
5861 | rtx_insn *insn, *new_insns; | |
5862 | rtx insn_set, insn_reg, new_reg; | |
5863 | int insn_regno; | |
5864 | bool succ_p = false; | |
5865 | int dst_regno = REGNO (dst_reg); | |
b8506a8a | 5866 | machine_mode dst_mode = GET_MODE (dst_reg); |
8a8330b7 VM |
5867 | enum reg_class cl = lra_get_allocno_class (dst_regno), insn_reg_cl; |
5868 | ||
5869 | invariant_ptr = insert_invariant (invariant_rtx); | |
5870 | if ((insn = invariant_ptr->insn) != NULL_RTX) | |
5871 | { | |
5872 | /* We have a subsequent insn using the invariant. */ | |
5873 | insn_set = single_set (insn); | |
5874 | lra_assert (insn_set != NULL); | |
5875 | insn_reg = SET_DEST (insn_set); | |
5876 | lra_assert (REG_P (insn_reg)); | |
5877 | insn_regno = REGNO (insn_reg); | |
5878 | insn_reg_cl = lra_get_allocno_class (insn_regno); | |
5879 | ||
5880 | if (dst_mode == GET_MODE (insn_reg) | |
5881 | /* We should consider only result move reg insns which are | |
5882 | cheap. */ | |
5883 | && targetm.register_move_cost (dst_mode, cl, insn_reg_cl) == 2 | |
5884 | && targetm.register_move_cost (dst_mode, cl, cl) == 2) | |
5885 | { | |
5886 | if (lra_dump_file != NULL) | |
5887 | fprintf (lra_dump_file, | |
5888 | " [[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[\n"); | |
5889 | new_reg = lra_create_new_reg (dst_mode, dst_reg, | |
5890 | cl, "invariant inheritance"); | |
5891 | bitmap_set_bit (&lra_inheritance_pseudos, REGNO (new_reg)); | |
5892 | bitmap_set_bit (&check_only_regs, REGNO (new_reg)); | |
b10d44ef | 5893 | lra_reg_info[REGNO (new_reg)].restore_rtx = PATTERN (insn); |
8a8330b7 VM |
5894 | start_sequence (); |
5895 | lra_emit_move (new_reg, dst_reg); | |
5896 | new_insns = get_insns (); | |
5897 | end_sequence (); | |
5898 | lra_process_new_insns (curr_insn, NULL, new_insns, | |
5899 | "Add invariant inheritance<-original"); | |
5900 | start_sequence (); | |
5901 | lra_emit_move (SET_DEST (insn_set), new_reg); | |
5902 | new_insns = get_insns (); | |
5903 | end_sequence (); | |
5904 | lra_process_new_insns (insn, NULL, new_insns, | |
5905 | "Changing reload<-inheritance"); | |
5906 | lra_set_insn_deleted (insn); | |
5907 | succ_p = true; | |
5908 | if (lra_dump_file != NULL) | |
5909 | { | |
5910 | fprintf (lra_dump_file, | |
5911 | " Invariant inheritance reuse change %d (bb%d):\n", | |
5912 | REGNO (new_reg), BLOCK_FOR_INSN (insn)->index); | |
5913 | dump_insn_slim (lra_dump_file, insn); | |
5914 | fprintf (lra_dump_file, | |
5915 | " ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]\n"); | |
5916 | } | |
5917 | } | |
5918 | } | |
5919 | invariant_ptr->insn = curr_insn; | |
5920 | return succ_p; | |
5921 | } | |
5922 | ||
55a2c322 VM |
5923 | /* Check only registers living at the current program point in the |
5924 | current EBB. */ | |
5925 | static bitmap_head live_regs; | |
5926 | ||
5927 | /* Update live info in EBB given by its HEAD and TAIL insns after | |
5928 | inheritance/split transformation. The function removes dead moves | |
5929 | too. */ | |
5930 | static void | |
cfa434f6 | 5931 | update_ebb_live_info (rtx_insn *head, rtx_insn *tail) |
55a2c322 VM |
5932 | { |
5933 | unsigned int j; | |
8e9d68a9 | 5934 | int i, regno; |
55a2c322 | 5935 | bool live_p; |
cfa434f6 DM |
5936 | rtx_insn *prev_insn; |
5937 | rtx set; | |
55a2c322 VM |
5938 | bool remove_p; |
5939 | basic_block last_bb, prev_bb, curr_bb; | |
5940 | bitmap_iterator bi; | |
5941 | struct lra_insn_reg *reg; | |
5942 | edge e; | |
5943 | edge_iterator ei; | |
5944 | ||
f4eafc30 | 5945 | last_bb = BLOCK_FOR_INSN (tail); |
55a2c322 VM |
5946 | prev_bb = NULL; |
5947 | for (curr_insn = tail; | |
5948 | curr_insn != PREV_INSN (head); | |
5949 | curr_insn = prev_insn) | |
5950 | { | |
5951 | prev_insn = PREV_INSN (curr_insn); | |
911598e3 VM |
5952 | /* We need to process empty blocks too. They contain |
5953 | NOTE_INSN_BASIC_BLOCK referring for the basic block. */ | |
5954 | if (NOTE_P (curr_insn) && NOTE_KIND (curr_insn) != NOTE_INSN_BASIC_BLOCK) | |
5955 | continue; | |
55a2c322 VM |
5956 | curr_bb = BLOCK_FOR_INSN (curr_insn); |
5957 | if (curr_bb != prev_bb) | |
5958 | { | |
5959 | if (prev_bb != NULL) | |
5960 | { | |
5961 | /* Update df_get_live_in (prev_bb): */ | |
5962 | EXECUTE_IF_SET_IN_BITMAP (&check_only_regs, 0, j, bi) | |
5963 | if (bitmap_bit_p (&live_regs, j)) | |
5964 | bitmap_set_bit (df_get_live_in (prev_bb), j); | |
5965 | else | |
5966 | bitmap_clear_bit (df_get_live_in (prev_bb), j); | |
5967 | } | |
5968 | if (curr_bb != last_bb) | |
5969 | { | |
5970 | /* Update df_get_live_out (curr_bb): */ | |
5971 | EXECUTE_IF_SET_IN_BITMAP (&check_only_regs, 0, j, bi) | |
5972 | { | |
5973 | live_p = bitmap_bit_p (&live_regs, j); | |
5974 | if (! live_p) | |
5975 | FOR_EACH_EDGE (e, ei, curr_bb->succs) | |
5976 | if (bitmap_bit_p (df_get_live_in (e->dest), j)) | |
5977 | { | |
5978 | live_p = true; | |
5979 | break; | |
5980 | } | |
5981 | if (live_p) | |
5982 | bitmap_set_bit (df_get_live_out (curr_bb), j); | |
5983 | else | |
5984 | bitmap_clear_bit (df_get_live_out (curr_bb), j); | |
5985 | } | |
5986 | } | |
5987 | prev_bb = curr_bb; | |
5988 | bitmap_and (&live_regs, &check_only_regs, df_get_live_out (curr_bb)); | |
5989 | } | |
44b94bdb | 5990 | if (! NONDEBUG_INSN_P (curr_insn)) |
55a2c322 VM |
5991 | continue; |
5992 | curr_id = lra_get_insn_recog_data (curr_insn); | |
8e9d68a9 | 5993 | curr_static_id = curr_id->insn_static_data; |
55a2c322 | 5994 | remove_p = false; |
53250f44 BS |
5995 | if ((set = single_set (curr_insn)) != NULL_RTX |
5996 | && REG_P (SET_DEST (set)) | |
55a2c322 | 5997 | && (regno = REGNO (SET_DEST (set))) >= FIRST_PSEUDO_REGISTER |
53250f44 | 5998 | && SET_DEST (set) != pic_offset_table_rtx |
55a2c322 VM |
5999 | && bitmap_bit_p (&check_only_regs, regno) |
6000 | && ! bitmap_bit_p (&live_regs, regno)) | |
6001 | remove_p = true; | |
6002 | /* See which defined values die here. */ | |
6003 | for (reg = curr_id->regs; reg != NULL; reg = reg->next) | |
6004 | if (reg->type == OP_OUT && ! reg->subreg_p) | |
6005 | bitmap_clear_bit (&live_regs, reg->regno); | |
8e9d68a9 VM |
6006 | for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next) |
6007 | if (reg->type == OP_OUT && ! reg->subreg_p) | |
6008 | bitmap_clear_bit (&live_regs, reg->regno); | |
9d86e84e VM |
6009 | if (curr_id->arg_hard_regs != NULL) |
6010 | /* Make clobbered argument hard registers die. */ | |
6011 | for (i = 0; (regno = curr_id->arg_hard_regs[i]) >= 0; i++) | |
6012 | if (regno >= FIRST_PSEUDO_REGISTER) | |
6013 | bitmap_clear_bit (&live_regs, regno - FIRST_PSEUDO_REGISTER); | |
55a2c322 VM |
6014 | /* Mark each used value as live. */ |
6015 | for (reg = curr_id->regs; reg != NULL; reg = reg->next) | |
d89ae27c | 6016 | if (reg->type != OP_OUT |
55a2c322 VM |
6017 | && bitmap_bit_p (&check_only_regs, reg->regno)) |
6018 | bitmap_set_bit (&live_regs, reg->regno); | |
8e9d68a9 VM |
6019 | for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next) |
6020 | if (reg->type != OP_OUT | |
6021 | && bitmap_bit_p (&check_only_regs, reg->regno)) | |
6022 | bitmap_set_bit (&live_regs, reg->regno); | |
6023 | if (curr_id->arg_hard_regs != NULL) | |
9d86e84e | 6024 | /* Make used argument hard registers live. */ |
8e9d68a9 | 6025 | for (i = 0; (regno = curr_id->arg_hard_regs[i]) >= 0; i++) |
9d86e84e VM |
6026 | if (regno < FIRST_PSEUDO_REGISTER |
6027 | && bitmap_bit_p (&check_only_regs, regno)) | |
8e9d68a9 | 6028 | bitmap_set_bit (&live_regs, regno); |
55a2c322 VM |
6029 | /* It is quite important to remove dead move insns because it |
6030 | means removing dead store. We don't need to process them for | |
6031 | constraints. */ | |
6032 | if (remove_p) | |
6033 | { | |
6034 | if (lra_dump_file != NULL) | |
6035 | { | |
6036 | fprintf (lra_dump_file, " Removing dead insn:\n "); | |
cfbeaedf | 6037 | dump_insn_slim (lra_dump_file, curr_insn); |
55a2c322 VM |
6038 | } |
6039 | lra_set_insn_deleted (curr_insn); | |
6040 | } | |
6041 | } | |
6042 | } | |
6043 | ||
6044 | /* The structure describes info to do an inheritance for the current | |
6045 | insn. We need to collect such info first before doing the | |
6046 | transformations because the transformations change the insn | |
6047 | internal representation. */ | |
6048 | struct to_inherit | |
6049 | { | |
6050 | /* Original regno. */ | |
6051 | int regno; | |
6052 | /* Subsequent insns which can inherit original reg value. */ | |
6053 | rtx insns; | |
6054 | }; | |
6055 | ||
6056 | /* Array containing all info for doing inheritance from the current | |
6057 | insn. */ | |
6058 | static struct to_inherit to_inherit[LRA_MAX_INSN_RELOADS]; | |
6059 | ||
6060 | /* Number elements in the previous array. */ | |
6061 | static int to_inherit_num; | |
6062 | ||
6063 | /* Add inheritance info REGNO and INSNS. Their meaning is described in | |
6064 | structure to_inherit. */ | |
6065 | static void | |
6066 | add_to_inherit (int regno, rtx insns) | |
6067 | { | |
6068 | int i; | |
6069 | ||
6070 | for (i = 0; i < to_inherit_num; i++) | |
6071 | if (to_inherit[i].regno == regno) | |
6072 | return; | |
6073 | lra_assert (to_inherit_num < LRA_MAX_INSN_RELOADS); | |
6074 | to_inherit[to_inherit_num].regno = regno; | |
6075 | to_inherit[to_inherit_num++].insns = insns; | |
6076 | } | |
6077 | ||
6078 | /* Return the last non-debug insn in basic block BB, or the block begin | |
6079 | note if none. */ | |
cfa434f6 | 6080 | static rtx_insn * |
55a2c322 VM |
6081 | get_last_insertion_point (basic_block bb) |
6082 | { | |
cfa434f6 | 6083 | rtx_insn *insn; |
55a2c322 VM |
6084 | |
6085 | FOR_BB_INSNS_REVERSE (bb, insn) | |
6086 | if (NONDEBUG_INSN_P (insn) || NOTE_INSN_BASIC_BLOCK_P (insn)) | |
6087 | return insn; | |
6088 | gcc_unreachable (); | |
6089 | } | |
6090 | ||
6091 | /* Set up RES by registers living on edges FROM except the edge (FROM, | |
6092 | TO) or by registers set up in a jump insn in BB FROM. */ | |
6093 | static void | |
6094 | get_live_on_other_edges (basic_block from, basic_block to, bitmap res) | |
6095 | { | |
cfa434f6 | 6096 | rtx_insn *last; |
55a2c322 VM |
6097 | struct lra_insn_reg *reg; |
6098 | edge e; | |
6099 | edge_iterator ei; | |
6100 | ||
6101 | lra_assert (to != NULL); | |
6102 | bitmap_clear (res); | |
6103 | FOR_EACH_EDGE (e, ei, from->succs) | |
6104 | if (e->dest != to) | |
6105 | bitmap_ior_into (res, df_get_live_in (e->dest)); | |
6106 | last = get_last_insertion_point (from); | |
6107 | if (! JUMP_P (last)) | |
6108 | return; | |
6109 | curr_id = lra_get_insn_recog_data (last); | |
6110 | for (reg = curr_id->regs; reg != NULL; reg = reg->next) | |
6111 | if (reg->type != OP_IN) | |
6112 | bitmap_set_bit (res, reg->regno); | |
6113 | } | |
f4eafc30 | 6114 | |
55a2c322 VM |
6115 | /* Used as a temporary results of some bitmap calculations. */ |
6116 | static bitmap_head temp_bitmap; | |
6117 | ||
8e9d68a9 VM |
6118 | /* We split for reloads of small class of hard regs. The following |
6119 | defines how many hard regs the class should have to be qualified as | |
6120 | small. The code is mostly oriented to x86/x86-64 architecture | |
6121 | where some insns need to use only specific register or pair of | |
6122 | registers and these register can live in RTL explicitly, e.g. for | |
6123 | parameter passing. */ | |
6124 | static const int max_small_class_regs_num = 2; | |
6125 | ||
55a2c322 VM |
6126 | /* Do inheritance/split transformations in EBB starting with HEAD and |
6127 | finishing on TAIL. We process EBB insns in the reverse order. | |
6128 | Return true if we did any inheritance/split transformation in the | |
6129 | EBB. | |
6130 | ||
6131 | We should avoid excessive splitting which results in worse code | |
6132 | because of inaccurate cost calculations for spilling new split | |
6133 | pseudos in such case. To achieve this we do splitting only if | |
6134 | register pressure is high in given basic block and there are reload | |
6135 | pseudos requiring hard registers. We could do more register | |
6136 | pressure calculations at any given program point to avoid necessary | |
6137 | splitting even more but it is to expensive and the current approach | |
6138 | works well enough. */ | |
6139 | static bool | |
cfa434f6 | 6140 | inherit_in_ebb (rtx_insn *head, rtx_insn *tail) |
55a2c322 VM |
6141 | { |
6142 | int i, src_regno, dst_regno, nregs; | |
df2980be | 6143 | bool change_p, succ_p, update_reloads_num_p; |
cfa434f6 | 6144 | rtx_insn *prev_insn, *last_insn; |
8a8330b7 | 6145 | rtx next_usage_insns, curr_set; |
55a2c322 VM |
6146 | enum reg_class cl; |
6147 | struct lra_insn_reg *reg; | |
6148 | basic_block last_processed_bb, curr_bb = NULL; | |
6149 | HARD_REG_SET potential_reload_hard_regs, live_hard_regs; | |
6150 | bitmap to_process; | |
6151 | unsigned int j; | |
6152 | bitmap_iterator bi; | |
6153 | bool head_p, after_p; | |
6154 | ||
6155 | change_p = false; | |
6156 | curr_usage_insns_check++; | |
8a8330b7 | 6157 | clear_invariants (); |
55a2c322 VM |
6158 | reloads_num = calls_num = 0; |
6159 | bitmap_clear (&check_only_regs); | |
8a8330b7 | 6160 | bitmap_clear (&invalid_invariant_regs); |
55a2c322 VM |
6161 | last_processed_bb = NULL; |
6162 | CLEAR_HARD_REG_SET (potential_reload_hard_regs); | |
8e9d68a9 VM |
6163 | COPY_HARD_REG_SET (live_hard_regs, eliminable_regset); |
6164 | IOR_HARD_REG_SET (live_hard_regs, lra_no_alloc_regs); | |
55a2c322 VM |
6165 | /* We don't process new insns generated in the loop. */ |
6166 | for (curr_insn = tail; curr_insn != PREV_INSN (head); curr_insn = prev_insn) | |
6167 | { | |
6168 | prev_insn = PREV_INSN (curr_insn); | |
6169 | if (BLOCK_FOR_INSN (curr_insn) != NULL) | |
6170 | curr_bb = BLOCK_FOR_INSN (curr_insn); | |
6171 | if (last_processed_bb != curr_bb) | |
6172 | { | |
6173 | /* We are at the end of BB. Add qualified living | |
6174 | pseudos for potential splitting. */ | |
6175 | to_process = df_get_live_out (curr_bb); | |
6176 | if (last_processed_bb != NULL) | |
f4eafc30 | 6177 | { |
55a2c322 VM |
6178 | /* We are somewhere in the middle of EBB. */ |
6179 | get_live_on_other_edges (curr_bb, last_processed_bb, | |
6180 | &temp_bitmap); | |
6181 | to_process = &temp_bitmap; | |
6182 | } | |
6183 | last_processed_bb = curr_bb; | |
6184 | last_insn = get_last_insertion_point (curr_bb); | |
6185 | after_p = (! JUMP_P (last_insn) | |
6186 | && (! CALL_P (last_insn) | |
6187 | || (find_reg_note (last_insn, | |
6188 | REG_NORETURN, NULL_RTX) == NULL_RTX | |
6189 | && ! SIBLING_CALL_P (last_insn)))); | |
55a2c322 VM |
6190 | CLEAR_HARD_REG_SET (potential_reload_hard_regs); |
6191 | EXECUTE_IF_SET_IN_BITMAP (to_process, 0, j, bi) | |
6192 | { | |
6193 | if ((int) j >= lra_constraint_new_regno_start) | |
6194 | break; | |
6195 | if (j < FIRST_PSEUDO_REGISTER || reg_renumber[j] >= 0) | |
6196 | { | |
6197 | if (j < FIRST_PSEUDO_REGISTER) | |
6198 | SET_HARD_REG_BIT (live_hard_regs, j); | |
6199 | else | |
6200 | add_to_hard_reg_set (&live_hard_regs, | |
6201 | PSEUDO_REGNO_MODE (j), | |
6202 | reg_renumber[j]); | |
6203 | setup_next_usage_insn (j, last_insn, reloads_num, after_p); | |
6204 | } | |
6205 | } | |
6206 | } | |
6207 | src_regno = dst_regno = -1; | |
8a8330b7 VM |
6208 | curr_set = single_set (curr_insn); |
6209 | if (curr_set != NULL_RTX && REG_P (SET_DEST (curr_set))) | |
6210 | dst_regno = REGNO (SET_DEST (curr_set)); | |
6211 | if (curr_set != NULL_RTX && REG_P (SET_SRC (curr_set))) | |
6212 | src_regno = REGNO (SET_SRC (curr_set)); | |
df2980be | 6213 | update_reloads_num_p = true; |
55a2c322 VM |
6214 | if (src_regno < lra_constraint_new_regno_start |
6215 | && src_regno >= FIRST_PSEUDO_REGISTER | |
6216 | && reg_renumber[src_regno] < 0 | |
6217 | && dst_regno >= lra_constraint_new_regno_start | |
6218 | && (cl = lra_get_allocno_class (dst_regno)) != NO_REGS) | |
6219 | { | |
6220 | /* 'reload_pseudo <- original_pseudo'. */ | |
8e9d68a9 VM |
6221 | if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num) |
6222 | reloads_num++; | |
df2980be | 6223 | update_reloads_num_p = false; |
55a2c322 VM |
6224 | succ_p = false; |
6225 | if (usage_insns[src_regno].check == curr_usage_insns_check | |
6226 | && (next_usage_insns = usage_insns[src_regno].insns) != NULL_RTX) | |
6227 | succ_p = inherit_reload_reg (false, src_regno, cl, | |
6228 | curr_insn, next_usage_insns); | |
6229 | if (succ_p) | |
6230 | change_p = true; | |
6231 | else | |
6232 | setup_next_usage_insn (src_regno, curr_insn, reloads_num, false); | |
6233 | if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs)) | |
6234 | IOR_HARD_REG_SET (potential_reload_hard_regs, | |
6235 | reg_class_contents[cl]); | |
6236 | } | |
8a8330b7 VM |
6237 | else if (src_regno < 0 |
6238 | && dst_regno >= lra_constraint_new_regno_start | |
6239 | && invariant_p (SET_SRC (curr_set)) | |
6240 | && (cl = lra_get_allocno_class (dst_regno)) != NO_REGS | |
f7abdf36 VM |
6241 | && ! bitmap_bit_p (&invalid_invariant_regs, dst_regno) |
6242 | && ! bitmap_bit_p (&invalid_invariant_regs, | |
6243 | ORIGINAL_REGNO(regno_reg_rtx[dst_regno]))) | |
8a8330b7 VM |
6244 | { |
6245 | /* 'reload_pseudo <- invariant'. */ | |
6246 | if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num) | |
6247 | reloads_num++; | |
6248 | update_reloads_num_p = false; | |
6249 | if (process_invariant_for_inheritance (SET_DEST (curr_set), SET_SRC (curr_set))) | |
6250 | change_p = true; | |
6251 | if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs)) | |
6252 | IOR_HARD_REG_SET (potential_reload_hard_regs, | |
6253 | reg_class_contents[cl]); | |
6254 | } | |
55a2c322 VM |
6255 | else if (src_regno >= lra_constraint_new_regno_start |
6256 | && dst_regno < lra_constraint_new_regno_start | |
6257 | && dst_regno >= FIRST_PSEUDO_REGISTER | |
6258 | && reg_renumber[dst_regno] < 0 | |
6259 | && (cl = lra_get_allocno_class (src_regno)) != NO_REGS | |
6260 | && usage_insns[dst_regno].check == curr_usage_insns_check | |
6261 | && (next_usage_insns | |
6262 | = usage_insns[dst_regno].insns) != NULL_RTX) | |
6263 | { | |
8e9d68a9 VM |
6264 | if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num) |
6265 | reloads_num++; | |
df2980be | 6266 | update_reloads_num_p = false; |
55a2c322 VM |
6267 | /* 'original_pseudo <- reload_pseudo'. */ |
6268 | if (! JUMP_P (curr_insn) | |
6269 | && inherit_reload_reg (true, dst_regno, cl, | |
6270 | curr_insn, next_usage_insns)) | |
6271 | change_p = true; | |
6272 | /* Invalidate. */ | |
6273 | usage_insns[dst_regno].check = 0; | |
6274 | if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs)) | |
6275 | IOR_HARD_REG_SET (potential_reload_hard_regs, | |
6276 | reg_class_contents[cl]); | |
6277 | } | |
6278 | else if (INSN_P (curr_insn)) | |
6279 | { | |
2f259720 | 6280 | int iter; |
55a2c322 VM |
6281 | int max_uid = get_max_uid (); |
6282 | ||
6283 | curr_id = lra_get_insn_recog_data (curr_insn); | |
2f259720 | 6284 | curr_static_id = curr_id->insn_static_data; |
55a2c322 VM |
6285 | to_inherit_num = 0; |
6286 | /* Process insn definitions. */ | |
2f259720 VM |
6287 | for (iter = 0; iter < 2; iter++) |
6288 | for (reg = iter == 0 ? curr_id->regs : curr_static_id->hard_regs; | |
6289 | reg != NULL; | |
6290 | reg = reg->next) | |
6291 | if (reg->type != OP_IN | |
6292 | && (dst_regno = reg->regno) < lra_constraint_new_regno_start) | |
6293 | { | |
6294 | if (dst_regno >= FIRST_PSEUDO_REGISTER && reg->type == OP_OUT | |
6295 | && reg_renumber[dst_regno] < 0 && ! reg->subreg_p | |
6296 | && usage_insns[dst_regno].check == curr_usage_insns_check | |
6297 | && (next_usage_insns | |
6298 | = usage_insns[dst_regno].insns) != NULL_RTX) | |
6299 | { | |
6300 | struct lra_insn_reg *r; | |
6301 | ||
6302 | for (r = curr_id->regs; r != NULL; r = r->next) | |
6303 | if (r->type != OP_OUT && r->regno == dst_regno) | |
6304 | break; | |
6305 | /* Don't do inheritance if the pseudo is also | |
6306 | used in the insn. */ | |
6307 | if (r == NULL) | |
6308 | /* We can not do inheritance right now | |
6309 | because the current insn reg info (chain | |
6310 | regs) can change after that. */ | |
6311 | add_to_inherit (dst_regno, next_usage_insns); | |
6312 | } | |
6313 | /* We can not process one reg twice here because of | |
6314 | usage_insns invalidation. */ | |
6315 | if ((dst_regno < FIRST_PSEUDO_REGISTER | |
6316 | || reg_renumber[dst_regno] >= 0) | |
e32e4c4a | 6317 | && ! reg->subreg_p && reg->type != OP_IN) |
2f259720 VM |
6318 | { |
6319 | HARD_REG_SET s; | |
6320 | ||
6321 | if (split_if_necessary (dst_regno, reg->biggest_mode, | |
6322 | potential_reload_hard_regs, | |
6323 | false, curr_insn, max_uid)) | |
6324 | change_p = true; | |
6325 | CLEAR_HARD_REG_SET (s); | |
6326 | if (dst_regno < FIRST_PSEUDO_REGISTER) | |
6327 | add_to_hard_reg_set (&s, reg->biggest_mode, dst_regno); | |
6328 | else | |
6329 | add_to_hard_reg_set (&s, PSEUDO_REGNO_MODE (dst_regno), | |
6330 | reg_renumber[dst_regno]); | |
6331 | AND_COMPL_HARD_REG_SET (live_hard_regs, s); | |
6332 | } | |
6333 | /* We should invalidate potential inheritance or | |
6334 | splitting for the current insn usages to the next | |
6335 | usage insns (see code below) as the output pseudo | |
6336 | prevents this. */ | |
6337 | if ((dst_regno >= FIRST_PSEUDO_REGISTER | |
6338 | && reg_renumber[dst_regno] < 0) | |
6339 | || (reg->type == OP_OUT && ! reg->subreg_p | |
6340 | && (dst_regno < FIRST_PSEUDO_REGISTER | |
6341 | || reg_renumber[dst_regno] >= 0))) | |
6342 | { | |
6343 | /* Invalidate and mark definitions. */ | |
6344 | if (dst_regno >= FIRST_PSEUDO_REGISTER) | |
6345 | usage_insns[dst_regno].check = -(int) INSN_UID (curr_insn); | |
6346 | else | |
6347 | { | |
ad474626 RS |
6348 | nregs = hard_regno_nregs (dst_regno, |
6349 | reg->biggest_mode); | |
2f259720 VM |
6350 | for (i = 0; i < nregs; i++) |
6351 | usage_insns[dst_regno + i].check | |
6352 | = -(int) INSN_UID (curr_insn); | |
6353 | } | |
6354 | } | |
6355 | } | |
9d86e84e VM |
6356 | /* Process clobbered call regs. */ |
6357 | if (curr_id->arg_hard_regs != NULL) | |
6358 | for (i = 0; (dst_regno = curr_id->arg_hard_regs[i]) >= 0; i++) | |
6359 | if (dst_regno >= FIRST_PSEUDO_REGISTER) | |
6360 | usage_insns[dst_regno - FIRST_PSEUDO_REGISTER].check | |
6361 | = -(int) INSN_UID (curr_insn); | |
55a2c322 VM |
6362 | if (! JUMP_P (curr_insn)) |
6363 | for (i = 0; i < to_inherit_num; i++) | |
6364 | if (inherit_reload_reg (true, to_inherit[i].regno, | |
6365 | ALL_REGS, curr_insn, | |
6366 | to_inherit[i].insns)) | |
6367 | change_p = true; | |
6368 | if (CALL_P (curr_insn)) | |
6369 | { | |
cfa434f6 DM |
6370 | rtx cheap, pat, dest; |
6371 | rtx_insn *restore; | |
55a2c322 VM |
6372 | int regno, hard_regno; |
6373 | ||
6374 | calls_num++; | |
6375 | if ((cheap = find_reg_note (curr_insn, | |
6376 | REG_RETURNED, NULL_RTX)) != NULL_RTX | |
6377 | && ((cheap = XEXP (cheap, 0)), true) | |
6378 | && (regno = REGNO (cheap)) >= FIRST_PSEUDO_REGISTER | |
6379 | && (hard_regno = reg_renumber[regno]) >= 0 | |
851dac7c | 6380 | && usage_insns[regno].check == curr_usage_insns_check |
55a2c322 VM |
6381 | /* If there are pending saves/restores, the |
6382 | optimization is not worth. */ | |
6383 | && usage_insns[regno].calls_num == calls_num - 1 | |
6384 | && TEST_HARD_REG_BIT (call_used_reg_set, hard_regno)) | |
6385 | { | |
6386 | /* Restore the pseudo from the call result as | |
6387 | REG_RETURNED note says that the pseudo value is | |
6388 | in the call result and the pseudo is an argument | |
6389 | of the call. */ | |
6390 | pat = PATTERN (curr_insn); | |
6391 | if (GET_CODE (pat) == PARALLEL) | |
6392 | pat = XVECEXP (pat, 0, 0); | |
6393 | dest = SET_DEST (pat); | |
54bddf1d IE |
6394 | /* For multiple return values dest is PARALLEL. |
6395 | Currently we handle only single return value case. */ | |
6396 | if (REG_P (dest)) | |
6397 | { | |
6398 | start_sequence (); | |
6399 | emit_move_insn (cheap, copy_rtx (dest)); | |
6400 | restore = get_insns (); | |
6401 | end_sequence (); | |
6402 | lra_process_new_insns (curr_insn, NULL, restore, | |
6403 | "Inserting call parameter restore"); | |
6404 | /* We don't need to save/restore of the pseudo from | |
6405 | this call. */ | |
6406 | usage_insns[regno].calls_num = calls_num; | |
6407 | bitmap_set_bit (&check_only_regs, regno); | |
6408 | } | |
55a2c322 VM |
6409 | } |
6410 | } | |
6411 | to_inherit_num = 0; | |
6412 | /* Process insn usages. */ | |
2f259720 VM |
6413 | for (iter = 0; iter < 2; iter++) |
6414 | for (reg = iter == 0 ? curr_id->regs : curr_static_id->hard_regs; | |
6415 | reg != NULL; | |
6416 | reg = reg->next) | |
6417 | if ((reg->type != OP_OUT | |
6418 | || (reg->type == OP_OUT && reg->subreg_p)) | |
6419 | && (src_regno = reg->regno) < lra_constraint_new_regno_start) | |
6420 | { | |
6421 | if (src_regno >= FIRST_PSEUDO_REGISTER | |
6422 | && reg_renumber[src_regno] < 0 && reg->type == OP_IN) | |
6423 | { | |
6424 | if (usage_insns[src_regno].check == curr_usage_insns_check | |
6425 | && (next_usage_insns | |
6426 | = usage_insns[src_regno].insns) != NULL_RTX | |
6427 | && NONDEBUG_INSN_P (curr_insn)) | |
6428 | add_to_inherit (src_regno, next_usage_insns); | |
6429 | else if (usage_insns[src_regno].check | |
6430 | != -(int) INSN_UID (curr_insn)) | |
6431 | /* Add usages but only if the reg is not set up | |
6432 | in the same insn. */ | |
6433 | add_next_usage_insn (src_regno, curr_insn, reloads_num); | |
6434 | } | |
6435 | else if (src_regno < FIRST_PSEUDO_REGISTER | |
6436 | || reg_renumber[src_regno] >= 0) | |
6437 | { | |
6438 | bool before_p; | |
e67d1102 | 6439 | rtx_insn *use_insn = curr_insn; |
2f259720 VM |
6440 | |
6441 | before_p = (JUMP_P (curr_insn) | |
6442 | || (CALL_P (curr_insn) && reg->type == OP_IN)); | |
6443 | if (NONDEBUG_INSN_P (curr_insn) | |
8e9d68a9 | 6444 | && (! JUMP_P (curr_insn) || reg->type == OP_IN) |
2f259720 VM |
6445 | && split_if_necessary (src_regno, reg->biggest_mode, |
6446 | potential_reload_hard_regs, | |
6447 | before_p, curr_insn, max_uid)) | |
6448 | { | |
6449 | if (reg->subreg_p) | |
6450 | lra_risky_transformations_p = true; | |
6451 | change_p = true; | |
8e9d68a9 | 6452 | /* Invalidate. */ |
2f259720 VM |
6453 | usage_insns[src_regno].check = 0; |
6454 | if (before_p) | |
6455 | use_insn = PREV_INSN (curr_insn); | |
6456 | } | |
6457 | if (NONDEBUG_INSN_P (curr_insn)) | |
6458 | { | |
6459 | if (src_regno < FIRST_PSEUDO_REGISTER) | |
6460 | add_to_hard_reg_set (&live_hard_regs, | |
6461 | reg->biggest_mode, src_regno); | |
6462 | else | |
6463 | add_to_hard_reg_set (&live_hard_regs, | |
6464 | PSEUDO_REGNO_MODE (src_regno), | |
6465 | reg_renumber[src_regno]); | |
6466 | } | |
16ba97b9 VM |
6467 | if (src_regno >= FIRST_PSEUDO_REGISTER) |
6468 | add_next_usage_insn (src_regno, use_insn, reloads_num); | |
6469 | else | |
6470 | { | |
6471 | for (i = 0; i < hard_regno_nregs (src_regno, reg->biggest_mode); i++) | |
6472 | add_next_usage_insn (src_regno + i, use_insn, reloads_num); | |
6473 | } | |
2f259720 VM |
6474 | } |
6475 | } | |
9d86e84e | 6476 | /* Process used call regs. */ |
df2980be VM |
6477 | if (curr_id->arg_hard_regs != NULL) |
6478 | for (i = 0; (src_regno = curr_id->arg_hard_regs[i]) >= 0; i++) | |
6479 | if (src_regno < FIRST_PSEUDO_REGISTER) | |
6480 | { | |
6481 | SET_HARD_REG_BIT (live_hard_regs, src_regno); | |
6482 | add_next_usage_insn (src_regno, curr_insn, reloads_num); | |
6483 | } | |
55a2c322 VM |
6484 | for (i = 0; i < to_inherit_num; i++) |
6485 | { | |
6486 | src_regno = to_inherit[i].regno; | |
6487 | if (inherit_reload_reg (false, src_regno, ALL_REGS, | |
6488 | curr_insn, to_inherit[i].insns)) | |
6489 | change_p = true; | |
6490 | else | |
6491 | setup_next_usage_insn (src_regno, curr_insn, reloads_num, false); | |
6492 | } | |
6493 | } | |
df2980be | 6494 | if (update_reloads_num_p |
8a8330b7 | 6495 | && NONDEBUG_INSN_P (curr_insn) && curr_set != NULL_RTX) |
df2980be VM |
6496 | { |
6497 | int regno = -1; | |
8a8330b7 VM |
6498 | if ((REG_P (SET_DEST (curr_set)) |
6499 | && (regno = REGNO (SET_DEST (curr_set))) >= lra_constraint_new_regno_start | |
df2980be VM |
6500 | && reg_renumber[regno] < 0 |
6501 | && (cl = lra_get_allocno_class (regno)) != NO_REGS) | |
8a8330b7 VM |
6502 | || (REG_P (SET_SRC (curr_set)) |
6503 | && (regno = REGNO (SET_SRC (curr_set))) >= lra_constraint_new_regno_start | |
df2980be VM |
6504 | && reg_renumber[regno] < 0 |
6505 | && (cl = lra_get_allocno_class (regno)) != NO_REGS)) | |
6506 | { | |
8e9d68a9 VM |
6507 | if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num) |
6508 | reloads_num++; | |
df2980be VM |
6509 | if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs)) |
6510 | IOR_HARD_REG_SET (potential_reload_hard_regs, | |
6511 | reg_class_contents[cl]); | |
6512 | } | |
6513 | } | |
8a8330b7 VM |
6514 | if (NONDEBUG_INSN_P (curr_insn)) |
6515 | { | |
6516 | int regno; | |
6517 | ||
6518 | /* Invalidate invariants with changed regs. */ | |
6519 | curr_id = lra_get_insn_recog_data (curr_insn); | |
6520 | for (reg = curr_id->regs; reg != NULL; reg = reg->next) | |
6521 | if (reg->type != OP_IN) | |
f7abdf36 VM |
6522 | { |
6523 | bitmap_set_bit (&invalid_invariant_regs, reg->regno); | |
6524 | bitmap_set_bit (&invalid_invariant_regs, | |
6525 | ORIGINAL_REGNO (regno_reg_rtx[reg->regno])); | |
6526 | } | |
8a8330b7 VM |
6527 | curr_static_id = curr_id->insn_static_data; |
6528 | for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next) | |
6529 | if (reg->type != OP_IN) | |
6530 | bitmap_set_bit (&invalid_invariant_regs, reg->regno); | |
6531 | if (curr_id->arg_hard_regs != NULL) | |
6532 | for (i = 0; (regno = curr_id->arg_hard_regs[i]) >= 0; i++) | |
f7abdf36 | 6533 | if (regno >= FIRST_PSEUDO_REGISTER) |
8a8330b7 | 6534 | bitmap_set_bit (&invalid_invariant_regs, |
f7abdf36 | 6535 | regno - FIRST_PSEUDO_REGISTER); |
8a8330b7 | 6536 | } |
55a2c322 VM |
6537 | /* We reached the start of the current basic block. */ |
6538 | if (prev_insn == NULL_RTX || prev_insn == PREV_INSN (head) | |
6539 | || BLOCK_FOR_INSN (prev_insn) != curr_bb) | |
6540 | { | |
6541 | /* We reached the beginning of the current block -- do | |
6542 | rest of spliting in the current BB. */ | |
6543 | to_process = df_get_live_in (curr_bb); | |
6544 | if (BLOCK_FOR_INSN (head) != curr_bb) | |
f4eafc30 | 6545 | { |
55a2c322 VM |
6546 | /* We are somewhere in the middle of EBB. */ |
6547 | get_live_on_other_edges (EDGE_PRED (curr_bb, 0)->src, | |
6548 | curr_bb, &temp_bitmap); | |
6549 | to_process = &temp_bitmap; | |
6550 | } | |
6551 | head_p = true; | |
6552 | EXECUTE_IF_SET_IN_BITMAP (to_process, 0, j, bi) | |
6553 | { | |
6554 | if ((int) j >= lra_constraint_new_regno_start) | |
6555 | break; | |
6556 | if (((int) j < FIRST_PSEUDO_REGISTER || reg_renumber[j] >= 0) | |
6557 | && usage_insns[j].check == curr_usage_insns_check | |
6558 | && (next_usage_insns = usage_insns[j].insns) != NULL_RTX) | |
6559 | { | |
6560 | if (need_for_split_p (potential_reload_hard_regs, j)) | |
6561 | { | |
6562 | if (lra_dump_file != NULL && head_p) | |
6563 | { | |
6564 | fprintf (lra_dump_file, | |
6565 | " ----------------------------------\n"); | |
6566 | head_p = false; | |
6567 | } | |
6568 | if (split_reg (false, j, bb_note (curr_bb), | |
6027ea4c | 6569 | next_usage_insns, NULL)) |
55a2c322 VM |
6570 | change_p = true; |
6571 | } | |
6572 | usage_insns[j].check = 0; | |
6573 | } | |
6574 | } | |
6575 | } | |
6576 | } | |
6577 | return change_p; | |
6578 | } | |
6579 | ||
6580 | /* This value affects EBB forming. If probability of edge from EBB to | |
6581 | a BB is not greater than the following value, we don't add the BB | |
f4eafc30 | 6582 | to EBB. */ |
fb8a0e40 VM |
6583 | #define EBB_PROBABILITY_CUTOFF \ |
6584 | ((REG_BR_PROB_BASE * LRA_INHERITANCE_EBB_PROBABILITY_CUTOFF) / 100) | |
55a2c322 VM |
6585 | |
6586 | /* Current number of inheritance/split iteration. */ | |
6587 | int lra_inheritance_iter; | |
6588 | ||
6589 | /* Entry function for inheritance/split pass. */ | |
6590 | void | |
6591 | lra_inheritance (void) | |
6592 | { | |
6593 | int i; | |
6594 | basic_block bb, start_bb; | |
6595 | edge e; | |
6596 | ||
55a2c322 | 6597 | lra_inheritance_iter++; |
8e3a4869 | 6598 | if (lra_inheritance_iter > LRA_MAX_INHERITANCE_PASSES) |
e731262b VM |
6599 | return; |
6600 | timevar_push (TV_LRA_INHERITANCE); | |
55a2c322 VM |
6601 | if (lra_dump_file != NULL) |
6602 | fprintf (lra_dump_file, "\n********** Inheritance #%d: **********\n\n", | |
6603 | lra_inheritance_iter); | |
6604 | curr_usage_insns_check = 0; | |
6605 | usage_insns = XNEWVEC (struct usage_insns, lra_constraint_new_regno_start); | |
6606 | for (i = 0; i < lra_constraint_new_regno_start; i++) | |
6607 | usage_insns[i].check = 0; | |
6608 | bitmap_initialize (&check_only_regs, ®_obstack); | |
8a8330b7 | 6609 | bitmap_initialize (&invalid_invariant_regs, ®_obstack); |
55a2c322 VM |
6610 | bitmap_initialize (&live_regs, ®_obstack); |
6611 | bitmap_initialize (&temp_bitmap, ®_obstack); | |
6612 | bitmap_initialize (&ebb_global_regs, ®_obstack); | |
11cd3bed | 6613 | FOR_EACH_BB_FN (bb, cfun) |
55a2c322 VM |
6614 | { |
6615 | start_bb = bb; | |
6616 | if (lra_dump_file != NULL) | |
6617 | fprintf (lra_dump_file, "EBB"); | |
6618 | /* Form a EBB starting with BB. */ | |
6619 | bitmap_clear (&ebb_global_regs); | |
6620 | bitmap_ior_into (&ebb_global_regs, df_get_live_in (bb)); | |
6621 | for (;;) | |
6622 | { | |
6623 | if (lra_dump_file != NULL) | |
6624 | fprintf (lra_dump_file, " %d", bb->index); | |
fefa31b5 DM |
6625 | if (bb->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun) |
6626 | || LABEL_P (BB_HEAD (bb->next_bb))) | |
55a2c322 VM |
6627 | break; |
6628 | e = find_fallthru_edge (bb->succs); | |
6629 | if (! e) | |
6630 | break; | |
357067f2 JH |
6631 | if (e->probability.initialized_p () |
6632 | && e->probability.to_reg_br_prob_base () < EBB_PROBABILITY_CUTOFF) | |
55a2c322 VM |
6633 | break; |
6634 | bb = bb->next_bb; | |
6635 | } | |
6636 | bitmap_ior_into (&ebb_global_regs, df_get_live_out (bb)); | |
6637 | if (lra_dump_file != NULL) | |
6638 | fprintf (lra_dump_file, "\n"); | |
6639 | if (inherit_in_ebb (BB_HEAD (start_bb), BB_END (bb))) | |
6640 | /* Remember that the EBB head and tail can change in | |
6641 | inherit_in_ebb. */ | |
6642 | update_ebb_live_info (BB_HEAD (start_bb), BB_END (bb)); | |
6643 | } | |
6644 | bitmap_clear (&ebb_global_regs); | |
6645 | bitmap_clear (&temp_bitmap); | |
6646 | bitmap_clear (&live_regs); | |
8a8330b7 | 6647 | bitmap_clear (&invalid_invariant_regs); |
55a2c322 VM |
6648 | bitmap_clear (&check_only_regs); |
6649 | free (usage_insns); | |
6650 | ||
6651 | timevar_pop (TV_LRA_INHERITANCE); | |
6652 | } | |
6653 | ||
6654 | \f | |
6655 | ||
6656 | /* This page contains code to undo failed inheritance/split | |
6657 | transformations. */ | |
6658 | ||
6659 | /* Current number of iteration undoing inheritance/split. */ | |
6660 | int lra_undo_inheritance_iter; | |
6661 | ||
6662 | /* Fix BB live info LIVE after removing pseudos created on pass doing | |
6663 | inheritance/split which are REMOVED_PSEUDOS. */ | |
6664 | static void | |
6665 | fix_bb_live_info (bitmap live, bitmap removed_pseudos) | |
6666 | { | |
6667 | unsigned int regno; | |
6668 | bitmap_iterator bi; | |
6669 | ||
6670 | EXECUTE_IF_SET_IN_BITMAP (removed_pseudos, 0, regno, bi) | |
8a8330b7 VM |
6671 | if (bitmap_clear_bit (live, regno) |
6672 | && REG_P (lra_reg_info[regno].restore_rtx)) | |
6673 | bitmap_set_bit (live, REGNO (lra_reg_info[regno].restore_rtx)); | |
55a2c322 VM |
6674 | } |
6675 | ||
6676 | /* Return regno of the (subreg of) REG. Otherwise, return a negative | |
6677 | number. */ | |
6678 | static int | |
6679 | get_regno (rtx reg) | |
6680 | { | |
6681 | if (GET_CODE (reg) == SUBREG) | |
6682 | reg = SUBREG_REG (reg); | |
6683 | if (REG_P (reg)) | |
6684 | return REGNO (reg); | |
6685 | return -1; | |
6686 | } | |
6687 | ||
cefe08a4 VM |
6688 | /* Delete a move INSN with destination reg DREGNO and a previous |
6689 | clobber insn with the same regno. The inheritance/split code can | |
6690 | generate moves with preceding clobber and when we delete such moves | |
6691 | we should delete the clobber insn too to keep the correct life | |
6692 | info. */ | |
6693 | static void | |
6694 | delete_move_and_clobber (rtx_insn *insn, int dregno) | |
6695 | { | |
6696 | rtx_insn *prev_insn = PREV_INSN (insn); | |
6697 | ||
6698 | lra_set_insn_deleted (insn); | |
79b57d18 | 6699 | lra_assert (dregno >= 0); |
cefe08a4 VM |
6700 | if (prev_insn != NULL && NONDEBUG_INSN_P (prev_insn) |
6701 | && GET_CODE (PATTERN (prev_insn)) == CLOBBER | |
6702 | && dregno == get_regno (XEXP (PATTERN (prev_insn), 0))) | |
6703 | lra_set_insn_deleted (prev_insn); | |
6704 | } | |
6705 | ||
55a2c322 VM |
6706 | /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and |
6707 | return true if we did any change. The undo transformations for | |
6708 | inheritance looks like | |
6709 | i <- i2 | |
6710 | p <- i => p <- i2 | |
6711 | or removing | |
6712 | p <- i, i <- p, and i <- i3 | |
6713 | where p is original pseudo from which inheritance pseudo i was | |
6714 | created, i and i3 are removed inheritance pseudos, i2 is another | |
6715 | not removed inheritance pseudo. All split pseudos or other | |
6716 | occurrences of removed inheritance pseudos are changed on the | |
6717 | corresponding original pseudos. | |
6718 | ||
6719 | The function also schedules insns changed and created during | |
6720 | inheritance/split pass for processing by the subsequent constraint | |
6721 | pass. */ | |
6722 | static bool | |
6723 | remove_inheritance_pseudos (bitmap remove_pseudos) | |
6724 | { | |
6725 | basic_block bb; | |
8a8330b7 VM |
6726 | int regno, sregno, prev_sregno, dregno; |
6727 | rtx restore_rtx; | |
cfa434f6 DM |
6728 | rtx set, prev_set; |
6729 | rtx_insn *prev_insn; | |
55a2c322 VM |
6730 | bool change_p, done_p; |
6731 | ||
6732 | change_p = ! bitmap_empty_p (remove_pseudos); | |
6733 | /* We can not finish the function right away if CHANGE_P is true | |
6734 | because we need to marks insns affected by previous | |
6735 | inheritance/split pass for processing by the subsequent | |
6736 | constraint pass. */ | |
11cd3bed | 6737 | FOR_EACH_BB_FN (bb, cfun) |
55a2c322 VM |
6738 | { |
6739 | fix_bb_live_info (df_get_live_in (bb), remove_pseudos); | |
6740 | fix_bb_live_info (df_get_live_out (bb), remove_pseudos); | |
6741 | FOR_BB_INSNS_REVERSE (bb, curr_insn) | |
6742 | { | |
6743 | if (! INSN_P (curr_insn)) | |
6744 | continue; | |
6745 | done_p = false; | |
6746 | sregno = dregno = -1; | |
6747 | if (change_p && NONDEBUG_INSN_P (curr_insn) | |
6748 | && (set = single_set (curr_insn)) != NULL_RTX) | |
6749 | { | |
6750 | dregno = get_regno (SET_DEST (set)); | |
6751 | sregno = get_regno (SET_SRC (set)); | |
6752 | } | |
f4eafc30 | 6753 | |
55a2c322 VM |
6754 | if (sregno >= 0 && dregno >= 0) |
6755 | { | |
8a8330b7 VM |
6756 | if (bitmap_bit_p (remove_pseudos, dregno) |
6757 | && ! REG_P (lra_reg_info[dregno].restore_rtx)) | |
6758 | { | |
6759 | /* invariant inheritance pseudo <- original pseudo */ | |
6760 | if (lra_dump_file != NULL) | |
6761 | { | |
6762 | fprintf (lra_dump_file, " Removing invariant inheritance:\n"); | |
6763 | dump_insn_slim (lra_dump_file, curr_insn); | |
6764 | fprintf (lra_dump_file, "\n"); | |
6765 | } | |
6766 | delete_move_and_clobber (curr_insn, dregno); | |
6767 | done_p = true; | |
6768 | } | |
6769 | else if (bitmap_bit_p (remove_pseudos, sregno) | |
6770 | && ! REG_P (lra_reg_info[sregno].restore_rtx)) | |
6771 | { | |
6772 | /* reload pseudo <- invariant inheritance pseudo */ | |
6773 | start_sequence (); | |
6774 | /* We can not just change the source. It might be | |
6775 | an insn different from the move. */ | |
b10d44ef | 6776 | emit_insn (lra_reg_info[sregno].restore_rtx); |
8a8330b7 VM |
6777 | rtx_insn *new_insns = get_insns (); |
6778 | end_sequence (); | |
b10d44ef VM |
6779 | lra_assert (single_set (new_insns) != NULL |
6780 | && SET_DEST (set) == SET_DEST (single_set (new_insns))); | |
8a8330b7 VM |
6781 | lra_process_new_insns (curr_insn, NULL, new_insns, |
6782 | "Changing reload<-invariant inheritance"); | |
6783 | delete_move_and_clobber (curr_insn, dregno); | |
6784 | done_p = true; | |
6785 | } | |
6786 | else if ((bitmap_bit_p (remove_pseudos, sregno) | |
6787 | && (get_regno (lra_reg_info[sregno].restore_rtx) == dregno | |
6788 | || (bitmap_bit_p (remove_pseudos, dregno) | |
6789 | && get_regno (lra_reg_info[sregno].restore_rtx) >= 0 | |
6790 | && (get_regno (lra_reg_info[sregno].restore_rtx) | |
6791 | == get_regno (lra_reg_info[dregno].restore_rtx))))) | |
55a2c322 | 6792 | || (bitmap_bit_p (remove_pseudos, dregno) |
8a8330b7 | 6793 | && get_regno (lra_reg_info[dregno].restore_rtx) == sregno)) |
55a2c322 VM |
6794 | /* One of the following cases: |
6795 | original <- removed inheritance pseudo | |
6796 | removed inherit pseudo <- another removed inherit pseudo | |
6797 | removed inherit pseudo <- original pseudo | |
6798 | Or | |
6799 | removed_split_pseudo <- original_reg | |
6800 | original_reg <- removed_split_pseudo */ | |
6801 | { | |
6802 | if (lra_dump_file != NULL) | |
6803 | { | |
6804 | fprintf (lra_dump_file, " Removing %s:\n", | |
6805 | bitmap_bit_p (&lra_split_regs, sregno) | |
6806 | || bitmap_bit_p (&lra_split_regs, dregno) | |
6807 | ? "split" : "inheritance"); | |
cfbeaedf | 6808 | dump_insn_slim (lra_dump_file, curr_insn); |
55a2c322 | 6809 | } |
cefe08a4 | 6810 | delete_move_and_clobber (curr_insn, dregno); |
55a2c322 VM |
6811 | done_p = true; |
6812 | } | |
6813 | else if (bitmap_bit_p (remove_pseudos, sregno) | |
6814 | && bitmap_bit_p (&lra_inheritance_pseudos, sregno)) | |
6815 | { | |
6816 | /* Search the following pattern: | |
6817 | inherit_or_split_pseudo1 <- inherit_or_split_pseudo2 | |
6818 | original_pseudo <- inherit_or_split_pseudo1 | |
6819 | where the 2nd insn is the current insn and | |
6820 | inherit_or_split_pseudo2 is not removed. If it is found, | |
6821 | change the current insn onto: | |
6822 | original_pseudo <- inherit_or_split_pseudo2. */ | |
6823 | for (prev_insn = PREV_INSN (curr_insn); | |
6824 | prev_insn != NULL_RTX && ! NONDEBUG_INSN_P (prev_insn); | |
6825 | prev_insn = PREV_INSN (prev_insn)) | |
6826 | ; | |
6827 | if (prev_insn != NULL_RTX && BLOCK_FOR_INSN (prev_insn) == bb | |
6828 | && (prev_set = single_set (prev_insn)) != NULL_RTX | |
6829 | /* There should be no subregs in insn we are | |
6830 | searching because only the original reg might | |
6831 | be in subreg when we changed the mode of | |
6832 | load/store for splitting. */ | |
6833 | && REG_P (SET_DEST (prev_set)) | |
6834 | && REG_P (SET_SRC (prev_set)) | |
6835 | && (int) REGNO (SET_DEST (prev_set)) == sregno | |
6836 | && ((prev_sregno = REGNO (SET_SRC (prev_set))) | |
6837 | >= FIRST_PSEUDO_REGISTER) | |
8a8330b7 VM |
6838 | && (lra_reg_info[prev_sregno].restore_rtx == NULL_RTX |
6839 | || | |
6840 | /* As we consider chain of inheritance or | |
6841 | splitting described in above comment we should | |
6842 | check that sregno and prev_sregno were | |
6843 | inheritance/split pseudos created from the | |
6844 | same original regno. */ | |
6845 | (get_regno (lra_reg_info[sregno].restore_rtx) >= 0 | |
6846 | && (get_regno (lra_reg_info[sregno].restore_rtx) | |
6847 | == get_regno (lra_reg_info[prev_sregno].restore_rtx)))) | |
55a2c322 VM |
6848 | && ! bitmap_bit_p (remove_pseudos, prev_sregno)) |
6849 | { | |
6850 | lra_assert (GET_MODE (SET_SRC (prev_set)) | |
6851 | == GET_MODE (regno_reg_rtx[sregno])); | |
ef61d1ab AK |
6852 | /* Although we have a single set, the insn can |
6853 | contain more one sregno register occurrence | |
6854 | as a source. Change all occurrences. */ | |
6855 | lra_substitute_pseudo_within_insn (curr_insn, sregno, | |
6856 | SET_SRC (prev_set), | |
6857 | false); | |
12b308fa VM |
6858 | /* As we are finishing with processing the insn |
6859 | here, check the destination too as it might | |
6860 | inheritance pseudo for another pseudo. */ | |
6861 | if (bitmap_bit_p (remove_pseudos, dregno) | |
6862 | && bitmap_bit_p (&lra_inheritance_pseudos, dregno) | |
8a8330b7 VM |
6863 | && (restore_rtx |
6864 | = lra_reg_info[dregno].restore_rtx) != NULL_RTX) | |
12b308fa VM |
6865 | { |
6866 | if (GET_CODE (SET_DEST (set)) == SUBREG) | |
8a8330b7 | 6867 | SUBREG_REG (SET_DEST (set)) = restore_rtx; |
12b308fa | 6868 | else |
8a8330b7 | 6869 | SET_DEST (set) = restore_rtx; |
12b308fa | 6870 | } |
55a2c322 VM |
6871 | lra_push_insn_and_update_insn_regno_info (curr_insn); |
6872 | lra_set_used_insn_alternative_by_uid | |
7874b7c5 | 6873 | (INSN_UID (curr_insn), LRA_UNKNOWN_ALT); |
55a2c322 VM |
6874 | done_p = true; |
6875 | if (lra_dump_file != NULL) | |
6876 | { | |
6877 | fprintf (lra_dump_file, " Change reload insn:\n"); | |
cfbeaedf | 6878 | dump_insn_slim (lra_dump_file, curr_insn); |
55a2c322 VM |
6879 | } |
6880 | } | |
6881 | } | |
6882 | } | |
6883 | if (! done_p) | |
6884 | { | |
6885 | struct lra_insn_reg *reg; | |
6886 | bool restored_regs_p = false; | |
6887 | bool kept_regs_p = false; | |
6888 | ||
6889 | curr_id = lra_get_insn_recog_data (curr_insn); | |
6890 | for (reg = curr_id->regs; reg != NULL; reg = reg->next) | |
6891 | { | |
6892 | regno = reg->regno; | |
8a8330b7 VM |
6893 | restore_rtx = lra_reg_info[regno].restore_rtx; |
6894 | if (restore_rtx != NULL_RTX) | |
55a2c322 VM |
6895 | { |
6896 | if (change_p && bitmap_bit_p (remove_pseudos, regno)) | |
6897 | { | |
ef87312e | 6898 | lra_substitute_pseudo_within_insn |
8a8330b7 | 6899 | (curr_insn, regno, restore_rtx, false); |
55a2c322 VM |
6900 | restored_regs_p = true; |
6901 | } | |
6902 | else | |
6903 | kept_regs_p = true; | |
6904 | } | |
6905 | } | |
6906 | if (NONDEBUG_INSN_P (curr_insn) && kept_regs_p) | |
6907 | { | |
6908 | /* The instruction has changed since the previous | |
6909 | constraints pass. */ | |
6910 | lra_push_insn_and_update_insn_regno_info (curr_insn); | |
6911 | lra_set_used_insn_alternative_by_uid | |
7874b7c5 | 6912 | (INSN_UID (curr_insn), LRA_UNKNOWN_ALT); |
55a2c322 VM |
6913 | } |
6914 | else if (restored_regs_p) | |
6915 | /* The instruction has been restored to the form that | |
6916 | it had during the previous constraints pass. */ | |
6917 | lra_update_insn_regno_info (curr_insn); | |
6918 | if (restored_regs_p && lra_dump_file != NULL) | |
6919 | { | |
6920 | fprintf (lra_dump_file, " Insn after restoring regs:\n"); | |
cfbeaedf | 6921 | dump_insn_slim (lra_dump_file, curr_insn); |
55a2c322 VM |
6922 | } |
6923 | } | |
6924 | } | |
6925 | } | |
6926 | return change_p; | |
6927 | } | |
6928 | ||
2b778c9d VM |
6929 | /* If optional reload pseudos failed to get a hard register or was not |
6930 | inherited, it is better to remove optional reloads. We do this | |
6931 | transformation after undoing inheritance to figure out necessity to | |
6932 | remove optional reloads easier. Return true if we do any | |
6933 | change. */ | |
6934 | static bool | |
6935 | undo_optional_reloads (void) | |
6936 | { | |
b0681c9e | 6937 | bool change_p, keep_p; |
2b778c9d VM |
6938 | unsigned int regno, uid; |
6939 | bitmap_iterator bi, bi2; | |
cfa434f6 DM |
6940 | rtx_insn *insn; |
6941 | rtx set, src, dest; | |
d648b5ff | 6942 | auto_bitmap removed_optional_reload_pseudos (®_obstack); |
2b778c9d | 6943 | |
d648b5ff | 6944 | bitmap_copy (removed_optional_reload_pseudos, &lra_optional_reload_pseudos); |
2b778c9d | 6945 | EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos, 0, regno, bi) |
aa940f7c VM |
6946 | { |
6947 | keep_p = false; | |
080cbf9e | 6948 | /* Keep optional reloads from previous subpasses. */ |
8a8330b7 | 6949 | if (lra_reg_info[regno].restore_rtx == NULL_RTX |
080cbf9e VM |
6950 | /* If the original pseudo changed its allocation, just |
6951 | removing the optional pseudo is dangerous as the original | |
6952 | pseudo will have longer live range. */ | |
8a8330b7 | 6953 | || reg_renumber[REGNO (lra_reg_info[regno].restore_rtx)] >= 0) |
aa940f7c VM |
6954 | keep_p = true; |
6955 | else if (reg_renumber[regno] >= 0) | |
6956 | EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi2) | |
b0681c9e | 6957 | { |
aa940f7c VM |
6958 | insn = lra_insn_recog_data[uid]->insn; |
6959 | if ((set = single_set (insn)) == NULL_RTX) | |
6960 | continue; | |
6961 | src = SET_SRC (set); | |
6962 | dest = SET_DEST (set); | |
6963 | if (! REG_P (src) || ! REG_P (dest)) | |
6964 | continue; | |
6965 | if (REGNO (dest) == regno | |
6966 | /* Ignore insn for optional reloads itself. */ | |
8a8330b7 | 6967 | && REGNO (lra_reg_info[regno].restore_rtx) != REGNO (src) |
aa940f7c VM |
6968 | /* Check only inheritance on last inheritance pass. */ |
6969 | && (int) REGNO (src) >= new_regno_start | |
6970 | /* Check that the optional reload was inherited. */ | |
6971 | && bitmap_bit_p (&lra_inheritance_pseudos, REGNO (src))) | |
6972 | { | |
6973 | keep_p = true; | |
6974 | break; | |
6975 | } | |
b0681c9e | 6976 | } |
aa940f7c VM |
6977 | if (keep_p) |
6978 | { | |
d648b5ff | 6979 | bitmap_clear_bit (removed_optional_reload_pseudos, regno); |
aa940f7c VM |
6980 | if (lra_dump_file != NULL) |
6981 | fprintf (lra_dump_file, "Keep optional reload reg %d\n", regno); | |
6982 | } | |
6983 | } | |
d648b5ff TS |
6984 | change_p = ! bitmap_empty_p (removed_optional_reload_pseudos); |
6985 | auto_bitmap insn_bitmap (®_obstack); | |
6986 | EXECUTE_IF_SET_IN_BITMAP (removed_optional_reload_pseudos, 0, regno, bi) | |
2b778c9d VM |
6987 | { |
6988 | if (lra_dump_file != NULL) | |
6989 | fprintf (lra_dump_file, "Remove optional reload reg %d\n", regno); | |
d648b5ff TS |
6990 | bitmap_copy (insn_bitmap, &lra_reg_info[regno].insn_bitmap); |
6991 | EXECUTE_IF_SET_IN_BITMAP (insn_bitmap, 0, uid, bi2) | |
2b778c9d VM |
6992 | { |
6993 | insn = lra_insn_recog_data[uid]->insn; | |
6994 | if ((set = single_set (insn)) != NULL_RTX) | |
6995 | { | |
6996 | src = SET_SRC (set); | |
6997 | dest = SET_DEST (set); | |
6998 | if (REG_P (src) && REG_P (dest) | |
6999 | && ((REGNO (src) == regno | |
8a8330b7 VM |
7000 | && (REGNO (lra_reg_info[regno].restore_rtx) |
7001 | == REGNO (dest))) | |
2b778c9d | 7002 | || (REGNO (dest) == regno |
8a8330b7 VM |
7003 | && (REGNO (lra_reg_info[regno].restore_rtx) |
7004 | == REGNO (src))))) | |
2b778c9d VM |
7005 | { |
7006 | if (lra_dump_file != NULL) | |
7007 | { | |
7008 | fprintf (lra_dump_file, " Deleting move %u\n", | |
7009 | INSN_UID (insn)); | |
7010 | dump_insn_slim (lra_dump_file, insn); | |
7011 | } | |
cefe08a4 | 7012 | delete_move_and_clobber (insn, REGNO (dest)); |
2b778c9d VM |
7013 | continue; |
7014 | } | |
7015 | /* We should not worry about generation memory-memory | |
7016 | moves here as if the corresponding inheritance did | |
7017 | not work (inheritance pseudo did not get a hard reg), | |
7018 | we remove the inheritance pseudo and the optional | |
7019 | reload. */ | |
7020 | } | |
ef87312e | 7021 | lra_substitute_pseudo_within_insn |
8a8330b7 | 7022 | (insn, regno, lra_reg_info[regno].restore_rtx, false); |
2b778c9d VM |
7023 | lra_update_insn_regno_info (insn); |
7024 | if (lra_dump_file != NULL) | |
7025 | { | |
7026 | fprintf (lra_dump_file, | |
7027 | " Restoring original insn:\n"); | |
7028 | dump_insn_slim (lra_dump_file, insn); | |
7029 | } | |
7030 | } | |
7031 | } | |
7032 | /* Clear restore_regnos. */ | |
7033 | EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos, 0, regno, bi) | |
8a8330b7 | 7034 | lra_reg_info[regno].restore_rtx = NULL_RTX; |
2b778c9d VM |
7035 | return change_p; |
7036 | } | |
7037 | ||
55a2c322 VM |
7038 | /* Entry function for undoing inheritance/split transformation. Return true |
7039 | if we did any RTL change in this pass. */ | |
7040 | bool | |
7041 | lra_undo_inheritance (void) | |
7042 | { | |
7043 | unsigned int regno; | |
8a8330b7 | 7044 | int hard_regno; |
55a2c322 | 7045 | int n_all_inherit, n_inherit, n_all_split, n_split; |
8a8330b7 | 7046 | rtx restore_rtx; |
55a2c322 VM |
7047 | bitmap_iterator bi; |
7048 | bool change_p; | |
7049 | ||
7050 | lra_undo_inheritance_iter++; | |
8e3a4869 | 7051 | if (lra_undo_inheritance_iter > LRA_MAX_INHERITANCE_PASSES) |
e731262b | 7052 | return false; |
55a2c322 VM |
7053 | if (lra_dump_file != NULL) |
7054 | fprintf (lra_dump_file, | |
7055 | "\n********** Undoing inheritance #%d: **********\n\n", | |
7056 | lra_undo_inheritance_iter); | |
d648b5ff | 7057 | auto_bitmap remove_pseudos (®_obstack); |
55a2c322 VM |
7058 | n_inherit = n_all_inherit = 0; |
7059 | EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos, 0, regno, bi) | |
8a8330b7 | 7060 | if (lra_reg_info[regno].restore_rtx != NULL_RTX) |
55a2c322 VM |
7061 | { |
7062 | n_all_inherit++; | |
b0681c9e VM |
7063 | if (reg_renumber[regno] < 0 |
7064 | /* If the original pseudo changed its allocation, just | |
7065 | removing inheritance is dangerous as for changing | |
7066 | allocation we used shorter live-ranges. */ | |
8a8330b7 VM |
7067 | && (! REG_P (lra_reg_info[regno].restore_rtx) |
7068 | || reg_renumber[REGNO (lra_reg_info[regno].restore_rtx)] < 0)) | |
d648b5ff | 7069 | bitmap_set_bit (remove_pseudos, regno); |
55a2c322 VM |
7070 | else |
7071 | n_inherit++; | |
7072 | } | |
7073 | if (lra_dump_file != NULL && n_all_inherit != 0) | |
7074 | fprintf (lra_dump_file, "Inherit %d out of %d (%.2f%%)\n", | |
7075 | n_inherit, n_all_inherit, | |
7076 | (double) n_inherit / n_all_inherit * 100); | |
7077 | n_split = n_all_split = 0; | |
7078 | EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs, 0, regno, bi) | |
8a8330b7 | 7079 | if ((restore_rtx = lra_reg_info[regno].restore_rtx) != NULL_RTX) |
55a2c322 | 7080 | { |
8a8330b7 VM |
7081 | int restore_regno = REGNO (restore_rtx); |
7082 | ||
55a2c322 VM |
7083 | n_all_split++; |
7084 | hard_regno = (restore_regno >= FIRST_PSEUDO_REGISTER | |
7085 | ? reg_renumber[restore_regno] : restore_regno); | |
7086 | if (hard_regno < 0 || reg_renumber[regno] == hard_regno) | |
d648b5ff | 7087 | bitmap_set_bit (remove_pseudos, regno); |
55a2c322 VM |
7088 | else |
7089 | { | |
7090 | n_split++; | |
7091 | if (lra_dump_file != NULL) | |
7092 | fprintf (lra_dump_file, " Keep split r%d (orig=r%d)\n", | |
7093 | regno, restore_regno); | |
7094 | } | |
7095 | } | |
7096 | if (lra_dump_file != NULL && n_all_split != 0) | |
7097 | fprintf (lra_dump_file, "Split %d out of %d (%.2f%%)\n", | |
7098 | n_split, n_all_split, | |
7099 | (double) n_split / n_all_split * 100); | |
d648b5ff | 7100 | change_p = remove_inheritance_pseudos (remove_pseudos); |
55a2c322 VM |
7101 | /* Clear restore_regnos. */ |
7102 | EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos, 0, regno, bi) | |
8a8330b7 | 7103 | lra_reg_info[regno].restore_rtx = NULL_RTX; |
55a2c322 | 7104 | EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs, 0, regno, bi) |
8a8330b7 | 7105 | lra_reg_info[regno].restore_rtx = NULL_RTX; |
2b778c9d | 7106 | change_p = undo_optional_reloads () || change_p; |
55a2c322 VM |
7107 | return change_p; |
7108 | } |