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55a2c322 | 1 | /* Code for RTL transformations to satisfy insn constraints. |
818ab71a | 2 | Copyright (C) 2010-2016 Free Software Foundation, Inc. |
55a2c322 VM |
3 | Contributed by Vladimir Makarov <vmakarov@redhat.com>. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it under | |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 3, or (at your option) any later | |
10 | version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | ||
22 | /* This file contains code for 3 passes: constraint pass, | |
23 | inheritance/split pass, and pass for undoing failed inheritance and | |
24 | split. | |
25 | ||
26 | The major goal of constraint pass is to transform RTL to satisfy | |
27 | insn and address constraints by: | |
28 | o choosing insn alternatives; | |
29 | o generating *reload insns* (or reloads in brief) and *reload | |
30 | pseudos* which will get necessary hard registers later; | |
31 | o substituting pseudos with equivalent values and removing the | |
32 | instructions that initialized those pseudos. | |
33 | ||
34 | The constraint pass has biggest and most complicated code in LRA. | |
35 | There are a lot of important details like: | |
36 | o reuse of input reload pseudos to simplify reload pseudo | |
37 | allocations; | |
38 | o some heuristics to choose insn alternative to improve the | |
39 | inheritance; | |
40 | o early clobbers etc. | |
41 | ||
42 | The pass is mimicking former reload pass in alternative choosing | |
43 | because the reload pass is oriented to current machine description | |
44 | model. It might be changed if the machine description model is | |
45 | changed. | |
46 | ||
47 | There is special code for preventing all LRA and this pass cycling | |
48 | in case of bugs. | |
49 | ||
50 | On the first iteration of the pass we process every instruction and | |
51 | choose an alternative for each one. On subsequent iterations we try | |
52 | to avoid reprocessing instructions if we can be sure that the old | |
53 | choice is still valid. | |
54 | ||
55 | The inheritance/spilt pass is to transform code to achieve | |
56 | ineheritance and live range splitting. It is done on backward | |
57 | traversal of EBBs. | |
58 | ||
59 | The inheritance optimization goal is to reuse values in hard | |
60 | registers. There is analogous optimization in old reload pass. The | |
61 | inheritance is achieved by following transformation: | |
62 | ||
63 | reload_p1 <- p reload_p1 <- p | |
64 | ... new_p <- reload_p1 | |
65 | ... => ... | |
66 | reload_p2 <- p reload_p2 <- new_p | |
67 | ||
68 | where p is spilled and not changed between the insns. Reload_p1 is | |
69 | also called *original pseudo* and new_p is called *inheritance | |
70 | pseudo*. | |
71 | ||
72 | The subsequent assignment pass will try to assign the same (or | |
73 | another if it is not possible) hard register to new_p as to | |
74 | reload_p1 or reload_p2. | |
75 | ||
76 | If the assignment pass fails to assign a hard register to new_p, | |
77 | this file will undo the inheritance and restore the original code. | |
78 | This is because implementing the above sequence with a spilled | |
79 | new_p would make the code much worse. The inheritance is done in | |
80 | EBB scope. The above is just a simplified example to get an idea | |
81 | of the inheritance as the inheritance is also done for non-reload | |
82 | insns. | |
83 | ||
84 | Splitting (transformation) is also done in EBB scope on the same | |
85 | pass as the inheritance: | |
86 | ||
87 | r <- ... or ... <- r r <- ... or ... <- r | |
88 | ... s <- r (new insn -- save) | |
f4eafc30 | 89 | ... => |
55a2c322 VM |
90 | ... r <- s (new insn -- restore) |
91 | ... <- r ... <- r | |
92 | ||
93 | The *split pseudo* s is assigned to the hard register of the | |
94 | original pseudo or hard register r. | |
95 | ||
96 | Splitting is done: | |
97 | o In EBBs with high register pressure for global pseudos (living | |
98 | in at least 2 BBs) and assigned to hard registers when there | |
99 | are more one reloads needing the hard registers; | |
100 | o for pseudos needing save/restore code around calls. | |
101 | ||
102 | If the split pseudo still has the same hard register as the | |
103 | original pseudo after the subsequent assignment pass or the | |
104 | original pseudo was split, the opposite transformation is done on | |
105 | the same pass for undoing inheritance. */ | |
106 | ||
107 | #undef REG_OK_STRICT | |
108 | ||
109 | #include "config.h" | |
110 | #include "system.h" | |
111 | #include "coretypes.h" | |
c7131fb2 | 112 | #include "backend.h" |
957060b5 | 113 | #include "target.h" |
55a2c322 | 114 | #include "rtl.h" |
957060b5 AM |
115 | #include "tree.h" |
116 | #include "predict.h" | |
c7131fb2 | 117 | #include "df.h" |
55a2c322 | 118 | #include "tm_p.h" |
957060b5 AM |
119 | #include "expmed.h" |
120 | #include "optabs.h" | |
55a2c322 | 121 | #include "regs.h" |
957060b5 | 122 | #include "ira.h" |
55a2c322 VM |
123 | #include "recog.h" |
124 | #include "output.h" | |
125 | #include "addresses.h" | |
55a2c322 | 126 | #include "expr.h" |
60393bbc | 127 | #include "cfgrtl.h" |
55a2c322 | 128 | #include "rtl-error.h" |
fb8a0e40 | 129 | #include "params.h" |
c7131fb2 | 130 | #include "lra.h" |
55a2c322 | 131 | #include "lra-int.h" |
013a8899 | 132 | #include "print-rtl.h" |
55a2c322 VM |
133 | |
134 | /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current | |
135 | insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted | |
136 | reload insns. */ | |
137 | static int bb_reload_num; | |
138 | ||
2c62cbaa VM |
139 | /* The current insn being processed and corresponding its single set |
140 | (NULL otherwise), its data (basic block, the insn data, the insn | |
141 | static data, and the mode of each operand). */ | |
cfa434f6 | 142 | static rtx_insn *curr_insn; |
2c62cbaa | 143 | static rtx curr_insn_set; |
55a2c322 VM |
144 | static basic_block curr_bb; |
145 | static lra_insn_recog_data_t curr_id; | |
146 | static struct lra_static_insn_data *curr_static_id; | |
ef4bddc2 | 147 | static machine_mode curr_operand_mode[MAX_RECOG_OPERANDS]; |
895ff86f VM |
148 | /* Mode of the register substituted by its equivalence with VOIDmode |
149 | (e.g. constant) and whose subreg is given operand of the current | |
150 | insn. VOIDmode in all other cases. */ | |
151 | static machine_mode original_subreg_reg_mode[MAX_RECOG_OPERANDS]; | |
55a2c322 VM |
152 | |
153 | \f | |
154 | ||
155 | /* Start numbers for new registers and insns at the current constraints | |
156 | pass start. */ | |
157 | static int new_regno_start; | |
158 | static int new_insn_uid_start; | |
159 | ||
277f65de RS |
160 | /* If LOC is nonnull, strip any outer subreg from it. */ |
161 | static inline rtx * | |
162 | strip_subreg (rtx *loc) | |
163 | { | |
164 | return loc && GET_CODE (*loc) == SUBREG ? &SUBREG_REG (*loc) : loc; | |
165 | } | |
166 | ||
55a2c322 VM |
167 | /* Return hard regno of REGNO or if it is was not assigned to a hard |
168 | register, use a hard register from its allocno class. */ | |
169 | static int | |
170 | get_try_hard_regno (int regno) | |
171 | { | |
172 | int hard_regno; | |
173 | enum reg_class rclass; | |
174 | ||
175 | if ((hard_regno = regno) >= FIRST_PSEUDO_REGISTER) | |
176 | hard_regno = lra_get_regno_hard_regno (regno); | |
177 | if (hard_regno >= 0) | |
178 | return hard_regno; | |
179 | rclass = lra_get_allocno_class (regno); | |
180 | if (rclass == NO_REGS) | |
181 | return -1; | |
182 | return ira_class_hard_regs[rclass][0]; | |
183 | } | |
184 | ||
185 | /* Return final hard regno (plus offset) which will be after | |
186 | elimination. We do this for matching constraints because the final | |
187 | hard regno could have a different class. */ | |
188 | static int | |
189 | get_final_hard_regno (int hard_regno, int offset) | |
190 | { | |
191 | if (hard_regno < 0) | |
192 | return hard_regno; | |
193 | hard_regno = lra_get_elimination_hard_regno (hard_regno); | |
194 | return hard_regno + offset; | |
195 | } | |
196 | ||
197 | /* Return hard regno of X after removing subreg and making | |
198 | elimination. If X is not a register or subreg of register, return | |
199 | -1. For pseudo use its assignment. */ | |
200 | static int | |
201 | get_hard_regno (rtx x) | |
202 | { | |
203 | rtx reg; | |
204 | int offset, hard_regno; | |
205 | ||
206 | reg = x; | |
207 | if (GET_CODE (x) == SUBREG) | |
208 | reg = SUBREG_REG (x); | |
209 | if (! REG_P (reg)) | |
210 | return -1; | |
211 | if ((hard_regno = REGNO (reg)) >= FIRST_PSEUDO_REGISTER) | |
212 | hard_regno = lra_get_regno_hard_regno (hard_regno); | |
213 | if (hard_regno < 0) | |
214 | return -1; | |
215 | offset = 0; | |
216 | if (GET_CODE (x) == SUBREG) | |
217 | offset += subreg_regno_offset (hard_regno, GET_MODE (reg), | |
218 | SUBREG_BYTE (x), GET_MODE (x)); | |
219 | return get_final_hard_regno (hard_regno, offset); | |
220 | } | |
221 | ||
222 | /* If REGNO is a hard register or has been allocated a hard register, | |
223 | return the class of that register. If REGNO is a reload pseudo | |
224 | created by the current constraints pass, return its allocno class. | |
225 | Return NO_REGS otherwise. */ | |
226 | static enum reg_class | |
227 | get_reg_class (int regno) | |
228 | { | |
229 | int hard_regno; | |
230 | ||
231 | if ((hard_regno = regno) >= FIRST_PSEUDO_REGISTER) | |
232 | hard_regno = lra_get_regno_hard_regno (regno); | |
233 | if (hard_regno >= 0) | |
234 | { | |
235 | hard_regno = get_final_hard_regno (hard_regno, 0); | |
236 | return REGNO_REG_CLASS (hard_regno); | |
237 | } | |
238 | if (regno >= new_regno_start) | |
239 | return lra_get_allocno_class (regno); | |
240 | return NO_REGS; | |
241 | } | |
242 | ||
243 | /* Return true if REG satisfies (or will satisfy) reg class constraint | |
244 | CL. Use elimination first if REG is a hard register. If REG is a | |
245 | reload pseudo created by this constraints pass, assume that it will | |
246 | be allocated a hard register from its allocno class, but allow that | |
247 | class to be narrowed to CL if it is currently a superset of CL. | |
248 | ||
249 | If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of | |
250 | REGNO (reg), or NO_REGS if no change in its class was needed. */ | |
251 | static bool | |
252 | in_class_p (rtx reg, enum reg_class cl, enum reg_class *new_class) | |
253 | { | |
254 | enum reg_class rclass, common_class; | |
ef4bddc2 | 255 | machine_mode reg_mode; |
55a2c322 VM |
256 | int class_size, hard_regno, nregs, i, j; |
257 | int regno = REGNO (reg); | |
f4eafc30 | 258 | |
55a2c322 VM |
259 | if (new_class != NULL) |
260 | *new_class = NO_REGS; | |
261 | if (regno < FIRST_PSEUDO_REGISTER) | |
262 | { | |
263 | rtx final_reg = reg; | |
264 | rtx *final_loc = &final_reg; | |
f4eafc30 | 265 | |
55a2c322 VM |
266 | lra_eliminate_reg_if_possible (final_loc); |
267 | return TEST_HARD_REG_BIT (reg_class_contents[cl], REGNO (*final_loc)); | |
268 | } | |
269 | reg_mode = GET_MODE (reg); | |
270 | rclass = get_reg_class (regno); | |
271 | if (regno < new_regno_start | |
272 | /* Do not allow the constraints for reload instructions to | |
273 | influence the classes of new pseudos. These reloads are | |
274 | typically moves that have many alternatives, and restricting | |
275 | reload pseudos for one alternative may lead to situations | |
276 | where other reload pseudos are no longer allocatable. */ | |
a2d0d374 VM |
277 | || (INSN_UID (curr_insn) >= new_insn_uid_start |
278 | && curr_insn_set != NULL | |
58532ca6 VM |
279 | && ((OBJECT_P (SET_SRC (curr_insn_set)) |
280 | && ! CONSTANT_P (SET_SRC (curr_insn_set))) | |
a2d0d374 | 281 | || (GET_CODE (SET_SRC (curr_insn_set)) == SUBREG |
58532ca6 VM |
282 | && OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set))) |
283 | && ! CONSTANT_P (SUBREG_REG (SET_SRC (curr_insn_set))))))) | |
55a2c322 VM |
284 | /* When we don't know what class will be used finally for reload |
285 | pseudos, we use ALL_REGS. */ | |
286 | return ((regno >= new_regno_start && rclass == ALL_REGS) | |
287 | || (rclass != NO_REGS && ira_class_subset_p[rclass][cl] | |
288 | && ! hard_reg_set_subset_p (reg_class_contents[cl], | |
289 | lra_no_alloc_regs))); | |
290 | else | |
291 | { | |
292 | common_class = ira_reg_class_subset[rclass][cl]; | |
293 | if (new_class != NULL) | |
294 | *new_class = common_class; | |
295 | if (hard_reg_set_subset_p (reg_class_contents[common_class], | |
296 | lra_no_alloc_regs)) | |
297 | return false; | |
298 | /* Check that there are enough allocatable regs. */ | |
299 | class_size = ira_class_hard_regs_num[common_class]; | |
300 | for (i = 0; i < class_size; i++) | |
301 | { | |
302 | hard_regno = ira_class_hard_regs[common_class][i]; | |
303 | nregs = hard_regno_nregs[hard_regno][reg_mode]; | |
304 | if (nregs == 1) | |
305 | return true; | |
306 | for (j = 0; j < nregs; j++) | |
f421c426 VM |
307 | if (TEST_HARD_REG_BIT (lra_no_alloc_regs, hard_regno + j) |
308 | || ! TEST_HARD_REG_BIT (reg_class_contents[common_class], | |
309 | hard_regno + j)) | |
55a2c322 VM |
310 | break; |
311 | if (j >= nregs) | |
312 | return true; | |
313 | } | |
314 | return false; | |
315 | } | |
316 | } | |
317 | ||
318 | /* Return true if REGNO satisfies a memory constraint. */ | |
319 | static bool | |
320 | in_mem_p (int regno) | |
321 | { | |
322 | return get_reg_class (regno) == NO_REGS; | |
323 | } | |
324 | ||
a953491e RS |
325 | /* Return 1 if ADDR is a valid memory address for mode MODE in address |
326 | space AS, and check that each pseudo has the proper kind of hard | |
327 | reg. */ | |
328 | static int | |
ef4bddc2 | 329 | valid_address_p (machine_mode mode ATTRIBUTE_UNUSED, |
a953491e RS |
330 | rtx addr, addr_space_t as) |
331 | { | |
332 | #ifdef GO_IF_LEGITIMATE_ADDRESS | |
333 | lra_assert (ADDR_SPACE_GENERIC_P (as)); | |
334 | GO_IF_LEGITIMATE_ADDRESS (mode, addr, win); | |
335 | return 0; | |
336 | ||
337 | win: | |
338 | return 1; | |
339 | #else | |
340 | return targetm.addr_space.legitimate_address_p (mode, addr, 0, as); | |
341 | #endif | |
342 | } | |
343 | ||
344 | namespace { | |
345 | /* Temporarily eliminates registers in an address (for the lifetime of | |
346 | the object). */ | |
347 | class address_eliminator { | |
348 | public: | |
349 | address_eliminator (struct address_info *ad); | |
350 | ~address_eliminator (); | |
351 | ||
352 | private: | |
353 | struct address_info *m_ad; | |
354 | rtx *m_base_loc; | |
355 | rtx m_base_reg; | |
356 | rtx *m_index_loc; | |
357 | rtx m_index_reg; | |
358 | }; | |
359 | } | |
360 | ||
361 | address_eliminator::address_eliminator (struct address_info *ad) | |
362 | : m_ad (ad), | |
363 | m_base_loc (strip_subreg (ad->base_term)), | |
364 | m_base_reg (NULL_RTX), | |
365 | m_index_loc (strip_subreg (ad->index_term)), | |
366 | m_index_reg (NULL_RTX) | |
367 | { | |
368 | if (m_base_loc != NULL) | |
369 | { | |
370 | m_base_reg = *m_base_loc; | |
371 | lra_eliminate_reg_if_possible (m_base_loc); | |
372 | if (m_ad->base_term2 != NULL) | |
373 | *m_ad->base_term2 = *m_ad->base_term; | |
374 | } | |
375 | if (m_index_loc != NULL) | |
376 | { | |
377 | m_index_reg = *m_index_loc; | |
378 | lra_eliminate_reg_if_possible (m_index_loc); | |
379 | } | |
380 | } | |
381 | ||
382 | address_eliminator::~address_eliminator () | |
383 | { | |
384 | if (m_base_loc && *m_base_loc != m_base_reg) | |
385 | { | |
386 | *m_base_loc = m_base_reg; | |
387 | if (m_ad->base_term2 != NULL) | |
388 | *m_ad->base_term2 = *m_ad->base_term; | |
389 | } | |
390 | if (m_index_loc && *m_index_loc != m_index_reg) | |
391 | *m_index_loc = m_index_reg; | |
392 | } | |
393 | ||
394 | /* Return true if the eliminated form of AD is a legitimate target address. */ | |
395 | static bool | |
396 | valid_address_p (struct address_info *ad) | |
397 | { | |
398 | address_eliminator eliminator (ad); | |
399 | return valid_address_p (ad->mode, *ad->outer, ad->as); | |
400 | } | |
401 | ||
a953491e | 402 | /* Return true if the eliminated form of memory reference OP satisfies |
9eb1ca69 | 403 | extra (special) memory constraint CONSTRAINT. */ |
a953491e | 404 | static bool |
777e635f | 405 | satisfies_memory_constraint_p (rtx op, enum constraint_num constraint) |
a953491e RS |
406 | { |
407 | struct address_info ad; | |
408 | ||
409 | decompose_mem_address (&ad, op); | |
410 | address_eliminator eliminator (&ad); | |
777e635f | 411 | return constraint_satisfied_p (op, constraint); |
a953491e RS |
412 | } |
413 | ||
414 | /* Return true if the eliminated form of address AD satisfies extra | |
415 | address constraint CONSTRAINT. */ | |
416 | static bool | |
417 | satisfies_address_constraint_p (struct address_info *ad, | |
777e635f | 418 | enum constraint_num constraint) |
a953491e RS |
419 | { |
420 | address_eliminator eliminator (ad); | |
777e635f | 421 | return constraint_satisfied_p (*ad->outer, constraint); |
a953491e RS |
422 | } |
423 | ||
424 | /* Return true if the eliminated form of address OP satisfies extra | |
425 | address constraint CONSTRAINT. */ | |
426 | static bool | |
777e635f | 427 | satisfies_address_constraint_p (rtx op, enum constraint_num constraint) |
a953491e RS |
428 | { |
429 | struct address_info ad; | |
430 | ||
431 | decompose_lea_address (&ad, &op); | |
432 | return satisfies_address_constraint_p (&ad, constraint); | |
433 | } | |
a953491e | 434 | |
4c2b2d79 VM |
435 | /* Initiate equivalences for LRA. As we keep original equivalences |
436 | before any elimination, we need to make copies otherwise any change | |
437 | in insns might change the equivalences. */ | |
438 | void | |
439 | lra_init_equiv (void) | |
440 | { | |
441 | ira_expand_reg_equiv (); | |
442 | for (int i = FIRST_PSEUDO_REGISTER; i < max_reg_num (); i++) | |
443 | { | |
444 | rtx res; | |
445 | ||
446 | if ((res = ira_reg_equiv[i].memory) != NULL_RTX) | |
447 | ira_reg_equiv[i].memory = copy_rtx (res); | |
448 | if ((res = ira_reg_equiv[i].invariant) != NULL_RTX) | |
449 | ira_reg_equiv[i].invariant = copy_rtx (res); | |
450 | } | |
451 | } | |
452 | ||
453 | static rtx loc_equivalence_callback (rtx, const_rtx, void *); | |
454 | ||
455 | /* Update equivalence for REGNO. We need to this as the equivalence | |
456 | might contain other pseudos which are changed by their | |
457 | equivalences. */ | |
458 | static void | |
459 | update_equiv (int regno) | |
460 | { | |
461 | rtx x; | |
462 | ||
463 | if ((x = ira_reg_equiv[regno].memory) != NULL_RTX) | |
464 | ira_reg_equiv[regno].memory | |
465 | = simplify_replace_fn_rtx (x, NULL_RTX, loc_equivalence_callback, | |
466 | NULL_RTX); | |
467 | if ((x = ira_reg_equiv[regno].invariant) != NULL_RTX) | |
468 | ira_reg_equiv[regno].invariant | |
469 | = simplify_replace_fn_rtx (x, NULL_RTX, loc_equivalence_callback, | |
470 | NULL_RTX); | |
471 | } | |
472 | ||
55a2c322 VM |
473 | /* If we have decided to substitute X with another value, return that |
474 | value, otherwise return X. */ | |
475 | static rtx | |
8d49e7ef | 476 | get_equiv (rtx x) |
55a2c322 VM |
477 | { |
478 | int regno; | |
479 | rtx res; | |
480 | ||
481 | if (! REG_P (x) || (regno = REGNO (x)) < FIRST_PSEUDO_REGISTER | |
482 | || ! ira_reg_equiv[regno].defined_p | |
483 | || ! ira_reg_equiv[regno].profitable_p | |
484 | || lra_get_regno_hard_regno (regno) >= 0) | |
485 | return x; | |
486 | if ((res = ira_reg_equiv[regno].memory) != NULL_RTX) | |
d6220b11 KK |
487 | { |
488 | if (targetm.cannot_substitute_mem_equiv_p (res)) | |
489 | return x; | |
490 | return res; | |
491 | } | |
55a2c322 VM |
492 | if ((res = ira_reg_equiv[regno].constant) != NULL_RTX) |
493 | return res; | |
494 | if ((res = ira_reg_equiv[regno].invariant) != NULL_RTX) | |
495 | return res; | |
496 | gcc_unreachable (); | |
497 | } | |
498 | ||
8d49e7ef VM |
499 | /* If we have decided to substitute X with the equivalent value, |
500 | return that value after elimination for INSN, otherwise return | |
501 | X. */ | |
502 | static rtx | |
cfa434f6 | 503 | get_equiv_with_elimination (rtx x, rtx_insn *insn) |
8d49e7ef VM |
504 | { |
505 | rtx res = get_equiv (x); | |
506 | ||
507 | if (x == res || CONSTANT_P (res)) | |
508 | return res; | |
d9cf932c | 509 | return lra_eliminate_regs_1 (insn, res, GET_MODE (res), |
a6af1bf9 | 510 | false, false, 0, true); |
8d49e7ef VM |
511 | } |
512 | ||
55a2c322 VM |
513 | /* Set up curr_operand_mode. */ |
514 | static void | |
515 | init_curr_operand_mode (void) | |
516 | { | |
517 | int nop = curr_static_id->n_operands; | |
518 | for (int i = 0; i < nop; i++) | |
519 | { | |
ef4bddc2 | 520 | machine_mode mode = GET_MODE (*curr_id->operand_loc[i]); |
55a2c322 VM |
521 | if (mode == VOIDmode) |
522 | { | |
523 | /* The .md mode for address operands is the mode of the | |
524 | addressed value rather than the mode of the address itself. */ | |
525 | if (curr_id->icode >= 0 && curr_static_id->operand[i].is_address) | |
526 | mode = Pmode; | |
527 | else | |
528 | mode = curr_static_id->operand[i].mode; | |
529 | } | |
530 | curr_operand_mode[i] = mode; | |
531 | } | |
532 | } | |
533 | ||
534 | \f | |
535 | ||
536 | /* The page contains code to reuse input reloads. */ | |
537 | ||
538 | /* Structure describes input reload of the current insns. */ | |
539 | struct input_reload | |
540 | { | |
541 | /* Reloaded value. */ | |
542 | rtx input; | |
543 | /* Reload pseudo used. */ | |
544 | rtx reg; | |
545 | }; | |
546 | ||
547 | /* The number of elements in the following array. */ | |
548 | static int curr_insn_input_reloads_num; | |
549 | /* Array containing info about input reloads. It is used to find the | |
550 | same input reload and reuse the reload pseudo in this case. */ | |
551 | static struct input_reload curr_insn_input_reloads[LRA_MAX_INSN_RELOADS]; | |
552 | ||
553 | /* Initiate data concerning reuse of input reloads for the current | |
554 | insn. */ | |
555 | static void | |
556 | init_curr_insn_input_reloads (void) | |
557 | { | |
558 | curr_insn_input_reloads_num = 0; | |
559 | } | |
560 | ||
55a2c322 | 561 | /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already |
95921002 VM |
562 | created input reload pseudo (only if TYPE is not OP_OUT). Don't |
563 | reuse pseudo if IN_SUBREG_P is true and the reused pseudo should be | |
564 | wrapped up in SUBREG. The result pseudo is returned through | |
565 | RESULT_REG. Return TRUE if we created a new pseudo, FALSE if we | |
566 | reused the already created input reload pseudo. Use TITLE to | |
567 | describe new registers for debug purposes. */ | |
55a2c322 | 568 | static bool |
ef4bddc2 | 569 | get_reload_reg (enum op_type type, machine_mode mode, rtx original, |
95921002 VM |
570 | enum reg_class rclass, bool in_subreg_p, |
571 | const char *title, rtx *result_reg) | |
55a2c322 VM |
572 | { |
573 | int i, regno; | |
574 | enum reg_class new_class; | |
575 | ||
576 | if (type == OP_OUT) | |
577 | { | |
578 | *result_reg | |
579 | = lra_create_new_reg_with_unique_value (mode, original, rclass, title); | |
580 | return true; | |
581 | } | |
73cca0cc VM |
582 | /* Prevent reuse value of expression with side effects, |
583 | e.g. volatile memory. */ | |
584 | if (! side_effects_p (original)) | |
585 | for (i = 0; i < curr_insn_input_reloads_num; i++) | |
586 | if (rtx_equal_p (curr_insn_input_reloads[i].input, original) | |
587 | && in_class_p (curr_insn_input_reloads[i].reg, rclass, &new_class)) | |
588 | { | |
5df81313 JJ |
589 | rtx reg = curr_insn_input_reloads[i].reg; |
590 | regno = REGNO (reg); | |
591 | /* If input is equal to original and both are VOIDmode, | |
592 | GET_MODE (reg) might be still different from mode. | |
593 | Ensure we don't return *result_reg with wrong mode. */ | |
594 | if (GET_MODE (reg) != mode) | |
595 | { | |
95921002 VM |
596 | if (in_subreg_p) |
597 | continue; | |
5df81313 JJ |
598 | if (GET_MODE_SIZE (GET_MODE (reg)) < GET_MODE_SIZE (mode)) |
599 | continue; | |
600 | reg = lowpart_subreg (mode, reg, GET_MODE (reg)); | |
601 | if (reg == NULL_RTX || GET_CODE (reg) != SUBREG) | |
602 | continue; | |
603 | } | |
604 | *result_reg = reg; | |
73cca0cc VM |
605 | if (lra_dump_file != NULL) |
606 | { | |
607 | fprintf (lra_dump_file, " Reuse r%d for reload ", regno); | |
608 | dump_value_slim (lra_dump_file, original, 1); | |
609 | } | |
610 | if (new_class != lra_get_allocno_class (regno)) | |
a2d0d374 | 611 | lra_change_class (regno, new_class, ", change to", false); |
73cca0cc VM |
612 | if (lra_dump_file != NULL) |
613 | fprintf (lra_dump_file, "\n"); | |
614 | return false; | |
615 | } | |
55a2c322 VM |
616 | *result_reg = lra_create_new_reg (mode, original, rclass, title); |
617 | lra_assert (curr_insn_input_reloads_num < LRA_MAX_INSN_RELOADS); | |
618 | curr_insn_input_reloads[curr_insn_input_reloads_num].input = original; | |
619 | curr_insn_input_reloads[curr_insn_input_reloads_num++].reg = *result_reg; | |
620 | return true; | |
621 | } | |
622 | ||
623 | \f | |
624 | ||
625 | /* The page contains code to extract memory address parts. */ | |
626 | ||
55a2c322 VM |
627 | /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudos. */ |
628 | static inline bool | |
629 | ok_for_index_p_nonstrict (rtx reg) | |
630 | { | |
631 | unsigned regno = REGNO (reg); | |
f4eafc30 | 632 | |
55a2c322 VM |
633 | return regno >= FIRST_PSEUDO_REGISTER || REGNO_OK_FOR_INDEX_P (regno); |
634 | } | |
635 | ||
636 | /* A version of regno_ok_for_base_p for use here, when all pseudos | |
637 | should count as OK. Arguments as for regno_ok_for_base_p. */ | |
638 | static inline bool | |
ef4bddc2 | 639 | ok_for_base_p_nonstrict (rtx reg, machine_mode mode, addr_space_t as, |
55a2c322 VM |
640 | enum rtx_code outer_code, enum rtx_code index_code) |
641 | { | |
642 | unsigned regno = REGNO (reg); | |
643 | ||
644 | if (regno >= FIRST_PSEUDO_REGISTER) | |
645 | return true; | |
646 | return ok_for_base_p_1 (regno, mode, as, outer_code, index_code); | |
647 | } | |
648 | ||
55a2c322 VM |
649 | \f |
650 | ||
651 | /* The page contains major code to choose the current insn alternative | |
652 | and generate reloads for it. */ | |
653 | ||
654 | /* Return the offset from REGNO of the least significant register | |
655 | in (reg:MODE REGNO). | |
656 | ||
657 | This function is used to tell whether two registers satisfy | |
658 | a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if: | |
659 | ||
660 | REGNO1 + lra_constraint_offset (REGNO1, MODE1) | |
661 | == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */ | |
662 | int | |
ef4bddc2 | 663 | lra_constraint_offset (int regno, machine_mode mode) |
55a2c322 VM |
664 | { |
665 | lra_assert (regno < FIRST_PSEUDO_REGISTER); | |
666 | if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (mode) > UNITS_PER_WORD | |
667 | && SCALAR_INT_MODE_P (mode)) | |
668 | return hard_regno_nregs[regno][mode] - 1; | |
669 | return 0; | |
670 | } | |
671 | ||
672 | /* Like rtx_equal_p except that it allows a REG and a SUBREG to match | |
673 | if they are the same hard reg, and has special hacks for | |
674 | auto-increment and auto-decrement. This is specifically intended for | |
675 | process_alt_operands to use in determining whether two operands | |
676 | match. X is the operand whose number is the lower of the two. | |
677 | ||
678 | It is supposed that X is the output operand and Y is the input | |
679 | operand. Y_HARD_REGNO is the final hard regno of register Y or | |
680 | register in subreg Y as we know it now. Otherwise, it is a | |
681 | negative value. */ | |
682 | static bool | |
683 | operands_match_p (rtx x, rtx y, int y_hard_regno) | |
684 | { | |
685 | int i; | |
686 | RTX_CODE code = GET_CODE (x); | |
687 | const char *fmt; | |
688 | ||
689 | if (x == y) | |
690 | return true; | |
691 | if ((code == REG || (code == SUBREG && REG_P (SUBREG_REG (x)))) | |
692 | && (REG_P (y) || (GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y))))) | |
693 | { | |
694 | int j; | |
f4eafc30 | 695 | |
55a2c322 VM |
696 | i = get_hard_regno (x); |
697 | if (i < 0) | |
698 | goto slow; | |
699 | ||
700 | if ((j = y_hard_regno) < 0) | |
701 | goto slow; | |
702 | ||
703 | i += lra_constraint_offset (i, GET_MODE (x)); | |
704 | j += lra_constraint_offset (j, GET_MODE (y)); | |
705 | ||
706 | return i == j; | |
707 | } | |
708 | ||
709 | /* If two operands must match, because they are really a single | |
710 | operand of an assembler insn, then two post-increments are invalid | |
711 | because the assembler insn would increment only once. On the | |
712 | other hand, a post-increment matches ordinary indexing if the | |
713 | post-increment is the output operand. */ | |
714 | if (code == POST_DEC || code == POST_INC || code == POST_MODIFY) | |
715 | return operands_match_p (XEXP (x, 0), y, y_hard_regno); | |
716 | ||
717 | /* Two pre-increments are invalid because the assembler insn would | |
718 | increment only once. On the other hand, a pre-increment matches | |
719 | ordinary indexing if the pre-increment is the input operand. */ | |
720 | if (GET_CODE (y) == PRE_DEC || GET_CODE (y) == PRE_INC | |
721 | || GET_CODE (y) == PRE_MODIFY) | |
722 | return operands_match_p (x, XEXP (y, 0), -1); | |
f4eafc30 | 723 | |
55a2c322 VM |
724 | slow: |
725 | ||
9fccb335 RS |
726 | if (code == REG && REG_P (y)) |
727 | return REGNO (x) == REGNO (y); | |
728 | ||
55a2c322 VM |
729 | if (code == REG && GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y)) |
730 | && x == SUBREG_REG (y)) | |
731 | return true; | |
732 | if (GET_CODE (y) == REG && code == SUBREG && REG_P (SUBREG_REG (x)) | |
733 | && SUBREG_REG (x) == y) | |
734 | return true; | |
735 | ||
736 | /* Now we have disposed of all the cases in which different rtx | |
737 | codes can match. */ | |
738 | if (code != GET_CODE (y)) | |
739 | return false; | |
740 | ||
741 | /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */ | |
742 | if (GET_MODE (x) != GET_MODE (y)) | |
743 | return false; | |
744 | ||
745 | switch (code) | |
746 | { | |
747 | CASE_CONST_UNIQUE: | |
748 | return false; | |
749 | ||
750 | case LABEL_REF: | |
a827d9b1 | 751 | return LABEL_REF_LABEL (x) == LABEL_REF_LABEL (y); |
55a2c322 VM |
752 | case SYMBOL_REF: |
753 | return XSTR (x, 0) == XSTR (y, 0); | |
754 | ||
755 | default: | |
756 | break; | |
757 | } | |
758 | ||
759 | /* Compare the elements. If any pair of corresponding elements fail | |
760 | to match, return false for the whole things. */ | |
761 | ||
762 | fmt = GET_RTX_FORMAT (code); | |
763 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
764 | { | |
765 | int val, j; | |
766 | switch (fmt[i]) | |
767 | { | |
768 | case 'w': | |
769 | if (XWINT (x, i) != XWINT (y, i)) | |
770 | return false; | |
771 | break; | |
772 | ||
773 | case 'i': | |
774 | if (XINT (x, i) != XINT (y, i)) | |
775 | return false; | |
776 | break; | |
777 | ||
778 | case 'e': | |
779 | val = operands_match_p (XEXP (x, i), XEXP (y, i), -1); | |
780 | if (val == 0) | |
781 | return false; | |
782 | break; | |
783 | ||
784 | case '0': | |
785 | break; | |
786 | ||
787 | case 'E': | |
788 | if (XVECLEN (x, i) != XVECLEN (y, i)) | |
789 | return false; | |
790 | for (j = XVECLEN (x, i) - 1; j >= 0; --j) | |
791 | { | |
792 | val = operands_match_p (XVECEXP (x, i, j), XVECEXP (y, i, j), -1); | |
793 | if (val == 0) | |
794 | return false; | |
795 | } | |
796 | break; | |
797 | ||
798 | /* It is believed that rtx's at this level will never | |
799 | contain anything but integers and other rtx's, except for | |
800 | within LABEL_REFs and SYMBOL_REFs. */ | |
801 | default: | |
802 | gcc_unreachable (); | |
803 | } | |
804 | } | |
805 | return true; | |
806 | } | |
807 | ||
808 | /* True if X is a constant that can be forced into the constant pool. | |
809 | MODE is the mode of the operand, or VOIDmode if not known. */ | |
810 | #define CONST_POOL_OK_P(MODE, X) \ | |
811 | ((MODE) != VOIDmode \ | |
812 | && CONSTANT_P (X) \ | |
813 | && GET_CODE (X) != HIGH \ | |
814 | && !targetm.cannot_force_const_mem (MODE, X)) | |
815 | ||
816 | /* True if C is a non-empty register class that has too few registers | |
817 | to be safely used as a reload target class. */ | |
a9711f36 VM |
818 | #define SMALL_REGISTER_CLASS_P(C) \ |
819 | (ira_class_hard_regs_num [(C)] == 1 \ | |
820 | || (ira_class_hard_regs_num [(C)] >= 1 \ | |
821 | && targetm.class_likely_spilled_p (C))) | |
55a2c322 VM |
822 | |
823 | /* If REG is a reload pseudo, try to make its class satisfying CL. */ | |
824 | static void | |
825 | narrow_reload_pseudo_class (rtx reg, enum reg_class cl) | |
826 | { | |
827 | enum reg_class rclass; | |
828 | ||
829 | /* Do not make more accurate class from reloads generated. They are | |
830 | mostly moves with a lot of constraints. Making more accurate | |
831 | class may results in very narrow class and impossibility of find | |
832 | registers for several reloads of one insn. */ | |
833 | if (INSN_UID (curr_insn) >= new_insn_uid_start) | |
834 | return; | |
835 | if (GET_CODE (reg) == SUBREG) | |
836 | reg = SUBREG_REG (reg); | |
837 | if (! REG_P (reg) || (int) REGNO (reg) < new_regno_start) | |
838 | return; | |
839 | if (in_class_p (reg, cl, &rclass) && rclass != cl) | |
a2d0d374 | 840 | lra_change_class (REGNO (reg), rclass, " Change to", true); |
55a2c322 VM |
841 | } |
842 | ||
843 | /* Generate reloads for matching OUT and INS (array of input operand | |
844 | numbers with end marker -1) with reg class GOAL_CLASS. Add input | |
511dcace VM |
845 | and output reloads correspondingly to the lists *BEFORE and *AFTER. |
846 | OUT might be negative. In this case we generate input reloads for | |
599e1cf8 VM |
847 | matched input operands INS. EARLY_CLOBBER_P is a flag that the |
848 | output operand is early clobbered for chosen alternative. */ | |
55a2c322 VM |
849 | static void |
850 | match_reload (signed char out, signed char *ins, enum reg_class goal_class, | |
599e1cf8 | 851 | rtx_insn **before, rtx_insn **after, bool early_clobber_p) |
55a2c322 VM |
852 | { |
853 | int i, in; | |
e67d1102 | 854 | rtx new_in_reg, new_out_reg, reg; |
ef4bddc2 | 855 | machine_mode inmode, outmode; |
55a2c322 | 856 | rtx in_rtx = *curr_id->operand_loc[ins[0]]; |
511dcace | 857 | rtx out_rtx = out < 0 ? in_rtx : *curr_id->operand_loc[out]; |
55a2c322 | 858 | |
55a2c322 | 859 | inmode = curr_operand_mode[ins[0]]; |
511dcace | 860 | outmode = out < 0 ? inmode : curr_operand_mode[out]; |
55a2c322 VM |
861 | push_to_sequence (*before); |
862 | if (inmode != outmode) | |
863 | { | |
864 | if (GET_MODE_SIZE (inmode) > GET_MODE_SIZE (outmode)) | |
865 | { | |
866 | reg = new_in_reg | |
867 | = lra_create_new_reg_with_unique_value (inmode, in_rtx, | |
868 | goal_class, ""); | |
869 | if (SCALAR_INT_MODE_P (inmode)) | |
870 | new_out_reg = gen_lowpart_SUBREG (outmode, reg); | |
871 | else | |
872 | new_out_reg = gen_rtx_SUBREG (outmode, reg, 0); | |
2c62cbaa | 873 | LRA_SUBREG_P (new_out_reg) = 1; |
350c0fe7 | 874 | /* If the input reg is dying here, we can use the same hard |
f681cf95 VM |
875 | register for REG and IN_RTX. We do it only for original |
876 | pseudos as reload pseudos can die although original | |
877 | pseudos still live where reload pseudos dies. */ | |
878 | if (REG_P (in_rtx) && (int) REGNO (in_rtx) < lra_new_regno_start | |
350c0fe7 | 879 | && find_regno_note (curr_insn, REG_DEAD, REGNO (in_rtx))) |
d70a81dd | 880 | lra_assign_reg_val (REGNO (in_rtx), REGNO (reg)); |
55a2c322 VM |
881 | } |
882 | else | |
883 | { | |
884 | reg = new_out_reg | |
885 | = lra_create_new_reg_with_unique_value (outmode, out_rtx, | |
886 | goal_class, ""); | |
887 | if (SCALAR_INT_MODE_P (outmode)) | |
888 | new_in_reg = gen_lowpart_SUBREG (inmode, reg); | |
889 | else | |
890 | new_in_reg = gen_rtx_SUBREG (inmode, reg, 0); | |
891 | /* NEW_IN_REG is non-paradoxical subreg. We don't want | |
892 | NEW_OUT_REG living above. We add clobber clause for | |
c5cd5a7e VM |
893 | this. This is just a temporary clobber. We can remove |
894 | it at the end of LRA work. */ | |
e67d1102 | 895 | rtx_insn *clobber = emit_clobber (new_out_reg); |
c5cd5a7e | 896 | LRA_TEMP_CLOBBER_P (PATTERN (clobber)) = 1; |
2c62cbaa | 897 | LRA_SUBREG_P (new_in_reg) = 1; |
350c0fe7 VM |
898 | if (GET_CODE (in_rtx) == SUBREG) |
899 | { | |
900 | rtx subreg_reg = SUBREG_REG (in_rtx); | |
901 | ||
902 | /* If SUBREG_REG is dying here and sub-registers IN_RTX | |
903 | and NEW_IN_REG are similar, we can use the same hard | |
904 | register for REG and SUBREG_REG. */ | |
f681cf95 VM |
905 | if (REG_P (subreg_reg) |
906 | && (int) REGNO (subreg_reg) < lra_new_regno_start | |
907 | && GET_MODE (subreg_reg) == outmode | |
350c0fe7 VM |
908 | && SUBREG_BYTE (in_rtx) == SUBREG_BYTE (new_in_reg) |
909 | && find_regno_note (curr_insn, REG_DEAD, REGNO (subreg_reg))) | |
d70a81dd | 910 | lra_assign_reg_val (REGNO (subreg_reg), REGNO (reg)); |
350c0fe7 | 911 | } |
55a2c322 VM |
912 | } |
913 | } | |
914 | else | |
915 | { | |
916 | /* Pseudos have values -- see comments for lra_reg_info. | |
917 | Different pseudos with the same value do not conflict even if | |
918 | they live in the same place. When we create a pseudo we | |
919 | assign value of original pseudo (if any) from which we | |
920 | created the new pseudo. If we create the pseudo from the | |
3363daad VM |
921 | input pseudo, the new pseudo will have no conflict with the |
922 | input pseudo which is wrong when the input pseudo lives after | |
923 | the insn and as the new pseudo value is changed by the insn | |
924 | output. Therefore we create the new pseudo from the output | |
925 | except the case when we have single matched dying input | |
926 | pseudo. | |
f4eafc30 | 927 | |
55a2c322 VM |
928 | We cannot reuse the current output register because we might |
929 | have a situation like "a <- a op b", where the constraints | |
930 | force the second input operand ("b") to match the output | |
931 | operand ("a"). "b" must then be copied into a new register | |
599e1cf8 VM |
932 | so that it doesn't clobber the current value of "a". |
933 | ||
934 | We can not use the same value if the output pseudo is | |
935 | early clobbered or the input pseudo is mentioned in the | |
936 | output, e.g. as an address part in memory, because | |
937 | output reload will actually extend the pseudo liveness. | |
938 | We don't care about eliminable hard regs here as we are | |
939 | interesting only in pseudos. */ | |
f4eafc30 | 940 | |
55a2c322 | 941 | new_in_reg = new_out_reg |
599e1cf8 | 942 | = (! early_clobber_p && ins[1] < 0 && REG_P (in_rtx) |
3363daad VM |
943 | && (int) REGNO (in_rtx) < lra_new_regno_start |
944 | && find_regno_note (curr_insn, REG_DEAD, REGNO (in_rtx)) | |
c9561e7b | 945 | && (out < 0 || regno_use_in (REGNO (in_rtx), out_rtx) == NULL_RTX) |
3363daad VM |
946 | ? lra_create_new_reg (inmode, in_rtx, goal_class, "") |
947 | : lra_create_new_reg_with_unique_value (outmode, out_rtx, | |
948 | goal_class, "")); | |
55a2c322 | 949 | } |
511dcace VM |
950 | /* In operand can be got from transformations before processing insn |
951 | constraints. One example of such transformations is subreg | |
952 | reloading (see function simplify_operand_subreg). The new | |
953 | pseudos created by the transformations might have inaccurate | |
55a2c322 VM |
954 | class (ALL_REGS) and we should make their classes more |
955 | accurate. */ | |
956 | narrow_reload_pseudo_class (in_rtx, goal_class); | |
55a2c322 VM |
957 | lra_emit_move (copy_rtx (new_in_reg), in_rtx); |
958 | *before = get_insns (); | |
959 | end_sequence (); | |
960 | for (i = 0; (in = ins[i]) >= 0; i++) | |
961 | { | |
962 | lra_assert | |
963 | (GET_MODE (*curr_id->operand_loc[in]) == VOIDmode | |
964 | || GET_MODE (new_in_reg) == GET_MODE (*curr_id->operand_loc[in])); | |
965 | *curr_id->operand_loc[in] = new_in_reg; | |
966 | } | |
967 | lra_update_dups (curr_id, ins); | |
511dcace VM |
968 | if (out < 0) |
969 | return; | |
970 | /* See a comment for the input operand above. */ | |
971 | narrow_reload_pseudo_class (out_rtx, goal_class); | |
55a2c322 VM |
972 | if (find_reg_note (curr_insn, REG_UNUSED, out_rtx) == NULL_RTX) |
973 | { | |
974 | start_sequence (); | |
975 | lra_emit_move (out_rtx, copy_rtx (new_out_reg)); | |
976 | emit_insn (*after); | |
977 | *after = get_insns (); | |
978 | end_sequence (); | |
979 | } | |
980 | *curr_id->operand_loc[out] = new_out_reg; | |
981 | lra_update_dup (curr_id, out); | |
982 | } | |
983 | ||
984 | /* Return register class which is union of all reg classes in insn | |
985 | constraint alternative string starting with P. */ | |
986 | static enum reg_class | |
987 | reg_class_from_constraints (const char *p) | |
988 | { | |
989 | int c, len; | |
990 | enum reg_class op_class = NO_REGS; | |
991 | ||
992 | do | |
993 | switch ((c = *p, len = CONSTRAINT_LEN (c, p)), c) | |
994 | { | |
995 | case '#': | |
996 | case ',': | |
997 | return op_class; | |
998 | ||
55a2c322 | 999 | case 'g': |
55a2c322 VM |
1000 | op_class = reg_class_subunion[op_class][GENERAL_REGS]; |
1001 | break; | |
f4eafc30 | 1002 | |
55a2c322 | 1003 | default: |
777e635f RS |
1004 | enum constraint_num cn = lookup_constraint (p); |
1005 | enum reg_class cl = reg_class_for_constraint (cn); | |
1006 | if (cl == NO_REGS) | |
55a2c322 | 1007 | { |
777e635f | 1008 | if (insn_extra_address_constraint (cn)) |
55a2c322 VM |
1009 | op_class |
1010 | = (reg_class_subunion | |
1011 | [op_class][base_reg_class (VOIDmode, ADDR_SPACE_GENERIC, | |
1012 | ADDRESS, SCRATCH)]); | |
55a2c322 VM |
1013 | break; |
1014 | } | |
f4eafc30 | 1015 | |
777e635f RS |
1016 | op_class = reg_class_subunion[op_class][cl]; |
1017 | break; | |
55a2c322 VM |
1018 | } |
1019 | while ((p += len), c); | |
1020 | return op_class; | |
1021 | } | |
1022 | ||
1023 | /* If OP is a register, return the class of the register as per | |
1024 | get_reg_class, otherwise return NO_REGS. */ | |
1025 | static inline enum reg_class | |
1026 | get_op_class (rtx op) | |
1027 | { | |
1028 | return REG_P (op) ? get_reg_class (REGNO (op)) : NO_REGS; | |
1029 | } | |
1030 | ||
1031 | /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo | |
1032 | otherwise. If modes of MEM_PSEUDO and VAL are different, use | |
1033 | SUBREG for VAL to make them equal. */ | |
cfa434f6 | 1034 | static rtx_insn * |
55a2c322 VM |
1035 | emit_spill_move (bool to_p, rtx mem_pseudo, rtx val) |
1036 | { | |
1037 | if (GET_MODE (mem_pseudo) != GET_MODE (val)) | |
2c62cbaa | 1038 | { |
cb1cca12 VM |
1039 | /* Usually size of mem_pseudo is greater than val size but in |
1040 | rare cases it can be less as it can be defined by target | |
1041 | dependent macro HARD_REGNO_CALLER_SAVE_MODE. */ | |
1ccd4874 VM |
1042 | if (! MEM_P (val)) |
1043 | { | |
1044 | val = gen_rtx_SUBREG (GET_MODE (mem_pseudo), | |
1045 | GET_CODE (val) == SUBREG ? SUBREG_REG (val) : val, | |
1046 | 0); | |
1047 | LRA_SUBREG_P (val) = 1; | |
1048 | } | |
1049 | else | |
1050 | { | |
1051 | mem_pseudo = gen_lowpart_SUBREG (GET_MODE (val), mem_pseudo); | |
1052 | LRA_SUBREG_P (mem_pseudo) = 1; | |
1053 | } | |
2c62cbaa | 1054 | } |
1476d1bd MM |
1055 | return to_p ? gen_move_insn (mem_pseudo, val) |
1056 | : gen_move_insn (val, mem_pseudo); | |
55a2c322 VM |
1057 | } |
1058 | ||
1059 | /* Process a special case insn (register move), return true if we | |
2c62cbaa VM |
1060 | don't need to process it anymore. INSN should be a single set |
1061 | insn. Set up that RTL was changed through CHANGE_P and macro | |
1062 | SECONDARY_MEMORY_NEEDED says to use secondary memory through | |
1063 | SEC_MEM_P. */ | |
55a2c322 | 1064 | static bool |
2c62cbaa | 1065 | check_and_process_move (bool *change_p, bool *sec_mem_p ATTRIBUTE_UNUSED) |
55a2c322 VM |
1066 | { |
1067 | int sregno, dregno; | |
ef0006eb | 1068 | rtx dest, src, dreg, sreg, new_reg, scratch_reg; |
cfa434f6 | 1069 | rtx_insn *before; |
55a2c322 | 1070 | enum reg_class dclass, sclass, secondary_class; |
55a2c322 VM |
1071 | secondary_reload_info sri; |
1072 | ||
2c62cbaa VM |
1073 | lra_assert (curr_insn_set != NULL_RTX); |
1074 | dreg = dest = SET_DEST (curr_insn_set); | |
1075 | sreg = src = SET_SRC (curr_insn_set); | |
55a2c322 VM |
1076 | if (GET_CODE (dest) == SUBREG) |
1077 | dreg = SUBREG_REG (dest); | |
1078 | if (GET_CODE (src) == SUBREG) | |
1079 | sreg = SUBREG_REG (src); | |
1ccd4874 | 1080 | if (! (REG_P (dreg) || MEM_P (dreg)) || ! (REG_P (sreg) || MEM_P (sreg))) |
55a2c322 VM |
1081 | return false; |
1082 | sclass = dclass = NO_REGS; | |
55a2c322 VM |
1083 | if (REG_P (dreg)) |
1084 | dclass = get_reg_class (REGNO (dreg)); | |
1085 | if (dclass == ALL_REGS) | |
1086 | /* ALL_REGS is used for new pseudos created by transformations | |
1087 | like reload of SUBREG_REG (see function | |
1088 | simplify_operand_subreg). We don't know their class yet. We | |
1089 | should figure out the class from processing the insn | |
1090 | constraints not in this fast path function. Even if ALL_REGS | |
1091 | were a right class for the pseudo, secondary_... hooks usually | |
1092 | are not define for ALL_REGS. */ | |
1093 | return false; | |
55a2c322 VM |
1094 | if (REG_P (sreg)) |
1095 | sclass = get_reg_class (REGNO (sreg)); | |
1096 | if (sclass == ALL_REGS) | |
1097 | /* See comments above. */ | |
1098 | return false; | |
1ccd4874 VM |
1099 | if (sclass == NO_REGS && dclass == NO_REGS) |
1100 | return false; | |
55a2c322 | 1101 | #ifdef SECONDARY_MEMORY_NEEDED |
1ccd4874 VM |
1102 | if (SECONDARY_MEMORY_NEEDED (sclass, dclass, GET_MODE (src)) |
1103 | #ifdef SECONDARY_MEMORY_NEEDED_MODE | |
1104 | && ((sclass != NO_REGS && dclass != NO_REGS) | |
1105 | || GET_MODE (src) != SECONDARY_MEMORY_NEEDED_MODE (GET_MODE (src))) | |
1106 | #endif | |
1107 | ) | |
55a2c322 VM |
1108 | { |
1109 | *sec_mem_p = true; | |
1110 | return false; | |
1111 | } | |
1112 | #endif | |
1ccd4874 VM |
1113 | if (! REG_P (dreg) || ! REG_P (sreg)) |
1114 | return false; | |
55a2c322 VM |
1115 | sri.prev_sri = NULL; |
1116 | sri.icode = CODE_FOR_nothing; | |
1117 | sri.extra_cost = 0; | |
1118 | secondary_class = NO_REGS; | |
1119 | /* Set up hard register for a reload pseudo for hook | |
1120 | secondary_reload because some targets just ignore unassigned | |
1121 | pseudos in the hook. */ | |
1122 | if (dclass != NO_REGS && lra_get_regno_hard_regno (REGNO (dreg)) < 0) | |
1123 | { | |
1124 | dregno = REGNO (dreg); | |
1125 | reg_renumber[dregno] = ira_class_hard_regs[dclass][0]; | |
1126 | } | |
1127 | else | |
1128 | dregno = -1; | |
1129 | if (sclass != NO_REGS && lra_get_regno_hard_regno (REGNO (sreg)) < 0) | |
1130 | { | |
1131 | sregno = REGNO (sreg); | |
1132 | reg_renumber[sregno] = ira_class_hard_regs[sclass][0]; | |
1133 | } | |
1134 | else | |
1135 | sregno = -1; | |
1136 | if (sclass != NO_REGS) | |
1137 | secondary_class | |
1138 | = (enum reg_class) targetm.secondary_reload (false, dest, | |
1139 | (reg_class_t) sclass, | |
1140 | GET_MODE (src), &sri); | |
1141 | if (sclass == NO_REGS | |
1142 | || ((secondary_class != NO_REGS || sri.icode != CODE_FOR_nothing) | |
1143 | && dclass != NO_REGS)) | |
1144 | { | |
55a2c322 VM |
1145 | enum reg_class old_sclass = secondary_class; |
1146 | secondary_reload_info old_sri = sri; | |
55a2c322 VM |
1147 | |
1148 | sri.prev_sri = NULL; | |
1149 | sri.icode = CODE_FOR_nothing; | |
1150 | sri.extra_cost = 0; | |
1151 | secondary_class | |
ef0006eb | 1152 | = (enum reg_class) targetm.secondary_reload (true, src, |
55a2c322 | 1153 | (reg_class_t) dclass, |
ef0006eb | 1154 | GET_MODE (src), &sri); |
55a2c322 VM |
1155 | /* Check the target hook consistency. */ |
1156 | lra_assert | |
1157 | ((secondary_class == NO_REGS && sri.icode == CODE_FOR_nothing) | |
1158 | || (old_sclass == NO_REGS && old_sri.icode == CODE_FOR_nothing) | |
1159 | || (secondary_class == old_sclass && sri.icode == old_sri.icode)); | |
1160 | } | |
1161 | if (sregno >= 0) | |
1162 | reg_renumber [sregno] = -1; | |
1163 | if (dregno >= 0) | |
1164 | reg_renumber [dregno] = -1; | |
1165 | if (secondary_class == NO_REGS && sri.icode == CODE_FOR_nothing) | |
1166 | return false; | |
1167 | *change_p = true; | |
1168 | new_reg = NULL_RTX; | |
1169 | if (secondary_class != NO_REGS) | |
ef0006eb | 1170 | new_reg = lra_create_new_reg_with_unique_value (GET_MODE (src), NULL_RTX, |
55a2c322 VM |
1171 | secondary_class, |
1172 | "secondary"); | |
1173 | start_sequence (); | |
55a2c322 | 1174 | if (sri.icode == CODE_FOR_nothing) |
ef0006eb | 1175 | lra_emit_move (new_reg, src); |
55a2c322 VM |
1176 | else |
1177 | { | |
1178 | enum reg_class scratch_class; | |
1179 | ||
1180 | scratch_class = (reg_class_from_constraints | |
1181 | (insn_data[sri.icode].operand[2].constraint)); | |
1182 | scratch_reg = (lra_create_new_reg_with_unique_value | |
1183 | (insn_data[sri.icode].operand[2].mode, NULL_RTX, | |
1184 | scratch_class, "scratch")); | |
1185 | emit_insn (GEN_FCN (sri.icode) (new_reg != NULL_RTX ? new_reg : dest, | |
ef0006eb | 1186 | src, scratch_reg)); |
55a2c322 VM |
1187 | } |
1188 | before = get_insns (); | |
1189 | end_sequence (); | |
cfa434f6 | 1190 | lra_process_new_insns (curr_insn, before, NULL, "Inserting the move"); |
55a2c322 | 1191 | if (new_reg != NULL_RTX) |
ef0006eb | 1192 | SET_SRC (curr_insn_set) = new_reg; |
55a2c322 VM |
1193 | else |
1194 | { | |
1195 | if (lra_dump_file != NULL) | |
1196 | { | |
1197 | fprintf (lra_dump_file, "Deleting move %u\n", INSN_UID (curr_insn)); | |
cfbeaedf | 1198 | dump_insn_slim (lra_dump_file, curr_insn); |
55a2c322 VM |
1199 | } |
1200 | lra_set_insn_deleted (curr_insn); | |
1201 | return true; | |
1202 | } | |
1203 | return false; | |
1204 | } | |
1205 | ||
1206 | /* The following data describe the result of process_alt_operands. | |
1207 | The data are used in curr_insn_transform to generate reloads. */ | |
1208 | ||
1209 | /* The chosen reg classes which should be used for the corresponding | |
1210 | operands. */ | |
1211 | static enum reg_class goal_alt[MAX_RECOG_OPERANDS]; | |
1212 | /* True if the operand should be the same as another operand and that | |
1213 | other operand does not need a reload. */ | |
1214 | static bool goal_alt_match_win[MAX_RECOG_OPERANDS]; | |
1215 | /* True if the operand does not need a reload. */ | |
1216 | static bool goal_alt_win[MAX_RECOG_OPERANDS]; | |
1217 | /* True if the operand can be offsetable memory. */ | |
1218 | static bool goal_alt_offmemok[MAX_RECOG_OPERANDS]; | |
1219 | /* The number of an operand to which given operand can be matched to. */ | |
1220 | static int goal_alt_matches[MAX_RECOG_OPERANDS]; | |
1221 | /* The number of elements in the following array. */ | |
1222 | static int goal_alt_dont_inherit_ops_num; | |
1223 | /* Numbers of operands whose reload pseudos should not be inherited. */ | |
1224 | static int goal_alt_dont_inherit_ops[MAX_RECOG_OPERANDS]; | |
1225 | /* True if the insn commutative operands should be swapped. */ | |
1226 | static bool goal_alt_swapped; | |
1227 | /* The chosen insn alternative. */ | |
1228 | static int goal_alt_number; | |
1229 | ||
1230 | /* The following five variables are used to choose the best insn | |
1231 | alternative. They reflect final characteristics of the best | |
1232 | alternative. */ | |
1233 | ||
1234 | /* Number of necessary reloads and overall cost reflecting the | |
1235 | previous value and other unpleasantness of the best alternative. */ | |
1236 | static int best_losers, best_overall; | |
55a2c322 VM |
1237 | /* Overall number hard registers used for reloads. For example, on |
1238 | some targets we need 2 general registers to reload DFmode and only | |
1239 | one floating point register. */ | |
1240 | static int best_reload_nregs; | |
1241 | /* Overall number reflecting distances of previous reloading the same | |
1242 | value. The distances are counted from the current BB start. It is | |
1243 | used to improve inheritance chances. */ | |
1244 | static int best_reload_sum; | |
1245 | ||
1246 | /* True if the current insn should have no correspondingly input or | |
1247 | output reloads. */ | |
1248 | static bool no_input_reloads_p, no_output_reloads_p; | |
1249 | ||
1250 | /* True if we swapped the commutative operands in the current | |
1251 | insn. */ | |
1252 | static int curr_swapped; | |
1253 | ||
d9cf932c VM |
1254 | /* if CHECK_ONLY_P is false, arrange for address element *LOC to be a |
1255 | register of class CL. Add any input reloads to list BEFORE. AFTER | |
1256 | is nonnull if *LOC is an automodified value; handle that case by | |
1257 | adding the required output reloads to list AFTER. Return true if | |
1258 | the RTL was changed. | |
1259 | ||
1260 | if CHECK_ONLY_P is true, check that the *LOC is a correct address | |
1261 | register. Return false if the address register is correct. */ | |
55a2c322 | 1262 | static bool |
d9cf932c | 1263 | process_addr_reg (rtx *loc, bool check_only_p, rtx_insn **before, rtx_insn **after, |
cfa434f6 | 1264 | enum reg_class cl) |
55a2c322 VM |
1265 | { |
1266 | int regno; | |
1267 | enum reg_class rclass, new_class; | |
277f65de | 1268 | rtx reg; |
55a2c322 | 1269 | rtx new_reg; |
ef4bddc2 | 1270 | machine_mode mode; |
95921002 | 1271 | bool subreg_p, before_p = false; |
55a2c322 | 1272 | |
95921002 VM |
1273 | subreg_p = GET_CODE (*loc) == SUBREG; |
1274 | if (subreg_p) | |
1275 | loc = &SUBREG_REG (*loc); | |
277f65de | 1276 | reg = *loc; |
55a2c322 VM |
1277 | mode = GET_MODE (reg); |
1278 | if (! REG_P (reg)) | |
1279 | { | |
d9cf932c VM |
1280 | if (check_only_p) |
1281 | return true; | |
55a2c322 VM |
1282 | /* Always reload memory in an address even if the target supports |
1283 | such addresses. */ | |
1284 | new_reg = lra_create_new_reg_with_unique_value (mode, reg, cl, "address"); | |
1285 | before_p = true; | |
1286 | } | |
1287 | else | |
1288 | { | |
1289 | regno = REGNO (reg); | |
1290 | rclass = get_reg_class (regno); | |
d9cf932c VM |
1291 | if (! check_only_p |
1292 | && (*loc = get_equiv_with_elimination (reg, curr_insn)) != reg) | |
55a2c322 VM |
1293 | { |
1294 | if (lra_dump_file != NULL) | |
1295 | { | |
1296 | fprintf (lra_dump_file, | |
1297 | "Changing pseudo %d in address of insn %u on equiv ", | |
1298 | REGNO (reg), INSN_UID (curr_insn)); | |
cfbeaedf | 1299 | dump_value_slim (lra_dump_file, *loc, 1); |
55a2c322 VM |
1300 | fprintf (lra_dump_file, "\n"); |
1301 | } | |
1302 | *loc = copy_rtx (*loc); | |
1303 | } | |
1304 | if (*loc != reg || ! in_class_p (reg, cl, &new_class)) | |
1305 | { | |
d9cf932c VM |
1306 | if (check_only_p) |
1307 | return true; | |
55a2c322 VM |
1308 | reg = *loc; |
1309 | if (get_reload_reg (after == NULL ? OP_IN : OP_INOUT, | |
95921002 | 1310 | mode, reg, cl, subreg_p, "address", &new_reg)) |
55a2c322 VM |
1311 | before_p = true; |
1312 | } | |
1313 | else if (new_class != NO_REGS && rclass != new_class) | |
1314 | { | |
d9cf932c VM |
1315 | if (check_only_p) |
1316 | return true; | |
a2d0d374 | 1317 | lra_change_class (regno, new_class, " Change to", true); |
55a2c322 VM |
1318 | return false; |
1319 | } | |
1320 | else | |
1321 | return false; | |
1322 | } | |
1323 | if (before_p) | |
1324 | { | |
1325 | push_to_sequence (*before); | |
1326 | lra_emit_move (new_reg, reg); | |
1327 | *before = get_insns (); | |
1328 | end_sequence (); | |
1329 | } | |
1330 | *loc = new_reg; | |
1331 | if (after != NULL) | |
1332 | { | |
1333 | start_sequence (); | |
9a9fe2b4 | 1334 | lra_emit_move (before_p ? copy_rtx (reg) : reg, new_reg); |
55a2c322 VM |
1335 | emit_insn (*after); |
1336 | *after = get_insns (); | |
1337 | end_sequence (); | |
1338 | } | |
1339 | return true; | |
1340 | } | |
1341 | ||
4f0bee4c WM |
1342 | /* Insert move insn in simplify_operand_subreg. BEFORE returns |
1343 | the insn to be inserted before curr insn. AFTER returns the | |
1344 | the insn to be inserted after curr insn. ORIGREG and NEWREG | |
1345 | are the original reg and new reg for reload. */ | |
1346 | static void | |
cfa434f6 DM |
1347 | insert_move_for_subreg (rtx_insn **before, rtx_insn **after, rtx origreg, |
1348 | rtx newreg) | |
4f0bee4c WM |
1349 | { |
1350 | if (before) | |
1351 | { | |
1352 | push_to_sequence (*before); | |
1353 | lra_emit_move (newreg, origreg); | |
1354 | *before = get_insns (); | |
1355 | end_sequence (); | |
1356 | } | |
1357 | if (after) | |
1358 | { | |
1359 | start_sequence (); | |
1360 | lra_emit_move (origreg, newreg); | |
1361 | emit_insn (*after); | |
1362 | *after = get_insns (); | |
1363 | end_sequence (); | |
1364 | } | |
1365 | } | |
1366 | ||
ef4bddc2 | 1367 | static int valid_address_p (machine_mode mode, rtx addr, addr_space_t as); |
ba38538f | 1368 | |
55a2c322 VM |
1369 | /* Make reloads for subreg in operand NOP with internal subreg mode |
1370 | REG_MODE, add new reloads for further processing. Return true if | |
895ff86f | 1371 | any change was done. */ |
55a2c322 | 1372 | static bool |
ef4bddc2 | 1373 | simplify_operand_subreg (int nop, machine_mode reg_mode) |
55a2c322 VM |
1374 | { |
1375 | int hard_regno; | |
cfa434f6 | 1376 | rtx_insn *before, *after; |
895ff86f | 1377 | machine_mode mode, innermode; |
55a2c322 VM |
1378 | rtx reg, new_reg; |
1379 | rtx operand = *curr_id->operand_loc[nop]; | |
4f0bee4c WM |
1380 | enum reg_class regclass; |
1381 | enum op_type type; | |
55a2c322 | 1382 | |
cfa434f6 | 1383 | before = after = NULL; |
55a2c322 VM |
1384 | |
1385 | if (GET_CODE (operand) != SUBREG) | |
1386 | return false; | |
f4eafc30 | 1387 | |
55a2c322 VM |
1388 | mode = GET_MODE (operand); |
1389 | reg = SUBREG_REG (operand); | |
895ff86f | 1390 | innermode = GET_MODE (reg); |
4f0bee4c | 1391 | type = curr_static_id->operand[nop].type; |
55a2c322 VM |
1392 | /* If we change address for paradoxical subreg of memory, the |
1393 | address might violate the necessary alignment or the access might | |
b28ece32 VM |
1394 | be slow. So take this into consideration. We should not worry |
1395 | about access beyond allocated memory for paradoxical memory | |
1396 | subregs as we don't substitute such equiv memory (see processing | |
1397 | equivalences in function lra_constraints) and because for spilled | |
1398 | pseudos we allocate stack memory enough for the biggest | |
1399 | corresponding paradoxical subreg. */ | |
ba38538f VM |
1400 | if (MEM_P (reg) |
1401 | && (! SLOW_UNALIGNED_ACCESS (mode, MEM_ALIGN (reg)) | |
1402 | || MEM_ALIGN (reg) >= GET_MODE_ALIGNMENT (mode))) | |
1403 | { | |
1404 | rtx subst, old = *curr_id->operand_loc[nop]; | |
1405 | ||
1406 | alter_subreg (curr_id->operand_loc[nop], false); | |
1407 | subst = *curr_id->operand_loc[nop]; | |
1408 | lra_assert (MEM_P (subst)); | |
895ff86f | 1409 | if (! valid_address_p (innermode, XEXP (reg, 0), |
ba38538f VM |
1410 | MEM_ADDR_SPACE (reg)) |
1411 | || valid_address_p (GET_MODE (subst), XEXP (subst, 0), | |
1412 | MEM_ADDR_SPACE (subst))) | |
1413 | return true; | |
95831c01 VM |
1414 | else if ((get_constraint_type (lookup_constraint |
1415 | (curr_static_id->operand[nop].constraint)) | |
1416 | != CT_SPECIAL_MEMORY) | |
1417 | /* We still can reload address and if the address is | |
1418 | valid, we can remove subreg without reloading its | |
1419 | inner memory. */ | |
1420 | && valid_address_p (GET_MODE (subst), | |
1421 | regno_reg_rtx | |
1422 | [ira_class_hard_regs | |
1423 | [base_reg_class (GET_MODE (subst), | |
1424 | MEM_ADDR_SPACE (subst), | |
1425 | ADDRESS, SCRATCH)][0]], | |
1426 | MEM_ADDR_SPACE (subst))) | |
1427 | return true; | |
1428 | ||
ba38538f VM |
1429 | /* If the address was valid and became invalid, prefer to reload |
1430 | the memory. Typical case is when the index scale should | |
1431 | correspond the memory. */ | |
1432 | *curr_id->operand_loc[nop] = old; | |
1433 | } | |
1434 | else if (REG_P (reg) && REGNO (reg) < FIRST_PSEUDO_REGISTER) | |
55a2c322 VM |
1435 | { |
1436 | alter_subreg (curr_id->operand_loc[nop], false); | |
1437 | return true; | |
1438 | } | |
895ff86f VM |
1439 | else if (CONSTANT_P (reg)) |
1440 | { | |
1441 | /* Try to simplify subreg of constant. It is usually result of | |
1442 | equivalence substitution. */ | |
1443 | if (innermode == VOIDmode | |
1444 | && (innermode = original_subreg_reg_mode[nop]) == VOIDmode) | |
1445 | innermode = curr_static_id->operand[nop].mode; | |
1446 | if ((new_reg = simplify_subreg (mode, reg, innermode, | |
1447 | SUBREG_BYTE (operand))) != NULL_RTX) | |
1448 | { | |
1449 | *curr_id->operand_loc[nop] = new_reg; | |
1450 | return true; | |
1451 | } | |
1452 | } | |
55a2c322 VM |
1453 | /* Put constant into memory when we have mixed modes. It generates |
1454 | a better code in most cases as it does not need a secondary | |
1455 | reload memory. It also prevents LRA looping when LRA is using | |
1456 | secondary reload memory again and again. */ | |
1457 | if (CONSTANT_P (reg) && CONST_POOL_OK_P (reg_mode, reg) | |
1458 | && SCALAR_INT_MODE_P (reg_mode) != SCALAR_INT_MODE_P (mode)) | |
1459 | { | |
1460 | SUBREG_REG (operand) = force_const_mem (reg_mode, reg); | |
1461 | alter_subreg (curr_id->operand_loc[nop], false); | |
1462 | return true; | |
1463 | } | |
1464 | /* Force a reload of the SUBREG_REG if this is a constant or PLUS or | |
1465 | if there may be a problem accessing OPERAND in the outer | |
1466 | mode. */ | |
1467 | if ((REG_P (reg) | |
1468 | && REGNO (reg) >= FIRST_PSEUDO_REGISTER | |
1469 | && (hard_regno = lra_get_regno_hard_regno (REGNO (reg))) >= 0 | |
1470 | /* Don't reload paradoxical subregs because we could be looping | |
1471 | having repeatedly final regno out of hard regs range. */ | |
895ff86f | 1472 | && (hard_regno_nregs[hard_regno][innermode] |
55a2c322 | 1473 | >= hard_regno_nregs[hard_regno][mode]) |
895ff86f | 1474 | && simplify_subreg_regno (hard_regno, innermode, |
2c62cbaa VM |
1475 | SUBREG_BYTE (operand), mode) < 0 |
1476 | /* Don't reload subreg for matching reload. It is actually | |
1477 | valid subreg in LRA. */ | |
1478 | && ! LRA_SUBREG_P (operand)) | |
55a2c322 VM |
1479 | || CONSTANT_P (reg) || GET_CODE (reg) == PLUS || MEM_P (reg)) |
1480 | { | |
6e23f296 VM |
1481 | enum reg_class rclass; |
1482 | ||
7613fa50 VM |
1483 | if (REG_P (reg)) |
1484 | /* There is a big probability that we will get the same class | |
6e23f296 VM |
1485 | for the new pseudo and we will get the same insn which |
1486 | means infinite looping. So spill the new pseudo. */ | |
1487 | rclass = NO_REGS; | |
1488 | else | |
1489 | /* The class will be defined later in curr_insn_transform. */ | |
1490 | rclass | |
1491 | = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS); | |
55a2c322 | 1492 | |
25bb0bb5 | 1493 | if (get_reload_reg (curr_static_id->operand[nop].type, reg_mode, reg, |
95921002 | 1494 | rclass, TRUE, "subreg reg", &new_reg)) |
55a2c322 | 1495 | { |
4f0bee4c | 1496 | bool insert_before, insert_after; |
2b778c9d | 1497 | bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg)); |
4f0bee4c WM |
1498 | |
1499 | insert_before = (type != OP_OUT | |
895ff86f | 1500 | || GET_MODE_SIZE (innermode) > GET_MODE_SIZE (mode)); |
4f0bee4c WM |
1501 | insert_after = (type != OP_IN); |
1502 | insert_move_for_subreg (insert_before ? &before : NULL, | |
1503 | insert_after ? &after : NULL, | |
1504 | reg, new_reg); | |
55a2c322 VM |
1505 | } |
1506 | SUBREG_REG (operand) = new_reg; | |
1507 | lra_process_new_insns (curr_insn, before, after, | |
1508 | "Inserting subreg reload"); | |
1509 | return true; | |
1510 | } | |
4f0bee4c WM |
1511 | /* Force a reload for a paradoxical subreg. For paradoxical subreg, |
1512 | IRA allocates hardreg to the inner pseudo reg according to its mode | |
1513 | instead of the outermode, so the size of the hardreg may not be enough | |
1514 | to contain the outermode operand, in that case we may need to insert | |
1515 | reload for the reg. For the following two types of paradoxical subreg, | |
1516 | we need to insert reload: | |
1517 | 1. If the op_type is OP_IN, and the hardreg could not be paired with | |
1518 | other hardreg to contain the outermode operand | |
1519 | (checked by in_hard_reg_set_p), we need to insert the reload. | |
1520 | 2. If the op_type is OP_OUT or OP_INOUT. | |
1521 | ||
1522 | Here is a paradoxical subreg example showing how the reload is generated: | |
1523 | ||
1524 | (insn 5 4 7 2 (set (reg:TI 106 [ __comp ]) | |
1525 | (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64} | |
1526 | ||
1527 | In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example | |
1528 | here, if reg107 is assigned to hardreg R15, because R15 is the last | |
1529 | hardreg, compiler cannot find another hardreg to pair with R15 to | |
1530 | contain TImode data. So we insert a TImode reload reg180 for it. | |
1531 | After reload is inserted: | |
1532 | ||
1533 | (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0) | |
1534 | (reg:DI 107 [ __comp ])) -1 | |
1535 | (insn 5 4 7 2 (set (reg:TI 106 [ __comp ]) | |
1536 | (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64} | |
1537 | ||
1538 | Two reload hard registers will be allocated to reg180 to save TImode data | |
1539 | in LRA_assign. */ | |
1540 | else if (REG_P (reg) | |
1541 | && REGNO (reg) >= FIRST_PSEUDO_REGISTER | |
1542 | && (hard_regno = lra_get_regno_hard_regno (REGNO (reg))) >= 0 | |
895ff86f | 1543 | && (hard_regno_nregs[hard_regno][innermode] |
4f0bee4c WM |
1544 | < hard_regno_nregs[hard_regno][mode]) |
1545 | && (regclass = lra_get_allocno_class (REGNO (reg))) | |
1546 | && (type != OP_IN | |
1547 | || !in_hard_reg_set_p (reg_class_contents[regclass], | |
1548 | mode, hard_regno))) | |
1549 | { | |
1550 | /* The class will be defined later in curr_insn_transform. */ | |
1551 | enum reg_class rclass | |
1552 | = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS); | |
1553 | ||
1554 | if (get_reload_reg (curr_static_id->operand[nop].type, mode, reg, | |
95921002 | 1555 | rclass, TRUE, "paradoxical subreg", &new_reg)) |
4f0bee4c WM |
1556 | { |
1557 | rtx subreg; | |
1558 | bool insert_before, insert_after; | |
1559 | ||
1560 | PUT_MODE (new_reg, mode); | |
ea09f50d | 1561 | subreg = gen_lowpart_SUBREG (innermode, new_reg); |
4f0bee4c WM |
1562 | bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg)); |
1563 | ||
1564 | insert_before = (type != OP_OUT); | |
1565 | insert_after = (type != OP_IN); | |
1566 | insert_move_for_subreg (insert_before ? &before : NULL, | |
1567 | insert_after ? &after : NULL, | |
1568 | reg, subreg); | |
1569 | } | |
1570 | SUBREG_REG (operand) = new_reg; | |
1571 | lra_process_new_insns (curr_insn, before, after, | |
1572 | "Inserting paradoxical subreg reload"); | |
1573 | return true; | |
1574 | } | |
55a2c322 VM |
1575 | return false; |
1576 | } | |
1577 | ||
1578 | /* Return TRUE if X refers for a hard register from SET. */ | |
1579 | static bool | |
1580 | uses_hard_regs_p (rtx x, HARD_REG_SET set) | |
1581 | { | |
1582 | int i, j, x_hard_regno; | |
ef4bddc2 | 1583 | machine_mode mode; |
55a2c322 VM |
1584 | const char *fmt; |
1585 | enum rtx_code code; | |
1586 | ||
1587 | if (x == NULL_RTX) | |
1588 | return false; | |
1589 | code = GET_CODE (x); | |
1590 | mode = GET_MODE (x); | |
1591 | if (code == SUBREG) | |
1592 | { | |
1593 | x = SUBREG_REG (x); | |
1594 | code = GET_CODE (x); | |
1595 | if (GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (mode)) | |
1596 | mode = GET_MODE (x); | |
1597 | } | |
f4eafc30 | 1598 | |
55a2c322 VM |
1599 | if (REG_P (x)) |
1600 | { | |
1601 | x_hard_regno = get_hard_regno (x); | |
1602 | return (x_hard_regno >= 0 | |
1603 | && overlaps_hard_reg_set_p (set, mode, x_hard_regno)); | |
1604 | } | |
1605 | if (MEM_P (x)) | |
1606 | { | |
277f65de | 1607 | struct address_info ad; |
55a2c322 | 1608 | |
277f65de RS |
1609 | decompose_mem_address (&ad, x); |
1610 | if (ad.base_term != NULL && uses_hard_regs_p (*ad.base_term, set)) | |
1611 | return true; | |
1612 | if (ad.index_term != NULL && uses_hard_regs_p (*ad.index_term, set)) | |
1613 | return true; | |
55a2c322 VM |
1614 | } |
1615 | fmt = GET_RTX_FORMAT (code); | |
1616 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1617 | { | |
1618 | if (fmt[i] == 'e') | |
1619 | { | |
1620 | if (uses_hard_regs_p (XEXP (x, i), set)) | |
1621 | return true; | |
1622 | } | |
1623 | else if (fmt[i] == 'E') | |
1624 | { | |
1625 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
1626 | if (uses_hard_regs_p (XVECEXP (x, i, j), set)) | |
1627 | return true; | |
1628 | } | |
1629 | } | |
1630 | return false; | |
1631 | } | |
1632 | ||
1633 | /* Return true if OP is a spilled pseudo. */ | |
1634 | static inline bool | |
1635 | spilled_pseudo_p (rtx op) | |
1636 | { | |
1637 | return (REG_P (op) | |
1638 | && REGNO (op) >= FIRST_PSEUDO_REGISTER && in_mem_p (REGNO (op))); | |
1639 | } | |
1640 | ||
1641 | /* Return true if X is a general constant. */ | |
1642 | static inline bool | |
1643 | general_constant_p (rtx x) | |
1644 | { | |
1645 | return CONSTANT_P (x) && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (x)); | |
1646 | } | |
1647 | ||
2c62cbaa VM |
1648 | static bool |
1649 | reg_in_class_p (rtx reg, enum reg_class cl) | |
1650 | { | |
1651 | if (cl == NO_REGS) | |
1652 | return get_reg_class (REGNO (reg)) == NO_REGS; | |
1653 | return in_class_p (reg, cl, NULL); | |
1654 | } | |
1655 | ||
3c954213 VM |
1656 | /* Return true if SET of RCLASS contains no hard regs which can be |
1657 | used in MODE. */ | |
1658 | static bool | |
1659 | prohibited_class_reg_set_mode_p (enum reg_class rclass, | |
1660 | HARD_REG_SET &set, | |
1661 | enum machine_mode mode) | |
1662 | { | |
1663 | HARD_REG_SET temp; | |
1664 | ||
c07ad89a | 1665 | lra_assert (hard_reg_set_subset_p (reg_class_contents[rclass], set)); |
3c954213 VM |
1666 | COPY_HARD_REG_SET (temp, set); |
1667 | AND_COMPL_HARD_REG_SET (temp, lra_no_alloc_regs); | |
1668 | return (hard_reg_set_subset_p | |
1669 | (temp, ira_prohibited_class_mode_regs[rclass][mode])); | |
1670 | } | |
1671 | ||
55a2c322 VM |
1672 | /* Major function to choose the current insn alternative and what |
1673 | operands should be reloaded and how. If ONLY_ALTERNATIVE is not | |
1674 | negative we should consider only this alternative. Return false if | |
1675 | we can not choose the alternative or find how to reload the | |
1676 | operands. */ | |
1677 | static bool | |
1678 | process_alt_operands (int only_alternative) | |
1679 | { | |
1680 | bool ok_p = false; | |
36ff9dfb | 1681 | int nop, overall, nalt; |
55a2c322 VM |
1682 | int n_alternatives = curr_static_id->n_alternatives; |
1683 | int n_operands = curr_static_id->n_operands; | |
1684 | /* LOSERS counts the operands that don't fit this alternative and | |
1685 | would require loading. */ | |
1686 | int losers; | |
1687 | /* REJECT is a count of how undesirable this alternative says it is | |
1688 | if any reloading is required. If the alternative matches exactly | |
1689 | then REJECT is ignored, but otherwise it gets this much counted | |
1690 | against it in addition to the reloading needed. */ | |
1691 | int reject; | |
d1457701 | 1692 | int op_reject; |
55a2c322 VM |
1693 | /* The number of elements in the following array. */ |
1694 | int early_clobbered_regs_num; | |
1695 | /* Numbers of operands which are early clobber registers. */ | |
1696 | int early_clobbered_nops[MAX_RECOG_OPERANDS]; | |
1697 | enum reg_class curr_alt[MAX_RECOG_OPERANDS]; | |
1698 | HARD_REG_SET curr_alt_set[MAX_RECOG_OPERANDS]; | |
1699 | bool curr_alt_match_win[MAX_RECOG_OPERANDS]; | |
1700 | bool curr_alt_win[MAX_RECOG_OPERANDS]; | |
1701 | bool curr_alt_offmemok[MAX_RECOG_OPERANDS]; | |
1702 | int curr_alt_matches[MAX_RECOG_OPERANDS]; | |
1703 | /* The number of elements in the following array. */ | |
1704 | int curr_alt_dont_inherit_ops_num; | |
1705 | /* Numbers of operands whose reload pseudos should not be inherited. */ | |
1706 | int curr_alt_dont_inherit_ops[MAX_RECOG_OPERANDS]; | |
1707 | rtx op; | |
1708 | /* The register when the operand is a subreg of register, otherwise the | |
1709 | operand itself. */ | |
1710 | rtx no_subreg_reg_operand[MAX_RECOG_OPERANDS]; | |
1711 | /* The register if the operand is a register or subreg of register, | |
1712 | otherwise NULL. */ | |
1713 | rtx operand_reg[MAX_RECOG_OPERANDS]; | |
1714 | int hard_regno[MAX_RECOG_OPERANDS]; | |
ef4bddc2 | 1715 | machine_mode biggest_mode[MAX_RECOG_OPERANDS]; |
55a2c322 VM |
1716 | int reload_nregs, reload_sum; |
1717 | bool costly_p; | |
1718 | enum reg_class cl; | |
1719 | ||
1720 | /* Calculate some data common for all alternatives to speed up the | |
1721 | function. */ | |
1722 | for (nop = 0; nop < n_operands; nop++) | |
1723 | { | |
7214306b VM |
1724 | rtx reg; |
1725 | ||
55a2c322 VM |
1726 | op = no_subreg_reg_operand[nop] = *curr_id->operand_loc[nop]; |
1727 | /* The real hard regno of the operand after the allocation. */ | |
1728 | hard_regno[nop] = get_hard_regno (op); | |
f4eafc30 | 1729 | |
7214306b VM |
1730 | operand_reg[nop] = reg = op; |
1731 | biggest_mode[nop] = GET_MODE (op); | |
1732 | if (GET_CODE (op) == SUBREG) | |
55a2c322 | 1733 | { |
7214306b | 1734 | operand_reg[nop] = reg = SUBREG_REG (op); |
55a2c322 | 1735 | if (GET_MODE_SIZE (biggest_mode[nop]) |
7214306b VM |
1736 | < GET_MODE_SIZE (GET_MODE (reg))) |
1737 | biggest_mode[nop] = GET_MODE (reg); | |
55a2c322 | 1738 | } |
7214306b | 1739 | if (! REG_P (reg)) |
55a2c322 | 1740 | operand_reg[nop] = NULL_RTX; |
7214306b VM |
1741 | else if (REGNO (reg) >= FIRST_PSEUDO_REGISTER |
1742 | || ((int) REGNO (reg) | |
1743 | == lra_get_elimination_hard_regno (REGNO (reg)))) | |
1744 | no_subreg_reg_operand[nop] = reg; | |
1745 | else | |
1746 | operand_reg[nop] = no_subreg_reg_operand[nop] | |
1747 | /* Just use natural mode for elimination result. It should | |
1748 | be enough for extra constraints hooks. */ | |
1749 | = regno_reg_rtx[hard_regno[nop]]; | |
55a2c322 VM |
1750 | } |
1751 | ||
1752 | /* The constraints are made of several alternatives. Each operand's | |
1753 | constraint looks like foo,bar,... with commas separating the | |
1754 | alternatives. The first alternatives for all operands go | |
1755 | together, the second alternatives go together, etc. | |
1756 | ||
1757 | First loop over alternatives. */ | |
9840b2fa | 1758 | alternative_mask preferred = curr_id->preferred_alternatives; |
4cc8d9d2 | 1759 | if (only_alternative >= 0) |
9840b2fa | 1760 | preferred &= ALTERNATIVE_BIT (only_alternative); |
4cc8d9d2 | 1761 | |
55a2c322 VM |
1762 | for (nalt = 0; nalt < n_alternatives; nalt++) |
1763 | { | |
1764 | /* Loop over operands for one constraint alternative. */ | |
9840b2fa | 1765 | if (!TEST_BIT (preferred, nalt)) |
55a2c322 VM |
1766 | continue; |
1767 | ||
1768 | overall = losers = reject = reload_nregs = reload_sum = 0; | |
1769 | for (nop = 0; nop < n_operands; nop++) | |
cb1cca12 VM |
1770 | { |
1771 | int inc = (curr_static_id | |
1772 | ->operand_alternative[nalt * n_operands + nop].reject); | |
1773 | if (lra_dump_file != NULL && inc != 0) | |
1774 | fprintf (lra_dump_file, | |
1775 | " Staticly defined alt reject+=%d\n", inc); | |
1776 | reject += inc; | |
1777 | } | |
55a2c322 VM |
1778 | early_clobbered_regs_num = 0; |
1779 | ||
1780 | for (nop = 0; nop < n_operands; nop++) | |
1781 | { | |
1782 | const char *p; | |
1783 | char *end; | |
1784 | int len, c, m, i, opalt_num, this_alternative_matches; | |
1785 | bool win, did_match, offmemok, early_clobber_p; | |
1786 | /* false => this operand can be reloaded somehow for this | |
1787 | alternative. */ | |
1788 | bool badop; | |
1789 | /* true => this operand can be reloaded if the alternative | |
1790 | allows regs. */ | |
1791 | bool winreg; | |
1792 | /* True if a constant forced into memory would be OK for | |
1793 | this operand. */ | |
1794 | bool constmemok; | |
1795 | enum reg_class this_alternative, this_costly_alternative; | |
1796 | HARD_REG_SET this_alternative_set, this_costly_alternative_set; | |
1797 | bool this_alternative_match_win, this_alternative_win; | |
1798 | bool this_alternative_offmemok; | |
80f466c4 | 1799 | bool scratch_p; |
ef4bddc2 | 1800 | machine_mode mode; |
777e635f | 1801 | enum constraint_num cn; |
55a2c322 VM |
1802 | |
1803 | opalt_num = nalt * n_operands + nop; | |
1804 | if (curr_static_id->operand_alternative[opalt_num].anything_ok) | |
1805 | { | |
1806 | /* Fast track for no constraints at all. */ | |
1807 | curr_alt[nop] = NO_REGS; | |
1808 | CLEAR_HARD_REG_SET (curr_alt_set[nop]); | |
1809 | curr_alt_win[nop] = true; | |
1810 | curr_alt_match_win[nop] = false; | |
1811 | curr_alt_offmemok[nop] = false; | |
1812 | curr_alt_matches[nop] = -1; | |
1813 | continue; | |
1814 | } | |
f4eafc30 | 1815 | |
55a2c322 VM |
1816 | op = no_subreg_reg_operand[nop]; |
1817 | mode = curr_operand_mode[nop]; | |
1818 | ||
1819 | win = did_match = winreg = offmemok = constmemok = false; | |
1820 | badop = true; | |
f4eafc30 | 1821 | |
55a2c322 VM |
1822 | early_clobber_p = false; |
1823 | p = curr_static_id->operand_alternative[opalt_num].constraint; | |
f4eafc30 | 1824 | |
55a2c322 VM |
1825 | this_costly_alternative = this_alternative = NO_REGS; |
1826 | /* We update set of possible hard regs besides its class | |
1827 | because reg class might be inaccurate. For example, | |
1828 | union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM | |
1829 | is translated in HI_REGS because classes are merged by | |
1830 | pairs and there is no accurate intermediate class. */ | |
1831 | CLEAR_HARD_REG_SET (this_alternative_set); | |
1832 | CLEAR_HARD_REG_SET (this_costly_alternative_set); | |
1833 | this_alternative_win = false; | |
1834 | this_alternative_match_win = false; | |
1835 | this_alternative_offmemok = false; | |
1836 | this_alternative_matches = -1; | |
f4eafc30 | 1837 | |
55a2c322 VM |
1838 | /* An empty constraint should be excluded by the fast |
1839 | track. */ | |
1840 | lra_assert (*p != 0 && *p != ','); | |
f4eafc30 | 1841 | |
d1457701 | 1842 | op_reject = 0; |
55a2c322 VM |
1843 | /* Scan this alternative's specs for this operand; set WIN |
1844 | if the operand fits any letter in this alternative. | |
1845 | Otherwise, clear BADOP if this operand could fit some | |
1846 | letter after reloads, or set WINREG if this operand could | |
1847 | fit after reloads provided the constraint allows some | |
1848 | registers. */ | |
1849 | costly_p = false; | |
1850 | do | |
1851 | { | |
1852 | switch ((c = *p, len = CONSTRAINT_LEN (c, p)), c) | |
1853 | { | |
1854 | case '\0': | |
1855 | len = 0; | |
1856 | break; | |
1857 | case ',': | |
1858 | c = '\0'; | |
1859 | break; | |
f4eafc30 | 1860 | |
55a2c322 VM |
1861 | case '&': |
1862 | early_clobber_p = true; | |
1863 | break; | |
f4eafc30 | 1864 | |
d1457701 VM |
1865 | case '$': |
1866 | op_reject += LRA_MAX_REJECT; | |
1867 | break; | |
1868 | case '^': | |
1869 | op_reject += LRA_LOSER_COST_FACTOR; | |
1870 | break; | |
1871 | ||
55a2c322 VM |
1872 | case '#': |
1873 | /* Ignore rest of this alternative. */ | |
1874 | c = '\0'; | |
1875 | break; | |
f4eafc30 | 1876 | |
55a2c322 VM |
1877 | case '0': case '1': case '2': case '3': case '4': |
1878 | case '5': case '6': case '7': case '8': case '9': | |
1879 | { | |
1880 | int m_hregno; | |
1881 | bool match_p; | |
f4eafc30 | 1882 | |
55a2c322 VM |
1883 | m = strtoul (p, &end, 10); |
1884 | p = end; | |
1885 | len = 0; | |
1886 | lra_assert (nop > m); | |
f4eafc30 | 1887 | |
55a2c322 VM |
1888 | this_alternative_matches = m; |
1889 | m_hregno = get_hard_regno (*curr_id->operand_loc[m]); | |
1890 | /* We are supposed to match a previous operand. | |
1891 | If we do, we win if that one did. If we do | |
1892 | not, count both of the operands as losers. | |
1893 | (This is too conservative, since most of the | |
1894 | time only a single reload insn will be needed | |
1895 | to make the two operands win. As a result, | |
1896 | this alternative may be rejected when it is | |
1897 | actually desirable.) */ | |
1898 | match_p = false; | |
1899 | if (operands_match_p (*curr_id->operand_loc[nop], | |
1900 | *curr_id->operand_loc[m], m_hregno)) | |
1901 | { | |
1902 | /* We should reject matching of an early | |
1903 | clobber operand if the matching operand is | |
1904 | not dying in the insn. */ | |
1905 | if (! curr_static_id->operand[m].early_clobber | |
1906 | || operand_reg[nop] == NULL_RTX | |
1907 | || (find_regno_note (curr_insn, REG_DEAD, | |
1c86bd80 VM |
1908 | REGNO (op)) |
1909 | || REGNO (op) == REGNO (operand_reg[m]))) | |
55a2c322 VM |
1910 | match_p = true; |
1911 | } | |
1912 | if (match_p) | |
1913 | { | |
1914 | /* If we are matching a non-offsettable | |
1915 | address where an offsettable address was | |
1916 | expected, then we must reject this | |
1917 | combination, because we can't reload | |
1918 | it. */ | |
1919 | if (curr_alt_offmemok[m] | |
1920 | && MEM_P (*curr_id->operand_loc[m]) | |
1921 | && curr_alt[m] == NO_REGS && ! curr_alt_win[m]) | |
1922 | continue; | |
55a2c322 VM |
1923 | } |
1924 | else | |
1925 | { | |
1926 | /* Operands don't match. Both operands must | |
1927 | allow a reload register, otherwise we | |
1928 | cannot make them match. */ | |
1929 | if (curr_alt[m] == NO_REGS) | |
1930 | break; | |
1931 | /* Retroactively mark the operand we had to | |
1932 | match as a loser, if it wasn't already and | |
1933 | it wasn't matched to a register constraint | |
1934 | (e.g it might be matched by memory). */ | |
1935 | if (curr_alt_win[m] | |
1936 | && (operand_reg[m] == NULL_RTX | |
1937 | || hard_regno[m] < 0)) | |
1938 | { | |
1939 | losers++; | |
1940 | reload_nregs | |
1941 | += (ira_reg_class_max_nregs[curr_alt[m]] | |
1942 | [GET_MODE (*curr_id->operand_loc[m])]); | |
1943 | } | |
f4eafc30 | 1944 | |
f4581282 VM |
1945 | /* Prefer matching earlyclobber alternative as |
1946 | it results in less hard regs required for | |
1947 | the insn than a non-matching earlyclobber | |
1948 | alternative. */ | |
1949 | if (curr_static_id->operand[m].early_clobber) | |
1950 | { | |
1951 | if (lra_dump_file != NULL) | |
1952 | fprintf | |
1953 | (lra_dump_file, | |
1954 | " %d Matching earlyclobber alt:" | |
1955 | " reject--\n", | |
1956 | nop); | |
1957 | reject--; | |
1958 | } | |
1959 | /* Otherwise we prefer no matching | |
1960 | alternatives because it gives more freedom | |
1961 | in RA. */ | |
1962 | else if (operand_reg[nop] == NULL_RTX | |
1963 | || (find_regno_note (curr_insn, REG_DEAD, | |
1964 | REGNO (operand_reg[nop])) | |
1965 | == NULL_RTX)) | |
cb1cca12 VM |
1966 | { |
1967 | if (lra_dump_file != NULL) | |
1968 | fprintf | |
1969 | (lra_dump_file, | |
1970 | " %d Matching alt: reject+=2\n", | |
1971 | nop); | |
1972 | reject += 2; | |
1973 | } | |
55a2c322 VM |
1974 | } |
1975 | /* If we have to reload this operand and some | |
1976 | previous operand also had to match the same | |
1977 | thing as this operand, we don't know how to do | |
1978 | that. */ | |
1979 | if (!match_p || !curr_alt_win[m]) | |
1980 | { | |
1981 | for (i = 0; i < nop; i++) | |
1982 | if (curr_alt_matches[i] == m) | |
1983 | break; | |
1984 | if (i < nop) | |
1985 | break; | |
1986 | } | |
1987 | else | |
1988 | did_match = true; | |
f4eafc30 | 1989 | |
55a2c322 VM |
1990 | /* This can be fixed with reloads if the operand |
1991 | we are supposed to match can be fixed with | |
1992 | reloads. */ | |
1993 | badop = false; | |
1994 | this_alternative = curr_alt[m]; | |
1995 | COPY_HARD_REG_SET (this_alternative_set, curr_alt_set[m]); | |
821b7577 | 1996 | winreg = this_alternative != NO_REGS; |
55a2c322 VM |
1997 | break; |
1998 | } | |
f4eafc30 | 1999 | |
55a2c322 VM |
2000 | case 'g': |
2001 | if (MEM_P (op) | |
2002 | || general_constant_p (op) | |
2003 | || spilled_pseudo_p (op)) | |
2004 | win = true; | |
777e635f | 2005 | cl = GENERAL_REGS; |
55a2c322 | 2006 | goto reg; |
f4eafc30 | 2007 | |
55a2c322 | 2008 | default: |
777e635f RS |
2009 | cn = lookup_constraint (p); |
2010 | switch (get_constraint_type (cn)) | |
55a2c322 | 2011 | { |
777e635f RS |
2012 | case CT_REGISTER: |
2013 | cl = reg_class_for_constraint (cn); | |
2014 | if (cl != NO_REGS) | |
2015 | goto reg; | |
2016 | break; | |
f4eafc30 | 2017 | |
d9c35eee RS |
2018 | case CT_CONST_INT: |
2019 | if (CONST_INT_P (op) | |
2020 | && insn_const_int_ok_for_constraint (INTVAL (op), cn)) | |
2021 | win = true; | |
2022 | break; | |
2023 | ||
777e635f RS |
2024 | case CT_MEMORY: |
2025 | if (MEM_P (op) | |
2026 | && satisfies_memory_constraint_p (op, cn)) | |
2027 | win = true; | |
2028 | else if (spilled_pseudo_p (op)) | |
2029 | win = true; | |
2030 | ||
2031 | /* If we didn't already win, we can reload constants | |
2032 | via force_const_mem or put the pseudo value into | |
2033 | memory, or make other memory by reloading the | |
2034 | address like for 'o'. */ | |
2035 | if (CONST_POOL_OK_P (mode, op) | |
2036 | || MEM_P (op) || REG_P (op)) | |
2037 | badop = false; | |
2038 | constmemok = true; | |
2039 | offmemok = true; | |
2040 | break; | |
2041 | ||
2042 | case CT_ADDRESS: | |
2043 | /* If we didn't already win, we can reload the address | |
2044 | into a base register. */ | |
2045 | if (satisfies_address_constraint_p (op, cn)) | |
2046 | win = true; | |
2047 | cl = base_reg_class (VOIDmode, ADDR_SPACE_GENERIC, | |
2048 | ADDRESS, SCRATCH); | |
2049 | badop = false; | |
2050 | goto reg; | |
2051 | ||
2052 | case CT_FIXED_FORM: | |
2053 | if (constraint_satisfied_p (op, cn)) | |
55a2c322 | 2054 | win = true; |
55a2c322 | 2055 | break; |
9eb1ca69 VM |
2056 | |
2057 | case CT_SPECIAL_MEMORY: | |
2058 | if (MEM_P (op) | |
2059 | && satisfies_memory_constraint_p (op, cn)) | |
2060 | win = true; | |
2061 | else if (spilled_pseudo_p (op)) | |
2062 | win = true; | |
2063 | break; | |
55a2c322 | 2064 | } |
777e635f | 2065 | break; |
f4eafc30 | 2066 | |
777e635f | 2067 | reg: |
55a2c322 VM |
2068 | this_alternative = reg_class_subunion[this_alternative][cl]; |
2069 | IOR_HARD_REG_SET (this_alternative_set, | |
2070 | reg_class_contents[cl]); | |
2071 | if (costly_p) | |
2072 | { | |
2073 | this_costly_alternative | |
2074 | = reg_class_subunion[this_costly_alternative][cl]; | |
2075 | IOR_HARD_REG_SET (this_costly_alternative_set, | |
2076 | reg_class_contents[cl]); | |
2077 | } | |
55a2c322 VM |
2078 | if (mode == BLKmode) |
2079 | break; | |
2080 | winreg = true; | |
2081 | if (REG_P (op)) | |
2082 | { | |
2083 | if (hard_regno[nop] >= 0 | |
2084 | && in_hard_reg_set_p (this_alternative_set, | |
2085 | mode, hard_regno[nop])) | |
2086 | win = true; | |
2087 | else if (hard_regno[nop] < 0 | |
2088 | && in_class_p (op, this_alternative, NULL)) | |
2089 | win = true; | |
2090 | } | |
2091 | break; | |
2092 | } | |
2093 | if (c != ' ' && c != '\t') | |
2094 | costly_p = c == '*'; | |
2095 | } | |
2096 | while ((p += len), c); | |
f4eafc30 | 2097 | |
80f466c4 VM |
2098 | scratch_p = (operand_reg[nop] != NULL_RTX |
2099 | && lra_former_scratch_p (REGNO (operand_reg[nop]))); | |
55a2c322 VM |
2100 | /* Record which operands fit this alternative. */ |
2101 | if (win) | |
2102 | { | |
2103 | this_alternative_win = true; | |
2104 | if (operand_reg[nop] != NULL_RTX) | |
2105 | { | |
2106 | if (hard_regno[nop] >= 0) | |
2107 | { | |
2108 | if (in_hard_reg_set_p (this_costly_alternative_set, | |
2109 | mode, hard_regno[nop])) | |
cb1cca12 VM |
2110 | { |
2111 | if (lra_dump_file != NULL) | |
2112 | fprintf (lra_dump_file, | |
2113 | " %d Costly set: reject++\n", | |
2114 | nop); | |
2115 | reject++; | |
2116 | } | |
55a2c322 VM |
2117 | } |
2118 | else | |
2119 | { | |
80f466c4 VM |
2120 | /* Prefer won reg to spilled pseudo under other |
2121 | equal conditions for possibe inheritance. */ | |
2122 | if (! scratch_p) | |
2123 | { | |
2124 | if (lra_dump_file != NULL) | |
2125 | fprintf | |
2126 | (lra_dump_file, | |
2127 | " %d Non pseudo reload: reject++\n", | |
2128 | nop); | |
2129 | reject++; | |
2130 | } | |
55a2c322 VM |
2131 | if (in_class_p (operand_reg[nop], |
2132 | this_costly_alternative, NULL)) | |
cb1cca12 VM |
2133 | { |
2134 | if (lra_dump_file != NULL) | |
2135 | fprintf | |
2136 | (lra_dump_file, | |
2137 | " %d Non pseudo costly reload:" | |
2138 | " reject++\n", | |
2139 | nop); | |
2140 | reject++; | |
2141 | } | |
55a2c322 VM |
2142 | } |
2143 | /* We simulate the behaviour of old reload here. | |
2144 | Although scratches need hard registers and it | |
2145 | might result in spilling other pseudos, no reload | |
2146 | insns are generated for the scratches. So it | |
2147 | might cost something but probably less than old | |
2148 | reload pass believes. */ | |
80f466c4 | 2149 | if (scratch_p) |
cb1cca12 VM |
2150 | { |
2151 | if (lra_dump_file != NULL) | |
2152 | fprintf (lra_dump_file, | |
80f466c4 | 2153 | " %d Scratch win: reject+=2\n", |
cb1cca12 | 2154 | nop); |
80f466c4 | 2155 | reject += 2; |
cb1cca12 | 2156 | } |
55a2c322 VM |
2157 | } |
2158 | } | |
2159 | else if (did_match) | |
2160 | this_alternative_match_win = true; | |
2161 | else | |
2162 | { | |
2163 | int const_to_mem = 0; | |
2164 | bool no_regs_p; | |
2165 | ||
d1457701 | 2166 | reject += op_reject; |
8d49e7ef VM |
2167 | /* Never do output reload of stack pointer. It makes |
2168 | impossible to do elimination when SP is changed in | |
2169 | RTL. */ | |
2170 | if (op == stack_pointer_rtx && ! frame_pointer_needed | |
2171 | && curr_static_id->operand[nop].type != OP_IN) | |
2172 | goto fail; | |
2173 | ||
e86c0101 SB |
2174 | /* If this alternative asks for a specific reg class, see if there |
2175 | is at least one allocatable register in that class. */ | |
55a2c322 VM |
2176 | no_regs_p |
2177 | = (this_alternative == NO_REGS | |
2178 | || (hard_reg_set_subset_p | |
2179 | (reg_class_contents[this_alternative], | |
2180 | lra_no_alloc_regs))); | |
e86c0101 SB |
2181 | |
2182 | /* For asms, verify that the class for this alternative is possible | |
2183 | for the mode that is specified. */ | |
ecee672b | 2184 | if (!no_regs_p && INSN_CODE (curr_insn) < 0) |
e86c0101 SB |
2185 | { |
2186 | int i; | |
2187 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
2188 | if (HARD_REGNO_MODE_OK (i, mode) | |
8f21260c VM |
2189 | && in_hard_reg_set_p (reg_class_contents[this_alternative], |
2190 | mode, i)) | |
e86c0101 SB |
2191 | break; |
2192 | if (i == FIRST_PSEUDO_REGISTER) | |
2193 | winreg = false; | |
2194 | } | |
2195 | ||
55a2c322 VM |
2196 | /* If this operand accepts a register, and if the |
2197 | register class has at least one allocatable register, | |
2198 | then this operand can be reloaded. */ | |
2199 | if (winreg && !no_regs_p) | |
2200 | badop = false; | |
f4eafc30 | 2201 | |
55a2c322 | 2202 | if (badop) |
8f21260c VM |
2203 | { |
2204 | if (lra_dump_file != NULL) | |
2205 | fprintf (lra_dump_file, | |
2206 | " alt=%d: Bad operand -- refuse\n", | |
2207 | nalt); | |
2208 | goto fail; | |
2209 | } | |
55a2c322 | 2210 | |
2ae577fd VM |
2211 | /* If not assigned pseudo has a class which a subset of |
2212 | required reg class, it is a less costly alternative | |
2213 | as the pseudo still can get a hard reg of necessary | |
2214 | class. */ | |
2215 | if (! no_regs_p && REG_P (op) && hard_regno[nop] < 0 | |
2216 | && (cl = get_reg_class (REGNO (op))) != NO_REGS | |
2217 | && ira_class_subset_p[this_alternative][cl]) | |
2218 | { | |
2219 | if (lra_dump_file != NULL) | |
2220 | fprintf | |
2221 | (lra_dump_file, | |
2222 | " %d Super set class reg: reject-=3\n", nop); | |
2223 | reject -= 3; | |
2224 | } | |
2225 | ||
55a2c322 VM |
2226 | this_alternative_offmemok = offmemok; |
2227 | if (this_costly_alternative != NO_REGS) | |
cb1cca12 VM |
2228 | { |
2229 | if (lra_dump_file != NULL) | |
2230 | fprintf (lra_dump_file, | |
2231 | " %d Costly loser: reject++\n", nop); | |
2232 | reject++; | |
2233 | } | |
55a2c322 VM |
2234 | /* If the operand is dying, has a matching constraint, |
2235 | and satisfies constraints of the matched operand | |
f4581282 | 2236 | which failed to satisfy the own constraints, most probably |
a9711f36 VM |
2237 | the reload for this operand will be gone. */ |
2238 | if (this_alternative_matches >= 0 | |
2239 | && !curr_alt_win[this_alternative_matches] | |
2240 | && REG_P (op) | |
2241 | && find_regno_note (curr_insn, REG_DEAD, REGNO (op)) | |
2242 | && (hard_regno[nop] >= 0 | |
2243 | ? in_hard_reg_set_p (this_alternative_set, | |
2244 | mode, hard_regno[nop]) | |
2245 | : in_class_p (op, this_alternative, NULL))) | |
2246 | { | |
2247 | if (lra_dump_file != NULL) | |
2248 | fprintf | |
2249 | (lra_dump_file, | |
2250 | " %d Dying matched operand reload: reject++\n", | |
2251 | nop); | |
2252 | reject++; | |
2253 | } | |
2254 | else | |
027ece11 | 2255 | { |
5306401f VM |
2256 | /* Strict_low_part requires to reload the register |
2257 | not the sub-register. In this case we should | |
2258 | check that a final reload hard reg can hold the | |
2259 | value mode. */ | |
027ece11 VM |
2260 | if (curr_static_id->operand[nop].strict_low |
2261 | && REG_P (op) | |
2262 | && hard_regno[nop] < 0 | |
2263 | && GET_CODE (*curr_id->operand_loc[nop]) == SUBREG | |
2264 | && ira_class_hard_regs_num[this_alternative] > 0 | |
2265 | && ! HARD_REGNO_MODE_OK (ira_class_hard_regs | |
2266 | [this_alternative][0], | |
00b7527b VM |
2267 | GET_MODE |
2268 | (*curr_id->operand_loc[nop]))) | |
8f21260c VM |
2269 | { |
2270 | if (lra_dump_file != NULL) | |
2271 | fprintf | |
2272 | (lra_dump_file, | |
2273 | " alt=%d: Strict low subreg reload -- refuse\n", | |
2274 | nalt); | |
2275 | goto fail; | |
2276 | } | |
027ece11 VM |
2277 | losers++; |
2278 | } | |
55a2c322 VM |
2279 | if (operand_reg[nop] != NULL_RTX |
2280 | /* Output operands and matched input operands are | |
2281 | not inherited. The following conditions do not | |
2282 | exactly describe the previous statement but they | |
2283 | are pretty close. */ | |
2284 | && curr_static_id->operand[nop].type != OP_OUT | |
2285 | && (this_alternative_matches < 0 | |
2286 | || curr_static_id->operand[nop].type != OP_IN)) | |
2287 | { | |
2288 | int last_reload = (lra_reg_info[ORIGINAL_REGNO | |
2289 | (operand_reg[nop])] | |
2290 | .last_reload); | |
2291 | ||
6334f3e9 VM |
2292 | /* The value of reload_sum has sense only if we |
2293 | process insns in their order. It happens only on | |
2294 | the first constraints sub-pass when we do most of | |
2295 | reload work. */ | |
2296 | if (lra_constraint_iter == 1 && last_reload > bb_reload_num) | |
55a2c322 VM |
2297 | reload_sum += last_reload - bb_reload_num; |
2298 | } | |
2299 | /* If this is a constant that is reloaded into the | |
2300 | desired class by copying it to memory first, count | |
2301 | that as another reload. This is consistent with | |
2302 | other code and is required to avoid choosing another | |
2303 | alternative when the constant is moved into memory. | |
2304 | Note that the test here is precisely the same as in | |
2305 | the code below that calls force_const_mem. */ | |
2306 | if (CONST_POOL_OK_P (mode, op) | |
2307 | && ((targetm.preferred_reload_class | |
2308 | (op, this_alternative) == NO_REGS) | |
2309 | || no_input_reloads_p)) | |
2310 | { | |
2311 | const_to_mem = 1; | |
2312 | if (! no_regs_p) | |
2313 | losers++; | |
2314 | } | |
f4eafc30 | 2315 | |
55a2c322 VM |
2316 | /* Alternative loses if it requires a type of reload not |
2317 | permitted for this insn. We can always reload | |
2318 | objects with a REG_UNUSED note. */ | |
2319 | if ((curr_static_id->operand[nop].type != OP_IN | |
2320 | && no_output_reloads_p | |
2321 | && ! find_reg_note (curr_insn, REG_UNUSED, op)) | |
2322 | || (curr_static_id->operand[nop].type != OP_OUT | |
8f21260c VM |
2323 | && no_input_reloads_p && ! const_to_mem) |
2324 | || (this_alternative_matches >= 0 | |
9102dadd VM |
2325 | && (no_input_reloads_p |
2326 | || (no_output_reloads_p | |
2327 | && (curr_static_id->operand | |
2328 | [this_alternative_matches].type != OP_IN) | |
2329 | && ! find_reg_note (curr_insn, REG_UNUSED, | |
2330 | no_subreg_reg_operand | |
2331 | [this_alternative_matches]))))) | |
8f21260c VM |
2332 | { |
2333 | if (lra_dump_file != NULL) | |
2334 | fprintf | |
2335 | (lra_dump_file, | |
2336 | " alt=%d: No input/otput reload -- refuse\n", | |
2337 | nalt); | |
2338 | goto fail; | |
2339 | } | |
f4eafc30 | 2340 | |
f66af4aa VM |
2341 | /* Alternative loses if it required class pseudo can not |
2342 | hold value of required mode. Such insns can be | |
7b6e0c54 | 2343 | described by insn definitions with mode iterators. */ |
f66af4aa VM |
2344 | if (GET_MODE (*curr_id->operand_loc[nop]) != VOIDmode |
2345 | && ! hard_reg_set_empty_p (this_alternative_set) | |
7b6e0c54 VM |
2346 | /* It is common practice for constraints to use a |
2347 | class which does not have actually enough regs to | |
2348 | hold the value (e.g. x86 AREG for mode requiring | |
2349 | more one general reg). Therefore we have 2 | |
2350 | conditions to check that the reload pseudo can | |
2351 | not hold the mode value. */ | |
f66af4aa VM |
2352 | && ! HARD_REGNO_MODE_OK (ira_class_hard_regs |
2353 | [this_alternative][0], | |
3c954213 | 2354 | GET_MODE (*curr_id->operand_loc[nop])) |
7b6e0c54 VM |
2355 | /* The above condition is not enough as the first |
2356 | reg in ira_class_hard_regs can be not aligned for | |
2357 | multi-words mode values. */ | |
3c954213 VM |
2358 | && (prohibited_class_reg_set_mode_p |
2359 | (this_alternative, this_alternative_set, | |
2360 | GET_MODE (*curr_id->operand_loc[nop])))) | |
2361 | { | |
2362 | if (lra_dump_file != NULL) | |
2363 | fprintf (lra_dump_file, | |
2364 | " alt=%d: reload pseudo for op %d " | |
2365 | " can not hold the mode value -- refuse\n", | |
2366 | nalt, nop); | |
2367 | goto fail; | |
f66af4aa VM |
2368 | } |
2369 | ||
821b7577 VM |
2370 | /* Check strong discouragement of reload of non-constant |
2371 | into class THIS_ALTERNATIVE. */ | |
2372 | if (! CONSTANT_P (op) && ! no_regs_p | |
2373 | && (targetm.preferred_reload_class | |
2374 | (op, this_alternative) == NO_REGS | |
2375 | || (curr_static_id->operand[nop].type == OP_OUT | |
2376 | && (targetm.preferred_output_reload_class | |
2377 | (op, this_alternative) == NO_REGS)))) | |
cb1cca12 VM |
2378 | { |
2379 | if (lra_dump_file != NULL) | |
2380 | fprintf (lra_dump_file, | |
2381 | " %d Non-prefered reload: reject+=%d\n", | |
2382 | nop, LRA_MAX_REJECT); | |
2383 | reject += LRA_MAX_REJECT; | |
2384 | } | |
f4eafc30 | 2385 | |
ed52a84e VM |
2386 | if (! (MEM_P (op) && offmemok) |
2387 | && ! (const_to_mem && constmemok)) | |
55a2c322 VM |
2388 | { |
2389 | /* We prefer to reload pseudos over reloading other | |
2390 | things, since such reloads may be able to be | |
2391 | eliminated later. So bump REJECT in other cases. | |
2392 | Don't do this in the case where we are forcing a | |
2393 | constant into memory and it will then win since | |
2394 | we don't want to have a different alternative | |
2395 | match then. */ | |
2396 | if (! (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER)) | |
cb1cca12 VM |
2397 | { |
2398 | if (lra_dump_file != NULL) | |
2399 | fprintf | |
2400 | (lra_dump_file, | |
2401 | " %d Non-pseudo reload: reject+=2\n", | |
2402 | nop); | |
2403 | reject += 2; | |
2404 | } | |
f4eafc30 | 2405 | |
55a2c322 VM |
2406 | if (! no_regs_p) |
2407 | reload_nregs | |
2408 | += ira_reg_class_max_nregs[this_alternative][mode]; | |
36ff9dfb VM |
2409 | |
2410 | if (SMALL_REGISTER_CLASS_P (this_alternative)) | |
cb1cca12 VM |
2411 | { |
2412 | if (lra_dump_file != NULL) | |
2413 | fprintf | |
2414 | (lra_dump_file, | |
2415 | " %d Small class reload: reject+=%d\n", | |
2416 | nop, LRA_LOSER_COST_FACTOR / 2); | |
2417 | reject += LRA_LOSER_COST_FACTOR / 2; | |
2418 | } | |
55a2c322 VM |
2419 | } |
2420 | ||
1bdc4b11 VM |
2421 | /* We are trying to spill pseudo into memory. It is |
2422 | usually more costly than moving to a hard register | |
2423 | although it might takes the same number of | |
2424 | reloads. */ | |
cb1cca12 VM |
2425 | if (no_regs_p && REG_P (op) && hard_regno[nop] >= 0) |
2426 | { | |
2427 | if (lra_dump_file != NULL) | |
2428 | fprintf | |
2429 | (lra_dump_file, | |
7891065a | 2430 | " %d Spill pseudo into memory: reject+=3\n", |
cb1cca12 VM |
2431 | nop); |
2432 | reject += 3; | |
7891065a VM |
2433 | if (VECTOR_MODE_P (mode)) |
2434 | { | |
2435 | /* Spilling vectors into memory is usually more | |
2436 | costly as they contain big values. */ | |
2437 | if (lra_dump_file != NULL) | |
2438 | fprintf | |
2439 | (lra_dump_file, | |
2440 | " %d Spill vector pseudo: reject+=2\n", | |
2441 | nop); | |
2442 | reject += 2; | |
2443 | } | |
cb1cca12 | 2444 | } |
1bdc4b11 | 2445 | |
7100b561 UB |
2446 | #ifdef SECONDARY_MEMORY_NEEDED |
2447 | /* If reload requires moving value through secondary | |
2448 | memory, it will need one more insn at least. */ | |
2449 | if (this_alternative != NO_REGS | |
2450 | && REG_P (op) && (cl = get_reg_class (REGNO (op))) != NO_REGS | |
2451 | && ((curr_static_id->operand[nop].type != OP_OUT | |
2452 | && SECONDARY_MEMORY_NEEDED (cl, this_alternative, | |
2453 | GET_MODE (op))) | |
2454 | || (curr_static_id->operand[nop].type != OP_IN | |
2455 | && SECONDARY_MEMORY_NEEDED (this_alternative, cl, | |
2456 | GET_MODE (op))))) | |
2457 | losers++; | |
2458 | #endif | |
55a2c322 VM |
2459 | /* Input reloads can be inherited more often than output |
2460 | reloads can be removed, so penalize output | |
2461 | reloads. */ | |
2462 | if (!REG_P (op) || curr_static_id->operand[nop].type != OP_IN) | |
cb1cca12 VM |
2463 | { |
2464 | if (lra_dump_file != NULL) | |
2465 | fprintf | |
2466 | (lra_dump_file, | |
2467 | " %d Non input pseudo reload: reject++\n", | |
2468 | nop); | |
2469 | reject++; | |
2470 | } | |
55a2c322 | 2471 | } |
f4eafc30 | 2472 | |
80f466c4 | 2473 | if (early_clobber_p && ! scratch_p) |
cb1cca12 VM |
2474 | { |
2475 | if (lra_dump_file != NULL) | |
2476 | fprintf (lra_dump_file, | |
2477 | " %d Early clobber: reject++\n", nop); | |
2478 | reject++; | |
2479 | } | |
55a2c322 VM |
2480 | /* ??? We check early clobbers after processing all operands |
2481 | (see loop below) and there we update the costs more. | |
2482 | Should we update the cost (may be approximately) here | |
2483 | because of early clobber register reloads or it is a rare | |
2484 | or non-important thing to be worth to do it. */ | |
821b7577 | 2485 | overall = losers * LRA_LOSER_COST_FACTOR + reject; |
55a2c322 | 2486 | if ((best_losers == 0 || losers != 0) && best_overall < overall) |
deca73f5 VM |
2487 | { |
2488 | if (lra_dump_file != NULL) | |
2489 | fprintf (lra_dump_file, | |
cb1cca12 | 2490 | " alt=%d,overall=%d,losers=%d -- refuse\n", |
deca73f5 VM |
2491 | nalt, overall, losers); |
2492 | goto fail; | |
2493 | } | |
55a2c322 VM |
2494 | |
2495 | curr_alt[nop] = this_alternative; | |
2496 | COPY_HARD_REG_SET (curr_alt_set[nop], this_alternative_set); | |
2497 | curr_alt_win[nop] = this_alternative_win; | |
2498 | curr_alt_match_win[nop] = this_alternative_match_win; | |
2499 | curr_alt_offmemok[nop] = this_alternative_offmemok; | |
2500 | curr_alt_matches[nop] = this_alternative_matches; | |
f4eafc30 | 2501 | |
55a2c322 VM |
2502 | if (this_alternative_matches >= 0 |
2503 | && !did_match && !this_alternative_win) | |
2504 | curr_alt_win[this_alternative_matches] = false; | |
f4eafc30 | 2505 | |
55a2c322 VM |
2506 | if (early_clobber_p && operand_reg[nop] != NULL_RTX) |
2507 | early_clobbered_nops[early_clobbered_regs_num++] = nop; | |
2508 | } | |
2c62cbaa VM |
2509 | if (curr_insn_set != NULL_RTX && n_operands == 2 |
2510 | /* Prevent processing non-move insns. */ | |
2511 | && (GET_CODE (SET_SRC (curr_insn_set)) == SUBREG | |
2512 | || SET_SRC (curr_insn_set) == no_subreg_reg_operand[1]) | |
2513 | && ((! curr_alt_win[0] && ! curr_alt_win[1] | |
2514 | && REG_P (no_subreg_reg_operand[0]) | |
2515 | && REG_P (no_subreg_reg_operand[1]) | |
2516 | && (reg_in_class_p (no_subreg_reg_operand[0], curr_alt[1]) | |
2517 | || reg_in_class_p (no_subreg_reg_operand[1], curr_alt[0]))) | |
2518 | || (! curr_alt_win[0] && curr_alt_win[1] | |
2519 | && REG_P (no_subreg_reg_operand[1]) | |
2520 | && reg_in_class_p (no_subreg_reg_operand[1], curr_alt[0])) | |
2521 | || (curr_alt_win[0] && ! curr_alt_win[1] | |
2522 | && REG_P (no_subreg_reg_operand[0]) | |
2523 | && reg_in_class_p (no_subreg_reg_operand[0], curr_alt[1]) | |
2524 | && (! CONST_POOL_OK_P (curr_operand_mode[1], | |
2525 | no_subreg_reg_operand[1]) | |
2526 | || (targetm.preferred_reload_class | |
2527 | (no_subreg_reg_operand[1], | |
2528 | (enum reg_class) curr_alt[1]) != NO_REGS)) | |
2529 | /* If it is a result of recent elimination in move | |
2530 | insn we can transform it into an add still by | |
2531 | using this alternative. */ | |
2532 | && GET_CODE (no_subreg_reg_operand[1]) != PLUS))) | |
cb1cca12 VM |
2533 | { |
2534 | /* We have a move insn and a new reload insn will be similar | |
2535 | to the current insn. We should avoid such situation as it | |
2536 | results in LRA cycling. */ | |
2537 | overall += LRA_MAX_REJECT; | |
2538 | } | |
55a2c322 VM |
2539 | ok_p = true; |
2540 | curr_alt_dont_inherit_ops_num = 0; | |
2541 | for (nop = 0; nop < early_clobbered_regs_num; nop++) | |
2542 | { | |
2194f7a2 | 2543 | int i, j, clobbered_hard_regno, first_conflict_j, last_conflict_j; |
55a2c322 VM |
2544 | HARD_REG_SET temp_set; |
2545 | ||
2546 | i = early_clobbered_nops[nop]; | |
2547 | if ((! curr_alt_win[i] && ! curr_alt_match_win[i]) | |
2548 | || hard_regno[i] < 0) | |
2549 | continue; | |
1c86bd80 | 2550 | lra_assert (operand_reg[i] != NULL_RTX); |
55a2c322 VM |
2551 | clobbered_hard_regno = hard_regno[i]; |
2552 | CLEAR_HARD_REG_SET (temp_set); | |
2553 | add_to_hard_reg_set (&temp_set, biggest_mode[i], clobbered_hard_regno); | |
2194f7a2 | 2554 | first_conflict_j = last_conflict_j = -1; |
55a2c322 VM |
2555 | for (j = 0; j < n_operands; j++) |
2556 | if (j == i | |
2557 | /* We don't want process insides of match_operator and | |
2558 | match_parallel because otherwise we would process | |
2559 | their operands once again generating a wrong | |
2560 | code. */ | |
2561 | || curr_static_id->operand[j].is_operator) | |
2562 | continue; | |
2563 | else if ((curr_alt_matches[j] == i && curr_alt_match_win[j]) | |
2564 | || (curr_alt_matches[i] == j && curr_alt_match_win[i])) | |
2565 | continue; | |
1c86bd80 VM |
2566 | /* If we don't reload j-th operand, check conflicts. */ |
2567 | else if ((curr_alt_win[j] || curr_alt_match_win[j]) | |
2568 | && uses_hard_regs_p (*curr_id->operand_loc[j], temp_set)) | |
2194f7a2 VM |
2569 | { |
2570 | if (first_conflict_j < 0) | |
2571 | first_conflict_j = j; | |
2572 | last_conflict_j = j; | |
2573 | } | |
2574 | if (last_conflict_j < 0) | |
55a2c322 | 2575 | continue; |
1c86bd80 VM |
2576 | /* If earlyclobber operand conflicts with another |
2577 | non-matching operand which is actually the same register | |
2578 | as the earlyclobber operand, it is better to reload the | |
2579 | another operand as an operand matching the earlyclobber | |
2580 | operand can be also the same. */ | |
2194f7a2 | 2581 | if (first_conflict_j == last_conflict_j |
e78dbb4a MS |
2582 | && operand_reg[last_conflict_j] != NULL_RTX |
2583 | && ! curr_alt_match_win[last_conflict_j] | |
2194f7a2 | 2584 | && REGNO (operand_reg[i]) == REGNO (operand_reg[last_conflict_j])) |
1c86bd80 | 2585 | { |
2194f7a2 VM |
2586 | curr_alt_win[last_conflict_j] = false; |
2587 | curr_alt_dont_inherit_ops[curr_alt_dont_inherit_ops_num++] | |
2588 | = last_conflict_j; | |
1c86bd80 | 2589 | losers++; |
deca73f5 VM |
2590 | /* Early clobber was already reflected in REJECT. */ |
2591 | lra_assert (reject > 0); | |
cb1cca12 VM |
2592 | if (lra_dump_file != NULL) |
2593 | fprintf | |
2594 | (lra_dump_file, | |
2595 | " %d Conflict early clobber reload: reject--\n", | |
2596 | i); | |
deca73f5 VM |
2597 | reject--; |
2598 | overall += LRA_LOSER_COST_FACTOR - 1; | |
1c86bd80 | 2599 | } |
55a2c322 VM |
2600 | else |
2601 | { | |
1c86bd80 VM |
2602 | /* We need to reload early clobbered register and the |
2603 | matched registers. */ | |
2604 | for (j = 0; j < n_operands; j++) | |
2605 | if (curr_alt_matches[j] == i) | |
2606 | { | |
2607 | curr_alt_match_win[j] = false; | |
2608 | losers++; | |
2609 | overall += LRA_LOSER_COST_FACTOR; | |
2610 | } | |
2611 | if (! curr_alt_match_win[i]) | |
2612 | curr_alt_dont_inherit_ops[curr_alt_dont_inherit_ops_num++] = i; | |
2613 | else | |
2614 | { | |
2615 | /* Remember pseudos used for match reloads are never | |
2616 | inherited. */ | |
2617 | lra_assert (curr_alt_matches[i] >= 0); | |
2618 | curr_alt_win[curr_alt_matches[i]] = false; | |
2619 | } | |
2620 | curr_alt_win[i] = curr_alt_match_win[i] = false; | |
2621 | losers++; | |
deca73f5 VM |
2622 | /* Early clobber was already reflected in REJECT. */ |
2623 | lra_assert (reject > 0); | |
cb1cca12 VM |
2624 | if (lra_dump_file != NULL) |
2625 | fprintf | |
2626 | (lra_dump_file, | |
2627 | " %d Matched conflict early clobber reloads:" | |
2628 | "reject--\n", | |
2629 | i); | |
deca73f5 VM |
2630 | reject--; |
2631 | overall += LRA_LOSER_COST_FACTOR - 1; | |
55a2c322 | 2632 | } |
55a2c322 | 2633 | } |
deca73f5 | 2634 | if (lra_dump_file != NULL) |
36ff9dfb VM |
2635 | fprintf (lra_dump_file, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n", |
2636 | nalt, overall, losers, reload_nregs); | |
deca73f5 | 2637 | |
55a2c322 VM |
2638 | /* If this alternative can be made to work by reloading, and it |
2639 | needs less reloading than the others checked so far, record | |
2640 | it as the chosen goal for reloading. */ | |
2641 | if ((best_losers != 0 && losers == 0) | |
2642 | || (((best_losers == 0 && losers == 0) | |
2643 | || (best_losers != 0 && losers != 0)) | |
2644 | && (best_overall > overall | |
2645 | || (best_overall == overall | |
2646 | /* If the cost of the reloads is the same, | |
2647 | prefer alternative which requires minimal | |
36ff9dfb VM |
2648 | number of reload regs. */ |
2649 | && (reload_nregs < best_reload_nregs | |
2650 | || (reload_nregs == best_reload_nregs | |
f15feaf9 VM |
2651 | && (best_reload_sum < reload_sum |
2652 | || (best_reload_sum == reload_sum | |
2653 | && nalt < goal_alt_number)))))))) | |
55a2c322 VM |
2654 | { |
2655 | for (nop = 0; nop < n_operands; nop++) | |
2656 | { | |
2657 | goal_alt_win[nop] = curr_alt_win[nop]; | |
2658 | goal_alt_match_win[nop] = curr_alt_match_win[nop]; | |
2659 | goal_alt_matches[nop] = curr_alt_matches[nop]; | |
2660 | goal_alt[nop] = curr_alt[nop]; | |
2661 | goal_alt_offmemok[nop] = curr_alt_offmemok[nop]; | |
2662 | } | |
2663 | goal_alt_dont_inherit_ops_num = curr_alt_dont_inherit_ops_num; | |
2664 | for (nop = 0; nop < curr_alt_dont_inherit_ops_num; nop++) | |
2665 | goal_alt_dont_inherit_ops[nop] = curr_alt_dont_inherit_ops[nop]; | |
2666 | goal_alt_swapped = curr_swapped; | |
2667 | best_overall = overall; | |
2668 | best_losers = losers; | |
55a2c322 VM |
2669 | best_reload_nregs = reload_nregs; |
2670 | best_reload_sum = reload_sum; | |
2671 | goal_alt_number = nalt; | |
2672 | } | |
2673 | if (losers == 0) | |
2674 | /* Everything is satisfied. Do not process alternatives | |
f4eafc30 | 2675 | anymore. */ |
55a2c322 VM |
2676 | break; |
2677 | fail: | |
2678 | ; | |
2679 | } | |
2680 | return ok_p; | |
2681 | } | |
2682 | ||
c31d2d11 RS |
2683 | /* Make reload base reg from address AD. */ |
2684 | static rtx | |
2685 | base_to_reg (struct address_info *ad) | |
2686 | { | |
2687 | enum reg_class cl; | |
2688 | int code = -1; | |
2689 | rtx new_inner = NULL_RTX; | |
2690 | rtx new_reg = NULL_RTX; | |
fee3e72c DM |
2691 | rtx_insn *insn; |
2692 | rtx_insn *last_insn = get_last_insn(); | |
c31d2d11 RS |
2693 | |
2694 | lra_assert (ad->base == ad->base_term && ad->disp == ad->disp_term); | |
2695 | cl = base_reg_class (ad->mode, ad->as, ad->base_outer_code, | |
2696 | get_index_code (ad)); | |
2697 | new_reg = lra_create_new_reg (GET_MODE (*ad->base_term), NULL_RTX, | |
2698 | cl, "base"); | |
2699 | new_inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), new_reg, | |
2700 | ad->disp_term == NULL | |
2701 | ? gen_int_mode (0, ad->mode) | |
2702 | : *ad->disp_term); | |
2703 | if (!valid_address_p (ad->mode, new_inner, ad->as)) | |
2704 | return NULL_RTX; | |
f7df4a84 | 2705 | insn = emit_insn (gen_rtx_SET (new_reg, *ad->base_term)); |
c31d2d11 RS |
2706 | code = recog_memoized (insn); |
2707 | if (code < 0) | |
2708 | { | |
2709 | delete_insns_since (last_insn); | |
2710 | return NULL_RTX; | |
2711 | } | |
2712 | ||
2713 | return new_inner; | |
2714 | } | |
2715 | ||
277f65de | 2716 | /* Make reload base reg + disp from address AD. Return the new pseudo. */ |
55a2c322 | 2717 | static rtx |
277f65de | 2718 | base_plus_disp_to_reg (struct address_info *ad) |
55a2c322 VM |
2719 | { |
2720 | enum reg_class cl; | |
2721 | rtx new_reg; | |
2722 | ||
277f65de RS |
2723 | lra_assert (ad->base == ad->base_term && ad->disp == ad->disp_term); |
2724 | cl = base_reg_class (ad->mode, ad->as, ad->base_outer_code, | |
2725 | get_index_code (ad)); | |
2726 | new_reg = lra_create_new_reg (GET_MODE (*ad->base_term), NULL_RTX, | |
2727 | cl, "base + disp"); | |
2728 | lra_emit_add (new_reg, *ad->base_term, *ad->disp_term); | |
55a2c322 VM |
2729 | return new_reg; |
2730 | } | |
2731 | ||
6e071b1e VM |
2732 | /* Make reload of index part of address AD. Return the new |
2733 | pseudo. */ | |
2734 | static rtx | |
2735 | index_part_to_reg (struct address_info *ad) | |
2736 | { | |
2737 | rtx new_reg; | |
2738 | ||
2739 | new_reg = lra_create_new_reg (GET_MODE (*ad->index), NULL_RTX, | |
2740 | INDEX_REG_CLASS, "index term"); | |
2741 | expand_mult (GET_MODE (*ad->index), *ad->index_term, | |
2742 | GEN_INT (get_index_scale (ad)), new_reg, 1); | |
2743 | return new_reg; | |
2744 | } | |
2745 | ||
277f65de RS |
2746 | /* Return true if we can add a displacement to address AD, even if that |
2747 | makes the address invalid. The fix-up code requires any new address | |
2748 | to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */ | |
02ea4bf4 | 2749 | static bool |
277f65de | 2750 | can_add_disp_p (struct address_info *ad) |
02ea4bf4 | 2751 | { |
277f65de RS |
2752 | return (!ad->autoinc_p |
2753 | && ad->segment == NULL | |
2754 | && ad->base == ad->base_term | |
2755 | && ad->disp == ad->disp_term); | |
02ea4bf4 RS |
2756 | } |
2757 | ||
277f65de RS |
2758 | /* Make equiv substitution in address AD. Return true if a substitution |
2759 | was made. */ | |
55a2c322 | 2760 | static bool |
277f65de | 2761 | equiv_address_substitution (struct address_info *ad) |
55a2c322 | 2762 | { |
277f65de | 2763 | rtx base_reg, new_base_reg, index_reg, new_index_reg, *base_term, *index_term; |
55a2c322 VM |
2764 | HOST_WIDE_INT disp, scale; |
2765 | bool change_p; | |
2766 | ||
277f65de RS |
2767 | base_term = strip_subreg (ad->base_term); |
2768 | if (base_term == NULL) | |
55a2c322 VM |
2769 | base_reg = new_base_reg = NULL_RTX; |
2770 | else | |
2771 | { | |
277f65de | 2772 | base_reg = *base_term; |
8d49e7ef | 2773 | new_base_reg = get_equiv_with_elimination (base_reg, curr_insn); |
55a2c322 | 2774 | } |
277f65de RS |
2775 | index_term = strip_subreg (ad->index_term); |
2776 | if (index_term == NULL) | |
55a2c322 VM |
2777 | index_reg = new_index_reg = NULL_RTX; |
2778 | else | |
2779 | { | |
277f65de | 2780 | index_reg = *index_term; |
8d49e7ef | 2781 | new_index_reg = get_equiv_with_elimination (index_reg, curr_insn); |
55a2c322 VM |
2782 | } |
2783 | if (base_reg == new_base_reg && index_reg == new_index_reg) | |
2784 | return false; | |
2785 | disp = 0; | |
2786 | change_p = false; | |
2787 | if (lra_dump_file != NULL) | |
2788 | { | |
2789 | fprintf (lra_dump_file, "Changing address in insn %d ", | |
2790 | INSN_UID (curr_insn)); | |
cfbeaedf | 2791 | dump_value_slim (lra_dump_file, *ad->outer, 1); |
55a2c322 VM |
2792 | } |
2793 | if (base_reg != new_base_reg) | |
2794 | { | |
2795 | if (REG_P (new_base_reg)) | |
2796 | { | |
277f65de | 2797 | *base_term = new_base_reg; |
55a2c322 VM |
2798 | change_p = true; |
2799 | } | |
2800 | else if (GET_CODE (new_base_reg) == PLUS | |
2801 | && REG_P (XEXP (new_base_reg, 0)) | |
02ea4bf4 | 2802 | && CONST_INT_P (XEXP (new_base_reg, 1)) |
277f65de | 2803 | && can_add_disp_p (ad)) |
55a2c322 VM |
2804 | { |
2805 | disp += INTVAL (XEXP (new_base_reg, 1)); | |
277f65de | 2806 | *base_term = XEXP (new_base_reg, 0); |
55a2c322 VM |
2807 | change_p = true; |
2808 | } | |
277f65de RS |
2809 | if (ad->base_term2 != NULL) |
2810 | *ad->base_term2 = *ad->base_term; | |
55a2c322 | 2811 | } |
55a2c322 VM |
2812 | if (index_reg != new_index_reg) |
2813 | { | |
2814 | if (REG_P (new_index_reg)) | |
2815 | { | |
277f65de | 2816 | *index_term = new_index_reg; |
55a2c322 VM |
2817 | change_p = true; |
2818 | } | |
2819 | else if (GET_CODE (new_index_reg) == PLUS | |
2820 | && REG_P (XEXP (new_index_reg, 0)) | |
02ea4bf4 | 2821 | && CONST_INT_P (XEXP (new_index_reg, 1)) |
277f65de | 2822 | && can_add_disp_p (ad) |
02ea4bf4 | 2823 | && (scale = get_index_scale (ad))) |
55a2c322 VM |
2824 | { |
2825 | disp += INTVAL (XEXP (new_index_reg, 1)) * scale; | |
277f65de | 2826 | *index_term = XEXP (new_index_reg, 0); |
55a2c322 VM |
2827 | change_p = true; |
2828 | } | |
2829 | } | |
2830 | if (disp != 0) | |
2831 | { | |
277f65de RS |
2832 | if (ad->disp != NULL) |
2833 | *ad->disp = plus_constant (GET_MODE (*ad->inner), *ad->disp, disp); | |
55a2c322 VM |
2834 | else |
2835 | { | |
277f65de RS |
2836 | *ad->inner = plus_constant (GET_MODE (*ad->inner), *ad->inner, disp); |
2837 | update_address (ad); | |
55a2c322 VM |
2838 | } |
2839 | change_p = true; | |
2840 | } | |
2841 | if (lra_dump_file != NULL) | |
2842 | { | |
2843 | if (! change_p) | |
2844 | fprintf (lra_dump_file, " -- no change\n"); | |
2845 | else | |
2846 | { | |
2847 | fprintf (lra_dump_file, " on equiv "); | |
cfbeaedf | 2848 | dump_value_slim (lra_dump_file, *ad->outer, 1); |
55a2c322 VM |
2849 | fprintf (lra_dump_file, "\n"); |
2850 | } | |
2851 | } | |
2852 | return change_p; | |
2853 | } | |
2854 | ||
d9cf932c VM |
2855 | /* Major function to make reloads for an address in operand NOP or |
2856 | check its correctness (If CHECK_ONLY_P is true). The supported | |
2857 | cases are: | |
bd3d34d4 | 2858 | |
5a107a0f VM |
2859 | 1) an address that existed before LRA started, at which point it |
2860 | must have been valid. These addresses are subject to elimination | |
2861 | and may have become invalid due to the elimination offset being out | |
2862 | of range. | |
bd3d34d4 | 2863 | |
5a107a0f VM |
2864 | 2) an address created by forcing a constant to memory |
2865 | (force_const_to_mem). The initial form of these addresses might | |
2866 | not be valid, and it is this function's job to make them valid. | |
bd3d34d4 RS |
2867 | |
2868 | 3) a frame address formed from a register and a (possibly zero) | |
5a107a0f VM |
2869 | constant offset. As above, these addresses might not be valid and |
2870 | this function must make them so. | |
bd3d34d4 RS |
2871 | |
2872 | Add reloads to the lists *BEFORE and *AFTER. We might need to add | |
55a2c322 | 2873 | reloads to *AFTER because of inc/dec, {pre, post} modify in the |
cc8849a1 VM |
2874 | address. Return true for any RTL change. |
2875 | ||
2876 | The function is a helper function which does not produce all | |
d9cf932c VM |
2877 | transformations (when CHECK_ONLY_P is false) which can be |
2878 | necessary. It does just basic steps. To do all necessary | |
2879 | transformations use function process_address. */ | |
55a2c322 | 2880 | static bool |
d9cf932c VM |
2881 | process_address_1 (int nop, bool check_only_p, |
2882 | rtx_insn **before, rtx_insn **after) | |
55a2c322 | 2883 | { |
277f65de RS |
2884 | struct address_info ad; |
2885 | rtx new_reg; | |
55a2c322 VM |
2886 | rtx op = *curr_id->operand_loc[nop]; |
2887 | const char *constraint = curr_static_id->operand[nop].constraint; | |
777e635f | 2888 | enum constraint_num cn = lookup_constraint (constraint); |
d9cf932c | 2889 | bool change_p = false; |
55a2c322 | 2890 | |
823bb054 SB |
2891 | if (MEM_P (op) |
2892 | && GET_MODE (op) == BLKmode | |
2893 | && GET_CODE (XEXP (op, 0)) == SCRATCH) | |
2894 | return false; | |
2895 | ||
8677664e | 2896 | if (insn_extra_address_constraint (cn)) |
277f65de | 2897 | decompose_lea_address (&ad, curr_id->operand_loc[nop]); |
55a2c322 | 2898 | else if (MEM_P (op)) |
277f65de | 2899 | decompose_mem_address (&ad, op); |
55a2c322 VM |
2900 | else if (GET_CODE (op) == SUBREG |
2901 | && MEM_P (SUBREG_REG (op))) | |
277f65de | 2902 | decompose_mem_address (&ad, SUBREG_REG (op)); |
55a2c322 VM |
2903 | else |
2904 | return false; | |
70712859 KK |
2905 | /* If INDEX_REG_CLASS is assigned to base_term already and isn't to |
2906 | index_term, swap them so to avoid assigning INDEX_REG_CLASS to both | |
2907 | when INDEX_REG_CLASS is a single register class. */ | |
2908 | if (ad.base_term != NULL | |
2909 | && ad.index_term != NULL | |
2910 | && ira_class_hard_regs_num[INDEX_REG_CLASS] == 1 | |
2911 | && REG_P (*ad.base_term) | |
2912 | && REG_P (*ad.index_term) | |
2913 | && in_class_p (*ad.base_term, INDEX_REG_CLASS, NULL) | |
2914 | && ! in_class_p (*ad.index_term, INDEX_REG_CLASS, NULL)) | |
2915 | { | |
2916 | std::swap (ad.base, ad.index); | |
2917 | std::swap (ad.base_term, ad.index_term); | |
2918 | } | |
d9cf932c VM |
2919 | if (! check_only_p) |
2920 | change_p = equiv_address_substitution (&ad); | |
277f65de | 2921 | if (ad.base_term != NULL |
55a2c322 | 2922 | && (process_addr_reg |
d9cf932c | 2923 | (ad.base_term, check_only_p, before, |
277f65de RS |
2924 | (ad.autoinc_p |
2925 | && !(REG_P (*ad.base_term) | |
2926 | && find_regno_note (curr_insn, REG_DEAD, | |
2927 | REGNO (*ad.base_term)) != NULL_RTX) | |
55a2c322 | 2928 | ? after : NULL), |
277f65de RS |
2929 | base_reg_class (ad.mode, ad.as, ad.base_outer_code, |
2930 | get_index_code (&ad))))) | |
55a2c322 VM |
2931 | { |
2932 | change_p = true; | |
277f65de RS |
2933 | if (ad.base_term2 != NULL) |
2934 | *ad.base_term2 = *ad.base_term; | |
55a2c322 | 2935 | } |
277f65de | 2936 | if (ad.index_term != NULL |
d9cf932c VM |
2937 | && process_addr_reg (ad.index_term, check_only_p, |
2938 | before, NULL, INDEX_REG_CLASS)) | |
55a2c322 VM |
2939 | change_p = true; |
2940 | ||
777e635f RS |
2941 | /* Target hooks sometimes don't treat extra-constraint addresses as |
2942 | legitimate address_operands, so handle them specially. */ | |
8677664e | 2943 | if (insn_extra_address_constraint (cn) |
777e635f | 2944 | && satisfies_address_constraint_p (&ad, cn)) |
2c62cbaa | 2945 | return change_p; |
2c62cbaa | 2946 | |
d9cf932c VM |
2947 | if (check_only_p) |
2948 | return change_p; | |
2949 | ||
277f65de | 2950 | /* There are three cases where the shape of *AD.INNER may now be invalid: |
bd3d34d4 RS |
2951 | |
2952 | 1) the original address was valid, but either elimination or | |
5a107a0f VM |
2953 | equiv_address_substitution was applied and that made |
2954 | the address invalid. | |
bd3d34d4 RS |
2955 | |
2956 | 2) the address is an invalid symbolic address created by | |
5a107a0f | 2957 | force_const_to_mem. |
bd3d34d4 RS |
2958 | |
2959 | 3) the address is a frame address with an invalid offset. | |
2960 | ||
c31d2d11 RS |
2961 | 4) the address is a frame address with an invalid base. |
2962 | ||
2c62cbaa VM |
2963 | All these cases involve a non-autoinc address, so there is no |
2964 | point revalidating other types. */ | |
2965 | if (ad.autoinc_p || valid_address_p (&ad)) | |
55a2c322 VM |
2966 | return change_p; |
2967 | ||
bd3d34d4 RS |
2968 | /* Any index existed before LRA started, so we can assume that the |
2969 | presence and shape of the index is valid. */ | |
55a2c322 | 2970 | push_to_sequence (*before); |
2c62cbaa | 2971 | lra_assert (ad.disp == ad.disp_term); |
277f65de | 2972 | if (ad.base == NULL) |
55a2c322 | 2973 | { |
277f65de | 2974 | if (ad.index == NULL) |
55a2c322 | 2975 | { |
95831c01 VM |
2976 | rtx_insn *insn; |
2977 | rtx_insn *last = get_last_insn (); | |
55a2c322 | 2978 | int code = -1; |
277f65de RS |
2979 | enum reg_class cl = base_reg_class (ad.mode, ad.as, |
2980 | SCRATCH, SCRATCH); | |
2c62cbaa | 2981 | rtx addr = *ad.inner; |
277f65de | 2982 | |
2c62cbaa | 2983 | new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "addr"); |
d0b2266a TS |
2984 | if (HAVE_lo_sum) |
2985 | { | |
d0b2266a TS |
2986 | /* addr => lo_sum (new_base, addr), case (2) above. */ |
2987 | insn = emit_insn (gen_rtx_SET | |
2988 | (new_reg, | |
2989 | gen_rtx_HIGH (Pmode, copy_rtx (addr)))); | |
2990 | code = recog_memoized (insn); | |
2991 | if (code >= 0) | |
2992 | { | |
2993 | *ad.inner = gen_rtx_LO_SUM (Pmode, new_reg, addr); | |
2994 | if (! valid_address_p (ad.mode, *ad.outer, ad.as)) | |
2995 | { | |
2996 | /* Try to put lo_sum into register. */ | |
2997 | insn = emit_insn (gen_rtx_SET | |
2998 | (new_reg, | |
2999 | gen_rtx_LO_SUM (Pmode, new_reg, addr))); | |
3000 | code = recog_memoized (insn); | |
3001 | if (code >= 0) | |
3002 | { | |
3003 | *ad.inner = new_reg; | |
3004 | if (! valid_address_p (ad.mode, *ad.outer, ad.as)) | |
3005 | { | |
3006 | *ad.inner = addr; | |
3007 | code = -1; | |
3008 | } | |
3009 | } | |
3010 | ||
3011 | } | |
3012 | } | |
3013 | if (code < 0) | |
3014 | delete_insns_since (last); | |
3015 | } | |
3016 | ||
55a2c322 VM |
3017 | if (code < 0) |
3018 | { | |
2c62cbaa VM |
3019 | /* addr => new_base, case (2) above. */ |
3020 | lra_emit_move (new_reg, addr); | |
95831c01 VM |
3021 | |
3022 | for (insn = last == NULL_RTX ? get_insns () : NEXT_INSN (last); | |
3023 | insn != NULL_RTX; | |
3024 | insn = NEXT_INSN (insn)) | |
3025 | if (recog_memoized (insn) < 0) | |
3026 | break; | |
3027 | if (insn != NULL_RTX) | |
3028 | { | |
3029 | /* Do nothing if we cannot generate right insns. | |
3030 | This is analogous to reload pass behaviour. */ | |
3031 | delete_insns_since (last); | |
3032 | end_sequence (); | |
3033 | return false; | |
3034 | } | |
2c62cbaa | 3035 | *ad.inner = new_reg; |
55a2c322 VM |
3036 | } |
3037 | } | |
3038 | else | |
3039 | { | |
bd3d34d4 RS |
3040 | /* index * scale + disp => new base + index * scale, |
3041 | case (1) above. */ | |
277f65de RS |
3042 | enum reg_class cl = base_reg_class (ad.mode, ad.as, PLUS, |
3043 | GET_CODE (*ad.index)); | |
55a2c322 VM |
3044 | |
3045 | lra_assert (INDEX_REG_CLASS != NO_REGS); | |
3046 | new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "disp"); | |
277f65de RS |
3047 | lra_emit_move (new_reg, *ad.disp); |
3048 | *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), | |
3049 | new_reg, *ad.index); | |
55a2c322 VM |
3050 | } |
3051 | } | |
277f65de | 3052 | else if (ad.index == NULL) |
55a2c322 | 3053 | { |
5a107a0f VM |
3054 | int regno; |
3055 | enum reg_class cl; | |
cfa434f6 DM |
3056 | rtx set; |
3057 | rtx_insn *insns, *last_insn; | |
c31d2d11 RS |
3058 | /* Try to reload base into register only if the base is invalid |
3059 | for the address but with valid offset, case (4) above. */ | |
3060 | start_sequence (); | |
3061 | new_reg = base_to_reg (&ad); | |
3062 | ||
bd3d34d4 | 3063 | /* base + disp => new base, cases (1) and (3) above. */ |
55a2c322 VM |
3064 | /* Another option would be to reload the displacement into an |
3065 | index register. However, postreload has code to optimize | |
3066 | address reloads that have the same base and different | |
3067 | displacements, so reloading into an index register would | |
3068 | not necessarily be a win. */ | |
c31d2d11 RS |
3069 | if (new_reg == NULL_RTX) |
3070 | new_reg = base_plus_disp_to_reg (&ad); | |
5a107a0f VM |
3071 | insns = get_insns (); |
3072 | last_insn = get_last_insn (); | |
3073 | /* If we generated at least two insns, try last insn source as | |
3074 | an address. If we succeed, we generate one less insn. */ | |
3075 | if (last_insn != insns && (set = single_set (last_insn)) != NULL_RTX | |
3076 | && GET_CODE (SET_SRC (set)) == PLUS | |
3077 | && REG_P (XEXP (SET_SRC (set), 0)) | |
3078 | && CONSTANT_P (XEXP (SET_SRC (set), 1))) | |
3079 | { | |
3080 | *ad.inner = SET_SRC (set); | |
3081 | if (valid_address_p (ad.mode, *ad.outer, ad.as)) | |
3082 | { | |
3083 | *ad.base_term = XEXP (SET_SRC (set), 0); | |
3084 | *ad.disp_term = XEXP (SET_SRC (set), 1); | |
3085 | cl = base_reg_class (ad.mode, ad.as, ad.base_outer_code, | |
3086 | get_index_code (&ad)); | |
3087 | regno = REGNO (*ad.base_term); | |
3088 | if (regno >= FIRST_PSEUDO_REGISTER | |
3089 | && cl != lra_get_allocno_class (regno)) | |
a2d0d374 | 3090 | lra_change_class (regno, cl, " Change to", true); |
5a107a0f VM |
3091 | new_reg = SET_SRC (set); |
3092 | delete_insns_since (PREV_INSN (last_insn)); | |
3093 | } | |
3094 | } | |
14133a4d KK |
3095 | /* Try if target can split displacement into legitimite new disp |
3096 | and offset. If it's the case, we replace the last insn with | |
3097 | insns for base + offset => new_reg and set new_reg + new disp | |
3098 | to *ad.inner. */ | |
3099 | last_insn = get_last_insn (); | |
3100 | if ((set = single_set (last_insn)) != NULL_RTX | |
3101 | && GET_CODE (SET_SRC (set)) == PLUS | |
3102 | && REG_P (XEXP (SET_SRC (set), 0)) | |
3103 | && REGNO (XEXP (SET_SRC (set), 0)) < FIRST_PSEUDO_REGISTER | |
3104 | && CONST_INT_P (XEXP (SET_SRC (set), 1))) | |
3105 | { | |
3106 | rtx addend, disp = XEXP (SET_SRC (set), 1); | |
3107 | if (targetm.legitimize_address_displacement (&disp, &addend, | |
3108 | ad.mode)) | |
3109 | { | |
3110 | rtx_insn *new_insns; | |
3111 | start_sequence (); | |
3112 | lra_emit_add (new_reg, XEXP (SET_SRC (set), 0), addend); | |
3113 | new_insns = get_insns (); | |
3114 | end_sequence (); | |
3115 | new_reg = gen_rtx_PLUS (Pmode, new_reg, disp); | |
3116 | delete_insns_since (PREV_INSN (last_insn)); | |
3117 | add_insn (new_insns); | |
3118 | insns = get_insns (); | |
3119 | } | |
3120 | } | |
5a107a0f VM |
3121 | end_sequence (); |
3122 | emit_insn (insns); | |
277f65de | 3123 | *ad.inner = new_reg; |
55a2c322 | 3124 | } |
6e071b1e | 3125 | else if (ad.disp_term != NULL) |
55a2c322 | 3126 | { |
bd3d34d4 RS |
3127 | /* base + scale * index + disp => new base + scale * index, |
3128 | case (1) above. */ | |
277f65de RS |
3129 | new_reg = base_plus_disp_to_reg (&ad); |
3130 | *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), | |
3131 | new_reg, *ad.index); | |
55a2c322 | 3132 | } |
5a770e01 VM |
3133 | else if (get_index_scale (&ad) == 1) |
3134 | { | |
3135 | /* The last transformation to one reg will be made in | |
3136 | curr_insn_transform function. */ | |
3137 | end_sequence (); | |
3138 | return false; | |
3139 | } | |
6e071b1e VM |
3140 | else |
3141 | { | |
3142 | /* base + scale * index => base + new_reg, | |
3143 | case (1) above. | |
3144 | Index part of address may become invalid. For example, we | |
3145 | changed pseudo on the equivalent memory and a subreg of the | |
3146 | pseudo onto the memory of different mode for which the scale is | |
3147 | prohibitted. */ | |
3148 | new_reg = index_part_to_reg (&ad); | |
3149 | *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), | |
3150 | *ad.base_term, new_reg); | |
3151 | } | |
55a2c322 VM |
3152 | *before = get_insns (); |
3153 | end_sequence (); | |
3154 | return true; | |
3155 | } | |
3156 | ||
d9cf932c VM |
3157 | /* If CHECK_ONLY_P is false, do address reloads until it is necessary. |
3158 | Use process_address_1 as a helper function. Return true for any | |
3159 | RTL changes. | |
3160 | ||
3161 | If CHECK_ONLY_P is true, just check address correctness. Return | |
3162 | false if the address correct. */ | |
cc8849a1 | 3163 | static bool |
d9cf932c VM |
3164 | process_address (int nop, bool check_only_p, |
3165 | rtx_insn **before, rtx_insn **after) | |
cc8849a1 VM |
3166 | { |
3167 | bool res = false; | |
3168 | ||
d9cf932c VM |
3169 | while (process_address_1 (nop, check_only_p, before, after)) |
3170 | { | |
3171 | if (check_only_p) | |
3172 | return true; | |
3173 | res = true; | |
3174 | } | |
cc8849a1 VM |
3175 | return res; |
3176 | } | |
3177 | ||
55a2c322 VM |
3178 | /* Emit insns to reload VALUE into a new register. VALUE is an |
3179 | auto-increment or auto-decrement RTX whose operand is a register or | |
3180 | memory location; so reloading involves incrementing that location. | |
3181 | IN is either identical to VALUE, or some cheaper place to reload | |
3182 | value being incremented/decremented from. | |
3183 | ||
3184 | INC_AMOUNT is the number to increment or decrement by (always | |
3185 | positive and ignored for POST_MODIFY/PRE_MODIFY). | |
3186 | ||
3187 | Return pseudo containing the result. */ | |
3188 | static rtx | |
3189 | emit_inc (enum reg_class new_rclass, rtx in, rtx value, int inc_amount) | |
3190 | { | |
3191 | /* REG or MEM to be copied and incremented. */ | |
3192 | rtx incloc = XEXP (value, 0); | |
3193 | /* Nonzero if increment after copying. */ | |
3194 | int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC | |
3195 | || GET_CODE (value) == POST_MODIFY); | |
cfa434f6 | 3196 | rtx_insn *last; |
55a2c322 | 3197 | rtx inc; |
647d790d | 3198 | rtx_insn *add_insn; |
55a2c322 VM |
3199 | int code; |
3200 | rtx real_in = in == value ? incloc : in; | |
3201 | rtx result; | |
3202 | bool plus_p = true; | |
3203 | ||
3204 | if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY) | |
3205 | { | |
3206 | lra_assert (GET_CODE (XEXP (value, 1)) == PLUS | |
3207 | || GET_CODE (XEXP (value, 1)) == MINUS); | |
3208 | lra_assert (rtx_equal_p (XEXP (XEXP (value, 1), 0), XEXP (value, 0))); | |
3209 | plus_p = GET_CODE (XEXP (value, 1)) == PLUS; | |
3210 | inc = XEXP (XEXP (value, 1), 1); | |
3211 | } | |
3212 | else | |
3213 | { | |
3214 | if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC) | |
3215 | inc_amount = -inc_amount; | |
3216 | ||
3217 | inc = GEN_INT (inc_amount); | |
3218 | } | |
3219 | ||
3220 | if (! post && REG_P (incloc)) | |
3221 | result = incloc; | |
3222 | else | |
3223 | result = lra_create_new_reg (GET_MODE (value), value, new_rclass, | |
3224 | "INC/DEC result"); | |
3225 | ||
3226 | if (real_in != result) | |
3227 | { | |
3228 | /* First copy the location to the result register. */ | |
3229 | lra_assert (REG_P (result)); | |
3230 | emit_insn (gen_move_insn (result, real_in)); | |
3231 | } | |
3232 | ||
3233 | /* We suppose that there are insns to add/sub with the constant | |
3234 | increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the | |
3235 | old reload worked with this assumption. If the assumption | |
3236 | becomes wrong, we should use approach in function | |
3237 | base_plus_disp_to_reg. */ | |
3238 | if (in == value) | |
3239 | { | |
3240 | /* See if we can directly increment INCLOC. */ | |
3241 | last = get_last_insn (); | |
3242 | add_insn = emit_insn (plus_p | |
3243 | ? gen_add2_insn (incloc, inc) | |
3244 | : gen_sub2_insn (incloc, inc)); | |
3245 | ||
3246 | code = recog_memoized (add_insn); | |
3247 | if (code >= 0) | |
3248 | { | |
3249 | if (! post && result != incloc) | |
3250 | emit_insn (gen_move_insn (result, incloc)); | |
3251 | return result; | |
3252 | } | |
3253 | delete_insns_since (last); | |
3254 | } | |
3255 | ||
3256 | /* If couldn't do the increment directly, must increment in RESULT. | |
3257 | The way we do this depends on whether this is pre- or | |
3258 | post-increment. For pre-increment, copy INCLOC to the reload | |
3259 | register, increment it there, then save back. */ | |
3260 | if (! post) | |
3261 | { | |
3262 | if (real_in != result) | |
3263 | emit_insn (gen_move_insn (result, real_in)); | |
3264 | if (plus_p) | |
3265 | emit_insn (gen_add2_insn (result, inc)); | |
3266 | else | |
3267 | emit_insn (gen_sub2_insn (result, inc)); | |
3268 | if (result != incloc) | |
3269 | emit_insn (gen_move_insn (incloc, result)); | |
3270 | } | |
3271 | else | |
3272 | { | |
3273 | /* Post-increment. | |
3274 | ||
3275 | Because this might be a jump insn or a compare, and because | |
3276 | RESULT may not be available after the insn in an input | |
3277 | reload, we must do the incrementing before the insn being | |
3278 | reloaded for. | |
3279 | ||
3280 | We have already copied IN to RESULT. Increment the copy in | |
3281 | RESULT, save that back, then decrement RESULT so it has | |
3282 | the original value. */ | |
3283 | if (plus_p) | |
3284 | emit_insn (gen_add2_insn (result, inc)); | |
3285 | else | |
3286 | emit_insn (gen_sub2_insn (result, inc)); | |
3287 | emit_insn (gen_move_insn (incloc, result)); | |
3288 | /* Restore non-modified value for the result. We prefer this | |
3289 | way because it does not require an additional hard | |
3290 | register. */ | |
3291 | if (plus_p) | |
3292 | { | |
3293 | if (CONST_INT_P (inc)) | |
69db2d57 RS |
3294 | emit_insn (gen_add2_insn (result, |
3295 | gen_int_mode (-INTVAL (inc), | |
3296 | GET_MODE (result)))); | |
55a2c322 VM |
3297 | else |
3298 | emit_insn (gen_sub2_insn (result, inc)); | |
3299 | } | |
3300 | else | |
3301 | emit_insn (gen_add2_insn (result, inc)); | |
3302 | } | |
3303 | return result; | |
3304 | } | |
3305 | ||
2c62cbaa VM |
3306 | /* Return true if the current move insn does not need processing as we |
3307 | already know that it satisfies its constraints. */ | |
3308 | static bool | |
3309 | simple_move_p (void) | |
3310 | { | |
3311 | rtx dest, src; | |
3312 | enum reg_class dclass, sclass; | |
3313 | ||
3314 | lra_assert (curr_insn_set != NULL_RTX); | |
3315 | dest = SET_DEST (curr_insn_set); | |
3316 | src = SET_SRC (curr_insn_set); | |
3317 | return ((dclass = get_op_class (dest)) != NO_REGS | |
3318 | && (sclass = get_op_class (src)) != NO_REGS | |
3319 | /* The backend guarantees that register moves of cost 2 | |
3320 | never need reloads. */ | |
03b9b5ce | 3321 | && targetm.register_move_cost (GET_MODE (src), sclass, dclass) == 2); |
2c62cbaa VM |
3322 | } |
3323 | ||
55a2c322 VM |
3324 | /* Swap operands NOP and NOP + 1. */ |
3325 | static inline void | |
3326 | swap_operands (int nop) | |
3327 | { | |
fab27f52 MM |
3328 | std::swap (curr_operand_mode[nop], curr_operand_mode[nop + 1]); |
3329 | std::swap (original_subreg_reg_mode[nop], original_subreg_reg_mode[nop + 1]); | |
3330 | std::swap (*curr_id->operand_loc[nop], *curr_id->operand_loc[nop + 1]); | |
55a2c322 VM |
3331 | /* Swap the duplicates too. */ |
3332 | lra_update_dup (curr_id, nop); | |
3333 | lra_update_dup (curr_id, nop + 1); | |
3334 | } | |
3335 | ||
3336 | /* Main entry point of the constraint code: search the body of the | |
3337 | current insn to choose the best alternative. It is mimicking insn | |
3338 | alternative cost calculation model of former reload pass. That is | |
3339 | because machine descriptions were written to use this model. This | |
3340 | model can be changed in future. Make commutative operand exchange | |
3341 | if it is chosen. | |
3342 | ||
d9cf932c VM |
3343 | if CHECK_ONLY_P is false, do RTL changes to satisfy the |
3344 | constraints. Return true if any change happened during function | |
3345 | call. | |
3346 | ||
3347 | If CHECK_ONLY_P is true then don't do any transformation. Just | |
3348 | check that the insn satisfies all constraints. If the insn does | |
3349 | not satisfy any constraint, return true. */ | |
55a2c322 | 3350 | static bool |
d9cf932c | 3351 | curr_insn_transform (bool check_only_p) |
55a2c322 VM |
3352 | { |
3353 | int i, j, k; | |
3354 | int n_operands; | |
3355 | int n_alternatives; | |
3356 | int commutative; | |
3357 | signed char goal_alt_matched[MAX_RECOG_OPERANDS][MAX_RECOG_OPERANDS]; | |
511dcace | 3358 | signed char match_inputs[MAX_RECOG_OPERANDS + 1]; |
cfa434f6 | 3359 | rtx_insn *before, *after; |
55a2c322 VM |
3360 | bool alt_p = false; |
3361 | /* Flag that the insn has been changed through a transformation. */ | |
3362 | bool change_p; | |
3363 | bool sec_mem_p; | |
3364 | #ifdef SECONDARY_MEMORY_NEEDED | |
3365 | bool use_sec_mem_p; | |
3366 | #endif | |
3367 | int max_regno_before; | |
3368 | int reused_alternative_num; | |
3369 | ||
2c62cbaa VM |
3370 | curr_insn_set = single_set (curr_insn); |
3371 | if (curr_insn_set != NULL_RTX && simple_move_p ()) | |
3372 | return false; | |
3373 | ||
55a2c322 VM |
3374 | no_input_reloads_p = no_output_reloads_p = false; |
3375 | goal_alt_number = -1; | |
2c62cbaa | 3376 | change_p = sec_mem_p = false; |
55a2c322 VM |
3377 | /* JUMP_INSNs and CALL_INSNs are not allowed to have any output |
3378 | reloads; neither are insns that SET cc0. Insns that use CC0 are | |
3379 | not allowed to have any input reloads. */ | |
3380 | if (JUMP_P (curr_insn) || CALL_P (curr_insn)) | |
3381 | no_output_reloads_p = true; | |
3382 | ||
058eb3b0 | 3383 | if (HAVE_cc0 && reg_referenced_p (cc0_rtx, PATTERN (curr_insn))) |
55a2c322 | 3384 | no_input_reloads_p = true; |
058eb3b0 | 3385 | if (HAVE_cc0 && reg_set_p (cc0_rtx, PATTERN (curr_insn))) |
55a2c322 | 3386 | no_output_reloads_p = true; |
55a2c322 VM |
3387 | |
3388 | n_operands = curr_static_id->n_operands; | |
3389 | n_alternatives = curr_static_id->n_alternatives; | |
3390 | ||
3391 | /* Just return "no reloads" if insn has no operands with | |
3392 | constraints. */ | |
3393 | if (n_operands == 0 || n_alternatives == 0) | |
3394 | return false; | |
3395 | ||
3396 | max_regno_before = max_reg_num (); | |
3397 | ||
3398 | for (i = 0; i < n_operands; i++) | |
3399 | { | |
3400 | goal_alt_matched[i][0] = -1; | |
3401 | goal_alt_matches[i] = -1; | |
3402 | } | |
3403 | ||
3404 | commutative = curr_static_id->commutative; | |
3405 | ||
3406 | /* Now see what we need for pseudos that didn't get hard regs or got | |
3407 | the wrong kind of hard reg. For this, we must consider all the | |
3408 | operands together against the register constraints. */ | |
3409 | ||
821b7577 | 3410 | best_losers = best_overall = INT_MAX; |
36ff9dfb | 3411 | best_reload_sum = 0; |
55a2c322 VM |
3412 | |
3413 | curr_swapped = false; | |
3414 | goal_alt_swapped = false; | |
3415 | ||
d9cf932c VM |
3416 | if (! check_only_p) |
3417 | /* Make equivalence substitution and memory subreg elimination | |
3418 | before address processing because an address legitimacy can | |
3419 | depend on memory mode. */ | |
3420 | for (i = 0; i < n_operands; i++) | |
3421 | { | |
0b87be09 | 3422 | rtx op, subst, old; |
d9cf932c | 3423 | bool op_change_p = false; |
0b87be09 VM |
3424 | |
3425 | if (curr_static_id->operand[i].is_operator) | |
3426 | continue; | |
d9cf932c | 3427 | |
0b87be09 | 3428 | old = op = *curr_id->operand_loc[i]; |
d9cf932c VM |
3429 | if (GET_CODE (old) == SUBREG) |
3430 | old = SUBREG_REG (old); | |
3431 | subst = get_equiv_with_elimination (old, curr_insn); | |
895ff86f | 3432 | original_subreg_reg_mode[i] = VOIDmode; |
d9cf932c VM |
3433 | if (subst != old) |
3434 | { | |
3435 | subst = copy_rtx (subst); | |
3436 | lra_assert (REG_P (old)); | |
895ff86f | 3437 | if (GET_CODE (op) != SUBREG) |
d9cf932c | 3438 | *curr_id->operand_loc[i] = subst; |
895ff86f VM |
3439 | else |
3440 | { | |
3441 | SUBREG_REG (op) = subst; | |
3442 | if (GET_MODE (subst) == VOIDmode) | |
3443 | original_subreg_reg_mode[i] = GET_MODE (old); | |
3444 | } | |
d9cf932c VM |
3445 | if (lra_dump_file != NULL) |
3446 | { | |
3447 | fprintf (lra_dump_file, | |
3448 | "Changing pseudo %d in operand %i of insn %u on equiv ", | |
3449 | REGNO (old), i, INSN_UID (curr_insn)); | |
3450 | dump_value_slim (lra_dump_file, subst, 1); | |
895ff86f | 3451 | fprintf (lra_dump_file, "\n"); |
d9cf932c VM |
3452 | } |
3453 | op_change_p = change_p = true; | |
3454 | } | |
3455 | if (simplify_operand_subreg (i, GET_MODE (old)) || op_change_p) | |
3456 | { | |
3457 | change_p = true; | |
3458 | lra_update_dup (curr_id, i); | |
3459 | } | |
3460 | } | |
55a2c322 VM |
3461 | |
3462 | /* Reload address registers and displacements. We do it before | |
3463 | finding an alternative because of memory constraints. */ | |
cfa434f6 | 3464 | before = after = NULL; |
55a2c322 VM |
3465 | for (i = 0; i < n_operands; i++) |
3466 | if (! curr_static_id->operand[i].is_operator | |
d9cf932c | 3467 | && process_address (i, check_only_p, &before, &after)) |
55a2c322 | 3468 | { |
d9cf932c VM |
3469 | if (check_only_p) |
3470 | return true; | |
55a2c322 VM |
3471 | change_p = true; |
3472 | lra_update_dup (curr_id, i); | |
3473 | } | |
cc8849a1 | 3474 | |
55a2c322 VM |
3475 | if (change_p) |
3476 | /* If we've changed the instruction then any alternative that | |
3477 | we chose previously may no longer be valid. */ | |
3478 | lra_set_used_insn_alternative (curr_insn, -1); | |
3479 | ||
d9cf932c | 3480 | if (! check_only_p && curr_insn_set != NULL_RTX |
2c62cbaa VM |
3481 | && check_and_process_move (&change_p, &sec_mem_p)) |
3482 | return change_p; | |
3483 | ||
55a2c322 VM |
3484 | try_swapped: |
3485 | ||
d9cf932c | 3486 | reused_alternative_num = check_only_p ? -1 : curr_id->used_insn_alternative; |
55a2c322 VM |
3487 | if (lra_dump_file != NULL && reused_alternative_num >= 0) |
3488 | fprintf (lra_dump_file, "Reusing alternative %d for insn #%u\n", | |
3489 | reused_alternative_num, INSN_UID (curr_insn)); | |
3490 | ||
3491 | if (process_alt_operands (reused_alternative_num)) | |
3492 | alt_p = true; | |
3493 | ||
d9cf932c VM |
3494 | if (check_only_p) |
3495 | return ! alt_p || best_losers != 0; | |
3496 | ||
55a2c322 VM |
3497 | /* If insn is commutative (it's safe to exchange a certain pair of |
3498 | operands) then we need to try each alternative twice, the second | |
3499 | time matching those two operands as if we had exchanged them. To | |
3500 | do this, really exchange them in operands. | |
3501 | ||
3502 | If we have just tried the alternatives the second time, return | |
3503 | operands to normal and drop through. */ | |
3504 | ||
3505 | if (reused_alternative_num < 0 && commutative >= 0) | |
3506 | { | |
3507 | curr_swapped = !curr_swapped; | |
3508 | if (curr_swapped) | |
3509 | { | |
3510 | swap_operands (commutative); | |
3511 | goto try_swapped; | |
3512 | } | |
3513 | else | |
3514 | swap_operands (commutative); | |
3515 | } | |
3516 | ||
55a2c322 VM |
3517 | if (! alt_p && ! sec_mem_p) |
3518 | { | |
3519 | /* No alternative works with reloads?? */ | |
3520 | if (INSN_CODE (curr_insn) >= 0) | |
3521 | fatal_insn ("unable to generate reloads for:", curr_insn); | |
3522 | error_for_asm (curr_insn, | |
3523 | "inconsistent operand constraints in an %<asm%>"); | |
3524 | /* Avoid further trouble with this insn. */ | |
3525 | PATTERN (curr_insn) = gen_rtx_USE (VOIDmode, const0_rtx); | |
3526 | lra_invalidate_insn_data (curr_insn); | |
3527 | return true; | |
3528 | } | |
3529 | ||
3530 | /* If the best alternative is with operands 1 and 2 swapped, swap | |
3531 | them. Update the operand numbers of any reloads already | |
3532 | pushed. */ | |
3533 | ||
3534 | if (goal_alt_swapped) | |
3535 | { | |
3536 | if (lra_dump_file != NULL) | |
3537 | fprintf (lra_dump_file, " Commutative operand exchange in insn %u\n", | |
3538 | INSN_UID (curr_insn)); | |
3539 | ||
3540 | /* Swap the duplicates too. */ | |
3541 | swap_operands (commutative); | |
3542 | change_p = true; | |
3543 | } | |
3544 | ||
3545 | #ifdef SECONDARY_MEMORY_NEEDED | |
3546 | /* Some target macros SECONDARY_MEMORY_NEEDED (e.g. x86) are defined | |
3547 | too conservatively. So we use the secondary memory only if there | |
3548 | is no any alternative without reloads. */ | |
3549 | use_sec_mem_p = false; | |
3550 | if (! alt_p) | |
3551 | use_sec_mem_p = true; | |
3552 | else if (sec_mem_p) | |
3553 | { | |
3554 | for (i = 0; i < n_operands; i++) | |
3555 | if (! goal_alt_win[i] && ! goal_alt_match_win[i]) | |
3556 | break; | |
3557 | use_sec_mem_p = i < n_operands; | |
3558 | } | |
3559 | ||
3560 | if (use_sec_mem_p) | |
3561 | { | |
89d56d79 | 3562 | rtx new_reg, src, dest, rld; |
ef4bddc2 | 3563 | machine_mode sec_mode, rld_mode; |
55a2c322 VM |
3564 | |
3565 | lra_assert (sec_mem_p); | |
66aa7879 VM |
3566 | lra_assert (curr_static_id->operand[0].type == OP_OUT |
3567 | && curr_static_id->operand[1].type == OP_IN); | |
3568 | dest = *curr_id->operand_loc[0]; | |
3569 | src = *curr_id->operand_loc[1]; | |
3570 | rld = (GET_MODE_SIZE (GET_MODE (dest)) <= GET_MODE_SIZE (GET_MODE (src)) | |
3571 | ? dest : src); | |
3572 | rld_mode = GET_MODE (rld); | |
55a2c322 | 3573 | #ifdef SECONDARY_MEMORY_NEEDED_MODE |
66aa7879 | 3574 | sec_mode = SECONDARY_MEMORY_NEEDED_MODE (rld_mode); |
55a2c322 | 3575 | #else |
66aa7879 | 3576 | sec_mode = rld_mode; |
55a2c322 VM |
3577 | #endif |
3578 | new_reg = lra_create_new_reg (sec_mode, NULL_RTX, | |
3579 | NO_REGS, "secondary"); | |
3580 | /* If the mode is changed, it should be wider. */ | |
66aa7879 | 3581 | lra_assert (GET_MODE_SIZE (sec_mode) >= GET_MODE_SIZE (rld_mode)); |
89d56d79 VM |
3582 | if (sec_mode != rld_mode) |
3583 | { | |
3584 | /* If the target says specifically to use another mode for | |
3585 | secondary memory moves we can not reuse the original | |
3586 | insn. */ | |
1ccd4874 | 3587 | after = emit_spill_move (false, new_reg, dest); |
cfa434f6 | 3588 | lra_process_new_insns (curr_insn, NULL, after, |
1ccd4874 VM |
3589 | "Inserting the sec. move"); |
3590 | /* We may have non null BEFORE here (e.g. after address | |
3591 | processing. */ | |
3592 | push_to_sequence (before); | |
3593 | before = emit_spill_move (true, new_reg, src); | |
3594 | emit_insn (before); | |
3595 | before = get_insns (); | |
3596 | end_sequence (); | |
cfa434f6 | 3597 | lra_process_new_insns (curr_insn, before, NULL, "Changing on"); |
1ccd4874 VM |
3598 | lra_set_insn_deleted (curr_insn); |
3599 | } | |
89d56d79 | 3600 | else if (dest == rld) |
1ccd4874 VM |
3601 | { |
3602 | *curr_id->operand_loc[0] = new_reg; | |
66aa7879 | 3603 | after = emit_spill_move (false, new_reg, dest); |
cfa434f6 | 3604 | lra_process_new_insns (curr_insn, NULL, after, |
66aa7879 VM |
3605 | "Inserting the sec. move"); |
3606 | } | |
3607 | else | |
3608 | { | |
89d56d79 | 3609 | *curr_id->operand_loc[1] = new_reg; |
1ccd4874 VM |
3610 | /* See comments above. */ |
3611 | push_to_sequence (before); | |
66aa7879 | 3612 | before = emit_spill_move (true, new_reg, src); |
1ccd4874 VM |
3613 | emit_insn (before); |
3614 | before = get_insns (); | |
3615 | end_sequence (); | |
cfa434f6 | 3616 | lra_process_new_insns (curr_insn, before, NULL, |
66aa7879 VM |
3617 | "Inserting the sec. move"); |
3618 | } | |
3619 | lra_update_insn_regno_info (curr_insn); | |
55a2c322 VM |
3620 | return true; |
3621 | } | |
3622 | #endif | |
3623 | ||
3624 | lra_assert (goal_alt_number >= 0); | |
3625 | lra_set_used_insn_alternative (curr_insn, goal_alt_number); | |
3626 | ||
3627 | if (lra_dump_file != NULL) | |
3628 | { | |
3629 | const char *p; | |
3630 | ||
3631 | fprintf (lra_dump_file, " Choosing alt %d in insn %u:", | |
3632 | goal_alt_number, INSN_UID (curr_insn)); | |
3633 | for (i = 0; i < n_operands; i++) | |
3634 | { | |
3635 | p = (curr_static_id->operand_alternative | |
3636 | [goal_alt_number * n_operands + i].constraint); | |
3637 | if (*p == '\0') | |
3638 | continue; | |
3639 | fprintf (lra_dump_file, " (%d) ", i); | |
3640 | for (; *p != '\0' && *p != ',' && *p != '#'; p++) | |
3641 | fputc (*p, lra_dump_file); | |
3642 | } | |
36ff9dfb VM |
3643 | if (INSN_CODE (curr_insn) >= 0 |
3644 | && (p = get_insn_name (INSN_CODE (curr_insn))) != NULL) | |
3645 | fprintf (lra_dump_file, " {%s}", p); | |
8d49e7ef VM |
3646 | if (curr_id->sp_offset != 0) |
3647 | fprintf (lra_dump_file, " (sp_off=%" HOST_WIDE_INT_PRINT "d)", | |
3648 | curr_id->sp_offset); | |
36ff9dfb | 3649 | fprintf (lra_dump_file, "\n"); |
55a2c322 VM |
3650 | } |
3651 | ||
3652 | /* Right now, for any pair of operands I and J that are required to | |
3653 | match, with J < I, goal_alt_matches[I] is J. Add I to | |
3654 | goal_alt_matched[J]. */ | |
f4eafc30 | 3655 | |
55a2c322 VM |
3656 | for (i = 0; i < n_operands; i++) |
3657 | if ((j = goal_alt_matches[i]) >= 0) | |
3658 | { | |
3659 | for (k = 0; goal_alt_matched[j][k] >= 0; k++) | |
3660 | ; | |
3661 | /* We allow matching one output operand and several input | |
3662 | operands. */ | |
3663 | lra_assert (k == 0 | |
3664 | || (curr_static_id->operand[j].type == OP_OUT | |
3665 | && curr_static_id->operand[i].type == OP_IN | |
3666 | && (curr_static_id->operand | |
3667 | [goal_alt_matched[j][0]].type == OP_IN))); | |
3668 | goal_alt_matched[j][k] = i; | |
3669 | goal_alt_matched[j][k + 1] = -1; | |
3670 | } | |
f4eafc30 | 3671 | |
55a2c322 VM |
3672 | for (i = 0; i < n_operands; i++) |
3673 | goal_alt_win[i] |= goal_alt_match_win[i]; | |
f4eafc30 | 3674 | |
55a2c322 VM |
3675 | /* Any constants that aren't allowed and can't be reloaded into |
3676 | registers are here changed into memory references. */ | |
3677 | for (i = 0; i < n_operands; i++) | |
3678 | if (goal_alt_win[i]) | |
3679 | { | |
3680 | int regno; | |
3681 | enum reg_class new_class; | |
3682 | rtx reg = *curr_id->operand_loc[i]; | |
3683 | ||
3684 | if (GET_CODE (reg) == SUBREG) | |
3685 | reg = SUBREG_REG (reg); | |
f4eafc30 | 3686 | |
55a2c322 VM |
3687 | if (REG_P (reg) && (regno = REGNO (reg)) >= FIRST_PSEUDO_REGISTER) |
3688 | { | |
3689 | bool ok_p = in_class_p (reg, goal_alt[i], &new_class); | |
3690 | ||
3691 | if (new_class != NO_REGS && get_reg_class (regno) != new_class) | |
3692 | { | |
3693 | lra_assert (ok_p); | |
a2d0d374 | 3694 | lra_change_class (regno, new_class, " Change to", true); |
55a2c322 VM |
3695 | } |
3696 | } | |
3697 | } | |
3698 | else | |
3699 | { | |
3700 | const char *constraint; | |
3701 | char c; | |
3702 | rtx op = *curr_id->operand_loc[i]; | |
3703 | rtx subreg = NULL_RTX; | |
ef4bddc2 | 3704 | machine_mode mode = curr_operand_mode[i]; |
f4eafc30 | 3705 | |
55a2c322 VM |
3706 | if (GET_CODE (op) == SUBREG) |
3707 | { | |
3708 | subreg = op; | |
3709 | op = SUBREG_REG (op); | |
3710 | mode = GET_MODE (op); | |
3711 | } | |
f4eafc30 | 3712 | |
55a2c322 VM |
3713 | if (CONST_POOL_OK_P (mode, op) |
3714 | && ((targetm.preferred_reload_class | |
3715 | (op, (enum reg_class) goal_alt[i]) == NO_REGS) | |
3716 | || no_input_reloads_p)) | |
3717 | { | |
3718 | rtx tem = force_const_mem (mode, op); | |
f4eafc30 | 3719 | |
55a2c322 VM |
3720 | change_p = true; |
3721 | if (subreg != NULL_RTX) | |
3722 | tem = gen_rtx_SUBREG (mode, tem, SUBREG_BYTE (subreg)); | |
f4eafc30 | 3723 | |
55a2c322 VM |
3724 | *curr_id->operand_loc[i] = tem; |
3725 | lra_update_dup (curr_id, i); | |
d9cf932c | 3726 | process_address (i, false, &before, &after); |
f4eafc30 | 3727 | |
55a2c322 VM |
3728 | /* If the alternative accepts constant pool refs directly |
3729 | there will be no reload needed at all. */ | |
3730 | if (subreg != NULL_RTX) | |
3731 | continue; | |
3732 | /* Skip alternatives before the one requested. */ | |
3733 | constraint = (curr_static_id->operand_alternative | |
3734 | [goal_alt_number * n_operands + i].constraint); | |
3735 | for (; | |
3736 | (c = *constraint) && c != ',' && c != '#'; | |
3737 | constraint += CONSTRAINT_LEN (c, constraint)) | |
3738 | { | |
777e635f | 3739 | enum constraint_num cn = lookup_constraint (constraint); |
9eb1ca69 VM |
3740 | if ((insn_extra_memory_constraint (cn) |
3741 | || insn_extra_special_memory_constraint (cn)) | |
777e635f | 3742 | && satisfies_memory_constraint_p (tem, cn)) |
55a2c322 | 3743 | break; |
55a2c322 VM |
3744 | } |
3745 | if (c == '\0' || c == ',' || c == '#') | |
3746 | continue; | |
f4eafc30 | 3747 | |
55a2c322 VM |
3748 | goal_alt_win[i] = true; |
3749 | } | |
3750 | } | |
f4eafc30 | 3751 | |
55a2c322 VM |
3752 | for (i = 0; i < n_operands; i++) |
3753 | { | |
2b778c9d VM |
3754 | int regno; |
3755 | bool optional_p = false; | |
55a2c322 VM |
3756 | rtx old, new_reg; |
3757 | rtx op = *curr_id->operand_loc[i]; | |
3758 | ||
3759 | if (goal_alt_win[i]) | |
3760 | { | |
3761 | if (goal_alt[i] == NO_REGS | |
3762 | && REG_P (op) | |
3763 | /* When we assign NO_REGS it means that we will not | |
3764 | assign a hard register to the scratch pseudo by | |
3765 | assigment pass and the scratch pseudo will be | |
3766 | spilled. Spilled scratch pseudos are transformed | |
3767 | back to scratches at the LRA end. */ | |
6c051d60 VM |
3768 | && lra_former_scratch_operand_p (curr_insn, i) |
3769 | && lra_former_scratch_p (REGNO (op))) | |
deca73f5 VM |
3770 | { |
3771 | int regno = REGNO (op); | |
a2d0d374 | 3772 | lra_change_class (regno, NO_REGS, " Change to", true); |
deca73f5 VM |
3773 | if (lra_get_regno_hard_regno (regno) >= 0) |
3774 | /* We don't have to mark all insn affected by the | |
3775 | spilled pseudo as there is only one such insn, the | |
3776 | current one. */ | |
3777 | reg_renumber[regno] = -1; | |
6c051d60 VM |
3778 | lra_assert (bitmap_single_bit_set_p |
3779 | (&lra_reg_info[REGNO (op)].insn_bitmap)); | |
deca73f5 | 3780 | } |
2b778c9d VM |
3781 | /* We can do an optional reload. If the pseudo got a hard |
3782 | reg, we might improve the code through inheritance. If | |
3783 | it does not get a hard register we coalesce memory/memory | |
3784 | moves later. Ignore move insns to avoid cycling. */ | |
b0681c9e | 3785 | if (! lra_simple_p |
2b778c9d VM |
3786 | && lra_undo_inheritance_iter < LRA_MAX_INHERITANCE_PASSES |
3787 | && goal_alt[i] != NO_REGS && REG_P (op) | |
3788 | && (regno = REGNO (op)) >= FIRST_PSEUDO_REGISTER | |
a2d0d374 | 3789 | && regno < new_regno_start |
b0681c9e | 3790 | && ! lra_former_scratch_p (regno) |
2b778c9d | 3791 | && reg_renumber[regno] < 0 |
3c954213 VM |
3792 | /* Check that the optional reload pseudo will be able to |
3793 | hold given mode value. */ | |
3794 | && ! (prohibited_class_reg_set_mode_p | |
3795 | (goal_alt[i], reg_class_contents[goal_alt[i]], | |
3796 | PSEUDO_REGNO_MODE (regno))) | |
2b778c9d | 3797 | && (curr_insn_set == NULL_RTX |
b0681c9e VM |
3798 | || !((REG_P (SET_SRC (curr_insn_set)) |
3799 | || MEM_P (SET_SRC (curr_insn_set)) | |
3800 | || GET_CODE (SET_SRC (curr_insn_set)) == SUBREG) | |
3801 | && (REG_P (SET_DEST (curr_insn_set)) | |
3802 | || MEM_P (SET_DEST (curr_insn_set)) | |
3803 | || GET_CODE (SET_DEST (curr_insn_set)) == SUBREG)))) | |
2b778c9d VM |
3804 | optional_p = true; |
3805 | else | |
3806 | continue; | |
55a2c322 | 3807 | } |
f4eafc30 | 3808 | |
55a2c322 VM |
3809 | /* Operands that match previous ones have already been handled. */ |
3810 | if (goal_alt_matches[i] >= 0) | |
3811 | continue; | |
3812 | ||
3813 | /* We should not have an operand with a non-offsettable address | |
3814 | appearing where an offsettable address will do. It also may | |
3815 | be a case when the address should be special in other words | |
3816 | not a general one (e.g. it needs no index reg). */ | |
3817 | if (goal_alt_matched[i][0] == -1 && goal_alt_offmemok[i] && MEM_P (op)) | |
3818 | { | |
3819 | enum reg_class rclass; | |
3820 | rtx *loc = &XEXP (op, 0); | |
3821 | enum rtx_code code = GET_CODE (*loc); | |
3822 | ||
3823 | push_to_sequence (before); | |
3824 | rclass = base_reg_class (GET_MODE (op), MEM_ADDR_SPACE (op), | |
3825 | MEM, SCRATCH); | |
3826 | if (GET_RTX_CLASS (code) == RTX_AUTOINC) | |
3827 | new_reg = emit_inc (rclass, *loc, *loc, | |
3828 | /* This value does not matter for MODIFY. */ | |
3829 | GET_MODE_SIZE (GET_MODE (op))); | |
95921002 | 3830 | else if (get_reload_reg (OP_IN, Pmode, *loc, rclass, FALSE, |
55a2c322 VM |
3831 | "offsetable address", &new_reg)) |
3832 | lra_emit_move (new_reg, *loc); | |
3833 | before = get_insns (); | |
3834 | end_sequence (); | |
3835 | *loc = new_reg; | |
3836 | lra_update_dup (curr_id, i); | |
3837 | } | |
3838 | else if (goal_alt_matched[i][0] == -1) | |
3839 | { | |
ef4bddc2 | 3840 | machine_mode mode; |
55a2c322 VM |
3841 | rtx reg, *loc; |
3842 | int hard_regno, byte; | |
3843 | enum op_type type = curr_static_id->operand[i].type; | |
3844 | ||
3845 | loc = curr_id->operand_loc[i]; | |
3846 | mode = curr_operand_mode[i]; | |
3847 | if (GET_CODE (*loc) == SUBREG) | |
3848 | { | |
3849 | reg = SUBREG_REG (*loc); | |
3850 | byte = SUBREG_BYTE (*loc); | |
3851 | if (REG_P (reg) | |
3852 | /* Strict_low_part requires reload the register not | |
3853 | the sub-register. */ | |
3854 | && (curr_static_id->operand[i].strict_low | |
3855 | || (GET_MODE_SIZE (mode) | |
3856 | <= GET_MODE_SIZE (GET_MODE (reg)) | |
3857 | && (hard_regno | |
3858 | = get_try_hard_regno (REGNO (reg))) >= 0 | |
3859 | && (simplify_subreg_regno | |
3860 | (hard_regno, | |
3861 | GET_MODE (reg), byte, mode) < 0) | |
3862 | && (goal_alt[i] == NO_REGS | |
3863 | || (simplify_subreg_regno | |
3864 | (ira_class_hard_regs[goal_alt[i]][0], | |
3865 | GET_MODE (reg), byte, mode) >= 0))))) | |
3866 | { | |
8b8e23de RS |
3867 | if (type == OP_OUT) |
3868 | type = OP_INOUT; | |
55a2c322 VM |
3869 | loc = &SUBREG_REG (*loc); |
3870 | mode = GET_MODE (*loc); | |
3871 | } | |
3872 | } | |
3873 | old = *loc; | |
95921002 VM |
3874 | if (get_reload_reg (type, mode, old, goal_alt[i], |
3875 | loc != curr_id->operand_loc[i], "", &new_reg) | |
55a2c322 VM |
3876 | && type != OP_OUT) |
3877 | { | |
3878 | push_to_sequence (before); | |
3879 | lra_emit_move (new_reg, old); | |
3880 | before = get_insns (); | |
3881 | end_sequence (); | |
3882 | } | |
3883 | *loc = new_reg; | |
3884 | if (type != OP_IN | |
3885 | && find_reg_note (curr_insn, REG_UNUSED, old) == NULL_RTX) | |
3886 | { | |
3887 | start_sequence (); | |
3888 | lra_emit_move (type == OP_INOUT ? copy_rtx (old) : old, new_reg); | |
3889 | emit_insn (after); | |
3890 | after = get_insns (); | |
3891 | end_sequence (); | |
3892 | *loc = new_reg; | |
3893 | } | |
3894 | for (j = 0; j < goal_alt_dont_inherit_ops_num; j++) | |
3895 | if (goal_alt_dont_inherit_ops[j] == i) | |
3896 | { | |
3897 | lra_set_regno_unique_value (REGNO (new_reg)); | |
3898 | break; | |
3899 | } | |
3900 | lra_update_dup (curr_id, i); | |
3901 | } | |
3902 | else if (curr_static_id->operand[i].type == OP_IN | |
3903 | && (curr_static_id->operand[goal_alt_matched[i][0]].type | |
3904 | == OP_OUT)) | |
3905 | { | |
511dcace VM |
3906 | /* generate reloads for input and matched outputs. */ |
3907 | match_inputs[0] = i; | |
3908 | match_inputs[1] = -1; | |
3909 | match_reload (goal_alt_matched[i][0], match_inputs, | |
599e1cf8 VM |
3910 | goal_alt[i], &before, &after, |
3911 | curr_static_id->operand_alternative | |
3912 | [goal_alt_number * n_operands + goal_alt_matched[i][0]] | |
3913 | .earlyclobber); | |
55a2c322 VM |
3914 | } |
3915 | else if (curr_static_id->operand[i].type == OP_OUT | |
3916 | && (curr_static_id->operand[goal_alt_matched[i][0]].type | |
3917 | == OP_IN)) | |
511dcace | 3918 | /* Generate reloads for output and matched inputs. */ |
599e1cf8 VM |
3919 | match_reload (i, goal_alt_matched[i], goal_alt[i], &before, &after, |
3920 | curr_static_id->operand_alternative | |
3921 | [goal_alt_number * n_operands + i].earlyclobber); | |
511dcace VM |
3922 | else if (curr_static_id->operand[i].type == OP_IN |
3923 | && (curr_static_id->operand[goal_alt_matched[i][0]].type | |
3924 | == OP_IN)) | |
3925 | { | |
3926 | /* Generate reloads for matched inputs. */ | |
3927 | match_inputs[0] = i; | |
3928 | for (j = 0; (k = goal_alt_matched[i][j]) >= 0; j++) | |
3929 | match_inputs[j + 1] = k; | |
3930 | match_inputs[j + 1] = -1; | |
599e1cf8 | 3931 | match_reload (-1, match_inputs, goal_alt[i], &before, &after, false); |
511dcace | 3932 | } |
55a2c322 VM |
3933 | else |
3934 | /* We must generate code in any case when function | |
3935 | process_alt_operands decides that it is possible. */ | |
3936 | gcc_unreachable (); | |
2b778c9d VM |
3937 | if (optional_p) |
3938 | { | |
3939 | lra_assert (REG_P (op)); | |
3940 | regno = REGNO (op); | |
3941 | op = *curr_id->operand_loc[i]; /* Substitution. */ | |
3942 | if (GET_CODE (op) == SUBREG) | |
3943 | op = SUBREG_REG (op); | |
3944 | gcc_assert (REG_P (op) && (int) REGNO (op) >= new_regno_start); | |
3945 | bitmap_set_bit (&lra_optional_reload_pseudos, REGNO (op)); | |
3946 | lra_reg_info[REGNO (op)].restore_regno = regno; | |
3947 | if (lra_dump_file != NULL) | |
3948 | fprintf (lra_dump_file, | |
3949 | " Making reload reg %d for reg %d optional\n", | |
3950 | REGNO (op), regno); | |
3951 | } | |
55a2c322 VM |
3952 | } |
3953 | if (before != NULL_RTX || after != NULL_RTX | |
3954 | || max_regno_before != max_reg_num ()) | |
3955 | change_p = true; | |
3956 | if (change_p) | |
3957 | { | |
3958 | lra_update_operator_dups (curr_id); | |
3959 | /* Something changes -- process the insn. */ | |
3960 | lra_update_insn_regno_info (curr_insn); | |
3961 | } | |
3962 | lra_process_new_insns (curr_insn, before, after, "Inserting insn reload"); | |
3963 | return change_p; | |
3964 | } | |
3965 | ||
d9cf932c VM |
3966 | /* Return true if INSN satisfies all constraints. In other words, no |
3967 | reload insns are needed. */ | |
3968 | bool | |
3969 | lra_constrain_insn (rtx_insn *insn) | |
3970 | { | |
3971 | int saved_new_regno_start = new_regno_start; | |
3972 | int saved_new_insn_uid_start = new_insn_uid_start; | |
3973 | bool change_p; | |
3974 | ||
3975 | curr_insn = insn; | |
3976 | curr_id = lra_get_insn_recog_data (curr_insn); | |
3977 | curr_static_id = curr_id->insn_static_data; | |
3978 | new_insn_uid_start = get_max_uid (); | |
3979 | new_regno_start = max_reg_num (); | |
3980 | change_p = curr_insn_transform (true); | |
3981 | new_regno_start = saved_new_regno_start; | |
3982 | new_insn_uid_start = saved_new_insn_uid_start; | |
3983 | return ! change_p; | |
3984 | } | |
3985 | ||
55a2c322 VM |
3986 | /* Return true if X is in LIST. */ |
3987 | static bool | |
3988 | in_list_p (rtx x, rtx list) | |
3989 | { | |
3990 | for (; list != NULL_RTX; list = XEXP (list, 1)) | |
3991 | if (XEXP (list, 0) == x) | |
3992 | return true; | |
3993 | return false; | |
3994 | } | |
3995 | ||
3996 | /* Return true if X contains an allocatable hard register (if | |
3997 | HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */ | |
3998 | static bool | |
3999 | contains_reg_p (rtx x, bool hard_reg_p, bool spilled_p) | |
4000 | { | |
4001 | int i, j; | |
4002 | const char *fmt; | |
4003 | enum rtx_code code; | |
4004 | ||
4005 | code = GET_CODE (x); | |
4006 | if (REG_P (x)) | |
4007 | { | |
4008 | int regno = REGNO (x); | |
4009 | HARD_REG_SET alloc_regs; | |
4010 | ||
4011 | if (hard_reg_p) | |
4012 | { | |
4013 | if (regno >= FIRST_PSEUDO_REGISTER) | |
4014 | regno = lra_get_regno_hard_regno (regno); | |
4015 | if (regno < 0) | |
4016 | return false; | |
4017 | COMPL_HARD_REG_SET (alloc_regs, lra_no_alloc_regs); | |
4018 | return overlaps_hard_reg_set_p (alloc_regs, GET_MODE (x), regno); | |
4019 | } | |
4020 | else | |
4021 | { | |
4022 | if (regno < FIRST_PSEUDO_REGISTER) | |
4023 | return false; | |
4024 | if (! spilled_p) | |
4025 | return true; | |
4026 | return lra_get_regno_hard_regno (regno) < 0; | |
4027 | } | |
4028 | } | |
4029 | fmt = GET_RTX_FORMAT (code); | |
4030 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
4031 | { | |
4032 | if (fmt[i] == 'e') | |
4033 | { | |
4034 | if (contains_reg_p (XEXP (x, i), hard_reg_p, spilled_p)) | |
4035 | return true; | |
4036 | } | |
4037 | else if (fmt[i] == 'E') | |
4038 | { | |
4039 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
4040 | if (contains_reg_p (XVECEXP (x, i, j), hard_reg_p, spilled_p)) | |
4041 | return true; | |
4042 | } | |
4043 | } | |
4044 | return false; | |
4045 | } | |
4046 | ||
28430b2e VM |
4047 | /* Process all regs in location *LOC and change them on equivalent |
4048 | substitution. Return true if any change was done. */ | |
55a2c322 | 4049 | static bool |
28430b2e | 4050 | loc_equivalence_change_p (rtx *loc) |
55a2c322 VM |
4051 | { |
4052 | rtx subst, reg, x = *loc; | |
4053 | bool result = false; | |
4054 | enum rtx_code code = GET_CODE (x); | |
4055 | const char *fmt; | |
4056 | int i, j; | |
4057 | ||
4058 | if (code == SUBREG) | |
4059 | { | |
4060 | reg = SUBREG_REG (x); | |
8d49e7ef | 4061 | if ((subst = get_equiv_with_elimination (reg, curr_insn)) != reg |
55a2c322 VM |
4062 | && GET_MODE (subst) == VOIDmode) |
4063 | { | |
4064 | /* We cannot reload debug location. Simplify subreg here | |
4065 | while we know the inner mode. */ | |
4066 | *loc = simplify_gen_subreg (GET_MODE (x), subst, | |
4067 | GET_MODE (reg), SUBREG_BYTE (x)); | |
4068 | return true; | |
4069 | } | |
4070 | } | |
8d49e7ef | 4071 | if (code == REG && (subst = get_equiv_with_elimination (x, curr_insn)) != x) |
55a2c322 VM |
4072 | { |
4073 | *loc = subst; | |
4074 | return true; | |
4075 | } | |
4076 | ||
4077 | /* Scan all the operand sub-expressions. */ | |
4078 | fmt = GET_RTX_FORMAT (code); | |
4079 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
4080 | { | |
4081 | if (fmt[i] == 'e') | |
28430b2e | 4082 | result = loc_equivalence_change_p (&XEXP (x, i)) || result; |
55a2c322 VM |
4083 | else if (fmt[i] == 'E') |
4084 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
4085 | result | |
28430b2e | 4086 | = loc_equivalence_change_p (&XVECEXP (x, i, j)) || result; |
55a2c322 VM |
4087 | } |
4088 | return result; | |
4089 | } | |
4090 | ||
d0608e59 | 4091 | /* Similar to loc_equivalence_change_p, but for use as |
4c2b2d79 VM |
4092 | simplify_replace_fn_rtx callback. DATA is insn for which the |
4093 | elimination is done. If it null we don't do the elimination. */ | |
d0608e59 | 4094 | static rtx |
4c2b2d79 | 4095 | loc_equivalence_callback (rtx loc, const_rtx, void *data) |
d0608e59 JJ |
4096 | { |
4097 | if (!REG_P (loc)) | |
4098 | return NULL_RTX; | |
4099 | ||
4c2b2d79 | 4100 | rtx subst = (data == NULL |
cfa434f6 | 4101 | ? get_equiv (loc) : get_equiv_with_elimination (loc, (rtx_insn *) data)); |
d0608e59 JJ |
4102 | if (subst != loc) |
4103 | return subst; | |
4104 | ||
4105 | return NULL_RTX; | |
4106 | } | |
4107 | ||
55a2c322 VM |
4108 | /* Maximum number of generated reload insns per an insn. It is for |
4109 | preventing this pass cycling in a bug case. */ | |
4110 | #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS | |
4111 | ||
4112 | /* The current iteration number of this LRA pass. */ | |
4113 | int lra_constraint_iter; | |
4114 | ||
55a2c322 VM |
4115 | /* True if we substituted equiv which needs checking register |
4116 | allocation correctness because the equivalent value contains | |
4117 | allocatable hard registers or when we restore multi-register | |
4118 | pseudo. */ | |
4119 | bool lra_risky_transformations_p; | |
4120 | ||
4121 | /* Return true if REGNO is referenced in more than one block. */ | |
4122 | static bool | |
4123 | multi_block_pseudo_p (int regno) | |
4124 | { | |
4125 | basic_block bb = NULL; | |
4126 | unsigned int uid; | |
4127 | bitmap_iterator bi; | |
f4eafc30 | 4128 | |
55a2c322 VM |
4129 | if (regno < FIRST_PSEUDO_REGISTER) |
4130 | return false; | |
f4eafc30 | 4131 | |
55a2c322 VM |
4132 | EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi) |
4133 | if (bb == NULL) | |
4134 | bb = BLOCK_FOR_INSN (lra_insn_recog_data[uid]->insn); | |
4135 | else if (BLOCK_FOR_INSN (lra_insn_recog_data[uid]->insn) != bb) | |
4136 | return true; | |
4137 | return false; | |
4138 | } | |
4139 | ||
1966c91b VM |
4140 | /* Return true if LIST contains a deleted insn. */ |
4141 | static bool | |
0cc97fc5 | 4142 | contains_deleted_insn_p (rtx_insn_list *list) |
1966c91b | 4143 | { |
0cc97fc5 DM |
4144 | for (; list != NULL_RTX; list = list->next ()) |
4145 | if (NOTE_P (list->insn ()) | |
4146 | && NOTE_KIND (list->insn ()) == NOTE_INSN_DELETED) | |
1966c91b VM |
4147 | return true; |
4148 | return false; | |
4149 | } | |
4150 | ||
55a2c322 VM |
4151 | /* Return true if X contains a pseudo dying in INSN. */ |
4152 | static bool | |
605780f6 | 4153 | dead_pseudo_p (rtx x, rtx_insn *insn) |
55a2c322 VM |
4154 | { |
4155 | int i, j; | |
4156 | const char *fmt; | |
4157 | enum rtx_code code; | |
4158 | ||
4159 | if (REG_P (x)) | |
4160 | return (insn != NULL_RTX | |
4161 | && find_regno_note (insn, REG_DEAD, REGNO (x)) != NULL_RTX); | |
4162 | code = GET_CODE (x); | |
4163 | fmt = GET_RTX_FORMAT (code); | |
4164 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
4165 | { | |
4166 | if (fmt[i] == 'e') | |
4167 | { | |
4168 | if (dead_pseudo_p (XEXP (x, i), insn)) | |
4169 | return true; | |
4170 | } | |
4171 | else if (fmt[i] == 'E') | |
4172 | { | |
4173 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
4174 | if (dead_pseudo_p (XVECEXP (x, i, j), insn)) | |
4175 | return true; | |
4176 | } | |
4177 | } | |
4178 | return false; | |
4179 | } | |
4180 | ||
4181 | /* Return true if INSN contains a dying pseudo in INSN right hand | |
4182 | side. */ | |
4183 | static bool | |
e8a54173 | 4184 | insn_rhs_dead_pseudo_p (rtx_insn *insn) |
55a2c322 VM |
4185 | { |
4186 | rtx set = single_set (insn); | |
4187 | ||
4188 | gcc_assert (set != NULL); | |
4189 | return dead_pseudo_p (SET_SRC (set), insn); | |
4190 | } | |
4191 | ||
4192 | /* Return true if any init insn of REGNO contains a dying pseudo in | |
4193 | insn right hand side. */ | |
4194 | static bool | |
4195 | init_insn_rhs_dead_pseudo_p (int regno) | |
4196 | { | |
0cc97fc5 | 4197 | rtx_insn_list *insns = ira_reg_equiv[regno].init_insns; |
55a2c322 VM |
4198 | |
4199 | if (insns == NULL) | |
4200 | return false; | |
0cc97fc5 DM |
4201 | for (; insns != NULL_RTX; insns = insns->next ()) |
4202 | if (insn_rhs_dead_pseudo_p (insns->insn ())) | |
55a2c322 VM |
4203 | return true; |
4204 | return false; | |
4205 | } | |
4206 | ||
01e54ef8 VM |
4207 | /* Return TRUE if REGNO has a reverse equivalence. The equivalence is |
4208 | reverse only if we have one init insn with given REGNO as a | |
4209 | source. */ | |
4210 | static bool | |
4211 | reverse_equiv_p (int regno) | |
4212 | { | |
0cc97fc5 DM |
4213 | rtx_insn_list *insns = ira_reg_equiv[regno].init_insns; |
4214 | rtx set; | |
01e54ef8 | 4215 | |
0cc97fc5 | 4216 | if (insns == NULL) |
01e54ef8 | 4217 | return false; |
0cc97fc5 DM |
4218 | if (! INSN_P (insns->insn ()) |
4219 | || insns->next () != NULL) | |
01e54ef8 | 4220 | return false; |
0cc97fc5 | 4221 | if ((set = single_set (insns->insn ())) == NULL_RTX) |
01e54ef8 VM |
4222 | return false; |
4223 | return REG_P (SET_SRC (set)) && (int) REGNO (SET_SRC (set)) == regno; | |
4224 | } | |
4225 | ||
4226 | /* Return TRUE if REGNO was reloaded in an equivalence init insn. We | |
4227 | call this function only for non-reverse equivalence. */ | |
4228 | static bool | |
4229 | contains_reloaded_insn_p (int regno) | |
4230 | { | |
4231 | rtx set; | |
0cc97fc5 | 4232 | rtx_insn_list *list = ira_reg_equiv[regno].init_insns; |
01e54ef8 | 4233 | |
0cc97fc5 DM |
4234 | for (; list != NULL; list = list->next ()) |
4235 | if ((set = single_set (list->insn ())) == NULL_RTX | |
01e54ef8 VM |
4236 | || ! REG_P (SET_DEST (set)) |
4237 | || (int) REGNO (SET_DEST (set)) != regno) | |
4238 | return true; | |
4239 | return false; | |
4240 | } | |
4241 | ||
55a2c322 VM |
4242 | /* Entry function of LRA constraint pass. Return true if the |
4243 | constraint pass did change the code. */ | |
4244 | bool | |
4245 | lra_constraints (bool first_p) | |
4246 | { | |
4247 | bool changed_p; | |
4248 | int i, hard_regno, new_insns_num; | |
6cd1dd26 VM |
4249 | unsigned int min_len, new_min_len, uid; |
4250 | rtx set, x, reg, dest_reg; | |
55a2c322 | 4251 | basic_block last_bb; |
6cd1dd26 VM |
4252 | bitmap_head equiv_insn_bitmap; |
4253 | bitmap_iterator bi; | |
55a2c322 VM |
4254 | |
4255 | lra_constraint_iter++; | |
4256 | if (lra_dump_file != NULL) | |
4257 | fprintf (lra_dump_file, "\n********** Local #%d: **********\n\n", | |
4258 | lra_constraint_iter); | |
55a2c322 | 4259 | changed_p = false; |
bcb21886 KY |
4260 | if (pic_offset_table_rtx |
4261 | && REGNO (pic_offset_table_rtx) >= FIRST_PSEUDO_REGISTER) | |
4262 | lra_risky_transformations_p = true; | |
4263 | else | |
4264 | lra_risky_transformations_p = false; | |
55a2c322 VM |
4265 | new_insn_uid_start = get_max_uid (); |
4266 | new_regno_start = first_p ? lra_constraint_new_regno_start : max_reg_num (); | |
8d49e7ef VM |
4267 | /* Mark used hard regs for target stack size calulations. */ |
4268 | for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++) | |
4269 | if (lra_reg_info[i].nrefs != 0 | |
4270 | && (hard_regno = lra_get_regno_hard_regno (i)) >= 0) | |
4271 | { | |
4272 | int j, nregs; | |
4273 | ||
4274 | nregs = hard_regno_nregs[hard_regno][lra_reg_info[i].biggest_mode]; | |
4275 | for (j = 0; j < nregs; j++) | |
4276 | df_set_regs_ever_live (hard_regno + j, true); | |
4277 | } | |
4278 | /* Do elimination before the equivalence processing as we can spill | |
4279 | some pseudos during elimination. */ | |
4280 | lra_eliminate (false, first_p); | |
6cd1dd26 | 4281 | bitmap_initialize (&equiv_insn_bitmap, ®_obstack); |
55a2c322 VM |
4282 | for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++) |
4283 | if (lra_reg_info[i].nrefs != 0) | |
4284 | { | |
4285 | ira_reg_equiv[i].profitable_p = true; | |
6cd1dd26 | 4286 | reg = regno_reg_rtx[i]; |
8d49e7ef | 4287 | if (lra_get_regno_hard_regno (i) < 0 && (x = get_equiv (reg)) != reg) |
55a2c322 VM |
4288 | { |
4289 | bool pseudo_p = contains_reg_p (x, false, false); | |
55a2c322 | 4290 | |
1966c91b VM |
4291 | /* After RTL transformation, we can not guarantee that |
4292 | pseudo in the substitution was not reloaded which might | |
4293 | make equivalence invalid. For example, in reverse | |
4294 | equiv of p0 | |
4295 | ||
4296 | p0 <- ... | |
4297 | ... | |
4298 | equiv_mem <- p0 | |
4299 | ||
4300 | the memory address register was reloaded before the 2nd | |
4301 | insn. */ | |
4302 | if ((! first_p && pseudo_p) | |
4303 | /* We don't use DF for compilation speed sake. So it | |
4304 | is problematic to update live info when we use an | |
4305 | equivalence containing pseudos in more than one | |
4306 | BB. */ | |
4307 | || (pseudo_p && multi_block_pseudo_p (i)) | |
4308 | /* If an init insn was deleted for some reason, cancel | |
4309 | the equiv. We could update the equiv insns after | |
4310 | transformations including an equiv insn deletion | |
4311 | but it is not worthy as such cases are extremely | |
4312 | rare. */ | |
4313 | || contains_deleted_insn_p (ira_reg_equiv[i].init_insns) | |
55a2c322 VM |
4314 | /* If it is not a reverse equivalence, we check that a |
4315 | pseudo in rhs of the init insn is not dying in the | |
4316 | insn. Otherwise, the live info at the beginning of | |
4317 | the corresponding BB might be wrong after we | |
4318 | removed the insn. When the equiv can be a | |
4319 | constant, the right hand side of the init insn can | |
4320 | be a pseudo. */ | |
01e54ef8 VM |
4321 | || (! reverse_equiv_p (i) |
4322 | && (init_insn_rhs_dead_pseudo_p (i) | |
4323 | /* If we reloaded the pseudo in an equivalence | |
4324 | init insn, we can not remove the equiv init | |
4325 | insns and the init insns might write into | |
4326 | const memory in this case. */ | |
4327 | || contains_reloaded_insn_p (i))) | |
b28ece32 VM |
4328 | /* Prevent access beyond equivalent memory for |
4329 | paradoxical subregs. */ | |
4330 | || (MEM_P (x) | |
4331 | && (GET_MODE_SIZE (lra_reg_info[i].biggest_mode) | |
bcb21886 KY |
4332 | > GET_MODE_SIZE (GET_MODE (x)))) |
4333 | || (pic_offset_table_rtx | |
4334 | && ((CONST_POOL_OK_P (PSEUDO_REGNO_MODE (i), x) | |
4335 | && (targetm.preferred_reload_class | |
4336 | (x, lra_get_allocno_class (i)) == NO_REGS)) | |
b81a2f0d | 4337 | || contains_symbol_ref_p (x)))) |
55a2c322 | 4338 | ira_reg_equiv[i].defined_p = false; |
55a2c322 VM |
4339 | if (contains_reg_p (x, false, true)) |
4340 | ira_reg_equiv[i].profitable_p = false; | |
8d49e7ef | 4341 | if (get_equiv (reg) != reg) |
6cd1dd26 | 4342 | bitmap_ior_into (&equiv_insn_bitmap, &lra_reg_info[i].insn_bitmap); |
55a2c322 VM |
4343 | } |
4344 | } | |
4c2b2d79 VM |
4345 | for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++) |
4346 | update_equiv (i); | |
6cd1dd26 VM |
4347 | /* We should add all insns containing pseudos which should be |
4348 | substituted by their equivalences. */ | |
4349 | EXECUTE_IF_SET_IN_BITMAP (&equiv_insn_bitmap, 0, uid, bi) | |
4350 | lra_push_insn_by_uid (uid); | |
55a2c322 VM |
4351 | min_len = lra_insn_stack_length (); |
4352 | new_insns_num = 0; | |
4353 | last_bb = NULL; | |
4354 | changed_p = false; | |
4355 | while ((new_min_len = lra_insn_stack_length ()) != 0) | |
4356 | { | |
4357 | curr_insn = lra_pop_insn (); | |
4358 | --new_min_len; | |
f4eafc30 | 4359 | curr_bb = BLOCK_FOR_INSN (curr_insn); |
55a2c322 VM |
4360 | if (curr_bb != last_bb) |
4361 | { | |
4362 | last_bb = curr_bb; | |
4363 | bb_reload_num = lra_curr_reload_num; | |
4364 | } | |
4365 | if (min_len > new_min_len) | |
4366 | { | |
4367 | min_len = new_min_len; | |
4368 | new_insns_num = 0; | |
4369 | } | |
4370 | if (new_insns_num > MAX_RELOAD_INSNS_NUMBER) | |
4371 | internal_error | |
4372 | ("Max. number of generated reload insns per insn is achieved (%d)\n", | |
4373 | MAX_RELOAD_INSNS_NUMBER); | |
4374 | new_insns_num++; | |
4375 | if (DEBUG_INSN_P (curr_insn)) | |
4376 | { | |
4377 | /* We need to check equivalence in debug insn and change | |
4378 | pseudo to the equivalent value if necessary. */ | |
4379 | curr_id = lra_get_insn_recog_data (curr_insn); | |
d0608e59 | 4380 | if (bitmap_bit_p (&equiv_insn_bitmap, INSN_UID (curr_insn))) |
4d64ce5c | 4381 | { |
d0608e59 JJ |
4382 | rtx old = *curr_id->operand_loc[0]; |
4383 | *curr_id->operand_loc[0] | |
4384 | = simplify_replace_fn_rtx (old, NULL_RTX, | |
4c2b2d79 | 4385 | loc_equivalence_callback, curr_insn); |
d0608e59 JJ |
4386 | if (old != *curr_id->operand_loc[0]) |
4387 | { | |
4388 | lra_update_insn_regno_info (curr_insn); | |
4389 | changed_p = true; | |
4390 | } | |
4d64ce5c | 4391 | } |
55a2c322 VM |
4392 | } |
4393 | else if (INSN_P (curr_insn)) | |
4394 | { | |
4395 | if ((set = single_set (curr_insn)) != NULL_RTX) | |
4396 | { | |
4397 | dest_reg = SET_DEST (set); | |
4398 | /* The equivalence pseudo could be set up as SUBREG in a | |
4399 | case when it is a call restore insn in a mode | |
4400 | different from the pseudo mode. */ | |
4401 | if (GET_CODE (dest_reg) == SUBREG) | |
4402 | dest_reg = SUBREG_REG (dest_reg); | |
4403 | if ((REG_P (dest_reg) | |
8d49e7ef | 4404 | && (x = get_equiv (dest_reg)) != dest_reg |
55a2c322 VM |
4405 | /* Remove insns which set up a pseudo whose value |
4406 | can not be changed. Such insns might be not in | |
4407 | init_insns because we don't update equiv data | |
4408 | during insn transformations. | |
5a107a0f | 4409 | |
55a2c322 VM |
4410 | As an example, let suppose that a pseudo got |
4411 | hard register and on the 1st pass was not | |
4412 | changed to equivalent constant. We generate an | |
4413 | additional insn setting up the pseudo because of | |
4414 | secondary memory movement. Then the pseudo is | |
4415 | spilled and we use the equiv constant. In this | |
4416 | case we should remove the additional insn and | |
f6937e32 | 4417 | this insn is not init_insns list. */ |
55a2c322 | 4418 | && (! MEM_P (x) || MEM_READONLY_P (x) |
f6937e32 VM |
4419 | /* Check that this is actually an insn setting |
4420 | up the equivalence. */ | |
55a2c322 VM |
4421 | || in_list_p (curr_insn, |
4422 | ira_reg_equiv | |
4423 | [REGNO (dest_reg)].init_insns))) | |
8d49e7ef | 4424 | || (((x = get_equiv (SET_SRC (set))) != SET_SRC (set)) |
55a2c322 VM |
4425 | && in_list_p (curr_insn, |
4426 | ira_reg_equiv | |
4427 | [REGNO (SET_SRC (set))].init_insns))) | |
4428 | { | |
4429 | /* This is equiv init insn of pseudo which did not get a | |
4430 | hard register -- remove the insn. */ | |
4431 | if (lra_dump_file != NULL) | |
4432 | { | |
4433 | fprintf (lra_dump_file, | |
4434 | " Removing equiv init insn %i (freq=%d)\n", | |
4435 | INSN_UID (curr_insn), | |
fef37404 | 4436 | REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn))); |
cfbeaedf | 4437 | dump_insn_slim (lra_dump_file, curr_insn); |
55a2c322 VM |
4438 | } |
4439 | if (contains_reg_p (x, true, false)) | |
4440 | lra_risky_transformations_p = true; | |
4441 | lra_set_insn_deleted (curr_insn); | |
4442 | continue; | |
4443 | } | |
4444 | } | |
4445 | curr_id = lra_get_insn_recog_data (curr_insn); | |
4446 | curr_static_id = curr_id->insn_static_data; | |
4447 | init_curr_insn_input_reloads (); | |
4448 | init_curr_operand_mode (); | |
d9cf932c | 4449 | if (curr_insn_transform (false)) |
55a2c322 | 4450 | changed_p = true; |
28430b2e VM |
4451 | /* Check non-transformed insns too for equiv change as USE |
4452 | or CLOBBER don't need reloads but can contain pseudos | |
4453 | being changed on their equivalences. */ | |
4454 | else if (bitmap_bit_p (&equiv_insn_bitmap, INSN_UID (curr_insn)) | |
4455 | && loc_equivalence_change_p (&PATTERN (curr_insn))) | |
4456 | { | |
4457 | lra_update_insn_regno_info (curr_insn); | |
4458 | changed_p = true; | |
4459 | } | |
55a2c322 VM |
4460 | } |
4461 | } | |
28430b2e | 4462 | bitmap_clear (&equiv_insn_bitmap); |
55a2c322 VM |
4463 | /* If we used a new hard regno, changed_p should be true because the |
4464 | hard reg is assigned to a new pseudo. */ | |
b2b29377 | 4465 | if (flag_checking && !changed_p) |
55a2c322 VM |
4466 | { |
4467 | for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++) | |
4468 | if (lra_reg_info[i].nrefs != 0 | |
4469 | && (hard_regno = lra_get_regno_hard_regno (i)) >= 0) | |
4470 | { | |
4471 | int j, nregs = hard_regno_nregs[hard_regno][PSEUDO_REGNO_MODE (i)]; | |
f4eafc30 | 4472 | |
55a2c322 VM |
4473 | for (j = 0; j < nregs; j++) |
4474 | lra_assert (df_regs_ever_live_p (hard_regno + j)); | |
4475 | } | |
4476 | } | |
55a2c322 VM |
4477 | return changed_p; |
4478 | } | |
4479 | ||
4480 | /* Initiate the LRA constraint pass. It is done once per | |
4481 | function. */ | |
4482 | void | |
4483 | lra_constraints_init (void) | |
4484 | { | |
4485 | } | |
4486 | ||
4487 | /* Finalize the LRA constraint pass. It is done once per | |
4488 | function. */ | |
4489 | void | |
4490 | lra_constraints_finish (void) | |
4491 | { | |
4492 | } | |
4493 | ||
4494 | \f | |
4495 | ||
4496 | /* This page contains code to do inheritance/split | |
4497 | transformations. */ | |
4498 | ||
4499 | /* Number of reloads passed so far in current EBB. */ | |
4500 | static int reloads_num; | |
4501 | ||
4502 | /* Number of calls passed so far in current EBB. */ | |
4503 | static int calls_num; | |
4504 | ||
4505 | /* Current reload pseudo check for validity of elements in | |
4506 | USAGE_INSNS. */ | |
4507 | static int curr_usage_insns_check; | |
4508 | ||
4509 | /* Info about last usage of registers in EBB to do inheritance/split | |
4510 | transformation. Inheritance transformation is done from a spilled | |
4511 | pseudo and split transformations from a hard register or a pseudo | |
4512 | assigned to a hard register. */ | |
4513 | struct usage_insns | |
4514 | { | |
4515 | /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member | |
4516 | value INSNS is valid. The insns is chain of optional debug insns | |
1ccd4874 VM |
4517 | and a finishing non-debug insn using the corresponding reg. The |
4518 | value is also used to mark the registers which are set up in the | |
4519 | current insn. The negated insn uid is used for this. */ | |
55a2c322 VM |
4520 | int check; |
4521 | /* Value of global reloads_num at the last insn in INSNS. */ | |
4522 | int reloads_num; | |
4523 | /* Value of global reloads_nums at the last insn in INSNS. */ | |
4524 | int calls_num; | |
4525 | /* It can be true only for splitting. And it means that the restore | |
4526 | insn should be put after insn given by the following member. */ | |
4527 | bool after_p; | |
4528 | /* Next insns in the current EBB which use the original reg and the | |
4529 | original reg value is not changed between the current insn and | |
4530 | the next insns. In order words, e.g. for inheritance, if we need | |
4531 | to use the original reg value again in the next insns we can try | |
4532 | to use the value in a hard register from a reload insn of the | |
4533 | current insn. */ | |
4534 | rtx insns; | |
4535 | }; | |
4536 | ||
4537 | /* Map: regno -> corresponding pseudo usage insns. */ | |
4538 | static struct usage_insns *usage_insns; | |
4539 | ||
4540 | static void | |
1476d1bd | 4541 | setup_next_usage_insn (int regno, rtx insn, int reloads_num, bool after_p) |
55a2c322 VM |
4542 | { |
4543 | usage_insns[regno].check = curr_usage_insns_check; | |
4544 | usage_insns[regno].insns = insn; | |
4545 | usage_insns[regno].reloads_num = reloads_num; | |
4546 | usage_insns[regno].calls_num = calls_num; | |
4547 | usage_insns[regno].after_p = after_p; | |
4548 | } | |
4549 | ||
4550 | /* The function is used to form list REGNO usages which consists of | |
4551 | optional debug insns finished by a non-debug insn using REGNO. | |
4552 | RELOADS_NUM is current number of reload insns processed so far. */ | |
4553 | static void | |
767dc529 | 4554 | add_next_usage_insn (int regno, rtx_insn *insn, int reloads_num) |
55a2c322 VM |
4555 | { |
4556 | rtx next_usage_insns; | |
f4eafc30 | 4557 | |
55a2c322 VM |
4558 | if (usage_insns[regno].check == curr_usage_insns_check |
4559 | && (next_usage_insns = usage_insns[regno].insns) != NULL_RTX | |
4560 | && DEBUG_INSN_P (insn)) | |
4561 | { | |
4562 | /* Check that we did not add the debug insn yet. */ | |
4563 | if (next_usage_insns != insn | |
4564 | && (GET_CODE (next_usage_insns) != INSN_LIST | |
4565 | || XEXP (next_usage_insns, 0) != insn)) | |
4566 | usage_insns[regno].insns = gen_rtx_INSN_LIST (VOIDmode, insn, | |
4567 | next_usage_insns); | |
4568 | } | |
4569 | else if (NONDEBUG_INSN_P (insn)) | |
4570 | setup_next_usage_insn (regno, insn, reloads_num, false); | |
4571 | else | |
4572 | usage_insns[regno].check = 0; | |
4573 | } | |
f4eafc30 | 4574 | |
bc3591eb | 4575 | /* Return first non-debug insn in list USAGE_INSNS. */ |
e8a54173 | 4576 | static rtx_insn * |
bc3591eb VM |
4577 | skip_usage_debug_insns (rtx usage_insns) |
4578 | { | |
4579 | rtx insn; | |
4580 | ||
4581 | /* Skip debug insns. */ | |
4582 | for (insn = usage_insns; | |
4583 | insn != NULL_RTX && GET_CODE (insn) == INSN_LIST; | |
4584 | insn = XEXP (insn, 1)) | |
4585 | ; | |
e8a54173 | 4586 | return safe_as_a <rtx_insn *> (insn); |
bc3591eb VM |
4587 | } |
4588 | ||
4589 | /* Return true if we need secondary memory moves for insn in | |
4590 | USAGE_INSNS after inserting inherited pseudo of class INHER_CL | |
4591 | into the insn. */ | |
4592 | static bool | |
fbebbadd JR |
4593 | check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED, |
4594 | rtx usage_insns ATTRIBUTE_UNUSED) | |
bc3591eb VM |
4595 | { |
4596 | #ifndef SECONDARY_MEMORY_NEEDED | |
4597 | return false; | |
4598 | #else | |
e8a54173 DM |
4599 | rtx_insn *insn; |
4600 | rtx set, dest; | |
bc3591eb VM |
4601 | enum reg_class cl; |
4602 | ||
4603 | if (inher_cl == ALL_REGS | |
4604 | || (insn = skip_usage_debug_insns (usage_insns)) == NULL_RTX) | |
4605 | return false; | |
4606 | lra_assert (INSN_P (insn)); | |
4607 | if ((set = single_set (insn)) == NULL_RTX || ! REG_P (SET_DEST (set))) | |
4608 | return false; | |
4609 | dest = SET_DEST (set); | |
4610 | if (! REG_P (dest)) | |
4611 | return false; | |
4612 | lra_assert (inher_cl != NO_REGS); | |
4613 | cl = get_reg_class (REGNO (dest)); | |
4614 | return (cl != NO_REGS && cl != ALL_REGS | |
4615 | && SECONDARY_MEMORY_NEEDED (inher_cl, cl, GET_MODE (dest))); | |
4616 | #endif | |
4617 | } | |
4618 | ||
55a2c322 VM |
4619 | /* Registers involved in inheritance/split in the current EBB |
4620 | (inheritance/split pseudos and original registers). */ | |
4621 | static bitmap_head check_only_regs; | |
4622 | ||
4623 | /* Do inheritance transformations for insn INSN, which defines (if | |
4624 | DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which | |
4625 | instruction in the EBB next uses ORIGINAL_REGNO; it has the same | |
4626 | form as the "insns" field of usage_insns. Return true if we | |
4627 | succeed in such transformation. | |
4628 | ||
4629 | The transformations look like: | |
4630 | ||
4631 | p <- ... i <- ... | |
4632 | ... p <- i (new insn) | |
4633 | ... => | |
4634 | <- ... p ... <- ... i ... | |
4635 | or | |
4636 | ... i <- p (new insn) | |
4637 | <- ... p ... <- ... i ... | |
4638 | ... => | |
4639 | <- ... p ... <- ... i ... | |
4640 | where p is a spilled original pseudo and i is a new inheritance pseudo. | |
f4eafc30 L |
4641 | |
4642 | ||
55a2c322 VM |
4643 | The inheritance pseudo has the smallest class of two classes CL and |
4644 | class of ORIGINAL REGNO. */ | |
4645 | static bool | |
4646 | inherit_reload_reg (bool def_p, int original_regno, | |
cfa434f6 | 4647 | enum reg_class cl, rtx_insn *insn, rtx next_usage_insns) |
55a2c322 | 4648 | { |
2ae577fd VM |
4649 | if (optimize_function_for_size_p (cfun)) |
4650 | return false; | |
4651 | ||
55a2c322 VM |
4652 | enum reg_class rclass = lra_get_allocno_class (original_regno); |
4653 | rtx original_reg = regno_reg_rtx[original_regno]; | |
cfa434f6 DM |
4654 | rtx new_reg, usage_insn; |
4655 | rtx_insn *new_insns; | |
55a2c322 VM |
4656 | |
4657 | lra_assert (! usage_insns[original_regno].after_p); | |
4658 | if (lra_dump_file != NULL) | |
4659 | fprintf (lra_dump_file, | |
bc3591eb | 4660 | " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n"); |
55a2c322 VM |
4661 | if (! ira_reg_classes_intersect_p[cl][rclass]) |
4662 | { | |
4663 | if (lra_dump_file != NULL) | |
4664 | { | |
4665 | fprintf (lra_dump_file, | |
bc3591eb | 4666 | " Rejecting inheritance for %d " |
55a2c322 VM |
4667 | "because of disjoint classes %s and %s\n", |
4668 | original_regno, reg_class_names[cl], | |
4669 | reg_class_names[rclass]); | |
4670 | fprintf (lra_dump_file, | |
bc3591eb | 4671 | " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); |
55a2c322 VM |
4672 | } |
4673 | return false; | |
4674 | } | |
4675 | if ((ira_class_subset_p[cl][rclass] && cl != rclass) | |
4676 | /* We don't use a subset of two classes because it can be | |
4677 | NO_REGS. This transformation is still profitable in most | |
4678 | cases even if the classes are not intersected as register | |
4679 | move is probably cheaper than a memory load. */ | |
4680 | || ira_class_hard_regs_num[cl] < ira_class_hard_regs_num[rclass]) | |
4681 | { | |
4682 | if (lra_dump_file != NULL) | |
4683 | fprintf (lra_dump_file, " Use smallest class of %s and %s\n", | |
4684 | reg_class_names[cl], reg_class_names[rclass]); | |
f4eafc30 | 4685 | |
55a2c322 VM |
4686 | rclass = cl; |
4687 | } | |
66aa7879 | 4688 | if (check_secondary_memory_needed_p (rclass, next_usage_insns)) |
bc3591eb VM |
4689 | { |
4690 | /* Reject inheritance resulting in secondary memory moves. | |
4691 | Otherwise, there is a danger in LRA cycling. Also such | |
4692 | transformation will be unprofitable. */ | |
4693 | if (lra_dump_file != NULL) | |
4694 | { | |
e8a54173 | 4695 | rtx_insn *insn = skip_usage_debug_insns (next_usage_insns); |
bc3591eb VM |
4696 | rtx set = single_set (insn); |
4697 | ||
4698 | lra_assert (set != NULL_RTX); | |
4699 | ||
4700 | rtx dest = SET_DEST (set); | |
4701 | ||
4702 | lra_assert (REG_P (dest)); | |
4703 | fprintf (lra_dump_file, | |
4704 | " Rejecting inheritance for insn %d(%s)<-%d(%s) " | |
4705 | "as secondary mem is needed\n", | |
4706 | REGNO (dest), reg_class_names[get_reg_class (REGNO (dest))], | |
66aa7879 | 4707 | original_regno, reg_class_names[rclass]); |
bc3591eb VM |
4708 | fprintf (lra_dump_file, |
4709 | " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); | |
4710 | } | |
4711 | return false; | |
4712 | } | |
55a2c322 VM |
4713 | new_reg = lra_create_new_reg (GET_MODE (original_reg), original_reg, |
4714 | rclass, "inheritance"); | |
4715 | start_sequence (); | |
4716 | if (def_p) | |
a810ee82 | 4717 | lra_emit_move (original_reg, new_reg); |
55a2c322 | 4718 | else |
a810ee82 | 4719 | lra_emit_move (new_reg, original_reg); |
55a2c322 VM |
4720 | new_insns = get_insns (); |
4721 | end_sequence (); | |
4722 | if (NEXT_INSN (new_insns) != NULL_RTX) | |
4723 | { | |
4724 | if (lra_dump_file != NULL) | |
4725 | { | |
4726 | fprintf (lra_dump_file, | |
bc3591eb | 4727 | " Rejecting inheritance %d->%d " |
55a2c322 VM |
4728 | "as it results in 2 or more insns:\n", |
4729 | original_regno, REGNO (new_reg)); | |
dc01c3d1 | 4730 | dump_rtl_slim (lra_dump_file, new_insns, NULL, -1, 0); |
55a2c322 VM |
4731 | fprintf (lra_dump_file, |
4732 | " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); | |
4733 | } | |
4734 | return false; | |
4735 | } | |
ef87312e | 4736 | lra_substitute_pseudo_within_insn (insn, original_regno, new_reg, false); |
55a2c322 VM |
4737 | lra_update_insn_regno_info (insn); |
4738 | if (! def_p) | |
4739 | /* We now have a new usage insn for original regno. */ | |
4740 | setup_next_usage_insn (original_regno, new_insns, reloads_num, false); | |
4741 | if (lra_dump_file != NULL) | |
bc3591eb | 4742 | fprintf (lra_dump_file, " Original reg change %d->%d (bb%d):\n", |
55a2c322 VM |
4743 | original_regno, REGNO (new_reg), BLOCK_FOR_INSN (insn)->index); |
4744 | lra_reg_info[REGNO (new_reg)].restore_regno = original_regno; | |
4745 | bitmap_set_bit (&check_only_regs, REGNO (new_reg)); | |
4746 | bitmap_set_bit (&check_only_regs, original_regno); | |
4747 | bitmap_set_bit (&lra_inheritance_pseudos, REGNO (new_reg)); | |
4748 | if (def_p) | |
cfa434f6 | 4749 | lra_process_new_insns (insn, NULL, new_insns, |
55a2c322 VM |
4750 | "Add original<-inheritance"); |
4751 | else | |
cfa434f6 | 4752 | lra_process_new_insns (insn, new_insns, NULL, |
55a2c322 VM |
4753 | "Add inheritance<-original"); |
4754 | while (next_usage_insns != NULL_RTX) | |
4755 | { | |
4756 | if (GET_CODE (next_usage_insns) != INSN_LIST) | |
4757 | { | |
4758 | usage_insn = next_usage_insns; | |
4759 | lra_assert (NONDEBUG_INSN_P (usage_insn)); | |
4760 | next_usage_insns = NULL; | |
4761 | } | |
4762 | else | |
4763 | { | |
4764 | usage_insn = XEXP (next_usage_insns, 0); | |
4765 | lra_assert (DEBUG_INSN_P (usage_insn)); | |
4766 | next_usage_insns = XEXP (next_usage_insns, 1); | |
4767 | } | |
ef87312e | 4768 | lra_substitute_pseudo (&usage_insn, original_regno, new_reg, false); |
cfa434f6 | 4769 | lra_update_insn_regno_info (as_a <rtx_insn *> (usage_insn)); |
55a2c322 VM |
4770 | if (lra_dump_file != NULL) |
4771 | { | |
4772 | fprintf (lra_dump_file, | |
4773 | " Inheritance reuse change %d->%d (bb%d):\n", | |
4774 | original_regno, REGNO (new_reg), | |
4775 | BLOCK_FOR_INSN (usage_insn)->index); | |
1476d1bd | 4776 | dump_insn_slim (lra_dump_file, as_a <rtx_insn *> (usage_insn)); |
55a2c322 VM |
4777 | } |
4778 | } | |
4779 | if (lra_dump_file != NULL) | |
4780 | fprintf (lra_dump_file, | |
4781 | " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); | |
4782 | return true; | |
4783 | } | |
4784 | ||
4785 | /* Return true if we need a caller save/restore for pseudo REGNO which | |
4786 | was assigned to a hard register. */ | |
4787 | static inline bool | |
4788 | need_for_call_save_p (int regno) | |
4789 | { | |
4790 | lra_assert (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] >= 0); | |
4791 | return (usage_insns[regno].calls_num < calls_num | |
4792 | && (overlaps_hard_reg_set_p | |
1e288103 | 4793 | ((flag_ipa_ra && |
10e1bdb2 TV |
4794 | ! hard_reg_set_empty_p (lra_reg_info[regno].actual_call_used_reg_set)) |
4795 | ? lra_reg_info[regno].actual_call_used_reg_set | |
4796 | : call_used_reg_set, | |
8a26ad39 VM |
4797 | PSEUDO_REGNO_MODE (regno), reg_renumber[regno]) |
4798 | || HARD_REGNO_CALL_PART_CLOBBERED (reg_renumber[regno], | |
4799 | PSEUDO_REGNO_MODE (regno)))); | |
55a2c322 VM |
4800 | } |
4801 | ||
1aa95df7 | 4802 | /* Global registers occurring in the current EBB. */ |
55a2c322 VM |
4803 | static bitmap_head ebb_global_regs; |
4804 | ||
4805 | /* Return true if we need a split for hard register REGNO or pseudo | |
4806 | REGNO which was assigned to a hard register. | |
4807 | POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be | |
4808 | used for reloads since the EBB end. It is an approximation of the | |
4809 | used hard registers in the split range. The exact value would | |
4810 | require expensive calculations. If we were aggressive with | |
4811 | splitting because of the approximation, the split pseudo will save | |
4812 | the same hard register assignment and will be removed in the undo | |
4813 | pass. We still need the approximation because too aggressive | |
4814 | splitting would result in too inaccurate cost calculation in the | |
4815 | assignment pass because of too many generated moves which will be | |
4816 | probably removed in the undo pass. */ | |
4817 | static inline bool | |
4818 | need_for_split_p (HARD_REG_SET potential_reload_hard_regs, int regno) | |
4819 | { | |
4820 | int hard_regno = regno < FIRST_PSEUDO_REGISTER ? regno : reg_renumber[regno]; | |
4821 | ||
4822 | lra_assert (hard_regno >= 0); | |
4823 | return ((TEST_HARD_REG_BIT (potential_reload_hard_regs, hard_regno) | |
4824 | /* Don't split eliminable hard registers, otherwise we can | |
4825 | split hard registers like hard frame pointer, which | |
4826 | lives on BB start/end according to DF-infrastructure, | |
4827 | when there is a pseudo assigned to the register and | |
4828 | living in the same BB. */ | |
4829 | && (regno >= FIRST_PSEUDO_REGISTER | |
4830 | || ! TEST_HARD_REG_BIT (eliminable_regset, hard_regno)) | |
4831 | && ! TEST_HARD_REG_BIT (lra_no_alloc_regs, hard_regno) | |
e32e4c4a VM |
4832 | /* Don't split call clobbered hard regs living through |
4833 | calls, otherwise we might have a check problem in the | |
4834 | assign sub-pass as in the most cases (exception is a | |
4835 | situation when lra_risky_transformations_p value is | |
4836 | true) the assign pass assumes that all pseudos living | |
4837 | through calls are assigned to call saved hard regs. */ | |
4838 | && (regno >= FIRST_PSEUDO_REGISTER | |
4839 | || ! TEST_HARD_REG_BIT (call_used_reg_set, regno) | |
4840 | || usage_insns[regno].calls_num == calls_num) | |
55a2c322 VM |
4841 | /* We need at least 2 reloads to make pseudo splitting |
4842 | profitable. We should provide hard regno splitting in | |
4843 | any case to solve 1st insn scheduling problem when | |
4844 | moving hard register definition up might result in | |
4845 | impossibility to find hard register for reload pseudo of | |
4846 | small register class. */ | |
4847 | && (usage_insns[regno].reloads_num | |
8e9d68a9 | 4848 | + (regno < FIRST_PSEUDO_REGISTER ? 0 : 3) < reloads_num) |
55a2c322 VM |
4849 | && (regno < FIRST_PSEUDO_REGISTER |
4850 | /* For short living pseudos, spilling + inheritance can | |
4851 | be considered a substitution for splitting. | |
4852 | Therefore we do not splitting for local pseudos. It | |
4853 | decreases also aggressiveness of splitting. The | |
4854 | minimal number of references is chosen taking into | |
4855 | account that for 2 references splitting has no sense | |
4856 | as we can just spill the pseudo. */ | |
4857 | || (regno >= FIRST_PSEUDO_REGISTER | |
4858 | && lra_reg_info[regno].nrefs > 3 | |
4859 | && bitmap_bit_p (&ebb_global_regs, regno)))) | |
4860 | || (regno >= FIRST_PSEUDO_REGISTER && need_for_call_save_p (regno))); | |
4861 | } | |
4862 | ||
4863 | /* Return class for the split pseudo created from original pseudo with | |
4864 | ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We | |
4865 | choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and | |
4866 | results in no secondary memory movements. */ | |
4867 | static enum reg_class | |
4868 | choose_split_class (enum reg_class allocno_class, | |
4869 | int hard_regno ATTRIBUTE_UNUSED, | |
ef4bddc2 | 4870 | machine_mode mode ATTRIBUTE_UNUSED) |
55a2c322 VM |
4871 | { |
4872 | #ifndef SECONDARY_MEMORY_NEEDED | |
4873 | return allocno_class; | |
4874 | #else | |
4875 | int i; | |
4876 | enum reg_class cl, best_cl = NO_REGS; | |
ef4dbe49 JR |
4877 | enum reg_class hard_reg_class ATTRIBUTE_UNUSED |
4878 | = REGNO_REG_CLASS (hard_regno); | |
f4eafc30 | 4879 | |
55a2c322 VM |
4880 | if (! SECONDARY_MEMORY_NEEDED (allocno_class, allocno_class, mode) |
4881 | && TEST_HARD_REG_BIT (reg_class_contents[allocno_class], hard_regno)) | |
4882 | return allocno_class; | |
4883 | for (i = 0; | |
4884 | (cl = reg_class_subclasses[allocno_class][i]) != LIM_REG_CLASSES; | |
4885 | i++) | |
4886 | if (! SECONDARY_MEMORY_NEEDED (cl, hard_reg_class, mode) | |
4887 | && ! SECONDARY_MEMORY_NEEDED (hard_reg_class, cl, mode) | |
4888 | && TEST_HARD_REG_BIT (reg_class_contents[cl], hard_regno) | |
4889 | && (best_cl == NO_REGS | |
4890 | || ira_class_hard_regs_num[best_cl] < ira_class_hard_regs_num[cl])) | |
4891 | best_cl = cl; | |
4892 | return best_cl; | |
4893 | #endif | |
4894 | } | |
4895 | ||
4896 | /* Do split transformations for insn INSN, which defines or uses | |
4897 | ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in | |
4898 | the EBB next uses ORIGINAL_REGNO; it has the same form as the | |
4899 | "insns" field of usage_insns. | |
4900 | ||
4901 | The transformations look like: | |
4902 | ||
4903 | p <- ... p <- ... | |
4904 | ... s <- p (new insn -- save) | |
4905 | ... => | |
4906 | ... p <- s (new insn -- restore) | |
4907 | <- ... p ... <- ... p ... | |
4908 | or | |
4909 | <- ... p ... <- ... p ... | |
4910 | ... s <- p (new insn -- save) | |
4911 | ... => | |
4912 | ... p <- s (new insn -- restore) | |
4913 | <- ... p ... <- ... p ... | |
4914 | ||
4915 | where p is an original pseudo got a hard register or a hard | |
4916 | register and s is a new split pseudo. The save is put before INSN | |
4917 | if BEFORE_P is true. Return true if we succeed in such | |
4918 | transformation. */ | |
4919 | static bool | |
cfa434f6 DM |
4920 | split_reg (bool before_p, int original_regno, rtx_insn *insn, |
4921 | rtx next_usage_insns) | |
55a2c322 VM |
4922 | { |
4923 | enum reg_class rclass; | |
4924 | rtx original_reg; | |
77bce07c | 4925 | int hard_regno, nregs; |
cfa434f6 DM |
4926 | rtx new_reg, usage_insn; |
4927 | rtx_insn *restore, *save; | |
55a2c322 VM |
4928 | bool after_p; |
4929 | bool call_save_p; | |
4930 | ||
4931 | if (original_regno < FIRST_PSEUDO_REGISTER) | |
4932 | { | |
4933 | rclass = ira_allocno_class_translate[REGNO_REG_CLASS (original_regno)]; | |
4934 | hard_regno = original_regno; | |
4935 | call_save_p = false; | |
77bce07c | 4936 | nregs = 1; |
55a2c322 VM |
4937 | } |
4938 | else | |
4939 | { | |
4940 | hard_regno = reg_renumber[original_regno]; | |
77bce07c | 4941 | nregs = hard_regno_nregs[hard_regno][PSEUDO_REGNO_MODE (original_regno)]; |
55a2c322 VM |
4942 | rclass = lra_get_allocno_class (original_regno); |
4943 | original_reg = regno_reg_rtx[original_regno]; | |
4944 | call_save_p = need_for_call_save_p (original_regno); | |
4945 | } | |
4946 | original_reg = regno_reg_rtx[original_regno]; | |
4947 | lra_assert (hard_regno >= 0); | |
4948 | if (lra_dump_file != NULL) | |
4949 | fprintf (lra_dump_file, | |
4950 | " ((((((((((((((((((((((((((((((((((((((((((((((((\n"); | |
4951 | if (call_save_p) | |
4952 | { | |
ef4bddc2 | 4953 | machine_mode mode = GET_MODE (original_reg); |
f4eafc30 | 4954 | |
cb1cca12 VM |
4955 | mode = HARD_REGNO_CALLER_SAVE_MODE (hard_regno, |
4956 | hard_regno_nregs[hard_regno][mode], | |
4957 | mode); | |
4958 | new_reg = lra_create_new_reg (mode, NULL_RTX, NO_REGS, "save"); | |
55a2c322 VM |
4959 | } |
4960 | else | |
4961 | { | |
4962 | rclass = choose_split_class (rclass, hard_regno, | |
4963 | GET_MODE (original_reg)); | |
4964 | if (rclass == NO_REGS) | |
4965 | { | |
4966 | if (lra_dump_file != NULL) | |
4967 | { | |
4968 | fprintf (lra_dump_file, | |
4969 | " Rejecting split of %d(%s): " | |
4970 | "no good reg class for %d(%s)\n", | |
4971 | original_regno, | |
4972 | reg_class_names[lra_get_allocno_class (original_regno)], | |
4973 | hard_regno, | |
4974 | reg_class_names[REGNO_REG_CLASS (hard_regno)]); | |
4975 | fprintf | |
4976 | (lra_dump_file, | |
4977 | " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); | |
4978 | } | |
4979 | return false; | |
4980 | } | |
4981 | new_reg = lra_create_new_reg (GET_MODE (original_reg), original_reg, | |
4982 | rclass, "split"); | |
4983 | reg_renumber[REGNO (new_reg)] = hard_regno; | |
4984 | } | |
4985 | save = emit_spill_move (true, new_reg, original_reg); | |
c61fe0cc | 4986 | if (NEXT_INSN (save) != NULL_RTX && !call_save_p) |
55a2c322 | 4987 | { |
55a2c322 VM |
4988 | if (lra_dump_file != NULL) |
4989 | { | |
4990 | fprintf | |
4991 | (lra_dump_file, | |
c61fe0cc KC |
4992 | " Rejecting split %d->%d resulting in > 2 save insns:\n", |
4993 | original_regno, REGNO (new_reg)); | |
dc01c3d1 | 4994 | dump_rtl_slim (lra_dump_file, save, NULL, -1, 0); |
55a2c322 VM |
4995 | fprintf (lra_dump_file, |
4996 | " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); | |
4997 | } | |
4998 | return false; | |
4999 | } | |
5000 | restore = emit_spill_move (false, new_reg, original_reg); | |
c61fe0cc | 5001 | if (NEXT_INSN (restore) != NULL_RTX && !call_save_p) |
55a2c322 | 5002 | { |
55a2c322 VM |
5003 | if (lra_dump_file != NULL) |
5004 | { | |
5005 | fprintf (lra_dump_file, | |
5006 | " Rejecting split %d->%d " | |
c61fe0cc KC |
5007 | "resulting in > 2 restore insns:\n", |
5008 | original_regno, REGNO (new_reg)); | |
dc01c3d1 | 5009 | dump_rtl_slim (lra_dump_file, restore, NULL, -1, 0); |
55a2c322 VM |
5010 | fprintf (lra_dump_file, |
5011 | " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); | |
5012 | } | |
5013 | return false; | |
5014 | } | |
5015 | after_p = usage_insns[original_regno].after_p; | |
5016 | lra_reg_info[REGNO (new_reg)].restore_regno = original_regno; | |
5017 | bitmap_set_bit (&check_only_regs, REGNO (new_reg)); | |
5018 | bitmap_set_bit (&check_only_regs, original_regno); | |
5019 | bitmap_set_bit (&lra_split_regs, REGNO (new_reg)); | |
5020 | for (;;) | |
5021 | { | |
5022 | if (GET_CODE (next_usage_insns) != INSN_LIST) | |
5023 | { | |
5024 | usage_insn = next_usage_insns; | |
5025 | break; | |
5026 | } | |
5027 | usage_insn = XEXP (next_usage_insns, 0); | |
5028 | lra_assert (DEBUG_INSN_P (usage_insn)); | |
5029 | next_usage_insns = XEXP (next_usage_insns, 1); | |
ef87312e | 5030 | lra_substitute_pseudo (&usage_insn, original_regno, new_reg, false); |
cfa434f6 | 5031 | lra_update_insn_regno_info (as_a <rtx_insn *> (usage_insn)); |
55a2c322 VM |
5032 | if (lra_dump_file != NULL) |
5033 | { | |
5034 | fprintf (lra_dump_file, " Split reuse change %d->%d:\n", | |
5035 | original_regno, REGNO (new_reg)); | |
1476d1bd | 5036 | dump_insn_slim (lra_dump_file, as_a <rtx_insn *> (usage_insn)); |
55a2c322 VM |
5037 | } |
5038 | } | |
5039 | lra_assert (NOTE_P (usage_insn) || NONDEBUG_INSN_P (usage_insn)); | |
5040 | lra_assert (usage_insn != insn || (after_p && before_p)); | |
cfa434f6 DM |
5041 | lra_process_new_insns (as_a <rtx_insn *> (usage_insn), |
5042 | after_p ? NULL : restore, | |
5043 | after_p ? restore : NULL, | |
55a2c322 VM |
5044 | call_save_p |
5045 | ? "Add reg<-save" : "Add reg<-split"); | |
cfa434f6 DM |
5046 | lra_process_new_insns (insn, before_p ? save : NULL, |
5047 | before_p ? NULL : save, | |
55a2c322 VM |
5048 | call_save_p |
5049 | ? "Add save<-reg" : "Add split<-reg"); | |
77bce07c VM |
5050 | if (nregs > 1) |
5051 | /* If we are trying to split multi-register. We should check | |
5052 | conflicts on the next assignment sub-pass. IRA can allocate on | |
5053 | sub-register levels, LRA do this on pseudos level right now and | |
5054 | this discrepancy may create allocation conflicts after | |
5055 | splitting. */ | |
5056 | lra_risky_transformations_p = true; | |
55a2c322 VM |
5057 | if (lra_dump_file != NULL) |
5058 | fprintf (lra_dump_file, | |
5059 | " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); | |
5060 | return true; | |
5061 | } | |
5062 | ||
5063 | /* Recognize that we need a split transformation for insn INSN, which | |
5064 | defines or uses REGNO in its insn biggest MODE (we use it only if | |
5065 | REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains | |
5066 | hard registers which might be used for reloads since the EBB end. | |
5067 | Put the save before INSN if BEFORE_P is true. MAX_UID is maximla | |
5068 | uid before starting INSN processing. Return true if we succeed in | |
5069 | such transformation. */ | |
5070 | static bool | |
ef4bddc2 | 5071 | split_if_necessary (int regno, machine_mode mode, |
55a2c322 | 5072 | HARD_REG_SET potential_reload_hard_regs, |
cfa434f6 | 5073 | bool before_p, rtx_insn *insn, int max_uid) |
55a2c322 VM |
5074 | { |
5075 | bool res = false; | |
5076 | int i, nregs = 1; | |
5077 | rtx next_usage_insns; | |
5078 | ||
5079 | if (regno < FIRST_PSEUDO_REGISTER) | |
5080 | nregs = hard_regno_nregs[regno][mode]; | |
5081 | for (i = 0; i < nregs; i++) | |
5082 | if (usage_insns[regno + i].check == curr_usage_insns_check | |
5083 | && (next_usage_insns = usage_insns[regno + i].insns) != NULL_RTX | |
5084 | /* To avoid processing the register twice or more. */ | |
5085 | && ((GET_CODE (next_usage_insns) != INSN_LIST | |
5086 | && INSN_UID (next_usage_insns) < max_uid) | |
5087 | || (GET_CODE (next_usage_insns) == INSN_LIST | |
5088 | && (INSN_UID (XEXP (next_usage_insns, 0)) < max_uid))) | |
5089 | && need_for_split_p (potential_reload_hard_regs, regno + i) | |
5090 | && split_reg (before_p, regno + i, insn, next_usage_insns)) | |
5091 | res = true; | |
5092 | return res; | |
5093 | } | |
5094 | ||
5095 | /* Check only registers living at the current program point in the | |
5096 | current EBB. */ | |
5097 | static bitmap_head live_regs; | |
5098 | ||
5099 | /* Update live info in EBB given by its HEAD and TAIL insns after | |
5100 | inheritance/split transformation. The function removes dead moves | |
5101 | too. */ | |
5102 | static void | |
cfa434f6 | 5103 | update_ebb_live_info (rtx_insn *head, rtx_insn *tail) |
55a2c322 VM |
5104 | { |
5105 | unsigned int j; | |
8e9d68a9 | 5106 | int i, regno; |
55a2c322 | 5107 | bool live_p; |
cfa434f6 DM |
5108 | rtx_insn *prev_insn; |
5109 | rtx set; | |
55a2c322 VM |
5110 | bool remove_p; |
5111 | basic_block last_bb, prev_bb, curr_bb; | |
5112 | bitmap_iterator bi; | |
5113 | struct lra_insn_reg *reg; | |
5114 | edge e; | |
5115 | edge_iterator ei; | |
5116 | ||
f4eafc30 | 5117 | last_bb = BLOCK_FOR_INSN (tail); |
55a2c322 VM |
5118 | prev_bb = NULL; |
5119 | for (curr_insn = tail; | |
5120 | curr_insn != PREV_INSN (head); | |
5121 | curr_insn = prev_insn) | |
5122 | { | |
5123 | prev_insn = PREV_INSN (curr_insn); | |
911598e3 VM |
5124 | /* We need to process empty blocks too. They contain |
5125 | NOTE_INSN_BASIC_BLOCK referring for the basic block. */ | |
5126 | if (NOTE_P (curr_insn) && NOTE_KIND (curr_insn) != NOTE_INSN_BASIC_BLOCK) | |
5127 | continue; | |
55a2c322 VM |
5128 | curr_bb = BLOCK_FOR_INSN (curr_insn); |
5129 | if (curr_bb != prev_bb) | |
5130 | { | |
5131 | if (prev_bb != NULL) | |
5132 | { | |
5133 | /* Update df_get_live_in (prev_bb): */ | |
5134 | EXECUTE_IF_SET_IN_BITMAP (&check_only_regs, 0, j, bi) | |
5135 | if (bitmap_bit_p (&live_regs, j)) | |
5136 | bitmap_set_bit (df_get_live_in (prev_bb), j); | |
5137 | else | |
5138 | bitmap_clear_bit (df_get_live_in (prev_bb), j); | |
5139 | } | |
5140 | if (curr_bb != last_bb) | |
5141 | { | |
5142 | /* Update df_get_live_out (curr_bb): */ | |
5143 | EXECUTE_IF_SET_IN_BITMAP (&check_only_regs, 0, j, bi) | |
5144 | { | |
5145 | live_p = bitmap_bit_p (&live_regs, j); | |
5146 | if (! live_p) | |
5147 | FOR_EACH_EDGE (e, ei, curr_bb->succs) | |
5148 | if (bitmap_bit_p (df_get_live_in (e->dest), j)) | |
5149 | { | |
5150 | live_p = true; | |
5151 | break; | |
5152 | } | |
5153 | if (live_p) | |
5154 | bitmap_set_bit (df_get_live_out (curr_bb), j); | |
5155 | else | |
5156 | bitmap_clear_bit (df_get_live_out (curr_bb), j); | |
5157 | } | |
5158 | } | |
5159 | prev_bb = curr_bb; | |
5160 | bitmap_and (&live_regs, &check_only_regs, df_get_live_out (curr_bb)); | |
5161 | } | |
44b94bdb | 5162 | if (! NONDEBUG_INSN_P (curr_insn)) |
55a2c322 VM |
5163 | continue; |
5164 | curr_id = lra_get_insn_recog_data (curr_insn); | |
8e9d68a9 | 5165 | curr_static_id = curr_id->insn_static_data; |
55a2c322 VM |
5166 | remove_p = false; |
5167 | if ((set = single_set (curr_insn)) != NULL_RTX && REG_P (SET_DEST (set)) | |
5168 | && (regno = REGNO (SET_DEST (set))) >= FIRST_PSEUDO_REGISTER | |
5169 | && bitmap_bit_p (&check_only_regs, regno) | |
5170 | && ! bitmap_bit_p (&live_regs, regno)) | |
5171 | remove_p = true; | |
5172 | /* See which defined values die here. */ | |
5173 | for (reg = curr_id->regs; reg != NULL; reg = reg->next) | |
5174 | if (reg->type == OP_OUT && ! reg->subreg_p) | |
5175 | bitmap_clear_bit (&live_regs, reg->regno); | |
8e9d68a9 VM |
5176 | for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next) |
5177 | if (reg->type == OP_OUT && ! reg->subreg_p) | |
5178 | bitmap_clear_bit (&live_regs, reg->regno); | |
9d86e84e VM |
5179 | if (curr_id->arg_hard_regs != NULL) |
5180 | /* Make clobbered argument hard registers die. */ | |
5181 | for (i = 0; (regno = curr_id->arg_hard_regs[i]) >= 0; i++) | |
5182 | if (regno >= FIRST_PSEUDO_REGISTER) | |
5183 | bitmap_clear_bit (&live_regs, regno - FIRST_PSEUDO_REGISTER); | |
55a2c322 VM |
5184 | /* Mark each used value as live. */ |
5185 | for (reg = curr_id->regs; reg != NULL; reg = reg->next) | |
d89ae27c | 5186 | if (reg->type != OP_OUT |
55a2c322 VM |
5187 | && bitmap_bit_p (&check_only_regs, reg->regno)) |
5188 | bitmap_set_bit (&live_regs, reg->regno); | |
8e9d68a9 VM |
5189 | for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next) |
5190 | if (reg->type != OP_OUT | |
5191 | && bitmap_bit_p (&check_only_regs, reg->regno)) | |
5192 | bitmap_set_bit (&live_regs, reg->regno); | |
5193 | if (curr_id->arg_hard_regs != NULL) | |
9d86e84e | 5194 | /* Make used argument hard registers live. */ |
8e9d68a9 | 5195 | for (i = 0; (regno = curr_id->arg_hard_regs[i]) >= 0; i++) |
9d86e84e VM |
5196 | if (regno < FIRST_PSEUDO_REGISTER |
5197 | && bitmap_bit_p (&check_only_regs, regno)) | |
8e9d68a9 | 5198 | bitmap_set_bit (&live_regs, regno); |
55a2c322 VM |
5199 | /* It is quite important to remove dead move insns because it |
5200 | means removing dead store. We don't need to process them for | |
5201 | constraints. */ | |
5202 | if (remove_p) | |
5203 | { | |
5204 | if (lra_dump_file != NULL) | |
5205 | { | |
5206 | fprintf (lra_dump_file, " Removing dead insn:\n "); | |
cfbeaedf | 5207 | dump_insn_slim (lra_dump_file, curr_insn); |
55a2c322 VM |
5208 | } |
5209 | lra_set_insn_deleted (curr_insn); | |
5210 | } | |
5211 | } | |
5212 | } | |
5213 | ||
5214 | /* The structure describes info to do an inheritance for the current | |
5215 | insn. We need to collect such info first before doing the | |
5216 | transformations because the transformations change the insn | |
5217 | internal representation. */ | |
5218 | struct to_inherit | |
5219 | { | |
5220 | /* Original regno. */ | |
5221 | int regno; | |
5222 | /* Subsequent insns which can inherit original reg value. */ | |
5223 | rtx insns; | |
5224 | }; | |
5225 | ||
5226 | /* Array containing all info for doing inheritance from the current | |
5227 | insn. */ | |
5228 | static struct to_inherit to_inherit[LRA_MAX_INSN_RELOADS]; | |
5229 | ||
5230 | /* Number elements in the previous array. */ | |
5231 | static int to_inherit_num; | |
5232 | ||
5233 | /* Add inheritance info REGNO and INSNS. Their meaning is described in | |
5234 | structure to_inherit. */ | |
5235 | static void | |
5236 | add_to_inherit (int regno, rtx insns) | |
5237 | { | |
5238 | int i; | |
5239 | ||
5240 | for (i = 0; i < to_inherit_num; i++) | |
5241 | if (to_inherit[i].regno == regno) | |
5242 | return; | |
5243 | lra_assert (to_inherit_num < LRA_MAX_INSN_RELOADS); | |
5244 | to_inherit[to_inherit_num].regno = regno; | |
5245 | to_inherit[to_inherit_num++].insns = insns; | |
5246 | } | |
5247 | ||
5248 | /* Return the last non-debug insn in basic block BB, or the block begin | |
5249 | note if none. */ | |
cfa434f6 | 5250 | static rtx_insn * |
55a2c322 VM |
5251 | get_last_insertion_point (basic_block bb) |
5252 | { | |
cfa434f6 | 5253 | rtx_insn *insn; |
55a2c322 VM |
5254 | |
5255 | FOR_BB_INSNS_REVERSE (bb, insn) | |
5256 | if (NONDEBUG_INSN_P (insn) || NOTE_INSN_BASIC_BLOCK_P (insn)) | |
5257 | return insn; | |
5258 | gcc_unreachable (); | |
5259 | } | |
5260 | ||
5261 | /* Set up RES by registers living on edges FROM except the edge (FROM, | |
5262 | TO) or by registers set up in a jump insn in BB FROM. */ | |
5263 | static void | |
5264 | get_live_on_other_edges (basic_block from, basic_block to, bitmap res) | |
5265 | { | |
cfa434f6 | 5266 | rtx_insn *last; |
55a2c322 VM |
5267 | struct lra_insn_reg *reg; |
5268 | edge e; | |
5269 | edge_iterator ei; | |
5270 | ||
5271 | lra_assert (to != NULL); | |
5272 | bitmap_clear (res); | |
5273 | FOR_EACH_EDGE (e, ei, from->succs) | |
5274 | if (e->dest != to) | |
5275 | bitmap_ior_into (res, df_get_live_in (e->dest)); | |
5276 | last = get_last_insertion_point (from); | |
5277 | if (! JUMP_P (last)) | |
5278 | return; | |
5279 | curr_id = lra_get_insn_recog_data (last); | |
5280 | for (reg = curr_id->regs; reg != NULL; reg = reg->next) | |
5281 | if (reg->type != OP_IN) | |
5282 | bitmap_set_bit (res, reg->regno); | |
5283 | } | |
f4eafc30 | 5284 | |
55a2c322 VM |
5285 | /* Used as a temporary results of some bitmap calculations. */ |
5286 | static bitmap_head temp_bitmap; | |
5287 | ||
8e9d68a9 VM |
5288 | /* We split for reloads of small class of hard regs. The following |
5289 | defines how many hard regs the class should have to be qualified as | |
5290 | small. The code is mostly oriented to x86/x86-64 architecture | |
5291 | where some insns need to use only specific register or pair of | |
5292 | registers and these register can live in RTL explicitly, e.g. for | |
5293 | parameter passing. */ | |
5294 | static const int max_small_class_regs_num = 2; | |
5295 | ||
55a2c322 VM |
5296 | /* Do inheritance/split transformations in EBB starting with HEAD and |
5297 | finishing on TAIL. We process EBB insns in the reverse order. | |
5298 | Return true if we did any inheritance/split transformation in the | |
5299 | EBB. | |
5300 | ||
5301 | We should avoid excessive splitting which results in worse code | |
5302 | because of inaccurate cost calculations for spilling new split | |
5303 | pseudos in such case. To achieve this we do splitting only if | |
5304 | register pressure is high in given basic block and there are reload | |
5305 | pseudos requiring hard registers. We could do more register | |
5306 | pressure calculations at any given program point to avoid necessary | |
5307 | splitting even more but it is to expensive and the current approach | |
5308 | works well enough. */ | |
5309 | static bool | |
cfa434f6 | 5310 | inherit_in_ebb (rtx_insn *head, rtx_insn *tail) |
55a2c322 VM |
5311 | { |
5312 | int i, src_regno, dst_regno, nregs; | |
df2980be | 5313 | bool change_p, succ_p, update_reloads_num_p; |
cfa434f6 DM |
5314 | rtx_insn *prev_insn, *last_insn; |
5315 | rtx next_usage_insns, set; | |
55a2c322 VM |
5316 | enum reg_class cl; |
5317 | struct lra_insn_reg *reg; | |
5318 | basic_block last_processed_bb, curr_bb = NULL; | |
5319 | HARD_REG_SET potential_reload_hard_regs, live_hard_regs; | |
5320 | bitmap to_process; | |
5321 | unsigned int j; | |
5322 | bitmap_iterator bi; | |
5323 | bool head_p, after_p; | |
5324 | ||
5325 | change_p = false; | |
5326 | curr_usage_insns_check++; | |
5327 | reloads_num = calls_num = 0; | |
5328 | bitmap_clear (&check_only_regs); | |
5329 | last_processed_bb = NULL; | |
5330 | CLEAR_HARD_REG_SET (potential_reload_hard_regs); | |
8e9d68a9 VM |
5331 | COPY_HARD_REG_SET (live_hard_regs, eliminable_regset); |
5332 | IOR_HARD_REG_SET (live_hard_regs, lra_no_alloc_regs); | |
55a2c322 VM |
5333 | /* We don't process new insns generated in the loop. */ |
5334 | for (curr_insn = tail; curr_insn != PREV_INSN (head); curr_insn = prev_insn) | |
5335 | { | |
5336 | prev_insn = PREV_INSN (curr_insn); | |
5337 | if (BLOCK_FOR_INSN (curr_insn) != NULL) | |
5338 | curr_bb = BLOCK_FOR_INSN (curr_insn); | |
5339 | if (last_processed_bb != curr_bb) | |
5340 | { | |
5341 | /* We are at the end of BB. Add qualified living | |
5342 | pseudos for potential splitting. */ | |
5343 | to_process = df_get_live_out (curr_bb); | |
5344 | if (last_processed_bb != NULL) | |
f4eafc30 | 5345 | { |
55a2c322 VM |
5346 | /* We are somewhere in the middle of EBB. */ |
5347 | get_live_on_other_edges (curr_bb, last_processed_bb, | |
5348 | &temp_bitmap); | |
5349 | to_process = &temp_bitmap; | |
5350 | } | |
5351 | last_processed_bb = curr_bb; | |
5352 | last_insn = get_last_insertion_point (curr_bb); | |
5353 | after_p = (! JUMP_P (last_insn) | |
5354 | && (! CALL_P (last_insn) | |
5355 | || (find_reg_note (last_insn, | |
5356 | REG_NORETURN, NULL_RTX) == NULL_RTX | |
5357 | && ! SIBLING_CALL_P (last_insn)))); | |
55a2c322 VM |
5358 | CLEAR_HARD_REG_SET (potential_reload_hard_regs); |
5359 | EXECUTE_IF_SET_IN_BITMAP (to_process, 0, j, bi) | |
5360 | { | |
5361 | if ((int) j >= lra_constraint_new_regno_start) | |
5362 | break; | |
5363 | if (j < FIRST_PSEUDO_REGISTER || reg_renumber[j] >= 0) | |
5364 | { | |
5365 | if (j < FIRST_PSEUDO_REGISTER) | |
5366 | SET_HARD_REG_BIT (live_hard_regs, j); | |
5367 | else | |
5368 | add_to_hard_reg_set (&live_hard_regs, | |
5369 | PSEUDO_REGNO_MODE (j), | |
5370 | reg_renumber[j]); | |
5371 | setup_next_usage_insn (j, last_insn, reloads_num, after_p); | |
5372 | } | |
5373 | } | |
5374 | } | |
5375 | src_regno = dst_regno = -1; | |
5376 | if (NONDEBUG_INSN_P (curr_insn) | |
5377 | && (set = single_set (curr_insn)) != NULL_RTX | |
5378 | && REG_P (SET_DEST (set)) && REG_P (SET_SRC (set))) | |
5379 | { | |
5380 | src_regno = REGNO (SET_SRC (set)); | |
5381 | dst_regno = REGNO (SET_DEST (set)); | |
5382 | } | |
df2980be | 5383 | update_reloads_num_p = true; |
55a2c322 VM |
5384 | if (src_regno < lra_constraint_new_regno_start |
5385 | && src_regno >= FIRST_PSEUDO_REGISTER | |
5386 | && reg_renumber[src_regno] < 0 | |
5387 | && dst_regno >= lra_constraint_new_regno_start | |
5388 | && (cl = lra_get_allocno_class (dst_regno)) != NO_REGS) | |
5389 | { | |
5390 | /* 'reload_pseudo <- original_pseudo'. */ | |
8e9d68a9 VM |
5391 | if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num) |
5392 | reloads_num++; | |
df2980be | 5393 | update_reloads_num_p = false; |
55a2c322 VM |
5394 | succ_p = false; |
5395 | if (usage_insns[src_regno].check == curr_usage_insns_check | |
5396 | && (next_usage_insns = usage_insns[src_regno].insns) != NULL_RTX) | |
5397 | succ_p = inherit_reload_reg (false, src_regno, cl, | |
5398 | curr_insn, next_usage_insns); | |
5399 | if (succ_p) | |
5400 | change_p = true; | |
5401 | else | |
5402 | setup_next_usage_insn (src_regno, curr_insn, reloads_num, false); | |
5403 | if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs)) | |
5404 | IOR_HARD_REG_SET (potential_reload_hard_regs, | |
5405 | reg_class_contents[cl]); | |
5406 | } | |
5407 | else if (src_regno >= lra_constraint_new_regno_start | |
5408 | && dst_regno < lra_constraint_new_regno_start | |
5409 | && dst_regno >= FIRST_PSEUDO_REGISTER | |
5410 | && reg_renumber[dst_regno] < 0 | |
5411 | && (cl = lra_get_allocno_class (src_regno)) != NO_REGS | |
5412 | && usage_insns[dst_regno].check == curr_usage_insns_check | |
5413 | && (next_usage_insns | |
5414 | = usage_insns[dst_regno].insns) != NULL_RTX) | |
5415 | { | |
8e9d68a9 VM |
5416 | if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num) |
5417 | reloads_num++; | |
df2980be | 5418 | update_reloads_num_p = false; |
55a2c322 VM |
5419 | /* 'original_pseudo <- reload_pseudo'. */ |
5420 | if (! JUMP_P (curr_insn) | |
5421 | && inherit_reload_reg (true, dst_regno, cl, | |
5422 | curr_insn, next_usage_insns)) | |
5423 | change_p = true; | |
5424 | /* Invalidate. */ | |
5425 | usage_insns[dst_regno].check = 0; | |
5426 | if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs)) | |
5427 | IOR_HARD_REG_SET (potential_reload_hard_regs, | |
5428 | reg_class_contents[cl]); | |
5429 | } | |
5430 | else if (INSN_P (curr_insn)) | |
5431 | { | |
2f259720 | 5432 | int iter; |
55a2c322 VM |
5433 | int max_uid = get_max_uid (); |
5434 | ||
5435 | curr_id = lra_get_insn_recog_data (curr_insn); | |
2f259720 | 5436 | curr_static_id = curr_id->insn_static_data; |
55a2c322 VM |
5437 | to_inherit_num = 0; |
5438 | /* Process insn definitions. */ | |
2f259720 VM |
5439 | for (iter = 0; iter < 2; iter++) |
5440 | for (reg = iter == 0 ? curr_id->regs : curr_static_id->hard_regs; | |
5441 | reg != NULL; | |
5442 | reg = reg->next) | |
5443 | if (reg->type != OP_IN | |
5444 | && (dst_regno = reg->regno) < lra_constraint_new_regno_start) | |
5445 | { | |
5446 | if (dst_regno >= FIRST_PSEUDO_REGISTER && reg->type == OP_OUT | |
5447 | && reg_renumber[dst_regno] < 0 && ! reg->subreg_p | |
5448 | && usage_insns[dst_regno].check == curr_usage_insns_check | |
5449 | && (next_usage_insns | |
5450 | = usage_insns[dst_regno].insns) != NULL_RTX) | |
5451 | { | |
5452 | struct lra_insn_reg *r; | |
5453 | ||
5454 | for (r = curr_id->regs; r != NULL; r = r->next) | |
5455 | if (r->type != OP_OUT && r->regno == dst_regno) | |
5456 | break; | |
5457 | /* Don't do inheritance if the pseudo is also | |
5458 | used in the insn. */ | |
5459 | if (r == NULL) | |
5460 | /* We can not do inheritance right now | |
5461 | because the current insn reg info (chain | |
5462 | regs) can change after that. */ | |
5463 | add_to_inherit (dst_regno, next_usage_insns); | |
5464 | } | |
5465 | /* We can not process one reg twice here because of | |
5466 | usage_insns invalidation. */ | |
5467 | if ((dst_regno < FIRST_PSEUDO_REGISTER | |
5468 | || reg_renumber[dst_regno] >= 0) | |
e32e4c4a | 5469 | && ! reg->subreg_p && reg->type != OP_IN) |
2f259720 VM |
5470 | { |
5471 | HARD_REG_SET s; | |
5472 | ||
5473 | if (split_if_necessary (dst_regno, reg->biggest_mode, | |
5474 | potential_reload_hard_regs, | |
5475 | false, curr_insn, max_uid)) | |
5476 | change_p = true; | |
5477 | CLEAR_HARD_REG_SET (s); | |
5478 | if (dst_regno < FIRST_PSEUDO_REGISTER) | |
5479 | add_to_hard_reg_set (&s, reg->biggest_mode, dst_regno); | |
5480 | else | |
5481 | add_to_hard_reg_set (&s, PSEUDO_REGNO_MODE (dst_regno), | |
5482 | reg_renumber[dst_regno]); | |
5483 | AND_COMPL_HARD_REG_SET (live_hard_regs, s); | |
5484 | } | |
5485 | /* We should invalidate potential inheritance or | |
5486 | splitting for the current insn usages to the next | |
5487 | usage insns (see code below) as the output pseudo | |
5488 | prevents this. */ | |
5489 | if ((dst_regno >= FIRST_PSEUDO_REGISTER | |
5490 | && reg_renumber[dst_regno] < 0) | |
5491 | || (reg->type == OP_OUT && ! reg->subreg_p | |
5492 | && (dst_regno < FIRST_PSEUDO_REGISTER | |
5493 | || reg_renumber[dst_regno] >= 0))) | |
5494 | { | |
5495 | /* Invalidate and mark definitions. */ | |
5496 | if (dst_regno >= FIRST_PSEUDO_REGISTER) | |
5497 | usage_insns[dst_regno].check = -(int) INSN_UID (curr_insn); | |
5498 | else | |
5499 | { | |
5500 | nregs = hard_regno_nregs[dst_regno][reg->biggest_mode]; | |
5501 | for (i = 0; i < nregs; i++) | |
5502 | usage_insns[dst_regno + i].check | |
5503 | = -(int) INSN_UID (curr_insn); | |
5504 | } | |
5505 | } | |
5506 | } | |
9d86e84e VM |
5507 | /* Process clobbered call regs. */ |
5508 | if (curr_id->arg_hard_regs != NULL) | |
5509 | for (i = 0; (dst_regno = curr_id->arg_hard_regs[i]) >= 0; i++) | |
5510 | if (dst_regno >= FIRST_PSEUDO_REGISTER) | |
5511 | usage_insns[dst_regno - FIRST_PSEUDO_REGISTER].check | |
5512 | = -(int) INSN_UID (curr_insn); | |
55a2c322 VM |
5513 | if (! JUMP_P (curr_insn)) |
5514 | for (i = 0; i < to_inherit_num; i++) | |
5515 | if (inherit_reload_reg (true, to_inherit[i].regno, | |
5516 | ALL_REGS, curr_insn, | |
5517 | to_inherit[i].insns)) | |
5518 | change_p = true; | |
5519 | if (CALL_P (curr_insn)) | |
5520 | { | |
cfa434f6 DM |
5521 | rtx cheap, pat, dest; |
5522 | rtx_insn *restore; | |
55a2c322 VM |
5523 | int regno, hard_regno; |
5524 | ||
5525 | calls_num++; | |
5526 | if ((cheap = find_reg_note (curr_insn, | |
5527 | REG_RETURNED, NULL_RTX)) != NULL_RTX | |
5528 | && ((cheap = XEXP (cheap, 0)), true) | |
5529 | && (regno = REGNO (cheap)) >= FIRST_PSEUDO_REGISTER | |
5530 | && (hard_regno = reg_renumber[regno]) >= 0 | |
5531 | /* If there are pending saves/restores, the | |
5532 | optimization is not worth. */ | |
5533 | && usage_insns[regno].calls_num == calls_num - 1 | |
5534 | && TEST_HARD_REG_BIT (call_used_reg_set, hard_regno)) | |
5535 | { | |
5536 | /* Restore the pseudo from the call result as | |
5537 | REG_RETURNED note says that the pseudo value is | |
5538 | in the call result and the pseudo is an argument | |
5539 | of the call. */ | |
5540 | pat = PATTERN (curr_insn); | |
5541 | if (GET_CODE (pat) == PARALLEL) | |
5542 | pat = XVECEXP (pat, 0, 0); | |
5543 | dest = SET_DEST (pat); | |
54bddf1d IE |
5544 | /* For multiple return values dest is PARALLEL. |
5545 | Currently we handle only single return value case. */ | |
5546 | if (REG_P (dest)) | |
5547 | { | |
5548 | start_sequence (); | |
5549 | emit_move_insn (cheap, copy_rtx (dest)); | |
5550 | restore = get_insns (); | |
5551 | end_sequence (); | |
5552 | lra_process_new_insns (curr_insn, NULL, restore, | |
5553 | "Inserting call parameter restore"); | |
5554 | /* We don't need to save/restore of the pseudo from | |
5555 | this call. */ | |
5556 | usage_insns[regno].calls_num = calls_num; | |
5557 | bitmap_set_bit (&check_only_regs, regno); | |
5558 | } | |
55a2c322 VM |
5559 | } |
5560 | } | |
5561 | to_inherit_num = 0; | |
5562 | /* Process insn usages. */ | |
2f259720 VM |
5563 | for (iter = 0; iter < 2; iter++) |
5564 | for (reg = iter == 0 ? curr_id->regs : curr_static_id->hard_regs; | |
5565 | reg != NULL; | |
5566 | reg = reg->next) | |
5567 | if ((reg->type != OP_OUT | |
5568 | || (reg->type == OP_OUT && reg->subreg_p)) | |
5569 | && (src_regno = reg->regno) < lra_constraint_new_regno_start) | |
5570 | { | |
5571 | if (src_regno >= FIRST_PSEUDO_REGISTER | |
5572 | && reg_renumber[src_regno] < 0 && reg->type == OP_IN) | |
5573 | { | |
5574 | if (usage_insns[src_regno].check == curr_usage_insns_check | |
5575 | && (next_usage_insns | |
5576 | = usage_insns[src_regno].insns) != NULL_RTX | |
5577 | && NONDEBUG_INSN_P (curr_insn)) | |
5578 | add_to_inherit (src_regno, next_usage_insns); | |
5579 | else if (usage_insns[src_regno].check | |
5580 | != -(int) INSN_UID (curr_insn)) | |
5581 | /* Add usages but only if the reg is not set up | |
5582 | in the same insn. */ | |
5583 | add_next_usage_insn (src_regno, curr_insn, reloads_num); | |
5584 | } | |
5585 | else if (src_regno < FIRST_PSEUDO_REGISTER | |
5586 | || reg_renumber[src_regno] >= 0) | |
5587 | { | |
5588 | bool before_p; | |
e67d1102 | 5589 | rtx_insn *use_insn = curr_insn; |
2f259720 VM |
5590 | |
5591 | before_p = (JUMP_P (curr_insn) | |
5592 | || (CALL_P (curr_insn) && reg->type == OP_IN)); | |
5593 | if (NONDEBUG_INSN_P (curr_insn) | |
8e9d68a9 | 5594 | && (! JUMP_P (curr_insn) || reg->type == OP_IN) |
2f259720 VM |
5595 | && split_if_necessary (src_regno, reg->biggest_mode, |
5596 | potential_reload_hard_regs, | |
5597 | before_p, curr_insn, max_uid)) | |
5598 | { | |
5599 | if (reg->subreg_p) | |
5600 | lra_risky_transformations_p = true; | |
5601 | change_p = true; | |
8e9d68a9 | 5602 | /* Invalidate. */ |
2f259720 VM |
5603 | usage_insns[src_regno].check = 0; |
5604 | if (before_p) | |
5605 | use_insn = PREV_INSN (curr_insn); | |
5606 | } | |
5607 | if (NONDEBUG_INSN_P (curr_insn)) | |
5608 | { | |
5609 | if (src_regno < FIRST_PSEUDO_REGISTER) | |
5610 | add_to_hard_reg_set (&live_hard_regs, | |
5611 | reg->biggest_mode, src_regno); | |
5612 | else | |
5613 | add_to_hard_reg_set (&live_hard_regs, | |
5614 | PSEUDO_REGNO_MODE (src_regno), | |
5615 | reg_renumber[src_regno]); | |
5616 | } | |
5617 | add_next_usage_insn (src_regno, use_insn, reloads_num); | |
5618 | } | |
5619 | } | |
9d86e84e | 5620 | /* Process used call regs. */ |
df2980be VM |
5621 | if (curr_id->arg_hard_regs != NULL) |
5622 | for (i = 0; (src_regno = curr_id->arg_hard_regs[i]) >= 0; i++) | |
5623 | if (src_regno < FIRST_PSEUDO_REGISTER) | |
5624 | { | |
5625 | SET_HARD_REG_BIT (live_hard_regs, src_regno); | |
5626 | add_next_usage_insn (src_regno, curr_insn, reloads_num); | |
5627 | } | |
55a2c322 VM |
5628 | for (i = 0; i < to_inherit_num; i++) |
5629 | { | |
5630 | src_regno = to_inherit[i].regno; | |
5631 | if (inherit_reload_reg (false, src_regno, ALL_REGS, | |
5632 | curr_insn, to_inherit[i].insns)) | |
5633 | change_p = true; | |
5634 | else | |
5635 | setup_next_usage_insn (src_regno, curr_insn, reloads_num, false); | |
5636 | } | |
5637 | } | |
df2980be VM |
5638 | if (update_reloads_num_p |
5639 | && NONDEBUG_INSN_P (curr_insn) | |
5640 | && (set = single_set (curr_insn)) != NULL_RTX) | |
5641 | { | |
5642 | int regno = -1; | |
5643 | if ((REG_P (SET_DEST (set)) | |
5644 | && (regno = REGNO (SET_DEST (set))) >= lra_constraint_new_regno_start | |
5645 | && reg_renumber[regno] < 0 | |
5646 | && (cl = lra_get_allocno_class (regno)) != NO_REGS) | |
5647 | || (REG_P (SET_SRC (set)) | |
5648 | && (regno = REGNO (SET_SRC (set))) >= lra_constraint_new_regno_start | |
5649 | && reg_renumber[regno] < 0 | |
5650 | && (cl = lra_get_allocno_class (regno)) != NO_REGS)) | |
5651 | { | |
8e9d68a9 VM |
5652 | if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num) |
5653 | reloads_num++; | |
df2980be VM |
5654 | if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs)) |
5655 | IOR_HARD_REG_SET (potential_reload_hard_regs, | |
5656 | reg_class_contents[cl]); | |
5657 | } | |
5658 | } | |
55a2c322 VM |
5659 | /* We reached the start of the current basic block. */ |
5660 | if (prev_insn == NULL_RTX || prev_insn == PREV_INSN (head) | |
5661 | || BLOCK_FOR_INSN (prev_insn) != curr_bb) | |
5662 | { | |
5663 | /* We reached the beginning of the current block -- do | |
5664 | rest of spliting in the current BB. */ | |
5665 | to_process = df_get_live_in (curr_bb); | |
5666 | if (BLOCK_FOR_INSN (head) != curr_bb) | |
f4eafc30 | 5667 | { |
55a2c322 VM |
5668 | /* We are somewhere in the middle of EBB. */ |
5669 | get_live_on_other_edges (EDGE_PRED (curr_bb, 0)->src, | |
5670 | curr_bb, &temp_bitmap); | |
5671 | to_process = &temp_bitmap; | |
5672 | } | |
5673 | head_p = true; | |
5674 | EXECUTE_IF_SET_IN_BITMAP (to_process, 0, j, bi) | |
5675 | { | |
5676 | if ((int) j >= lra_constraint_new_regno_start) | |
5677 | break; | |
5678 | if (((int) j < FIRST_PSEUDO_REGISTER || reg_renumber[j] >= 0) | |
5679 | && usage_insns[j].check == curr_usage_insns_check | |
5680 | && (next_usage_insns = usage_insns[j].insns) != NULL_RTX) | |
5681 | { | |
5682 | if (need_for_split_p (potential_reload_hard_regs, j)) | |
5683 | { | |
5684 | if (lra_dump_file != NULL && head_p) | |
5685 | { | |
5686 | fprintf (lra_dump_file, | |
5687 | " ----------------------------------\n"); | |
5688 | head_p = false; | |
5689 | } | |
5690 | if (split_reg (false, j, bb_note (curr_bb), | |
5691 | next_usage_insns)) | |
5692 | change_p = true; | |
5693 | } | |
5694 | usage_insns[j].check = 0; | |
5695 | } | |
5696 | } | |
5697 | } | |
5698 | } | |
5699 | return change_p; | |
5700 | } | |
5701 | ||
5702 | /* This value affects EBB forming. If probability of edge from EBB to | |
5703 | a BB is not greater than the following value, we don't add the BB | |
f4eafc30 | 5704 | to EBB. */ |
fb8a0e40 VM |
5705 | #define EBB_PROBABILITY_CUTOFF \ |
5706 | ((REG_BR_PROB_BASE * LRA_INHERITANCE_EBB_PROBABILITY_CUTOFF) / 100) | |
55a2c322 VM |
5707 | |
5708 | /* Current number of inheritance/split iteration. */ | |
5709 | int lra_inheritance_iter; | |
5710 | ||
5711 | /* Entry function for inheritance/split pass. */ | |
5712 | void | |
5713 | lra_inheritance (void) | |
5714 | { | |
5715 | int i; | |
5716 | basic_block bb, start_bb; | |
5717 | edge e; | |
5718 | ||
55a2c322 | 5719 | lra_inheritance_iter++; |
8e3a4869 | 5720 | if (lra_inheritance_iter > LRA_MAX_INHERITANCE_PASSES) |
e731262b VM |
5721 | return; |
5722 | timevar_push (TV_LRA_INHERITANCE); | |
55a2c322 VM |
5723 | if (lra_dump_file != NULL) |
5724 | fprintf (lra_dump_file, "\n********** Inheritance #%d: **********\n\n", | |
5725 | lra_inheritance_iter); | |
5726 | curr_usage_insns_check = 0; | |
5727 | usage_insns = XNEWVEC (struct usage_insns, lra_constraint_new_regno_start); | |
5728 | for (i = 0; i < lra_constraint_new_regno_start; i++) | |
5729 | usage_insns[i].check = 0; | |
5730 | bitmap_initialize (&check_only_regs, ®_obstack); | |
5731 | bitmap_initialize (&live_regs, ®_obstack); | |
5732 | bitmap_initialize (&temp_bitmap, ®_obstack); | |
5733 | bitmap_initialize (&ebb_global_regs, ®_obstack); | |
11cd3bed | 5734 | FOR_EACH_BB_FN (bb, cfun) |
55a2c322 VM |
5735 | { |
5736 | start_bb = bb; | |
5737 | if (lra_dump_file != NULL) | |
5738 | fprintf (lra_dump_file, "EBB"); | |
5739 | /* Form a EBB starting with BB. */ | |
5740 | bitmap_clear (&ebb_global_regs); | |
5741 | bitmap_ior_into (&ebb_global_regs, df_get_live_in (bb)); | |
5742 | for (;;) | |
5743 | { | |
5744 | if (lra_dump_file != NULL) | |
5745 | fprintf (lra_dump_file, " %d", bb->index); | |
fefa31b5 DM |
5746 | if (bb->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun) |
5747 | || LABEL_P (BB_HEAD (bb->next_bb))) | |
55a2c322 VM |
5748 | break; |
5749 | e = find_fallthru_edge (bb->succs); | |
5750 | if (! e) | |
5751 | break; | |
fb8a0e40 | 5752 | if (e->probability < EBB_PROBABILITY_CUTOFF) |
55a2c322 VM |
5753 | break; |
5754 | bb = bb->next_bb; | |
5755 | } | |
5756 | bitmap_ior_into (&ebb_global_regs, df_get_live_out (bb)); | |
5757 | if (lra_dump_file != NULL) | |
5758 | fprintf (lra_dump_file, "\n"); | |
5759 | if (inherit_in_ebb (BB_HEAD (start_bb), BB_END (bb))) | |
5760 | /* Remember that the EBB head and tail can change in | |
5761 | inherit_in_ebb. */ | |
5762 | update_ebb_live_info (BB_HEAD (start_bb), BB_END (bb)); | |
5763 | } | |
5764 | bitmap_clear (&ebb_global_regs); | |
5765 | bitmap_clear (&temp_bitmap); | |
5766 | bitmap_clear (&live_regs); | |
5767 | bitmap_clear (&check_only_regs); | |
5768 | free (usage_insns); | |
5769 | ||
5770 | timevar_pop (TV_LRA_INHERITANCE); | |
5771 | } | |
5772 | ||
5773 | \f | |
5774 | ||
5775 | /* This page contains code to undo failed inheritance/split | |
5776 | transformations. */ | |
5777 | ||
5778 | /* Current number of iteration undoing inheritance/split. */ | |
5779 | int lra_undo_inheritance_iter; | |
5780 | ||
5781 | /* Fix BB live info LIVE after removing pseudos created on pass doing | |
5782 | inheritance/split which are REMOVED_PSEUDOS. */ | |
5783 | static void | |
5784 | fix_bb_live_info (bitmap live, bitmap removed_pseudos) | |
5785 | { | |
5786 | unsigned int regno; | |
5787 | bitmap_iterator bi; | |
5788 | ||
5789 | EXECUTE_IF_SET_IN_BITMAP (removed_pseudos, 0, regno, bi) | |
5790 | if (bitmap_clear_bit (live, regno)) | |
5791 | bitmap_set_bit (live, lra_reg_info[regno].restore_regno); | |
5792 | } | |
5793 | ||
5794 | /* Return regno of the (subreg of) REG. Otherwise, return a negative | |
5795 | number. */ | |
5796 | static int | |
5797 | get_regno (rtx reg) | |
5798 | { | |
5799 | if (GET_CODE (reg) == SUBREG) | |
5800 | reg = SUBREG_REG (reg); | |
5801 | if (REG_P (reg)) | |
5802 | return REGNO (reg); | |
5803 | return -1; | |
5804 | } | |
5805 | ||
5806 | /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and | |
5807 | return true if we did any change. The undo transformations for | |
5808 | inheritance looks like | |
5809 | i <- i2 | |
5810 | p <- i => p <- i2 | |
5811 | or removing | |
5812 | p <- i, i <- p, and i <- i3 | |
5813 | where p is original pseudo from which inheritance pseudo i was | |
5814 | created, i and i3 are removed inheritance pseudos, i2 is another | |
5815 | not removed inheritance pseudo. All split pseudos or other | |
5816 | occurrences of removed inheritance pseudos are changed on the | |
5817 | corresponding original pseudos. | |
5818 | ||
5819 | The function also schedules insns changed and created during | |
5820 | inheritance/split pass for processing by the subsequent constraint | |
5821 | pass. */ | |
5822 | static bool | |
5823 | remove_inheritance_pseudos (bitmap remove_pseudos) | |
5824 | { | |
5825 | basic_block bb; | |
5826 | int regno, sregno, prev_sregno, dregno, restore_regno; | |
cfa434f6 DM |
5827 | rtx set, prev_set; |
5828 | rtx_insn *prev_insn; | |
55a2c322 VM |
5829 | bool change_p, done_p; |
5830 | ||
5831 | change_p = ! bitmap_empty_p (remove_pseudos); | |
5832 | /* We can not finish the function right away if CHANGE_P is true | |
5833 | because we need to marks insns affected by previous | |
5834 | inheritance/split pass for processing by the subsequent | |
5835 | constraint pass. */ | |
11cd3bed | 5836 | FOR_EACH_BB_FN (bb, cfun) |
55a2c322 VM |
5837 | { |
5838 | fix_bb_live_info (df_get_live_in (bb), remove_pseudos); | |
5839 | fix_bb_live_info (df_get_live_out (bb), remove_pseudos); | |
5840 | FOR_BB_INSNS_REVERSE (bb, curr_insn) | |
5841 | { | |
5842 | if (! INSN_P (curr_insn)) | |
5843 | continue; | |
5844 | done_p = false; | |
5845 | sregno = dregno = -1; | |
5846 | if (change_p && NONDEBUG_INSN_P (curr_insn) | |
5847 | && (set = single_set (curr_insn)) != NULL_RTX) | |
5848 | { | |
5849 | dregno = get_regno (SET_DEST (set)); | |
5850 | sregno = get_regno (SET_SRC (set)); | |
5851 | } | |
f4eafc30 | 5852 | |
55a2c322 VM |
5853 | if (sregno >= 0 && dregno >= 0) |
5854 | { | |
5855 | if ((bitmap_bit_p (remove_pseudos, sregno) | |
5856 | && (lra_reg_info[sregno].restore_regno == dregno | |
5857 | || (bitmap_bit_p (remove_pseudos, dregno) | |
5858 | && (lra_reg_info[sregno].restore_regno | |
5859 | == lra_reg_info[dregno].restore_regno)))) | |
5860 | || (bitmap_bit_p (remove_pseudos, dregno) | |
5861 | && lra_reg_info[dregno].restore_regno == sregno)) | |
5862 | /* One of the following cases: | |
5863 | original <- removed inheritance pseudo | |
5864 | removed inherit pseudo <- another removed inherit pseudo | |
5865 | removed inherit pseudo <- original pseudo | |
5866 | Or | |
5867 | removed_split_pseudo <- original_reg | |
5868 | original_reg <- removed_split_pseudo */ | |
5869 | { | |
5870 | if (lra_dump_file != NULL) | |
5871 | { | |
5872 | fprintf (lra_dump_file, " Removing %s:\n", | |
5873 | bitmap_bit_p (&lra_split_regs, sregno) | |
5874 | || bitmap_bit_p (&lra_split_regs, dregno) | |
5875 | ? "split" : "inheritance"); | |
cfbeaedf | 5876 | dump_insn_slim (lra_dump_file, curr_insn); |
55a2c322 VM |
5877 | } |
5878 | lra_set_insn_deleted (curr_insn); | |
5879 | done_p = true; | |
5880 | } | |
5881 | else if (bitmap_bit_p (remove_pseudos, sregno) | |
5882 | && bitmap_bit_p (&lra_inheritance_pseudos, sregno)) | |
5883 | { | |
5884 | /* Search the following pattern: | |
5885 | inherit_or_split_pseudo1 <- inherit_or_split_pseudo2 | |
5886 | original_pseudo <- inherit_or_split_pseudo1 | |
5887 | where the 2nd insn is the current insn and | |
5888 | inherit_or_split_pseudo2 is not removed. If it is found, | |
5889 | change the current insn onto: | |
5890 | original_pseudo <- inherit_or_split_pseudo2. */ | |
5891 | for (prev_insn = PREV_INSN (curr_insn); | |
5892 | prev_insn != NULL_RTX && ! NONDEBUG_INSN_P (prev_insn); | |
5893 | prev_insn = PREV_INSN (prev_insn)) | |
5894 | ; | |
5895 | if (prev_insn != NULL_RTX && BLOCK_FOR_INSN (prev_insn) == bb | |
5896 | && (prev_set = single_set (prev_insn)) != NULL_RTX | |
5897 | /* There should be no subregs in insn we are | |
5898 | searching because only the original reg might | |
5899 | be in subreg when we changed the mode of | |
5900 | load/store for splitting. */ | |
5901 | && REG_P (SET_DEST (prev_set)) | |
5902 | && REG_P (SET_SRC (prev_set)) | |
5903 | && (int) REGNO (SET_DEST (prev_set)) == sregno | |
5904 | && ((prev_sregno = REGNO (SET_SRC (prev_set))) | |
5905 | >= FIRST_PSEUDO_REGISTER) | |
5906 | /* As we consider chain of inheritance or | |
5907 | splitting described in above comment we should | |
5908 | check that sregno and prev_sregno were | |
5909 | inheritance/split pseudos created from the | |
5910 | same original regno. */ | |
5911 | && (lra_reg_info[sregno].restore_regno | |
5912 | == lra_reg_info[prev_sregno].restore_regno) | |
5913 | && ! bitmap_bit_p (remove_pseudos, prev_sregno)) | |
5914 | { | |
5915 | lra_assert (GET_MODE (SET_SRC (prev_set)) | |
5916 | == GET_MODE (regno_reg_rtx[sregno])); | |
5917 | if (GET_CODE (SET_SRC (set)) == SUBREG) | |
5918 | SUBREG_REG (SET_SRC (set)) = SET_SRC (prev_set); | |
5919 | else | |
5920 | SET_SRC (set) = SET_SRC (prev_set); | |
12b308fa VM |
5921 | /* As we are finishing with processing the insn |
5922 | here, check the destination too as it might | |
5923 | inheritance pseudo for another pseudo. */ | |
5924 | if (bitmap_bit_p (remove_pseudos, dregno) | |
5925 | && bitmap_bit_p (&lra_inheritance_pseudos, dregno) | |
5926 | && (restore_regno | |
5927 | = lra_reg_info[dregno].restore_regno) >= 0) | |
5928 | { | |
5929 | if (GET_CODE (SET_DEST (set)) == SUBREG) | |
5930 | SUBREG_REG (SET_DEST (set)) | |
5931 | = regno_reg_rtx[restore_regno]; | |
5932 | else | |
5933 | SET_DEST (set) = regno_reg_rtx[restore_regno]; | |
5934 | } | |
55a2c322 VM |
5935 | lra_push_insn_and_update_insn_regno_info (curr_insn); |
5936 | lra_set_used_insn_alternative_by_uid | |
5937 | (INSN_UID (curr_insn), -1); | |
5938 | done_p = true; | |
5939 | if (lra_dump_file != NULL) | |
5940 | { | |
5941 | fprintf (lra_dump_file, " Change reload insn:\n"); | |
cfbeaedf | 5942 | dump_insn_slim (lra_dump_file, curr_insn); |
55a2c322 VM |
5943 | } |
5944 | } | |
5945 | } | |
5946 | } | |
5947 | if (! done_p) | |
5948 | { | |
5949 | struct lra_insn_reg *reg; | |
5950 | bool restored_regs_p = false; | |
5951 | bool kept_regs_p = false; | |
5952 | ||
5953 | curr_id = lra_get_insn_recog_data (curr_insn); | |
5954 | for (reg = curr_id->regs; reg != NULL; reg = reg->next) | |
5955 | { | |
5956 | regno = reg->regno; | |
5957 | restore_regno = lra_reg_info[regno].restore_regno; | |
5958 | if (restore_regno >= 0) | |
5959 | { | |
5960 | if (change_p && bitmap_bit_p (remove_pseudos, regno)) | |
5961 | { | |
ef87312e VM |
5962 | lra_substitute_pseudo_within_insn |
5963 | (curr_insn, regno, regno_reg_rtx[restore_regno], | |
5964 | false); | |
55a2c322 VM |
5965 | restored_regs_p = true; |
5966 | } | |
5967 | else | |
5968 | kept_regs_p = true; | |
5969 | } | |
5970 | } | |
5971 | if (NONDEBUG_INSN_P (curr_insn) && kept_regs_p) | |
5972 | { | |
5973 | /* The instruction has changed since the previous | |
5974 | constraints pass. */ | |
5975 | lra_push_insn_and_update_insn_regno_info (curr_insn); | |
5976 | lra_set_used_insn_alternative_by_uid | |
5977 | (INSN_UID (curr_insn), -1); | |
5978 | } | |
5979 | else if (restored_regs_p) | |
5980 | /* The instruction has been restored to the form that | |
5981 | it had during the previous constraints pass. */ | |
5982 | lra_update_insn_regno_info (curr_insn); | |
5983 | if (restored_regs_p && lra_dump_file != NULL) | |
5984 | { | |
5985 | fprintf (lra_dump_file, " Insn after restoring regs:\n"); | |
cfbeaedf | 5986 | dump_insn_slim (lra_dump_file, curr_insn); |
55a2c322 VM |
5987 | } |
5988 | } | |
5989 | } | |
5990 | } | |
5991 | return change_p; | |
5992 | } | |
5993 | ||
2b778c9d VM |
5994 | /* If optional reload pseudos failed to get a hard register or was not |
5995 | inherited, it is better to remove optional reloads. We do this | |
5996 | transformation after undoing inheritance to figure out necessity to | |
5997 | remove optional reloads easier. Return true if we do any | |
5998 | change. */ | |
5999 | static bool | |
6000 | undo_optional_reloads (void) | |
6001 | { | |
b0681c9e | 6002 | bool change_p, keep_p; |
2b778c9d VM |
6003 | unsigned int regno, uid; |
6004 | bitmap_iterator bi, bi2; | |
cfa434f6 DM |
6005 | rtx_insn *insn; |
6006 | rtx set, src, dest; | |
2b778c9d VM |
6007 | bitmap_head removed_optional_reload_pseudos, insn_bitmap; |
6008 | ||
6009 | bitmap_initialize (&removed_optional_reload_pseudos, ®_obstack); | |
6010 | bitmap_copy (&removed_optional_reload_pseudos, &lra_optional_reload_pseudos); | |
6011 | EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos, 0, regno, bi) | |
aa940f7c VM |
6012 | { |
6013 | keep_p = false; | |
080cbf9e VM |
6014 | /* Keep optional reloads from previous subpasses. */ |
6015 | if (lra_reg_info[regno].restore_regno < 0 | |
6016 | /* If the original pseudo changed its allocation, just | |
6017 | removing the optional pseudo is dangerous as the original | |
6018 | pseudo will have longer live range. */ | |
6019 | || reg_renumber[lra_reg_info[regno].restore_regno] >= 0) | |
aa940f7c VM |
6020 | keep_p = true; |
6021 | else if (reg_renumber[regno] >= 0) | |
6022 | EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi2) | |
b0681c9e | 6023 | { |
aa940f7c VM |
6024 | insn = lra_insn_recog_data[uid]->insn; |
6025 | if ((set = single_set (insn)) == NULL_RTX) | |
6026 | continue; | |
6027 | src = SET_SRC (set); | |
6028 | dest = SET_DEST (set); | |
6029 | if (! REG_P (src) || ! REG_P (dest)) | |
6030 | continue; | |
6031 | if (REGNO (dest) == regno | |
6032 | /* Ignore insn for optional reloads itself. */ | |
6033 | && lra_reg_info[regno].restore_regno != (int) REGNO (src) | |
6034 | /* Check only inheritance on last inheritance pass. */ | |
6035 | && (int) REGNO (src) >= new_regno_start | |
6036 | /* Check that the optional reload was inherited. */ | |
6037 | && bitmap_bit_p (&lra_inheritance_pseudos, REGNO (src))) | |
6038 | { | |
6039 | keep_p = true; | |
6040 | break; | |
6041 | } | |
b0681c9e | 6042 | } |
aa940f7c VM |
6043 | if (keep_p) |
6044 | { | |
6045 | bitmap_clear_bit (&removed_optional_reload_pseudos, regno); | |
6046 | if (lra_dump_file != NULL) | |
6047 | fprintf (lra_dump_file, "Keep optional reload reg %d\n", regno); | |
6048 | } | |
6049 | } | |
2b778c9d VM |
6050 | change_p = ! bitmap_empty_p (&removed_optional_reload_pseudos); |
6051 | bitmap_initialize (&insn_bitmap, ®_obstack); | |
6052 | EXECUTE_IF_SET_IN_BITMAP (&removed_optional_reload_pseudos, 0, regno, bi) | |
6053 | { | |
6054 | if (lra_dump_file != NULL) | |
6055 | fprintf (lra_dump_file, "Remove optional reload reg %d\n", regno); | |
6056 | bitmap_copy (&insn_bitmap, &lra_reg_info[regno].insn_bitmap); | |
6057 | EXECUTE_IF_SET_IN_BITMAP (&insn_bitmap, 0, uid, bi2) | |
6058 | { | |
6059 | insn = lra_insn_recog_data[uid]->insn; | |
6060 | if ((set = single_set (insn)) != NULL_RTX) | |
6061 | { | |
6062 | src = SET_SRC (set); | |
6063 | dest = SET_DEST (set); | |
6064 | if (REG_P (src) && REG_P (dest) | |
6065 | && ((REGNO (src) == regno | |
6066 | && (lra_reg_info[regno].restore_regno | |
6067 | == (int) REGNO (dest))) | |
6068 | || (REGNO (dest) == regno | |
6069 | && (lra_reg_info[regno].restore_regno | |
6070 | == (int) REGNO (src))))) | |
6071 | { | |
6072 | if (lra_dump_file != NULL) | |
6073 | { | |
6074 | fprintf (lra_dump_file, " Deleting move %u\n", | |
6075 | INSN_UID (insn)); | |
6076 | dump_insn_slim (lra_dump_file, insn); | |
6077 | } | |
6078 | lra_set_insn_deleted (insn); | |
6079 | continue; | |
6080 | } | |
6081 | /* We should not worry about generation memory-memory | |
6082 | moves here as if the corresponding inheritance did | |
6083 | not work (inheritance pseudo did not get a hard reg), | |
6084 | we remove the inheritance pseudo and the optional | |
6085 | reload. */ | |
6086 | } | |
ef87312e VM |
6087 | lra_substitute_pseudo_within_insn |
6088 | (insn, regno, regno_reg_rtx[lra_reg_info[regno].restore_regno], | |
6089 | false); | |
2b778c9d VM |
6090 | lra_update_insn_regno_info (insn); |
6091 | if (lra_dump_file != NULL) | |
6092 | { | |
6093 | fprintf (lra_dump_file, | |
6094 | " Restoring original insn:\n"); | |
6095 | dump_insn_slim (lra_dump_file, insn); | |
6096 | } | |
6097 | } | |
6098 | } | |
6099 | /* Clear restore_regnos. */ | |
6100 | EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos, 0, regno, bi) | |
6101 | lra_reg_info[regno].restore_regno = -1; | |
6102 | bitmap_clear (&insn_bitmap); | |
6103 | bitmap_clear (&removed_optional_reload_pseudos); | |
6104 | return change_p; | |
6105 | } | |
6106 | ||
55a2c322 VM |
6107 | /* Entry function for undoing inheritance/split transformation. Return true |
6108 | if we did any RTL change in this pass. */ | |
6109 | bool | |
6110 | lra_undo_inheritance (void) | |
6111 | { | |
6112 | unsigned int regno; | |
6113 | int restore_regno, hard_regno; | |
6114 | int n_all_inherit, n_inherit, n_all_split, n_split; | |
6115 | bitmap_head remove_pseudos; | |
6116 | bitmap_iterator bi; | |
6117 | bool change_p; | |
6118 | ||
6119 | lra_undo_inheritance_iter++; | |
8e3a4869 | 6120 | if (lra_undo_inheritance_iter > LRA_MAX_INHERITANCE_PASSES) |
e731262b | 6121 | return false; |
55a2c322 VM |
6122 | if (lra_dump_file != NULL) |
6123 | fprintf (lra_dump_file, | |
6124 | "\n********** Undoing inheritance #%d: **********\n\n", | |
6125 | lra_undo_inheritance_iter); | |
6126 | bitmap_initialize (&remove_pseudos, ®_obstack); | |
6127 | n_inherit = n_all_inherit = 0; | |
6128 | EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos, 0, regno, bi) | |
6129 | if (lra_reg_info[regno].restore_regno >= 0) | |
6130 | { | |
6131 | n_all_inherit++; | |
b0681c9e VM |
6132 | if (reg_renumber[regno] < 0 |
6133 | /* If the original pseudo changed its allocation, just | |
6134 | removing inheritance is dangerous as for changing | |
6135 | allocation we used shorter live-ranges. */ | |
6136 | && reg_renumber[lra_reg_info[regno].restore_regno] < 0) | |
55a2c322 VM |
6137 | bitmap_set_bit (&remove_pseudos, regno); |
6138 | else | |
6139 | n_inherit++; | |
6140 | } | |
6141 | if (lra_dump_file != NULL && n_all_inherit != 0) | |
6142 | fprintf (lra_dump_file, "Inherit %d out of %d (%.2f%%)\n", | |
6143 | n_inherit, n_all_inherit, | |
6144 | (double) n_inherit / n_all_inherit * 100); | |
6145 | n_split = n_all_split = 0; | |
6146 | EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs, 0, regno, bi) | |
6147 | if ((restore_regno = lra_reg_info[regno].restore_regno) >= 0) | |
6148 | { | |
6149 | n_all_split++; | |
6150 | hard_regno = (restore_regno >= FIRST_PSEUDO_REGISTER | |
6151 | ? reg_renumber[restore_regno] : restore_regno); | |
6152 | if (hard_regno < 0 || reg_renumber[regno] == hard_regno) | |
6153 | bitmap_set_bit (&remove_pseudos, regno); | |
6154 | else | |
6155 | { | |
6156 | n_split++; | |
6157 | if (lra_dump_file != NULL) | |
6158 | fprintf (lra_dump_file, " Keep split r%d (orig=r%d)\n", | |
6159 | regno, restore_regno); | |
6160 | } | |
6161 | } | |
6162 | if (lra_dump_file != NULL && n_all_split != 0) | |
6163 | fprintf (lra_dump_file, "Split %d out of %d (%.2f%%)\n", | |
6164 | n_split, n_all_split, | |
6165 | (double) n_split / n_all_split * 100); | |
6166 | change_p = remove_inheritance_pseudos (&remove_pseudos); | |
6167 | bitmap_clear (&remove_pseudos); | |
6168 | /* Clear restore_regnos. */ | |
6169 | EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos, 0, regno, bi) | |
6170 | lra_reg_info[regno].restore_regno = -1; | |
6171 | EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs, 0, regno, bi) | |
6172 | lra_reg_info[regno].restore_regno = -1; | |
2b778c9d | 6173 | change_p = undo_optional_reloads () || change_p; |
55a2c322 VM |
6174 | return change_p; |
6175 | } |