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55a2c322 | 1 | /* Code for RTL transformations to satisfy insn constraints. |
cbe34bb5 | 2 | Copyright (C) 2010-2017 Free Software Foundation, Inc. |
55a2c322 VM |
3 | Contributed by Vladimir Makarov <vmakarov@redhat.com>. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it under | |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 3, or (at your option) any later | |
10 | version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | ||
22 | /* This file contains code for 3 passes: constraint pass, | |
23 | inheritance/split pass, and pass for undoing failed inheritance and | |
24 | split. | |
25 | ||
26 | The major goal of constraint pass is to transform RTL to satisfy | |
27 | insn and address constraints by: | |
28 | o choosing insn alternatives; | |
29 | o generating *reload insns* (or reloads in brief) and *reload | |
30 | pseudos* which will get necessary hard registers later; | |
31 | o substituting pseudos with equivalent values and removing the | |
32 | instructions that initialized those pseudos. | |
33 | ||
34 | The constraint pass has biggest and most complicated code in LRA. | |
35 | There are a lot of important details like: | |
36 | o reuse of input reload pseudos to simplify reload pseudo | |
37 | allocations; | |
38 | o some heuristics to choose insn alternative to improve the | |
39 | inheritance; | |
40 | o early clobbers etc. | |
41 | ||
42 | The pass is mimicking former reload pass in alternative choosing | |
43 | because the reload pass is oriented to current machine description | |
44 | model. It might be changed if the machine description model is | |
45 | changed. | |
46 | ||
47 | There is special code for preventing all LRA and this pass cycling | |
48 | in case of bugs. | |
49 | ||
50 | On the first iteration of the pass we process every instruction and | |
51 | choose an alternative for each one. On subsequent iterations we try | |
52 | to avoid reprocessing instructions if we can be sure that the old | |
53 | choice is still valid. | |
54 | ||
55 | The inheritance/spilt pass is to transform code to achieve | |
56 | ineheritance and live range splitting. It is done on backward | |
57 | traversal of EBBs. | |
58 | ||
59 | The inheritance optimization goal is to reuse values in hard | |
60 | registers. There is analogous optimization in old reload pass. The | |
61 | inheritance is achieved by following transformation: | |
62 | ||
63 | reload_p1 <- p reload_p1 <- p | |
64 | ... new_p <- reload_p1 | |
65 | ... => ... | |
66 | reload_p2 <- p reload_p2 <- new_p | |
67 | ||
68 | where p is spilled and not changed between the insns. Reload_p1 is | |
69 | also called *original pseudo* and new_p is called *inheritance | |
70 | pseudo*. | |
71 | ||
72 | The subsequent assignment pass will try to assign the same (or | |
73 | another if it is not possible) hard register to new_p as to | |
74 | reload_p1 or reload_p2. | |
75 | ||
76 | If the assignment pass fails to assign a hard register to new_p, | |
77 | this file will undo the inheritance and restore the original code. | |
78 | This is because implementing the above sequence with a spilled | |
79 | new_p would make the code much worse. The inheritance is done in | |
80 | EBB scope. The above is just a simplified example to get an idea | |
81 | of the inheritance as the inheritance is also done for non-reload | |
82 | insns. | |
83 | ||
84 | Splitting (transformation) is also done in EBB scope on the same | |
85 | pass as the inheritance: | |
86 | ||
87 | r <- ... or ... <- r r <- ... or ... <- r | |
88 | ... s <- r (new insn -- save) | |
f4eafc30 | 89 | ... => |
55a2c322 VM |
90 | ... r <- s (new insn -- restore) |
91 | ... <- r ... <- r | |
92 | ||
93 | The *split pseudo* s is assigned to the hard register of the | |
94 | original pseudo or hard register r. | |
95 | ||
96 | Splitting is done: | |
97 | o In EBBs with high register pressure for global pseudos (living | |
98 | in at least 2 BBs) and assigned to hard registers when there | |
99 | are more one reloads needing the hard registers; | |
100 | o for pseudos needing save/restore code around calls. | |
101 | ||
102 | If the split pseudo still has the same hard register as the | |
103 | original pseudo after the subsequent assignment pass or the | |
104 | original pseudo was split, the opposite transformation is done on | |
105 | the same pass for undoing inheritance. */ | |
106 | ||
107 | #undef REG_OK_STRICT | |
108 | ||
109 | #include "config.h" | |
110 | #include "system.h" | |
111 | #include "coretypes.h" | |
c7131fb2 | 112 | #include "backend.h" |
957060b5 | 113 | #include "target.h" |
55a2c322 | 114 | #include "rtl.h" |
957060b5 AM |
115 | #include "tree.h" |
116 | #include "predict.h" | |
c7131fb2 | 117 | #include "df.h" |
4d0cdd0c | 118 | #include "memmodel.h" |
55a2c322 | 119 | #include "tm_p.h" |
957060b5 AM |
120 | #include "expmed.h" |
121 | #include "optabs.h" | |
55a2c322 | 122 | #include "regs.h" |
957060b5 | 123 | #include "ira.h" |
55a2c322 VM |
124 | #include "recog.h" |
125 | #include "output.h" | |
126 | #include "addresses.h" | |
55a2c322 | 127 | #include "expr.h" |
60393bbc | 128 | #include "cfgrtl.h" |
55a2c322 | 129 | #include "rtl-error.h" |
fb8a0e40 | 130 | #include "params.h" |
c7131fb2 | 131 | #include "lra.h" |
55a2c322 | 132 | #include "lra-int.h" |
013a8899 | 133 | #include "print-rtl.h" |
55a2c322 VM |
134 | |
135 | /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current | |
136 | insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted | |
137 | reload insns. */ | |
138 | static int bb_reload_num; | |
139 | ||
2c62cbaa VM |
140 | /* The current insn being processed and corresponding its single set |
141 | (NULL otherwise), its data (basic block, the insn data, the insn | |
142 | static data, and the mode of each operand). */ | |
cfa434f6 | 143 | static rtx_insn *curr_insn; |
2c62cbaa | 144 | static rtx curr_insn_set; |
55a2c322 VM |
145 | static basic_block curr_bb; |
146 | static lra_insn_recog_data_t curr_id; | |
147 | static struct lra_static_insn_data *curr_static_id; | |
ef4bddc2 | 148 | static machine_mode curr_operand_mode[MAX_RECOG_OPERANDS]; |
895ff86f VM |
149 | /* Mode of the register substituted by its equivalence with VOIDmode |
150 | (e.g. constant) and whose subreg is given operand of the current | |
151 | insn. VOIDmode in all other cases. */ | |
152 | static machine_mode original_subreg_reg_mode[MAX_RECOG_OPERANDS]; | |
55a2c322 VM |
153 | |
154 | \f | |
155 | ||
156 | /* Start numbers for new registers and insns at the current constraints | |
157 | pass start. */ | |
158 | static int new_regno_start; | |
159 | static int new_insn_uid_start; | |
160 | ||
277f65de RS |
161 | /* If LOC is nonnull, strip any outer subreg from it. */ |
162 | static inline rtx * | |
163 | strip_subreg (rtx *loc) | |
164 | { | |
165 | return loc && GET_CODE (*loc) == SUBREG ? &SUBREG_REG (*loc) : loc; | |
166 | } | |
167 | ||
55a2c322 VM |
168 | /* Return hard regno of REGNO or if it is was not assigned to a hard |
169 | register, use a hard register from its allocno class. */ | |
170 | static int | |
171 | get_try_hard_regno (int regno) | |
172 | { | |
173 | int hard_regno; | |
174 | enum reg_class rclass; | |
175 | ||
176 | if ((hard_regno = regno) >= FIRST_PSEUDO_REGISTER) | |
177 | hard_regno = lra_get_regno_hard_regno (regno); | |
178 | if (hard_regno >= 0) | |
179 | return hard_regno; | |
180 | rclass = lra_get_allocno_class (regno); | |
181 | if (rclass == NO_REGS) | |
182 | return -1; | |
183 | return ira_class_hard_regs[rclass][0]; | |
184 | } | |
185 | ||
9d0a9bb4 PB |
186 | /* Return the hard regno of X after removing its subreg. If X is not |
187 | a register or a subreg of a register, return -1. If X is a pseudo, | |
1686923c BE |
188 | use its assignment. If FINAL_P return the final hard regno which will |
189 | be after elimination. */ | |
55a2c322 | 190 | static int |
1686923c | 191 | get_hard_regno (rtx x, bool final_p) |
55a2c322 VM |
192 | { |
193 | rtx reg; | |
1686923c | 194 | int hard_regno; |
55a2c322 VM |
195 | |
196 | reg = x; | |
9d0a9bb4 | 197 | if (SUBREG_P (x)) |
55a2c322 VM |
198 | reg = SUBREG_REG (x); |
199 | if (! REG_P (reg)) | |
200 | return -1; | |
9d0a9bb4 | 201 | if (! HARD_REGISTER_NUM_P (hard_regno = REGNO (reg))) |
55a2c322 VM |
202 | hard_regno = lra_get_regno_hard_regno (hard_regno); |
203 | if (hard_regno < 0) | |
204 | return -1; | |
1686923c BE |
205 | if (final_p) |
206 | hard_regno = lra_get_elimination_hard_regno (hard_regno); | |
9d0a9bb4 | 207 | if (SUBREG_P (x)) |
1686923c BE |
208 | hard_regno += subreg_regno_offset (hard_regno, GET_MODE (reg), |
209 | SUBREG_BYTE (x), GET_MODE (x)); | |
210 | return hard_regno; | |
55a2c322 VM |
211 | } |
212 | ||
213 | /* If REGNO is a hard register or has been allocated a hard register, | |
214 | return the class of that register. If REGNO is a reload pseudo | |
215 | created by the current constraints pass, return its allocno class. | |
216 | Return NO_REGS otherwise. */ | |
217 | static enum reg_class | |
218 | get_reg_class (int regno) | |
219 | { | |
220 | int hard_regno; | |
221 | ||
1686923c | 222 | if (! HARD_REGISTER_NUM_P (hard_regno = regno)) |
55a2c322 VM |
223 | hard_regno = lra_get_regno_hard_regno (regno); |
224 | if (hard_regno >= 0) | |
225 | { | |
1686923c | 226 | hard_regno = lra_get_elimination_hard_regno (hard_regno); |
55a2c322 VM |
227 | return REGNO_REG_CLASS (hard_regno); |
228 | } | |
229 | if (regno >= new_regno_start) | |
230 | return lra_get_allocno_class (regno); | |
231 | return NO_REGS; | |
232 | } | |
233 | ||
234 | /* Return true if REG satisfies (or will satisfy) reg class constraint | |
235 | CL. Use elimination first if REG is a hard register. If REG is a | |
236 | reload pseudo created by this constraints pass, assume that it will | |
237 | be allocated a hard register from its allocno class, but allow that | |
238 | class to be narrowed to CL if it is currently a superset of CL. | |
239 | ||
240 | If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of | |
241 | REGNO (reg), or NO_REGS if no change in its class was needed. */ | |
242 | static bool | |
243 | in_class_p (rtx reg, enum reg_class cl, enum reg_class *new_class) | |
244 | { | |
245 | enum reg_class rclass, common_class; | |
ef4bddc2 | 246 | machine_mode reg_mode; |
55a2c322 VM |
247 | int class_size, hard_regno, nregs, i, j; |
248 | int regno = REGNO (reg); | |
f4eafc30 | 249 | |
55a2c322 VM |
250 | if (new_class != NULL) |
251 | *new_class = NO_REGS; | |
252 | if (regno < FIRST_PSEUDO_REGISTER) | |
253 | { | |
254 | rtx final_reg = reg; | |
255 | rtx *final_loc = &final_reg; | |
f4eafc30 | 256 | |
55a2c322 VM |
257 | lra_eliminate_reg_if_possible (final_loc); |
258 | return TEST_HARD_REG_BIT (reg_class_contents[cl], REGNO (*final_loc)); | |
259 | } | |
260 | reg_mode = GET_MODE (reg); | |
261 | rclass = get_reg_class (regno); | |
262 | if (regno < new_regno_start | |
263 | /* Do not allow the constraints for reload instructions to | |
264 | influence the classes of new pseudos. These reloads are | |
265 | typically moves that have many alternatives, and restricting | |
266 | reload pseudos for one alternative may lead to situations | |
267 | where other reload pseudos are no longer allocatable. */ | |
a2d0d374 VM |
268 | || (INSN_UID (curr_insn) >= new_insn_uid_start |
269 | && curr_insn_set != NULL | |
58532ca6 VM |
270 | && ((OBJECT_P (SET_SRC (curr_insn_set)) |
271 | && ! CONSTANT_P (SET_SRC (curr_insn_set))) | |
a2d0d374 | 272 | || (GET_CODE (SET_SRC (curr_insn_set)) == SUBREG |
58532ca6 VM |
273 | && OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set))) |
274 | && ! CONSTANT_P (SUBREG_REG (SET_SRC (curr_insn_set))))))) | |
55a2c322 VM |
275 | /* When we don't know what class will be used finally for reload |
276 | pseudos, we use ALL_REGS. */ | |
277 | return ((regno >= new_regno_start && rclass == ALL_REGS) | |
278 | || (rclass != NO_REGS && ira_class_subset_p[rclass][cl] | |
279 | && ! hard_reg_set_subset_p (reg_class_contents[cl], | |
280 | lra_no_alloc_regs))); | |
281 | else | |
282 | { | |
283 | common_class = ira_reg_class_subset[rclass][cl]; | |
284 | if (new_class != NULL) | |
285 | *new_class = common_class; | |
286 | if (hard_reg_set_subset_p (reg_class_contents[common_class], | |
287 | lra_no_alloc_regs)) | |
288 | return false; | |
289 | /* Check that there are enough allocatable regs. */ | |
290 | class_size = ira_class_hard_regs_num[common_class]; | |
291 | for (i = 0; i < class_size; i++) | |
292 | { | |
293 | hard_regno = ira_class_hard_regs[common_class][i]; | |
294 | nregs = hard_regno_nregs[hard_regno][reg_mode]; | |
295 | if (nregs == 1) | |
296 | return true; | |
297 | for (j = 0; j < nregs; j++) | |
f421c426 VM |
298 | if (TEST_HARD_REG_BIT (lra_no_alloc_regs, hard_regno + j) |
299 | || ! TEST_HARD_REG_BIT (reg_class_contents[common_class], | |
300 | hard_regno + j)) | |
55a2c322 VM |
301 | break; |
302 | if (j >= nregs) | |
303 | return true; | |
304 | } | |
305 | return false; | |
306 | } | |
307 | } | |
308 | ||
309 | /* Return true if REGNO satisfies a memory constraint. */ | |
310 | static bool | |
311 | in_mem_p (int regno) | |
312 | { | |
313 | return get_reg_class (regno) == NO_REGS; | |
314 | } | |
315 | ||
a953491e RS |
316 | /* Return 1 if ADDR is a valid memory address for mode MODE in address |
317 | space AS, and check that each pseudo has the proper kind of hard | |
318 | reg. */ | |
319 | static int | |
ef4bddc2 | 320 | valid_address_p (machine_mode mode ATTRIBUTE_UNUSED, |
a953491e RS |
321 | rtx addr, addr_space_t as) |
322 | { | |
323 | #ifdef GO_IF_LEGITIMATE_ADDRESS | |
324 | lra_assert (ADDR_SPACE_GENERIC_P (as)); | |
325 | GO_IF_LEGITIMATE_ADDRESS (mode, addr, win); | |
326 | return 0; | |
327 | ||
328 | win: | |
329 | return 1; | |
330 | #else | |
331 | return targetm.addr_space.legitimate_address_p (mode, addr, 0, as); | |
332 | #endif | |
333 | } | |
334 | ||
335 | namespace { | |
336 | /* Temporarily eliminates registers in an address (for the lifetime of | |
337 | the object). */ | |
338 | class address_eliminator { | |
339 | public: | |
340 | address_eliminator (struct address_info *ad); | |
341 | ~address_eliminator (); | |
342 | ||
343 | private: | |
344 | struct address_info *m_ad; | |
345 | rtx *m_base_loc; | |
346 | rtx m_base_reg; | |
347 | rtx *m_index_loc; | |
348 | rtx m_index_reg; | |
349 | }; | |
350 | } | |
351 | ||
352 | address_eliminator::address_eliminator (struct address_info *ad) | |
353 | : m_ad (ad), | |
354 | m_base_loc (strip_subreg (ad->base_term)), | |
355 | m_base_reg (NULL_RTX), | |
356 | m_index_loc (strip_subreg (ad->index_term)), | |
357 | m_index_reg (NULL_RTX) | |
358 | { | |
359 | if (m_base_loc != NULL) | |
360 | { | |
361 | m_base_reg = *m_base_loc; | |
362 | lra_eliminate_reg_if_possible (m_base_loc); | |
363 | if (m_ad->base_term2 != NULL) | |
364 | *m_ad->base_term2 = *m_ad->base_term; | |
365 | } | |
366 | if (m_index_loc != NULL) | |
367 | { | |
368 | m_index_reg = *m_index_loc; | |
369 | lra_eliminate_reg_if_possible (m_index_loc); | |
370 | } | |
371 | } | |
372 | ||
373 | address_eliminator::~address_eliminator () | |
374 | { | |
375 | if (m_base_loc && *m_base_loc != m_base_reg) | |
376 | { | |
377 | *m_base_loc = m_base_reg; | |
378 | if (m_ad->base_term2 != NULL) | |
379 | *m_ad->base_term2 = *m_ad->base_term; | |
380 | } | |
381 | if (m_index_loc && *m_index_loc != m_index_reg) | |
382 | *m_index_loc = m_index_reg; | |
383 | } | |
384 | ||
385 | /* Return true if the eliminated form of AD is a legitimate target address. */ | |
386 | static bool | |
387 | valid_address_p (struct address_info *ad) | |
388 | { | |
389 | address_eliminator eliminator (ad); | |
390 | return valid_address_p (ad->mode, *ad->outer, ad->as); | |
391 | } | |
392 | ||
a953491e | 393 | /* Return true if the eliminated form of memory reference OP satisfies |
9eb1ca69 | 394 | extra (special) memory constraint CONSTRAINT. */ |
a953491e | 395 | static bool |
777e635f | 396 | satisfies_memory_constraint_p (rtx op, enum constraint_num constraint) |
a953491e RS |
397 | { |
398 | struct address_info ad; | |
399 | ||
400 | decompose_mem_address (&ad, op); | |
401 | address_eliminator eliminator (&ad); | |
777e635f | 402 | return constraint_satisfied_p (op, constraint); |
a953491e RS |
403 | } |
404 | ||
405 | /* Return true if the eliminated form of address AD satisfies extra | |
406 | address constraint CONSTRAINT. */ | |
407 | static bool | |
408 | satisfies_address_constraint_p (struct address_info *ad, | |
777e635f | 409 | enum constraint_num constraint) |
a953491e RS |
410 | { |
411 | address_eliminator eliminator (ad); | |
777e635f | 412 | return constraint_satisfied_p (*ad->outer, constraint); |
a953491e RS |
413 | } |
414 | ||
415 | /* Return true if the eliminated form of address OP satisfies extra | |
416 | address constraint CONSTRAINT. */ | |
417 | static bool | |
777e635f | 418 | satisfies_address_constraint_p (rtx op, enum constraint_num constraint) |
a953491e RS |
419 | { |
420 | struct address_info ad; | |
421 | ||
422 | decompose_lea_address (&ad, &op); | |
423 | return satisfies_address_constraint_p (&ad, constraint); | |
424 | } | |
a953491e | 425 | |
4c2b2d79 VM |
426 | /* Initiate equivalences for LRA. As we keep original equivalences |
427 | before any elimination, we need to make copies otherwise any change | |
428 | in insns might change the equivalences. */ | |
429 | void | |
430 | lra_init_equiv (void) | |
431 | { | |
432 | ira_expand_reg_equiv (); | |
433 | for (int i = FIRST_PSEUDO_REGISTER; i < max_reg_num (); i++) | |
434 | { | |
435 | rtx res; | |
436 | ||
437 | if ((res = ira_reg_equiv[i].memory) != NULL_RTX) | |
438 | ira_reg_equiv[i].memory = copy_rtx (res); | |
439 | if ((res = ira_reg_equiv[i].invariant) != NULL_RTX) | |
440 | ira_reg_equiv[i].invariant = copy_rtx (res); | |
441 | } | |
442 | } | |
443 | ||
444 | static rtx loc_equivalence_callback (rtx, const_rtx, void *); | |
445 | ||
446 | /* Update equivalence for REGNO. We need to this as the equivalence | |
447 | might contain other pseudos which are changed by their | |
448 | equivalences. */ | |
449 | static void | |
450 | update_equiv (int regno) | |
451 | { | |
452 | rtx x; | |
453 | ||
454 | if ((x = ira_reg_equiv[regno].memory) != NULL_RTX) | |
455 | ira_reg_equiv[regno].memory | |
456 | = simplify_replace_fn_rtx (x, NULL_RTX, loc_equivalence_callback, | |
457 | NULL_RTX); | |
458 | if ((x = ira_reg_equiv[regno].invariant) != NULL_RTX) | |
459 | ira_reg_equiv[regno].invariant | |
460 | = simplify_replace_fn_rtx (x, NULL_RTX, loc_equivalence_callback, | |
461 | NULL_RTX); | |
462 | } | |
463 | ||
55a2c322 VM |
464 | /* If we have decided to substitute X with another value, return that |
465 | value, otherwise return X. */ | |
466 | static rtx | |
8d49e7ef | 467 | get_equiv (rtx x) |
55a2c322 VM |
468 | { |
469 | int regno; | |
470 | rtx res; | |
471 | ||
472 | if (! REG_P (x) || (regno = REGNO (x)) < FIRST_PSEUDO_REGISTER | |
473 | || ! ira_reg_equiv[regno].defined_p | |
474 | || ! ira_reg_equiv[regno].profitable_p | |
475 | || lra_get_regno_hard_regno (regno) >= 0) | |
476 | return x; | |
477 | if ((res = ira_reg_equiv[regno].memory) != NULL_RTX) | |
d6220b11 KK |
478 | { |
479 | if (targetm.cannot_substitute_mem_equiv_p (res)) | |
480 | return x; | |
481 | return res; | |
482 | } | |
55a2c322 VM |
483 | if ((res = ira_reg_equiv[regno].constant) != NULL_RTX) |
484 | return res; | |
485 | if ((res = ira_reg_equiv[regno].invariant) != NULL_RTX) | |
486 | return res; | |
487 | gcc_unreachable (); | |
488 | } | |
489 | ||
8d49e7ef VM |
490 | /* If we have decided to substitute X with the equivalent value, |
491 | return that value after elimination for INSN, otherwise return | |
492 | X. */ | |
493 | static rtx | |
cfa434f6 | 494 | get_equiv_with_elimination (rtx x, rtx_insn *insn) |
8d49e7ef VM |
495 | { |
496 | rtx res = get_equiv (x); | |
497 | ||
498 | if (x == res || CONSTANT_P (res)) | |
499 | return res; | |
d9cf932c | 500 | return lra_eliminate_regs_1 (insn, res, GET_MODE (res), |
a6af1bf9 | 501 | false, false, 0, true); |
8d49e7ef VM |
502 | } |
503 | ||
55a2c322 VM |
504 | /* Set up curr_operand_mode. */ |
505 | static void | |
506 | init_curr_operand_mode (void) | |
507 | { | |
508 | int nop = curr_static_id->n_operands; | |
509 | for (int i = 0; i < nop; i++) | |
510 | { | |
ef4bddc2 | 511 | machine_mode mode = GET_MODE (*curr_id->operand_loc[i]); |
55a2c322 VM |
512 | if (mode == VOIDmode) |
513 | { | |
514 | /* The .md mode for address operands is the mode of the | |
515 | addressed value rather than the mode of the address itself. */ | |
516 | if (curr_id->icode >= 0 && curr_static_id->operand[i].is_address) | |
517 | mode = Pmode; | |
518 | else | |
519 | mode = curr_static_id->operand[i].mode; | |
520 | } | |
521 | curr_operand_mode[i] = mode; | |
522 | } | |
523 | } | |
524 | ||
525 | \f | |
526 | ||
527 | /* The page contains code to reuse input reloads. */ | |
528 | ||
529 | /* Structure describes input reload of the current insns. */ | |
530 | struct input_reload | |
531 | { | |
3f156a6c VM |
532 | /* True for input reload of matched operands. */ |
533 | bool match_p; | |
55a2c322 VM |
534 | /* Reloaded value. */ |
535 | rtx input; | |
536 | /* Reload pseudo used. */ | |
537 | rtx reg; | |
538 | }; | |
539 | ||
540 | /* The number of elements in the following array. */ | |
541 | static int curr_insn_input_reloads_num; | |
542 | /* Array containing info about input reloads. It is used to find the | |
543 | same input reload and reuse the reload pseudo in this case. */ | |
544 | static struct input_reload curr_insn_input_reloads[LRA_MAX_INSN_RELOADS]; | |
545 | ||
546 | /* Initiate data concerning reuse of input reloads for the current | |
547 | insn. */ | |
548 | static void | |
549 | init_curr_insn_input_reloads (void) | |
550 | { | |
551 | curr_insn_input_reloads_num = 0; | |
552 | } | |
553 | ||
55a2c322 | 554 | /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already |
95921002 VM |
555 | created input reload pseudo (only if TYPE is not OP_OUT). Don't |
556 | reuse pseudo if IN_SUBREG_P is true and the reused pseudo should be | |
557 | wrapped up in SUBREG. The result pseudo is returned through | |
558 | RESULT_REG. Return TRUE if we created a new pseudo, FALSE if we | |
559 | reused the already created input reload pseudo. Use TITLE to | |
560 | describe new registers for debug purposes. */ | |
55a2c322 | 561 | static bool |
ef4bddc2 | 562 | get_reload_reg (enum op_type type, machine_mode mode, rtx original, |
95921002 VM |
563 | enum reg_class rclass, bool in_subreg_p, |
564 | const char *title, rtx *result_reg) | |
55a2c322 VM |
565 | { |
566 | int i, regno; | |
567 | enum reg_class new_class; | |
3f156a6c | 568 | bool unique_p = false; |
55a2c322 VM |
569 | |
570 | if (type == OP_OUT) | |
571 | { | |
572 | *result_reg | |
573 | = lra_create_new_reg_with_unique_value (mode, original, rclass, title); | |
574 | return true; | |
575 | } | |
73cca0cc VM |
576 | /* Prevent reuse value of expression with side effects, |
577 | e.g. volatile memory. */ | |
578 | if (! side_effects_p (original)) | |
579 | for (i = 0; i < curr_insn_input_reloads_num; i++) | |
3f156a6c VM |
580 | { |
581 | if (! curr_insn_input_reloads[i].match_p | |
582 | && rtx_equal_p (curr_insn_input_reloads[i].input, original) | |
583 | && in_class_p (curr_insn_input_reloads[i].reg, rclass, &new_class)) | |
584 | { | |
585 | rtx reg = curr_insn_input_reloads[i].reg; | |
586 | regno = REGNO (reg); | |
587 | /* If input is equal to original and both are VOIDmode, | |
588 | GET_MODE (reg) might be still different from mode. | |
589 | Ensure we don't return *result_reg with wrong mode. */ | |
590 | if (GET_MODE (reg) != mode) | |
591 | { | |
592 | if (in_subreg_p) | |
593 | continue; | |
594 | if (GET_MODE_SIZE (GET_MODE (reg)) < GET_MODE_SIZE (mode)) | |
595 | continue; | |
596 | reg = lowpart_subreg (mode, reg, GET_MODE (reg)); | |
597 | if (reg == NULL_RTX || GET_CODE (reg) != SUBREG) | |
598 | continue; | |
599 | } | |
600 | *result_reg = reg; | |
601 | if (lra_dump_file != NULL) | |
602 | { | |
603 | fprintf (lra_dump_file, " Reuse r%d for reload ", regno); | |
604 | dump_value_slim (lra_dump_file, original, 1); | |
605 | } | |
606 | if (new_class != lra_get_allocno_class (regno)) | |
607 | lra_change_class (regno, new_class, ", change to", false); | |
608 | if (lra_dump_file != NULL) | |
609 | fprintf (lra_dump_file, "\n"); | |
610 | return false; | |
611 | } | |
612 | /* If we have an input reload with a different mode, make sure it | |
613 | will get a different hard reg. */ | |
614 | else if (REG_P (original) | |
615 | && REG_P (curr_insn_input_reloads[i].input) | |
616 | && REGNO (original) == REGNO (curr_insn_input_reloads[i].input) | |
617 | && (GET_MODE (original) | |
618 | != GET_MODE (curr_insn_input_reloads[i].input))) | |
619 | unique_p = true; | |
620 | } | |
621 | *result_reg = (unique_p | |
622 | ? lra_create_new_reg_with_unique_value | |
623 | : lra_create_new_reg) (mode, original, rclass, title); | |
55a2c322 VM |
624 | lra_assert (curr_insn_input_reloads_num < LRA_MAX_INSN_RELOADS); |
625 | curr_insn_input_reloads[curr_insn_input_reloads_num].input = original; | |
3f156a6c | 626 | curr_insn_input_reloads[curr_insn_input_reloads_num].match_p = false; |
55a2c322 VM |
627 | curr_insn_input_reloads[curr_insn_input_reloads_num++].reg = *result_reg; |
628 | return true; | |
629 | } | |
630 | ||
631 | \f | |
632 | ||
633 | /* The page contains code to extract memory address parts. */ | |
634 | ||
55a2c322 VM |
635 | /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudos. */ |
636 | static inline bool | |
637 | ok_for_index_p_nonstrict (rtx reg) | |
638 | { | |
639 | unsigned regno = REGNO (reg); | |
f4eafc30 | 640 | |
55a2c322 VM |
641 | return regno >= FIRST_PSEUDO_REGISTER || REGNO_OK_FOR_INDEX_P (regno); |
642 | } | |
643 | ||
644 | /* A version of regno_ok_for_base_p for use here, when all pseudos | |
645 | should count as OK. Arguments as for regno_ok_for_base_p. */ | |
646 | static inline bool | |
ef4bddc2 | 647 | ok_for_base_p_nonstrict (rtx reg, machine_mode mode, addr_space_t as, |
55a2c322 VM |
648 | enum rtx_code outer_code, enum rtx_code index_code) |
649 | { | |
650 | unsigned regno = REGNO (reg); | |
651 | ||
652 | if (regno >= FIRST_PSEUDO_REGISTER) | |
653 | return true; | |
654 | return ok_for_base_p_1 (regno, mode, as, outer_code, index_code); | |
655 | } | |
656 | ||
55a2c322 VM |
657 | \f |
658 | ||
659 | /* The page contains major code to choose the current insn alternative | |
660 | and generate reloads for it. */ | |
661 | ||
662 | /* Return the offset from REGNO of the least significant register | |
663 | in (reg:MODE REGNO). | |
664 | ||
665 | This function is used to tell whether two registers satisfy | |
666 | a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if: | |
667 | ||
668 | REGNO1 + lra_constraint_offset (REGNO1, MODE1) | |
669 | == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */ | |
670 | int | |
ef4bddc2 | 671 | lra_constraint_offset (int regno, machine_mode mode) |
55a2c322 VM |
672 | { |
673 | lra_assert (regno < FIRST_PSEUDO_REGISTER); | |
674 | if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (mode) > UNITS_PER_WORD | |
675 | && SCALAR_INT_MODE_P (mode)) | |
676 | return hard_regno_nregs[regno][mode] - 1; | |
677 | return 0; | |
678 | } | |
679 | ||
680 | /* Like rtx_equal_p except that it allows a REG and a SUBREG to match | |
681 | if they are the same hard reg, and has special hacks for | |
682 | auto-increment and auto-decrement. This is specifically intended for | |
683 | process_alt_operands to use in determining whether two operands | |
684 | match. X is the operand whose number is the lower of the two. | |
685 | ||
686 | It is supposed that X is the output operand and Y is the input | |
687 | operand. Y_HARD_REGNO is the final hard regno of register Y or | |
688 | register in subreg Y as we know it now. Otherwise, it is a | |
689 | negative value. */ | |
690 | static bool | |
691 | operands_match_p (rtx x, rtx y, int y_hard_regno) | |
692 | { | |
693 | int i; | |
694 | RTX_CODE code = GET_CODE (x); | |
695 | const char *fmt; | |
696 | ||
697 | if (x == y) | |
698 | return true; | |
699 | if ((code == REG || (code == SUBREG && REG_P (SUBREG_REG (x)))) | |
700 | && (REG_P (y) || (GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y))))) | |
701 | { | |
702 | int j; | |
f4eafc30 | 703 | |
1686923c | 704 | i = get_hard_regno (x, false); |
55a2c322 VM |
705 | if (i < 0) |
706 | goto slow; | |
707 | ||
708 | if ((j = y_hard_regno) < 0) | |
709 | goto slow; | |
710 | ||
711 | i += lra_constraint_offset (i, GET_MODE (x)); | |
712 | j += lra_constraint_offset (j, GET_MODE (y)); | |
713 | ||
714 | return i == j; | |
715 | } | |
716 | ||
717 | /* If two operands must match, because they are really a single | |
718 | operand of an assembler insn, then two post-increments are invalid | |
719 | because the assembler insn would increment only once. On the | |
720 | other hand, a post-increment matches ordinary indexing if the | |
721 | post-increment is the output operand. */ | |
722 | if (code == POST_DEC || code == POST_INC || code == POST_MODIFY) | |
723 | return operands_match_p (XEXP (x, 0), y, y_hard_regno); | |
724 | ||
725 | /* Two pre-increments are invalid because the assembler insn would | |
726 | increment only once. On the other hand, a pre-increment matches | |
727 | ordinary indexing if the pre-increment is the input operand. */ | |
728 | if (GET_CODE (y) == PRE_DEC || GET_CODE (y) == PRE_INC | |
729 | || GET_CODE (y) == PRE_MODIFY) | |
730 | return operands_match_p (x, XEXP (y, 0), -1); | |
f4eafc30 | 731 | |
55a2c322 VM |
732 | slow: |
733 | ||
9fccb335 RS |
734 | if (code == REG && REG_P (y)) |
735 | return REGNO (x) == REGNO (y); | |
736 | ||
55a2c322 VM |
737 | if (code == REG && GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y)) |
738 | && x == SUBREG_REG (y)) | |
739 | return true; | |
740 | if (GET_CODE (y) == REG && code == SUBREG && REG_P (SUBREG_REG (x)) | |
741 | && SUBREG_REG (x) == y) | |
742 | return true; | |
743 | ||
744 | /* Now we have disposed of all the cases in which different rtx | |
745 | codes can match. */ | |
746 | if (code != GET_CODE (y)) | |
747 | return false; | |
748 | ||
749 | /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */ | |
750 | if (GET_MODE (x) != GET_MODE (y)) | |
751 | return false; | |
752 | ||
753 | switch (code) | |
754 | { | |
755 | CASE_CONST_UNIQUE: | |
756 | return false; | |
757 | ||
758 | case LABEL_REF: | |
04a121a7 | 759 | return label_ref_label (x) == label_ref_label (y); |
55a2c322 VM |
760 | case SYMBOL_REF: |
761 | return XSTR (x, 0) == XSTR (y, 0); | |
762 | ||
763 | default: | |
764 | break; | |
765 | } | |
766 | ||
767 | /* Compare the elements. If any pair of corresponding elements fail | |
768 | to match, return false for the whole things. */ | |
769 | ||
770 | fmt = GET_RTX_FORMAT (code); | |
771 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
772 | { | |
773 | int val, j; | |
774 | switch (fmt[i]) | |
775 | { | |
776 | case 'w': | |
777 | if (XWINT (x, i) != XWINT (y, i)) | |
778 | return false; | |
779 | break; | |
780 | ||
781 | case 'i': | |
782 | if (XINT (x, i) != XINT (y, i)) | |
783 | return false; | |
784 | break; | |
785 | ||
786 | case 'e': | |
787 | val = operands_match_p (XEXP (x, i), XEXP (y, i), -1); | |
788 | if (val == 0) | |
789 | return false; | |
790 | break; | |
791 | ||
792 | case '0': | |
793 | break; | |
794 | ||
795 | case 'E': | |
796 | if (XVECLEN (x, i) != XVECLEN (y, i)) | |
797 | return false; | |
798 | for (j = XVECLEN (x, i) - 1; j >= 0; --j) | |
799 | { | |
800 | val = operands_match_p (XVECEXP (x, i, j), XVECEXP (y, i, j), -1); | |
801 | if (val == 0) | |
802 | return false; | |
803 | } | |
804 | break; | |
805 | ||
806 | /* It is believed that rtx's at this level will never | |
807 | contain anything but integers and other rtx's, except for | |
808 | within LABEL_REFs and SYMBOL_REFs. */ | |
809 | default: | |
810 | gcc_unreachable (); | |
811 | } | |
812 | } | |
813 | return true; | |
814 | } | |
815 | ||
816 | /* True if X is a constant that can be forced into the constant pool. | |
817 | MODE is the mode of the operand, or VOIDmode if not known. */ | |
818 | #define CONST_POOL_OK_P(MODE, X) \ | |
819 | ((MODE) != VOIDmode \ | |
820 | && CONSTANT_P (X) \ | |
821 | && GET_CODE (X) != HIGH \ | |
822 | && !targetm.cannot_force_const_mem (MODE, X)) | |
823 | ||
824 | /* True if C is a non-empty register class that has too few registers | |
825 | to be safely used as a reload target class. */ | |
a9711f36 VM |
826 | #define SMALL_REGISTER_CLASS_P(C) \ |
827 | (ira_class_hard_regs_num [(C)] == 1 \ | |
828 | || (ira_class_hard_regs_num [(C)] >= 1 \ | |
829 | && targetm.class_likely_spilled_p (C))) | |
55a2c322 VM |
830 | |
831 | /* If REG is a reload pseudo, try to make its class satisfying CL. */ | |
832 | static void | |
833 | narrow_reload_pseudo_class (rtx reg, enum reg_class cl) | |
834 | { | |
835 | enum reg_class rclass; | |
836 | ||
837 | /* Do not make more accurate class from reloads generated. They are | |
838 | mostly moves with a lot of constraints. Making more accurate | |
839 | class may results in very narrow class and impossibility of find | |
840 | registers for several reloads of one insn. */ | |
841 | if (INSN_UID (curr_insn) >= new_insn_uid_start) | |
842 | return; | |
843 | if (GET_CODE (reg) == SUBREG) | |
844 | reg = SUBREG_REG (reg); | |
845 | if (! REG_P (reg) || (int) REGNO (reg) < new_regno_start) | |
846 | return; | |
847 | if (in_class_p (reg, cl, &rclass) && rclass != cl) | |
a2d0d374 | 848 | lra_change_class (REGNO (reg), rclass, " Change to", true); |
55a2c322 VM |
849 | } |
850 | ||
4be9717c VM |
851 | /* Searches X for any reference to a reg with the same value as REGNO, |
852 | returning the rtx of the reference found if any. Otherwise, | |
853 | returns NULL_RTX. */ | |
854 | static rtx | |
855 | regno_val_use_in (unsigned int regno, rtx x) | |
856 | { | |
857 | const char *fmt; | |
858 | int i, j; | |
859 | rtx tem; | |
860 | ||
861 | if (REG_P (x) && lra_reg_info[REGNO (x)].val == lra_reg_info[regno].val) | |
862 | return x; | |
863 | ||
864 | fmt = GET_RTX_FORMAT (GET_CODE (x)); | |
865 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) | |
866 | { | |
867 | if (fmt[i] == 'e') | |
868 | { | |
869 | if ((tem = regno_val_use_in (regno, XEXP (x, i)))) | |
870 | return tem; | |
871 | } | |
872 | else if (fmt[i] == 'E') | |
873 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
874 | if ((tem = regno_val_use_in (regno , XVECEXP (x, i, j)))) | |
875 | return tem; | |
876 | } | |
877 | ||
878 | return NULL_RTX; | |
879 | } | |
880 | ||
55a2c322 | 881 | /* Generate reloads for matching OUT and INS (array of input operand |
aefae0f1 TP |
882 | numbers with end marker -1) with reg class GOAL_CLASS, considering |
883 | output operands OUTS (similar array to INS) needing to be in different | |
884 | registers. Add input and output reloads correspondingly to the lists | |
885 | *BEFORE and *AFTER. OUT might be negative. In this case we generate | |
886 | input reloads for matched input operands INS. EARLY_CLOBBER_P is a flag | |
887 | that the output operand is early clobbered for chosen alternative. */ | |
55a2c322 | 888 | static void |
aefae0f1 TP |
889 | match_reload (signed char out, signed char *ins, signed char *outs, |
890 | enum reg_class goal_class, rtx_insn **before, | |
891 | rtx_insn **after, bool early_clobber_p) | |
55a2c322 | 892 | { |
aefae0f1 | 893 | bool out_conflict; |
55a2c322 | 894 | int i, in; |
e67d1102 | 895 | rtx new_in_reg, new_out_reg, reg; |
ef4bddc2 | 896 | machine_mode inmode, outmode; |
55a2c322 | 897 | rtx in_rtx = *curr_id->operand_loc[ins[0]]; |
511dcace | 898 | rtx out_rtx = out < 0 ? in_rtx : *curr_id->operand_loc[out]; |
55a2c322 | 899 | |
55a2c322 | 900 | inmode = curr_operand_mode[ins[0]]; |
511dcace | 901 | outmode = out < 0 ? inmode : curr_operand_mode[out]; |
55a2c322 VM |
902 | push_to_sequence (*before); |
903 | if (inmode != outmode) | |
904 | { | |
905 | if (GET_MODE_SIZE (inmode) > GET_MODE_SIZE (outmode)) | |
906 | { | |
907 | reg = new_in_reg | |
908 | = lra_create_new_reg_with_unique_value (inmode, in_rtx, | |
909 | goal_class, ""); | |
910 | if (SCALAR_INT_MODE_P (inmode)) | |
911 | new_out_reg = gen_lowpart_SUBREG (outmode, reg); | |
912 | else | |
913 | new_out_reg = gen_rtx_SUBREG (outmode, reg, 0); | |
2c62cbaa | 914 | LRA_SUBREG_P (new_out_reg) = 1; |
350c0fe7 | 915 | /* If the input reg is dying here, we can use the same hard |
f681cf95 VM |
916 | register for REG and IN_RTX. We do it only for original |
917 | pseudos as reload pseudos can die although original | |
918 | pseudos still live where reload pseudos dies. */ | |
919 | if (REG_P (in_rtx) && (int) REGNO (in_rtx) < lra_new_regno_start | |
350c0fe7 | 920 | && find_regno_note (curr_insn, REG_DEAD, REGNO (in_rtx))) |
d70a81dd | 921 | lra_assign_reg_val (REGNO (in_rtx), REGNO (reg)); |
55a2c322 VM |
922 | } |
923 | else | |
924 | { | |
925 | reg = new_out_reg | |
926 | = lra_create_new_reg_with_unique_value (outmode, out_rtx, | |
927 | goal_class, ""); | |
928 | if (SCALAR_INT_MODE_P (outmode)) | |
929 | new_in_reg = gen_lowpart_SUBREG (inmode, reg); | |
930 | else | |
931 | new_in_reg = gen_rtx_SUBREG (inmode, reg, 0); | |
932 | /* NEW_IN_REG is non-paradoxical subreg. We don't want | |
933 | NEW_OUT_REG living above. We add clobber clause for | |
c5cd5a7e VM |
934 | this. This is just a temporary clobber. We can remove |
935 | it at the end of LRA work. */ | |
e67d1102 | 936 | rtx_insn *clobber = emit_clobber (new_out_reg); |
c5cd5a7e | 937 | LRA_TEMP_CLOBBER_P (PATTERN (clobber)) = 1; |
2c62cbaa | 938 | LRA_SUBREG_P (new_in_reg) = 1; |
350c0fe7 VM |
939 | if (GET_CODE (in_rtx) == SUBREG) |
940 | { | |
941 | rtx subreg_reg = SUBREG_REG (in_rtx); | |
942 | ||
943 | /* If SUBREG_REG is dying here and sub-registers IN_RTX | |
944 | and NEW_IN_REG are similar, we can use the same hard | |
945 | register for REG and SUBREG_REG. */ | |
f681cf95 VM |
946 | if (REG_P (subreg_reg) |
947 | && (int) REGNO (subreg_reg) < lra_new_regno_start | |
948 | && GET_MODE (subreg_reg) == outmode | |
350c0fe7 VM |
949 | && SUBREG_BYTE (in_rtx) == SUBREG_BYTE (new_in_reg) |
950 | && find_regno_note (curr_insn, REG_DEAD, REGNO (subreg_reg))) | |
d70a81dd | 951 | lra_assign_reg_val (REGNO (subreg_reg), REGNO (reg)); |
350c0fe7 | 952 | } |
55a2c322 VM |
953 | } |
954 | } | |
955 | else | |
956 | { | |
957 | /* Pseudos have values -- see comments for lra_reg_info. | |
958 | Different pseudos with the same value do not conflict even if | |
959 | they live in the same place. When we create a pseudo we | |
960 | assign value of original pseudo (if any) from which we | |
961 | created the new pseudo. If we create the pseudo from the | |
3363daad VM |
962 | input pseudo, the new pseudo will have no conflict with the |
963 | input pseudo which is wrong when the input pseudo lives after | |
964 | the insn and as the new pseudo value is changed by the insn | |
965 | output. Therefore we create the new pseudo from the output | |
966 | except the case when we have single matched dying input | |
967 | pseudo. | |
f4eafc30 | 968 | |
55a2c322 VM |
969 | We cannot reuse the current output register because we might |
970 | have a situation like "a <- a op b", where the constraints | |
971 | force the second input operand ("b") to match the output | |
972 | operand ("a"). "b" must then be copied into a new register | |
599e1cf8 VM |
973 | so that it doesn't clobber the current value of "a". |
974 | ||
975 | We can not use the same value if the output pseudo is | |
976 | early clobbered or the input pseudo is mentioned in the | |
977 | output, e.g. as an address part in memory, because | |
978 | output reload will actually extend the pseudo liveness. | |
979 | We don't care about eliminable hard regs here as we are | |
980 | interesting only in pseudos. */ | |
f4eafc30 | 981 | |
aefae0f1 TP |
982 | /* Matching input's register value is the same as one of the other |
983 | output operand. Output operands in a parallel insn must be in | |
984 | different registers. */ | |
985 | out_conflict = false; | |
986 | if (REG_P (in_rtx)) | |
987 | { | |
988 | for (i = 0; outs[i] >= 0; i++) | |
989 | { | |
990 | rtx other_out_rtx = *curr_id->operand_loc[outs[i]]; | |
991 | if (REG_P (other_out_rtx) | |
992 | && (regno_val_use_in (REGNO (in_rtx), other_out_rtx) | |
993 | != NULL_RTX)) | |
994 | { | |
995 | out_conflict = true; | |
996 | break; | |
997 | } | |
998 | } | |
999 | } | |
1000 | ||
55a2c322 | 1001 | new_in_reg = new_out_reg |
599e1cf8 | 1002 | = (! early_clobber_p && ins[1] < 0 && REG_P (in_rtx) |
3363daad VM |
1003 | && (int) REGNO (in_rtx) < lra_new_regno_start |
1004 | && find_regno_note (curr_insn, REG_DEAD, REGNO (in_rtx)) | |
4be9717c VM |
1005 | && (out < 0 |
1006 | || regno_val_use_in (REGNO (in_rtx), out_rtx) == NULL_RTX) | |
aefae0f1 | 1007 | && !out_conflict |
3363daad VM |
1008 | ? lra_create_new_reg (inmode, in_rtx, goal_class, "") |
1009 | : lra_create_new_reg_with_unique_value (outmode, out_rtx, | |
1010 | goal_class, "")); | |
55a2c322 | 1011 | } |
511dcace VM |
1012 | /* In operand can be got from transformations before processing insn |
1013 | constraints. One example of such transformations is subreg | |
1014 | reloading (see function simplify_operand_subreg). The new | |
1015 | pseudos created by the transformations might have inaccurate | |
55a2c322 VM |
1016 | class (ALL_REGS) and we should make their classes more |
1017 | accurate. */ | |
1018 | narrow_reload_pseudo_class (in_rtx, goal_class); | |
55a2c322 VM |
1019 | lra_emit_move (copy_rtx (new_in_reg), in_rtx); |
1020 | *before = get_insns (); | |
1021 | end_sequence (); | |
3f156a6c VM |
1022 | /* Add the new pseudo to consider values of subsequent input reload |
1023 | pseudos. */ | |
1024 | lra_assert (curr_insn_input_reloads_num < LRA_MAX_INSN_RELOADS); | |
1025 | curr_insn_input_reloads[curr_insn_input_reloads_num].input = in_rtx; | |
1026 | curr_insn_input_reloads[curr_insn_input_reloads_num].match_p = true; | |
1027 | curr_insn_input_reloads[curr_insn_input_reloads_num++].reg = new_in_reg; | |
55a2c322 VM |
1028 | for (i = 0; (in = ins[i]) >= 0; i++) |
1029 | { | |
1030 | lra_assert | |
1031 | (GET_MODE (*curr_id->operand_loc[in]) == VOIDmode | |
1032 | || GET_MODE (new_in_reg) == GET_MODE (*curr_id->operand_loc[in])); | |
1033 | *curr_id->operand_loc[in] = new_in_reg; | |
1034 | } | |
1035 | lra_update_dups (curr_id, ins); | |
511dcace VM |
1036 | if (out < 0) |
1037 | return; | |
1038 | /* See a comment for the input operand above. */ | |
1039 | narrow_reload_pseudo_class (out_rtx, goal_class); | |
55a2c322 VM |
1040 | if (find_reg_note (curr_insn, REG_UNUSED, out_rtx) == NULL_RTX) |
1041 | { | |
1042 | start_sequence (); | |
1043 | lra_emit_move (out_rtx, copy_rtx (new_out_reg)); | |
1044 | emit_insn (*after); | |
1045 | *after = get_insns (); | |
1046 | end_sequence (); | |
1047 | } | |
1048 | *curr_id->operand_loc[out] = new_out_reg; | |
1049 | lra_update_dup (curr_id, out); | |
1050 | } | |
1051 | ||
1052 | /* Return register class which is union of all reg classes in insn | |
1053 | constraint alternative string starting with P. */ | |
1054 | static enum reg_class | |
1055 | reg_class_from_constraints (const char *p) | |
1056 | { | |
1057 | int c, len; | |
1058 | enum reg_class op_class = NO_REGS; | |
1059 | ||
1060 | do | |
1061 | switch ((c = *p, len = CONSTRAINT_LEN (c, p)), c) | |
1062 | { | |
1063 | case '#': | |
1064 | case ',': | |
1065 | return op_class; | |
1066 | ||
55a2c322 | 1067 | case 'g': |
55a2c322 VM |
1068 | op_class = reg_class_subunion[op_class][GENERAL_REGS]; |
1069 | break; | |
f4eafc30 | 1070 | |
55a2c322 | 1071 | default: |
777e635f RS |
1072 | enum constraint_num cn = lookup_constraint (p); |
1073 | enum reg_class cl = reg_class_for_constraint (cn); | |
1074 | if (cl == NO_REGS) | |
55a2c322 | 1075 | { |
777e635f | 1076 | if (insn_extra_address_constraint (cn)) |
55a2c322 VM |
1077 | op_class |
1078 | = (reg_class_subunion | |
1079 | [op_class][base_reg_class (VOIDmode, ADDR_SPACE_GENERIC, | |
1080 | ADDRESS, SCRATCH)]); | |
55a2c322 VM |
1081 | break; |
1082 | } | |
f4eafc30 | 1083 | |
777e635f RS |
1084 | op_class = reg_class_subunion[op_class][cl]; |
1085 | break; | |
55a2c322 VM |
1086 | } |
1087 | while ((p += len), c); | |
1088 | return op_class; | |
1089 | } | |
1090 | ||
1091 | /* If OP is a register, return the class of the register as per | |
1092 | get_reg_class, otherwise return NO_REGS. */ | |
1093 | static inline enum reg_class | |
1094 | get_op_class (rtx op) | |
1095 | { | |
1096 | return REG_P (op) ? get_reg_class (REGNO (op)) : NO_REGS; | |
1097 | } | |
1098 | ||
1099 | /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo | |
1100 | otherwise. If modes of MEM_PSEUDO and VAL are different, use | |
1101 | SUBREG for VAL to make them equal. */ | |
cfa434f6 | 1102 | static rtx_insn * |
55a2c322 VM |
1103 | emit_spill_move (bool to_p, rtx mem_pseudo, rtx val) |
1104 | { | |
1105 | if (GET_MODE (mem_pseudo) != GET_MODE (val)) | |
2c62cbaa | 1106 | { |
cb1cca12 VM |
1107 | /* Usually size of mem_pseudo is greater than val size but in |
1108 | rare cases it can be less as it can be defined by target | |
1109 | dependent macro HARD_REGNO_CALLER_SAVE_MODE. */ | |
1ccd4874 VM |
1110 | if (! MEM_P (val)) |
1111 | { | |
54b84aa9 EB |
1112 | val = gen_lowpart_SUBREG (GET_MODE (mem_pseudo), |
1113 | GET_CODE (val) == SUBREG | |
1114 | ? SUBREG_REG (val) : val); | |
1ccd4874 VM |
1115 | LRA_SUBREG_P (val) = 1; |
1116 | } | |
1117 | else | |
1118 | { | |
1119 | mem_pseudo = gen_lowpart_SUBREG (GET_MODE (val), mem_pseudo); | |
1120 | LRA_SUBREG_P (mem_pseudo) = 1; | |
1121 | } | |
2c62cbaa | 1122 | } |
1476d1bd MM |
1123 | return to_p ? gen_move_insn (mem_pseudo, val) |
1124 | : gen_move_insn (val, mem_pseudo); | |
55a2c322 VM |
1125 | } |
1126 | ||
1127 | /* Process a special case insn (register move), return true if we | |
2c62cbaa VM |
1128 | don't need to process it anymore. INSN should be a single set |
1129 | insn. Set up that RTL was changed through CHANGE_P and macro | |
1130 | SECONDARY_MEMORY_NEEDED says to use secondary memory through | |
1131 | SEC_MEM_P. */ | |
55a2c322 | 1132 | static bool |
2c62cbaa | 1133 | check_and_process_move (bool *change_p, bool *sec_mem_p ATTRIBUTE_UNUSED) |
55a2c322 VM |
1134 | { |
1135 | int sregno, dregno; | |
ef0006eb | 1136 | rtx dest, src, dreg, sreg, new_reg, scratch_reg; |
cfa434f6 | 1137 | rtx_insn *before; |
55a2c322 | 1138 | enum reg_class dclass, sclass, secondary_class; |
55a2c322 VM |
1139 | secondary_reload_info sri; |
1140 | ||
2c62cbaa VM |
1141 | lra_assert (curr_insn_set != NULL_RTX); |
1142 | dreg = dest = SET_DEST (curr_insn_set); | |
1143 | sreg = src = SET_SRC (curr_insn_set); | |
55a2c322 VM |
1144 | if (GET_CODE (dest) == SUBREG) |
1145 | dreg = SUBREG_REG (dest); | |
1146 | if (GET_CODE (src) == SUBREG) | |
1147 | sreg = SUBREG_REG (src); | |
1ccd4874 | 1148 | if (! (REG_P (dreg) || MEM_P (dreg)) || ! (REG_P (sreg) || MEM_P (sreg))) |
55a2c322 VM |
1149 | return false; |
1150 | sclass = dclass = NO_REGS; | |
55a2c322 VM |
1151 | if (REG_P (dreg)) |
1152 | dclass = get_reg_class (REGNO (dreg)); | |
48855443 | 1153 | gcc_assert (dclass < LIM_REG_CLASSES); |
55a2c322 VM |
1154 | if (dclass == ALL_REGS) |
1155 | /* ALL_REGS is used for new pseudos created by transformations | |
1156 | like reload of SUBREG_REG (see function | |
1157 | simplify_operand_subreg). We don't know their class yet. We | |
1158 | should figure out the class from processing the insn | |
1159 | constraints not in this fast path function. Even if ALL_REGS | |
1160 | were a right class for the pseudo, secondary_... hooks usually | |
1161 | are not define for ALL_REGS. */ | |
1162 | return false; | |
55a2c322 VM |
1163 | if (REG_P (sreg)) |
1164 | sclass = get_reg_class (REGNO (sreg)); | |
48855443 | 1165 | gcc_assert (sclass < LIM_REG_CLASSES); |
55a2c322 VM |
1166 | if (sclass == ALL_REGS) |
1167 | /* See comments above. */ | |
1168 | return false; | |
1ccd4874 VM |
1169 | if (sclass == NO_REGS && dclass == NO_REGS) |
1170 | return false; | |
55a2c322 | 1171 | #ifdef SECONDARY_MEMORY_NEEDED |
1ccd4874 VM |
1172 | if (SECONDARY_MEMORY_NEEDED (sclass, dclass, GET_MODE (src)) |
1173 | #ifdef SECONDARY_MEMORY_NEEDED_MODE | |
1174 | && ((sclass != NO_REGS && dclass != NO_REGS) | |
1175 | || GET_MODE (src) != SECONDARY_MEMORY_NEEDED_MODE (GET_MODE (src))) | |
1176 | #endif | |
1177 | ) | |
55a2c322 VM |
1178 | { |
1179 | *sec_mem_p = true; | |
1180 | return false; | |
1181 | } | |
1182 | #endif | |
1ccd4874 VM |
1183 | if (! REG_P (dreg) || ! REG_P (sreg)) |
1184 | return false; | |
55a2c322 VM |
1185 | sri.prev_sri = NULL; |
1186 | sri.icode = CODE_FOR_nothing; | |
1187 | sri.extra_cost = 0; | |
1188 | secondary_class = NO_REGS; | |
1189 | /* Set up hard register for a reload pseudo for hook | |
1190 | secondary_reload because some targets just ignore unassigned | |
1191 | pseudos in the hook. */ | |
1192 | if (dclass != NO_REGS && lra_get_regno_hard_regno (REGNO (dreg)) < 0) | |
1193 | { | |
1194 | dregno = REGNO (dreg); | |
1195 | reg_renumber[dregno] = ira_class_hard_regs[dclass][0]; | |
1196 | } | |
1197 | else | |
1198 | dregno = -1; | |
1199 | if (sclass != NO_REGS && lra_get_regno_hard_regno (REGNO (sreg)) < 0) | |
1200 | { | |
1201 | sregno = REGNO (sreg); | |
1202 | reg_renumber[sregno] = ira_class_hard_regs[sclass][0]; | |
1203 | } | |
1204 | else | |
1205 | sregno = -1; | |
1206 | if (sclass != NO_REGS) | |
1207 | secondary_class | |
1208 | = (enum reg_class) targetm.secondary_reload (false, dest, | |
1209 | (reg_class_t) sclass, | |
1210 | GET_MODE (src), &sri); | |
1211 | if (sclass == NO_REGS | |
1212 | || ((secondary_class != NO_REGS || sri.icode != CODE_FOR_nothing) | |
1213 | && dclass != NO_REGS)) | |
1214 | { | |
55a2c322 VM |
1215 | enum reg_class old_sclass = secondary_class; |
1216 | secondary_reload_info old_sri = sri; | |
55a2c322 VM |
1217 | |
1218 | sri.prev_sri = NULL; | |
1219 | sri.icode = CODE_FOR_nothing; | |
1220 | sri.extra_cost = 0; | |
1221 | secondary_class | |
ef0006eb | 1222 | = (enum reg_class) targetm.secondary_reload (true, src, |
55a2c322 | 1223 | (reg_class_t) dclass, |
ef0006eb | 1224 | GET_MODE (src), &sri); |
55a2c322 VM |
1225 | /* Check the target hook consistency. */ |
1226 | lra_assert | |
1227 | ((secondary_class == NO_REGS && sri.icode == CODE_FOR_nothing) | |
1228 | || (old_sclass == NO_REGS && old_sri.icode == CODE_FOR_nothing) | |
1229 | || (secondary_class == old_sclass && sri.icode == old_sri.icode)); | |
1230 | } | |
1231 | if (sregno >= 0) | |
1232 | reg_renumber [sregno] = -1; | |
1233 | if (dregno >= 0) | |
1234 | reg_renumber [dregno] = -1; | |
1235 | if (secondary_class == NO_REGS && sri.icode == CODE_FOR_nothing) | |
1236 | return false; | |
1237 | *change_p = true; | |
1238 | new_reg = NULL_RTX; | |
1239 | if (secondary_class != NO_REGS) | |
ef0006eb | 1240 | new_reg = lra_create_new_reg_with_unique_value (GET_MODE (src), NULL_RTX, |
55a2c322 VM |
1241 | secondary_class, |
1242 | "secondary"); | |
1243 | start_sequence (); | |
55a2c322 | 1244 | if (sri.icode == CODE_FOR_nothing) |
ef0006eb | 1245 | lra_emit_move (new_reg, src); |
55a2c322 VM |
1246 | else |
1247 | { | |
1248 | enum reg_class scratch_class; | |
1249 | ||
1250 | scratch_class = (reg_class_from_constraints | |
1251 | (insn_data[sri.icode].operand[2].constraint)); | |
1252 | scratch_reg = (lra_create_new_reg_with_unique_value | |
1253 | (insn_data[sri.icode].operand[2].mode, NULL_RTX, | |
1254 | scratch_class, "scratch")); | |
1255 | emit_insn (GEN_FCN (sri.icode) (new_reg != NULL_RTX ? new_reg : dest, | |
ef0006eb | 1256 | src, scratch_reg)); |
55a2c322 VM |
1257 | } |
1258 | before = get_insns (); | |
1259 | end_sequence (); | |
cfa434f6 | 1260 | lra_process_new_insns (curr_insn, before, NULL, "Inserting the move"); |
55a2c322 | 1261 | if (new_reg != NULL_RTX) |
ef0006eb | 1262 | SET_SRC (curr_insn_set) = new_reg; |
55a2c322 VM |
1263 | else |
1264 | { | |
1265 | if (lra_dump_file != NULL) | |
1266 | { | |
1267 | fprintf (lra_dump_file, "Deleting move %u\n", INSN_UID (curr_insn)); | |
cfbeaedf | 1268 | dump_insn_slim (lra_dump_file, curr_insn); |
55a2c322 VM |
1269 | } |
1270 | lra_set_insn_deleted (curr_insn); | |
1271 | return true; | |
1272 | } | |
1273 | return false; | |
1274 | } | |
1275 | ||
1276 | /* The following data describe the result of process_alt_operands. | |
1277 | The data are used in curr_insn_transform to generate reloads. */ | |
1278 | ||
1279 | /* The chosen reg classes which should be used for the corresponding | |
1280 | operands. */ | |
1281 | static enum reg_class goal_alt[MAX_RECOG_OPERANDS]; | |
1282 | /* True if the operand should be the same as another operand and that | |
1283 | other operand does not need a reload. */ | |
1284 | static bool goal_alt_match_win[MAX_RECOG_OPERANDS]; | |
1285 | /* True if the operand does not need a reload. */ | |
1286 | static bool goal_alt_win[MAX_RECOG_OPERANDS]; | |
1287 | /* True if the operand can be offsetable memory. */ | |
1288 | static bool goal_alt_offmemok[MAX_RECOG_OPERANDS]; | |
1289 | /* The number of an operand to which given operand can be matched to. */ | |
1290 | static int goal_alt_matches[MAX_RECOG_OPERANDS]; | |
1291 | /* The number of elements in the following array. */ | |
1292 | static int goal_alt_dont_inherit_ops_num; | |
1293 | /* Numbers of operands whose reload pseudos should not be inherited. */ | |
1294 | static int goal_alt_dont_inherit_ops[MAX_RECOG_OPERANDS]; | |
1295 | /* True if the insn commutative operands should be swapped. */ | |
1296 | static bool goal_alt_swapped; | |
1297 | /* The chosen insn alternative. */ | |
1298 | static int goal_alt_number; | |
1299 | ||
987b67f1 VM |
1300 | /* True if the corresponding operand is the result of an equivalence |
1301 | substitution. */ | |
1302 | static bool equiv_substition_p[MAX_RECOG_OPERANDS]; | |
1303 | ||
55a2c322 VM |
1304 | /* The following five variables are used to choose the best insn |
1305 | alternative. They reflect final characteristics of the best | |
1306 | alternative. */ | |
1307 | ||
1308 | /* Number of necessary reloads and overall cost reflecting the | |
1309 | previous value and other unpleasantness of the best alternative. */ | |
1310 | static int best_losers, best_overall; | |
55a2c322 VM |
1311 | /* Overall number hard registers used for reloads. For example, on |
1312 | some targets we need 2 general registers to reload DFmode and only | |
1313 | one floating point register. */ | |
1314 | static int best_reload_nregs; | |
1315 | /* Overall number reflecting distances of previous reloading the same | |
1316 | value. The distances are counted from the current BB start. It is | |
1317 | used to improve inheritance chances. */ | |
1318 | static int best_reload_sum; | |
1319 | ||
1320 | /* True if the current insn should have no correspondingly input or | |
1321 | output reloads. */ | |
1322 | static bool no_input_reloads_p, no_output_reloads_p; | |
1323 | ||
1324 | /* True if we swapped the commutative operands in the current | |
1325 | insn. */ | |
1326 | static int curr_swapped; | |
1327 | ||
d9cf932c VM |
1328 | /* if CHECK_ONLY_P is false, arrange for address element *LOC to be a |
1329 | register of class CL. Add any input reloads to list BEFORE. AFTER | |
1330 | is nonnull if *LOC is an automodified value; handle that case by | |
1331 | adding the required output reloads to list AFTER. Return true if | |
1332 | the RTL was changed. | |
1333 | ||
1334 | if CHECK_ONLY_P is true, check that the *LOC is a correct address | |
1335 | register. Return false if the address register is correct. */ | |
55a2c322 | 1336 | static bool |
d9cf932c | 1337 | process_addr_reg (rtx *loc, bool check_only_p, rtx_insn **before, rtx_insn **after, |
cfa434f6 | 1338 | enum reg_class cl) |
55a2c322 VM |
1339 | { |
1340 | int regno; | |
1341 | enum reg_class rclass, new_class; | |
277f65de | 1342 | rtx reg; |
55a2c322 | 1343 | rtx new_reg; |
ef4bddc2 | 1344 | machine_mode mode; |
95921002 | 1345 | bool subreg_p, before_p = false; |
55a2c322 | 1346 | |
95921002 VM |
1347 | subreg_p = GET_CODE (*loc) == SUBREG; |
1348 | if (subreg_p) | |
ada2eb68 JW |
1349 | { |
1350 | reg = SUBREG_REG (*loc); | |
1351 | mode = GET_MODE (reg); | |
1352 | ||
1353 | /* For mode with size bigger than ptr_mode, there unlikely to be "mov" | |
1354 | between two registers with different classes, but there normally will | |
1355 | be "mov" which transfers element of vector register into the general | |
1356 | register, and this normally will be a subreg which should be reloaded | |
1357 | as a whole. This is particularly likely to be triggered when | |
1358 | -fno-split-wide-types specified. */ | |
3c11e1af JW |
1359 | if (!REG_P (reg) |
1360 | || in_class_p (reg, cl, &new_class) | |
ada2eb68 JW |
1361 | || GET_MODE_SIZE (mode) <= GET_MODE_SIZE (ptr_mode)) |
1362 | loc = &SUBREG_REG (*loc); | |
1363 | } | |
1364 | ||
277f65de | 1365 | reg = *loc; |
55a2c322 VM |
1366 | mode = GET_MODE (reg); |
1367 | if (! REG_P (reg)) | |
1368 | { | |
d9cf932c VM |
1369 | if (check_only_p) |
1370 | return true; | |
55a2c322 VM |
1371 | /* Always reload memory in an address even if the target supports |
1372 | such addresses. */ | |
1373 | new_reg = lra_create_new_reg_with_unique_value (mode, reg, cl, "address"); | |
1374 | before_p = true; | |
1375 | } | |
1376 | else | |
1377 | { | |
1378 | regno = REGNO (reg); | |
1379 | rclass = get_reg_class (regno); | |
d9cf932c VM |
1380 | if (! check_only_p |
1381 | && (*loc = get_equiv_with_elimination (reg, curr_insn)) != reg) | |
55a2c322 VM |
1382 | { |
1383 | if (lra_dump_file != NULL) | |
1384 | { | |
1385 | fprintf (lra_dump_file, | |
1386 | "Changing pseudo %d in address of insn %u on equiv ", | |
1387 | REGNO (reg), INSN_UID (curr_insn)); | |
cfbeaedf | 1388 | dump_value_slim (lra_dump_file, *loc, 1); |
55a2c322 VM |
1389 | fprintf (lra_dump_file, "\n"); |
1390 | } | |
1391 | *loc = copy_rtx (*loc); | |
1392 | } | |
1393 | if (*loc != reg || ! in_class_p (reg, cl, &new_class)) | |
1394 | { | |
d9cf932c VM |
1395 | if (check_only_p) |
1396 | return true; | |
55a2c322 VM |
1397 | reg = *loc; |
1398 | if (get_reload_reg (after == NULL ? OP_IN : OP_INOUT, | |
95921002 | 1399 | mode, reg, cl, subreg_p, "address", &new_reg)) |
55a2c322 VM |
1400 | before_p = true; |
1401 | } | |
1402 | else if (new_class != NO_REGS && rclass != new_class) | |
1403 | { | |
d9cf932c VM |
1404 | if (check_only_p) |
1405 | return true; | |
a2d0d374 | 1406 | lra_change_class (regno, new_class, " Change to", true); |
55a2c322 VM |
1407 | return false; |
1408 | } | |
1409 | else | |
1410 | return false; | |
1411 | } | |
1412 | if (before_p) | |
1413 | { | |
1414 | push_to_sequence (*before); | |
1415 | lra_emit_move (new_reg, reg); | |
1416 | *before = get_insns (); | |
1417 | end_sequence (); | |
1418 | } | |
1419 | *loc = new_reg; | |
1420 | if (after != NULL) | |
1421 | { | |
1422 | start_sequence (); | |
9a9fe2b4 | 1423 | lra_emit_move (before_p ? copy_rtx (reg) : reg, new_reg); |
55a2c322 VM |
1424 | emit_insn (*after); |
1425 | *after = get_insns (); | |
1426 | end_sequence (); | |
1427 | } | |
1428 | return true; | |
1429 | } | |
1430 | ||
4f0bee4c WM |
1431 | /* Insert move insn in simplify_operand_subreg. BEFORE returns |
1432 | the insn to be inserted before curr insn. AFTER returns the | |
1433 | the insn to be inserted after curr insn. ORIGREG and NEWREG | |
1434 | are the original reg and new reg for reload. */ | |
1435 | static void | |
cfa434f6 DM |
1436 | insert_move_for_subreg (rtx_insn **before, rtx_insn **after, rtx origreg, |
1437 | rtx newreg) | |
4f0bee4c WM |
1438 | { |
1439 | if (before) | |
1440 | { | |
1441 | push_to_sequence (*before); | |
1442 | lra_emit_move (newreg, origreg); | |
1443 | *before = get_insns (); | |
1444 | end_sequence (); | |
1445 | } | |
1446 | if (after) | |
1447 | { | |
1448 | start_sequence (); | |
1449 | lra_emit_move (origreg, newreg); | |
1450 | emit_insn (*after); | |
1451 | *after = get_insns (); | |
1452 | end_sequence (); | |
1453 | } | |
1454 | } | |
1455 | ||
ef4bddc2 | 1456 | static int valid_address_p (machine_mode mode, rtx addr, addr_space_t as); |
ab5d2233 | 1457 | static bool process_address (int, bool, rtx_insn **, rtx_insn **); |
ba38538f | 1458 | |
55a2c322 VM |
1459 | /* Make reloads for subreg in operand NOP with internal subreg mode |
1460 | REG_MODE, add new reloads for further processing. Return true if | |
895ff86f | 1461 | any change was done. */ |
55a2c322 | 1462 | static bool |
ef4bddc2 | 1463 | simplify_operand_subreg (int nop, machine_mode reg_mode) |
55a2c322 VM |
1464 | { |
1465 | int hard_regno; | |
cfa434f6 | 1466 | rtx_insn *before, *after; |
895ff86f | 1467 | machine_mode mode, innermode; |
55a2c322 VM |
1468 | rtx reg, new_reg; |
1469 | rtx operand = *curr_id->operand_loc[nop]; | |
4f0bee4c WM |
1470 | enum reg_class regclass; |
1471 | enum op_type type; | |
55a2c322 | 1472 | |
cfa434f6 | 1473 | before = after = NULL; |
55a2c322 VM |
1474 | |
1475 | if (GET_CODE (operand) != SUBREG) | |
1476 | return false; | |
f4eafc30 | 1477 | |
55a2c322 VM |
1478 | mode = GET_MODE (operand); |
1479 | reg = SUBREG_REG (operand); | |
895ff86f | 1480 | innermode = GET_MODE (reg); |
4f0bee4c | 1481 | type = curr_static_id->operand[nop].type; |
2e186411 | 1482 | if (MEM_P (reg)) |
ba38538f | 1483 | { |
ab5d2233 EB |
1484 | const bool addr_was_valid |
1485 | = valid_address_p (innermode, XEXP (reg, 0), MEM_ADDR_SPACE (reg)); | |
ba38538f | 1486 | alter_subreg (curr_id->operand_loc[nop], false); |
ab5d2233 | 1487 | rtx subst = *curr_id->operand_loc[nop]; |
ba38538f | 1488 | lra_assert (MEM_P (subst)); |
ab5d2233 EB |
1489 | |
1490 | if (!addr_was_valid | |
ba38538f | 1491 | || valid_address_p (GET_MODE (subst), XEXP (subst, 0), |
2e186411 AM |
1492 | MEM_ADDR_SPACE (subst)) |
1493 | || ((get_constraint_type (lookup_constraint | |
1494 | (curr_static_id->operand[nop].constraint)) | |
1495 | != CT_SPECIAL_MEMORY) | |
1496 | /* We still can reload address and if the address is | |
1497 | valid, we can remove subreg without reloading its | |
1498 | inner memory. */ | |
1499 | && valid_address_p (GET_MODE (subst), | |
1500 | regno_reg_rtx | |
1501 | [ira_class_hard_regs | |
1502 | [base_reg_class (GET_MODE (subst), | |
1503 | MEM_ADDR_SPACE (subst), | |
1504 | ADDRESS, SCRATCH)][0]], | |
1505 | MEM_ADDR_SPACE (subst)))) | |
1506 | { | |
ab5d2233 | 1507 | /* If we change the address for a paradoxical subreg of memory, the |
2e186411 | 1508 | address might violate the necessary alignment or the access might |
ab5d2233 EB |
1509 | be slow. So take this into consideration. We need not worry |
1510 | about accesses beyond allocated memory for paradoxical memory | |
2e186411 AM |
1511 | subregs as we don't substitute such equiv memory (see processing |
1512 | equivalences in function lra_constraints) and because for spilled | |
1513 | pseudos we allocate stack memory enough for the biggest | |
1514 | corresponding paradoxical subreg. */ | |
86a21121 PC |
1515 | if (!(MEM_ALIGN (reg) < GET_MODE_ALIGNMENT (mode) |
1516 | && SLOW_UNALIGNED_ACCESS (mode, MEM_ALIGN (reg))) | |
1517 | || (MEM_ALIGN (reg) < GET_MODE_ALIGNMENT (innermode) | |
1518 | && SLOW_UNALIGNED_ACCESS (innermode, MEM_ALIGN (reg)))) | |
2e186411 AM |
1519 | return true; |
1520 | ||
ab5d2233 EB |
1521 | *curr_id->operand_loc[nop] = operand; |
1522 | ||
1523 | /* But if the address was not valid, we cannot reload the MEM without | |
1524 | reloading the address first. */ | |
1525 | if (!addr_was_valid) | |
1526 | process_address (nop, false, &before, &after); | |
1527 | ||
2e186411 AM |
1528 | /* INNERMODE is fast, MODE slow. Reload the mem in INNERMODE. */ |
1529 | enum reg_class rclass | |
1530 | = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS); | |
ab5d2233 EB |
1531 | if (get_reload_reg (curr_static_id->operand[nop].type, innermode, |
1532 | reg, rclass, TRUE, "slow mem", &new_reg)) | |
2e186411 AM |
1533 | { |
1534 | bool insert_before, insert_after; | |
1535 | bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg)); | |
1536 | ||
1537 | insert_before = (type != OP_OUT | |
ab5d2233 EB |
1538 | || GET_MODE_SIZE (innermode) |
1539 | > GET_MODE_SIZE (mode)); | |
2e186411 AM |
1540 | insert_after = type != OP_IN; |
1541 | insert_move_for_subreg (insert_before ? &before : NULL, | |
1542 | insert_after ? &after : NULL, | |
1543 | reg, new_reg); | |
1544 | } | |
2e186411 AM |
1545 | SUBREG_REG (operand) = new_reg; |
1546 | ||
1547 | /* Convert to MODE. */ | |
1548 | reg = operand; | |
ab5d2233 EB |
1549 | rclass |
1550 | = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS); | |
2e186411 AM |
1551 | if (get_reload_reg (curr_static_id->operand[nop].type, mode, reg, |
1552 | rclass, TRUE, "slow mem", &new_reg)) | |
1553 | { | |
1554 | bool insert_before, insert_after; | |
1555 | bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg)); | |
1556 | ||
1557 | insert_before = type != OP_OUT; | |
1558 | insert_after = type != OP_IN; | |
1559 | insert_move_for_subreg (insert_before ? &before : NULL, | |
1560 | insert_after ? &after : NULL, | |
1561 | reg, new_reg); | |
1562 | } | |
1563 | *curr_id->operand_loc[nop] = new_reg; | |
1564 | lra_process_new_insns (curr_insn, before, after, | |
1565 | "Inserting slow mem reload"); | |
1566 | return true; | |
1567 | } | |
95831c01 | 1568 | |
ba38538f VM |
1569 | /* If the address was valid and became invalid, prefer to reload |
1570 | the memory. Typical case is when the index scale should | |
1571 | correspond the memory. */ | |
2e186411 | 1572 | *curr_id->operand_loc[nop] = operand; |
ab5d2233 | 1573 | return false; |
ba38538f VM |
1574 | } |
1575 | else if (REG_P (reg) && REGNO (reg) < FIRST_PSEUDO_REGISTER) | |
55a2c322 VM |
1576 | { |
1577 | alter_subreg (curr_id->operand_loc[nop], false); | |
1578 | return true; | |
1579 | } | |
895ff86f VM |
1580 | else if (CONSTANT_P (reg)) |
1581 | { | |
1582 | /* Try to simplify subreg of constant. It is usually result of | |
1583 | equivalence substitution. */ | |
1584 | if (innermode == VOIDmode | |
1585 | && (innermode = original_subreg_reg_mode[nop]) == VOIDmode) | |
1586 | innermode = curr_static_id->operand[nop].mode; | |
1587 | if ((new_reg = simplify_subreg (mode, reg, innermode, | |
1588 | SUBREG_BYTE (operand))) != NULL_RTX) | |
1589 | { | |
1590 | *curr_id->operand_loc[nop] = new_reg; | |
1591 | return true; | |
1592 | } | |
1593 | } | |
55a2c322 VM |
1594 | /* Put constant into memory when we have mixed modes. It generates |
1595 | a better code in most cases as it does not need a secondary | |
1596 | reload memory. It also prevents LRA looping when LRA is using | |
1597 | secondary reload memory again and again. */ | |
1598 | if (CONSTANT_P (reg) && CONST_POOL_OK_P (reg_mode, reg) | |
1599 | && SCALAR_INT_MODE_P (reg_mode) != SCALAR_INT_MODE_P (mode)) | |
1600 | { | |
1601 | SUBREG_REG (operand) = force_const_mem (reg_mode, reg); | |
1602 | alter_subreg (curr_id->operand_loc[nop], false); | |
1603 | return true; | |
1604 | } | |
1605 | /* Force a reload of the SUBREG_REG if this is a constant or PLUS or | |
1606 | if there may be a problem accessing OPERAND in the outer | |
1607 | mode. */ | |
1608 | if ((REG_P (reg) | |
1609 | && REGNO (reg) >= FIRST_PSEUDO_REGISTER | |
1610 | && (hard_regno = lra_get_regno_hard_regno (REGNO (reg))) >= 0 | |
1611 | /* Don't reload paradoxical subregs because we could be looping | |
1612 | having repeatedly final regno out of hard regs range. */ | |
895ff86f | 1613 | && (hard_regno_nregs[hard_regno][innermode] |
55a2c322 | 1614 | >= hard_regno_nregs[hard_regno][mode]) |
895ff86f | 1615 | && simplify_subreg_regno (hard_regno, innermode, |
2c62cbaa VM |
1616 | SUBREG_BYTE (operand), mode) < 0 |
1617 | /* Don't reload subreg for matching reload. It is actually | |
1618 | valid subreg in LRA. */ | |
1619 | && ! LRA_SUBREG_P (operand)) | |
55a2c322 VM |
1620 | || CONSTANT_P (reg) || GET_CODE (reg) == PLUS || MEM_P (reg)) |
1621 | { | |
6e23f296 VM |
1622 | enum reg_class rclass; |
1623 | ||
7613fa50 VM |
1624 | if (REG_P (reg)) |
1625 | /* There is a big probability that we will get the same class | |
6e23f296 VM |
1626 | for the new pseudo and we will get the same insn which |
1627 | means infinite looping. So spill the new pseudo. */ | |
1628 | rclass = NO_REGS; | |
1629 | else | |
1630 | /* The class will be defined later in curr_insn_transform. */ | |
1631 | rclass | |
1632 | = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS); | |
55a2c322 | 1633 | |
25bb0bb5 | 1634 | if (get_reload_reg (curr_static_id->operand[nop].type, reg_mode, reg, |
95921002 | 1635 | rclass, TRUE, "subreg reg", &new_reg)) |
55a2c322 | 1636 | { |
4f0bee4c | 1637 | bool insert_before, insert_after; |
2b778c9d | 1638 | bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg)); |
4f0bee4c WM |
1639 | |
1640 | insert_before = (type != OP_OUT | |
895ff86f | 1641 | || GET_MODE_SIZE (innermode) > GET_MODE_SIZE (mode)); |
4f0bee4c WM |
1642 | insert_after = (type != OP_IN); |
1643 | insert_move_for_subreg (insert_before ? &before : NULL, | |
1644 | insert_after ? &after : NULL, | |
1645 | reg, new_reg); | |
55a2c322 VM |
1646 | } |
1647 | SUBREG_REG (operand) = new_reg; | |
1648 | lra_process_new_insns (curr_insn, before, after, | |
1649 | "Inserting subreg reload"); | |
1650 | return true; | |
1651 | } | |
4f0bee4c WM |
1652 | /* Force a reload for a paradoxical subreg. For paradoxical subreg, |
1653 | IRA allocates hardreg to the inner pseudo reg according to its mode | |
1654 | instead of the outermode, so the size of the hardreg may not be enough | |
1655 | to contain the outermode operand, in that case we may need to insert | |
1656 | reload for the reg. For the following two types of paradoxical subreg, | |
1657 | we need to insert reload: | |
1658 | 1. If the op_type is OP_IN, and the hardreg could not be paired with | |
1659 | other hardreg to contain the outermode operand | |
1660 | (checked by in_hard_reg_set_p), we need to insert the reload. | |
1661 | 2. If the op_type is OP_OUT or OP_INOUT. | |
1662 | ||
1663 | Here is a paradoxical subreg example showing how the reload is generated: | |
1664 | ||
1665 | (insn 5 4 7 2 (set (reg:TI 106 [ __comp ]) | |
1666 | (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64} | |
1667 | ||
1668 | In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example | |
1669 | here, if reg107 is assigned to hardreg R15, because R15 is the last | |
1670 | hardreg, compiler cannot find another hardreg to pair with R15 to | |
1671 | contain TImode data. So we insert a TImode reload reg180 for it. | |
1672 | After reload is inserted: | |
1673 | ||
1674 | (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0) | |
1675 | (reg:DI 107 [ __comp ])) -1 | |
1676 | (insn 5 4 7 2 (set (reg:TI 106 [ __comp ]) | |
1677 | (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64} | |
1678 | ||
1679 | Two reload hard registers will be allocated to reg180 to save TImode data | |
1680 | in LRA_assign. */ | |
1681 | else if (REG_P (reg) | |
1682 | && REGNO (reg) >= FIRST_PSEUDO_REGISTER | |
1683 | && (hard_regno = lra_get_regno_hard_regno (REGNO (reg))) >= 0 | |
895ff86f | 1684 | && (hard_regno_nregs[hard_regno][innermode] |
4f0bee4c WM |
1685 | < hard_regno_nregs[hard_regno][mode]) |
1686 | && (regclass = lra_get_allocno_class (REGNO (reg))) | |
1687 | && (type != OP_IN | |
1688 | || !in_hard_reg_set_p (reg_class_contents[regclass], | |
1689 | mode, hard_regno))) | |
1690 | { | |
1691 | /* The class will be defined later in curr_insn_transform. */ | |
1692 | enum reg_class rclass | |
1693 | = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS); | |
1694 | ||
1695 | if (get_reload_reg (curr_static_id->operand[nop].type, mode, reg, | |
95921002 | 1696 | rclass, TRUE, "paradoxical subreg", &new_reg)) |
4f0bee4c WM |
1697 | { |
1698 | rtx subreg; | |
1699 | bool insert_before, insert_after; | |
1700 | ||
1701 | PUT_MODE (new_reg, mode); | |
ea09f50d | 1702 | subreg = gen_lowpart_SUBREG (innermode, new_reg); |
4f0bee4c WM |
1703 | bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg)); |
1704 | ||
1705 | insert_before = (type != OP_OUT); | |
1706 | insert_after = (type != OP_IN); | |
1707 | insert_move_for_subreg (insert_before ? &before : NULL, | |
1708 | insert_after ? &after : NULL, | |
1709 | reg, subreg); | |
1710 | } | |
1711 | SUBREG_REG (operand) = new_reg; | |
1712 | lra_process_new_insns (curr_insn, before, after, | |
1713 | "Inserting paradoxical subreg reload"); | |
1714 | return true; | |
1715 | } | |
55a2c322 VM |
1716 | return false; |
1717 | } | |
1718 | ||
1719 | /* Return TRUE if X refers for a hard register from SET. */ | |
1720 | static bool | |
1721 | uses_hard_regs_p (rtx x, HARD_REG_SET set) | |
1722 | { | |
1723 | int i, j, x_hard_regno; | |
ef4bddc2 | 1724 | machine_mode mode; |
55a2c322 VM |
1725 | const char *fmt; |
1726 | enum rtx_code code; | |
1727 | ||
1728 | if (x == NULL_RTX) | |
1729 | return false; | |
1730 | code = GET_CODE (x); | |
1731 | mode = GET_MODE (x); | |
1732 | if (code == SUBREG) | |
1733 | { | |
1734 | x = SUBREG_REG (x); | |
1735 | code = GET_CODE (x); | |
1736 | if (GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (mode)) | |
1737 | mode = GET_MODE (x); | |
1738 | } | |
f4eafc30 | 1739 | |
55a2c322 VM |
1740 | if (REG_P (x)) |
1741 | { | |
1686923c | 1742 | x_hard_regno = get_hard_regno (x, true); |
55a2c322 VM |
1743 | return (x_hard_regno >= 0 |
1744 | && overlaps_hard_reg_set_p (set, mode, x_hard_regno)); | |
1745 | } | |
1746 | if (MEM_P (x)) | |
1747 | { | |
277f65de | 1748 | struct address_info ad; |
55a2c322 | 1749 | |
277f65de RS |
1750 | decompose_mem_address (&ad, x); |
1751 | if (ad.base_term != NULL && uses_hard_regs_p (*ad.base_term, set)) | |
1752 | return true; | |
1753 | if (ad.index_term != NULL && uses_hard_regs_p (*ad.index_term, set)) | |
1754 | return true; | |
55a2c322 VM |
1755 | } |
1756 | fmt = GET_RTX_FORMAT (code); | |
1757 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1758 | { | |
1759 | if (fmt[i] == 'e') | |
1760 | { | |
1761 | if (uses_hard_regs_p (XEXP (x, i), set)) | |
1762 | return true; | |
1763 | } | |
1764 | else if (fmt[i] == 'E') | |
1765 | { | |
1766 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
1767 | if (uses_hard_regs_p (XVECEXP (x, i, j), set)) | |
1768 | return true; | |
1769 | } | |
1770 | } | |
1771 | return false; | |
1772 | } | |
1773 | ||
1774 | /* Return true if OP is a spilled pseudo. */ | |
1775 | static inline bool | |
1776 | spilled_pseudo_p (rtx op) | |
1777 | { | |
1778 | return (REG_P (op) | |
1779 | && REGNO (op) >= FIRST_PSEUDO_REGISTER && in_mem_p (REGNO (op))); | |
1780 | } | |
1781 | ||
1782 | /* Return true if X is a general constant. */ | |
1783 | static inline bool | |
1784 | general_constant_p (rtx x) | |
1785 | { | |
1786 | return CONSTANT_P (x) && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (x)); | |
1787 | } | |
1788 | ||
2c62cbaa VM |
1789 | static bool |
1790 | reg_in_class_p (rtx reg, enum reg_class cl) | |
1791 | { | |
1792 | if (cl == NO_REGS) | |
1793 | return get_reg_class (REGNO (reg)) == NO_REGS; | |
1794 | return in_class_p (reg, cl, NULL); | |
1795 | } | |
1796 | ||
3c954213 VM |
1797 | /* Return true if SET of RCLASS contains no hard regs which can be |
1798 | used in MODE. */ | |
1799 | static bool | |
1800 | prohibited_class_reg_set_mode_p (enum reg_class rclass, | |
1801 | HARD_REG_SET &set, | |
1802 | enum machine_mode mode) | |
1803 | { | |
1804 | HARD_REG_SET temp; | |
1805 | ||
c07ad89a | 1806 | lra_assert (hard_reg_set_subset_p (reg_class_contents[rclass], set)); |
3c954213 VM |
1807 | COPY_HARD_REG_SET (temp, set); |
1808 | AND_COMPL_HARD_REG_SET (temp, lra_no_alloc_regs); | |
1809 | return (hard_reg_set_subset_p | |
1810 | (temp, ira_prohibited_class_mode_regs[rclass][mode])); | |
1811 | } | |
1812 | ||
55a2c322 VM |
1813 | /* Major function to choose the current insn alternative and what |
1814 | operands should be reloaded and how. If ONLY_ALTERNATIVE is not | |
1815 | negative we should consider only this alternative. Return false if | |
1816 | we can not choose the alternative or find how to reload the | |
1817 | operands. */ | |
1818 | static bool | |
1819 | process_alt_operands (int only_alternative) | |
1820 | { | |
1821 | bool ok_p = false; | |
36ff9dfb | 1822 | int nop, overall, nalt; |
55a2c322 VM |
1823 | int n_alternatives = curr_static_id->n_alternatives; |
1824 | int n_operands = curr_static_id->n_operands; | |
1825 | /* LOSERS counts the operands that don't fit this alternative and | |
1826 | would require loading. */ | |
1827 | int losers; | |
1828 | /* REJECT is a count of how undesirable this alternative says it is | |
1829 | if any reloading is required. If the alternative matches exactly | |
1830 | then REJECT is ignored, but otherwise it gets this much counted | |
1831 | against it in addition to the reloading needed. */ | |
1832 | int reject; | |
d1457701 | 1833 | int op_reject; |
55a2c322 VM |
1834 | /* The number of elements in the following array. */ |
1835 | int early_clobbered_regs_num; | |
1836 | /* Numbers of operands which are early clobber registers. */ | |
1837 | int early_clobbered_nops[MAX_RECOG_OPERANDS]; | |
1838 | enum reg_class curr_alt[MAX_RECOG_OPERANDS]; | |
1839 | HARD_REG_SET curr_alt_set[MAX_RECOG_OPERANDS]; | |
1840 | bool curr_alt_match_win[MAX_RECOG_OPERANDS]; | |
1841 | bool curr_alt_win[MAX_RECOG_OPERANDS]; | |
1842 | bool curr_alt_offmemok[MAX_RECOG_OPERANDS]; | |
1843 | int curr_alt_matches[MAX_RECOG_OPERANDS]; | |
1844 | /* The number of elements in the following array. */ | |
1845 | int curr_alt_dont_inherit_ops_num; | |
1846 | /* Numbers of operands whose reload pseudos should not be inherited. */ | |
1847 | int curr_alt_dont_inherit_ops[MAX_RECOG_OPERANDS]; | |
1848 | rtx op; | |
1849 | /* The register when the operand is a subreg of register, otherwise the | |
1850 | operand itself. */ | |
1851 | rtx no_subreg_reg_operand[MAX_RECOG_OPERANDS]; | |
1852 | /* The register if the operand is a register or subreg of register, | |
1853 | otherwise NULL. */ | |
1854 | rtx operand_reg[MAX_RECOG_OPERANDS]; | |
1855 | int hard_regno[MAX_RECOG_OPERANDS]; | |
ef4bddc2 | 1856 | machine_mode biggest_mode[MAX_RECOG_OPERANDS]; |
55a2c322 VM |
1857 | int reload_nregs, reload_sum; |
1858 | bool costly_p; | |
1859 | enum reg_class cl; | |
1860 | ||
1861 | /* Calculate some data common for all alternatives to speed up the | |
1862 | function. */ | |
1863 | for (nop = 0; nop < n_operands; nop++) | |
1864 | { | |
7214306b VM |
1865 | rtx reg; |
1866 | ||
55a2c322 VM |
1867 | op = no_subreg_reg_operand[nop] = *curr_id->operand_loc[nop]; |
1868 | /* The real hard regno of the operand after the allocation. */ | |
1686923c | 1869 | hard_regno[nop] = get_hard_regno (op, true); |
f4eafc30 | 1870 | |
7214306b VM |
1871 | operand_reg[nop] = reg = op; |
1872 | biggest_mode[nop] = GET_MODE (op); | |
1873 | if (GET_CODE (op) == SUBREG) | |
55a2c322 | 1874 | { |
7214306b | 1875 | operand_reg[nop] = reg = SUBREG_REG (op); |
55a2c322 | 1876 | if (GET_MODE_SIZE (biggest_mode[nop]) |
7214306b VM |
1877 | < GET_MODE_SIZE (GET_MODE (reg))) |
1878 | biggest_mode[nop] = GET_MODE (reg); | |
55a2c322 | 1879 | } |
7214306b | 1880 | if (! REG_P (reg)) |
55a2c322 | 1881 | operand_reg[nop] = NULL_RTX; |
7214306b VM |
1882 | else if (REGNO (reg) >= FIRST_PSEUDO_REGISTER |
1883 | || ((int) REGNO (reg) | |
1884 | == lra_get_elimination_hard_regno (REGNO (reg)))) | |
1885 | no_subreg_reg_operand[nop] = reg; | |
1886 | else | |
1887 | operand_reg[nop] = no_subreg_reg_operand[nop] | |
1888 | /* Just use natural mode for elimination result. It should | |
1889 | be enough for extra constraints hooks. */ | |
1890 | = regno_reg_rtx[hard_regno[nop]]; | |
55a2c322 VM |
1891 | } |
1892 | ||
1893 | /* The constraints are made of several alternatives. Each operand's | |
1894 | constraint looks like foo,bar,... with commas separating the | |
1895 | alternatives. The first alternatives for all operands go | |
1896 | together, the second alternatives go together, etc. | |
1897 | ||
1898 | First loop over alternatives. */ | |
9840b2fa | 1899 | alternative_mask preferred = curr_id->preferred_alternatives; |
4cc8d9d2 | 1900 | if (only_alternative >= 0) |
9840b2fa | 1901 | preferred &= ALTERNATIVE_BIT (only_alternative); |
4cc8d9d2 | 1902 | |
55a2c322 VM |
1903 | for (nalt = 0; nalt < n_alternatives; nalt++) |
1904 | { | |
1905 | /* Loop over operands for one constraint alternative. */ | |
9840b2fa | 1906 | if (!TEST_BIT (preferred, nalt)) |
55a2c322 VM |
1907 | continue; |
1908 | ||
1909 | overall = losers = reject = reload_nregs = reload_sum = 0; | |
1910 | for (nop = 0; nop < n_operands; nop++) | |
cb1cca12 VM |
1911 | { |
1912 | int inc = (curr_static_id | |
1913 | ->operand_alternative[nalt * n_operands + nop].reject); | |
1914 | if (lra_dump_file != NULL && inc != 0) | |
1915 | fprintf (lra_dump_file, | |
1916 | " Staticly defined alt reject+=%d\n", inc); | |
1917 | reject += inc; | |
1918 | } | |
55a2c322 VM |
1919 | early_clobbered_regs_num = 0; |
1920 | ||
1921 | for (nop = 0; nop < n_operands; nop++) | |
1922 | { | |
1923 | const char *p; | |
1924 | char *end; | |
1925 | int len, c, m, i, opalt_num, this_alternative_matches; | |
1926 | bool win, did_match, offmemok, early_clobber_p; | |
1927 | /* false => this operand can be reloaded somehow for this | |
1928 | alternative. */ | |
1929 | bool badop; | |
1930 | /* true => this operand can be reloaded if the alternative | |
1931 | allows regs. */ | |
1932 | bool winreg; | |
1933 | /* True if a constant forced into memory would be OK for | |
1934 | this operand. */ | |
1935 | bool constmemok; | |
1936 | enum reg_class this_alternative, this_costly_alternative; | |
1937 | HARD_REG_SET this_alternative_set, this_costly_alternative_set; | |
1938 | bool this_alternative_match_win, this_alternative_win; | |
1939 | bool this_alternative_offmemok; | |
80f466c4 | 1940 | bool scratch_p; |
ef4bddc2 | 1941 | machine_mode mode; |
777e635f | 1942 | enum constraint_num cn; |
55a2c322 VM |
1943 | |
1944 | opalt_num = nalt * n_operands + nop; | |
1945 | if (curr_static_id->operand_alternative[opalt_num].anything_ok) | |
1946 | { | |
1947 | /* Fast track for no constraints at all. */ | |
1948 | curr_alt[nop] = NO_REGS; | |
1949 | CLEAR_HARD_REG_SET (curr_alt_set[nop]); | |
1950 | curr_alt_win[nop] = true; | |
1951 | curr_alt_match_win[nop] = false; | |
1952 | curr_alt_offmemok[nop] = false; | |
1953 | curr_alt_matches[nop] = -1; | |
1954 | continue; | |
1955 | } | |
f4eafc30 | 1956 | |
55a2c322 VM |
1957 | op = no_subreg_reg_operand[nop]; |
1958 | mode = curr_operand_mode[nop]; | |
1959 | ||
1960 | win = did_match = winreg = offmemok = constmemok = false; | |
1961 | badop = true; | |
f4eafc30 | 1962 | |
55a2c322 VM |
1963 | early_clobber_p = false; |
1964 | p = curr_static_id->operand_alternative[opalt_num].constraint; | |
f4eafc30 | 1965 | |
55a2c322 VM |
1966 | this_costly_alternative = this_alternative = NO_REGS; |
1967 | /* We update set of possible hard regs besides its class | |
1968 | because reg class might be inaccurate. For example, | |
1969 | union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM | |
1970 | is translated in HI_REGS because classes are merged by | |
1971 | pairs and there is no accurate intermediate class. */ | |
1972 | CLEAR_HARD_REG_SET (this_alternative_set); | |
1973 | CLEAR_HARD_REG_SET (this_costly_alternative_set); | |
1974 | this_alternative_win = false; | |
1975 | this_alternative_match_win = false; | |
1976 | this_alternative_offmemok = false; | |
1977 | this_alternative_matches = -1; | |
f4eafc30 | 1978 | |
55a2c322 VM |
1979 | /* An empty constraint should be excluded by the fast |
1980 | track. */ | |
1981 | lra_assert (*p != 0 && *p != ','); | |
f4eafc30 | 1982 | |
d1457701 | 1983 | op_reject = 0; |
55a2c322 VM |
1984 | /* Scan this alternative's specs for this operand; set WIN |
1985 | if the operand fits any letter in this alternative. | |
1986 | Otherwise, clear BADOP if this operand could fit some | |
1987 | letter after reloads, or set WINREG if this operand could | |
1988 | fit after reloads provided the constraint allows some | |
1989 | registers. */ | |
1990 | costly_p = false; | |
1991 | do | |
1992 | { | |
1993 | switch ((c = *p, len = CONSTRAINT_LEN (c, p)), c) | |
1994 | { | |
1995 | case '\0': | |
1996 | len = 0; | |
1997 | break; | |
1998 | case ',': | |
1999 | c = '\0'; | |
2000 | break; | |
f4eafc30 | 2001 | |
55a2c322 VM |
2002 | case '&': |
2003 | early_clobber_p = true; | |
2004 | break; | |
f4eafc30 | 2005 | |
d1457701 VM |
2006 | case '$': |
2007 | op_reject += LRA_MAX_REJECT; | |
2008 | break; | |
2009 | case '^': | |
2010 | op_reject += LRA_LOSER_COST_FACTOR; | |
2011 | break; | |
2012 | ||
55a2c322 VM |
2013 | case '#': |
2014 | /* Ignore rest of this alternative. */ | |
2015 | c = '\0'; | |
2016 | break; | |
f4eafc30 | 2017 | |
55a2c322 VM |
2018 | case '0': case '1': case '2': case '3': case '4': |
2019 | case '5': case '6': case '7': case '8': case '9': | |
2020 | { | |
2021 | int m_hregno; | |
2022 | bool match_p; | |
f4eafc30 | 2023 | |
55a2c322 VM |
2024 | m = strtoul (p, &end, 10); |
2025 | p = end; | |
2026 | len = 0; | |
2027 | lra_assert (nop > m); | |
f4eafc30 | 2028 | |
55a2c322 | 2029 | this_alternative_matches = m; |
1686923c | 2030 | m_hregno = get_hard_regno (*curr_id->operand_loc[m], false); |
55a2c322 VM |
2031 | /* We are supposed to match a previous operand. |
2032 | If we do, we win if that one did. If we do | |
2033 | not, count both of the operands as losers. | |
2034 | (This is too conservative, since most of the | |
2035 | time only a single reload insn will be needed | |
2036 | to make the two operands win. As a result, | |
2037 | this alternative may be rejected when it is | |
2038 | actually desirable.) */ | |
2039 | match_p = false; | |
2040 | if (operands_match_p (*curr_id->operand_loc[nop], | |
2041 | *curr_id->operand_loc[m], m_hregno)) | |
2042 | { | |
2043 | /* We should reject matching of an early | |
2044 | clobber operand if the matching operand is | |
2045 | not dying in the insn. */ | |
2046 | if (! curr_static_id->operand[m].early_clobber | |
2047 | || operand_reg[nop] == NULL_RTX | |
2048 | || (find_regno_note (curr_insn, REG_DEAD, | |
1c86bd80 VM |
2049 | REGNO (op)) |
2050 | || REGNO (op) == REGNO (operand_reg[m]))) | |
55a2c322 VM |
2051 | match_p = true; |
2052 | } | |
2053 | if (match_p) | |
2054 | { | |
2055 | /* If we are matching a non-offsettable | |
2056 | address where an offsettable address was | |
2057 | expected, then we must reject this | |
2058 | combination, because we can't reload | |
2059 | it. */ | |
2060 | if (curr_alt_offmemok[m] | |
2061 | && MEM_P (*curr_id->operand_loc[m]) | |
2062 | && curr_alt[m] == NO_REGS && ! curr_alt_win[m]) | |
2063 | continue; | |
55a2c322 VM |
2064 | } |
2065 | else | |
2066 | { | |
2067 | /* Operands don't match. Both operands must | |
2068 | allow a reload register, otherwise we | |
2069 | cannot make them match. */ | |
2070 | if (curr_alt[m] == NO_REGS) | |
2071 | break; | |
2072 | /* Retroactively mark the operand we had to | |
2073 | match as a loser, if it wasn't already and | |
2074 | it wasn't matched to a register constraint | |
2075 | (e.g it might be matched by memory). */ | |
2076 | if (curr_alt_win[m] | |
2077 | && (operand_reg[m] == NULL_RTX | |
2078 | || hard_regno[m] < 0)) | |
2079 | { | |
2080 | losers++; | |
2081 | reload_nregs | |
2082 | += (ira_reg_class_max_nregs[curr_alt[m]] | |
2083 | [GET_MODE (*curr_id->operand_loc[m])]); | |
2084 | } | |
f4eafc30 | 2085 | |
f4581282 VM |
2086 | /* Prefer matching earlyclobber alternative as |
2087 | it results in less hard regs required for | |
2088 | the insn than a non-matching earlyclobber | |
2089 | alternative. */ | |
2090 | if (curr_static_id->operand[m].early_clobber) | |
2091 | { | |
2092 | if (lra_dump_file != NULL) | |
2093 | fprintf | |
2094 | (lra_dump_file, | |
2095 | " %d Matching earlyclobber alt:" | |
2096 | " reject--\n", | |
2097 | nop); | |
2098 | reject--; | |
2099 | } | |
2100 | /* Otherwise we prefer no matching | |
2101 | alternatives because it gives more freedom | |
2102 | in RA. */ | |
2103 | else if (operand_reg[nop] == NULL_RTX | |
2104 | || (find_regno_note (curr_insn, REG_DEAD, | |
2105 | REGNO (operand_reg[nop])) | |
2106 | == NULL_RTX)) | |
cb1cca12 VM |
2107 | { |
2108 | if (lra_dump_file != NULL) | |
2109 | fprintf | |
2110 | (lra_dump_file, | |
2111 | " %d Matching alt: reject+=2\n", | |
2112 | nop); | |
2113 | reject += 2; | |
2114 | } | |
55a2c322 VM |
2115 | } |
2116 | /* If we have to reload this operand and some | |
2117 | previous operand also had to match the same | |
2118 | thing as this operand, we don't know how to do | |
2119 | that. */ | |
2120 | if (!match_p || !curr_alt_win[m]) | |
2121 | { | |
2122 | for (i = 0; i < nop; i++) | |
2123 | if (curr_alt_matches[i] == m) | |
2124 | break; | |
2125 | if (i < nop) | |
2126 | break; | |
2127 | } | |
2128 | else | |
2129 | did_match = true; | |
f4eafc30 | 2130 | |
55a2c322 VM |
2131 | /* This can be fixed with reloads if the operand |
2132 | we are supposed to match can be fixed with | |
2133 | reloads. */ | |
2134 | badop = false; | |
2135 | this_alternative = curr_alt[m]; | |
2136 | COPY_HARD_REG_SET (this_alternative_set, curr_alt_set[m]); | |
821b7577 | 2137 | winreg = this_alternative != NO_REGS; |
55a2c322 VM |
2138 | break; |
2139 | } | |
f4eafc30 | 2140 | |
55a2c322 VM |
2141 | case 'g': |
2142 | if (MEM_P (op) | |
2143 | || general_constant_p (op) | |
2144 | || spilled_pseudo_p (op)) | |
2145 | win = true; | |
777e635f | 2146 | cl = GENERAL_REGS; |
55a2c322 | 2147 | goto reg; |
f4eafc30 | 2148 | |
55a2c322 | 2149 | default: |
777e635f RS |
2150 | cn = lookup_constraint (p); |
2151 | switch (get_constraint_type (cn)) | |
55a2c322 | 2152 | { |
777e635f RS |
2153 | case CT_REGISTER: |
2154 | cl = reg_class_for_constraint (cn); | |
2155 | if (cl != NO_REGS) | |
2156 | goto reg; | |
2157 | break; | |
f4eafc30 | 2158 | |
d9c35eee RS |
2159 | case CT_CONST_INT: |
2160 | if (CONST_INT_P (op) | |
2161 | && insn_const_int_ok_for_constraint (INTVAL (op), cn)) | |
2162 | win = true; | |
2163 | break; | |
2164 | ||
777e635f RS |
2165 | case CT_MEMORY: |
2166 | if (MEM_P (op) | |
2167 | && satisfies_memory_constraint_p (op, cn)) | |
2168 | win = true; | |
2169 | else if (spilled_pseudo_p (op)) | |
2170 | win = true; | |
2171 | ||
2172 | /* If we didn't already win, we can reload constants | |
2173 | via force_const_mem or put the pseudo value into | |
2174 | memory, or make other memory by reloading the | |
2175 | address like for 'o'. */ | |
2176 | if (CONST_POOL_OK_P (mode, op) | |
987b67f1 VM |
2177 | || MEM_P (op) || REG_P (op) |
2178 | /* We can restore the equiv insn by a | |
2179 | reload. */ | |
2180 | || equiv_substition_p[nop]) | |
777e635f RS |
2181 | badop = false; |
2182 | constmemok = true; | |
2183 | offmemok = true; | |
2184 | break; | |
2185 | ||
2186 | case CT_ADDRESS: | |
2187 | /* If we didn't already win, we can reload the address | |
2188 | into a base register. */ | |
2189 | if (satisfies_address_constraint_p (op, cn)) | |
2190 | win = true; | |
2191 | cl = base_reg_class (VOIDmode, ADDR_SPACE_GENERIC, | |
2192 | ADDRESS, SCRATCH); | |
2193 | badop = false; | |
2194 | goto reg; | |
2195 | ||
2196 | case CT_FIXED_FORM: | |
2197 | if (constraint_satisfied_p (op, cn)) | |
55a2c322 | 2198 | win = true; |
55a2c322 | 2199 | break; |
9eb1ca69 VM |
2200 | |
2201 | case CT_SPECIAL_MEMORY: | |
2202 | if (MEM_P (op) | |
2203 | && satisfies_memory_constraint_p (op, cn)) | |
2204 | win = true; | |
2205 | else if (spilled_pseudo_p (op)) | |
2206 | win = true; | |
2207 | break; | |
55a2c322 | 2208 | } |
777e635f | 2209 | break; |
f4eafc30 | 2210 | |
777e635f | 2211 | reg: |
55a2c322 VM |
2212 | this_alternative = reg_class_subunion[this_alternative][cl]; |
2213 | IOR_HARD_REG_SET (this_alternative_set, | |
2214 | reg_class_contents[cl]); | |
2215 | if (costly_p) | |
2216 | { | |
2217 | this_costly_alternative | |
2218 | = reg_class_subunion[this_costly_alternative][cl]; | |
2219 | IOR_HARD_REG_SET (this_costly_alternative_set, | |
2220 | reg_class_contents[cl]); | |
2221 | } | |
55a2c322 VM |
2222 | if (mode == BLKmode) |
2223 | break; | |
2224 | winreg = true; | |
2225 | if (REG_P (op)) | |
2226 | { | |
2227 | if (hard_regno[nop] >= 0 | |
2228 | && in_hard_reg_set_p (this_alternative_set, | |
2229 | mode, hard_regno[nop])) | |
2230 | win = true; | |
2231 | else if (hard_regno[nop] < 0 | |
2232 | && in_class_p (op, this_alternative, NULL)) | |
2233 | win = true; | |
2234 | } | |
2235 | break; | |
2236 | } | |
2237 | if (c != ' ' && c != '\t') | |
2238 | costly_p = c == '*'; | |
2239 | } | |
2240 | while ((p += len), c); | |
f4eafc30 | 2241 | |
80f466c4 VM |
2242 | scratch_p = (operand_reg[nop] != NULL_RTX |
2243 | && lra_former_scratch_p (REGNO (operand_reg[nop]))); | |
55a2c322 VM |
2244 | /* Record which operands fit this alternative. */ |
2245 | if (win) | |
2246 | { | |
2247 | this_alternative_win = true; | |
2248 | if (operand_reg[nop] != NULL_RTX) | |
2249 | { | |
2250 | if (hard_regno[nop] >= 0) | |
2251 | { | |
2252 | if (in_hard_reg_set_p (this_costly_alternative_set, | |
2253 | mode, hard_regno[nop])) | |
cb1cca12 VM |
2254 | { |
2255 | if (lra_dump_file != NULL) | |
2256 | fprintf (lra_dump_file, | |
2257 | " %d Costly set: reject++\n", | |
2258 | nop); | |
2259 | reject++; | |
2260 | } | |
55a2c322 VM |
2261 | } |
2262 | else | |
2263 | { | |
80f466c4 VM |
2264 | /* Prefer won reg to spilled pseudo under other |
2265 | equal conditions for possibe inheritance. */ | |
2266 | if (! scratch_p) | |
2267 | { | |
2268 | if (lra_dump_file != NULL) | |
2269 | fprintf | |
2270 | (lra_dump_file, | |
2271 | " %d Non pseudo reload: reject++\n", | |
2272 | nop); | |
2273 | reject++; | |
2274 | } | |
55a2c322 VM |
2275 | if (in_class_p (operand_reg[nop], |
2276 | this_costly_alternative, NULL)) | |
cb1cca12 VM |
2277 | { |
2278 | if (lra_dump_file != NULL) | |
2279 | fprintf | |
2280 | (lra_dump_file, | |
2281 | " %d Non pseudo costly reload:" | |
2282 | " reject++\n", | |
2283 | nop); | |
2284 | reject++; | |
2285 | } | |
55a2c322 | 2286 | } |
9c582551 | 2287 | /* We simulate the behavior of old reload here. |
55a2c322 VM |
2288 | Although scratches need hard registers and it |
2289 | might result in spilling other pseudos, no reload | |
2290 | insns are generated for the scratches. So it | |
2291 | might cost something but probably less than old | |
2292 | reload pass believes. */ | |
80f466c4 | 2293 | if (scratch_p) |
cb1cca12 VM |
2294 | { |
2295 | if (lra_dump_file != NULL) | |
2296 | fprintf (lra_dump_file, | |
80f466c4 | 2297 | " %d Scratch win: reject+=2\n", |
cb1cca12 | 2298 | nop); |
80f466c4 | 2299 | reject += 2; |
cb1cca12 | 2300 | } |
55a2c322 VM |
2301 | } |
2302 | } | |
2303 | else if (did_match) | |
2304 | this_alternative_match_win = true; | |
2305 | else | |
2306 | { | |
2307 | int const_to_mem = 0; | |
2308 | bool no_regs_p; | |
2309 | ||
d1457701 | 2310 | reject += op_reject; |
8d49e7ef VM |
2311 | /* Never do output reload of stack pointer. It makes |
2312 | impossible to do elimination when SP is changed in | |
2313 | RTL. */ | |
2314 | if (op == stack_pointer_rtx && ! frame_pointer_needed | |
2315 | && curr_static_id->operand[nop].type != OP_IN) | |
2316 | goto fail; | |
2317 | ||
e86c0101 SB |
2318 | /* If this alternative asks for a specific reg class, see if there |
2319 | is at least one allocatable register in that class. */ | |
55a2c322 VM |
2320 | no_regs_p |
2321 | = (this_alternative == NO_REGS | |
2322 | || (hard_reg_set_subset_p | |
2323 | (reg_class_contents[this_alternative], | |
2324 | lra_no_alloc_regs))); | |
e86c0101 SB |
2325 | |
2326 | /* For asms, verify that the class for this alternative is possible | |
2327 | for the mode that is specified. */ | |
ecee672b | 2328 | if (!no_regs_p && INSN_CODE (curr_insn) < 0) |
e86c0101 SB |
2329 | { |
2330 | int i; | |
2331 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
2332 | if (HARD_REGNO_MODE_OK (i, mode) | |
8f21260c VM |
2333 | && in_hard_reg_set_p (reg_class_contents[this_alternative], |
2334 | mode, i)) | |
e86c0101 SB |
2335 | break; |
2336 | if (i == FIRST_PSEUDO_REGISTER) | |
2337 | winreg = false; | |
2338 | } | |
2339 | ||
55a2c322 VM |
2340 | /* If this operand accepts a register, and if the |
2341 | register class has at least one allocatable register, | |
2342 | then this operand can be reloaded. */ | |
2343 | if (winreg && !no_regs_p) | |
2344 | badop = false; | |
f4eafc30 | 2345 | |
55a2c322 | 2346 | if (badop) |
8f21260c VM |
2347 | { |
2348 | if (lra_dump_file != NULL) | |
2349 | fprintf (lra_dump_file, | |
2350 | " alt=%d: Bad operand -- refuse\n", | |
2351 | nalt); | |
2352 | goto fail; | |
2353 | } | |
55a2c322 | 2354 | |
d13835b6 VM |
2355 | if (this_alternative != NO_REGS) |
2356 | { | |
2357 | HARD_REG_SET available_regs; | |
2358 | ||
2359 | COPY_HARD_REG_SET (available_regs, | |
2360 | reg_class_contents[this_alternative]); | |
2361 | AND_COMPL_HARD_REG_SET | |
2362 | (available_regs, | |
2363 | ira_prohibited_class_mode_regs[this_alternative][mode]); | |
2364 | AND_COMPL_HARD_REG_SET (available_regs, lra_no_alloc_regs); | |
2365 | if (hard_reg_set_empty_p (available_regs)) | |
2366 | { | |
2367 | /* There are no hard regs holding a value of given | |
2368 | mode. */ | |
2369 | if (offmemok) | |
2370 | { | |
2371 | this_alternative = NO_REGS; | |
2372 | if (lra_dump_file != NULL) | |
2373 | fprintf (lra_dump_file, | |
2374 | " %d Using memory because of" | |
2375 | " a bad mode: reject+=2\n", | |
2376 | nop); | |
2377 | reject += 2; | |
2378 | } | |
2379 | else | |
2380 | { | |
2381 | if (lra_dump_file != NULL) | |
2382 | fprintf (lra_dump_file, | |
2383 | " alt=%d: Wrong mode -- refuse\n", | |
2384 | nalt); | |
2385 | goto fail; | |
2386 | } | |
2387 | } | |
2388 | } | |
2389 | ||
2ae577fd VM |
2390 | /* If not assigned pseudo has a class which a subset of |
2391 | required reg class, it is a less costly alternative | |
2392 | as the pseudo still can get a hard reg of necessary | |
2393 | class. */ | |
2394 | if (! no_regs_p && REG_P (op) && hard_regno[nop] < 0 | |
2395 | && (cl = get_reg_class (REGNO (op))) != NO_REGS | |
2396 | && ira_class_subset_p[this_alternative][cl]) | |
2397 | { | |
2398 | if (lra_dump_file != NULL) | |
2399 | fprintf | |
2400 | (lra_dump_file, | |
2401 | " %d Super set class reg: reject-=3\n", nop); | |
2402 | reject -= 3; | |
2403 | } | |
2404 | ||
55a2c322 VM |
2405 | this_alternative_offmemok = offmemok; |
2406 | if (this_costly_alternative != NO_REGS) | |
cb1cca12 VM |
2407 | { |
2408 | if (lra_dump_file != NULL) | |
2409 | fprintf (lra_dump_file, | |
2410 | " %d Costly loser: reject++\n", nop); | |
2411 | reject++; | |
2412 | } | |
55a2c322 VM |
2413 | /* If the operand is dying, has a matching constraint, |
2414 | and satisfies constraints of the matched operand | |
f4581282 | 2415 | which failed to satisfy the own constraints, most probably |
a9711f36 VM |
2416 | the reload for this operand will be gone. */ |
2417 | if (this_alternative_matches >= 0 | |
2418 | && !curr_alt_win[this_alternative_matches] | |
2419 | && REG_P (op) | |
2420 | && find_regno_note (curr_insn, REG_DEAD, REGNO (op)) | |
2421 | && (hard_regno[nop] >= 0 | |
2422 | ? in_hard_reg_set_p (this_alternative_set, | |
2423 | mode, hard_regno[nop]) | |
2424 | : in_class_p (op, this_alternative, NULL))) | |
2425 | { | |
2426 | if (lra_dump_file != NULL) | |
2427 | fprintf | |
2428 | (lra_dump_file, | |
2429 | " %d Dying matched operand reload: reject++\n", | |
2430 | nop); | |
2431 | reject++; | |
2432 | } | |
2433 | else | |
027ece11 | 2434 | { |
5306401f VM |
2435 | /* Strict_low_part requires to reload the register |
2436 | not the sub-register. In this case we should | |
2437 | check that a final reload hard reg can hold the | |
2438 | value mode. */ | |
027ece11 VM |
2439 | if (curr_static_id->operand[nop].strict_low |
2440 | && REG_P (op) | |
2441 | && hard_regno[nop] < 0 | |
2442 | && GET_CODE (*curr_id->operand_loc[nop]) == SUBREG | |
2443 | && ira_class_hard_regs_num[this_alternative] > 0 | |
2444 | && ! HARD_REGNO_MODE_OK (ira_class_hard_regs | |
2445 | [this_alternative][0], | |
00b7527b VM |
2446 | GET_MODE |
2447 | (*curr_id->operand_loc[nop]))) | |
8f21260c VM |
2448 | { |
2449 | if (lra_dump_file != NULL) | |
2450 | fprintf | |
2451 | (lra_dump_file, | |
2452 | " alt=%d: Strict low subreg reload -- refuse\n", | |
2453 | nalt); | |
2454 | goto fail; | |
2455 | } | |
027ece11 VM |
2456 | losers++; |
2457 | } | |
55a2c322 VM |
2458 | if (operand_reg[nop] != NULL_RTX |
2459 | /* Output operands and matched input operands are | |
2460 | not inherited. The following conditions do not | |
2461 | exactly describe the previous statement but they | |
2462 | are pretty close. */ | |
2463 | && curr_static_id->operand[nop].type != OP_OUT | |
2464 | && (this_alternative_matches < 0 | |
2465 | || curr_static_id->operand[nop].type != OP_IN)) | |
2466 | { | |
2467 | int last_reload = (lra_reg_info[ORIGINAL_REGNO | |
2468 | (operand_reg[nop])] | |
2469 | .last_reload); | |
2470 | ||
6334f3e9 VM |
2471 | /* The value of reload_sum has sense only if we |
2472 | process insns in their order. It happens only on | |
2473 | the first constraints sub-pass when we do most of | |
2474 | reload work. */ | |
2475 | if (lra_constraint_iter == 1 && last_reload > bb_reload_num) | |
55a2c322 VM |
2476 | reload_sum += last_reload - bb_reload_num; |
2477 | } | |
2478 | /* If this is a constant that is reloaded into the | |
2479 | desired class by copying it to memory first, count | |
2480 | that as another reload. This is consistent with | |
2481 | other code and is required to avoid choosing another | |
2482 | alternative when the constant is moved into memory. | |
2483 | Note that the test here is precisely the same as in | |
2484 | the code below that calls force_const_mem. */ | |
2485 | if (CONST_POOL_OK_P (mode, op) | |
2486 | && ((targetm.preferred_reload_class | |
2487 | (op, this_alternative) == NO_REGS) | |
2488 | || no_input_reloads_p)) | |
2489 | { | |
2490 | const_to_mem = 1; | |
2491 | if (! no_regs_p) | |
2492 | losers++; | |
2493 | } | |
f4eafc30 | 2494 | |
55a2c322 VM |
2495 | /* Alternative loses if it requires a type of reload not |
2496 | permitted for this insn. We can always reload | |
2497 | objects with a REG_UNUSED note. */ | |
2498 | if ((curr_static_id->operand[nop].type != OP_IN | |
2499 | && no_output_reloads_p | |
2500 | && ! find_reg_note (curr_insn, REG_UNUSED, op)) | |
2501 | || (curr_static_id->operand[nop].type != OP_OUT | |
8f21260c VM |
2502 | && no_input_reloads_p && ! const_to_mem) |
2503 | || (this_alternative_matches >= 0 | |
9102dadd VM |
2504 | && (no_input_reloads_p |
2505 | || (no_output_reloads_p | |
2506 | && (curr_static_id->operand | |
2507 | [this_alternative_matches].type != OP_IN) | |
2508 | && ! find_reg_note (curr_insn, REG_UNUSED, | |
2509 | no_subreg_reg_operand | |
2510 | [this_alternative_matches]))))) | |
8f21260c VM |
2511 | { |
2512 | if (lra_dump_file != NULL) | |
2513 | fprintf | |
2514 | (lra_dump_file, | |
2515 | " alt=%d: No input/otput reload -- refuse\n", | |
2516 | nalt); | |
2517 | goto fail; | |
2518 | } | |
f4eafc30 | 2519 | |
f66af4aa VM |
2520 | /* Alternative loses if it required class pseudo can not |
2521 | hold value of required mode. Such insns can be | |
7b6e0c54 | 2522 | described by insn definitions with mode iterators. */ |
f66af4aa VM |
2523 | if (GET_MODE (*curr_id->operand_loc[nop]) != VOIDmode |
2524 | && ! hard_reg_set_empty_p (this_alternative_set) | |
7b6e0c54 VM |
2525 | /* It is common practice for constraints to use a |
2526 | class which does not have actually enough regs to | |
2527 | hold the value (e.g. x86 AREG for mode requiring | |
2528 | more one general reg). Therefore we have 2 | |
2529 | conditions to check that the reload pseudo can | |
2530 | not hold the mode value. */ | |
f66af4aa VM |
2531 | && ! HARD_REGNO_MODE_OK (ira_class_hard_regs |
2532 | [this_alternative][0], | |
3c954213 | 2533 | GET_MODE (*curr_id->operand_loc[nop])) |
7b6e0c54 VM |
2534 | /* The above condition is not enough as the first |
2535 | reg in ira_class_hard_regs can be not aligned for | |
2536 | multi-words mode values. */ | |
3c954213 VM |
2537 | && (prohibited_class_reg_set_mode_p |
2538 | (this_alternative, this_alternative_set, | |
2539 | GET_MODE (*curr_id->operand_loc[nop])))) | |
2540 | { | |
2541 | if (lra_dump_file != NULL) | |
2542 | fprintf (lra_dump_file, | |
2543 | " alt=%d: reload pseudo for op %d " | |
2544 | " can not hold the mode value -- refuse\n", | |
2545 | nalt, nop); | |
2546 | goto fail; | |
f66af4aa VM |
2547 | } |
2548 | ||
821b7577 VM |
2549 | /* Check strong discouragement of reload of non-constant |
2550 | into class THIS_ALTERNATIVE. */ | |
2551 | if (! CONSTANT_P (op) && ! no_regs_p | |
2552 | && (targetm.preferred_reload_class | |
2553 | (op, this_alternative) == NO_REGS | |
2554 | || (curr_static_id->operand[nop].type == OP_OUT | |
2555 | && (targetm.preferred_output_reload_class | |
2556 | (op, this_alternative) == NO_REGS)))) | |
cb1cca12 VM |
2557 | { |
2558 | if (lra_dump_file != NULL) | |
2559 | fprintf (lra_dump_file, | |
2560 | " %d Non-prefered reload: reject+=%d\n", | |
2561 | nop, LRA_MAX_REJECT); | |
2562 | reject += LRA_MAX_REJECT; | |
2563 | } | |
f4eafc30 | 2564 | |
ed52a84e VM |
2565 | if (! (MEM_P (op) && offmemok) |
2566 | && ! (const_to_mem && constmemok)) | |
55a2c322 VM |
2567 | { |
2568 | /* We prefer to reload pseudos over reloading other | |
2569 | things, since such reloads may be able to be | |
2570 | eliminated later. So bump REJECT in other cases. | |
2571 | Don't do this in the case where we are forcing a | |
2572 | constant into memory and it will then win since | |
2573 | we don't want to have a different alternative | |
2574 | match then. */ | |
2575 | if (! (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER)) | |
cb1cca12 VM |
2576 | { |
2577 | if (lra_dump_file != NULL) | |
2578 | fprintf | |
2579 | (lra_dump_file, | |
2580 | " %d Non-pseudo reload: reject+=2\n", | |
2581 | nop); | |
2582 | reject += 2; | |
2583 | } | |
f4eafc30 | 2584 | |
55a2c322 VM |
2585 | if (! no_regs_p) |
2586 | reload_nregs | |
2587 | += ira_reg_class_max_nregs[this_alternative][mode]; | |
36ff9dfb VM |
2588 | |
2589 | if (SMALL_REGISTER_CLASS_P (this_alternative)) | |
cb1cca12 VM |
2590 | { |
2591 | if (lra_dump_file != NULL) | |
2592 | fprintf | |
2593 | (lra_dump_file, | |
2594 | " %d Small class reload: reject+=%d\n", | |
2595 | nop, LRA_LOSER_COST_FACTOR / 2); | |
2596 | reject += LRA_LOSER_COST_FACTOR / 2; | |
2597 | } | |
55a2c322 VM |
2598 | } |
2599 | ||
1bdc4b11 VM |
2600 | /* We are trying to spill pseudo into memory. It is |
2601 | usually more costly than moving to a hard register | |
2602 | although it might takes the same number of | |
5f225ef4 VM |
2603 | reloads. |
2604 | ||
2605 | Non-pseudo spill may happen also. Suppose a target allows both | |
2606 | register and memory in the operand constraint alternatives, | |
2607 | then it's typical that an eliminable register has a substition | |
2608 | of "base + offset" which can either be reloaded by a simple | |
2609 | "new_reg <= base + offset" which will match the register | |
2610 | constraint, or a similar reg addition followed by further spill | |
2611 | to and reload from memory which will match the memory | |
2612 | constraint, but this memory spill will be much more costly | |
2613 | usually. | |
2614 | ||
2615 | Code below increases the reject for both pseudo and non-pseudo | |
2616 | spill. */ | |
10406801 JW |
2617 | if (no_regs_p |
2618 | && !(MEM_P (op) && offmemok) | |
2619 | && !(REG_P (op) && hard_regno[nop] < 0)) | |
cb1cca12 VM |
2620 | { |
2621 | if (lra_dump_file != NULL) | |
2622 | fprintf | |
2623 | (lra_dump_file, | |
5f225ef4 VM |
2624 | " %d Spill %spseudo into memory: reject+=3\n", |
2625 | nop, REG_P (op) ? "" : "Non-"); | |
cb1cca12 | 2626 | reject += 3; |
7891065a VM |
2627 | if (VECTOR_MODE_P (mode)) |
2628 | { | |
2629 | /* Spilling vectors into memory is usually more | |
2630 | costly as they contain big values. */ | |
2631 | if (lra_dump_file != NULL) | |
2632 | fprintf | |
2633 | (lra_dump_file, | |
2634 | " %d Spill vector pseudo: reject+=2\n", | |
2635 | nop); | |
2636 | reject += 2; | |
2637 | } | |
cb1cca12 | 2638 | } |
1bdc4b11 | 2639 | |
7100b561 UB |
2640 | #ifdef SECONDARY_MEMORY_NEEDED |
2641 | /* If reload requires moving value through secondary | |
2642 | memory, it will need one more insn at least. */ | |
2643 | if (this_alternative != NO_REGS | |
2644 | && REG_P (op) && (cl = get_reg_class (REGNO (op))) != NO_REGS | |
2645 | && ((curr_static_id->operand[nop].type != OP_OUT | |
2646 | && SECONDARY_MEMORY_NEEDED (cl, this_alternative, | |
2647 | GET_MODE (op))) | |
2648 | || (curr_static_id->operand[nop].type != OP_IN | |
2649 | && SECONDARY_MEMORY_NEEDED (this_alternative, cl, | |
2650 | GET_MODE (op))))) | |
2651 | losers++; | |
2652 | #endif | |
55a2c322 VM |
2653 | /* Input reloads can be inherited more often than output |
2654 | reloads can be removed, so penalize output | |
2655 | reloads. */ | |
2656 | if (!REG_P (op) || curr_static_id->operand[nop].type != OP_IN) | |
cb1cca12 VM |
2657 | { |
2658 | if (lra_dump_file != NULL) | |
2659 | fprintf | |
2660 | (lra_dump_file, | |
2661 | " %d Non input pseudo reload: reject++\n", | |
2662 | nop); | |
2663 | reject++; | |
2664 | } | |
55a2c322 | 2665 | } |
f4eafc30 | 2666 | |
80f466c4 | 2667 | if (early_clobber_p && ! scratch_p) |
cb1cca12 VM |
2668 | { |
2669 | if (lra_dump_file != NULL) | |
2670 | fprintf (lra_dump_file, | |
2671 | " %d Early clobber: reject++\n", nop); | |
2672 | reject++; | |
2673 | } | |
55a2c322 VM |
2674 | /* ??? We check early clobbers after processing all operands |
2675 | (see loop below) and there we update the costs more. | |
2676 | Should we update the cost (may be approximately) here | |
2677 | because of early clobber register reloads or it is a rare | |
2678 | or non-important thing to be worth to do it. */ | |
821b7577 | 2679 | overall = losers * LRA_LOSER_COST_FACTOR + reject; |
55a2c322 | 2680 | if ((best_losers == 0 || losers != 0) && best_overall < overall) |
deca73f5 VM |
2681 | { |
2682 | if (lra_dump_file != NULL) | |
2683 | fprintf (lra_dump_file, | |
cb1cca12 | 2684 | " alt=%d,overall=%d,losers=%d -- refuse\n", |
deca73f5 VM |
2685 | nalt, overall, losers); |
2686 | goto fail; | |
2687 | } | |
55a2c322 VM |
2688 | |
2689 | curr_alt[nop] = this_alternative; | |
2690 | COPY_HARD_REG_SET (curr_alt_set[nop], this_alternative_set); | |
2691 | curr_alt_win[nop] = this_alternative_win; | |
2692 | curr_alt_match_win[nop] = this_alternative_match_win; | |
2693 | curr_alt_offmemok[nop] = this_alternative_offmemok; | |
2694 | curr_alt_matches[nop] = this_alternative_matches; | |
f4eafc30 | 2695 | |
55a2c322 VM |
2696 | if (this_alternative_matches >= 0 |
2697 | && !did_match && !this_alternative_win) | |
2698 | curr_alt_win[this_alternative_matches] = false; | |
f4eafc30 | 2699 | |
55a2c322 VM |
2700 | if (early_clobber_p && operand_reg[nop] != NULL_RTX) |
2701 | early_clobbered_nops[early_clobbered_regs_num++] = nop; | |
2702 | } | |
2c62cbaa VM |
2703 | if (curr_insn_set != NULL_RTX && n_operands == 2 |
2704 | /* Prevent processing non-move insns. */ | |
2705 | && (GET_CODE (SET_SRC (curr_insn_set)) == SUBREG | |
2706 | || SET_SRC (curr_insn_set) == no_subreg_reg_operand[1]) | |
2707 | && ((! curr_alt_win[0] && ! curr_alt_win[1] | |
2708 | && REG_P (no_subreg_reg_operand[0]) | |
2709 | && REG_P (no_subreg_reg_operand[1]) | |
2710 | && (reg_in_class_p (no_subreg_reg_operand[0], curr_alt[1]) | |
2711 | || reg_in_class_p (no_subreg_reg_operand[1], curr_alt[0]))) | |
2712 | || (! curr_alt_win[0] && curr_alt_win[1] | |
2713 | && REG_P (no_subreg_reg_operand[1]) | |
2714 | && reg_in_class_p (no_subreg_reg_operand[1], curr_alt[0])) | |
2715 | || (curr_alt_win[0] && ! curr_alt_win[1] | |
2716 | && REG_P (no_subreg_reg_operand[0]) | |
2717 | && reg_in_class_p (no_subreg_reg_operand[0], curr_alt[1]) | |
2718 | && (! CONST_POOL_OK_P (curr_operand_mode[1], | |
2719 | no_subreg_reg_operand[1]) | |
2720 | || (targetm.preferred_reload_class | |
2721 | (no_subreg_reg_operand[1], | |
2722 | (enum reg_class) curr_alt[1]) != NO_REGS)) | |
2723 | /* If it is a result of recent elimination in move | |
2724 | insn we can transform it into an add still by | |
2725 | using this alternative. */ | |
2726 | && GET_CODE (no_subreg_reg_operand[1]) != PLUS))) | |
cb1cca12 VM |
2727 | { |
2728 | /* We have a move insn and a new reload insn will be similar | |
2729 | to the current insn. We should avoid such situation as it | |
2730 | results in LRA cycling. */ | |
2731 | overall += LRA_MAX_REJECT; | |
2732 | } | |
55a2c322 VM |
2733 | ok_p = true; |
2734 | curr_alt_dont_inherit_ops_num = 0; | |
2735 | for (nop = 0; nop < early_clobbered_regs_num; nop++) | |
2736 | { | |
2194f7a2 | 2737 | int i, j, clobbered_hard_regno, first_conflict_j, last_conflict_j; |
55a2c322 VM |
2738 | HARD_REG_SET temp_set; |
2739 | ||
2740 | i = early_clobbered_nops[nop]; | |
2741 | if ((! curr_alt_win[i] && ! curr_alt_match_win[i]) | |
2742 | || hard_regno[i] < 0) | |
2743 | continue; | |
1c86bd80 | 2744 | lra_assert (operand_reg[i] != NULL_RTX); |
55a2c322 VM |
2745 | clobbered_hard_regno = hard_regno[i]; |
2746 | CLEAR_HARD_REG_SET (temp_set); | |
2747 | add_to_hard_reg_set (&temp_set, biggest_mode[i], clobbered_hard_regno); | |
2194f7a2 | 2748 | first_conflict_j = last_conflict_j = -1; |
55a2c322 VM |
2749 | for (j = 0; j < n_operands; j++) |
2750 | if (j == i | |
2751 | /* We don't want process insides of match_operator and | |
2752 | match_parallel because otherwise we would process | |
2753 | their operands once again generating a wrong | |
2754 | code. */ | |
2755 | || curr_static_id->operand[j].is_operator) | |
2756 | continue; | |
2757 | else if ((curr_alt_matches[j] == i && curr_alt_match_win[j]) | |
2758 | || (curr_alt_matches[i] == j && curr_alt_match_win[i])) | |
2759 | continue; | |
1c86bd80 VM |
2760 | /* If we don't reload j-th operand, check conflicts. */ |
2761 | else if ((curr_alt_win[j] || curr_alt_match_win[j]) | |
2762 | && uses_hard_regs_p (*curr_id->operand_loc[j], temp_set)) | |
2194f7a2 VM |
2763 | { |
2764 | if (first_conflict_j < 0) | |
2765 | first_conflict_j = j; | |
2766 | last_conflict_j = j; | |
2767 | } | |
2768 | if (last_conflict_j < 0) | |
55a2c322 | 2769 | continue; |
1c86bd80 VM |
2770 | /* If earlyclobber operand conflicts with another |
2771 | non-matching operand which is actually the same register | |
2772 | as the earlyclobber operand, it is better to reload the | |
2773 | another operand as an operand matching the earlyclobber | |
2774 | operand can be also the same. */ | |
2194f7a2 | 2775 | if (first_conflict_j == last_conflict_j |
e78dbb4a MS |
2776 | && operand_reg[last_conflict_j] != NULL_RTX |
2777 | && ! curr_alt_match_win[last_conflict_j] | |
2194f7a2 | 2778 | && REGNO (operand_reg[i]) == REGNO (operand_reg[last_conflict_j])) |
1c86bd80 | 2779 | { |
2194f7a2 VM |
2780 | curr_alt_win[last_conflict_j] = false; |
2781 | curr_alt_dont_inherit_ops[curr_alt_dont_inherit_ops_num++] | |
2782 | = last_conflict_j; | |
1c86bd80 | 2783 | losers++; |
deca73f5 VM |
2784 | /* Early clobber was already reflected in REJECT. */ |
2785 | lra_assert (reject > 0); | |
cb1cca12 VM |
2786 | if (lra_dump_file != NULL) |
2787 | fprintf | |
2788 | (lra_dump_file, | |
2789 | " %d Conflict early clobber reload: reject--\n", | |
2790 | i); | |
deca73f5 VM |
2791 | reject--; |
2792 | overall += LRA_LOSER_COST_FACTOR - 1; | |
1c86bd80 | 2793 | } |
55a2c322 VM |
2794 | else |
2795 | { | |
1c86bd80 VM |
2796 | /* We need to reload early clobbered register and the |
2797 | matched registers. */ | |
2798 | for (j = 0; j < n_operands; j++) | |
2799 | if (curr_alt_matches[j] == i) | |
2800 | { | |
2801 | curr_alt_match_win[j] = false; | |
2802 | losers++; | |
2803 | overall += LRA_LOSER_COST_FACTOR; | |
2804 | } | |
2805 | if (! curr_alt_match_win[i]) | |
2806 | curr_alt_dont_inherit_ops[curr_alt_dont_inherit_ops_num++] = i; | |
2807 | else | |
2808 | { | |
2809 | /* Remember pseudos used for match reloads are never | |
2810 | inherited. */ | |
2811 | lra_assert (curr_alt_matches[i] >= 0); | |
2812 | curr_alt_win[curr_alt_matches[i]] = false; | |
2813 | } | |
2814 | curr_alt_win[i] = curr_alt_match_win[i] = false; | |
2815 | losers++; | |
deca73f5 VM |
2816 | /* Early clobber was already reflected in REJECT. */ |
2817 | lra_assert (reject > 0); | |
cb1cca12 VM |
2818 | if (lra_dump_file != NULL) |
2819 | fprintf | |
2820 | (lra_dump_file, | |
2821 | " %d Matched conflict early clobber reloads:" | |
2822 | "reject--\n", | |
2823 | i); | |
deca73f5 VM |
2824 | reject--; |
2825 | overall += LRA_LOSER_COST_FACTOR - 1; | |
55a2c322 | 2826 | } |
55a2c322 | 2827 | } |
deca73f5 | 2828 | if (lra_dump_file != NULL) |
36ff9dfb VM |
2829 | fprintf (lra_dump_file, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n", |
2830 | nalt, overall, losers, reload_nregs); | |
deca73f5 | 2831 | |
55a2c322 VM |
2832 | /* If this alternative can be made to work by reloading, and it |
2833 | needs less reloading than the others checked so far, record | |
2834 | it as the chosen goal for reloading. */ | |
2835 | if ((best_losers != 0 && losers == 0) | |
2836 | || (((best_losers == 0 && losers == 0) | |
2837 | || (best_losers != 0 && losers != 0)) | |
2838 | && (best_overall > overall | |
2839 | || (best_overall == overall | |
2840 | /* If the cost of the reloads is the same, | |
2841 | prefer alternative which requires minimal | |
36ff9dfb VM |
2842 | number of reload regs. */ |
2843 | && (reload_nregs < best_reload_nregs | |
2844 | || (reload_nregs == best_reload_nregs | |
f15feaf9 VM |
2845 | && (best_reload_sum < reload_sum |
2846 | || (best_reload_sum == reload_sum | |
2847 | && nalt < goal_alt_number)))))))) | |
55a2c322 VM |
2848 | { |
2849 | for (nop = 0; nop < n_operands; nop++) | |
2850 | { | |
2851 | goal_alt_win[nop] = curr_alt_win[nop]; | |
2852 | goal_alt_match_win[nop] = curr_alt_match_win[nop]; | |
2853 | goal_alt_matches[nop] = curr_alt_matches[nop]; | |
2854 | goal_alt[nop] = curr_alt[nop]; | |
2855 | goal_alt_offmemok[nop] = curr_alt_offmemok[nop]; | |
2856 | } | |
2857 | goal_alt_dont_inherit_ops_num = curr_alt_dont_inherit_ops_num; | |
2858 | for (nop = 0; nop < curr_alt_dont_inherit_ops_num; nop++) | |
2859 | goal_alt_dont_inherit_ops[nop] = curr_alt_dont_inherit_ops[nop]; | |
2860 | goal_alt_swapped = curr_swapped; | |
2861 | best_overall = overall; | |
2862 | best_losers = losers; | |
55a2c322 VM |
2863 | best_reload_nregs = reload_nregs; |
2864 | best_reload_sum = reload_sum; | |
2865 | goal_alt_number = nalt; | |
2866 | } | |
2867 | if (losers == 0) | |
2868 | /* Everything is satisfied. Do not process alternatives | |
f4eafc30 | 2869 | anymore. */ |
55a2c322 VM |
2870 | break; |
2871 | fail: | |
2872 | ; | |
2873 | } | |
2874 | return ok_p; | |
2875 | } | |
2876 | ||
c31d2d11 RS |
2877 | /* Make reload base reg from address AD. */ |
2878 | static rtx | |
2879 | base_to_reg (struct address_info *ad) | |
2880 | { | |
2881 | enum reg_class cl; | |
2882 | int code = -1; | |
2883 | rtx new_inner = NULL_RTX; | |
2884 | rtx new_reg = NULL_RTX; | |
fee3e72c DM |
2885 | rtx_insn *insn; |
2886 | rtx_insn *last_insn = get_last_insn(); | |
c31d2d11 RS |
2887 | |
2888 | lra_assert (ad->base == ad->base_term && ad->disp == ad->disp_term); | |
2889 | cl = base_reg_class (ad->mode, ad->as, ad->base_outer_code, | |
2890 | get_index_code (ad)); | |
2891 | new_reg = lra_create_new_reg (GET_MODE (*ad->base_term), NULL_RTX, | |
2892 | cl, "base"); | |
2893 | new_inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), new_reg, | |
2894 | ad->disp_term == NULL | |
2895 | ? gen_int_mode (0, ad->mode) | |
2896 | : *ad->disp_term); | |
2897 | if (!valid_address_p (ad->mode, new_inner, ad->as)) | |
2898 | return NULL_RTX; | |
f7df4a84 | 2899 | insn = emit_insn (gen_rtx_SET (new_reg, *ad->base_term)); |
c31d2d11 RS |
2900 | code = recog_memoized (insn); |
2901 | if (code < 0) | |
2902 | { | |
2903 | delete_insns_since (last_insn); | |
2904 | return NULL_RTX; | |
2905 | } | |
2906 | ||
2907 | return new_inner; | |
2908 | } | |
2909 | ||
277f65de | 2910 | /* Make reload base reg + disp from address AD. Return the new pseudo. */ |
55a2c322 | 2911 | static rtx |
277f65de | 2912 | base_plus_disp_to_reg (struct address_info *ad) |
55a2c322 VM |
2913 | { |
2914 | enum reg_class cl; | |
2915 | rtx new_reg; | |
2916 | ||
277f65de RS |
2917 | lra_assert (ad->base == ad->base_term && ad->disp == ad->disp_term); |
2918 | cl = base_reg_class (ad->mode, ad->as, ad->base_outer_code, | |
2919 | get_index_code (ad)); | |
2920 | new_reg = lra_create_new_reg (GET_MODE (*ad->base_term), NULL_RTX, | |
2921 | cl, "base + disp"); | |
2922 | lra_emit_add (new_reg, *ad->base_term, *ad->disp_term); | |
55a2c322 VM |
2923 | return new_reg; |
2924 | } | |
2925 | ||
6e071b1e VM |
2926 | /* Make reload of index part of address AD. Return the new |
2927 | pseudo. */ | |
2928 | static rtx | |
2929 | index_part_to_reg (struct address_info *ad) | |
2930 | { | |
2931 | rtx new_reg; | |
2932 | ||
2933 | new_reg = lra_create_new_reg (GET_MODE (*ad->index), NULL_RTX, | |
2934 | INDEX_REG_CLASS, "index term"); | |
2935 | expand_mult (GET_MODE (*ad->index), *ad->index_term, | |
2936 | GEN_INT (get_index_scale (ad)), new_reg, 1); | |
2937 | return new_reg; | |
2938 | } | |
2939 | ||
277f65de RS |
2940 | /* Return true if we can add a displacement to address AD, even if that |
2941 | makes the address invalid. The fix-up code requires any new address | |
2942 | to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */ | |
02ea4bf4 | 2943 | static bool |
277f65de | 2944 | can_add_disp_p (struct address_info *ad) |
02ea4bf4 | 2945 | { |
277f65de RS |
2946 | return (!ad->autoinc_p |
2947 | && ad->segment == NULL | |
2948 | && ad->base == ad->base_term | |
2949 | && ad->disp == ad->disp_term); | |
02ea4bf4 RS |
2950 | } |
2951 | ||
277f65de RS |
2952 | /* Make equiv substitution in address AD. Return true if a substitution |
2953 | was made. */ | |
55a2c322 | 2954 | static bool |
277f65de | 2955 | equiv_address_substitution (struct address_info *ad) |
55a2c322 | 2956 | { |
277f65de | 2957 | rtx base_reg, new_base_reg, index_reg, new_index_reg, *base_term, *index_term; |
55a2c322 VM |
2958 | HOST_WIDE_INT disp, scale; |
2959 | bool change_p; | |
2960 | ||
277f65de RS |
2961 | base_term = strip_subreg (ad->base_term); |
2962 | if (base_term == NULL) | |
55a2c322 VM |
2963 | base_reg = new_base_reg = NULL_RTX; |
2964 | else | |
2965 | { | |
277f65de | 2966 | base_reg = *base_term; |
8d49e7ef | 2967 | new_base_reg = get_equiv_with_elimination (base_reg, curr_insn); |
55a2c322 | 2968 | } |
277f65de RS |
2969 | index_term = strip_subreg (ad->index_term); |
2970 | if (index_term == NULL) | |
55a2c322 VM |
2971 | index_reg = new_index_reg = NULL_RTX; |
2972 | else | |
2973 | { | |
277f65de | 2974 | index_reg = *index_term; |
8d49e7ef | 2975 | new_index_reg = get_equiv_with_elimination (index_reg, curr_insn); |
55a2c322 VM |
2976 | } |
2977 | if (base_reg == new_base_reg && index_reg == new_index_reg) | |
2978 | return false; | |
2979 | disp = 0; | |
2980 | change_p = false; | |
2981 | if (lra_dump_file != NULL) | |
2982 | { | |
2983 | fprintf (lra_dump_file, "Changing address in insn %d ", | |
2984 | INSN_UID (curr_insn)); | |
cfbeaedf | 2985 | dump_value_slim (lra_dump_file, *ad->outer, 1); |
55a2c322 VM |
2986 | } |
2987 | if (base_reg != new_base_reg) | |
2988 | { | |
2989 | if (REG_P (new_base_reg)) | |
2990 | { | |
277f65de | 2991 | *base_term = new_base_reg; |
55a2c322 VM |
2992 | change_p = true; |
2993 | } | |
2994 | else if (GET_CODE (new_base_reg) == PLUS | |
2995 | && REG_P (XEXP (new_base_reg, 0)) | |
02ea4bf4 | 2996 | && CONST_INT_P (XEXP (new_base_reg, 1)) |
277f65de | 2997 | && can_add_disp_p (ad)) |
55a2c322 VM |
2998 | { |
2999 | disp += INTVAL (XEXP (new_base_reg, 1)); | |
277f65de | 3000 | *base_term = XEXP (new_base_reg, 0); |
55a2c322 VM |
3001 | change_p = true; |
3002 | } | |
277f65de RS |
3003 | if (ad->base_term2 != NULL) |
3004 | *ad->base_term2 = *ad->base_term; | |
55a2c322 | 3005 | } |
55a2c322 VM |
3006 | if (index_reg != new_index_reg) |
3007 | { | |
3008 | if (REG_P (new_index_reg)) | |
3009 | { | |
277f65de | 3010 | *index_term = new_index_reg; |
55a2c322 VM |
3011 | change_p = true; |
3012 | } | |
3013 | else if (GET_CODE (new_index_reg) == PLUS | |
3014 | && REG_P (XEXP (new_index_reg, 0)) | |
02ea4bf4 | 3015 | && CONST_INT_P (XEXP (new_index_reg, 1)) |
277f65de | 3016 | && can_add_disp_p (ad) |
02ea4bf4 | 3017 | && (scale = get_index_scale (ad))) |
55a2c322 VM |
3018 | { |
3019 | disp += INTVAL (XEXP (new_index_reg, 1)) * scale; | |
277f65de | 3020 | *index_term = XEXP (new_index_reg, 0); |
55a2c322 VM |
3021 | change_p = true; |
3022 | } | |
3023 | } | |
3024 | if (disp != 0) | |
3025 | { | |
277f65de RS |
3026 | if (ad->disp != NULL) |
3027 | *ad->disp = plus_constant (GET_MODE (*ad->inner), *ad->disp, disp); | |
55a2c322 VM |
3028 | else |
3029 | { | |
277f65de RS |
3030 | *ad->inner = plus_constant (GET_MODE (*ad->inner), *ad->inner, disp); |
3031 | update_address (ad); | |
55a2c322 VM |
3032 | } |
3033 | change_p = true; | |
3034 | } | |
3035 | if (lra_dump_file != NULL) | |
3036 | { | |
3037 | if (! change_p) | |
3038 | fprintf (lra_dump_file, " -- no change\n"); | |
3039 | else | |
3040 | { | |
3041 | fprintf (lra_dump_file, " on equiv "); | |
cfbeaedf | 3042 | dump_value_slim (lra_dump_file, *ad->outer, 1); |
55a2c322 VM |
3043 | fprintf (lra_dump_file, "\n"); |
3044 | } | |
3045 | } | |
3046 | return change_p; | |
3047 | } | |
3048 | ||
d9cf932c VM |
3049 | /* Major function to make reloads for an address in operand NOP or |
3050 | check its correctness (If CHECK_ONLY_P is true). The supported | |
3051 | cases are: | |
bd3d34d4 | 3052 | |
5a107a0f VM |
3053 | 1) an address that existed before LRA started, at which point it |
3054 | must have been valid. These addresses are subject to elimination | |
3055 | and may have become invalid due to the elimination offset being out | |
3056 | of range. | |
bd3d34d4 | 3057 | |
5a107a0f VM |
3058 | 2) an address created by forcing a constant to memory |
3059 | (force_const_to_mem). The initial form of these addresses might | |
3060 | not be valid, and it is this function's job to make them valid. | |
bd3d34d4 RS |
3061 | |
3062 | 3) a frame address formed from a register and a (possibly zero) | |
5a107a0f VM |
3063 | constant offset. As above, these addresses might not be valid and |
3064 | this function must make them so. | |
bd3d34d4 RS |
3065 | |
3066 | Add reloads to the lists *BEFORE and *AFTER. We might need to add | |
55a2c322 | 3067 | reloads to *AFTER because of inc/dec, {pre, post} modify in the |
cc8849a1 VM |
3068 | address. Return true for any RTL change. |
3069 | ||
3070 | The function is a helper function which does not produce all | |
d9cf932c VM |
3071 | transformations (when CHECK_ONLY_P is false) which can be |
3072 | necessary. It does just basic steps. To do all necessary | |
3073 | transformations use function process_address. */ | |
55a2c322 | 3074 | static bool |
d9cf932c VM |
3075 | process_address_1 (int nop, bool check_only_p, |
3076 | rtx_insn **before, rtx_insn **after) | |
55a2c322 | 3077 | { |
277f65de RS |
3078 | struct address_info ad; |
3079 | rtx new_reg; | |
bc2fc1f3 | 3080 | HOST_WIDE_INT scale; |
55a2c322 VM |
3081 | rtx op = *curr_id->operand_loc[nop]; |
3082 | const char *constraint = curr_static_id->operand[nop].constraint; | |
777e635f | 3083 | enum constraint_num cn = lookup_constraint (constraint); |
d9cf932c | 3084 | bool change_p = false; |
55a2c322 | 3085 | |
823bb054 SB |
3086 | if (MEM_P (op) |
3087 | && GET_MODE (op) == BLKmode | |
3088 | && GET_CODE (XEXP (op, 0)) == SCRATCH) | |
3089 | return false; | |
3090 | ||
8677664e | 3091 | if (insn_extra_address_constraint (cn)) |
277f65de | 3092 | decompose_lea_address (&ad, curr_id->operand_loc[nop]); |
164f0634 EB |
3093 | /* Do not attempt to decompose arbitrary addresses generated by combine |
3094 | for asm operands with loose constraints, e.g 'X'. */ | |
3095 | else if (MEM_P (op) | |
3096 | && !(get_constraint_type (cn) == CT_FIXED_FORM | |
3097 | && constraint_satisfied_p (op, cn))) | |
277f65de | 3098 | decompose_mem_address (&ad, op); |
55a2c322 VM |
3099 | else if (GET_CODE (op) == SUBREG |
3100 | && MEM_P (SUBREG_REG (op))) | |
277f65de | 3101 | decompose_mem_address (&ad, SUBREG_REG (op)); |
55a2c322 VM |
3102 | else |
3103 | return false; | |
70712859 KK |
3104 | /* If INDEX_REG_CLASS is assigned to base_term already and isn't to |
3105 | index_term, swap them so to avoid assigning INDEX_REG_CLASS to both | |
3106 | when INDEX_REG_CLASS is a single register class. */ | |
3107 | if (ad.base_term != NULL | |
3108 | && ad.index_term != NULL | |
3109 | && ira_class_hard_regs_num[INDEX_REG_CLASS] == 1 | |
3110 | && REG_P (*ad.base_term) | |
3111 | && REG_P (*ad.index_term) | |
3112 | && in_class_p (*ad.base_term, INDEX_REG_CLASS, NULL) | |
3113 | && ! in_class_p (*ad.index_term, INDEX_REG_CLASS, NULL)) | |
3114 | { | |
3115 | std::swap (ad.base, ad.index); | |
3116 | std::swap (ad.base_term, ad.index_term); | |
3117 | } | |
d9cf932c VM |
3118 | if (! check_only_p) |
3119 | change_p = equiv_address_substitution (&ad); | |
277f65de | 3120 | if (ad.base_term != NULL |
55a2c322 | 3121 | && (process_addr_reg |
d9cf932c | 3122 | (ad.base_term, check_only_p, before, |
277f65de RS |
3123 | (ad.autoinc_p |
3124 | && !(REG_P (*ad.base_term) | |
3125 | && find_regno_note (curr_insn, REG_DEAD, | |
3126 | REGNO (*ad.base_term)) != NULL_RTX) | |
55a2c322 | 3127 | ? after : NULL), |
277f65de RS |
3128 | base_reg_class (ad.mode, ad.as, ad.base_outer_code, |
3129 | get_index_code (&ad))))) | |
55a2c322 VM |
3130 | { |
3131 | change_p = true; | |
277f65de RS |
3132 | if (ad.base_term2 != NULL) |
3133 | *ad.base_term2 = *ad.base_term; | |
55a2c322 | 3134 | } |
277f65de | 3135 | if (ad.index_term != NULL |
d9cf932c VM |
3136 | && process_addr_reg (ad.index_term, check_only_p, |
3137 | before, NULL, INDEX_REG_CLASS)) | |
55a2c322 VM |
3138 | change_p = true; |
3139 | ||
777e635f RS |
3140 | /* Target hooks sometimes don't treat extra-constraint addresses as |
3141 | legitimate address_operands, so handle them specially. */ | |
8677664e | 3142 | if (insn_extra_address_constraint (cn) |
777e635f | 3143 | && satisfies_address_constraint_p (&ad, cn)) |
2c62cbaa | 3144 | return change_p; |
2c62cbaa | 3145 | |
d9cf932c VM |
3146 | if (check_only_p) |
3147 | return change_p; | |
3148 | ||
277f65de | 3149 | /* There are three cases where the shape of *AD.INNER may now be invalid: |
bd3d34d4 RS |
3150 | |
3151 | 1) the original address was valid, but either elimination or | |
5a107a0f VM |
3152 | equiv_address_substitution was applied and that made |
3153 | the address invalid. | |
bd3d34d4 RS |
3154 | |
3155 | 2) the address is an invalid symbolic address created by | |
5a107a0f | 3156 | force_const_to_mem. |
bd3d34d4 RS |
3157 | |
3158 | 3) the address is a frame address with an invalid offset. | |
3159 | ||
c31d2d11 RS |
3160 | 4) the address is a frame address with an invalid base. |
3161 | ||
2c62cbaa VM |
3162 | All these cases involve a non-autoinc address, so there is no |
3163 | point revalidating other types. */ | |
3164 | if (ad.autoinc_p || valid_address_p (&ad)) | |
55a2c322 VM |
3165 | return change_p; |
3166 | ||
bd3d34d4 RS |
3167 | /* Any index existed before LRA started, so we can assume that the |
3168 | presence and shape of the index is valid. */ | |
55a2c322 | 3169 | push_to_sequence (*before); |
2c62cbaa | 3170 | lra_assert (ad.disp == ad.disp_term); |
277f65de | 3171 | if (ad.base == NULL) |
55a2c322 | 3172 | { |
277f65de | 3173 | if (ad.index == NULL) |
55a2c322 | 3174 | { |
95831c01 VM |
3175 | rtx_insn *insn; |
3176 | rtx_insn *last = get_last_insn (); | |
55a2c322 | 3177 | int code = -1; |
277f65de RS |
3178 | enum reg_class cl = base_reg_class (ad.mode, ad.as, |
3179 | SCRATCH, SCRATCH); | |
2c62cbaa | 3180 | rtx addr = *ad.inner; |
277f65de | 3181 | |
2c62cbaa | 3182 | new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "addr"); |
d0b2266a TS |
3183 | if (HAVE_lo_sum) |
3184 | { | |
d0b2266a TS |
3185 | /* addr => lo_sum (new_base, addr), case (2) above. */ |
3186 | insn = emit_insn (gen_rtx_SET | |
3187 | (new_reg, | |
3188 | gen_rtx_HIGH (Pmode, copy_rtx (addr)))); | |
3189 | code = recog_memoized (insn); | |
3190 | if (code >= 0) | |
3191 | { | |
3192 | *ad.inner = gen_rtx_LO_SUM (Pmode, new_reg, addr); | |
3193 | if (! valid_address_p (ad.mode, *ad.outer, ad.as)) | |
3194 | { | |
3195 | /* Try to put lo_sum into register. */ | |
3196 | insn = emit_insn (gen_rtx_SET | |
3197 | (new_reg, | |
3198 | gen_rtx_LO_SUM (Pmode, new_reg, addr))); | |
3199 | code = recog_memoized (insn); | |
3200 | if (code >= 0) | |
3201 | { | |
3202 | *ad.inner = new_reg; | |
3203 | if (! valid_address_p (ad.mode, *ad.outer, ad.as)) | |
3204 | { | |
3205 | *ad.inner = addr; | |
3206 | code = -1; | |
3207 | } | |
3208 | } | |
3209 | ||
3210 | } | |
3211 | } | |
3212 | if (code < 0) | |
3213 | delete_insns_since (last); | |
3214 | } | |
3215 | ||
55a2c322 VM |
3216 | if (code < 0) |
3217 | { | |
2c62cbaa VM |
3218 | /* addr => new_base, case (2) above. */ |
3219 | lra_emit_move (new_reg, addr); | |
95831c01 VM |
3220 | |
3221 | for (insn = last == NULL_RTX ? get_insns () : NEXT_INSN (last); | |
3222 | insn != NULL_RTX; | |
3223 | insn = NEXT_INSN (insn)) | |
3224 | if (recog_memoized (insn) < 0) | |
3225 | break; | |
3226 | if (insn != NULL_RTX) | |
3227 | { | |
3228 | /* Do nothing if we cannot generate right insns. | |
9c582551 | 3229 | This is analogous to reload pass behavior. */ |
95831c01 VM |
3230 | delete_insns_since (last); |
3231 | end_sequence (); | |
3232 | return false; | |
3233 | } | |
2c62cbaa | 3234 | *ad.inner = new_reg; |
55a2c322 VM |
3235 | } |
3236 | } | |
3237 | else | |
3238 | { | |
bd3d34d4 RS |
3239 | /* index * scale + disp => new base + index * scale, |
3240 | case (1) above. */ | |
277f65de RS |
3241 | enum reg_class cl = base_reg_class (ad.mode, ad.as, PLUS, |
3242 | GET_CODE (*ad.index)); | |
55a2c322 VM |
3243 | |
3244 | lra_assert (INDEX_REG_CLASS != NO_REGS); | |
3245 | new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "disp"); | |
277f65de RS |
3246 | lra_emit_move (new_reg, *ad.disp); |
3247 | *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), | |
3248 | new_reg, *ad.index); | |
55a2c322 VM |
3249 | } |
3250 | } | |
277f65de | 3251 | else if (ad.index == NULL) |
55a2c322 | 3252 | { |
5a107a0f VM |
3253 | int regno; |
3254 | enum reg_class cl; | |
cfa434f6 DM |
3255 | rtx set; |
3256 | rtx_insn *insns, *last_insn; | |
c31d2d11 RS |
3257 | /* Try to reload base into register only if the base is invalid |
3258 | for the address but with valid offset, case (4) above. */ | |
3259 | start_sequence (); | |
3260 | new_reg = base_to_reg (&ad); | |
3261 | ||
bd3d34d4 | 3262 | /* base + disp => new base, cases (1) and (3) above. */ |
55a2c322 VM |
3263 | /* Another option would be to reload the displacement into an |
3264 | index register. However, postreload has code to optimize | |
3265 | address reloads that have the same base and different | |
3266 | displacements, so reloading into an index register would | |
3267 | not necessarily be a win. */ | |
c31d2d11 RS |
3268 | if (new_reg == NULL_RTX) |
3269 | new_reg = base_plus_disp_to_reg (&ad); | |
5a107a0f VM |
3270 | insns = get_insns (); |
3271 | last_insn = get_last_insn (); | |
3272 | /* If we generated at least two insns, try last insn source as | |
3273 | an address. If we succeed, we generate one less insn. */ | |
3274 | if (last_insn != insns && (set = single_set (last_insn)) != NULL_RTX | |
3275 | && GET_CODE (SET_SRC (set)) == PLUS | |
3276 | && REG_P (XEXP (SET_SRC (set), 0)) | |
3277 | && CONSTANT_P (XEXP (SET_SRC (set), 1))) | |
3278 | { | |
3279 | *ad.inner = SET_SRC (set); | |
3280 | if (valid_address_p (ad.mode, *ad.outer, ad.as)) | |
3281 | { | |
3282 | *ad.base_term = XEXP (SET_SRC (set), 0); | |
3283 | *ad.disp_term = XEXP (SET_SRC (set), 1); | |
3284 | cl = base_reg_class (ad.mode, ad.as, ad.base_outer_code, | |
3285 | get_index_code (&ad)); | |
3286 | regno = REGNO (*ad.base_term); | |
3287 | if (regno >= FIRST_PSEUDO_REGISTER | |
3288 | && cl != lra_get_allocno_class (regno)) | |
a2d0d374 | 3289 | lra_change_class (regno, cl, " Change to", true); |
5a107a0f VM |
3290 | new_reg = SET_SRC (set); |
3291 | delete_insns_since (PREV_INSN (last_insn)); | |
3292 | } | |
3293 | } | |
14133a4d KK |
3294 | /* Try if target can split displacement into legitimite new disp |
3295 | and offset. If it's the case, we replace the last insn with | |
3296 | insns for base + offset => new_reg and set new_reg + new disp | |
3297 | to *ad.inner. */ | |
3298 | last_insn = get_last_insn (); | |
3299 | if ((set = single_set (last_insn)) != NULL_RTX | |
3300 | && GET_CODE (SET_SRC (set)) == PLUS | |
3301 | && REG_P (XEXP (SET_SRC (set), 0)) | |
3302 | && REGNO (XEXP (SET_SRC (set), 0)) < FIRST_PSEUDO_REGISTER | |
3303 | && CONST_INT_P (XEXP (SET_SRC (set), 1))) | |
3304 | { | |
3305 | rtx addend, disp = XEXP (SET_SRC (set), 1); | |
3306 | if (targetm.legitimize_address_displacement (&disp, &addend, | |
3307 | ad.mode)) | |
3308 | { | |
3309 | rtx_insn *new_insns; | |
3310 | start_sequence (); | |
3311 | lra_emit_add (new_reg, XEXP (SET_SRC (set), 0), addend); | |
3312 | new_insns = get_insns (); | |
3313 | end_sequence (); | |
3314 | new_reg = gen_rtx_PLUS (Pmode, new_reg, disp); | |
3315 | delete_insns_since (PREV_INSN (last_insn)); | |
3316 | add_insn (new_insns); | |
3317 | insns = get_insns (); | |
3318 | } | |
3319 | } | |
5a107a0f VM |
3320 | end_sequence (); |
3321 | emit_insn (insns); | |
277f65de | 3322 | *ad.inner = new_reg; |
55a2c322 | 3323 | } |
6e071b1e | 3324 | else if (ad.disp_term != NULL) |
55a2c322 | 3325 | { |
bd3d34d4 RS |
3326 | /* base + scale * index + disp => new base + scale * index, |
3327 | case (1) above. */ | |
277f65de RS |
3328 | new_reg = base_plus_disp_to_reg (&ad); |
3329 | *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), | |
3330 | new_reg, *ad.index); | |
55a2c322 | 3331 | } |
bc2fc1f3 | 3332 | else if ((scale = get_index_scale (&ad)) == 1) |
5a770e01 VM |
3333 | { |
3334 | /* The last transformation to one reg will be made in | |
3335 | curr_insn_transform function. */ | |
3336 | end_sequence (); | |
3337 | return false; | |
3338 | } | |
bc2fc1f3 | 3339 | else if (scale != 0) |
6e071b1e VM |
3340 | { |
3341 | /* base + scale * index => base + new_reg, | |
3342 | case (1) above. | |
3343 | Index part of address may become invalid. For example, we | |
3344 | changed pseudo on the equivalent memory and a subreg of the | |
3345 | pseudo onto the memory of different mode for which the scale is | |
3346 | prohibitted. */ | |
3347 | new_reg = index_part_to_reg (&ad); | |
3348 | *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), | |
3349 | *ad.base_term, new_reg); | |
3350 | } | |
bc2fc1f3 VM |
3351 | else |
3352 | { | |
3353 | enum reg_class cl = base_reg_class (ad.mode, ad.as, | |
3354 | SCRATCH, SCRATCH); | |
3355 | rtx addr = *ad.inner; | |
3356 | ||
3357 | new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "addr"); | |
3358 | /* addr => new_base. */ | |
3359 | lra_emit_move (new_reg, addr); | |
3360 | *ad.inner = new_reg; | |
3361 | } | |
55a2c322 VM |
3362 | *before = get_insns (); |
3363 | end_sequence (); | |
3364 | return true; | |
3365 | } | |
3366 | ||
d9cf932c VM |
3367 | /* If CHECK_ONLY_P is false, do address reloads until it is necessary. |
3368 | Use process_address_1 as a helper function. Return true for any | |
3369 | RTL changes. | |
3370 | ||
3371 | If CHECK_ONLY_P is true, just check address correctness. Return | |
3372 | false if the address correct. */ | |
cc8849a1 | 3373 | static bool |
d9cf932c VM |
3374 | process_address (int nop, bool check_only_p, |
3375 | rtx_insn **before, rtx_insn **after) | |
cc8849a1 VM |
3376 | { |
3377 | bool res = false; | |
3378 | ||
d9cf932c VM |
3379 | while (process_address_1 (nop, check_only_p, before, after)) |
3380 | { | |
3381 | if (check_only_p) | |
3382 | return true; | |
3383 | res = true; | |
3384 | } | |
cc8849a1 VM |
3385 | return res; |
3386 | } | |
3387 | ||
55a2c322 VM |
3388 | /* Emit insns to reload VALUE into a new register. VALUE is an |
3389 | auto-increment or auto-decrement RTX whose operand is a register or | |
3390 | memory location; so reloading involves incrementing that location. | |
3391 | IN is either identical to VALUE, or some cheaper place to reload | |
3392 | value being incremented/decremented from. | |
3393 | ||
3394 | INC_AMOUNT is the number to increment or decrement by (always | |
3395 | positive and ignored for POST_MODIFY/PRE_MODIFY). | |
3396 | ||
3397 | Return pseudo containing the result. */ | |
3398 | static rtx | |
3399 | emit_inc (enum reg_class new_rclass, rtx in, rtx value, int inc_amount) | |
3400 | { | |
3401 | /* REG or MEM to be copied and incremented. */ | |
3402 | rtx incloc = XEXP (value, 0); | |
3403 | /* Nonzero if increment after copying. */ | |
3404 | int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC | |
3405 | || GET_CODE (value) == POST_MODIFY); | |
cfa434f6 | 3406 | rtx_insn *last; |
55a2c322 | 3407 | rtx inc; |
647d790d | 3408 | rtx_insn *add_insn; |
55a2c322 VM |
3409 | int code; |
3410 | rtx real_in = in == value ? incloc : in; | |
3411 | rtx result; | |
3412 | bool plus_p = true; | |
3413 | ||
3414 | if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY) | |
3415 | { | |
3416 | lra_assert (GET_CODE (XEXP (value, 1)) == PLUS | |
3417 | || GET_CODE (XEXP (value, 1)) == MINUS); | |
3418 | lra_assert (rtx_equal_p (XEXP (XEXP (value, 1), 0), XEXP (value, 0))); | |
3419 | plus_p = GET_CODE (XEXP (value, 1)) == PLUS; | |
3420 | inc = XEXP (XEXP (value, 1), 1); | |
3421 | } | |
3422 | else | |
3423 | { | |
3424 | if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC) | |
3425 | inc_amount = -inc_amount; | |
3426 | ||
3427 | inc = GEN_INT (inc_amount); | |
3428 | } | |
3429 | ||
3430 | if (! post && REG_P (incloc)) | |
3431 | result = incloc; | |
3432 | else | |
3433 | result = lra_create_new_reg (GET_MODE (value), value, new_rclass, | |
3434 | "INC/DEC result"); | |
3435 | ||
3436 | if (real_in != result) | |
3437 | { | |
3438 | /* First copy the location to the result register. */ | |
3439 | lra_assert (REG_P (result)); | |
3440 | emit_insn (gen_move_insn (result, real_in)); | |
3441 | } | |
3442 | ||
3443 | /* We suppose that there are insns to add/sub with the constant | |
3444 | increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the | |
3445 | old reload worked with this assumption. If the assumption | |
3446 | becomes wrong, we should use approach in function | |
3447 | base_plus_disp_to_reg. */ | |
3448 | if (in == value) | |
3449 | { | |
3450 | /* See if we can directly increment INCLOC. */ | |
3451 | last = get_last_insn (); | |
3452 | add_insn = emit_insn (plus_p | |
3453 | ? gen_add2_insn (incloc, inc) | |
3454 | : gen_sub2_insn (incloc, inc)); | |
3455 | ||
3456 | code = recog_memoized (add_insn); | |
3457 | if (code >= 0) | |
3458 | { | |
3459 | if (! post && result != incloc) | |
3460 | emit_insn (gen_move_insn (result, incloc)); | |
3461 | return result; | |
3462 | } | |
3463 | delete_insns_since (last); | |
3464 | } | |
3465 | ||
3466 | /* If couldn't do the increment directly, must increment in RESULT. | |
3467 | The way we do this depends on whether this is pre- or | |
3468 | post-increment. For pre-increment, copy INCLOC to the reload | |
3469 | register, increment it there, then save back. */ | |
3470 | if (! post) | |
3471 | { | |
3472 | if (real_in != result) | |
3473 | emit_insn (gen_move_insn (result, real_in)); | |
3474 | if (plus_p) | |
3475 | emit_insn (gen_add2_insn (result, inc)); | |
3476 | else | |
3477 | emit_insn (gen_sub2_insn (result, inc)); | |
3478 | if (result != incloc) | |
3479 | emit_insn (gen_move_insn (incloc, result)); | |
3480 | } | |
3481 | else | |
3482 | { | |
3483 | /* Post-increment. | |
3484 | ||
3485 | Because this might be a jump insn or a compare, and because | |
3486 | RESULT may not be available after the insn in an input | |
3487 | reload, we must do the incrementing before the insn being | |
3488 | reloaded for. | |
3489 | ||
3490 | We have already copied IN to RESULT. Increment the copy in | |
3491 | RESULT, save that back, then decrement RESULT so it has | |
3492 | the original value. */ | |
3493 | if (plus_p) | |
3494 | emit_insn (gen_add2_insn (result, inc)); | |
3495 | else | |
3496 | emit_insn (gen_sub2_insn (result, inc)); | |
3497 | emit_insn (gen_move_insn (incloc, result)); | |
3498 | /* Restore non-modified value for the result. We prefer this | |
3499 | way because it does not require an additional hard | |
3500 | register. */ | |
3501 | if (plus_p) | |
3502 | { | |
3503 | if (CONST_INT_P (inc)) | |
69db2d57 RS |
3504 | emit_insn (gen_add2_insn (result, |
3505 | gen_int_mode (-INTVAL (inc), | |
3506 | GET_MODE (result)))); | |
55a2c322 VM |
3507 | else |
3508 | emit_insn (gen_sub2_insn (result, inc)); | |
3509 | } | |
3510 | else | |
3511 | emit_insn (gen_add2_insn (result, inc)); | |
3512 | } | |
3513 | return result; | |
3514 | } | |
3515 | ||
2c62cbaa VM |
3516 | /* Return true if the current move insn does not need processing as we |
3517 | already know that it satisfies its constraints. */ | |
3518 | static bool | |
3519 | simple_move_p (void) | |
3520 | { | |
3521 | rtx dest, src; | |
3522 | enum reg_class dclass, sclass; | |
3523 | ||
3524 | lra_assert (curr_insn_set != NULL_RTX); | |
3525 | dest = SET_DEST (curr_insn_set); | |
3526 | src = SET_SRC (curr_insn_set); | |
2008be40 SB |
3527 | |
3528 | /* If the instruction has multiple sets we need to process it even if it | |
3529 | is single_set. This can happen if one or more of the SETs are dead. | |
3530 | See PR73650. */ | |
3531 | if (multiple_sets (curr_insn)) | |
3532 | return false; | |
3533 | ||
2c62cbaa VM |
3534 | return ((dclass = get_op_class (dest)) != NO_REGS |
3535 | && (sclass = get_op_class (src)) != NO_REGS | |
3536 | /* The backend guarantees that register moves of cost 2 | |
3537 | never need reloads. */ | |
03b9b5ce | 3538 | && targetm.register_move_cost (GET_MODE (src), sclass, dclass) == 2); |
2c62cbaa VM |
3539 | } |
3540 | ||
55a2c322 VM |
3541 | /* Swap operands NOP and NOP + 1. */ |
3542 | static inline void | |
3543 | swap_operands (int nop) | |
3544 | { | |
fab27f52 MM |
3545 | std::swap (curr_operand_mode[nop], curr_operand_mode[nop + 1]); |
3546 | std::swap (original_subreg_reg_mode[nop], original_subreg_reg_mode[nop + 1]); | |
3547 | std::swap (*curr_id->operand_loc[nop], *curr_id->operand_loc[nop + 1]); | |
987b67f1 | 3548 | std::swap (equiv_substition_p[nop], equiv_substition_p[nop + 1]); |
55a2c322 VM |
3549 | /* Swap the duplicates too. */ |
3550 | lra_update_dup (curr_id, nop); | |
3551 | lra_update_dup (curr_id, nop + 1); | |
3552 | } | |
3553 | ||
3554 | /* Main entry point of the constraint code: search the body of the | |
3555 | current insn to choose the best alternative. It is mimicking insn | |
3556 | alternative cost calculation model of former reload pass. That is | |
3557 | because machine descriptions were written to use this model. This | |
3558 | model can be changed in future. Make commutative operand exchange | |
3559 | if it is chosen. | |
3560 | ||
d9cf932c VM |
3561 | if CHECK_ONLY_P is false, do RTL changes to satisfy the |
3562 | constraints. Return true if any change happened during function | |
3563 | call. | |
3564 | ||
3565 | If CHECK_ONLY_P is true then don't do any transformation. Just | |
3566 | check that the insn satisfies all constraints. If the insn does | |
3567 | not satisfy any constraint, return true. */ | |
55a2c322 | 3568 | static bool |
d9cf932c | 3569 | curr_insn_transform (bool check_only_p) |
55a2c322 VM |
3570 | { |
3571 | int i, j, k; | |
3572 | int n_operands; | |
3573 | int n_alternatives; | |
aefae0f1 | 3574 | int n_outputs; |
55a2c322 VM |
3575 | int commutative; |
3576 | signed char goal_alt_matched[MAX_RECOG_OPERANDS][MAX_RECOG_OPERANDS]; | |
511dcace | 3577 | signed char match_inputs[MAX_RECOG_OPERANDS + 1]; |
aefae0f1 | 3578 | signed char outputs[MAX_RECOG_OPERANDS + 1]; |
cfa434f6 | 3579 | rtx_insn *before, *after; |
55a2c322 VM |
3580 | bool alt_p = false; |
3581 | /* Flag that the insn has been changed through a transformation. */ | |
3582 | bool change_p; | |
3583 | bool sec_mem_p; | |
3584 | #ifdef SECONDARY_MEMORY_NEEDED | |
3585 | bool use_sec_mem_p; | |
3586 | #endif | |
3587 | int max_regno_before; | |
3588 | int reused_alternative_num; | |
3589 | ||
2c62cbaa VM |
3590 | curr_insn_set = single_set (curr_insn); |
3591 | if (curr_insn_set != NULL_RTX && simple_move_p ()) | |
3592 | return false; | |
3593 | ||
55a2c322 VM |
3594 | no_input_reloads_p = no_output_reloads_p = false; |
3595 | goal_alt_number = -1; | |
2c62cbaa | 3596 | change_p = sec_mem_p = false; |
55a2c322 VM |
3597 | /* JUMP_INSNs and CALL_INSNs are not allowed to have any output |
3598 | reloads; neither are insns that SET cc0. Insns that use CC0 are | |
3599 | not allowed to have any input reloads. */ | |
3600 | if (JUMP_P (curr_insn) || CALL_P (curr_insn)) | |
3601 | no_output_reloads_p = true; | |
3602 | ||
058eb3b0 | 3603 | if (HAVE_cc0 && reg_referenced_p (cc0_rtx, PATTERN (curr_insn))) |
55a2c322 | 3604 | no_input_reloads_p = true; |
058eb3b0 | 3605 | if (HAVE_cc0 && reg_set_p (cc0_rtx, PATTERN (curr_insn))) |
55a2c322 | 3606 | no_output_reloads_p = true; |
55a2c322 VM |
3607 | |
3608 | n_operands = curr_static_id->n_operands; | |
3609 | n_alternatives = curr_static_id->n_alternatives; | |
3610 | ||
3611 | /* Just return "no reloads" if insn has no operands with | |
3612 | constraints. */ | |
3613 | if (n_operands == 0 || n_alternatives == 0) | |
3614 | return false; | |
3615 | ||
3616 | max_regno_before = max_reg_num (); | |
3617 | ||
3618 | for (i = 0; i < n_operands; i++) | |
3619 | { | |
3620 | goal_alt_matched[i][0] = -1; | |
3621 | goal_alt_matches[i] = -1; | |
3622 | } | |
3623 | ||
3624 | commutative = curr_static_id->commutative; | |
3625 | ||
3626 | /* Now see what we need for pseudos that didn't get hard regs or got | |
3627 | the wrong kind of hard reg. For this, we must consider all the | |
3628 | operands together against the register constraints. */ | |
3629 | ||
821b7577 | 3630 | best_losers = best_overall = INT_MAX; |
36ff9dfb | 3631 | best_reload_sum = 0; |
55a2c322 VM |
3632 | |
3633 | curr_swapped = false; | |
3634 | goal_alt_swapped = false; | |
3635 | ||
d9cf932c VM |
3636 | if (! check_only_p) |
3637 | /* Make equivalence substitution and memory subreg elimination | |
3638 | before address processing because an address legitimacy can | |
3639 | depend on memory mode. */ | |
3640 | for (i = 0; i < n_operands; i++) | |
3641 | { | |
0b87be09 | 3642 | rtx op, subst, old; |
d9cf932c | 3643 | bool op_change_p = false; |
0b87be09 VM |
3644 | |
3645 | if (curr_static_id->operand[i].is_operator) | |
3646 | continue; | |
d9cf932c | 3647 | |
0b87be09 | 3648 | old = op = *curr_id->operand_loc[i]; |
d9cf932c VM |
3649 | if (GET_CODE (old) == SUBREG) |
3650 | old = SUBREG_REG (old); | |
3651 | subst = get_equiv_with_elimination (old, curr_insn); | |
895ff86f | 3652 | original_subreg_reg_mode[i] = VOIDmode; |
987b67f1 | 3653 | equiv_substition_p[i] = false; |
d9cf932c VM |
3654 | if (subst != old) |
3655 | { | |
987b67f1 | 3656 | equiv_substition_p[i] = true; |
d9cf932c VM |
3657 | subst = copy_rtx (subst); |
3658 | lra_assert (REG_P (old)); | |
895ff86f | 3659 | if (GET_CODE (op) != SUBREG) |
d9cf932c | 3660 | *curr_id->operand_loc[i] = subst; |
895ff86f VM |
3661 | else |
3662 | { | |
3663 | SUBREG_REG (op) = subst; | |
3664 | if (GET_MODE (subst) == VOIDmode) | |
3665 | original_subreg_reg_mode[i] = GET_MODE (old); | |
3666 | } | |
d9cf932c VM |
3667 | if (lra_dump_file != NULL) |
3668 | { | |
3669 | fprintf (lra_dump_file, | |
3670 | "Changing pseudo %d in operand %i of insn %u on equiv ", | |
3671 | REGNO (old), i, INSN_UID (curr_insn)); | |
3672 | dump_value_slim (lra_dump_file, subst, 1); | |
895ff86f | 3673 | fprintf (lra_dump_file, "\n"); |
d9cf932c VM |
3674 | } |
3675 | op_change_p = change_p = true; | |
3676 | } | |
3677 | if (simplify_operand_subreg (i, GET_MODE (old)) || op_change_p) | |
3678 | { | |
3679 | change_p = true; | |
3680 | lra_update_dup (curr_id, i); | |
3681 | } | |
3682 | } | |
55a2c322 VM |
3683 | |
3684 | /* Reload address registers and displacements. We do it before | |
3685 | finding an alternative because of memory constraints. */ | |
cfa434f6 | 3686 | before = after = NULL; |
55a2c322 VM |
3687 | for (i = 0; i < n_operands; i++) |
3688 | if (! curr_static_id->operand[i].is_operator | |
d9cf932c | 3689 | && process_address (i, check_only_p, &before, &after)) |
55a2c322 | 3690 | { |
d9cf932c VM |
3691 | if (check_only_p) |
3692 | return true; | |
55a2c322 VM |
3693 | change_p = true; |
3694 | lra_update_dup (curr_id, i); | |
3695 | } | |
cc8849a1 | 3696 | |
55a2c322 VM |
3697 | if (change_p) |
3698 | /* If we've changed the instruction then any alternative that | |
3699 | we chose previously may no longer be valid. */ | |
3700 | lra_set_used_insn_alternative (curr_insn, -1); | |
3701 | ||
d9cf932c | 3702 | if (! check_only_p && curr_insn_set != NULL_RTX |
2c62cbaa VM |
3703 | && check_and_process_move (&change_p, &sec_mem_p)) |
3704 | return change_p; | |
3705 | ||
55a2c322 VM |
3706 | try_swapped: |
3707 | ||
d9cf932c | 3708 | reused_alternative_num = check_only_p ? -1 : curr_id->used_insn_alternative; |
55a2c322 VM |
3709 | if (lra_dump_file != NULL && reused_alternative_num >= 0) |
3710 | fprintf (lra_dump_file, "Reusing alternative %d for insn #%u\n", | |
3711 | reused_alternative_num, INSN_UID (curr_insn)); | |
3712 | ||
3713 | if (process_alt_operands (reused_alternative_num)) | |
3714 | alt_p = true; | |
3715 | ||
d9cf932c VM |
3716 | if (check_only_p) |
3717 | return ! alt_p || best_losers != 0; | |
3718 | ||
55a2c322 VM |
3719 | /* If insn is commutative (it's safe to exchange a certain pair of |
3720 | operands) then we need to try each alternative twice, the second | |
3721 | time matching those two operands as if we had exchanged them. To | |
3722 | do this, really exchange them in operands. | |
3723 | ||
3724 | If we have just tried the alternatives the second time, return | |
3725 | operands to normal and drop through. */ | |
3726 | ||
3727 | if (reused_alternative_num < 0 && commutative >= 0) | |
3728 | { | |
3729 | curr_swapped = !curr_swapped; | |
3730 | if (curr_swapped) | |
3731 | { | |
3732 | swap_operands (commutative); | |
3733 | goto try_swapped; | |
3734 | } | |
3735 | else | |
3736 | swap_operands (commutative); | |
3737 | } | |
3738 | ||
55a2c322 VM |
3739 | if (! alt_p && ! sec_mem_p) |
3740 | { | |
3741 | /* No alternative works with reloads?? */ | |
3742 | if (INSN_CODE (curr_insn) >= 0) | |
3743 | fatal_insn ("unable to generate reloads for:", curr_insn); | |
3744 | error_for_asm (curr_insn, | |
3745 | "inconsistent operand constraints in an %<asm%>"); | |
3746 | /* Avoid further trouble with this insn. */ | |
3747 | PATTERN (curr_insn) = gen_rtx_USE (VOIDmode, const0_rtx); | |
3748 | lra_invalidate_insn_data (curr_insn); | |
3749 | return true; | |
3750 | } | |
3751 | ||
3752 | /* If the best alternative is with operands 1 and 2 swapped, swap | |
3753 | them. Update the operand numbers of any reloads already | |
3754 | pushed. */ | |
3755 | ||
3756 | if (goal_alt_swapped) | |
3757 | { | |
3758 | if (lra_dump_file != NULL) | |
3759 | fprintf (lra_dump_file, " Commutative operand exchange in insn %u\n", | |
3760 | INSN_UID (curr_insn)); | |
3761 | ||
3762 | /* Swap the duplicates too. */ | |
3763 | swap_operands (commutative); | |
3764 | change_p = true; | |
3765 | } | |
3766 | ||
3767 | #ifdef SECONDARY_MEMORY_NEEDED | |
3768 | /* Some target macros SECONDARY_MEMORY_NEEDED (e.g. x86) are defined | |
3769 | too conservatively. So we use the secondary memory only if there | |
3770 | is no any alternative without reloads. */ | |
3771 | use_sec_mem_p = false; | |
3772 | if (! alt_p) | |
3773 | use_sec_mem_p = true; | |
3774 | else if (sec_mem_p) | |
3775 | { | |
3776 | for (i = 0; i < n_operands; i++) | |
3777 | if (! goal_alt_win[i] && ! goal_alt_match_win[i]) | |
3778 | break; | |
3779 | use_sec_mem_p = i < n_operands; | |
3780 | } | |
3781 | ||
3782 | if (use_sec_mem_p) | |
3783 | { | |
e03dd765 | 3784 | int in = -1, out = -1; |
89d56d79 | 3785 | rtx new_reg, src, dest, rld; |
ef4bddc2 | 3786 | machine_mode sec_mode, rld_mode; |
55a2c322 | 3787 | |
e03dd765 VM |
3788 | lra_assert (curr_insn_set != NULL_RTX && sec_mem_p); |
3789 | dest = SET_DEST (curr_insn_set); | |
3790 | src = SET_SRC (curr_insn_set); | |
3791 | for (i = 0; i < n_operands; i++) | |
3792 | if (*curr_id->operand_loc[i] == dest) | |
3793 | out = i; | |
3794 | else if (*curr_id->operand_loc[i] == src) | |
3795 | in = i; | |
3796 | for (i = 0; i < curr_static_id->n_dups; i++) | |
3797 | if (out < 0 && *curr_id->dup_loc[i] == dest) | |
3798 | out = curr_static_id->dup_num[i]; | |
3799 | else if (in < 0 && *curr_id->dup_loc[i] == src) | |
3800 | in = curr_static_id->dup_num[i]; | |
3801 | lra_assert (out >= 0 && in >= 0 | |
3802 | && curr_static_id->operand[out].type == OP_OUT | |
3803 | && curr_static_id->operand[in].type == OP_IN); | |
66aa7879 VM |
3804 | rld = (GET_MODE_SIZE (GET_MODE (dest)) <= GET_MODE_SIZE (GET_MODE (src)) |
3805 | ? dest : src); | |
3806 | rld_mode = GET_MODE (rld); | |
55a2c322 | 3807 | #ifdef SECONDARY_MEMORY_NEEDED_MODE |
66aa7879 | 3808 | sec_mode = SECONDARY_MEMORY_NEEDED_MODE (rld_mode); |
55a2c322 | 3809 | #else |
66aa7879 | 3810 | sec_mode = rld_mode; |
55a2c322 VM |
3811 | #endif |
3812 | new_reg = lra_create_new_reg (sec_mode, NULL_RTX, | |
3813 | NO_REGS, "secondary"); | |
3814 | /* If the mode is changed, it should be wider. */ | |
66aa7879 | 3815 | lra_assert (GET_MODE_SIZE (sec_mode) >= GET_MODE_SIZE (rld_mode)); |
89d56d79 VM |
3816 | if (sec_mode != rld_mode) |
3817 | { | |
3818 | /* If the target says specifically to use another mode for | |
3819 | secondary memory moves we can not reuse the original | |
3820 | insn. */ | |
1ccd4874 | 3821 | after = emit_spill_move (false, new_reg, dest); |
cfa434f6 | 3822 | lra_process_new_insns (curr_insn, NULL, after, |
1ccd4874 VM |
3823 | "Inserting the sec. move"); |
3824 | /* We may have non null BEFORE here (e.g. after address | |
3825 | processing. */ | |
3826 | push_to_sequence (before); | |
3827 | before = emit_spill_move (true, new_reg, src); | |
3828 | emit_insn (before); | |
3829 | before = get_insns (); | |
3830 | end_sequence (); | |
cfa434f6 | 3831 | lra_process_new_insns (curr_insn, before, NULL, "Changing on"); |
1ccd4874 VM |
3832 | lra_set_insn_deleted (curr_insn); |
3833 | } | |
89d56d79 | 3834 | else if (dest == rld) |
1ccd4874 | 3835 | { |
e03dd765 VM |
3836 | *curr_id->operand_loc[out] = new_reg; |
3837 | lra_update_dup (curr_id, out); | |
66aa7879 | 3838 | after = emit_spill_move (false, new_reg, dest); |
cfa434f6 | 3839 | lra_process_new_insns (curr_insn, NULL, after, |
66aa7879 VM |
3840 | "Inserting the sec. move"); |
3841 | } | |
3842 | else | |
3843 | { | |
e03dd765 VM |
3844 | *curr_id->operand_loc[in] = new_reg; |
3845 | lra_update_dup (curr_id, in); | |
1ccd4874 VM |
3846 | /* See comments above. */ |
3847 | push_to_sequence (before); | |
66aa7879 | 3848 | before = emit_spill_move (true, new_reg, src); |
1ccd4874 VM |
3849 | emit_insn (before); |
3850 | before = get_insns (); | |
3851 | end_sequence (); | |
cfa434f6 | 3852 | lra_process_new_insns (curr_insn, before, NULL, |
66aa7879 VM |
3853 | "Inserting the sec. move"); |
3854 | } | |
3855 | lra_update_insn_regno_info (curr_insn); | |
55a2c322 VM |
3856 | return true; |
3857 | } | |
3858 | #endif | |
3859 | ||
3860 | lra_assert (goal_alt_number >= 0); | |
3861 | lra_set_used_insn_alternative (curr_insn, goal_alt_number); | |
3862 | ||
3863 | if (lra_dump_file != NULL) | |
3864 | { | |
3865 | const char *p; | |
3866 | ||
3867 | fprintf (lra_dump_file, " Choosing alt %d in insn %u:", | |
3868 | goal_alt_number, INSN_UID (curr_insn)); | |
3869 | for (i = 0; i < n_operands; i++) | |
3870 | { | |
3871 | p = (curr_static_id->operand_alternative | |
3872 | [goal_alt_number * n_operands + i].constraint); | |
3873 | if (*p == '\0') | |
3874 | continue; | |
3875 | fprintf (lra_dump_file, " (%d) ", i); | |
3876 | for (; *p != '\0' && *p != ',' && *p != '#'; p++) | |
3877 | fputc (*p, lra_dump_file); | |
3878 | } | |
36ff9dfb VM |
3879 | if (INSN_CODE (curr_insn) >= 0 |
3880 | && (p = get_insn_name (INSN_CODE (curr_insn))) != NULL) | |
3881 | fprintf (lra_dump_file, " {%s}", p); | |
8d49e7ef VM |
3882 | if (curr_id->sp_offset != 0) |
3883 | fprintf (lra_dump_file, " (sp_off=%" HOST_WIDE_INT_PRINT "d)", | |
3884 | curr_id->sp_offset); | |
36ff9dfb | 3885 | fprintf (lra_dump_file, "\n"); |
55a2c322 VM |
3886 | } |
3887 | ||
3888 | /* Right now, for any pair of operands I and J that are required to | |
3889 | match, with J < I, goal_alt_matches[I] is J. Add I to | |
3890 | goal_alt_matched[J]. */ | |
f4eafc30 | 3891 | |
55a2c322 VM |
3892 | for (i = 0; i < n_operands; i++) |
3893 | if ((j = goal_alt_matches[i]) >= 0) | |
3894 | { | |
3895 | for (k = 0; goal_alt_matched[j][k] >= 0; k++) | |
3896 | ; | |
3897 | /* We allow matching one output operand and several input | |
3898 | operands. */ | |
3899 | lra_assert (k == 0 | |
3900 | || (curr_static_id->operand[j].type == OP_OUT | |
3901 | && curr_static_id->operand[i].type == OP_IN | |
3902 | && (curr_static_id->operand | |
3903 | [goal_alt_matched[j][0]].type == OP_IN))); | |
3904 | goal_alt_matched[j][k] = i; | |
3905 | goal_alt_matched[j][k + 1] = -1; | |
3906 | } | |
f4eafc30 | 3907 | |
55a2c322 VM |
3908 | for (i = 0; i < n_operands; i++) |
3909 | goal_alt_win[i] |= goal_alt_match_win[i]; | |
f4eafc30 | 3910 | |
55a2c322 VM |
3911 | /* Any constants that aren't allowed and can't be reloaded into |
3912 | registers are here changed into memory references. */ | |
3913 | for (i = 0; i < n_operands; i++) | |
3914 | if (goal_alt_win[i]) | |
3915 | { | |
3916 | int regno; | |
3917 | enum reg_class new_class; | |
3918 | rtx reg = *curr_id->operand_loc[i]; | |
3919 | ||
3920 | if (GET_CODE (reg) == SUBREG) | |
3921 | reg = SUBREG_REG (reg); | |
f4eafc30 | 3922 | |
55a2c322 VM |
3923 | if (REG_P (reg) && (regno = REGNO (reg)) >= FIRST_PSEUDO_REGISTER) |
3924 | { | |
3925 | bool ok_p = in_class_p (reg, goal_alt[i], &new_class); | |
3926 | ||
3927 | if (new_class != NO_REGS && get_reg_class (regno) != new_class) | |
3928 | { | |
3929 | lra_assert (ok_p); | |
a2d0d374 | 3930 | lra_change_class (regno, new_class, " Change to", true); |
55a2c322 VM |
3931 | } |
3932 | } | |
3933 | } | |
3934 | else | |
3935 | { | |
3936 | const char *constraint; | |
3937 | char c; | |
3938 | rtx op = *curr_id->operand_loc[i]; | |
3939 | rtx subreg = NULL_RTX; | |
ef4bddc2 | 3940 | machine_mode mode = curr_operand_mode[i]; |
f4eafc30 | 3941 | |
55a2c322 VM |
3942 | if (GET_CODE (op) == SUBREG) |
3943 | { | |
3944 | subreg = op; | |
3945 | op = SUBREG_REG (op); | |
3946 | mode = GET_MODE (op); | |
3947 | } | |
f4eafc30 | 3948 | |
55a2c322 VM |
3949 | if (CONST_POOL_OK_P (mode, op) |
3950 | && ((targetm.preferred_reload_class | |
3951 | (op, (enum reg_class) goal_alt[i]) == NO_REGS) | |
3952 | || no_input_reloads_p)) | |
3953 | { | |
3954 | rtx tem = force_const_mem (mode, op); | |
f4eafc30 | 3955 | |
55a2c322 VM |
3956 | change_p = true; |
3957 | if (subreg != NULL_RTX) | |
3958 | tem = gen_rtx_SUBREG (mode, tem, SUBREG_BYTE (subreg)); | |
f4eafc30 | 3959 | |
55a2c322 VM |
3960 | *curr_id->operand_loc[i] = tem; |
3961 | lra_update_dup (curr_id, i); | |
d9cf932c | 3962 | process_address (i, false, &before, &after); |
f4eafc30 | 3963 | |
55a2c322 VM |
3964 | /* If the alternative accepts constant pool refs directly |
3965 | there will be no reload needed at all. */ | |
3966 | if (subreg != NULL_RTX) | |
3967 | continue; | |
3968 | /* Skip alternatives before the one requested. */ | |
3969 | constraint = (curr_static_id->operand_alternative | |
3970 | [goal_alt_number * n_operands + i].constraint); | |
3971 | for (; | |
3972 | (c = *constraint) && c != ',' && c != '#'; | |
3973 | constraint += CONSTRAINT_LEN (c, constraint)) | |
3974 | { | |
777e635f | 3975 | enum constraint_num cn = lookup_constraint (constraint); |
9eb1ca69 VM |
3976 | if ((insn_extra_memory_constraint (cn) |
3977 | || insn_extra_special_memory_constraint (cn)) | |
777e635f | 3978 | && satisfies_memory_constraint_p (tem, cn)) |
55a2c322 | 3979 | break; |
55a2c322 VM |
3980 | } |
3981 | if (c == '\0' || c == ',' || c == '#') | |
3982 | continue; | |
f4eafc30 | 3983 | |
55a2c322 VM |
3984 | goal_alt_win[i] = true; |
3985 | } | |
3986 | } | |
f4eafc30 | 3987 | |
aefae0f1 TP |
3988 | n_outputs = 0; |
3989 | outputs[0] = -1; | |
55a2c322 VM |
3990 | for (i = 0; i < n_operands; i++) |
3991 | { | |
2b778c9d VM |
3992 | int regno; |
3993 | bool optional_p = false; | |
55a2c322 VM |
3994 | rtx old, new_reg; |
3995 | rtx op = *curr_id->operand_loc[i]; | |
3996 | ||
3997 | if (goal_alt_win[i]) | |
3998 | { | |
3999 | if (goal_alt[i] == NO_REGS | |
4000 | && REG_P (op) | |
4001 | /* When we assign NO_REGS it means that we will not | |
4002 | assign a hard register to the scratch pseudo by | |
4003 | assigment pass and the scratch pseudo will be | |
4004 | spilled. Spilled scratch pseudos are transformed | |
4005 | back to scratches at the LRA end. */ | |
6c051d60 VM |
4006 | && lra_former_scratch_operand_p (curr_insn, i) |
4007 | && lra_former_scratch_p (REGNO (op))) | |
deca73f5 VM |
4008 | { |
4009 | int regno = REGNO (op); | |
a2d0d374 | 4010 | lra_change_class (regno, NO_REGS, " Change to", true); |
deca73f5 VM |
4011 | if (lra_get_regno_hard_regno (regno) >= 0) |
4012 | /* We don't have to mark all insn affected by the | |
4013 | spilled pseudo as there is only one such insn, the | |
4014 | current one. */ | |
4015 | reg_renumber[regno] = -1; | |
6c051d60 VM |
4016 | lra_assert (bitmap_single_bit_set_p |
4017 | (&lra_reg_info[REGNO (op)].insn_bitmap)); | |
deca73f5 | 4018 | } |
2b778c9d VM |
4019 | /* We can do an optional reload. If the pseudo got a hard |
4020 | reg, we might improve the code through inheritance. If | |
4021 | it does not get a hard register we coalesce memory/memory | |
4022 | moves later. Ignore move insns to avoid cycling. */ | |
b0681c9e | 4023 | if (! lra_simple_p |
2b778c9d VM |
4024 | && lra_undo_inheritance_iter < LRA_MAX_INHERITANCE_PASSES |
4025 | && goal_alt[i] != NO_REGS && REG_P (op) | |
4026 | && (regno = REGNO (op)) >= FIRST_PSEUDO_REGISTER | |
a2d0d374 | 4027 | && regno < new_regno_start |
b0681c9e | 4028 | && ! lra_former_scratch_p (regno) |
2b778c9d | 4029 | && reg_renumber[regno] < 0 |
3c954213 VM |
4030 | /* Check that the optional reload pseudo will be able to |
4031 | hold given mode value. */ | |
4032 | && ! (prohibited_class_reg_set_mode_p | |
4033 | (goal_alt[i], reg_class_contents[goal_alt[i]], | |
4034 | PSEUDO_REGNO_MODE (regno))) | |
2b778c9d | 4035 | && (curr_insn_set == NULL_RTX |
b0681c9e VM |
4036 | || !((REG_P (SET_SRC (curr_insn_set)) |
4037 | || MEM_P (SET_SRC (curr_insn_set)) | |
4038 | || GET_CODE (SET_SRC (curr_insn_set)) == SUBREG) | |
4039 | && (REG_P (SET_DEST (curr_insn_set)) | |
4040 | || MEM_P (SET_DEST (curr_insn_set)) | |
4041 | || GET_CODE (SET_DEST (curr_insn_set)) == SUBREG)))) | |
2b778c9d VM |
4042 | optional_p = true; |
4043 | else | |
4044 | continue; | |
55a2c322 | 4045 | } |
f4eafc30 | 4046 | |
55a2c322 VM |
4047 | /* Operands that match previous ones have already been handled. */ |
4048 | if (goal_alt_matches[i] >= 0) | |
4049 | continue; | |
4050 | ||
4051 | /* We should not have an operand with a non-offsettable address | |
4052 | appearing where an offsettable address will do. It also may | |
4053 | be a case when the address should be special in other words | |
4054 | not a general one (e.g. it needs no index reg). */ | |
4055 | if (goal_alt_matched[i][0] == -1 && goal_alt_offmemok[i] && MEM_P (op)) | |
4056 | { | |
4057 | enum reg_class rclass; | |
4058 | rtx *loc = &XEXP (op, 0); | |
4059 | enum rtx_code code = GET_CODE (*loc); | |
4060 | ||
4061 | push_to_sequence (before); | |
4062 | rclass = base_reg_class (GET_MODE (op), MEM_ADDR_SPACE (op), | |
4063 | MEM, SCRATCH); | |
4064 | if (GET_RTX_CLASS (code) == RTX_AUTOINC) | |
4065 | new_reg = emit_inc (rclass, *loc, *loc, | |
4066 | /* This value does not matter for MODIFY. */ | |
4067 | GET_MODE_SIZE (GET_MODE (op))); | |
95921002 | 4068 | else if (get_reload_reg (OP_IN, Pmode, *loc, rclass, FALSE, |
55a2c322 VM |
4069 | "offsetable address", &new_reg)) |
4070 | lra_emit_move (new_reg, *loc); | |
4071 | before = get_insns (); | |
4072 | end_sequence (); | |
4073 | *loc = new_reg; | |
4074 | lra_update_dup (curr_id, i); | |
4075 | } | |
4076 | else if (goal_alt_matched[i][0] == -1) | |
4077 | { | |
ef4bddc2 | 4078 | machine_mode mode; |
55a2c322 VM |
4079 | rtx reg, *loc; |
4080 | int hard_regno, byte; | |
4081 | enum op_type type = curr_static_id->operand[i].type; | |
4082 | ||
4083 | loc = curr_id->operand_loc[i]; | |
4084 | mode = curr_operand_mode[i]; | |
4085 | if (GET_CODE (*loc) == SUBREG) | |
4086 | { | |
4087 | reg = SUBREG_REG (*loc); | |
4088 | byte = SUBREG_BYTE (*loc); | |
4089 | if (REG_P (reg) | |
4090 | /* Strict_low_part requires reload the register not | |
4091 | the sub-register. */ | |
4092 | && (curr_static_id->operand[i].strict_low | |
4093 | || (GET_MODE_SIZE (mode) | |
4094 | <= GET_MODE_SIZE (GET_MODE (reg)) | |
4095 | && (hard_regno | |
4096 | = get_try_hard_regno (REGNO (reg))) >= 0 | |
4097 | && (simplify_subreg_regno | |
4098 | (hard_regno, | |
4099 | GET_MODE (reg), byte, mode) < 0) | |
4100 | && (goal_alt[i] == NO_REGS | |
4101 | || (simplify_subreg_regno | |
4102 | (ira_class_hard_regs[goal_alt[i]][0], | |
4103 | GET_MODE (reg), byte, mode) >= 0))))) | |
4104 | { | |
8b8e23de RS |
4105 | if (type == OP_OUT) |
4106 | type = OP_INOUT; | |
55a2c322 VM |
4107 | loc = &SUBREG_REG (*loc); |
4108 | mode = GET_MODE (*loc); | |
4109 | } | |
4110 | } | |
4111 | old = *loc; | |
95921002 VM |
4112 | if (get_reload_reg (type, mode, old, goal_alt[i], |
4113 | loc != curr_id->operand_loc[i], "", &new_reg) | |
55a2c322 VM |
4114 | && type != OP_OUT) |
4115 | { | |
4116 | push_to_sequence (before); | |
4117 | lra_emit_move (new_reg, old); | |
4118 | before = get_insns (); | |
4119 | end_sequence (); | |
4120 | } | |
4121 | *loc = new_reg; | |
4122 | if (type != OP_IN | |
4123 | && find_reg_note (curr_insn, REG_UNUSED, old) == NULL_RTX) | |
4124 | { | |
4125 | start_sequence (); | |
4126 | lra_emit_move (type == OP_INOUT ? copy_rtx (old) : old, new_reg); | |
4127 | emit_insn (after); | |
4128 | after = get_insns (); | |
4129 | end_sequence (); | |
4130 | *loc = new_reg; | |
4131 | } | |
4132 | for (j = 0; j < goal_alt_dont_inherit_ops_num; j++) | |
4133 | if (goal_alt_dont_inherit_ops[j] == i) | |
4134 | { | |
4135 | lra_set_regno_unique_value (REGNO (new_reg)); | |
4136 | break; | |
4137 | } | |
4138 | lra_update_dup (curr_id, i); | |
4139 | } | |
4140 | else if (curr_static_id->operand[i].type == OP_IN | |
4141 | && (curr_static_id->operand[goal_alt_matched[i][0]].type | |
4142 | == OP_OUT)) | |
4143 | { | |
511dcace VM |
4144 | /* generate reloads for input and matched outputs. */ |
4145 | match_inputs[0] = i; | |
4146 | match_inputs[1] = -1; | |
aefae0f1 | 4147 | match_reload (goal_alt_matched[i][0], match_inputs, outputs, |
599e1cf8 VM |
4148 | goal_alt[i], &before, &after, |
4149 | curr_static_id->operand_alternative | |
4150 | [goal_alt_number * n_operands + goal_alt_matched[i][0]] | |
4151 | .earlyclobber); | |
55a2c322 VM |
4152 | } |
4153 | else if (curr_static_id->operand[i].type == OP_OUT | |
4154 | && (curr_static_id->operand[goal_alt_matched[i][0]].type | |
4155 | == OP_IN)) | |
511dcace | 4156 | /* Generate reloads for output and matched inputs. */ |
aefae0f1 TP |
4157 | match_reload (i, goal_alt_matched[i], outputs, goal_alt[i], &before, |
4158 | &after, curr_static_id->operand_alternative | |
4159 | [goal_alt_number * n_operands + i].earlyclobber); | |
511dcace VM |
4160 | else if (curr_static_id->operand[i].type == OP_IN |
4161 | && (curr_static_id->operand[goal_alt_matched[i][0]].type | |
4162 | == OP_IN)) | |
4163 | { | |
4164 | /* Generate reloads for matched inputs. */ | |
4165 | match_inputs[0] = i; | |
4166 | for (j = 0; (k = goal_alt_matched[i][j]) >= 0; j++) | |
4167 | match_inputs[j + 1] = k; | |
4168 | match_inputs[j + 1] = -1; | |
aefae0f1 TP |
4169 | match_reload (-1, match_inputs, outputs, goal_alt[i], &before, |
4170 | &after, false); | |
511dcace | 4171 | } |
55a2c322 VM |
4172 | else |
4173 | /* We must generate code in any case when function | |
4174 | process_alt_operands decides that it is possible. */ | |
4175 | gcc_unreachable (); | |
aefae0f1 TP |
4176 | |
4177 | /* Memorise processed outputs so that output remaining to be processed | |
4178 | can avoid using the same register value (see match_reload). */ | |
4179 | if (curr_static_id->operand[i].type == OP_OUT) | |
4180 | { | |
4181 | outputs[n_outputs++] = i; | |
4182 | outputs[n_outputs] = -1; | |
4183 | } | |
4184 | ||
2b778c9d VM |
4185 | if (optional_p) |
4186 | { | |
8a8330b7 VM |
4187 | rtx reg = op; |
4188 | ||
4189 | lra_assert (REG_P (reg)); | |
4190 | regno = REGNO (reg); | |
2b778c9d VM |
4191 | op = *curr_id->operand_loc[i]; /* Substitution. */ |
4192 | if (GET_CODE (op) == SUBREG) | |
4193 | op = SUBREG_REG (op); | |
4194 | gcc_assert (REG_P (op) && (int) REGNO (op) >= new_regno_start); | |
4195 | bitmap_set_bit (&lra_optional_reload_pseudos, REGNO (op)); | |
8a8330b7 | 4196 | lra_reg_info[REGNO (op)].restore_rtx = reg; |
2b778c9d VM |
4197 | if (lra_dump_file != NULL) |
4198 | fprintf (lra_dump_file, | |
4199 | " Making reload reg %d for reg %d optional\n", | |
4200 | REGNO (op), regno); | |
4201 | } | |
55a2c322 VM |
4202 | } |
4203 | if (before != NULL_RTX || after != NULL_RTX | |
4204 | || max_regno_before != max_reg_num ()) | |
4205 | change_p = true; | |
4206 | if (change_p) | |
4207 | { | |
4208 | lra_update_operator_dups (curr_id); | |
4209 | /* Something changes -- process the insn. */ | |
4210 | lra_update_insn_regno_info (curr_insn); | |
4211 | } | |
4212 | lra_process_new_insns (curr_insn, before, after, "Inserting insn reload"); | |
4213 | return change_p; | |
4214 | } | |
4215 | ||
d9cf932c VM |
4216 | /* Return true if INSN satisfies all constraints. In other words, no |
4217 | reload insns are needed. */ | |
4218 | bool | |
4219 | lra_constrain_insn (rtx_insn *insn) | |
4220 | { | |
4221 | int saved_new_regno_start = new_regno_start; | |
4222 | int saved_new_insn_uid_start = new_insn_uid_start; | |
4223 | bool change_p; | |
4224 | ||
4225 | curr_insn = insn; | |
4226 | curr_id = lra_get_insn_recog_data (curr_insn); | |
4227 | curr_static_id = curr_id->insn_static_data; | |
4228 | new_insn_uid_start = get_max_uid (); | |
4229 | new_regno_start = max_reg_num (); | |
4230 | change_p = curr_insn_transform (true); | |
4231 | new_regno_start = saved_new_regno_start; | |
4232 | new_insn_uid_start = saved_new_insn_uid_start; | |
4233 | return ! change_p; | |
4234 | } | |
4235 | ||
55a2c322 VM |
4236 | /* Return true if X is in LIST. */ |
4237 | static bool | |
4238 | in_list_p (rtx x, rtx list) | |
4239 | { | |
4240 | for (; list != NULL_RTX; list = XEXP (list, 1)) | |
4241 | if (XEXP (list, 0) == x) | |
4242 | return true; | |
4243 | return false; | |
4244 | } | |
4245 | ||
4246 | /* Return true if X contains an allocatable hard register (if | |
4247 | HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */ | |
4248 | static bool | |
4249 | contains_reg_p (rtx x, bool hard_reg_p, bool spilled_p) | |
4250 | { | |
4251 | int i, j; | |
4252 | const char *fmt; | |
4253 | enum rtx_code code; | |
4254 | ||
4255 | code = GET_CODE (x); | |
4256 | if (REG_P (x)) | |
4257 | { | |
4258 | int regno = REGNO (x); | |
4259 | HARD_REG_SET alloc_regs; | |
4260 | ||
4261 | if (hard_reg_p) | |
4262 | { | |
4263 | if (regno >= FIRST_PSEUDO_REGISTER) | |
4264 | regno = lra_get_regno_hard_regno (regno); | |
4265 | if (regno < 0) | |
4266 | return false; | |
4267 | COMPL_HARD_REG_SET (alloc_regs, lra_no_alloc_regs); | |
4268 | return overlaps_hard_reg_set_p (alloc_regs, GET_MODE (x), regno); | |
4269 | } | |
4270 | else | |
4271 | { | |
4272 | if (regno < FIRST_PSEUDO_REGISTER) | |
4273 | return false; | |
4274 | if (! spilled_p) | |
4275 | return true; | |
4276 | return lra_get_regno_hard_regno (regno) < 0; | |
4277 | } | |
4278 | } | |
4279 | fmt = GET_RTX_FORMAT (code); | |
4280 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
4281 | { | |
4282 | if (fmt[i] == 'e') | |
4283 | { | |
4284 | if (contains_reg_p (XEXP (x, i), hard_reg_p, spilled_p)) | |
4285 | return true; | |
4286 | } | |
4287 | else if (fmt[i] == 'E') | |
4288 | { | |
4289 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
4290 | if (contains_reg_p (XVECEXP (x, i, j), hard_reg_p, spilled_p)) | |
4291 | return true; | |
4292 | } | |
4293 | } | |
4294 | return false; | |
4295 | } | |
4296 | ||
28430b2e VM |
4297 | /* Process all regs in location *LOC and change them on equivalent |
4298 | substitution. Return true if any change was done. */ | |
55a2c322 | 4299 | static bool |
28430b2e | 4300 | loc_equivalence_change_p (rtx *loc) |
55a2c322 VM |
4301 | { |
4302 | rtx subst, reg, x = *loc; | |
4303 | bool result = false; | |
4304 | enum rtx_code code = GET_CODE (x); | |
4305 | const char *fmt; | |
4306 | int i, j; | |
4307 | ||
4308 | if (code == SUBREG) | |
4309 | { | |
4310 | reg = SUBREG_REG (x); | |
8d49e7ef | 4311 | if ((subst = get_equiv_with_elimination (reg, curr_insn)) != reg |
55a2c322 VM |
4312 | && GET_MODE (subst) == VOIDmode) |
4313 | { | |
4314 | /* We cannot reload debug location. Simplify subreg here | |
4315 | while we know the inner mode. */ | |
4316 | *loc = simplify_gen_subreg (GET_MODE (x), subst, | |
4317 | GET_MODE (reg), SUBREG_BYTE (x)); | |
4318 | return true; | |
4319 | } | |
4320 | } | |
8d49e7ef | 4321 | if (code == REG && (subst = get_equiv_with_elimination (x, curr_insn)) != x) |
55a2c322 VM |
4322 | { |
4323 | *loc = subst; | |
4324 | return true; | |
4325 | } | |
4326 | ||
4327 | /* Scan all the operand sub-expressions. */ | |
4328 | fmt = GET_RTX_FORMAT (code); | |
4329 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
4330 | { | |
4331 | if (fmt[i] == 'e') | |
28430b2e | 4332 | result = loc_equivalence_change_p (&XEXP (x, i)) || result; |
55a2c322 VM |
4333 | else if (fmt[i] == 'E') |
4334 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
4335 | result | |
28430b2e | 4336 | = loc_equivalence_change_p (&XVECEXP (x, i, j)) || result; |
55a2c322 VM |
4337 | } |
4338 | return result; | |
4339 | } | |
4340 | ||
d0608e59 | 4341 | /* Similar to loc_equivalence_change_p, but for use as |
4c2b2d79 VM |
4342 | simplify_replace_fn_rtx callback. DATA is insn for which the |
4343 | elimination is done. If it null we don't do the elimination. */ | |
d0608e59 | 4344 | static rtx |
4c2b2d79 | 4345 | loc_equivalence_callback (rtx loc, const_rtx, void *data) |
d0608e59 JJ |
4346 | { |
4347 | if (!REG_P (loc)) | |
4348 | return NULL_RTX; | |
4349 | ||
4c2b2d79 | 4350 | rtx subst = (data == NULL |
cfa434f6 | 4351 | ? get_equiv (loc) : get_equiv_with_elimination (loc, (rtx_insn *) data)); |
d0608e59 JJ |
4352 | if (subst != loc) |
4353 | return subst; | |
4354 | ||
4355 | return NULL_RTX; | |
4356 | } | |
4357 | ||
55a2c322 VM |
4358 | /* Maximum number of generated reload insns per an insn. It is for |
4359 | preventing this pass cycling in a bug case. */ | |
4360 | #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS | |
4361 | ||
4362 | /* The current iteration number of this LRA pass. */ | |
4363 | int lra_constraint_iter; | |
4364 | ||
55a2c322 VM |
4365 | /* True if we substituted equiv which needs checking register |
4366 | allocation correctness because the equivalent value contains | |
4367 | allocatable hard registers or when we restore multi-register | |
4368 | pseudo. */ | |
4369 | bool lra_risky_transformations_p; | |
4370 | ||
4371 | /* Return true if REGNO is referenced in more than one block. */ | |
4372 | static bool | |
4373 | multi_block_pseudo_p (int regno) | |
4374 | { | |
4375 | basic_block bb = NULL; | |
4376 | unsigned int uid; | |
4377 | bitmap_iterator bi; | |
f4eafc30 | 4378 | |
55a2c322 VM |
4379 | if (regno < FIRST_PSEUDO_REGISTER) |
4380 | return false; | |
f4eafc30 | 4381 | |
55a2c322 VM |
4382 | EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi) |
4383 | if (bb == NULL) | |
4384 | bb = BLOCK_FOR_INSN (lra_insn_recog_data[uid]->insn); | |
4385 | else if (BLOCK_FOR_INSN (lra_insn_recog_data[uid]->insn) != bb) | |
4386 | return true; | |
4387 | return false; | |
4388 | } | |
4389 | ||
1966c91b VM |
4390 | /* Return true if LIST contains a deleted insn. */ |
4391 | static bool | |
0cc97fc5 | 4392 | contains_deleted_insn_p (rtx_insn_list *list) |
1966c91b | 4393 | { |
0cc97fc5 DM |
4394 | for (; list != NULL_RTX; list = list->next ()) |
4395 | if (NOTE_P (list->insn ()) | |
4396 | && NOTE_KIND (list->insn ()) == NOTE_INSN_DELETED) | |
1966c91b VM |
4397 | return true; |
4398 | return false; | |
4399 | } | |
4400 | ||
55a2c322 VM |
4401 | /* Return true if X contains a pseudo dying in INSN. */ |
4402 | static bool | |
605780f6 | 4403 | dead_pseudo_p (rtx x, rtx_insn *insn) |
55a2c322 VM |
4404 | { |
4405 | int i, j; | |
4406 | const char *fmt; | |
4407 | enum rtx_code code; | |
4408 | ||
4409 | if (REG_P (x)) | |
4410 | return (insn != NULL_RTX | |
4411 | && find_regno_note (insn, REG_DEAD, REGNO (x)) != NULL_RTX); | |
4412 | code = GET_CODE (x); | |
4413 | fmt = GET_RTX_FORMAT (code); | |
4414 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
4415 | { | |
4416 | if (fmt[i] == 'e') | |
4417 | { | |
4418 | if (dead_pseudo_p (XEXP (x, i), insn)) | |
4419 | return true; | |
4420 | } | |
4421 | else if (fmt[i] == 'E') | |
4422 | { | |
4423 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
4424 | if (dead_pseudo_p (XVECEXP (x, i, j), insn)) | |
4425 | return true; | |
4426 | } | |
4427 | } | |
4428 | return false; | |
4429 | } | |
4430 | ||
4431 | /* Return true if INSN contains a dying pseudo in INSN right hand | |
4432 | side. */ | |
4433 | static bool | |
e8a54173 | 4434 | insn_rhs_dead_pseudo_p (rtx_insn *insn) |
55a2c322 VM |
4435 | { |
4436 | rtx set = single_set (insn); | |
4437 | ||
4438 | gcc_assert (set != NULL); | |
4439 | return dead_pseudo_p (SET_SRC (set), insn); | |
4440 | } | |
4441 | ||
4442 | /* Return true if any init insn of REGNO contains a dying pseudo in | |
4443 | insn right hand side. */ | |
4444 | static bool | |
4445 | init_insn_rhs_dead_pseudo_p (int regno) | |
4446 | { | |
0cc97fc5 | 4447 | rtx_insn_list *insns = ira_reg_equiv[regno].init_insns; |
55a2c322 VM |
4448 | |
4449 | if (insns == NULL) | |
4450 | return false; | |
0cc97fc5 DM |
4451 | for (; insns != NULL_RTX; insns = insns->next ()) |
4452 | if (insn_rhs_dead_pseudo_p (insns->insn ())) | |
55a2c322 VM |
4453 | return true; |
4454 | return false; | |
4455 | } | |
4456 | ||
01e54ef8 VM |
4457 | /* Return TRUE if REGNO has a reverse equivalence. The equivalence is |
4458 | reverse only if we have one init insn with given REGNO as a | |
4459 | source. */ | |
4460 | static bool | |
4461 | reverse_equiv_p (int regno) | |
4462 | { | |
0cc97fc5 DM |
4463 | rtx_insn_list *insns = ira_reg_equiv[regno].init_insns; |
4464 | rtx set; | |
01e54ef8 | 4465 | |
0cc97fc5 | 4466 | if (insns == NULL) |
01e54ef8 | 4467 | return false; |
0cc97fc5 DM |
4468 | if (! INSN_P (insns->insn ()) |
4469 | || insns->next () != NULL) | |
01e54ef8 | 4470 | return false; |
0cc97fc5 | 4471 | if ((set = single_set (insns->insn ())) == NULL_RTX) |
01e54ef8 VM |
4472 | return false; |
4473 | return REG_P (SET_SRC (set)) && (int) REGNO (SET_SRC (set)) == regno; | |
4474 | } | |
4475 | ||
4476 | /* Return TRUE if REGNO was reloaded in an equivalence init insn. We | |
4477 | call this function only for non-reverse equivalence. */ | |
4478 | static bool | |
4479 | contains_reloaded_insn_p (int regno) | |
4480 | { | |
4481 | rtx set; | |
0cc97fc5 | 4482 | rtx_insn_list *list = ira_reg_equiv[regno].init_insns; |
01e54ef8 | 4483 | |
0cc97fc5 DM |
4484 | for (; list != NULL; list = list->next ()) |
4485 | if ((set = single_set (list->insn ())) == NULL_RTX | |
01e54ef8 VM |
4486 | || ! REG_P (SET_DEST (set)) |
4487 | || (int) REGNO (SET_DEST (set)) != regno) | |
4488 | return true; | |
4489 | return false; | |
4490 | } | |
4491 | ||
55a2c322 VM |
4492 | /* Entry function of LRA constraint pass. Return true if the |
4493 | constraint pass did change the code. */ | |
4494 | bool | |
4495 | lra_constraints (bool first_p) | |
4496 | { | |
4497 | bool changed_p; | |
4498 | int i, hard_regno, new_insns_num; | |
6cd1dd26 VM |
4499 | unsigned int min_len, new_min_len, uid; |
4500 | rtx set, x, reg, dest_reg; | |
55a2c322 | 4501 | basic_block last_bb; |
6cd1dd26 VM |
4502 | bitmap_head equiv_insn_bitmap; |
4503 | bitmap_iterator bi; | |
55a2c322 VM |
4504 | |
4505 | lra_constraint_iter++; | |
4506 | if (lra_dump_file != NULL) | |
4507 | fprintf (lra_dump_file, "\n********** Local #%d: **********\n\n", | |
4508 | lra_constraint_iter); | |
55a2c322 | 4509 | changed_p = false; |
bcb21886 KY |
4510 | if (pic_offset_table_rtx |
4511 | && REGNO (pic_offset_table_rtx) >= FIRST_PSEUDO_REGISTER) | |
4512 | lra_risky_transformations_p = true; | |
4513 | else | |
4514 | lra_risky_transformations_p = false; | |
55a2c322 VM |
4515 | new_insn_uid_start = get_max_uid (); |
4516 | new_regno_start = first_p ? lra_constraint_new_regno_start : max_reg_num (); | |
8d49e7ef VM |
4517 | /* Mark used hard regs for target stack size calulations. */ |
4518 | for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++) | |
4519 | if (lra_reg_info[i].nrefs != 0 | |
4520 | && (hard_regno = lra_get_regno_hard_regno (i)) >= 0) | |
4521 | { | |
4522 | int j, nregs; | |
4523 | ||
4524 | nregs = hard_regno_nregs[hard_regno][lra_reg_info[i].biggest_mode]; | |
4525 | for (j = 0; j < nregs; j++) | |
4526 | df_set_regs_ever_live (hard_regno + j, true); | |
4527 | } | |
4528 | /* Do elimination before the equivalence processing as we can spill | |
4529 | some pseudos during elimination. */ | |
4530 | lra_eliminate (false, first_p); | |
6cd1dd26 | 4531 | bitmap_initialize (&equiv_insn_bitmap, ®_obstack); |
55a2c322 VM |
4532 | for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++) |
4533 | if (lra_reg_info[i].nrefs != 0) | |
4534 | { | |
4535 | ira_reg_equiv[i].profitable_p = true; | |
6cd1dd26 | 4536 | reg = regno_reg_rtx[i]; |
8d49e7ef | 4537 | if (lra_get_regno_hard_regno (i) < 0 && (x = get_equiv (reg)) != reg) |
55a2c322 VM |
4538 | { |
4539 | bool pseudo_p = contains_reg_p (x, false, false); | |
55a2c322 | 4540 | |
1966c91b VM |
4541 | /* After RTL transformation, we can not guarantee that |
4542 | pseudo in the substitution was not reloaded which might | |
4543 | make equivalence invalid. For example, in reverse | |
4544 | equiv of p0 | |
4545 | ||
4546 | p0 <- ... | |
4547 | ... | |
4548 | equiv_mem <- p0 | |
4549 | ||
4550 | the memory address register was reloaded before the 2nd | |
4551 | insn. */ | |
4552 | if ((! first_p && pseudo_p) | |
4553 | /* We don't use DF for compilation speed sake. So it | |
4554 | is problematic to update live info when we use an | |
4555 | equivalence containing pseudos in more than one | |
4556 | BB. */ | |
4557 | || (pseudo_p && multi_block_pseudo_p (i)) | |
4558 | /* If an init insn was deleted for some reason, cancel | |
4559 | the equiv. We could update the equiv insns after | |
4560 | transformations including an equiv insn deletion | |
4561 | but it is not worthy as such cases are extremely | |
4562 | rare. */ | |
4563 | || contains_deleted_insn_p (ira_reg_equiv[i].init_insns) | |
55a2c322 VM |
4564 | /* If it is not a reverse equivalence, we check that a |
4565 | pseudo in rhs of the init insn is not dying in the | |
4566 | insn. Otherwise, the live info at the beginning of | |
4567 | the corresponding BB might be wrong after we | |
4568 | removed the insn. When the equiv can be a | |
4569 | constant, the right hand side of the init insn can | |
4570 | be a pseudo. */ | |
01e54ef8 VM |
4571 | || (! reverse_equiv_p (i) |
4572 | && (init_insn_rhs_dead_pseudo_p (i) | |
4573 | /* If we reloaded the pseudo in an equivalence | |
4574 | init insn, we can not remove the equiv init | |
4575 | insns and the init insns might write into | |
4576 | const memory in this case. */ | |
4577 | || contains_reloaded_insn_p (i))) | |
b28ece32 VM |
4578 | /* Prevent access beyond equivalent memory for |
4579 | paradoxical subregs. */ | |
4580 | || (MEM_P (x) | |
4581 | && (GET_MODE_SIZE (lra_reg_info[i].biggest_mode) | |
bcb21886 KY |
4582 | > GET_MODE_SIZE (GET_MODE (x)))) |
4583 | || (pic_offset_table_rtx | |
4584 | && ((CONST_POOL_OK_P (PSEUDO_REGNO_MODE (i), x) | |
4585 | && (targetm.preferred_reload_class | |
4586 | (x, lra_get_allocno_class (i)) == NO_REGS)) | |
b81a2f0d | 4587 | || contains_symbol_ref_p (x)))) |
55a2c322 | 4588 | ira_reg_equiv[i].defined_p = false; |
55a2c322 VM |
4589 | if (contains_reg_p (x, false, true)) |
4590 | ira_reg_equiv[i].profitable_p = false; | |
8d49e7ef | 4591 | if (get_equiv (reg) != reg) |
6cd1dd26 | 4592 | bitmap_ior_into (&equiv_insn_bitmap, &lra_reg_info[i].insn_bitmap); |
55a2c322 VM |
4593 | } |
4594 | } | |
4c2b2d79 VM |
4595 | for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++) |
4596 | update_equiv (i); | |
6cd1dd26 VM |
4597 | /* We should add all insns containing pseudos which should be |
4598 | substituted by their equivalences. */ | |
4599 | EXECUTE_IF_SET_IN_BITMAP (&equiv_insn_bitmap, 0, uid, bi) | |
4600 | lra_push_insn_by_uid (uid); | |
55a2c322 VM |
4601 | min_len = lra_insn_stack_length (); |
4602 | new_insns_num = 0; | |
4603 | last_bb = NULL; | |
4604 | changed_p = false; | |
4605 | while ((new_min_len = lra_insn_stack_length ()) != 0) | |
4606 | { | |
4607 | curr_insn = lra_pop_insn (); | |
4608 | --new_min_len; | |
f4eafc30 | 4609 | curr_bb = BLOCK_FOR_INSN (curr_insn); |
55a2c322 VM |
4610 | if (curr_bb != last_bb) |
4611 | { | |
4612 | last_bb = curr_bb; | |
4613 | bb_reload_num = lra_curr_reload_num; | |
4614 | } | |
4615 | if (min_len > new_min_len) | |
4616 | { | |
4617 | min_len = new_min_len; | |
4618 | new_insns_num = 0; | |
4619 | } | |
4620 | if (new_insns_num > MAX_RELOAD_INSNS_NUMBER) | |
4621 | internal_error | |
4622 | ("Max. number of generated reload insns per insn is achieved (%d)\n", | |
4623 | MAX_RELOAD_INSNS_NUMBER); | |
4624 | new_insns_num++; | |
4625 | if (DEBUG_INSN_P (curr_insn)) | |
4626 | { | |
4627 | /* We need to check equivalence in debug insn and change | |
4628 | pseudo to the equivalent value if necessary. */ | |
4629 | curr_id = lra_get_insn_recog_data (curr_insn); | |
d0608e59 | 4630 | if (bitmap_bit_p (&equiv_insn_bitmap, INSN_UID (curr_insn))) |
4d64ce5c | 4631 | { |
d0608e59 JJ |
4632 | rtx old = *curr_id->operand_loc[0]; |
4633 | *curr_id->operand_loc[0] | |
4634 | = simplify_replace_fn_rtx (old, NULL_RTX, | |
4c2b2d79 | 4635 | loc_equivalence_callback, curr_insn); |
d0608e59 JJ |
4636 | if (old != *curr_id->operand_loc[0]) |
4637 | { | |
4638 | lra_update_insn_regno_info (curr_insn); | |
4639 | changed_p = true; | |
4640 | } | |
4d64ce5c | 4641 | } |
55a2c322 VM |
4642 | } |
4643 | else if (INSN_P (curr_insn)) | |
4644 | { | |
4645 | if ((set = single_set (curr_insn)) != NULL_RTX) | |
4646 | { | |
4647 | dest_reg = SET_DEST (set); | |
4648 | /* The equivalence pseudo could be set up as SUBREG in a | |
4649 | case when it is a call restore insn in a mode | |
4650 | different from the pseudo mode. */ | |
4651 | if (GET_CODE (dest_reg) == SUBREG) | |
4652 | dest_reg = SUBREG_REG (dest_reg); | |
4653 | if ((REG_P (dest_reg) | |
8d49e7ef | 4654 | && (x = get_equiv (dest_reg)) != dest_reg |
55a2c322 VM |
4655 | /* Remove insns which set up a pseudo whose value |
4656 | can not be changed. Such insns might be not in | |
4657 | init_insns because we don't update equiv data | |
4658 | during insn transformations. | |
5a107a0f | 4659 | |
55a2c322 VM |
4660 | As an example, let suppose that a pseudo got |
4661 | hard register and on the 1st pass was not | |
4662 | changed to equivalent constant. We generate an | |
4663 | additional insn setting up the pseudo because of | |
4664 | secondary memory movement. Then the pseudo is | |
4665 | spilled and we use the equiv constant. In this | |
4666 | case we should remove the additional insn and | |
f6937e32 | 4667 | this insn is not init_insns list. */ |
55a2c322 | 4668 | && (! MEM_P (x) || MEM_READONLY_P (x) |
f6937e32 VM |
4669 | /* Check that this is actually an insn setting |
4670 | up the equivalence. */ | |
55a2c322 VM |
4671 | || in_list_p (curr_insn, |
4672 | ira_reg_equiv | |
4673 | [REGNO (dest_reg)].init_insns))) | |
8d49e7ef | 4674 | || (((x = get_equiv (SET_SRC (set))) != SET_SRC (set)) |
55a2c322 VM |
4675 | && in_list_p (curr_insn, |
4676 | ira_reg_equiv | |
4677 | [REGNO (SET_SRC (set))].init_insns))) | |
4678 | { | |
4679 | /* This is equiv init insn of pseudo which did not get a | |
4680 | hard register -- remove the insn. */ | |
4681 | if (lra_dump_file != NULL) | |
4682 | { | |
4683 | fprintf (lra_dump_file, | |
4684 | " Removing equiv init insn %i (freq=%d)\n", | |
4685 | INSN_UID (curr_insn), | |
fef37404 | 4686 | REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn))); |
cfbeaedf | 4687 | dump_insn_slim (lra_dump_file, curr_insn); |
55a2c322 VM |
4688 | } |
4689 | if (contains_reg_p (x, true, false)) | |
4690 | lra_risky_transformations_p = true; | |
4691 | lra_set_insn_deleted (curr_insn); | |
4692 | continue; | |
4693 | } | |
4694 | } | |
4695 | curr_id = lra_get_insn_recog_data (curr_insn); | |
4696 | curr_static_id = curr_id->insn_static_data; | |
4697 | init_curr_insn_input_reloads (); | |
4698 | init_curr_operand_mode (); | |
d9cf932c | 4699 | if (curr_insn_transform (false)) |
55a2c322 | 4700 | changed_p = true; |
28430b2e VM |
4701 | /* Check non-transformed insns too for equiv change as USE |
4702 | or CLOBBER don't need reloads but can contain pseudos | |
4703 | being changed on their equivalences. */ | |
4704 | else if (bitmap_bit_p (&equiv_insn_bitmap, INSN_UID (curr_insn)) | |
4705 | && loc_equivalence_change_p (&PATTERN (curr_insn))) | |
4706 | { | |
4707 | lra_update_insn_regno_info (curr_insn); | |
4708 | changed_p = true; | |
4709 | } | |
55a2c322 VM |
4710 | } |
4711 | } | |
28430b2e | 4712 | bitmap_clear (&equiv_insn_bitmap); |
55a2c322 VM |
4713 | /* If we used a new hard regno, changed_p should be true because the |
4714 | hard reg is assigned to a new pseudo. */ | |
b2b29377 | 4715 | if (flag_checking && !changed_p) |
55a2c322 VM |
4716 | { |
4717 | for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++) | |
4718 | if (lra_reg_info[i].nrefs != 0 | |
4719 | && (hard_regno = lra_get_regno_hard_regno (i)) >= 0) | |
4720 | { | |
4721 | int j, nregs = hard_regno_nregs[hard_regno][PSEUDO_REGNO_MODE (i)]; | |
f4eafc30 | 4722 | |
55a2c322 VM |
4723 | for (j = 0; j < nregs; j++) |
4724 | lra_assert (df_regs_ever_live_p (hard_regno + j)); | |
4725 | } | |
4726 | } | |
55a2c322 VM |
4727 | return changed_p; |
4728 | } | |
4729 | ||
8a8330b7 VM |
4730 | static void initiate_invariants (void); |
4731 | static void finish_invariants (void); | |
4732 | ||
55a2c322 VM |
4733 | /* Initiate the LRA constraint pass. It is done once per |
4734 | function. */ | |
4735 | void | |
4736 | lra_constraints_init (void) | |
4737 | { | |
8a8330b7 | 4738 | initiate_invariants (); |
55a2c322 VM |
4739 | } |
4740 | ||
4741 | /* Finalize the LRA constraint pass. It is done once per | |
4742 | function. */ | |
4743 | void | |
4744 | lra_constraints_finish (void) | |
4745 | { | |
8a8330b7 VM |
4746 | finish_invariants (); |
4747 | } | |
4748 | ||
4749 | \f | |
4750 | ||
4751 | /* Structure describes invariants for ineheritance. */ | |
eb0f8780 | 4752 | struct lra_invariant |
8a8330b7 VM |
4753 | { |
4754 | /* The order number of the invariant. */ | |
4755 | int num; | |
4756 | /* The invariant RTX. */ | |
4757 | rtx invariant_rtx; | |
4758 | /* The origin insn of the invariant. */ | |
4759 | rtx_insn *insn; | |
4760 | }; | |
4761 | ||
eb0f8780 | 4762 | typedef lra_invariant invariant_t; |
8a8330b7 VM |
4763 | typedef invariant_t *invariant_ptr_t; |
4764 | typedef const invariant_t *const_invariant_ptr_t; | |
4765 | ||
4766 | /* Pointer to the inheritance invariants. */ | |
4767 | static vec<invariant_ptr_t> invariants; | |
4768 | ||
4769 | /* Allocation pool for the invariants. */ | |
eb0f8780 | 4770 | static object_allocator<lra_invariant> *invariants_pool; |
8a8330b7 VM |
4771 | |
4772 | /* Hash table for the invariants. */ | |
4773 | static htab_t invariant_table; | |
4774 | ||
4775 | /* Hash function for INVARIANT. */ | |
4776 | static hashval_t | |
4777 | invariant_hash (const void *invariant) | |
4778 | { | |
4779 | rtx inv = ((const_invariant_ptr_t) invariant)->invariant_rtx; | |
4780 | return lra_rtx_hash (inv); | |
4781 | } | |
4782 | ||
4783 | /* Equal function for invariants INVARIANT1 and INVARIANT2. */ | |
4784 | static int | |
4785 | invariant_eq_p (const void *invariant1, const void *invariant2) | |
4786 | { | |
4787 | rtx inv1 = ((const_invariant_ptr_t) invariant1)->invariant_rtx; | |
4788 | rtx inv2 = ((const_invariant_ptr_t) invariant2)->invariant_rtx; | |
4789 | ||
4790 | return rtx_equal_p (inv1, inv2); | |
4791 | } | |
4792 | ||
4793 | /* Insert INVARIANT_RTX into the table if it is not there yet. Return | |
4794 | invariant which is in the table. */ | |
4795 | static invariant_ptr_t | |
4796 | insert_invariant (rtx invariant_rtx) | |
4797 | { | |
4798 | void **entry_ptr; | |
4799 | invariant_t invariant; | |
4800 | invariant_ptr_t invariant_ptr; | |
4801 | ||
4802 | invariant.invariant_rtx = invariant_rtx; | |
4803 | entry_ptr = htab_find_slot (invariant_table, &invariant, INSERT); | |
4804 | if (*entry_ptr == NULL) | |
4805 | { | |
4806 | invariant_ptr = invariants_pool->allocate (); | |
4807 | invariant_ptr->invariant_rtx = invariant_rtx; | |
4808 | invariant_ptr->insn = NULL; | |
4809 | invariants.safe_push (invariant_ptr); | |
4810 | *entry_ptr = (void *) invariant_ptr; | |
4811 | } | |
4812 | return (invariant_ptr_t) *entry_ptr; | |
4813 | } | |
4814 | ||
4815 | /* Initiate the invariant table. */ | |
4816 | static void | |
4817 | initiate_invariants (void) | |
4818 | { | |
4819 | invariants.create (100); | |
eb0f8780 ML |
4820 | invariants_pool |
4821 | = new object_allocator<lra_invariant> ("Inheritance invariants"); | |
8a8330b7 VM |
4822 | invariant_table = htab_create (100, invariant_hash, invariant_eq_p, NULL); |
4823 | } | |
4824 | ||
4825 | /* Finish the invariant table. */ | |
4826 | static void | |
4827 | finish_invariants (void) | |
4828 | { | |
4829 | htab_delete (invariant_table); | |
4830 | delete invariants_pool; | |
4831 | invariants.release (); | |
4832 | } | |
4833 | ||
4834 | /* Make the invariant table empty. */ | |
4835 | static void | |
4836 | clear_invariants (void) | |
4837 | { | |
4838 | htab_empty (invariant_table); | |
4839 | invariants_pool->release (); | |
4840 | invariants.truncate (0); | |
55a2c322 VM |
4841 | } |
4842 | ||
4843 | \f | |
4844 | ||
4845 | /* This page contains code to do inheritance/split | |
4846 | transformations. */ | |
4847 | ||
4848 | /* Number of reloads passed so far in current EBB. */ | |
4849 | static int reloads_num; | |
4850 | ||
4851 | /* Number of calls passed so far in current EBB. */ | |
4852 | static int calls_num; | |
4853 | ||
4854 | /* Current reload pseudo check for validity of elements in | |
4855 | USAGE_INSNS. */ | |
4856 | static int curr_usage_insns_check; | |
4857 | ||
4858 | /* Info about last usage of registers in EBB to do inheritance/split | |
4859 | transformation. Inheritance transformation is done from a spilled | |
4860 | pseudo and split transformations from a hard register or a pseudo | |
4861 | assigned to a hard register. */ | |
4862 | struct usage_insns | |
4863 | { | |
4864 | /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member | |
4865 | value INSNS is valid. The insns is chain of optional debug insns | |
1ccd4874 VM |
4866 | and a finishing non-debug insn using the corresponding reg. The |
4867 | value is also used to mark the registers which are set up in the | |
4868 | current insn. The negated insn uid is used for this. */ | |
55a2c322 VM |
4869 | int check; |
4870 | /* Value of global reloads_num at the last insn in INSNS. */ | |
4871 | int reloads_num; | |
4872 | /* Value of global reloads_nums at the last insn in INSNS. */ | |
4873 | int calls_num; | |
4874 | /* It can be true only for splitting. And it means that the restore | |
4875 | insn should be put after insn given by the following member. */ | |
4876 | bool after_p; | |
4877 | /* Next insns in the current EBB which use the original reg and the | |
4878 | original reg value is not changed between the current insn and | |
4879 | the next insns. In order words, e.g. for inheritance, if we need | |
4880 | to use the original reg value again in the next insns we can try | |
4881 | to use the value in a hard register from a reload insn of the | |
4882 | current insn. */ | |
4883 | rtx insns; | |
4884 | }; | |
4885 | ||
4886 | /* Map: regno -> corresponding pseudo usage insns. */ | |
4887 | static struct usage_insns *usage_insns; | |
4888 | ||
4889 | static void | |
1476d1bd | 4890 | setup_next_usage_insn (int regno, rtx insn, int reloads_num, bool after_p) |
55a2c322 VM |
4891 | { |
4892 | usage_insns[regno].check = curr_usage_insns_check; | |
4893 | usage_insns[regno].insns = insn; | |
4894 | usage_insns[regno].reloads_num = reloads_num; | |
4895 | usage_insns[regno].calls_num = calls_num; | |
4896 | usage_insns[regno].after_p = after_p; | |
4897 | } | |
4898 | ||
4899 | /* The function is used to form list REGNO usages which consists of | |
4900 | optional debug insns finished by a non-debug insn using REGNO. | |
4901 | RELOADS_NUM is current number of reload insns processed so far. */ | |
4902 | static void | |
767dc529 | 4903 | add_next_usage_insn (int regno, rtx_insn *insn, int reloads_num) |
55a2c322 VM |
4904 | { |
4905 | rtx next_usage_insns; | |
f4eafc30 | 4906 | |
55a2c322 VM |
4907 | if (usage_insns[regno].check == curr_usage_insns_check |
4908 | && (next_usage_insns = usage_insns[regno].insns) != NULL_RTX | |
4909 | && DEBUG_INSN_P (insn)) | |
4910 | { | |
4911 | /* Check that we did not add the debug insn yet. */ | |
4912 | if (next_usage_insns != insn | |
4913 | && (GET_CODE (next_usage_insns) != INSN_LIST | |
4914 | || XEXP (next_usage_insns, 0) != insn)) | |
4915 | usage_insns[regno].insns = gen_rtx_INSN_LIST (VOIDmode, insn, | |
4916 | next_usage_insns); | |
4917 | } | |
4918 | else if (NONDEBUG_INSN_P (insn)) | |
4919 | setup_next_usage_insn (regno, insn, reloads_num, false); | |
4920 | else | |
4921 | usage_insns[regno].check = 0; | |
4922 | } | |
f4eafc30 | 4923 | |
bc3591eb | 4924 | /* Return first non-debug insn in list USAGE_INSNS. */ |
e8a54173 | 4925 | static rtx_insn * |
bc3591eb VM |
4926 | skip_usage_debug_insns (rtx usage_insns) |
4927 | { | |
4928 | rtx insn; | |
4929 | ||
4930 | /* Skip debug insns. */ | |
4931 | for (insn = usage_insns; | |
4932 | insn != NULL_RTX && GET_CODE (insn) == INSN_LIST; | |
4933 | insn = XEXP (insn, 1)) | |
4934 | ; | |
e8a54173 | 4935 | return safe_as_a <rtx_insn *> (insn); |
bc3591eb VM |
4936 | } |
4937 | ||
4938 | /* Return true if we need secondary memory moves for insn in | |
4939 | USAGE_INSNS after inserting inherited pseudo of class INHER_CL | |
4940 | into the insn. */ | |
4941 | static bool | |
fbebbadd JR |
4942 | check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED, |
4943 | rtx usage_insns ATTRIBUTE_UNUSED) | |
bc3591eb VM |
4944 | { |
4945 | #ifndef SECONDARY_MEMORY_NEEDED | |
4946 | return false; | |
4947 | #else | |
e8a54173 DM |
4948 | rtx_insn *insn; |
4949 | rtx set, dest; | |
bc3591eb VM |
4950 | enum reg_class cl; |
4951 | ||
4952 | if (inher_cl == ALL_REGS | |
4953 | || (insn = skip_usage_debug_insns (usage_insns)) == NULL_RTX) | |
4954 | return false; | |
4955 | lra_assert (INSN_P (insn)); | |
4956 | if ((set = single_set (insn)) == NULL_RTX || ! REG_P (SET_DEST (set))) | |
4957 | return false; | |
4958 | dest = SET_DEST (set); | |
4959 | if (! REG_P (dest)) | |
4960 | return false; | |
4961 | lra_assert (inher_cl != NO_REGS); | |
4962 | cl = get_reg_class (REGNO (dest)); | |
4963 | return (cl != NO_REGS && cl != ALL_REGS | |
4964 | && SECONDARY_MEMORY_NEEDED (inher_cl, cl, GET_MODE (dest))); | |
4965 | #endif | |
4966 | } | |
4967 | ||
55a2c322 VM |
4968 | /* Registers involved in inheritance/split in the current EBB |
4969 | (inheritance/split pseudos and original registers). */ | |
4970 | static bitmap_head check_only_regs; | |
4971 | ||
8a8330b7 VM |
4972 | /* Reload pseudos can not be involded in invariant inheritance in the |
4973 | current EBB. */ | |
4974 | static bitmap_head invalid_invariant_regs; | |
4975 | ||
55a2c322 VM |
4976 | /* Do inheritance transformations for insn INSN, which defines (if |
4977 | DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which | |
4978 | instruction in the EBB next uses ORIGINAL_REGNO; it has the same | |
4979 | form as the "insns" field of usage_insns. Return true if we | |
4980 | succeed in such transformation. | |
4981 | ||
4982 | The transformations look like: | |
4983 | ||
4984 | p <- ... i <- ... | |
4985 | ... p <- i (new insn) | |
4986 | ... => | |
4987 | <- ... p ... <- ... i ... | |
4988 | or | |
4989 | ... i <- p (new insn) | |
4990 | <- ... p ... <- ... i ... | |
4991 | ... => | |
4992 | <- ... p ... <- ... i ... | |
4993 | where p is a spilled original pseudo and i is a new inheritance pseudo. | |
f4eafc30 L |
4994 | |
4995 | ||
55a2c322 VM |
4996 | The inheritance pseudo has the smallest class of two classes CL and |
4997 | class of ORIGINAL REGNO. */ | |
4998 | static bool | |
4999 | inherit_reload_reg (bool def_p, int original_regno, | |
cfa434f6 | 5000 | enum reg_class cl, rtx_insn *insn, rtx next_usage_insns) |
55a2c322 | 5001 | { |
2ae577fd VM |
5002 | if (optimize_function_for_size_p (cfun)) |
5003 | return false; | |
5004 | ||
55a2c322 VM |
5005 | enum reg_class rclass = lra_get_allocno_class (original_regno); |
5006 | rtx original_reg = regno_reg_rtx[original_regno]; | |
cfa434f6 DM |
5007 | rtx new_reg, usage_insn; |
5008 | rtx_insn *new_insns; | |
55a2c322 VM |
5009 | |
5010 | lra_assert (! usage_insns[original_regno].after_p); | |
5011 | if (lra_dump_file != NULL) | |
5012 | fprintf (lra_dump_file, | |
bc3591eb | 5013 | " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n"); |
55a2c322 VM |
5014 | if (! ira_reg_classes_intersect_p[cl][rclass]) |
5015 | { | |
5016 | if (lra_dump_file != NULL) | |
5017 | { | |
5018 | fprintf (lra_dump_file, | |
bc3591eb | 5019 | " Rejecting inheritance for %d " |
55a2c322 VM |
5020 | "because of disjoint classes %s and %s\n", |
5021 | original_regno, reg_class_names[cl], | |
5022 | reg_class_names[rclass]); | |
5023 | fprintf (lra_dump_file, | |
bc3591eb | 5024 | " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); |
55a2c322 VM |
5025 | } |
5026 | return false; | |
5027 | } | |
5028 | if ((ira_class_subset_p[cl][rclass] && cl != rclass) | |
5029 | /* We don't use a subset of two classes because it can be | |
5030 | NO_REGS. This transformation is still profitable in most | |
5031 | cases even if the classes are not intersected as register | |
5032 | move is probably cheaper than a memory load. */ | |
5033 | || ira_class_hard_regs_num[cl] < ira_class_hard_regs_num[rclass]) | |
5034 | { | |
5035 | if (lra_dump_file != NULL) | |
5036 | fprintf (lra_dump_file, " Use smallest class of %s and %s\n", | |
5037 | reg_class_names[cl], reg_class_names[rclass]); | |
f4eafc30 | 5038 | |
55a2c322 VM |
5039 | rclass = cl; |
5040 | } | |
66aa7879 | 5041 | if (check_secondary_memory_needed_p (rclass, next_usage_insns)) |
bc3591eb VM |
5042 | { |
5043 | /* Reject inheritance resulting in secondary memory moves. | |
5044 | Otherwise, there is a danger in LRA cycling. Also such | |
5045 | transformation will be unprofitable. */ | |
5046 | if (lra_dump_file != NULL) | |
5047 | { | |
e8a54173 | 5048 | rtx_insn *insn = skip_usage_debug_insns (next_usage_insns); |
bc3591eb VM |
5049 | rtx set = single_set (insn); |
5050 | ||
5051 | lra_assert (set != NULL_RTX); | |
5052 | ||
5053 | rtx dest = SET_DEST (set); | |
5054 | ||
5055 | lra_assert (REG_P (dest)); | |
5056 | fprintf (lra_dump_file, | |
5057 | " Rejecting inheritance for insn %d(%s)<-%d(%s) " | |
5058 | "as secondary mem is needed\n", | |
5059 | REGNO (dest), reg_class_names[get_reg_class (REGNO (dest))], | |
66aa7879 | 5060 | original_regno, reg_class_names[rclass]); |
bc3591eb VM |
5061 | fprintf (lra_dump_file, |
5062 | " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); | |
5063 | } | |
5064 | return false; | |
5065 | } | |
55a2c322 VM |
5066 | new_reg = lra_create_new_reg (GET_MODE (original_reg), original_reg, |
5067 | rclass, "inheritance"); | |
5068 | start_sequence (); | |
5069 | if (def_p) | |
a810ee82 | 5070 | lra_emit_move (original_reg, new_reg); |
55a2c322 | 5071 | else |
a810ee82 | 5072 | lra_emit_move (new_reg, original_reg); |
55a2c322 VM |
5073 | new_insns = get_insns (); |
5074 | end_sequence (); | |
5075 | if (NEXT_INSN (new_insns) != NULL_RTX) | |
5076 | { | |
5077 | if (lra_dump_file != NULL) | |
5078 | { | |
5079 | fprintf (lra_dump_file, | |
bc3591eb | 5080 | " Rejecting inheritance %d->%d " |
55a2c322 VM |
5081 | "as it results in 2 or more insns:\n", |
5082 | original_regno, REGNO (new_reg)); | |
dc01c3d1 | 5083 | dump_rtl_slim (lra_dump_file, new_insns, NULL, -1, 0); |
55a2c322 VM |
5084 | fprintf (lra_dump_file, |
5085 | " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); | |
5086 | } | |
5087 | return false; | |
5088 | } | |
ef87312e | 5089 | lra_substitute_pseudo_within_insn (insn, original_regno, new_reg, false); |
55a2c322 VM |
5090 | lra_update_insn_regno_info (insn); |
5091 | if (! def_p) | |
5092 | /* We now have a new usage insn for original regno. */ | |
5093 | setup_next_usage_insn (original_regno, new_insns, reloads_num, false); | |
5094 | if (lra_dump_file != NULL) | |
bc3591eb | 5095 | fprintf (lra_dump_file, " Original reg change %d->%d (bb%d):\n", |
55a2c322 | 5096 | original_regno, REGNO (new_reg), BLOCK_FOR_INSN (insn)->index); |
8a8330b7 | 5097 | lra_reg_info[REGNO (new_reg)].restore_rtx = regno_reg_rtx[original_regno]; |
55a2c322 VM |
5098 | bitmap_set_bit (&check_only_regs, REGNO (new_reg)); |
5099 | bitmap_set_bit (&check_only_regs, original_regno); | |
5100 | bitmap_set_bit (&lra_inheritance_pseudos, REGNO (new_reg)); | |
5101 | if (def_p) | |
cfa434f6 | 5102 | lra_process_new_insns (insn, NULL, new_insns, |
55a2c322 VM |
5103 | "Add original<-inheritance"); |
5104 | else | |
cfa434f6 | 5105 | lra_process_new_insns (insn, new_insns, NULL, |
55a2c322 VM |
5106 | "Add inheritance<-original"); |
5107 | while (next_usage_insns != NULL_RTX) | |
5108 | { | |
5109 | if (GET_CODE (next_usage_insns) != INSN_LIST) | |
5110 | { | |
5111 | usage_insn = next_usage_insns; | |
5112 | lra_assert (NONDEBUG_INSN_P (usage_insn)); | |
5113 | next_usage_insns = NULL; | |
5114 | } | |
5115 | else | |
5116 | { | |
5117 | usage_insn = XEXP (next_usage_insns, 0); | |
5118 | lra_assert (DEBUG_INSN_P (usage_insn)); | |
5119 | next_usage_insns = XEXP (next_usage_insns, 1); | |
5120 | } | |
ef87312e | 5121 | lra_substitute_pseudo (&usage_insn, original_regno, new_reg, false); |
cfa434f6 | 5122 | lra_update_insn_regno_info (as_a <rtx_insn *> (usage_insn)); |
55a2c322 VM |
5123 | if (lra_dump_file != NULL) |
5124 | { | |
5125 | fprintf (lra_dump_file, | |
5126 | " Inheritance reuse change %d->%d (bb%d):\n", | |
5127 | original_regno, REGNO (new_reg), | |
5128 | BLOCK_FOR_INSN (usage_insn)->index); | |
1476d1bd | 5129 | dump_insn_slim (lra_dump_file, as_a <rtx_insn *> (usage_insn)); |
55a2c322 VM |
5130 | } |
5131 | } | |
5132 | if (lra_dump_file != NULL) | |
5133 | fprintf (lra_dump_file, | |
5134 | " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); | |
5135 | return true; | |
5136 | } | |
5137 | ||
5138 | /* Return true if we need a caller save/restore for pseudo REGNO which | |
5139 | was assigned to a hard register. */ | |
5140 | static inline bool | |
5141 | need_for_call_save_p (int regno) | |
5142 | { | |
5143 | lra_assert (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] >= 0); | |
5144 | return (usage_insns[regno].calls_num < calls_num | |
5145 | && (overlaps_hard_reg_set_p | |
1e288103 | 5146 | ((flag_ipa_ra && |
10e1bdb2 TV |
5147 | ! hard_reg_set_empty_p (lra_reg_info[regno].actual_call_used_reg_set)) |
5148 | ? lra_reg_info[regno].actual_call_used_reg_set | |
5149 | : call_used_reg_set, | |
8a26ad39 VM |
5150 | PSEUDO_REGNO_MODE (regno), reg_renumber[regno]) |
5151 | || HARD_REGNO_CALL_PART_CLOBBERED (reg_renumber[regno], | |
5152 | PSEUDO_REGNO_MODE (regno)))); | |
55a2c322 VM |
5153 | } |
5154 | ||
1aa95df7 | 5155 | /* Global registers occurring in the current EBB. */ |
55a2c322 VM |
5156 | static bitmap_head ebb_global_regs; |
5157 | ||
5158 | /* Return true if we need a split for hard register REGNO or pseudo | |
5159 | REGNO which was assigned to a hard register. | |
5160 | POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be | |
5161 | used for reloads since the EBB end. It is an approximation of the | |
5162 | used hard registers in the split range. The exact value would | |
5163 | require expensive calculations. If we were aggressive with | |
5164 | splitting because of the approximation, the split pseudo will save | |
5165 | the same hard register assignment and will be removed in the undo | |
5166 | pass. We still need the approximation because too aggressive | |
5167 | splitting would result in too inaccurate cost calculation in the | |
5168 | assignment pass because of too many generated moves which will be | |
5169 | probably removed in the undo pass. */ | |
5170 | static inline bool | |
5171 | need_for_split_p (HARD_REG_SET potential_reload_hard_regs, int regno) | |
5172 | { | |
5173 | int hard_regno = regno < FIRST_PSEUDO_REGISTER ? regno : reg_renumber[regno]; | |
5174 | ||
5175 | lra_assert (hard_regno >= 0); | |
5176 | return ((TEST_HARD_REG_BIT (potential_reload_hard_regs, hard_regno) | |
5177 | /* Don't split eliminable hard registers, otherwise we can | |
5178 | split hard registers like hard frame pointer, which | |
5179 | lives on BB start/end according to DF-infrastructure, | |
5180 | when there is a pseudo assigned to the register and | |
5181 | living in the same BB. */ | |
5182 | && (regno >= FIRST_PSEUDO_REGISTER | |
5183 | || ! TEST_HARD_REG_BIT (eliminable_regset, hard_regno)) | |
5184 | && ! TEST_HARD_REG_BIT (lra_no_alloc_regs, hard_regno) | |
e32e4c4a VM |
5185 | /* Don't split call clobbered hard regs living through |
5186 | calls, otherwise we might have a check problem in the | |
5187 | assign sub-pass as in the most cases (exception is a | |
5188 | situation when lra_risky_transformations_p value is | |
5189 | true) the assign pass assumes that all pseudos living | |
5190 | through calls are assigned to call saved hard regs. */ | |
5191 | && (regno >= FIRST_PSEUDO_REGISTER | |
5192 | || ! TEST_HARD_REG_BIT (call_used_reg_set, regno) | |
5193 | || usage_insns[regno].calls_num == calls_num) | |
55a2c322 VM |
5194 | /* We need at least 2 reloads to make pseudo splitting |
5195 | profitable. We should provide hard regno splitting in | |
5196 | any case to solve 1st insn scheduling problem when | |
5197 | moving hard register definition up might result in | |
5198 | impossibility to find hard register for reload pseudo of | |
5199 | small register class. */ | |
5200 | && (usage_insns[regno].reloads_num | |
8e9d68a9 | 5201 | + (regno < FIRST_PSEUDO_REGISTER ? 0 : 3) < reloads_num) |
55a2c322 VM |
5202 | && (regno < FIRST_PSEUDO_REGISTER |
5203 | /* For short living pseudos, spilling + inheritance can | |
5204 | be considered a substitution for splitting. | |
5205 | Therefore we do not splitting for local pseudos. It | |
5206 | decreases also aggressiveness of splitting. The | |
5207 | minimal number of references is chosen taking into | |
5208 | account that for 2 references splitting has no sense | |
5209 | as we can just spill the pseudo. */ | |
5210 | || (regno >= FIRST_PSEUDO_REGISTER | |
5211 | && lra_reg_info[regno].nrefs > 3 | |
5212 | && bitmap_bit_p (&ebb_global_regs, regno)))) | |
5213 | || (regno >= FIRST_PSEUDO_REGISTER && need_for_call_save_p (regno))); | |
5214 | } | |
5215 | ||
5216 | /* Return class for the split pseudo created from original pseudo with | |
5217 | ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We | |
5218 | choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and | |
5219 | results in no secondary memory movements. */ | |
5220 | static enum reg_class | |
5221 | choose_split_class (enum reg_class allocno_class, | |
5222 | int hard_regno ATTRIBUTE_UNUSED, | |
ef4bddc2 | 5223 | machine_mode mode ATTRIBUTE_UNUSED) |
55a2c322 VM |
5224 | { |
5225 | #ifndef SECONDARY_MEMORY_NEEDED | |
5226 | return allocno_class; | |
5227 | #else | |
5228 | int i; | |
5229 | enum reg_class cl, best_cl = NO_REGS; | |
ef4dbe49 JR |
5230 | enum reg_class hard_reg_class ATTRIBUTE_UNUSED |
5231 | = REGNO_REG_CLASS (hard_regno); | |
f4eafc30 | 5232 | |
55a2c322 VM |
5233 | if (! SECONDARY_MEMORY_NEEDED (allocno_class, allocno_class, mode) |
5234 | && TEST_HARD_REG_BIT (reg_class_contents[allocno_class], hard_regno)) | |
5235 | return allocno_class; | |
5236 | for (i = 0; | |
5237 | (cl = reg_class_subclasses[allocno_class][i]) != LIM_REG_CLASSES; | |
5238 | i++) | |
5239 | if (! SECONDARY_MEMORY_NEEDED (cl, hard_reg_class, mode) | |
5240 | && ! SECONDARY_MEMORY_NEEDED (hard_reg_class, cl, mode) | |
5241 | && TEST_HARD_REG_BIT (reg_class_contents[cl], hard_regno) | |
5242 | && (best_cl == NO_REGS | |
5243 | || ira_class_hard_regs_num[best_cl] < ira_class_hard_regs_num[cl])) | |
5244 | best_cl = cl; | |
5245 | return best_cl; | |
5246 | #endif | |
5247 | } | |
5248 | ||
5249 | /* Do split transformations for insn INSN, which defines or uses | |
5250 | ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in | |
5251 | the EBB next uses ORIGINAL_REGNO; it has the same form as the | |
5252 | "insns" field of usage_insns. | |
5253 | ||
5254 | The transformations look like: | |
5255 | ||
5256 | p <- ... p <- ... | |
5257 | ... s <- p (new insn -- save) | |
5258 | ... => | |
5259 | ... p <- s (new insn -- restore) | |
5260 | <- ... p ... <- ... p ... | |
5261 | or | |
5262 | <- ... p ... <- ... p ... | |
5263 | ... s <- p (new insn -- save) | |
5264 | ... => | |
5265 | ... p <- s (new insn -- restore) | |
5266 | <- ... p ... <- ... p ... | |
5267 | ||
5268 | where p is an original pseudo got a hard register or a hard | |
5269 | register and s is a new split pseudo. The save is put before INSN | |
5270 | if BEFORE_P is true. Return true if we succeed in such | |
5271 | transformation. */ | |
5272 | static bool | |
cfa434f6 DM |
5273 | split_reg (bool before_p, int original_regno, rtx_insn *insn, |
5274 | rtx next_usage_insns) | |
55a2c322 VM |
5275 | { |
5276 | enum reg_class rclass; | |
5277 | rtx original_reg; | |
77bce07c | 5278 | int hard_regno, nregs; |
cfa434f6 DM |
5279 | rtx new_reg, usage_insn; |
5280 | rtx_insn *restore, *save; | |
55a2c322 VM |
5281 | bool after_p; |
5282 | bool call_save_p; | |
3cbf012a | 5283 | machine_mode mode; |
55a2c322 VM |
5284 | |
5285 | if (original_regno < FIRST_PSEUDO_REGISTER) | |
5286 | { | |
5287 | rclass = ira_allocno_class_translate[REGNO_REG_CLASS (original_regno)]; | |
5288 | hard_regno = original_regno; | |
5289 | call_save_p = false; | |
77bce07c | 5290 | nregs = 1; |
3cbf012a BS |
5291 | mode = lra_reg_info[hard_regno].biggest_mode; |
5292 | machine_mode reg_rtx_mode = GET_MODE (regno_reg_rtx[hard_regno]); | |
5c6a601c BS |
5293 | /* A reg can have a biggest_mode of VOIDmode if it was only ever seen |
5294 | as part of a multi-word register. In that case, or if the biggest | |
5295 | mode was larger than a register, just use the reg_rtx. Otherwise, | |
5296 | limit the size to that of the biggest access in the function. */ | |
5297 | if (mode == VOIDmode | |
5298 | || GET_MODE_SIZE (mode) > GET_MODE_SIZE (reg_rtx_mode)) | |
3cbf012a BS |
5299 | { |
5300 | original_reg = regno_reg_rtx[hard_regno]; | |
5301 | mode = reg_rtx_mode; | |
5302 | } | |
5303 | else | |
5304 | original_reg = gen_rtx_REG (mode, hard_regno); | |
55a2c322 VM |
5305 | } |
5306 | else | |
5307 | { | |
3cbf012a | 5308 | mode = PSEUDO_REGNO_MODE (original_regno); |
55a2c322 | 5309 | hard_regno = reg_renumber[original_regno]; |
3cbf012a | 5310 | nregs = hard_regno_nregs[hard_regno][mode]; |
55a2c322 VM |
5311 | rclass = lra_get_allocno_class (original_regno); |
5312 | original_reg = regno_reg_rtx[original_regno]; | |
5313 | call_save_p = need_for_call_save_p (original_regno); | |
5314 | } | |
55a2c322 VM |
5315 | lra_assert (hard_regno >= 0); |
5316 | if (lra_dump_file != NULL) | |
5317 | fprintf (lra_dump_file, | |
5318 | " ((((((((((((((((((((((((((((((((((((((((((((((((\n"); | |
3cbf012a | 5319 | |
55a2c322 VM |
5320 | if (call_save_p) |
5321 | { | |
cb1cca12 VM |
5322 | mode = HARD_REGNO_CALLER_SAVE_MODE (hard_regno, |
5323 | hard_regno_nregs[hard_regno][mode], | |
5324 | mode); | |
5325 | new_reg = lra_create_new_reg (mode, NULL_RTX, NO_REGS, "save"); | |
55a2c322 VM |
5326 | } |
5327 | else | |
5328 | { | |
3cbf012a | 5329 | rclass = choose_split_class (rclass, hard_regno, mode); |
55a2c322 VM |
5330 | if (rclass == NO_REGS) |
5331 | { | |
5332 | if (lra_dump_file != NULL) | |
5333 | { | |
5334 | fprintf (lra_dump_file, | |
5335 | " Rejecting split of %d(%s): " | |
5336 | "no good reg class for %d(%s)\n", | |
5337 | original_regno, | |
5338 | reg_class_names[lra_get_allocno_class (original_regno)], | |
5339 | hard_regno, | |
5340 | reg_class_names[REGNO_REG_CLASS (hard_regno)]); | |
5341 | fprintf | |
5342 | (lra_dump_file, | |
5343 | " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); | |
5344 | } | |
5345 | return false; | |
5346 | } | |
3cbf012a | 5347 | new_reg = lra_create_new_reg (mode, original_reg, rclass, "split"); |
55a2c322 VM |
5348 | reg_renumber[REGNO (new_reg)] = hard_regno; |
5349 | } | |
5350 | save = emit_spill_move (true, new_reg, original_reg); | |
c61fe0cc | 5351 | if (NEXT_INSN (save) != NULL_RTX && !call_save_p) |
55a2c322 | 5352 | { |
55a2c322 VM |
5353 | if (lra_dump_file != NULL) |
5354 | { | |
5355 | fprintf | |
5356 | (lra_dump_file, | |
c61fe0cc KC |
5357 | " Rejecting split %d->%d resulting in > 2 save insns:\n", |
5358 | original_regno, REGNO (new_reg)); | |
dc01c3d1 | 5359 | dump_rtl_slim (lra_dump_file, save, NULL, -1, 0); |
55a2c322 VM |
5360 | fprintf (lra_dump_file, |
5361 | " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); | |
5362 | } | |
5363 | return false; | |
5364 | } | |
5365 | restore = emit_spill_move (false, new_reg, original_reg); | |
c61fe0cc | 5366 | if (NEXT_INSN (restore) != NULL_RTX && !call_save_p) |
55a2c322 | 5367 | { |
55a2c322 VM |
5368 | if (lra_dump_file != NULL) |
5369 | { | |
5370 | fprintf (lra_dump_file, | |
5371 | " Rejecting split %d->%d " | |
c61fe0cc KC |
5372 | "resulting in > 2 restore insns:\n", |
5373 | original_regno, REGNO (new_reg)); | |
dc01c3d1 | 5374 | dump_rtl_slim (lra_dump_file, restore, NULL, -1, 0); |
55a2c322 VM |
5375 | fprintf (lra_dump_file, |
5376 | " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); | |
5377 | } | |
5378 | return false; | |
5379 | } | |
5380 | after_p = usage_insns[original_regno].after_p; | |
8a8330b7 | 5381 | lra_reg_info[REGNO (new_reg)].restore_rtx = regno_reg_rtx[original_regno]; |
55a2c322 VM |
5382 | bitmap_set_bit (&check_only_regs, REGNO (new_reg)); |
5383 | bitmap_set_bit (&check_only_regs, original_regno); | |
5384 | bitmap_set_bit (&lra_split_regs, REGNO (new_reg)); | |
5385 | for (;;) | |
5386 | { | |
5387 | if (GET_CODE (next_usage_insns) != INSN_LIST) | |
5388 | { | |
5389 | usage_insn = next_usage_insns; | |
5390 | break; | |
5391 | } | |
5392 | usage_insn = XEXP (next_usage_insns, 0); | |
5393 | lra_assert (DEBUG_INSN_P (usage_insn)); | |
5394 | next_usage_insns = XEXP (next_usage_insns, 1); | |
ef87312e | 5395 | lra_substitute_pseudo (&usage_insn, original_regno, new_reg, false); |
cfa434f6 | 5396 | lra_update_insn_regno_info (as_a <rtx_insn *> (usage_insn)); |
55a2c322 VM |
5397 | if (lra_dump_file != NULL) |
5398 | { | |
5399 | fprintf (lra_dump_file, " Split reuse change %d->%d:\n", | |
5400 | original_regno, REGNO (new_reg)); | |
1476d1bd | 5401 | dump_insn_slim (lra_dump_file, as_a <rtx_insn *> (usage_insn)); |
55a2c322 VM |
5402 | } |
5403 | } | |
5404 | lra_assert (NOTE_P (usage_insn) || NONDEBUG_INSN_P (usage_insn)); | |
5405 | lra_assert (usage_insn != insn || (after_p && before_p)); | |
cfa434f6 DM |
5406 | lra_process_new_insns (as_a <rtx_insn *> (usage_insn), |
5407 | after_p ? NULL : restore, | |
5408 | after_p ? restore : NULL, | |
55a2c322 VM |
5409 | call_save_p |
5410 | ? "Add reg<-save" : "Add reg<-split"); | |
cfa434f6 DM |
5411 | lra_process_new_insns (insn, before_p ? save : NULL, |
5412 | before_p ? NULL : save, | |
55a2c322 VM |
5413 | call_save_p |
5414 | ? "Add save<-reg" : "Add split<-reg"); | |
77bce07c VM |
5415 | if (nregs > 1) |
5416 | /* If we are trying to split multi-register. We should check | |
5417 | conflicts on the next assignment sub-pass. IRA can allocate on | |
5418 | sub-register levels, LRA do this on pseudos level right now and | |
5419 | this discrepancy may create allocation conflicts after | |
5420 | splitting. */ | |
5421 | lra_risky_transformations_p = true; | |
55a2c322 VM |
5422 | if (lra_dump_file != NULL) |
5423 | fprintf (lra_dump_file, | |
5424 | " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); | |
5425 | return true; | |
5426 | } | |
5427 | ||
5428 | /* Recognize that we need a split transformation for insn INSN, which | |
5429 | defines or uses REGNO in its insn biggest MODE (we use it only if | |
5430 | REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains | |
5431 | hard registers which might be used for reloads since the EBB end. | |
5432 | Put the save before INSN if BEFORE_P is true. MAX_UID is maximla | |
5433 | uid before starting INSN processing. Return true if we succeed in | |
5434 | such transformation. */ | |
5435 | static bool | |
ef4bddc2 | 5436 | split_if_necessary (int regno, machine_mode mode, |
55a2c322 | 5437 | HARD_REG_SET potential_reload_hard_regs, |
cfa434f6 | 5438 | bool before_p, rtx_insn *insn, int max_uid) |
55a2c322 VM |
5439 | { |
5440 | bool res = false; | |
5441 | int i, nregs = 1; | |
5442 | rtx next_usage_insns; | |
5443 | ||
5444 | if (regno < FIRST_PSEUDO_REGISTER) | |
5445 | nregs = hard_regno_nregs[regno][mode]; | |
5446 | for (i = 0; i < nregs; i++) | |
5447 | if (usage_insns[regno + i].check == curr_usage_insns_check | |
5448 | && (next_usage_insns = usage_insns[regno + i].insns) != NULL_RTX | |
5449 | /* To avoid processing the register twice or more. */ | |
5450 | && ((GET_CODE (next_usage_insns) != INSN_LIST | |
5451 | && INSN_UID (next_usage_insns) < max_uid) | |
5452 | || (GET_CODE (next_usage_insns) == INSN_LIST | |
5453 | && (INSN_UID (XEXP (next_usage_insns, 0)) < max_uid))) | |
5454 | && need_for_split_p (potential_reload_hard_regs, regno + i) | |
5455 | && split_reg (before_p, regno + i, insn, next_usage_insns)) | |
5456 | res = true; | |
5457 | return res; | |
5458 | } | |
5459 | ||
8a8330b7 VM |
5460 | /* Return TRUE if rtx X is considered as an invariant for |
5461 | inheritance. */ | |
5462 | static bool | |
5463 | invariant_p (const_rtx x) | |
5464 | { | |
5465 | machine_mode mode; | |
5466 | const char *fmt; | |
5467 | enum rtx_code code; | |
5468 | int i, j; | |
5469 | ||
5470 | code = GET_CODE (x); | |
5471 | mode = GET_MODE (x); | |
5472 | if (code == SUBREG) | |
5473 | { | |
5474 | x = SUBREG_REG (x); | |
5475 | code = GET_CODE (x); | |
5476 | if (GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (mode)) | |
5477 | mode = GET_MODE (x); | |
5478 | } | |
5479 | ||
5480 | if (MEM_P (x)) | |
5481 | return false; | |
5482 | ||
5483 | if (REG_P (x)) | |
5484 | { | |
5485 | int i, nregs, regno = REGNO (x); | |
5486 | ||
5487 | if (regno >= FIRST_PSEUDO_REGISTER || regno == STACK_POINTER_REGNUM | |
5488 | || TEST_HARD_REG_BIT (eliminable_regset, regno) | |
5489 | || GET_MODE_CLASS (GET_MODE (x)) == MODE_CC) | |
5490 | return false; | |
5491 | nregs = hard_regno_nregs[regno][mode]; | |
5492 | for (i = 0; i < nregs; i++) | |
5493 | if (! fixed_regs[regno + i] | |
5494 | /* A hard register may be clobbered in the current insn | |
5495 | but we can ignore this case because if the hard | |
5496 | register is used it should be set somewhere after the | |
5497 | clobber. */ | |
5498 | || bitmap_bit_p (&invalid_invariant_regs, regno + i)) | |
5499 | return false; | |
5500 | } | |
5501 | fmt = GET_RTX_FORMAT (code); | |
5502 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
5503 | { | |
5504 | if (fmt[i] == 'e') | |
5505 | { | |
5506 | if (! invariant_p (XEXP (x, i))) | |
5507 | return false; | |
5508 | } | |
5509 | else if (fmt[i] == 'E') | |
5510 | { | |
5511 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
5512 | if (! invariant_p (XVECEXP (x, i, j))) | |
5513 | return false; | |
5514 | } | |
5515 | } | |
5516 | return true; | |
5517 | } | |
5518 | ||
5519 | /* We have 'dest_reg <- invariant'. Let us try to make an invariant | |
5520 | inheritance transformation (using dest_reg instead invariant in a | |
5521 | subsequent insn). */ | |
5522 | static bool | |
5523 | process_invariant_for_inheritance (rtx dst_reg, rtx invariant_rtx) | |
5524 | { | |
5525 | invariant_ptr_t invariant_ptr; | |
5526 | rtx_insn *insn, *new_insns; | |
5527 | rtx insn_set, insn_reg, new_reg; | |
5528 | int insn_regno; | |
5529 | bool succ_p = false; | |
5530 | int dst_regno = REGNO (dst_reg); | |
5531 | enum machine_mode dst_mode = GET_MODE (dst_reg); | |
5532 | enum reg_class cl = lra_get_allocno_class (dst_regno), insn_reg_cl; | |
5533 | ||
5534 | invariant_ptr = insert_invariant (invariant_rtx); | |
5535 | if ((insn = invariant_ptr->insn) != NULL_RTX) | |
5536 | { | |
5537 | /* We have a subsequent insn using the invariant. */ | |
5538 | insn_set = single_set (insn); | |
5539 | lra_assert (insn_set != NULL); | |
5540 | insn_reg = SET_DEST (insn_set); | |
5541 | lra_assert (REG_P (insn_reg)); | |
5542 | insn_regno = REGNO (insn_reg); | |
5543 | insn_reg_cl = lra_get_allocno_class (insn_regno); | |
5544 | ||
5545 | if (dst_mode == GET_MODE (insn_reg) | |
5546 | /* We should consider only result move reg insns which are | |
5547 | cheap. */ | |
5548 | && targetm.register_move_cost (dst_mode, cl, insn_reg_cl) == 2 | |
5549 | && targetm.register_move_cost (dst_mode, cl, cl) == 2) | |
5550 | { | |
5551 | if (lra_dump_file != NULL) | |
5552 | fprintf (lra_dump_file, | |
5553 | " [[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[\n"); | |
5554 | new_reg = lra_create_new_reg (dst_mode, dst_reg, | |
5555 | cl, "invariant inheritance"); | |
5556 | bitmap_set_bit (&lra_inheritance_pseudos, REGNO (new_reg)); | |
5557 | bitmap_set_bit (&check_only_regs, REGNO (new_reg)); | |
b10d44ef | 5558 | lra_reg_info[REGNO (new_reg)].restore_rtx = PATTERN (insn); |
8a8330b7 VM |
5559 | start_sequence (); |
5560 | lra_emit_move (new_reg, dst_reg); | |
5561 | new_insns = get_insns (); | |
5562 | end_sequence (); | |
5563 | lra_process_new_insns (curr_insn, NULL, new_insns, | |
5564 | "Add invariant inheritance<-original"); | |
5565 | start_sequence (); | |
5566 | lra_emit_move (SET_DEST (insn_set), new_reg); | |
5567 | new_insns = get_insns (); | |
5568 | end_sequence (); | |
5569 | lra_process_new_insns (insn, NULL, new_insns, | |
5570 | "Changing reload<-inheritance"); | |
5571 | lra_set_insn_deleted (insn); | |
5572 | succ_p = true; | |
5573 | if (lra_dump_file != NULL) | |
5574 | { | |
5575 | fprintf (lra_dump_file, | |
5576 | " Invariant inheritance reuse change %d (bb%d):\n", | |
5577 | REGNO (new_reg), BLOCK_FOR_INSN (insn)->index); | |
5578 | dump_insn_slim (lra_dump_file, insn); | |
5579 | fprintf (lra_dump_file, | |
5580 | " ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]\n"); | |
5581 | } | |
5582 | } | |
5583 | } | |
5584 | invariant_ptr->insn = curr_insn; | |
5585 | return succ_p; | |
5586 | } | |
5587 | ||
55a2c322 VM |
5588 | /* Check only registers living at the current program point in the |
5589 | current EBB. */ | |
5590 | static bitmap_head live_regs; | |
5591 | ||
5592 | /* Update live info in EBB given by its HEAD and TAIL insns after | |
5593 | inheritance/split transformation. The function removes dead moves | |
5594 | too. */ | |
5595 | static void | |
cfa434f6 | 5596 | update_ebb_live_info (rtx_insn *head, rtx_insn *tail) |
55a2c322 VM |
5597 | { |
5598 | unsigned int j; | |
8e9d68a9 | 5599 | int i, regno; |
55a2c322 | 5600 | bool live_p; |
cfa434f6 DM |
5601 | rtx_insn *prev_insn; |
5602 | rtx set; | |
55a2c322 VM |
5603 | bool remove_p; |
5604 | basic_block last_bb, prev_bb, curr_bb; | |
5605 | bitmap_iterator bi; | |
5606 | struct lra_insn_reg *reg; | |
5607 | edge e; | |
5608 | edge_iterator ei; | |
5609 | ||
f4eafc30 | 5610 | last_bb = BLOCK_FOR_INSN (tail); |
55a2c322 VM |
5611 | prev_bb = NULL; |
5612 | for (curr_insn = tail; | |
5613 | curr_insn != PREV_INSN (head); | |
5614 | curr_insn = prev_insn) | |
5615 | { | |
5616 | prev_insn = PREV_INSN (curr_insn); | |
911598e3 VM |
5617 | /* We need to process empty blocks too. They contain |
5618 | NOTE_INSN_BASIC_BLOCK referring for the basic block. */ | |
5619 | if (NOTE_P (curr_insn) && NOTE_KIND (curr_insn) != NOTE_INSN_BASIC_BLOCK) | |
5620 | continue; | |
55a2c322 VM |
5621 | curr_bb = BLOCK_FOR_INSN (curr_insn); |
5622 | if (curr_bb != prev_bb) | |
5623 | { | |
5624 | if (prev_bb != NULL) | |
5625 | { | |
5626 | /* Update df_get_live_in (prev_bb): */ | |
5627 | EXECUTE_IF_SET_IN_BITMAP (&check_only_regs, 0, j, bi) | |
5628 | if (bitmap_bit_p (&live_regs, j)) | |
5629 | bitmap_set_bit (df_get_live_in (prev_bb), j); | |
5630 | else | |
5631 | bitmap_clear_bit (df_get_live_in (prev_bb), j); | |
5632 | } | |
5633 | if (curr_bb != last_bb) | |
5634 | { | |
5635 | /* Update df_get_live_out (curr_bb): */ | |
5636 | EXECUTE_IF_SET_IN_BITMAP (&check_only_regs, 0, j, bi) | |
5637 | { | |
5638 | live_p = bitmap_bit_p (&live_regs, j); | |
5639 | if (! live_p) | |
5640 | FOR_EACH_EDGE (e, ei, curr_bb->succs) | |
5641 | if (bitmap_bit_p (df_get_live_in (e->dest), j)) | |
5642 | { | |
5643 | live_p = true; | |
5644 | break; | |
5645 | } | |
5646 | if (live_p) | |
5647 | bitmap_set_bit (df_get_live_out (curr_bb), j); | |
5648 | else | |
5649 | bitmap_clear_bit (df_get_live_out (curr_bb), j); | |
5650 | } | |
5651 | } | |
5652 | prev_bb = curr_bb; | |
5653 | bitmap_and (&live_regs, &check_only_regs, df_get_live_out (curr_bb)); | |
5654 | } | |
44b94bdb | 5655 | if (! NONDEBUG_INSN_P (curr_insn)) |
55a2c322 VM |
5656 | continue; |
5657 | curr_id = lra_get_insn_recog_data (curr_insn); | |
8e9d68a9 | 5658 | curr_static_id = curr_id->insn_static_data; |
55a2c322 | 5659 | remove_p = false; |
53250f44 BS |
5660 | if ((set = single_set (curr_insn)) != NULL_RTX |
5661 | && REG_P (SET_DEST (set)) | |
55a2c322 | 5662 | && (regno = REGNO (SET_DEST (set))) >= FIRST_PSEUDO_REGISTER |
53250f44 | 5663 | && SET_DEST (set) != pic_offset_table_rtx |
55a2c322 VM |
5664 | && bitmap_bit_p (&check_only_regs, regno) |
5665 | && ! bitmap_bit_p (&live_regs, regno)) | |
5666 | remove_p = true; | |
5667 | /* See which defined values die here. */ | |
5668 | for (reg = curr_id->regs; reg != NULL; reg = reg->next) | |
5669 | if (reg->type == OP_OUT && ! reg->subreg_p) | |
5670 | bitmap_clear_bit (&live_regs, reg->regno); | |
8e9d68a9 VM |
5671 | for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next) |
5672 | if (reg->type == OP_OUT && ! reg->subreg_p) | |
5673 | bitmap_clear_bit (&live_regs, reg->regno); | |
9d86e84e VM |
5674 | if (curr_id->arg_hard_regs != NULL) |
5675 | /* Make clobbered argument hard registers die. */ | |
5676 | for (i = 0; (regno = curr_id->arg_hard_regs[i]) >= 0; i++) | |
5677 | if (regno >= FIRST_PSEUDO_REGISTER) | |
5678 | bitmap_clear_bit (&live_regs, regno - FIRST_PSEUDO_REGISTER); | |
55a2c322 VM |
5679 | /* Mark each used value as live. */ |
5680 | for (reg = curr_id->regs; reg != NULL; reg = reg->next) | |
d89ae27c | 5681 | if (reg->type != OP_OUT |
55a2c322 VM |
5682 | && bitmap_bit_p (&check_only_regs, reg->regno)) |
5683 | bitmap_set_bit (&live_regs, reg->regno); | |
8e9d68a9 VM |
5684 | for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next) |
5685 | if (reg->type != OP_OUT | |
5686 | && bitmap_bit_p (&check_only_regs, reg->regno)) | |
5687 | bitmap_set_bit (&live_regs, reg->regno); | |
5688 | if (curr_id->arg_hard_regs != NULL) | |
9d86e84e | 5689 | /* Make used argument hard registers live. */ |
8e9d68a9 | 5690 | for (i = 0; (regno = curr_id->arg_hard_regs[i]) >= 0; i++) |
9d86e84e VM |
5691 | if (regno < FIRST_PSEUDO_REGISTER |
5692 | && bitmap_bit_p (&check_only_regs, regno)) | |
8e9d68a9 | 5693 | bitmap_set_bit (&live_regs, regno); |
55a2c322 VM |
5694 | /* It is quite important to remove dead move insns because it |
5695 | means removing dead store. We don't need to process them for | |
5696 | constraints. */ | |
5697 | if (remove_p) | |
5698 | { | |
5699 | if (lra_dump_file != NULL) | |
5700 | { | |
5701 | fprintf (lra_dump_file, " Removing dead insn:\n "); | |
cfbeaedf | 5702 | dump_insn_slim (lra_dump_file, curr_insn); |
55a2c322 VM |
5703 | } |
5704 | lra_set_insn_deleted (curr_insn); | |
5705 | } | |
5706 | } | |
5707 | } | |
5708 | ||
5709 | /* The structure describes info to do an inheritance for the current | |
5710 | insn. We need to collect such info first before doing the | |
5711 | transformations because the transformations change the insn | |
5712 | internal representation. */ | |
5713 | struct to_inherit | |
5714 | { | |
5715 | /* Original regno. */ | |
5716 | int regno; | |
5717 | /* Subsequent insns which can inherit original reg value. */ | |
5718 | rtx insns; | |
5719 | }; | |
5720 | ||
5721 | /* Array containing all info for doing inheritance from the current | |
5722 | insn. */ | |
5723 | static struct to_inherit to_inherit[LRA_MAX_INSN_RELOADS]; | |
5724 | ||
5725 | /* Number elements in the previous array. */ | |
5726 | static int to_inherit_num; | |
5727 | ||
5728 | /* Add inheritance info REGNO and INSNS. Their meaning is described in | |
5729 | structure to_inherit. */ | |
5730 | static void | |
5731 | add_to_inherit (int regno, rtx insns) | |
5732 | { | |
5733 | int i; | |
5734 | ||
5735 | for (i = 0; i < to_inherit_num; i++) | |
5736 | if (to_inherit[i].regno == regno) | |
5737 | return; | |
5738 | lra_assert (to_inherit_num < LRA_MAX_INSN_RELOADS); | |
5739 | to_inherit[to_inherit_num].regno = regno; | |
5740 | to_inherit[to_inherit_num++].insns = insns; | |
5741 | } | |
5742 | ||
5743 | /* Return the last non-debug insn in basic block BB, or the block begin | |
5744 | note if none. */ | |
cfa434f6 | 5745 | static rtx_insn * |
55a2c322 VM |
5746 | get_last_insertion_point (basic_block bb) |
5747 | { | |
cfa434f6 | 5748 | rtx_insn *insn; |
55a2c322 VM |
5749 | |
5750 | FOR_BB_INSNS_REVERSE (bb, insn) | |
5751 | if (NONDEBUG_INSN_P (insn) || NOTE_INSN_BASIC_BLOCK_P (insn)) | |
5752 | return insn; | |
5753 | gcc_unreachable (); | |
5754 | } | |
5755 | ||
5756 | /* Set up RES by registers living on edges FROM except the edge (FROM, | |
5757 | TO) or by registers set up in a jump insn in BB FROM. */ | |
5758 | static void | |
5759 | get_live_on_other_edges (basic_block from, basic_block to, bitmap res) | |
5760 | { | |
cfa434f6 | 5761 | rtx_insn *last; |
55a2c322 VM |
5762 | struct lra_insn_reg *reg; |
5763 | edge e; | |
5764 | edge_iterator ei; | |
5765 | ||
5766 | lra_assert (to != NULL); | |
5767 | bitmap_clear (res); | |
5768 | FOR_EACH_EDGE (e, ei, from->succs) | |
5769 | if (e->dest != to) | |
5770 | bitmap_ior_into (res, df_get_live_in (e->dest)); | |
5771 | last = get_last_insertion_point (from); | |
5772 | if (! JUMP_P (last)) | |
5773 | return; | |
5774 | curr_id = lra_get_insn_recog_data (last); | |
5775 | for (reg = curr_id->regs; reg != NULL; reg = reg->next) | |
5776 | if (reg->type != OP_IN) | |
5777 | bitmap_set_bit (res, reg->regno); | |
5778 | } | |
f4eafc30 | 5779 | |
55a2c322 VM |
5780 | /* Used as a temporary results of some bitmap calculations. */ |
5781 | static bitmap_head temp_bitmap; | |
5782 | ||
8e9d68a9 VM |
5783 | /* We split for reloads of small class of hard regs. The following |
5784 | defines how many hard regs the class should have to be qualified as | |
5785 | small. The code is mostly oriented to x86/x86-64 architecture | |
5786 | where some insns need to use only specific register or pair of | |
5787 | registers and these register can live in RTL explicitly, e.g. for | |
5788 | parameter passing. */ | |
5789 | static const int max_small_class_regs_num = 2; | |
5790 | ||
55a2c322 VM |
5791 | /* Do inheritance/split transformations in EBB starting with HEAD and |
5792 | finishing on TAIL. We process EBB insns in the reverse order. | |
5793 | Return true if we did any inheritance/split transformation in the | |
5794 | EBB. | |
5795 | ||
5796 | We should avoid excessive splitting which results in worse code | |
5797 | because of inaccurate cost calculations for spilling new split | |
5798 | pseudos in such case. To achieve this we do splitting only if | |
5799 | register pressure is high in given basic block and there are reload | |
5800 | pseudos requiring hard registers. We could do more register | |
5801 | pressure calculations at any given program point to avoid necessary | |
5802 | splitting even more but it is to expensive and the current approach | |
5803 | works well enough. */ | |
5804 | static bool | |
cfa434f6 | 5805 | inherit_in_ebb (rtx_insn *head, rtx_insn *tail) |
55a2c322 VM |
5806 | { |
5807 | int i, src_regno, dst_regno, nregs; | |
df2980be | 5808 | bool change_p, succ_p, update_reloads_num_p; |
cfa434f6 | 5809 | rtx_insn *prev_insn, *last_insn; |
8a8330b7 | 5810 | rtx next_usage_insns, curr_set; |
55a2c322 VM |
5811 | enum reg_class cl; |
5812 | struct lra_insn_reg *reg; | |
5813 | basic_block last_processed_bb, curr_bb = NULL; | |
5814 | HARD_REG_SET potential_reload_hard_regs, live_hard_regs; | |
5815 | bitmap to_process; | |
5816 | unsigned int j; | |
5817 | bitmap_iterator bi; | |
5818 | bool head_p, after_p; | |
5819 | ||
5820 | change_p = false; | |
5821 | curr_usage_insns_check++; | |
8a8330b7 | 5822 | clear_invariants (); |
55a2c322 VM |
5823 | reloads_num = calls_num = 0; |
5824 | bitmap_clear (&check_only_regs); | |
8a8330b7 | 5825 | bitmap_clear (&invalid_invariant_regs); |
55a2c322 VM |
5826 | last_processed_bb = NULL; |
5827 | CLEAR_HARD_REG_SET (potential_reload_hard_regs); | |
8e9d68a9 VM |
5828 | COPY_HARD_REG_SET (live_hard_regs, eliminable_regset); |
5829 | IOR_HARD_REG_SET (live_hard_regs, lra_no_alloc_regs); | |
55a2c322 VM |
5830 | /* We don't process new insns generated in the loop. */ |
5831 | for (curr_insn = tail; curr_insn != PREV_INSN (head); curr_insn = prev_insn) | |
5832 | { | |
5833 | prev_insn = PREV_INSN (curr_insn); | |
5834 | if (BLOCK_FOR_INSN (curr_insn) != NULL) | |
5835 | curr_bb = BLOCK_FOR_INSN (curr_insn); | |
5836 | if (last_processed_bb != curr_bb) | |
5837 | { | |
5838 | /* We are at the end of BB. Add qualified living | |
5839 | pseudos for potential splitting. */ | |
5840 | to_process = df_get_live_out (curr_bb); | |
5841 | if (last_processed_bb != NULL) | |
f4eafc30 | 5842 | { |
55a2c322 VM |
5843 | /* We are somewhere in the middle of EBB. */ |
5844 | get_live_on_other_edges (curr_bb, last_processed_bb, | |
5845 | &temp_bitmap); | |
5846 | to_process = &temp_bitmap; | |
5847 | } | |
5848 | last_processed_bb = curr_bb; | |
5849 | last_insn = get_last_insertion_point (curr_bb); | |
5850 | after_p = (! JUMP_P (last_insn) | |
5851 | && (! CALL_P (last_insn) | |
5852 | || (find_reg_note (last_insn, | |
5853 | REG_NORETURN, NULL_RTX) == NULL_RTX | |
5854 | && ! SIBLING_CALL_P (last_insn)))); | |
55a2c322 VM |
5855 | CLEAR_HARD_REG_SET (potential_reload_hard_regs); |
5856 | EXECUTE_IF_SET_IN_BITMAP (to_process, 0, j, bi) | |
5857 | { | |
5858 | if ((int) j >= lra_constraint_new_regno_start) | |
5859 | break; | |
5860 | if (j < FIRST_PSEUDO_REGISTER || reg_renumber[j] >= 0) | |
5861 | { | |
5862 | if (j < FIRST_PSEUDO_REGISTER) | |
5863 | SET_HARD_REG_BIT (live_hard_regs, j); | |
5864 | else | |
5865 | add_to_hard_reg_set (&live_hard_regs, | |
5866 | PSEUDO_REGNO_MODE (j), | |
5867 | reg_renumber[j]); | |
5868 | setup_next_usage_insn (j, last_insn, reloads_num, after_p); | |
5869 | } | |
5870 | } | |
5871 | } | |
5872 | src_regno = dst_regno = -1; | |
8a8330b7 VM |
5873 | curr_set = single_set (curr_insn); |
5874 | if (curr_set != NULL_RTX && REG_P (SET_DEST (curr_set))) | |
5875 | dst_regno = REGNO (SET_DEST (curr_set)); | |
5876 | if (curr_set != NULL_RTX && REG_P (SET_SRC (curr_set))) | |
5877 | src_regno = REGNO (SET_SRC (curr_set)); | |
df2980be | 5878 | update_reloads_num_p = true; |
55a2c322 VM |
5879 | if (src_regno < lra_constraint_new_regno_start |
5880 | && src_regno >= FIRST_PSEUDO_REGISTER | |
5881 | && reg_renumber[src_regno] < 0 | |
5882 | && dst_regno >= lra_constraint_new_regno_start | |
5883 | && (cl = lra_get_allocno_class (dst_regno)) != NO_REGS) | |
5884 | { | |
5885 | /* 'reload_pseudo <- original_pseudo'. */ | |
8e9d68a9 VM |
5886 | if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num) |
5887 | reloads_num++; | |
df2980be | 5888 | update_reloads_num_p = false; |
55a2c322 VM |
5889 | succ_p = false; |
5890 | if (usage_insns[src_regno].check == curr_usage_insns_check | |
5891 | && (next_usage_insns = usage_insns[src_regno].insns) != NULL_RTX) | |
5892 | succ_p = inherit_reload_reg (false, src_regno, cl, | |
5893 | curr_insn, next_usage_insns); | |
5894 | if (succ_p) | |
5895 | change_p = true; | |
5896 | else | |
5897 | setup_next_usage_insn (src_regno, curr_insn, reloads_num, false); | |
5898 | if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs)) | |
5899 | IOR_HARD_REG_SET (potential_reload_hard_regs, | |
5900 | reg_class_contents[cl]); | |
5901 | } | |
8a8330b7 VM |
5902 | else if (src_regno < 0 |
5903 | && dst_regno >= lra_constraint_new_regno_start | |
5904 | && invariant_p (SET_SRC (curr_set)) | |
5905 | && (cl = lra_get_allocno_class (dst_regno)) != NO_REGS | |
f7abdf36 VM |
5906 | && ! bitmap_bit_p (&invalid_invariant_regs, dst_regno) |
5907 | && ! bitmap_bit_p (&invalid_invariant_regs, | |
5908 | ORIGINAL_REGNO(regno_reg_rtx[dst_regno]))) | |
8a8330b7 VM |
5909 | { |
5910 | /* 'reload_pseudo <- invariant'. */ | |
5911 | if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num) | |
5912 | reloads_num++; | |
5913 | update_reloads_num_p = false; | |
5914 | if (process_invariant_for_inheritance (SET_DEST (curr_set), SET_SRC (curr_set))) | |
5915 | change_p = true; | |
5916 | if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs)) | |
5917 | IOR_HARD_REG_SET (potential_reload_hard_regs, | |
5918 | reg_class_contents[cl]); | |
5919 | } | |
55a2c322 VM |
5920 | else if (src_regno >= lra_constraint_new_regno_start |
5921 | && dst_regno < lra_constraint_new_regno_start | |
5922 | && dst_regno >= FIRST_PSEUDO_REGISTER | |
5923 | && reg_renumber[dst_regno] < 0 | |
5924 | && (cl = lra_get_allocno_class (src_regno)) != NO_REGS | |
5925 | && usage_insns[dst_regno].check == curr_usage_insns_check | |
5926 | && (next_usage_insns | |
5927 | = usage_insns[dst_regno].insns) != NULL_RTX) | |
5928 | { | |
8e9d68a9 VM |
5929 | if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num) |
5930 | reloads_num++; | |
df2980be | 5931 | update_reloads_num_p = false; |
55a2c322 VM |
5932 | /* 'original_pseudo <- reload_pseudo'. */ |
5933 | if (! JUMP_P (curr_insn) | |
5934 | && inherit_reload_reg (true, dst_regno, cl, | |
5935 | curr_insn, next_usage_insns)) | |
5936 | change_p = true; | |
5937 | /* Invalidate. */ | |
5938 | usage_insns[dst_regno].check = 0; | |
5939 | if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs)) | |
5940 | IOR_HARD_REG_SET (potential_reload_hard_regs, | |
5941 | reg_class_contents[cl]); | |
5942 | } | |
5943 | else if (INSN_P (curr_insn)) | |
5944 | { | |
2f259720 | 5945 | int iter; |
55a2c322 VM |
5946 | int max_uid = get_max_uid (); |
5947 | ||
5948 | curr_id = lra_get_insn_recog_data (curr_insn); | |
2f259720 | 5949 | curr_static_id = curr_id->insn_static_data; |
55a2c322 VM |
5950 | to_inherit_num = 0; |
5951 | /* Process insn definitions. */ | |
2f259720 VM |
5952 | for (iter = 0; iter < 2; iter++) |
5953 | for (reg = iter == 0 ? curr_id->regs : curr_static_id->hard_regs; | |
5954 | reg != NULL; | |
5955 | reg = reg->next) | |
5956 | if (reg->type != OP_IN | |
5957 | && (dst_regno = reg->regno) < lra_constraint_new_regno_start) | |
5958 | { | |
5959 | if (dst_regno >= FIRST_PSEUDO_REGISTER && reg->type == OP_OUT | |
5960 | && reg_renumber[dst_regno] < 0 && ! reg->subreg_p | |
5961 | && usage_insns[dst_regno].check == curr_usage_insns_check | |
5962 | && (next_usage_insns | |
5963 | = usage_insns[dst_regno].insns) != NULL_RTX) | |
5964 | { | |
5965 | struct lra_insn_reg *r; | |
5966 | ||
5967 | for (r = curr_id->regs; r != NULL; r = r->next) | |
5968 | if (r->type != OP_OUT && r->regno == dst_regno) | |
5969 | break; | |
5970 | /* Don't do inheritance if the pseudo is also | |
5971 | used in the insn. */ | |
5972 | if (r == NULL) | |
5973 | /* We can not do inheritance right now | |
5974 | because the current insn reg info (chain | |
5975 | regs) can change after that. */ | |
5976 | add_to_inherit (dst_regno, next_usage_insns); | |
5977 | } | |
5978 | /* We can not process one reg twice here because of | |
5979 | usage_insns invalidation. */ | |
5980 | if ((dst_regno < FIRST_PSEUDO_REGISTER | |
5981 | || reg_renumber[dst_regno] >= 0) | |
e32e4c4a | 5982 | && ! reg->subreg_p && reg->type != OP_IN) |
2f259720 VM |
5983 | { |
5984 | HARD_REG_SET s; | |
5985 | ||
5986 | if (split_if_necessary (dst_regno, reg->biggest_mode, | |
5987 | potential_reload_hard_regs, | |
5988 | false, curr_insn, max_uid)) | |
5989 | change_p = true; | |
5990 | CLEAR_HARD_REG_SET (s); | |
5991 | if (dst_regno < FIRST_PSEUDO_REGISTER) | |
5992 | add_to_hard_reg_set (&s, reg->biggest_mode, dst_regno); | |
5993 | else | |
5994 | add_to_hard_reg_set (&s, PSEUDO_REGNO_MODE (dst_regno), | |
5995 | reg_renumber[dst_regno]); | |
5996 | AND_COMPL_HARD_REG_SET (live_hard_regs, s); | |
5997 | } | |
5998 | /* We should invalidate potential inheritance or | |
5999 | splitting for the current insn usages to the next | |
6000 | usage insns (see code below) as the output pseudo | |
6001 | prevents this. */ | |
6002 | if ((dst_regno >= FIRST_PSEUDO_REGISTER | |
6003 | && reg_renumber[dst_regno] < 0) | |
6004 | || (reg->type == OP_OUT && ! reg->subreg_p | |
6005 | && (dst_regno < FIRST_PSEUDO_REGISTER | |
6006 | || reg_renumber[dst_regno] >= 0))) | |
6007 | { | |
6008 | /* Invalidate and mark definitions. */ | |
6009 | if (dst_regno >= FIRST_PSEUDO_REGISTER) | |
6010 | usage_insns[dst_regno].check = -(int) INSN_UID (curr_insn); | |
6011 | else | |
6012 | { | |
6013 | nregs = hard_regno_nregs[dst_regno][reg->biggest_mode]; | |
6014 | for (i = 0; i < nregs; i++) | |
6015 | usage_insns[dst_regno + i].check | |
6016 | = -(int) INSN_UID (curr_insn); | |
6017 | } | |
6018 | } | |
6019 | } | |
9d86e84e VM |
6020 | /* Process clobbered call regs. */ |
6021 | if (curr_id->arg_hard_regs != NULL) | |
6022 | for (i = 0; (dst_regno = curr_id->arg_hard_regs[i]) >= 0; i++) | |
6023 | if (dst_regno >= FIRST_PSEUDO_REGISTER) | |
6024 | usage_insns[dst_regno - FIRST_PSEUDO_REGISTER].check | |
6025 | = -(int) INSN_UID (curr_insn); | |
55a2c322 VM |
6026 | if (! JUMP_P (curr_insn)) |
6027 | for (i = 0; i < to_inherit_num; i++) | |
6028 | if (inherit_reload_reg (true, to_inherit[i].regno, | |
6029 | ALL_REGS, curr_insn, | |
6030 | to_inherit[i].insns)) | |
6031 | change_p = true; | |
6032 | if (CALL_P (curr_insn)) | |
6033 | { | |
cfa434f6 DM |
6034 | rtx cheap, pat, dest; |
6035 | rtx_insn *restore; | |
55a2c322 VM |
6036 | int regno, hard_regno; |
6037 | ||
6038 | calls_num++; | |
6039 | if ((cheap = find_reg_note (curr_insn, | |
6040 | REG_RETURNED, NULL_RTX)) != NULL_RTX | |
6041 | && ((cheap = XEXP (cheap, 0)), true) | |
6042 | && (regno = REGNO (cheap)) >= FIRST_PSEUDO_REGISTER | |
6043 | && (hard_regno = reg_renumber[regno]) >= 0 | |
6044 | /* If there are pending saves/restores, the | |
6045 | optimization is not worth. */ | |
6046 | && usage_insns[regno].calls_num == calls_num - 1 | |
6047 | && TEST_HARD_REG_BIT (call_used_reg_set, hard_regno)) | |
6048 | { | |
6049 | /* Restore the pseudo from the call result as | |
6050 | REG_RETURNED note says that the pseudo value is | |
6051 | in the call result and the pseudo is an argument | |
6052 | of the call. */ | |
6053 | pat = PATTERN (curr_insn); | |
6054 | if (GET_CODE (pat) == PARALLEL) | |
6055 | pat = XVECEXP (pat, 0, 0); | |
6056 | dest = SET_DEST (pat); | |
54bddf1d IE |
6057 | /* For multiple return values dest is PARALLEL. |
6058 | Currently we handle only single return value case. */ | |
6059 | if (REG_P (dest)) | |
6060 | { | |
6061 | start_sequence (); | |
6062 | emit_move_insn (cheap, copy_rtx (dest)); | |
6063 | restore = get_insns (); | |
6064 | end_sequence (); | |
6065 | lra_process_new_insns (curr_insn, NULL, restore, | |
6066 | "Inserting call parameter restore"); | |
6067 | /* We don't need to save/restore of the pseudo from | |
6068 | this call. */ | |
6069 | usage_insns[regno].calls_num = calls_num; | |
6070 | bitmap_set_bit (&check_only_regs, regno); | |
6071 | } | |
55a2c322 VM |
6072 | } |
6073 | } | |
6074 | to_inherit_num = 0; | |
6075 | /* Process insn usages. */ | |
2f259720 VM |
6076 | for (iter = 0; iter < 2; iter++) |
6077 | for (reg = iter == 0 ? curr_id->regs : curr_static_id->hard_regs; | |
6078 | reg != NULL; | |
6079 | reg = reg->next) | |
6080 | if ((reg->type != OP_OUT | |
6081 | || (reg->type == OP_OUT && reg->subreg_p)) | |
6082 | && (src_regno = reg->regno) < lra_constraint_new_regno_start) | |
6083 | { | |
6084 | if (src_regno >= FIRST_PSEUDO_REGISTER | |
6085 | && reg_renumber[src_regno] < 0 && reg->type == OP_IN) | |
6086 | { | |
6087 | if (usage_insns[src_regno].check == curr_usage_insns_check | |
6088 | && (next_usage_insns | |
6089 | = usage_insns[src_regno].insns) != NULL_RTX | |
6090 | && NONDEBUG_INSN_P (curr_insn)) | |
6091 | add_to_inherit (src_regno, next_usage_insns); | |
6092 | else if (usage_insns[src_regno].check | |
6093 | != -(int) INSN_UID (curr_insn)) | |
6094 | /* Add usages but only if the reg is not set up | |
6095 | in the same insn. */ | |
6096 | add_next_usage_insn (src_regno, curr_insn, reloads_num); | |
6097 | } | |
6098 | else if (src_regno < FIRST_PSEUDO_REGISTER | |
6099 | || reg_renumber[src_regno] >= 0) | |
6100 | { | |
6101 | bool before_p; | |
e67d1102 | 6102 | rtx_insn *use_insn = curr_insn; |
2f259720 VM |
6103 | |
6104 | before_p = (JUMP_P (curr_insn) | |
6105 | || (CALL_P (curr_insn) && reg->type == OP_IN)); | |
6106 | if (NONDEBUG_INSN_P (curr_insn) | |
8e9d68a9 | 6107 | && (! JUMP_P (curr_insn) || reg->type == OP_IN) |
2f259720 VM |
6108 | && split_if_necessary (src_regno, reg->biggest_mode, |
6109 | potential_reload_hard_regs, | |
6110 | before_p, curr_insn, max_uid)) | |
6111 | { | |
6112 | if (reg->subreg_p) | |
6113 | lra_risky_transformations_p = true; | |
6114 | change_p = true; | |
8e9d68a9 | 6115 | /* Invalidate. */ |
2f259720 VM |
6116 | usage_insns[src_regno].check = 0; |
6117 | if (before_p) | |
6118 | use_insn = PREV_INSN (curr_insn); | |
6119 | } | |
6120 | if (NONDEBUG_INSN_P (curr_insn)) | |
6121 | { | |
6122 | if (src_regno < FIRST_PSEUDO_REGISTER) | |
6123 | add_to_hard_reg_set (&live_hard_regs, | |
6124 | reg->biggest_mode, src_regno); | |
6125 | else | |
6126 | add_to_hard_reg_set (&live_hard_regs, | |
6127 | PSEUDO_REGNO_MODE (src_regno), | |
6128 | reg_renumber[src_regno]); | |
6129 | } | |
6130 | add_next_usage_insn (src_regno, use_insn, reloads_num); | |
6131 | } | |
6132 | } | |
9d86e84e | 6133 | /* Process used call regs. */ |
df2980be VM |
6134 | if (curr_id->arg_hard_regs != NULL) |
6135 | for (i = 0; (src_regno = curr_id->arg_hard_regs[i]) >= 0; i++) | |
6136 | if (src_regno < FIRST_PSEUDO_REGISTER) | |
6137 | { | |
6138 | SET_HARD_REG_BIT (live_hard_regs, src_regno); | |
6139 | add_next_usage_insn (src_regno, curr_insn, reloads_num); | |
6140 | } | |
55a2c322 VM |
6141 | for (i = 0; i < to_inherit_num; i++) |
6142 | { | |
6143 | src_regno = to_inherit[i].regno; | |
6144 | if (inherit_reload_reg (false, src_regno, ALL_REGS, | |
6145 | curr_insn, to_inherit[i].insns)) | |
6146 | change_p = true; | |
6147 | else | |
6148 | setup_next_usage_insn (src_regno, curr_insn, reloads_num, false); | |
6149 | } | |
6150 | } | |
df2980be | 6151 | if (update_reloads_num_p |
8a8330b7 | 6152 | && NONDEBUG_INSN_P (curr_insn) && curr_set != NULL_RTX) |
df2980be VM |
6153 | { |
6154 | int regno = -1; | |
8a8330b7 VM |
6155 | if ((REG_P (SET_DEST (curr_set)) |
6156 | && (regno = REGNO (SET_DEST (curr_set))) >= lra_constraint_new_regno_start | |
df2980be VM |
6157 | && reg_renumber[regno] < 0 |
6158 | && (cl = lra_get_allocno_class (regno)) != NO_REGS) | |
8a8330b7 VM |
6159 | || (REG_P (SET_SRC (curr_set)) |
6160 | && (regno = REGNO (SET_SRC (curr_set))) >= lra_constraint_new_regno_start | |
df2980be VM |
6161 | && reg_renumber[regno] < 0 |
6162 | && (cl = lra_get_allocno_class (regno)) != NO_REGS)) | |
6163 | { | |
8e9d68a9 VM |
6164 | if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num) |
6165 | reloads_num++; | |
df2980be VM |
6166 | if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs)) |
6167 | IOR_HARD_REG_SET (potential_reload_hard_regs, | |
6168 | reg_class_contents[cl]); | |
6169 | } | |
6170 | } | |
8a8330b7 VM |
6171 | if (NONDEBUG_INSN_P (curr_insn)) |
6172 | { | |
6173 | int regno; | |
6174 | ||
6175 | /* Invalidate invariants with changed regs. */ | |
6176 | curr_id = lra_get_insn_recog_data (curr_insn); | |
6177 | for (reg = curr_id->regs; reg != NULL; reg = reg->next) | |
6178 | if (reg->type != OP_IN) | |
f7abdf36 VM |
6179 | { |
6180 | bitmap_set_bit (&invalid_invariant_regs, reg->regno); | |
6181 | bitmap_set_bit (&invalid_invariant_regs, | |
6182 | ORIGINAL_REGNO (regno_reg_rtx[reg->regno])); | |
6183 | } | |
8a8330b7 VM |
6184 | curr_static_id = curr_id->insn_static_data; |
6185 | for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next) | |
6186 | if (reg->type != OP_IN) | |
6187 | bitmap_set_bit (&invalid_invariant_regs, reg->regno); | |
6188 | if (curr_id->arg_hard_regs != NULL) | |
6189 | for (i = 0; (regno = curr_id->arg_hard_regs[i]) >= 0; i++) | |
f7abdf36 | 6190 | if (regno >= FIRST_PSEUDO_REGISTER) |
8a8330b7 | 6191 | bitmap_set_bit (&invalid_invariant_regs, |
f7abdf36 | 6192 | regno - FIRST_PSEUDO_REGISTER); |
8a8330b7 | 6193 | } |
55a2c322 VM |
6194 | /* We reached the start of the current basic block. */ |
6195 | if (prev_insn == NULL_RTX || prev_insn == PREV_INSN (head) | |
6196 | || BLOCK_FOR_INSN (prev_insn) != curr_bb) | |
6197 | { | |
6198 | /* We reached the beginning of the current block -- do | |
6199 | rest of spliting in the current BB. */ | |
6200 | to_process = df_get_live_in (curr_bb); | |
6201 | if (BLOCK_FOR_INSN (head) != curr_bb) | |
f4eafc30 | 6202 | { |
55a2c322 VM |
6203 | /* We are somewhere in the middle of EBB. */ |
6204 | get_live_on_other_edges (EDGE_PRED (curr_bb, 0)->src, | |
6205 | curr_bb, &temp_bitmap); | |
6206 | to_process = &temp_bitmap; | |
6207 | } | |
6208 | head_p = true; | |
6209 | EXECUTE_IF_SET_IN_BITMAP (to_process, 0, j, bi) | |
6210 | { | |
6211 | if ((int) j >= lra_constraint_new_regno_start) | |
6212 | break; | |
6213 | if (((int) j < FIRST_PSEUDO_REGISTER || reg_renumber[j] >= 0) | |
6214 | && usage_insns[j].check == curr_usage_insns_check | |
6215 | && (next_usage_insns = usage_insns[j].insns) != NULL_RTX) | |
6216 | { | |
6217 | if (need_for_split_p (potential_reload_hard_regs, j)) | |
6218 | { | |
6219 | if (lra_dump_file != NULL && head_p) | |
6220 | { | |
6221 | fprintf (lra_dump_file, | |
6222 | " ----------------------------------\n"); | |
6223 | head_p = false; | |
6224 | } | |
6225 | if (split_reg (false, j, bb_note (curr_bb), | |
6226 | next_usage_insns)) | |
6227 | change_p = true; | |
6228 | } | |
6229 | usage_insns[j].check = 0; | |
6230 | } | |
6231 | } | |
6232 | } | |
6233 | } | |
6234 | return change_p; | |
6235 | } | |
6236 | ||
6237 | /* This value affects EBB forming. If probability of edge from EBB to | |
6238 | a BB is not greater than the following value, we don't add the BB | |
f4eafc30 | 6239 | to EBB. */ |
fb8a0e40 VM |
6240 | #define EBB_PROBABILITY_CUTOFF \ |
6241 | ((REG_BR_PROB_BASE * LRA_INHERITANCE_EBB_PROBABILITY_CUTOFF) / 100) | |
55a2c322 VM |
6242 | |
6243 | /* Current number of inheritance/split iteration. */ | |
6244 | int lra_inheritance_iter; | |
6245 | ||
6246 | /* Entry function for inheritance/split pass. */ | |
6247 | void | |
6248 | lra_inheritance (void) | |
6249 | { | |
6250 | int i; | |
6251 | basic_block bb, start_bb; | |
6252 | edge e; | |
6253 | ||
55a2c322 | 6254 | lra_inheritance_iter++; |
8e3a4869 | 6255 | if (lra_inheritance_iter > LRA_MAX_INHERITANCE_PASSES) |
e731262b VM |
6256 | return; |
6257 | timevar_push (TV_LRA_INHERITANCE); | |
55a2c322 VM |
6258 | if (lra_dump_file != NULL) |
6259 | fprintf (lra_dump_file, "\n********** Inheritance #%d: **********\n\n", | |
6260 | lra_inheritance_iter); | |
6261 | curr_usage_insns_check = 0; | |
6262 | usage_insns = XNEWVEC (struct usage_insns, lra_constraint_new_regno_start); | |
6263 | for (i = 0; i < lra_constraint_new_regno_start; i++) | |
6264 | usage_insns[i].check = 0; | |
6265 | bitmap_initialize (&check_only_regs, ®_obstack); | |
8a8330b7 | 6266 | bitmap_initialize (&invalid_invariant_regs, ®_obstack); |
55a2c322 VM |
6267 | bitmap_initialize (&live_regs, ®_obstack); |
6268 | bitmap_initialize (&temp_bitmap, ®_obstack); | |
6269 | bitmap_initialize (&ebb_global_regs, ®_obstack); | |
11cd3bed | 6270 | FOR_EACH_BB_FN (bb, cfun) |
55a2c322 VM |
6271 | { |
6272 | start_bb = bb; | |
6273 | if (lra_dump_file != NULL) | |
6274 | fprintf (lra_dump_file, "EBB"); | |
6275 | /* Form a EBB starting with BB. */ | |
6276 | bitmap_clear (&ebb_global_regs); | |
6277 | bitmap_ior_into (&ebb_global_regs, df_get_live_in (bb)); | |
6278 | for (;;) | |
6279 | { | |
6280 | if (lra_dump_file != NULL) | |
6281 | fprintf (lra_dump_file, " %d", bb->index); | |
fefa31b5 DM |
6282 | if (bb->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun) |
6283 | || LABEL_P (BB_HEAD (bb->next_bb))) | |
55a2c322 VM |
6284 | break; |
6285 | e = find_fallthru_edge (bb->succs); | |
6286 | if (! e) | |
6287 | break; | |
fb8a0e40 | 6288 | if (e->probability < EBB_PROBABILITY_CUTOFF) |
55a2c322 VM |
6289 | break; |
6290 | bb = bb->next_bb; | |
6291 | } | |
6292 | bitmap_ior_into (&ebb_global_regs, df_get_live_out (bb)); | |
6293 | if (lra_dump_file != NULL) | |
6294 | fprintf (lra_dump_file, "\n"); | |
6295 | if (inherit_in_ebb (BB_HEAD (start_bb), BB_END (bb))) | |
6296 | /* Remember that the EBB head and tail can change in | |
6297 | inherit_in_ebb. */ | |
6298 | update_ebb_live_info (BB_HEAD (start_bb), BB_END (bb)); | |
6299 | } | |
6300 | bitmap_clear (&ebb_global_regs); | |
6301 | bitmap_clear (&temp_bitmap); | |
6302 | bitmap_clear (&live_regs); | |
8a8330b7 | 6303 | bitmap_clear (&invalid_invariant_regs); |
55a2c322 VM |
6304 | bitmap_clear (&check_only_regs); |
6305 | free (usage_insns); | |
6306 | ||
6307 | timevar_pop (TV_LRA_INHERITANCE); | |
6308 | } | |
6309 | ||
6310 | \f | |
6311 | ||
6312 | /* This page contains code to undo failed inheritance/split | |
6313 | transformations. */ | |
6314 | ||
6315 | /* Current number of iteration undoing inheritance/split. */ | |
6316 | int lra_undo_inheritance_iter; | |
6317 | ||
6318 | /* Fix BB live info LIVE after removing pseudos created on pass doing | |
6319 | inheritance/split which are REMOVED_PSEUDOS. */ | |
6320 | static void | |
6321 | fix_bb_live_info (bitmap live, bitmap removed_pseudos) | |
6322 | { | |
6323 | unsigned int regno; | |
6324 | bitmap_iterator bi; | |
6325 | ||
6326 | EXECUTE_IF_SET_IN_BITMAP (removed_pseudos, 0, regno, bi) | |
8a8330b7 VM |
6327 | if (bitmap_clear_bit (live, regno) |
6328 | && REG_P (lra_reg_info[regno].restore_rtx)) | |
6329 | bitmap_set_bit (live, REGNO (lra_reg_info[regno].restore_rtx)); | |
55a2c322 VM |
6330 | } |
6331 | ||
6332 | /* Return regno of the (subreg of) REG. Otherwise, return a negative | |
6333 | number. */ | |
6334 | static int | |
6335 | get_regno (rtx reg) | |
6336 | { | |
6337 | if (GET_CODE (reg) == SUBREG) | |
6338 | reg = SUBREG_REG (reg); | |
6339 | if (REG_P (reg)) | |
6340 | return REGNO (reg); | |
6341 | return -1; | |
6342 | } | |
6343 | ||
cefe08a4 VM |
6344 | /* Delete a move INSN with destination reg DREGNO and a previous |
6345 | clobber insn with the same regno. The inheritance/split code can | |
6346 | generate moves with preceding clobber and when we delete such moves | |
6347 | we should delete the clobber insn too to keep the correct life | |
6348 | info. */ | |
6349 | static void | |
6350 | delete_move_and_clobber (rtx_insn *insn, int dregno) | |
6351 | { | |
6352 | rtx_insn *prev_insn = PREV_INSN (insn); | |
6353 | ||
6354 | lra_set_insn_deleted (insn); | |
79b57d18 | 6355 | lra_assert (dregno >= 0); |
cefe08a4 VM |
6356 | if (prev_insn != NULL && NONDEBUG_INSN_P (prev_insn) |
6357 | && GET_CODE (PATTERN (prev_insn)) == CLOBBER | |
6358 | && dregno == get_regno (XEXP (PATTERN (prev_insn), 0))) | |
6359 | lra_set_insn_deleted (prev_insn); | |
6360 | } | |
6361 | ||
55a2c322 VM |
6362 | /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and |
6363 | return true if we did any change. The undo transformations for | |
6364 | inheritance looks like | |
6365 | i <- i2 | |
6366 | p <- i => p <- i2 | |
6367 | or removing | |
6368 | p <- i, i <- p, and i <- i3 | |
6369 | where p is original pseudo from which inheritance pseudo i was | |
6370 | created, i and i3 are removed inheritance pseudos, i2 is another | |
6371 | not removed inheritance pseudo. All split pseudos or other | |
6372 | occurrences of removed inheritance pseudos are changed on the | |
6373 | corresponding original pseudos. | |
6374 | ||
6375 | The function also schedules insns changed and created during | |
6376 | inheritance/split pass for processing by the subsequent constraint | |
6377 | pass. */ | |
6378 | static bool | |
6379 | remove_inheritance_pseudos (bitmap remove_pseudos) | |
6380 | { | |
6381 | basic_block bb; | |
8a8330b7 VM |
6382 | int regno, sregno, prev_sregno, dregno; |
6383 | rtx restore_rtx; | |
cfa434f6 DM |
6384 | rtx set, prev_set; |
6385 | rtx_insn *prev_insn; | |
55a2c322 VM |
6386 | bool change_p, done_p; |
6387 | ||
6388 | change_p = ! bitmap_empty_p (remove_pseudos); | |
6389 | /* We can not finish the function right away if CHANGE_P is true | |
6390 | because we need to marks insns affected by previous | |
6391 | inheritance/split pass for processing by the subsequent | |
6392 | constraint pass. */ | |
11cd3bed | 6393 | FOR_EACH_BB_FN (bb, cfun) |
55a2c322 VM |
6394 | { |
6395 | fix_bb_live_info (df_get_live_in (bb), remove_pseudos); | |
6396 | fix_bb_live_info (df_get_live_out (bb), remove_pseudos); | |
6397 | FOR_BB_INSNS_REVERSE (bb, curr_insn) | |
6398 | { | |
6399 | if (! INSN_P (curr_insn)) | |
6400 | continue; | |
6401 | done_p = false; | |
6402 | sregno = dregno = -1; | |
6403 | if (change_p && NONDEBUG_INSN_P (curr_insn) | |
6404 | && (set = single_set (curr_insn)) != NULL_RTX) | |
6405 | { | |
6406 | dregno = get_regno (SET_DEST (set)); | |
6407 | sregno = get_regno (SET_SRC (set)); | |
6408 | } | |
f4eafc30 | 6409 | |
55a2c322 VM |
6410 | if (sregno >= 0 && dregno >= 0) |
6411 | { | |
8a8330b7 VM |
6412 | if (bitmap_bit_p (remove_pseudos, dregno) |
6413 | && ! REG_P (lra_reg_info[dregno].restore_rtx)) | |
6414 | { | |
6415 | /* invariant inheritance pseudo <- original pseudo */ | |
6416 | if (lra_dump_file != NULL) | |
6417 | { | |
6418 | fprintf (lra_dump_file, " Removing invariant inheritance:\n"); | |
6419 | dump_insn_slim (lra_dump_file, curr_insn); | |
6420 | fprintf (lra_dump_file, "\n"); | |
6421 | } | |
6422 | delete_move_and_clobber (curr_insn, dregno); | |
6423 | done_p = true; | |
6424 | } | |
6425 | else if (bitmap_bit_p (remove_pseudos, sregno) | |
6426 | && ! REG_P (lra_reg_info[sregno].restore_rtx)) | |
6427 | { | |
6428 | /* reload pseudo <- invariant inheritance pseudo */ | |
6429 | start_sequence (); | |
6430 | /* We can not just change the source. It might be | |
6431 | an insn different from the move. */ | |
b10d44ef | 6432 | emit_insn (lra_reg_info[sregno].restore_rtx); |
8a8330b7 VM |
6433 | rtx_insn *new_insns = get_insns (); |
6434 | end_sequence (); | |
b10d44ef VM |
6435 | lra_assert (single_set (new_insns) != NULL |
6436 | && SET_DEST (set) == SET_DEST (single_set (new_insns))); | |
8a8330b7 VM |
6437 | lra_process_new_insns (curr_insn, NULL, new_insns, |
6438 | "Changing reload<-invariant inheritance"); | |
6439 | delete_move_and_clobber (curr_insn, dregno); | |
6440 | done_p = true; | |
6441 | } | |
6442 | else if ((bitmap_bit_p (remove_pseudos, sregno) | |
6443 | && (get_regno (lra_reg_info[sregno].restore_rtx) == dregno | |
6444 | || (bitmap_bit_p (remove_pseudos, dregno) | |
6445 | && get_regno (lra_reg_info[sregno].restore_rtx) >= 0 | |
6446 | && (get_regno (lra_reg_info[sregno].restore_rtx) | |
6447 | == get_regno (lra_reg_info[dregno].restore_rtx))))) | |
55a2c322 | 6448 | || (bitmap_bit_p (remove_pseudos, dregno) |
8a8330b7 | 6449 | && get_regno (lra_reg_info[dregno].restore_rtx) == sregno)) |
55a2c322 VM |
6450 | /* One of the following cases: |
6451 | original <- removed inheritance pseudo | |
6452 | removed inherit pseudo <- another removed inherit pseudo | |
6453 | removed inherit pseudo <- original pseudo | |
6454 | Or | |
6455 | removed_split_pseudo <- original_reg | |
6456 | original_reg <- removed_split_pseudo */ | |
6457 | { | |
6458 | if (lra_dump_file != NULL) | |
6459 | { | |
6460 | fprintf (lra_dump_file, " Removing %s:\n", | |
6461 | bitmap_bit_p (&lra_split_regs, sregno) | |
6462 | || bitmap_bit_p (&lra_split_regs, dregno) | |
6463 | ? "split" : "inheritance"); | |
cfbeaedf | 6464 | dump_insn_slim (lra_dump_file, curr_insn); |
55a2c322 | 6465 | } |
cefe08a4 | 6466 | delete_move_and_clobber (curr_insn, dregno); |
55a2c322 VM |
6467 | done_p = true; |
6468 | } | |
6469 | else if (bitmap_bit_p (remove_pseudos, sregno) | |
6470 | && bitmap_bit_p (&lra_inheritance_pseudos, sregno)) | |
6471 | { | |
6472 | /* Search the following pattern: | |
6473 | inherit_or_split_pseudo1 <- inherit_or_split_pseudo2 | |
6474 | original_pseudo <- inherit_or_split_pseudo1 | |
6475 | where the 2nd insn is the current insn and | |
6476 | inherit_or_split_pseudo2 is not removed. If it is found, | |
6477 | change the current insn onto: | |
6478 | original_pseudo <- inherit_or_split_pseudo2. */ | |
6479 | for (prev_insn = PREV_INSN (curr_insn); | |
6480 | prev_insn != NULL_RTX && ! NONDEBUG_INSN_P (prev_insn); | |
6481 | prev_insn = PREV_INSN (prev_insn)) | |
6482 | ; | |
6483 | if (prev_insn != NULL_RTX && BLOCK_FOR_INSN (prev_insn) == bb | |
6484 | && (prev_set = single_set (prev_insn)) != NULL_RTX | |
6485 | /* There should be no subregs in insn we are | |
6486 | searching because only the original reg might | |
6487 | be in subreg when we changed the mode of | |
6488 | load/store for splitting. */ | |
6489 | && REG_P (SET_DEST (prev_set)) | |
6490 | && REG_P (SET_SRC (prev_set)) | |
6491 | && (int) REGNO (SET_DEST (prev_set)) == sregno | |
6492 | && ((prev_sregno = REGNO (SET_SRC (prev_set))) | |
6493 | >= FIRST_PSEUDO_REGISTER) | |
8a8330b7 VM |
6494 | && (lra_reg_info[prev_sregno].restore_rtx == NULL_RTX |
6495 | || | |
6496 | /* As we consider chain of inheritance or | |
6497 | splitting described in above comment we should | |
6498 | check that sregno and prev_sregno were | |
6499 | inheritance/split pseudos created from the | |
6500 | same original regno. */ | |
6501 | (get_regno (lra_reg_info[sregno].restore_rtx) >= 0 | |
6502 | && (get_regno (lra_reg_info[sregno].restore_rtx) | |
6503 | == get_regno (lra_reg_info[prev_sregno].restore_rtx)))) | |
55a2c322 VM |
6504 | && ! bitmap_bit_p (remove_pseudos, prev_sregno)) |
6505 | { | |
6506 | lra_assert (GET_MODE (SET_SRC (prev_set)) | |
6507 | == GET_MODE (regno_reg_rtx[sregno])); | |
6508 | if (GET_CODE (SET_SRC (set)) == SUBREG) | |
6509 | SUBREG_REG (SET_SRC (set)) = SET_SRC (prev_set); | |
6510 | else | |
6511 | SET_SRC (set) = SET_SRC (prev_set); | |
12b308fa VM |
6512 | /* As we are finishing with processing the insn |
6513 | here, check the destination too as it might | |
6514 | inheritance pseudo for another pseudo. */ | |
6515 | if (bitmap_bit_p (remove_pseudos, dregno) | |
6516 | && bitmap_bit_p (&lra_inheritance_pseudos, dregno) | |
8a8330b7 VM |
6517 | && (restore_rtx |
6518 | = lra_reg_info[dregno].restore_rtx) != NULL_RTX) | |
12b308fa VM |
6519 | { |
6520 | if (GET_CODE (SET_DEST (set)) == SUBREG) | |
8a8330b7 | 6521 | SUBREG_REG (SET_DEST (set)) = restore_rtx; |
12b308fa | 6522 | else |
8a8330b7 | 6523 | SET_DEST (set) = restore_rtx; |
12b308fa | 6524 | } |
55a2c322 VM |
6525 | lra_push_insn_and_update_insn_regno_info (curr_insn); |
6526 | lra_set_used_insn_alternative_by_uid | |
6527 | (INSN_UID (curr_insn), -1); | |
6528 | done_p = true; | |
6529 | if (lra_dump_file != NULL) | |
6530 | { | |
6531 | fprintf (lra_dump_file, " Change reload insn:\n"); | |
cfbeaedf | 6532 | dump_insn_slim (lra_dump_file, curr_insn); |
55a2c322 VM |
6533 | } |
6534 | } | |
6535 | } | |
6536 | } | |
6537 | if (! done_p) | |
6538 | { | |
6539 | struct lra_insn_reg *reg; | |
6540 | bool restored_regs_p = false; | |
6541 | bool kept_regs_p = false; | |
6542 | ||
6543 | curr_id = lra_get_insn_recog_data (curr_insn); | |
6544 | for (reg = curr_id->regs; reg != NULL; reg = reg->next) | |
6545 | { | |
6546 | regno = reg->regno; | |
8a8330b7 VM |
6547 | restore_rtx = lra_reg_info[regno].restore_rtx; |
6548 | if (restore_rtx != NULL_RTX) | |
55a2c322 VM |
6549 | { |
6550 | if (change_p && bitmap_bit_p (remove_pseudos, regno)) | |
6551 | { | |
ef87312e | 6552 | lra_substitute_pseudo_within_insn |
8a8330b7 | 6553 | (curr_insn, regno, restore_rtx, false); |
55a2c322 VM |
6554 | restored_regs_p = true; |
6555 | } | |
6556 | else | |
6557 | kept_regs_p = true; | |
6558 | } | |
6559 | } | |
6560 | if (NONDEBUG_INSN_P (curr_insn) && kept_regs_p) | |
6561 | { | |
6562 | /* The instruction has changed since the previous | |
6563 | constraints pass. */ | |
6564 | lra_push_insn_and_update_insn_regno_info (curr_insn); | |
6565 | lra_set_used_insn_alternative_by_uid | |
6566 | (INSN_UID (curr_insn), -1); | |
6567 | } | |
6568 | else if (restored_regs_p) | |
6569 | /* The instruction has been restored to the form that | |
6570 | it had during the previous constraints pass. */ | |
6571 | lra_update_insn_regno_info (curr_insn); | |
6572 | if (restored_regs_p && lra_dump_file != NULL) | |
6573 | { | |
6574 | fprintf (lra_dump_file, " Insn after restoring regs:\n"); | |
cfbeaedf | 6575 | dump_insn_slim (lra_dump_file, curr_insn); |
55a2c322 VM |
6576 | } |
6577 | } | |
6578 | } | |
6579 | } | |
6580 | return change_p; | |
6581 | } | |
6582 | ||
2b778c9d VM |
6583 | /* If optional reload pseudos failed to get a hard register or was not |
6584 | inherited, it is better to remove optional reloads. We do this | |
6585 | transformation after undoing inheritance to figure out necessity to | |
6586 | remove optional reloads easier. Return true if we do any | |
6587 | change. */ | |
6588 | static bool | |
6589 | undo_optional_reloads (void) | |
6590 | { | |
b0681c9e | 6591 | bool change_p, keep_p; |
2b778c9d VM |
6592 | unsigned int regno, uid; |
6593 | bitmap_iterator bi, bi2; | |
cfa434f6 DM |
6594 | rtx_insn *insn; |
6595 | rtx set, src, dest; | |
2b778c9d VM |
6596 | bitmap_head removed_optional_reload_pseudos, insn_bitmap; |
6597 | ||
6598 | bitmap_initialize (&removed_optional_reload_pseudos, ®_obstack); | |
6599 | bitmap_copy (&removed_optional_reload_pseudos, &lra_optional_reload_pseudos); | |
6600 | EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos, 0, regno, bi) | |
aa940f7c VM |
6601 | { |
6602 | keep_p = false; | |
080cbf9e | 6603 | /* Keep optional reloads from previous subpasses. */ |
8a8330b7 | 6604 | if (lra_reg_info[regno].restore_rtx == NULL_RTX |
080cbf9e VM |
6605 | /* If the original pseudo changed its allocation, just |
6606 | removing the optional pseudo is dangerous as the original | |
6607 | pseudo will have longer live range. */ | |
8a8330b7 | 6608 | || reg_renumber[REGNO (lra_reg_info[regno].restore_rtx)] >= 0) |
aa940f7c VM |
6609 | keep_p = true; |
6610 | else if (reg_renumber[regno] >= 0) | |
6611 | EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi2) | |
b0681c9e | 6612 | { |
aa940f7c VM |
6613 | insn = lra_insn_recog_data[uid]->insn; |
6614 | if ((set = single_set (insn)) == NULL_RTX) | |
6615 | continue; | |
6616 | src = SET_SRC (set); | |
6617 | dest = SET_DEST (set); | |
6618 | if (! REG_P (src) || ! REG_P (dest)) | |
6619 | continue; | |
6620 | if (REGNO (dest) == regno | |
6621 | /* Ignore insn for optional reloads itself. */ | |
8a8330b7 | 6622 | && REGNO (lra_reg_info[regno].restore_rtx) != REGNO (src) |
aa940f7c VM |
6623 | /* Check only inheritance on last inheritance pass. */ |
6624 | && (int) REGNO (src) >= new_regno_start | |
6625 | /* Check that the optional reload was inherited. */ | |
6626 | && bitmap_bit_p (&lra_inheritance_pseudos, REGNO (src))) | |
6627 | { | |
6628 | keep_p = true; | |
6629 | break; | |
6630 | } | |
b0681c9e | 6631 | } |
aa940f7c VM |
6632 | if (keep_p) |
6633 | { | |
6634 | bitmap_clear_bit (&removed_optional_reload_pseudos, regno); | |
6635 | if (lra_dump_file != NULL) | |
6636 | fprintf (lra_dump_file, "Keep optional reload reg %d\n", regno); | |
6637 | } | |
6638 | } | |
2b778c9d VM |
6639 | change_p = ! bitmap_empty_p (&removed_optional_reload_pseudos); |
6640 | bitmap_initialize (&insn_bitmap, ®_obstack); | |
6641 | EXECUTE_IF_SET_IN_BITMAP (&removed_optional_reload_pseudos, 0, regno, bi) | |
6642 | { | |
6643 | if (lra_dump_file != NULL) | |
6644 | fprintf (lra_dump_file, "Remove optional reload reg %d\n", regno); | |
6645 | bitmap_copy (&insn_bitmap, &lra_reg_info[regno].insn_bitmap); | |
6646 | EXECUTE_IF_SET_IN_BITMAP (&insn_bitmap, 0, uid, bi2) | |
6647 | { | |
6648 | insn = lra_insn_recog_data[uid]->insn; | |
6649 | if ((set = single_set (insn)) != NULL_RTX) | |
6650 | { | |
6651 | src = SET_SRC (set); | |
6652 | dest = SET_DEST (set); | |
6653 | if (REG_P (src) && REG_P (dest) | |
6654 | && ((REGNO (src) == regno | |
8a8330b7 VM |
6655 | && (REGNO (lra_reg_info[regno].restore_rtx) |
6656 | == REGNO (dest))) | |
2b778c9d | 6657 | || (REGNO (dest) == regno |
8a8330b7 VM |
6658 | && (REGNO (lra_reg_info[regno].restore_rtx) |
6659 | == REGNO (src))))) | |
2b778c9d VM |
6660 | { |
6661 | if (lra_dump_file != NULL) | |
6662 | { | |
6663 | fprintf (lra_dump_file, " Deleting move %u\n", | |
6664 | INSN_UID (insn)); | |
6665 | dump_insn_slim (lra_dump_file, insn); | |
6666 | } | |
cefe08a4 | 6667 | delete_move_and_clobber (insn, REGNO (dest)); |
2b778c9d VM |
6668 | continue; |
6669 | } | |
6670 | /* We should not worry about generation memory-memory | |
6671 | moves here as if the corresponding inheritance did | |
6672 | not work (inheritance pseudo did not get a hard reg), | |
6673 | we remove the inheritance pseudo and the optional | |
6674 | reload. */ | |
6675 | } | |
ef87312e | 6676 | lra_substitute_pseudo_within_insn |
8a8330b7 | 6677 | (insn, regno, lra_reg_info[regno].restore_rtx, false); |
2b778c9d VM |
6678 | lra_update_insn_regno_info (insn); |
6679 | if (lra_dump_file != NULL) | |
6680 | { | |
6681 | fprintf (lra_dump_file, | |
6682 | " Restoring original insn:\n"); | |
6683 | dump_insn_slim (lra_dump_file, insn); | |
6684 | } | |
6685 | } | |
6686 | } | |
6687 | /* Clear restore_regnos. */ | |
6688 | EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos, 0, regno, bi) | |
8a8330b7 | 6689 | lra_reg_info[regno].restore_rtx = NULL_RTX; |
2b778c9d VM |
6690 | bitmap_clear (&insn_bitmap); |
6691 | bitmap_clear (&removed_optional_reload_pseudos); | |
6692 | return change_p; | |
6693 | } | |
6694 | ||
55a2c322 VM |
6695 | /* Entry function for undoing inheritance/split transformation. Return true |
6696 | if we did any RTL change in this pass. */ | |
6697 | bool | |
6698 | lra_undo_inheritance (void) | |
6699 | { | |
6700 | unsigned int regno; | |
8a8330b7 | 6701 | int hard_regno; |
55a2c322 | 6702 | int n_all_inherit, n_inherit, n_all_split, n_split; |
8a8330b7 | 6703 | rtx restore_rtx; |
55a2c322 VM |
6704 | bitmap_head remove_pseudos; |
6705 | bitmap_iterator bi; | |
6706 | bool change_p; | |
6707 | ||
6708 | lra_undo_inheritance_iter++; | |
8e3a4869 | 6709 | if (lra_undo_inheritance_iter > LRA_MAX_INHERITANCE_PASSES) |
e731262b | 6710 | return false; |
55a2c322 VM |
6711 | if (lra_dump_file != NULL) |
6712 | fprintf (lra_dump_file, | |
6713 | "\n********** Undoing inheritance #%d: **********\n\n", | |
6714 | lra_undo_inheritance_iter); | |
6715 | bitmap_initialize (&remove_pseudos, ®_obstack); | |
6716 | n_inherit = n_all_inherit = 0; | |
6717 | EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos, 0, regno, bi) | |
8a8330b7 | 6718 | if (lra_reg_info[regno].restore_rtx != NULL_RTX) |
55a2c322 VM |
6719 | { |
6720 | n_all_inherit++; | |
b0681c9e VM |
6721 | if (reg_renumber[regno] < 0 |
6722 | /* If the original pseudo changed its allocation, just | |
6723 | removing inheritance is dangerous as for changing | |
6724 | allocation we used shorter live-ranges. */ | |
8a8330b7 VM |
6725 | && (! REG_P (lra_reg_info[regno].restore_rtx) |
6726 | || reg_renumber[REGNO (lra_reg_info[regno].restore_rtx)] < 0)) | |
55a2c322 VM |
6727 | bitmap_set_bit (&remove_pseudos, regno); |
6728 | else | |
6729 | n_inherit++; | |
6730 | } | |
6731 | if (lra_dump_file != NULL && n_all_inherit != 0) | |
6732 | fprintf (lra_dump_file, "Inherit %d out of %d (%.2f%%)\n", | |
6733 | n_inherit, n_all_inherit, | |
6734 | (double) n_inherit / n_all_inherit * 100); | |
6735 | n_split = n_all_split = 0; | |
6736 | EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs, 0, regno, bi) | |
8a8330b7 | 6737 | if ((restore_rtx = lra_reg_info[regno].restore_rtx) != NULL_RTX) |
55a2c322 | 6738 | { |
8a8330b7 VM |
6739 | int restore_regno = REGNO (restore_rtx); |
6740 | ||
55a2c322 VM |
6741 | n_all_split++; |
6742 | hard_regno = (restore_regno >= FIRST_PSEUDO_REGISTER | |
6743 | ? reg_renumber[restore_regno] : restore_regno); | |
6744 | if (hard_regno < 0 || reg_renumber[regno] == hard_regno) | |
6745 | bitmap_set_bit (&remove_pseudos, regno); | |
6746 | else | |
6747 | { | |
6748 | n_split++; | |
6749 | if (lra_dump_file != NULL) | |
6750 | fprintf (lra_dump_file, " Keep split r%d (orig=r%d)\n", | |
6751 | regno, restore_regno); | |
6752 | } | |
6753 | } | |
6754 | if (lra_dump_file != NULL && n_all_split != 0) | |
6755 | fprintf (lra_dump_file, "Split %d out of %d (%.2f%%)\n", | |
6756 | n_split, n_all_split, | |
6757 | (double) n_split / n_all_split * 100); | |
6758 | change_p = remove_inheritance_pseudos (&remove_pseudos); | |
6759 | bitmap_clear (&remove_pseudos); | |
6760 | /* Clear restore_regnos. */ | |
6761 | EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos, 0, regno, bi) | |
8a8330b7 | 6762 | lra_reg_info[regno].restore_rtx = NULL_RTX; |
55a2c322 | 6763 | EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs, 0, regno, bi) |
8a8330b7 | 6764 | lra_reg_info[regno].restore_rtx = NULL_RTX; |
2b778c9d | 6765 | change_p = undo_optional_reloads () || change_p; |
55a2c322 VM |
6766 | return change_p; |
6767 | } |