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55a2c322 | 1 | /* Code for RTL transformations to satisfy insn constraints. |
8d9254fc | 2 | Copyright (C) 2010-2020 Free Software Foundation, Inc. |
55a2c322 VM |
3 | Contributed by Vladimir Makarov <vmakarov@redhat.com>. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it under | |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 3, or (at your option) any later | |
10 | version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | ||
22 | /* This file contains code for 3 passes: constraint pass, | |
23 | inheritance/split pass, and pass for undoing failed inheritance and | |
24 | split. | |
25 | ||
26 | The major goal of constraint pass is to transform RTL to satisfy | |
27 | insn and address constraints by: | |
28 | o choosing insn alternatives; | |
29 | o generating *reload insns* (or reloads in brief) and *reload | |
30 | pseudos* which will get necessary hard registers later; | |
31 | o substituting pseudos with equivalent values and removing the | |
32 | instructions that initialized those pseudos. | |
33 | ||
34 | The constraint pass has biggest and most complicated code in LRA. | |
35 | There are a lot of important details like: | |
36 | o reuse of input reload pseudos to simplify reload pseudo | |
37 | allocations; | |
38 | o some heuristics to choose insn alternative to improve the | |
39 | inheritance; | |
40 | o early clobbers etc. | |
41 | ||
42 | The pass is mimicking former reload pass in alternative choosing | |
43 | because the reload pass is oriented to current machine description | |
44 | model. It might be changed if the machine description model is | |
45 | changed. | |
46 | ||
47 | There is special code for preventing all LRA and this pass cycling | |
48 | in case of bugs. | |
49 | ||
50 | On the first iteration of the pass we process every instruction and | |
51 | choose an alternative for each one. On subsequent iterations we try | |
52 | to avoid reprocessing instructions if we can be sure that the old | |
53 | choice is still valid. | |
54 | ||
55 | The inheritance/spilt pass is to transform code to achieve | |
56 | ineheritance and live range splitting. It is done on backward | |
57 | traversal of EBBs. | |
58 | ||
59 | The inheritance optimization goal is to reuse values in hard | |
60 | registers. There is analogous optimization in old reload pass. The | |
61 | inheritance is achieved by following transformation: | |
62 | ||
63 | reload_p1 <- p reload_p1 <- p | |
64 | ... new_p <- reload_p1 | |
65 | ... => ... | |
66 | reload_p2 <- p reload_p2 <- new_p | |
67 | ||
68 | where p is spilled and not changed between the insns. Reload_p1 is | |
69 | also called *original pseudo* and new_p is called *inheritance | |
70 | pseudo*. | |
71 | ||
72 | The subsequent assignment pass will try to assign the same (or | |
73 | another if it is not possible) hard register to new_p as to | |
74 | reload_p1 or reload_p2. | |
75 | ||
76 | If the assignment pass fails to assign a hard register to new_p, | |
77 | this file will undo the inheritance and restore the original code. | |
78 | This is because implementing the above sequence with a spilled | |
79 | new_p would make the code much worse. The inheritance is done in | |
80 | EBB scope. The above is just a simplified example to get an idea | |
81 | of the inheritance as the inheritance is also done for non-reload | |
82 | insns. | |
83 | ||
84 | Splitting (transformation) is also done in EBB scope on the same | |
85 | pass as the inheritance: | |
86 | ||
87 | r <- ... or ... <- r r <- ... or ... <- r | |
88 | ... s <- r (new insn -- save) | |
f4eafc30 | 89 | ... => |
55a2c322 VM |
90 | ... r <- s (new insn -- restore) |
91 | ... <- r ... <- r | |
92 | ||
93 | The *split pseudo* s is assigned to the hard register of the | |
94 | original pseudo or hard register r. | |
95 | ||
96 | Splitting is done: | |
97 | o In EBBs with high register pressure for global pseudos (living | |
98 | in at least 2 BBs) and assigned to hard registers when there | |
99 | are more one reloads needing the hard registers; | |
100 | o for pseudos needing save/restore code around calls. | |
101 | ||
102 | If the split pseudo still has the same hard register as the | |
103 | original pseudo after the subsequent assignment pass or the | |
104 | original pseudo was split, the opposite transformation is done on | |
105 | the same pass for undoing inheritance. */ | |
106 | ||
107 | #undef REG_OK_STRICT | |
108 | ||
109 | #include "config.h" | |
110 | #include "system.h" | |
111 | #include "coretypes.h" | |
c7131fb2 | 112 | #include "backend.h" |
957060b5 | 113 | #include "target.h" |
55a2c322 | 114 | #include "rtl.h" |
957060b5 AM |
115 | #include "tree.h" |
116 | #include "predict.h" | |
c7131fb2 | 117 | #include "df.h" |
4d0cdd0c | 118 | #include "memmodel.h" |
55a2c322 | 119 | #include "tm_p.h" |
957060b5 AM |
120 | #include "expmed.h" |
121 | #include "optabs.h" | |
55a2c322 | 122 | #include "regs.h" |
957060b5 | 123 | #include "ira.h" |
55a2c322 VM |
124 | #include "recog.h" |
125 | #include "output.h" | |
126 | #include "addresses.h" | |
55a2c322 | 127 | #include "expr.h" |
60393bbc | 128 | #include "cfgrtl.h" |
55a2c322 | 129 | #include "rtl-error.h" |
c7131fb2 | 130 | #include "lra.h" |
55a2c322 | 131 | #include "lra-int.h" |
013a8899 | 132 | #include "print-rtl.h" |
6ee2cc70 | 133 | #include "function-abi.h" |
6b3034ea | 134 | #include "rtl-iter.h" |
55a2c322 VM |
135 | |
136 | /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current | |
137 | insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted | |
138 | reload insns. */ | |
139 | static int bb_reload_num; | |
140 | ||
2c62cbaa VM |
141 | /* The current insn being processed and corresponding its single set |
142 | (NULL otherwise), its data (basic block, the insn data, the insn | |
143 | static data, and the mode of each operand). */ | |
cfa434f6 | 144 | static rtx_insn *curr_insn; |
2c62cbaa | 145 | static rtx curr_insn_set; |
55a2c322 VM |
146 | static basic_block curr_bb; |
147 | static lra_insn_recog_data_t curr_id; | |
148 | static struct lra_static_insn_data *curr_static_id; | |
ef4bddc2 | 149 | static machine_mode curr_operand_mode[MAX_RECOG_OPERANDS]; |
895ff86f VM |
150 | /* Mode of the register substituted by its equivalence with VOIDmode |
151 | (e.g. constant) and whose subreg is given operand of the current | |
152 | insn. VOIDmode in all other cases. */ | |
153 | static machine_mode original_subreg_reg_mode[MAX_RECOG_OPERANDS]; | |
55a2c322 VM |
154 | |
155 | \f | |
156 | ||
157 | /* Start numbers for new registers and insns at the current constraints | |
158 | pass start. */ | |
159 | static int new_regno_start; | |
160 | static int new_insn_uid_start; | |
161 | ||
277f65de RS |
162 | /* If LOC is nonnull, strip any outer subreg from it. */ |
163 | static inline rtx * | |
164 | strip_subreg (rtx *loc) | |
165 | { | |
166 | return loc && GET_CODE (*loc) == SUBREG ? &SUBREG_REG (*loc) : loc; | |
167 | } | |
168 | ||
55a2c322 VM |
169 | /* Return hard regno of REGNO or if it is was not assigned to a hard |
170 | register, use a hard register from its allocno class. */ | |
171 | static int | |
172 | get_try_hard_regno (int regno) | |
173 | { | |
174 | int hard_regno; | |
175 | enum reg_class rclass; | |
176 | ||
177 | if ((hard_regno = regno) >= FIRST_PSEUDO_REGISTER) | |
178 | hard_regno = lra_get_regno_hard_regno (regno); | |
179 | if (hard_regno >= 0) | |
180 | return hard_regno; | |
181 | rclass = lra_get_allocno_class (regno); | |
182 | if (rclass == NO_REGS) | |
183 | return -1; | |
184 | return ira_class_hard_regs[rclass][0]; | |
185 | } | |
186 | ||
9d0a9bb4 PB |
187 | /* Return the hard regno of X after removing its subreg. If X is not |
188 | a register or a subreg of a register, return -1. If X is a pseudo, | |
1686923c BE |
189 | use its assignment. If FINAL_P return the final hard regno which will |
190 | be after elimination. */ | |
55a2c322 | 191 | static int |
1686923c | 192 | get_hard_regno (rtx x, bool final_p) |
55a2c322 VM |
193 | { |
194 | rtx reg; | |
1686923c | 195 | int hard_regno; |
55a2c322 VM |
196 | |
197 | reg = x; | |
9d0a9bb4 | 198 | if (SUBREG_P (x)) |
55a2c322 VM |
199 | reg = SUBREG_REG (x); |
200 | if (! REG_P (reg)) | |
201 | return -1; | |
9d0a9bb4 | 202 | if (! HARD_REGISTER_NUM_P (hard_regno = REGNO (reg))) |
55a2c322 VM |
203 | hard_regno = lra_get_regno_hard_regno (hard_regno); |
204 | if (hard_regno < 0) | |
205 | return -1; | |
1686923c BE |
206 | if (final_p) |
207 | hard_regno = lra_get_elimination_hard_regno (hard_regno); | |
9d0a9bb4 | 208 | if (SUBREG_P (x)) |
1686923c BE |
209 | hard_regno += subreg_regno_offset (hard_regno, GET_MODE (reg), |
210 | SUBREG_BYTE (x), GET_MODE (x)); | |
211 | return hard_regno; | |
55a2c322 VM |
212 | } |
213 | ||
214 | /* If REGNO is a hard register or has been allocated a hard register, | |
215 | return the class of that register. If REGNO is a reload pseudo | |
216 | created by the current constraints pass, return its allocno class. | |
217 | Return NO_REGS otherwise. */ | |
218 | static enum reg_class | |
219 | get_reg_class (int regno) | |
220 | { | |
221 | int hard_regno; | |
222 | ||
1686923c | 223 | if (! HARD_REGISTER_NUM_P (hard_regno = regno)) |
55a2c322 VM |
224 | hard_regno = lra_get_regno_hard_regno (regno); |
225 | if (hard_regno >= 0) | |
226 | { | |
1686923c | 227 | hard_regno = lra_get_elimination_hard_regno (hard_regno); |
55a2c322 VM |
228 | return REGNO_REG_CLASS (hard_regno); |
229 | } | |
230 | if (regno >= new_regno_start) | |
231 | return lra_get_allocno_class (regno); | |
232 | return NO_REGS; | |
233 | } | |
234 | ||
235 | /* Return true if REG satisfies (or will satisfy) reg class constraint | |
236 | CL. Use elimination first if REG is a hard register. If REG is a | |
237 | reload pseudo created by this constraints pass, assume that it will | |
238 | be allocated a hard register from its allocno class, but allow that | |
239 | class to be narrowed to CL if it is currently a superset of CL. | |
240 | ||
241 | If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of | |
242 | REGNO (reg), or NO_REGS if no change in its class was needed. */ | |
243 | static bool | |
244 | in_class_p (rtx reg, enum reg_class cl, enum reg_class *new_class) | |
245 | { | |
246 | enum reg_class rclass, common_class; | |
ef4bddc2 | 247 | machine_mode reg_mode; |
55a2c322 VM |
248 | int class_size, hard_regno, nregs, i, j; |
249 | int regno = REGNO (reg); | |
f4eafc30 | 250 | |
55a2c322 VM |
251 | if (new_class != NULL) |
252 | *new_class = NO_REGS; | |
253 | if (regno < FIRST_PSEUDO_REGISTER) | |
254 | { | |
255 | rtx final_reg = reg; | |
256 | rtx *final_loc = &final_reg; | |
f4eafc30 | 257 | |
55a2c322 VM |
258 | lra_eliminate_reg_if_possible (final_loc); |
259 | return TEST_HARD_REG_BIT (reg_class_contents[cl], REGNO (*final_loc)); | |
260 | } | |
261 | reg_mode = GET_MODE (reg); | |
262 | rclass = get_reg_class (regno); | |
263 | if (regno < new_regno_start | |
264 | /* Do not allow the constraints for reload instructions to | |
265 | influence the classes of new pseudos. These reloads are | |
266 | typically moves that have many alternatives, and restricting | |
267 | reload pseudos for one alternative may lead to situations | |
268 | where other reload pseudos are no longer allocatable. */ | |
a2d0d374 VM |
269 | || (INSN_UID (curr_insn) >= new_insn_uid_start |
270 | && curr_insn_set != NULL | |
58532ca6 VM |
271 | && ((OBJECT_P (SET_SRC (curr_insn_set)) |
272 | && ! CONSTANT_P (SET_SRC (curr_insn_set))) | |
a2d0d374 | 273 | || (GET_CODE (SET_SRC (curr_insn_set)) == SUBREG |
58532ca6 VM |
274 | && OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set))) |
275 | && ! CONSTANT_P (SUBREG_REG (SET_SRC (curr_insn_set))))))) | |
55a2c322 VM |
276 | /* When we don't know what class will be used finally for reload |
277 | pseudos, we use ALL_REGS. */ | |
278 | return ((regno >= new_regno_start && rclass == ALL_REGS) | |
279 | || (rclass != NO_REGS && ira_class_subset_p[rclass][cl] | |
280 | && ! hard_reg_set_subset_p (reg_class_contents[cl], | |
281 | lra_no_alloc_regs))); | |
282 | else | |
283 | { | |
284 | common_class = ira_reg_class_subset[rclass][cl]; | |
285 | if (new_class != NULL) | |
286 | *new_class = common_class; | |
287 | if (hard_reg_set_subset_p (reg_class_contents[common_class], | |
288 | lra_no_alloc_regs)) | |
289 | return false; | |
290 | /* Check that there are enough allocatable regs. */ | |
291 | class_size = ira_class_hard_regs_num[common_class]; | |
292 | for (i = 0; i < class_size; i++) | |
293 | { | |
294 | hard_regno = ira_class_hard_regs[common_class][i]; | |
ad474626 | 295 | nregs = hard_regno_nregs (hard_regno, reg_mode); |
55a2c322 VM |
296 | if (nregs == 1) |
297 | return true; | |
298 | for (j = 0; j < nregs; j++) | |
f421c426 VM |
299 | if (TEST_HARD_REG_BIT (lra_no_alloc_regs, hard_regno + j) |
300 | || ! TEST_HARD_REG_BIT (reg_class_contents[common_class], | |
301 | hard_regno + j)) | |
55a2c322 VM |
302 | break; |
303 | if (j >= nregs) | |
304 | return true; | |
305 | } | |
306 | return false; | |
307 | } | |
308 | } | |
309 | ||
310 | /* Return true if REGNO satisfies a memory constraint. */ | |
311 | static bool | |
312 | in_mem_p (int regno) | |
313 | { | |
314 | return get_reg_class (regno) == NO_REGS; | |
315 | } | |
316 | ||
a953491e RS |
317 | /* Return 1 if ADDR is a valid memory address for mode MODE in address |
318 | space AS, and check that each pseudo has the proper kind of hard | |
319 | reg. */ | |
320 | static int | |
ef4bddc2 | 321 | valid_address_p (machine_mode mode ATTRIBUTE_UNUSED, |
a953491e RS |
322 | rtx addr, addr_space_t as) |
323 | { | |
324 | #ifdef GO_IF_LEGITIMATE_ADDRESS | |
325 | lra_assert (ADDR_SPACE_GENERIC_P (as)); | |
326 | GO_IF_LEGITIMATE_ADDRESS (mode, addr, win); | |
327 | return 0; | |
328 | ||
329 | win: | |
330 | return 1; | |
331 | #else | |
332 | return targetm.addr_space.legitimate_address_p (mode, addr, 0, as); | |
333 | #endif | |
334 | } | |
335 | ||
336 | namespace { | |
337 | /* Temporarily eliminates registers in an address (for the lifetime of | |
338 | the object). */ | |
339 | class address_eliminator { | |
340 | public: | |
341 | address_eliminator (struct address_info *ad); | |
342 | ~address_eliminator (); | |
343 | ||
344 | private: | |
345 | struct address_info *m_ad; | |
346 | rtx *m_base_loc; | |
347 | rtx m_base_reg; | |
348 | rtx *m_index_loc; | |
349 | rtx m_index_reg; | |
350 | }; | |
351 | } | |
352 | ||
353 | address_eliminator::address_eliminator (struct address_info *ad) | |
354 | : m_ad (ad), | |
355 | m_base_loc (strip_subreg (ad->base_term)), | |
356 | m_base_reg (NULL_RTX), | |
357 | m_index_loc (strip_subreg (ad->index_term)), | |
358 | m_index_reg (NULL_RTX) | |
359 | { | |
360 | if (m_base_loc != NULL) | |
361 | { | |
362 | m_base_reg = *m_base_loc; | |
9cb95c07 VM |
363 | /* If we have non-legitimate address which is decomposed not in |
364 | the way we expected, don't do elimination here. In such case | |
365 | the address will be reloaded and elimination will be done in | |
366 | reload insn finally. */ | |
367 | if (REG_P (m_base_reg)) | |
368 | lra_eliminate_reg_if_possible (m_base_loc); | |
a953491e RS |
369 | if (m_ad->base_term2 != NULL) |
370 | *m_ad->base_term2 = *m_ad->base_term; | |
371 | } | |
372 | if (m_index_loc != NULL) | |
373 | { | |
374 | m_index_reg = *m_index_loc; | |
9cb95c07 VM |
375 | if (REG_P (m_index_reg)) |
376 | lra_eliminate_reg_if_possible (m_index_loc); | |
a953491e RS |
377 | } |
378 | } | |
379 | ||
380 | address_eliminator::~address_eliminator () | |
381 | { | |
382 | if (m_base_loc && *m_base_loc != m_base_reg) | |
383 | { | |
384 | *m_base_loc = m_base_reg; | |
385 | if (m_ad->base_term2 != NULL) | |
386 | *m_ad->base_term2 = *m_ad->base_term; | |
387 | } | |
388 | if (m_index_loc && *m_index_loc != m_index_reg) | |
389 | *m_index_loc = m_index_reg; | |
390 | } | |
391 | ||
1aeffdce RS |
392 | /* Return true if the eliminated form of AD is a legitimate target address. |
393 | If OP is a MEM, AD is the address within OP, otherwise OP should be | |
394 | ignored. CONSTRAINT is one constraint that the operand may need | |
395 | to meet. */ | |
a953491e | 396 | static bool |
1aeffdce RS |
397 | valid_address_p (rtx op, struct address_info *ad, |
398 | enum constraint_num constraint) | |
a953491e RS |
399 | { |
400 | address_eliminator eliminator (ad); | |
1aeffdce RS |
401 | |
402 | /* Allow a memory OP if it matches CONSTRAINT, even if CONSTRAINT is more | |
403 | forgiving than "m". */ | |
404 | if (MEM_P (op) | |
405 | && (insn_extra_memory_constraint (constraint) | |
406 | || insn_extra_special_memory_constraint (constraint)) | |
407 | && constraint_satisfied_p (op, constraint)) | |
408 | return true; | |
409 | ||
a953491e RS |
410 | return valid_address_p (ad->mode, *ad->outer, ad->as); |
411 | } | |
412 | ||
a953491e | 413 | /* Return true if the eliminated form of memory reference OP satisfies |
9eb1ca69 | 414 | extra (special) memory constraint CONSTRAINT. */ |
a953491e | 415 | static bool |
777e635f | 416 | satisfies_memory_constraint_p (rtx op, enum constraint_num constraint) |
a953491e RS |
417 | { |
418 | struct address_info ad; | |
419 | ||
420 | decompose_mem_address (&ad, op); | |
421 | address_eliminator eliminator (&ad); | |
777e635f | 422 | return constraint_satisfied_p (op, constraint); |
a953491e RS |
423 | } |
424 | ||
425 | /* Return true if the eliminated form of address AD satisfies extra | |
426 | address constraint CONSTRAINT. */ | |
427 | static bool | |
428 | satisfies_address_constraint_p (struct address_info *ad, | |
777e635f | 429 | enum constraint_num constraint) |
a953491e RS |
430 | { |
431 | address_eliminator eliminator (ad); | |
777e635f | 432 | return constraint_satisfied_p (*ad->outer, constraint); |
a953491e RS |
433 | } |
434 | ||
435 | /* Return true if the eliminated form of address OP satisfies extra | |
436 | address constraint CONSTRAINT. */ | |
437 | static bool | |
777e635f | 438 | satisfies_address_constraint_p (rtx op, enum constraint_num constraint) |
a953491e RS |
439 | { |
440 | struct address_info ad; | |
441 | ||
442 | decompose_lea_address (&ad, &op); | |
443 | return satisfies_address_constraint_p (&ad, constraint); | |
444 | } | |
a953491e | 445 | |
4c2b2d79 VM |
446 | /* Initiate equivalences for LRA. As we keep original equivalences |
447 | before any elimination, we need to make copies otherwise any change | |
448 | in insns might change the equivalences. */ | |
449 | void | |
450 | lra_init_equiv (void) | |
451 | { | |
452 | ira_expand_reg_equiv (); | |
453 | for (int i = FIRST_PSEUDO_REGISTER; i < max_reg_num (); i++) | |
454 | { | |
455 | rtx res; | |
456 | ||
457 | if ((res = ira_reg_equiv[i].memory) != NULL_RTX) | |
458 | ira_reg_equiv[i].memory = copy_rtx (res); | |
459 | if ((res = ira_reg_equiv[i].invariant) != NULL_RTX) | |
460 | ira_reg_equiv[i].invariant = copy_rtx (res); | |
461 | } | |
462 | } | |
463 | ||
464 | static rtx loc_equivalence_callback (rtx, const_rtx, void *); | |
465 | ||
466 | /* Update equivalence for REGNO. We need to this as the equivalence | |
467 | might contain other pseudos which are changed by their | |
468 | equivalences. */ | |
469 | static void | |
470 | update_equiv (int regno) | |
471 | { | |
472 | rtx x; | |
473 | ||
474 | if ((x = ira_reg_equiv[regno].memory) != NULL_RTX) | |
475 | ira_reg_equiv[regno].memory | |
476 | = simplify_replace_fn_rtx (x, NULL_RTX, loc_equivalence_callback, | |
477 | NULL_RTX); | |
478 | if ((x = ira_reg_equiv[regno].invariant) != NULL_RTX) | |
479 | ira_reg_equiv[regno].invariant | |
480 | = simplify_replace_fn_rtx (x, NULL_RTX, loc_equivalence_callback, | |
481 | NULL_RTX); | |
482 | } | |
483 | ||
55a2c322 VM |
484 | /* If we have decided to substitute X with another value, return that |
485 | value, otherwise return X. */ | |
486 | static rtx | |
8d49e7ef | 487 | get_equiv (rtx x) |
55a2c322 VM |
488 | { |
489 | int regno; | |
490 | rtx res; | |
491 | ||
492 | if (! REG_P (x) || (regno = REGNO (x)) < FIRST_PSEUDO_REGISTER | |
493 | || ! ira_reg_equiv[regno].defined_p | |
494 | || ! ira_reg_equiv[regno].profitable_p | |
495 | || lra_get_regno_hard_regno (regno) >= 0) | |
496 | return x; | |
497 | if ((res = ira_reg_equiv[regno].memory) != NULL_RTX) | |
d6220b11 KK |
498 | { |
499 | if (targetm.cannot_substitute_mem_equiv_p (res)) | |
500 | return x; | |
501 | return res; | |
502 | } | |
55a2c322 VM |
503 | if ((res = ira_reg_equiv[regno].constant) != NULL_RTX) |
504 | return res; | |
505 | if ((res = ira_reg_equiv[regno].invariant) != NULL_RTX) | |
506 | return res; | |
507 | gcc_unreachable (); | |
508 | } | |
509 | ||
8d49e7ef VM |
510 | /* If we have decided to substitute X with the equivalent value, |
511 | return that value after elimination for INSN, otherwise return | |
512 | X. */ | |
513 | static rtx | |
cfa434f6 | 514 | get_equiv_with_elimination (rtx x, rtx_insn *insn) |
8d49e7ef VM |
515 | { |
516 | rtx res = get_equiv (x); | |
517 | ||
518 | if (x == res || CONSTANT_P (res)) | |
519 | return res; | |
d9cf932c | 520 | return lra_eliminate_regs_1 (insn, res, GET_MODE (res), |
a6af1bf9 | 521 | false, false, 0, true); |
8d49e7ef VM |
522 | } |
523 | ||
55a2c322 VM |
524 | /* Set up curr_operand_mode. */ |
525 | static void | |
526 | init_curr_operand_mode (void) | |
527 | { | |
528 | int nop = curr_static_id->n_operands; | |
529 | for (int i = 0; i < nop; i++) | |
530 | { | |
ef4bddc2 | 531 | machine_mode mode = GET_MODE (*curr_id->operand_loc[i]); |
55a2c322 VM |
532 | if (mode == VOIDmode) |
533 | { | |
534 | /* The .md mode for address operands is the mode of the | |
535 | addressed value rather than the mode of the address itself. */ | |
536 | if (curr_id->icode >= 0 && curr_static_id->operand[i].is_address) | |
537 | mode = Pmode; | |
538 | else | |
539 | mode = curr_static_id->operand[i].mode; | |
540 | } | |
541 | curr_operand_mode[i] = mode; | |
542 | } | |
543 | } | |
544 | ||
545 | \f | |
546 | ||
547 | /* The page contains code to reuse input reloads. */ | |
548 | ||
549 | /* Structure describes input reload of the current insns. */ | |
550 | struct input_reload | |
551 | { | |
3f156a6c VM |
552 | /* True for input reload of matched operands. */ |
553 | bool match_p; | |
55a2c322 VM |
554 | /* Reloaded value. */ |
555 | rtx input; | |
556 | /* Reload pseudo used. */ | |
557 | rtx reg; | |
558 | }; | |
559 | ||
560 | /* The number of elements in the following array. */ | |
561 | static int curr_insn_input_reloads_num; | |
562 | /* Array containing info about input reloads. It is used to find the | |
563 | same input reload and reuse the reload pseudo in this case. */ | |
564 | static struct input_reload curr_insn_input_reloads[LRA_MAX_INSN_RELOADS]; | |
565 | ||
566 | /* Initiate data concerning reuse of input reloads for the current | |
567 | insn. */ | |
568 | static void | |
569 | init_curr_insn_input_reloads (void) | |
570 | { | |
571 | curr_insn_input_reloads_num = 0; | |
572 | } | |
573 | ||
6b3034ea AC |
574 | /* The canonical form of an rtx inside a MEM is not necessarily the same as the |
575 | canonical form of the rtx outside the MEM. Fix this up in the case that | |
576 | we're reloading an address (and therefore pulling it outside a MEM). */ | |
577 | static rtx | |
578 | canonicalize_reload_addr (rtx addr) | |
579 | { | |
580 | subrtx_var_iterator::array_type array; | |
581 | FOR_EACH_SUBRTX_VAR (iter, array, addr, NONCONST) | |
582 | { | |
583 | rtx x = *iter; | |
584 | if (GET_CODE (x) == MULT && CONST_INT_P (XEXP (x, 1))) | |
585 | { | |
586 | const HOST_WIDE_INT ci = INTVAL (XEXP (x, 1)); | |
587 | const int pwr2 = exact_log2 (ci); | |
588 | if (pwr2 > 0) | |
589 | { | |
590 | /* Rewrite this to use a shift instead, which is canonical when | |
591 | outside of a MEM. */ | |
592 | PUT_CODE (x, ASHIFT); | |
593 | XEXP (x, 1) = GEN_INT (pwr2); | |
594 | } | |
595 | } | |
596 | } | |
597 | ||
598 | return addr; | |
599 | } | |
600 | ||
55a2c322 | 601 | /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already |
95921002 VM |
602 | created input reload pseudo (only if TYPE is not OP_OUT). Don't |
603 | reuse pseudo if IN_SUBREG_P is true and the reused pseudo should be | |
604 | wrapped up in SUBREG. The result pseudo is returned through | |
605 | RESULT_REG. Return TRUE if we created a new pseudo, FALSE if we | |
606 | reused the already created input reload pseudo. Use TITLE to | |
607 | describe new registers for debug purposes. */ | |
55a2c322 | 608 | static bool |
ef4bddc2 | 609 | get_reload_reg (enum op_type type, machine_mode mode, rtx original, |
95921002 VM |
610 | enum reg_class rclass, bool in_subreg_p, |
611 | const char *title, rtx *result_reg) | |
55a2c322 VM |
612 | { |
613 | int i, regno; | |
614 | enum reg_class new_class; | |
3f156a6c | 615 | bool unique_p = false; |
55a2c322 VM |
616 | |
617 | if (type == OP_OUT) | |
618 | { | |
619 | *result_reg | |
620 | = lra_create_new_reg_with_unique_value (mode, original, rclass, title); | |
621 | return true; | |
622 | } | |
73cca0cc VM |
623 | /* Prevent reuse value of expression with side effects, |
624 | e.g. volatile memory. */ | |
625 | if (! side_effects_p (original)) | |
626 | for (i = 0; i < curr_insn_input_reloads_num; i++) | |
3f156a6c VM |
627 | { |
628 | if (! curr_insn_input_reloads[i].match_p | |
629 | && rtx_equal_p (curr_insn_input_reloads[i].input, original) | |
630 | && in_class_p (curr_insn_input_reloads[i].reg, rclass, &new_class)) | |
631 | { | |
632 | rtx reg = curr_insn_input_reloads[i].reg; | |
633 | regno = REGNO (reg); | |
634 | /* If input is equal to original and both are VOIDmode, | |
635 | GET_MODE (reg) might be still different from mode. | |
636 | Ensure we don't return *result_reg with wrong mode. */ | |
637 | if (GET_MODE (reg) != mode) | |
638 | { | |
639 | if (in_subreg_p) | |
640 | continue; | |
cf098191 RS |
641 | if (maybe_lt (GET_MODE_SIZE (GET_MODE (reg)), |
642 | GET_MODE_SIZE (mode))) | |
3f156a6c VM |
643 | continue; |
644 | reg = lowpart_subreg (mode, reg, GET_MODE (reg)); | |
645 | if (reg == NULL_RTX || GET_CODE (reg) != SUBREG) | |
646 | continue; | |
647 | } | |
648 | *result_reg = reg; | |
649 | if (lra_dump_file != NULL) | |
650 | { | |
651 | fprintf (lra_dump_file, " Reuse r%d for reload ", regno); | |
652 | dump_value_slim (lra_dump_file, original, 1); | |
653 | } | |
654 | if (new_class != lra_get_allocno_class (regno)) | |
655 | lra_change_class (regno, new_class, ", change to", false); | |
656 | if (lra_dump_file != NULL) | |
657 | fprintf (lra_dump_file, "\n"); | |
658 | return false; | |
659 | } | |
660 | /* If we have an input reload with a different mode, make sure it | |
661 | will get a different hard reg. */ | |
662 | else if (REG_P (original) | |
663 | && REG_P (curr_insn_input_reloads[i].input) | |
664 | && REGNO (original) == REGNO (curr_insn_input_reloads[i].input) | |
665 | && (GET_MODE (original) | |
666 | != GET_MODE (curr_insn_input_reloads[i].input))) | |
667 | unique_p = true; | |
668 | } | |
669 | *result_reg = (unique_p | |
670 | ? lra_create_new_reg_with_unique_value | |
671 | : lra_create_new_reg) (mode, original, rclass, title); | |
55a2c322 VM |
672 | lra_assert (curr_insn_input_reloads_num < LRA_MAX_INSN_RELOADS); |
673 | curr_insn_input_reloads[curr_insn_input_reloads_num].input = original; | |
3f156a6c | 674 | curr_insn_input_reloads[curr_insn_input_reloads_num].match_p = false; |
55a2c322 VM |
675 | curr_insn_input_reloads[curr_insn_input_reloads_num++].reg = *result_reg; |
676 | return true; | |
677 | } | |
678 | ||
679 | \f | |
55a2c322 VM |
680 | /* The page contains major code to choose the current insn alternative |
681 | and generate reloads for it. */ | |
682 | ||
683 | /* Return the offset from REGNO of the least significant register | |
684 | in (reg:MODE REGNO). | |
685 | ||
686 | This function is used to tell whether two registers satisfy | |
687 | a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if: | |
688 | ||
689 | REGNO1 + lra_constraint_offset (REGNO1, MODE1) | |
690 | == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */ | |
691 | int | |
ef4bddc2 | 692 | lra_constraint_offset (int regno, machine_mode mode) |
55a2c322 VM |
693 | { |
694 | lra_assert (regno < FIRST_PSEUDO_REGISTER); | |
b0567726 RS |
695 | |
696 | scalar_int_mode int_mode; | |
697 | if (WORDS_BIG_ENDIAN | |
698 | && is_a <scalar_int_mode> (mode, &int_mode) | |
699 | && GET_MODE_SIZE (int_mode) > UNITS_PER_WORD) | |
ad474626 | 700 | return hard_regno_nregs (regno, mode) - 1; |
55a2c322 VM |
701 | return 0; |
702 | } | |
703 | ||
704 | /* Like rtx_equal_p except that it allows a REG and a SUBREG to match | |
705 | if they are the same hard reg, and has special hacks for | |
706 | auto-increment and auto-decrement. This is specifically intended for | |
707 | process_alt_operands to use in determining whether two operands | |
708 | match. X is the operand whose number is the lower of the two. | |
709 | ||
710 | It is supposed that X is the output operand and Y is the input | |
711 | operand. Y_HARD_REGNO is the final hard regno of register Y or | |
712 | register in subreg Y as we know it now. Otherwise, it is a | |
713 | negative value. */ | |
714 | static bool | |
715 | operands_match_p (rtx x, rtx y, int y_hard_regno) | |
716 | { | |
717 | int i; | |
718 | RTX_CODE code = GET_CODE (x); | |
719 | const char *fmt; | |
720 | ||
721 | if (x == y) | |
722 | return true; | |
723 | if ((code == REG || (code == SUBREG && REG_P (SUBREG_REG (x)))) | |
724 | && (REG_P (y) || (GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y))))) | |
725 | { | |
726 | int j; | |
f4eafc30 | 727 | |
1686923c | 728 | i = get_hard_regno (x, false); |
55a2c322 VM |
729 | if (i < 0) |
730 | goto slow; | |
731 | ||
732 | if ((j = y_hard_regno) < 0) | |
733 | goto slow; | |
734 | ||
735 | i += lra_constraint_offset (i, GET_MODE (x)); | |
736 | j += lra_constraint_offset (j, GET_MODE (y)); | |
737 | ||
738 | return i == j; | |
739 | } | |
740 | ||
741 | /* If two operands must match, because they are really a single | |
742 | operand of an assembler insn, then two post-increments are invalid | |
743 | because the assembler insn would increment only once. On the | |
744 | other hand, a post-increment matches ordinary indexing if the | |
745 | post-increment is the output operand. */ | |
746 | if (code == POST_DEC || code == POST_INC || code == POST_MODIFY) | |
747 | return operands_match_p (XEXP (x, 0), y, y_hard_regno); | |
748 | ||
749 | /* Two pre-increments are invalid because the assembler insn would | |
750 | increment only once. On the other hand, a pre-increment matches | |
751 | ordinary indexing if the pre-increment is the input operand. */ | |
752 | if (GET_CODE (y) == PRE_DEC || GET_CODE (y) == PRE_INC | |
753 | || GET_CODE (y) == PRE_MODIFY) | |
754 | return operands_match_p (x, XEXP (y, 0), -1); | |
f4eafc30 | 755 | |
55a2c322 VM |
756 | slow: |
757 | ||
9fccb335 RS |
758 | if (code == REG && REG_P (y)) |
759 | return REGNO (x) == REGNO (y); | |
760 | ||
55a2c322 VM |
761 | if (code == REG && GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y)) |
762 | && x == SUBREG_REG (y)) | |
763 | return true; | |
764 | if (GET_CODE (y) == REG && code == SUBREG && REG_P (SUBREG_REG (x)) | |
765 | && SUBREG_REG (x) == y) | |
766 | return true; | |
767 | ||
768 | /* Now we have disposed of all the cases in which different rtx | |
769 | codes can match. */ | |
770 | if (code != GET_CODE (y)) | |
771 | return false; | |
772 | ||
773 | /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */ | |
774 | if (GET_MODE (x) != GET_MODE (y)) | |
775 | return false; | |
776 | ||
777 | switch (code) | |
778 | { | |
779 | CASE_CONST_UNIQUE: | |
780 | return false; | |
781 | ||
782 | case LABEL_REF: | |
04a121a7 | 783 | return label_ref_label (x) == label_ref_label (y); |
55a2c322 VM |
784 | case SYMBOL_REF: |
785 | return XSTR (x, 0) == XSTR (y, 0); | |
786 | ||
787 | default: | |
788 | break; | |
789 | } | |
790 | ||
791 | /* Compare the elements. If any pair of corresponding elements fail | |
792 | to match, return false for the whole things. */ | |
793 | ||
794 | fmt = GET_RTX_FORMAT (code); | |
795 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
796 | { | |
797 | int val, j; | |
798 | switch (fmt[i]) | |
799 | { | |
800 | case 'w': | |
801 | if (XWINT (x, i) != XWINT (y, i)) | |
802 | return false; | |
803 | break; | |
804 | ||
805 | case 'i': | |
806 | if (XINT (x, i) != XINT (y, i)) | |
807 | return false; | |
808 | break; | |
809 | ||
91914e56 RS |
810 | case 'p': |
811 | if (maybe_ne (SUBREG_BYTE (x), SUBREG_BYTE (y))) | |
812 | return false; | |
813 | break; | |
814 | ||
55a2c322 VM |
815 | case 'e': |
816 | val = operands_match_p (XEXP (x, i), XEXP (y, i), -1); | |
817 | if (val == 0) | |
818 | return false; | |
819 | break; | |
820 | ||
821 | case '0': | |
822 | break; | |
823 | ||
824 | case 'E': | |
825 | if (XVECLEN (x, i) != XVECLEN (y, i)) | |
826 | return false; | |
827 | for (j = XVECLEN (x, i) - 1; j >= 0; --j) | |
828 | { | |
829 | val = operands_match_p (XVECEXP (x, i, j), XVECEXP (y, i, j), -1); | |
830 | if (val == 0) | |
831 | return false; | |
832 | } | |
833 | break; | |
834 | ||
835 | /* It is believed that rtx's at this level will never | |
836 | contain anything but integers and other rtx's, except for | |
837 | within LABEL_REFs and SYMBOL_REFs. */ | |
838 | default: | |
839 | gcc_unreachable (); | |
840 | } | |
841 | } | |
842 | return true; | |
843 | } | |
844 | ||
845 | /* True if X is a constant that can be forced into the constant pool. | |
846 | MODE is the mode of the operand, or VOIDmode if not known. */ | |
847 | #define CONST_POOL_OK_P(MODE, X) \ | |
848 | ((MODE) != VOIDmode \ | |
849 | && CONSTANT_P (X) \ | |
850 | && GET_CODE (X) != HIGH \ | |
cf098191 | 851 | && GET_MODE_SIZE (MODE).is_constant () \ |
55a2c322 VM |
852 | && !targetm.cannot_force_const_mem (MODE, X)) |
853 | ||
854 | /* True if C is a non-empty register class that has too few registers | |
855 | to be safely used as a reload target class. */ | |
a9711f36 VM |
856 | #define SMALL_REGISTER_CLASS_P(C) \ |
857 | (ira_class_hard_regs_num [(C)] == 1 \ | |
858 | || (ira_class_hard_regs_num [(C)] >= 1 \ | |
859 | && targetm.class_likely_spilled_p (C))) | |
55a2c322 VM |
860 | |
861 | /* If REG is a reload pseudo, try to make its class satisfying CL. */ | |
862 | static void | |
863 | narrow_reload_pseudo_class (rtx reg, enum reg_class cl) | |
864 | { | |
865 | enum reg_class rclass; | |
866 | ||
867 | /* Do not make more accurate class from reloads generated. They are | |
868 | mostly moves with a lot of constraints. Making more accurate | |
869 | class may results in very narrow class and impossibility of find | |
870 | registers for several reloads of one insn. */ | |
871 | if (INSN_UID (curr_insn) >= new_insn_uid_start) | |
872 | return; | |
873 | if (GET_CODE (reg) == SUBREG) | |
874 | reg = SUBREG_REG (reg); | |
875 | if (! REG_P (reg) || (int) REGNO (reg) < new_regno_start) | |
876 | return; | |
877 | if (in_class_p (reg, cl, &rclass) && rclass != cl) | |
a2d0d374 | 878 | lra_change_class (REGNO (reg), rclass, " Change to", true); |
55a2c322 VM |
879 | } |
880 | ||
4be9717c VM |
881 | /* Searches X for any reference to a reg with the same value as REGNO, |
882 | returning the rtx of the reference found if any. Otherwise, | |
883 | returns NULL_RTX. */ | |
884 | static rtx | |
885 | regno_val_use_in (unsigned int regno, rtx x) | |
886 | { | |
887 | const char *fmt; | |
888 | int i, j; | |
889 | rtx tem; | |
890 | ||
891 | if (REG_P (x) && lra_reg_info[REGNO (x)].val == lra_reg_info[regno].val) | |
892 | return x; | |
893 | ||
894 | fmt = GET_RTX_FORMAT (GET_CODE (x)); | |
895 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) | |
896 | { | |
897 | if (fmt[i] == 'e') | |
898 | { | |
899 | if ((tem = regno_val_use_in (regno, XEXP (x, i)))) | |
900 | return tem; | |
901 | } | |
902 | else if (fmt[i] == 'E') | |
903 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
904 | if ((tem = regno_val_use_in (regno , XVECEXP (x, i, j)))) | |
905 | return tem; | |
906 | } | |
907 | ||
908 | return NULL_RTX; | |
909 | } | |
910 | ||
d8321b33 VM |
911 | /* Return true if all current insn non-output operands except INS (it |
912 | has a negaitve end marker) do not use pseudos with the same value | |
913 | as REGNO. */ | |
914 | static bool | |
915 | check_conflict_input_operands (int regno, signed char *ins) | |
916 | { | |
917 | int in; | |
918 | int n_operands = curr_static_id->n_operands; | |
919 | ||
920 | for (int nop = 0; nop < n_operands; nop++) | |
921 | if (! curr_static_id->operand[nop].is_operator | |
922 | && curr_static_id->operand[nop].type != OP_OUT) | |
923 | { | |
924 | for (int i = 0; (in = ins[i]) >= 0; i++) | |
925 | if (in == nop) | |
926 | break; | |
927 | if (in < 0 | |
928 | && regno_val_use_in (regno, *curr_id->operand_loc[nop]) != NULL_RTX) | |
929 | return false; | |
930 | } | |
931 | return true; | |
932 | } | |
933 | ||
55a2c322 | 934 | /* Generate reloads for matching OUT and INS (array of input operand |
aefae0f1 TP |
935 | numbers with end marker -1) with reg class GOAL_CLASS, considering |
936 | output operands OUTS (similar array to INS) needing to be in different | |
937 | registers. Add input and output reloads correspondingly to the lists | |
938 | *BEFORE and *AFTER. OUT might be negative. In this case we generate | |
939 | input reloads for matched input operands INS. EARLY_CLOBBER_P is a flag | |
940 | that the output operand is early clobbered for chosen alternative. */ | |
55a2c322 | 941 | static void |
aefae0f1 TP |
942 | match_reload (signed char out, signed char *ins, signed char *outs, |
943 | enum reg_class goal_class, rtx_insn **before, | |
944 | rtx_insn **after, bool early_clobber_p) | |
55a2c322 | 945 | { |
aefae0f1 | 946 | bool out_conflict; |
55a2c322 | 947 | int i, in; |
e67d1102 | 948 | rtx new_in_reg, new_out_reg, reg; |
ef4bddc2 | 949 | machine_mode inmode, outmode; |
55a2c322 | 950 | rtx in_rtx = *curr_id->operand_loc[ins[0]]; |
511dcace | 951 | rtx out_rtx = out < 0 ? in_rtx : *curr_id->operand_loc[out]; |
55a2c322 | 952 | |
55a2c322 | 953 | inmode = curr_operand_mode[ins[0]]; |
511dcace | 954 | outmode = out < 0 ? inmode : curr_operand_mode[out]; |
55a2c322 VM |
955 | push_to_sequence (*before); |
956 | if (inmode != outmode) | |
957 | { | |
00224b1a RS |
958 | /* process_alt_operands has already checked that the mode sizes |
959 | are ordered. */ | |
bd4288c0 | 960 | if (partial_subreg_p (outmode, inmode)) |
55a2c322 VM |
961 | { |
962 | reg = new_in_reg | |
963 | = lra_create_new_reg_with_unique_value (inmode, in_rtx, | |
964 | goal_class, ""); | |
98a05c03 | 965 | new_out_reg = gen_lowpart_SUBREG (outmode, reg); |
2c62cbaa | 966 | LRA_SUBREG_P (new_out_reg) = 1; |
350c0fe7 | 967 | /* If the input reg is dying here, we can use the same hard |
f681cf95 VM |
968 | register for REG and IN_RTX. We do it only for original |
969 | pseudos as reload pseudos can die although original | |
970 | pseudos still live where reload pseudos dies. */ | |
971 | if (REG_P (in_rtx) && (int) REGNO (in_rtx) < lra_new_regno_start | |
d8321b33 VM |
972 | && find_regno_note (curr_insn, REG_DEAD, REGNO (in_rtx)) |
973 | && (!early_clobber_p | |
974 | || check_conflict_input_operands(REGNO (in_rtx), ins))) | |
d70a81dd | 975 | lra_assign_reg_val (REGNO (in_rtx), REGNO (reg)); |
55a2c322 VM |
976 | } |
977 | else | |
978 | { | |
979 | reg = new_out_reg | |
980 | = lra_create_new_reg_with_unique_value (outmode, out_rtx, | |
981 | goal_class, ""); | |
98a05c03 | 982 | new_in_reg = gen_lowpart_SUBREG (inmode, reg); |
55a2c322 VM |
983 | /* NEW_IN_REG is non-paradoxical subreg. We don't want |
984 | NEW_OUT_REG living above. We add clobber clause for | |
c5cd5a7e VM |
985 | this. This is just a temporary clobber. We can remove |
986 | it at the end of LRA work. */ | |
e67d1102 | 987 | rtx_insn *clobber = emit_clobber (new_out_reg); |
c5cd5a7e | 988 | LRA_TEMP_CLOBBER_P (PATTERN (clobber)) = 1; |
2c62cbaa | 989 | LRA_SUBREG_P (new_in_reg) = 1; |
350c0fe7 VM |
990 | if (GET_CODE (in_rtx) == SUBREG) |
991 | { | |
992 | rtx subreg_reg = SUBREG_REG (in_rtx); | |
993 | ||
994 | /* If SUBREG_REG is dying here and sub-registers IN_RTX | |
995 | and NEW_IN_REG are similar, we can use the same hard | |
996 | register for REG and SUBREG_REG. */ | |
f681cf95 VM |
997 | if (REG_P (subreg_reg) |
998 | && (int) REGNO (subreg_reg) < lra_new_regno_start | |
999 | && GET_MODE (subreg_reg) == outmode | |
91914e56 | 1000 | && known_eq (SUBREG_BYTE (in_rtx), SUBREG_BYTE (new_in_reg)) |
d8321b33 VM |
1001 | && find_regno_note (curr_insn, REG_DEAD, REGNO (subreg_reg)) |
1002 | && (! early_clobber_p | |
1003 | || check_conflict_input_operands (REGNO (subreg_reg), | |
1004 | ins))) | |
d70a81dd | 1005 | lra_assign_reg_val (REGNO (subreg_reg), REGNO (reg)); |
350c0fe7 | 1006 | } |
55a2c322 VM |
1007 | } |
1008 | } | |
1009 | else | |
1010 | { | |
1011 | /* Pseudos have values -- see comments for lra_reg_info. | |
1012 | Different pseudos with the same value do not conflict even if | |
1013 | they live in the same place. When we create a pseudo we | |
1014 | assign value of original pseudo (if any) from which we | |
1015 | created the new pseudo. If we create the pseudo from the | |
3363daad VM |
1016 | input pseudo, the new pseudo will have no conflict with the |
1017 | input pseudo which is wrong when the input pseudo lives after | |
1018 | the insn and as the new pseudo value is changed by the insn | |
1019 | output. Therefore we create the new pseudo from the output | |
1020 | except the case when we have single matched dying input | |
1021 | pseudo. | |
f4eafc30 | 1022 | |
55a2c322 VM |
1023 | We cannot reuse the current output register because we might |
1024 | have a situation like "a <- a op b", where the constraints | |
1025 | force the second input operand ("b") to match the output | |
1026 | operand ("a"). "b" must then be copied into a new register | |
599e1cf8 VM |
1027 | so that it doesn't clobber the current value of "a". |
1028 | ||
67914693 | 1029 | We cannot use the same value if the output pseudo is |
599e1cf8 VM |
1030 | early clobbered or the input pseudo is mentioned in the |
1031 | output, e.g. as an address part in memory, because | |
1032 | output reload will actually extend the pseudo liveness. | |
1033 | We don't care about eliminable hard regs here as we are | |
1034 | interesting only in pseudos. */ | |
f4eafc30 | 1035 | |
aefae0f1 TP |
1036 | /* Matching input's register value is the same as one of the other |
1037 | output operand. Output operands in a parallel insn must be in | |
1038 | different registers. */ | |
1039 | out_conflict = false; | |
1040 | if (REG_P (in_rtx)) | |
1041 | { | |
1042 | for (i = 0; outs[i] >= 0; i++) | |
1043 | { | |
1044 | rtx other_out_rtx = *curr_id->operand_loc[outs[i]]; | |
1045 | if (REG_P (other_out_rtx) | |
1046 | && (regno_val_use_in (REGNO (in_rtx), other_out_rtx) | |
1047 | != NULL_RTX)) | |
1048 | { | |
1049 | out_conflict = true; | |
1050 | break; | |
1051 | } | |
1052 | } | |
1053 | } | |
1054 | ||
55a2c322 | 1055 | new_in_reg = new_out_reg |
599e1cf8 | 1056 | = (! early_clobber_p && ins[1] < 0 && REG_P (in_rtx) |
3363daad VM |
1057 | && (int) REGNO (in_rtx) < lra_new_regno_start |
1058 | && find_regno_note (curr_insn, REG_DEAD, REGNO (in_rtx)) | |
d8321b33 VM |
1059 | && (! early_clobber_p |
1060 | || check_conflict_input_operands (REGNO (in_rtx), ins)) | |
4be9717c VM |
1061 | && (out < 0 |
1062 | || regno_val_use_in (REGNO (in_rtx), out_rtx) == NULL_RTX) | |
aefae0f1 | 1063 | && !out_conflict |
3363daad VM |
1064 | ? lra_create_new_reg (inmode, in_rtx, goal_class, "") |
1065 | : lra_create_new_reg_with_unique_value (outmode, out_rtx, | |
1066 | goal_class, "")); | |
55a2c322 | 1067 | } |
511dcace VM |
1068 | /* In operand can be got from transformations before processing insn |
1069 | constraints. One example of such transformations is subreg | |
1070 | reloading (see function simplify_operand_subreg). The new | |
1071 | pseudos created by the transformations might have inaccurate | |
55a2c322 VM |
1072 | class (ALL_REGS) and we should make their classes more |
1073 | accurate. */ | |
1074 | narrow_reload_pseudo_class (in_rtx, goal_class); | |
55a2c322 VM |
1075 | lra_emit_move (copy_rtx (new_in_reg), in_rtx); |
1076 | *before = get_insns (); | |
1077 | end_sequence (); | |
3f156a6c VM |
1078 | /* Add the new pseudo to consider values of subsequent input reload |
1079 | pseudos. */ | |
1080 | lra_assert (curr_insn_input_reloads_num < LRA_MAX_INSN_RELOADS); | |
1081 | curr_insn_input_reloads[curr_insn_input_reloads_num].input = in_rtx; | |
1082 | curr_insn_input_reloads[curr_insn_input_reloads_num].match_p = true; | |
1083 | curr_insn_input_reloads[curr_insn_input_reloads_num++].reg = new_in_reg; | |
55a2c322 | 1084 | for (i = 0; (in = ins[i]) >= 0; i++) |
60257913 VM |
1085 | if (GET_MODE (*curr_id->operand_loc[in]) == VOIDmode |
1086 | || GET_MODE (new_in_reg) == GET_MODE (*curr_id->operand_loc[in])) | |
55a2c322 | 1087 | *curr_id->operand_loc[in] = new_in_reg; |
60257913 VM |
1088 | else |
1089 | { | |
1090 | lra_assert | |
1091 | (GET_MODE (new_out_reg) == GET_MODE (*curr_id->operand_loc[in])); | |
1092 | *curr_id->operand_loc[in] = new_out_reg; | |
1093 | } | |
55a2c322 | 1094 | lra_update_dups (curr_id, ins); |
511dcace VM |
1095 | if (out < 0) |
1096 | return; | |
1097 | /* See a comment for the input operand above. */ | |
1098 | narrow_reload_pseudo_class (out_rtx, goal_class); | |
55a2c322 VM |
1099 | if (find_reg_note (curr_insn, REG_UNUSED, out_rtx) == NULL_RTX) |
1100 | { | |
1101 | start_sequence (); | |
5261cf8c VM |
1102 | if (out >= 0 && curr_static_id->operand[out].strict_low) |
1103 | out_rtx = gen_rtx_STRICT_LOW_PART (VOIDmode, out_rtx); | |
55a2c322 VM |
1104 | lra_emit_move (out_rtx, copy_rtx (new_out_reg)); |
1105 | emit_insn (*after); | |
1106 | *after = get_insns (); | |
1107 | end_sequence (); | |
1108 | } | |
1109 | *curr_id->operand_loc[out] = new_out_reg; | |
1110 | lra_update_dup (curr_id, out); | |
1111 | } | |
1112 | ||
1113 | /* Return register class which is union of all reg classes in insn | |
1114 | constraint alternative string starting with P. */ | |
1115 | static enum reg_class | |
1116 | reg_class_from_constraints (const char *p) | |
1117 | { | |
1118 | int c, len; | |
1119 | enum reg_class op_class = NO_REGS; | |
1120 | ||
1121 | do | |
1122 | switch ((c = *p, len = CONSTRAINT_LEN (c, p)), c) | |
1123 | { | |
1124 | case '#': | |
1125 | case ',': | |
1126 | return op_class; | |
1127 | ||
55a2c322 | 1128 | case 'g': |
55a2c322 VM |
1129 | op_class = reg_class_subunion[op_class][GENERAL_REGS]; |
1130 | break; | |
f4eafc30 | 1131 | |
55a2c322 | 1132 | default: |
777e635f RS |
1133 | enum constraint_num cn = lookup_constraint (p); |
1134 | enum reg_class cl = reg_class_for_constraint (cn); | |
1135 | if (cl == NO_REGS) | |
55a2c322 | 1136 | { |
777e635f | 1137 | if (insn_extra_address_constraint (cn)) |
55a2c322 VM |
1138 | op_class |
1139 | = (reg_class_subunion | |
1140 | [op_class][base_reg_class (VOIDmode, ADDR_SPACE_GENERIC, | |
1141 | ADDRESS, SCRATCH)]); | |
55a2c322 VM |
1142 | break; |
1143 | } | |
f4eafc30 | 1144 | |
777e635f RS |
1145 | op_class = reg_class_subunion[op_class][cl]; |
1146 | break; | |
55a2c322 VM |
1147 | } |
1148 | while ((p += len), c); | |
1149 | return op_class; | |
1150 | } | |
1151 | ||
1152 | /* If OP is a register, return the class of the register as per | |
1153 | get_reg_class, otherwise return NO_REGS. */ | |
1154 | static inline enum reg_class | |
1155 | get_op_class (rtx op) | |
1156 | { | |
1157 | return REG_P (op) ? get_reg_class (REGNO (op)) : NO_REGS; | |
1158 | } | |
1159 | ||
1160 | /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo | |
1161 | otherwise. If modes of MEM_PSEUDO and VAL are different, use | |
1162 | SUBREG for VAL to make them equal. */ | |
cfa434f6 | 1163 | static rtx_insn * |
55a2c322 VM |
1164 | emit_spill_move (bool to_p, rtx mem_pseudo, rtx val) |
1165 | { | |
1166 | if (GET_MODE (mem_pseudo) != GET_MODE (val)) | |
2c62cbaa | 1167 | { |
cb1cca12 VM |
1168 | /* Usually size of mem_pseudo is greater than val size but in |
1169 | rare cases it can be less as it can be defined by target | |
1170 | dependent macro HARD_REGNO_CALLER_SAVE_MODE. */ | |
1ccd4874 VM |
1171 | if (! MEM_P (val)) |
1172 | { | |
54b84aa9 EB |
1173 | val = gen_lowpart_SUBREG (GET_MODE (mem_pseudo), |
1174 | GET_CODE (val) == SUBREG | |
1175 | ? SUBREG_REG (val) : val); | |
1ccd4874 VM |
1176 | LRA_SUBREG_P (val) = 1; |
1177 | } | |
1178 | else | |
1179 | { | |
1180 | mem_pseudo = gen_lowpart_SUBREG (GET_MODE (val), mem_pseudo); | |
1181 | LRA_SUBREG_P (mem_pseudo) = 1; | |
1182 | } | |
2c62cbaa | 1183 | } |
1476d1bd MM |
1184 | return to_p ? gen_move_insn (mem_pseudo, val) |
1185 | : gen_move_insn (val, mem_pseudo); | |
55a2c322 VM |
1186 | } |
1187 | ||
1188 | /* Process a special case insn (register move), return true if we | |
2c62cbaa | 1189 | don't need to process it anymore. INSN should be a single set |
f15643d4 RS |
1190 | insn. Set up that RTL was changed through CHANGE_P and that hook |
1191 | TARGET_SECONDARY_MEMORY_NEEDED says to use secondary memory through | |
2c62cbaa | 1192 | SEC_MEM_P. */ |
55a2c322 | 1193 | static bool |
2c62cbaa | 1194 | check_and_process_move (bool *change_p, bool *sec_mem_p ATTRIBUTE_UNUSED) |
55a2c322 VM |
1195 | { |
1196 | int sregno, dregno; | |
ef0006eb | 1197 | rtx dest, src, dreg, sreg, new_reg, scratch_reg; |
cfa434f6 | 1198 | rtx_insn *before; |
55a2c322 | 1199 | enum reg_class dclass, sclass, secondary_class; |
55a2c322 VM |
1200 | secondary_reload_info sri; |
1201 | ||
2c62cbaa VM |
1202 | lra_assert (curr_insn_set != NULL_RTX); |
1203 | dreg = dest = SET_DEST (curr_insn_set); | |
1204 | sreg = src = SET_SRC (curr_insn_set); | |
55a2c322 VM |
1205 | if (GET_CODE (dest) == SUBREG) |
1206 | dreg = SUBREG_REG (dest); | |
1207 | if (GET_CODE (src) == SUBREG) | |
1208 | sreg = SUBREG_REG (src); | |
1ccd4874 | 1209 | if (! (REG_P (dreg) || MEM_P (dreg)) || ! (REG_P (sreg) || MEM_P (sreg))) |
55a2c322 VM |
1210 | return false; |
1211 | sclass = dclass = NO_REGS; | |
55a2c322 VM |
1212 | if (REG_P (dreg)) |
1213 | dclass = get_reg_class (REGNO (dreg)); | |
48855443 | 1214 | gcc_assert (dclass < LIM_REG_CLASSES); |
55a2c322 VM |
1215 | if (dclass == ALL_REGS) |
1216 | /* ALL_REGS is used for new pseudos created by transformations | |
1217 | like reload of SUBREG_REG (see function | |
1218 | simplify_operand_subreg). We don't know their class yet. We | |
1219 | should figure out the class from processing the insn | |
1220 | constraints not in this fast path function. Even if ALL_REGS | |
1221 | were a right class for the pseudo, secondary_... hooks usually | |
1222 | are not define for ALL_REGS. */ | |
1223 | return false; | |
55a2c322 VM |
1224 | if (REG_P (sreg)) |
1225 | sclass = get_reg_class (REGNO (sreg)); | |
48855443 | 1226 | gcc_assert (sclass < LIM_REG_CLASSES); |
55a2c322 VM |
1227 | if (sclass == ALL_REGS) |
1228 | /* See comments above. */ | |
1229 | return false; | |
1ccd4874 VM |
1230 | if (sclass == NO_REGS && dclass == NO_REGS) |
1231 | return false; | |
f15643d4 | 1232 | if (targetm.secondary_memory_needed (GET_MODE (src), sclass, dclass) |
1ccd4874 | 1233 | && ((sclass != NO_REGS && dclass != NO_REGS) |
94e23f53 RS |
1234 | || (GET_MODE (src) |
1235 | != targetm.secondary_memory_needed_mode (GET_MODE (src))))) | |
55a2c322 VM |
1236 | { |
1237 | *sec_mem_p = true; | |
1238 | return false; | |
1239 | } | |
1ccd4874 VM |
1240 | if (! REG_P (dreg) || ! REG_P (sreg)) |
1241 | return false; | |
55a2c322 VM |
1242 | sri.prev_sri = NULL; |
1243 | sri.icode = CODE_FOR_nothing; | |
1244 | sri.extra_cost = 0; | |
1245 | secondary_class = NO_REGS; | |
1246 | /* Set up hard register for a reload pseudo for hook | |
1247 | secondary_reload because some targets just ignore unassigned | |
1248 | pseudos in the hook. */ | |
1249 | if (dclass != NO_REGS && lra_get_regno_hard_regno (REGNO (dreg)) < 0) | |
1250 | { | |
1251 | dregno = REGNO (dreg); | |
1252 | reg_renumber[dregno] = ira_class_hard_regs[dclass][0]; | |
1253 | } | |
1254 | else | |
1255 | dregno = -1; | |
1256 | if (sclass != NO_REGS && lra_get_regno_hard_regno (REGNO (sreg)) < 0) | |
1257 | { | |
1258 | sregno = REGNO (sreg); | |
1259 | reg_renumber[sregno] = ira_class_hard_regs[sclass][0]; | |
1260 | } | |
1261 | else | |
1262 | sregno = -1; | |
1263 | if (sclass != NO_REGS) | |
1264 | secondary_class | |
1265 | = (enum reg_class) targetm.secondary_reload (false, dest, | |
1266 | (reg_class_t) sclass, | |
1267 | GET_MODE (src), &sri); | |
1268 | if (sclass == NO_REGS | |
1269 | || ((secondary_class != NO_REGS || sri.icode != CODE_FOR_nothing) | |
1270 | && dclass != NO_REGS)) | |
1271 | { | |
55a2c322 VM |
1272 | enum reg_class old_sclass = secondary_class; |
1273 | secondary_reload_info old_sri = sri; | |
55a2c322 VM |
1274 | |
1275 | sri.prev_sri = NULL; | |
1276 | sri.icode = CODE_FOR_nothing; | |
1277 | sri.extra_cost = 0; | |
1278 | secondary_class | |
ef0006eb | 1279 | = (enum reg_class) targetm.secondary_reload (true, src, |
55a2c322 | 1280 | (reg_class_t) dclass, |
ef0006eb | 1281 | GET_MODE (src), &sri); |
55a2c322 VM |
1282 | /* Check the target hook consistency. */ |
1283 | lra_assert | |
1284 | ((secondary_class == NO_REGS && sri.icode == CODE_FOR_nothing) | |
1285 | || (old_sclass == NO_REGS && old_sri.icode == CODE_FOR_nothing) | |
1286 | || (secondary_class == old_sclass && sri.icode == old_sri.icode)); | |
1287 | } | |
1288 | if (sregno >= 0) | |
1289 | reg_renumber [sregno] = -1; | |
1290 | if (dregno >= 0) | |
1291 | reg_renumber [dregno] = -1; | |
1292 | if (secondary_class == NO_REGS && sri.icode == CODE_FOR_nothing) | |
1293 | return false; | |
1294 | *change_p = true; | |
1295 | new_reg = NULL_RTX; | |
1296 | if (secondary_class != NO_REGS) | |
ef0006eb | 1297 | new_reg = lra_create_new_reg_with_unique_value (GET_MODE (src), NULL_RTX, |
55a2c322 VM |
1298 | secondary_class, |
1299 | "secondary"); | |
1300 | start_sequence (); | |
55a2c322 | 1301 | if (sri.icode == CODE_FOR_nothing) |
ef0006eb | 1302 | lra_emit_move (new_reg, src); |
55a2c322 VM |
1303 | else |
1304 | { | |
1305 | enum reg_class scratch_class; | |
1306 | ||
1307 | scratch_class = (reg_class_from_constraints | |
1308 | (insn_data[sri.icode].operand[2].constraint)); | |
1309 | scratch_reg = (lra_create_new_reg_with_unique_value | |
1310 | (insn_data[sri.icode].operand[2].mode, NULL_RTX, | |
1311 | scratch_class, "scratch")); | |
1312 | emit_insn (GEN_FCN (sri.icode) (new_reg != NULL_RTX ? new_reg : dest, | |
ef0006eb | 1313 | src, scratch_reg)); |
55a2c322 VM |
1314 | } |
1315 | before = get_insns (); | |
1316 | end_sequence (); | |
cfa434f6 | 1317 | lra_process_new_insns (curr_insn, before, NULL, "Inserting the move"); |
55a2c322 | 1318 | if (new_reg != NULL_RTX) |
ef0006eb | 1319 | SET_SRC (curr_insn_set) = new_reg; |
55a2c322 VM |
1320 | else |
1321 | { | |
1322 | if (lra_dump_file != NULL) | |
1323 | { | |
1324 | fprintf (lra_dump_file, "Deleting move %u\n", INSN_UID (curr_insn)); | |
cfbeaedf | 1325 | dump_insn_slim (lra_dump_file, curr_insn); |
55a2c322 VM |
1326 | } |
1327 | lra_set_insn_deleted (curr_insn); | |
1328 | return true; | |
1329 | } | |
1330 | return false; | |
1331 | } | |
1332 | ||
1333 | /* The following data describe the result of process_alt_operands. | |
1334 | The data are used in curr_insn_transform to generate reloads. */ | |
1335 | ||
1336 | /* The chosen reg classes which should be used for the corresponding | |
1337 | operands. */ | |
1338 | static enum reg_class goal_alt[MAX_RECOG_OPERANDS]; | |
1339 | /* True if the operand should be the same as another operand and that | |
1340 | other operand does not need a reload. */ | |
1341 | static bool goal_alt_match_win[MAX_RECOG_OPERANDS]; | |
1342 | /* True if the operand does not need a reload. */ | |
1343 | static bool goal_alt_win[MAX_RECOG_OPERANDS]; | |
1344 | /* True if the operand can be offsetable memory. */ | |
1345 | static bool goal_alt_offmemok[MAX_RECOG_OPERANDS]; | |
1346 | /* The number of an operand to which given operand can be matched to. */ | |
1347 | static int goal_alt_matches[MAX_RECOG_OPERANDS]; | |
1348 | /* The number of elements in the following array. */ | |
1349 | static int goal_alt_dont_inherit_ops_num; | |
1350 | /* Numbers of operands whose reload pseudos should not be inherited. */ | |
1351 | static int goal_alt_dont_inherit_ops[MAX_RECOG_OPERANDS]; | |
1352 | /* True if the insn commutative operands should be swapped. */ | |
1353 | static bool goal_alt_swapped; | |
1354 | /* The chosen insn alternative. */ | |
1355 | static int goal_alt_number; | |
1356 | ||
987b67f1 VM |
1357 | /* True if the corresponding operand is the result of an equivalence |
1358 | substitution. */ | |
1359 | static bool equiv_substition_p[MAX_RECOG_OPERANDS]; | |
1360 | ||
55a2c322 VM |
1361 | /* The following five variables are used to choose the best insn |
1362 | alternative. They reflect final characteristics of the best | |
1363 | alternative. */ | |
1364 | ||
1365 | /* Number of necessary reloads and overall cost reflecting the | |
1366 | previous value and other unpleasantness of the best alternative. */ | |
1367 | static int best_losers, best_overall; | |
55a2c322 VM |
1368 | /* Overall number hard registers used for reloads. For example, on |
1369 | some targets we need 2 general registers to reload DFmode and only | |
1370 | one floating point register. */ | |
1371 | static int best_reload_nregs; | |
1372 | /* Overall number reflecting distances of previous reloading the same | |
1373 | value. The distances are counted from the current BB start. It is | |
1374 | used to improve inheritance chances. */ | |
1375 | static int best_reload_sum; | |
1376 | ||
1377 | /* True if the current insn should have no correspondingly input or | |
1378 | output reloads. */ | |
1379 | static bool no_input_reloads_p, no_output_reloads_p; | |
1380 | ||
1381 | /* True if we swapped the commutative operands in the current | |
1382 | insn. */ | |
1383 | static int curr_swapped; | |
1384 | ||
d9cf932c VM |
1385 | /* if CHECK_ONLY_P is false, arrange for address element *LOC to be a |
1386 | register of class CL. Add any input reloads to list BEFORE. AFTER | |
1387 | is nonnull if *LOC is an automodified value; handle that case by | |
1388 | adding the required output reloads to list AFTER. Return true if | |
1389 | the RTL was changed. | |
1390 | ||
1391 | if CHECK_ONLY_P is true, check that the *LOC is a correct address | |
1392 | register. Return false if the address register is correct. */ | |
55a2c322 | 1393 | static bool |
d9cf932c | 1394 | process_addr_reg (rtx *loc, bool check_only_p, rtx_insn **before, rtx_insn **after, |
cfa434f6 | 1395 | enum reg_class cl) |
55a2c322 VM |
1396 | { |
1397 | int regno; | |
1398 | enum reg_class rclass, new_class; | |
277f65de | 1399 | rtx reg; |
55a2c322 | 1400 | rtx new_reg; |
ef4bddc2 | 1401 | machine_mode mode; |
95921002 | 1402 | bool subreg_p, before_p = false; |
55a2c322 | 1403 | |
95921002 VM |
1404 | subreg_p = GET_CODE (*loc) == SUBREG; |
1405 | if (subreg_p) | |
ada2eb68 JW |
1406 | { |
1407 | reg = SUBREG_REG (*loc); | |
1408 | mode = GET_MODE (reg); | |
1409 | ||
1410 | /* For mode with size bigger than ptr_mode, there unlikely to be "mov" | |
1411 | between two registers with different classes, but there normally will | |
1412 | be "mov" which transfers element of vector register into the general | |
1413 | register, and this normally will be a subreg which should be reloaded | |
1414 | as a whole. This is particularly likely to be triggered when | |
1415 | -fno-split-wide-types specified. */ | |
3c11e1af JW |
1416 | if (!REG_P (reg) |
1417 | || in_class_p (reg, cl, &new_class) | |
cf098191 | 1418 | || known_le (GET_MODE_SIZE (mode), GET_MODE_SIZE (ptr_mode))) |
ada2eb68 JW |
1419 | loc = &SUBREG_REG (*loc); |
1420 | } | |
1421 | ||
277f65de | 1422 | reg = *loc; |
55a2c322 VM |
1423 | mode = GET_MODE (reg); |
1424 | if (! REG_P (reg)) | |
1425 | { | |
d9cf932c VM |
1426 | if (check_only_p) |
1427 | return true; | |
55a2c322 VM |
1428 | /* Always reload memory in an address even if the target supports |
1429 | such addresses. */ | |
1430 | new_reg = lra_create_new_reg_with_unique_value (mode, reg, cl, "address"); | |
1431 | before_p = true; | |
1432 | } | |
1433 | else | |
1434 | { | |
1435 | regno = REGNO (reg); | |
1436 | rclass = get_reg_class (regno); | |
d9cf932c VM |
1437 | if (! check_only_p |
1438 | && (*loc = get_equiv_with_elimination (reg, curr_insn)) != reg) | |
55a2c322 VM |
1439 | { |
1440 | if (lra_dump_file != NULL) | |
1441 | { | |
1442 | fprintf (lra_dump_file, | |
1443 | "Changing pseudo %d in address of insn %u on equiv ", | |
1444 | REGNO (reg), INSN_UID (curr_insn)); | |
cfbeaedf | 1445 | dump_value_slim (lra_dump_file, *loc, 1); |
55a2c322 VM |
1446 | fprintf (lra_dump_file, "\n"); |
1447 | } | |
1448 | *loc = copy_rtx (*loc); | |
1449 | } | |
1450 | if (*loc != reg || ! in_class_p (reg, cl, &new_class)) | |
1451 | { | |
d9cf932c VM |
1452 | if (check_only_p) |
1453 | return true; | |
55a2c322 VM |
1454 | reg = *loc; |
1455 | if (get_reload_reg (after == NULL ? OP_IN : OP_INOUT, | |
95921002 | 1456 | mode, reg, cl, subreg_p, "address", &new_reg)) |
55a2c322 VM |
1457 | before_p = true; |
1458 | } | |
1459 | else if (new_class != NO_REGS && rclass != new_class) | |
1460 | { | |
d9cf932c VM |
1461 | if (check_only_p) |
1462 | return true; | |
a2d0d374 | 1463 | lra_change_class (regno, new_class, " Change to", true); |
55a2c322 VM |
1464 | return false; |
1465 | } | |
1466 | else | |
1467 | return false; | |
1468 | } | |
1469 | if (before_p) | |
1470 | { | |
1471 | push_to_sequence (*before); | |
1472 | lra_emit_move (new_reg, reg); | |
1473 | *before = get_insns (); | |
1474 | end_sequence (); | |
1475 | } | |
1476 | *loc = new_reg; | |
1477 | if (after != NULL) | |
1478 | { | |
1479 | start_sequence (); | |
9a9fe2b4 | 1480 | lra_emit_move (before_p ? copy_rtx (reg) : reg, new_reg); |
55a2c322 VM |
1481 | emit_insn (*after); |
1482 | *after = get_insns (); | |
1483 | end_sequence (); | |
1484 | } | |
1485 | return true; | |
1486 | } | |
1487 | ||
4f0bee4c WM |
1488 | /* Insert move insn in simplify_operand_subreg. BEFORE returns |
1489 | the insn to be inserted before curr insn. AFTER returns the | |
1490 | the insn to be inserted after curr insn. ORIGREG and NEWREG | |
1491 | are the original reg and new reg for reload. */ | |
1492 | static void | |
cfa434f6 DM |
1493 | insert_move_for_subreg (rtx_insn **before, rtx_insn **after, rtx origreg, |
1494 | rtx newreg) | |
4f0bee4c WM |
1495 | { |
1496 | if (before) | |
1497 | { | |
1498 | push_to_sequence (*before); | |
1499 | lra_emit_move (newreg, origreg); | |
1500 | *before = get_insns (); | |
1501 | end_sequence (); | |
1502 | } | |
1503 | if (after) | |
1504 | { | |
1505 | start_sequence (); | |
1506 | lra_emit_move (origreg, newreg); | |
1507 | emit_insn (*after); | |
1508 | *after = get_insns (); | |
1509 | end_sequence (); | |
1510 | } | |
1511 | } | |
1512 | ||
ef4bddc2 | 1513 | static int valid_address_p (machine_mode mode, rtx addr, addr_space_t as); |
ab5d2233 | 1514 | static bool process_address (int, bool, rtx_insn **, rtx_insn **); |
ba38538f | 1515 | |
55a2c322 VM |
1516 | /* Make reloads for subreg in operand NOP with internal subreg mode |
1517 | REG_MODE, add new reloads for further processing. Return true if | |
895ff86f | 1518 | any change was done. */ |
55a2c322 | 1519 | static bool |
ef4bddc2 | 1520 | simplify_operand_subreg (int nop, machine_mode reg_mode) |
55a2c322 | 1521 | { |
497498c8 | 1522 | int hard_regno, inner_hard_regno; |
cfa434f6 | 1523 | rtx_insn *before, *after; |
895ff86f | 1524 | machine_mode mode, innermode; |
55a2c322 VM |
1525 | rtx reg, new_reg; |
1526 | rtx operand = *curr_id->operand_loc[nop]; | |
4f0bee4c WM |
1527 | enum reg_class regclass; |
1528 | enum op_type type; | |
55a2c322 | 1529 | |
cfa434f6 | 1530 | before = after = NULL; |
55a2c322 VM |
1531 | |
1532 | if (GET_CODE (operand) != SUBREG) | |
1533 | return false; | |
f4eafc30 | 1534 | |
55a2c322 VM |
1535 | mode = GET_MODE (operand); |
1536 | reg = SUBREG_REG (operand); | |
895ff86f | 1537 | innermode = GET_MODE (reg); |
4f0bee4c | 1538 | type = curr_static_id->operand[nop].type; |
2e186411 | 1539 | if (MEM_P (reg)) |
ba38538f | 1540 | { |
ab5d2233 EB |
1541 | const bool addr_was_valid |
1542 | = valid_address_p (innermode, XEXP (reg, 0), MEM_ADDR_SPACE (reg)); | |
ba38538f | 1543 | alter_subreg (curr_id->operand_loc[nop], false); |
ab5d2233 | 1544 | rtx subst = *curr_id->operand_loc[nop]; |
ba38538f | 1545 | lra_assert (MEM_P (subst)); |
8eaff6ef VM |
1546 | const bool addr_is_valid = valid_address_p (GET_MODE (subst), |
1547 | XEXP (subst, 0), | |
1548 | MEM_ADDR_SPACE (subst)); | |
ab5d2233 | 1549 | if (!addr_was_valid |
8eaff6ef | 1550 | || addr_is_valid |
2e186411 AM |
1551 | || ((get_constraint_type (lookup_constraint |
1552 | (curr_static_id->operand[nop].constraint)) | |
1553 | != CT_SPECIAL_MEMORY) | |
1554 | /* We still can reload address and if the address is | |
1555 | valid, we can remove subreg without reloading its | |
1556 | inner memory. */ | |
1557 | && valid_address_p (GET_MODE (subst), | |
1558 | regno_reg_rtx | |
1559 | [ira_class_hard_regs | |
1560 | [base_reg_class (GET_MODE (subst), | |
1561 | MEM_ADDR_SPACE (subst), | |
1562 | ADDRESS, SCRATCH)][0]], | |
1563 | MEM_ADDR_SPACE (subst)))) | |
1564 | { | |
ab5d2233 | 1565 | /* If we change the address for a paradoxical subreg of memory, the |
849fccf8 EB |
1566 | new address might violate the necessary alignment or the access |
1567 | might be slow; take this into consideration. We need not worry | |
ab5d2233 | 1568 | about accesses beyond allocated memory for paradoxical memory |
2e186411 AM |
1569 | subregs as we don't substitute such equiv memory (see processing |
1570 | equivalences in function lra_constraints) and because for spilled | |
1571 | pseudos we allocate stack memory enough for the biggest | |
198075e1 MF |
1572 | corresponding paradoxical subreg. |
1573 | ||
1574 | However, do not blindly simplify a (subreg (mem ...)) for | |
1575 | WORD_REGISTER_OPERATIONS targets as this may lead to loading junk | |
1576 | data into a register when the inner is narrower than outer or | |
1577 | missing important data from memory when the inner is wider than | |
1578 | outer. This rule only applies to modes that are no wider than | |
8eaff6ef VM |
1579 | a word. |
1580 | ||
1581 | If valid memory becomes invalid after subreg elimination | |
f8dc3fb2 VM |
1582 | and address might be different we still have to reload |
1583 | memory. | |
8eaff6ef | 1584 | */ |
f8dc3fb2 VM |
1585 | if ((! addr_was_valid |
1586 | || addr_is_valid | |
1587 | || known_eq (GET_MODE_SIZE (mode), GET_MODE_SIZE (innermode))) | |
8eaff6ef VM |
1588 | && !(maybe_ne (GET_MODE_PRECISION (mode), |
1589 | GET_MODE_PRECISION (innermode)) | |
1590 | && known_le (GET_MODE_SIZE (mode), UNITS_PER_WORD) | |
1591 | && known_le (GET_MODE_SIZE (innermode), UNITS_PER_WORD) | |
1592 | && WORD_REGISTER_OPERATIONS) | |
198075e1 | 1593 | && (!(MEM_ALIGN (subst) < GET_MODE_ALIGNMENT (mode) |
e0bd6c9f | 1594 | && targetm.slow_unaligned_access (mode, MEM_ALIGN (subst))) |
198075e1 | 1595 | || (MEM_ALIGN (reg) < GET_MODE_ALIGNMENT (innermode) |
e0bd6c9f RS |
1596 | && targetm.slow_unaligned_access (innermode, |
1597 | MEM_ALIGN (reg))))) | |
2e186411 AM |
1598 | return true; |
1599 | ||
ab5d2233 EB |
1600 | *curr_id->operand_loc[nop] = operand; |
1601 | ||
1602 | /* But if the address was not valid, we cannot reload the MEM without | |
1603 | reloading the address first. */ | |
1604 | if (!addr_was_valid) | |
1605 | process_address (nop, false, &before, &after); | |
1606 | ||
2e186411 AM |
1607 | /* INNERMODE is fast, MODE slow. Reload the mem in INNERMODE. */ |
1608 | enum reg_class rclass | |
1609 | = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS); | |
ab5d2233 | 1610 | if (get_reload_reg (curr_static_id->operand[nop].type, innermode, |
8eaff6ef | 1611 | reg, rclass, TRUE, "slow/invalid mem", &new_reg)) |
2e186411 AM |
1612 | { |
1613 | bool insert_before, insert_after; | |
1614 | bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg)); | |
1615 | ||
1616 | insert_before = (type != OP_OUT | |
bd4288c0 | 1617 | || partial_subreg_p (mode, innermode)); |
2e186411 AM |
1618 | insert_after = type != OP_IN; |
1619 | insert_move_for_subreg (insert_before ? &before : NULL, | |
1620 | insert_after ? &after : NULL, | |
1621 | reg, new_reg); | |
1622 | } | |
2e186411 AM |
1623 | SUBREG_REG (operand) = new_reg; |
1624 | ||
1625 | /* Convert to MODE. */ | |
1626 | reg = operand; | |
ab5d2233 EB |
1627 | rclass |
1628 | = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS); | |
2e186411 | 1629 | if (get_reload_reg (curr_static_id->operand[nop].type, mode, reg, |
8eaff6ef | 1630 | rclass, TRUE, "slow/invalid mem", &new_reg)) |
2e186411 AM |
1631 | { |
1632 | bool insert_before, insert_after; | |
1633 | bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg)); | |
1634 | ||
1635 | insert_before = type != OP_OUT; | |
1636 | insert_after = type != OP_IN; | |
1637 | insert_move_for_subreg (insert_before ? &before : NULL, | |
1638 | insert_after ? &after : NULL, | |
1639 | reg, new_reg); | |
1640 | } | |
1641 | *curr_id->operand_loc[nop] = new_reg; | |
1642 | lra_process_new_insns (curr_insn, before, after, | |
8eaff6ef | 1643 | "Inserting slow/invalid mem reload"); |
2e186411 AM |
1644 | return true; |
1645 | } | |
95831c01 | 1646 | |
ba38538f VM |
1647 | /* If the address was valid and became invalid, prefer to reload |
1648 | the memory. Typical case is when the index scale should | |
1649 | correspond the memory. */ | |
2e186411 | 1650 | *curr_id->operand_loc[nop] = operand; |
77850e96 MF |
1651 | /* Do not return false here as the MEM_P (reg) will be processed |
1652 | later in this function. */ | |
ba38538f VM |
1653 | } |
1654 | else if (REG_P (reg) && REGNO (reg) < FIRST_PSEUDO_REGISTER) | |
55a2c322 VM |
1655 | { |
1656 | alter_subreg (curr_id->operand_loc[nop], false); | |
1657 | return true; | |
1658 | } | |
895ff86f VM |
1659 | else if (CONSTANT_P (reg)) |
1660 | { | |
1661 | /* Try to simplify subreg of constant. It is usually result of | |
1662 | equivalence substitution. */ | |
1663 | if (innermode == VOIDmode | |
1664 | && (innermode = original_subreg_reg_mode[nop]) == VOIDmode) | |
1665 | innermode = curr_static_id->operand[nop].mode; | |
1666 | if ((new_reg = simplify_subreg (mode, reg, innermode, | |
1667 | SUBREG_BYTE (operand))) != NULL_RTX) | |
1668 | { | |
1669 | *curr_id->operand_loc[nop] = new_reg; | |
1670 | return true; | |
1671 | } | |
1672 | } | |
55a2c322 VM |
1673 | /* Put constant into memory when we have mixed modes. It generates |
1674 | a better code in most cases as it does not need a secondary | |
1675 | reload memory. It also prevents LRA looping when LRA is using | |
1676 | secondary reload memory again and again. */ | |
1677 | if (CONSTANT_P (reg) && CONST_POOL_OK_P (reg_mode, reg) | |
1678 | && SCALAR_INT_MODE_P (reg_mode) != SCALAR_INT_MODE_P (mode)) | |
1679 | { | |
1680 | SUBREG_REG (operand) = force_const_mem (reg_mode, reg); | |
1681 | alter_subreg (curr_id->operand_loc[nop], false); | |
1682 | return true; | |
1683 | } | |
1684 | /* Force a reload of the SUBREG_REG if this is a constant or PLUS or | |
1685 | if there may be a problem accessing OPERAND in the outer | |
1686 | mode. */ | |
1687 | if ((REG_P (reg) | |
1688 | && REGNO (reg) >= FIRST_PSEUDO_REGISTER | |
1689 | && (hard_regno = lra_get_regno_hard_regno (REGNO (reg))) >= 0 | |
1690 | /* Don't reload paradoxical subregs because we could be looping | |
1691 | having repeatedly final regno out of hard regs range. */ | |
ad474626 RS |
1692 | && (hard_regno_nregs (hard_regno, innermode) |
1693 | >= hard_regno_nregs (hard_regno, mode)) | |
895ff86f | 1694 | && simplify_subreg_regno (hard_regno, innermode, |
2c62cbaa VM |
1695 | SUBREG_BYTE (operand), mode) < 0 |
1696 | /* Don't reload subreg for matching reload. It is actually | |
1697 | valid subreg in LRA. */ | |
1698 | && ! LRA_SUBREG_P (operand)) | |
55a2c322 VM |
1699 | || CONSTANT_P (reg) || GET_CODE (reg) == PLUS || MEM_P (reg)) |
1700 | { | |
6e23f296 VM |
1701 | enum reg_class rclass; |
1702 | ||
7613fa50 VM |
1703 | if (REG_P (reg)) |
1704 | /* There is a big probability that we will get the same class | |
6e23f296 VM |
1705 | for the new pseudo and we will get the same insn which |
1706 | means infinite looping. So spill the new pseudo. */ | |
1707 | rclass = NO_REGS; | |
1708 | else | |
1709 | /* The class will be defined later in curr_insn_transform. */ | |
1710 | rclass | |
1711 | = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS); | |
55a2c322 | 1712 | |
25bb0bb5 | 1713 | if (get_reload_reg (curr_static_id->operand[nop].type, reg_mode, reg, |
95921002 | 1714 | rclass, TRUE, "subreg reg", &new_reg)) |
55a2c322 | 1715 | { |
4f0bee4c | 1716 | bool insert_before, insert_after; |
2b778c9d | 1717 | bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg)); |
4f0bee4c WM |
1718 | |
1719 | insert_before = (type != OP_OUT | |
9eaf97d6 | 1720 | || read_modify_subreg_p (operand)); |
4f0bee4c WM |
1721 | insert_after = (type != OP_IN); |
1722 | insert_move_for_subreg (insert_before ? &before : NULL, | |
1723 | insert_after ? &after : NULL, | |
1724 | reg, new_reg); | |
55a2c322 VM |
1725 | } |
1726 | SUBREG_REG (operand) = new_reg; | |
1727 | lra_process_new_insns (curr_insn, before, after, | |
1728 | "Inserting subreg reload"); | |
1729 | return true; | |
1730 | } | |
4f0bee4c WM |
1731 | /* Force a reload for a paradoxical subreg. For paradoxical subreg, |
1732 | IRA allocates hardreg to the inner pseudo reg according to its mode | |
1733 | instead of the outermode, so the size of the hardreg may not be enough | |
1734 | to contain the outermode operand, in that case we may need to insert | |
1735 | reload for the reg. For the following two types of paradoxical subreg, | |
1736 | we need to insert reload: | |
1737 | 1. If the op_type is OP_IN, and the hardreg could not be paired with | |
1738 | other hardreg to contain the outermode operand | |
1739 | (checked by in_hard_reg_set_p), we need to insert the reload. | |
1740 | 2. If the op_type is OP_OUT or OP_INOUT. | |
1741 | ||
1742 | Here is a paradoxical subreg example showing how the reload is generated: | |
1743 | ||
1744 | (insn 5 4 7 2 (set (reg:TI 106 [ __comp ]) | |
1745 | (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64} | |
1746 | ||
1747 | In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example | |
1748 | here, if reg107 is assigned to hardreg R15, because R15 is the last | |
1749 | hardreg, compiler cannot find another hardreg to pair with R15 to | |
1750 | contain TImode data. So we insert a TImode reload reg180 for it. | |
1751 | After reload is inserted: | |
1752 | ||
1753 | (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0) | |
1754 | (reg:DI 107 [ __comp ])) -1 | |
1755 | (insn 5 4 7 2 (set (reg:TI 106 [ __comp ]) | |
1756 | (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64} | |
1757 | ||
1758 | Two reload hard registers will be allocated to reg180 to save TImode data | |
8fd96632 RS |
1759 | in LRA_assign. |
1760 | ||
1761 | For LRA pseudos this should normally be handled by the biggest_mode | |
1762 | mechanism. However, it's possible for new uses of an LRA pseudo | |
1763 | to be introduced after we've allocated it, such as when undoing | |
1764 | inheritance, and the allocated register might not then be appropriate | |
1765 | for the new uses. */ | |
4f0bee4c WM |
1766 | else if (REG_P (reg) |
1767 | && REGNO (reg) >= FIRST_PSEUDO_REGISTER | |
497498c8 RS |
1768 | && paradoxical_subreg_p (operand) |
1769 | && (inner_hard_regno = lra_get_regno_hard_regno (REGNO (reg))) >= 0 | |
1770 | && ((hard_regno | |
1771 | = simplify_subreg_regno (inner_hard_regno, innermode, | |
1772 | SUBREG_BYTE (operand), mode)) < 0 | |
1773 | || ((hard_regno_nregs (inner_hard_regno, innermode) | |
1774 | < hard_regno_nregs (hard_regno, mode)) | |
1775 | && (regclass = lra_get_allocno_class (REGNO (reg))) | |
1776 | && (type != OP_IN | |
1777 | || !in_hard_reg_set_p (reg_class_contents[regclass], | |
1778 | mode, hard_regno) | |
1779 | || overlaps_hard_reg_set_p (lra_no_alloc_regs, | |
1780 | mode, hard_regno))))) | |
4f0bee4c WM |
1781 | { |
1782 | /* The class will be defined later in curr_insn_transform. */ | |
1783 | enum reg_class rclass | |
1784 | = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS); | |
1785 | ||
1786 | if (get_reload_reg (curr_static_id->operand[nop].type, mode, reg, | |
95921002 | 1787 | rclass, TRUE, "paradoxical subreg", &new_reg)) |
4f0bee4c WM |
1788 | { |
1789 | rtx subreg; | |
1790 | bool insert_before, insert_after; | |
1791 | ||
1792 | PUT_MODE (new_reg, mode); | |
ea09f50d | 1793 | subreg = gen_lowpart_SUBREG (innermode, new_reg); |
4f0bee4c WM |
1794 | bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg)); |
1795 | ||
1796 | insert_before = (type != OP_OUT); | |
1797 | insert_after = (type != OP_IN); | |
1798 | insert_move_for_subreg (insert_before ? &before : NULL, | |
1799 | insert_after ? &after : NULL, | |
1800 | reg, subreg); | |
1801 | } | |
1802 | SUBREG_REG (operand) = new_reg; | |
1803 | lra_process_new_insns (curr_insn, before, after, | |
1804 | "Inserting paradoxical subreg reload"); | |
1805 | return true; | |
1806 | } | |
55a2c322 VM |
1807 | return false; |
1808 | } | |
1809 | ||
1810 | /* Return TRUE if X refers for a hard register from SET. */ | |
1811 | static bool | |
1812 | uses_hard_regs_p (rtx x, HARD_REG_SET set) | |
1813 | { | |
1814 | int i, j, x_hard_regno; | |
ef4bddc2 | 1815 | machine_mode mode; |
55a2c322 VM |
1816 | const char *fmt; |
1817 | enum rtx_code code; | |
1818 | ||
1819 | if (x == NULL_RTX) | |
1820 | return false; | |
1821 | code = GET_CODE (x); | |
1822 | mode = GET_MODE (x); | |
145d4e1a | 1823 | |
55a2c322 VM |
1824 | if (code == SUBREG) |
1825 | { | |
145d4e1a AV |
1826 | /* For all SUBREGs we want to check whether the full multi-register |
1827 | overlaps the set. For normal SUBREGs this means 'get_hard_regno' of | |
1828 | the inner register, for paradoxical SUBREGs this means the | |
1829 | 'get_hard_regno' of the full SUBREG and for complete SUBREGs either is | |
1830 | fine. Use the wider mode for all cases. */ | |
1831 | rtx subreg = SUBREG_REG (x); | |
bd5a2c67 | 1832 | mode = wider_subreg_mode (x); |
145d4e1a AV |
1833 | if (mode == GET_MODE (subreg)) |
1834 | { | |
1835 | x = subreg; | |
1836 | code = GET_CODE (x); | |
1837 | } | |
55a2c322 | 1838 | } |
f4eafc30 | 1839 | |
145d4e1a | 1840 | if (REG_P (x) || SUBREG_P (x)) |
55a2c322 | 1841 | { |
1686923c | 1842 | x_hard_regno = get_hard_regno (x, true); |
55a2c322 VM |
1843 | return (x_hard_regno >= 0 |
1844 | && overlaps_hard_reg_set_p (set, mode, x_hard_regno)); | |
1845 | } | |
1846 | if (MEM_P (x)) | |
1847 | { | |
277f65de | 1848 | struct address_info ad; |
55a2c322 | 1849 | |
277f65de RS |
1850 | decompose_mem_address (&ad, x); |
1851 | if (ad.base_term != NULL && uses_hard_regs_p (*ad.base_term, set)) | |
1852 | return true; | |
1853 | if (ad.index_term != NULL && uses_hard_regs_p (*ad.index_term, set)) | |
1854 | return true; | |
55a2c322 VM |
1855 | } |
1856 | fmt = GET_RTX_FORMAT (code); | |
1857 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1858 | { | |
1859 | if (fmt[i] == 'e') | |
1860 | { | |
1861 | if (uses_hard_regs_p (XEXP (x, i), set)) | |
1862 | return true; | |
1863 | } | |
1864 | else if (fmt[i] == 'E') | |
1865 | { | |
1866 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
1867 | if (uses_hard_regs_p (XVECEXP (x, i, j), set)) | |
1868 | return true; | |
1869 | } | |
1870 | } | |
1871 | return false; | |
1872 | } | |
1873 | ||
1874 | /* Return true if OP is a spilled pseudo. */ | |
1875 | static inline bool | |
1876 | spilled_pseudo_p (rtx op) | |
1877 | { | |
1878 | return (REG_P (op) | |
1879 | && REGNO (op) >= FIRST_PSEUDO_REGISTER && in_mem_p (REGNO (op))); | |
1880 | } | |
1881 | ||
1882 | /* Return true if X is a general constant. */ | |
1883 | static inline bool | |
1884 | general_constant_p (rtx x) | |
1885 | { | |
1886 | return CONSTANT_P (x) && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (x)); | |
1887 | } | |
1888 | ||
2c62cbaa VM |
1889 | static bool |
1890 | reg_in_class_p (rtx reg, enum reg_class cl) | |
1891 | { | |
1892 | if (cl == NO_REGS) | |
1893 | return get_reg_class (REGNO (reg)) == NO_REGS; | |
1894 | return in_class_p (reg, cl, NULL); | |
1895 | } | |
1896 | ||
3c954213 VM |
1897 | /* Return true if SET of RCLASS contains no hard regs which can be |
1898 | used in MODE. */ | |
1899 | static bool | |
1900 | prohibited_class_reg_set_mode_p (enum reg_class rclass, | |
1901 | HARD_REG_SET &set, | |
b8506a8a | 1902 | machine_mode mode) |
3c954213 VM |
1903 | { |
1904 | HARD_REG_SET temp; | |
1905 | ||
c07ad89a | 1906 | lra_assert (hard_reg_set_subset_p (reg_class_contents[rclass], set)); |
d15e5131 | 1907 | temp = set & ~lra_no_alloc_regs; |
3c954213 VM |
1908 | return (hard_reg_set_subset_p |
1909 | (temp, ira_prohibited_class_mode_regs[rclass][mode])); | |
1910 | } | |
1911 | ||
9b195552 VM |
1912 | |
1913 | /* Used to check validity info about small class input operands. It | |
1914 | should be incremented at start of processing an insn | |
1915 | alternative. */ | |
1916 | static unsigned int curr_small_class_check = 0; | |
1917 | ||
a25f3e8e RS |
1918 | /* Update number of used inputs of class OP_CLASS for operand NOP |
1919 | of alternative NALT. Return true if we have more such class operands | |
1920 | than the number of available regs. */ | |
9b195552 | 1921 | static bool |
a25f3e8e RS |
1922 | update_and_check_small_class_inputs (int nop, int nalt, |
1923 | enum reg_class op_class) | |
9b195552 VM |
1924 | { |
1925 | static unsigned int small_class_check[LIM_REG_CLASSES]; | |
1926 | static int small_class_input_nums[LIM_REG_CLASSES]; | |
1927 | ||
1928 | if (SMALL_REGISTER_CLASS_P (op_class) | |
1929 | /* We are interesting in classes became small because of fixing | |
1930 | some hard regs, e.g. by an user through GCC options. */ | |
1931 | && hard_reg_set_intersect_p (reg_class_contents[op_class], | |
1932 | ira_no_alloc_regs) | |
1933 | && (curr_static_id->operand[nop].type != OP_OUT | |
a25f3e8e | 1934 | || TEST_BIT (curr_static_id->operand[nop].early_clobber_alts, nalt))) |
9b195552 VM |
1935 | { |
1936 | if (small_class_check[op_class] == curr_small_class_check) | |
1937 | small_class_input_nums[op_class]++; | |
1938 | else | |
1939 | { | |
1940 | small_class_check[op_class] = curr_small_class_check; | |
1941 | small_class_input_nums[op_class] = 1; | |
1942 | } | |
1943 | if (small_class_input_nums[op_class] > ira_class_hard_regs_num[op_class]) | |
1944 | return true; | |
1945 | } | |
1946 | return false; | |
1947 | } | |
1948 | ||
55a2c322 VM |
1949 | /* Major function to choose the current insn alternative and what |
1950 | operands should be reloaded and how. If ONLY_ALTERNATIVE is not | |
1951 | negative we should consider only this alternative. Return false if | |
67914693 | 1952 | we cannot choose the alternative or find how to reload the |
55a2c322 VM |
1953 | operands. */ |
1954 | static bool | |
1955 | process_alt_operands (int only_alternative) | |
1956 | { | |
1957 | bool ok_p = false; | |
36ff9dfb | 1958 | int nop, overall, nalt; |
55a2c322 VM |
1959 | int n_alternatives = curr_static_id->n_alternatives; |
1960 | int n_operands = curr_static_id->n_operands; | |
1961 | /* LOSERS counts the operands that don't fit this alternative and | |
1962 | would require loading. */ | |
1963 | int losers; | |
feca7b89 | 1964 | int addr_losers; |
55a2c322 VM |
1965 | /* REJECT is a count of how undesirable this alternative says it is |
1966 | if any reloading is required. If the alternative matches exactly | |
1967 | then REJECT is ignored, but otherwise it gets this much counted | |
1968 | against it in addition to the reloading needed. */ | |
1969 | int reject; | |
feca7b89 VM |
1970 | /* This is defined by '!' or '?' alternative constraint and added to |
1971 | reject. But in some cases it can be ignored. */ | |
1972 | int static_reject; | |
d1457701 | 1973 | int op_reject; |
55a2c322 VM |
1974 | /* The number of elements in the following array. */ |
1975 | int early_clobbered_regs_num; | |
1976 | /* Numbers of operands which are early clobber registers. */ | |
1977 | int early_clobbered_nops[MAX_RECOG_OPERANDS]; | |
1978 | enum reg_class curr_alt[MAX_RECOG_OPERANDS]; | |
1979 | HARD_REG_SET curr_alt_set[MAX_RECOG_OPERANDS]; | |
1980 | bool curr_alt_match_win[MAX_RECOG_OPERANDS]; | |
1981 | bool curr_alt_win[MAX_RECOG_OPERANDS]; | |
1982 | bool curr_alt_offmemok[MAX_RECOG_OPERANDS]; | |
1983 | int curr_alt_matches[MAX_RECOG_OPERANDS]; | |
1984 | /* The number of elements in the following array. */ | |
1985 | int curr_alt_dont_inherit_ops_num; | |
1986 | /* Numbers of operands whose reload pseudos should not be inherited. */ | |
1987 | int curr_alt_dont_inherit_ops[MAX_RECOG_OPERANDS]; | |
1988 | rtx op; | |
1989 | /* The register when the operand is a subreg of register, otherwise the | |
1990 | operand itself. */ | |
1991 | rtx no_subreg_reg_operand[MAX_RECOG_OPERANDS]; | |
1992 | /* The register if the operand is a register or subreg of register, | |
1993 | otherwise NULL. */ | |
1994 | rtx operand_reg[MAX_RECOG_OPERANDS]; | |
1995 | int hard_regno[MAX_RECOG_OPERANDS]; | |
ef4bddc2 | 1996 | machine_mode biggest_mode[MAX_RECOG_OPERANDS]; |
55a2c322 VM |
1997 | int reload_nregs, reload_sum; |
1998 | bool costly_p; | |
1999 | enum reg_class cl; | |
2000 | ||
2001 | /* Calculate some data common for all alternatives to speed up the | |
2002 | function. */ | |
2003 | for (nop = 0; nop < n_operands; nop++) | |
2004 | { | |
7214306b VM |
2005 | rtx reg; |
2006 | ||
55a2c322 VM |
2007 | op = no_subreg_reg_operand[nop] = *curr_id->operand_loc[nop]; |
2008 | /* The real hard regno of the operand after the allocation. */ | |
1686923c | 2009 | hard_regno[nop] = get_hard_regno (op, true); |
f4eafc30 | 2010 | |
7214306b VM |
2011 | operand_reg[nop] = reg = op; |
2012 | biggest_mode[nop] = GET_MODE (op); | |
2013 | if (GET_CODE (op) == SUBREG) | |
55a2c322 | 2014 | { |
bd5a2c67 | 2015 | biggest_mode[nop] = wider_subreg_mode (op); |
7214306b | 2016 | operand_reg[nop] = reg = SUBREG_REG (op); |
55a2c322 | 2017 | } |
7214306b | 2018 | if (! REG_P (reg)) |
55a2c322 | 2019 | operand_reg[nop] = NULL_RTX; |
7214306b VM |
2020 | else if (REGNO (reg) >= FIRST_PSEUDO_REGISTER |
2021 | || ((int) REGNO (reg) | |
2022 | == lra_get_elimination_hard_regno (REGNO (reg)))) | |
2023 | no_subreg_reg_operand[nop] = reg; | |
2024 | else | |
2025 | operand_reg[nop] = no_subreg_reg_operand[nop] | |
2026 | /* Just use natural mode for elimination result. It should | |
2027 | be enough for extra constraints hooks. */ | |
2028 | = regno_reg_rtx[hard_regno[nop]]; | |
55a2c322 VM |
2029 | } |
2030 | ||
2031 | /* The constraints are made of several alternatives. Each operand's | |
2032 | constraint looks like foo,bar,... with commas separating the | |
2033 | alternatives. The first alternatives for all operands go | |
2034 | together, the second alternatives go together, etc. | |
2035 | ||
2036 | First loop over alternatives. */ | |
9840b2fa | 2037 | alternative_mask preferred = curr_id->preferred_alternatives; |
4cc8d9d2 | 2038 | if (only_alternative >= 0) |
9840b2fa | 2039 | preferred &= ALTERNATIVE_BIT (only_alternative); |
4cc8d9d2 | 2040 | |
55a2c322 VM |
2041 | for (nalt = 0; nalt < n_alternatives; nalt++) |
2042 | { | |
2043 | /* Loop over operands for one constraint alternative. */ | |
9840b2fa | 2044 | if (!TEST_BIT (preferred, nalt)) |
55a2c322 VM |
2045 | continue; |
2046 | ||
dbe7895c | 2047 | bool matching_early_clobber[MAX_RECOG_OPERANDS]; |
9b195552 | 2048 | curr_small_class_check++; |
feca7b89 VM |
2049 | overall = losers = addr_losers = 0; |
2050 | static_reject = reject = reload_nregs = reload_sum = 0; | |
55a2c322 | 2051 | for (nop = 0; nop < n_operands; nop++) |
cb1cca12 VM |
2052 | { |
2053 | int inc = (curr_static_id | |
2054 | ->operand_alternative[nalt * n_operands + nop].reject); | |
2055 | if (lra_dump_file != NULL && inc != 0) | |
2056 | fprintf (lra_dump_file, | |
2057 | " Staticly defined alt reject+=%d\n", inc); | |
feca7b89 | 2058 | static_reject += inc; |
dbe7895c | 2059 | matching_early_clobber[nop] = 0; |
cb1cca12 | 2060 | } |
feca7b89 | 2061 | reject += static_reject; |
55a2c322 VM |
2062 | early_clobbered_regs_num = 0; |
2063 | ||
2064 | for (nop = 0; nop < n_operands; nop++) | |
2065 | { | |
2066 | const char *p; | |
2067 | char *end; | |
2068 | int len, c, m, i, opalt_num, this_alternative_matches; | |
2069 | bool win, did_match, offmemok, early_clobber_p; | |
2070 | /* false => this operand can be reloaded somehow for this | |
2071 | alternative. */ | |
2072 | bool badop; | |
2073 | /* true => this operand can be reloaded if the alternative | |
2074 | allows regs. */ | |
2075 | bool winreg; | |
2076 | /* True if a constant forced into memory would be OK for | |
2077 | this operand. */ | |
2078 | bool constmemok; | |
2079 | enum reg_class this_alternative, this_costly_alternative; | |
2080 | HARD_REG_SET this_alternative_set, this_costly_alternative_set; | |
2081 | bool this_alternative_match_win, this_alternative_win; | |
2082 | bool this_alternative_offmemok; | |
80f466c4 | 2083 | bool scratch_p; |
ef4bddc2 | 2084 | machine_mode mode; |
777e635f | 2085 | enum constraint_num cn; |
55a2c322 VM |
2086 | |
2087 | opalt_num = nalt * n_operands + nop; | |
2088 | if (curr_static_id->operand_alternative[opalt_num].anything_ok) | |
2089 | { | |
2090 | /* Fast track for no constraints at all. */ | |
2091 | curr_alt[nop] = NO_REGS; | |
2092 | CLEAR_HARD_REG_SET (curr_alt_set[nop]); | |
2093 | curr_alt_win[nop] = true; | |
2094 | curr_alt_match_win[nop] = false; | |
2095 | curr_alt_offmemok[nop] = false; | |
2096 | curr_alt_matches[nop] = -1; | |
2097 | continue; | |
2098 | } | |
f4eafc30 | 2099 | |
55a2c322 VM |
2100 | op = no_subreg_reg_operand[nop]; |
2101 | mode = curr_operand_mode[nop]; | |
2102 | ||
2103 | win = did_match = winreg = offmemok = constmemok = false; | |
2104 | badop = true; | |
f4eafc30 | 2105 | |
55a2c322 VM |
2106 | early_clobber_p = false; |
2107 | p = curr_static_id->operand_alternative[opalt_num].constraint; | |
f4eafc30 | 2108 | |
55a2c322 VM |
2109 | this_costly_alternative = this_alternative = NO_REGS; |
2110 | /* We update set of possible hard regs besides its class | |
2111 | because reg class might be inaccurate. For example, | |
2112 | union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM | |
2113 | is translated in HI_REGS because classes are merged by | |
2114 | pairs and there is no accurate intermediate class. */ | |
2115 | CLEAR_HARD_REG_SET (this_alternative_set); | |
2116 | CLEAR_HARD_REG_SET (this_costly_alternative_set); | |
2117 | this_alternative_win = false; | |
2118 | this_alternative_match_win = false; | |
2119 | this_alternative_offmemok = false; | |
2120 | this_alternative_matches = -1; | |
f4eafc30 | 2121 | |
55a2c322 VM |
2122 | /* An empty constraint should be excluded by the fast |
2123 | track. */ | |
2124 | lra_assert (*p != 0 && *p != ','); | |
f4eafc30 | 2125 | |
d1457701 | 2126 | op_reject = 0; |
55a2c322 VM |
2127 | /* Scan this alternative's specs for this operand; set WIN |
2128 | if the operand fits any letter in this alternative. | |
2129 | Otherwise, clear BADOP if this operand could fit some | |
2130 | letter after reloads, or set WINREG if this operand could | |
2131 | fit after reloads provided the constraint allows some | |
2132 | registers. */ | |
2133 | costly_p = false; | |
2134 | do | |
2135 | { | |
2136 | switch ((c = *p, len = CONSTRAINT_LEN (c, p)), c) | |
2137 | { | |
2138 | case '\0': | |
2139 | len = 0; | |
2140 | break; | |
2141 | case ',': | |
2142 | c = '\0'; | |
2143 | break; | |
f4eafc30 | 2144 | |
55a2c322 VM |
2145 | case '&': |
2146 | early_clobber_p = true; | |
2147 | break; | |
f4eafc30 | 2148 | |
d1457701 VM |
2149 | case '$': |
2150 | op_reject += LRA_MAX_REJECT; | |
2151 | break; | |
2152 | case '^': | |
2153 | op_reject += LRA_LOSER_COST_FACTOR; | |
2154 | break; | |
2155 | ||
55a2c322 VM |
2156 | case '#': |
2157 | /* Ignore rest of this alternative. */ | |
2158 | c = '\0'; | |
2159 | break; | |
f4eafc30 | 2160 | |
55a2c322 VM |
2161 | case '0': case '1': case '2': case '3': case '4': |
2162 | case '5': case '6': case '7': case '8': case '9': | |
2163 | { | |
2164 | int m_hregno; | |
2165 | bool match_p; | |
f4eafc30 | 2166 | |
55a2c322 VM |
2167 | m = strtoul (p, &end, 10); |
2168 | p = end; | |
2169 | len = 0; | |
2170 | lra_assert (nop > m); | |
f4eafc30 | 2171 | |
00224b1a RS |
2172 | /* Reject matches if we don't know which operand is |
2173 | bigger. This situation would arguably be a bug in | |
2174 | an .md pattern, but could also occur in a user asm. */ | |
2175 | if (!ordered_p (GET_MODE_SIZE (biggest_mode[m]), | |
2176 | GET_MODE_SIZE (biggest_mode[nop]))) | |
2177 | break; | |
2178 | ||
a426543a VM |
2179 | /* Don't match wrong asm insn operands for proper |
2180 | diagnostic later. */ | |
2181 | if (INSN_CODE (curr_insn) < 0 | |
2182 | && (curr_operand_mode[m] == BLKmode | |
2183 | || curr_operand_mode[nop] == BLKmode) | |
2184 | && curr_operand_mode[m] != curr_operand_mode[nop]) | |
2185 | break; | |
2186 | ||
1686923c | 2187 | m_hregno = get_hard_regno (*curr_id->operand_loc[m], false); |
55a2c322 VM |
2188 | /* We are supposed to match a previous operand. |
2189 | If we do, we win if that one did. If we do | |
2190 | not, count both of the operands as losers. | |
2191 | (This is too conservative, since most of the | |
2192 | time only a single reload insn will be needed | |
2193 | to make the two operands win. As a result, | |
2194 | this alternative may be rejected when it is | |
2195 | actually desirable.) */ | |
2196 | match_p = false; | |
2197 | if (operands_match_p (*curr_id->operand_loc[nop], | |
2198 | *curr_id->operand_loc[m], m_hregno)) | |
2199 | { | |
2200 | /* We should reject matching of an early | |
2201 | clobber operand if the matching operand is | |
2202 | not dying in the insn. */ | |
a25f3e8e RS |
2203 | if (!TEST_BIT (curr_static_id->operand[m] |
2204 | .early_clobber_alts, nalt) | |
55a2c322 VM |
2205 | || operand_reg[nop] == NULL_RTX |
2206 | || (find_regno_note (curr_insn, REG_DEAD, | |
1c86bd80 VM |
2207 | REGNO (op)) |
2208 | || REGNO (op) == REGNO (operand_reg[m]))) | |
55a2c322 VM |
2209 | match_p = true; |
2210 | } | |
2211 | if (match_p) | |
2212 | { | |
2213 | /* If we are matching a non-offsettable | |
2214 | address where an offsettable address was | |
2215 | expected, then we must reject this | |
2216 | combination, because we can't reload | |
2217 | it. */ | |
2218 | if (curr_alt_offmemok[m] | |
2219 | && MEM_P (*curr_id->operand_loc[m]) | |
2220 | && curr_alt[m] == NO_REGS && ! curr_alt_win[m]) | |
2221 | continue; | |
55a2c322 VM |
2222 | } |
2223 | else | |
2224 | { | |
9f41de41 VM |
2225 | /* If the operands do not match and one |
2226 | operand is INOUT, we can not match them. | |
2227 | Try other possibilities, e.g. other | |
2228 | alternatives or commutative operand | |
2229 | exchange. */ | |
2230 | if (curr_static_id->operand[nop].type == OP_INOUT | |
2231 | || curr_static_id->operand[m].type == OP_INOUT) | |
2232 | break; | |
2f0b80c7 | 2233 | /* Operands don't match. If the operands are |
613caed2 VM |
2234 | different user defined explicit hard |
2235 | registers, then we cannot make them match | |
2236 | when one is early clobber operand. */ | |
2f0b80c7 PB |
2237 | if ((REG_P (*curr_id->operand_loc[nop]) |
2238 | || SUBREG_P (*curr_id->operand_loc[nop])) | |
2239 | && (REG_P (*curr_id->operand_loc[m]) | |
2240 | || SUBREG_P (*curr_id->operand_loc[m]))) | |
2241 | { | |
2242 | rtx nop_reg = *curr_id->operand_loc[nop]; | |
2243 | if (SUBREG_P (nop_reg)) | |
2244 | nop_reg = SUBREG_REG (nop_reg); | |
2245 | rtx m_reg = *curr_id->operand_loc[m]; | |
2246 | if (SUBREG_P (m_reg)) | |
2247 | m_reg = SUBREG_REG (m_reg); | |
2248 | ||
2249 | if (REG_P (nop_reg) | |
2250 | && HARD_REGISTER_P (nop_reg) | |
2251 | && REG_USERVAR_P (nop_reg) | |
2252 | && REG_P (m_reg) | |
2253 | && HARD_REGISTER_P (m_reg) | |
2254 | && REG_USERVAR_P (m_reg)) | |
613caed2 VM |
2255 | { |
2256 | int i; | |
2257 | ||
2258 | for (i = 0; i < early_clobbered_regs_num; i++) | |
2259 | if (m == early_clobbered_nops[i]) | |
2260 | break; | |
2261 | if (i < early_clobbered_regs_num | |
2262 | || early_clobber_p) | |
2263 | break; | |
2264 | } | |
2f0b80c7 | 2265 | } |
2f0b80c7 PB |
2266 | /* Both operands must allow a reload register, |
2267 | otherwise we cannot make them match. */ | |
55a2c322 VM |
2268 | if (curr_alt[m] == NO_REGS) |
2269 | break; | |
2270 | /* Retroactively mark the operand we had to | |
2271 | match as a loser, if it wasn't already and | |
2272 | it wasn't matched to a register constraint | |
2273 | (e.g it might be matched by memory). */ | |
2274 | if (curr_alt_win[m] | |
2275 | && (operand_reg[m] == NULL_RTX | |
2276 | || hard_regno[m] < 0)) | |
2277 | { | |
2278 | losers++; | |
2279 | reload_nregs | |
2280 | += (ira_reg_class_max_nregs[curr_alt[m]] | |
2281 | [GET_MODE (*curr_id->operand_loc[m])]); | |
2282 | } | |
f4eafc30 | 2283 | |
f4581282 VM |
2284 | /* Prefer matching earlyclobber alternative as |
2285 | it results in less hard regs required for | |
2286 | the insn than a non-matching earlyclobber | |
2287 | alternative. */ | |
a25f3e8e RS |
2288 | if (TEST_BIT (curr_static_id->operand[m] |
2289 | .early_clobber_alts, nalt)) | |
f4581282 VM |
2290 | { |
2291 | if (lra_dump_file != NULL) | |
2292 | fprintf | |
2293 | (lra_dump_file, | |
2294 | " %d Matching earlyclobber alt:" | |
2295 | " reject--\n", | |
2296 | nop); | |
dbe7895c AS |
2297 | if (!matching_early_clobber[m]) |
2298 | { | |
2299 | reject--; | |
2300 | matching_early_clobber[m] = 1; | |
2301 | } | |
f4581282 VM |
2302 | } |
2303 | /* Otherwise we prefer no matching | |
2304 | alternatives because it gives more freedom | |
2305 | in RA. */ | |
2306 | else if (operand_reg[nop] == NULL_RTX | |
2307 | || (find_regno_note (curr_insn, REG_DEAD, | |
2308 | REGNO (operand_reg[nop])) | |
2309 | == NULL_RTX)) | |
cb1cca12 VM |
2310 | { |
2311 | if (lra_dump_file != NULL) | |
2312 | fprintf | |
2313 | (lra_dump_file, | |
2314 | " %d Matching alt: reject+=2\n", | |
2315 | nop); | |
2316 | reject += 2; | |
2317 | } | |
55a2c322 VM |
2318 | } |
2319 | /* If we have to reload this operand and some | |
2320 | previous operand also had to match the same | |
2321 | thing as this operand, we don't know how to do | |
2322 | that. */ | |
2323 | if (!match_p || !curr_alt_win[m]) | |
2324 | { | |
2325 | for (i = 0; i < nop; i++) | |
2326 | if (curr_alt_matches[i] == m) | |
2327 | break; | |
2328 | if (i < nop) | |
2329 | break; | |
2330 | } | |
2331 | else | |
2332 | did_match = true; | |
f4eafc30 | 2333 | |
28ed1460 | 2334 | this_alternative_matches = m; |
55a2c322 VM |
2335 | /* This can be fixed with reloads if the operand |
2336 | we are supposed to match can be fixed with | |
2337 | reloads. */ | |
2338 | badop = false; | |
2339 | this_alternative = curr_alt[m]; | |
6576d245 | 2340 | this_alternative_set = curr_alt_set[m]; |
821b7577 | 2341 | winreg = this_alternative != NO_REGS; |
55a2c322 VM |
2342 | break; |
2343 | } | |
f4eafc30 | 2344 | |
55a2c322 VM |
2345 | case 'g': |
2346 | if (MEM_P (op) | |
2347 | || general_constant_p (op) | |
2348 | || spilled_pseudo_p (op)) | |
2349 | win = true; | |
777e635f | 2350 | cl = GENERAL_REGS; |
55a2c322 | 2351 | goto reg; |
f4eafc30 | 2352 | |
55a2c322 | 2353 | default: |
777e635f RS |
2354 | cn = lookup_constraint (p); |
2355 | switch (get_constraint_type (cn)) | |
55a2c322 | 2356 | { |
777e635f RS |
2357 | case CT_REGISTER: |
2358 | cl = reg_class_for_constraint (cn); | |
2359 | if (cl != NO_REGS) | |
2360 | goto reg; | |
2361 | break; | |
f4eafc30 | 2362 | |
d9c35eee RS |
2363 | case CT_CONST_INT: |
2364 | if (CONST_INT_P (op) | |
2365 | && insn_const_int_ok_for_constraint (INTVAL (op), cn)) | |
2366 | win = true; | |
2367 | break; | |
2368 | ||
777e635f RS |
2369 | case CT_MEMORY: |
2370 | if (MEM_P (op) | |
2371 | && satisfies_memory_constraint_p (op, cn)) | |
2372 | win = true; | |
2373 | else if (spilled_pseudo_p (op)) | |
2374 | win = true; | |
2375 | ||
2376 | /* If we didn't already win, we can reload constants | |
2377 | via force_const_mem or put the pseudo value into | |
2378 | memory, or make other memory by reloading the | |
2379 | address like for 'o'. */ | |
2380 | if (CONST_POOL_OK_P (mode, op) | |
987b67f1 VM |
2381 | || MEM_P (op) || REG_P (op) |
2382 | /* We can restore the equiv insn by a | |
2383 | reload. */ | |
2384 | || equiv_substition_p[nop]) | |
777e635f RS |
2385 | badop = false; |
2386 | constmemok = true; | |
2387 | offmemok = true; | |
2388 | break; | |
2389 | ||
2390 | case CT_ADDRESS: | |
998fd141 AO |
2391 | /* An asm operand with an address constraint |
2392 | that doesn't satisfy address_operand has | |
2393 | is_address cleared, so that we don't try to | |
2394 | make a non-address fit. */ | |
2395 | if (!curr_static_id->operand[nop].is_address) | |
2396 | break; | |
777e635f RS |
2397 | /* If we didn't already win, we can reload the address |
2398 | into a base register. */ | |
2399 | if (satisfies_address_constraint_p (op, cn)) | |
2400 | win = true; | |
2401 | cl = base_reg_class (VOIDmode, ADDR_SPACE_GENERIC, | |
2402 | ADDRESS, SCRATCH); | |
2403 | badop = false; | |
2404 | goto reg; | |
2405 | ||
2406 | case CT_FIXED_FORM: | |
2407 | if (constraint_satisfied_p (op, cn)) | |
55a2c322 | 2408 | win = true; |
55a2c322 | 2409 | break; |
9eb1ca69 VM |
2410 | |
2411 | case CT_SPECIAL_MEMORY: | |
2412 | if (MEM_P (op) | |
2413 | && satisfies_memory_constraint_p (op, cn)) | |
2414 | win = true; | |
2415 | else if (spilled_pseudo_p (op)) | |
2416 | win = true; | |
2417 | break; | |
55a2c322 | 2418 | } |
777e635f | 2419 | break; |
f4eafc30 | 2420 | |
777e635f | 2421 | reg: |
a5b821e4 JJ |
2422 | if (mode == BLKmode) |
2423 | break; | |
55a2c322 | 2424 | this_alternative = reg_class_subunion[this_alternative][cl]; |
44942965 | 2425 | this_alternative_set |= reg_class_contents[cl]; |
55a2c322 VM |
2426 | if (costly_p) |
2427 | { | |
2428 | this_costly_alternative | |
2429 | = reg_class_subunion[this_costly_alternative][cl]; | |
44942965 | 2430 | this_costly_alternative_set |= reg_class_contents[cl]; |
55a2c322 | 2431 | } |
55a2c322 VM |
2432 | winreg = true; |
2433 | if (REG_P (op)) | |
2434 | { | |
2435 | if (hard_regno[nop] >= 0 | |
2436 | && in_hard_reg_set_p (this_alternative_set, | |
2437 | mode, hard_regno[nop])) | |
2438 | win = true; | |
2439 | else if (hard_regno[nop] < 0 | |
2440 | && in_class_p (op, this_alternative, NULL)) | |
2441 | win = true; | |
2442 | } | |
2443 | break; | |
2444 | } | |
2445 | if (c != ' ' && c != '\t') | |
2446 | costly_p = c == '*'; | |
2447 | } | |
2448 | while ((p += len), c); | |
f4eafc30 | 2449 | |
80f466c4 VM |
2450 | scratch_p = (operand_reg[nop] != NULL_RTX |
2451 | && lra_former_scratch_p (REGNO (operand_reg[nop]))); | |
55a2c322 VM |
2452 | /* Record which operands fit this alternative. */ |
2453 | if (win) | |
2454 | { | |
2455 | this_alternative_win = true; | |
2456 | if (operand_reg[nop] != NULL_RTX) | |
2457 | { | |
2458 | if (hard_regno[nop] >= 0) | |
2459 | { | |
2460 | if (in_hard_reg_set_p (this_costly_alternative_set, | |
2461 | mode, hard_regno[nop])) | |
cb1cca12 VM |
2462 | { |
2463 | if (lra_dump_file != NULL) | |
2464 | fprintf (lra_dump_file, | |
2465 | " %d Costly set: reject++\n", | |
2466 | nop); | |
2467 | reject++; | |
2468 | } | |
55a2c322 VM |
2469 | } |
2470 | else | |
2471 | { | |
80f466c4 VM |
2472 | /* Prefer won reg to spilled pseudo under other |
2473 | equal conditions for possibe inheritance. */ | |
2474 | if (! scratch_p) | |
2475 | { | |
2476 | if (lra_dump_file != NULL) | |
2477 | fprintf | |
2478 | (lra_dump_file, | |
2479 | " %d Non pseudo reload: reject++\n", | |
2480 | nop); | |
2481 | reject++; | |
2482 | } | |
55a2c322 VM |
2483 | if (in_class_p (operand_reg[nop], |
2484 | this_costly_alternative, NULL)) | |
cb1cca12 VM |
2485 | { |
2486 | if (lra_dump_file != NULL) | |
2487 | fprintf | |
2488 | (lra_dump_file, | |
2489 | " %d Non pseudo costly reload:" | |
2490 | " reject++\n", | |
2491 | nop); | |
2492 | reject++; | |
2493 | } | |
55a2c322 | 2494 | } |
9c582551 | 2495 | /* We simulate the behavior of old reload here. |
55a2c322 VM |
2496 | Although scratches need hard registers and it |
2497 | might result in spilling other pseudos, no reload | |
2498 | insns are generated for the scratches. So it | |
2499 | might cost something but probably less than old | |
2500 | reload pass believes. */ | |
80f466c4 | 2501 | if (scratch_p) |
cb1cca12 VM |
2502 | { |
2503 | if (lra_dump_file != NULL) | |
2504 | fprintf (lra_dump_file, | |
80f466c4 | 2505 | " %d Scratch win: reject+=2\n", |
cb1cca12 | 2506 | nop); |
80f466c4 | 2507 | reject += 2; |
cb1cca12 | 2508 | } |
55a2c322 VM |
2509 | } |
2510 | } | |
2511 | else if (did_match) | |
2512 | this_alternative_match_win = true; | |
2513 | else | |
2514 | { | |
2515 | int const_to_mem = 0; | |
2516 | bool no_regs_p; | |
2517 | ||
d1457701 | 2518 | reject += op_reject; |
8d49e7ef VM |
2519 | /* Never do output reload of stack pointer. It makes |
2520 | impossible to do elimination when SP is changed in | |
2521 | RTL. */ | |
2522 | if (op == stack_pointer_rtx && ! frame_pointer_needed | |
2523 | && curr_static_id->operand[nop].type != OP_IN) | |
2524 | goto fail; | |
2525 | ||
e86c0101 SB |
2526 | /* If this alternative asks for a specific reg class, see if there |
2527 | is at least one allocatable register in that class. */ | |
55a2c322 VM |
2528 | no_regs_p |
2529 | = (this_alternative == NO_REGS | |
2530 | || (hard_reg_set_subset_p | |
2531 | (reg_class_contents[this_alternative], | |
2532 | lra_no_alloc_regs))); | |
e86c0101 SB |
2533 | |
2534 | /* For asms, verify that the class for this alternative is possible | |
2535 | for the mode that is specified. */ | |
ecee672b | 2536 | if (!no_regs_p && INSN_CODE (curr_insn) < 0) |
e86c0101 SB |
2537 | { |
2538 | int i; | |
2539 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
f939c3e6 | 2540 | if (targetm.hard_regno_mode_ok (i, mode) |
8f21260c VM |
2541 | && in_hard_reg_set_p (reg_class_contents[this_alternative], |
2542 | mode, i)) | |
e86c0101 SB |
2543 | break; |
2544 | if (i == FIRST_PSEUDO_REGISTER) | |
2545 | winreg = false; | |
2546 | } | |
2547 | ||
55a2c322 VM |
2548 | /* If this operand accepts a register, and if the |
2549 | register class has at least one allocatable register, | |
2550 | then this operand can be reloaded. */ | |
2551 | if (winreg && !no_regs_p) | |
2552 | badop = false; | |
f4eafc30 | 2553 | |
55a2c322 | 2554 | if (badop) |
8f21260c VM |
2555 | { |
2556 | if (lra_dump_file != NULL) | |
2557 | fprintf (lra_dump_file, | |
2558 | " alt=%d: Bad operand -- refuse\n", | |
2559 | nalt); | |
2560 | goto fail; | |
2561 | } | |
55a2c322 | 2562 | |
d13835b6 VM |
2563 | if (this_alternative != NO_REGS) |
2564 | { | |
d15e5131 RS |
2565 | HARD_REG_SET available_regs |
2566 | = (reg_class_contents[this_alternative] | |
2567 | & ~((ira_prohibited_class_mode_regs | |
2568 | [this_alternative][mode]) | |
2569 | | lra_no_alloc_regs)); | |
d13835b6 VM |
2570 | if (hard_reg_set_empty_p (available_regs)) |
2571 | { | |
2572 | /* There are no hard regs holding a value of given | |
2573 | mode. */ | |
2574 | if (offmemok) | |
2575 | { | |
2576 | this_alternative = NO_REGS; | |
2577 | if (lra_dump_file != NULL) | |
2578 | fprintf (lra_dump_file, | |
2579 | " %d Using memory because of" | |
2580 | " a bad mode: reject+=2\n", | |
2581 | nop); | |
2582 | reject += 2; | |
2583 | } | |
2584 | else | |
2585 | { | |
2586 | if (lra_dump_file != NULL) | |
2587 | fprintf (lra_dump_file, | |
2588 | " alt=%d: Wrong mode -- refuse\n", | |
2589 | nalt); | |
2590 | goto fail; | |
2591 | } | |
2592 | } | |
2593 | } | |
2594 | ||
2ae577fd VM |
2595 | /* If not assigned pseudo has a class which a subset of |
2596 | required reg class, it is a less costly alternative | |
2597 | as the pseudo still can get a hard reg of necessary | |
2598 | class. */ | |
2599 | if (! no_regs_p && REG_P (op) && hard_regno[nop] < 0 | |
2600 | && (cl = get_reg_class (REGNO (op))) != NO_REGS | |
2601 | && ira_class_subset_p[this_alternative][cl]) | |
2602 | { | |
2603 | if (lra_dump_file != NULL) | |
2604 | fprintf | |
2605 | (lra_dump_file, | |
2606 | " %d Super set class reg: reject-=3\n", nop); | |
2607 | reject -= 3; | |
2608 | } | |
2609 | ||
55a2c322 VM |
2610 | this_alternative_offmemok = offmemok; |
2611 | if (this_costly_alternative != NO_REGS) | |
cb1cca12 VM |
2612 | { |
2613 | if (lra_dump_file != NULL) | |
2614 | fprintf (lra_dump_file, | |
2615 | " %d Costly loser: reject++\n", nop); | |
2616 | reject++; | |
2617 | } | |
55a2c322 VM |
2618 | /* If the operand is dying, has a matching constraint, |
2619 | and satisfies constraints of the matched operand | |
f4581282 | 2620 | which failed to satisfy the own constraints, most probably |
a9711f36 VM |
2621 | the reload for this operand will be gone. */ |
2622 | if (this_alternative_matches >= 0 | |
2623 | && !curr_alt_win[this_alternative_matches] | |
2624 | && REG_P (op) | |
2625 | && find_regno_note (curr_insn, REG_DEAD, REGNO (op)) | |
2626 | && (hard_regno[nop] >= 0 | |
2627 | ? in_hard_reg_set_p (this_alternative_set, | |
2628 | mode, hard_regno[nop]) | |
2629 | : in_class_p (op, this_alternative, NULL))) | |
2630 | { | |
2631 | if (lra_dump_file != NULL) | |
2632 | fprintf | |
2633 | (lra_dump_file, | |
2634 | " %d Dying matched operand reload: reject++\n", | |
2635 | nop); | |
2636 | reject++; | |
2637 | } | |
2638 | else | |
027ece11 | 2639 | { |
5306401f VM |
2640 | /* Strict_low_part requires to reload the register |
2641 | not the sub-register. In this case we should | |
2642 | check that a final reload hard reg can hold the | |
2643 | value mode. */ | |
027ece11 VM |
2644 | if (curr_static_id->operand[nop].strict_low |
2645 | && REG_P (op) | |
2646 | && hard_regno[nop] < 0 | |
2647 | && GET_CODE (*curr_id->operand_loc[nop]) == SUBREG | |
2648 | && ira_class_hard_regs_num[this_alternative] > 0 | |
f939c3e6 RS |
2649 | && (!targetm.hard_regno_mode_ok |
2650 | (ira_class_hard_regs[this_alternative][0], | |
2651 | GET_MODE (*curr_id->operand_loc[nop])))) | |
8f21260c VM |
2652 | { |
2653 | if (lra_dump_file != NULL) | |
2654 | fprintf | |
2655 | (lra_dump_file, | |
2656 | " alt=%d: Strict low subreg reload -- refuse\n", | |
2657 | nalt); | |
2658 | goto fail; | |
2659 | } | |
027ece11 VM |
2660 | losers++; |
2661 | } | |
55a2c322 VM |
2662 | if (operand_reg[nop] != NULL_RTX |
2663 | /* Output operands and matched input operands are | |
2664 | not inherited. The following conditions do not | |
2665 | exactly describe the previous statement but they | |
2666 | are pretty close. */ | |
2667 | && curr_static_id->operand[nop].type != OP_OUT | |
2668 | && (this_alternative_matches < 0 | |
2669 | || curr_static_id->operand[nop].type != OP_IN)) | |
2670 | { | |
2671 | int last_reload = (lra_reg_info[ORIGINAL_REGNO | |
2672 | (operand_reg[nop])] | |
2673 | .last_reload); | |
2674 | ||
6334f3e9 VM |
2675 | /* The value of reload_sum has sense only if we |
2676 | process insns in their order. It happens only on | |
2677 | the first constraints sub-pass when we do most of | |
2678 | reload work. */ | |
2679 | if (lra_constraint_iter == 1 && last_reload > bb_reload_num) | |
55a2c322 VM |
2680 | reload_sum += last_reload - bb_reload_num; |
2681 | } | |
2682 | /* If this is a constant that is reloaded into the | |
2683 | desired class by copying it to memory first, count | |
2684 | that as another reload. This is consistent with | |
2685 | other code and is required to avoid choosing another | |
2686 | alternative when the constant is moved into memory. | |
2687 | Note that the test here is precisely the same as in | |
2688 | the code below that calls force_const_mem. */ | |
2689 | if (CONST_POOL_OK_P (mode, op) | |
2690 | && ((targetm.preferred_reload_class | |
2691 | (op, this_alternative) == NO_REGS) | |
2692 | || no_input_reloads_p)) | |
2693 | { | |
2694 | const_to_mem = 1; | |
2695 | if (! no_regs_p) | |
2696 | losers++; | |
2697 | } | |
f4eafc30 | 2698 | |
55a2c322 VM |
2699 | /* Alternative loses if it requires a type of reload not |
2700 | permitted for this insn. We can always reload | |
2701 | objects with a REG_UNUSED note. */ | |
2702 | if ((curr_static_id->operand[nop].type != OP_IN | |
2703 | && no_output_reloads_p | |
2704 | && ! find_reg_note (curr_insn, REG_UNUSED, op)) | |
2705 | || (curr_static_id->operand[nop].type != OP_OUT | |
8f21260c VM |
2706 | && no_input_reloads_p && ! const_to_mem) |
2707 | || (this_alternative_matches >= 0 | |
9102dadd VM |
2708 | && (no_input_reloads_p |
2709 | || (no_output_reloads_p | |
2710 | && (curr_static_id->operand | |
2711 | [this_alternative_matches].type != OP_IN) | |
2712 | && ! find_reg_note (curr_insn, REG_UNUSED, | |
2713 | no_subreg_reg_operand | |
2714 | [this_alternative_matches]))))) | |
8f21260c VM |
2715 | { |
2716 | if (lra_dump_file != NULL) | |
2717 | fprintf | |
2718 | (lra_dump_file, | |
2719 | " alt=%d: No input/otput reload -- refuse\n", | |
2720 | nalt); | |
2721 | goto fail; | |
2722 | } | |
f4eafc30 | 2723 | |
67914693 | 2724 | /* Alternative loses if it required class pseudo cannot |
f66af4aa | 2725 | hold value of required mode. Such insns can be |
7b6e0c54 | 2726 | described by insn definitions with mode iterators. */ |
f66af4aa VM |
2727 | if (GET_MODE (*curr_id->operand_loc[nop]) != VOIDmode |
2728 | && ! hard_reg_set_empty_p (this_alternative_set) | |
7b6e0c54 VM |
2729 | /* It is common practice for constraints to use a |
2730 | class which does not have actually enough regs to | |
2731 | hold the value (e.g. x86 AREG for mode requiring | |
2732 | more one general reg). Therefore we have 2 | |
155ed511 SL |
2733 | conditions to check that the reload pseudo cannot |
2734 | hold the mode value. */ | |
f939c3e6 RS |
2735 | && (!targetm.hard_regno_mode_ok |
2736 | (ira_class_hard_regs[this_alternative][0], | |
2737 | GET_MODE (*curr_id->operand_loc[nop]))) | |
7b6e0c54 VM |
2738 | /* The above condition is not enough as the first |
2739 | reg in ira_class_hard_regs can be not aligned for | |
2740 | multi-words mode values. */ | |
3c954213 VM |
2741 | && (prohibited_class_reg_set_mode_p |
2742 | (this_alternative, this_alternative_set, | |
2743 | GET_MODE (*curr_id->operand_loc[nop])))) | |
2744 | { | |
2745 | if (lra_dump_file != NULL) | |
2746 | fprintf (lra_dump_file, | |
2747 | " alt=%d: reload pseudo for op %d " | |
0d7bac69 | 2748 | "cannot hold the mode value -- refuse\n", |
3c954213 VM |
2749 | nalt, nop); |
2750 | goto fail; | |
f66af4aa VM |
2751 | } |
2752 | ||
821b7577 VM |
2753 | /* Check strong discouragement of reload of non-constant |
2754 | into class THIS_ALTERNATIVE. */ | |
2755 | if (! CONSTANT_P (op) && ! no_regs_p | |
2756 | && (targetm.preferred_reload_class | |
2757 | (op, this_alternative) == NO_REGS | |
2758 | || (curr_static_id->operand[nop].type == OP_OUT | |
2759 | && (targetm.preferred_output_reload_class | |
2760 | (op, this_alternative) == NO_REGS)))) | |
cb1cca12 | 2761 | { |
a8a728aa VM |
2762 | if (offmemok && REG_P (op)) |
2763 | { | |
2764 | if (lra_dump_file != NULL) | |
2765 | fprintf | |
2766 | (lra_dump_file, | |
2767 | " %d Spill pseudo into memory: reject+=3\n", | |
2768 | nop); | |
2769 | reject += 3; | |
2770 | } | |
2771 | else | |
2772 | { | |
2773 | if (lra_dump_file != NULL) | |
2774 | fprintf | |
2775 | (lra_dump_file, | |
2776 | " %d Non-prefered reload: reject+=%d\n", | |
2777 | nop, LRA_MAX_REJECT); | |
2778 | reject += LRA_MAX_REJECT; | |
2779 | } | |
cb1cca12 | 2780 | } |
f4eafc30 | 2781 | |
ed52a84e VM |
2782 | if (! (MEM_P (op) && offmemok) |
2783 | && ! (const_to_mem && constmemok)) | |
55a2c322 VM |
2784 | { |
2785 | /* We prefer to reload pseudos over reloading other | |
2786 | things, since such reloads may be able to be | |
2787 | eliminated later. So bump REJECT in other cases. | |
2788 | Don't do this in the case where we are forcing a | |
2789 | constant into memory and it will then win since | |
2790 | we don't want to have a different alternative | |
2791 | match then. */ | |
2792 | if (! (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER)) | |
cb1cca12 VM |
2793 | { |
2794 | if (lra_dump_file != NULL) | |
2795 | fprintf | |
2796 | (lra_dump_file, | |
2797 | " %d Non-pseudo reload: reject+=2\n", | |
2798 | nop); | |
2799 | reject += 2; | |
2800 | } | |
f4eafc30 | 2801 | |
55a2c322 VM |
2802 | if (! no_regs_p) |
2803 | reload_nregs | |
2804 | += ira_reg_class_max_nregs[this_alternative][mode]; | |
36ff9dfb VM |
2805 | |
2806 | if (SMALL_REGISTER_CLASS_P (this_alternative)) | |
cb1cca12 VM |
2807 | { |
2808 | if (lra_dump_file != NULL) | |
2809 | fprintf | |
2810 | (lra_dump_file, | |
2811 | " %d Small class reload: reject+=%d\n", | |
2812 | nop, LRA_LOSER_COST_FACTOR / 2); | |
2813 | reject += LRA_LOSER_COST_FACTOR / 2; | |
2814 | } | |
55a2c322 VM |
2815 | } |
2816 | ||
1bdc4b11 VM |
2817 | /* We are trying to spill pseudo into memory. It is |
2818 | usually more costly than moving to a hard register | |
2819 | although it might takes the same number of | |
5f225ef4 VM |
2820 | reloads. |
2821 | ||
2822 | Non-pseudo spill may happen also. Suppose a target allows both | |
2823 | register and memory in the operand constraint alternatives, | |
2824 | then it's typical that an eliminable register has a substition | |
2825 | of "base + offset" which can either be reloaded by a simple | |
2826 | "new_reg <= base + offset" which will match the register | |
2827 | constraint, or a similar reg addition followed by further spill | |
2828 | to and reload from memory which will match the memory | |
2829 | constraint, but this memory spill will be much more costly | |
2830 | usually. | |
2831 | ||
2832 | Code below increases the reject for both pseudo and non-pseudo | |
2833 | spill. */ | |
10406801 JW |
2834 | if (no_regs_p |
2835 | && !(MEM_P (op) && offmemok) | |
2836 | && !(REG_P (op) && hard_regno[nop] < 0)) | |
cb1cca12 VM |
2837 | { |
2838 | if (lra_dump_file != NULL) | |
2839 | fprintf | |
2840 | (lra_dump_file, | |
5f225ef4 VM |
2841 | " %d Spill %spseudo into memory: reject+=3\n", |
2842 | nop, REG_P (op) ? "" : "Non-"); | |
cb1cca12 | 2843 | reject += 3; |
7891065a VM |
2844 | if (VECTOR_MODE_P (mode)) |
2845 | { | |
2846 | /* Spilling vectors into memory is usually more | |
2847 | costly as they contain big values. */ | |
2848 | if (lra_dump_file != NULL) | |
2849 | fprintf | |
2850 | (lra_dump_file, | |
2851 | " %d Spill vector pseudo: reject+=2\n", | |
2852 | nop); | |
2853 | reject += 2; | |
2854 | } | |
cb1cca12 | 2855 | } |
1bdc4b11 | 2856 | |
4796d8f6 VM |
2857 | /* When we use an operand requiring memory in given |
2858 | alternative, the insn should write *and* read the | |
2859 | value to/from memory it is costly in comparison with | |
2860 | an insn alternative which does not use memory | |
2861 | (e.g. register or immediate operand). We exclude | |
2862 | memory operand for such case as we can satisfy the | |
2863 | memory constraints by reloading address. */ | |
2864 | if (no_regs_p && offmemok && !MEM_P (op)) | |
9b195552 VM |
2865 | { |
2866 | if (lra_dump_file != NULL) | |
2867 | fprintf | |
2868 | (lra_dump_file, | |
2869 | " Using memory insn operand %d: reject+=3\n", | |
2870 | nop); | |
2871 | reject += 3; | |
2872 | } | |
2873 | ||
7100b561 UB |
2874 | /* If reload requires moving value through secondary |
2875 | memory, it will need one more insn at least. */ | |
2876 | if (this_alternative != NO_REGS | |
2877 | && REG_P (op) && (cl = get_reg_class (REGNO (op))) != NO_REGS | |
2878 | && ((curr_static_id->operand[nop].type != OP_OUT | |
f15643d4 RS |
2879 | && targetm.secondary_memory_needed (GET_MODE (op), cl, |
2880 | this_alternative)) | |
7100b561 | 2881 | || (curr_static_id->operand[nop].type != OP_IN |
f15643d4 RS |
2882 | && (targetm.secondary_memory_needed |
2883 | (GET_MODE (op), this_alternative, cl))))) | |
7100b561 | 2884 | losers++; |
f15643d4 | 2885 | |
feca7b89 VM |
2886 | if (MEM_P (op) && offmemok) |
2887 | addr_losers++; | |
82396b8c | 2888 | else |
8b8e41e5 | 2889 | { |
82396b8c VM |
2890 | /* Input reloads can be inherited more often than |
2891 | output reloads can be removed, so penalize output | |
2892 | reloads. */ | |
2893 | if (!REG_P (op) || curr_static_id->operand[nop].type != OP_IN) | |
2894 | { | |
2895 | if (lra_dump_file != NULL) | |
2896 | fprintf | |
2897 | (lra_dump_file, | |
2898 | " %d Non input pseudo reload: reject++\n", | |
2899 | nop); | |
2900 | reject++; | |
2901 | } | |
2902 | ||
2903 | if (curr_static_id->operand[nop].type == OP_INOUT) | |
2904 | { | |
2905 | if (lra_dump_file != NULL) | |
2906 | fprintf | |
2907 | (lra_dump_file, | |
2908 | " %d Input/Output reload: reject+=%d\n", | |
2909 | nop, LRA_LOSER_COST_FACTOR); | |
2910 | reject += LRA_LOSER_COST_FACTOR; | |
2911 | } | |
8b8e41e5 | 2912 | } |
55a2c322 | 2913 | } |
f4eafc30 | 2914 | |
80f466c4 | 2915 | if (early_clobber_p && ! scratch_p) |
cb1cca12 VM |
2916 | { |
2917 | if (lra_dump_file != NULL) | |
2918 | fprintf (lra_dump_file, | |
2919 | " %d Early clobber: reject++\n", nop); | |
2920 | reject++; | |
2921 | } | |
55a2c322 VM |
2922 | /* ??? We check early clobbers after processing all operands |
2923 | (see loop below) and there we update the costs more. | |
2924 | Should we update the cost (may be approximately) here | |
2925 | because of early clobber register reloads or it is a rare | |
2926 | or non-important thing to be worth to do it. */ | |
feca7b89 VM |
2927 | overall = (losers * LRA_LOSER_COST_FACTOR + reject |
2928 | - (addr_losers == losers ? static_reject : 0)); | |
55a2c322 | 2929 | if ((best_losers == 0 || losers != 0) && best_overall < overall) |
deca73f5 VM |
2930 | { |
2931 | if (lra_dump_file != NULL) | |
2932 | fprintf (lra_dump_file, | |
cb1cca12 | 2933 | " alt=%d,overall=%d,losers=%d -- refuse\n", |
deca73f5 VM |
2934 | nalt, overall, losers); |
2935 | goto fail; | |
2936 | } | |
55a2c322 | 2937 | |
a25f3e8e RS |
2938 | if (update_and_check_small_class_inputs (nop, nalt, |
2939 | this_alternative)) | |
9b195552 VM |
2940 | { |
2941 | if (lra_dump_file != NULL) | |
2942 | fprintf (lra_dump_file, | |
2943 | " alt=%d, not enough small class regs -- refuse\n", | |
2944 | nalt); | |
2945 | goto fail; | |
2946 | } | |
55a2c322 | 2947 | curr_alt[nop] = this_alternative; |
6576d245 | 2948 | curr_alt_set[nop] = this_alternative_set; |
55a2c322 VM |
2949 | curr_alt_win[nop] = this_alternative_win; |
2950 | curr_alt_match_win[nop] = this_alternative_match_win; | |
2951 | curr_alt_offmemok[nop] = this_alternative_offmemok; | |
2952 | curr_alt_matches[nop] = this_alternative_matches; | |
f4eafc30 | 2953 | |
55a2c322 VM |
2954 | if (this_alternative_matches >= 0 |
2955 | && !did_match && !this_alternative_win) | |
2956 | curr_alt_win[this_alternative_matches] = false; | |
f4eafc30 | 2957 | |
55a2c322 VM |
2958 | if (early_clobber_p && operand_reg[nop] != NULL_RTX) |
2959 | early_clobbered_nops[early_clobbered_regs_num++] = nop; | |
2960 | } | |
feca7b89 | 2961 | |
2c62cbaa VM |
2962 | if (curr_insn_set != NULL_RTX && n_operands == 2 |
2963 | /* Prevent processing non-move insns. */ | |
2964 | && (GET_CODE (SET_SRC (curr_insn_set)) == SUBREG | |
2965 | || SET_SRC (curr_insn_set) == no_subreg_reg_operand[1]) | |
2966 | && ((! curr_alt_win[0] && ! curr_alt_win[1] | |
2967 | && REG_P (no_subreg_reg_operand[0]) | |
2968 | && REG_P (no_subreg_reg_operand[1]) | |
2969 | && (reg_in_class_p (no_subreg_reg_operand[0], curr_alt[1]) | |
2970 | || reg_in_class_p (no_subreg_reg_operand[1], curr_alt[0]))) | |
2971 | || (! curr_alt_win[0] && curr_alt_win[1] | |
2972 | && REG_P (no_subreg_reg_operand[1]) | |
feca7b89 VM |
2973 | /* Check that we reload memory not the memory |
2974 | address. */ | |
9125b9fc VM |
2975 | && ! (curr_alt_offmemok[0] |
2976 | && MEM_P (no_subreg_reg_operand[0])) | |
2c62cbaa VM |
2977 | && reg_in_class_p (no_subreg_reg_operand[1], curr_alt[0])) |
2978 | || (curr_alt_win[0] && ! curr_alt_win[1] | |
2979 | && REG_P (no_subreg_reg_operand[0]) | |
feca7b89 VM |
2980 | /* Check that we reload memory not the memory |
2981 | address. */ | |
9125b9fc VM |
2982 | && ! (curr_alt_offmemok[1] |
2983 | && MEM_P (no_subreg_reg_operand[1])) | |
2c62cbaa VM |
2984 | && reg_in_class_p (no_subreg_reg_operand[0], curr_alt[1]) |
2985 | && (! CONST_POOL_OK_P (curr_operand_mode[1], | |
2986 | no_subreg_reg_operand[1]) | |
2987 | || (targetm.preferred_reload_class | |
2988 | (no_subreg_reg_operand[1], | |
2989 | (enum reg_class) curr_alt[1]) != NO_REGS)) | |
2990 | /* If it is a result of recent elimination in move | |
2991 | insn we can transform it into an add still by | |
2992 | using this alternative. */ | |
b4c96972 RS |
2993 | && GET_CODE (no_subreg_reg_operand[1]) != PLUS |
2994 | /* Likewise if the source has been replaced with an | |
2995 | equivalent value. This only happens once -- the reload | |
2996 | will use the equivalent value instead of the register it | |
2997 | replaces -- so there should be no danger of cycling. */ | |
2998 | && !equiv_substition_p[1]))) | |
cb1cca12 VM |
2999 | { |
3000 | /* We have a move insn and a new reload insn will be similar | |
9125b9fc VM |
3001 | to the current insn. We should avoid such situation as |
3002 | it results in LRA cycling. */ | |
3003 | if (lra_dump_file != NULL) | |
3004 | fprintf (lra_dump_file, | |
3005 | " Cycle danger: overall += LRA_MAX_REJECT\n"); | |
cb1cca12 VM |
3006 | overall += LRA_MAX_REJECT; |
3007 | } | |
55a2c322 VM |
3008 | ok_p = true; |
3009 | curr_alt_dont_inherit_ops_num = 0; | |
3010 | for (nop = 0; nop < early_clobbered_regs_num; nop++) | |
3011 | { | |
2194f7a2 | 3012 | int i, j, clobbered_hard_regno, first_conflict_j, last_conflict_j; |
55a2c322 VM |
3013 | HARD_REG_SET temp_set; |
3014 | ||
3015 | i = early_clobbered_nops[nop]; | |
3016 | if ((! curr_alt_win[i] && ! curr_alt_match_win[i]) | |
3017 | || hard_regno[i] < 0) | |
3018 | continue; | |
1c86bd80 | 3019 | lra_assert (operand_reg[i] != NULL_RTX); |
55a2c322 VM |
3020 | clobbered_hard_regno = hard_regno[i]; |
3021 | CLEAR_HARD_REG_SET (temp_set); | |
3022 | add_to_hard_reg_set (&temp_set, biggest_mode[i], clobbered_hard_regno); | |
2194f7a2 | 3023 | first_conflict_j = last_conflict_j = -1; |
55a2c322 VM |
3024 | for (j = 0; j < n_operands; j++) |
3025 | if (j == i | |
3026 | /* We don't want process insides of match_operator and | |
3027 | match_parallel because otherwise we would process | |
3028 | their operands once again generating a wrong | |
3029 | code. */ | |
3030 | || curr_static_id->operand[j].is_operator) | |
3031 | continue; | |
3032 | else if ((curr_alt_matches[j] == i && curr_alt_match_win[j]) | |
3033 | || (curr_alt_matches[i] == j && curr_alt_match_win[i])) | |
3034 | continue; | |
1c86bd80 VM |
3035 | /* If we don't reload j-th operand, check conflicts. */ |
3036 | else if ((curr_alt_win[j] || curr_alt_match_win[j]) | |
3037 | && uses_hard_regs_p (*curr_id->operand_loc[j], temp_set)) | |
2194f7a2 VM |
3038 | { |
3039 | if (first_conflict_j < 0) | |
3040 | first_conflict_j = j; | |
3041 | last_conflict_j = j; | |
2f0b80c7 PB |
3042 | /* Both the earlyclobber operand and conflicting operand |
3043 | cannot both be user defined hard registers. */ | |
3044 | if (HARD_REGISTER_P (operand_reg[i]) | |
3045 | && REG_USERVAR_P (operand_reg[i]) | |
3046 | && operand_reg[j] != NULL_RTX | |
3047 | && HARD_REGISTER_P (operand_reg[j]) | |
3048 | && REG_USERVAR_P (operand_reg[j])) | |
3049 | fatal_insn ("unable to generate reloads for " | |
3050 | "impossible constraints:", curr_insn); | |
2194f7a2 VM |
3051 | } |
3052 | if (last_conflict_j < 0) | |
55a2c322 | 3053 | continue; |
2f0b80c7 PB |
3054 | |
3055 | /* If an earlyclobber operand conflicts with another non-matching | |
3056 | operand (ie, they have been assigned the same hard register), | |
3057 | then it is better to reload the other operand, as there may | |
3058 | exist yet another operand with a matching constraint associated | |
3059 | with the earlyclobber operand. However, if one of the operands | |
3060 | is an explicit use of a hard register, then we must reload the | |
3061 | other non-hard register operand. */ | |
3062 | if (HARD_REGISTER_P (operand_reg[i]) | |
3063 | || (first_conflict_j == last_conflict_j | |
3064 | && operand_reg[last_conflict_j] != NULL_RTX | |
3065 | && !curr_alt_match_win[last_conflict_j] | |
3066 | && !HARD_REGISTER_P (operand_reg[last_conflict_j]))) | |
1c86bd80 | 3067 | { |
2194f7a2 VM |
3068 | curr_alt_win[last_conflict_j] = false; |
3069 | curr_alt_dont_inherit_ops[curr_alt_dont_inherit_ops_num++] | |
3070 | = last_conflict_j; | |
1c86bd80 | 3071 | losers++; |
cb1cca12 VM |
3072 | if (lra_dump_file != NULL) |
3073 | fprintf | |
3074 | (lra_dump_file, | |
3075 | " %d Conflict early clobber reload: reject--\n", | |
3076 | i); | |
1c86bd80 | 3077 | } |
55a2c322 VM |
3078 | else |
3079 | { | |
1c86bd80 VM |
3080 | /* We need to reload early clobbered register and the |
3081 | matched registers. */ | |
3082 | for (j = 0; j < n_operands; j++) | |
3083 | if (curr_alt_matches[j] == i) | |
3084 | { | |
3085 | curr_alt_match_win[j] = false; | |
3086 | losers++; | |
3087 | overall += LRA_LOSER_COST_FACTOR; | |
3088 | } | |
3089 | if (! curr_alt_match_win[i]) | |
3090 | curr_alt_dont_inherit_ops[curr_alt_dont_inherit_ops_num++] = i; | |
3091 | else | |
3092 | { | |
3093 | /* Remember pseudos used for match reloads are never | |
3094 | inherited. */ | |
3095 | lra_assert (curr_alt_matches[i] >= 0); | |
3096 | curr_alt_win[curr_alt_matches[i]] = false; | |
3097 | } | |
3098 | curr_alt_win[i] = curr_alt_match_win[i] = false; | |
3099 | losers++; | |
cb1cca12 VM |
3100 | if (lra_dump_file != NULL) |
3101 | fprintf | |
3102 | (lra_dump_file, | |
aa326bfb | 3103 | " %d Matched conflict early clobber reloads: " |
cb1cca12 VM |
3104 | "reject--\n", |
3105 | i); | |
dbe7895c AS |
3106 | } |
3107 | /* Early clobber was already reflected in REJECT. */ | |
3108 | if (!matching_early_clobber[i]) | |
3109 | { | |
3110 | lra_assert (reject > 0); | |
deca73f5 | 3111 | reject--; |
dbe7895c | 3112 | matching_early_clobber[i] = 1; |
55a2c322 | 3113 | } |
dbe7895c | 3114 | overall += LRA_LOSER_COST_FACTOR - 1; |
55a2c322 | 3115 | } |
deca73f5 | 3116 | if (lra_dump_file != NULL) |
36ff9dfb VM |
3117 | fprintf (lra_dump_file, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n", |
3118 | nalt, overall, losers, reload_nregs); | |
deca73f5 | 3119 | |
55a2c322 VM |
3120 | /* If this alternative can be made to work by reloading, and it |
3121 | needs less reloading than the others checked so far, record | |
3122 | it as the chosen goal for reloading. */ | |
3123 | if ((best_losers != 0 && losers == 0) | |
3124 | || (((best_losers == 0 && losers == 0) | |
3125 | || (best_losers != 0 && losers != 0)) | |
3126 | && (best_overall > overall | |
3127 | || (best_overall == overall | |
3128 | /* If the cost of the reloads is the same, | |
3129 | prefer alternative which requires minimal | |
36ff9dfb VM |
3130 | number of reload regs. */ |
3131 | && (reload_nregs < best_reload_nregs | |
3132 | || (reload_nregs == best_reload_nregs | |
f15feaf9 VM |
3133 | && (best_reload_sum < reload_sum |
3134 | || (best_reload_sum == reload_sum | |
3135 | && nalt < goal_alt_number)))))))) | |
55a2c322 VM |
3136 | { |
3137 | for (nop = 0; nop < n_operands; nop++) | |
3138 | { | |
3139 | goal_alt_win[nop] = curr_alt_win[nop]; | |
3140 | goal_alt_match_win[nop] = curr_alt_match_win[nop]; | |
3141 | goal_alt_matches[nop] = curr_alt_matches[nop]; | |
3142 | goal_alt[nop] = curr_alt[nop]; | |
3143 | goal_alt_offmemok[nop] = curr_alt_offmemok[nop]; | |
3144 | } | |
3145 | goal_alt_dont_inherit_ops_num = curr_alt_dont_inherit_ops_num; | |
3146 | for (nop = 0; nop < curr_alt_dont_inherit_ops_num; nop++) | |
3147 | goal_alt_dont_inherit_ops[nop] = curr_alt_dont_inherit_ops[nop]; | |
3148 | goal_alt_swapped = curr_swapped; | |
3149 | best_overall = overall; | |
3150 | best_losers = losers; | |
55a2c322 VM |
3151 | best_reload_nregs = reload_nregs; |
3152 | best_reload_sum = reload_sum; | |
3153 | goal_alt_number = nalt; | |
3154 | } | |
3155 | if (losers == 0) | |
3156 | /* Everything is satisfied. Do not process alternatives | |
f4eafc30 | 3157 | anymore. */ |
55a2c322 VM |
3158 | break; |
3159 | fail: | |
3160 | ; | |
3161 | } | |
3162 | return ok_p; | |
3163 | } | |
3164 | ||
c31d2d11 RS |
3165 | /* Make reload base reg from address AD. */ |
3166 | static rtx | |
3167 | base_to_reg (struct address_info *ad) | |
3168 | { | |
3169 | enum reg_class cl; | |
3170 | int code = -1; | |
3171 | rtx new_inner = NULL_RTX; | |
3172 | rtx new_reg = NULL_RTX; | |
fee3e72c DM |
3173 | rtx_insn *insn; |
3174 | rtx_insn *last_insn = get_last_insn(); | |
c31d2d11 | 3175 | |
0a001dcb | 3176 | lra_assert (ad->disp == ad->disp_term); |
c31d2d11 RS |
3177 | cl = base_reg_class (ad->mode, ad->as, ad->base_outer_code, |
3178 | get_index_code (ad)); | |
0a001dcb | 3179 | new_reg = lra_create_new_reg (GET_MODE (*ad->base), NULL_RTX, |
c31d2d11 RS |
3180 | cl, "base"); |
3181 | new_inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), new_reg, | |
3182 | ad->disp_term == NULL | |
0a001dcb | 3183 | ? const0_rtx |
c31d2d11 RS |
3184 | : *ad->disp_term); |
3185 | if (!valid_address_p (ad->mode, new_inner, ad->as)) | |
3186 | return NULL_RTX; | |
0a001dcb | 3187 | insn = emit_insn (gen_rtx_SET (new_reg, *ad->base)); |
c31d2d11 RS |
3188 | code = recog_memoized (insn); |
3189 | if (code < 0) | |
3190 | { | |
3191 | delete_insns_since (last_insn); | |
3192 | return NULL_RTX; | |
3193 | } | |
3194 | ||
3195 | return new_inner; | |
3196 | } | |
3197 | ||
9005477f | 3198 | /* Make reload base reg + DISP from address AD. Return the new pseudo. */ |
55a2c322 | 3199 | static rtx |
9005477f | 3200 | base_plus_disp_to_reg (struct address_info *ad, rtx disp) |
55a2c322 VM |
3201 | { |
3202 | enum reg_class cl; | |
3203 | rtx new_reg; | |
3204 | ||
9005477f | 3205 | lra_assert (ad->base == ad->base_term); |
277f65de RS |
3206 | cl = base_reg_class (ad->mode, ad->as, ad->base_outer_code, |
3207 | get_index_code (ad)); | |
3208 | new_reg = lra_create_new_reg (GET_MODE (*ad->base_term), NULL_RTX, | |
3209 | cl, "base + disp"); | |
9005477f | 3210 | lra_emit_add (new_reg, *ad->base_term, disp); |
55a2c322 VM |
3211 | return new_reg; |
3212 | } | |
3213 | ||
6e071b1e VM |
3214 | /* Make reload of index part of address AD. Return the new |
3215 | pseudo. */ | |
3216 | static rtx | |
3217 | index_part_to_reg (struct address_info *ad) | |
3218 | { | |
3219 | rtx new_reg; | |
3220 | ||
3221 | new_reg = lra_create_new_reg (GET_MODE (*ad->index), NULL_RTX, | |
3222 | INDEX_REG_CLASS, "index term"); | |
3223 | expand_mult (GET_MODE (*ad->index), *ad->index_term, | |
3224 | GEN_INT (get_index_scale (ad)), new_reg, 1); | |
3225 | return new_reg; | |
3226 | } | |
3227 | ||
277f65de RS |
3228 | /* Return true if we can add a displacement to address AD, even if that |
3229 | makes the address invalid. The fix-up code requires any new address | |
3230 | to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */ | |
02ea4bf4 | 3231 | static bool |
277f65de | 3232 | can_add_disp_p (struct address_info *ad) |
02ea4bf4 | 3233 | { |
277f65de RS |
3234 | return (!ad->autoinc_p |
3235 | && ad->segment == NULL | |
3236 | && ad->base == ad->base_term | |
3237 | && ad->disp == ad->disp_term); | |
02ea4bf4 RS |
3238 | } |
3239 | ||
277f65de RS |
3240 | /* Make equiv substitution in address AD. Return true if a substitution |
3241 | was made. */ | |
55a2c322 | 3242 | static bool |
277f65de | 3243 | equiv_address_substitution (struct address_info *ad) |
55a2c322 | 3244 | { |
277f65de | 3245 | rtx base_reg, new_base_reg, index_reg, new_index_reg, *base_term, *index_term; |
73ca989c RS |
3246 | poly_int64 disp; |
3247 | HOST_WIDE_INT scale; | |
55a2c322 VM |
3248 | bool change_p; |
3249 | ||
277f65de RS |
3250 | base_term = strip_subreg (ad->base_term); |
3251 | if (base_term == NULL) | |
55a2c322 VM |
3252 | base_reg = new_base_reg = NULL_RTX; |
3253 | else | |
3254 | { | |
277f65de | 3255 | base_reg = *base_term; |
8d49e7ef | 3256 | new_base_reg = get_equiv_with_elimination (base_reg, curr_insn); |
55a2c322 | 3257 | } |
277f65de RS |
3258 | index_term = strip_subreg (ad->index_term); |
3259 | if (index_term == NULL) | |
55a2c322 VM |
3260 | index_reg = new_index_reg = NULL_RTX; |
3261 | else | |
3262 | { | |
277f65de | 3263 | index_reg = *index_term; |
8d49e7ef | 3264 | new_index_reg = get_equiv_with_elimination (index_reg, curr_insn); |
55a2c322 VM |
3265 | } |
3266 | if (base_reg == new_base_reg && index_reg == new_index_reg) | |
3267 | return false; | |
3268 | disp = 0; | |
3269 | change_p = false; | |
3270 | if (lra_dump_file != NULL) | |
3271 | { | |
3272 | fprintf (lra_dump_file, "Changing address in insn %d ", | |
3273 | INSN_UID (curr_insn)); | |
cfbeaedf | 3274 | dump_value_slim (lra_dump_file, *ad->outer, 1); |
55a2c322 VM |
3275 | } |
3276 | if (base_reg != new_base_reg) | |
3277 | { | |
73ca989c | 3278 | poly_int64 offset; |
55a2c322 VM |
3279 | if (REG_P (new_base_reg)) |
3280 | { | |
277f65de | 3281 | *base_term = new_base_reg; |
55a2c322 VM |
3282 | change_p = true; |
3283 | } | |
3284 | else if (GET_CODE (new_base_reg) == PLUS | |
3285 | && REG_P (XEXP (new_base_reg, 0)) | |
73ca989c | 3286 | && poly_int_rtx_p (XEXP (new_base_reg, 1), &offset) |
277f65de | 3287 | && can_add_disp_p (ad)) |
55a2c322 | 3288 | { |
73ca989c | 3289 | disp += offset; |
277f65de | 3290 | *base_term = XEXP (new_base_reg, 0); |
55a2c322 VM |
3291 | change_p = true; |
3292 | } | |
277f65de RS |
3293 | if (ad->base_term2 != NULL) |
3294 | *ad->base_term2 = *ad->base_term; | |
55a2c322 | 3295 | } |
55a2c322 VM |
3296 | if (index_reg != new_index_reg) |
3297 | { | |
73ca989c | 3298 | poly_int64 offset; |
55a2c322 VM |
3299 | if (REG_P (new_index_reg)) |
3300 | { | |
277f65de | 3301 | *index_term = new_index_reg; |
55a2c322 VM |
3302 | change_p = true; |
3303 | } | |
3304 | else if (GET_CODE (new_index_reg) == PLUS | |
3305 | && REG_P (XEXP (new_index_reg, 0)) | |
73ca989c | 3306 | && poly_int_rtx_p (XEXP (new_index_reg, 1), &offset) |
277f65de | 3307 | && can_add_disp_p (ad) |
02ea4bf4 | 3308 | && (scale = get_index_scale (ad))) |
55a2c322 | 3309 | { |
73ca989c | 3310 | disp += offset * scale; |
277f65de | 3311 | *index_term = XEXP (new_index_reg, 0); |
55a2c322 VM |
3312 | change_p = true; |
3313 | } | |
3314 | } | |
73ca989c | 3315 | if (maybe_ne (disp, 0)) |
55a2c322 | 3316 | { |
277f65de RS |
3317 | if (ad->disp != NULL) |
3318 | *ad->disp = plus_constant (GET_MODE (*ad->inner), *ad->disp, disp); | |
55a2c322 VM |
3319 | else |
3320 | { | |
277f65de RS |
3321 | *ad->inner = plus_constant (GET_MODE (*ad->inner), *ad->inner, disp); |
3322 | update_address (ad); | |
55a2c322 VM |
3323 | } |
3324 | change_p = true; | |
3325 | } | |
3326 | if (lra_dump_file != NULL) | |
3327 | { | |
3328 | if (! change_p) | |
3329 | fprintf (lra_dump_file, " -- no change\n"); | |
3330 | else | |
3331 | { | |
3332 | fprintf (lra_dump_file, " on equiv "); | |
cfbeaedf | 3333 | dump_value_slim (lra_dump_file, *ad->outer, 1); |
55a2c322 VM |
3334 | fprintf (lra_dump_file, "\n"); |
3335 | } | |
3336 | } | |
3337 | return change_p; | |
3338 | } | |
3339 | ||
d9cf932c VM |
3340 | /* Major function to make reloads for an address in operand NOP or |
3341 | check its correctness (If CHECK_ONLY_P is true). The supported | |
3342 | cases are: | |
bd3d34d4 | 3343 | |
5a107a0f VM |
3344 | 1) an address that existed before LRA started, at which point it |
3345 | must have been valid. These addresses are subject to elimination | |
3346 | and may have become invalid due to the elimination offset being out | |
3347 | of range. | |
bd3d34d4 | 3348 | |
5a107a0f VM |
3349 | 2) an address created by forcing a constant to memory |
3350 | (force_const_to_mem). The initial form of these addresses might | |
3351 | not be valid, and it is this function's job to make them valid. | |
bd3d34d4 RS |
3352 | |
3353 | 3) a frame address formed from a register and a (possibly zero) | |
5a107a0f VM |
3354 | constant offset. As above, these addresses might not be valid and |
3355 | this function must make them so. | |
bd3d34d4 RS |
3356 | |
3357 | Add reloads to the lists *BEFORE and *AFTER. We might need to add | |
55a2c322 | 3358 | reloads to *AFTER because of inc/dec, {pre, post} modify in the |
cc8849a1 VM |
3359 | address. Return true for any RTL change. |
3360 | ||
3361 | The function is a helper function which does not produce all | |
d9cf932c VM |
3362 | transformations (when CHECK_ONLY_P is false) which can be |
3363 | necessary. It does just basic steps. To do all necessary | |
3364 | transformations use function process_address. */ | |
55a2c322 | 3365 | static bool |
d9cf932c VM |
3366 | process_address_1 (int nop, bool check_only_p, |
3367 | rtx_insn **before, rtx_insn **after) | |
55a2c322 | 3368 | { |
277f65de RS |
3369 | struct address_info ad; |
3370 | rtx new_reg; | |
bc2fc1f3 | 3371 | HOST_WIDE_INT scale; |
55a2c322 VM |
3372 | rtx op = *curr_id->operand_loc[nop]; |
3373 | const char *constraint = curr_static_id->operand[nop].constraint; | |
777e635f | 3374 | enum constraint_num cn = lookup_constraint (constraint); |
d9cf932c | 3375 | bool change_p = false; |
55a2c322 | 3376 | |
823bb054 SB |
3377 | if (MEM_P (op) |
3378 | && GET_MODE (op) == BLKmode | |
3379 | && GET_CODE (XEXP (op, 0)) == SCRATCH) | |
3380 | return false; | |
3381 | ||
998fd141 AO |
3382 | if (insn_extra_address_constraint (cn) |
3383 | /* When we find an asm operand with an address constraint that | |
3384 | doesn't satisfy address_operand to begin with, we clear | |
3385 | is_address, so that we don't try to make a non-address fit. | |
3386 | If the asm statement got this far, it's because other | |
3387 | constraints are available, and we'll use them, disregarding | |
3388 | the unsatisfiable address ones. */ | |
3389 | && curr_static_id->operand[nop].is_address) | |
277f65de | 3390 | decompose_lea_address (&ad, curr_id->operand_loc[nop]); |
164f0634 EB |
3391 | /* Do not attempt to decompose arbitrary addresses generated by combine |
3392 | for asm operands with loose constraints, e.g 'X'. */ | |
3393 | else if (MEM_P (op) | |
a81a0bfa TP |
3394 | && !(INSN_CODE (curr_insn) < 0 |
3395 | && get_constraint_type (cn) == CT_FIXED_FORM | |
164f0634 | 3396 | && constraint_satisfied_p (op, cn))) |
277f65de | 3397 | decompose_mem_address (&ad, op); |
55a2c322 VM |
3398 | else if (GET_CODE (op) == SUBREG |
3399 | && MEM_P (SUBREG_REG (op))) | |
277f65de | 3400 | decompose_mem_address (&ad, SUBREG_REG (op)); |
55a2c322 VM |
3401 | else |
3402 | return false; | |
70712859 KK |
3403 | /* If INDEX_REG_CLASS is assigned to base_term already and isn't to |
3404 | index_term, swap them so to avoid assigning INDEX_REG_CLASS to both | |
3405 | when INDEX_REG_CLASS is a single register class. */ | |
3406 | if (ad.base_term != NULL | |
3407 | && ad.index_term != NULL | |
3408 | && ira_class_hard_regs_num[INDEX_REG_CLASS] == 1 | |
3409 | && REG_P (*ad.base_term) | |
3410 | && REG_P (*ad.index_term) | |
3411 | && in_class_p (*ad.base_term, INDEX_REG_CLASS, NULL) | |
3412 | && ! in_class_p (*ad.index_term, INDEX_REG_CLASS, NULL)) | |
3413 | { | |
3414 | std::swap (ad.base, ad.index); | |
3415 | std::swap (ad.base_term, ad.index_term); | |
3416 | } | |
d9cf932c VM |
3417 | if (! check_only_p) |
3418 | change_p = equiv_address_substitution (&ad); | |
277f65de | 3419 | if (ad.base_term != NULL |
55a2c322 | 3420 | && (process_addr_reg |
d9cf932c | 3421 | (ad.base_term, check_only_p, before, |
277f65de RS |
3422 | (ad.autoinc_p |
3423 | && !(REG_P (*ad.base_term) | |
3424 | && find_regno_note (curr_insn, REG_DEAD, | |
3425 | REGNO (*ad.base_term)) != NULL_RTX) | |
55a2c322 | 3426 | ? after : NULL), |
277f65de RS |
3427 | base_reg_class (ad.mode, ad.as, ad.base_outer_code, |
3428 | get_index_code (&ad))))) | |
55a2c322 VM |
3429 | { |
3430 | change_p = true; | |
277f65de RS |
3431 | if (ad.base_term2 != NULL) |
3432 | *ad.base_term2 = *ad.base_term; | |
55a2c322 | 3433 | } |
277f65de | 3434 | if (ad.index_term != NULL |
d9cf932c VM |
3435 | && process_addr_reg (ad.index_term, check_only_p, |
3436 | before, NULL, INDEX_REG_CLASS)) | |
55a2c322 VM |
3437 | change_p = true; |
3438 | ||
777e635f RS |
3439 | /* Target hooks sometimes don't treat extra-constraint addresses as |
3440 | legitimate address_operands, so handle them specially. */ | |
8677664e | 3441 | if (insn_extra_address_constraint (cn) |
777e635f | 3442 | && satisfies_address_constraint_p (&ad, cn)) |
2c62cbaa | 3443 | return change_p; |
2c62cbaa | 3444 | |
d9cf932c VM |
3445 | if (check_only_p) |
3446 | return change_p; | |
3447 | ||
277f65de | 3448 | /* There are three cases where the shape of *AD.INNER may now be invalid: |
bd3d34d4 RS |
3449 | |
3450 | 1) the original address was valid, but either elimination or | |
5a107a0f VM |
3451 | equiv_address_substitution was applied and that made |
3452 | the address invalid. | |
bd3d34d4 RS |
3453 | |
3454 | 2) the address is an invalid symbolic address created by | |
5a107a0f | 3455 | force_const_to_mem. |
bd3d34d4 RS |
3456 | |
3457 | 3) the address is a frame address with an invalid offset. | |
3458 | ||
c31d2d11 RS |
3459 | 4) the address is a frame address with an invalid base. |
3460 | ||
2c62cbaa VM |
3461 | All these cases involve a non-autoinc address, so there is no |
3462 | point revalidating other types. */ | |
1aeffdce | 3463 | if (ad.autoinc_p || valid_address_p (op, &ad, cn)) |
55a2c322 VM |
3464 | return change_p; |
3465 | ||
bd3d34d4 RS |
3466 | /* Any index existed before LRA started, so we can assume that the |
3467 | presence and shape of the index is valid. */ | |
55a2c322 | 3468 | push_to_sequence (*before); |
2c62cbaa | 3469 | lra_assert (ad.disp == ad.disp_term); |
277f65de | 3470 | if (ad.base == NULL) |
55a2c322 | 3471 | { |
277f65de | 3472 | if (ad.index == NULL) |
55a2c322 | 3473 | { |
95831c01 VM |
3474 | rtx_insn *insn; |
3475 | rtx_insn *last = get_last_insn (); | |
55a2c322 | 3476 | int code = -1; |
277f65de RS |
3477 | enum reg_class cl = base_reg_class (ad.mode, ad.as, |
3478 | SCRATCH, SCRATCH); | |
2c62cbaa | 3479 | rtx addr = *ad.inner; |
277f65de | 3480 | |
2c62cbaa | 3481 | new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "addr"); |
d0b2266a TS |
3482 | if (HAVE_lo_sum) |
3483 | { | |
d0b2266a TS |
3484 | /* addr => lo_sum (new_base, addr), case (2) above. */ |
3485 | insn = emit_insn (gen_rtx_SET | |
3486 | (new_reg, | |
3487 | gen_rtx_HIGH (Pmode, copy_rtx (addr)))); | |
3488 | code = recog_memoized (insn); | |
3489 | if (code >= 0) | |
3490 | { | |
3491 | *ad.inner = gen_rtx_LO_SUM (Pmode, new_reg, addr); | |
1aeffdce | 3492 | if (!valid_address_p (op, &ad, cn)) |
d0b2266a TS |
3493 | { |
3494 | /* Try to put lo_sum into register. */ | |
3495 | insn = emit_insn (gen_rtx_SET | |
3496 | (new_reg, | |
3497 | gen_rtx_LO_SUM (Pmode, new_reg, addr))); | |
3498 | code = recog_memoized (insn); | |
3499 | if (code >= 0) | |
3500 | { | |
3501 | *ad.inner = new_reg; | |
1aeffdce | 3502 | if (!valid_address_p (op, &ad, cn)) |
d0b2266a TS |
3503 | { |
3504 | *ad.inner = addr; | |
3505 | code = -1; | |
3506 | } | |
3507 | } | |
3508 | ||
3509 | } | |
3510 | } | |
3511 | if (code < 0) | |
3512 | delete_insns_since (last); | |
3513 | } | |
3514 | ||
55a2c322 VM |
3515 | if (code < 0) |
3516 | { | |
2c62cbaa VM |
3517 | /* addr => new_base, case (2) above. */ |
3518 | lra_emit_move (new_reg, addr); | |
95831c01 VM |
3519 | |
3520 | for (insn = last == NULL_RTX ? get_insns () : NEXT_INSN (last); | |
3521 | insn != NULL_RTX; | |
3522 | insn = NEXT_INSN (insn)) | |
3523 | if (recog_memoized (insn) < 0) | |
3524 | break; | |
3525 | if (insn != NULL_RTX) | |
3526 | { | |
3527 | /* Do nothing if we cannot generate right insns. | |
9c582551 | 3528 | This is analogous to reload pass behavior. */ |
95831c01 VM |
3529 | delete_insns_since (last); |
3530 | end_sequence (); | |
3531 | return false; | |
3532 | } | |
2c62cbaa | 3533 | *ad.inner = new_reg; |
55a2c322 VM |
3534 | } |
3535 | } | |
3536 | else | |
3537 | { | |
bd3d34d4 RS |
3538 | /* index * scale + disp => new base + index * scale, |
3539 | case (1) above. */ | |
277f65de RS |
3540 | enum reg_class cl = base_reg_class (ad.mode, ad.as, PLUS, |
3541 | GET_CODE (*ad.index)); | |
55a2c322 VM |
3542 | |
3543 | lra_assert (INDEX_REG_CLASS != NO_REGS); | |
3544 | new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "disp"); | |
277f65de RS |
3545 | lra_emit_move (new_reg, *ad.disp); |
3546 | *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), | |
3547 | new_reg, *ad.index); | |
55a2c322 VM |
3548 | } |
3549 | } | |
277f65de | 3550 | else if (ad.index == NULL) |
55a2c322 | 3551 | { |
5a107a0f VM |
3552 | int regno; |
3553 | enum reg_class cl; | |
cfa434f6 DM |
3554 | rtx set; |
3555 | rtx_insn *insns, *last_insn; | |
c31d2d11 RS |
3556 | /* Try to reload base into register only if the base is invalid |
3557 | for the address but with valid offset, case (4) above. */ | |
3558 | start_sequence (); | |
3559 | new_reg = base_to_reg (&ad); | |
3560 | ||
bd3d34d4 | 3561 | /* base + disp => new base, cases (1) and (3) above. */ |
55a2c322 VM |
3562 | /* Another option would be to reload the displacement into an |
3563 | index register. However, postreload has code to optimize | |
3564 | address reloads that have the same base and different | |
3565 | displacements, so reloading into an index register would | |
3566 | not necessarily be a win. */ | |
c31d2d11 | 3567 | if (new_reg == NULL_RTX) |
9005477f RS |
3568 | { |
3569 | /* See if the target can split the displacement into a | |
3570 | legitimate new displacement from a local anchor. */ | |
3571 | gcc_assert (ad.disp == ad.disp_term); | |
3572 | poly_int64 orig_offset; | |
3573 | rtx offset1, offset2; | |
3574 | if (poly_int_rtx_p (*ad.disp, &orig_offset) | |
3575 | && targetm.legitimize_address_displacement (&offset1, &offset2, | |
3576 | orig_offset, | |
3577 | ad.mode)) | |
3578 | { | |
3579 | new_reg = base_plus_disp_to_reg (&ad, offset1); | |
3580 | new_reg = gen_rtx_PLUS (GET_MODE (new_reg), new_reg, offset2); | |
3581 | } | |
3582 | else | |
3583 | new_reg = base_plus_disp_to_reg (&ad, *ad.disp); | |
3584 | } | |
5a107a0f VM |
3585 | insns = get_insns (); |
3586 | last_insn = get_last_insn (); | |
3587 | /* If we generated at least two insns, try last insn source as | |
3588 | an address. If we succeed, we generate one less insn. */ | |
9005477f RS |
3589 | if (REG_P (new_reg) |
3590 | && last_insn != insns | |
3591 | && (set = single_set (last_insn)) != NULL_RTX | |
5a107a0f VM |
3592 | && GET_CODE (SET_SRC (set)) == PLUS |
3593 | && REG_P (XEXP (SET_SRC (set), 0)) | |
3594 | && CONSTANT_P (XEXP (SET_SRC (set), 1))) | |
3595 | { | |
3596 | *ad.inner = SET_SRC (set); | |
1aeffdce | 3597 | if (valid_address_p (op, &ad, cn)) |
5a107a0f VM |
3598 | { |
3599 | *ad.base_term = XEXP (SET_SRC (set), 0); | |
3600 | *ad.disp_term = XEXP (SET_SRC (set), 1); | |
3601 | cl = base_reg_class (ad.mode, ad.as, ad.base_outer_code, | |
3602 | get_index_code (&ad)); | |
3603 | regno = REGNO (*ad.base_term); | |
3604 | if (regno >= FIRST_PSEUDO_REGISTER | |
3605 | && cl != lra_get_allocno_class (regno)) | |
a2d0d374 | 3606 | lra_change_class (regno, cl, " Change to", true); |
5a107a0f VM |
3607 | new_reg = SET_SRC (set); |
3608 | delete_insns_since (PREV_INSN (last_insn)); | |
3609 | } | |
3610 | } | |
3611 | end_sequence (); | |
3612 | emit_insn (insns); | |
277f65de | 3613 | *ad.inner = new_reg; |
55a2c322 | 3614 | } |
6e071b1e | 3615 | else if (ad.disp_term != NULL) |
55a2c322 | 3616 | { |
bd3d34d4 RS |
3617 | /* base + scale * index + disp => new base + scale * index, |
3618 | case (1) above. */ | |
9005477f RS |
3619 | gcc_assert (ad.disp == ad.disp_term); |
3620 | new_reg = base_plus_disp_to_reg (&ad, *ad.disp); | |
277f65de RS |
3621 | *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), |
3622 | new_reg, *ad.index); | |
55a2c322 | 3623 | } |
bc2fc1f3 | 3624 | else if ((scale = get_index_scale (&ad)) == 1) |
5a770e01 VM |
3625 | { |
3626 | /* The last transformation to one reg will be made in | |
3627 | curr_insn_transform function. */ | |
3628 | end_sequence (); | |
3629 | return false; | |
3630 | } | |
bc2fc1f3 | 3631 | else if (scale != 0) |
6e071b1e VM |
3632 | { |
3633 | /* base + scale * index => base + new_reg, | |
3634 | case (1) above. | |
3635 | Index part of address may become invalid. For example, we | |
3636 | changed pseudo on the equivalent memory and a subreg of the | |
3637 | pseudo onto the memory of different mode for which the scale is | |
3638 | prohibitted. */ | |
3639 | new_reg = index_part_to_reg (&ad); | |
3640 | *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), | |
3641 | *ad.base_term, new_reg); | |
3642 | } | |
bc2fc1f3 VM |
3643 | else |
3644 | { | |
3645 | enum reg_class cl = base_reg_class (ad.mode, ad.as, | |
3646 | SCRATCH, SCRATCH); | |
3647 | rtx addr = *ad.inner; | |
3648 | ||
3649 | new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "addr"); | |
3650 | /* addr => new_base. */ | |
3651 | lra_emit_move (new_reg, addr); | |
3652 | *ad.inner = new_reg; | |
3653 | } | |
55a2c322 VM |
3654 | *before = get_insns (); |
3655 | end_sequence (); | |
3656 | return true; | |
3657 | } | |
3658 | ||
d9cf932c VM |
3659 | /* If CHECK_ONLY_P is false, do address reloads until it is necessary. |
3660 | Use process_address_1 as a helper function. Return true for any | |
3661 | RTL changes. | |
3662 | ||
3663 | If CHECK_ONLY_P is true, just check address correctness. Return | |
3664 | false if the address correct. */ | |
cc8849a1 | 3665 | static bool |
d9cf932c VM |
3666 | process_address (int nop, bool check_only_p, |
3667 | rtx_insn **before, rtx_insn **after) | |
cc8849a1 VM |
3668 | { |
3669 | bool res = false; | |
3670 | ||
d9cf932c VM |
3671 | while (process_address_1 (nop, check_only_p, before, after)) |
3672 | { | |
3673 | if (check_only_p) | |
3674 | return true; | |
3675 | res = true; | |
3676 | } | |
cc8849a1 VM |
3677 | return res; |
3678 | } | |
3679 | ||
55a2c322 VM |
3680 | /* Emit insns to reload VALUE into a new register. VALUE is an |
3681 | auto-increment or auto-decrement RTX whose operand is a register or | |
3682 | memory location; so reloading involves incrementing that location. | |
3683 | IN is either identical to VALUE, or some cheaper place to reload | |
3684 | value being incremented/decremented from. | |
3685 | ||
3686 | INC_AMOUNT is the number to increment or decrement by (always | |
3687 | positive and ignored for POST_MODIFY/PRE_MODIFY). | |
3688 | ||
3689 | Return pseudo containing the result. */ | |
3690 | static rtx | |
31ae0e43 | 3691 | emit_inc (enum reg_class new_rclass, rtx in, rtx value, poly_int64 inc_amount) |
55a2c322 VM |
3692 | { |
3693 | /* REG or MEM to be copied and incremented. */ | |
3694 | rtx incloc = XEXP (value, 0); | |
3695 | /* Nonzero if increment after copying. */ | |
3696 | int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC | |
3697 | || GET_CODE (value) == POST_MODIFY); | |
cfa434f6 | 3698 | rtx_insn *last; |
55a2c322 | 3699 | rtx inc; |
647d790d | 3700 | rtx_insn *add_insn; |
55a2c322 VM |
3701 | int code; |
3702 | rtx real_in = in == value ? incloc : in; | |
3703 | rtx result; | |
3704 | bool plus_p = true; | |
3705 | ||
3706 | if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY) | |
3707 | { | |
3708 | lra_assert (GET_CODE (XEXP (value, 1)) == PLUS | |
3709 | || GET_CODE (XEXP (value, 1)) == MINUS); | |
3710 | lra_assert (rtx_equal_p (XEXP (XEXP (value, 1), 0), XEXP (value, 0))); | |
3711 | plus_p = GET_CODE (XEXP (value, 1)) == PLUS; | |
3712 | inc = XEXP (XEXP (value, 1), 1); | |
3713 | } | |
3714 | else | |
3715 | { | |
3716 | if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC) | |
3717 | inc_amount = -inc_amount; | |
3718 | ||
31ae0e43 | 3719 | inc = gen_int_mode (inc_amount, GET_MODE (value)); |
55a2c322 VM |
3720 | } |
3721 | ||
3722 | if (! post && REG_P (incloc)) | |
3723 | result = incloc; | |
3724 | else | |
3725 | result = lra_create_new_reg (GET_MODE (value), value, new_rclass, | |
3726 | "INC/DEC result"); | |
3727 | ||
3728 | if (real_in != result) | |
3729 | { | |
3730 | /* First copy the location to the result register. */ | |
3731 | lra_assert (REG_P (result)); | |
3732 | emit_insn (gen_move_insn (result, real_in)); | |
3733 | } | |
3734 | ||
3735 | /* We suppose that there are insns to add/sub with the constant | |
3736 | increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the | |
3737 | old reload worked with this assumption. If the assumption | |
3738 | becomes wrong, we should use approach in function | |
3739 | base_plus_disp_to_reg. */ | |
3740 | if (in == value) | |
3741 | { | |
3742 | /* See if we can directly increment INCLOC. */ | |
3743 | last = get_last_insn (); | |
3744 | add_insn = emit_insn (plus_p | |
3745 | ? gen_add2_insn (incloc, inc) | |
3746 | : gen_sub2_insn (incloc, inc)); | |
3747 | ||
3748 | code = recog_memoized (add_insn); | |
3749 | if (code >= 0) | |
3750 | { | |
3751 | if (! post && result != incloc) | |
3752 | emit_insn (gen_move_insn (result, incloc)); | |
3753 | return result; | |
3754 | } | |
3755 | delete_insns_since (last); | |
3756 | } | |
3757 | ||
3758 | /* If couldn't do the increment directly, must increment in RESULT. | |
3759 | The way we do this depends on whether this is pre- or | |
3760 | post-increment. For pre-increment, copy INCLOC to the reload | |
3761 | register, increment it there, then save back. */ | |
3762 | if (! post) | |
3763 | { | |
3764 | if (real_in != result) | |
3765 | emit_insn (gen_move_insn (result, real_in)); | |
3766 | if (plus_p) | |
3767 | emit_insn (gen_add2_insn (result, inc)); | |
3768 | else | |
3769 | emit_insn (gen_sub2_insn (result, inc)); | |
3770 | if (result != incloc) | |
3771 | emit_insn (gen_move_insn (incloc, result)); | |
3772 | } | |
3773 | else | |
3774 | { | |
3775 | /* Post-increment. | |
3776 | ||
3777 | Because this might be a jump insn or a compare, and because | |
3778 | RESULT may not be available after the insn in an input | |
3779 | reload, we must do the incrementing before the insn being | |
3780 | reloaded for. | |
3781 | ||
3782 | We have already copied IN to RESULT. Increment the copy in | |
3783 | RESULT, save that back, then decrement RESULT so it has | |
3784 | the original value. */ | |
3785 | if (plus_p) | |
3786 | emit_insn (gen_add2_insn (result, inc)); | |
3787 | else | |
3788 | emit_insn (gen_sub2_insn (result, inc)); | |
3789 | emit_insn (gen_move_insn (incloc, result)); | |
3790 | /* Restore non-modified value for the result. We prefer this | |
3791 | way because it does not require an additional hard | |
3792 | register. */ | |
3793 | if (plus_p) | |
3794 | { | |
73ca989c RS |
3795 | poly_int64 offset; |
3796 | if (poly_int_rtx_p (inc, &offset)) | |
69db2d57 | 3797 | emit_insn (gen_add2_insn (result, |
73ca989c | 3798 | gen_int_mode (-offset, |
69db2d57 | 3799 | GET_MODE (result)))); |
55a2c322 VM |
3800 | else |
3801 | emit_insn (gen_sub2_insn (result, inc)); | |
3802 | } | |
3803 | else | |
3804 | emit_insn (gen_add2_insn (result, inc)); | |
3805 | } | |
3806 | return result; | |
3807 | } | |
3808 | ||
2c62cbaa VM |
3809 | /* Return true if the current move insn does not need processing as we |
3810 | already know that it satisfies its constraints. */ | |
3811 | static bool | |
3812 | simple_move_p (void) | |
3813 | { | |
3814 | rtx dest, src; | |
3815 | enum reg_class dclass, sclass; | |
3816 | ||
3817 | lra_assert (curr_insn_set != NULL_RTX); | |
3818 | dest = SET_DEST (curr_insn_set); | |
3819 | src = SET_SRC (curr_insn_set); | |
2008be40 SB |
3820 | |
3821 | /* If the instruction has multiple sets we need to process it even if it | |
3822 | is single_set. This can happen if one or more of the SETs are dead. | |
3823 | See PR73650. */ | |
3824 | if (multiple_sets (curr_insn)) | |
3825 | return false; | |
3826 | ||
2c62cbaa VM |
3827 | return ((dclass = get_op_class (dest)) != NO_REGS |
3828 | && (sclass = get_op_class (src)) != NO_REGS | |
3829 | /* The backend guarantees that register moves of cost 2 | |
3830 | never need reloads. */ | |
03b9b5ce | 3831 | && targetm.register_move_cost (GET_MODE (src), sclass, dclass) == 2); |
2c62cbaa VM |
3832 | } |
3833 | ||
55a2c322 VM |
3834 | /* Swap operands NOP and NOP + 1. */ |
3835 | static inline void | |
3836 | swap_operands (int nop) | |
3837 | { | |
fab27f52 MM |
3838 | std::swap (curr_operand_mode[nop], curr_operand_mode[nop + 1]); |
3839 | std::swap (original_subreg_reg_mode[nop], original_subreg_reg_mode[nop + 1]); | |
3840 | std::swap (*curr_id->operand_loc[nop], *curr_id->operand_loc[nop + 1]); | |
987b67f1 | 3841 | std::swap (equiv_substition_p[nop], equiv_substition_p[nop + 1]); |
55a2c322 VM |
3842 | /* Swap the duplicates too. */ |
3843 | lra_update_dup (curr_id, nop); | |
3844 | lra_update_dup (curr_id, nop + 1); | |
3845 | } | |
3846 | ||
3847 | /* Main entry point of the constraint code: search the body of the | |
3848 | current insn to choose the best alternative. It is mimicking insn | |
3849 | alternative cost calculation model of former reload pass. That is | |
3850 | because machine descriptions were written to use this model. This | |
3851 | model can be changed in future. Make commutative operand exchange | |
3852 | if it is chosen. | |
3853 | ||
d9cf932c VM |
3854 | if CHECK_ONLY_P is false, do RTL changes to satisfy the |
3855 | constraints. Return true if any change happened during function | |
3856 | call. | |
3857 | ||
3858 | If CHECK_ONLY_P is true then don't do any transformation. Just | |
3859 | check that the insn satisfies all constraints. If the insn does | |
3860 | not satisfy any constraint, return true. */ | |
55a2c322 | 3861 | static bool |
d9cf932c | 3862 | curr_insn_transform (bool check_only_p) |
55a2c322 VM |
3863 | { |
3864 | int i, j, k; | |
3865 | int n_operands; | |
3866 | int n_alternatives; | |
aefae0f1 | 3867 | int n_outputs; |
55a2c322 VM |
3868 | int commutative; |
3869 | signed char goal_alt_matched[MAX_RECOG_OPERANDS][MAX_RECOG_OPERANDS]; | |
511dcace | 3870 | signed char match_inputs[MAX_RECOG_OPERANDS + 1]; |
aefae0f1 | 3871 | signed char outputs[MAX_RECOG_OPERANDS + 1]; |
cfa434f6 | 3872 | rtx_insn *before, *after; |
55a2c322 VM |
3873 | bool alt_p = false; |
3874 | /* Flag that the insn has been changed through a transformation. */ | |
3875 | bool change_p; | |
3876 | bool sec_mem_p; | |
55a2c322 | 3877 | bool use_sec_mem_p; |
55a2c322 VM |
3878 | int max_regno_before; |
3879 | int reused_alternative_num; | |
3880 | ||
2c62cbaa VM |
3881 | curr_insn_set = single_set (curr_insn); |
3882 | if (curr_insn_set != NULL_RTX && simple_move_p ()) | |
7874b7c5 VM |
3883 | { |
3884 | /* We assume that the corresponding insn alternative has no | |
3885 | earlier clobbers. If it is not the case, don't define move | |
3886 | cost equal to 2 for the corresponding register classes. */ | |
3887 | lra_set_used_insn_alternative (curr_insn, LRA_NON_CLOBBERED_ALT); | |
3888 | return false; | |
3889 | } | |
2c62cbaa | 3890 | |
55a2c322 VM |
3891 | no_input_reloads_p = no_output_reloads_p = false; |
3892 | goal_alt_number = -1; | |
2c62cbaa | 3893 | change_p = sec_mem_p = false; |
55a2c322 VM |
3894 | /* JUMP_INSNs and CALL_INSNs are not allowed to have any output |
3895 | reloads; neither are insns that SET cc0. Insns that use CC0 are | |
3896 | not allowed to have any input reloads. */ | |
3897 | if (JUMP_P (curr_insn) || CALL_P (curr_insn)) | |
3898 | no_output_reloads_p = true; | |
3899 | ||
058eb3b0 | 3900 | if (HAVE_cc0 && reg_referenced_p (cc0_rtx, PATTERN (curr_insn))) |
55a2c322 | 3901 | no_input_reloads_p = true; |
058eb3b0 | 3902 | if (HAVE_cc0 && reg_set_p (cc0_rtx, PATTERN (curr_insn))) |
55a2c322 | 3903 | no_output_reloads_p = true; |
55a2c322 VM |
3904 | |
3905 | n_operands = curr_static_id->n_operands; | |
3906 | n_alternatives = curr_static_id->n_alternatives; | |
3907 | ||
3908 | /* Just return "no reloads" if insn has no operands with | |
3909 | constraints. */ | |
3910 | if (n_operands == 0 || n_alternatives == 0) | |
3911 | return false; | |
3912 | ||
3913 | max_regno_before = max_reg_num (); | |
3914 | ||
3915 | for (i = 0; i < n_operands; i++) | |
3916 | { | |
3917 | goal_alt_matched[i][0] = -1; | |
3918 | goal_alt_matches[i] = -1; | |
3919 | } | |
3920 | ||
3921 | commutative = curr_static_id->commutative; | |
3922 | ||
3923 | /* Now see what we need for pseudos that didn't get hard regs or got | |
3924 | the wrong kind of hard reg. For this, we must consider all the | |
3925 | operands together against the register constraints. */ | |
3926 | ||
821b7577 | 3927 | best_losers = best_overall = INT_MAX; |
36ff9dfb | 3928 | best_reload_sum = 0; |
55a2c322 VM |
3929 | |
3930 | curr_swapped = false; | |
3931 | goal_alt_swapped = false; | |
3932 | ||
d9cf932c VM |
3933 | if (! check_only_p) |
3934 | /* Make equivalence substitution and memory subreg elimination | |
3935 | before address processing because an address legitimacy can | |
3936 | depend on memory mode. */ | |
3937 | for (i = 0; i < n_operands; i++) | |
3938 | { | |
0b87be09 | 3939 | rtx op, subst, old; |
d9cf932c | 3940 | bool op_change_p = false; |
0b87be09 VM |
3941 | |
3942 | if (curr_static_id->operand[i].is_operator) | |
3943 | continue; | |
d9cf932c | 3944 | |
0b87be09 | 3945 | old = op = *curr_id->operand_loc[i]; |
d9cf932c VM |
3946 | if (GET_CODE (old) == SUBREG) |
3947 | old = SUBREG_REG (old); | |
3948 | subst = get_equiv_with_elimination (old, curr_insn); | |
895ff86f | 3949 | original_subreg_reg_mode[i] = VOIDmode; |
987b67f1 | 3950 | equiv_substition_p[i] = false; |
d9cf932c VM |
3951 | if (subst != old) |
3952 | { | |
987b67f1 | 3953 | equiv_substition_p[i] = true; |
d9cf932c VM |
3954 | subst = copy_rtx (subst); |
3955 | lra_assert (REG_P (old)); | |
895ff86f | 3956 | if (GET_CODE (op) != SUBREG) |
d9cf932c | 3957 | *curr_id->operand_loc[i] = subst; |
895ff86f VM |
3958 | else |
3959 | { | |
3960 | SUBREG_REG (op) = subst; | |
3961 | if (GET_MODE (subst) == VOIDmode) | |
3962 | original_subreg_reg_mode[i] = GET_MODE (old); | |
3963 | } | |
d9cf932c VM |
3964 | if (lra_dump_file != NULL) |
3965 | { | |
3966 | fprintf (lra_dump_file, | |
3967 | "Changing pseudo %d in operand %i of insn %u on equiv ", | |
3968 | REGNO (old), i, INSN_UID (curr_insn)); | |
3969 | dump_value_slim (lra_dump_file, subst, 1); | |
895ff86f | 3970 | fprintf (lra_dump_file, "\n"); |
d9cf932c VM |
3971 | } |
3972 | op_change_p = change_p = true; | |
3973 | } | |
3974 | if (simplify_operand_subreg (i, GET_MODE (old)) || op_change_p) | |
3975 | { | |
3976 | change_p = true; | |
3977 | lra_update_dup (curr_id, i); | |
3978 | } | |
3979 | } | |
55a2c322 VM |
3980 | |
3981 | /* Reload address registers and displacements. We do it before | |
3982 | finding an alternative because of memory constraints. */ | |
cfa434f6 | 3983 | before = after = NULL; |
55a2c322 VM |
3984 | for (i = 0; i < n_operands; i++) |
3985 | if (! curr_static_id->operand[i].is_operator | |
d9cf932c | 3986 | && process_address (i, check_only_p, &before, &after)) |
55a2c322 | 3987 | { |
d9cf932c VM |
3988 | if (check_only_p) |
3989 | return true; | |
55a2c322 VM |
3990 | change_p = true; |
3991 | lra_update_dup (curr_id, i); | |
3992 | } | |
cc8849a1 | 3993 | |
55a2c322 VM |
3994 | if (change_p) |
3995 | /* If we've changed the instruction then any alternative that | |
3996 | we chose previously may no longer be valid. */ | |
7874b7c5 | 3997 | lra_set_used_insn_alternative (curr_insn, LRA_UNKNOWN_ALT); |
55a2c322 | 3998 | |
d9cf932c | 3999 | if (! check_only_p && curr_insn_set != NULL_RTX |
2c62cbaa VM |
4000 | && check_and_process_move (&change_p, &sec_mem_p)) |
4001 | return change_p; | |
4002 | ||
55a2c322 VM |
4003 | try_swapped: |
4004 | ||
7874b7c5 | 4005 | reused_alternative_num = check_only_p ? LRA_UNKNOWN_ALT : curr_id->used_insn_alternative; |
55a2c322 VM |
4006 | if (lra_dump_file != NULL && reused_alternative_num >= 0) |
4007 | fprintf (lra_dump_file, "Reusing alternative %d for insn #%u\n", | |
4008 | reused_alternative_num, INSN_UID (curr_insn)); | |
4009 | ||
4010 | if (process_alt_operands (reused_alternative_num)) | |
4011 | alt_p = true; | |
4012 | ||
d9cf932c VM |
4013 | if (check_only_p) |
4014 | return ! alt_p || best_losers != 0; | |
4015 | ||
55a2c322 VM |
4016 | /* If insn is commutative (it's safe to exchange a certain pair of |
4017 | operands) then we need to try each alternative twice, the second | |
4018 | time matching those two operands as if we had exchanged them. To | |
4019 | do this, really exchange them in operands. | |
4020 | ||
4021 | If we have just tried the alternatives the second time, return | |
4022 | operands to normal and drop through. */ | |
4023 | ||
4024 | if (reused_alternative_num < 0 && commutative >= 0) | |
4025 | { | |
4026 | curr_swapped = !curr_swapped; | |
4027 | if (curr_swapped) | |
4028 | { | |
4029 | swap_operands (commutative); | |
4030 | goto try_swapped; | |
4031 | } | |
4032 | else | |
4033 | swap_operands (commutative); | |
4034 | } | |
4035 | ||
55a2c322 VM |
4036 | if (! alt_p && ! sec_mem_p) |
4037 | { | |
4038 | /* No alternative works with reloads?? */ | |
4039 | if (INSN_CODE (curr_insn) >= 0) | |
4040 | fatal_insn ("unable to generate reloads for:", curr_insn); | |
4041 | error_for_asm (curr_insn, | |
4042 | "inconsistent operand constraints in an %<asm%>"); | |
11067dee | 4043 | lra_asm_error_p = true; |
8b4aea73 VM |
4044 | /* Avoid further trouble with this insn. Don't generate use |
4045 | pattern here as we could use the insn SP offset. */ | |
4046 | lra_set_insn_deleted (curr_insn); | |
55a2c322 VM |
4047 | return true; |
4048 | } | |
4049 | ||
4050 | /* If the best alternative is with operands 1 and 2 swapped, swap | |
4051 | them. Update the operand numbers of any reloads already | |
4052 | pushed. */ | |
4053 | ||
4054 | if (goal_alt_swapped) | |
4055 | { | |
4056 | if (lra_dump_file != NULL) | |
4057 | fprintf (lra_dump_file, " Commutative operand exchange in insn %u\n", | |
4058 | INSN_UID (curr_insn)); | |
4059 | ||
4060 | /* Swap the duplicates too. */ | |
4061 | swap_operands (commutative); | |
4062 | change_p = true; | |
4063 | } | |
4064 | ||
f15643d4 | 4065 | /* Some targets' TARGET_SECONDARY_MEMORY_NEEDED (e.g. x86) are defined |
55a2c322 VM |
4066 | too conservatively. So we use the secondary memory only if there |
4067 | is no any alternative without reloads. */ | |
4068 | use_sec_mem_p = false; | |
4069 | if (! alt_p) | |
4070 | use_sec_mem_p = true; | |
4071 | else if (sec_mem_p) | |
4072 | { | |
4073 | for (i = 0; i < n_operands; i++) | |
4074 | if (! goal_alt_win[i] && ! goal_alt_match_win[i]) | |
4075 | break; | |
4076 | use_sec_mem_p = i < n_operands; | |
4077 | } | |
4078 | ||
4079 | if (use_sec_mem_p) | |
4080 | { | |
e03dd765 | 4081 | int in = -1, out = -1; |
89d56d79 | 4082 | rtx new_reg, src, dest, rld; |
ef4bddc2 | 4083 | machine_mode sec_mode, rld_mode; |
55a2c322 | 4084 | |
e03dd765 VM |
4085 | lra_assert (curr_insn_set != NULL_RTX && sec_mem_p); |
4086 | dest = SET_DEST (curr_insn_set); | |
4087 | src = SET_SRC (curr_insn_set); | |
4088 | for (i = 0; i < n_operands; i++) | |
4089 | if (*curr_id->operand_loc[i] == dest) | |
4090 | out = i; | |
4091 | else if (*curr_id->operand_loc[i] == src) | |
4092 | in = i; | |
4093 | for (i = 0; i < curr_static_id->n_dups; i++) | |
4094 | if (out < 0 && *curr_id->dup_loc[i] == dest) | |
4095 | out = curr_static_id->dup_num[i]; | |
4096 | else if (in < 0 && *curr_id->dup_loc[i] == src) | |
4097 | in = curr_static_id->dup_num[i]; | |
4098 | lra_assert (out >= 0 && in >= 0 | |
4099 | && curr_static_id->operand[out].type == OP_OUT | |
4100 | && curr_static_id->operand[in].type == OP_IN); | |
bd4288c0 | 4101 | rld = partial_subreg_p (GET_MODE (src), GET_MODE (dest)) ? src : dest; |
66aa7879 | 4102 | rld_mode = GET_MODE (rld); |
94e23f53 | 4103 | sec_mode = targetm.secondary_memory_needed_mode (rld_mode); |
55a2c322 VM |
4104 | new_reg = lra_create_new_reg (sec_mode, NULL_RTX, |
4105 | NO_REGS, "secondary"); | |
4106 | /* If the mode is changed, it should be wider. */ | |
bd4288c0 | 4107 | lra_assert (!partial_subreg_p (sec_mode, rld_mode)); |
89d56d79 VM |
4108 | if (sec_mode != rld_mode) |
4109 | { | |
4110 | /* If the target says specifically to use another mode for | |
67914693 | 4111 | secondary memory moves we cannot reuse the original |
89d56d79 | 4112 | insn. */ |
1ccd4874 | 4113 | after = emit_spill_move (false, new_reg, dest); |
cfa434f6 | 4114 | lra_process_new_insns (curr_insn, NULL, after, |
1ccd4874 VM |
4115 | "Inserting the sec. move"); |
4116 | /* We may have non null BEFORE here (e.g. after address | |
4117 | processing. */ | |
4118 | push_to_sequence (before); | |
4119 | before = emit_spill_move (true, new_reg, src); | |
4120 | emit_insn (before); | |
4121 | before = get_insns (); | |
4122 | end_sequence (); | |
cfa434f6 | 4123 | lra_process_new_insns (curr_insn, before, NULL, "Changing on"); |
1ccd4874 VM |
4124 | lra_set_insn_deleted (curr_insn); |
4125 | } | |
89d56d79 | 4126 | else if (dest == rld) |
1ccd4874 | 4127 | { |
e03dd765 VM |
4128 | *curr_id->operand_loc[out] = new_reg; |
4129 | lra_update_dup (curr_id, out); | |
66aa7879 | 4130 | after = emit_spill_move (false, new_reg, dest); |
cfa434f6 | 4131 | lra_process_new_insns (curr_insn, NULL, after, |
66aa7879 VM |
4132 | "Inserting the sec. move"); |
4133 | } | |
4134 | else | |
4135 | { | |
e03dd765 VM |
4136 | *curr_id->operand_loc[in] = new_reg; |
4137 | lra_update_dup (curr_id, in); | |
1ccd4874 VM |
4138 | /* See comments above. */ |
4139 | push_to_sequence (before); | |
66aa7879 | 4140 | before = emit_spill_move (true, new_reg, src); |
1ccd4874 VM |
4141 | emit_insn (before); |
4142 | before = get_insns (); | |
4143 | end_sequence (); | |
cfa434f6 | 4144 | lra_process_new_insns (curr_insn, before, NULL, |
66aa7879 VM |
4145 | "Inserting the sec. move"); |
4146 | } | |
4147 | lra_update_insn_regno_info (curr_insn); | |
55a2c322 VM |
4148 | return true; |
4149 | } | |
55a2c322 VM |
4150 | |
4151 | lra_assert (goal_alt_number >= 0); | |
4152 | lra_set_used_insn_alternative (curr_insn, goal_alt_number); | |
4153 | ||
4154 | if (lra_dump_file != NULL) | |
4155 | { | |
4156 | const char *p; | |
4157 | ||
4158 | fprintf (lra_dump_file, " Choosing alt %d in insn %u:", | |
4159 | goal_alt_number, INSN_UID (curr_insn)); | |
4160 | for (i = 0; i < n_operands; i++) | |
4161 | { | |
4162 | p = (curr_static_id->operand_alternative | |
4163 | [goal_alt_number * n_operands + i].constraint); | |
4164 | if (*p == '\0') | |
4165 | continue; | |
4166 | fprintf (lra_dump_file, " (%d) ", i); | |
4167 | for (; *p != '\0' && *p != ',' && *p != '#'; p++) | |
4168 | fputc (*p, lra_dump_file); | |
4169 | } | |
36ff9dfb VM |
4170 | if (INSN_CODE (curr_insn) >= 0 |
4171 | && (p = get_insn_name (INSN_CODE (curr_insn))) != NULL) | |
4172 | fprintf (lra_dump_file, " {%s}", p); | |
73ca989c RS |
4173 | if (maybe_ne (curr_id->sp_offset, 0)) |
4174 | { | |
4175 | fprintf (lra_dump_file, " (sp_off="); | |
4176 | print_dec (curr_id->sp_offset, lra_dump_file); | |
4177 | fprintf (lra_dump_file, ")"); | |
4178 | } | |
4179 | fprintf (lra_dump_file, "\n"); | |
55a2c322 VM |
4180 | } |
4181 | ||
4182 | /* Right now, for any pair of operands I and J that are required to | |
4183 | match, with J < I, goal_alt_matches[I] is J. Add I to | |
4184 | goal_alt_matched[J]. */ | |
f4eafc30 | 4185 | |
55a2c322 VM |
4186 | for (i = 0; i < n_operands; i++) |
4187 | if ((j = goal_alt_matches[i]) >= 0) | |
4188 | { | |
4189 | for (k = 0; goal_alt_matched[j][k] >= 0; k++) | |
4190 | ; | |
4191 | /* We allow matching one output operand and several input | |
4192 | operands. */ | |
4193 | lra_assert (k == 0 | |
4194 | || (curr_static_id->operand[j].type == OP_OUT | |
4195 | && curr_static_id->operand[i].type == OP_IN | |
4196 | && (curr_static_id->operand | |
4197 | [goal_alt_matched[j][0]].type == OP_IN))); | |
4198 | goal_alt_matched[j][k] = i; | |
4199 | goal_alt_matched[j][k + 1] = -1; | |
4200 | } | |
f4eafc30 | 4201 | |
55a2c322 VM |
4202 | for (i = 0; i < n_operands; i++) |
4203 | goal_alt_win[i] |= goal_alt_match_win[i]; | |
f4eafc30 | 4204 | |
55a2c322 VM |
4205 | /* Any constants that aren't allowed and can't be reloaded into |
4206 | registers are here changed into memory references. */ | |
4207 | for (i = 0; i < n_operands; i++) | |
4208 | if (goal_alt_win[i]) | |
4209 | { | |
4210 | int regno; | |
4211 | enum reg_class new_class; | |
4212 | rtx reg = *curr_id->operand_loc[i]; | |
4213 | ||
4214 | if (GET_CODE (reg) == SUBREG) | |
4215 | reg = SUBREG_REG (reg); | |
f4eafc30 | 4216 | |
55a2c322 VM |
4217 | if (REG_P (reg) && (regno = REGNO (reg)) >= FIRST_PSEUDO_REGISTER) |
4218 | { | |
4219 | bool ok_p = in_class_p (reg, goal_alt[i], &new_class); | |
4220 | ||
4221 | if (new_class != NO_REGS && get_reg_class (regno) != new_class) | |
4222 | { | |
4223 | lra_assert (ok_p); | |
a2d0d374 | 4224 | lra_change_class (regno, new_class, " Change to", true); |
55a2c322 VM |
4225 | } |
4226 | } | |
4227 | } | |
4228 | else | |
4229 | { | |
4230 | const char *constraint; | |
4231 | char c; | |
4232 | rtx op = *curr_id->operand_loc[i]; | |
4233 | rtx subreg = NULL_RTX; | |
ef4bddc2 | 4234 | machine_mode mode = curr_operand_mode[i]; |
f4eafc30 | 4235 | |
55a2c322 VM |
4236 | if (GET_CODE (op) == SUBREG) |
4237 | { | |
4238 | subreg = op; | |
4239 | op = SUBREG_REG (op); | |
4240 | mode = GET_MODE (op); | |
4241 | } | |
f4eafc30 | 4242 | |
55a2c322 VM |
4243 | if (CONST_POOL_OK_P (mode, op) |
4244 | && ((targetm.preferred_reload_class | |
4245 | (op, (enum reg_class) goal_alt[i]) == NO_REGS) | |
4246 | || no_input_reloads_p)) | |
4247 | { | |
4248 | rtx tem = force_const_mem (mode, op); | |
f4eafc30 | 4249 | |
55a2c322 VM |
4250 | change_p = true; |
4251 | if (subreg != NULL_RTX) | |
4252 | tem = gen_rtx_SUBREG (mode, tem, SUBREG_BYTE (subreg)); | |
f4eafc30 | 4253 | |
55a2c322 VM |
4254 | *curr_id->operand_loc[i] = tem; |
4255 | lra_update_dup (curr_id, i); | |
d9cf932c | 4256 | process_address (i, false, &before, &after); |
f4eafc30 | 4257 | |
55a2c322 VM |
4258 | /* If the alternative accepts constant pool refs directly |
4259 | there will be no reload needed at all. */ | |
4260 | if (subreg != NULL_RTX) | |
4261 | continue; | |
4262 | /* Skip alternatives before the one requested. */ | |
4263 | constraint = (curr_static_id->operand_alternative | |
4264 | [goal_alt_number * n_operands + i].constraint); | |
4265 | for (; | |
4266 | (c = *constraint) && c != ',' && c != '#'; | |
4267 | constraint += CONSTRAINT_LEN (c, constraint)) | |
4268 | { | |
777e635f | 4269 | enum constraint_num cn = lookup_constraint (constraint); |
9eb1ca69 VM |
4270 | if ((insn_extra_memory_constraint (cn) |
4271 | || insn_extra_special_memory_constraint (cn)) | |
777e635f | 4272 | && satisfies_memory_constraint_p (tem, cn)) |
55a2c322 | 4273 | break; |
55a2c322 VM |
4274 | } |
4275 | if (c == '\0' || c == ',' || c == '#') | |
4276 | continue; | |
f4eafc30 | 4277 | |
55a2c322 VM |
4278 | goal_alt_win[i] = true; |
4279 | } | |
4280 | } | |
f4eafc30 | 4281 | |
aefae0f1 TP |
4282 | n_outputs = 0; |
4283 | outputs[0] = -1; | |
55a2c322 VM |
4284 | for (i = 0; i < n_operands; i++) |
4285 | { | |
2b778c9d VM |
4286 | int regno; |
4287 | bool optional_p = false; | |
55a2c322 VM |
4288 | rtx old, new_reg; |
4289 | rtx op = *curr_id->operand_loc[i]; | |
4290 | ||
4291 | if (goal_alt_win[i]) | |
4292 | { | |
4293 | if (goal_alt[i] == NO_REGS | |
4294 | && REG_P (op) | |
4295 | /* When we assign NO_REGS it means that we will not | |
4296 | assign a hard register to the scratch pseudo by | |
4297 | assigment pass and the scratch pseudo will be | |
4298 | spilled. Spilled scratch pseudos are transformed | |
4299 | back to scratches at the LRA end. */ | |
6c051d60 VM |
4300 | && lra_former_scratch_operand_p (curr_insn, i) |
4301 | && lra_former_scratch_p (REGNO (op))) | |
deca73f5 VM |
4302 | { |
4303 | int regno = REGNO (op); | |
a2d0d374 | 4304 | lra_change_class (regno, NO_REGS, " Change to", true); |
deca73f5 VM |
4305 | if (lra_get_regno_hard_regno (regno) >= 0) |
4306 | /* We don't have to mark all insn affected by the | |
4307 | spilled pseudo as there is only one such insn, the | |
4308 | current one. */ | |
4309 | reg_renumber[regno] = -1; | |
6c051d60 VM |
4310 | lra_assert (bitmap_single_bit_set_p |
4311 | (&lra_reg_info[REGNO (op)].insn_bitmap)); | |
deca73f5 | 4312 | } |
2b778c9d VM |
4313 | /* We can do an optional reload. If the pseudo got a hard |
4314 | reg, we might improve the code through inheritance. If | |
4315 | it does not get a hard register we coalesce memory/memory | |
4316 | moves later. Ignore move insns to avoid cycling. */ | |
b0681c9e | 4317 | if (! lra_simple_p |
2b778c9d VM |
4318 | && lra_undo_inheritance_iter < LRA_MAX_INHERITANCE_PASSES |
4319 | && goal_alt[i] != NO_REGS && REG_P (op) | |
4320 | && (regno = REGNO (op)) >= FIRST_PSEUDO_REGISTER | |
a2d0d374 | 4321 | && regno < new_regno_start |
b0681c9e | 4322 | && ! lra_former_scratch_p (regno) |
2b778c9d | 4323 | && reg_renumber[regno] < 0 |
3c954213 VM |
4324 | /* Check that the optional reload pseudo will be able to |
4325 | hold given mode value. */ | |
4326 | && ! (prohibited_class_reg_set_mode_p | |
4327 | (goal_alt[i], reg_class_contents[goal_alt[i]], | |
4328 | PSEUDO_REGNO_MODE (regno))) | |
2b778c9d | 4329 | && (curr_insn_set == NULL_RTX |
b0681c9e VM |
4330 | || !((REG_P (SET_SRC (curr_insn_set)) |
4331 | || MEM_P (SET_SRC (curr_insn_set)) | |
4332 | || GET_CODE (SET_SRC (curr_insn_set)) == SUBREG) | |
4333 | && (REG_P (SET_DEST (curr_insn_set)) | |
4334 | || MEM_P (SET_DEST (curr_insn_set)) | |
4335 | || GET_CODE (SET_DEST (curr_insn_set)) == SUBREG)))) | |
2b778c9d | 4336 | optional_p = true; |
c07a0a22 VM |
4337 | else if (goal_alt_matched[i][0] != -1 |
4338 | && curr_static_id->operand[i].type == OP_OUT | |
4339 | && (curr_static_id->operand_alternative | |
33163a62 VM |
4340 | [goal_alt_number * n_operands + i].earlyclobber) |
4341 | && REG_P (op)) | |
c07a0a22 | 4342 | { |
33163a62 VM |
4343 | for (j = 0; goal_alt_matched[i][j] != -1; j++) |
4344 | { | |
4345 | rtx op2 = *curr_id->operand_loc[goal_alt_matched[i][j]]; | |
4346 | ||
4347 | if (REG_P (op2) && REGNO (op) != REGNO (op2)) | |
4348 | break; | |
4349 | } | |
4350 | if (goal_alt_matched[i][j] != -1) | |
4351 | { | |
4352 | /* Generate reloads for different output and matched | |
4353 | input registers. This is the easiest way to avoid | |
4354 | creation of non-existing register conflicts in | |
4355 | lra-lives.c. */ | |
4356 | match_reload (i, goal_alt_matched[i], outputs, goal_alt[i], &before, | |
4357 | &after, TRUE); | |
4358 | outputs[n_outputs++] = i; | |
4359 | outputs[n_outputs] = -1; | |
4360 | } | |
c07a0a22 VM |
4361 | continue; |
4362 | } | |
2b778c9d VM |
4363 | else |
4364 | continue; | |
55a2c322 | 4365 | } |
f4eafc30 | 4366 | |
55a2c322 VM |
4367 | /* Operands that match previous ones have already been handled. */ |
4368 | if (goal_alt_matches[i] >= 0) | |
4369 | continue; | |
4370 | ||
4371 | /* We should not have an operand with a non-offsettable address | |
4372 | appearing where an offsettable address will do. It also may | |
4373 | be a case when the address should be special in other words | |
4374 | not a general one (e.g. it needs no index reg). */ | |
4375 | if (goal_alt_matched[i][0] == -1 && goal_alt_offmemok[i] && MEM_P (op)) | |
4376 | { | |
4377 | enum reg_class rclass; | |
4378 | rtx *loc = &XEXP (op, 0); | |
4379 | enum rtx_code code = GET_CODE (*loc); | |
4380 | ||
4381 | push_to_sequence (before); | |
4382 | rclass = base_reg_class (GET_MODE (op), MEM_ADDR_SPACE (op), | |
4383 | MEM, SCRATCH); | |
4384 | if (GET_RTX_CLASS (code) == RTX_AUTOINC) | |
4385 | new_reg = emit_inc (rclass, *loc, *loc, | |
4386 | /* This value does not matter for MODIFY. */ | |
4387 | GET_MODE_SIZE (GET_MODE (op))); | |
95921002 | 4388 | else if (get_reload_reg (OP_IN, Pmode, *loc, rclass, FALSE, |
55a2c322 | 4389 | "offsetable address", &new_reg)) |
634c3ff0 VM |
4390 | { |
4391 | rtx addr = *loc; | |
4392 | enum rtx_code code = GET_CODE (addr); | |
6b3034ea AC |
4393 | bool align_p = false; |
4394 | ||
634c3ff0 | 4395 | if (code == AND && CONST_INT_P (XEXP (addr, 1))) |
6b3034ea AC |
4396 | { |
4397 | /* (and ... (const_int -X)) is used to align to X bytes. */ | |
4398 | align_p = true; | |
4399 | addr = XEXP (*loc, 0); | |
4400 | } | |
4401 | else | |
4402 | addr = canonicalize_reload_addr (addr); | |
4403 | ||
634c3ff0 | 4404 | lra_emit_move (new_reg, addr); |
6b3034ea | 4405 | if (align_p) |
634c3ff0 VM |
4406 | emit_move_insn (new_reg, gen_rtx_AND (GET_MODE (new_reg), new_reg, XEXP (*loc, 1))); |
4407 | } | |
55a2c322 VM |
4408 | before = get_insns (); |
4409 | end_sequence (); | |
4410 | *loc = new_reg; | |
4411 | lra_update_dup (curr_id, i); | |
4412 | } | |
4413 | else if (goal_alt_matched[i][0] == -1) | |
4414 | { | |
ef4bddc2 | 4415 | machine_mode mode; |
55a2c322 | 4416 | rtx reg, *loc; |
91914e56 | 4417 | int hard_regno; |
55a2c322 VM |
4418 | enum op_type type = curr_static_id->operand[i].type; |
4419 | ||
4420 | loc = curr_id->operand_loc[i]; | |
4421 | mode = curr_operand_mode[i]; | |
4422 | if (GET_CODE (*loc) == SUBREG) | |
4423 | { | |
4424 | reg = SUBREG_REG (*loc); | |
91914e56 | 4425 | poly_int64 byte = SUBREG_BYTE (*loc); |
55a2c322 | 4426 | if (REG_P (reg) |
8e02e8a0 MF |
4427 | /* Strict_low_part requires reloading the register and not |
4428 | just the subreg. Likewise for a strict subreg no wider | |
4429 | than a word for WORD_REGISTER_OPERATIONS targets. */ | |
55a2c322 | 4430 | && (curr_static_id->operand[i].strict_low |
03a95621 | 4431 | || (!paradoxical_subreg_p (mode, GET_MODE (reg)) |
55a2c322 VM |
4432 | && (hard_regno |
4433 | = get_try_hard_regno (REGNO (reg))) >= 0 | |
4434 | && (simplify_subreg_regno | |
4435 | (hard_regno, | |
4436 | GET_MODE (reg), byte, mode) < 0) | |
4437 | && (goal_alt[i] == NO_REGS | |
4438 | || (simplify_subreg_regno | |
4439 | (ira_class_hard_regs[goal_alt[i]][0], | |
8e02e8a0 | 4440 | GET_MODE (reg), byte, mode) >= 0))) |
e5f83886 | 4441 | || (partial_subreg_p (mode, GET_MODE (reg)) |
cf098191 RS |
4442 | && known_le (GET_MODE_SIZE (GET_MODE (reg)), |
4443 | UNITS_PER_WORD) | |
8e02e8a0 | 4444 | && WORD_REGISTER_OPERATIONS))) |
55a2c322 | 4445 | { |
62cdb862 MF |
4446 | /* An OP_INOUT is required when reloading a subreg of a |
4447 | mode wider than a word to ensure that data beyond the | |
4448 | word being reloaded is preserved. Also automatically | |
4449 | ensure that strict_low_part reloads are made into | |
4450 | OP_INOUT which should already be true from the backend | |
4451 | constraints. */ | |
4452 | if (type == OP_OUT | |
4453 | && (curr_static_id->operand[i].strict_low | |
9eaf97d6 | 4454 | || read_modify_subreg_p (*loc))) |
8b8e23de | 4455 | type = OP_INOUT; |
55a2c322 VM |
4456 | loc = &SUBREG_REG (*loc); |
4457 | mode = GET_MODE (*loc); | |
4458 | } | |
4459 | } | |
4460 | old = *loc; | |
95921002 VM |
4461 | if (get_reload_reg (type, mode, old, goal_alt[i], |
4462 | loc != curr_id->operand_loc[i], "", &new_reg) | |
55a2c322 VM |
4463 | && type != OP_OUT) |
4464 | { | |
4465 | push_to_sequence (before); | |
4466 | lra_emit_move (new_reg, old); | |
4467 | before = get_insns (); | |
4468 | end_sequence (); | |
4469 | } | |
4470 | *loc = new_reg; | |
4471 | if (type != OP_IN | |
4472 | && find_reg_note (curr_insn, REG_UNUSED, old) == NULL_RTX) | |
4473 | { | |
4474 | start_sequence (); | |
4475 | lra_emit_move (type == OP_INOUT ? copy_rtx (old) : old, new_reg); | |
4476 | emit_insn (after); | |
4477 | after = get_insns (); | |
4478 | end_sequence (); | |
4479 | *loc = new_reg; | |
4480 | } | |
4481 | for (j = 0; j < goal_alt_dont_inherit_ops_num; j++) | |
4482 | if (goal_alt_dont_inherit_ops[j] == i) | |
4483 | { | |
4484 | lra_set_regno_unique_value (REGNO (new_reg)); | |
4485 | break; | |
4486 | } | |
4487 | lra_update_dup (curr_id, i); | |
4488 | } | |
4489 | else if (curr_static_id->operand[i].type == OP_IN | |
4490 | && (curr_static_id->operand[goal_alt_matched[i][0]].type | |
57d69a63 VM |
4491 | == OP_OUT |
4492 | || (curr_static_id->operand[goal_alt_matched[i][0]].type | |
4493 | == OP_INOUT | |
4494 | && (operands_match_p | |
4495 | (*curr_id->operand_loc[i], | |
4496 | *curr_id->operand_loc[goal_alt_matched[i][0]], | |
4497 | -1))))) | |
55a2c322 | 4498 | { |
511dcace VM |
4499 | /* generate reloads for input and matched outputs. */ |
4500 | match_inputs[0] = i; | |
4501 | match_inputs[1] = -1; | |
aefae0f1 | 4502 | match_reload (goal_alt_matched[i][0], match_inputs, outputs, |
599e1cf8 VM |
4503 | goal_alt[i], &before, &after, |
4504 | curr_static_id->operand_alternative | |
4505 | [goal_alt_number * n_operands + goal_alt_matched[i][0]] | |
4506 | .earlyclobber); | |
55a2c322 | 4507 | } |
57d69a63 VM |
4508 | else if ((curr_static_id->operand[i].type == OP_OUT |
4509 | || (curr_static_id->operand[i].type == OP_INOUT | |
4510 | && (operands_match_p | |
4511 | (*curr_id->operand_loc[i], | |
4512 | *curr_id->operand_loc[goal_alt_matched[i][0]], | |
4513 | -1)))) | |
55a2c322 | 4514 | && (curr_static_id->operand[goal_alt_matched[i][0]].type |
57d69a63 | 4515 | == OP_IN)) |
511dcace | 4516 | /* Generate reloads for output and matched inputs. */ |
aefae0f1 TP |
4517 | match_reload (i, goal_alt_matched[i], outputs, goal_alt[i], &before, |
4518 | &after, curr_static_id->operand_alternative | |
4519 | [goal_alt_number * n_operands + i].earlyclobber); | |
511dcace VM |
4520 | else if (curr_static_id->operand[i].type == OP_IN |
4521 | && (curr_static_id->operand[goal_alt_matched[i][0]].type | |
4522 | == OP_IN)) | |
4523 | { | |
4524 | /* Generate reloads for matched inputs. */ | |
4525 | match_inputs[0] = i; | |
4526 | for (j = 0; (k = goal_alt_matched[i][j]) >= 0; j++) | |
4527 | match_inputs[j + 1] = k; | |
4528 | match_inputs[j + 1] = -1; | |
aefae0f1 TP |
4529 | match_reload (-1, match_inputs, outputs, goal_alt[i], &before, |
4530 | &after, false); | |
511dcace | 4531 | } |
55a2c322 VM |
4532 | else |
4533 | /* We must generate code in any case when function | |
4534 | process_alt_operands decides that it is possible. */ | |
4535 | gcc_unreachable (); | |
aefae0f1 TP |
4536 | |
4537 | /* Memorise processed outputs so that output remaining to be processed | |
4538 | can avoid using the same register value (see match_reload). */ | |
4539 | if (curr_static_id->operand[i].type == OP_OUT) | |
4540 | { | |
4541 | outputs[n_outputs++] = i; | |
4542 | outputs[n_outputs] = -1; | |
4543 | } | |
4544 | ||
2b778c9d VM |
4545 | if (optional_p) |
4546 | { | |
8a8330b7 VM |
4547 | rtx reg = op; |
4548 | ||
4549 | lra_assert (REG_P (reg)); | |
4550 | regno = REGNO (reg); | |
2b778c9d VM |
4551 | op = *curr_id->operand_loc[i]; /* Substitution. */ |
4552 | if (GET_CODE (op) == SUBREG) | |
4553 | op = SUBREG_REG (op); | |
4554 | gcc_assert (REG_P (op) && (int) REGNO (op) >= new_regno_start); | |
4555 | bitmap_set_bit (&lra_optional_reload_pseudos, REGNO (op)); | |
8a8330b7 | 4556 | lra_reg_info[REGNO (op)].restore_rtx = reg; |
2b778c9d VM |
4557 | if (lra_dump_file != NULL) |
4558 | fprintf (lra_dump_file, | |
4559 | " Making reload reg %d for reg %d optional\n", | |
4560 | REGNO (op), regno); | |
4561 | } | |
55a2c322 VM |
4562 | } |
4563 | if (before != NULL_RTX || after != NULL_RTX | |
4564 | || max_regno_before != max_reg_num ()) | |
4565 | change_p = true; | |
4566 | if (change_p) | |
4567 | { | |
4568 | lra_update_operator_dups (curr_id); | |
4569 | /* Something changes -- process the insn. */ | |
4570 | lra_update_insn_regno_info (curr_insn); | |
4571 | } | |
4572 | lra_process_new_insns (curr_insn, before, after, "Inserting insn reload"); | |
4573 | return change_p; | |
4574 | } | |
4575 | ||
d9cf932c VM |
4576 | /* Return true if INSN satisfies all constraints. In other words, no |
4577 | reload insns are needed. */ | |
4578 | bool | |
4579 | lra_constrain_insn (rtx_insn *insn) | |
4580 | { | |
4581 | int saved_new_regno_start = new_regno_start; | |
4582 | int saved_new_insn_uid_start = new_insn_uid_start; | |
4583 | bool change_p; | |
4584 | ||
4585 | curr_insn = insn; | |
4586 | curr_id = lra_get_insn_recog_data (curr_insn); | |
4587 | curr_static_id = curr_id->insn_static_data; | |
4588 | new_insn_uid_start = get_max_uid (); | |
4589 | new_regno_start = max_reg_num (); | |
4590 | change_p = curr_insn_transform (true); | |
4591 | new_regno_start = saved_new_regno_start; | |
4592 | new_insn_uid_start = saved_new_insn_uid_start; | |
4593 | return ! change_p; | |
4594 | } | |
4595 | ||
55a2c322 VM |
4596 | /* Return true if X is in LIST. */ |
4597 | static bool | |
4598 | in_list_p (rtx x, rtx list) | |
4599 | { | |
4600 | for (; list != NULL_RTX; list = XEXP (list, 1)) | |
4601 | if (XEXP (list, 0) == x) | |
4602 | return true; | |
4603 | return false; | |
4604 | } | |
4605 | ||
4606 | /* Return true if X contains an allocatable hard register (if | |
4607 | HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */ | |
4608 | static bool | |
4609 | contains_reg_p (rtx x, bool hard_reg_p, bool spilled_p) | |
4610 | { | |
4611 | int i, j; | |
4612 | const char *fmt; | |
4613 | enum rtx_code code; | |
4614 | ||
4615 | code = GET_CODE (x); | |
4616 | if (REG_P (x)) | |
4617 | { | |
4618 | int regno = REGNO (x); | |
4619 | HARD_REG_SET alloc_regs; | |
4620 | ||
4621 | if (hard_reg_p) | |
4622 | { | |
4623 | if (regno >= FIRST_PSEUDO_REGISTER) | |
4624 | regno = lra_get_regno_hard_regno (regno); | |
4625 | if (regno < 0) | |
4626 | return false; | |
50b3f54d | 4627 | alloc_regs = ~lra_no_alloc_regs; |
55a2c322 VM |
4628 | return overlaps_hard_reg_set_p (alloc_regs, GET_MODE (x), regno); |
4629 | } | |
4630 | else | |
4631 | { | |
4632 | if (regno < FIRST_PSEUDO_REGISTER) | |
4633 | return false; | |
4634 | if (! spilled_p) | |
4635 | return true; | |
4636 | return lra_get_regno_hard_regno (regno) < 0; | |
4637 | } | |
4638 | } | |
4639 | fmt = GET_RTX_FORMAT (code); | |
4640 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
4641 | { | |
4642 | if (fmt[i] == 'e') | |
4643 | { | |
4644 | if (contains_reg_p (XEXP (x, i), hard_reg_p, spilled_p)) | |
4645 | return true; | |
4646 | } | |
4647 | else if (fmt[i] == 'E') | |
4648 | { | |
4649 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
4650 | if (contains_reg_p (XVECEXP (x, i, j), hard_reg_p, spilled_p)) | |
4651 | return true; | |
4652 | } | |
4653 | } | |
4654 | return false; | |
4655 | } | |
4656 | ||
28430b2e VM |
4657 | /* Process all regs in location *LOC and change them on equivalent |
4658 | substitution. Return true if any change was done. */ | |
55a2c322 | 4659 | static bool |
28430b2e | 4660 | loc_equivalence_change_p (rtx *loc) |
55a2c322 VM |
4661 | { |
4662 | rtx subst, reg, x = *loc; | |
4663 | bool result = false; | |
4664 | enum rtx_code code = GET_CODE (x); | |
4665 | const char *fmt; | |
4666 | int i, j; | |
4667 | ||
4668 | if (code == SUBREG) | |
4669 | { | |
4670 | reg = SUBREG_REG (x); | |
8d49e7ef | 4671 | if ((subst = get_equiv_with_elimination (reg, curr_insn)) != reg |
55a2c322 VM |
4672 | && GET_MODE (subst) == VOIDmode) |
4673 | { | |
4674 | /* We cannot reload debug location. Simplify subreg here | |
4675 | while we know the inner mode. */ | |
4676 | *loc = simplify_gen_subreg (GET_MODE (x), subst, | |
4677 | GET_MODE (reg), SUBREG_BYTE (x)); | |
4678 | return true; | |
4679 | } | |
4680 | } | |
8d49e7ef | 4681 | if (code == REG && (subst = get_equiv_with_elimination (x, curr_insn)) != x) |
55a2c322 VM |
4682 | { |
4683 | *loc = subst; | |
4684 | return true; | |
4685 | } | |
4686 | ||
4687 | /* Scan all the operand sub-expressions. */ | |
4688 | fmt = GET_RTX_FORMAT (code); | |
4689 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
4690 | { | |
4691 | if (fmt[i] == 'e') | |
28430b2e | 4692 | result = loc_equivalence_change_p (&XEXP (x, i)) || result; |
55a2c322 VM |
4693 | else if (fmt[i] == 'E') |
4694 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
4695 | result | |
28430b2e | 4696 | = loc_equivalence_change_p (&XVECEXP (x, i, j)) || result; |
55a2c322 VM |
4697 | } |
4698 | return result; | |
4699 | } | |
4700 | ||
d0608e59 | 4701 | /* Similar to loc_equivalence_change_p, but for use as |
4c2b2d79 VM |
4702 | simplify_replace_fn_rtx callback. DATA is insn for which the |
4703 | elimination is done. If it null we don't do the elimination. */ | |
d0608e59 | 4704 | static rtx |
4c2b2d79 | 4705 | loc_equivalence_callback (rtx loc, const_rtx, void *data) |
d0608e59 JJ |
4706 | { |
4707 | if (!REG_P (loc)) | |
4708 | return NULL_RTX; | |
4709 | ||
4c2b2d79 | 4710 | rtx subst = (data == NULL |
cfa434f6 | 4711 | ? get_equiv (loc) : get_equiv_with_elimination (loc, (rtx_insn *) data)); |
d0608e59 JJ |
4712 | if (subst != loc) |
4713 | return subst; | |
4714 | ||
4715 | return NULL_RTX; | |
4716 | } | |
4717 | ||
55a2c322 VM |
4718 | /* Maximum number of generated reload insns per an insn. It is for |
4719 | preventing this pass cycling in a bug case. */ | |
4720 | #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS | |
4721 | ||
4722 | /* The current iteration number of this LRA pass. */ | |
4723 | int lra_constraint_iter; | |
4724 | ||
7436a1c6 VM |
4725 | /* True if we should during assignment sub-pass check assignment |
4726 | correctness for all pseudos and spill some of them to correct | |
4727 | conflicts. It can be necessary when we substitute equiv which | |
4728 | needs checking register allocation correctness because the | |
4729 | equivalent value contains allocatable hard registers, or when we | |
4730 | restore multi-register pseudo, or when we change the insn code and | |
4731 | its operand became INOUT operand when it was IN one before. */ | |
4732 | bool check_and_force_assignment_correctness_p; | |
55a2c322 VM |
4733 | |
4734 | /* Return true if REGNO is referenced in more than one block. */ | |
4735 | static bool | |
4736 | multi_block_pseudo_p (int regno) | |
4737 | { | |
4738 | basic_block bb = NULL; | |
4739 | unsigned int uid; | |
4740 | bitmap_iterator bi; | |
f4eafc30 | 4741 | |
55a2c322 VM |
4742 | if (regno < FIRST_PSEUDO_REGISTER) |
4743 | return false; | |
f4eafc30 | 4744 | |
55a2c322 VM |
4745 | EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi) |
4746 | if (bb == NULL) | |
4747 | bb = BLOCK_FOR_INSN (lra_insn_recog_data[uid]->insn); | |
4748 | else if (BLOCK_FOR_INSN (lra_insn_recog_data[uid]->insn) != bb) | |
4749 | return true; | |
4750 | return false; | |
4751 | } | |
4752 | ||
1966c91b VM |
4753 | /* Return true if LIST contains a deleted insn. */ |
4754 | static bool | |
0cc97fc5 | 4755 | contains_deleted_insn_p (rtx_insn_list *list) |
1966c91b | 4756 | { |
0cc97fc5 DM |
4757 | for (; list != NULL_RTX; list = list->next ()) |
4758 | if (NOTE_P (list->insn ()) | |
4759 | && NOTE_KIND (list->insn ()) == NOTE_INSN_DELETED) | |
1966c91b VM |
4760 | return true; |
4761 | return false; | |
4762 | } | |
4763 | ||
55a2c322 VM |
4764 | /* Return true if X contains a pseudo dying in INSN. */ |
4765 | static bool | |
605780f6 | 4766 | dead_pseudo_p (rtx x, rtx_insn *insn) |
55a2c322 VM |
4767 | { |
4768 | int i, j; | |
4769 | const char *fmt; | |
4770 | enum rtx_code code; | |
4771 | ||
4772 | if (REG_P (x)) | |
4773 | return (insn != NULL_RTX | |
4774 | && find_regno_note (insn, REG_DEAD, REGNO (x)) != NULL_RTX); | |
4775 | code = GET_CODE (x); | |
4776 | fmt = GET_RTX_FORMAT (code); | |
4777 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
4778 | { | |
4779 | if (fmt[i] == 'e') | |
4780 | { | |
4781 | if (dead_pseudo_p (XEXP (x, i), insn)) | |
4782 | return true; | |
4783 | } | |
4784 | else if (fmt[i] == 'E') | |
4785 | { | |
4786 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
4787 | if (dead_pseudo_p (XVECEXP (x, i, j), insn)) | |
4788 | return true; | |
4789 | } | |
4790 | } | |
4791 | return false; | |
4792 | } | |
4793 | ||
4794 | /* Return true if INSN contains a dying pseudo in INSN right hand | |
4795 | side. */ | |
4796 | static bool | |
e8a54173 | 4797 | insn_rhs_dead_pseudo_p (rtx_insn *insn) |
55a2c322 VM |
4798 | { |
4799 | rtx set = single_set (insn); | |
4800 | ||
4801 | gcc_assert (set != NULL); | |
4802 | return dead_pseudo_p (SET_SRC (set), insn); | |
4803 | } | |
4804 | ||
4805 | /* Return true if any init insn of REGNO contains a dying pseudo in | |
4806 | insn right hand side. */ | |
4807 | static bool | |
4808 | init_insn_rhs_dead_pseudo_p (int regno) | |
4809 | { | |
0cc97fc5 | 4810 | rtx_insn_list *insns = ira_reg_equiv[regno].init_insns; |
55a2c322 VM |
4811 | |
4812 | if (insns == NULL) | |
4813 | return false; | |
0cc97fc5 DM |
4814 | for (; insns != NULL_RTX; insns = insns->next ()) |
4815 | if (insn_rhs_dead_pseudo_p (insns->insn ())) | |
55a2c322 VM |
4816 | return true; |
4817 | return false; | |
4818 | } | |
4819 | ||
01e54ef8 VM |
4820 | /* Return TRUE if REGNO has a reverse equivalence. The equivalence is |
4821 | reverse only if we have one init insn with given REGNO as a | |
4822 | source. */ | |
4823 | static bool | |
4824 | reverse_equiv_p (int regno) | |
4825 | { | |
0cc97fc5 DM |
4826 | rtx_insn_list *insns = ira_reg_equiv[regno].init_insns; |
4827 | rtx set; | |
01e54ef8 | 4828 | |
0cc97fc5 | 4829 | if (insns == NULL) |
01e54ef8 | 4830 | return false; |
0cc97fc5 DM |
4831 | if (! INSN_P (insns->insn ()) |
4832 | || insns->next () != NULL) | |
01e54ef8 | 4833 | return false; |
0cc97fc5 | 4834 | if ((set = single_set (insns->insn ())) == NULL_RTX) |
01e54ef8 VM |
4835 | return false; |
4836 | return REG_P (SET_SRC (set)) && (int) REGNO (SET_SRC (set)) == regno; | |
4837 | } | |
4838 | ||
4839 | /* Return TRUE if REGNO was reloaded in an equivalence init insn. We | |
4840 | call this function only for non-reverse equivalence. */ | |
4841 | static bool | |
4842 | contains_reloaded_insn_p (int regno) | |
4843 | { | |
4844 | rtx set; | |
0cc97fc5 | 4845 | rtx_insn_list *list = ira_reg_equiv[regno].init_insns; |
01e54ef8 | 4846 | |
0cc97fc5 DM |
4847 | for (; list != NULL; list = list->next ()) |
4848 | if ((set = single_set (list->insn ())) == NULL_RTX | |
01e54ef8 VM |
4849 | || ! REG_P (SET_DEST (set)) |
4850 | || (int) REGNO (SET_DEST (set)) != regno) | |
4851 | return true; | |
4852 | return false; | |
4853 | } | |
4854 | ||
55a2c322 VM |
4855 | /* Entry function of LRA constraint pass. Return true if the |
4856 | constraint pass did change the code. */ | |
4857 | bool | |
4858 | lra_constraints (bool first_p) | |
4859 | { | |
4860 | bool changed_p; | |
4861 | int i, hard_regno, new_insns_num; | |
6cd1dd26 VM |
4862 | unsigned int min_len, new_min_len, uid; |
4863 | rtx set, x, reg, dest_reg; | |
55a2c322 | 4864 | basic_block last_bb; |
6cd1dd26 | 4865 | bitmap_iterator bi; |
55a2c322 VM |
4866 | |
4867 | lra_constraint_iter++; | |
4868 | if (lra_dump_file != NULL) | |
4869 | fprintf (lra_dump_file, "\n********** Local #%d: **********\n\n", | |
4870 | lra_constraint_iter); | |
55a2c322 | 4871 | changed_p = false; |
bcb21886 KY |
4872 | if (pic_offset_table_rtx |
4873 | && REGNO (pic_offset_table_rtx) >= FIRST_PSEUDO_REGISTER) | |
7436a1c6 VM |
4874 | check_and_force_assignment_correctness_p = true; |
4875 | else if (first_p) | |
15961e4a VM |
4876 | /* On the first iteration we should check IRA assignment |
4877 | correctness. In rare cases, the assignments can be wrong as | |
7e4d17a8 VM |
4878 | early clobbers operands are ignored in IRA or usages of |
4879 | paradoxical sub-registers are not taken into account by | |
4880 | IRA. */ | |
7436a1c6 | 4881 | check_and_force_assignment_correctness_p = true; |
55a2c322 VM |
4882 | new_insn_uid_start = get_max_uid (); |
4883 | new_regno_start = first_p ? lra_constraint_new_regno_start : max_reg_num (); | |
8d49e7ef VM |
4884 | /* Mark used hard regs for target stack size calulations. */ |
4885 | for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++) | |
4886 | if (lra_reg_info[i].nrefs != 0 | |
4887 | && (hard_regno = lra_get_regno_hard_regno (i)) >= 0) | |
4888 | { | |
4889 | int j, nregs; | |
4890 | ||
ad474626 | 4891 | nregs = hard_regno_nregs (hard_regno, lra_reg_info[i].biggest_mode); |
8d49e7ef VM |
4892 | for (j = 0; j < nregs; j++) |
4893 | df_set_regs_ever_live (hard_regno + j, true); | |
4894 | } | |
4895 | /* Do elimination before the equivalence processing as we can spill | |
4896 | some pseudos during elimination. */ | |
4897 | lra_eliminate (false, first_p); | |
d648b5ff | 4898 | auto_bitmap equiv_insn_bitmap (®_obstack); |
55a2c322 VM |
4899 | for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++) |
4900 | if (lra_reg_info[i].nrefs != 0) | |
4901 | { | |
4902 | ira_reg_equiv[i].profitable_p = true; | |
6cd1dd26 | 4903 | reg = regno_reg_rtx[i]; |
8d49e7ef | 4904 | if (lra_get_regno_hard_regno (i) < 0 && (x = get_equiv (reg)) != reg) |
55a2c322 VM |
4905 | { |
4906 | bool pseudo_p = contains_reg_p (x, false, false); | |
55a2c322 | 4907 | |
67914693 | 4908 | /* After RTL transformation, we cannot guarantee that |
1966c91b VM |
4909 | pseudo in the substitution was not reloaded which might |
4910 | make equivalence invalid. For example, in reverse | |
4911 | equiv of p0 | |
4912 | ||
4913 | p0 <- ... | |
4914 | ... | |
4915 | equiv_mem <- p0 | |
4916 | ||
4917 | the memory address register was reloaded before the 2nd | |
4918 | insn. */ | |
4919 | if ((! first_p && pseudo_p) | |
4920 | /* We don't use DF for compilation speed sake. So it | |
4921 | is problematic to update live info when we use an | |
4922 | equivalence containing pseudos in more than one | |
4923 | BB. */ | |
4924 | || (pseudo_p && multi_block_pseudo_p (i)) | |
4925 | /* If an init insn was deleted for some reason, cancel | |
4926 | the equiv. We could update the equiv insns after | |
4927 | transformations including an equiv insn deletion | |
4928 | but it is not worthy as such cases are extremely | |
4929 | rare. */ | |
4930 | || contains_deleted_insn_p (ira_reg_equiv[i].init_insns) | |
55a2c322 VM |
4931 | /* If it is not a reverse equivalence, we check that a |
4932 | pseudo in rhs of the init insn is not dying in the | |
4933 | insn. Otherwise, the live info at the beginning of | |
4934 | the corresponding BB might be wrong after we | |
4935 | removed the insn. When the equiv can be a | |
4936 | constant, the right hand side of the init insn can | |
4937 | be a pseudo. */ | |
01e54ef8 VM |
4938 | || (! reverse_equiv_p (i) |
4939 | && (init_insn_rhs_dead_pseudo_p (i) | |
4940 | /* If we reloaded the pseudo in an equivalence | |
67914693 | 4941 | init insn, we cannot remove the equiv init |
01e54ef8 VM |
4942 | insns and the init insns might write into |
4943 | const memory in this case. */ | |
4944 | || contains_reloaded_insn_p (i))) | |
b28ece32 VM |
4945 | /* Prevent access beyond equivalent memory for |
4946 | paradoxical subregs. */ | |
4947 | || (MEM_P (x) | |
cf098191 RS |
4948 | && maybe_gt (GET_MODE_SIZE (lra_reg_info[i].biggest_mode), |
4949 | GET_MODE_SIZE (GET_MODE (x)))) | |
bcb21886 KY |
4950 | || (pic_offset_table_rtx |
4951 | && ((CONST_POOL_OK_P (PSEUDO_REGNO_MODE (i), x) | |
4952 | && (targetm.preferred_reload_class | |
4953 | (x, lra_get_allocno_class (i)) == NO_REGS)) | |
b81a2f0d | 4954 | || contains_symbol_ref_p (x)))) |
55a2c322 | 4955 | ira_reg_equiv[i].defined_p = false; |
55a2c322 VM |
4956 | if (contains_reg_p (x, false, true)) |
4957 | ira_reg_equiv[i].profitable_p = false; | |
8d49e7ef | 4958 | if (get_equiv (reg) != reg) |
d648b5ff | 4959 | bitmap_ior_into (equiv_insn_bitmap, &lra_reg_info[i].insn_bitmap); |
55a2c322 VM |
4960 | } |
4961 | } | |
4c2b2d79 VM |
4962 | for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++) |
4963 | update_equiv (i); | |
6cd1dd26 VM |
4964 | /* We should add all insns containing pseudos which should be |
4965 | substituted by their equivalences. */ | |
d648b5ff | 4966 | EXECUTE_IF_SET_IN_BITMAP (equiv_insn_bitmap, 0, uid, bi) |
6cd1dd26 | 4967 | lra_push_insn_by_uid (uid); |
55a2c322 VM |
4968 | min_len = lra_insn_stack_length (); |
4969 | new_insns_num = 0; | |
4970 | last_bb = NULL; | |
4971 | changed_p = false; | |
4972 | while ((new_min_len = lra_insn_stack_length ()) != 0) | |
4973 | { | |
4974 | curr_insn = lra_pop_insn (); | |
4975 | --new_min_len; | |
f4eafc30 | 4976 | curr_bb = BLOCK_FOR_INSN (curr_insn); |
55a2c322 VM |
4977 | if (curr_bb != last_bb) |
4978 | { | |
4979 | last_bb = curr_bb; | |
4980 | bb_reload_num = lra_curr_reload_num; | |
4981 | } | |
4982 | if (min_len > new_min_len) | |
4983 | { | |
4984 | min_len = new_min_len; | |
4985 | new_insns_num = 0; | |
4986 | } | |
4987 | if (new_insns_num > MAX_RELOAD_INSNS_NUMBER) | |
4988 | internal_error | |
a9c697b8 | 4989 | ("maximum number of generated reload insns per insn achieved (%d)", |
55a2c322 VM |
4990 | MAX_RELOAD_INSNS_NUMBER); |
4991 | new_insns_num++; | |
4992 | if (DEBUG_INSN_P (curr_insn)) | |
4993 | { | |
4994 | /* We need to check equivalence in debug insn and change | |
4995 | pseudo to the equivalent value if necessary. */ | |
4996 | curr_id = lra_get_insn_recog_data (curr_insn); | |
d648b5ff | 4997 | if (bitmap_bit_p (equiv_insn_bitmap, INSN_UID (curr_insn))) |
4d64ce5c | 4998 | { |
d0608e59 JJ |
4999 | rtx old = *curr_id->operand_loc[0]; |
5000 | *curr_id->operand_loc[0] | |
5001 | = simplify_replace_fn_rtx (old, NULL_RTX, | |
4c2b2d79 | 5002 | loc_equivalence_callback, curr_insn); |
d0608e59 JJ |
5003 | if (old != *curr_id->operand_loc[0]) |
5004 | { | |
5005 | lra_update_insn_regno_info (curr_insn); | |
5006 | changed_p = true; | |
5007 | } | |
4d64ce5c | 5008 | } |
55a2c322 VM |
5009 | } |
5010 | else if (INSN_P (curr_insn)) | |
5011 | { | |
5012 | if ((set = single_set (curr_insn)) != NULL_RTX) | |
5013 | { | |
5014 | dest_reg = SET_DEST (set); | |
5015 | /* The equivalence pseudo could be set up as SUBREG in a | |
5016 | case when it is a call restore insn in a mode | |
5017 | different from the pseudo mode. */ | |
5018 | if (GET_CODE (dest_reg) == SUBREG) | |
5019 | dest_reg = SUBREG_REG (dest_reg); | |
5020 | if ((REG_P (dest_reg) | |
8d49e7ef | 5021 | && (x = get_equiv (dest_reg)) != dest_reg |
55a2c322 | 5022 | /* Remove insns which set up a pseudo whose value |
67914693 | 5023 | cannot be changed. Such insns might be not in |
55a2c322 VM |
5024 | init_insns because we don't update equiv data |
5025 | during insn transformations. | |
5a107a0f | 5026 | |
55a2c322 VM |
5027 | As an example, let suppose that a pseudo got |
5028 | hard register and on the 1st pass was not | |
5029 | changed to equivalent constant. We generate an | |
5030 | additional insn setting up the pseudo because of | |
5031 | secondary memory movement. Then the pseudo is | |
5032 | spilled and we use the equiv constant. In this | |
5033 | case we should remove the additional insn and | |
f6937e32 | 5034 | this insn is not init_insns list. */ |
55a2c322 | 5035 | && (! MEM_P (x) || MEM_READONLY_P (x) |
f6937e32 VM |
5036 | /* Check that this is actually an insn setting |
5037 | up the equivalence. */ | |
55a2c322 VM |
5038 | || in_list_p (curr_insn, |
5039 | ira_reg_equiv | |
5040 | [REGNO (dest_reg)].init_insns))) | |
8d49e7ef | 5041 | || (((x = get_equiv (SET_SRC (set))) != SET_SRC (set)) |
55a2c322 VM |
5042 | && in_list_p (curr_insn, |
5043 | ira_reg_equiv | |
5044 | [REGNO (SET_SRC (set))].init_insns))) | |
5045 | { | |
5046 | /* This is equiv init insn of pseudo which did not get a | |
5047 | hard register -- remove the insn. */ | |
5048 | if (lra_dump_file != NULL) | |
5049 | { | |
5050 | fprintf (lra_dump_file, | |
5051 | " Removing equiv init insn %i (freq=%d)\n", | |
5052 | INSN_UID (curr_insn), | |
fef37404 | 5053 | REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn))); |
cfbeaedf | 5054 | dump_insn_slim (lra_dump_file, curr_insn); |
55a2c322 VM |
5055 | } |
5056 | if (contains_reg_p (x, true, false)) | |
7436a1c6 | 5057 | check_and_force_assignment_correctness_p = true; |
55a2c322 VM |
5058 | lra_set_insn_deleted (curr_insn); |
5059 | continue; | |
5060 | } | |
5061 | } | |
5062 | curr_id = lra_get_insn_recog_data (curr_insn); | |
5063 | curr_static_id = curr_id->insn_static_data; | |
5064 | init_curr_insn_input_reloads (); | |
5065 | init_curr_operand_mode (); | |
d9cf932c | 5066 | if (curr_insn_transform (false)) |
55a2c322 | 5067 | changed_p = true; |
28430b2e VM |
5068 | /* Check non-transformed insns too for equiv change as USE |
5069 | or CLOBBER don't need reloads but can contain pseudos | |
5070 | being changed on their equivalences. */ | |
d648b5ff | 5071 | else if (bitmap_bit_p (equiv_insn_bitmap, INSN_UID (curr_insn)) |
28430b2e VM |
5072 | && loc_equivalence_change_p (&PATTERN (curr_insn))) |
5073 | { | |
5074 | lra_update_insn_regno_info (curr_insn); | |
5075 | changed_p = true; | |
5076 | } | |
55a2c322 VM |
5077 | } |
5078 | } | |
d648b5ff | 5079 | |
55a2c322 VM |
5080 | /* If we used a new hard regno, changed_p should be true because the |
5081 | hard reg is assigned to a new pseudo. */ | |
b2b29377 | 5082 | if (flag_checking && !changed_p) |
55a2c322 VM |
5083 | { |
5084 | for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++) | |
5085 | if (lra_reg_info[i].nrefs != 0 | |
5086 | && (hard_regno = lra_get_regno_hard_regno (i)) >= 0) | |
5087 | { | |
ad474626 RS |
5088 | int j, nregs = hard_regno_nregs (hard_regno, |
5089 | PSEUDO_REGNO_MODE (i)); | |
f4eafc30 | 5090 | |
55a2c322 VM |
5091 | for (j = 0; j < nregs; j++) |
5092 | lra_assert (df_regs_ever_live_p (hard_regno + j)); | |
5093 | } | |
5094 | } | |
55a2c322 VM |
5095 | return changed_p; |
5096 | } | |
5097 | ||
8a8330b7 VM |
5098 | static void initiate_invariants (void); |
5099 | static void finish_invariants (void); | |
5100 | ||
55a2c322 VM |
5101 | /* Initiate the LRA constraint pass. It is done once per |
5102 | function. */ | |
5103 | void | |
5104 | lra_constraints_init (void) | |
5105 | { | |
8a8330b7 | 5106 | initiate_invariants (); |
55a2c322 VM |
5107 | } |
5108 | ||
5109 | /* Finalize the LRA constraint pass. It is done once per | |
5110 | function. */ | |
5111 | void | |
5112 | lra_constraints_finish (void) | |
5113 | { | |
8a8330b7 VM |
5114 | finish_invariants (); |
5115 | } | |
5116 | ||
5117 | \f | |
5118 | ||
5119 | /* Structure describes invariants for ineheritance. */ | |
eb0f8780 | 5120 | struct lra_invariant |
8a8330b7 VM |
5121 | { |
5122 | /* The order number of the invariant. */ | |
5123 | int num; | |
5124 | /* The invariant RTX. */ | |
5125 | rtx invariant_rtx; | |
5126 | /* The origin insn of the invariant. */ | |
5127 | rtx_insn *insn; | |
5128 | }; | |
5129 | ||
eb0f8780 | 5130 | typedef lra_invariant invariant_t; |
8a8330b7 VM |
5131 | typedef invariant_t *invariant_ptr_t; |
5132 | typedef const invariant_t *const_invariant_ptr_t; | |
5133 | ||
5134 | /* Pointer to the inheritance invariants. */ | |
5135 | static vec<invariant_ptr_t> invariants; | |
5136 | ||
5137 | /* Allocation pool for the invariants. */ | |
eb0f8780 | 5138 | static object_allocator<lra_invariant> *invariants_pool; |
8a8330b7 VM |
5139 | |
5140 | /* Hash table for the invariants. */ | |
5141 | static htab_t invariant_table; | |
5142 | ||
5143 | /* Hash function for INVARIANT. */ | |
5144 | static hashval_t | |
5145 | invariant_hash (const void *invariant) | |
5146 | { | |
5147 | rtx inv = ((const_invariant_ptr_t) invariant)->invariant_rtx; | |
5148 | return lra_rtx_hash (inv); | |
5149 | } | |
5150 | ||
5151 | /* Equal function for invariants INVARIANT1 and INVARIANT2. */ | |
5152 | static int | |
5153 | invariant_eq_p (const void *invariant1, const void *invariant2) | |
5154 | { | |
5155 | rtx inv1 = ((const_invariant_ptr_t) invariant1)->invariant_rtx; | |
5156 | rtx inv2 = ((const_invariant_ptr_t) invariant2)->invariant_rtx; | |
5157 | ||
5158 | return rtx_equal_p (inv1, inv2); | |
5159 | } | |
5160 | ||
5161 | /* Insert INVARIANT_RTX into the table if it is not there yet. Return | |
5162 | invariant which is in the table. */ | |
5163 | static invariant_ptr_t | |
5164 | insert_invariant (rtx invariant_rtx) | |
5165 | { | |
5166 | void **entry_ptr; | |
5167 | invariant_t invariant; | |
5168 | invariant_ptr_t invariant_ptr; | |
5169 | ||
5170 | invariant.invariant_rtx = invariant_rtx; | |
5171 | entry_ptr = htab_find_slot (invariant_table, &invariant, INSERT); | |
5172 | if (*entry_ptr == NULL) | |
5173 | { | |
5174 | invariant_ptr = invariants_pool->allocate (); | |
5175 | invariant_ptr->invariant_rtx = invariant_rtx; | |
5176 | invariant_ptr->insn = NULL; | |
5177 | invariants.safe_push (invariant_ptr); | |
5178 | *entry_ptr = (void *) invariant_ptr; | |
5179 | } | |
5180 | return (invariant_ptr_t) *entry_ptr; | |
5181 | } | |
5182 | ||
5183 | /* Initiate the invariant table. */ | |
5184 | static void | |
5185 | initiate_invariants (void) | |
5186 | { | |
5187 | invariants.create (100); | |
eb0f8780 ML |
5188 | invariants_pool |
5189 | = new object_allocator<lra_invariant> ("Inheritance invariants"); | |
8a8330b7 VM |
5190 | invariant_table = htab_create (100, invariant_hash, invariant_eq_p, NULL); |
5191 | } | |
5192 | ||
5193 | /* Finish the invariant table. */ | |
5194 | static void | |
5195 | finish_invariants (void) | |
5196 | { | |
5197 | htab_delete (invariant_table); | |
5198 | delete invariants_pool; | |
5199 | invariants.release (); | |
5200 | } | |
5201 | ||
5202 | /* Make the invariant table empty. */ | |
5203 | static void | |
5204 | clear_invariants (void) | |
5205 | { | |
5206 | htab_empty (invariant_table); | |
5207 | invariants_pool->release (); | |
5208 | invariants.truncate (0); | |
55a2c322 VM |
5209 | } |
5210 | ||
5211 | \f | |
5212 | ||
5213 | /* This page contains code to do inheritance/split | |
5214 | transformations. */ | |
5215 | ||
5216 | /* Number of reloads passed so far in current EBB. */ | |
5217 | static int reloads_num; | |
5218 | ||
5219 | /* Number of calls passed so far in current EBB. */ | |
5220 | static int calls_num; | |
5221 | ||
a1e6ee38 RS |
5222 | /* Index ID is the CALLS_NUM associated the last call we saw with |
5223 | ABI identifier ID. */ | |
5224 | static int last_call_for_abi[NUM_ABI_IDS]; | |
5225 | ||
5226 | /* Which registers have been fully or partially clobbered by a call | |
5227 | since they were last used. */ | |
5228 | static HARD_REG_SET full_and_partial_call_clobbers; | |
5229 | ||
55a2c322 VM |
5230 | /* Current reload pseudo check for validity of elements in |
5231 | USAGE_INSNS. */ | |
5232 | static int curr_usage_insns_check; | |
5233 | ||
5234 | /* Info about last usage of registers in EBB to do inheritance/split | |
5235 | transformation. Inheritance transformation is done from a spilled | |
5236 | pseudo and split transformations from a hard register or a pseudo | |
5237 | assigned to a hard register. */ | |
5238 | struct usage_insns | |
5239 | { | |
5240 | /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member | |
5241 | value INSNS is valid. The insns is chain of optional debug insns | |
1ccd4874 VM |
5242 | and a finishing non-debug insn using the corresponding reg. The |
5243 | value is also used to mark the registers which are set up in the | |
5244 | current insn. The negated insn uid is used for this. */ | |
55a2c322 VM |
5245 | int check; |
5246 | /* Value of global reloads_num at the last insn in INSNS. */ | |
5247 | int reloads_num; | |
5248 | /* Value of global reloads_nums at the last insn in INSNS. */ | |
5249 | int calls_num; | |
5250 | /* It can be true only for splitting. And it means that the restore | |
5251 | insn should be put after insn given by the following member. */ | |
5252 | bool after_p; | |
5253 | /* Next insns in the current EBB which use the original reg and the | |
5254 | original reg value is not changed between the current insn and | |
5255 | the next insns. In order words, e.g. for inheritance, if we need | |
5256 | to use the original reg value again in the next insns we can try | |
5257 | to use the value in a hard register from a reload insn of the | |
5258 | current insn. */ | |
5259 | rtx insns; | |
5260 | }; | |
5261 | ||
5262 | /* Map: regno -> corresponding pseudo usage insns. */ | |
5263 | static struct usage_insns *usage_insns; | |
5264 | ||
5265 | static void | |
1476d1bd | 5266 | setup_next_usage_insn (int regno, rtx insn, int reloads_num, bool after_p) |
55a2c322 VM |
5267 | { |
5268 | usage_insns[regno].check = curr_usage_insns_check; | |
5269 | usage_insns[regno].insns = insn; | |
5270 | usage_insns[regno].reloads_num = reloads_num; | |
5271 | usage_insns[regno].calls_num = calls_num; | |
5272 | usage_insns[regno].after_p = after_p; | |
a1e6ee38 RS |
5273 | if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] >= 0) |
5274 | remove_from_hard_reg_set (&full_and_partial_call_clobbers, | |
5275 | PSEUDO_REGNO_MODE (regno), | |
5276 | reg_renumber[regno]); | |
55a2c322 VM |
5277 | } |
5278 | ||
5279 | /* The function is used to form list REGNO usages which consists of | |
5280 | optional debug insns finished by a non-debug insn using REGNO. | |
5281 | RELOADS_NUM is current number of reload insns processed so far. */ | |
5282 | static void | |
767dc529 | 5283 | add_next_usage_insn (int regno, rtx_insn *insn, int reloads_num) |
55a2c322 VM |
5284 | { |
5285 | rtx next_usage_insns; | |
f4eafc30 | 5286 | |
55a2c322 VM |
5287 | if (usage_insns[regno].check == curr_usage_insns_check |
5288 | && (next_usage_insns = usage_insns[regno].insns) != NULL_RTX | |
5289 | && DEBUG_INSN_P (insn)) | |
5290 | { | |
5291 | /* Check that we did not add the debug insn yet. */ | |
5292 | if (next_usage_insns != insn | |
5293 | && (GET_CODE (next_usage_insns) != INSN_LIST | |
5294 | || XEXP (next_usage_insns, 0) != insn)) | |
5295 | usage_insns[regno].insns = gen_rtx_INSN_LIST (VOIDmode, insn, | |
5296 | next_usage_insns); | |
5297 | } | |
5298 | else if (NONDEBUG_INSN_P (insn)) | |
5299 | setup_next_usage_insn (regno, insn, reloads_num, false); | |
5300 | else | |
5301 | usage_insns[regno].check = 0; | |
5302 | } | |
f4eafc30 | 5303 | |
bc3591eb | 5304 | /* Return first non-debug insn in list USAGE_INSNS. */ |
e8a54173 | 5305 | static rtx_insn * |
bc3591eb VM |
5306 | skip_usage_debug_insns (rtx usage_insns) |
5307 | { | |
5308 | rtx insn; | |
5309 | ||
5310 | /* Skip debug insns. */ | |
5311 | for (insn = usage_insns; | |
5312 | insn != NULL_RTX && GET_CODE (insn) == INSN_LIST; | |
5313 | insn = XEXP (insn, 1)) | |
5314 | ; | |
e8a54173 | 5315 | return safe_as_a <rtx_insn *> (insn); |
bc3591eb VM |
5316 | } |
5317 | ||
5318 | /* Return true if we need secondary memory moves for insn in | |
5319 | USAGE_INSNS after inserting inherited pseudo of class INHER_CL | |
5320 | into the insn. */ | |
5321 | static bool | |
fbebbadd JR |
5322 | check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED, |
5323 | rtx usage_insns ATTRIBUTE_UNUSED) | |
bc3591eb | 5324 | { |
e8a54173 DM |
5325 | rtx_insn *insn; |
5326 | rtx set, dest; | |
bc3591eb VM |
5327 | enum reg_class cl; |
5328 | ||
5329 | if (inher_cl == ALL_REGS | |
5330 | || (insn = skip_usage_debug_insns (usage_insns)) == NULL_RTX) | |
5331 | return false; | |
5332 | lra_assert (INSN_P (insn)); | |
5333 | if ((set = single_set (insn)) == NULL_RTX || ! REG_P (SET_DEST (set))) | |
5334 | return false; | |
5335 | dest = SET_DEST (set); | |
5336 | if (! REG_P (dest)) | |
5337 | return false; | |
5338 | lra_assert (inher_cl != NO_REGS); | |
5339 | cl = get_reg_class (REGNO (dest)); | |
5340 | return (cl != NO_REGS && cl != ALL_REGS | |
f15643d4 | 5341 | && targetm.secondary_memory_needed (GET_MODE (dest), inher_cl, cl)); |
bc3591eb VM |
5342 | } |
5343 | ||
55a2c322 VM |
5344 | /* Registers involved in inheritance/split in the current EBB |
5345 | (inheritance/split pseudos and original registers). */ | |
5346 | static bitmap_head check_only_regs; | |
5347 | ||
67914693 | 5348 | /* Reload pseudos cannot be involded in invariant inheritance in the |
8a8330b7 VM |
5349 | current EBB. */ |
5350 | static bitmap_head invalid_invariant_regs; | |
5351 | ||
55a2c322 VM |
5352 | /* Do inheritance transformations for insn INSN, which defines (if |
5353 | DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which | |
5354 | instruction in the EBB next uses ORIGINAL_REGNO; it has the same | |
5355 | form as the "insns" field of usage_insns. Return true if we | |
5356 | succeed in such transformation. | |
5357 | ||
5358 | The transformations look like: | |
5359 | ||
5360 | p <- ... i <- ... | |
5361 | ... p <- i (new insn) | |
5362 | ... => | |
5363 | <- ... p ... <- ... i ... | |
5364 | or | |
5365 | ... i <- p (new insn) | |
5366 | <- ... p ... <- ... i ... | |
5367 | ... => | |
5368 | <- ... p ... <- ... i ... | |
5369 | where p is a spilled original pseudo and i is a new inheritance pseudo. | |
f4eafc30 L |
5370 | |
5371 | ||
55a2c322 VM |
5372 | The inheritance pseudo has the smallest class of two classes CL and |
5373 | class of ORIGINAL REGNO. */ | |
5374 | static bool | |
5375 | inherit_reload_reg (bool def_p, int original_regno, | |
cfa434f6 | 5376 | enum reg_class cl, rtx_insn *insn, rtx next_usage_insns) |
55a2c322 | 5377 | { |
2ae577fd VM |
5378 | if (optimize_function_for_size_p (cfun)) |
5379 | return false; | |
5380 | ||
55a2c322 VM |
5381 | enum reg_class rclass = lra_get_allocno_class (original_regno); |
5382 | rtx original_reg = regno_reg_rtx[original_regno]; | |
cfa434f6 DM |
5383 | rtx new_reg, usage_insn; |
5384 | rtx_insn *new_insns; | |
55a2c322 VM |
5385 | |
5386 | lra_assert (! usage_insns[original_regno].after_p); | |
5387 | if (lra_dump_file != NULL) | |
5388 | fprintf (lra_dump_file, | |
bc3591eb | 5389 | " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n"); |
55a2c322 VM |
5390 | if (! ira_reg_classes_intersect_p[cl][rclass]) |
5391 | { | |
5392 | if (lra_dump_file != NULL) | |
5393 | { | |
5394 | fprintf (lra_dump_file, | |
bc3591eb | 5395 | " Rejecting inheritance for %d " |
55a2c322 VM |
5396 | "because of disjoint classes %s and %s\n", |
5397 | original_regno, reg_class_names[cl], | |
5398 | reg_class_names[rclass]); | |
5399 | fprintf (lra_dump_file, | |
bc3591eb | 5400 | " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); |
55a2c322 VM |
5401 | } |
5402 | return false; | |
5403 | } | |
5404 | if ((ira_class_subset_p[cl][rclass] && cl != rclass) | |
5405 | /* We don't use a subset of two classes because it can be | |
5406 | NO_REGS. This transformation is still profitable in most | |
5407 | cases even if the classes are not intersected as register | |
5408 | move is probably cheaper than a memory load. */ | |
5409 | || ira_class_hard_regs_num[cl] < ira_class_hard_regs_num[rclass]) | |
5410 | { | |
5411 | if (lra_dump_file != NULL) | |
5412 | fprintf (lra_dump_file, " Use smallest class of %s and %s\n", | |
5413 | reg_class_names[cl], reg_class_names[rclass]); | |
f4eafc30 | 5414 | |
55a2c322 VM |
5415 | rclass = cl; |
5416 | } | |
66aa7879 | 5417 | if (check_secondary_memory_needed_p (rclass, next_usage_insns)) |
bc3591eb VM |
5418 | { |
5419 | /* Reject inheritance resulting in secondary memory moves. | |
5420 | Otherwise, there is a danger in LRA cycling. Also such | |
5421 | transformation will be unprofitable. */ | |
5422 | if (lra_dump_file != NULL) | |
5423 | { | |
e8a54173 | 5424 | rtx_insn *insn = skip_usage_debug_insns (next_usage_insns); |
bc3591eb VM |
5425 | rtx set = single_set (insn); |
5426 | ||
5427 | lra_assert (set != NULL_RTX); | |
5428 | ||
5429 | rtx dest = SET_DEST (set); | |
5430 | ||
5431 | lra_assert (REG_P (dest)); | |
5432 | fprintf (lra_dump_file, | |
5433 | " Rejecting inheritance for insn %d(%s)<-%d(%s) " | |
5434 | "as secondary mem is needed\n", | |
5435 | REGNO (dest), reg_class_names[get_reg_class (REGNO (dest))], | |
66aa7879 | 5436 | original_regno, reg_class_names[rclass]); |
bc3591eb VM |
5437 | fprintf (lra_dump_file, |
5438 | " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); | |
5439 | } | |
5440 | return false; | |
5441 | } | |
55a2c322 VM |
5442 | new_reg = lra_create_new_reg (GET_MODE (original_reg), original_reg, |
5443 | rclass, "inheritance"); | |
5444 | start_sequence (); | |
5445 | if (def_p) | |
a810ee82 | 5446 | lra_emit_move (original_reg, new_reg); |
55a2c322 | 5447 | else |
a810ee82 | 5448 | lra_emit_move (new_reg, original_reg); |
55a2c322 VM |
5449 | new_insns = get_insns (); |
5450 | end_sequence (); | |
5451 | if (NEXT_INSN (new_insns) != NULL_RTX) | |
5452 | { | |
5453 | if (lra_dump_file != NULL) | |
5454 | { | |
5455 | fprintf (lra_dump_file, | |
bc3591eb | 5456 | " Rejecting inheritance %d->%d " |
55a2c322 VM |
5457 | "as it results in 2 or more insns:\n", |
5458 | original_regno, REGNO (new_reg)); | |
dc01c3d1 | 5459 | dump_rtl_slim (lra_dump_file, new_insns, NULL, -1, 0); |
55a2c322 VM |
5460 | fprintf (lra_dump_file, |
5461 | " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); | |
5462 | } | |
5463 | return false; | |
5464 | } | |
ef87312e | 5465 | lra_substitute_pseudo_within_insn (insn, original_regno, new_reg, false); |
55a2c322 VM |
5466 | lra_update_insn_regno_info (insn); |
5467 | if (! def_p) | |
5468 | /* We now have a new usage insn for original regno. */ | |
5469 | setup_next_usage_insn (original_regno, new_insns, reloads_num, false); | |
5470 | if (lra_dump_file != NULL) | |
bc3591eb | 5471 | fprintf (lra_dump_file, " Original reg change %d->%d (bb%d):\n", |
55a2c322 | 5472 | original_regno, REGNO (new_reg), BLOCK_FOR_INSN (insn)->index); |
8a8330b7 | 5473 | lra_reg_info[REGNO (new_reg)].restore_rtx = regno_reg_rtx[original_regno]; |
55a2c322 VM |
5474 | bitmap_set_bit (&check_only_regs, REGNO (new_reg)); |
5475 | bitmap_set_bit (&check_only_regs, original_regno); | |
5476 | bitmap_set_bit (&lra_inheritance_pseudos, REGNO (new_reg)); | |
5477 | if (def_p) | |
cfa434f6 | 5478 | lra_process_new_insns (insn, NULL, new_insns, |
55a2c322 VM |
5479 | "Add original<-inheritance"); |
5480 | else | |
cfa434f6 | 5481 | lra_process_new_insns (insn, new_insns, NULL, |
55a2c322 VM |
5482 | "Add inheritance<-original"); |
5483 | while (next_usage_insns != NULL_RTX) | |
5484 | { | |
5485 | if (GET_CODE (next_usage_insns) != INSN_LIST) | |
5486 | { | |
5487 | usage_insn = next_usage_insns; | |
5488 | lra_assert (NONDEBUG_INSN_P (usage_insn)); | |
5489 | next_usage_insns = NULL; | |
5490 | } | |
5491 | else | |
5492 | { | |
5493 | usage_insn = XEXP (next_usage_insns, 0); | |
5494 | lra_assert (DEBUG_INSN_P (usage_insn)); | |
5495 | next_usage_insns = XEXP (next_usage_insns, 1); | |
5496 | } | |
33006d53 JJ |
5497 | lra_substitute_pseudo (&usage_insn, original_regno, new_reg, false, |
5498 | DEBUG_INSN_P (usage_insn)); | |
cfa434f6 | 5499 | lra_update_insn_regno_info (as_a <rtx_insn *> (usage_insn)); |
55a2c322 VM |
5500 | if (lra_dump_file != NULL) |
5501 | { | |
96a95ac1 | 5502 | basic_block bb = BLOCK_FOR_INSN (usage_insn); |
55a2c322 VM |
5503 | fprintf (lra_dump_file, |
5504 | " Inheritance reuse change %d->%d (bb%d):\n", | |
5505 | original_regno, REGNO (new_reg), | |
96a95ac1 | 5506 | bb ? bb->index : -1); |
1476d1bd | 5507 | dump_insn_slim (lra_dump_file, as_a <rtx_insn *> (usage_insn)); |
55a2c322 VM |
5508 | } |
5509 | } | |
5510 | if (lra_dump_file != NULL) | |
5511 | fprintf (lra_dump_file, | |
5512 | " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); | |
5513 | return true; | |
5514 | } | |
5515 | ||
5516 | /* Return true if we need a caller save/restore for pseudo REGNO which | |
5517 | was assigned to a hard register. */ | |
5518 | static inline bool | |
5519 | need_for_call_save_p (int regno) | |
5520 | { | |
5521 | lra_assert (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] >= 0); | |
a1e6ee38 RS |
5522 | if (usage_insns[regno].calls_num < calls_num) |
5523 | { | |
5524 | unsigned int abis = 0; | |
5525 | for (unsigned int i = 0; i < NUM_ABI_IDS; ++i) | |
5526 | if (last_call_for_abi[i] > usage_insns[regno].calls_num) | |
5527 | abis |= 1 << i; | |
5528 | gcc_assert (abis); | |
5529 | if (call_clobbered_in_region_p (abis, full_and_partial_call_clobbers, | |
5530 | PSEUDO_REGNO_MODE (regno), | |
5531 | reg_renumber[regno])) | |
5532 | return true; | |
5533 | } | |
5534 | return false; | |
55a2c322 VM |
5535 | } |
5536 | ||
1aa95df7 | 5537 | /* Global registers occurring in the current EBB. */ |
55a2c322 VM |
5538 | static bitmap_head ebb_global_regs; |
5539 | ||
5540 | /* Return true if we need a split for hard register REGNO or pseudo | |
5541 | REGNO which was assigned to a hard register. | |
5542 | POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be | |
5543 | used for reloads since the EBB end. It is an approximation of the | |
5544 | used hard registers in the split range. The exact value would | |
5545 | require expensive calculations. If we were aggressive with | |
5546 | splitting because of the approximation, the split pseudo will save | |
5547 | the same hard register assignment and will be removed in the undo | |
5548 | pass. We still need the approximation because too aggressive | |
5549 | splitting would result in too inaccurate cost calculation in the | |
5550 | assignment pass because of too many generated moves which will be | |
5551 | probably removed in the undo pass. */ | |
5552 | static inline bool | |
5553 | need_for_split_p (HARD_REG_SET potential_reload_hard_regs, int regno) | |
5554 | { | |
5555 | int hard_regno = regno < FIRST_PSEUDO_REGISTER ? regno : reg_renumber[regno]; | |
5556 | ||
5557 | lra_assert (hard_regno >= 0); | |
5558 | return ((TEST_HARD_REG_BIT (potential_reload_hard_regs, hard_regno) | |
5559 | /* Don't split eliminable hard registers, otherwise we can | |
5560 | split hard registers like hard frame pointer, which | |
5561 | lives on BB start/end according to DF-infrastructure, | |
5562 | when there is a pseudo assigned to the register and | |
5563 | living in the same BB. */ | |
5564 | && (regno >= FIRST_PSEUDO_REGISTER | |
5565 | || ! TEST_HARD_REG_BIT (eliminable_regset, hard_regno)) | |
5566 | && ! TEST_HARD_REG_BIT (lra_no_alloc_regs, hard_regno) | |
e32e4c4a VM |
5567 | /* Don't split call clobbered hard regs living through |
5568 | calls, otherwise we might have a check problem in the | |
5569 | assign sub-pass as in the most cases (exception is a | |
7436a1c6 | 5570 | situation when check_and_force_assignment_correctness_p value is |
e32e4c4a VM |
5571 | true) the assign pass assumes that all pseudos living |
5572 | through calls are assigned to call saved hard regs. */ | |
5573 | && (regno >= FIRST_PSEUDO_REGISTER | |
a1e6ee38 | 5574 | || !TEST_HARD_REG_BIT (full_and_partial_call_clobbers, regno)) |
55a2c322 VM |
5575 | /* We need at least 2 reloads to make pseudo splitting |
5576 | profitable. We should provide hard regno splitting in | |
5577 | any case to solve 1st insn scheduling problem when | |
5578 | moving hard register definition up might result in | |
5579 | impossibility to find hard register for reload pseudo of | |
5580 | small register class. */ | |
5581 | && (usage_insns[regno].reloads_num | |
8e9d68a9 | 5582 | + (regno < FIRST_PSEUDO_REGISTER ? 0 : 3) < reloads_num) |
55a2c322 VM |
5583 | && (regno < FIRST_PSEUDO_REGISTER |
5584 | /* For short living pseudos, spilling + inheritance can | |
5585 | be considered a substitution for splitting. | |
5586 | Therefore we do not splitting for local pseudos. It | |
5587 | decreases also aggressiveness of splitting. The | |
5588 | minimal number of references is chosen taking into | |
5589 | account that for 2 references splitting has no sense | |
5590 | as we can just spill the pseudo. */ | |
5591 | || (regno >= FIRST_PSEUDO_REGISTER | |
5592 | && lra_reg_info[regno].nrefs > 3 | |
5593 | && bitmap_bit_p (&ebb_global_regs, regno)))) | |
5594 | || (regno >= FIRST_PSEUDO_REGISTER && need_for_call_save_p (regno))); | |
5595 | } | |
5596 | ||
5597 | /* Return class for the split pseudo created from original pseudo with | |
5598 | ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We | |
5599 | choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and | |
5600 | results in no secondary memory movements. */ | |
5601 | static enum reg_class | |
5602 | choose_split_class (enum reg_class allocno_class, | |
5603 | int hard_regno ATTRIBUTE_UNUSED, | |
ef4bddc2 | 5604 | machine_mode mode ATTRIBUTE_UNUSED) |
55a2c322 | 5605 | { |
55a2c322 VM |
5606 | int i; |
5607 | enum reg_class cl, best_cl = NO_REGS; | |
ef4dbe49 JR |
5608 | enum reg_class hard_reg_class ATTRIBUTE_UNUSED |
5609 | = REGNO_REG_CLASS (hard_regno); | |
f4eafc30 | 5610 | |
f15643d4 | 5611 | if (! targetm.secondary_memory_needed (mode, allocno_class, allocno_class) |
55a2c322 VM |
5612 | && TEST_HARD_REG_BIT (reg_class_contents[allocno_class], hard_regno)) |
5613 | return allocno_class; | |
5614 | for (i = 0; | |
5615 | (cl = reg_class_subclasses[allocno_class][i]) != LIM_REG_CLASSES; | |
5616 | i++) | |
f15643d4 RS |
5617 | if (! targetm.secondary_memory_needed (mode, cl, hard_reg_class) |
5618 | && ! targetm.secondary_memory_needed (mode, hard_reg_class, cl) | |
55a2c322 VM |
5619 | && TEST_HARD_REG_BIT (reg_class_contents[cl], hard_regno) |
5620 | && (best_cl == NO_REGS | |
5621 | || ira_class_hard_regs_num[best_cl] < ira_class_hard_regs_num[cl])) | |
5622 | best_cl = cl; | |
5623 | return best_cl; | |
55a2c322 VM |
5624 | } |
5625 | ||
8ffa3150 RS |
5626 | /* Copy any equivalence information from ORIGINAL_REGNO to NEW_REGNO. |
5627 | It only makes sense to call this function if NEW_REGNO is always | |
5628 | equal to ORIGINAL_REGNO. */ | |
5629 | ||
5630 | static void | |
5631 | lra_copy_reg_equiv (unsigned int new_regno, unsigned int original_regno) | |
5632 | { | |
5633 | if (!ira_reg_equiv[original_regno].defined_p) | |
5634 | return; | |
5635 | ||
5636 | ira_expand_reg_equiv (); | |
5637 | ira_reg_equiv[new_regno].defined_p = true; | |
5638 | if (ira_reg_equiv[original_regno].memory) | |
5639 | ira_reg_equiv[new_regno].memory | |
5640 | = copy_rtx (ira_reg_equiv[original_regno].memory); | |
5641 | if (ira_reg_equiv[original_regno].constant) | |
5642 | ira_reg_equiv[new_regno].constant | |
5643 | = copy_rtx (ira_reg_equiv[original_regno].constant); | |
5644 | if (ira_reg_equiv[original_regno].invariant) | |
5645 | ira_reg_equiv[new_regno].invariant | |
5646 | = copy_rtx (ira_reg_equiv[original_regno].invariant); | |
5647 | } | |
5648 | ||
55a2c322 VM |
5649 | /* Do split transformations for insn INSN, which defines or uses |
5650 | ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in | |
5651 | the EBB next uses ORIGINAL_REGNO; it has the same form as the | |
6027ea4c | 5652 | "insns" field of usage_insns. If TO is not NULL, we don't use |
037586dd VM |
5653 | usage_insns, we put restore insns after TO insn. It is a case when |
5654 | we call it from lra_split_hard_reg_for, outside the inheritance | |
5655 | pass. | |
55a2c322 VM |
5656 | |
5657 | The transformations look like: | |
5658 | ||
5659 | p <- ... p <- ... | |
5660 | ... s <- p (new insn -- save) | |
5661 | ... => | |
5662 | ... p <- s (new insn -- restore) | |
5663 | <- ... p ... <- ... p ... | |
5664 | or | |
5665 | <- ... p ... <- ... p ... | |
5666 | ... s <- p (new insn -- save) | |
5667 | ... => | |
5668 | ... p <- s (new insn -- restore) | |
5669 | <- ... p ... <- ... p ... | |
5670 | ||
5671 | where p is an original pseudo got a hard register or a hard | |
5672 | register and s is a new split pseudo. The save is put before INSN | |
5673 | if BEFORE_P is true. Return true if we succeed in such | |
5674 | transformation. */ | |
5675 | static bool | |
cfa434f6 | 5676 | split_reg (bool before_p, int original_regno, rtx_insn *insn, |
6027ea4c | 5677 | rtx next_usage_insns, rtx_insn *to) |
55a2c322 VM |
5678 | { |
5679 | enum reg_class rclass; | |
5680 | rtx original_reg; | |
77bce07c | 5681 | int hard_regno, nregs; |
cfa434f6 DM |
5682 | rtx new_reg, usage_insn; |
5683 | rtx_insn *restore, *save; | |
55a2c322 VM |
5684 | bool after_p; |
5685 | bool call_save_p; | |
3cbf012a | 5686 | machine_mode mode; |
55a2c322 VM |
5687 | |
5688 | if (original_regno < FIRST_PSEUDO_REGISTER) | |
5689 | { | |
5690 | rclass = ira_allocno_class_translate[REGNO_REG_CLASS (original_regno)]; | |
5691 | hard_regno = original_regno; | |
5692 | call_save_p = false; | |
77bce07c | 5693 | nregs = 1; |
3cbf012a BS |
5694 | mode = lra_reg_info[hard_regno].biggest_mode; |
5695 | machine_mode reg_rtx_mode = GET_MODE (regno_reg_rtx[hard_regno]); | |
5c6a601c BS |
5696 | /* A reg can have a biggest_mode of VOIDmode if it was only ever seen |
5697 | as part of a multi-word register. In that case, or if the biggest | |
5698 | mode was larger than a register, just use the reg_rtx. Otherwise, | |
5699 | limit the size to that of the biggest access in the function. */ | |
5700 | if (mode == VOIDmode | |
03a95621 | 5701 | || paradoxical_subreg_p (mode, reg_rtx_mode)) |
3cbf012a BS |
5702 | { |
5703 | original_reg = regno_reg_rtx[hard_regno]; | |
5704 | mode = reg_rtx_mode; | |
5705 | } | |
5706 | else | |
5707 | original_reg = gen_rtx_REG (mode, hard_regno); | |
55a2c322 VM |
5708 | } |
5709 | else | |
5710 | { | |
3cbf012a | 5711 | mode = PSEUDO_REGNO_MODE (original_regno); |
55a2c322 | 5712 | hard_regno = reg_renumber[original_regno]; |
ad474626 | 5713 | nregs = hard_regno_nregs (hard_regno, mode); |
55a2c322 VM |
5714 | rclass = lra_get_allocno_class (original_regno); |
5715 | original_reg = regno_reg_rtx[original_regno]; | |
5716 | call_save_p = need_for_call_save_p (original_regno); | |
5717 | } | |
55a2c322 VM |
5718 | lra_assert (hard_regno >= 0); |
5719 | if (lra_dump_file != NULL) | |
5720 | fprintf (lra_dump_file, | |
5721 | " ((((((((((((((((((((((((((((((((((((((((((((((((\n"); | |
3cbf012a | 5722 | |
55a2c322 VM |
5723 | if (call_save_p) |
5724 | { | |
cb1cca12 | 5725 | mode = HARD_REGNO_CALLER_SAVE_MODE (hard_regno, |
ad474626 | 5726 | hard_regno_nregs (hard_regno, mode), |
cb1cca12 VM |
5727 | mode); |
5728 | new_reg = lra_create_new_reg (mode, NULL_RTX, NO_REGS, "save"); | |
55a2c322 VM |
5729 | } |
5730 | else | |
5731 | { | |
3cbf012a | 5732 | rclass = choose_split_class (rclass, hard_regno, mode); |
55a2c322 VM |
5733 | if (rclass == NO_REGS) |
5734 | { | |
5735 | if (lra_dump_file != NULL) | |
5736 | { | |
5737 | fprintf (lra_dump_file, | |
5738 | " Rejecting split of %d(%s): " | |
5739 | "no good reg class for %d(%s)\n", | |
5740 | original_regno, | |
5741 | reg_class_names[lra_get_allocno_class (original_regno)], | |
5742 | hard_regno, | |
5743 | reg_class_names[REGNO_REG_CLASS (hard_regno)]); | |
5744 | fprintf | |
5745 | (lra_dump_file, | |
5746 | " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); | |
5747 | } | |
5748 | return false; | |
5749 | } | |
1b51df94 MF |
5750 | /* Split_if_necessary can split hard registers used as part of a |
5751 | multi-register mode but splits each register individually. The | |
5752 | mode used for each independent register may not be supported | |
5753 | so reject the split. Splitting the wider mode should theoretically | |
5754 | be possible but is not implemented. */ | |
f939c3e6 | 5755 | if (!targetm.hard_regno_mode_ok (hard_regno, mode)) |
1b51df94 MF |
5756 | { |
5757 | if (lra_dump_file != NULL) | |
5758 | { | |
5759 | fprintf (lra_dump_file, | |
5760 | " Rejecting split of %d(%s): unsuitable mode %s\n", | |
5761 | original_regno, | |
5762 | reg_class_names[lra_get_allocno_class (original_regno)], | |
5763 | GET_MODE_NAME (mode)); | |
5764 | fprintf | |
5765 | (lra_dump_file, | |
5766 | " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); | |
5767 | } | |
5768 | return false; | |
5769 | } | |
3cbf012a | 5770 | new_reg = lra_create_new_reg (mode, original_reg, rclass, "split"); |
55a2c322 VM |
5771 | reg_renumber[REGNO (new_reg)] = hard_regno; |
5772 | } | |
8ffa3150 | 5773 | int new_regno = REGNO (new_reg); |
55a2c322 | 5774 | save = emit_spill_move (true, new_reg, original_reg); |
c61fe0cc | 5775 | if (NEXT_INSN (save) != NULL_RTX && !call_save_p) |
55a2c322 | 5776 | { |
55a2c322 VM |
5777 | if (lra_dump_file != NULL) |
5778 | { | |
5779 | fprintf | |
5780 | (lra_dump_file, | |
c61fe0cc | 5781 | " Rejecting split %d->%d resulting in > 2 save insns:\n", |
8ffa3150 | 5782 | original_regno, new_regno); |
dc01c3d1 | 5783 | dump_rtl_slim (lra_dump_file, save, NULL, -1, 0); |
55a2c322 VM |
5784 | fprintf (lra_dump_file, |
5785 | " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); | |
5786 | } | |
5787 | return false; | |
5788 | } | |
5789 | restore = emit_spill_move (false, new_reg, original_reg); | |
c61fe0cc | 5790 | if (NEXT_INSN (restore) != NULL_RTX && !call_save_p) |
55a2c322 | 5791 | { |
55a2c322 VM |
5792 | if (lra_dump_file != NULL) |
5793 | { | |
5794 | fprintf (lra_dump_file, | |
5795 | " Rejecting split %d->%d " | |
c61fe0cc | 5796 | "resulting in > 2 restore insns:\n", |
8ffa3150 | 5797 | original_regno, new_regno); |
dc01c3d1 | 5798 | dump_rtl_slim (lra_dump_file, restore, NULL, -1, 0); |
55a2c322 VM |
5799 | fprintf (lra_dump_file, |
5800 | " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); | |
5801 | } | |
5802 | return false; | |
5803 | } | |
8ffa3150 RS |
5804 | /* Transfer equivalence information to the spill register, so that |
5805 | if we fail to allocate the spill register, we have the option of | |
5806 | rematerializing the original value instead of spilling to the stack. */ | |
5807 | if (!HARD_REGISTER_NUM_P (original_regno) | |
5808 | && mode == PSEUDO_REGNO_MODE (original_regno)) | |
5809 | lra_copy_reg_equiv (new_regno, original_regno); | |
8ffa3150 | 5810 | lra_reg_info[new_regno].restore_rtx = regno_reg_rtx[original_regno]; |
8ffa3150 | 5811 | bitmap_set_bit (&lra_split_regs, new_regno); |
6027ea4c | 5812 | if (to != NULL) |
55a2c322 | 5813 | { |
037586dd | 5814 | lra_assert (next_usage_insns == NULL); |
6027ea4c VM |
5815 | usage_insn = to; |
5816 | after_p = TRUE; | |
5817 | } | |
5818 | else | |
5819 | { | |
037586dd VM |
5820 | /* We need check_only_regs only inside the inheritance pass. */ |
5821 | bitmap_set_bit (&check_only_regs, new_regno); | |
5822 | bitmap_set_bit (&check_only_regs, original_regno); | |
6027ea4c VM |
5823 | after_p = usage_insns[original_regno].after_p; |
5824 | for (;;) | |
b3231b65 | 5825 | { |
6027ea4c VM |
5826 | if (GET_CODE (next_usage_insns) != INSN_LIST) |
5827 | { | |
5828 | usage_insn = next_usage_insns; | |
5829 | break; | |
5830 | } | |
5831 | usage_insn = XEXP (next_usage_insns, 0); | |
5832 | lra_assert (DEBUG_INSN_P (usage_insn)); | |
5833 | next_usage_insns = XEXP (next_usage_insns, 1); | |
5834 | lra_substitute_pseudo (&usage_insn, original_regno, new_reg, false, | |
5835 | true); | |
5836 | lra_update_insn_regno_info (as_a <rtx_insn *> (usage_insn)); | |
5837 | if (lra_dump_file != NULL) | |
5838 | { | |
5839 | fprintf (lra_dump_file, " Split reuse change %d->%d:\n", | |
5840 | original_regno, new_regno); | |
5841 | dump_insn_slim (lra_dump_file, as_a <rtx_insn *> (usage_insn)); | |
5842 | } | |
55a2c322 VM |
5843 | } |
5844 | } | |
5845 | lra_assert (NOTE_P (usage_insn) || NONDEBUG_INSN_P (usage_insn)); | |
5846 | lra_assert (usage_insn != insn || (after_p && before_p)); | |
cfa434f6 DM |
5847 | lra_process_new_insns (as_a <rtx_insn *> (usage_insn), |
5848 | after_p ? NULL : restore, | |
5849 | after_p ? restore : NULL, | |
55a2c322 VM |
5850 | call_save_p |
5851 | ? "Add reg<-save" : "Add reg<-split"); | |
cfa434f6 DM |
5852 | lra_process_new_insns (insn, before_p ? save : NULL, |
5853 | before_p ? NULL : save, | |
55a2c322 VM |
5854 | call_save_p |
5855 | ? "Add save<-reg" : "Add split<-reg"); | |
77bce07c VM |
5856 | if (nregs > 1) |
5857 | /* If we are trying to split multi-register. We should check | |
5858 | conflicts on the next assignment sub-pass. IRA can allocate on | |
5859 | sub-register levels, LRA do this on pseudos level right now and | |
5860 | this discrepancy may create allocation conflicts after | |
5861 | splitting. */ | |
7436a1c6 | 5862 | check_and_force_assignment_correctness_p = true; |
55a2c322 VM |
5863 | if (lra_dump_file != NULL) |
5864 | fprintf (lra_dump_file, | |
5865 | " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); | |
5866 | return true; | |
5867 | } | |
5868 | ||
6027ea4c VM |
5869 | /* Split a hard reg for reload pseudo REGNO having RCLASS and living |
5870 | in the range [FROM, TO]. Return true if did a split. Otherwise, | |
5871 | return false. */ | |
5872 | bool | |
5873 | spill_hard_reg_in_range (int regno, enum reg_class rclass, rtx_insn *from, rtx_insn *to) | |
5874 | { | |
5875 | int i, hard_regno; | |
5876 | int rclass_size; | |
5877 | rtx_insn *insn; | |
7293e3f5 VM |
5878 | unsigned int uid; |
5879 | bitmap_iterator bi; | |
5880 | HARD_REG_SET ignore; | |
6027ea4c VM |
5881 | |
5882 | lra_assert (from != NULL && to != NULL); | |
7293e3f5 VM |
5883 | CLEAR_HARD_REG_SET (ignore); |
5884 | EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi) | |
5885 | { | |
5886 | lra_insn_recog_data_t id = lra_insn_recog_data[uid]; | |
5887 | struct lra_static_insn_data *static_id = id->insn_static_data; | |
5888 | struct lra_insn_reg *reg; | |
5889 | ||
5890 | for (reg = id->regs; reg != NULL; reg = reg->next) | |
65e87462 | 5891 | if (reg->regno < FIRST_PSEUDO_REGISTER) |
7293e3f5 VM |
5892 | SET_HARD_REG_BIT (ignore, reg->regno); |
5893 | for (reg = static_id->hard_regs; reg != NULL; reg = reg->next) | |
5894 | SET_HARD_REG_BIT (ignore, reg->regno); | |
5895 | } | |
6027ea4c VM |
5896 | rclass_size = ira_class_hard_regs_num[rclass]; |
5897 | for (i = 0; i < rclass_size; i++) | |
5898 | { | |
5899 | hard_regno = ira_class_hard_regs[rclass][i]; | |
7293e3f5 VM |
5900 | if (! TEST_HARD_REG_BIT (lra_reg_info[regno].conflict_hard_regs, hard_regno) |
5901 | || TEST_HARD_REG_BIT (ignore, hard_regno)) | |
6027ea4c VM |
5902 | continue; |
5903 | for (insn = from; insn != NEXT_INSN (to); insn = NEXT_INSN (insn)) | |
dc843a85 | 5904 | { |
3664a0f1 | 5905 | struct lra_static_insn_data *static_id; |
dc843a85 IL |
5906 | struct lra_insn_reg *reg; |
5907 | ||
3664a0f1 IL |
5908 | if (!INSN_P (insn)) |
5909 | continue; | |
5910 | if (bitmap_bit_p (&lra_reg_info[hard_regno].insn_bitmap, | |
5911 | INSN_UID (insn))) | |
dc843a85 | 5912 | break; |
3664a0f1 | 5913 | static_id = lra_get_insn_recog_data (insn)->insn_static_data; |
dc843a85 IL |
5914 | for (reg = static_id->hard_regs; reg != NULL; reg = reg->next) |
5915 | if (reg->regno == hard_regno) | |
5916 | break; | |
5917 | if (reg != NULL) | |
5918 | break; | |
5919 | } | |
6027ea4c VM |
5920 | if (insn != NEXT_INSN (to)) |
5921 | continue; | |
5922 | if (split_reg (TRUE, hard_regno, from, NULL, to)) | |
5923 | return true; | |
5924 | } | |
5925 | return false; | |
5926 | } | |
5927 | ||
55a2c322 VM |
5928 | /* Recognize that we need a split transformation for insn INSN, which |
5929 | defines or uses REGNO in its insn biggest MODE (we use it only if | |
5930 | REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains | |
5931 | hard registers which might be used for reloads since the EBB end. | |
5932 | Put the save before INSN if BEFORE_P is true. MAX_UID is maximla | |
5933 | uid before starting INSN processing. Return true if we succeed in | |
5934 | such transformation. */ | |
5935 | static bool | |
ef4bddc2 | 5936 | split_if_necessary (int regno, machine_mode mode, |
55a2c322 | 5937 | HARD_REG_SET potential_reload_hard_regs, |
cfa434f6 | 5938 | bool before_p, rtx_insn *insn, int max_uid) |
55a2c322 VM |
5939 | { |
5940 | bool res = false; | |
5941 | int i, nregs = 1; | |
5942 | rtx next_usage_insns; | |
5943 | ||
5944 | if (regno < FIRST_PSEUDO_REGISTER) | |
ad474626 | 5945 | nregs = hard_regno_nregs (regno, mode); |
55a2c322 VM |
5946 | for (i = 0; i < nregs; i++) |
5947 | if (usage_insns[regno + i].check == curr_usage_insns_check | |
5948 | && (next_usage_insns = usage_insns[regno + i].insns) != NULL_RTX | |
5949 | /* To avoid processing the register twice or more. */ | |
5950 | && ((GET_CODE (next_usage_insns) != INSN_LIST | |
5951 | && INSN_UID (next_usage_insns) < max_uid) | |
5952 | || (GET_CODE (next_usage_insns) == INSN_LIST | |
5953 | && (INSN_UID (XEXP (next_usage_insns, 0)) < max_uid))) | |
5954 | && need_for_split_p (potential_reload_hard_regs, regno + i) | |
6027ea4c | 5955 | && split_reg (before_p, regno + i, insn, next_usage_insns, NULL)) |
55a2c322 VM |
5956 | res = true; |
5957 | return res; | |
5958 | } | |
5959 | ||
8a8330b7 VM |
5960 | /* Return TRUE if rtx X is considered as an invariant for |
5961 | inheritance. */ | |
5962 | static bool | |
5963 | invariant_p (const_rtx x) | |
5964 | { | |
5965 | machine_mode mode; | |
5966 | const char *fmt; | |
5967 | enum rtx_code code; | |
5968 | int i, j; | |
5969 | ||
850b8aa3 SB |
5970 | if (side_effects_p (x)) |
5971 | return false; | |
5972 | ||
8a8330b7 VM |
5973 | code = GET_CODE (x); |
5974 | mode = GET_MODE (x); | |
5975 | if (code == SUBREG) | |
5976 | { | |
5977 | x = SUBREG_REG (x); | |
5978 | code = GET_CODE (x); | |
bd5a2c67 | 5979 | mode = wider_subreg_mode (mode, GET_MODE (x)); |
8a8330b7 VM |
5980 | } |
5981 | ||
5982 | if (MEM_P (x)) | |
5983 | return false; | |
5984 | ||
5985 | if (REG_P (x)) | |
5986 | { | |
5987 | int i, nregs, regno = REGNO (x); | |
5988 | ||
5989 | if (regno >= FIRST_PSEUDO_REGISTER || regno == STACK_POINTER_REGNUM | |
5990 | || TEST_HARD_REG_BIT (eliminable_regset, regno) | |
5991 | || GET_MODE_CLASS (GET_MODE (x)) == MODE_CC) | |
5992 | return false; | |
ad474626 | 5993 | nregs = hard_regno_nregs (regno, mode); |
8a8330b7 VM |
5994 | for (i = 0; i < nregs; i++) |
5995 | if (! fixed_regs[regno + i] | |
5996 | /* A hard register may be clobbered in the current insn | |
5997 | but we can ignore this case because if the hard | |
5998 | register is used it should be set somewhere after the | |
5999 | clobber. */ | |
6000 | || bitmap_bit_p (&invalid_invariant_regs, regno + i)) | |
6001 | return false; | |
6002 | } | |
6003 | fmt = GET_RTX_FORMAT (code); | |
6004 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
6005 | { | |
6006 | if (fmt[i] == 'e') | |
6007 | { | |
6008 | if (! invariant_p (XEXP (x, i))) | |
6009 | return false; | |
6010 | } | |
6011 | else if (fmt[i] == 'E') | |
6012 | { | |
6013 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
6014 | if (! invariant_p (XVECEXP (x, i, j))) | |
6015 | return false; | |
6016 | } | |
6017 | } | |
6018 | return true; | |
6019 | } | |
6020 | ||
6021 | /* We have 'dest_reg <- invariant'. Let us try to make an invariant | |
6022 | inheritance transformation (using dest_reg instead invariant in a | |
6023 | subsequent insn). */ | |
6024 | static bool | |
6025 | process_invariant_for_inheritance (rtx dst_reg, rtx invariant_rtx) | |
6026 | { | |
6027 | invariant_ptr_t invariant_ptr; | |
6028 | rtx_insn *insn, *new_insns; | |
6029 | rtx insn_set, insn_reg, new_reg; | |
6030 | int insn_regno; | |
6031 | bool succ_p = false; | |
6032 | int dst_regno = REGNO (dst_reg); | |
b8506a8a | 6033 | machine_mode dst_mode = GET_MODE (dst_reg); |
8a8330b7 VM |
6034 | enum reg_class cl = lra_get_allocno_class (dst_regno), insn_reg_cl; |
6035 | ||
6036 | invariant_ptr = insert_invariant (invariant_rtx); | |
6037 | if ((insn = invariant_ptr->insn) != NULL_RTX) | |
6038 | { | |
6039 | /* We have a subsequent insn using the invariant. */ | |
6040 | insn_set = single_set (insn); | |
6041 | lra_assert (insn_set != NULL); | |
6042 | insn_reg = SET_DEST (insn_set); | |
6043 | lra_assert (REG_P (insn_reg)); | |
6044 | insn_regno = REGNO (insn_reg); | |
6045 | insn_reg_cl = lra_get_allocno_class (insn_regno); | |
6046 | ||
6047 | if (dst_mode == GET_MODE (insn_reg) | |
6048 | /* We should consider only result move reg insns which are | |
6049 | cheap. */ | |
6050 | && targetm.register_move_cost (dst_mode, cl, insn_reg_cl) == 2 | |
6051 | && targetm.register_move_cost (dst_mode, cl, cl) == 2) | |
6052 | { | |
6053 | if (lra_dump_file != NULL) | |
6054 | fprintf (lra_dump_file, | |
6055 | " [[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[\n"); | |
6056 | new_reg = lra_create_new_reg (dst_mode, dst_reg, | |
6057 | cl, "invariant inheritance"); | |
6058 | bitmap_set_bit (&lra_inheritance_pseudos, REGNO (new_reg)); | |
6059 | bitmap_set_bit (&check_only_regs, REGNO (new_reg)); | |
b10d44ef | 6060 | lra_reg_info[REGNO (new_reg)].restore_rtx = PATTERN (insn); |
8a8330b7 VM |
6061 | start_sequence (); |
6062 | lra_emit_move (new_reg, dst_reg); | |
6063 | new_insns = get_insns (); | |
6064 | end_sequence (); | |
6065 | lra_process_new_insns (curr_insn, NULL, new_insns, | |
6066 | "Add invariant inheritance<-original"); | |
6067 | start_sequence (); | |
6068 | lra_emit_move (SET_DEST (insn_set), new_reg); | |
6069 | new_insns = get_insns (); | |
6070 | end_sequence (); | |
6071 | lra_process_new_insns (insn, NULL, new_insns, | |
6072 | "Changing reload<-inheritance"); | |
6073 | lra_set_insn_deleted (insn); | |
6074 | succ_p = true; | |
6075 | if (lra_dump_file != NULL) | |
6076 | { | |
6077 | fprintf (lra_dump_file, | |
6078 | " Invariant inheritance reuse change %d (bb%d):\n", | |
6079 | REGNO (new_reg), BLOCK_FOR_INSN (insn)->index); | |
6080 | dump_insn_slim (lra_dump_file, insn); | |
6081 | fprintf (lra_dump_file, | |
6082 | " ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]\n"); | |
6083 | } | |
6084 | } | |
6085 | } | |
6086 | invariant_ptr->insn = curr_insn; | |
6087 | return succ_p; | |
6088 | } | |
6089 | ||
55a2c322 VM |
6090 | /* Check only registers living at the current program point in the |
6091 | current EBB. */ | |
6092 | static bitmap_head live_regs; | |
6093 | ||
6094 | /* Update live info in EBB given by its HEAD and TAIL insns after | |
6095 | inheritance/split transformation. The function removes dead moves | |
6096 | too. */ | |
6097 | static void | |
cfa434f6 | 6098 | update_ebb_live_info (rtx_insn *head, rtx_insn *tail) |
55a2c322 VM |
6099 | { |
6100 | unsigned int j; | |
8e9d68a9 | 6101 | int i, regno; |
55a2c322 | 6102 | bool live_p; |
cfa434f6 DM |
6103 | rtx_insn *prev_insn; |
6104 | rtx set; | |
55a2c322 VM |
6105 | bool remove_p; |
6106 | basic_block last_bb, prev_bb, curr_bb; | |
6107 | bitmap_iterator bi; | |
6108 | struct lra_insn_reg *reg; | |
6109 | edge e; | |
6110 | edge_iterator ei; | |
6111 | ||
f4eafc30 | 6112 | last_bb = BLOCK_FOR_INSN (tail); |
55a2c322 VM |
6113 | prev_bb = NULL; |
6114 | for (curr_insn = tail; | |
6115 | curr_insn != PREV_INSN (head); | |
6116 | curr_insn = prev_insn) | |
6117 | { | |
6118 | prev_insn = PREV_INSN (curr_insn); | |
911598e3 VM |
6119 | /* We need to process empty blocks too. They contain |
6120 | NOTE_INSN_BASIC_BLOCK referring for the basic block. */ | |
6121 | if (NOTE_P (curr_insn) && NOTE_KIND (curr_insn) != NOTE_INSN_BASIC_BLOCK) | |
6122 | continue; | |
55a2c322 VM |
6123 | curr_bb = BLOCK_FOR_INSN (curr_insn); |
6124 | if (curr_bb != prev_bb) | |
6125 | { | |
6126 | if (prev_bb != NULL) | |
6127 | { | |
6128 | /* Update df_get_live_in (prev_bb): */ | |
6129 | EXECUTE_IF_SET_IN_BITMAP (&check_only_regs, 0, j, bi) | |
6130 | if (bitmap_bit_p (&live_regs, j)) | |
6131 | bitmap_set_bit (df_get_live_in (prev_bb), j); | |
6132 | else | |
6133 | bitmap_clear_bit (df_get_live_in (prev_bb), j); | |
6134 | } | |
6135 | if (curr_bb != last_bb) | |
6136 | { | |
6137 | /* Update df_get_live_out (curr_bb): */ | |
6138 | EXECUTE_IF_SET_IN_BITMAP (&check_only_regs, 0, j, bi) | |
6139 | { | |
6140 | live_p = bitmap_bit_p (&live_regs, j); | |
6141 | if (! live_p) | |
6142 | FOR_EACH_EDGE (e, ei, curr_bb->succs) | |
6143 | if (bitmap_bit_p (df_get_live_in (e->dest), j)) | |
6144 | { | |
6145 | live_p = true; | |
6146 | break; | |
6147 | } | |
6148 | if (live_p) | |
6149 | bitmap_set_bit (df_get_live_out (curr_bb), j); | |
6150 | else | |
6151 | bitmap_clear_bit (df_get_live_out (curr_bb), j); | |
6152 | } | |
6153 | } | |
6154 | prev_bb = curr_bb; | |
6155 | bitmap_and (&live_regs, &check_only_regs, df_get_live_out (curr_bb)); | |
6156 | } | |
44b94bdb | 6157 | if (! NONDEBUG_INSN_P (curr_insn)) |
55a2c322 VM |
6158 | continue; |
6159 | curr_id = lra_get_insn_recog_data (curr_insn); | |
8e9d68a9 | 6160 | curr_static_id = curr_id->insn_static_data; |
55a2c322 | 6161 | remove_p = false; |
53250f44 BS |
6162 | if ((set = single_set (curr_insn)) != NULL_RTX |
6163 | && REG_P (SET_DEST (set)) | |
55a2c322 | 6164 | && (regno = REGNO (SET_DEST (set))) >= FIRST_PSEUDO_REGISTER |
53250f44 | 6165 | && SET_DEST (set) != pic_offset_table_rtx |
55a2c322 VM |
6166 | && bitmap_bit_p (&check_only_regs, regno) |
6167 | && ! bitmap_bit_p (&live_regs, regno)) | |
6168 | remove_p = true; | |
6169 | /* See which defined values die here. */ | |
6170 | for (reg = curr_id->regs; reg != NULL; reg = reg->next) | |
6171 | if (reg->type == OP_OUT && ! reg->subreg_p) | |
6172 | bitmap_clear_bit (&live_regs, reg->regno); | |
8e9d68a9 VM |
6173 | for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next) |
6174 | if (reg->type == OP_OUT && ! reg->subreg_p) | |
6175 | bitmap_clear_bit (&live_regs, reg->regno); | |
9d86e84e VM |
6176 | if (curr_id->arg_hard_regs != NULL) |
6177 | /* Make clobbered argument hard registers die. */ | |
6178 | for (i = 0; (regno = curr_id->arg_hard_regs[i]) >= 0; i++) | |
6179 | if (regno >= FIRST_PSEUDO_REGISTER) | |
6180 | bitmap_clear_bit (&live_regs, regno - FIRST_PSEUDO_REGISTER); | |
55a2c322 VM |
6181 | /* Mark each used value as live. */ |
6182 | for (reg = curr_id->regs; reg != NULL; reg = reg->next) | |
d89ae27c | 6183 | if (reg->type != OP_OUT |
55a2c322 VM |
6184 | && bitmap_bit_p (&check_only_regs, reg->regno)) |
6185 | bitmap_set_bit (&live_regs, reg->regno); | |
8e9d68a9 VM |
6186 | for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next) |
6187 | if (reg->type != OP_OUT | |
6188 | && bitmap_bit_p (&check_only_regs, reg->regno)) | |
6189 | bitmap_set_bit (&live_regs, reg->regno); | |
6190 | if (curr_id->arg_hard_regs != NULL) | |
9d86e84e | 6191 | /* Make used argument hard registers live. */ |
8e9d68a9 | 6192 | for (i = 0; (regno = curr_id->arg_hard_regs[i]) >= 0; i++) |
9d86e84e VM |
6193 | if (regno < FIRST_PSEUDO_REGISTER |
6194 | && bitmap_bit_p (&check_only_regs, regno)) | |
8e9d68a9 | 6195 | bitmap_set_bit (&live_regs, regno); |
55a2c322 VM |
6196 | /* It is quite important to remove dead move insns because it |
6197 | means removing dead store. We don't need to process them for | |
6198 | constraints. */ | |
6199 | if (remove_p) | |
6200 | { | |
6201 | if (lra_dump_file != NULL) | |
6202 | { | |
6203 | fprintf (lra_dump_file, " Removing dead insn:\n "); | |
cfbeaedf | 6204 | dump_insn_slim (lra_dump_file, curr_insn); |
55a2c322 VM |
6205 | } |
6206 | lra_set_insn_deleted (curr_insn); | |
6207 | } | |
6208 | } | |
6209 | } | |
6210 | ||
6211 | /* The structure describes info to do an inheritance for the current | |
6212 | insn. We need to collect such info first before doing the | |
6213 | transformations because the transformations change the insn | |
6214 | internal representation. */ | |
6215 | struct to_inherit | |
6216 | { | |
6217 | /* Original regno. */ | |
6218 | int regno; | |
6219 | /* Subsequent insns which can inherit original reg value. */ | |
6220 | rtx insns; | |
6221 | }; | |
6222 | ||
6223 | /* Array containing all info for doing inheritance from the current | |
6224 | insn. */ | |
6225 | static struct to_inherit to_inherit[LRA_MAX_INSN_RELOADS]; | |
6226 | ||
6227 | /* Number elements in the previous array. */ | |
6228 | static int to_inherit_num; | |
6229 | ||
6230 | /* Add inheritance info REGNO and INSNS. Their meaning is described in | |
6231 | structure to_inherit. */ | |
6232 | static void | |
6233 | add_to_inherit (int regno, rtx insns) | |
6234 | { | |
6235 | int i; | |
6236 | ||
6237 | for (i = 0; i < to_inherit_num; i++) | |
6238 | if (to_inherit[i].regno == regno) | |
6239 | return; | |
6240 | lra_assert (to_inherit_num < LRA_MAX_INSN_RELOADS); | |
6241 | to_inherit[to_inherit_num].regno = regno; | |
6242 | to_inherit[to_inherit_num++].insns = insns; | |
6243 | } | |
6244 | ||
6245 | /* Return the last non-debug insn in basic block BB, or the block begin | |
6246 | note if none. */ | |
cfa434f6 | 6247 | static rtx_insn * |
55a2c322 VM |
6248 | get_last_insertion_point (basic_block bb) |
6249 | { | |
cfa434f6 | 6250 | rtx_insn *insn; |
55a2c322 VM |
6251 | |
6252 | FOR_BB_INSNS_REVERSE (bb, insn) | |
6253 | if (NONDEBUG_INSN_P (insn) || NOTE_INSN_BASIC_BLOCK_P (insn)) | |
6254 | return insn; | |
6255 | gcc_unreachable (); | |
6256 | } | |
6257 | ||
6258 | /* Set up RES by registers living on edges FROM except the edge (FROM, | |
6259 | TO) or by registers set up in a jump insn in BB FROM. */ | |
6260 | static void | |
6261 | get_live_on_other_edges (basic_block from, basic_block to, bitmap res) | |
6262 | { | |
cfa434f6 | 6263 | rtx_insn *last; |
55a2c322 VM |
6264 | struct lra_insn_reg *reg; |
6265 | edge e; | |
6266 | edge_iterator ei; | |
6267 | ||
6268 | lra_assert (to != NULL); | |
6269 | bitmap_clear (res); | |
6270 | FOR_EACH_EDGE (e, ei, from->succs) | |
6271 | if (e->dest != to) | |
6272 | bitmap_ior_into (res, df_get_live_in (e->dest)); | |
6273 | last = get_last_insertion_point (from); | |
6274 | if (! JUMP_P (last)) | |
6275 | return; | |
6276 | curr_id = lra_get_insn_recog_data (last); | |
6277 | for (reg = curr_id->regs; reg != NULL; reg = reg->next) | |
6278 | if (reg->type != OP_IN) | |
6279 | bitmap_set_bit (res, reg->regno); | |
6280 | } | |
f4eafc30 | 6281 | |
55a2c322 VM |
6282 | /* Used as a temporary results of some bitmap calculations. */ |
6283 | static bitmap_head temp_bitmap; | |
6284 | ||
8e9d68a9 VM |
6285 | /* We split for reloads of small class of hard regs. The following |
6286 | defines how many hard regs the class should have to be qualified as | |
6287 | small. The code is mostly oriented to x86/x86-64 architecture | |
6288 | where some insns need to use only specific register or pair of | |
6289 | registers and these register can live in RTL explicitly, e.g. for | |
6290 | parameter passing. */ | |
6291 | static const int max_small_class_regs_num = 2; | |
6292 | ||
55a2c322 VM |
6293 | /* Do inheritance/split transformations in EBB starting with HEAD and |
6294 | finishing on TAIL. We process EBB insns in the reverse order. | |
6295 | Return true if we did any inheritance/split transformation in the | |
6296 | EBB. | |
6297 | ||
6298 | We should avoid excessive splitting which results in worse code | |
6299 | because of inaccurate cost calculations for spilling new split | |
6300 | pseudos in such case. To achieve this we do splitting only if | |
6301 | register pressure is high in given basic block and there are reload | |
6302 | pseudos requiring hard registers. We could do more register | |
6303 | pressure calculations at any given program point to avoid necessary | |
6304 | splitting even more but it is to expensive and the current approach | |
6305 | works well enough. */ | |
6306 | static bool | |
cfa434f6 | 6307 | inherit_in_ebb (rtx_insn *head, rtx_insn *tail) |
55a2c322 VM |
6308 | { |
6309 | int i, src_regno, dst_regno, nregs; | |
df2980be | 6310 | bool change_p, succ_p, update_reloads_num_p; |
cfa434f6 | 6311 | rtx_insn *prev_insn, *last_insn; |
8a8330b7 | 6312 | rtx next_usage_insns, curr_set; |
55a2c322 VM |
6313 | enum reg_class cl; |
6314 | struct lra_insn_reg *reg; | |
6315 | basic_block last_processed_bb, curr_bb = NULL; | |
6316 | HARD_REG_SET potential_reload_hard_regs, live_hard_regs; | |
6317 | bitmap to_process; | |
6318 | unsigned int j; | |
6319 | bitmap_iterator bi; | |
6320 | bool head_p, after_p; | |
6321 | ||
6322 | change_p = false; | |
6323 | curr_usage_insns_check++; | |
8a8330b7 | 6324 | clear_invariants (); |
55a2c322 | 6325 | reloads_num = calls_num = 0; |
a1e6ee38 RS |
6326 | for (unsigned int i = 0; i < NUM_ABI_IDS; ++i) |
6327 | last_call_for_abi[i] = 0; | |
6328 | CLEAR_HARD_REG_SET (full_and_partial_call_clobbers); | |
55a2c322 | 6329 | bitmap_clear (&check_only_regs); |
8a8330b7 | 6330 | bitmap_clear (&invalid_invariant_regs); |
55a2c322 VM |
6331 | last_processed_bb = NULL; |
6332 | CLEAR_HARD_REG_SET (potential_reload_hard_regs); | |
44942965 | 6333 | live_hard_regs = eliminable_regset | lra_no_alloc_regs; |
55a2c322 VM |
6334 | /* We don't process new insns generated in the loop. */ |
6335 | for (curr_insn = tail; curr_insn != PREV_INSN (head); curr_insn = prev_insn) | |
6336 | { | |
6337 | prev_insn = PREV_INSN (curr_insn); | |
6338 | if (BLOCK_FOR_INSN (curr_insn) != NULL) | |
6339 | curr_bb = BLOCK_FOR_INSN (curr_insn); | |
6340 | if (last_processed_bb != curr_bb) | |
6341 | { | |
6342 | /* We are at the end of BB. Add qualified living | |
6343 | pseudos for potential splitting. */ | |
6344 | to_process = df_get_live_out (curr_bb); | |
6345 | if (last_processed_bb != NULL) | |
f4eafc30 | 6346 | { |
55a2c322 VM |
6347 | /* We are somewhere in the middle of EBB. */ |
6348 | get_live_on_other_edges (curr_bb, last_processed_bb, | |
6349 | &temp_bitmap); | |
6350 | to_process = &temp_bitmap; | |
6351 | } | |
6352 | last_processed_bb = curr_bb; | |
6353 | last_insn = get_last_insertion_point (curr_bb); | |
6354 | after_p = (! JUMP_P (last_insn) | |
6355 | && (! CALL_P (last_insn) | |
6356 | || (find_reg_note (last_insn, | |
6357 | REG_NORETURN, NULL_RTX) == NULL_RTX | |
6358 | && ! SIBLING_CALL_P (last_insn)))); | |
55a2c322 VM |
6359 | CLEAR_HARD_REG_SET (potential_reload_hard_regs); |
6360 | EXECUTE_IF_SET_IN_BITMAP (to_process, 0, j, bi) | |
6361 | { | |
6362 | if ((int) j >= lra_constraint_new_regno_start) | |
6363 | break; | |
6364 | if (j < FIRST_PSEUDO_REGISTER || reg_renumber[j] >= 0) | |
6365 | { | |
6366 | if (j < FIRST_PSEUDO_REGISTER) | |
6367 | SET_HARD_REG_BIT (live_hard_regs, j); | |
6368 | else | |
6369 | add_to_hard_reg_set (&live_hard_regs, | |
6370 | PSEUDO_REGNO_MODE (j), | |
6371 | reg_renumber[j]); | |
6372 | setup_next_usage_insn (j, last_insn, reloads_num, after_p); | |
6373 | } | |
6374 | } | |
6375 | } | |
6376 | src_regno = dst_regno = -1; | |
8a8330b7 VM |
6377 | curr_set = single_set (curr_insn); |
6378 | if (curr_set != NULL_RTX && REG_P (SET_DEST (curr_set))) | |
6379 | dst_regno = REGNO (SET_DEST (curr_set)); | |
6380 | if (curr_set != NULL_RTX && REG_P (SET_SRC (curr_set))) | |
6381 | src_regno = REGNO (SET_SRC (curr_set)); | |
df2980be | 6382 | update_reloads_num_p = true; |
55a2c322 VM |
6383 | if (src_regno < lra_constraint_new_regno_start |
6384 | && src_regno >= FIRST_PSEUDO_REGISTER | |
6385 | && reg_renumber[src_regno] < 0 | |
6386 | && dst_regno >= lra_constraint_new_regno_start | |
6387 | && (cl = lra_get_allocno_class (dst_regno)) != NO_REGS) | |
6388 | { | |
6389 | /* 'reload_pseudo <- original_pseudo'. */ | |
8e9d68a9 VM |
6390 | if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num) |
6391 | reloads_num++; | |
df2980be | 6392 | update_reloads_num_p = false; |
55a2c322 VM |
6393 | succ_p = false; |
6394 | if (usage_insns[src_regno].check == curr_usage_insns_check | |
6395 | && (next_usage_insns = usage_insns[src_regno].insns) != NULL_RTX) | |
6396 | succ_p = inherit_reload_reg (false, src_regno, cl, | |
6397 | curr_insn, next_usage_insns); | |
6398 | if (succ_p) | |
6399 | change_p = true; | |
6400 | else | |
6401 | setup_next_usage_insn (src_regno, curr_insn, reloads_num, false); | |
6402 | if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs)) | |
44942965 | 6403 | potential_reload_hard_regs |= reg_class_contents[cl]; |
55a2c322 | 6404 | } |
8a8330b7 VM |
6405 | else if (src_regno < 0 |
6406 | && dst_regno >= lra_constraint_new_regno_start | |
6407 | && invariant_p (SET_SRC (curr_set)) | |
6408 | && (cl = lra_get_allocno_class (dst_regno)) != NO_REGS | |
f7abdf36 VM |
6409 | && ! bitmap_bit_p (&invalid_invariant_regs, dst_regno) |
6410 | && ! bitmap_bit_p (&invalid_invariant_regs, | |
6411 | ORIGINAL_REGNO(regno_reg_rtx[dst_regno]))) | |
8a8330b7 VM |
6412 | { |
6413 | /* 'reload_pseudo <- invariant'. */ | |
6414 | if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num) | |
6415 | reloads_num++; | |
6416 | update_reloads_num_p = false; | |
6417 | if (process_invariant_for_inheritance (SET_DEST (curr_set), SET_SRC (curr_set))) | |
6418 | change_p = true; | |
6419 | if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs)) | |
44942965 | 6420 | potential_reload_hard_regs |= reg_class_contents[cl]; |
8a8330b7 | 6421 | } |
55a2c322 VM |
6422 | else if (src_regno >= lra_constraint_new_regno_start |
6423 | && dst_regno < lra_constraint_new_regno_start | |
6424 | && dst_regno >= FIRST_PSEUDO_REGISTER | |
6425 | && reg_renumber[dst_regno] < 0 | |
6426 | && (cl = lra_get_allocno_class (src_regno)) != NO_REGS | |
6427 | && usage_insns[dst_regno].check == curr_usage_insns_check | |
6428 | && (next_usage_insns | |
6429 | = usage_insns[dst_regno].insns) != NULL_RTX) | |
6430 | { | |
8e9d68a9 VM |
6431 | if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num) |
6432 | reloads_num++; | |
df2980be | 6433 | update_reloads_num_p = false; |
55a2c322 VM |
6434 | /* 'original_pseudo <- reload_pseudo'. */ |
6435 | if (! JUMP_P (curr_insn) | |
6436 | && inherit_reload_reg (true, dst_regno, cl, | |
6437 | curr_insn, next_usage_insns)) | |
6438 | change_p = true; | |
6439 | /* Invalidate. */ | |
6440 | usage_insns[dst_regno].check = 0; | |
6441 | if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs)) | |
44942965 | 6442 | potential_reload_hard_regs |= reg_class_contents[cl]; |
55a2c322 VM |
6443 | } |
6444 | else if (INSN_P (curr_insn)) | |
6445 | { | |
2f259720 | 6446 | int iter; |
55a2c322 VM |
6447 | int max_uid = get_max_uid (); |
6448 | ||
6449 | curr_id = lra_get_insn_recog_data (curr_insn); | |
2f259720 | 6450 | curr_static_id = curr_id->insn_static_data; |
55a2c322 VM |
6451 | to_inherit_num = 0; |
6452 | /* Process insn definitions. */ | |
2f259720 VM |
6453 | for (iter = 0; iter < 2; iter++) |
6454 | for (reg = iter == 0 ? curr_id->regs : curr_static_id->hard_regs; | |
6455 | reg != NULL; | |
6456 | reg = reg->next) | |
6457 | if (reg->type != OP_IN | |
6458 | && (dst_regno = reg->regno) < lra_constraint_new_regno_start) | |
6459 | { | |
6460 | if (dst_regno >= FIRST_PSEUDO_REGISTER && reg->type == OP_OUT | |
6461 | && reg_renumber[dst_regno] < 0 && ! reg->subreg_p | |
6462 | && usage_insns[dst_regno].check == curr_usage_insns_check | |
6463 | && (next_usage_insns | |
6464 | = usage_insns[dst_regno].insns) != NULL_RTX) | |
6465 | { | |
6466 | struct lra_insn_reg *r; | |
6467 | ||
6468 | for (r = curr_id->regs; r != NULL; r = r->next) | |
6469 | if (r->type != OP_OUT && r->regno == dst_regno) | |
6470 | break; | |
6471 | /* Don't do inheritance if the pseudo is also | |
6472 | used in the insn. */ | |
6473 | if (r == NULL) | |
67914693 | 6474 | /* We cannot do inheritance right now |
2f259720 VM |
6475 | because the current insn reg info (chain |
6476 | regs) can change after that. */ | |
6477 | add_to_inherit (dst_regno, next_usage_insns); | |
6478 | } | |
67914693 | 6479 | /* We cannot process one reg twice here because of |
2f259720 VM |
6480 | usage_insns invalidation. */ |
6481 | if ((dst_regno < FIRST_PSEUDO_REGISTER | |
6482 | || reg_renumber[dst_regno] >= 0) | |
e32e4c4a | 6483 | && ! reg->subreg_p && reg->type != OP_IN) |
2f259720 VM |
6484 | { |
6485 | HARD_REG_SET s; | |
6486 | ||
6487 | if (split_if_necessary (dst_regno, reg->biggest_mode, | |
6488 | potential_reload_hard_regs, | |
6489 | false, curr_insn, max_uid)) | |
6490 | change_p = true; | |
6491 | CLEAR_HARD_REG_SET (s); | |
6492 | if (dst_regno < FIRST_PSEUDO_REGISTER) | |
6493 | add_to_hard_reg_set (&s, reg->biggest_mode, dst_regno); | |
6494 | else | |
6495 | add_to_hard_reg_set (&s, PSEUDO_REGNO_MODE (dst_regno), | |
6496 | reg_renumber[dst_regno]); | |
d15e5131 RS |
6497 | live_hard_regs &= ~s; |
6498 | potential_reload_hard_regs &= ~s; | |
2f259720 VM |
6499 | } |
6500 | /* We should invalidate potential inheritance or | |
6501 | splitting for the current insn usages to the next | |
6502 | usage insns (see code below) as the output pseudo | |
6503 | prevents this. */ | |
6504 | if ((dst_regno >= FIRST_PSEUDO_REGISTER | |
6505 | && reg_renumber[dst_regno] < 0) | |
6506 | || (reg->type == OP_OUT && ! reg->subreg_p | |
6507 | && (dst_regno < FIRST_PSEUDO_REGISTER | |
6508 | || reg_renumber[dst_regno] >= 0))) | |
6509 | { | |
6510 | /* Invalidate and mark definitions. */ | |
6511 | if (dst_regno >= FIRST_PSEUDO_REGISTER) | |
6512 | usage_insns[dst_regno].check = -(int) INSN_UID (curr_insn); | |
6513 | else | |
6514 | { | |
ad474626 RS |
6515 | nregs = hard_regno_nregs (dst_regno, |
6516 | reg->biggest_mode); | |
2f259720 VM |
6517 | for (i = 0; i < nregs; i++) |
6518 | usage_insns[dst_regno + i].check | |
6519 | = -(int) INSN_UID (curr_insn); | |
6520 | } | |
6521 | } | |
6522 | } | |
9d86e84e VM |
6523 | /* Process clobbered call regs. */ |
6524 | if (curr_id->arg_hard_regs != NULL) | |
6525 | for (i = 0; (dst_regno = curr_id->arg_hard_regs[i]) >= 0; i++) | |
6526 | if (dst_regno >= FIRST_PSEUDO_REGISTER) | |
6527 | usage_insns[dst_regno - FIRST_PSEUDO_REGISTER].check | |
6528 | = -(int) INSN_UID (curr_insn); | |
55a2c322 VM |
6529 | if (! JUMP_P (curr_insn)) |
6530 | for (i = 0; i < to_inherit_num; i++) | |
6531 | if (inherit_reload_reg (true, to_inherit[i].regno, | |
6532 | ALL_REGS, curr_insn, | |
6533 | to_inherit[i].insns)) | |
6534 | change_p = true; | |
6535 | if (CALL_P (curr_insn)) | |
6536 | { | |
cfa434f6 DM |
6537 | rtx cheap, pat, dest; |
6538 | rtx_insn *restore; | |
55a2c322 VM |
6539 | int regno, hard_regno; |
6540 | ||
6541 | calls_num++; | |
a1e6ee38 RS |
6542 | function_abi callee_abi = insn_callee_abi (curr_insn); |
6543 | last_call_for_abi[callee_abi.id ()] = calls_num; | |
6544 | full_and_partial_call_clobbers | |
6545 | |= callee_abi.full_and_partial_reg_clobbers (); | |
55a2c322 VM |
6546 | if ((cheap = find_reg_note (curr_insn, |
6547 | REG_RETURNED, NULL_RTX)) != NULL_RTX | |
6548 | && ((cheap = XEXP (cheap, 0)), true) | |
6549 | && (regno = REGNO (cheap)) >= FIRST_PSEUDO_REGISTER | |
6550 | && (hard_regno = reg_renumber[regno]) >= 0 | |
851dac7c | 6551 | && usage_insns[regno].check == curr_usage_insns_check |
55a2c322 VM |
6552 | /* If there are pending saves/restores, the |
6553 | optimization is not worth. */ | |
6554 | && usage_insns[regno].calls_num == calls_num - 1 | |
a1e6ee38 | 6555 | && callee_abi.clobbers_reg_p (GET_MODE (cheap), hard_regno)) |
55a2c322 VM |
6556 | { |
6557 | /* Restore the pseudo from the call result as | |
6558 | REG_RETURNED note says that the pseudo value is | |
6559 | in the call result and the pseudo is an argument | |
6560 | of the call. */ | |
6561 | pat = PATTERN (curr_insn); | |
6562 | if (GET_CODE (pat) == PARALLEL) | |
6563 | pat = XVECEXP (pat, 0, 0); | |
6564 | dest = SET_DEST (pat); | |
54bddf1d IE |
6565 | /* For multiple return values dest is PARALLEL. |
6566 | Currently we handle only single return value case. */ | |
6567 | if (REG_P (dest)) | |
6568 | { | |
6569 | start_sequence (); | |
6570 | emit_move_insn (cheap, copy_rtx (dest)); | |
6571 | restore = get_insns (); | |
6572 | end_sequence (); | |
6573 | lra_process_new_insns (curr_insn, NULL, restore, | |
6574 | "Inserting call parameter restore"); | |
6575 | /* We don't need to save/restore of the pseudo from | |
6576 | this call. */ | |
6577 | usage_insns[regno].calls_num = calls_num; | |
a1e6ee38 RS |
6578 | remove_from_hard_reg_set |
6579 | (&full_and_partial_call_clobbers, | |
6580 | GET_MODE (cheap), hard_regno); | |
54bddf1d IE |
6581 | bitmap_set_bit (&check_only_regs, regno); |
6582 | } | |
55a2c322 VM |
6583 | } |
6584 | } | |
6585 | to_inherit_num = 0; | |
6586 | /* Process insn usages. */ | |
2f259720 VM |
6587 | for (iter = 0; iter < 2; iter++) |
6588 | for (reg = iter == 0 ? curr_id->regs : curr_static_id->hard_regs; | |
6589 | reg != NULL; | |
6590 | reg = reg->next) | |
6591 | if ((reg->type != OP_OUT | |
6592 | || (reg->type == OP_OUT && reg->subreg_p)) | |
6593 | && (src_regno = reg->regno) < lra_constraint_new_regno_start) | |
6594 | { | |
6595 | if (src_regno >= FIRST_PSEUDO_REGISTER | |
6596 | && reg_renumber[src_regno] < 0 && reg->type == OP_IN) | |
6597 | { | |
6598 | if (usage_insns[src_regno].check == curr_usage_insns_check | |
6599 | && (next_usage_insns | |
6600 | = usage_insns[src_regno].insns) != NULL_RTX | |
6601 | && NONDEBUG_INSN_P (curr_insn)) | |
6602 | add_to_inherit (src_regno, next_usage_insns); | |
6603 | else if (usage_insns[src_regno].check | |
6604 | != -(int) INSN_UID (curr_insn)) | |
6605 | /* Add usages but only if the reg is not set up | |
6606 | in the same insn. */ | |
6607 | add_next_usage_insn (src_regno, curr_insn, reloads_num); | |
6608 | } | |
6609 | else if (src_regno < FIRST_PSEUDO_REGISTER | |
6610 | || reg_renumber[src_regno] >= 0) | |
6611 | { | |
6612 | bool before_p; | |
e67d1102 | 6613 | rtx_insn *use_insn = curr_insn; |
2f259720 VM |
6614 | |
6615 | before_p = (JUMP_P (curr_insn) | |
6616 | || (CALL_P (curr_insn) && reg->type == OP_IN)); | |
6617 | if (NONDEBUG_INSN_P (curr_insn) | |
8e9d68a9 | 6618 | && (! JUMP_P (curr_insn) || reg->type == OP_IN) |
2f259720 VM |
6619 | && split_if_necessary (src_regno, reg->biggest_mode, |
6620 | potential_reload_hard_regs, | |
6621 | before_p, curr_insn, max_uid)) | |
6622 | { | |
6623 | if (reg->subreg_p) | |
7436a1c6 | 6624 | check_and_force_assignment_correctness_p = true; |
2f259720 | 6625 | change_p = true; |
8e9d68a9 | 6626 | /* Invalidate. */ |
2f259720 VM |
6627 | usage_insns[src_regno].check = 0; |
6628 | if (before_p) | |
6629 | use_insn = PREV_INSN (curr_insn); | |
6630 | } | |
6631 | if (NONDEBUG_INSN_P (curr_insn)) | |
6632 | { | |
6633 | if (src_regno < FIRST_PSEUDO_REGISTER) | |
6634 | add_to_hard_reg_set (&live_hard_regs, | |
6635 | reg->biggest_mode, src_regno); | |
6636 | else | |
6637 | add_to_hard_reg_set (&live_hard_regs, | |
6638 | PSEUDO_REGNO_MODE (src_regno), | |
6639 | reg_renumber[src_regno]); | |
6640 | } | |
16ba97b9 VM |
6641 | if (src_regno >= FIRST_PSEUDO_REGISTER) |
6642 | add_next_usage_insn (src_regno, use_insn, reloads_num); | |
6643 | else | |
6644 | { | |
6645 | for (i = 0; i < hard_regno_nregs (src_regno, reg->biggest_mode); i++) | |
6646 | add_next_usage_insn (src_regno + i, use_insn, reloads_num); | |
6647 | } | |
2f259720 VM |
6648 | } |
6649 | } | |
9d86e84e | 6650 | /* Process used call regs. */ |
df2980be VM |
6651 | if (curr_id->arg_hard_regs != NULL) |
6652 | for (i = 0; (src_regno = curr_id->arg_hard_regs[i]) >= 0; i++) | |
6653 | if (src_regno < FIRST_PSEUDO_REGISTER) | |
6654 | { | |
6655 | SET_HARD_REG_BIT (live_hard_regs, src_regno); | |
6656 | add_next_usage_insn (src_regno, curr_insn, reloads_num); | |
6657 | } | |
55a2c322 VM |
6658 | for (i = 0; i < to_inherit_num; i++) |
6659 | { | |
6660 | src_regno = to_inherit[i].regno; | |
6661 | if (inherit_reload_reg (false, src_regno, ALL_REGS, | |
6662 | curr_insn, to_inherit[i].insns)) | |
6663 | change_p = true; | |
6664 | else | |
6665 | setup_next_usage_insn (src_regno, curr_insn, reloads_num, false); | |
6666 | } | |
6667 | } | |
df2980be | 6668 | if (update_reloads_num_p |
8a8330b7 | 6669 | && NONDEBUG_INSN_P (curr_insn) && curr_set != NULL_RTX) |
df2980be VM |
6670 | { |
6671 | int regno = -1; | |
8a8330b7 VM |
6672 | if ((REG_P (SET_DEST (curr_set)) |
6673 | && (regno = REGNO (SET_DEST (curr_set))) >= lra_constraint_new_regno_start | |
df2980be VM |
6674 | && reg_renumber[regno] < 0 |
6675 | && (cl = lra_get_allocno_class (regno)) != NO_REGS) | |
8a8330b7 VM |
6676 | || (REG_P (SET_SRC (curr_set)) |
6677 | && (regno = REGNO (SET_SRC (curr_set))) >= lra_constraint_new_regno_start | |
df2980be VM |
6678 | && reg_renumber[regno] < 0 |
6679 | && (cl = lra_get_allocno_class (regno)) != NO_REGS)) | |
6680 | { | |
8e9d68a9 VM |
6681 | if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num) |
6682 | reloads_num++; | |
df2980be | 6683 | if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs)) |
44942965 | 6684 | potential_reload_hard_regs |= reg_class_contents[cl]; |
df2980be VM |
6685 | } |
6686 | } | |
8a8330b7 VM |
6687 | if (NONDEBUG_INSN_P (curr_insn)) |
6688 | { | |
6689 | int regno; | |
6690 | ||
6691 | /* Invalidate invariants with changed regs. */ | |
6692 | curr_id = lra_get_insn_recog_data (curr_insn); | |
6693 | for (reg = curr_id->regs; reg != NULL; reg = reg->next) | |
6694 | if (reg->type != OP_IN) | |
f7abdf36 VM |
6695 | { |
6696 | bitmap_set_bit (&invalid_invariant_regs, reg->regno); | |
6697 | bitmap_set_bit (&invalid_invariant_regs, | |
6698 | ORIGINAL_REGNO (regno_reg_rtx[reg->regno])); | |
6699 | } | |
8a8330b7 VM |
6700 | curr_static_id = curr_id->insn_static_data; |
6701 | for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next) | |
6702 | if (reg->type != OP_IN) | |
6703 | bitmap_set_bit (&invalid_invariant_regs, reg->regno); | |
6704 | if (curr_id->arg_hard_regs != NULL) | |
6705 | for (i = 0; (regno = curr_id->arg_hard_regs[i]) >= 0; i++) | |
f7abdf36 | 6706 | if (regno >= FIRST_PSEUDO_REGISTER) |
8a8330b7 | 6707 | bitmap_set_bit (&invalid_invariant_regs, |
f7abdf36 | 6708 | regno - FIRST_PSEUDO_REGISTER); |
8a8330b7 | 6709 | } |
55a2c322 VM |
6710 | /* We reached the start of the current basic block. */ |
6711 | if (prev_insn == NULL_RTX || prev_insn == PREV_INSN (head) | |
6712 | || BLOCK_FOR_INSN (prev_insn) != curr_bb) | |
6713 | { | |
6714 | /* We reached the beginning of the current block -- do | |
6715 | rest of spliting in the current BB. */ | |
6716 | to_process = df_get_live_in (curr_bb); | |
6717 | if (BLOCK_FOR_INSN (head) != curr_bb) | |
f4eafc30 | 6718 | { |
55a2c322 VM |
6719 | /* We are somewhere in the middle of EBB. */ |
6720 | get_live_on_other_edges (EDGE_PRED (curr_bb, 0)->src, | |
6721 | curr_bb, &temp_bitmap); | |
6722 | to_process = &temp_bitmap; | |
6723 | } | |
6724 | head_p = true; | |
6725 | EXECUTE_IF_SET_IN_BITMAP (to_process, 0, j, bi) | |
6726 | { | |
6727 | if ((int) j >= lra_constraint_new_regno_start) | |
6728 | break; | |
6729 | if (((int) j < FIRST_PSEUDO_REGISTER || reg_renumber[j] >= 0) | |
6730 | && usage_insns[j].check == curr_usage_insns_check | |
6731 | && (next_usage_insns = usage_insns[j].insns) != NULL_RTX) | |
6732 | { | |
6733 | if (need_for_split_p (potential_reload_hard_regs, j)) | |
6734 | { | |
6735 | if (lra_dump_file != NULL && head_p) | |
6736 | { | |
6737 | fprintf (lra_dump_file, | |
6738 | " ----------------------------------\n"); | |
6739 | head_p = false; | |
6740 | } | |
6741 | if (split_reg (false, j, bb_note (curr_bb), | |
6027ea4c | 6742 | next_usage_insns, NULL)) |
55a2c322 VM |
6743 | change_p = true; |
6744 | } | |
6745 | usage_insns[j].check = 0; | |
6746 | } | |
6747 | } | |
6748 | } | |
6749 | } | |
6750 | return change_p; | |
6751 | } | |
6752 | ||
6753 | /* This value affects EBB forming. If probability of edge from EBB to | |
6754 | a BB is not greater than the following value, we don't add the BB | |
f4eafc30 | 6755 | to EBB. */ |
fb8a0e40 | 6756 | #define EBB_PROBABILITY_CUTOFF \ |
028d4092 | 6757 | ((REG_BR_PROB_BASE * param_lra_inheritance_ebb_probability_cutoff) / 100) |
55a2c322 VM |
6758 | |
6759 | /* Current number of inheritance/split iteration. */ | |
6760 | int lra_inheritance_iter; | |
6761 | ||
6762 | /* Entry function for inheritance/split pass. */ | |
6763 | void | |
6764 | lra_inheritance (void) | |
6765 | { | |
6766 | int i; | |
6767 | basic_block bb, start_bb; | |
6768 | edge e; | |
6769 | ||
55a2c322 | 6770 | lra_inheritance_iter++; |
8e3a4869 | 6771 | if (lra_inheritance_iter > LRA_MAX_INHERITANCE_PASSES) |
e731262b VM |
6772 | return; |
6773 | timevar_push (TV_LRA_INHERITANCE); | |
55a2c322 VM |
6774 | if (lra_dump_file != NULL) |
6775 | fprintf (lra_dump_file, "\n********** Inheritance #%d: **********\n\n", | |
6776 | lra_inheritance_iter); | |
6777 | curr_usage_insns_check = 0; | |
6778 | usage_insns = XNEWVEC (struct usage_insns, lra_constraint_new_regno_start); | |
6779 | for (i = 0; i < lra_constraint_new_regno_start; i++) | |
6780 | usage_insns[i].check = 0; | |
6781 | bitmap_initialize (&check_only_regs, ®_obstack); | |
8a8330b7 | 6782 | bitmap_initialize (&invalid_invariant_regs, ®_obstack); |
55a2c322 VM |
6783 | bitmap_initialize (&live_regs, ®_obstack); |
6784 | bitmap_initialize (&temp_bitmap, ®_obstack); | |
6785 | bitmap_initialize (&ebb_global_regs, ®_obstack); | |
11cd3bed | 6786 | FOR_EACH_BB_FN (bb, cfun) |
55a2c322 VM |
6787 | { |
6788 | start_bb = bb; | |
6789 | if (lra_dump_file != NULL) | |
6790 | fprintf (lra_dump_file, "EBB"); | |
6791 | /* Form a EBB starting with BB. */ | |
6792 | bitmap_clear (&ebb_global_regs); | |
6793 | bitmap_ior_into (&ebb_global_regs, df_get_live_in (bb)); | |
6794 | for (;;) | |
6795 | { | |
6796 | if (lra_dump_file != NULL) | |
6797 | fprintf (lra_dump_file, " %d", bb->index); | |
fefa31b5 DM |
6798 | if (bb->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun) |
6799 | || LABEL_P (BB_HEAD (bb->next_bb))) | |
55a2c322 VM |
6800 | break; |
6801 | e = find_fallthru_edge (bb->succs); | |
6802 | if (! e) | |
6803 | break; | |
357067f2 JH |
6804 | if (e->probability.initialized_p () |
6805 | && e->probability.to_reg_br_prob_base () < EBB_PROBABILITY_CUTOFF) | |
55a2c322 VM |
6806 | break; |
6807 | bb = bb->next_bb; | |
6808 | } | |
6809 | bitmap_ior_into (&ebb_global_regs, df_get_live_out (bb)); | |
6810 | if (lra_dump_file != NULL) | |
6811 | fprintf (lra_dump_file, "\n"); | |
6812 | if (inherit_in_ebb (BB_HEAD (start_bb), BB_END (bb))) | |
6813 | /* Remember that the EBB head and tail can change in | |
6814 | inherit_in_ebb. */ | |
6815 | update_ebb_live_info (BB_HEAD (start_bb), BB_END (bb)); | |
6816 | } | |
1c252ef3 RB |
6817 | bitmap_release (&ebb_global_regs); |
6818 | bitmap_release (&temp_bitmap); | |
6819 | bitmap_release (&live_regs); | |
6820 | bitmap_release (&invalid_invariant_regs); | |
6821 | bitmap_release (&check_only_regs); | |
55a2c322 VM |
6822 | free (usage_insns); |
6823 | ||
6824 | timevar_pop (TV_LRA_INHERITANCE); | |
6825 | } | |
6826 | ||
6827 | \f | |
6828 | ||
6829 | /* This page contains code to undo failed inheritance/split | |
6830 | transformations. */ | |
6831 | ||
6832 | /* Current number of iteration undoing inheritance/split. */ | |
6833 | int lra_undo_inheritance_iter; | |
6834 | ||
6835 | /* Fix BB live info LIVE after removing pseudos created on pass doing | |
6836 | inheritance/split which are REMOVED_PSEUDOS. */ | |
6837 | static void | |
6838 | fix_bb_live_info (bitmap live, bitmap removed_pseudos) | |
6839 | { | |
6840 | unsigned int regno; | |
6841 | bitmap_iterator bi; | |
6842 | ||
6843 | EXECUTE_IF_SET_IN_BITMAP (removed_pseudos, 0, regno, bi) | |
8a8330b7 VM |
6844 | if (bitmap_clear_bit (live, regno) |
6845 | && REG_P (lra_reg_info[regno].restore_rtx)) | |
6846 | bitmap_set_bit (live, REGNO (lra_reg_info[regno].restore_rtx)); | |
55a2c322 VM |
6847 | } |
6848 | ||
6849 | /* Return regno of the (subreg of) REG. Otherwise, return a negative | |
6850 | number. */ | |
6851 | static int | |
6852 | get_regno (rtx reg) | |
6853 | { | |
6854 | if (GET_CODE (reg) == SUBREG) | |
6855 | reg = SUBREG_REG (reg); | |
6856 | if (REG_P (reg)) | |
6857 | return REGNO (reg); | |
6858 | return -1; | |
6859 | } | |
6860 | ||
cefe08a4 VM |
6861 | /* Delete a move INSN with destination reg DREGNO and a previous |
6862 | clobber insn with the same regno. The inheritance/split code can | |
6863 | generate moves with preceding clobber and when we delete such moves | |
6864 | we should delete the clobber insn too to keep the correct life | |
6865 | info. */ | |
6866 | static void | |
6867 | delete_move_and_clobber (rtx_insn *insn, int dregno) | |
6868 | { | |
6869 | rtx_insn *prev_insn = PREV_INSN (insn); | |
6870 | ||
6871 | lra_set_insn_deleted (insn); | |
79b57d18 | 6872 | lra_assert (dregno >= 0); |
cefe08a4 VM |
6873 | if (prev_insn != NULL && NONDEBUG_INSN_P (prev_insn) |
6874 | && GET_CODE (PATTERN (prev_insn)) == CLOBBER | |
6875 | && dregno == get_regno (XEXP (PATTERN (prev_insn), 0))) | |
6876 | lra_set_insn_deleted (prev_insn); | |
6877 | } | |
6878 | ||
55a2c322 VM |
6879 | /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and |
6880 | return true if we did any change. The undo transformations for | |
6881 | inheritance looks like | |
6882 | i <- i2 | |
6883 | p <- i => p <- i2 | |
6884 | or removing | |
6885 | p <- i, i <- p, and i <- i3 | |
6886 | where p is original pseudo from which inheritance pseudo i was | |
6887 | created, i and i3 are removed inheritance pseudos, i2 is another | |
6888 | not removed inheritance pseudo. All split pseudos or other | |
6889 | occurrences of removed inheritance pseudos are changed on the | |
6890 | corresponding original pseudos. | |
6891 | ||
6892 | The function also schedules insns changed and created during | |
6893 | inheritance/split pass for processing by the subsequent constraint | |
6894 | pass. */ | |
6895 | static bool | |
6896 | remove_inheritance_pseudos (bitmap remove_pseudos) | |
6897 | { | |
6898 | basic_block bb; | |
8a8330b7 VM |
6899 | int regno, sregno, prev_sregno, dregno; |
6900 | rtx restore_rtx; | |
cfa434f6 DM |
6901 | rtx set, prev_set; |
6902 | rtx_insn *prev_insn; | |
55a2c322 VM |
6903 | bool change_p, done_p; |
6904 | ||
6905 | change_p = ! bitmap_empty_p (remove_pseudos); | |
67914693 | 6906 | /* We cannot finish the function right away if CHANGE_P is true |
55a2c322 VM |
6907 | because we need to marks insns affected by previous |
6908 | inheritance/split pass for processing by the subsequent | |
6909 | constraint pass. */ | |
11cd3bed | 6910 | FOR_EACH_BB_FN (bb, cfun) |
55a2c322 VM |
6911 | { |
6912 | fix_bb_live_info (df_get_live_in (bb), remove_pseudos); | |
6913 | fix_bb_live_info (df_get_live_out (bb), remove_pseudos); | |
6914 | FOR_BB_INSNS_REVERSE (bb, curr_insn) | |
6915 | { | |
6916 | if (! INSN_P (curr_insn)) | |
6917 | continue; | |
6918 | done_p = false; | |
6919 | sregno = dregno = -1; | |
6920 | if (change_p && NONDEBUG_INSN_P (curr_insn) | |
6921 | && (set = single_set (curr_insn)) != NULL_RTX) | |
6922 | { | |
6923 | dregno = get_regno (SET_DEST (set)); | |
6924 | sregno = get_regno (SET_SRC (set)); | |
6925 | } | |
f4eafc30 | 6926 | |
55a2c322 VM |
6927 | if (sregno >= 0 && dregno >= 0) |
6928 | { | |
8a8330b7 VM |
6929 | if (bitmap_bit_p (remove_pseudos, dregno) |
6930 | && ! REG_P (lra_reg_info[dregno].restore_rtx)) | |
6931 | { | |
6932 | /* invariant inheritance pseudo <- original pseudo */ | |
6933 | if (lra_dump_file != NULL) | |
6934 | { | |
6935 | fprintf (lra_dump_file, " Removing invariant inheritance:\n"); | |
6936 | dump_insn_slim (lra_dump_file, curr_insn); | |
6937 | fprintf (lra_dump_file, "\n"); | |
6938 | } | |
6939 | delete_move_and_clobber (curr_insn, dregno); | |
6940 | done_p = true; | |
6941 | } | |
6942 | else if (bitmap_bit_p (remove_pseudos, sregno) | |
6943 | && ! REG_P (lra_reg_info[sregno].restore_rtx)) | |
6944 | { | |
6945 | /* reload pseudo <- invariant inheritance pseudo */ | |
6946 | start_sequence (); | |
67914693 | 6947 | /* We cannot just change the source. It might be |
8a8330b7 | 6948 | an insn different from the move. */ |
b10d44ef | 6949 | emit_insn (lra_reg_info[sregno].restore_rtx); |
8a8330b7 VM |
6950 | rtx_insn *new_insns = get_insns (); |
6951 | end_sequence (); | |
b10d44ef VM |
6952 | lra_assert (single_set (new_insns) != NULL |
6953 | && SET_DEST (set) == SET_DEST (single_set (new_insns))); | |
8a8330b7 VM |
6954 | lra_process_new_insns (curr_insn, NULL, new_insns, |
6955 | "Changing reload<-invariant inheritance"); | |
6956 | delete_move_and_clobber (curr_insn, dregno); | |
6957 | done_p = true; | |
6958 | } | |
6959 | else if ((bitmap_bit_p (remove_pseudos, sregno) | |
6960 | && (get_regno (lra_reg_info[sregno].restore_rtx) == dregno | |
6961 | || (bitmap_bit_p (remove_pseudos, dregno) | |
6962 | && get_regno (lra_reg_info[sregno].restore_rtx) >= 0 | |
6963 | && (get_regno (lra_reg_info[sregno].restore_rtx) | |
6964 | == get_regno (lra_reg_info[dregno].restore_rtx))))) | |
55a2c322 | 6965 | || (bitmap_bit_p (remove_pseudos, dregno) |
8a8330b7 | 6966 | && get_regno (lra_reg_info[dregno].restore_rtx) == sregno)) |
55a2c322 VM |
6967 | /* One of the following cases: |
6968 | original <- removed inheritance pseudo | |
6969 | removed inherit pseudo <- another removed inherit pseudo | |
6970 | removed inherit pseudo <- original pseudo | |
6971 | Or | |
6972 | removed_split_pseudo <- original_reg | |
6973 | original_reg <- removed_split_pseudo */ | |
6974 | { | |
6975 | if (lra_dump_file != NULL) | |
6976 | { | |
6977 | fprintf (lra_dump_file, " Removing %s:\n", | |
6978 | bitmap_bit_p (&lra_split_regs, sregno) | |
6979 | || bitmap_bit_p (&lra_split_regs, dregno) | |
6980 | ? "split" : "inheritance"); | |
cfbeaedf | 6981 | dump_insn_slim (lra_dump_file, curr_insn); |
55a2c322 | 6982 | } |
cefe08a4 | 6983 | delete_move_and_clobber (curr_insn, dregno); |
55a2c322 VM |
6984 | done_p = true; |
6985 | } | |
6986 | else if (bitmap_bit_p (remove_pseudos, sregno) | |
6987 | && bitmap_bit_p (&lra_inheritance_pseudos, sregno)) | |
6988 | { | |
6989 | /* Search the following pattern: | |
6990 | inherit_or_split_pseudo1 <- inherit_or_split_pseudo2 | |
6991 | original_pseudo <- inherit_or_split_pseudo1 | |
6992 | where the 2nd insn is the current insn and | |
6993 | inherit_or_split_pseudo2 is not removed. If it is found, | |
6994 | change the current insn onto: | |
6995 | original_pseudo <- inherit_or_split_pseudo2. */ | |
6996 | for (prev_insn = PREV_INSN (curr_insn); | |
6997 | prev_insn != NULL_RTX && ! NONDEBUG_INSN_P (prev_insn); | |
6998 | prev_insn = PREV_INSN (prev_insn)) | |
6999 | ; | |
7000 | if (prev_insn != NULL_RTX && BLOCK_FOR_INSN (prev_insn) == bb | |
7001 | && (prev_set = single_set (prev_insn)) != NULL_RTX | |
7002 | /* There should be no subregs in insn we are | |
7003 | searching because only the original reg might | |
7004 | be in subreg when we changed the mode of | |
7005 | load/store for splitting. */ | |
7006 | && REG_P (SET_DEST (prev_set)) | |
7007 | && REG_P (SET_SRC (prev_set)) | |
7008 | && (int) REGNO (SET_DEST (prev_set)) == sregno | |
7009 | && ((prev_sregno = REGNO (SET_SRC (prev_set))) | |
7010 | >= FIRST_PSEUDO_REGISTER) | |
8a8330b7 VM |
7011 | && (lra_reg_info[prev_sregno].restore_rtx == NULL_RTX |
7012 | || | |
7013 | /* As we consider chain of inheritance or | |
7014 | splitting described in above comment we should | |
7015 | check that sregno and prev_sregno were | |
7016 | inheritance/split pseudos created from the | |
7017 | same original regno. */ | |
7018 | (get_regno (lra_reg_info[sregno].restore_rtx) >= 0 | |
7019 | && (get_regno (lra_reg_info[sregno].restore_rtx) | |
7020 | == get_regno (lra_reg_info[prev_sregno].restore_rtx)))) | |
55a2c322 VM |
7021 | && ! bitmap_bit_p (remove_pseudos, prev_sregno)) |
7022 | { | |
7023 | lra_assert (GET_MODE (SET_SRC (prev_set)) | |
7024 | == GET_MODE (regno_reg_rtx[sregno])); | |
ef61d1ab AK |
7025 | /* Although we have a single set, the insn can |
7026 | contain more one sregno register occurrence | |
7027 | as a source. Change all occurrences. */ | |
7028 | lra_substitute_pseudo_within_insn (curr_insn, sregno, | |
7029 | SET_SRC (prev_set), | |
7030 | false); | |
12b308fa VM |
7031 | /* As we are finishing with processing the insn |
7032 | here, check the destination too as it might | |
7033 | inheritance pseudo for another pseudo. */ | |
7034 | if (bitmap_bit_p (remove_pseudos, dregno) | |
7035 | && bitmap_bit_p (&lra_inheritance_pseudos, dregno) | |
8a8330b7 VM |
7036 | && (restore_rtx |
7037 | = lra_reg_info[dregno].restore_rtx) != NULL_RTX) | |
12b308fa VM |
7038 | { |
7039 | if (GET_CODE (SET_DEST (set)) == SUBREG) | |
8a8330b7 | 7040 | SUBREG_REG (SET_DEST (set)) = restore_rtx; |
12b308fa | 7041 | else |
8a8330b7 | 7042 | SET_DEST (set) = restore_rtx; |
12b308fa | 7043 | } |
55a2c322 VM |
7044 | lra_push_insn_and_update_insn_regno_info (curr_insn); |
7045 | lra_set_used_insn_alternative_by_uid | |
7874b7c5 | 7046 | (INSN_UID (curr_insn), LRA_UNKNOWN_ALT); |
55a2c322 VM |
7047 | done_p = true; |
7048 | if (lra_dump_file != NULL) | |
7049 | { | |
7050 | fprintf (lra_dump_file, " Change reload insn:\n"); | |
cfbeaedf | 7051 | dump_insn_slim (lra_dump_file, curr_insn); |
55a2c322 VM |
7052 | } |
7053 | } | |
7054 | } | |
7055 | } | |
7056 | if (! done_p) | |
7057 | { | |
7058 | struct lra_insn_reg *reg; | |
7059 | bool restored_regs_p = false; | |
7060 | bool kept_regs_p = false; | |
7061 | ||
7062 | curr_id = lra_get_insn_recog_data (curr_insn); | |
7063 | for (reg = curr_id->regs; reg != NULL; reg = reg->next) | |
7064 | { | |
7065 | regno = reg->regno; | |
8a8330b7 VM |
7066 | restore_rtx = lra_reg_info[regno].restore_rtx; |
7067 | if (restore_rtx != NULL_RTX) | |
55a2c322 VM |
7068 | { |
7069 | if (change_p && bitmap_bit_p (remove_pseudos, regno)) | |
7070 | { | |
ef87312e | 7071 | lra_substitute_pseudo_within_insn |
8a8330b7 | 7072 | (curr_insn, regno, restore_rtx, false); |
55a2c322 VM |
7073 | restored_regs_p = true; |
7074 | } | |
7075 | else | |
7076 | kept_regs_p = true; | |
7077 | } | |
7078 | } | |
7079 | if (NONDEBUG_INSN_P (curr_insn) && kept_regs_p) | |
7080 | { | |
7081 | /* The instruction has changed since the previous | |
7082 | constraints pass. */ | |
7083 | lra_push_insn_and_update_insn_regno_info (curr_insn); | |
7084 | lra_set_used_insn_alternative_by_uid | |
7874b7c5 | 7085 | (INSN_UID (curr_insn), LRA_UNKNOWN_ALT); |
55a2c322 VM |
7086 | } |
7087 | else if (restored_regs_p) | |
7088 | /* The instruction has been restored to the form that | |
7089 | it had during the previous constraints pass. */ | |
7090 | lra_update_insn_regno_info (curr_insn); | |
7091 | if (restored_regs_p && lra_dump_file != NULL) | |
7092 | { | |
7093 | fprintf (lra_dump_file, " Insn after restoring regs:\n"); | |
cfbeaedf | 7094 | dump_insn_slim (lra_dump_file, curr_insn); |
55a2c322 VM |
7095 | } |
7096 | } | |
7097 | } | |
7098 | } | |
7099 | return change_p; | |
7100 | } | |
7101 | ||
2b778c9d VM |
7102 | /* If optional reload pseudos failed to get a hard register or was not |
7103 | inherited, it is better to remove optional reloads. We do this | |
7104 | transformation after undoing inheritance to figure out necessity to | |
7105 | remove optional reloads easier. Return true if we do any | |
7106 | change. */ | |
7107 | static bool | |
7108 | undo_optional_reloads (void) | |
7109 | { | |
b0681c9e | 7110 | bool change_p, keep_p; |
2b778c9d VM |
7111 | unsigned int regno, uid; |
7112 | bitmap_iterator bi, bi2; | |
cfa434f6 DM |
7113 | rtx_insn *insn; |
7114 | rtx set, src, dest; | |
d648b5ff | 7115 | auto_bitmap removed_optional_reload_pseudos (®_obstack); |
2b778c9d | 7116 | |
d648b5ff | 7117 | bitmap_copy (removed_optional_reload_pseudos, &lra_optional_reload_pseudos); |
2b778c9d | 7118 | EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos, 0, regno, bi) |
aa940f7c VM |
7119 | { |
7120 | keep_p = false; | |
080cbf9e | 7121 | /* Keep optional reloads from previous subpasses. */ |
8a8330b7 | 7122 | if (lra_reg_info[regno].restore_rtx == NULL_RTX |
080cbf9e VM |
7123 | /* If the original pseudo changed its allocation, just |
7124 | removing the optional pseudo is dangerous as the original | |
7125 | pseudo will have longer live range. */ | |
8a8330b7 | 7126 | || reg_renumber[REGNO (lra_reg_info[regno].restore_rtx)] >= 0) |
aa940f7c VM |
7127 | keep_p = true; |
7128 | else if (reg_renumber[regno] >= 0) | |
7129 | EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi2) | |
b0681c9e | 7130 | { |
aa940f7c VM |
7131 | insn = lra_insn_recog_data[uid]->insn; |
7132 | if ((set = single_set (insn)) == NULL_RTX) | |
7133 | continue; | |
7134 | src = SET_SRC (set); | |
7135 | dest = SET_DEST (set); | |
7136 | if (! REG_P (src) || ! REG_P (dest)) | |
7137 | continue; | |
7138 | if (REGNO (dest) == regno | |
7139 | /* Ignore insn for optional reloads itself. */ | |
8a8330b7 | 7140 | && REGNO (lra_reg_info[regno].restore_rtx) != REGNO (src) |
aa940f7c VM |
7141 | /* Check only inheritance on last inheritance pass. */ |
7142 | && (int) REGNO (src) >= new_regno_start | |
7143 | /* Check that the optional reload was inherited. */ | |
7144 | && bitmap_bit_p (&lra_inheritance_pseudos, REGNO (src))) | |
7145 | { | |
7146 | keep_p = true; | |
7147 | break; | |
7148 | } | |
b0681c9e | 7149 | } |
aa940f7c VM |
7150 | if (keep_p) |
7151 | { | |
d648b5ff | 7152 | bitmap_clear_bit (removed_optional_reload_pseudos, regno); |
aa940f7c VM |
7153 | if (lra_dump_file != NULL) |
7154 | fprintf (lra_dump_file, "Keep optional reload reg %d\n", regno); | |
7155 | } | |
7156 | } | |
d648b5ff TS |
7157 | change_p = ! bitmap_empty_p (removed_optional_reload_pseudos); |
7158 | auto_bitmap insn_bitmap (®_obstack); | |
7159 | EXECUTE_IF_SET_IN_BITMAP (removed_optional_reload_pseudos, 0, regno, bi) | |
2b778c9d VM |
7160 | { |
7161 | if (lra_dump_file != NULL) | |
7162 | fprintf (lra_dump_file, "Remove optional reload reg %d\n", regno); | |
d648b5ff TS |
7163 | bitmap_copy (insn_bitmap, &lra_reg_info[regno].insn_bitmap); |
7164 | EXECUTE_IF_SET_IN_BITMAP (insn_bitmap, 0, uid, bi2) | |
2b778c9d VM |
7165 | { |
7166 | insn = lra_insn_recog_data[uid]->insn; | |
7167 | if ((set = single_set (insn)) != NULL_RTX) | |
7168 | { | |
7169 | src = SET_SRC (set); | |
7170 | dest = SET_DEST (set); | |
7171 | if (REG_P (src) && REG_P (dest) | |
7172 | && ((REGNO (src) == regno | |
8a8330b7 VM |
7173 | && (REGNO (lra_reg_info[regno].restore_rtx) |
7174 | == REGNO (dest))) | |
2b778c9d | 7175 | || (REGNO (dest) == regno |
8a8330b7 VM |
7176 | && (REGNO (lra_reg_info[regno].restore_rtx) |
7177 | == REGNO (src))))) | |
2b778c9d VM |
7178 | { |
7179 | if (lra_dump_file != NULL) | |
7180 | { | |
7181 | fprintf (lra_dump_file, " Deleting move %u\n", | |
7182 | INSN_UID (insn)); | |
7183 | dump_insn_slim (lra_dump_file, insn); | |
7184 | } | |
cefe08a4 | 7185 | delete_move_and_clobber (insn, REGNO (dest)); |
2b778c9d VM |
7186 | continue; |
7187 | } | |
7188 | /* We should not worry about generation memory-memory | |
7189 | moves here as if the corresponding inheritance did | |
7190 | not work (inheritance pseudo did not get a hard reg), | |
7191 | we remove the inheritance pseudo and the optional | |
7192 | reload. */ | |
7193 | } | |
ef87312e | 7194 | lra_substitute_pseudo_within_insn |
8a8330b7 | 7195 | (insn, regno, lra_reg_info[regno].restore_rtx, false); |
2b778c9d VM |
7196 | lra_update_insn_regno_info (insn); |
7197 | if (lra_dump_file != NULL) | |
7198 | { | |
7199 | fprintf (lra_dump_file, | |
7200 | " Restoring original insn:\n"); | |
7201 | dump_insn_slim (lra_dump_file, insn); | |
7202 | } | |
7203 | } | |
7204 | } | |
7205 | /* Clear restore_regnos. */ | |
7206 | EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos, 0, regno, bi) | |
8a8330b7 | 7207 | lra_reg_info[regno].restore_rtx = NULL_RTX; |
2b778c9d VM |
7208 | return change_p; |
7209 | } | |
7210 | ||
55a2c322 VM |
7211 | /* Entry function for undoing inheritance/split transformation. Return true |
7212 | if we did any RTL change in this pass. */ | |
7213 | bool | |
7214 | lra_undo_inheritance (void) | |
7215 | { | |
7216 | unsigned int regno; | |
8a8330b7 | 7217 | int hard_regno; |
55a2c322 | 7218 | int n_all_inherit, n_inherit, n_all_split, n_split; |
8a8330b7 | 7219 | rtx restore_rtx; |
55a2c322 VM |
7220 | bitmap_iterator bi; |
7221 | bool change_p; | |
7222 | ||
7223 | lra_undo_inheritance_iter++; | |
8e3a4869 | 7224 | if (lra_undo_inheritance_iter > LRA_MAX_INHERITANCE_PASSES) |
e731262b | 7225 | return false; |
55a2c322 VM |
7226 | if (lra_dump_file != NULL) |
7227 | fprintf (lra_dump_file, | |
7228 | "\n********** Undoing inheritance #%d: **********\n\n", | |
7229 | lra_undo_inheritance_iter); | |
d648b5ff | 7230 | auto_bitmap remove_pseudos (®_obstack); |
55a2c322 VM |
7231 | n_inherit = n_all_inherit = 0; |
7232 | EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos, 0, regno, bi) | |
8a8330b7 | 7233 | if (lra_reg_info[regno].restore_rtx != NULL_RTX) |
55a2c322 VM |
7234 | { |
7235 | n_all_inherit++; | |
b0681c9e VM |
7236 | if (reg_renumber[regno] < 0 |
7237 | /* If the original pseudo changed its allocation, just | |
7238 | removing inheritance is dangerous as for changing | |
7239 | allocation we used shorter live-ranges. */ | |
8a8330b7 VM |
7240 | && (! REG_P (lra_reg_info[regno].restore_rtx) |
7241 | || reg_renumber[REGNO (lra_reg_info[regno].restore_rtx)] < 0)) | |
d648b5ff | 7242 | bitmap_set_bit (remove_pseudos, regno); |
55a2c322 VM |
7243 | else |
7244 | n_inherit++; | |
7245 | } | |
7246 | if (lra_dump_file != NULL && n_all_inherit != 0) | |
7247 | fprintf (lra_dump_file, "Inherit %d out of %d (%.2f%%)\n", | |
7248 | n_inherit, n_all_inherit, | |
7249 | (double) n_inherit / n_all_inherit * 100); | |
7250 | n_split = n_all_split = 0; | |
7251 | EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs, 0, regno, bi) | |
8a8330b7 | 7252 | if ((restore_rtx = lra_reg_info[regno].restore_rtx) != NULL_RTX) |
55a2c322 | 7253 | { |
8a8330b7 VM |
7254 | int restore_regno = REGNO (restore_rtx); |
7255 | ||
55a2c322 VM |
7256 | n_all_split++; |
7257 | hard_regno = (restore_regno >= FIRST_PSEUDO_REGISTER | |
7258 | ? reg_renumber[restore_regno] : restore_regno); | |
7259 | if (hard_regno < 0 || reg_renumber[regno] == hard_regno) | |
d648b5ff | 7260 | bitmap_set_bit (remove_pseudos, regno); |
55a2c322 VM |
7261 | else |
7262 | { | |
7263 | n_split++; | |
7264 | if (lra_dump_file != NULL) | |
7265 | fprintf (lra_dump_file, " Keep split r%d (orig=r%d)\n", | |
7266 | regno, restore_regno); | |
7267 | } | |
7268 | } | |
7269 | if (lra_dump_file != NULL && n_all_split != 0) | |
7270 | fprintf (lra_dump_file, "Split %d out of %d (%.2f%%)\n", | |
7271 | n_split, n_all_split, | |
7272 | (double) n_split / n_all_split * 100); | |
d648b5ff | 7273 | change_p = remove_inheritance_pseudos (remove_pseudos); |
55a2c322 VM |
7274 | /* Clear restore_regnos. */ |
7275 | EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos, 0, regno, bi) | |
8a8330b7 | 7276 | lra_reg_info[regno].restore_rtx = NULL_RTX; |
55a2c322 | 7277 | EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs, 0, regno, bi) |
8a8330b7 | 7278 | lra_reg_info[regno].restore_rtx = NULL_RTX; |
2b778c9d | 7279 | change_p = undo_optional_reloads () || change_p; |
55a2c322 VM |
7280 | return change_p; |
7281 | } |