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c6a6cdaa | 1 | /* Code for RTL transformations to satisfy insn constraints. |
711789cc | 2 | Copyright (C) 2010-2013 Free Software Foundation, Inc. |
c6a6cdaa | 3 | Contributed by Vladimir Makarov <vmakarov@redhat.com>. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it under | |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 3, or (at your option) any later | |
10 | version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | ||
22 | /* This file contains code for 3 passes: constraint pass, | |
23 | inheritance/split pass, and pass for undoing failed inheritance and | |
24 | split. | |
25 | ||
26 | The major goal of constraint pass is to transform RTL to satisfy | |
27 | insn and address constraints by: | |
28 | o choosing insn alternatives; | |
29 | o generating *reload insns* (or reloads in brief) and *reload | |
30 | pseudos* which will get necessary hard registers later; | |
31 | o substituting pseudos with equivalent values and removing the | |
32 | instructions that initialized those pseudos. | |
33 | ||
34 | The constraint pass has biggest and most complicated code in LRA. | |
35 | There are a lot of important details like: | |
36 | o reuse of input reload pseudos to simplify reload pseudo | |
37 | allocations; | |
38 | o some heuristics to choose insn alternative to improve the | |
39 | inheritance; | |
40 | o early clobbers etc. | |
41 | ||
42 | The pass is mimicking former reload pass in alternative choosing | |
43 | because the reload pass is oriented to current machine description | |
44 | model. It might be changed if the machine description model is | |
45 | changed. | |
46 | ||
47 | There is special code for preventing all LRA and this pass cycling | |
48 | in case of bugs. | |
49 | ||
50 | On the first iteration of the pass we process every instruction and | |
51 | choose an alternative for each one. On subsequent iterations we try | |
52 | to avoid reprocessing instructions if we can be sure that the old | |
53 | choice is still valid. | |
54 | ||
55 | The inheritance/spilt pass is to transform code to achieve | |
56 | ineheritance and live range splitting. It is done on backward | |
57 | traversal of EBBs. | |
58 | ||
59 | The inheritance optimization goal is to reuse values in hard | |
60 | registers. There is analogous optimization in old reload pass. The | |
61 | inheritance is achieved by following transformation: | |
62 | ||
63 | reload_p1 <- p reload_p1 <- p | |
64 | ... new_p <- reload_p1 | |
65 | ... => ... | |
66 | reload_p2 <- p reload_p2 <- new_p | |
67 | ||
68 | where p is spilled and not changed between the insns. Reload_p1 is | |
69 | also called *original pseudo* and new_p is called *inheritance | |
70 | pseudo*. | |
71 | ||
72 | The subsequent assignment pass will try to assign the same (or | |
73 | another if it is not possible) hard register to new_p as to | |
74 | reload_p1 or reload_p2. | |
75 | ||
76 | If the assignment pass fails to assign a hard register to new_p, | |
77 | this file will undo the inheritance and restore the original code. | |
78 | This is because implementing the above sequence with a spilled | |
79 | new_p would make the code much worse. The inheritance is done in | |
80 | EBB scope. The above is just a simplified example to get an idea | |
81 | of the inheritance as the inheritance is also done for non-reload | |
82 | insns. | |
83 | ||
84 | Splitting (transformation) is also done in EBB scope on the same | |
85 | pass as the inheritance: | |
86 | ||
87 | r <- ... or ... <- r r <- ... or ... <- r | |
88 | ... s <- r (new insn -- save) | |
1a8f8886 | 89 | ... => |
c6a6cdaa | 90 | ... r <- s (new insn -- restore) |
91 | ... <- r ... <- r | |
92 | ||
93 | The *split pseudo* s is assigned to the hard register of the | |
94 | original pseudo or hard register r. | |
95 | ||
96 | Splitting is done: | |
97 | o In EBBs with high register pressure for global pseudos (living | |
98 | in at least 2 BBs) and assigned to hard registers when there | |
99 | are more one reloads needing the hard registers; | |
100 | o for pseudos needing save/restore code around calls. | |
101 | ||
102 | If the split pseudo still has the same hard register as the | |
103 | original pseudo after the subsequent assignment pass or the | |
104 | original pseudo was split, the opposite transformation is done on | |
105 | the same pass for undoing inheritance. */ | |
106 | ||
107 | #undef REG_OK_STRICT | |
108 | ||
109 | #include "config.h" | |
110 | #include "system.h" | |
111 | #include "coretypes.h" | |
112 | #include "tm.h" | |
113 | #include "hard-reg-set.h" | |
114 | #include "rtl.h" | |
115 | #include "tm_p.h" | |
116 | #include "regs.h" | |
117 | #include "insn-config.h" | |
118 | #include "insn-codes.h" | |
119 | #include "recog.h" | |
120 | #include "output.h" | |
121 | #include "addresses.h" | |
122 | #include "target.h" | |
123 | #include "function.h" | |
124 | #include "expr.h" | |
125 | #include "basic-block.h" | |
126 | #include "except.h" | |
127 | #include "optabs.h" | |
128 | #include "df.h" | |
129 | #include "ira.h" | |
130 | #include "rtl-error.h" | |
131 | #include "lra-int.h" | |
132 | ||
133 | /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current | |
134 | insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted | |
135 | reload insns. */ | |
136 | static int bb_reload_num; | |
137 | ||
ea99c7a1 | 138 | /* The current insn being processed and corresponding its single set |
139 | (NULL otherwise), its data (basic block, the insn data, the insn | |
140 | static data, and the mode of each operand). */ | |
c6a6cdaa | 141 | static rtx curr_insn; |
ea99c7a1 | 142 | static rtx curr_insn_set; |
c6a6cdaa | 143 | static basic_block curr_bb; |
144 | static lra_insn_recog_data_t curr_id; | |
145 | static struct lra_static_insn_data *curr_static_id; | |
146 | static enum machine_mode curr_operand_mode[MAX_RECOG_OPERANDS]; | |
147 | ||
148 | \f | |
149 | ||
150 | /* Start numbers for new registers and insns at the current constraints | |
151 | pass start. */ | |
152 | static int new_regno_start; | |
153 | static int new_insn_uid_start; | |
154 | ||
1efe9e9d | 155 | /* If LOC is nonnull, strip any outer subreg from it. */ |
156 | static inline rtx * | |
157 | strip_subreg (rtx *loc) | |
158 | { | |
159 | return loc && GET_CODE (*loc) == SUBREG ? &SUBREG_REG (*loc) : loc; | |
160 | } | |
161 | ||
c6a6cdaa | 162 | /* Return hard regno of REGNO or if it is was not assigned to a hard |
163 | register, use a hard register from its allocno class. */ | |
164 | static int | |
165 | get_try_hard_regno (int regno) | |
166 | { | |
167 | int hard_regno; | |
168 | enum reg_class rclass; | |
169 | ||
170 | if ((hard_regno = regno) >= FIRST_PSEUDO_REGISTER) | |
171 | hard_regno = lra_get_regno_hard_regno (regno); | |
172 | if (hard_regno >= 0) | |
173 | return hard_regno; | |
174 | rclass = lra_get_allocno_class (regno); | |
175 | if (rclass == NO_REGS) | |
176 | return -1; | |
177 | return ira_class_hard_regs[rclass][0]; | |
178 | } | |
179 | ||
180 | /* Return final hard regno (plus offset) which will be after | |
181 | elimination. We do this for matching constraints because the final | |
182 | hard regno could have a different class. */ | |
183 | static int | |
184 | get_final_hard_regno (int hard_regno, int offset) | |
185 | { | |
186 | if (hard_regno < 0) | |
187 | return hard_regno; | |
188 | hard_regno = lra_get_elimination_hard_regno (hard_regno); | |
189 | return hard_regno + offset; | |
190 | } | |
191 | ||
192 | /* Return hard regno of X after removing subreg and making | |
193 | elimination. If X is not a register or subreg of register, return | |
194 | -1. For pseudo use its assignment. */ | |
195 | static int | |
196 | get_hard_regno (rtx x) | |
197 | { | |
198 | rtx reg; | |
199 | int offset, hard_regno; | |
200 | ||
201 | reg = x; | |
202 | if (GET_CODE (x) == SUBREG) | |
203 | reg = SUBREG_REG (x); | |
204 | if (! REG_P (reg)) | |
205 | return -1; | |
206 | if ((hard_regno = REGNO (reg)) >= FIRST_PSEUDO_REGISTER) | |
207 | hard_regno = lra_get_regno_hard_regno (hard_regno); | |
208 | if (hard_regno < 0) | |
209 | return -1; | |
210 | offset = 0; | |
211 | if (GET_CODE (x) == SUBREG) | |
212 | offset += subreg_regno_offset (hard_regno, GET_MODE (reg), | |
213 | SUBREG_BYTE (x), GET_MODE (x)); | |
214 | return get_final_hard_regno (hard_regno, offset); | |
215 | } | |
216 | ||
217 | /* If REGNO is a hard register or has been allocated a hard register, | |
218 | return the class of that register. If REGNO is a reload pseudo | |
219 | created by the current constraints pass, return its allocno class. | |
220 | Return NO_REGS otherwise. */ | |
221 | static enum reg_class | |
222 | get_reg_class (int regno) | |
223 | { | |
224 | int hard_regno; | |
225 | ||
226 | if ((hard_regno = regno) >= FIRST_PSEUDO_REGISTER) | |
227 | hard_regno = lra_get_regno_hard_regno (regno); | |
228 | if (hard_regno >= 0) | |
229 | { | |
230 | hard_regno = get_final_hard_regno (hard_regno, 0); | |
231 | return REGNO_REG_CLASS (hard_regno); | |
232 | } | |
233 | if (regno >= new_regno_start) | |
234 | return lra_get_allocno_class (regno); | |
235 | return NO_REGS; | |
236 | } | |
237 | ||
238 | /* Return true if REG satisfies (or will satisfy) reg class constraint | |
239 | CL. Use elimination first if REG is a hard register. If REG is a | |
240 | reload pseudo created by this constraints pass, assume that it will | |
241 | be allocated a hard register from its allocno class, but allow that | |
242 | class to be narrowed to CL if it is currently a superset of CL. | |
243 | ||
244 | If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of | |
245 | REGNO (reg), or NO_REGS if no change in its class was needed. */ | |
246 | static bool | |
247 | in_class_p (rtx reg, enum reg_class cl, enum reg_class *new_class) | |
248 | { | |
249 | enum reg_class rclass, common_class; | |
250 | enum machine_mode reg_mode; | |
251 | int class_size, hard_regno, nregs, i, j; | |
252 | int regno = REGNO (reg); | |
1a8f8886 | 253 | |
c6a6cdaa | 254 | if (new_class != NULL) |
255 | *new_class = NO_REGS; | |
256 | if (regno < FIRST_PSEUDO_REGISTER) | |
257 | { | |
258 | rtx final_reg = reg; | |
259 | rtx *final_loc = &final_reg; | |
1a8f8886 | 260 | |
c6a6cdaa | 261 | lra_eliminate_reg_if_possible (final_loc); |
262 | return TEST_HARD_REG_BIT (reg_class_contents[cl], REGNO (*final_loc)); | |
263 | } | |
264 | reg_mode = GET_MODE (reg); | |
265 | rclass = get_reg_class (regno); | |
266 | if (regno < new_regno_start | |
267 | /* Do not allow the constraints for reload instructions to | |
268 | influence the classes of new pseudos. These reloads are | |
269 | typically moves that have many alternatives, and restricting | |
270 | reload pseudos for one alternative may lead to situations | |
271 | where other reload pseudos are no longer allocatable. */ | |
7619e612 | 272 | || (INSN_UID (curr_insn) >= new_insn_uid_start |
273 | && curr_insn_set != NULL | |
58f94f4a | 274 | && ((OBJECT_P (SET_SRC (curr_insn_set)) |
275 | && ! CONSTANT_P (SET_SRC (curr_insn_set))) | |
7619e612 | 276 | || (GET_CODE (SET_SRC (curr_insn_set)) == SUBREG |
58f94f4a | 277 | && OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set))) |
278 | && ! CONSTANT_P (SUBREG_REG (SET_SRC (curr_insn_set))))))) | |
c6a6cdaa | 279 | /* When we don't know what class will be used finally for reload |
280 | pseudos, we use ALL_REGS. */ | |
281 | return ((regno >= new_regno_start && rclass == ALL_REGS) | |
282 | || (rclass != NO_REGS && ira_class_subset_p[rclass][cl] | |
283 | && ! hard_reg_set_subset_p (reg_class_contents[cl], | |
284 | lra_no_alloc_regs))); | |
285 | else | |
286 | { | |
287 | common_class = ira_reg_class_subset[rclass][cl]; | |
288 | if (new_class != NULL) | |
289 | *new_class = common_class; | |
290 | if (hard_reg_set_subset_p (reg_class_contents[common_class], | |
291 | lra_no_alloc_regs)) | |
292 | return false; | |
293 | /* Check that there are enough allocatable regs. */ | |
294 | class_size = ira_class_hard_regs_num[common_class]; | |
295 | for (i = 0; i < class_size; i++) | |
296 | { | |
297 | hard_regno = ira_class_hard_regs[common_class][i]; | |
298 | nregs = hard_regno_nregs[hard_regno][reg_mode]; | |
299 | if (nregs == 1) | |
300 | return true; | |
301 | for (j = 0; j < nregs; j++) | |
68132dc4 | 302 | if (TEST_HARD_REG_BIT (lra_no_alloc_regs, hard_regno + j) |
303 | || ! TEST_HARD_REG_BIT (reg_class_contents[common_class], | |
304 | hard_regno + j)) | |
c6a6cdaa | 305 | break; |
306 | if (j >= nregs) | |
307 | return true; | |
308 | } | |
309 | return false; | |
310 | } | |
311 | } | |
312 | ||
313 | /* Return true if REGNO satisfies a memory constraint. */ | |
314 | static bool | |
315 | in_mem_p (int regno) | |
316 | { | |
317 | return get_reg_class (regno) == NO_REGS; | |
318 | } | |
319 | ||
320 | /* If we have decided to substitute X with another value, return that | |
321 | value, otherwise return X. */ | |
322 | static rtx | |
3b3a5e5f | 323 | get_equiv (rtx x) |
c6a6cdaa | 324 | { |
325 | int regno; | |
326 | rtx res; | |
327 | ||
328 | if (! REG_P (x) || (regno = REGNO (x)) < FIRST_PSEUDO_REGISTER | |
329 | || ! ira_reg_equiv[regno].defined_p | |
330 | || ! ira_reg_equiv[regno].profitable_p | |
331 | || lra_get_regno_hard_regno (regno) >= 0) | |
332 | return x; | |
333 | if ((res = ira_reg_equiv[regno].memory) != NULL_RTX) | |
334 | return res; | |
335 | if ((res = ira_reg_equiv[regno].constant) != NULL_RTX) | |
336 | return res; | |
337 | if ((res = ira_reg_equiv[regno].invariant) != NULL_RTX) | |
338 | return res; | |
339 | gcc_unreachable (); | |
340 | } | |
341 | ||
3b3a5e5f | 342 | /* If we have decided to substitute X with the equivalent value, |
343 | return that value after elimination for INSN, otherwise return | |
344 | X. */ | |
345 | static rtx | |
346 | get_equiv_with_elimination (rtx x, rtx insn) | |
347 | { | |
348 | rtx res = get_equiv (x); | |
349 | ||
350 | if (x == res || CONSTANT_P (res)) | |
351 | return res; | |
352 | return lra_eliminate_regs_1 (insn, res, GET_MODE (res), false, false, true); | |
353 | } | |
354 | ||
c6a6cdaa | 355 | /* Set up curr_operand_mode. */ |
356 | static void | |
357 | init_curr_operand_mode (void) | |
358 | { | |
359 | int nop = curr_static_id->n_operands; | |
360 | for (int i = 0; i < nop; i++) | |
361 | { | |
362 | enum machine_mode mode = GET_MODE (*curr_id->operand_loc[i]); | |
363 | if (mode == VOIDmode) | |
364 | { | |
365 | /* The .md mode for address operands is the mode of the | |
366 | addressed value rather than the mode of the address itself. */ | |
367 | if (curr_id->icode >= 0 && curr_static_id->operand[i].is_address) | |
368 | mode = Pmode; | |
369 | else | |
370 | mode = curr_static_id->operand[i].mode; | |
371 | } | |
372 | curr_operand_mode[i] = mode; | |
373 | } | |
374 | } | |
375 | ||
376 | \f | |
377 | ||
378 | /* The page contains code to reuse input reloads. */ | |
379 | ||
380 | /* Structure describes input reload of the current insns. */ | |
381 | struct input_reload | |
382 | { | |
383 | /* Reloaded value. */ | |
384 | rtx input; | |
385 | /* Reload pseudo used. */ | |
386 | rtx reg; | |
387 | }; | |
388 | ||
389 | /* The number of elements in the following array. */ | |
390 | static int curr_insn_input_reloads_num; | |
391 | /* Array containing info about input reloads. It is used to find the | |
392 | same input reload and reuse the reload pseudo in this case. */ | |
393 | static struct input_reload curr_insn_input_reloads[LRA_MAX_INSN_RELOADS]; | |
394 | ||
395 | /* Initiate data concerning reuse of input reloads for the current | |
396 | insn. */ | |
397 | static void | |
398 | init_curr_insn_input_reloads (void) | |
399 | { | |
400 | curr_insn_input_reloads_num = 0; | |
401 | } | |
402 | ||
c6a6cdaa | 403 | /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already |
404 | created input reload pseudo (only if TYPE is not OP_OUT). The | |
405 | result pseudo is returned through RESULT_REG. Return TRUE if we | |
406 | created a new pseudo, FALSE if we reused the already created input | |
407 | reload pseudo. Use TITLE to describe new registers for debug | |
408 | purposes. */ | |
409 | static bool | |
410 | get_reload_reg (enum op_type type, enum machine_mode mode, rtx original, | |
411 | enum reg_class rclass, const char *title, rtx *result_reg) | |
412 | { | |
413 | int i, regno; | |
414 | enum reg_class new_class; | |
415 | ||
416 | if (type == OP_OUT) | |
417 | { | |
418 | *result_reg | |
419 | = lra_create_new_reg_with_unique_value (mode, original, rclass, title); | |
420 | return true; | |
421 | } | |
85276115 | 422 | /* Prevent reuse value of expression with side effects, |
423 | e.g. volatile memory. */ | |
424 | if (! side_effects_p (original)) | |
425 | for (i = 0; i < curr_insn_input_reloads_num; i++) | |
426 | if (rtx_equal_p (curr_insn_input_reloads[i].input, original) | |
427 | && in_class_p (curr_insn_input_reloads[i].reg, rclass, &new_class)) | |
428 | { | |
5ef30aea | 429 | rtx reg = curr_insn_input_reloads[i].reg; |
430 | regno = REGNO (reg); | |
431 | /* If input is equal to original and both are VOIDmode, | |
432 | GET_MODE (reg) might be still different from mode. | |
433 | Ensure we don't return *result_reg with wrong mode. */ | |
434 | if (GET_MODE (reg) != mode) | |
435 | { | |
436 | if (GET_MODE_SIZE (GET_MODE (reg)) < GET_MODE_SIZE (mode)) | |
437 | continue; | |
438 | reg = lowpart_subreg (mode, reg, GET_MODE (reg)); | |
439 | if (reg == NULL_RTX || GET_CODE (reg) != SUBREG) | |
440 | continue; | |
441 | } | |
442 | *result_reg = reg; | |
85276115 | 443 | if (lra_dump_file != NULL) |
444 | { | |
445 | fprintf (lra_dump_file, " Reuse r%d for reload ", regno); | |
446 | dump_value_slim (lra_dump_file, original, 1); | |
447 | } | |
448 | if (new_class != lra_get_allocno_class (regno)) | |
7619e612 | 449 | lra_change_class (regno, new_class, ", change to", false); |
85276115 | 450 | if (lra_dump_file != NULL) |
451 | fprintf (lra_dump_file, "\n"); | |
452 | return false; | |
453 | } | |
c6a6cdaa | 454 | *result_reg = lra_create_new_reg (mode, original, rclass, title); |
455 | lra_assert (curr_insn_input_reloads_num < LRA_MAX_INSN_RELOADS); | |
456 | curr_insn_input_reloads[curr_insn_input_reloads_num].input = original; | |
457 | curr_insn_input_reloads[curr_insn_input_reloads_num++].reg = *result_reg; | |
458 | return true; | |
459 | } | |
460 | ||
461 | \f | |
462 | ||
463 | /* The page contains code to extract memory address parts. */ | |
464 | ||
c6a6cdaa | 465 | /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudos. */ |
466 | static inline bool | |
467 | ok_for_index_p_nonstrict (rtx reg) | |
468 | { | |
469 | unsigned regno = REGNO (reg); | |
1a8f8886 | 470 | |
c6a6cdaa | 471 | return regno >= FIRST_PSEUDO_REGISTER || REGNO_OK_FOR_INDEX_P (regno); |
472 | } | |
473 | ||
474 | /* A version of regno_ok_for_base_p for use here, when all pseudos | |
475 | should count as OK. Arguments as for regno_ok_for_base_p. */ | |
476 | static inline bool | |
477 | ok_for_base_p_nonstrict (rtx reg, enum machine_mode mode, addr_space_t as, | |
478 | enum rtx_code outer_code, enum rtx_code index_code) | |
479 | { | |
480 | unsigned regno = REGNO (reg); | |
481 | ||
482 | if (regno >= FIRST_PSEUDO_REGISTER) | |
483 | return true; | |
484 | return ok_for_base_p_1 (regno, mode, as, outer_code, index_code); | |
485 | } | |
486 | ||
c6a6cdaa | 487 | \f |
488 | ||
489 | /* The page contains major code to choose the current insn alternative | |
490 | and generate reloads for it. */ | |
491 | ||
492 | /* Return the offset from REGNO of the least significant register | |
493 | in (reg:MODE REGNO). | |
494 | ||
495 | This function is used to tell whether two registers satisfy | |
496 | a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if: | |
497 | ||
498 | REGNO1 + lra_constraint_offset (REGNO1, MODE1) | |
499 | == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */ | |
500 | int | |
501 | lra_constraint_offset (int regno, enum machine_mode mode) | |
502 | { | |
503 | lra_assert (regno < FIRST_PSEUDO_REGISTER); | |
504 | if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (mode) > UNITS_PER_WORD | |
505 | && SCALAR_INT_MODE_P (mode)) | |
506 | return hard_regno_nregs[regno][mode] - 1; | |
507 | return 0; | |
508 | } | |
509 | ||
510 | /* Like rtx_equal_p except that it allows a REG and a SUBREG to match | |
511 | if they are the same hard reg, and has special hacks for | |
512 | auto-increment and auto-decrement. This is specifically intended for | |
513 | process_alt_operands to use in determining whether two operands | |
514 | match. X is the operand whose number is the lower of the two. | |
515 | ||
516 | It is supposed that X is the output operand and Y is the input | |
517 | operand. Y_HARD_REGNO is the final hard regno of register Y or | |
518 | register in subreg Y as we know it now. Otherwise, it is a | |
519 | negative value. */ | |
520 | static bool | |
521 | operands_match_p (rtx x, rtx y, int y_hard_regno) | |
522 | { | |
523 | int i; | |
524 | RTX_CODE code = GET_CODE (x); | |
525 | const char *fmt; | |
526 | ||
527 | if (x == y) | |
528 | return true; | |
529 | if ((code == REG || (code == SUBREG && REG_P (SUBREG_REG (x)))) | |
530 | && (REG_P (y) || (GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y))))) | |
531 | { | |
532 | int j; | |
1a8f8886 | 533 | |
c6a6cdaa | 534 | i = get_hard_regno (x); |
535 | if (i < 0) | |
536 | goto slow; | |
537 | ||
538 | if ((j = y_hard_regno) < 0) | |
539 | goto slow; | |
540 | ||
541 | i += lra_constraint_offset (i, GET_MODE (x)); | |
542 | j += lra_constraint_offset (j, GET_MODE (y)); | |
543 | ||
544 | return i == j; | |
545 | } | |
546 | ||
547 | /* If two operands must match, because they are really a single | |
548 | operand of an assembler insn, then two post-increments are invalid | |
549 | because the assembler insn would increment only once. On the | |
550 | other hand, a post-increment matches ordinary indexing if the | |
551 | post-increment is the output operand. */ | |
552 | if (code == POST_DEC || code == POST_INC || code == POST_MODIFY) | |
553 | return operands_match_p (XEXP (x, 0), y, y_hard_regno); | |
554 | ||
555 | /* Two pre-increments are invalid because the assembler insn would | |
556 | increment only once. On the other hand, a pre-increment matches | |
557 | ordinary indexing if the pre-increment is the input operand. */ | |
558 | if (GET_CODE (y) == PRE_DEC || GET_CODE (y) == PRE_INC | |
559 | || GET_CODE (y) == PRE_MODIFY) | |
560 | return operands_match_p (x, XEXP (y, 0), -1); | |
1a8f8886 | 561 | |
c6a6cdaa | 562 | slow: |
563 | ||
564 | if (code == REG && GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y)) | |
565 | && x == SUBREG_REG (y)) | |
566 | return true; | |
567 | if (GET_CODE (y) == REG && code == SUBREG && REG_P (SUBREG_REG (x)) | |
568 | && SUBREG_REG (x) == y) | |
569 | return true; | |
570 | ||
571 | /* Now we have disposed of all the cases in which different rtx | |
572 | codes can match. */ | |
573 | if (code != GET_CODE (y)) | |
574 | return false; | |
575 | ||
576 | /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */ | |
577 | if (GET_MODE (x) != GET_MODE (y)) | |
578 | return false; | |
579 | ||
580 | switch (code) | |
581 | { | |
582 | CASE_CONST_UNIQUE: | |
583 | return false; | |
584 | ||
585 | case LABEL_REF: | |
586 | return XEXP (x, 0) == XEXP (y, 0); | |
587 | case SYMBOL_REF: | |
588 | return XSTR (x, 0) == XSTR (y, 0); | |
589 | ||
590 | default: | |
591 | break; | |
592 | } | |
593 | ||
594 | /* Compare the elements. If any pair of corresponding elements fail | |
595 | to match, return false for the whole things. */ | |
596 | ||
597 | fmt = GET_RTX_FORMAT (code); | |
598 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
599 | { | |
600 | int val, j; | |
601 | switch (fmt[i]) | |
602 | { | |
603 | case 'w': | |
604 | if (XWINT (x, i) != XWINT (y, i)) | |
605 | return false; | |
606 | break; | |
607 | ||
608 | case 'i': | |
609 | if (XINT (x, i) != XINT (y, i)) | |
610 | return false; | |
611 | break; | |
612 | ||
613 | case 'e': | |
614 | val = operands_match_p (XEXP (x, i), XEXP (y, i), -1); | |
615 | if (val == 0) | |
616 | return false; | |
617 | break; | |
618 | ||
619 | case '0': | |
620 | break; | |
621 | ||
622 | case 'E': | |
623 | if (XVECLEN (x, i) != XVECLEN (y, i)) | |
624 | return false; | |
625 | for (j = XVECLEN (x, i) - 1; j >= 0; --j) | |
626 | { | |
627 | val = operands_match_p (XVECEXP (x, i, j), XVECEXP (y, i, j), -1); | |
628 | if (val == 0) | |
629 | return false; | |
630 | } | |
631 | break; | |
632 | ||
633 | /* It is believed that rtx's at this level will never | |
634 | contain anything but integers and other rtx's, except for | |
635 | within LABEL_REFs and SYMBOL_REFs. */ | |
636 | default: | |
637 | gcc_unreachable (); | |
638 | } | |
639 | } | |
640 | return true; | |
641 | } | |
642 | ||
643 | /* True if X is a constant that can be forced into the constant pool. | |
644 | MODE is the mode of the operand, or VOIDmode if not known. */ | |
645 | #define CONST_POOL_OK_P(MODE, X) \ | |
646 | ((MODE) != VOIDmode \ | |
647 | && CONSTANT_P (X) \ | |
648 | && GET_CODE (X) != HIGH \ | |
649 | && !targetm.cannot_force_const_mem (MODE, X)) | |
650 | ||
651 | /* True if C is a non-empty register class that has too few registers | |
652 | to be safely used as a reload target class. */ | |
653 | #define SMALL_REGISTER_CLASS_P(C) \ | |
654 | (reg_class_size [(C)] == 1 \ | |
655 | || (reg_class_size [(C)] >= 1 && targetm.class_likely_spilled_p (C))) | |
656 | ||
657 | /* If REG is a reload pseudo, try to make its class satisfying CL. */ | |
658 | static void | |
659 | narrow_reload_pseudo_class (rtx reg, enum reg_class cl) | |
660 | { | |
661 | enum reg_class rclass; | |
662 | ||
663 | /* Do not make more accurate class from reloads generated. They are | |
664 | mostly moves with a lot of constraints. Making more accurate | |
665 | class may results in very narrow class and impossibility of find | |
666 | registers for several reloads of one insn. */ | |
667 | if (INSN_UID (curr_insn) >= new_insn_uid_start) | |
668 | return; | |
669 | if (GET_CODE (reg) == SUBREG) | |
670 | reg = SUBREG_REG (reg); | |
671 | if (! REG_P (reg) || (int) REGNO (reg) < new_regno_start) | |
672 | return; | |
673 | if (in_class_p (reg, cl, &rclass) && rclass != cl) | |
7619e612 | 674 | lra_change_class (REGNO (reg), rclass, " Change to", true); |
c6a6cdaa | 675 | } |
676 | ||
677 | /* Generate reloads for matching OUT and INS (array of input operand | |
678 | numbers with end marker -1) with reg class GOAL_CLASS. Add input | |
aa3ce8ba | 679 | and output reloads correspondingly to the lists *BEFORE and *AFTER. |
680 | OUT might be negative. In this case we generate input reloads for | |
681 | matched input operands INS. */ | |
c6a6cdaa | 682 | static void |
683 | match_reload (signed char out, signed char *ins, enum reg_class goal_class, | |
684 | rtx *before, rtx *after) | |
685 | { | |
686 | int i, in; | |
ae72d5b2 | 687 | rtx new_in_reg, new_out_reg, reg, clobber; |
c6a6cdaa | 688 | enum machine_mode inmode, outmode; |
689 | rtx in_rtx = *curr_id->operand_loc[ins[0]]; | |
aa3ce8ba | 690 | rtx out_rtx = out < 0 ? in_rtx : *curr_id->operand_loc[out]; |
c6a6cdaa | 691 | |
c6a6cdaa | 692 | inmode = curr_operand_mode[ins[0]]; |
aa3ce8ba | 693 | outmode = out < 0 ? inmode : curr_operand_mode[out]; |
c6a6cdaa | 694 | push_to_sequence (*before); |
695 | if (inmode != outmode) | |
696 | { | |
697 | if (GET_MODE_SIZE (inmode) > GET_MODE_SIZE (outmode)) | |
698 | { | |
699 | reg = new_in_reg | |
700 | = lra_create_new_reg_with_unique_value (inmode, in_rtx, | |
701 | goal_class, ""); | |
702 | if (SCALAR_INT_MODE_P (inmode)) | |
703 | new_out_reg = gen_lowpart_SUBREG (outmode, reg); | |
704 | else | |
705 | new_out_reg = gen_rtx_SUBREG (outmode, reg, 0); | |
ea99c7a1 | 706 | LRA_SUBREG_P (new_out_reg) = 1; |
ad6dc746 | 707 | /* If the input reg is dying here, we can use the same hard |
edfb1d8f | 708 | register for REG and IN_RTX. We do it only for original |
709 | pseudos as reload pseudos can die although original | |
710 | pseudos still live where reload pseudos dies. */ | |
711 | if (REG_P (in_rtx) && (int) REGNO (in_rtx) < lra_new_regno_start | |
ad6dc746 | 712 | && find_regno_note (curr_insn, REG_DEAD, REGNO (in_rtx))) |
a1064490 | 713 | lra_assign_reg_val (REGNO (in_rtx), REGNO (reg)); |
c6a6cdaa | 714 | } |
715 | else | |
716 | { | |
717 | reg = new_out_reg | |
718 | = lra_create_new_reg_with_unique_value (outmode, out_rtx, | |
719 | goal_class, ""); | |
720 | if (SCALAR_INT_MODE_P (outmode)) | |
721 | new_in_reg = gen_lowpart_SUBREG (inmode, reg); | |
722 | else | |
723 | new_in_reg = gen_rtx_SUBREG (inmode, reg, 0); | |
724 | /* NEW_IN_REG is non-paradoxical subreg. We don't want | |
725 | NEW_OUT_REG living above. We add clobber clause for | |
ae72d5b2 | 726 | this. This is just a temporary clobber. We can remove |
727 | it at the end of LRA work. */ | |
728 | clobber = emit_clobber (new_out_reg); | |
729 | LRA_TEMP_CLOBBER_P (PATTERN (clobber)) = 1; | |
ea99c7a1 | 730 | LRA_SUBREG_P (new_in_reg) = 1; |
ad6dc746 | 731 | if (GET_CODE (in_rtx) == SUBREG) |
732 | { | |
733 | rtx subreg_reg = SUBREG_REG (in_rtx); | |
734 | ||
735 | /* If SUBREG_REG is dying here and sub-registers IN_RTX | |
736 | and NEW_IN_REG are similar, we can use the same hard | |
737 | register for REG and SUBREG_REG. */ | |
edfb1d8f | 738 | if (REG_P (subreg_reg) |
739 | && (int) REGNO (subreg_reg) < lra_new_regno_start | |
740 | && GET_MODE (subreg_reg) == outmode | |
ad6dc746 | 741 | && SUBREG_BYTE (in_rtx) == SUBREG_BYTE (new_in_reg) |
742 | && find_regno_note (curr_insn, REG_DEAD, REGNO (subreg_reg))) | |
a1064490 | 743 | lra_assign_reg_val (REGNO (subreg_reg), REGNO (reg)); |
ad6dc746 | 744 | } |
c6a6cdaa | 745 | } |
746 | } | |
747 | else | |
748 | { | |
749 | /* Pseudos have values -- see comments for lra_reg_info. | |
750 | Different pseudos with the same value do not conflict even if | |
751 | they live in the same place. When we create a pseudo we | |
752 | assign value of original pseudo (if any) from which we | |
753 | created the new pseudo. If we create the pseudo from the | |
754 | input pseudo, the new pseudo will no conflict with the input | |
755 | pseudo which is wrong when the input pseudo lives after the | |
756 | insn and as the new pseudo value is changed by the insn | |
757 | output. Therefore we create the new pseudo from the output. | |
1a8f8886 | 758 | |
c6a6cdaa | 759 | We cannot reuse the current output register because we might |
760 | have a situation like "a <- a op b", where the constraints | |
761 | force the second input operand ("b") to match the output | |
762 | operand ("a"). "b" must then be copied into a new register | |
763 | so that it doesn't clobber the current value of "a". */ | |
1a8f8886 | 764 | |
c6a6cdaa | 765 | new_in_reg = new_out_reg |
766 | = lra_create_new_reg_with_unique_value (outmode, out_rtx, | |
767 | goal_class, ""); | |
768 | } | |
aa3ce8ba | 769 | /* In operand can be got from transformations before processing insn |
770 | constraints. One example of such transformations is subreg | |
771 | reloading (see function simplify_operand_subreg). The new | |
772 | pseudos created by the transformations might have inaccurate | |
c6a6cdaa | 773 | class (ALL_REGS) and we should make their classes more |
774 | accurate. */ | |
775 | narrow_reload_pseudo_class (in_rtx, goal_class); | |
c6a6cdaa | 776 | lra_emit_move (copy_rtx (new_in_reg), in_rtx); |
777 | *before = get_insns (); | |
778 | end_sequence (); | |
779 | for (i = 0; (in = ins[i]) >= 0; i++) | |
780 | { | |
781 | lra_assert | |
782 | (GET_MODE (*curr_id->operand_loc[in]) == VOIDmode | |
783 | || GET_MODE (new_in_reg) == GET_MODE (*curr_id->operand_loc[in])); | |
784 | *curr_id->operand_loc[in] = new_in_reg; | |
785 | } | |
786 | lra_update_dups (curr_id, ins); | |
aa3ce8ba | 787 | if (out < 0) |
788 | return; | |
789 | /* See a comment for the input operand above. */ | |
790 | narrow_reload_pseudo_class (out_rtx, goal_class); | |
c6a6cdaa | 791 | if (find_reg_note (curr_insn, REG_UNUSED, out_rtx) == NULL_RTX) |
792 | { | |
793 | start_sequence (); | |
794 | lra_emit_move (out_rtx, copy_rtx (new_out_reg)); | |
795 | emit_insn (*after); | |
796 | *after = get_insns (); | |
797 | end_sequence (); | |
798 | } | |
799 | *curr_id->operand_loc[out] = new_out_reg; | |
800 | lra_update_dup (curr_id, out); | |
801 | } | |
802 | ||
803 | /* Return register class which is union of all reg classes in insn | |
804 | constraint alternative string starting with P. */ | |
805 | static enum reg_class | |
806 | reg_class_from_constraints (const char *p) | |
807 | { | |
808 | int c, len; | |
809 | enum reg_class op_class = NO_REGS; | |
810 | ||
811 | do | |
812 | switch ((c = *p, len = CONSTRAINT_LEN (c, p)), c) | |
813 | { | |
814 | case '#': | |
815 | case ',': | |
816 | return op_class; | |
817 | ||
818 | case 'p': | |
819 | op_class = (reg_class_subunion | |
820 | [op_class][base_reg_class (VOIDmode, ADDR_SPACE_GENERIC, | |
821 | ADDRESS, SCRATCH)]); | |
822 | break; | |
1a8f8886 | 823 | |
c6a6cdaa | 824 | case 'g': |
825 | case 'r': | |
826 | op_class = reg_class_subunion[op_class][GENERAL_REGS]; | |
827 | break; | |
1a8f8886 | 828 | |
c6a6cdaa | 829 | default: |
830 | if (REG_CLASS_FROM_CONSTRAINT (c, p) == NO_REGS) | |
831 | { | |
832 | #ifdef EXTRA_CONSTRAINT_STR | |
833 | if (EXTRA_ADDRESS_CONSTRAINT (c, p)) | |
834 | op_class | |
835 | = (reg_class_subunion | |
836 | [op_class][base_reg_class (VOIDmode, ADDR_SPACE_GENERIC, | |
837 | ADDRESS, SCRATCH)]); | |
838 | #endif | |
839 | break; | |
840 | } | |
1a8f8886 | 841 | |
c6a6cdaa | 842 | op_class |
843 | = reg_class_subunion[op_class][REG_CLASS_FROM_CONSTRAINT (c, p)]; | |
844 | break; | |
845 | } | |
846 | while ((p += len), c); | |
847 | return op_class; | |
848 | } | |
849 | ||
850 | /* If OP is a register, return the class of the register as per | |
851 | get_reg_class, otherwise return NO_REGS. */ | |
852 | static inline enum reg_class | |
853 | get_op_class (rtx op) | |
854 | { | |
855 | return REG_P (op) ? get_reg_class (REGNO (op)) : NO_REGS; | |
856 | } | |
857 | ||
858 | /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo | |
859 | otherwise. If modes of MEM_PSEUDO and VAL are different, use | |
860 | SUBREG for VAL to make them equal. */ | |
861 | static rtx | |
862 | emit_spill_move (bool to_p, rtx mem_pseudo, rtx val) | |
863 | { | |
864 | if (GET_MODE (mem_pseudo) != GET_MODE (val)) | |
ea99c7a1 | 865 | { |
34575461 | 866 | /* Usually size of mem_pseudo is greater than val size but in |
867 | rare cases it can be less as it can be defined by target | |
868 | dependent macro HARD_REGNO_CALLER_SAVE_MODE. */ | |
cc0dc61b | 869 | if (! MEM_P (val)) |
870 | { | |
871 | val = gen_rtx_SUBREG (GET_MODE (mem_pseudo), | |
872 | GET_CODE (val) == SUBREG ? SUBREG_REG (val) : val, | |
873 | 0); | |
874 | LRA_SUBREG_P (val) = 1; | |
875 | } | |
876 | else | |
877 | { | |
878 | mem_pseudo = gen_lowpart_SUBREG (GET_MODE (val), mem_pseudo); | |
879 | LRA_SUBREG_P (mem_pseudo) = 1; | |
880 | } | |
ea99c7a1 | 881 | } |
c6a6cdaa | 882 | return (to_p |
50580188 | 883 | ? gen_move_insn (mem_pseudo, val) |
884 | : gen_move_insn (val, mem_pseudo)); | |
c6a6cdaa | 885 | } |
886 | ||
887 | /* Process a special case insn (register move), return true if we | |
ea99c7a1 | 888 | don't need to process it anymore. INSN should be a single set |
889 | insn. Set up that RTL was changed through CHANGE_P and macro | |
890 | SECONDARY_MEMORY_NEEDED says to use secondary memory through | |
891 | SEC_MEM_P. */ | |
c6a6cdaa | 892 | static bool |
ea99c7a1 | 893 | check_and_process_move (bool *change_p, bool *sec_mem_p ATTRIBUTE_UNUSED) |
c6a6cdaa | 894 | { |
895 | int sregno, dregno; | |
ea99c7a1 | 896 | rtx dest, src, dreg, sreg, old_sreg, new_reg, before, scratch_reg; |
c6a6cdaa | 897 | enum reg_class dclass, sclass, secondary_class; |
898 | enum machine_mode sreg_mode; | |
899 | secondary_reload_info sri; | |
900 | ||
ea99c7a1 | 901 | lra_assert (curr_insn_set != NULL_RTX); |
902 | dreg = dest = SET_DEST (curr_insn_set); | |
903 | sreg = src = SET_SRC (curr_insn_set); | |
c6a6cdaa | 904 | if (GET_CODE (dest) == SUBREG) |
905 | dreg = SUBREG_REG (dest); | |
906 | if (GET_CODE (src) == SUBREG) | |
907 | sreg = SUBREG_REG (src); | |
cc0dc61b | 908 | if (! (REG_P (dreg) || MEM_P (dreg)) || ! (REG_P (sreg) || MEM_P (sreg))) |
c6a6cdaa | 909 | return false; |
910 | sclass = dclass = NO_REGS; | |
c6a6cdaa | 911 | if (REG_P (dreg)) |
912 | dclass = get_reg_class (REGNO (dreg)); | |
913 | if (dclass == ALL_REGS) | |
914 | /* ALL_REGS is used for new pseudos created by transformations | |
915 | like reload of SUBREG_REG (see function | |
916 | simplify_operand_subreg). We don't know their class yet. We | |
917 | should figure out the class from processing the insn | |
918 | constraints not in this fast path function. Even if ALL_REGS | |
919 | were a right class for the pseudo, secondary_... hooks usually | |
920 | are not define for ALL_REGS. */ | |
921 | return false; | |
922 | sreg_mode = GET_MODE (sreg); | |
923 | old_sreg = sreg; | |
c6a6cdaa | 924 | if (REG_P (sreg)) |
925 | sclass = get_reg_class (REGNO (sreg)); | |
926 | if (sclass == ALL_REGS) | |
927 | /* See comments above. */ | |
928 | return false; | |
cc0dc61b | 929 | if (sclass == NO_REGS && dclass == NO_REGS) |
930 | return false; | |
c6a6cdaa | 931 | #ifdef SECONDARY_MEMORY_NEEDED |
cc0dc61b | 932 | if (SECONDARY_MEMORY_NEEDED (sclass, dclass, GET_MODE (src)) |
933 | #ifdef SECONDARY_MEMORY_NEEDED_MODE | |
934 | && ((sclass != NO_REGS && dclass != NO_REGS) | |
935 | || GET_MODE (src) != SECONDARY_MEMORY_NEEDED_MODE (GET_MODE (src))) | |
936 | #endif | |
937 | ) | |
c6a6cdaa | 938 | { |
939 | *sec_mem_p = true; | |
940 | return false; | |
941 | } | |
942 | #endif | |
cc0dc61b | 943 | if (! REG_P (dreg) || ! REG_P (sreg)) |
944 | return false; | |
c6a6cdaa | 945 | sri.prev_sri = NULL; |
946 | sri.icode = CODE_FOR_nothing; | |
947 | sri.extra_cost = 0; | |
948 | secondary_class = NO_REGS; | |
949 | /* Set up hard register for a reload pseudo for hook | |
950 | secondary_reload because some targets just ignore unassigned | |
951 | pseudos in the hook. */ | |
952 | if (dclass != NO_REGS && lra_get_regno_hard_regno (REGNO (dreg)) < 0) | |
953 | { | |
954 | dregno = REGNO (dreg); | |
955 | reg_renumber[dregno] = ira_class_hard_regs[dclass][0]; | |
956 | } | |
957 | else | |
958 | dregno = -1; | |
959 | if (sclass != NO_REGS && lra_get_regno_hard_regno (REGNO (sreg)) < 0) | |
960 | { | |
961 | sregno = REGNO (sreg); | |
962 | reg_renumber[sregno] = ira_class_hard_regs[sclass][0]; | |
963 | } | |
964 | else | |
965 | sregno = -1; | |
966 | if (sclass != NO_REGS) | |
967 | secondary_class | |
968 | = (enum reg_class) targetm.secondary_reload (false, dest, | |
969 | (reg_class_t) sclass, | |
970 | GET_MODE (src), &sri); | |
971 | if (sclass == NO_REGS | |
972 | || ((secondary_class != NO_REGS || sri.icode != CODE_FOR_nothing) | |
973 | && dclass != NO_REGS)) | |
974 | { | |
c6a6cdaa | 975 | enum reg_class old_sclass = secondary_class; |
976 | secondary_reload_info old_sri = sri; | |
c6a6cdaa | 977 | |
978 | sri.prev_sri = NULL; | |
979 | sri.icode = CODE_FOR_nothing; | |
980 | sri.extra_cost = 0; | |
981 | secondary_class | |
982 | = (enum reg_class) targetm.secondary_reload (true, sreg, | |
983 | (reg_class_t) dclass, | |
984 | sreg_mode, &sri); | |
985 | /* Check the target hook consistency. */ | |
986 | lra_assert | |
987 | ((secondary_class == NO_REGS && sri.icode == CODE_FOR_nothing) | |
988 | || (old_sclass == NO_REGS && old_sri.icode == CODE_FOR_nothing) | |
989 | || (secondary_class == old_sclass && sri.icode == old_sri.icode)); | |
990 | } | |
991 | if (sregno >= 0) | |
992 | reg_renumber [sregno] = -1; | |
993 | if (dregno >= 0) | |
994 | reg_renumber [dregno] = -1; | |
995 | if (secondary_class == NO_REGS && sri.icode == CODE_FOR_nothing) | |
996 | return false; | |
997 | *change_p = true; | |
998 | new_reg = NULL_RTX; | |
999 | if (secondary_class != NO_REGS) | |
1000 | new_reg = lra_create_new_reg_with_unique_value (sreg_mode, NULL_RTX, | |
1001 | secondary_class, | |
1002 | "secondary"); | |
1003 | start_sequence (); | |
1004 | if (old_sreg != sreg) | |
1005 | sreg = copy_rtx (sreg); | |
1006 | if (sri.icode == CODE_FOR_nothing) | |
1007 | lra_emit_move (new_reg, sreg); | |
1008 | else | |
1009 | { | |
1010 | enum reg_class scratch_class; | |
1011 | ||
1012 | scratch_class = (reg_class_from_constraints | |
1013 | (insn_data[sri.icode].operand[2].constraint)); | |
1014 | scratch_reg = (lra_create_new_reg_with_unique_value | |
1015 | (insn_data[sri.icode].operand[2].mode, NULL_RTX, | |
1016 | scratch_class, "scratch")); | |
1017 | emit_insn (GEN_FCN (sri.icode) (new_reg != NULL_RTX ? new_reg : dest, | |
1018 | sreg, scratch_reg)); | |
1019 | } | |
1020 | before = get_insns (); | |
1021 | end_sequence (); | |
1022 | lra_process_new_insns (curr_insn, before, NULL_RTX, "Inserting the move"); | |
1023 | if (new_reg != NULL_RTX) | |
1024 | { | |
1025 | if (GET_CODE (src) == SUBREG) | |
1026 | SUBREG_REG (src) = new_reg; | |
1027 | else | |
ea99c7a1 | 1028 | SET_SRC (curr_insn_set) = new_reg; |
c6a6cdaa | 1029 | } |
1030 | else | |
1031 | { | |
1032 | if (lra_dump_file != NULL) | |
1033 | { | |
1034 | fprintf (lra_dump_file, "Deleting move %u\n", INSN_UID (curr_insn)); | |
6dde9719 | 1035 | dump_insn_slim (lra_dump_file, curr_insn); |
c6a6cdaa | 1036 | } |
1037 | lra_set_insn_deleted (curr_insn); | |
1038 | return true; | |
1039 | } | |
1040 | return false; | |
1041 | } | |
1042 | ||
1043 | /* The following data describe the result of process_alt_operands. | |
1044 | The data are used in curr_insn_transform to generate reloads. */ | |
1045 | ||
1046 | /* The chosen reg classes which should be used for the corresponding | |
1047 | operands. */ | |
1048 | static enum reg_class goal_alt[MAX_RECOG_OPERANDS]; | |
1049 | /* True if the operand should be the same as another operand and that | |
1050 | other operand does not need a reload. */ | |
1051 | static bool goal_alt_match_win[MAX_RECOG_OPERANDS]; | |
1052 | /* True if the operand does not need a reload. */ | |
1053 | static bool goal_alt_win[MAX_RECOG_OPERANDS]; | |
1054 | /* True if the operand can be offsetable memory. */ | |
1055 | static bool goal_alt_offmemok[MAX_RECOG_OPERANDS]; | |
1056 | /* The number of an operand to which given operand can be matched to. */ | |
1057 | static int goal_alt_matches[MAX_RECOG_OPERANDS]; | |
1058 | /* The number of elements in the following array. */ | |
1059 | static int goal_alt_dont_inherit_ops_num; | |
1060 | /* Numbers of operands whose reload pseudos should not be inherited. */ | |
1061 | static int goal_alt_dont_inherit_ops[MAX_RECOG_OPERANDS]; | |
1062 | /* True if the insn commutative operands should be swapped. */ | |
1063 | static bool goal_alt_swapped; | |
1064 | /* The chosen insn alternative. */ | |
1065 | static int goal_alt_number; | |
1066 | ||
1067 | /* The following five variables are used to choose the best insn | |
1068 | alternative. They reflect final characteristics of the best | |
1069 | alternative. */ | |
1070 | ||
1071 | /* Number of necessary reloads and overall cost reflecting the | |
1072 | previous value and other unpleasantness of the best alternative. */ | |
1073 | static int best_losers, best_overall; | |
c6a6cdaa | 1074 | /* Overall number hard registers used for reloads. For example, on |
1075 | some targets we need 2 general registers to reload DFmode and only | |
1076 | one floating point register. */ | |
1077 | static int best_reload_nregs; | |
1078 | /* Overall number reflecting distances of previous reloading the same | |
1079 | value. The distances are counted from the current BB start. It is | |
1080 | used to improve inheritance chances. */ | |
1081 | static int best_reload_sum; | |
1082 | ||
1083 | /* True if the current insn should have no correspondingly input or | |
1084 | output reloads. */ | |
1085 | static bool no_input_reloads_p, no_output_reloads_p; | |
1086 | ||
1087 | /* True if we swapped the commutative operands in the current | |
1088 | insn. */ | |
1089 | static int curr_swapped; | |
1090 | ||
1091 | /* Arrange for address element *LOC to be a register of class CL. | |
1092 | Add any input reloads to list BEFORE. AFTER is nonnull if *LOC is an | |
1093 | automodified value; handle that case by adding the required output | |
1094 | reloads to list AFTER. Return true if the RTL was changed. */ | |
1095 | static bool | |
1096 | process_addr_reg (rtx *loc, rtx *before, rtx *after, enum reg_class cl) | |
1097 | { | |
1098 | int regno; | |
1099 | enum reg_class rclass, new_class; | |
1efe9e9d | 1100 | rtx reg; |
c6a6cdaa | 1101 | rtx new_reg; |
1102 | enum machine_mode mode; | |
1103 | bool before_p = false; | |
1104 | ||
1efe9e9d | 1105 | loc = strip_subreg (loc); |
1106 | reg = *loc; | |
c6a6cdaa | 1107 | mode = GET_MODE (reg); |
1108 | if (! REG_P (reg)) | |
1109 | { | |
1110 | /* Always reload memory in an address even if the target supports | |
1111 | such addresses. */ | |
1112 | new_reg = lra_create_new_reg_with_unique_value (mode, reg, cl, "address"); | |
1113 | before_p = true; | |
1114 | } | |
1115 | else | |
1116 | { | |
1117 | regno = REGNO (reg); | |
1118 | rclass = get_reg_class (regno); | |
3b3a5e5f | 1119 | if ((*loc = get_equiv_with_elimination (reg, curr_insn)) != reg) |
c6a6cdaa | 1120 | { |
1121 | if (lra_dump_file != NULL) | |
1122 | { | |
1123 | fprintf (lra_dump_file, | |
1124 | "Changing pseudo %d in address of insn %u on equiv ", | |
1125 | REGNO (reg), INSN_UID (curr_insn)); | |
6dde9719 | 1126 | dump_value_slim (lra_dump_file, *loc, 1); |
c6a6cdaa | 1127 | fprintf (lra_dump_file, "\n"); |
1128 | } | |
1129 | *loc = copy_rtx (*loc); | |
1130 | } | |
1131 | if (*loc != reg || ! in_class_p (reg, cl, &new_class)) | |
1132 | { | |
1133 | reg = *loc; | |
1134 | if (get_reload_reg (after == NULL ? OP_IN : OP_INOUT, | |
1135 | mode, reg, cl, "address", &new_reg)) | |
1136 | before_p = true; | |
1137 | } | |
1138 | else if (new_class != NO_REGS && rclass != new_class) | |
1139 | { | |
7619e612 | 1140 | lra_change_class (regno, new_class, " Change to", true); |
c6a6cdaa | 1141 | return false; |
1142 | } | |
1143 | else | |
1144 | return false; | |
1145 | } | |
1146 | if (before_p) | |
1147 | { | |
1148 | push_to_sequence (*before); | |
1149 | lra_emit_move (new_reg, reg); | |
1150 | *before = get_insns (); | |
1151 | end_sequence (); | |
1152 | } | |
1153 | *loc = new_reg; | |
1154 | if (after != NULL) | |
1155 | { | |
1156 | start_sequence (); | |
1157 | lra_emit_move (reg, new_reg); | |
1158 | emit_insn (*after); | |
1159 | *after = get_insns (); | |
1160 | end_sequence (); | |
1161 | } | |
1162 | return true; | |
1163 | } | |
1164 | ||
c5334148 | 1165 | /* Insert move insn in simplify_operand_subreg. BEFORE returns |
1166 | the insn to be inserted before curr insn. AFTER returns the | |
1167 | the insn to be inserted after curr insn. ORIGREG and NEWREG | |
1168 | are the original reg and new reg for reload. */ | |
1169 | static void | |
1170 | insert_move_for_subreg (rtx *before, rtx *after, rtx origreg, rtx newreg) | |
1171 | { | |
1172 | if (before) | |
1173 | { | |
1174 | push_to_sequence (*before); | |
1175 | lra_emit_move (newreg, origreg); | |
1176 | *before = get_insns (); | |
1177 | end_sequence (); | |
1178 | } | |
1179 | if (after) | |
1180 | { | |
1181 | start_sequence (); | |
1182 | lra_emit_move (origreg, newreg); | |
1183 | emit_insn (*after); | |
1184 | *after = get_insns (); | |
1185 | end_sequence (); | |
1186 | } | |
1187 | } | |
1188 | ||
c6a6cdaa | 1189 | /* Make reloads for subreg in operand NOP with internal subreg mode |
1190 | REG_MODE, add new reloads for further processing. Return true if | |
1191 | any reload was generated. */ | |
1192 | static bool | |
1193 | simplify_operand_subreg (int nop, enum machine_mode reg_mode) | |
1194 | { | |
1195 | int hard_regno; | |
1196 | rtx before, after; | |
1197 | enum machine_mode mode; | |
1198 | rtx reg, new_reg; | |
1199 | rtx operand = *curr_id->operand_loc[nop]; | |
c5334148 | 1200 | enum reg_class regclass; |
1201 | enum op_type type; | |
c6a6cdaa | 1202 | |
1203 | before = after = NULL_RTX; | |
1204 | ||
1205 | if (GET_CODE (operand) != SUBREG) | |
1206 | return false; | |
1a8f8886 | 1207 | |
c6a6cdaa | 1208 | mode = GET_MODE (operand); |
1209 | reg = SUBREG_REG (operand); | |
c5334148 | 1210 | type = curr_static_id->operand[nop].type; |
c6a6cdaa | 1211 | /* If we change address for paradoxical subreg of memory, the |
1212 | address might violate the necessary alignment or the access might | |
fc8a0f60 | 1213 | be slow. So take this into consideration. We should not worry |
1214 | about access beyond allocated memory for paradoxical memory | |
1215 | subregs as we don't substitute such equiv memory (see processing | |
1216 | equivalences in function lra_constraints) and because for spilled | |
1217 | pseudos we allocate stack memory enough for the biggest | |
1218 | corresponding paradoxical subreg. */ | |
c6a6cdaa | 1219 | if ((MEM_P (reg) |
341cc052 | 1220 | && (! SLOW_UNALIGNED_ACCESS (mode, MEM_ALIGN (reg)) |
c6a6cdaa | 1221 | || MEM_ALIGN (reg) >= GET_MODE_ALIGNMENT (mode))) |
1222 | || (REG_P (reg) && REGNO (reg) < FIRST_PSEUDO_REGISTER)) | |
1223 | { | |
1224 | alter_subreg (curr_id->operand_loc[nop], false); | |
1225 | return true; | |
1226 | } | |
1227 | /* Put constant into memory when we have mixed modes. It generates | |
1228 | a better code in most cases as it does not need a secondary | |
1229 | reload memory. It also prevents LRA looping when LRA is using | |
1230 | secondary reload memory again and again. */ | |
1231 | if (CONSTANT_P (reg) && CONST_POOL_OK_P (reg_mode, reg) | |
1232 | && SCALAR_INT_MODE_P (reg_mode) != SCALAR_INT_MODE_P (mode)) | |
1233 | { | |
1234 | SUBREG_REG (operand) = force_const_mem (reg_mode, reg); | |
1235 | alter_subreg (curr_id->operand_loc[nop], false); | |
1236 | return true; | |
1237 | } | |
1238 | /* Force a reload of the SUBREG_REG if this is a constant or PLUS or | |
1239 | if there may be a problem accessing OPERAND in the outer | |
1240 | mode. */ | |
1241 | if ((REG_P (reg) | |
1242 | && REGNO (reg) >= FIRST_PSEUDO_REGISTER | |
1243 | && (hard_regno = lra_get_regno_hard_regno (REGNO (reg))) >= 0 | |
1244 | /* Don't reload paradoxical subregs because we could be looping | |
1245 | having repeatedly final regno out of hard regs range. */ | |
1246 | && (hard_regno_nregs[hard_regno][GET_MODE (reg)] | |
1247 | >= hard_regno_nregs[hard_regno][mode]) | |
1248 | && simplify_subreg_regno (hard_regno, GET_MODE (reg), | |
ea99c7a1 | 1249 | SUBREG_BYTE (operand), mode) < 0 |
1250 | /* Don't reload subreg for matching reload. It is actually | |
1251 | valid subreg in LRA. */ | |
1252 | && ! LRA_SUBREG_P (operand)) | |
c6a6cdaa | 1253 | || CONSTANT_P (reg) || GET_CODE (reg) == PLUS || MEM_P (reg)) |
1254 | { | |
c6a6cdaa | 1255 | /* The class will be defined later in curr_insn_transform. */ |
1256 | enum reg_class rclass | |
1257 | = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS); | |
1258 | ||
4aa54340 | 1259 | if (get_reload_reg (curr_static_id->operand[nop].type, reg_mode, reg, |
1260 | rclass, "subreg reg", &new_reg)) | |
c6a6cdaa | 1261 | { |
c5334148 | 1262 | bool insert_before, insert_after; |
1f3a048a | 1263 | bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg)); |
c5334148 | 1264 | |
1265 | insert_before = (type != OP_OUT | |
1266 | || GET_MODE_SIZE (GET_MODE (reg)) > GET_MODE_SIZE (mode)); | |
1267 | insert_after = (type != OP_IN); | |
1268 | insert_move_for_subreg (insert_before ? &before : NULL, | |
1269 | insert_after ? &after : NULL, | |
1270 | reg, new_reg); | |
c6a6cdaa | 1271 | } |
1272 | SUBREG_REG (operand) = new_reg; | |
1273 | lra_process_new_insns (curr_insn, before, after, | |
1274 | "Inserting subreg reload"); | |
1275 | return true; | |
1276 | } | |
c5334148 | 1277 | /* Force a reload for a paradoxical subreg. For paradoxical subreg, |
1278 | IRA allocates hardreg to the inner pseudo reg according to its mode | |
1279 | instead of the outermode, so the size of the hardreg may not be enough | |
1280 | to contain the outermode operand, in that case we may need to insert | |
1281 | reload for the reg. For the following two types of paradoxical subreg, | |
1282 | we need to insert reload: | |
1283 | 1. If the op_type is OP_IN, and the hardreg could not be paired with | |
1284 | other hardreg to contain the outermode operand | |
1285 | (checked by in_hard_reg_set_p), we need to insert the reload. | |
1286 | 2. If the op_type is OP_OUT or OP_INOUT. | |
1287 | ||
1288 | Here is a paradoxical subreg example showing how the reload is generated: | |
1289 | ||
1290 | (insn 5 4 7 2 (set (reg:TI 106 [ __comp ]) | |
1291 | (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64} | |
1292 | ||
1293 | In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example | |
1294 | here, if reg107 is assigned to hardreg R15, because R15 is the last | |
1295 | hardreg, compiler cannot find another hardreg to pair with R15 to | |
1296 | contain TImode data. So we insert a TImode reload reg180 for it. | |
1297 | After reload is inserted: | |
1298 | ||
1299 | (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0) | |
1300 | (reg:DI 107 [ __comp ])) -1 | |
1301 | (insn 5 4 7 2 (set (reg:TI 106 [ __comp ]) | |
1302 | (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64} | |
1303 | ||
1304 | Two reload hard registers will be allocated to reg180 to save TImode data | |
1305 | in LRA_assign. */ | |
1306 | else if (REG_P (reg) | |
1307 | && REGNO (reg) >= FIRST_PSEUDO_REGISTER | |
1308 | && (hard_regno = lra_get_regno_hard_regno (REGNO (reg))) >= 0 | |
1309 | && (hard_regno_nregs[hard_regno][GET_MODE (reg)] | |
1310 | < hard_regno_nregs[hard_regno][mode]) | |
1311 | && (regclass = lra_get_allocno_class (REGNO (reg))) | |
1312 | && (type != OP_IN | |
1313 | || !in_hard_reg_set_p (reg_class_contents[regclass], | |
1314 | mode, hard_regno))) | |
1315 | { | |
1316 | /* The class will be defined later in curr_insn_transform. */ | |
1317 | enum reg_class rclass | |
1318 | = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS); | |
1319 | ||
1320 | if (get_reload_reg (curr_static_id->operand[nop].type, mode, reg, | |
1321 | rclass, "paradoxical subreg", &new_reg)) | |
1322 | { | |
1323 | rtx subreg; | |
1324 | bool insert_before, insert_after; | |
1325 | ||
1326 | PUT_MODE (new_reg, mode); | |
1327 | subreg = simplify_gen_subreg (GET_MODE (reg), new_reg, mode, 0); | |
1328 | bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg)); | |
1329 | ||
1330 | insert_before = (type != OP_OUT); | |
1331 | insert_after = (type != OP_IN); | |
1332 | insert_move_for_subreg (insert_before ? &before : NULL, | |
1333 | insert_after ? &after : NULL, | |
1334 | reg, subreg); | |
1335 | } | |
1336 | SUBREG_REG (operand) = new_reg; | |
1337 | lra_process_new_insns (curr_insn, before, after, | |
1338 | "Inserting paradoxical subreg reload"); | |
1339 | return true; | |
1340 | } | |
c6a6cdaa | 1341 | return false; |
1342 | } | |
1343 | ||
1344 | /* Return TRUE if X refers for a hard register from SET. */ | |
1345 | static bool | |
1346 | uses_hard_regs_p (rtx x, HARD_REG_SET set) | |
1347 | { | |
1348 | int i, j, x_hard_regno; | |
1349 | enum machine_mode mode; | |
1350 | const char *fmt; | |
1351 | enum rtx_code code; | |
1352 | ||
1353 | if (x == NULL_RTX) | |
1354 | return false; | |
1355 | code = GET_CODE (x); | |
1356 | mode = GET_MODE (x); | |
1357 | if (code == SUBREG) | |
1358 | { | |
1359 | x = SUBREG_REG (x); | |
1360 | code = GET_CODE (x); | |
1361 | if (GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (mode)) | |
1362 | mode = GET_MODE (x); | |
1363 | } | |
1a8f8886 | 1364 | |
c6a6cdaa | 1365 | if (REG_P (x)) |
1366 | { | |
1367 | x_hard_regno = get_hard_regno (x); | |
1368 | return (x_hard_regno >= 0 | |
1369 | && overlaps_hard_reg_set_p (set, mode, x_hard_regno)); | |
1370 | } | |
1371 | if (MEM_P (x)) | |
1372 | { | |
1efe9e9d | 1373 | struct address_info ad; |
c6a6cdaa | 1374 | |
1efe9e9d | 1375 | decompose_mem_address (&ad, x); |
1376 | if (ad.base_term != NULL && uses_hard_regs_p (*ad.base_term, set)) | |
1377 | return true; | |
1378 | if (ad.index_term != NULL && uses_hard_regs_p (*ad.index_term, set)) | |
1379 | return true; | |
c6a6cdaa | 1380 | } |
1381 | fmt = GET_RTX_FORMAT (code); | |
1382 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1383 | { | |
1384 | if (fmt[i] == 'e') | |
1385 | { | |
1386 | if (uses_hard_regs_p (XEXP (x, i), set)) | |
1387 | return true; | |
1388 | } | |
1389 | else if (fmt[i] == 'E') | |
1390 | { | |
1391 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
1392 | if (uses_hard_regs_p (XVECEXP (x, i, j), set)) | |
1393 | return true; | |
1394 | } | |
1395 | } | |
1396 | return false; | |
1397 | } | |
1398 | ||
1399 | /* Return true if OP is a spilled pseudo. */ | |
1400 | static inline bool | |
1401 | spilled_pseudo_p (rtx op) | |
1402 | { | |
1403 | return (REG_P (op) | |
1404 | && REGNO (op) >= FIRST_PSEUDO_REGISTER && in_mem_p (REGNO (op))); | |
1405 | } | |
1406 | ||
1407 | /* Return true if X is a general constant. */ | |
1408 | static inline bool | |
1409 | general_constant_p (rtx x) | |
1410 | { | |
1411 | return CONSTANT_P (x) && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (x)); | |
1412 | } | |
1413 | ||
ea99c7a1 | 1414 | static bool |
1415 | reg_in_class_p (rtx reg, enum reg_class cl) | |
1416 | { | |
1417 | if (cl == NO_REGS) | |
1418 | return get_reg_class (REGNO (reg)) == NO_REGS; | |
1419 | return in_class_p (reg, cl, NULL); | |
1420 | } | |
1421 | ||
c6a6cdaa | 1422 | /* Major function to choose the current insn alternative and what |
1423 | operands should be reloaded and how. If ONLY_ALTERNATIVE is not | |
1424 | negative we should consider only this alternative. Return false if | |
1425 | we can not choose the alternative or find how to reload the | |
1426 | operands. */ | |
1427 | static bool | |
1428 | process_alt_operands (int only_alternative) | |
1429 | { | |
1430 | bool ok_p = false; | |
273c330a | 1431 | int nop, overall, nalt; |
c6a6cdaa | 1432 | int n_alternatives = curr_static_id->n_alternatives; |
1433 | int n_operands = curr_static_id->n_operands; | |
1434 | /* LOSERS counts the operands that don't fit this alternative and | |
1435 | would require loading. */ | |
1436 | int losers; | |
1437 | /* REJECT is a count of how undesirable this alternative says it is | |
1438 | if any reloading is required. If the alternative matches exactly | |
1439 | then REJECT is ignored, but otherwise it gets this much counted | |
1440 | against it in addition to the reloading needed. */ | |
1441 | int reject; | |
1442 | /* The number of elements in the following array. */ | |
1443 | int early_clobbered_regs_num; | |
1444 | /* Numbers of operands which are early clobber registers. */ | |
1445 | int early_clobbered_nops[MAX_RECOG_OPERANDS]; | |
1446 | enum reg_class curr_alt[MAX_RECOG_OPERANDS]; | |
1447 | HARD_REG_SET curr_alt_set[MAX_RECOG_OPERANDS]; | |
1448 | bool curr_alt_match_win[MAX_RECOG_OPERANDS]; | |
1449 | bool curr_alt_win[MAX_RECOG_OPERANDS]; | |
1450 | bool curr_alt_offmemok[MAX_RECOG_OPERANDS]; | |
1451 | int curr_alt_matches[MAX_RECOG_OPERANDS]; | |
1452 | /* The number of elements in the following array. */ | |
1453 | int curr_alt_dont_inherit_ops_num; | |
1454 | /* Numbers of operands whose reload pseudos should not be inherited. */ | |
1455 | int curr_alt_dont_inherit_ops[MAX_RECOG_OPERANDS]; | |
1456 | rtx op; | |
1457 | /* The register when the operand is a subreg of register, otherwise the | |
1458 | operand itself. */ | |
1459 | rtx no_subreg_reg_operand[MAX_RECOG_OPERANDS]; | |
1460 | /* The register if the operand is a register or subreg of register, | |
1461 | otherwise NULL. */ | |
1462 | rtx operand_reg[MAX_RECOG_OPERANDS]; | |
1463 | int hard_regno[MAX_RECOG_OPERANDS]; | |
1464 | enum machine_mode biggest_mode[MAX_RECOG_OPERANDS]; | |
1465 | int reload_nregs, reload_sum; | |
1466 | bool costly_p; | |
1467 | enum reg_class cl; | |
1468 | ||
1469 | /* Calculate some data common for all alternatives to speed up the | |
1470 | function. */ | |
1471 | for (nop = 0; nop < n_operands; nop++) | |
1472 | { | |
0244be31 | 1473 | rtx reg; |
1474 | ||
c6a6cdaa | 1475 | op = no_subreg_reg_operand[nop] = *curr_id->operand_loc[nop]; |
1476 | /* The real hard regno of the operand after the allocation. */ | |
1477 | hard_regno[nop] = get_hard_regno (op); | |
1a8f8886 | 1478 | |
0244be31 | 1479 | operand_reg[nop] = reg = op; |
1480 | biggest_mode[nop] = GET_MODE (op); | |
1481 | if (GET_CODE (op) == SUBREG) | |
c6a6cdaa | 1482 | { |
0244be31 | 1483 | operand_reg[nop] = reg = SUBREG_REG (op); |
c6a6cdaa | 1484 | if (GET_MODE_SIZE (biggest_mode[nop]) |
0244be31 | 1485 | < GET_MODE_SIZE (GET_MODE (reg))) |
1486 | biggest_mode[nop] = GET_MODE (reg); | |
c6a6cdaa | 1487 | } |
0244be31 | 1488 | if (! REG_P (reg)) |
c6a6cdaa | 1489 | operand_reg[nop] = NULL_RTX; |
0244be31 | 1490 | else if (REGNO (reg) >= FIRST_PSEUDO_REGISTER |
1491 | || ((int) REGNO (reg) | |
1492 | == lra_get_elimination_hard_regno (REGNO (reg)))) | |
1493 | no_subreg_reg_operand[nop] = reg; | |
1494 | else | |
1495 | operand_reg[nop] = no_subreg_reg_operand[nop] | |
1496 | /* Just use natural mode for elimination result. It should | |
1497 | be enough for extra constraints hooks. */ | |
1498 | = regno_reg_rtx[hard_regno[nop]]; | |
c6a6cdaa | 1499 | } |
1500 | ||
1501 | /* The constraints are made of several alternatives. Each operand's | |
1502 | constraint looks like foo,bar,... with commas separating the | |
1503 | alternatives. The first alternatives for all operands go | |
1504 | together, the second alternatives go together, etc. | |
1505 | ||
1506 | First loop over alternatives. */ | |
1507 | for (nalt = 0; nalt < n_alternatives; nalt++) | |
1508 | { | |
1509 | /* Loop over operands for one constraint alternative. */ | |
ea99c7a1 | 1510 | #if HAVE_ATTR_enabled |
c6a6cdaa | 1511 | if (curr_id->alternative_enabled_p != NULL |
1512 | && ! curr_id->alternative_enabled_p[nalt]) | |
1513 | continue; | |
1514 | #endif | |
1515 | ||
1516 | if (only_alternative >= 0 && nalt != only_alternative) | |
1517 | continue; | |
1518 | ||
273c330a | 1519 | |
c6a6cdaa | 1520 | overall = losers = reject = reload_nregs = reload_sum = 0; |
1521 | for (nop = 0; nop < n_operands; nop++) | |
34575461 | 1522 | { |
1523 | int inc = (curr_static_id | |
1524 | ->operand_alternative[nalt * n_operands + nop].reject); | |
1525 | if (lra_dump_file != NULL && inc != 0) | |
1526 | fprintf (lra_dump_file, | |
1527 | " Staticly defined alt reject+=%d\n", inc); | |
1528 | reject += inc; | |
1529 | } | |
c6a6cdaa | 1530 | early_clobbered_regs_num = 0; |
1531 | ||
1532 | for (nop = 0; nop < n_operands; nop++) | |
1533 | { | |
1534 | const char *p; | |
1535 | char *end; | |
1536 | int len, c, m, i, opalt_num, this_alternative_matches; | |
1537 | bool win, did_match, offmemok, early_clobber_p; | |
1538 | /* false => this operand can be reloaded somehow for this | |
1539 | alternative. */ | |
1540 | bool badop; | |
1541 | /* true => this operand can be reloaded if the alternative | |
1542 | allows regs. */ | |
1543 | bool winreg; | |
1544 | /* True if a constant forced into memory would be OK for | |
1545 | this operand. */ | |
1546 | bool constmemok; | |
1547 | enum reg_class this_alternative, this_costly_alternative; | |
1548 | HARD_REG_SET this_alternative_set, this_costly_alternative_set; | |
1549 | bool this_alternative_match_win, this_alternative_win; | |
1550 | bool this_alternative_offmemok; | |
2b1732ad | 1551 | bool scratch_p; |
c6a6cdaa | 1552 | enum machine_mode mode; |
1553 | ||
1554 | opalt_num = nalt * n_operands + nop; | |
1555 | if (curr_static_id->operand_alternative[opalt_num].anything_ok) | |
1556 | { | |
1557 | /* Fast track for no constraints at all. */ | |
1558 | curr_alt[nop] = NO_REGS; | |
1559 | CLEAR_HARD_REG_SET (curr_alt_set[nop]); | |
1560 | curr_alt_win[nop] = true; | |
1561 | curr_alt_match_win[nop] = false; | |
1562 | curr_alt_offmemok[nop] = false; | |
1563 | curr_alt_matches[nop] = -1; | |
1564 | continue; | |
1565 | } | |
1a8f8886 | 1566 | |
c6a6cdaa | 1567 | op = no_subreg_reg_operand[nop]; |
1568 | mode = curr_operand_mode[nop]; | |
1569 | ||
1570 | win = did_match = winreg = offmemok = constmemok = false; | |
1571 | badop = true; | |
1a8f8886 | 1572 | |
c6a6cdaa | 1573 | early_clobber_p = false; |
1574 | p = curr_static_id->operand_alternative[opalt_num].constraint; | |
1a8f8886 | 1575 | |
c6a6cdaa | 1576 | this_costly_alternative = this_alternative = NO_REGS; |
1577 | /* We update set of possible hard regs besides its class | |
1578 | because reg class might be inaccurate. For example, | |
1579 | union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM | |
1580 | is translated in HI_REGS because classes are merged by | |
1581 | pairs and there is no accurate intermediate class. */ | |
1582 | CLEAR_HARD_REG_SET (this_alternative_set); | |
1583 | CLEAR_HARD_REG_SET (this_costly_alternative_set); | |
1584 | this_alternative_win = false; | |
1585 | this_alternative_match_win = false; | |
1586 | this_alternative_offmemok = false; | |
1587 | this_alternative_matches = -1; | |
1a8f8886 | 1588 | |
c6a6cdaa | 1589 | /* An empty constraint should be excluded by the fast |
1590 | track. */ | |
1591 | lra_assert (*p != 0 && *p != ','); | |
1a8f8886 | 1592 | |
c6a6cdaa | 1593 | /* Scan this alternative's specs for this operand; set WIN |
1594 | if the operand fits any letter in this alternative. | |
1595 | Otherwise, clear BADOP if this operand could fit some | |
1596 | letter after reloads, or set WINREG if this operand could | |
1597 | fit after reloads provided the constraint allows some | |
1598 | registers. */ | |
1599 | costly_p = false; | |
1600 | do | |
1601 | { | |
1602 | switch ((c = *p, len = CONSTRAINT_LEN (c, p)), c) | |
1603 | { | |
1604 | case '\0': | |
1605 | len = 0; | |
1606 | break; | |
1607 | case ',': | |
1608 | c = '\0'; | |
1609 | break; | |
1a8f8886 | 1610 | |
c6a6cdaa | 1611 | case '=': case '+': case '?': case '*': case '!': |
1612 | case ' ': case '\t': | |
1613 | break; | |
1a8f8886 | 1614 | |
c6a6cdaa | 1615 | case '%': |
1616 | /* We only support one commutative marker, the first | |
1617 | one. We already set commutative above. */ | |
1618 | break; | |
1a8f8886 | 1619 | |
c6a6cdaa | 1620 | case '&': |
1621 | early_clobber_p = true; | |
1622 | break; | |
1a8f8886 | 1623 | |
c6a6cdaa | 1624 | case '#': |
1625 | /* Ignore rest of this alternative. */ | |
1626 | c = '\0'; | |
1627 | break; | |
1a8f8886 | 1628 | |
c6a6cdaa | 1629 | case '0': case '1': case '2': case '3': case '4': |
1630 | case '5': case '6': case '7': case '8': case '9': | |
1631 | { | |
1632 | int m_hregno; | |
1633 | bool match_p; | |
1a8f8886 | 1634 | |
c6a6cdaa | 1635 | m = strtoul (p, &end, 10); |
1636 | p = end; | |
1637 | len = 0; | |
1638 | lra_assert (nop > m); | |
1a8f8886 | 1639 | |
c6a6cdaa | 1640 | this_alternative_matches = m; |
1641 | m_hregno = get_hard_regno (*curr_id->operand_loc[m]); | |
1642 | /* We are supposed to match a previous operand. | |
1643 | If we do, we win if that one did. If we do | |
1644 | not, count both of the operands as losers. | |
1645 | (This is too conservative, since most of the | |
1646 | time only a single reload insn will be needed | |
1647 | to make the two operands win. As a result, | |
1648 | this alternative may be rejected when it is | |
1649 | actually desirable.) */ | |
1650 | match_p = false; | |
1651 | if (operands_match_p (*curr_id->operand_loc[nop], | |
1652 | *curr_id->operand_loc[m], m_hregno)) | |
1653 | { | |
1654 | /* We should reject matching of an early | |
1655 | clobber operand if the matching operand is | |
1656 | not dying in the insn. */ | |
1657 | if (! curr_static_id->operand[m].early_clobber | |
1658 | || operand_reg[nop] == NULL_RTX | |
1659 | || (find_regno_note (curr_insn, REG_DEAD, | |
89c2edcf | 1660 | REGNO (op)) |
1661 | || REGNO (op) == REGNO (operand_reg[m]))) | |
c6a6cdaa | 1662 | match_p = true; |
1663 | } | |
1664 | if (match_p) | |
1665 | { | |
1666 | /* If we are matching a non-offsettable | |
1667 | address where an offsettable address was | |
1668 | expected, then we must reject this | |
1669 | combination, because we can't reload | |
1670 | it. */ | |
1671 | if (curr_alt_offmemok[m] | |
1672 | && MEM_P (*curr_id->operand_loc[m]) | |
1673 | && curr_alt[m] == NO_REGS && ! curr_alt_win[m]) | |
1674 | continue; | |
1a8f8886 | 1675 | |
c6a6cdaa | 1676 | } |
1677 | else | |
1678 | { | |
1679 | /* Operands don't match. Both operands must | |
1680 | allow a reload register, otherwise we | |
1681 | cannot make them match. */ | |
1682 | if (curr_alt[m] == NO_REGS) | |
1683 | break; | |
1684 | /* Retroactively mark the operand we had to | |
1685 | match as a loser, if it wasn't already and | |
1686 | it wasn't matched to a register constraint | |
1687 | (e.g it might be matched by memory). */ | |
1688 | if (curr_alt_win[m] | |
1689 | && (operand_reg[m] == NULL_RTX | |
1690 | || hard_regno[m] < 0)) | |
1691 | { | |
1692 | losers++; | |
1693 | reload_nregs | |
1694 | += (ira_reg_class_max_nregs[curr_alt[m]] | |
1695 | [GET_MODE (*curr_id->operand_loc[m])]); | |
1696 | } | |
1a8f8886 | 1697 | |
c6a6cdaa | 1698 | /* We prefer no matching alternatives because |
1699 | it gives more freedom in RA. */ | |
1700 | if (operand_reg[nop] == NULL_RTX | |
1701 | || (find_regno_note (curr_insn, REG_DEAD, | |
1702 | REGNO (operand_reg[nop])) | |
1703 | == NULL_RTX)) | |
34575461 | 1704 | { |
1705 | if (lra_dump_file != NULL) | |
1706 | fprintf | |
1707 | (lra_dump_file, | |
1708 | " %d Matching alt: reject+=2\n", | |
1709 | nop); | |
1710 | reject += 2; | |
1711 | } | |
c6a6cdaa | 1712 | } |
1713 | /* If we have to reload this operand and some | |
1714 | previous operand also had to match the same | |
1715 | thing as this operand, we don't know how to do | |
1716 | that. */ | |
1717 | if (!match_p || !curr_alt_win[m]) | |
1718 | { | |
1719 | for (i = 0; i < nop; i++) | |
1720 | if (curr_alt_matches[i] == m) | |
1721 | break; | |
1722 | if (i < nop) | |
1723 | break; | |
1724 | } | |
1725 | else | |
1726 | did_match = true; | |
1a8f8886 | 1727 | |
c6a6cdaa | 1728 | /* This can be fixed with reloads if the operand |
1729 | we are supposed to match can be fixed with | |
1730 | reloads. */ | |
1731 | badop = false; | |
1732 | this_alternative = curr_alt[m]; | |
1733 | COPY_HARD_REG_SET (this_alternative_set, curr_alt_set[m]); | |
4b3aba76 | 1734 | winreg = this_alternative != NO_REGS; |
c6a6cdaa | 1735 | break; |
1736 | } | |
1a8f8886 | 1737 | |
c6a6cdaa | 1738 | case 'p': |
1739 | cl = base_reg_class (VOIDmode, ADDR_SPACE_GENERIC, | |
1740 | ADDRESS, SCRATCH); | |
1741 | this_alternative = reg_class_subunion[this_alternative][cl]; | |
1742 | IOR_HARD_REG_SET (this_alternative_set, | |
1743 | reg_class_contents[cl]); | |
1744 | if (costly_p) | |
1745 | { | |
1746 | this_costly_alternative | |
1747 | = reg_class_subunion[this_costly_alternative][cl]; | |
1748 | IOR_HARD_REG_SET (this_costly_alternative_set, | |
1749 | reg_class_contents[cl]); | |
1750 | } | |
1751 | win = true; | |
1752 | badop = false; | |
1753 | break; | |
1a8f8886 | 1754 | |
c6a6cdaa | 1755 | case TARGET_MEM_CONSTRAINT: |
1756 | if (MEM_P (op) || spilled_pseudo_p (op)) | |
1757 | win = true; | |
70892847 | 1758 | /* We can put constant or pseudo value into memory |
1759 | to satisfy the constraint. */ | |
1760 | if (CONST_POOL_OK_P (mode, op) || REG_P (op)) | |
c6a6cdaa | 1761 | badop = false; |
1762 | constmemok = true; | |
1763 | break; | |
1a8f8886 | 1764 | |
c6a6cdaa | 1765 | case '<': |
1766 | if (MEM_P (op) | |
1767 | && (GET_CODE (XEXP (op, 0)) == PRE_DEC | |
1768 | || GET_CODE (XEXP (op, 0)) == POST_DEC)) | |
1769 | win = true; | |
1770 | break; | |
1a8f8886 | 1771 | |
c6a6cdaa | 1772 | case '>': |
1773 | if (MEM_P (op) | |
1774 | && (GET_CODE (XEXP (op, 0)) == PRE_INC | |
1775 | || GET_CODE (XEXP (op, 0)) == POST_INC)) | |
1776 | win = true; | |
1777 | break; | |
1a8f8886 | 1778 | |
c6a6cdaa | 1779 | /* Memory op whose address is not offsettable. */ |
1780 | case 'V': | |
1781 | if (MEM_P (op) | |
1782 | && ! offsettable_nonstrict_memref_p (op)) | |
1783 | win = true; | |
1784 | break; | |
1a8f8886 | 1785 | |
c6a6cdaa | 1786 | /* Memory operand whose address is offsettable. */ |
1787 | case 'o': | |
1788 | if ((MEM_P (op) | |
1789 | && offsettable_nonstrict_memref_p (op)) | |
1790 | || spilled_pseudo_p (op)) | |
1791 | win = true; | |
70892847 | 1792 | /* We can put constant or pseudo value into memory |
1793 | or make memory address offsetable to satisfy the | |
1794 | constraint. */ | |
1795 | if (CONST_POOL_OK_P (mode, op) || MEM_P (op) || REG_P (op)) | |
c6a6cdaa | 1796 | badop = false; |
1797 | constmemok = true; | |
1798 | offmemok = true; | |
1799 | break; | |
1a8f8886 | 1800 | |
c6a6cdaa | 1801 | case 'E': |
1802 | case 'F': | |
1803 | if (GET_CODE (op) == CONST_DOUBLE | |
1804 | || (GET_CODE (op) == CONST_VECTOR | |
1805 | && (GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT))) | |
1806 | win = true; | |
1807 | break; | |
1a8f8886 | 1808 | |
c6a6cdaa | 1809 | case 'G': |
1810 | case 'H': | |
c625778b | 1811 | if (CONST_DOUBLE_AS_FLOAT_P (op) |
c6a6cdaa | 1812 | && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, c, p)) |
1813 | win = true; | |
1814 | break; | |
1a8f8886 | 1815 | |
c6a6cdaa | 1816 | case 's': |
c625778b | 1817 | if (CONST_SCALAR_INT_P (op)) |
c6a6cdaa | 1818 | break; |
70892847 | 1819 | |
c6a6cdaa | 1820 | case 'i': |
1821 | if (general_constant_p (op)) | |
1822 | win = true; | |
1823 | break; | |
1a8f8886 | 1824 | |
c6a6cdaa | 1825 | case 'n': |
c625778b | 1826 | if (CONST_SCALAR_INT_P (op)) |
c6a6cdaa | 1827 | win = true; |
1828 | break; | |
1a8f8886 | 1829 | |
c6a6cdaa | 1830 | case 'I': |
1831 | case 'J': | |
1832 | case 'K': | |
1833 | case 'L': | |
1834 | case 'M': | |
1835 | case 'N': | |
1836 | case 'O': | |
1837 | case 'P': | |
1838 | if (CONST_INT_P (op) | |
1839 | && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), c, p)) | |
1840 | win = true; | |
1841 | break; | |
1a8f8886 | 1842 | |
c6a6cdaa | 1843 | case 'X': |
1844 | /* This constraint should be excluded by the fast | |
1845 | track. */ | |
1846 | gcc_unreachable (); | |
1847 | break; | |
1a8f8886 | 1848 | |
c6a6cdaa | 1849 | case 'g': |
1850 | if (MEM_P (op) | |
1851 | || general_constant_p (op) | |
1852 | || spilled_pseudo_p (op)) | |
1853 | win = true; | |
1854 | /* Drop through into 'r' case. */ | |
1a8f8886 | 1855 | |
c6a6cdaa | 1856 | case 'r': |
1857 | this_alternative | |
1858 | = reg_class_subunion[this_alternative][GENERAL_REGS]; | |
1859 | IOR_HARD_REG_SET (this_alternative_set, | |
1860 | reg_class_contents[GENERAL_REGS]); | |
1861 | if (costly_p) | |
1862 | { | |
1863 | this_costly_alternative | |
1864 | = (reg_class_subunion | |
1865 | [this_costly_alternative][GENERAL_REGS]); | |
1866 | IOR_HARD_REG_SET (this_costly_alternative_set, | |
1867 | reg_class_contents[GENERAL_REGS]); | |
1868 | } | |
1869 | goto reg; | |
1a8f8886 | 1870 | |
c6a6cdaa | 1871 | default: |
1872 | if (REG_CLASS_FROM_CONSTRAINT (c, p) == NO_REGS) | |
1873 | { | |
1874 | #ifdef EXTRA_CONSTRAINT_STR | |
1875 | if (EXTRA_MEMORY_CONSTRAINT (c, p)) | |
1876 | { | |
1877 | if (EXTRA_CONSTRAINT_STR (op, c, p)) | |
1878 | win = true; | |
1879 | else if (spilled_pseudo_p (op)) | |
1880 | win = true; | |
1a8f8886 | 1881 | |
c6a6cdaa | 1882 | /* If we didn't already win, we can reload |
70892847 | 1883 | constants via force_const_mem or put the |
1884 | pseudo value into memory, or make other | |
1885 | memory by reloading the address like for | |
c6a6cdaa | 1886 | 'o'. */ |
70892847 | 1887 | if (CONST_POOL_OK_P (mode, op) |
1888 | || MEM_P (op) || REG_P (op)) | |
c6a6cdaa | 1889 | badop = false; |
1890 | constmemok = true; | |
1891 | offmemok = true; | |
1892 | break; | |
1893 | } | |
1894 | if (EXTRA_ADDRESS_CONSTRAINT (c, p)) | |
1895 | { | |
1896 | if (EXTRA_CONSTRAINT_STR (op, c, p)) | |
1897 | win = true; | |
1a8f8886 | 1898 | |
c6a6cdaa | 1899 | /* If we didn't already win, we can reload |
1900 | the address into a base register. */ | |
1901 | cl = base_reg_class (VOIDmode, ADDR_SPACE_GENERIC, | |
1902 | ADDRESS, SCRATCH); | |
1903 | this_alternative | |
1904 | = reg_class_subunion[this_alternative][cl]; | |
1905 | IOR_HARD_REG_SET (this_alternative_set, | |
1906 | reg_class_contents[cl]); | |
1907 | if (costly_p) | |
1908 | { | |
1909 | this_costly_alternative | |
1910 | = (reg_class_subunion | |
1911 | [this_costly_alternative][cl]); | |
1912 | IOR_HARD_REG_SET (this_costly_alternative_set, | |
1913 | reg_class_contents[cl]); | |
1914 | } | |
1915 | badop = false; | |
1916 | break; | |
1917 | } | |
1a8f8886 | 1918 | |
c6a6cdaa | 1919 | if (EXTRA_CONSTRAINT_STR (op, c, p)) |
1920 | win = true; | |
1921 | #endif | |
1922 | break; | |
1923 | } | |
1a8f8886 | 1924 | |
c6a6cdaa | 1925 | cl = REG_CLASS_FROM_CONSTRAINT (c, p); |
1926 | this_alternative = reg_class_subunion[this_alternative][cl]; | |
1927 | IOR_HARD_REG_SET (this_alternative_set, | |
1928 | reg_class_contents[cl]); | |
1929 | if (costly_p) | |
1930 | { | |
1931 | this_costly_alternative | |
1932 | = reg_class_subunion[this_costly_alternative][cl]; | |
1933 | IOR_HARD_REG_SET (this_costly_alternative_set, | |
1934 | reg_class_contents[cl]); | |
1935 | } | |
1936 | reg: | |
1937 | if (mode == BLKmode) | |
1938 | break; | |
1939 | winreg = true; | |
1940 | if (REG_P (op)) | |
1941 | { | |
1942 | if (hard_regno[nop] >= 0 | |
1943 | && in_hard_reg_set_p (this_alternative_set, | |
1944 | mode, hard_regno[nop])) | |
1945 | win = true; | |
1946 | else if (hard_regno[nop] < 0 | |
1947 | && in_class_p (op, this_alternative, NULL)) | |
1948 | win = true; | |
1949 | } | |
1950 | break; | |
1951 | } | |
1952 | if (c != ' ' && c != '\t') | |
1953 | costly_p = c == '*'; | |
1954 | } | |
1955 | while ((p += len), c); | |
1a8f8886 | 1956 | |
2b1732ad | 1957 | scratch_p = (operand_reg[nop] != NULL_RTX |
1958 | && lra_former_scratch_p (REGNO (operand_reg[nop]))); | |
c6a6cdaa | 1959 | /* Record which operands fit this alternative. */ |
1960 | if (win) | |
1961 | { | |
1962 | this_alternative_win = true; | |
1963 | if (operand_reg[nop] != NULL_RTX) | |
1964 | { | |
1965 | if (hard_regno[nop] >= 0) | |
1966 | { | |
1967 | if (in_hard_reg_set_p (this_costly_alternative_set, | |
1968 | mode, hard_regno[nop])) | |
34575461 | 1969 | { |
1970 | if (lra_dump_file != NULL) | |
1971 | fprintf (lra_dump_file, | |
1972 | " %d Costly set: reject++\n", | |
1973 | nop); | |
1974 | reject++; | |
1975 | } | |
c6a6cdaa | 1976 | } |
1977 | else | |
1978 | { | |
2b1732ad | 1979 | /* Prefer won reg to spilled pseudo under other |
1980 | equal conditions for possibe inheritance. */ | |
1981 | if (! scratch_p) | |
1982 | { | |
1983 | if (lra_dump_file != NULL) | |
1984 | fprintf | |
1985 | (lra_dump_file, | |
1986 | " %d Non pseudo reload: reject++\n", | |
1987 | nop); | |
1988 | reject++; | |
1989 | } | |
c6a6cdaa | 1990 | if (in_class_p (operand_reg[nop], |
1991 | this_costly_alternative, NULL)) | |
34575461 | 1992 | { |
1993 | if (lra_dump_file != NULL) | |
1994 | fprintf | |
1995 | (lra_dump_file, | |
1996 | " %d Non pseudo costly reload:" | |
1997 | " reject++\n", | |
1998 | nop); | |
1999 | reject++; | |
2000 | } | |
c6a6cdaa | 2001 | } |
2002 | /* We simulate the behaviour of old reload here. | |
2003 | Although scratches need hard registers and it | |
2004 | might result in spilling other pseudos, no reload | |
2005 | insns are generated for the scratches. So it | |
2006 | might cost something but probably less than old | |
2007 | reload pass believes. */ | |
2b1732ad | 2008 | if (scratch_p) |
34575461 | 2009 | { |
2010 | if (lra_dump_file != NULL) | |
2011 | fprintf (lra_dump_file, | |
2b1732ad | 2012 | " %d Scratch win: reject+=2\n", |
34575461 | 2013 | nop); |
2b1732ad | 2014 | reject += 2; |
34575461 | 2015 | } |
c6a6cdaa | 2016 | } |
2017 | } | |
2018 | else if (did_match) | |
2019 | this_alternative_match_win = true; | |
2020 | else | |
2021 | { | |
2022 | int const_to_mem = 0; | |
2023 | bool no_regs_p; | |
2024 | ||
3b3a5e5f | 2025 | /* Never do output reload of stack pointer. It makes |
2026 | impossible to do elimination when SP is changed in | |
2027 | RTL. */ | |
2028 | if (op == stack_pointer_rtx && ! frame_pointer_needed | |
2029 | && curr_static_id->operand[nop].type != OP_IN) | |
2030 | goto fail; | |
2031 | ||
aa46b107 | 2032 | /* If this alternative asks for a specific reg class, see if there |
2033 | is at least one allocatable register in that class. */ | |
c6a6cdaa | 2034 | no_regs_p |
2035 | = (this_alternative == NO_REGS | |
2036 | || (hard_reg_set_subset_p | |
2037 | (reg_class_contents[this_alternative], | |
2038 | lra_no_alloc_regs))); | |
aa46b107 | 2039 | |
2040 | /* For asms, verify that the class for this alternative is possible | |
2041 | for the mode that is specified. */ | |
1524bcdc | 2042 | if (!no_regs_p && INSN_CODE (curr_insn) < 0) |
aa46b107 | 2043 | { |
2044 | int i; | |
2045 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
2046 | if (HARD_REGNO_MODE_OK (i, mode) | |
2047 | && in_hard_reg_set_p (reg_class_contents[this_alternative], mode, i)) | |
2048 | break; | |
2049 | if (i == FIRST_PSEUDO_REGISTER) | |
2050 | winreg = false; | |
2051 | } | |
2052 | ||
c6a6cdaa | 2053 | /* If this operand accepts a register, and if the |
2054 | register class has at least one allocatable register, | |
2055 | then this operand can be reloaded. */ | |
2056 | if (winreg && !no_regs_p) | |
2057 | badop = false; | |
1a8f8886 | 2058 | |
c6a6cdaa | 2059 | if (badop) |
2060 | goto fail; | |
2061 | ||
2062 | this_alternative_offmemok = offmemok; | |
2063 | if (this_costly_alternative != NO_REGS) | |
34575461 | 2064 | { |
2065 | if (lra_dump_file != NULL) | |
2066 | fprintf (lra_dump_file, | |
2067 | " %d Costly loser: reject++\n", nop); | |
2068 | reject++; | |
2069 | } | |
c6a6cdaa | 2070 | /* If the operand is dying, has a matching constraint, |
2071 | and satisfies constraints of the matched operand | |
2072 | which failed to satisfy the own constraints, we do | |
2073 | not need to generate a reload insn for this | |
2074 | operand. */ | |
2075 | if (!(this_alternative_matches >= 0 | |
2076 | && !curr_alt_win[this_alternative_matches] | |
2077 | && REG_P (op) | |
2078 | && find_regno_note (curr_insn, REG_DEAD, REGNO (op)) | |
2079 | && (hard_regno[nop] >= 0 | |
2080 | ? in_hard_reg_set_p (this_alternative_set, | |
2081 | mode, hard_regno[nop]) | |
2082 | : in_class_p (op, this_alternative, NULL)))) | |
2e620dc7 | 2083 | { |
92dfb77d | 2084 | /* Strict_low_part requires to reload the register |
2085 | not the sub-register. In this case we should | |
2086 | check that a final reload hard reg can hold the | |
2087 | value mode. */ | |
2e620dc7 | 2088 | if (curr_static_id->operand[nop].strict_low |
2089 | && REG_P (op) | |
2090 | && hard_regno[nop] < 0 | |
2091 | && GET_CODE (*curr_id->operand_loc[nop]) == SUBREG | |
2092 | && ira_class_hard_regs_num[this_alternative] > 0 | |
2093 | && ! HARD_REGNO_MODE_OK (ira_class_hard_regs | |
2094 | [this_alternative][0], | |
8177deec | 2095 | GET_MODE |
2096 | (*curr_id->operand_loc[nop]))) | |
2e620dc7 | 2097 | goto fail; |
2098 | losers++; | |
2099 | } | |
c6a6cdaa | 2100 | if (operand_reg[nop] != NULL_RTX |
2101 | /* Output operands and matched input operands are | |
2102 | not inherited. The following conditions do not | |
2103 | exactly describe the previous statement but they | |
2104 | are pretty close. */ | |
2105 | && curr_static_id->operand[nop].type != OP_OUT | |
2106 | && (this_alternative_matches < 0 | |
2107 | || curr_static_id->operand[nop].type != OP_IN)) | |
2108 | { | |
2109 | int last_reload = (lra_reg_info[ORIGINAL_REGNO | |
2110 | (operand_reg[nop])] | |
2111 | .last_reload); | |
2112 | ||
2113 | if (last_reload > bb_reload_num) | |
2114 | reload_sum += last_reload - bb_reload_num; | |
2115 | } | |
2116 | /* If this is a constant that is reloaded into the | |
2117 | desired class by copying it to memory first, count | |
2118 | that as another reload. This is consistent with | |
2119 | other code and is required to avoid choosing another | |
2120 | alternative when the constant is moved into memory. | |
2121 | Note that the test here is precisely the same as in | |
2122 | the code below that calls force_const_mem. */ | |
2123 | if (CONST_POOL_OK_P (mode, op) | |
2124 | && ((targetm.preferred_reload_class | |
2125 | (op, this_alternative) == NO_REGS) | |
2126 | || no_input_reloads_p)) | |
2127 | { | |
2128 | const_to_mem = 1; | |
2129 | if (! no_regs_p) | |
2130 | losers++; | |
2131 | } | |
1a8f8886 | 2132 | |
c6a6cdaa | 2133 | /* Alternative loses if it requires a type of reload not |
2134 | permitted for this insn. We can always reload | |
2135 | objects with a REG_UNUSED note. */ | |
2136 | if ((curr_static_id->operand[nop].type != OP_IN | |
2137 | && no_output_reloads_p | |
2138 | && ! find_reg_note (curr_insn, REG_UNUSED, op)) | |
2139 | || (curr_static_id->operand[nop].type != OP_OUT | |
2140 | && no_input_reloads_p && ! const_to_mem)) | |
2141 | goto fail; | |
1a8f8886 | 2142 | |
4b3aba76 | 2143 | /* Check strong discouragement of reload of non-constant |
2144 | into class THIS_ALTERNATIVE. */ | |
2145 | if (! CONSTANT_P (op) && ! no_regs_p | |
2146 | && (targetm.preferred_reload_class | |
2147 | (op, this_alternative) == NO_REGS | |
2148 | || (curr_static_id->operand[nop].type == OP_OUT | |
2149 | && (targetm.preferred_output_reload_class | |
2150 | (op, this_alternative) == NO_REGS)))) | |
34575461 | 2151 | { |
2152 | if (lra_dump_file != NULL) | |
2153 | fprintf (lra_dump_file, | |
2154 | " %d Non-prefered reload: reject+=%d\n", | |
2155 | nop, LRA_MAX_REJECT); | |
2156 | reject += LRA_MAX_REJECT; | |
2157 | } | |
1a8f8886 | 2158 | |
0178c26e | 2159 | if (! (MEM_P (op) && offmemok) |
2160 | && ! (const_to_mem && constmemok)) | |
c6a6cdaa | 2161 | { |
2162 | /* We prefer to reload pseudos over reloading other | |
2163 | things, since such reloads may be able to be | |
2164 | eliminated later. So bump REJECT in other cases. | |
2165 | Don't do this in the case where we are forcing a | |
2166 | constant into memory and it will then win since | |
2167 | we don't want to have a different alternative | |
2168 | match then. */ | |
2169 | if (! (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER)) | |
34575461 | 2170 | { |
2171 | if (lra_dump_file != NULL) | |
2172 | fprintf | |
2173 | (lra_dump_file, | |
2174 | " %d Non-pseudo reload: reject+=2\n", | |
2175 | nop); | |
2176 | reject += 2; | |
2177 | } | |
1a8f8886 | 2178 | |
c6a6cdaa | 2179 | if (! no_regs_p) |
2180 | reload_nregs | |
2181 | += ira_reg_class_max_nregs[this_alternative][mode]; | |
273c330a | 2182 | |
2183 | if (SMALL_REGISTER_CLASS_P (this_alternative)) | |
34575461 | 2184 | { |
2185 | if (lra_dump_file != NULL) | |
2186 | fprintf | |
2187 | (lra_dump_file, | |
2188 | " %d Small class reload: reject+=%d\n", | |
2189 | nop, LRA_LOSER_COST_FACTOR / 2); | |
2190 | reject += LRA_LOSER_COST_FACTOR / 2; | |
2191 | } | |
c6a6cdaa | 2192 | } |
2193 | ||
70892847 | 2194 | /* We are trying to spill pseudo into memory. It is |
2195 | usually more costly than moving to a hard register | |
2196 | although it might takes the same number of | |
2197 | reloads. */ | |
34575461 | 2198 | if (no_regs_p && REG_P (op) && hard_regno[nop] >= 0) |
2199 | { | |
2200 | if (lra_dump_file != NULL) | |
2201 | fprintf | |
2202 | (lra_dump_file, | |
2203 | " %d Spill pseudo in memory: reject+=3\n", | |
2204 | nop); | |
2205 | reject += 3; | |
2206 | } | |
70892847 | 2207 | |
2590979b | 2208 | #ifdef SECONDARY_MEMORY_NEEDED |
2209 | /* If reload requires moving value through secondary | |
2210 | memory, it will need one more insn at least. */ | |
2211 | if (this_alternative != NO_REGS | |
2212 | && REG_P (op) && (cl = get_reg_class (REGNO (op))) != NO_REGS | |
2213 | && ((curr_static_id->operand[nop].type != OP_OUT | |
2214 | && SECONDARY_MEMORY_NEEDED (cl, this_alternative, | |
2215 | GET_MODE (op))) | |
2216 | || (curr_static_id->operand[nop].type != OP_IN | |
2217 | && SECONDARY_MEMORY_NEEDED (this_alternative, cl, | |
2218 | GET_MODE (op))))) | |
2219 | losers++; | |
2220 | #endif | |
c6a6cdaa | 2221 | /* Input reloads can be inherited more often than output |
2222 | reloads can be removed, so penalize output | |
2223 | reloads. */ | |
2224 | if (!REG_P (op) || curr_static_id->operand[nop].type != OP_IN) | |
34575461 | 2225 | { |
2226 | if (lra_dump_file != NULL) | |
2227 | fprintf | |
2228 | (lra_dump_file, | |
2229 | " %d Non input pseudo reload: reject++\n", | |
2230 | nop); | |
2231 | reject++; | |
2232 | } | |
c6a6cdaa | 2233 | } |
1a8f8886 | 2234 | |
2b1732ad | 2235 | if (early_clobber_p && ! scratch_p) |
34575461 | 2236 | { |
2237 | if (lra_dump_file != NULL) | |
2238 | fprintf (lra_dump_file, | |
2239 | " %d Early clobber: reject++\n", nop); | |
2240 | reject++; | |
2241 | } | |
c6a6cdaa | 2242 | /* ??? We check early clobbers after processing all operands |
2243 | (see loop below) and there we update the costs more. | |
2244 | Should we update the cost (may be approximately) here | |
2245 | because of early clobber register reloads or it is a rare | |
2246 | or non-important thing to be worth to do it. */ | |
4b3aba76 | 2247 | overall = losers * LRA_LOSER_COST_FACTOR + reject; |
c6a6cdaa | 2248 | if ((best_losers == 0 || losers != 0) && best_overall < overall) |
f7c98bb1 | 2249 | { |
2250 | if (lra_dump_file != NULL) | |
2251 | fprintf (lra_dump_file, | |
34575461 | 2252 | " alt=%d,overall=%d,losers=%d -- refuse\n", |
f7c98bb1 | 2253 | nalt, overall, losers); |
2254 | goto fail; | |
2255 | } | |
c6a6cdaa | 2256 | |
2257 | curr_alt[nop] = this_alternative; | |
2258 | COPY_HARD_REG_SET (curr_alt_set[nop], this_alternative_set); | |
2259 | curr_alt_win[nop] = this_alternative_win; | |
2260 | curr_alt_match_win[nop] = this_alternative_match_win; | |
2261 | curr_alt_offmemok[nop] = this_alternative_offmemok; | |
2262 | curr_alt_matches[nop] = this_alternative_matches; | |
1a8f8886 | 2263 | |
c6a6cdaa | 2264 | if (this_alternative_matches >= 0 |
2265 | && !did_match && !this_alternative_win) | |
2266 | curr_alt_win[this_alternative_matches] = false; | |
1a8f8886 | 2267 | |
c6a6cdaa | 2268 | if (early_clobber_p && operand_reg[nop] != NULL_RTX) |
2269 | early_clobbered_nops[early_clobbered_regs_num++] = nop; | |
2270 | } | |
ea99c7a1 | 2271 | if (curr_insn_set != NULL_RTX && n_operands == 2 |
2272 | /* Prevent processing non-move insns. */ | |
2273 | && (GET_CODE (SET_SRC (curr_insn_set)) == SUBREG | |
2274 | || SET_SRC (curr_insn_set) == no_subreg_reg_operand[1]) | |
2275 | && ((! curr_alt_win[0] && ! curr_alt_win[1] | |
2276 | && REG_P (no_subreg_reg_operand[0]) | |
2277 | && REG_P (no_subreg_reg_operand[1]) | |
2278 | && (reg_in_class_p (no_subreg_reg_operand[0], curr_alt[1]) | |
2279 | || reg_in_class_p (no_subreg_reg_operand[1], curr_alt[0]))) | |
2280 | || (! curr_alt_win[0] && curr_alt_win[1] | |
2281 | && REG_P (no_subreg_reg_operand[1]) | |
2282 | && reg_in_class_p (no_subreg_reg_operand[1], curr_alt[0])) | |
2283 | || (curr_alt_win[0] && ! curr_alt_win[1] | |
2284 | && REG_P (no_subreg_reg_operand[0]) | |
2285 | && reg_in_class_p (no_subreg_reg_operand[0], curr_alt[1]) | |
2286 | && (! CONST_POOL_OK_P (curr_operand_mode[1], | |
2287 | no_subreg_reg_operand[1]) | |
2288 | || (targetm.preferred_reload_class | |
2289 | (no_subreg_reg_operand[1], | |
2290 | (enum reg_class) curr_alt[1]) != NO_REGS)) | |
2291 | /* If it is a result of recent elimination in move | |
2292 | insn we can transform it into an add still by | |
2293 | using this alternative. */ | |
2294 | && GET_CODE (no_subreg_reg_operand[1]) != PLUS))) | |
34575461 | 2295 | { |
2296 | /* We have a move insn and a new reload insn will be similar | |
2297 | to the current insn. We should avoid such situation as it | |
2298 | results in LRA cycling. */ | |
2299 | overall += LRA_MAX_REJECT; | |
2300 | } | |
c6a6cdaa | 2301 | ok_p = true; |
2302 | curr_alt_dont_inherit_ops_num = 0; | |
2303 | for (nop = 0; nop < early_clobbered_regs_num; nop++) | |
2304 | { | |
8c3a9b39 | 2305 | int i, j, clobbered_hard_regno, first_conflict_j, last_conflict_j; |
c6a6cdaa | 2306 | HARD_REG_SET temp_set; |
2307 | ||
2308 | i = early_clobbered_nops[nop]; | |
2309 | if ((! curr_alt_win[i] && ! curr_alt_match_win[i]) | |
2310 | || hard_regno[i] < 0) | |
2311 | continue; | |
89c2edcf | 2312 | lra_assert (operand_reg[i] != NULL_RTX); |
c6a6cdaa | 2313 | clobbered_hard_regno = hard_regno[i]; |
2314 | CLEAR_HARD_REG_SET (temp_set); | |
2315 | add_to_hard_reg_set (&temp_set, biggest_mode[i], clobbered_hard_regno); | |
8c3a9b39 | 2316 | first_conflict_j = last_conflict_j = -1; |
c6a6cdaa | 2317 | for (j = 0; j < n_operands; j++) |
2318 | if (j == i | |
2319 | /* We don't want process insides of match_operator and | |
2320 | match_parallel because otherwise we would process | |
2321 | their operands once again generating a wrong | |
2322 | code. */ | |
2323 | || curr_static_id->operand[j].is_operator) | |
2324 | continue; | |
2325 | else if ((curr_alt_matches[j] == i && curr_alt_match_win[j]) | |
2326 | || (curr_alt_matches[i] == j && curr_alt_match_win[i])) | |
2327 | continue; | |
89c2edcf | 2328 | /* If we don't reload j-th operand, check conflicts. */ |
2329 | else if ((curr_alt_win[j] || curr_alt_match_win[j]) | |
2330 | && uses_hard_regs_p (*curr_id->operand_loc[j], temp_set)) | |
8c3a9b39 | 2331 | { |
2332 | if (first_conflict_j < 0) | |
2333 | first_conflict_j = j; | |
2334 | last_conflict_j = j; | |
2335 | } | |
2336 | if (last_conflict_j < 0) | |
c6a6cdaa | 2337 | continue; |
89c2edcf | 2338 | /* If earlyclobber operand conflicts with another |
2339 | non-matching operand which is actually the same register | |
2340 | as the earlyclobber operand, it is better to reload the | |
2341 | another operand as an operand matching the earlyclobber | |
2342 | operand can be also the same. */ | |
8c3a9b39 | 2343 | if (first_conflict_j == last_conflict_j |
2344 | && operand_reg[last_conflict_j] | |
2345 | != NULL_RTX && ! curr_alt_match_win[last_conflict_j] | |
2346 | && REGNO (operand_reg[i]) == REGNO (operand_reg[last_conflict_j])) | |
89c2edcf | 2347 | { |
8c3a9b39 | 2348 | curr_alt_win[last_conflict_j] = false; |
2349 | curr_alt_dont_inherit_ops[curr_alt_dont_inherit_ops_num++] | |
2350 | = last_conflict_j; | |
89c2edcf | 2351 | losers++; |
f7c98bb1 | 2352 | /* Early clobber was already reflected in REJECT. */ |
2353 | lra_assert (reject > 0); | |
34575461 | 2354 | if (lra_dump_file != NULL) |
2355 | fprintf | |
2356 | (lra_dump_file, | |
2357 | " %d Conflict early clobber reload: reject--\n", | |
2358 | i); | |
f7c98bb1 | 2359 | reject--; |
2360 | overall += LRA_LOSER_COST_FACTOR - 1; | |
89c2edcf | 2361 | } |
c6a6cdaa | 2362 | else |
2363 | { | |
89c2edcf | 2364 | /* We need to reload early clobbered register and the |
2365 | matched registers. */ | |
2366 | for (j = 0; j < n_operands; j++) | |
2367 | if (curr_alt_matches[j] == i) | |
2368 | { | |
2369 | curr_alt_match_win[j] = false; | |
2370 | losers++; | |
2371 | overall += LRA_LOSER_COST_FACTOR; | |
2372 | } | |
2373 | if (! curr_alt_match_win[i]) | |
2374 | curr_alt_dont_inherit_ops[curr_alt_dont_inherit_ops_num++] = i; | |
2375 | else | |
2376 | { | |
2377 | /* Remember pseudos used for match reloads are never | |
2378 | inherited. */ | |
2379 | lra_assert (curr_alt_matches[i] >= 0); | |
2380 | curr_alt_win[curr_alt_matches[i]] = false; | |
2381 | } | |
2382 | curr_alt_win[i] = curr_alt_match_win[i] = false; | |
2383 | losers++; | |
f7c98bb1 | 2384 | /* Early clobber was already reflected in REJECT. */ |
2385 | lra_assert (reject > 0); | |
34575461 | 2386 | if (lra_dump_file != NULL) |
2387 | fprintf | |
2388 | (lra_dump_file, | |
2389 | " %d Matched conflict early clobber reloads:" | |
2390 | "reject--\n", | |
2391 | i); | |
f7c98bb1 | 2392 | reject--; |
2393 | overall += LRA_LOSER_COST_FACTOR - 1; | |
c6a6cdaa | 2394 | } |
c6a6cdaa | 2395 | } |
f7c98bb1 | 2396 | if (lra_dump_file != NULL) |
273c330a | 2397 | fprintf (lra_dump_file, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n", |
2398 | nalt, overall, losers, reload_nregs); | |
f7c98bb1 | 2399 | |
c6a6cdaa | 2400 | /* If this alternative can be made to work by reloading, and it |
2401 | needs less reloading than the others checked so far, record | |
2402 | it as the chosen goal for reloading. */ | |
2403 | if ((best_losers != 0 && losers == 0) | |
2404 | || (((best_losers == 0 && losers == 0) | |
2405 | || (best_losers != 0 && losers != 0)) | |
2406 | && (best_overall > overall | |
2407 | || (best_overall == overall | |
2408 | /* If the cost of the reloads is the same, | |
2409 | prefer alternative which requires minimal | |
273c330a | 2410 | number of reload regs. */ |
2411 | && (reload_nregs < best_reload_nregs | |
2412 | || (reload_nregs == best_reload_nregs | |
04dda2a2 | 2413 | && (best_reload_sum < reload_sum |
2414 | || (best_reload_sum == reload_sum | |
2415 | && nalt < goal_alt_number)))))))) | |
c6a6cdaa | 2416 | { |
2417 | for (nop = 0; nop < n_operands; nop++) | |
2418 | { | |
2419 | goal_alt_win[nop] = curr_alt_win[nop]; | |
2420 | goal_alt_match_win[nop] = curr_alt_match_win[nop]; | |
2421 | goal_alt_matches[nop] = curr_alt_matches[nop]; | |
2422 | goal_alt[nop] = curr_alt[nop]; | |
2423 | goal_alt_offmemok[nop] = curr_alt_offmemok[nop]; | |
2424 | } | |
2425 | goal_alt_dont_inherit_ops_num = curr_alt_dont_inherit_ops_num; | |
2426 | for (nop = 0; nop < curr_alt_dont_inherit_ops_num; nop++) | |
2427 | goal_alt_dont_inherit_ops[nop] = curr_alt_dont_inherit_ops[nop]; | |
2428 | goal_alt_swapped = curr_swapped; | |
2429 | best_overall = overall; | |
2430 | best_losers = losers; | |
c6a6cdaa | 2431 | best_reload_nregs = reload_nregs; |
2432 | best_reload_sum = reload_sum; | |
2433 | goal_alt_number = nalt; | |
2434 | } | |
2435 | if (losers == 0) | |
2436 | /* Everything is satisfied. Do not process alternatives | |
1a8f8886 | 2437 | anymore. */ |
c6a6cdaa | 2438 | break; |
2439 | fail: | |
2440 | ; | |
2441 | } | |
2442 | return ok_p; | |
2443 | } | |
2444 | ||
2445 | /* Return 1 if ADDR is a valid memory address for mode MODE in address | |
2446 | space AS, and check that each pseudo has the proper kind of hard | |
2447 | reg. */ | |
2448 | static int | |
2449 | valid_address_p (enum machine_mode mode ATTRIBUTE_UNUSED, | |
2450 | rtx addr, addr_space_t as) | |
2451 | { | |
2452 | #ifdef GO_IF_LEGITIMATE_ADDRESS | |
2453 | lra_assert (ADDR_SPACE_GENERIC_P (as)); | |
2454 | GO_IF_LEGITIMATE_ADDRESS (mode, addr, win); | |
2455 | return 0; | |
1a8f8886 | 2456 | |
c6a6cdaa | 2457 | win: |
2458 | return 1; | |
2459 | #else | |
2460 | return targetm.addr_space.legitimate_address_p (mode, addr, 0, as); | |
2461 | #endif | |
2462 | } | |
2463 | ||
1efe9e9d | 2464 | /* Return whether address AD is valid. */ |
cbdc5144 | 2465 | |
2466 | static bool | |
1efe9e9d | 2467 | valid_address_p (struct address_info *ad) |
cbdc5144 | 2468 | { |
2469 | /* Some ports do not check displacements for eliminable registers, | |
2470 | so we replace them temporarily with the elimination target. */ | |
2471 | rtx saved_base_reg = NULL_RTX; | |
2472 | rtx saved_index_reg = NULL_RTX; | |
1efe9e9d | 2473 | rtx *base_term = strip_subreg (ad->base_term); |
2474 | rtx *index_term = strip_subreg (ad->index_term); | |
2475 | if (base_term != NULL) | |
cbdc5144 | 2476 | { |
1efe9e9d | 2477 | saved_base_reg = *base_term; |
2478 | lra_eliminate_reg_if_possible (base_term); | |
2479 | if (ad->base_term2 != NULL) | |
2480 | *ad->base_term2 = *ad->base_term; | |
cbdc5144 | 2481 | } |
1efe9e9d | 2482 | if (index_term != NULL) |
cbdc5144 | 2483 | { |
1efe9e9d | 2484 | saved_index_reg = *index_term; |
2485 | lra_eliminate_reg_if_possible (index_term); | |
cbdc5144 | 2486 | } |
1efe9e9d | 2487 | bool ok_p = valid_address_p (ad->mode, *ad->outer, ad->as); |
cbdc5144 | 2488 | if (saved_base_reg != NULL_RTX) |
2489 | { | |
1efe9e9d | 2490 | *base_term = saved_base_reg; |
2491 | if (ad->base_term2 != NULL) | |
2492 | *ad->base_term2 = *ad->base_term; | |
cbdc5144 | 2493 | } |
2494 | if (saved_index_reg != NULL_RTX) | |
1efe9e9d | 2495 | *index_term = saved_index_reg; |
cbdc5144 | 2496 | return ok_p; |
2497 | } | |
2498 | ||
1efe9e9d | 2499 | /* Make reload base reg + disp from address AD. Return the new pseudo. */ |
c6a6cdaa | 2500 | static rtx |
1efe9e9d | 2501 | base_plus_disp_to_reg (struct address_info *ad) |
c6a6cdaa | 2502 | { |
2503 | enum reg_class cl; | |
2504 | rtx new_reg; | |
2505 | ||
1efe9e9d | 2506 | lra_assert (ad->base == ad->base_term && ad->disp == ad->disp_term); |
2507 | cl = base_reg_class (ad->mode, ad->as, ad->base_outer_code, | |
2508 | get_index_code (ad)); | |
2509 | new_reg = lra_create_new_reg (GET_MODE (*ad->base_term), NULL_RTX, | |
2510 | cl, "base + disp"); | |
2511 | lra_emit_add (new_reg, *ad->base_term, *ad->disp_term); | |
c6a6cdaa | 2512 | return new_reg; |
2513 | } | |
2514 | ||
1efe9e9d | 2515 | /* Return true if we can add a displacement to address AD, even if that |
2516 | makes the address invalid. The fix-up code requires any new address | |
2517 | to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */ | |
809320f0 | 2518 | static bool |
1efe9e9d | 2519 | can_add_disp_p (struct address_info *ad) |
809320f0 | 2520 | { |
1efe9e9d | 2521 | return (!ad->autoinc_p |
2522 | && ad->segment == NULL | |
2523 | && ad->base == ad->base_term | |
2524 | && ad->disp == ad->disp_term); | |
809320f0 | 2525 | } |
2526 | ||
1efe9e9d | 2527 | /* Make equiv substitution in address AD. Return true if a substitution |
2528 | was made. */ | |
c6a6cdaa | 2529 | static bool |
1efe9e9d | 2530 | equiv_address_substitution (struct address_info *ad) |
c6a6cdaa | 2531 | { |
1efe9e9d | 2532 | rtx base_reg, new_base_reg, index_reg, new_index_reg, *base_term, *index_term; |
c6a6cdaa | 2533 | HOST_WIDE_INT disp, scale; |
2534 | bool change_p; | |
2535 | ||
1efe9e9d | 2536 | base_term = strip_subreg (ad->base_term); |
2537 | if (base_term == NULL) | |
c6a6cdaa | 2538 | base_reg = new_base_reg = NULL_RTX; |
2539 | else | |
2540 | { | |
1efe9e9d | 2541 | base_reg = *base_term; |
3b3a5e5f | 2542 | new_base_reg = get_equiv_with_elimination (base_reg, curr_insn); |
c6a6cdaa | 2543 | } |
1efe9e9d | 2544 | index_term = strip_subreg (ad->index_term); |
2545 | if (index_term == NULL) | |
c6a6cdaa | 2546 | index_reg = new_index_reg = NULL_RTX; |
2547 | else | |
2548 | { | |
1efe9e9d | 2549 | index_reg = *index_term; |
3b3a5e5f | 2550 | new_index_reg = get_equiv_with_elimination (index_reg, curr_insn); |
c6a6cdaa | 2551 | } |
2552 | if (base_reg == new_base_reg && index_reg == new_index_reg) | |
2553 | return false; | |
2554 | disp = 0; | |
2555 | change_p = false; | |
2556 | if (lra_dump_file != NULL) | |
2557 | { | |
2558 | fprintf (lra_dump_file, "Changing address in insn %d ", | |
2559 | INSN_UID (curr_insn)); | |
6dde9719 | 2560 | dump_value_slim (lra_dump_file, *ad->outer, 1); |
c6a6cdaa | 2561 | } |
2562 | if (base_reg != new_base_reg) | |
2563 | { | |
2564 | if (REG_P (new_base_reg)) | |
2565 | { | |
1efe9e9d | 2566 | *base_term = new_base_reg; |
c6a6cdaa | 2567 | change_p = true; |
2568 | } | |
2569 | else if (GET_CODE (new_base_reg) == PLUS | |
2570 | && REG_P (XEXP (new_base_reg, 0)) | |
809320f0 | 2571 | && CONST_INT_P (XEXP (new_base_reg, 1)) |
1efe9e9d | 2572 | && can_add_disp_p (ad)) |
c6a6cdaa | 2573 | { |
2574 | disp += INTVAL (XEXP (new_base_reg, 1)); | |
1efe9e9d | 2575 | *base_term = XEXP (new_base_reg, 0); |
c6a6cdaa | 2576 | change_p = true; |
2577 | } | |
1efe9e9d | 2578 | if (ad->base_term2 != NULL) |
2579 | *ad->base_term2 = *ad->base_term; | |
c6a6cdaa | 2580 | } |
c6a6cdaa | 2581 | if (index_reg != new_index_reg) |
2582 | { | |
2583 | if (REG_P (new_index_reg)) | |
2584 | { | |
1efe9e9d | 2585 | *index_term = new_index_reg; |
c6a6cdaa | 2586 | change_p = true; |
2587 | } | |
2588 | else if (GET_CODE (new_index_reg) == PLUS | |
2589 | && REG_P (XEXP (new_index_reg, 0)) | |
809320f0 | 2590 | && CONST_INT_P (XEXP (new_index_reg, 1)) |
1efe9e9d | 2591 | && can_add_disp_p (ad) |
809320f0 | 2592 | && (scale = get_index_scale (ad))) |
c6a6cdaa | 2593 | { |
2594 | disp += INTVAL (XEXP (new_index_reg, 1)) * scale; | |
1efe9e9d | 2595 | *index_term = XEXP (new_index_reg, 0); |
c6a6cdaa | 2596 | change_p = true; |
2597 | } | |
2598 | } | |
2599 | if (disp != 0) | |
2600 | { | |
1efe9e9d | 2601 | if (ad->disp != NULL) |
2602 | *ad->disp = plus_constant (GET_MODE (*ad->inner), *ad->disp, disp); | |
c6a6cdaa | 2603 | else |
2604 | { | |
1efe9e9d | 2605 | *ad->inner = plus_constant (GET_MODE (*ad->inner), *ad->inner, disp); |
2606 | update_address (ad); | |
c6a6cdaa | 2607 | } |
2608 | change_p = true; | |
2609 | } | |
2610 | if (lra_dump_file != NULL) | |
2611 | { | |
2612 | if (! change_p) | |
2613 | fprintf (lra_dump_file, " -- no change\n"); | |
2614 | else | |
2615 | { | |
2616 | fprintf (lra_dump_file, " on equiv "); | |
6dde9719 | 2617 | dump_value_slim (lra_dump_file, *ad->outer, 1); |
c6a6cdaa | 2618 | fprintf (lra_dump_file, "\n"); |
2619 | } | |
2620 | } | |
2621 | return change_p; | |
2622 | } | |
2623 | ||
d9b69682 | 2624 | /* Major function to make reloads for an address in operand NOP. |
2625 | The supported cases are: | |
2626 | ||
c625778b | 2627 | 1) an address that existed before LRA started, at which point it |
2628 | must have been valid. These addresses are subject to elimination | |
2629 | and may have become invalid due to the elimination offset being out | |
2630 | of range. | |
d9b69682 | 2631 | |
c625778b | 2632 | 2) an address created by forcing a constant to memory |
2633 | (force_const_to_mem). The initial form of these addresses might | |
2634 | not be valid, and it is this function's job to make them valid. | |
d9b69682 | 2635 | |
2636 | 3) a frame address formed from a register and a (possibly zero) | |
c625778b | 2637 | constant offset. As above, these addresses might not be valid and |
2638 | this function must make them so. | |
d9b69682 | 2639 | |
2640 | Add reloads to the lists *BEFORE and *AFTER. We might need to add | |
c6a6cdaa | 2641 | reloads to *AFTER because of inc/dec, {pre, post} modify in the |
2642 | address. Return true for any RTL change. */ | |
2643 | static bool | |
2644 | process_address (int nop, rtx *before, rtx *after) | |
2645 | { | |
1efe9e9d | 2646 | struct address_info ad; |
2647 | rtx new_reg; | |
c6a6cdaa | 2648 | rtx op = *curr_id->operand_loc[nop]; |
2649 | const char *constraint = curr_static_id->operand[nop].constraint; | |
2650 | bool change_p; | |
c6a6cdaa | 2651 | |
2652 | if (constraint[0] == 'p' | |
2653 | || EXTRA_ADDRESS_CONSTRAINT (constraint[0], constraint)) | |
1efe9e9d | 2654 | decompose_lea_address (&ad, curr_id->operand_loc[nop]); |
c6a6cdaa | 2655 | else if (MEM_P (op)) |
1efe9e9d | 2656 | decompose_mem_address (&ad, op); |
c6a6cdaa | 2657 | else if (GET_CODE (op) == SUBREG |
2658 | && MEM_P (SUBREG_REG (op))) | |
1efe9e9d | 2659 | decompose_mem_address (&ad, SUBREG_REG (op)); |
c6a6cdaa | 2660 | else |
2661 | return false; | |
1efe9e9d | 2662 | change_p = equiv_address_substitution (&ad); |
2663 | if (ad.base_term != NULL | |
c6a6cdaa | 2664 | && (process_addr_reg |
1efe9e9d | 2665 | (ad.base_term, before, |
2666 | (ad.autoinc_p | |
2667 | && !(REG_P (*ad.base_term) | |
2668 | && find_regno_note (curr_insn, REG_DEAD, | |
2669 | REGNO (*ad.base_term)) != NULL_RTX) | |
c6a6cdaa | 2670 | ? after : NULL), |
1efe9e9d | 2671 | base_reg_class (ad.mode, ad.as, ad.base_outer_code, |
2672 | get_index_code (&ad))))) | |
c6a6cdaa | 2673 | { |
2674 | change_p = true; | |
1efe9e9d | 2675 | if (ad.base_term2 != NULL) |
2676 | *ad.base_term2 = *ad.base_term; | |
c6a6cdaa | 2677 | } |
1efe9e9d | 2678 | if (ad.index_term != NULL |
2679 | && process_addr_reg (ad.index_term, before, NULL, INDEX_REG_CLASS)) | |
c6a6cdaa | 2680 | change_p = true; |
2681 | ||
ea99c7a1 | 2682 | #ifdef EXTRA_CONSTRAINT_STR |
2683 | /* Target hooks sometimes reject extra constraint addresses -- use | |
2684 | EXTRA_CONSTRAINT_STR for the validation. */ | |
2685 | if (constraint[0] != 'p' | |
2686 | && EXTRA_ADDRESS_CONSTRAINT (constraint[0], constraint) | |
2687 | && EXTRA_CONSTRAINT_STR (op, constraint[0], constraint)) | |
2688 | return change_p; | |
2689 | #endif | |
2690 | ||
1efe9e9d | 2691 | /* There are three cases where the shape of *AD.INNER may now be invalid: |
d9b69682 | 2692 | |
2693 | 1) the original address was valid, but either elimination or | |
c625778b | 2694 | equiv_address_substitution was applied and that made |
2695 | the address invalid. | |
d9b69682 | 2696 | |
2697 | 2) the address is an invalid symbolic address created by | |
c625778b | 2698 | force_const_to_mem. |
d9b69682 | 2699 | |
2700 | 3) the address is a frame address with an invalid offset. | |
2701 | ||
ea99c7a1 | 2702 | All these cases involve a non-autoinc address, so there is no |
2703 | point revalidating other types. */ | |
2704 | if (ad.autoinc_p || valid_address_p (&ad)) | |
c6a6cdaa | 2705 | return change_p; |
2706 | ||
d9b69682 | 2707 | /* Any index existed before LRA started, so we can assume that the |
2708 | presence and shape of the index is valid. */ | |
c6a6cdaa | 2709 | push_to_sequence (*before); |
ea99c7a1 | 2710 | lra_assert (ad.disp == ad.disp_term); |
1efe9e9d | 2711 | if (ad.base == NULL) |
c6a6cdaa | 2712 | { |
1efe9e9d | 2713 | if (ad.index == NULL) |
c6a6cdaa | 2714 | { |
2715 | int code = -1; | |
1efe9e9d | 2716 | enum reg_class cl = base_reg_class (ad.mode, ad.as, |
2717 | SCRATCH, SCRATCH); | |
ea99c7a1 | 2718 | rtx addr = *ad.inner; |
1efe9e9d | 2719 | |
ea99c7a1 | 2720 | new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "addr"); |
c6a6cdaa | 2721 | #ifdef HAVE_lo_sum |
2722 | { | |
2723 | rtx insn; | |
2724 | rtx last = get_last_insn (); | |
2725 | ||
ea99c7a1 | 2726 | /* addr => lo_sum (new_base, addr), case (2) above. */ |
c6a6cdaa | 2727 | insn = emit_insn (gen_rtx_SET |
2728 | (VOIDmode, new_reg, | |
ea99c7a1 | 2729 | gen_rtx_HIGH (Pmode, copy_rtx (addr)))); |
c6a6cdaa | 2730 | code = recog_memoized (insn); |
2731 | if (code >= 0) | |
2732 | { | |
ea99c7a1 | 2733 | *ad.inner = gen_rtx_LO_SUM (Pmode, new_reg, addr); |
1efe9e9d | 2734 | if (! valid_address_p (ad.mode, *ad.outer, ad.as)) |
c6a6cdaa | 2735 | { |
ea99c7a1 | 2736 | /* Try to put lo_sum into register. */ |
2737 | insn = emit_insn (gen_rtx_SET | |
2738 | (VOIDmode, new_reg, | |
2739 | gen_rtx_LO_SUM (Pmode, new_reg, addr))); | |
2740 | code = recog_memoized (insn); | |
2741 | if (code >= 0) | |
2742 | { | |
2743 | *ad.inner = new_reg; | |
2744 | if (! valid_address_p (ad.mode, *ad.outer, ad.as)) | |
2745 | { | |
2746 | *ad.inner = addr; | |
2747 | code = -1; | |
2748 | } | |
2749 | } | |
2750 | ||
c6a6cdaa | 2751 | } |
2752 | } | |
2753 | if (code < 0) | |
2754 | delete_insns_since (last); | |
2755 | } | |
2756 | #endif | |
2757 | if (code < 0) | |
2758 | { | |
ea99c7a1 | 2759 | /* addr => new_base, case (2) above. */ |
2760 | lra_emit_move (new_reg, addr); | |
2761 | *ad.inner = new_reg; | |
c6a6cdaa | 2762 | } |
2763 | } | |
2764 | else | |
2765 | { | |
d9b69682 | 2766 | /* index * scale + disp => new base + index * scale, |
2767 | case (1) above. */ | |
1efe9e9d | 2768 | enum reg_class cl = base_reg_class (ad.mode, ad.as, PLUS, |
2769 | GET_CODE (*ad.index)); | |
c6a6cdaa | 2770 | |
2771 | lra_assert (INDEX_REG_CLASS != NO_REGS); | |
2772 | new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "disp"); | |
1efe9e9d | 2773 | lra_emit_move (new_reg, *ad.disp); |
2774 | *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), | |
2775 | new_reg, *ad.index); | |
c6a6cdaa | 2776 | } |
2777 | } | |
1efe9e9d | 2778 | else if (ad.index == NULL) |
c6a6cdaa | 2779 | { |
c625778b | 2780 | int regno; |
2781 | enum reg_class cl; | |
2782 | rtx set, insns, last_insn; | |
d9b69682 | 2783 | /* base + disp => new base, cases (1) and (3) above. */ |
c6a6cdaa | 2784 | /* Another option would be to reload the displacement into an |
2785 | index register. However, postreload has code to optimize | |
2786 | address reloads that have the same base and different | |
2787 | displacements, so reloading into an index register would | |
2788 | not necessarily be a win. */ | |
c625778b | 2789 | start_sequence (); |
1efe9e9d | 2790 | new_reg = base_plus_disp_to_reg (&ad); |
c625778b | 2791 | insns = get_insns (); |
2792 | last_insn = get_last_insn (); | |
2793 | /* If we generated at least two insns, try last insn source as | |
2794 | an address. If we succeed, we generate one less insn. */ | |
2795 | if (last_insn != insns && (set = single_set (last_insn)) != NULL_RTX | |
2796 | && GET_CODE (SET_SRC (set)) == PLUS | |
2797 | && REG_P (XEXP (SET_SRC (set), 0)) | |
2798 | && CONSTANT_P (XEXP (SET_SRC (set), 1))) | |
2799 | { | |
2800 | *ad.inner = SET_SRC (set); | |
2801 | if (valid_address_p (ad.mode, *ad.outer, ad.as)) | |
2802 | { | |
2803 | *ad.base_term = XEXP (SET_SRC (set), 0); | |
2804 | *ad.disp_term = XEXP (SET_SRC (set), 1); | |
2805 | cl = base_reg_class (ad.mode, ad.as, ad.base_outer_code, | |
2806 | get_index_code (&ad)); | |
2807 | regno = REGNO (*ad.base_term); | |
2808 | if (regno >= FIRST_PSEUDO_REGISTER | |
2809 | && cl != lra_get_allocno_class (regno)) | |
7619e612 | 2810 | lra_change_class (regno, cl, " Change to", true); |
c625778b | 2811 | new_reg = SET_SRC (set); |
2812 | delete_insns_since (PREV_INSN (last_insn)); | |
2813 | } | |
2814 | } | |
2815 | end_sequence (); | |
2816 | emit_insn (insns); | |
1efe9e9d | 2817 | *ad.inner = new_reg; |
c6a6cdaa | 2818 | } |
2819 | else | |
2820 | { | |
d9b69682 | 2821 | /* base + scale * index + disp => new base + scale * index, |
2822 | case (1) above. */ | |
1efe9e9d | 2823 | new_reg = base_plus_disp_to_reg (&ad); |
2824 | *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), | |
2825 | new_reg, *ad.index); | |
c6a6cdaa | 2826 | } |
2827 | *before = get_insns (); | |
2828 | end_sequence (); | |
2829 | return true; | |
2830 | } | |
2831 | ||
2832 | /* Emit insns to reload VALUE into a new register. VALUE is an | |
2833 | auto-increment or auto-decrement RTX whose operand is a register or | |
2834 | memory location; so reloading involves incrementing that location. | |
2835 | IN is either identical to VALUE, or some cheaper place to reload | |
2836 | value being incremented/decremented from. | |
2837 | ||
2838 | INC_AMOUNT is the number to increment or decrement by (always | |
2839 | positive and ignored for POST_MODIFY/PRE_MODIFY). | |
2840 | ||
2841 | Return pseudo containing the result. */ | |
2842 | static rtx | |
2843 | emit_inc (enum reg_class new_rclass, rtx in, rtx value, int inc_amount) | |
2844 | { | |
2845 | /* REG or MEM to be copied and incremented. */ | |
2846 | rtx incloc = XEXP (value, 0); | |
2847 | /* Nonzero if increment after copying. */ | |
2848 | int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC | |
2849 | || GET_CODE (value) == POST_MODIFY); | |
2850 | rtx last; | |
2851 | rtx inc; | |
2852 | rtx add_insn; | |
2853 | int code; | |
2854 | rtx real_in = in == value ? incloc : in; | |
2855 | rtx result; | |
2856 | bool plus_p = true; | |
2857 | ||
2858 | if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY) | |
2859 | { | |
2860 | lra_assert (GET_CODE (XEXP (value, 1)) == PLUS | |
2861 | || GET_CODE (XEXP (value, 1)) == MINUS); | |
2862 | lra_assert (rtx_equal_p (XEXP (XEXP (value, 1), 0), XEXP (value, 0))); | |
2863 | plus_p = GET_CODE (XEXP (value, 1)) == PLUS; | |
2864 | inc = XEXP (XEXP (value, 1), 1); | |
2865 | } | |
2866 | else | |
2867 | { | |
2868 | if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC) | |
2869 | inc_amount = -inc_amount; | |
2870 | ||
2871 | inc = GEN_INT (inc_amount); | |
2872 | } | |
2873 | ||
2874 | if (! post && REG_P (incloc)) | |
2875 | result = incloc; | |
2876 | else | |
2877 | result = lra_create_new_reg (GET_MODE (value), value, new_rclass, | |
2878 | "INC/DEC result"); | |
2879 | ||
2880 | if (real_in != result) | |
2881 | { | |
2882 | /* First copy the location to the result register. */ | |
2883 | lra_assert (REG_P (result)); | |
2884 | emit_insn (gen_move_insn (result, real_in)); | |
2885 | } | |
2886 | ||
2887 | /* We suppose that there are insns to add/sub with the constant | |
2888 | increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the | |
2889 | old reload worked with this assumption. If the assumption | |
2890 | becomes wrong, we should use approach in function | |
2891 | base_plus_disp_to_reg. */ | |
2892 | if (in == value) | |
2893 | { | |
2894 | /* See if we can directly increment INCLOC. */ | |
2895 | last = get_last_insn (); | |
2896 | add_insn = emit_insn (plus_p | |
2897 | ? gen_add2_insn (incloc, inc) | |
2898 | : gen_sub2_insn (incloc, inc)); | |
2899 | ||
2900 | code = recog_memoized (add_insn); | |
2901 | if (code >= 0) | |
2902 | { | |
2903 | if (! post && result != incloc) | |
2904 | emit_insn (gen_move_insn (result, incloc)); | |
2905 | return result; | |
2906 | } | |
2907 | delete_insns_since (last); | |
2908 | } | |
2909 | ||
2910 | /* If couldn't do the increment directly, must increment in RESULT. | |
2911 | The way we do this depends on whether this is pre- or | |
2912 | post-increment. For pre-increment, copy INCLOC to the reload | |
2913 | register, increment it there, then save back. */ | |
2914 | if (! post) | |
2915 | { | |
2916 | if (real_in != result) | |
2917 | emit_insn (gen_move_insn (result, real_in)); | |
2918 | if (plus_p) | |
2919 | emit_insn (gen_add2_insn (result, inc)); | |
2920 | else | |
2921 | emit_insn (gen_sub2_insn (result, inc)); | |
2922 | if (result != incloc) | |
2923 | emit_insn (gen_move_insn (incloc, result)); | |
2924 | } | |
2925 | else | |
2926 | { | |
2927 | /* Post-increment. | |
2928 | ||
2929 | Because this might be a jump insn or a compare, and because | |
2930 | RESULT may not be available after the insn in an input | |
2931 | reload, we must do the incrementing before the insn being | |
2932 | reloaded for. | |
2933 | ||
2934 | We have already copied IN to RESULT. Increment the copy in | |
2935 | RESULT, save that back, then decrement RESULT so it has | |
2936 | the original value. */ | |
2937 | if (plus_p) | |
2938 | emit_insn (gen_add2_insn (result, inc)); | |
2939 | else | |
2940 | emit_insn (gen_sub2_insn (result, inc)); | |
2941 | emit_insn (gen_move_insn (incloc, result)); | |
2942 | /* Restore non-modified value for the result. We prefer this | |
2943 | way because it does not require an additional hard | |
2944 | register. */ | |
2945 | if (plus_p) | |
2946 | { | |
2947 | if (CONST_INT_P (inc)) | |
d11aedc7 | 2948 | emit_insn (gen_add2_insn (result, |
2949 | gen_int_mode (-INTVAL (inc), | |
2950 | GET_MODE (result)))); | |
c6a6cdaa | 2951 | else |
2952 | emit_insn (gen_sub2_insn (result, inc)); | |
2953 | } | |
2954 | else | |
2955 | emit_insn (gen_add2_insn (result, inc)); | |
2956 | } | |
2957 | return result; | |
2958 | } | |
2959 | ||
ea99c7a1 | 2960 | /* Return true if the current move insn does not need processing as we |
2961 | already know that it satisfies its constraints. */ | |
2962 | static bool | |
2963 | simple_move_p (void) | |
2964 | { | |
2965 | rtx dest, src; | |
2966 | enum reg_class dclass, sclass; | |
2967 | ||
2968 | lra_assert (curr_insn_set != NULL_RTX); | |
2969 | dest = SET_DEST (curr_insn_set); | |
2970 | src = SET_SRC (curr_insn_set); | |
2971 | return ((dclass = get_op_class (dest)) != NO_REGS | |
2972 | && (sclass = get_op_class (src)) != NO_REGS | |
2973 | /* The backend guarantees that register moves of cost 2 | |
2974 | never need reloads. */ | |
2975 | && targetm.register_move_cost (GET_MODE (src), dclass, sclass) == 2); | |
2976 | } | |
2977 | ||
c6a6cdaa | 2978 | /* Swap operands NOP and NOP + 1. */ |
2979 | static inline void | |
2980 | swap_operands (int nop) | |
2981 | { | |
2982 | enum machine_mode mode = curr_operand_mode[nop]; | |
2983 | curr_operand_mode[nop] = curr_operand_mode[nop + 1]; | |
2984 | curr_operand_mode[nop + 1] = mode; | |
2985 | rtx x = *curr_id->operand_loc[nop]; | |
2986 | *curr_id->operand_loc[nop] = *curr_id->operand_loc[nop + 1]; | |
2987 | *curr_id->operand_loc[nop + 1] = x; | |
2988 | /* Swap the duplicates too. */ | |
2989 | lra_update_dup (curr_id, nop); | |
2990 | lra_update_dup (curr_id, nop + 1); | |
2991 | } | |
2992 | ||
2993 | /* Main entry point of the constraint code: search the body of the | |
2994 | current insn to choose the best alternative. It is mimicking insn | |
2995 | alternative cost calculation model of former reload pass. That is | |
2996 | because machine descriptions were written to use this model. This | |
2997 | model can be changed in future. Make commutative operand exchange | |
2998 | if it is chosen. | |
2999 | ||
3000 | Return true if some RTL changes happened during function call. */ | |
3001 | static bool | |
3002 | curr_insn_transform (void) | |
3003 | { | |
3004 | int i, j, k; | |
3005 | int n_operands; | |
3006 | int n_alternatives; | |
3007 | int commutative; | |
3008 | signed char goal_alt_matched[MAX_RECOG_OPERANDS][MAX_RECOG_OPERANDS]; | |
aa3ce8ba | 3009 | signed char match_inputs[MAX_RECOG_OPERANDS + 1]; |
c6a6cdaa | 3010 | rtx before, after; |
3011 | bool alt_p = false; | |
3012 | /* Flag that the insn has been changed through a transformation. */ | |
3013 | bool change_p; | |
3014 | bool sec_mem_p; | |
3015 | #ifdef SECONDARY_MEMORY_NEEDED | |
3016 | bool use_sec_mem_p; | |
3017 | #endif | |
3018 | int max_regno_before; | |
3019 | int reused_alternative_num; | |
3020 | ||
ea99c7a1 | 3021 | curr_insn_set = single_set (curr_insn); |
3022 | if (curr_insn_set != NULL_RTX && simple_move_p ()) | |
3023 | return false; | |
3024 | ||
c6a6cdaa | 3025 | no_input_reloads_p = no_output_reloads_p = false; |
3026 | goal_alt_number = -1; | |
ea99c7a1 | 3027 | change_p = sec_mem_p = false; |
c6a6cdaa | 3028 | /* JUMP_INSNs and CALL_INSNs are not allowed to have any output |
3029 | reloads; neither are insns that SET cc0. Insns that use CC0 are | |
3030 | not allowed to have any input reloads. */ | |
3031 | if (JUMP_P (curr_insn) || CALL_P (curr_insn)) | |
3032 | no_output_reloads_p = true; | |
3033 | ||
3034 | #ifdef HAVE_cc0 | |
3035 | if (reg_referenced_p (cc0_rtx, PATTERN (curr_insn))) | |
3036 | no_input_reloads_p = true; | |
3037 | if (reg_set_p (cc0_rtx, PATTERN (curr_insn))) | |
3038 | no_output_reloads_p = true; | |
3039 | #endif | |
3040 | ||
3041 | n_operands = curr_static_id->n_operands; | |
3042 | n_alternatives = curr_static_id->n_alternatives; | |
3043 | ||
3044 | /* Just return "no reloads" if insn has no operands with | |
3045 | constraints. */ | |
3046 | if (n_operands == 0 || n_alternatives == 0) | |
3047 | return false; | |
3048 | ||
3049 | max_regno_before = max_reg_num (); | |
3050 | ||
3051 | for (i = 0; i < n_operands; i++) | |
3052 | { | |
3053 | goal_alt_matched[i][0] = -1; | |
3054 | goal_alt_matches[i] = -1; | |
3055 | } | |
3056 | ||
3057 | commutative = curr_static_id->commutative; | |
3058 | ||
3059 | /* Now see what we need for pseudos that didn't get hard regs or got | |
3060 | the wrong kind of hard reg. For this, we must consider all the | |
3061 | operands together against the register constraints. */ | |
3062 | ||
4b3aba76 | 3063 | best_losers = best_overall = INT_MAX; |
273c330a | 3064 | best_reload_sum = 0; |
c6a6cdaa | 3065 | |
3066 | curr_swapped = false; | |
3067 | goal_alt_swapped = false; | |
3068 | ||
3069 | /* Make equivalence substitution and memory subreg elimination | |
3070 | before address processing because an address legitimacy can | |
3071 | depend on memory mode. */ | |
3072 | for (i = 0; i < n_operands; i++) | |
3073 | { | |
3074 | rtx op = *curr_id->operand_loc[i]; | |
3075 | rtx subst, old = op; | |
3076 | bool op_change_p = false; | |
3077 | ||
3078 | if (GET_CODE (old) == SUBREG) | |
3079 | old = SUBREG_REG (old); | |
3b3a5e5f | 3080 | subst = get_equiv_with_elimination (old, curr_insn); |
c6a6cdaa | 3081 | if (subst != old) |
3082 | { | |
3083 | subst = copy_rtx (subst); | |
3084 | lra_assert (REG_P (old)); | |
3085 | if (GET_CODE (op) == SUBREG) | |
3086 | SUBREG_REG (op) = subst; | |
3087 | else | |
3088 | *curr_id->operand_loc[i] = subst; | |
3089 | if (lra_dump_file != NULL) | |
3090 | { | |
3091 | fprintf (lra_dump_file, | |
3092 | "Changing pseudo %d in operand %i of insn %u on equiv ", | |
3093 | REGNO (old), i, INSN_UID (curr_insn)); | |
6dde9719 | 3094 | dump_value_slim (lra_dump_file, subst, 1); |
c6a6cdaa | 3095 | fprintf (lra_dump_file, "\n"); |
3096 | } | |
3097 | op_change_p = change_p = true; | |
3098 | } | |
3099 | if (simplify_operand_subreg (i, GET_MODE (old)) || op_change_p) | |
3100 | { | |
3101 | change_p = true; | |
3102 | lra_update_dup (curr_id, i); | |
3103 | } | |
3104 | } | |
3105 | ||
3106 | /* Reload address registers and displacements. We do it before | |
3107 | finding an alternative because of memory constraints. */ | |
3108 | before = after = NULL_RTX; | |
3109 | for (i = 0; i < n_operands; i++) | |
3110 | if (! curr_static_id->operand[i].is_operator | |
3111 | && process_address (i, &before, &after)) | |
3112 | { | |
3113 | change_p = true; | |
3114 | lra_update_dup (curr_id, i); | |
3115 | } | |
1a8f8886 | 3116 | |
c6a6cdaa | 3117 | if (change_p) |
3118 | /* If we've changed the instruction then any alternative that | |
3119 | we chose previously may no longer be valid. */ | |
3120 | lra_set_used_insn_alternative (curr_insn, -1); | |
3121 | ||
ea99c7a1 | 3122 | if (curr_insn_set != NULL_RTX |
3123 | && check_and_process_move (&change_p, &sec_mem_p)) | |
3124 | return change_p; | |
3125 | ||
c6a6cdaa | 3126 | try_swapped: |
3127 | ||
3128 | reused_alternative_num = curr_id->used_insn_alternative; | |
3129 | if (lra_dump_file != NULL && reused_alternative_num >= 0) | |
3130 | fprintf (lra_dump_file, "Reusing alternative %d for insn #%u\n", | |
3131 | reused_alternative_num, INSN_UID (curr_insn)); | |
3132 | ||
3133 | if (process_alt_operands (reused_alternative_num)) | |
3134 | alt_p = true; | |
3135 | ||
3136 | /* If insn is commutative (it's safe to exchange a certain pair of | |
3137 | operands) then we need to try each alternative twice, the second | |
3138 | time matching those two operands as if we had exchanged them. To | |
3139 | do this, really exchange them in operands. | |
3140 | ||
3141 | If we have just tried the alternatives the second time, return | |
3142 | operands to normal and drop through. */ | |
3143 | ||
3144 | if (reused_alternative_num < 0 && commutative >= 0) | |
3145 | { | |
3146 | curr_swapped = !curr_swapped; | |
3147 | if (curr_swapped) | |
3148 | { | |
3149 | swap_operands (commutative); | |
3150 | goto try_swapped; | |
3151 | } | |
3152 | else | |
3153 | swap_operands (commutative); | |
3154 | } | |
3155 | ||
c6a6cdaa | 3156 | if (! alt_p && ! sec_mem_p) |
3157 | { | |
3158 | /* No alternative works with reloads?? */ | |
3159 | if (INSN_CODE (curr_insn) >= 0) | |
3160 | fatal_insn ("unable to generate reloads for:", curr_insn); | |
3161 | error_for_asm (curr_insn, | |
3162 | "inconsistent operand constraints in an %<asm%>"); | |
3163 | /* Avoid further trouble with this insn. */ | |
3164 | PATTERN (curr_insn) = gen_rtx_USE (VOIDmode, const0_rtx); | |
3165 | lra_invalidate_insn_data (curr_insn); | |
3166 | return true; | |
3167 | } | |
3168 | ||
3169 | /* If the best alternative is with operands 1 and 2 swapped, swap | |
3170 | them. Update the operand numbers of any reloads already | |
3171 | pushed. */ | |
3172 | ||
3173 | if (goal_alt_swapped) | |
3174 | { | |
3175 | if (lra_dump_file != NULL) | |
3176 | fprintf (lra_dump_file, " Commutative operand exchange in insn %u\n", | |
3177 | INSN_UID (curr_insn)); | |
3178 | ||
3179 | /* Swap the duplicates too. */ | |
3180 | swap_operands (commutative); | |
3181 | change_p = true; | |
3182 | } | |
3183 | ||
3184 | #ifdef SECONDARY_MEMORY_NEEDED | |
3185 | /* Some target macros SECONDARY_MEMORY_NEEDED (e.g. x86) are defined | |
3186 | too conservatively. So we use the secondary memory only if there | |
3187 | is no any alternative without reloads. */ | |
3188 | use_sec_mem_p = false; | |
3189 | if (! alt_p) | |
3190 | use_sec_mem_p = true; | |
3191 | else if (sec_mem_p) | |
3192 | { | |
3193 | for (i = 0; i < n_operands; i++) | |
3194 | if (! goal_alt_win[i] && ! goal_alt_match_win[i]) | |
3195 | break; | |
3196 | use_sec_mem_p = i < n_operands; | |
3197 | } | |
3198 | ||
3199 | if (use_sec_mem_p) | |
3200 | { | |
e0420317 | 3201 | rtx new_reg, src, dest, rld; |
c47331e3 | 3202 | enum machine_mode sec_mode, rld_mode; |
c6a6cdaa | 3203 | |
3204 | lra_assert (sec_mem_p); | |
c47331e3 | 3205 | lra_assert (curr_static_id->operand[0].type == OP_OUT |
3206 | && curr_static_id->operand[1].type == OP_IN); | |
3207 | dest = *curr_id->operand_loc[0]; | |
3208 | src = *curr_id->operand_loc[1]; | |
3209 | rld = (GET_MODE_SIZE (GET_MODE (dest)) <= GET_MODE_SIZE (GET_MODE (src)) | |
3210 | ? dest : src); | |
3211 | rld_mode = GET_MODE (rld); | |
c6a6cdaa | 3212 | #ifdef SECONDARY_MEMORY_NEEDED_MODE |
c47331e3 | 3213 | sec_mode = SECONDARY_MEMORY_NEEDED_MODE (rld_mode); |
c6a6cdaa | 3214 | #else |
c47331e3 | 3215 | sec_mode = rld_mode; |
c6a6cdaa | 3216 | #endif |
3217 | new_reg = lra_create_new_reg (sec_mode, NULL_RTX, | |
3218 | NO_REGS, "secondary"); | |
3219 | /* If the mode is changed, it should be wider. */ | |
c47331e3 | 3220 | lra_assert (GET_MODE_SIZE (sec_mode) >= GET_MODE_SIZE (rld_mode)); |
e0420317 | 3221 | if (sec_mode != rld_mode) |
3222 | { | |
3223 | /* If the target says specifically to use another mode for | |
3224 | secondary memory moves we can not reuse the original | |
3225 | insn. */ | |
cc0dc61b | 3226 | after = emit_spill_move (false, new_reg, dest); |
3227 | lra_process_new_insns (curr_insn, NULL_RTX, after, | |
3228 | "Inserting the sec. move"); | |
3229 | /* We may have non null BEFORE here (e.g. after address | |
3230 | processing. */ | |
3231 | push_to_sequence (before); | |
3232 | before = emit_spill_move (true, new_reg, src); | |
3233 | emit_insn (before); | |
3234 | before = get_insns (); | |
3235 | end_sequence (); | |
3236 | lra_process_new_insns (curr_insn, before, NULL_RTX, "Changing on"); | |
3237 | lra_set_insn_deleted (curr_insn); | |
3238 | } | |
e0420317 | 3239 | else if (dest == rld) |
cc0dc61b | 3240 | { |
3241 | *curr_id->operand_loc[0] = new_reg; | |
c47331e3 | 3242 | after = emit_spill_move (false, new_reg, dest); |
3243 | lra_process_new_insns (curr_insn, NULL_RTX, after, | |
3244 | "Inserting the sec. move"); | |
3245 | } | |
3246 | else | |
3247 | { | |
e0420317 | 3248 | *curr_id->operand_loc[1] = new_reg; |
cc0dc61b | 3249 | /* See comments above. */ |
3250 | push_to_sequence (before); | |
c47331e3 | 3251 | before = emit_spill_move (true, new_reg, src); |
cc0dc61b | 3252 | emit_insn (before); |
3253 | before = get_insns (); | |
3254 | end_sequence (); | |
c47331e3 | 3255 | lra_process_new_insns (curr_insn, before, NULL_RTX, |
3256 | "Inserting the sec. move"); | |
3257 | } | |
3258 | lra_update_insn_regno_info (curr_insn); | |
c6a6cdaa | 3259 | return true; |
3260 | } | |
3261 | #endif | |
3262 | ||
3263 | lra_assert (goal_alt_number >= 0); | |
3264 | lra_set_used_insn_alternative (curr_insn, goal_alt_number); | |
3265 | ||
3266 | if (lra_dump_file != NULL) | |
3267 | { | |
3268 | const char *p; | |
3269 | ||
3270 | fprintf (lra_dump_file, " Choosing alt %d in insn %u:", | |
3271 | goal_alt_number, INSN_UID (curr_insn)); | |
3272 | for (i = 0; i < n_operands; i++) | |
3273 | { | |
3274 | p = (curr_static_id->operand_alternative | |
3275 | [goal_alt_number * n_operands + i].constraint); | |
3276 | if (*p == '\0') | |
3277 | continue; | |
3278 | fprintf (lra_dump_file, " (%d) ", i); | |
3279 | for (; *p != '\0' && *p != ',' && *p != '#'; p++) | |
3280 | fputc (*p, lra_dump_file); | |
3281 | } | |
273c330a | 3282 | if (INSN_CODE (curr_insn) >= 0 |
3283 | && (p = get_insn_name (INSN_CODE (curr_insn))) != NULL) | |
3284 | fprintf (lra_dump_file, " {%s}", p); | |
3b3a5e5f | 3285 | if (curr_id->sp_offset != 0) |
3286 | fprintf (lra_dump_file, " (sp_off=%" HOST_WIDE_INT_PRINT "d)", | |
3287 | curr_id->sp_offset); | |
273c330a | 3288 | fprintf (lra_dump_file, "\n"); |
c6a6cdaa | 3289 | } |
3290 | ||
3291 | /* Right now, for any pair of operands I and J that are required to | |
3292 | match, with J < I, goal_alt_matches[I] is J. Add I to | |
3293 | goal_alt_matched[J]. */ | |
1a8f8886 | 3294 | |
c6a6cdaa | 3295 | for (i = 0; i < n_operands; i++) |
3296 | if ((j = goal_alt_matches[i]) >= 0) | |
3297 | { | |
3298 | for (k = 0; goal_alt_matched[j][k] >= 0; k++) | |
3299 | ; | |
3300 | /* We allow matching one output operand and several input | |
3301 | operands. */ | |
3302 | lra_assert (k == 0 | |
3303 | || (curr_static_id->operand[j].type == OP_OUT | |
3304 | && curr_static_id->operand[i].type == OP_IN | |
3305 | && (curr_static_id->operand | |
3306 | [goal_alt_matched[j][0]].type == OP_IN))); | |
3307 | goal_alt_matched[j][k] = i; | |
3308 | goal_alt_matched[j][k + 1] = -1; | |
3309 | } | |
1a8f8886 | 3310 | |
c6a6cdaa | 3311 | for (i = 0; i < n_operands; i++) |
3312 | goal_alt_win[i] |= goal_alt_match_win[i]; | |
1a8f8886 | 3313 | |
c6a6cdaa | 3314 | /* Any constants that aren't allowed and can't be reloaded into |
3315 | registers are here changed into memory references. */ | |
3316 | for (i = 0; i < n_operands; i++) | |
3317 | if (goal_alt_win[i]) | |
3318 | { | |
3319 | int regno; | |
3320 | enum reg_class new_class; | |
3321 | rtx reg = *curr_id->operand_loc[i]; | |
3322 | ||
3323 | if (GET_CODE (reg) == SUBREG) | |
3324 | reg = SUBREG_REG (reg); | |
1a8f8886 | 3325 | |
c6a6cdaa | 3326 | if (REG_P (reg) && (regno = REGNO (reg)) >= FIRST_PSEUDO_REGISTER) |
3327 | { | |
3328 | bool ok_p = in_class_p (reg, goal_alt[i], &new_class); | |
3329 | ||
3330 | if (new_class != NO_REGS && get_reg_class (regno) != new_class) | |
3331 | { | |
3332 | lra_assert (ok_p); | |
7619e612 | 3333 | lra_change_class (regno, new_class, " Change to", true); |
c6a6cdaa | 3334 | } |
3335 | } | |
3336 | } | |
3337 | else | |
3338 | { | |
3339 | const char *constraint; | |
3340 | char c; | |
3341 | rtx op = *curr_id->operand_loc[i]; | |
3342 | rtx subreg = NULL_RTX; | |
3343 | enum machine_mode mode = curr_operand_mode[i]; | |
1a8f8886 | 3344 | |
c6a6cdaa | 3345 | if (GET_CODE (op) == SUBREG) |
3346 | { | |
3347 | subreg = op; | |
3348 | op = SUBREG_REG (op); | |
3349 | mode = GET_MODE (op); | |
3350 | } | |
1a8f8886 | 3351 | |
c6a6cdaa | 3352 | if (CONST_POOL_OK_P (mode, op) |
3353 | && ((targetm.preferred_reload_class | |
3354 | (op, (enum reg_class) goal_alt[i]) == NO_REGS) | |
3355 | || no_input_reloads_p)) | |
3356 | { | |
3357 | rtx tem = force_const_mem (mode, op); | |
1a8f8886 | 3358 | |
c6a6cdaa | 3359 | change_p = true; |
3360 | if (subreg != NULL_RTX) | |
3361 | tem = gen_rtx_SUBREG (mode, tem, SUBREG_BYTE (subreg)); | |
1a8f8886 | 3362 | |
c6a6cdaa | 3363 | *curr_id->operand_loc[i] = tem; |
3364 | lra_update_dup (curr_id, i); | |
3365 | process_address (i, &before, &after); | |
1a8f8886 | 3366 | |
c6a6cdaa | 3367 | /* If the alternative accepts constant pool refs directly |
3368 | there will be no reload needed at all. */ | |
3369 | if (subreg != NULL_RTX) | |
3370 | continue; | |
3371 | /* Skip alternatives before the one requested. */ | |
3372 | constraint = (curr_static_id->operand_alternative | |
3373 | [goal_alt_number * n_operands + i].constraint); | |
3374 | for (; | |
3375 | (c = *constraint) && c != ',' && c != '#'; | |
3376 | constraint += CONSTRAINT_LEN (c, constraint)) | |
3377 | { | |
3378 | if (c == TARGET_MEM_CONSTRAINT || c == 'o') | |
3379 | break; | |
3380 | #ifdef EXTRA_CONSTRAINT_STR | |
3381 | if (EXTRA_MEMORY_CONSTRAINT (c, constraint) | |
3382 | && EXTRA_CONSTRAINT_STR (tem, c, constraint)) | |
3383 | break; | |
3384 | #endif | |
3385 | } | |
3386 | if (c == '\0' || c == ',' || c == '#') | |
3387 | continue; | |
1a8f8886 | 3388 | |
c6a6cdaa | 3389 | goal_alt_win[i] = true; |
3390 | } | |
3391 | } | |
1a8f8886 | 3392 | |
c6a6cdaa | 3393 | for (i = 0; i < n_operands; i++) |
3394 | { | |
1f3a048a | 3395 | int regno; |
3396 | bool optional_p = false; | |
c6a6cdaa | 3397 | rtx old, new_reg; |
3398 | rtx op = *curr_id->operand_loc[i]; | |
3399 | ||
3400 | if (goal_alt_win[i]) | |
3401 | { | |
3402 | if (goal_alt[i] == NO_REGS | |
3403 | && REG_P (op) | |
3404 | /* When we assign NO_REGS it means that we will not | |
3405 | assign a hard register to the scratch pseudo by | |
3406 | assigment pass and the scratch pseudo will be | |
3407 | spilled. Spilled scratch pseudos are transformed | |
3408 | back to scratches at the LRA end. */ | |
3409 | && lra_former_scratch_operand_p (curr_insn, i)) | |
f7c98bb1 | 3410 | { |
3411 | int regno = REGNO (op); | |
7619e612 | 3412 | lra_change_class (regno, NO_REGS, " Change to", true); |
f7c98bb1 | 3413 | if (lra_get_regno_hard_regno (regno) >= 0) |
3414 | /* We don't have to mark all insn affected by the | |
3415 | spilled pseudo as there is only one such insn, the | |
3416 | current one. */ | |
3417 | reg_renumber[regno] = -1; | |
3418 | } | |
1f3a048a | 3419 | /* We can do an optional reload. If the pseudo got a hard |
3420 | reg, we might improve the code through inheritance. If | |
3421 | it does not get a hard register we coalesce memory/memory | |
3422 | moves later. Ignore move insns to avoid cycling. */ | |
267200f3 | 3423 | if (! lra_simple_p |
1f3a048a | 3424 | && lra_undo_inheritance_iter < LRA_MAX_INHERITANCE_PASSES |
3425 | && goal_alt[i] != NO_REGS && REG_P (op) | |
3426 | && (regno = REGNO (op)) >= FIRST_PSEUDO_REGISTER | |
7619e612 | 3427 | && regno < new_regno_start |
267200f3 | 3428 | && ! lra_former_scratch_p (regno) |
1f3a048a | 3429 | && reg_renumber[regno] < 0 |
3430 | && (curr_insn_set == NULL_RTX | |
267200f3 | 3431 | || !((REG_P (SET_SRC (curr_insn_set)) |
3432 | || MEM_P (SET_SRC (curr_insn_set)) | |
3433 | || GET_CODE (SET_SRC (curr_insn_set)) == SUBREG) | |
3434 | && (REG_P (SET_DEST (curr_insn_set)) | |
3435 | || MEM_P (SET_DEST (curr_insn_set)) | |
3436 | || GET_CODE (SET_DEST (curr_insn_set)) == SUBREG)))) | |
1f3a048a | 3437 | optional_p = true; |
3438 | else | |
3439 | continue; | |
c6a6cdaa | 3440 | } |
1a8f8886 | 3441 | |
c6a6cdaa | 3442 | /* Operands that match previous ones have already been handled. */ |
3443 | if (goal_alt_matches[i] >= 0) | |
3444 | continue; | |
3445 | ||
3446 | /* We should not have an operand with a non-offsettable address | |
3447 | appearing where an offsettable address will do. It also may | |
3448 | be a case when the address should be special in other words | |
3449 | not a general one (e.g. it needs no index reg). */ | |
3450 | if (goal_alt_matched[i][0] == -1 && goal_alt_offmemok[i] && MEM_P (op)) | |
3451 | { | |
3452 | enum reg_class rclass; | |
3453 | rtx *loc = &XEXP (op, 0); | |
3454 | enum rtx_code code = GET_CODE (*loc); | |
3455 | ||
3456 | push_to_sequence (before); | |
3457 | rclass = base_reg_class (GET_MODE (op), MEM_ADDR_SPACE (op), | |
3458 | MEM, SCRATCH); | |
3459 | if (GET_RTX_CLASS (code) == RTX_AUTOINC) | |
3460 | new_reg = emit_inc (rclass, *loc, *loc, | |
3461 | /* This value does not matter for MODIFY. */ | |
3462 | GET_MODE_SIZE (GET_MODE (op))); | |
3463 | else if (get_reload_reg (OP_IN, Pmode, *loc, rclass, | |
3464 | "offsetable address", &new_reg)) | |
3465 | lra_emit_move (new_reg, *loc); | |
3466 | before = get_insns (); | |
3467 | end_sequence (); | |
3468 | *loc = new_reg; | |
3469 | lra_update_dup (curr_id, i); | |
3470 | } | |
3471 | else if (goal_alt_matched[i][0] == -1) | |
3472 | { | |
3473 | enum machine_mode mode; | |
3474 | rtx reg, *loc; | |
3475 | int hard_regno, byte; | |
3476 | enum op_type type = curr_static_id->operand[i].type; | |
3477 | ||
3478 | loc = curr_id->operand_loc[i]; | |
3479 | mode = curr_operand_mode[i]; | |
3480 | if (GET_CODE (*loc) == SUBREG) | |
3481 | { | |
3482 | reg = SUBREG_REG (*loc); | |
3483 | byte = SUBREG_BYTE (*loc); | |
3484 | if (REG_P (reg) | |
3485 | /* Strict_low_part requires reload the register not | |
3486 | the sub-register. */ | |
3487 | && (curr_static_id->operand[i].strict_low | |
3488 | || (GET_MODE_SIZE (mode) | |
3489 | <= GET_MODE_SIZE (GET_MODE (reg)) | |
3490 | && (hard_regno | |
3491 | = get_try_hard_regno (REGNO (reg))) >= 0 | |
3492 | && (simplify_subreg_regno | |
3493 | (hard_regno, | |
3494 | GET_MODE (reg), byte, mode) < 0) | |
3495 | && (goal_alt[i] == NO_REGS | |
3496 | || (simplify_subreg_regno | |
3497 | (ira_class_hard_regs[goal_alt[i]][0], | |
3498 | GET_MODE (reg), byte, mode) >= 0))))) | |
3499 | { | |
3500 | loc = &SUBREG_REG (*loc); | |
3501 | mode = GET_MODE (*loc); | |
3502 | } | |
3503 | } | |
3504 | old = *loc; | |
3505 | if (get_reload_reg (type, mode, old, goal_alt[i], "", &new_reg) | |
3506 | && type != OP_OUT) | |
3507 | { | |
3508 | push_to_sequence (before); | |
3509 | lra_emit_move (new_reg, old); | |
3510 | before = get_insns (); | |
3511 | end_sequence (); | |
3512 | } | |
3513 | *loc = new_reg; | |
3514 | if (type != OP_IN | |
3515 | && find_reg_note (curr_insn, REG_UNUSED, old) == NULL_RTX) | |
3516 | { | |
3517 | start_sequence (); | |
3518 | lra_emit_move (type == OP_INOUT ? copy_rtx (old) : old, new_reg); | |
3519 | emit_insn (after); | |
3520 | after = get_insns (); | |
3521 | end_sequence (); | |
3522 | *loc = new_reg; | |
3523 | } | |
3524 | for (j = 0; j < goal_alt_dont_inherit_ops_num; j++) | |
3525 | if (goal_alt_dont_inherit_ops[j] == i) | |
3526 | { | |
3527 | lra_set_regno_unique_value (REGNO (new_reg)); | |
3528 | break; | |
3529 | } | |
3530 | lra_update_dup (curr_id, i); | |
3531 | } | |
3532 | else if (curr_static_id->operand[i].type == OP_IN | |
3533 | && (curr_static_id->operand[goal_alt_matched[i][0]].type | |
3534 | == OP_OUT)) | |
3535 | { | |
aa3ce8ba | 3536 | /* generate reloads for input and matched outputs. */ |
3537 | match_inputs[0] = i; | |
3538 | match_inputs[1] = -1; | |
3539 | match_reload (goal_alt_matched[i][0], match_inputs, | |
c6a6cdaa | 3540 | goal_alt[i], &before, &after); |
3541 | } | |
3542 | else if (curr_static_id->operand[i].type == OP_OUT | |
3543 | && (curr_static_id->operand[goal_alt_matched[i][0]].type | |
3544 | == OP_IN)) | |
aa3ce8ba | 3545 | /* Generate reloads for output and matched inputs. */ |
c6a6cdaa | 3546 | match_reload (i, goal_alt_matched[i], goal_alt[i], &before, &after); |
aa3ce8ba | 3547 | else if (curr_static_id->operand[i].type == OP_IN |
3548 | && (curr_static_id->operand[goal_alt_matched[i][0]].type | |
3549 | == OP_IN)) | |
3550 | { | |
3551 | /* Generate reloads for matched inputs. */ | |
3552 | match_inputs[0] = i; | |
3553 | for (j = 0; (k = goal_alt_matched[i][j]) >= 0; j++) | |
3554 | match_inputs[j + 1] = k; | |
3555 | match_inputs[j + 1] = -1; | |
3556 | match_reload (-1, match_inputs, goal_alt[i], &before, &after); | |
3557 | } | |
c6a6cdaa | 3558 | else |
3559 | /* We must generate code in any case when function | |
3560 | process_alt_operands decides that it is possible. */ | |
3561 | gcc_unreachable (); | |
1f3a048a | 3562 | if (optional_p) |
3563 | { | |
3564 | lra_assert (REG_P (op)); | |
3565 | regno = REGNO (op); | |
3566 | op = *curr_id->operand_loc[i]; /* Substitution. */ | |
3567 | if (GET_CODE (op) == SUBREG) | |
3568 | op = SUBREG_REG (op); | |
3569 | gcc_assert (REG_P (op) && (int) REGNO (op) >= new_regno_start); | |
3570 | bitmap_set_bit (&lra_optional_reload_pseudos, REGNO (op)); | |
3571 | lra_reg_info[REGNO (op)].restore_regno = regno; | |
3572 | if (lra_dump_file != NULL) | |
3573 | fprintf (lra_dump_file, | |
3574 | " Making reload reg %d for reg %d optional\n", | |
3575 | REGNO (op), regno); | |
3576 | } | |
c6a6cdaa | 3577 | } |
3578 | if (before != NULL_RTX || after != NULL_RTX | |
3579 | || max_regno_before != max_reg_num ()) | |
3580 | change_p = true; | |
3581 | if (change_p) | |
3582 | { | |
3583 | lra_update_operator_dups (curr_id); | |
3584 | /* Something changes -- process the insn. */ | |
3585 | lra_update_insn_regno_info (curr_insn); | |
3586 | } | |
3587 | lra_process_new_insns (curr_insn, before, after, "Inserting insn reload"); | |
3588 | return change_p; | |
3589 | } | |
3590 | ||
3591 | /* Return true if X is in LIST. */ | |
3592 | static bool | |
3593 | in_list_p (rtx x, rtx list) | |
3594 | { | |
3595 | for (; list != NULL_RTX; list = XEXP (list, 1)) | |
3596 | if (XEXP (list, 0) == x) | |
3597 | return true; | |
3598 | return false; | |
3599 | } | |
3600 | ||
3601 | /* Return true if X contains an allocatable hard register (if | |
3602 | HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */ | |
3603 | static bool | |
3604 | contains_reg_p (rtx x, bool hard_reg_p, bool spilled_p) | |
3605 | { | |
3606 | int i, j; | |
3607 | const char *fmt; | |
3608 | enum rtx_code code; | |
3609 | ||
3610 | code = GET_CODE (x); | |
3611 | if (REG_P (x)) | |
3612 | { | |
3613 | int regno = REGNO (x); | |
3614 | HARD_REG_SET alloc_regs; | |
3615 | ||
3616 | if (hard_reg_p) | |
3617 | { | |
3618 | if (regno >= FIRST_PSEUDO_REGISTER) | |
3619 | regno = lra_get_regno_hard_regno (regno); | |
3620 | if (regno < 0) | |
3621 | return false; | |
3622 | COMPL_HARD_REG_SET (alloc_regs, lra_no_alloc_regs); | |
3623 | return overlaps_hard_reg_set_p (alloc_regs, GET_MODE (x), regno); | |
3624 | } | |
3625 | else | |
3626 | { | |
3627 | if (regno < FIRST_PSEUDO_REGISTER) | |
3628 | return false; | |
3629 | if (! spilled_p) | |
3630 | return true; | |
3631 | return lra_get_regno_hard_regno (regno) < 0; | |
3632 | } | |
3633 | } | |
3634 | fmt = GET_RTX_FORMAT (code); | |
3635 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3636 | { | |
3637 | if (fmt[i] == 'e') | |
3638 | { | |
3639 | if (contains_reg_p (XEXP (x, i), hard_reg_p, spilled_p)) | |
3640 | return true; | |
3641 | } | |
3642 | else if (fmt[i] == 'E') | |
3643 | { | |
3644 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
3645 | if (contains_reg_p (XVECEXP (x, i, j), hard_reg_p, spilled_p)) | |
3646 | return true; | |
3647 | } | |
3648 | } | |
3649 | return false; | |
3650 | } | |
3651 | ||
d596f8db | 3652 | /* Process all regs in location *LOC and change them on equivalent |
3653 | substitution. Return true if any change was done. */ | |
c6a6cdaa | 3654 | static bool |
d596f8db | 3655 | loc_equivalence_change_p (rtx *loc) |
c6a6cdaa | 3656 | { |
3657 | rtx subst, reg, x = *loc; | |
3658 | bool result = false; | |
3659 | enum rtx_code code = GET_CODE (x); | |
3660 | const char *fmt; | |
3661 | int i, j; | |
3662 | ||
3663 | if (code == SUBREG) | |
3664 | { | |
3665 | reg = SUBREG_REG (x); | |
3b3a5e5f | 3666 | if ((subst = get_equiv_with_elimination (reg, curr_insn)) != reg |
c6a6cdaa | 3667 | && GET_MODE (subst) == VOIDmode) |
3668 | { | |
3669 | /* We cannot reload debug location. Simplify subreg here | |
3670 | while we know the inner mode. */ | |
3671 | *loc = simplify_gen_subreg (GET_MODE (x), subst, | |
3672 | GET_MODE (reg), SUBREG_BYTE (x)); | |
3673 | return true; | |
3674 | } | |
3675 | } | |
3b3a5e5f | 3676 | if (code == REG && (subst = get_equiv_with_elimination (x, curr_insn)) != x) |
c6a6cdaa | 3677 | { |
3678 | *loc = subst; | |
3679 | return true; | |
3680 | } | |
3681 | ||
3682 | /* Scan all the operand sub-expressions. */ | |
3683 | fmt = GET_RTX_FORMAT (code); | |
3684 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3685 | { | |
3686 | if (fmt[i] == 'e') | |
d596f8db | 3687 | result = loc_equivalence_change_p (&XEXP (x, i)) || result; |
c6a6cdaa | 3688 | else if (fmt[i] == 'E') |
3689 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
3690 | result | |
d596f8db | 3691 | = loc_equivalence_change_p (&XVECEXP (x, i, j)) || result; |
c6a6cdaa | 3692 | } |
3693 | return result; | |
3694 | } | |
3695 | ||
136e5c8e | 3696 | /* Similar to loc_equivalence_change_p, but for use as |
3697 | simplify_replace_fn_rtx callback. */ | |
3698 | static rtx | |
3699 | loc_equivalence_callback (rtx loc, const_rtx, void *) | |
3700 | { | |
3701 | if (!REG_P (loc)) | |
3702 | return NULL_RTX; | |
3703 | ||
3b3a5e5f | 3704 | rtx subst = get_equiv_with_elimination (loc, curr_insn); |
136e5c8e | 3705 | if (subst != loc) |
3706 | return subst; | |
3707 | ||
3708 | return NULL_RTX; | |
3709 | } | |
3710 | ||
c6a6cdaa | 3711 | /* Maximum number of generated reload insns per an insn. It is for |
3712 | preventing this pass cycling in a bug case. */ | |
3713 | #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS | |
3714 | ||
3715 | /* The current iteration number of this LRA pass. */ | |
3716 | int lra_constraint_iter; | |
3717 | ||
3718 | /* The current iteration number of this LRA pass after the last spill | |
3719 | pass. */ | |
3720 | int lra_constraint_iter_after_spill; | |
3721 | ||
3722 | /* True if we substituted equiv which needs checking register | |
3723 | allocation correctness because the equivalent value contains | |
3724 | allocatable hard registers or when we restore multi-register | |
3725 | pseudo. */ | |
3726 | bool lra_risky_transformations_p; | |
3727 | ||
3728 | /* Return true if REGNO is referenced in more than one block. */ | |
3729 | static bool | |
3730 | multi_block_pseudo_p (int regno) | |
3731 | { | |
3732 | basic_block bb = NULL; | |
3733 | unsigned int uid; | |
3734 | bitmap_iterator bi; | |
1a8f8886 | 3735 | |
c6a6cdaa | 3736 | if (regno < FIRST_PSEUDO_REGISTER) |
3737 | return false; | |
1a8f8886 | 3738 | |
c6a6cdaa | 3739 | EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi) |
3740 | if (bb == NULL) | |
3741 | bb = BLOCK_FOR_INSN (lra_insn_recog_data[uid]->insn); | |
3742 | else if (BLOCK_FOR_INSN (lra_insn_recog_data[uid]->insn) != bb) | |
3743 | return true; | |
3744 | return false; | |
3745 | } | |
3746 | ||
7a438292 | 3747 | /* Return true if LIST contains a deleted insn. */ |
3748 | static bool | |
3749 | contains_deleted_insn_p (rtx list) | |
3750 | { | |
3751 | for (; list != NULL_RTX; list = XEXP (list, 1)) | |
3752 | if (NOTE_P (XEXP (list, 0)) | |
3753 | && NOTE_KIND (XEXP (list, 0)) == NOTE_INSN_DELETED) | |
3754 | return true; | |
3755 | return false; | |
3756 | } | |
3757 | ||
c6a6cdaa | 3758 | /* Return true if X contains a pseudo dying in INSN. */ |
3759 | static bool | |
3760 | dead_pseudo_p (rtx x, rtx insn) | |
3761 | { | |
3762 | int i, j; | |
3763 | const char *fmt; | |
3764 | enum rtx_code code; | |
3765 | ||
3766 | if (REG_P (x)) | |
3767 | return (insn != NULL_RTX | |
3768 | && find_regno_note (insn, REG_DEAD, REGNO (x)) != NULL_RTX); | |
3769 | code = GET_CODE (x); | |
3770 | fmt = GET_RTX_FORMAT (code); | |
3771 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3772 | { | |
3773 | if (fmt[i] == 'e') | |
3774 | { | |
3775 | if (dead_pseudo_p (XEXP (x, i), insn)) | |
3776 | return true; | |
3777 | } | |
3778 | else if (fmt[i] == 'E') | |
3779 | { | |
3780 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
3781 | if (dead_pseudo_p (XVECEXP (x, i, j), insn)) | |
3782 | return true; | |
3783 | } | |
3784 | } | |
3785 | return false; | |
3786 | } | |
3787 | ||
3788 | /* Return true if INSN contains a dying pseudo in INSN right hand | |
3789 | side. */ | |
3790 | static bool | |
3791 | insn_rhs_dead_pseudo_p (rtx insn) | |
3792 | { | |
3793 | rtx set = single_set (insn); | |
3794 | ||
3795 | gcc_assert (set != NULL); | |
3796 | return dead_pseudo_p (SET_SRC (set), insn); | |
3797 | } | |
3798 | ||
3799 | /* Return true if any init insn of REGNO contains a dying pseudo in | |
3800 | insn right hand side. */ | |
3801 | static bool | |
3802 | init_insn_rhs_dead_pseudo_p (int regno) | |
3803 | { | |
3804 | rtx insns = ira_reg_equiv[regno].init_insns; | |
3805 | ||
3806 | if (insns == NULL) | |
3807 | return false; | |
3808 | if (INSN_P (insns)) | |
3809 | return insn_rhs_dead_pseudo_p (insns); | |
3810 | for (; insns != NULL_RTX; insns = XEXP (insns, 1)) | |
3811 | if (insn_rhs_dead_pseudo_p (XEXP (insns, 0))) | |
3812 | return true; | |
3813 | return false; | |
3814 | } | |
3815 | ||
691cfda4 | 3816 | /* Return TRUE if REGNO has a reverse equivalence. The equivalence is |
3817 | reverse only if we have one init insn with given REGNO as a | |
3818 | source. */ | |
3819 | static bool | |
3820 | reverse_equiv_p (int regno) | |
3821 | { | |
3822 | rtx insns, set; | |
3823 | ||
3824 | if ((insns = ira_reg_equiv[regno].init_insns) == NULL_RTX) | |
3825 | return false; | |
3826 | if (! INSN_P (XEXP (insns, 0)) | |
3827 | || XEXP (insns, 1) != NULL_RTX) | |
3828 | return false; | |
3829 | if ((set = single_set (XEXP (insns, 0))) == NULL_RTX) | |
3830 | return false; | |
3831 | return REG_P (SET_SRC (set)) && (int) REGNO (SET_SRC (set)) == regno; | |
3832 | } | |
3833 | ||
3834 | /* Return TRUE if REGNO was reloaded in an equivalence init insn. We | |
3835 | call this function only for non-reverse equivalence. */ | |
3836 | static bool | |
3837 | contains_reloaded_insn_p (int regno) | |
3838 | { | |
3839 | rtx set; | |
3840 | rtx list = ira_reg_equiv[regno].init_insns; | |
3841 | ||
3842 | for (; list != NULL_RTX; list = XEXP (list, 1)) | |
3843 | if ((set = single_set (XEXP (list, 0))) == NULL_RTX | |
3844 | || ! REG_P (SET_DEST (set)) | |
3845 | || (int) REGNO (SET_DEST (set)) != regno) | |
3846 | return true; | |
3847 | return false; | |
3848 | } | |
3849 | ||
c6a6cdaa | 3850 | /* Entry function of LRA constraint pass. Return true if the |
3851 | constraint pass did change the code. */ | |
3852 | bool | |
3853 | lra_constraints (bool first_p) | |
3854 | { | |
3855 | bool changed_p; | |
3856 | int i, hard_regno, new_insns_num; | |
f7b7100e | 3857 | unsigned int min_len, new_min_len, uid; |
3858 | rtx set, x, reg, dest_reg; | |
c6a6cdaa | 3859 | basic_block last_bb; |
f7b7100e | 3860 | bitmap_head equiv_insn_bitmap; |
3861 | bitmap_iterator bi; | |
c6a6cdaa | 3862 | |
3863 | lra_constraint_iter++; | |
3864 | if (lra_dump_file != NULL) | |
3865 | fprintf (lra_dump_file, "\n********** Local #%d: **********\n\n", | |
3866 | lra_constraint_iter); | |
3867 | lra_constraint_iter_after_spill++; | |
47f6add2 | 3868 | if (lra_constraint_iter_after_spill > LRA_MAX_CONSTRAINT_ITERATION_NUMBER) |
c6a6cdaa | 3869 | internal_error |
3870 | ("Maximum number of LRA constraint passes is achieved (%d)\n", | |
47f6add2 | 3871 | LRA_MAX_CONSTRAINT_ITERATION_NUMBER); |
c6a6cdaa | 3872 | changed_p = false; |
3873 | lra_risky_transformations_p = false; | |
3874 | new_insn_uid_start = get_max_uid (); | |
3875 | new_regno_start = first_p ? lra_constraint_new_regno_start : max_reg_num (); | |
3b3a5e5f | 3876 | /* Mark used hard regs for target stack size calulations. */ |
3877 | for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++) | |
3878 | if (lra_reg_info[i].nrefs != 0 | |
3879 | && (hard_regno = lra_get_regno_hard_regno (i)) >= 0) | |
3880 | { | |
3881 | int j, nregs; | |
3882 | ||
3883 | nregs = hard_regno_nregs[hard_regno][lra_reg_info[i].biggest_mode]; | |
3884 | for (j = 0; j < nregs; j++) | |
3885 | df_set_regs_ever_live (hard_regno + j, true); | |
3886 | } | |
3887 | /* Do elimination before the equivalence processing as we can spill | |
3888 | some pseudos during elimination. */ | |
3889 | lra_eliminate (false, first_p); | |
f7b7100e | 3890 | bitmap_initialize (&equiv_insn_bitmap, ®_obstack); |
c6a6cdaa | 3891 | for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++) |
3892 | if (lra_reg_info[i].nrefs != 0) | |
3893 | { | |
3894 | ira_reg_equiv[i].profitable_p = true; | |
f7b7100e | 3895 | reg = regno_reg_rtx[i]; |
3b3a5e5f | 3896 | if (lra_get_regno_hard_regno (i) < 0 && (x = get_equiv (reg)) != reg) |
c6a6cdaa | 3897 | { |
3898 | bool pseudo_p = contains_reg_p (x, false, false); | |
c6a6cdaa | 3899 | |
7a438292 | 3900 | /* After RTL transformation, we can not guarantee that |
3901 | pseudo in the substitution was not reloaded which might | |
3902 | make equivalence invalid. For example, in reverse | |
3903 | equiv of p0 | |
3904 | ||
3905 | p0 <- ... | |
3906 | ... | |
3907 | equiv_mem <- p0 | |
3908 | ||
3909 | the memory address register was reloaded before the 2nd | |
3910 | insn. */ | |
3911 | if ((! first_p && pseudo_p) | |
3912 | /* We don't use DF for compilation speed sake. So it | |
3913 | is problematic to update live info when we use an | |
3914 | equivalence containing pseudos in more than one | |
3915 | BB. */ | |
3916 | || (pseudo_p && multi_block_pseudo_p (i)) | |
3917 | /* If an init insn was deleted for some reason, cancel | |
3918 | the equiv. We could update the equiv insns after | |
3919 | transformations including an equiv insn deletion | |
3920 | but it is not worthy as such cases are extremely | |
3921 | rare. */ | |
3922 | || contains_deleted_insn_p (ira_reg_equiv[i].init_insns) | |
c6a6cdaa | 3923 | /* If it is not a reverse equivalence, we check that a |
3924 | pseudo in rhs of the init insn is not dying in the | |
3925 | insn. Otherwise, the live info at the beginning of | |
3926 | the corresponding BB might be wrong after we | |
3927 | removed the insn. When the equiv can be a | |
3928 | constant, the right hand side of the init insn can | |
3929 | be a pseudo. */ | |
691cfda4 | 3930 | || (! reverse_equiv_p (i) |
3931 | && (init_insn_rhs_dead_pseudo_p (i) | |
3932 | /* If we reloaded the pseudo in an equivalence | |
3933 | init insn, we can not remove the equiv init | |
3934 | insns and the init insns might write into | |
3935 | const memory in this case. */ | |
3936 | || contains_reloaded_insn_p (i))) | |
fc8a0f60 | 3937 | /* Prevent access beyond equivalent memory for |
3938 | paradoxical subregs. */ | |
3939 | || (MEM_P (x) | |
3940 | && (GET_MODE_SIZE (lra_reg_info[i].biggest_mode) | |
3941 | > GET_MODE_SIZE (GET_MODE (x))))) | |
c6a6cdaa | 3942 | ira_reg_equiv[i].defined_p = false; |
c6a6cdaa | 3943 | if (contains_reg_p (x, false, true)) |
3944 | ira_reg_equiv[i].profitable_p = false; | |
3b3a5e5f | 3945 | if (get_equiv (reg) != reg) |
f7b7100e | 3946 | bitmap_ior_into (&equiv_insn_bitmap, &lra_reg_info[i].insn_bitmap); |
c6a6cdaa | 3947 | } |
3948 | } | |
f7b7100e | 3949 | /* We should add all insns containing pseudos which should be |
3950 | substituted by their equivalences. */ | |
3951 | EXECUTE_IF_SET_IN_BITMAP (&equiv_insn_bitmap, 0, uid, bi) | |
3952 | lra_push_insn_by_uid (uid); | |
c6a6cdaa | 3953 | min_len = lra_insn_stack_length (); |
3954 | new_insns_num = 0; | |
3955 | last_bb = NULL; | |
3956 | changed_p = false; | |
3957 | while ((new_min_len = lra_insn_stack_length ()) != 0) | |
3958 | { | |
3959 | curr_insn = lra_pop_insn (); | |
3960 | --new_min_len; | |
1a8f8886 | 3961 | curr_bb = BLOCK_FOR_INSN (curr_insn); |
c6a6cdaa | 3962 | if (curr_bb != last_bb) |
3963 | { | |
3964 | last_bb = curr_bb; | |
3965 | bb_reload_num = lra_curr_reload_num; | |
3966 | } | |
3967 | if (min_len > new_min_len) | |
3968 | { | |
3969 | min_len = new_min_len; | |
3970 | new_insns_num = 0; | |
3971 | } | |
3972 | if (new_insns_num > MAX_RELOAD_INSNS_NUMBER) | |
3973 | internal_error | |
3974 | ("Max. number of generated reload insns per insn is achieved (%d)\n", | |
3975 | MAX_RELOAD_INSNS_NUMBER); | |
3976 | new_insns_num++; | |
3977 | if (DEBUG_INSN_P (curr_insn)) | |
3978 | { | |
3979 | /* We need to check equivalence in debug insn and change | |
3980 | pseudo to the equivalent value if necessary. */ | |
3981 | curr_id = lra_get_insn_recog_data (curr_insn); | |
136e5c8e | 3982 | if (bitmap_bit_p (&equiv_insn_bitmap, INSN_UID (curr_insn))) |
e717b69a | 3983 | { |
136e5c8e | 3984 | rtx old = *curr_id->operand_loc[0]; |
3985 | *curr_id->operand_loc[0] | |
3986 | = simplify_replace_fn_rtx (old, NULL_RTX, | |
3987 | loc_equivalence_callback, NULL); | |
3988 | if (old != *curr_id->operand_loc[0]) | |
3989 | { | |
3990 | lra_update_insn_regno_info (curr_insn); | |
3991 | changed_p = true; | |
3992 | } | |
e717b69a | 3993 | } |
c6a6cdaa | 3994 | } |
3995 | else if (INSN_P (curr_insn)) | |
3996 | { | |
3997 | if ((set = single_set (curr_insn)) != NULL_RTX) | |
3998 | { | |
3999 | dest_reg = SET_DEST (set); | |
4000 | /* The equivalence pseudo could be set up as SUBREG in a | |
4001 | case when it is a call restore insn in a mode | |
4002 | different from the pseudo mode. */ | |
4003 | if (GET_CODE (dest_reg) == SUBREG) | |
4004 | dest_reg = SUBREG_REG (dest_reg); | |
4005 | if ((REG_P (dest_reg) | |
3b3a5e5f | 4006 | && (x = get_equiv (dest_reg)) != dest_reg |
c6a6cdaa | 4007 | /* Remove insns which set up a pseudo whose value |
4008 | can not be changed. Such insns might be not in | |
4009 | init_insns because we don't update equiv data | |
4010 | during insn transformations. | |
c625778b | 4011 | |
c6a6cdaa | 4012 | As an example, let suppose that a pseudo got |
4013 | hard register and on the 1st pass was not | |
4014 | changed to equivalent constant. We generate an | |
4015 | additional insn setting up the pseudo because of | |
4016 | secondary memory movement. Then the pseudo is | |
4017 | spilled and we use the equiv constant. In this | |
4018 | case we should remove the additional insn and | |
e454a550 | 4019 | this insn is not init_insns list. */ |
c6a6cdaa | 4020 | && (! MEM_P (x) || MEM_READONLY_P (x) |
e454a550 | 4021 | /* Check that this is actually an insn setting |
4022 | up the equivalence. */ | |
c6a6cdaa | 4023 | || in_list_p (curr_insn, |
4024 | ira_reg_equiv | |
4025 | [REGNO (dest_reg)].init_insns))) | |
3b3a5e5f | 4026 | || (((x = get_equiv (SET_SRC (set))) != SET_SRC (set)) |
c6a6cdaa | 4027 | && in_list_p (curr_insn, |
4028 | ira_reg_equiv | |
4029 | [REGNO (SET_SRC (set))].init_insns))) | |
4030 | { | |
4031 | /* This is equiv init insn of pseudo which did not get a | |
4032 | hard register -- remove the insn. */ | |
4033 | if (lra_dump_file != NULL) | |
4034 | { | |
4035 | fprintf (lra_dump_file, | |
4036 | " Removing equiv init insn %i (freq=%d)\n", | |
4037 | INSN_UID (curr_insn), | |
4038 | BLOCK_FOR_INSN (curr_insn)->frequency); | |
6dde9719 | 4039 | dump_insn_slim (lra_dump_file, curr_insn); |
c6a6cdaa | 4040 | } |
4041 | if (contains_reg_p (x, true, false)) | |
4042 | lra_risky_transformations_p = true; | |
4043 | lra_set_insn_deleted (curr_insn); | |
4044 | continue; | |
4045 | } | |
4046 | } | |
4047 | curr_id = lra_get_insn_recog_data (curr_insn); | |
4048 | curr_static_id = curr_id->insn_static_data; | |
4049 | init_curr_insn_input_reloads (); | |
4050 | init_curr_operand_mode (); | |
4051 | if (curr_insn_transform ()) | |
4052 | changed_p = true; | |
d596f8db | 4053 | /* Check non-transformed insns too for equiv change as USE |
4054 | or CLOBBER don't need reloads but can contain pseudos | |
4055 | being changed on their equivalences. */ | |
4056 | else if (bitmap_bit_p (&equiv_insn_bitmap, INSN_UID (curr_insn)) | |
4057 | && loc_equivalence_change_p (&PATTERN (curr_insn))) | |
4058 | { | |
4059 | lra_update_insn_regno_info (curr_insn); | |
4060 | changed_p = true; | |
4061 | } | |
c6a6cdaa | 4062 | } |
4063 | } | |
d596f8db | 4064 | bitmap_clear (&equiv_insn_bitmap); |
c6a6cdaa | 4065 | /* If we used a new hard regno, changed_p should be true because the |
4066 | hard reg is assigned to a new pseudo. */ | |
4067 | #ifdef ENABLE_CHECKING | |
4068 | if (! changed_p) | |
4069 | { | |
4070 | for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++) | |
4071 | if (lra_reg_info[i].nrefs != 0 | |
4072 | && (hard_regno = lra_get_regno_hard_regno (i)) >= 0) | |
4073 | { | |
4074 | int j, nregs = hard_regno_nregs[hard_regno][PSEUDO_REGNO_MODE (i)]; | |
1a8f8886 | 4075 | |
c6a6cdaa | 4076 | for (j = 0; j < nregs; j++) |
4077 | lra_assert (df_regs_ever_live_p (hard_regno + j)); | |
4078 | } | |
4079 | } | |
4080 | #endif | |
4081 | return changed_p; | |
4082 | } | |
4083 | ||
4084 | /* Initiate the LRA constraint pass. It is done once per | |
4085 | function. */ | |
4086 | void | |
4087 | lra_constraints_init (void) | |
4088 | { | |
4089 | } | |
4090 | ||
4091 | /* Finalize the LRA constraint pass. It is done once per | |
4092 | function. */ | |
4093 | void | |
4094 | lra_constraints_finish (void) | |
4095 | { | |
4096 | } | |
4097 | ||
4098 | \f | |
4099 | ||
4100 | /* This page contains code to do inheritance/split | |
4101 | transformations. */ | |
4102 | ||
4103 | /* Number of reloads passed so far in current EBB. */ | |
4104 | static int reloads_num; | |
4105 | ||
4106 | /* Number of calls passed so far in current EBB. */ | |
4107 | static int calls_num; | |
4108 | ||
4109 | /* Current reload pseudo check for validity of elements in | |
4110 | USAGE_INSNS. */ | |
4111 | static int curr_usage_insns_check; | |
4112 | ||
4113 | /* Info about last usage of registers in EBB to do inheritance/split | |
4114 | transformation. Inheritance transformation is done from a spilled | |
4115 | pseudo and split transformations from a hard register or a pseudo | |
4116 | assigned to a hard register. */ | |
4117 | struct usage_insns | |
4118 | { | |
4119 | /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member | |
4120 | value INSNS is valid. The insns is chain of optional debug insns | |
cc0dc61b | 4121 | and a finishing non-debug insn using the corresponding reg. The |
4122 | value is also used to mark the registers which are set up in the | |
4123 | current insn. The negated insn uid is used for this. */ | |
c6a6cdaa | 4124 | int check; |
4125 | /* Value of global reloads_num at the last insn in INSNS. */ | |
4126 | int reloads_num; | |
4127 | /* Value of global reloads_nums at the last insn in INSNS. */ | |
4128 | int calls_num; | |
4129 | /* It can be true only for splitting. And it means that the restore | |
4130 | insn should be put after insn given by the following member. */ | |
4131 | bool after_p; | |
4132 | /* Next insns in the current EBB which use the original reg and the | |
4133 | original reg value is not changed between the current insn and | |
4134 | the next insns. In order words, e.g. for inheritance, if we need | |
4135 | to use the original reg value again in the next insns we can try | |
4136 | to use the value in a hard register from a reload insn of the | |
4137 | current insn. */ | |
4138 | rtx insns; | |
4139 | }; | |
4140 | ||
4141 | /* Map: regno -> corresponding pseudo usage insns. */ | |
4142 | static struct usage_insns *usage_insns; | |
4143 | ||
4144 | static void | |
4145 | setup_next_usage_insn (int regno, rtx insn, int reloads_num, bool after_p) | |
4146 | { | |
4147 | usage_insns[regno].check = curr_usage_insns_check; | |
4148 | usage_insns[regno].insns = insn; | |
4149 | usage_insns[regno].reloads_num = reloads_num; | |
4150 | usage_insns[regno].calls_num = calls_num; | |
4151 | usage_insns[regno].after_p = after_p; | |
4152 | } | |
4153 | ||
4154 | /* The function is used to form list REGNO usages which consists of | |
4155 | optional debug insns finished by a non-debug insn using REGNO. | |
4156 | RELOADS_NUM is current number of reload insns processed so far. */ | |
4157 | static void | |
4158 | add_next_usage_insn (int regno, rtx insn, int reloads_num) | |
4159 | { | |
4160 | rtx next_usage_insns; | |
1a8f8886 | 4161 | |
c6a6cdaa | 4162 | if (usage_insns[regno].check == curr_usage_insns_check |
4163 | && (next_usage_insns = usage_insns[regno].insns) != NULL_RTX | |
4164 | && DEBUG_INSN_P (insn)) | |
4165 | { | |
4166 | /* Check that we did not add the debug insn yet. */ | |
4167 | if (next_usage_insns != insn | |
4168 | && (GET_CODE (next_usage_insns) != INSN_LIST | |
4169 | || XEXP (next_usage_insns, 0) != insn)) | |
4170 | usage_insns[regno].insns = gen_rtx_INSN_LIST (VOIDmode, insn, | |
4171 | next_usage_insns); | |
4172 | } | |
4173 | else if (NONDEBUG_INSN_P (insn)) | |
4174 | setup_next_usage_insn (regno, insn, reloads_num, false); | |
4175 | else | |
4176 | usage_insns[regno].check = 0; | |
4177 | } | |
1a8f8886 | 4178 | |
c6a6cdaa | 4179 | /* Replace all references to register OLD_REGNO in *LOC with pseudo |
4180 | register NEW_REG. Return true if any change was made. */ | |
4181 | static bool | |
4182 | substitute_pseudo (rtx *loc, int old_regno, rtx new_reg) | |
4183 | { | |
4184 | rtx x = *loc; | |
4185 | bool result = false; | |
4186 | enum rtx_code code; | |
4187 | const char *fmt; | |
4188 | int i, j; | |
4189 | ||
4190 | if (x == NULL_RTX) | |
4191 | return false; | |
4192 | ||
4193 | code = GET_CODE (x); | |
4194 | if (code == REG && (int) REGNO (x) == old_regno) | |
4195 | { | |
4196 | enum machine_mode mode = GET_MODE (*loc); | |
4197 | enum machine_mode inner_mode = GET_MODE (new_reg); | |
4198 | ||
4199 | if (mode != inner_mode) | |
4200 | { | |
4201 | if (GET_MODE_SIZE (mode) >= GET_MODE_SIZE (inner_mode) | |
4202 | || ! SCALAR_INT_MODE_P (inner_mode)) | |
4203 | new_reg = gen_rtx_SUBREG (mode, new_reg, 0); | |
4204 | else | |
4205 | new_reg = gen_lowpart_SUBREG (mode, new_reg); | |
4206 | } | |
4207 | *loc = new_reg; | |
4208 | return true; | |
4209 | } | |
4210 | ||
4211 | /* Scan all the operand sub-expressions. */ | |
4212 | fmt = GET_RTX_FORMAT (code); | |
4213 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
4214 | { | |
4215 | if (fmt[i] == 'e') | |
4216 | { | |
4217 | if (substitute_pseudo (&XEXP (x, i), old_regno, new_reg)) | |
4218 | result = true; | |
4219 | } | |
4220 | else if (fmt[i] == 'E') | |
4221 | { | |
4222 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
4223 | if (substitute_pseudo (&XVECEXP (x, i, j), old_regno, new_reg)) | |
4224 | result = true; | |
4225 | } | |
4226 | } | |
4227 | return result; | |
4228 | } | |
4229 | ||
5bb0e0fd | 4230 | /* Return first non-debug insn in list USAGE_INSNS. */ |
4231 | static rtx | |
4232 | skip_usage_debug_insns (rtx usage_insns) | |
4233 | { | |
4234 | rtx insn; | |
4235 | ||
4236 | /* Skip debug insns. */ | |
4237 | for (insn = usage_insns; | |
4238 | insn != NULL_RTX && GET_CODE (insn) == INSN_LIST; | |
4239 | insn = XEXP (insn, 1)) | |
4240 | ; | |
4241 | return insn; | |
4242 | } | |
4243 | ||
4244 | /* Return true if we need secondary memory moves for insn in | |
4245 | USAGE_INSNS after inserting inherited pseudo of class INHER_CL | |
4246 | into the insn. */ | |
4247 | static bool | |
acb7fe1f | 4248 | check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED, |
4249 | rtx usage_insns ATTRIBUTE_UNUSED) | |
5bb0e0fd | 4250 | { |
4251 | #ifndef SECONDARY_MEMORY_NEEDED | |
4252 | return false; | |
4253 | #else | |
4254 | rtx insn, set, dest; | |
4255 | enum reg_class cl; | |
4256 | ||
4257 | if (inher_cl == ALL_REGS | |
4258 | || (insn = skip_usage_debug_insns (usage_insns)) == NULL_RTX) | |
4259 | return false; | |
4260 | lra_assert (INSN_P (insn)); | |
4261 | if ((set = single_set (insn)) == NULL_RTX || ! REG_P (SET_DEST (set))) | |
4262 | return false; | |
4263 | dest = SET_DEST (set); | |
4264 | if (! REG_P (dest)) | |
4265 | return false; | |
4266 | lra_assert (inher_cl != NO_REGS); | |
4267 | cl = get_reg_class (REGNO (dest)); | |
4268 | return (cl != NO_REGS && cl != ALL_REGS | |
4269 | && SECONDARY_MEMORY_NEEDED (inher_cl, cl, GET_MODE (dest))); | |
4270 | #endif | |
4271 | } | |
4272 | ||
c6a6cdaa | 4273 | /* Registers involved in inheritance/split in the current EBB |
4274 | (inheritance/split pseudos and original registers). */ | |
4275 | static bitmap_head check_only_regs; | |
4276 | ||
4277 | /* Do inheritance transformations for insn INSN, which defines (if | |
4278 | DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which | |
4279 | instruction in the EBB next uses ORIGINAL_REGNO; it has the same | |
4280 | form as the "insns" field of usage_insns. Return true if we | |
4281 | succeed in such transformation. | |
4282 | ||
4283 | The transformations look like: | |
4284 | ||
4285 | p <- ... i <- ... | |
4286 | ... p <- i (new insn) | |
4287 | ... => | |
4288 | <- ... p ... <- ... i ... | |
4289 | or | |
4290 | ... i <- p (new insn) | |
4291 | <- ... p ... <- ... i ... | |
4292 | ... => | |
4293 | <- ... p ... <- ... i ... | |
4294 | where p is a spilled original pseudo and i is a new inheritance pseudo. | |
1a8f8886 | 4295 | |
4296 | ||
c6a6cdaa | 4297 | The inheritance pseudo has the smallest class of two classes CL and |
4298 | class of ORIGINAL REGNO. */ | |
4299 | static bool | |
4300 | inherit_reload_reg (bool def_p, int original_regno, | |
4301 | enum reg_class cl, rtx insn, rtx next_usage_insns) | |
4302 | { | |
4303 | enum reg_class rclass = lra_get_allocno_class (original_regno); | |
4304 | rtx original_reg = regno_reg_rtx[original_regno]; | |
4305 | rtx new_reg, new_insns, usage_insn; | |
4306 | ||
4307 | lra_assert (! usage_insns[original_regno].after_p); | |
4308 | if (lra_dump_file != NULL) | |
4309 | fprintf (lra_dump_file, | |
5bb0e0fd | 4310 | " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n"); |
c6a6cdaa | 4311 | if (! ira_reg_classes_intersect_p[cl][rclass]) |
4312 | { | |
4313 | if (lra_dump_file != NULL) | |
4314 | { | |
4315 | fprintf (lra_dump_file, | |
5bb0e0fd | 4316 | " Rejecting inheritance for %d " |
c6a6cdaa | 4317 | "because of disjoint classes %s and %s\n", |
4318 | original_regno, reg_class_names[cl], | |
4319 | reg_class_names[rclass]); | |
4320 | fprintf (lra_dump_file, | |
5bb0e0fd | 4321 | " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); |
c6a6cdaa | 4322 | } |
4323 | return false; | |
4324 | } | |
4325 | if ((ira_class_subset_p[cl][rclass] && cl != rclass) | |
4326 | /* We don't use a subset of two classes because it can be | |
4327 | NO_REGS. This transformation is still profitable in most | |
4328 | cases even if the classes are not intersected as register | |
4329 | move is probably cheaper than a memory load. */ | |
4330 | || ira_class_hard_regs_num[cl] < ira_class_hard_regs_num[rclass]) | |
4331 | { | |
4332 | if (lra_dump_file != NULL) | |
4333 | fprintf (lra_dump_file, " Use smallest class of %s and %s\n", | |
4334 | reg_class_names[cl], reg_class_names[rclass]); | |
1a8f8886 | 4335 | |
c6a6cdaa | 4336 | rclass = cl; |
4337 | } | |
c47331e3 | 4338 | if (check_secondary_memory_needed_p (rclass, next_usage_insns)) |
5bb0e0fd | 4339 | { |
4340 | /* Reject inheritance resulting in secondary memory moves. | |
4341 | Otherwise, there is a danger in LRA cycling. Also such | |
4342 | transformation will be unprofitable. */ | |
4343 | if (lra_dump_file != NULL) | |
4344 | { | |
4345 | rtx insn = skip_usage_debug_insns (next_usage_insns); | |
4346 | rtx set = single_set (insn); | |
4347 | ||
4348 | lra_assert (set != NULL_RTX); | |
4349 | ||
4350 | rtx dest = SET_DEST (set); | |
4351 | ||
4352 | lra_assert (REG_P (dest)); | |
4353 | fprintf (lra_dump_file, | |
4354 | " Rejecting inheritance for insn %d(%s)<-%d(%s) " | |
4355 | "as secondary mem is needed\n", | |
4356 | REGNO (dest), reg_class_names[get_reg_class (REGNO (dest))], | |
c47331e3 | 4357 | original_regno, reg_class_names[rclass]); |
5bb0e0fd | 4358 | fprintf (lra_dump_file, |
4359 | " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); | |
4360 | } | |
4361 | return false; | |
4362 | } | |
c6a6cdaa | 4363 | new_reg = lra_create_new_reg (GET_MODE (original_reg), original_reg, |
4364 | rclass, "inheritance"); | |
4365 | start_sequence (); | |
4366 | if (def_p) | |
4367 | emit_move_insn (original_reg, new_reg); | |
4368 | else | |
4369 | emit_move_insn (new_reg, original_reg); | |
4370 | new_insns = get_insns (); | |
4371 | end_sequence (); | |
4372 | if (NEXT_INSN (new_insns) != NULL_RTX) | |
4373 | { | |
4374 | if (lra_dump_file != NULL) | |
4375 | { | |
4376 | fprintf (lra_dump_file, | |
5bb0e0fd | 4377 | " Rejecting inheritance %d->%d " |
c6a6cdaa | 4378 | "as it results in 2 or more insns:\n", |
4379 | original_regno, REGNO (new_reg)); | |
6dde9719 | 4380 | dump_rtl_slim (lra_dump_file, new_insns, NULL_RTX, -1, 0); |
c6a6cdaa | 4381 | fprintf (lra_dump_file, |
4382 | " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); | |
4383 | } | |
4384 | return false; | |
4385 | } | |
4386 | substitute_pseudo (&insn, original_regno, new_reg); | |
4387 | lra_update_insn_regno_info (insn); | |
4388 | if (! def_p) | |
4389 | /* We now have a new usage insn for original regno. */ | |
4390 | setup_next_usage_insn (original_regno, new_insns, reloads_num, false); | |
4391 | if (lra_dump_file != NULL) | |
5bb0e0fd | 4392 | fprintf (lra_dump_file, " Original reg change %d->%d (bb%d):\n", |
c6a6cdaa | 4393 | original_regno, REGNO (new_reg), BLOCK_FOR_INSN (insn)->index); |
4394 | lra_reg_info[REGNO (new_reg)].restore_regno = original_regno; | |
4395 | bitmap_set_bit (&check_only_regs, REGNO (new_reg)); | |
4396 | bitmap_set_bit (&check_only_regs, original_regno); | |
4397 | bitmap_set_bit (&lra_inheritance_pseudos, REGNO (new_reg)); | |
4398 | if (def_p) | |
4399 | lra_process_new_insns (insn, NULL_RTX, new_insns, | |
4400 | "Add original<-inheritance"); | |
4401 | else | |
4402 | lra_process_new_insns (insn, new_insns, NULL_RTX, | |
4403 | "Add inheritance<-original"); | |
4404 | while (next_usage_insns != NULL_RTX) | |
4405 | { | |
4406 | if (GET_CODE (next_usage_insns) != INSN_LIST) | |
4407 | { | |
4408 | usage_insn = next_usage_insns; | |
4409 | lra_assert (NONDEBUG_INSN_P (usage_insn)); | |
4410 | next_usage_insns = NULL; | |
4411 | } | |
4412 | else | |
4413 | { | |
4414 | usage_insn = XEXP (next_usage_insns, 0); | |
4415 | lra_assert (DEBUG_INSN_P (usage_insn)); | |
4416 | next_usage_insns = XEXP (next_usage_insns, 1); | |
4417 | } | |
4418 | substitute_pseudo (&usage_insn, original_regno, new_reg); | |
4419 | lra_update_insn_regno_info (usage_insn); | |
4420 | if (lra_dump_file != NULL) | |
4421 | { | |
4422 | fprintf (lra_dump_file, | |
4423 | " Inheritance reuse change %d->%d (bb%d):\n", | |
4424 | original_regno, REGNO (new_reg), | |
4425 | BLOCK_FOR_INSN (usage_insn)->index); | |
6dde9719 | 4426 | dump_insn_slim (lra_dump_file, usage_insn); |
c6a6cdaa | 4427 | } |
4428 | } | |
4429 | if (lra_dump_file != NULL) | |
4430 | fprintf (lra_dump_file, | |
4431 | " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); | |
4432 | return true; | |
4433 | } | |
4434 | ||
4435 | /* Return true if we need a caller save/restore for pseudo REGNO which | |
4436 | was assigned to a hard register. */ | |
4437 | static inline bool | |
4438 | need_for_call_save_p (int regno) | |
4439 | { | |
4440 | lra_assert (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] >= 0); | |
4441 | return (usage_insns[regno].calls_num < calls_num | |
4442 | && (overlaps_hard_reg_set_p | |
4443 | (call_used_reg_set, | |
a766a8b0 | 4444 | PSEUDO_REGNO_MODE (regno), reg_renumber[regno]) |
4445 | || HARD_REGNO_CALL_PART_CLOBBERED (reg_renumber[regno], | |
4446 | PSEUDO_REGNO_MODE (regno)))); | |
c6a6cdaa | 4447 | } |
4448 | ||
75de4aa2 | 4449 | /* Global registers occurring in the current EBB. */ |
c6a6cdaa | 4450 | static bitmap_head ebb_global_regs; |
4451 | ||
4452 | /* Return true if we need a split for hard register REGNO or pseudo | |
4453 | REGNO which was assigned to a hard register. | |
4454 | POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be | |
4455 | used for reloads since the EBB end. It is an approximation of the | |
4456 | used hard registers in the split range. The exact value would | |
4457 | require expensive calculations. If we were aggressive with | |
4458 | splitting because of the approximation, the split pseudo will save | |
4459 | the same hard register assignment and will be removed in the undo | |
4460 | pass. We still need the approximation because too aggressive | |
4461 | splitting would result in too inaccurate cost calculation in the | |
4462 | assignment pass because of too many generated moves which will be | |
4463 | probably removed in the undo pass. */ | |
4464 | static inline bool | |
4465 | need_for_split_p (HARD_REG_SET potential_reload_hard_regs, int regno) | |
4466 | { | |
4467 | int hard_regno = regno < FIRST_PSEUDO_REGISTER ? regno : reg_renumber[regno]; | |
4468 | ||
4469 | lra_assert (hard_regno >= 0); | |
4470 | return ((TEST_HARD_REG_BIT (potential_reload_hard_regs, hard_regno) | |
4471 | /* Don't split eliminable hard registers, otherwise we can | |
4472 | split hard registers like hard frame pointer, which | |
4473 | lives on BB start/end according to DF-infrastructure, | |
4474 | when there is a pseudo assigned to the register and | |
4475 | living in the same BB. */ | |
4476 | && (regno >= FIRST_PSEUDO_REGISTER | |
4477 | || ! TEST_HARD_REG_BIT (eliminable_regset, hard_regno)) | |
4478 | && ! TEST_HARD_REG_BIT (lra_no_alloc_regs, hard_regno) | |
0157439c | 4479 | /* Don't split call clobbered hard regs living through |
4480 | calls, otherwise we might have a check problem in the | |
4481 | assign sub-pass as in the most cases (exception is a | |
4482 | situation when lra_risky_transformations_p value is | |
4483 | true) the assign pass assumes that all pseudos living | |
4484 | through calls are assigned to call saved hard regs. */ | |
4485 | && (regno >= FIRST_PSEUDO_REGISTER | |
4486 | || ! TEST_HARD_REG_BIT (call_used_reg_set, regno) | |
4487 | || usage_insns[regno].calls_num == calls_num) | |
c6a6cdaa | 4488 | /* We need at least 2 reloads to make pseudo splitting |
4489 | profitable. We should provide hard regno splitting in | |
4490 | any case to solve 1st insn scheduling problem when | |
4491 | moving hard register definition up might result in | |
4492 | impossibility to find hard register for reload pseudo of | |
4493 | small register class. */ | |
4494 | && (usage_insns[regno].reloads_num | |
4495 | + (regno < FIRST_PSEUDO_REGISTER ? 0 : 2) < reloads_num) | |
4496 | && (regno < FIRST_PSEUDO_REGISTER | |
4497 | /* For short living pseudos, spilling + inheritance can | |
4498 | be considered a substitution for splitting. | |
4499 | Therefore we do not splitting for local pseudos. It | |
4500 | decreases also aggressiveness of splitting. The | |
4501 | minimal number of references is chosen taking into | |
4502 | account that for 2 references splitting has no sense | |
4503 | as we can just spill the pseudo. */ | |
4504 | || (regno >= FIRST_PSEUDO_REGISTER | |
4505 | && lra_reg_info[regno].nrefs > 3 | |
4506 | && bitmap_bit_p (&ebb_global_regs, regno)))) | |
4507 | || (regno >= FIRST_PSEUDO_REGISTER && need_for_call_save_p (regno))); | |
4508 | } | |
4509 | ||
4510 | /* Return class for the split pseudo created from original pseudo with | |
4511 | ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We | |
4512 | choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and | |
4513 | results in no secondary memory movements. */ | |
4514 | static enum reg_class | |
4515 | choose_split_class (enum reg_class allocno_class, | |
4516 | int hard_regno ATTRIBUTE_UNUSED, | |
4517 | enum machine_mode mode ATTRIBUTE_UNUSED) | |
4518 | { | |
4519 | #ifndef SECONDARY_MEMORY_NEEDED | |
4520 | return allocno_class; | |
4521 | #else | |
4522 | int i; | |
4523 | enum reg_class cl, best_cl = NO_REGS; | |
d810a474 | 4524 | enum reg_class hard_reg_class ATTRIBUTE_UNUSED |
4525 | = REGNO_REG_CLASS (hard_regno); | |
1a8f8886 | 4526 | |
c6a6cdaa | 4527 | if (! SECONDARY_MEMORY_NEEDED (allocno_class, allocno_class, mode) |
4528 | && TEST_HARD_REG_BIT (reg_class_contents[allocno_class], hard_regno)) | |
4529 | return allocno_class; | |
4530 | for (i = 0; | |
4531 | (cl = reg_class_subclasses[allocno_class][i]) != LIM_REG_CLASSES; | |
4532 | i++) | |
4533 | if (! SECONDARY_MEMORY_NEEDED (cl, hard_reg_class, mode) | |
4534 | && ! SECONDARY_MEMORY_NEEDED (hard_reg_class, cl, mode) | |
4535 | && TEST_HARD_REG_BIT (reg_class_contents[cl], hard_regno) | |
4536 | && (best_cl == NO_REGS | |
4537 | || ira_class_hard_regs_num[best_cl] < ira_class_hard_regs_num[cl])) | |
4538 | best_cl = cl; | |
4539 | return best_cl; | |
4540 | #endif | |
4541 | } | |
4542 | ||
4543 | /* Do split transformations for insn INSN, which defines or uses | |
4544 | ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in | |
4545 | the EBB next uses ORIGINAL_REGNO; it has the same form as the | |
4546 | "insns" field of usage_insns. | |
4547 | ||
4548 | The transformations look like: | |
4549 | ||
4550 | p <- ... p <- ... | |
4551 | ... s <- p (new insn -- save) | |
4552 | ... => | |
4553 | ... p <- s (new insn -- restore) | |
4554 | <- ... p ... <- ... p ... | |
4555 | or | |
4556 | <- ... p ... <- ... p ... | |
4557 | ... s <- p (new insn -- save) | |
4558 | ... => | |
4559 | ... p <- s (new insn -- restore) | |
4560 | <- ... p ... <- ... p ... | |
4561 | ||
4562 | where p is an original pseudo got a hard register or a hard | |
4563 | register and s is a new split pseudo. The save is put before INSN | |
4564 | if BEFORE_P is true. Return true if we succeed in such | |
4565 | transformation. */ | |
4566 | static bool | |
4567 | split_reg (bool before_p, int original_regno, rtx insn, rtx next_usage_insns) | |
4568 | { | |
4569 | enum reg_class rclass; | |
4570 | rtx original_reg; | |
74855d08 | 4571 | int hard_regno, nregs; |
c6a6cdaa | 4572 | rtx new_reg, save, restore, usage_insn; |
4573 | bool after_p; | |
4574 | bool call_save_p; | |
4575 | ||
4576 | if (original_regno < FIRST_PSEUDO_REGISTER) | |
4577 | { | |
4578 | rclass = ira_allocno_class_translate[REGNO_REG_CLASS (original_regno)]; | |
4579 | hard_regno = original_regno; | |
4580 | call_save_p = false; | |
74855d08 | 4581 | nregs = 1; |
c6a6cdaa | 4582 | } |
4583 | else | |
4584 | { | |
4585 | hard_regno = reg_renumber[original_regno]; | |
74855d08 | 4586 | nregs = hard_regno_nregs[hard_regno][PSEUDO_REGNO_MODE (original_regno)]; |
c6a6cdaa | 4587 | rclass = lra_get_allocno_class (original_regno); |
4588 | original_reg = regno_reg_rtx[original_regno]; | |
4589 | call_save_p = need_for_call_save_p (original_regno); | |
4590 | } | |
4591 | original_reg = regno_reg_rtx[original_regno]; | |
4592 | lra_assert (hard_regno >= 0); | |
4593 | if (lra_dump_file != NULL) | |
4594 | fprintf (lra_dump_file, | |
4595 | " ((((((((((((((((((((((((((((((((((((((((((((((((\n"); | |
4596 | if (call_save_p) | |
4597 | { | |
34575461 | 4598 | enum machine_mode mode = GET_MODE (original_reg); |
1a8f8886 | 4599 | |
34575461 | 4600 | mode = HARD_REGNO_CALLER_SAVE_MODE (hard_regno, |
4601 | hard_regno_nregs[hard_regno][mode], | |
4602 | mode); | |
4603 | new_reg = lra_create_new_reg (mode, NULL_RTX, NO_REGS, "save"); | |
c6a6cdaa | 4604 | } |
4605 | else | |
4606 | { | |
4607 | rclass = choose_split_class (rclass, hard_regno, | |
4608 | GET_MODE (original_reg)); | |
4609 | if (rclass == NO_REGS) | |
4610 | { | |
4611 | if (lra_dump_file != NULL) | |
4612 | { | |
4613 | fprintf (lra_dump_file, | |
4614 | " Rejecting split of %d(%s): " | |
4615 | "no good reg class for %d(%s)\n", | |
4616 | original_regno, | |
4617 | reg_class_names[lra_get_allocno_class (original_regno)], | |
4618 | hard_regno, | |
4619 | reg_class_names[REGNO_REG_CLASS (hard_regno)]); | |
4620 | fprintf | |
4621 | (lra_dump_file, | |
4622 | " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); | |
4623 | } | |
4624 | return false; | |
4625 | } | |
4626 | new_reg = lra_create_new_reg (GET_MODE (original_reg), original_reg, | |
4627 | rclass, "split"); | |
4628 | reg_renumber[REGNO (new_reg)] = hard_regno; | |
4629 | } | |
4630 | save = emit_spill_move (true, new_reg, original_reg); | |
4631 | if (NEXT_INSN (save) != NULL_RTX) | |
4632 | { | |
4633 | lra_assert (! call_save_p); | |
4634 | if (lra_dump_file != NULL) | |
4635 | { | |
4636 | fprintf | |
4637 | (lra_dump_file, | |
4638 | " Rejecting split %d->%d resulting in > 2 %s save insns:\n", | |
4639 | original_regno, REGNO (new_reg), call_save_p ? "call" : ""); | |
6dde9719 | 4640 | dump_rtl_slim (lra_dump_file, save, NULL_RTX, -1, 0); |
c6a6cdaa | 4641 | fprintf (lra_dump_file, |
4642 | " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); | |
4643 | } | |
4644 | return false; | |
4645 | } | |
4646 | restore = emit_spill_move (false, new_reg, original_reg); | |
4647 | if (NEXT_INSN (restore) != NULL_RTX) | |
4648 | { | |
4649 | lra_assert (! call_save_p); | |
4650 | if (lra_dump_file != NULL) | |
4651 | { | |
4652 | fprintf (lra_dump_file, | |
4653 | " Rejecting split %d->%d " | |
4654 | "resulting in > 2 %s restore insns:\n", | |
4655 | original_regno, REGNO (new_reg), call_save_p ? "call" : ""); | |
6dde9719 | 4656 | dump_rtl_slim (lra_dump_file, restore, NULL_RTX, -1, 0); |
c6a6cdaa | 4657 | fprintf (lra_dump_file, |
4658 | " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); | |
4659 | } | |
4660 | return false; | |
4661 | } | |
4662 | after_p = usage_insns[original_regno].after_p; | |
4663 | lra_reg_info[REGNO (new_reg)].restore_regno = original_regno; | |
4664 | bitmap_set_bit (&check_only_regs, REGNO (new_reg)); | |
4665 | bitmap_set_bit (&check_only_regs, original_regno); | |
4666 | bitmap_set_bit (&lra_split_regs, REGNO (new_reg)); | |
4667 | for (;;) | |
4668 | { | |
4669 | if (GET_CODE (next_usage_insns) != INSN_LIST) | |
4670 | { | |
4671 | usage_insn = next_usage_insns; | |
4672 | break; | |
4673 | } | |
4674 | usage_insn = XEXP (next_usage_insns, 0); | |
4675 | lra_assert (DEBUG_INSN_P (usage_insn)); | |
4676 | next_usage_insns = XEXP (next_usage_insns, 1); | |
4677 | substitute_pseudo (&usage_insn, original_regno, new_reg); | |
4678 | lra_update_insn_regno_info (usage_insn); | |
4679 | if (lra_dump_file != NULL) | |
4680 | { | |
4681 | fprintf (lra_dump_file, " Split reuse change %d->%d:\n", | |
4682 | original_regno, REGNO (new_reg)); | |
6dde9719 | 4683 | dump_insn_slim (lra_dump_file, usage_insn); |
c6a6cdaa | 4684 | } |
4685 | } | |
4686 | lra_assert (NOTE_P (usage_insn) || NONDEBUG_INSN_P (usage_insn)); | |
4687 | lra_assert (usage_insn != insn || (after_p && before_p)); | |
4688 | lra_process_new_insns (usage_insn, after_p ? NULL_RTX : restore, | |
4689 | after_p ? restore : NULL_RTX, | |
4690 | call_save_p | |
4691 | ? "Add reg<-save" : "Add reg<-split"); | |
4692 | lra_process_new_insns (insn, before_p ? save : NULL_RTX, | |
4693 | before_p ? NULL_RTX : save, | |
4694 | call_save_p | |
4695 | ? "Add save<-reg" : "Add split<-reg"); | |
74855d08 | 4696 | if (nregs > 1) |
4697 | /* If we are trying to split multi-register. We should check | |
4698 | conflicts on the next assignment sub-pass. IRA can allocate on | |
4699 | sub-register levels, LRA do this on pseudos level right now and | |
4700 | this discrepancy may create allocation conflicts after | |
4701 | splitting. */ | |
4702 | lra_risky_transformations_p = true; | |
c6a6cdaa | 4703 | if (lra_dump_file != NULL) |
4704 | fprintf (lra_dump_file, | |
4705 | " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); | |
4706 | return true; | |
4707 | } | |
4708 | ||
4709 | /* Recognize that we need a split transformation for insn INSN, which | |
4710 | defines or uses REGNO in its insn biggest MODE (we use it only if | |
4711 | REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains | |
4712 | hard registers which might be used for reloads since the EBB end. | |
4713 | Put the save before INSN if BEFORE_P is true. MAX_UID is maximla | |
4714 | uid before starting INSN processing. Return true if we succeed in | |
4715 | such transformation. */ | |
4716 | static bool | |
4717 | split_if_necessary (int regno, enum machine_mode mode, | |
4718 | HARD_REG_SET potential_reload_hard_regs, | |
4719 | bool before_p, rtx insn, int max_uid) | |
4720 | { | |
4721 | bool res = false; | |
4722 | int i, nregs = 1; | |
4723 | rtx next_usage_insns; | |
4724 | ||
4725 | if (regno < FIRST_PSEUDO_REGISTER) | |
4726 | nregs = hard_regno_nregs[regno][mode]; | |
4727 | for (i = 0; i < nregs; i++) | |
4728 | if (usage_insns[regno + i].check == curr_usage_insns_check | |
4729 | && (next_usage_insns = usage_insns[regno + i].insns) != NULL_RTX | |
4730 | /* To avoid processing the register twice or more. */ | |
4731 | && ((GET_CODE (next_usage_insns) != INSN_LIST | |
4732 | && INSN_UID (next_usage_insns) < max_uid) | |
4733 | || (GET_CODE (next_usage_insns) == INSN_LIST | |
4734 | && (INSN_UID (XEXP (next_usage_insns, 0)) < max_uid))) | |
4735 | && need_for_split_p (potential_reload_hard_regs, regno + i) | |
4736 | && split_reg (before_p, regno + i, insn, next_usage_insns)) | |
4737 | res = true; | |
4738 | return res; | |
4739 | } | |
4740 | ||
4741 | /* Check only registers living at the current program point in the | |
4742 | current EBB. */ | |
4743 | static bitmap_head live_regs; | |
4744 | ||
4745 | /* Update live info in EBB given by its HEAD and TAIL insns after | |
4746 | inheritance/split transformation. The function removes dead moves | |
4747 | too. */ | |
4748 | static void | |
4749 | update_ebb_live_info (rtx head, rtx tail) | |
4750 | { | |
4751 | unsigned int j; | |
4752 | int regno; | |
4753 | bool live_p; | |
4754 | rtx prev_insn, set; | |
4755 | bool remove_p; | |
4756 | basic_block last_bb, prev_bb, curr_bb; | |
4757 | bitmap_iterator bi; | |
4758 | struct lra_insn_reg *reg; | |
4759 | edge e; | |
4760 | edge_iterator ei; | |
4761 | ||
1a8f8886 | 4762 | last_bb = BLOCK_FOR_INSN (tail); |
c6a6cdaa | 4763 | prev_bb = NULL; |
4764 | for (curr_insn = tail; | |
4765 | curr_insn != PREV_INSN (head); | |
4766 | curr_insn = prev_insn) | |
4767 | { | |
4768 | prev_insn = PREV_INSN (curr_insn); | |
76d77f1e | 4769 | /* We need to process empty blocks too. They contain |
4770 | NOTE_INSN_BASIC_BLOCK referring for the basic block. */ | |
4771 | if (NOTE_P (curr_insn) && NOTE_KIND (curr_insn) != NOTE_INSN_BASIC_BLOCK) | |
4772 | continue; | |
c6a6cdaa | 4773 | curr_bb = BLOCK_FOR_INSN (curr_insn); |
4774 | if (curr_bb != prev_bb) | |
4775 | { | |
4776 | if (prev_bb != NULL) | |
4777 | { | |
4778 | /* Update df_get_live_in (prev_bb): */ | |
4779 | EXECUTE_IF_SET_IN_BITMAP (&check_only_regs, 0, j, bi) | |
4780 | if (bitmap_bit_p (&live_regs, j)) | |
4781 | bitmap_set_bit (df_get_live_in (prev_bb), j); | |
4782 | else | |
4783 | bitmap_clear_bit (df_get_live_in (prev_bb), j); | |
4784 | } | |
4785 | if (curr_bb != last_bb) | |
4786 | { | |
4787 | /* Update df_get_live_out (curr_bb): */ | |
4788 | EXECUTE_IF_SET_IN_BITMAP (&check_only_regs, 0, j, bi) | |
4789 | { | |
4790 | live_p = bitmap_bit_p (&live_regs, j); | |
4791 | if (! live_p) | |
4792 | FOR_EACH_EDGE (e, ei, curr_bb->succs) | |
4793 | if (bitmap_bit_p (df_get_live_in (e->dest), j)) | |
4794 | { | |
4795 | live_p = true; | |
4796 | break; | |
4797 | } | |
4798 | if (live_p) | |
4799 | bitmap_set_bit (df_get_live_out (curr_bb), j); | |
4800 | else | |
4801 | bitmap_clear_bit (df_get_live_out (curr_bb), j); | |
4802 | } | |
4803 | } | |
4804 | prev_bb = curr_bb; | |
4805 | bitmap_and (&live_regs, &check_only_regs, df_get_live_out (curr_bb)); | |
4806 | } | |
0f31edc8 | 4807 | if (! NONDEBUG_INSN_P (curr_insn)) |
c6a6cdaa | 4808 | continue; |
4809 | curr_id = lra_get_insn_recog_data (curr_insn); | |
4810 | remove_p = false; | |
4811 | if ((set = single_set (curr_insn)) != NULL_RTX && REG_P (SET_DEST (set)) | |
4812 | && (regno = REGNO (SET_DEST (set))) >= FIRST_PSEUDO_REGISTER | |
4813 | && bitmap_bit_p (&check_only_regs, regno) | |
4814 | && ! bitmap_bit_p (&live_regs, regno)) | |
4815 | remove_p = true; | |
4816 | /* See which defined values die here. */ | |
4817 | for (reg = curr_id->regs; reg != NULL; reg = reg->next) | |
4818 | if (reg->type == OP_OUT && ! reg->subreg_p) | |
4819 | bitmap_clear_bit (&live_regs, reg->regno); | |
4820 | /* Mark each used value as live. */ | |
4821 | for (reg = curr_id->regs; reg != NULL; reg = reg->next) | |
53d78539 | 4822 | if (reg->type != OP_OUT |
c6a6cdaa | 4823 | && bitmap_bit_p (&check_only_regs, reg->regno)) |
4824 | bitmap_set_bit (&live_regs, reg->regno); | |
4825 | /* It is quite important to remove dead move insns because it | |
4826 | means removing dead store. We don't need to process them for | |
4827 | constraints. */ | |
4828 | if (remove_p) | |
4829 | { | |
4830 | if (lra_dump_file != NULL) | |
4831 | { | |
4832 | fprintf (lra_dump_file, " Removing dead insn:\n "); | |
6dde9719 | 4833 | dump_insn_slim (lra_dump_file, curr_insn); |
c6a6cdaa | 4834 | } |
4835 | lra_set_insn_deleted (curr_insn); | |
4836 | } | |
4837 | } | |
4838 | } | |
4839 | ||
4840 | /* The structure describes info to do an inheritance for the current | |
4841 | insn. We need to collect such info first before doing the | |
4842 | transformations because the transformations change the insn | |
4843 | internal representation. */ | |
4844 | struct to_inherit | |
4845 | { | |
4846 | /* Original regno. */ | |
4847 | int regno; | |
4848 | /* Subsequent insns which can inherit original reg value. */ | |
4849 | rtx insns; | |
4850 | }; | |
4851 | ||
4852 | /* Array containing all info for doing inheritance from the current | |
4853 | insn. */ | |
4854 | static struct to_inherit to_inherit[LRA_MAX_INSN_RELOADS]; | |
4855 | ||
4856 | /* Number elements in the previous array. */ | |
4857 | static int to_inherit_num; | |
4858 | ||
4859 | /* Add inheritance info REGNO and INSNS. Their meaning is described in | |
4860 | structure to_inherit. */ | |
4861 | static void | |
4862 | add_to_inherit (int regno, rtx insns) | |
4863 | { | |
4864 | int i; | |
4865 | ||
4866 | for (i = 0; i < to_inherit_num; i++) | |
4867 | if (to_inherit[i].regno == regno) | |
4868 | return; | |
4869 | lra_assert (to_inherit_num < LRA_MAX_INSN_RELOADS); | |
4870 | to_inherit[to_inherit_num].regno = regno; | |
4871 | to_inherit[to_inherit_num++].insns = insns; | |
4872 | } | |
4873 | ||
4874 | /* Return the last non-debug insn in basic block BB, or the block begin | |
4875 | note if none. */ | |
4876 | static rtx | |
4877 | get_last_insertion_point (basic_block bb) | |
4878 | { | |
4879 | rtx insn; | |
4880 | ||
4881 | FOR_BB_INSNS_REVERSE (bb, insn) | |
4882 | if (NONDEBUG_INSN_P (insn) || NOTE_INSN_BASIC_BLOCK_P (insn)) | |
4883 | return insn; | |
4884 | gcc_unreachable (); | |
4885 | } | |
4886 | ||
4887 | /* Set up RES by registers living on edges FROM except the edge (FROM, | |
4888 | TO) or by registers set up in a jump insn in BB FROM. */ | |
4889 | static void | |
4890 | get_live_on_other_edges (basic_block from, basic_block to, bitmap res) | |
4891 | { | |
4892 | rtx last; | |
4893 | struct lra_insn_reg *reg; | |
4894 | edge e; | |
4895 | edge_iterator ei; | |
4896 | ||
4897 | lra_assert (to != NULL); | |
4898 | bitmap_clear (res); | |
4899 | FOR_EACH_EDGE (e, ei, from->succs) | |
4900 | if (e->dest != to) | |
4901 | bitmap_ior_into (res, df_get_live_in (e->dest)); | |
4902 | last = get_last_insertion_point (from); | |
4903 | if (! JUMP_P (last)) | |
4904 | return; | |
4905 | curr_id = lra_get_insn_recog_data (last); | |
4906 | for (reg = curr_id->regs; reg != NULL; reg = reg->next) | |
4907 | if (reg->type != OP_IN) | |
4908 | bitmap_set_bit (res, reg->regno); | |
4909 | } | |
1a8f8886 | 4910 | |
c6a6cdaa | 4911 | /* Used as a temporary results of some bitmap calculations. */ |
4912 | static bitmap_head temp_bitmap; | |
4913 | ||
4914 | /* Do inheritance/split transformations in EBB starting with HEAD and | |
4915 | finishing on TAIL. We process EBB insns in the reverse order. | |
4916 | Return true if we did any inheritance/split transformation in the | |
4917 | EBB. | |
4918 | ||
4919 | We should avoid excessive splitting which results in worse code | |
4920 | because of inaccurate cost calculations for spilling new split | |
4921 | pseudos in such case. To achieve this we do splitting only if | |
4922 | register pressure is high in given basic block and there are reload | |
4923 | pseudos requiring hard registers. We could do more register | |
4924 | pressure calculations at any given program point to avoid necessary | |
4925 | splitting even more but it is to expensive and the current approach | |
4926 | works well enough. */ | |
4927 | static bool | |
4928 | inherit_in_ebb (rtx head, rtx tail) | |
4929 | { | |
4930 | int i, src_regno, dst_regno, nregs; | |
4931 | bool change_p, succ_p; | |
4932 | rtx prev_insn, next_usage_insns, set, last_insn; | |
4933 | enum reg_class cl; | |
4934 | struct lra_insn_reg *reg; | |
4935 | basic_block last_processed_bb, curr_bb = NULL; | |
4936 | HARD_REG_SET potential_reload_hard_regs, live_hard_regs; | |
4937 | bitmap to_process; | |
4938 | unsigned int j; | |
4939 | bitmap_iterator bi; | |
4940 | bool head_p, after_p; | |
4941 | ||
4942 | change_p = false; | |
4943 | curr_usage_insns_check++; | |
4944 | reloads_num = calls_num = 0; | |
4945 | bitmap_clear (&check_only_regs); | |
4946 | last_processed_bb = NULL; | |
4947 | CLEAR_HARD_REG_SET (potential_reload_hard_regs); | |
4948 | CLEAR_HARD_REG_SET (live_hard_regs); | |
4949 | /* We don't process new insns generated in the loop. */ | |
4950 | for (curr_insn = tail; curr_insn != PREV_INSN (head); curr_insn = prev_insn) | |
4951 | { | |
4952 | prev_insn = PREV_INSN (curr_insn); | |
4953 | if (BLOCK_FOR_INSN (curr_insn) != NULL) | |
4954 | curr_bb = BLOCK_FOR_INSN (curr_insn); | |
4955 | if (last_processed_bb != curr_bb) | |
4956 | { | |
4957 | /* We are at the end of BB. Add qualified living | |
4958 | pseudos for potential splitting. */ | |
4959 | to_process = df_get_live_out (curr_bb); | |
4960 | if (last_processed_bb != NULL) | |
1a8f8886 | 4961 | { |
c6a6cdaa | 4962 | /* We are somewhere in the middle of EBB. */ |
4963 | get_live_on_other_edges (curr_bb, last_processed_bb, | |
4964 | &temp_bitmap); | |
4965 | to_process = &temp_bitmap; | |
4966 | } | |
4967 | last_processed_bb = curr_bb; | |
4968 | last_insn = get_last_insertion_point (curr_bb); | |
4969 | after_p = (! JUMP_P (last_insn) | |
4970 | && (! CALL_P (last_insn) | |
4971 | || (find_reg_note (last_insn, | |
4972 | REG_NORETURN, NULL_RTX) == NULL_RTX | |
4973 | && ! SIBLING_CALL_P (last_insn)))); | |
4974 | REG_SET_TO_HARD_REG_SET (live_hard_regs, df_get_live_out (curr_bb)); | |
4975 | IOR_HARD_REG_SET (live_hard_regs, eliminable_regset); | |
4976 | IOR_HARD_REG_SET (live_hard_regs, lra_no_alloc_regs); | |
4977 | CLEAR_HARD_REG_SET (potential_reload_hard_regs); | |
4978 | EXECUTE_IF_SET_IN_BITMAP (to_process, 0, j, bi) | |
4979 | { | |
4980 | if ((int) j >= lra_constraint_new_regno_start) | |
4981 | break; | |
4982 | if (j < FIRST_PSEUDO_REGISTER || reg_renumber[j] >= 0) | |
4983 | { | |
4984 | if (j < FIRST_PSEUDO_REGISTER) | |
4985 | SET_HARD_REG_BIT (live_hard_regs, j); | |
4986 | else | |
4987 | add_to_hard_reg_set (&live_hard_regs, | |
4988 | PSEUDO_REGNO_MODE (j), | |
4989 | reg_renumber[j]); | |
4990 | setup_next_usage_insn (j, last_insn, reloads_num, after_p); | |
4991 | } | |
4992 | } | |
4993 | } | |
4994 | src_regno = dst_regno = -1; | |
4995 | if (NONDEBUG_INSN_P (curr_insn) | |
4996 | && (set = single_set (curr_insn)) != NULL_RTX | |
4997 | && REG_P (SET_DEST (set)) && REG_P (SET_SRC (set))) | |
4998 | { | |
4999 | src_regno = REGNO (SET_SRC (set)); | |
5000 | dst_regno = REGNO (SET_DEST (set)); | |
5001 | } | |
5002 | if (src_regno < lra_constraint_new_regno_start | |
5003 | && src_regno >= FIRST_PSEUDO_REGISTER | |
5004 | && reg_renumber[src_regno] < 0 | |
5005 | && dst_regno >= lra_constraint_new_regno_start | |
5006 | && (cl = lra_get_allocno_class (dst_regno)) != NO_REGS) | |
5007 | { | |
5008 | /* 'reload_pseudo <- original_pseudo'. */ | |
5009 | reloads_num++; | |
5010 | succ_p = false; | |
5011 | if (usage_insns[src_regno].check == curr_usage_insns_check | |
5012 | && (next_usage_insns = usage_insns[src_regno].insns) != NULL_RTX) | |
5013 | succ_p = inherit_reload_reg (false, src_regno, cl, | |
5014 | curr_insn, next_usage_insns); | |
5015 | if (succ_p) | |
5016 | change_p = true; | |
5017 | else | |
5018 | setup_next_usage_insn (src_regno, curr_insn, reloads_num, false); | |
5019 | if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs)) | |
5020 | IOR_HARD_REG_SET (potential_reload_hard_regs, | |
5021 | reg_class_contents[cl]); | |
5022 | } | |
5023 | else if (src_regno >= lra_constraint_new_regno_start | |
5024 | && dst_regno < lra_constraint_new_regno_start | |
5025 | && dst_regno >= FIRST_PSEUDO_REGISTER | |
5026 | && reg_renumber[dst_regno] < 0 | |
5027 | && (cl = lra_get_allocno_class (src_regno)) != NO_REGS | |
5028 | && usage_insns[dst_regno].check == curr_usage_insns_check | |
5029 | && (next_usage_insns | |
5030 | = usage_insns[dst_regno].insns) != NULL_RTX) | |
5031 | { | |
5032 | reloads_num++; | |
5033 | /* 'original_pseudo <- reload_pseudo'. */ | |
5034 | if (! JUMP_P (curr_insn) | |
5035 | && inherit_reload_reg (true, dst_regno, cl, | |
5036 | curr_insn, next_usage_insns)) | |
5037 | change_p = true; | |
5038 | /* Invalidate. */ | |
5039 | usage_insns[dst_regno].check = 0; | |
5040 | if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs)) | |
5041 | IOR_HARD_REG_SET (potential_reload_hard_regs, | |
5042 | reg_class_contents[cl]); | |
5043 | } | |
5044 | else if (INSN_P (curr_insn)) | |
5045 | { | |
bf63c98f | 5046 | int iter; |
c6a6cdaa | 5047 | int max_uid = get_max_uid (); |
5048 | ||
5049 | curr_id = lra_get_insn_recog_data (curr_insn); | |
bf63c98f | 5050 | curr_static_id = curr_id->insn_static_data; |
c6a6cdaa | 5051 | to_inherit_num = 0; |
5052 | /* Process insn definitions. */ | |
bf63c98f | 5053 | for (iter = 0; iter < 2; iter++) |
5054 | for (reg = iter == 0 ? curr_id->regs : curr_static_id->hard_regs; | |
5055 | reg != NULL; | |
5056 | reg = reg->next) | |
5057 | if (reg->type != OP_IN | |
5058 | && (dst_regno = reg->regno) < lra_constraint_new_regno_start) | |
5059 | { | |
5060 | if (dst_regno >= FIRST_PSEUDO_REGISTER && reg->type == OP_OUT | |
5061 | && reg_renumber[dst_regno] < 0 && ! reg->subreg_p | |
5062 | && usage_insns[dst_regno].check == curr_usage_insns_check | |
5063 | && (next_usage_insns | |
5064 | = usage_insns[dst_regno].insns) != NULL_RTX) | |
5065 | { | |
5066 | struct lra_insn_reg *r; | |
5067 | ||
5068 | for (r = curr_id->regs; r != NULL; r = r->next) | |
5069 | if (r->type != OP_OUT && r->regno == dst_regno) | |
5070 | break; | |
5071 | /* Don't do inheritance if the pseudo is also | |
5072 | used in the insn. */ | |
5073 | if (r == NULL) | |
5074 | /* We can not do inheritance right now | |
5075 | because the current insn reg info (chain | |
5076 | regs) can change after that. */ | |
5077 | add_to_inherit (dst_regno, next_usage_insns); | |
5078 | } | |
5079 | /* We can not process one reg twice here because of | |
5080 | usage_insns invalidation. */ | |
5081 | if ((dst_regno < FIRST_PSEUDO_REGISTER | |
5082 | || reg_renumber[dst_regno] >= 0) | |
0157439c | 5083 | && ! reg->subreg_p && reg->type != OP_IN) |
bf63c98f | 5084 | { |
5085 | HARD_REG_SET s; | |
5086 | ||
5087 | if (split_if_necessary (dst_regno, reg->biggest_mode, | |
5088 | potential_reload_hard_regs, | |
5089 | false, curr_insn, max_uid)) | |
5090 | change_p = true; | |
5091 | CLEAR_HARD_REG_SET (s); | |
5092 | if (dst_regno < FIRST_PSEUDO_REGISTER) | |
5093 | add_to_hard_reg_set (&s, reg->biggest_mode, dst_regno); | |
5094 | else | |
5095 | add_to_hard_reg_set (&s, PSEUDO_REGNO_MODE (dst_regno), | |
5096 | reg_renumber[dst_regno]); | |
5097 | AND_COMPL_HARD_REG_SET (live_hard_regs, s); | |
5098 | } | |
5099 | /* We should invalidate potential inheritance or | |
5100 | splitting for the current insn usages to the next | |
5101 | usage insns (see code below) as the output pseudo | |
5102 | prevents this. */ | |
5103 | if ((dst_regno >= FIRST_PSEUDO_REGISTER | |
5104 | && reg_renumber[dst_regno] < 0) | |
5105 | || (reg->type == OP_OUT && ! reg->subreg_p | |
5106 | && (dst_regno < FIRST_PSEUDO_REGISTER | |
5107 | || reg_renumber[dst_regno] >= 0))) | |
5108 | { | |
5109 | /* Invalidate and mark definitions. */ | |
5110 | if (dst_regno >= FIRST_PSEUDO_REGISTER) | |
5111 | usage_insns[dst_regno].check = -(int) INSN_UID (curr_insn); | |
5112 | else | |
5113 | { | |
5114 | nregs = hard_regno_nregs[dst_regno][reg->biggest_mode]; | |
5115 | for (i = 0; i < nregs; i++) | |
5116 | usage_insns[dst_regno + i].check | |
5117 | = -(int) INSN_UID (curr_insn); | |
5118 | } | |
5119 | } | |
5120 | } | |
c6a6cdaa | 5121 | if (! JUMP_P (curr_insn)) |
5122 | for (i = 0; i < to_inherit_num; i++) | |
5123 | if (inherit_reload_reg (true, to_inherit[i].regno, | |
5124 | ALL_REGS, curr_insn, | |
5125 | to_inherit[i].insns)) | |
5126 | change_p = true; | |
5127 | if (CALL_P (curr_insn)) | |
5128 | { | |
5129 | rtx cheap, pat, dest, restore; | |
5130 | int regno, hard_regno; | |
5131 | ||
5132 | calls_num++; | |
5133 | if ((cheap = find_reg_note (curr_insn, | |
5134 | REG_RETURNED, NULL_RTX)) != NULL_RTX | |
5135 | && ((cheap = XEXP (cheap, 0)), true) | |
5136 | && (regno = REGNO (cheap)) >= FIRST_PSEUDO_REGISTER | |
5137 | && (hard_regno = reg_renumber[regno]) >= 0 | |
5138 | /* If there are pending saves/restores, the | |
5139 | optimization is not worth. */ | |
5140 | && usage_insns[regno].calls_num == calls_num - 1 | |
5141 | && TEST_HARD_REG_BIT (call_used_reg_set, hard_regno)) | |
5142 | { | |
5143 | /* Restore the pseudo from the call result as | |
5144 | REG_RETURNED note says that the pseudo value is | |
5145 | in the call result and the pseudo is an argument | |
5146 | of the call. */ | |
5147 | pat = PATTERN (curr_insn); | |
5148 | if (GET_CODE (pat) == PARALLEL) | |
5149 | pat = XVECEXP (pat, 0, 0); | |
5150 | dest = SET_DEST (pat); | |
5151 | start_sequence (); | |
5152 | emit_move_insn (cheap, copy_rtx (dest)); | |
5153 | restore = get_insns (); | |
5154 | end_sequence (); | |
5155 | lra_process_new_insns (curr_insn, NULL, restore, | |
5156 | "Inserting call parameter restore"); | |
5157 | /* We don't need to save/restore of the pseudo from | |
5158 | this call. */ | |
5159 | usage_insns[regno].calls_num = calls_num; | |
5160 | bitmap_set_bit (&check_only_regs, regno); | |
5161 | } | |
5162 | } | |
5163 | to_inherit_num = 0; | |
5164 | /* Process insn usages. */ | |
bf63c98f | 5165 | for (iter = 0; iter < 2; iter++) |
5166 | for (reg = iter == 0 ? curr_id->regs : curr_static_id->hard_regs; | |
5167 | reg != NULL; | |
5168 | reg = reg->next) | |
5169 | if ((reg->type != OP_OUT | |
5170 | || (reg->type == OP_OUT && reg->subreg_p)) | |
5171 | && (src_regno = reg->regno) < lra_constraint_new_regno_start) | |
5172 | { | |
5173 | if (src_regno >= FIRST_PSEUDO_REGISTER | |
5174 | && reg_renumber[src_regno] < 0 && reg->type == OP_IN) | |
5175 | { | |
5176 | if (usage_insns[src_regno].check == curr_usage_insns_check | |
5177 | && (next_usage_insns | |
5178 | = usage_insns[src_regno].insns) != NULL_RTX | |
5179 | && NONDEBUG_INSN_P (curr_insn)) | |
5180 | add_to_inherit (src_regno, next_usage_insns); | |
5181 | else if (usage_insns[src_regno].check | |
5182 | != -(int) INSN_UID (curr_insn)) | |
5183 | /* Add usages but only if the reg is not set up | |
5184 | in the same insn. */ | |
5185 | add_next_usage_insn (src_regno, curr_insn, reloads_num); | |
5186 | } | |
5187 | else if (src_regno < FIRST_PSEUDO_REGISTER | |
5188 | || reg_renumber[src_regno] >= 0) | |
5189 | { | |
5190 | bool before_p; | |
5191 | rtx use_insn = curr_insn; | |
5192 | ||
5193 | before_p = (JUMP_P (curr_insn) | |
5194 | || (CALL_P (curr_insn) && reg->type == OP_IN)); | |
5195 | if (NONDEBUG_INSN_P (curr_insn) | |
5196 | && split_if_necessary (src_regno, reg->biggest_mode, | |
5197 | potential_reload_hard_regs, | |
5198 | before_p, curr_insn, max_uid)) | |
5199 | { | |
5200 | if (reg->subreg_p) | |
5201 | lra_risky_transformations_p = true; | |
5202 | change_p = true; | |
5203 | /* Invalidate. */ | |
5204 | usage_insns[src_regno].check = 0; | |
5205 | if (before_p) | |
5206 | use_insn = PREV_INSN (curr_insn); | |
5207 | } | |
5208 | if (NONDEBUG_INSN_P (curr_insn)) | |
5209 | { | |
5210 | if (src_regno < FIRST_PSEUDO_REGISTER) | |
5211 | add_to_hard_reg_set (&live_hard_regs, | |
5212 | reg->biggest_mode, src_regno); | |
5213 | else | |
5214 | add_to_hard_reg_set (&live_hard_regs, | |
5215 | PSEUDO_REGNO_MODE (src_regno), | |
5216 | reg_renumber[src_regno]); | |
5217 | } | |
5218 | add_next_usage_insn (src_regno, use_insn, reloads_num); | |
5219 | } | |
5220 | } | |
c6a6cdaa | 5221 | for (i = 0; i < to_inherit_num; i++) |
5222 | { | |
5223 | src_regno = to_inherit[i].regno; | |
5224 | if (inherit_reload_reg (false, src_regno, ALL_REGS, | |
5225 | curr_insn, to_inherit[i].insns)) | |
5226 | change_p = true; | |
5227 | else | |
5228 | setup_next_usage_insn (src_regno, curr_insn, reloads_num, false); | |
5229 | } | |
5230 | } | |
5231 | /* We reached the start of the current basic block. */ | |
5232 | if (prev_insn == NULL_RTX || prev_insn == PREV_INSN (head) | |
5233 | || BLOCK_FOR_INSN (prev_insn) != curr_bb) | |
5234 | { | |
5235 | /* We reached the beginning of the current block -- do | |
5236 | rest of spliting in the current BB. */ | |
5237 | to_process = df_get_live_in (curr_bb); | |
5238 | if (BLOCK_FOR_INSN (head) != curr_bb) | |
1a8f8886 | 5239 | { |
c6a6cdaa | 5240 | /* We are somewhere in the middle of EBB. */ |
5241 | get_live_on_other_edges (EDGE_PRED (curr_bb, 0)->src, | |
5242 | curr_bb, &temp_bitmap); | |
5243 | to_process = &temp_bitmap; | |
5244 | } | |
5245 | head_p = true; | |
5246 | EXECUTE_IF_SET_IN_BITMAP (to_process, 0, j, bi) | |
5247 | { | |
5248 | if ((int) j >= lra_constraint_new_regno_start) | |
5249 | break; | |
5250 | if (((int) j < FIRST_PSEUDO_REGISTER || reg_renumber[j] >= 0) | |
5251 | && usage_insns[j].check == curr_usage_insns_check | |
5252 | && (next_usage_insns = usage_insns[j].insns) != NULL_RTX) | |
5253 | { | |
5254 | if (need_for_split_p (potential_reload_hard_regs, j)) | |
5255 | { | |
5256 | if (lra_dump_file != NULL && head_p) | |
5257 | { | |
5258 | fprintf (lra_dump_file, | |
5259 | " ----------------------------------\n"); | |
5260 | head_p = false; | |
5261 | } | |
5262 | if (split_reg (false, j, bb_note (curr_bb), | |
5263 | next_usage_insns)) | |
5264 | change_p = true; | |
5265 | } | |
5266 | usage_insns[j].check = 0; | |
5267 | } | |
5268 | } | |
5269 | } | |
5270 | } | |
5271 | return change_p; | |
5272 | } | |
5273 | ||
5274 | /* This value affects EBB forming. If probability of edge from EBB to | |
5275 | a BB is not greater than the following value, we don't add the BB | |
1a8f8886 | 5276 | to EBB. */ |
ea99c7a1 | 5277 | #define EBB_PROBABILITY_CUTOFF ((REG_BR_PROB_BASE * 50) / 100) |
c6a6cdaa | 5278 | |
5279 | /* Current number of inheritance/split iteration. */ | |
5280 | int lra_inheritance_iter; | |
5281 | ||
5282 | /* Entry function for inheritance/split pass. */ | |
5283 | void | |
5284 | lra_inheritance (void) | |
5285 | { | |
5286 | int i; | |
5287 | basic_block bb, start_bb; | |
5288 | edge e; | |
5289 | ||
c6a6cdaa | 5290 | lra_inheritance_iter++; |
47f6add2 | 5291 | if (lra_inheritance_iter > LRA_MAX_INHERITANCE_PASSES) |
7b184c47 | 5292 | return; |
5293 | timevar_push (TV_LRA_INHERITANCE); | |
c6a6cdaa | 5294 | if (lra_dump_file != NULL) |
5295 | fprintf (lra_dump_file, "\n********** Inheritance #%d: **********\n\n", | |
5296 | lra_inheritance_iter); | |
5297 | curr_usage_insns_check = 0; | |
5298 | usage_insns = XNEWVEC (struct usage_insns, lra_constraint_new_regno_start); | |
5299 | for (i = 0; i < lra_constraint_new_regno_start; i++) | |
5300 | usage_insns[i].check = 0; | |
5301 | bitmap_initialize (&check_only_regs, ®_obstack); | |
5302 | bitmap_initialize (&live_regs, ®_obstack); | |
5303 | bitmap_initialize (&temp_bitmap, ®_obstack); | |
5304 | bitmap_initialize (&ebb_global_regs, ®_obstack); | |
fc00614f | 5305 | FOR_EACH_BB_FN (bb, cfun) |
c6a6cdaa | 5306 | { |
5307 | start_bb = bb; | |
5308 | if (lra_dump_file != NULL) | |
5309 | fprintf (lra_dump_file, "EBB"); | |
5310 | /* Form a EBB starting with BB. */ | |
5311 | bitmap_clear (&ebb_global_regs); | |
5312 | bitmap_ior_into (&ebb_global_regs, df_get_live_in (bb)); | |
5313 | for (;;) | |
5314 | { | |
5315 | if (lra_dump_file != NULL) | |
5316 | fprintf (lra_dump_file, " %d", bb->index); | |
34154e27 | 5317 | if (bb->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun) |
5318 | || LABEL_P (BB_HEAD (bb->next_bb))) | |
c6a6cdaa | 5319 | break; |
5320 | e = find_fallthru_edge (bb->succs); | |
5321 | if (! e) | |
5322 | break; | |
5323 | if (e->probability <= EBB_PROBABILITY_CUTOFF) | |
5324 | break; | |
5325 | bb = bb->next_bb; | |
5326 | } | |
5327 | bitmap_ior_into (&ebb_global_regs, df_get_live_out (bb)); | |
5328 | if (lra_dump_file != NULL) | |
5329 | fprintf (lra_dump_file, "\n"); | |
5330 | if (inherit_in_ebb (BB_HEAD (start_bb), BB_END (bb))) | |
5331 | /* Remember that the EBB head and tail can change in | |
5332 | inherit_in_ebb. */ | |
5333 | update_ebb_live_info (BB_HEAD (start_bb), BB_END (bb)); | |
5334 | } | |
5335 | bitmap_clear (&ebb_global_regs); | |
5336 | bitmap_clear (&temp_bitmap); | |
5337 | bitmap_clear (&live_regs); | |
5338 | bitmap_clear (&check_only_regs); | |
5339 | free (usage_insns); | |
5340 | ||
5341 | timevar_pop (TV_LRA_INHERITANCE); | |
5342 | } | |
5343 | ||
5344 | \f | |
5345 | ||
5346 | /* This page contains code to undo failed inheritance/split | |
5347 | transformations. */ | |
5348 | ||
5349 | /* Current number of iteration undoing inheritance/split. */ | |
5350 | int lra_undo_inheritance_iter; | |
5351 | ||
5352 | /* Fix BB live info LIVE after removing pseudos created on pass doing | |
5353 | inheritance/split which are REMOVED_PSEUDOS. */ | |
5354 | static void | |
5355 | fix_bb_live_info (bitmap live, bitmap removed_pseudos) | |
5356 | { | |
5357 | unsigned int regno; | |
5358 | bitmap_iterator bi; | |
5359 | ||
5360 | EXECUTE_IF_SET_IN_BITMAP (removed_pseudos, 0, regno, bi) | |
5361 | if (bitmap_clear_bit (live, regno)) | |
5362 | bitmap_set_bit (live, lra_reg_info[regno].restore_regno); | |
5363 | } | |
5364 | ||
5365 | /* Return regno of the (subreg of) REG. Otherwise, return a negative | |
5366 | number. */ | |
5367 | static int | |
5368 | get_regno (rtx reg) | |
5369 | { | |
5370 | if (GET_CODE (reg) == SUBREG) | |
5371 | reg = SUBREG_REG (reg); | |
5372 | if (REG_P (reg)) | |
5373 | return REGNO (reg); | |
5374 | return -1; | |
5375 | } | |
5376 | ||
5377 | /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and | |
5378 | return true if we did any change. The undo transformations for | |
5379 | inheritance looks like | |
5380 | i <- i2 | |
5381 | p <- i => p <- i2 | |
5382 | or removing | |
5383 | p <- i, i <- p, and i <- i3 | |
5384 | where p is original pseudo from which inheritance pseudo i was | |
5385 | created, i and i3 are removed inheritance pseudos, i2 is another | |
5386 | not removed inheritance pseudo. All split pseudos or other | |
5387 | occurrences of removed inheritance pseudos are changed on the | |
5388 | corresponding original pseudos. | |
5389 | ||
5390 | The function also schedules insns changed and created during | |
5391 | inheritance/split pass for processing by the subsequent constraint | |
5392 | pass. */ | |
5393 | static bool | |
5394 | remove_inheritance_pseudos (bitmap remove_pseudos) | |
5395 | { | |
5396 | basic_block bb; | |
5397 | int regno, sregno, prev_sregno, dregno, restore_regno; | |
5398 | rtx set, prev_set, prev_insn; | |
5399 | bool change_p, done_p; | |
5400 | ||
5401 | change_p = ! bitmap_empty_p (remove_pseudos); | |
5402 | /* We can not finish the function right away if CHANGE_P is true | |
5403 | because we need to marks insns affected by previous | |
5404 | inheritance/split pass for processing by the subsequent | |
5405 | constraint pass. */ | |
fc00614f | 5406 | FOR_EACH_BB_FN (bb, cfun) |
c6a6cdaa | 5407 | { |
5408 | fix_bb_live_info (df_get_live_in (bb), remove_pseudos); | |
5409 | fix_bb_live_info (df_get_live_out (bb), remove_pseudos); | |
5410 | FOR_BB_INSNS_REVERSE (bb, curr_insn) | |
5411 | { | |
5412 | if (! INSN_P (curr_insn)) | |
5413 | continue; | |
5414 | done_p = false; | |
5415 | sregno = dregno = -1; | |
5416 | if (change_p && NONDEBUG_INSN_P (curr_insn) | |
5417 | && (set = single_set (curr_insn)) != NULL_RTX) | |
5418 | { | |
5419 | dregno = get_regno (SET_DEST (set)); | |
5420 | sregno = get_regno (SET_SRC (set)); | |
5421 | } | |
1a8f8886 | 5422 | |
c6a6cdaa | 5423 | if (sregno >= 0 && dregno >= 0) |
5424 | { | |
5425 | if ((bitmap_bit_p (remove_pseudos, sregno) | |
5426 | && (lra_reg_info[sregno].restore_regno == dregno | |
5427 | || (bitmap_bit_p (remove_pseudos, dregno) | |
5428 | && (lra_reg_info[sregno].restore_regno | |
5429 | == lra_reg_info[dregno].restore_regno)))) | |
5430 | || (bitmap_bit_p (remove_pseudos, dregno) | |
5431 | && lra_reg_info[dregno].restore_regno == sregno)) | |
5432 | /* One of the following cases: | |
5433 | original <- removed inheritance pseudo | |
5434 | removed inherit pseudo <- another removed inherit pseudo | |
5435 | removed inherit pseudo <- original pseudo | |
5436 | Or | |
5437 | removed_split_pseudo <- original_reg | |
5438 | original_reg <- removed_split_pseudo */ | |
5439 | { | |
5440 | if (lra_dump_file != NULL) | |
5441 | { | |
5442 | fprintf (lra_dump_file, " Removing %s:\n", | |
5443 | bitmap_bit_p (&lra_split_regs, sregno) | |
5444 | || bitmap_bit_p (&lra_split_regs, dregno) | |
5445 | ? "split" : "inheritance"); | |
6dde9719 | 5446 | dump_insn_slim (lra_dump_file, curr_insn); |
c6a6cdaa | 5447 | } |
5448 | lra_set_insn_deleted (curr_insn); | |
5449 | done_p = true; | |
5450 | } | |
5451 | else if (bitmap_bit_p (remove_pseudos, sregno) | |
5452 | && bitmap_bit_p (&lra_inheritance_pseudos, sregno)) | |
5453 | { | |
5454 | /* Search the following pattern: | |
5455 | inherit_or_split_pseudo1 <- inherit_or_split_pseudo2 | |
5456 | original_pseudo <- inherit_or_split_pseudo1 | |
5457 | where the 2nd insn is the current insn and | |
5458 | inherit_or_split_pseudo2 is not removed. If it is found, | |
5459 | change the current insn onto: | |
5460 | original_pseudo <- inherit_or_split_pseudo2. */ | |
5461 | for (prev_insn = PREV_INSN (curr_insn); | |
5462 | prev_insn != NULL_RTX && ! NONDEBUG_INSN_P (prev_insn); | |
5463 | prev_insn = PREV_INSN (prev_insn)) | |
5464 | ; | |
5465 | if (prev_insn != NULL_RTX && BLOCK_FOR_INSN (prev_insn) == bb | |
5466 | && (prev_set = single_set (prev_insn)) != NULL_RTX | |
5467 | /* There should be no subregs in insn we are | |
5468 | searching because only the original reg might | |
5469 | be in subreg when we changed the mode of | |
5470 | load/store for splitting. */ | |
5471 | && REG_P (SET_DEST (prev_set)) | |
5472 | && REG_P (SET_SRC (prev_set)) | |
5473 | && (int) REGNO (SET_DEST (prev_set)) == sregno | |
5474 | && ((prev_sregno = REGNO (SET_SRC (prev_set))) | |
5475 | >= FIRST_PSEUDO_REGISTER) | |
5476 | /* As we consider chain of inheritance or | |
5477 | splitting described in above comment we should | |
5478 | check that sregno and prev_sregno were | |
5479 | inheritance/split pseudos created from the | |
5480 | same original regno. */ | |
5481 | && (lra_reg_info[sregno].restore_regno | |
5482 | == lra_reg_info[prev_sregno].restore_regno) | |
5483 | && ! bitmap_bit_p (remove_pseudos, prev_sregno)) | |
5484 | { | |
5485 | lra_assert (GET_MODE (SET_SRC (prev_set)) | |
5486 | == GET_MODE (regno_reg_rtx[sregno])); | |
5487 | if (GET_CODE (SET_SRC (set)) == SUBREG) | |
5488 | SUBREG_REG (SET_SRC (set)) = SET_SRC (prev_set); | |
5489 | else | |
5490 | SET_SRC (set) = SET_SRC (prev_set); | |
5491 | lra_push_insn_and_update_insn_regno_info (curr_insn); | |
5492 | lra_set_used_insn_alternative_by_uid | |
5493 | (INSN_UID (curr_insn), -1); | |
5494 | done_p = true; | |
5495 | if (lra_dump_file != NULL) | |
5496 | { | |
5497 | fprintf (lra_dump_file, " Change reload insn:\n"); | |
6dde9719 | 5498 | dump_insn_slim (lra_dump_file, curr_insn); |
c6a6cdaa | 5499 | } |
5500 | } | |
5501 | } | |
5502 | } | |
5503 | if (! done_p) | |
5504 | { | |
5505 | struct lra_insn_reg *reg; | |
5506 | bool restored_regs_p = false; | |
5507 | bool kept_regs_p = false; | |
5508 | ||
5509 | curr_id = lra_get_insn_recog_data (curr_insn); | |
5510 | for (reg = curr_id->regs; reg != NULL; reg = reg->next) | |
5511 | { | |
5512 | regno = reg->regno; | |
5513 | restore_regno = lra_reg_info[regno].restore_regno; | |
5514 | if (restore_regno >= 0) | |
5515 | { | |
5516 | if (change_p && bitmap_bit_p (remove_pseudos, regno)) | |
5517 | { | |
5518 | substitute_pseudo (&curr_insn, regno, | |
5519 | regno_reg_rtx[restore_regno]); | |
5520 | restored_regs_p = true; | |
5521 | } | |
5522 | else | |
5523 | kept_regs_p = true; | |
5524 | } | |
5525 | } | |
5526 | if (NONDEBUG_INSN_P (curr_insn) && kept_regs_p) | |
5527 | { | |
5528 | /* The instruction has changed since the previous | |
5529 | constraints pass. */ | |
5530 | lra_push_insn_and_update_insn_regno_info (curr_insn); | |
5531 | lra_set_used_insn_alternative_by_uid | |
5532 | (INSN_UID (curr_insn), -1); | |
5533 | } | |
5534 | else if (restored_regs_p) | |
5535 | /* The instruction has been restored to the form that | |
5536 | it had during the previous constraints pass. */ | |
5537 | lra_update_insn_regno_info (curr_insn); | |
5538 | if (restored_regs_p && lra_dump_file != NULL) | |
5539 | { | |
5540 | fprintf (lra_dump_file, " Insn after restoring regs:\n"); | |
6dde9719 | 5541 | dump_insn_slim (lra_dump_file, curr_insn); |
c6a6cdaa | 5542 | } |
5543 | } | |
5544 | } | |
5545 | } | |
5546 | return change_p; | |
5547 | } | |
5548 | ||
1f3a048a | 5549 | /* If optional reload pseudos failed to get a hard register or was not |
5550 | inherited, it is better to remove optional reloads. We do this | |
5551 | transformation after undoing inheritance to figure out necessity to | |
5552 | remove optional reloads easier. Return true if we do any | |
5553 | change. */ | |
5554 | static bool | |
5555 | undo_optional_reloads (void) | |
5556 | { | |
267200f3 | 5557 | bool change_p, keep_p; |
1f3a048a | 5558 | unsigned int regno, uid; |
5559 | bitmap_iterator bi, bi2; | |
5560 | rtx insn, set, src, dest; | |
5561 | bitmap_head removed_optional_reload_pseudos, insn_bitmap; | |
5562 | ||
5563 | bitmap_initialize (&removed_optional_reload_pseudos, ®_obstack); | |
5564 | bitmap_copy (&removed_optional_reload_pseudos, &lra_optional_reload_pseudos); | |
5565 | EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos, 0, regno, bi) | |
0c4735d1 | 5566 | { |
5567 | keep_p = false; | |
95563487 | 5568 | /* Keep optional reloads from previous subpasses. */ |
5569 | if (lra_reg_info[regno].restore_regno < 0 | |
5570 | /* If the original pseudo changed its allocation, just | |
5571 | removing the optional pseudo is dangerous as the original | |
5572 | pseudo will have longer live range. */ | |
5573 | || reg_renumber[lra_reg_info[regno].restore_regno] >= 0) | |
0c4735d1 | 5574 | keep_p = true; |
5575 | else if (reg_renumber[regno] >= 0) | |
5576 | EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi2) | |
267200f3 | 5577 | { |
0c4735d1 | 5578 | insn = lra_insn_recog_data[uid]->insn; |
5579 | if ((set = single_set (insn)) == NULL_RTX) | |
5580 | continue; | |
5581 | src = SET_SRC (set); | |
5582 | dest = SET_DEST (set); | |
5583 | if (! REG_P (src) || ! REG_P (dest)) | |
5584 | continue; | |
5585 | if (REGNO (dest) == regno | |
5586 | /* Ignore insn for optional reloads itself. */ | |
5587 | && lra_reg_info[regno].restore_regno != (int) REGNO (src) | |
5588 | /* Check only inheritance on last inheritance pass. */ | |
5589 | && (int) REGNO (src) >= new_regno_start | |
5590 | /* Check that the optional reload was inherited. */ | |
5591 | && bitmap_bit_p (&lra_inheritance_pseudos, REGNO (src))) | |
5592 | { | |
5593 | keep_p = true; | |
5594 | break; | |
5595 | } | |
267200f3 | 5596 | } |
0c4735d1 | 5597 | if (keep_p) |
5598 | { | |
5599 | bitmap_clear_bit (&removed_optional_reload_pseudos, regno); | |
5600 | if (lra_dump_file != NULL) | |
5601 | fprintf (lra_dump_file, "Keep optional reload reg %d\n", regno); | |
5602 | } | |
5603 | } | |
1f3a048a | 5604 | change_p = ! bitmap_empty_p (&removed_optional_reload_pseudos); |
5605 | bitmap_initialize (&insn_bitmap, ®_obstack); | |
5606 | EXECUTE_IF_SET_IN_BITMAP (&removed_optional_reload_pseudos, 0, regno, bi) | |
5607 | { | |
5608 | if (lra_dump_file != NULL) | |
5609 | fprintf (lra_dump_file, "Remove optional reload reg %d\n", regno); | |
5610 | bitmap_copy (&insn_bitmap, &lra_reg_info[regno].insn_bitmap); | |
5611 | EXECUTE_IF_SET_IN_BITMAP (&insn_bitmap, 0, uid, bi2) | |
5612 | { | |
5613 | insn = lra_insn_recog_data[uid]->insn; | |
5614 | if ((set = single_set (insn)) != NULL_RTX) | |
5615 | { | |
5616 | src = SET_SRC (set); | |
5617 | dest = SET_DEST (set); | |
5618 | if (REG_P (src) && REG_P (dest) | |
5619 | && ((REGNO (src) == regno | |
5620 | && (lra_reg_info[regno].restore_regno | |
5621 | == (int) REGNO (dest))) | |
5622 | || (REGNO (dest) == regno | |
5623 | && (lra_reg_info[regno].restore_regno | |
5624 | == (int) REGNO (src))))) | |
5625 | { | |
5626 | if (lra_dump_file != NULL) | |
5627 | { | |
5628 | fprintf (lra_dump_file, " Deleting move %u\n", | |
5629 | INSN_UID (insn)); | |
5630 | dump_insn_slim (lra_dump_file, insn); | |
5631 | } | |
5632 | lra_set_insn_deleted (insn); | |
5633 | continue; | |
5634 | } | |
5635 | /* We should not worry about generation memory-memory | |
5636 | moves here as if the corresponding inheritance did | |
5637 | not work (inheritance pseudo did not get a hard reg), | |
5638 | we remove the inheritance pseudo and the optional | |
5639 | reload. */ | |
5640 | } | |
5641 | substitute_pseudo (&insn, regno, | |
5642 | regno_reg_rtx[lra_reg_info[regno].restore_regno]); | |
5643 | lra_update_insn_regno_info (insn); | |
5644 | if (lra_dump_file != NULL) | |
5645 | { | |
5646 | fprintf (lra_dump_file, | |
5647 | " Restoring original insn:\n"); | |
5648 | dump_insn_slim (lra_dump_file, insn); | |
5649 | } | |
5650 | } | |
5651 | } | |
5652 | /* Clear restore_regnos. */ | |
5653 | EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos, 0, regno, bi) | |
5654 | lra_reg_info[regno].restore_regno = -1; | |
5655 | bitmap_clear (&insn_bitmap); | |
5656 | bitmap_clear (&removed_optional_reload_pseudos); | |
5657 | return change_p; | |
5658 | } | |
5659 | ||
c6a6cdaa | 5660 | /* Entry function for undoing inheritance/split transformation. Return true |
5661 | if we did any RTL change in this pass. */ | |
5662 | bool | |
5663 | lra_undo_inheritance (void) | |
5664 | { | |
5665 | unsigned int regno; | |
5666 | int restore_regno, hard_regno; | |
5667 | int n_all_inherit, n_inherit, n_all_split, n_split; | |
5668 | bitmap_head remove_pseudos; | |
5669 | bitmap_iterator bi; | |
5670 | bool change_p; | |
5671 | ||
5672 | lra_undo_inheritance_iter++; | |
47f6add2 | 5673 | if (lra_undo_inheritance_iter > LRA_MAX_INHERITANCE_PASSES) |
7b184c47 | 5674 | return false; |
c6a6cdaa | 5675 | if (lra_dump_file != NULL) |
5676 | fprintf (lra_dump_file, | |
5677 | "\n********** Undoing inheritance #%d: **********\n\n", | |
5678 | lra_undo_inheritance_iter); | |
5679 | bitmap_initialize (&remove_pseudos, ®_obstack); | |
5680 | n_inherit = n_all_inherit = 0; | |
5681 | EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos, 0, regno, bi) | |
5682 | if (lra_reg_info[regno].restore_regno >= 0) | |
5683 | { | |
5684 | n_all_inherit++; | |
267200f3 | 5685 | if (reg_renumber[regno] < 0 |
5686 | /* If the original pseudo changed its allocation, just | |
5687 | removing inheritance is dangerous as for changing | |
5688 | allocation we used shorter live-ranges. */ | |
5689 | && reg_renumber[lra_reg_info[regno].restore_regno] < 0) | |
c6a6cdaa | 5690 | bitmap_set_bit (&remove_pseudos, regno); |
5691 | else | |
5692 | n_inherit++; | |
5693 | } | |
5694 | if (lra_dump_file != NULL && n_all_inherit != 0) | |
5695 | fprintf (lra_dump_file, "Inherit %d out of %d (%.2f%%)\n", | |
5696 | n_inherit, n_all_inherit, | |
5697 | (double) n_inherit / n_all_inherit * 100); | |
5698 | n_split = n_all_split = 0; | |
5699 | EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs, 0, regno, bi) | |
5700 | if ((restore_regno = lra_reg_info[regno].restore_regno) >= 0) | |
5701 | { | |
5702 | n_all_split++; | |
5703 | hard_regno = (restore_regno >= FIRST_PSEUDO_REGISTER | |
5704 | ? reg_renumber[restore_regno] : restore_regno); | |
5705 | if (hard_regno < 0 || reg_renumber[regno] == hard_regno) | |
5706 | bitmap_set_bit (&remove_pseudos, regno); | |
5707 | else | |
5708 | { | |
5709 | n_split++; | |
5710 | if (lra_dump_file != NULL) | |
5711 | fprintf (lra_dump_file, " Keep split r%d (orig=r%d)\n", | |
5712 | regno, restore_regno); | |
5713 | } | |
5714 | } | |
5715 | if (lra_dump_file != NULL && n_all_split != 0) | |
5716 | fprintf (lra_dump_file, "Split %d out of %d (%.2f%%)\n", | |
5717 | n_split, n_all_split, | |
5718 | (double) n_split / n_all_split * 100); | |
5719 | change_p = remove_inheritance_pseudos (&remove_pseudos); | |
5720 | bitmap_clear (&remove_pseudos); | |
5721 | /* Clear restore_regnos. */ | |
5722 | EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos, 0, regno, bi) | |
5723 | lra_reg_info[regno].restore_regno = -1; | |
5724 | EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs, 0, regno, bi) | |
5725 | lra_reg_info[regno].restore_regno = -1; | |
1f3a048a | 5726 | change_p = undo_optional_reloads () || change_p; |
c6a6cdaa | 5727 | return change_p; |
5728 | } |