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55a2c322 | 1 | /* Code for RTL register eliminations. |
99dee823 | 2 | Copyright (C) 2010-2021 Free Software Foundation, Inc. |
55a2c322 VM |
3 | Contributed by Vladimir Makarov <vmakarov@redhat.com>. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it under | |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 3, or (at your option) any later | |
10 | version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | /* Eliminable registers (like a soft argument or frame pointer) are | |
22 | widely used in RTL. These eliminable registers should be replaced | |
23 | by real hard registers (like the stack pointer or hard frame | |
24 | pointer) plus some offset. The offsets usually change whenever the | |
25 | stack is expanded. We know the final offsets only at the very end | |
26 | of LRA. | |
27 | ||
28 | Within LRA, we usually keep the RTL in such a state that the | |
29 | eliminable registers can be replaced by just the corresponding hard | |
30 | register (without any offset). To achieve this we should add the | |
31 | initial elimination offset at the beginning of LRA and update the | |
32 | offsets whenever the stack is expanded. We need to do this before | |
33 | every constraint pass because the choice of offset often affects | |
34 | whether a particular address or memory constraint is satisfied. | |
35 | ||
36 | We keep RTL code at most time in such state that the virtual | |
37 | registers can be changed by just the corresponding hard registers | |
38 | (with zero offsets) and we have the right RTL code. To achieve this | |
39 | we should add initial offset at the beginning of LRA work and update | |
40 | offsets after each stack expanding. But actually we update virtual | |
41 | registers to the same virtual registers + corresponding offsets | |
42 | before every constraint pass because it affects constraint | |
43 | satisfaction (e.g. an address displacement became too big for some | |
44 | target). | |
45 | ||
46 | The final change of eliminable registers to the corresponding hard | |
47 | registers are done at the very end of LRA when there were no change | |
48 | in offsets anymore: | |
49 | ||
50 | fp + 42 => sp + 42 | |
51 | ||
52 | */ | |
53 | ||
54 | #include "config.h" | |
55 | #include "system.h" | |
56 | #include "coretypes.h" | |
c7131fb2 | 57 | #include "backend.h" |
957060b5 | 58 | #include "target.h" |
55a2c322 | 59 | #include "rtl.h" |
957060b5 | 60 | #include "tree.h" |
c7131fb2 | 61 | #include "df.h" |
4d0cdd0c | 62 | #include "memmodel.h" |
55a2c322 | 63 | #include "tm_p.h" |
957060b5 | 64 | #include "optabs.h" |
55a2c322 | 65 | #include "regs.h" |
957060b5 | 66 | #include "ira.h" |
55a2c322 VM |
67 | #include "recog.h" |
68 | #include "output.h" | |
55a2c322 VM |
69 | #include "rtl-error.h" |
70 | #include "lra-int.h" | |
71 | ||
72 | /* This structure is used to record information about hard register | |
73 | eliminations. */ | |
6c1dae73 | 74 | class lra_elim_table |
55a2c322 | 75 | { |
6c1dae73 | 76 | public: |
55a2c322 | 77 | /* Hard register number to be eliminated. */ |
f4eafc30 | 78 | int from; |
55a2c322 | 79 | /* Hard register number used as replacement. */ |
f4eafc30 | 80 | int to; |
55a2c322 VM |
81 | /* Difference between values of the two hard registers above on |
82 | previous iteration. */ | |
73ca989c | 83 | poly_int64 previous_offset; |
55a2c322 | 84 | /* Difference between the values on the current iteration. */ |
73ca989c | 85 | poly_int64 offset; |
55a2c322 | 86 | /* Nonzero if this elimination can be done. */ |
f4eafc30 | 87 | bool can_eliminate; |
55a2c322 VM |
88 | /* CAN_ELIMINATE since the last check. */ |
89 | bool prev_can_eliminate; | |
90 | /* REG rtx for the register to be eliminated. We cannot simply | |
91 | compare the number since we might then spuriously replace a hard | |
92 | register corresponding to a pseudo assigned to the reg to be | |
93 | eliminated. */ | |
f4eafc30 | 94 | rtx from_rtx; |
55a2c322 | 95 | /* REG rtx for the replacement. */ |
f4eafc30 | 96 | rtx to_rtx; |
55a2c322 VM |
97 | }; |
98 | ||
99 | /* The elimination table. Each array entry describes one possible way | |
100 | of eliminating a register in favor of another. If there is more | |
101 | than one way of eliminating a particular register, the most | |
102 | preferred should be specified first. */ | |
99b1c316 | 103 | static class lra_elim_table *reg_eliminate = 0; |
55a2c322 VM |
104 | |
105 | /* This is an intermediate structure to initialize the table. It has | |
106 | exactly the members provided by ELIMINABLE_REGS. */ | |
107 | static const struct elim_table_1 | |
108 | { | |
109 | const int from; | |
110 | const int to; | |
111 | } reg_eliminate_1[] = | |
112 | ||
55a2c322 | 113 | ELIMINABLE_REGS; |
55a2c322 VM |
114 | |
115 | #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1) | |
116 | ||
117 | /* Print info about elimination table to file F. */ | |
118 | static void | |
119 | print_elim_table (FILE *f) | |
120 | { | |
99b1c316 | 121 | class lra_elim_table *ep; |
55a2c322 VM |
122 | |
123 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
73ca989c RS |
124 | { |
125 | fprintf (f, "%s eliminate %d to %d (offset=", | |
126 | ep->can_eliminate ? "Can" : "Can't", ep->from, ep->to); | |
127 | print_dec (ep->offset, f); | |
128 | fprintf (f, ", prev_offset="); | |
129 | print_dec (ep->previous_offset, f); | |
130 | fprintf (f, ")\n"); | |
131 | } | |
55a2c322 VM |
132 | } |
133 | ||
134 | /* Print info about elimination table to stderr. */ | |
135 | void | |
136 | lra_debug_elim_table (void) | |
137 | { | |
138 | print_elim_table (stderr); | |
139 | } | |
140 | ||
141 | /* Setup possibility of elimination in elimination table element EP to | |
142 | VALUE. Setup FRAME_POINTER_NEEDED if elimination from frame | |
143 | pointer to stack pointer is not possible anymore. */ | |
144 | static void | |
99b1c316 | 145 | setup_can_eliminate (class lra_elim_table *ep, bool value) |
55a2c322 VM |
146 | { |
147 | ep->can_eliminate = ep->prev_can_eliminate = value; | |
148 | if (! value | |
149 | && ep->from == FRAME_POINTER_REGNUM && ep->to == STACK_POINTER_REGNUM) | |
150 | frame_pointer_needed = 1; | |
d303ff97 L |
151 | if (!frame_pointer_needed) |
152 | REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = 0; | |
55a2c322 VM |
153 | } |
154 | ||
155 | /* Map: eliminable "from" register -> its current elimination, | |
156 | or NULL if none. The elimination table may contain more than | |
157 | one elimination for the same hard register, but this map specifies | |
158 | the one that we are currently using. */ | |
99b1c316 | 159 | static class lra_elim_table *elimination_map[FIRST_PSEUDO_REGISTER]; |
55a2c322 VM |
160 | |
161 | /* When an eliminable hard register becomes not eliminable, we use the | |
162 | following special structure to restore original offsets for the | |
163 | register. */ | |
99b1c316 | 164 | static class lra_elim_table self_elim_table; |
55a2c322 VM |
165 | |
166 | /* Offsets should be used to restore original offsets for eliminable | |
167 | hard register which just became not eliminable. Zero, | |
168 | otherwise. */ | |
73ca989c | 169 | static poly_int64_pod self_elim_offsets[FIRST_PSEUDO_REGISTER]; |
55a2c322 VM |
170 | |
171 | /* Map: hard regno -> RTL presentation. RTL presentations of all | |
172 | potentially eliminable hard registers are stored in the map. */ | |
173 | static rtx eliminable_reg_rtx[FIRST_PSEUDO_REGISTER]; | |
174 | ||
175 | /* Set up ELIMINATION_MAP of the currently used eliminations. */ | |
176 | static void | |
177 | setup_elimination_map (void) | |
178 | { | |
179 | int i; | |
99b1c316 | 180 | class lra_elim_table *ep; |
55a2c322 VM |
181 | |
182 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
183 | elimination_map[i] = NULL; | |
184 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
185 | if (ep->can_eliminate && elimination_map[ep->from] == NULL) | |
186 | elimination_map[ep->from] = ep; | |
187 | } | |
188 | ||
189 | \f | |
190 | ||
191 | /* Compute the sum of X and Y, making canonicalizations assumed in an | |
192 | address, namely: sum constant integers, surround the sum of two | |
193 | constants with a CONST, put the constant as the second operand, and | |
194 | group the constant on the outermost sum. | |
195 | ||
196 | This routine assumes both inputs are already in canonical form. */ | |
197 | static rtx | |
198 | form_sum (rtx x, rtx y) | |
199 | { | |
ef4bddc2 | 200 | machine_mode mode = GET_MODE (x); |
73ca989c | 201 | poly_int64 offset; |
55a2c322 VM |
202 | |
203 | if (mode == VOIDmode) | |
204 | mode = GET_MODE (y); | |
205 | ||
206 | if (mode == VOIDmode) | |
207 | mode = Pmode; | |
208 | ||
73ca989c RS |
209 | if (poly_int_rtx_p (x, &offset)) |
210 | return plus_constant (mode, y, offset); | |
211 | else if (poly_int_rtx_p (y, &offset)) | |
212 | return plus_constant (mode, x, offset); | |
55a2c322 | 213 | else if (CONSTANT_P (x)) |
4e1952ab | 214 | std::swap (x, y); |
55a2c322 VM |
215 | |
216 | if (GET_CODE (x) == PLUS && CONSTANT_P (XEXP (x, 1))) | |
217 | return form_sum (XEXP (x, 0), form_sum (XEXP (x, 1), y)); | |
218 | ||
219 | /* Note that if the operands of Y are specified in the opposite | |
220 | order in the recursive calls below, infinite recursion will | |
221 | occur. */ | |
222 | if (GET_CODE (y) == PLUS && CONSTANT_P (XEXP (y, 1))) | |
223 | return form_sum (form_sum (x, XEXP (y, 0)), XEXP (y, 1)); | |
224 | ||
225 | /* If both constant, encapsulate sum. Otherwise, just form sum. A | |
226 | constant will have been placed second. */ | |
227 | if (CONSTANT_P (x) && CONSTANT_P (y)) | |
228 | { | |
229 | if (GET_CODE (x) == CONST) | |
230 | x = XEXP (x, 0); | |
231 | if (GET_CODE (y) == CONST) | |
232 | y = XEXP (y, 0); | |
233 | ||
234 | return gen_rtx_CONST (VOIDmode, gen_rtx_PLUS (mode, x, y)); | |
235 | } | |
236 | ||
237 | return gen_rtx_PLUS (mode, x, y); | |
238 | } | |
239 | ||
240 | /* Return the current substitution hard register of the elimination of | |
241 | HARD_REGNO. If HARD_REGNO is not eliminable, return itself. */ | |
242 | int | |
243 | lra_get_elimination_hard_regno (int hard_regno) | |
244 | { | |
99b1c316 | 245 | class lra_elim_table *ep; |
55a2c322 VM |
246 | |
247 | if (hard_regno < 0 || hard_regno >= FIRST_PSEUDO_REGISTER) | |
248 | return hard_regno; | |
249 | if ((ep = elimination_map[hard_regno]) == NULL) | |
250 | return hard_regno; | |
251 | return ep->to; | |
252 | } | |
253 | ||
254 | /* Return elimination which will be used for hard reg REG, NULL | |
255 | otherwise. */ | |
99b1c316 | 256 | static class lra_elim_table * |
55a2c322 VM |
257 | get_elimination (rtx reg) |
258 | { | |
259 | int hard_regno; | |
99b1c316 | 260 | class lra_elim_table *ep; |
55a2c322 VM |
261 | |
262 | lra_assert (REG_P (reg)); | |
263 | if ((hard_regno = REGNO (reg)) < 0 || hard_regno >= FIRST_PSEUDO_REGISTER) | |
264 | return NULL; | |
265 | if ((ep = elimination_map[hard_regno]) != NULL) | |
266 | return ep->from_rtx != reg ? NULL : ep; | |
73ca989c RS |
267 | poly_int64 offset = self_elim_offsets[hard_regno]; |
268 | if (known_eq (offset, 0)) | |
55a2c322 VM |
269 | return NULL; |
270 | /* This is an iteration to restore offsets just after HARD_REGNO | |
271 | stopped to be eliminable. */ | |
272 | self_elim_table.from = self_elim_table.to = hard_regno; | |
273 | self_elim_table.from_rtx | |
274 | = self_elim_table.to_rtx | |
275 | = eliminable_reg_rtx[hard_regno]; | |
276 | lra_assert (self_elim_table.from_rtx != NULL); | |
277 | self_elim_table.offset = offset; | |
278 | return &self_elim_table; | |
279 | } | |
280 | ||
18c8f1a8 VM |
281 | /* Transform (subreg (plus reg const)) to (plus (subreg reg) const) |
282 | when it is possible. Return X or the transformation result if the | |
283 | transformation is done. */ | |
284 | static rtx | |
285 | move_plus_up (rtx x) | |
286 | { | |
287 | rtx subreg_reg; | |
b8506a8a | 288 | machine_mode x_mode, subreg_reg_mode; |
18c8f1a8 VM |
289 | |
290 | if (GET_CODE (x) != SUBREG || !subreg_lowpart_p (x)) | |
291 | return x; | |
292 | subreg_reg = SUBREG_REG (x); | |
293 | x_mode = GET_MODE (x); | |
294 | subreg_reg_mode = GET_MODE (subreg_reg); | |
03a95621 RS |
295 | if (!paradoxical_subreg_p (x) |
296 | && GET_CODE (subreg_reg) == PLUS | |
cd65ae90 JJ |
297 | && CONSTANT_P (XEXP (subreg_reg, 1)) |
298 | && GET_MODE_CLASS (x_mode) == MODE_INT | |
299 | && GET_MODE_CLASS (subreg_reg_mode) == MODE_INT) | |
26ff85b0 JJ |
300 | { |
301 | rtx cst = simplify_subreg (x_mode, XEXP (subreg_reg, 1), subreg_reg_mode, | |
302 | subreg_lowpart_offset (x_mode, | |
303 | subreg_reg_mode)); | |
304 | if (cst && CONSTANT_P (cst)) | |
861c7bcd JJ |
305 | return gen_rtx_PLUS (x_mode, lowpart_subreg (x_mode, |
306 | XEXP (subreg_reg, 0), | |
26ff85b0 JJ |
307 | subreg_reg_mode), cst); |
308 | } | |
18c8f1a8 VM |
309 | return x; |
310 | } | |
311 | ||
55a2c322 | 312 | /* Scan X and replace any eliminable registers (such as fp) with a |
8d49e7ef | 313 | replacement (such as sp) if SUBST_P, plus an offset. The offset is |
55a2c322 VM |
314 | a change in the offset between the eliminable register and its |
315 | substitution if UPDATE_P, or the full offset if FULL_P, or | |
8d49e7ef | 316 | otherwise zero. If FULL_P, we also use the SP offsets for |
d9cf932c | 317 | elimination to SP. If UPDATE_P, use UPDATE_SP_OFFSET for updating |
a6af1bf9 VM |
318 | offsets of register elimnable to SP. If UPDATE_SP_OFFSET is |
319 | non-zero, don't use difference of the offset and the previous | |
320 | offset. | |
55a2c322 VM |
321 | |
322 | MEM_MODE is the mode of an enclosing MEM. We need this to know how | |
323 | much to adjust a register for, e.g., PRE_DEC. Also, if we are | |
324 | inside a MEM, we are allowed to replace a sum of a hard register | |
325 | and the constant zero with the hard register, which we cannot do | |
326 | outside a MEM. In addition, we need to record the fact that a | |
327 | hard register is referenced outside a MEM. | |
328 | ||
8d49e7ef VM |
329 | If we make full substitution to SP for non-null INSN, add the insn |
330 | sp offset. */ | |
55a2c322 | 331 | rtx |
ef4bddc2 | 332 | lra_eliminate_regs_1 (rtx_insn *insn, rtx x, machine_mode mem_mode, |
d9cf932c | 333 | bool subst_p, bool update_p, |
73ca989c | 334 | poly_int64 update_sp_offset, bool full_p) |
55a2c322 VM |
335 | { |
336 | enum rtx_code code = GET_CODE (x); | |
99b1c316 | 337 | class lra_elim_table *ep; |
55a2c322 VM |
338 | rtx new_rtx; |
339 | int i, j; | |
340 | const char *fmt; | |
341 | int copied = 0; | |
342 | ||
a6af1bf9 | 343 | lra_assert (!update_p || !full_p); |
73ca989c RS |
344 | lra_assert (known_eq (update_sp_offset, 0) |
345 | || (!subst_p && update_p && !full_p)); | |
55a2c322 VM |
346 | if (! current_function_decl) |
347 | return x; | |
348 | ||
349 | switch (code) | |
350 | { | |
351 | CASE_CONST_ANY: | |
352 | case CONST: | |
353 | case SYMBOL_REF: | |
354 | case CODE_LABEL: | |
355 | case PC: | |
55a2c322 VM |
356 | case ASM_INPUT: |
357 | case ADDR_VEC: | |
358 | case ADDR_DIFF_VEC: | |
359 | case RETURN: | |
360 | return x; | |
361 | ||
362 | case REG: | |
363 | /* First handle the case where we encounter a bare hard register | |
364 | that is eliminable. Replace it with a PLUS. */ | |
365 | if ((ep = get_elimination (x)) != NULL) | |
366 | { | |
367 | rtx to = subst_p ? ep->to_rtx : ep->from_rtx; | |
f4eafc30 | 368 | |
73ca989c | 369 | if (maybe_ne (update_sp_offset, 0)) |
a6af1bf9 VM |
370 | { |
371 | if (ep->to_rtx == stack_pointer_rtx) | |
372 | return plus_constant (Pmode, to, update_sp_offset); | |
373 | return to; | |
374 | } | |
375 | else if (update_p) | |
376 | return plus_constant (Pmode, to, ep->offset - ep->previous_offset); | |
55a2c322 | 377 | else if (full_p) |
8d49e7ef VM |
378 | return plus_constant (Pmode, to, |
379 | ep->offset | |
380 | - (insn != NULL_RTX | |
381 | && ep->to_rtx == stack_pointer_rtx | |
382 | ? lra_get_insn_recog_data (insn)->sp_offset | |
383 | : 0)); | |
55a2c322 VM |
384 | else |
385 | return to; | |
386 | } | |
387 | return x; | |
388 | ||
389 | case PLUS: | |
390 | /* If this is the sum of an eliminable register and a constant, rework | |
391 | the sum. */ | |
392 | if (REG_P (XEXP (x, 0)) && CONSTANT_P (XEXP (x, 1))) | |
393 | { | |
394 | if ((ep = get_elimination (XEXP (x, 0))) != NULL) | |
395 | { | |
73ca989c | 396 | poly_int64 offset, curr_offset; |
55a2c322 | 397 | rtx to = subst_p ? ep->to_rtx : ep->from_rtx; |
f4eafc30 | 398 | |
55a2c322 VM |
399 | if (! update_p && ! full_p) |
400 | return gen_rtx_PLUS (Pmode, to, XEXP (x, 1)); | |
a6af1bf9 | 401 | |
73ca989c | 402 | if (maybe_ne (update_sp_offset, 0)) |
a6af1bf9 VM |
403 | offset = ep->to_rtx == stack_pointer_rtx ? update_sp_offset : 0; |
404 | else | |
405 | offset = (update_p | |
406 | ? ep->offset - ep->previous_offset : ep->offset); | |
8d49e7ef VM |
407 | if (full_p && insn != NULL_RTX && ep->to_rtx == stack_pointer_rtx) |
408 | offset -= lra_get_insn_recog_data (insn)->sp_offset; | |
73ca989c RS |
409 | if (poly_int_rtx_p (XEXP (x, 1), &curr_offset) |
410 | && known_eq (curr_offset, -offset)) | |
55a2c322 VM |
411 | return to; |
412 | else | |
413 | return gen_rtx_PLUS (Pmode, to, | |
414 | plus_constant (Pmode, | |
415 | XEXP (x, 1), offset)); | |
416 | } | |
417 | ||
418 | /* If the hard register is not eliminable, we are done since | |
419 | the other operand is a constant. */ | |
420 | return x; | |
421 | } | |
422 | ||
423 | /* If this is part of an address, we want to bring any constant | |
424 | to the outermost PLUS. We will do this by doing hard | |
425 | register replacement in our operands and seeing if a constant | |
426 | shows up in one of them. | |
427 | ||
428 | Note that there is no risk of modifying the structure of the | |
429 | insn, since we only get called for its operands, thus we are | |
430 | either modifying the address inside a MEM, or something like | |
431 | an address operand of a load-address insn. */ | |
432 | ||
433 | { | |
8d49e7ef | 434 | rtx new0 = lra_eliminate_regs_1 (insn, XEXP (x, 0), mem_mode, |
d9cf932c VM |
435 | subst_p, update_p, |
436 | update_sp_offset, full_p); | |
8d49e7ef | 437 | rtx new1 = lra_eliminate_regs_1 (insn, XEXP (x, 1), mem_mode, |
d9cf932c VM |
438 | subst_p, update_p, |
439 | update_sp_offset, full_p); | |
55a2c322 | 440 | |
18c8f1a8 VM |
441 | new0 = move_plus_up (new0); |
442 | new1 = move_plus_up (new1); | |
55a2c322 VM |
443 | if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)) |
444 | return form_sum (new0, new1); | |
445 | } | |
446 | return x; | |
447 | ||
448 | case MULT: | |
449 | /* If this is the product of an eliminable hard register and a | |
450 | constant, apply the distribute law and move the constant out | |
451 | so that we have (plus (mult ..) ..). This is needed in order | |
452 | to keep load-address insns valid. This case is pathological. | |
453 | We ignore the possibility of overflow here. */ | |
454 | if (REG_P (XEXP (x, 0)) && CONST_INT_P (XEXP (x, 1)) | |
455 | && (ep = get_elimination (XEXP (x, 0))) != NULL) | |
456 | { | |
457 | rtx to = subst_p ? ep->to_rtx : ep->from_rtx; | |
f4eafc30 | 458 | |
73ca989c | 459 | if (maybe_ne (update_sp_offset, 0)) |
a6af1bf9 VM |
460 | { |
461 | if (ep->to_rtx == stack_pointer_rtx) | |
462 | return plus_constant (Pmode, | |
463 | gen_rtx_MULT (Pmode, to, XEXP (x, 1)), | |
464 | update_sp_offset * INTVAL (XEXP (x, 1))); | |
465 | return gen_rtx_MULT (Pmode, to, XEXP (x, 1)); | |
466 | } | |
467 | else if (update_p) | |
d9cf932c VM |
468 | return plus_constant (Pmode, |
469 | gen_rtx_MULT (Pmode, to, XEXP (x, 1)), | |
a6af1bf9 | 470 | (ep->offset - ep->previous_offset) |
d9cf932c | 471 | * INTVAL (XEXP (x, 1))); |
55a2c322 | 472 | else if (full_p) |
8d49e7ef | 473 | { |
73ca989c | 474 | poly_int64 offset = ep->offset; |
8d49e7ef VM |
475 | |
476 | if (insn != NULL_RTX && ep->to_rtx == stack_pointer_rtx) | |
477 | offset -= lra_get_insn_recog_data (insn)->sp_offset; | |
478 | return | |
479 | plus_constant (Pmode, | |
480 | gen_rtx_MULT (Pmode, to, XEXP (x, 1)), | |
481 | offset * INTVAL (XEXP (x, 1))); | |
482 | } | |
55a2c322 VM |
483 | else |
484 | return gen_rtx_MULT (Pmode, to, XEXP (x, 1)); | |
485 | } | |
f4eafc30 | 486 | |
191816a3 | 487 | /* fall through */ |
55a2c322 VM |
488 | |
489 | case CALL: | |
490 | case COMPARE: | |
491 | /* See comments before PLUS about handling MINUS. */ | |
492 | case MINUS: | |
493 | case DIV: case UDIV: | |
494 | case MOD: case UMOD: | |
495 | case AND: case IOR: case XOR: | |
496 | case ROTATERT: case ROTATE: | |
497 | case ASHIFTRT: case LSHIFTRT: case ASHIFT: | |
498 | case NE: case EQ: | |
499 | case GE: case GT: case GEU: case GTU: | |
500 | case LE: case LT: case LEU: case LTU: | |
501 | { | |
8d49e7ef | 502 | rtx new0 = lra_eliminate_regs_1 (insn, XEXP (x, 0), mem_mode, |
d9cf932c VM |
503 | subst_p, update_p, |
504 | update_sp_offset, full_p); | |
55a2c322 | 505 | rtx new1 = XEXP (x, 1) |
8d49e7ef | 506 | ? lra_eliminate_regs_1 (insn, XEXP (x, 1), mem_mode, |
d9cf932c VM |
507 | subst_p, update_p, |
508 | update_sp_offset, full_p) : 0; | |
55a2c322 VM |
509 | |
510 | if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)) | |
511 | return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1); | |
512 | } | |
513 | return x; | |
514 | ||
515 | case EXPR_LIST: | |
516 | /* If we have something in XEXP (x, 0), the usual case, | |
517 | eliminate it. */ | |
518 | if (XEXP (x, 0)) | |
519 | { | |
8d49e7ef | 520 | new_rtx = lra_eliminate_regs_1 (insn, XEXP (x, 0), mem_mode, |
d9cf932c VM |
521 | subst_p, update_p, |
522 | update_sp_offset, full_p); | |
55a2c322 VM |
523 | if (new_rtx != XEXP (x, 0)) |
524 | { | |
525 | /* If this is a REG_DEAD note, it is not valid anymore. | |
526 | Using the eliminated version could result in creating a | |
527 | REG_DEAD note for the stack or frame pointer. */ | |
528 | if (REG_NOTE_KIND (x) == REG_DEAD) | |
529 | return (XEXP (x, 1) | |
8d49e7ef | 530 | ? lra_eliminate_regs_1 (insn, XEXP (x, 1), mem_mode, |
d9cf932c VM |
531 | subst_p, update_p, |
532 | update_sp_offset, full_p) | |
55a2c322 VM |
533 | : NULL_RTX); |
534 | ||
535 | x = alloc_reg_note (REG_NOTE_KIND (x), new_rtx, XEXP (x, 1)); | |
536 | } | |
537 | } | |
538 | ||
191816a3 | 539 | /* fall through */ |
55a2c322 VM |
540 | |
541 | case INSN_LIST: | |
f91aec98 | 542 | case INT_LIST: |
55a2c322 VM |
543 | /* Now do eliminations in the rest of the chain. If this was |
544 | an EXPR_LIST, this might result in allocating more memory than is | |
545 | strictly needed, but it simplifies the code. */ | |
546 | if (XEXP (x, 1)) | |
547 | { | |
8d49e7ef | 548 | new_rtx = lra_eliminate_regs_1 (insn, XEXP (x, 1), mem_mode, |
d9cf932c VM |
549 | subst_p, update_p, |
550 | update_sp_offset, full_p); | |
55a2c322 VM |
551 | if (new_rtx != XEXP (x, 1)) |
552 | return | |
553 | gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), | |
554 | XEXP (x, 0), new_rtx); | |
555 | } | |
556 | return x; | |
557 | ||
558 | case PRE_INC: | |
559 | case POST_INC: | |
560 | case PRE_DEC: | |
561 | case POST_DEC: | |
562 | /* We do not support elimination of a register that is modified. | |
563 | elimination_effects has already make sure that this does not | |
564 | happen. */ | |
565 | return x; | |
566 | ||
567 | case PRE_MODIFY: | |
568 | case POST_MODIFY: | |
569 | /* We do not support elimination of a hard register that is | |
570 | modified. LRA has already make sure that this does not | |
571 | happen. The only remaining case we need to consider here is | |
572 | that the increment value may be an eliminable register. */ | |
573 | if (GET_CODE (XEXP (x, 1)) == PLUS | |
574 | && XEXP (XEXP (x, 1), 0) == XEXP (x, 0)) | |
575 | { | |
8d49e7ef | 576 | rtx new_rtx = lra_eliminate_regs_1 (insn, XEXP (XEXP (x, 1), 1), |
d9cf932c VM |
577 | mem_mode, subst_p, update_p, |
578 | update_sp_offset, full_p); | |
55a2c322 VM |
579 | |
580 | if (new_rtx != XEXP (XEXP (x, 1), 1)) | |
581 | return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0), | |
582 | gen_rtx_PLUS (GET_MODE (x), | |
583 | XEXP (x, 0), new_rtx)); | |
584 | } | |
585 | return x; | |
586 | ||
587 | case STRICT_LOW_PART: | |
588 | case NEG: case NOT: | |
589 | case SIGN_EXTEND: case ZERO_EXTEND: | |
590 | case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: | |
591 | case FLOAT: case FIX: | |
592 | case UNSIGNED_FIX: case UNSIGNED_FLOAT: | |
593 | case ABS: | |
594 | case SQRT: | |
595 | case FFS: | |
596 | case CLZ: | |
597 | case CTZ: | |
598 | case POPCOUNT: | |
599 | case PARITY: | |
600 | case BSWAP: | |
8d49e7ef | 601 | new_rtx = lra_eliminate_regs_1 (insn, XEXP (x, 0), mem_mode, |
d9cf932c VM |
602 | subst_p, update_p, |
603 | update_sp_offset, full_p); | |
55a2c322 VM |
604 | if (new_rtx != XEXP (x, 0)) |
605 | return gen_rtx_fmt_e (code, GET_MODE (x), new_rtx); | |
606 | return x; | |
607 | ||
608 | case SUBREG: | |
8d49e7ef | 609 | new_rtx = lra_eliminate_regs_1 (insn, SUBREG_REG (x), mem_mode, |
d9cf932c VM |
610 | subst_p, update_p, |
611 | update_sp_offset, full_p); | |
55a2c322 VM |
612 | |
613 | if (new_rtx != SUBREG_REG (x)) | |
614 | { | |
03a95621 | 615 | if (MEM_P (new_rtx) && !paradoxical_subreg_p (x)) |
55a2c322 VM |
616 | { |
617 | SUBREG_REG (x) = new_rtx; | |
618 | alter_subreg (&x, false); | |
619 | return x; | |
620 | } | |
b17ec42d VM |
621 | else if (! subst_p) |
622 | { | |
623 | /* LRA can transform subregs itself. So don't call | |
624 | simplify_gen_subreg until LRA transformations are | |
625 | finished. Function simplify_gen_subreg can do | |
626 | non-trivial transformations (like truncation) which | |
627 | might make LRA work to fail. */ | |
628 | SUBREG_REG (x) = new_rtx; | |
629 | return x; | |
630 | } | |
55a2c322 | 631 | else |
baa061be RS |
632 | return simplify_gen_subreg (GET_MODE (x), new_rtx, |
633 | GET_MODE (new_rtx), SUBREG_BYTE (x)); | |
55a2c322 VM |
634 | } |
635 | ||
636 | return x; | |
637 | ||
638 | case MEM: | |
639 | /* Our only special processing is to pass the mode of the MEM to our | |
640 | recursive call and copy the flags. While we are here, handle this | |
641 | case more efficiently. */ | |
642 | return | |
643 | replace_equiv_address_nv | |
644 | (x, | |
8d49e7ef | 645 | lra_eliminate_regs_1 (insn, XEXP (x, 0), GET_MODE (x), |
d9cf932c | 646 | subst_p, update_p, update_sp_offset, full_p)); |
55a2c322 VM |
647 | |
648 | case USE: | |
649 | /* Handle insn_list USE that a call to a pure function may generate. */ | |
8d49e7ef | 650 | new_rtx = lra_eliminate_regs_1 (insn, XEXP (x, 0), VOIDmode, |
d9cf932c | 651 | subst_p, update_p, update_sp_offset, full_p); |
55a2c322 VM |
652 | if (new_rtx != XEXP (x, 0)) |
653 | return gen_rtx_USE (GET_MODE (x), new_rtx); | |
654 | return x; | |
655 | ||
656 | case CLOBBER: | |
657 | case SET: | |
658 | gcc_unreachable (); | |
659 | ||
660 | default: | |
661 | break; | |
662 | } | |
663 | ||
664 | /* Process each of our operands recursively. If any have changed, make a | |
665 | copy of the rtx. */ | |
666 | fmt = GET_RTX_FORMAT (code); | |
667 | for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) | |
668 | { | |
669 | if (*fmt == 'e') | |
670 | { | |
8d49e7ef | 671 | new_rtx = lra_eliminate_regs_1 (insn, XEXP (x, i), mem_mode, |
d9cf932c VM |
672 | subst_p, update_p, |
673 | update_sp_offset, full_p); | |
55a2c322 VM |
674 | if (new_rtx != XEXP (x, i) && ! copied) |
675 | { | |
676 | x = shallow_copy_rtx (x); | |
677 | copied = 1; | |
678 | } | |
679 | XEXP (x, i) = new_rtx; | |
680 | } | |
681 | else if (*fmt == 'E') | |
682 | { | |
683 | int copied_vec = 0; | |
684 | for (j = 0; j < XVECLEN (x, i); j++) | |
685 | { | |
8d49e7ef | 686 | new_rtx = lra_eliminate_regs_1 (insn, XVECEXP (x, i, j), mem_mode, |
d9cf932c VM |
687 | subst_p, update_p, |
688 | update_sp_offset, full_p); | |
55a2c322 VM |
689 | if (new_rtx != XVECEXP (x, i, j) && ! copied_vec) |
690 | { | |
691 | rtvec new_v = gen_rtvec_v (XVECLEN (x, i), | |
692 | XVEC (x, i)->elem); | |
693 | if (! copied) | |
694 | { | |
695 | x = shallow_copy_rtx (x); | |
696 | copied = 1; | |
697 | } | |
698 | XVEC (x, i) = new_v; | |
699 | copied_vec = 1; | |
700 | } | |
701 | XVECEXP (x, i, j) = new_rtx; | |
702 | } | |
703 | } | |
704 | } | |
705 | ||
706 | return x; | |
707 | } | |
708 | ||
709 | /* This function is used externally in subsequent passes of GCC. It | |
710 | always does a full elimination of X. */ | |
711 | rtx | |
ef4bddc2 | 712 | lra_eliminate_regs (rtx x, machine_mode mem_mode, |
55a2c322 VM |
713 | rtx insn ATTRIBUTE_UNUSED) |
714 | { | |
d9cf932c | 715 | return lra_eliminate_regs_1 (NULL, x, mem_mode, true, false, 0, true); |
55a2c322 VM |
716 | } |
717 | ||
8d49e7ef VM |
718 | /* Stack pointer offset before the current insn relative to one at the |
719 | func start. RTL insns can change SP explicitly. We keep the | |
720 | changes from one insn to another through this variable. */ | |
73ca989c | 721 | static poly_int64 curr_sp_change; |
8d49e7ef | 722 | |
55a2c322 VM |
723 | /* Scan rtx X for references to elimination source or target registers |
724 | in contexts that would prevent the elimination from happening. | |
725 | Update the table of eliminables to reflect the changed state. | |
726 | MEM_MODE is the mode of an enclosing MEM rtx, or VOIDmode if not | |
727 | within a MEM. */ | |
728 | static void | |
ef4bddc2 | 729 | mark_not_eliminable (rtx x, machine_mode mem_mode) |
55a2c322 VM |
730 | { |
731 | enum rtx_code code = GET_CODE (x); | |
99b1c316 | 732 | class lra_elim_table *ep; |
55a2c322 VM |
733 | int i, j; |
734 | const char *fmt; | |
73ca989c | 735 | poly_int64 offset = 0; |
55a2c322 VM |
736 | |
737 | switch (code) | |
738 | { | |
739 | case PRE_INC: | |
740 | case POST_INC: | |
741 | case PRE_DEC: | |
742 | case POST_DEC: | |
743 | case POST_MODIFY: | |
744 | case PRE_MODIFY: | |
8d49e7ef VM |
745 | if (XEXP (x, 0) == stack_pointer_rtx |
746 | && ((code != PRE_MODIFY && code != POST_MODIFY) | |
747 | || (GET_CODE (XEXP (x, 1)) == PLUS | |
748 | && XEXP (x, 0) == XEXP (XEXP (x, 1), 0) | |
73ca989c | 749 | && poly_int_rtx_p (XEXP (XEXP (x, 1), 1), &offset)))) |
8d49e7ef | 750 | { |
7b4df2bf | 751 | poly_int64 size = GET_MODE_SIZE (mem_mode); |
8d49e7ef VM |
752 | |
753 | #ifdef PUSH_ROUNDING | |
754 | /* If more bytes than MEM_MODE are pushed, account for | |
755 | them. */ | |
756 | size = PUSH_ROUNDING (size); | |
757 | #endif | |
758 | if (code == PRE_DEC || code == POST_DEC) | |
759 | curr_sp_change -= size; | |
760 | else if (code == PRE_INC || code == POST_INC) | |
761 | curr_sp_change += size; | |
762 | else if (code == PRE_MODIFY || code == POST_MODIFY) | |
73ca989c | 763 | curr_sp_change += offset; |
8d49e7ef VM |
764 | } |
765 | else if (REG_P (XEXP (x, 0)) | |
766 | && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER) | |
767 | { | |
768 | /* If we modify the source of an elimination rule, disable | |
769 | it. Do the same if it is the destination and not the | |
770 | hard frame register. */ | |
771 | for (ep = reg_eliminate; | |
772 | ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
55a2c322 | 773 | ep++) |
8d49e7ef VM |
774 | if (ep->from_rtx == XEXP (x, 0) |
775 | || (ep->to_rtx == XEXP (x, 0) | |
776 | && ep->to_rtx != hard_frame_pointer_rtx)) | |
777 | setup_can_eliminate (ep, false); | |
778 | } | |
55a2c322 VM |
779 | return; |
780 | ||
781 | case USE: | |
782 | if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER) | |
783 | /* If using a hard register that is the source of an eliminate | |
784 | we still think can be performed, note it cannot be | |
785 | performed since we don't know how this hard register is | |
786 | used. */ | |
787 | for (ep = reg_eliminate; | |
788 | ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
789 | ep++) | |
790 | if (ep->from_rtx == XEXP (x, 0) | |
791 | && ep->to_rtx != hard_frame_pointer_rtx) | |
792 | setup_can_eliminate (ep, false); | |
793 | return; | |
794 | ||
795 | case CLOBBER: | |
796 | if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER) | |
797 | /* If clobbering a hard register that is the replacement | |
798 | register for an elimination we still think can be | |
799 | performed, note that it cannot be performed. Otherwise, we | |
800 | need not be concerned about it. */ | |
801 | for (ep = reg_eliminate; | |
802 | ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
803 | ep++) | |
804 | if (ep->to_rtx == XEXP (x, 0) | |
805 | && ep->to_rtx != hard_frame_pointer_rtx) | |
806 | setup_can_eliminate (ep, false); | |
807 | return; | |
808 | ||
809 | case SET: | |
8d49e7ef VM |
810 | if (SET_DEST (x) == stack_pointer_rtx |
811 | && GET_CODE (SET_SRC (x)) == PLUS | |
812 | && XEXP (SET_SRC (x), 0) == SET_DEST (x) | |
73ca989c | 813 | && poly_int_rtx_p (XEXP (SET_SRC (x), 1), &offset)) |
8d49e7ef | 814 | { |
73ca989c | 815 | curr_sp_change += offset; |
8d49e7ef VM |
816 | return; |
817 | } | |
818 | if (! REG_P (SET_DEST (x)) | |
819 | || REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER) | |
820 | mark_not_eliminable (SET_DEST (x), mem_mode); | |
821 | else | |
55a2c322 VM |
822 | { |
823 | /* See if this is setting the replacement hard register for | |
824 | an elimination. | |
8d49e7ef | 825 | |
55a2c322 VM |
826 | If DEST is the hard frame pointer, we do nothing because |
827 | we assume that all assignments to the frame pointer are | |
828 | for non-local gotos and are being done at a time when | |
829 | they are valid and do not disturb anything else. Some | |
830 | machines want to eliminate a fake argument pointer (or | |
831 | even a fake frame pointer) with either the real frame | |
832 | pointer or the stack pointer. Assignments to the hard | |
833 | frame pointer must not prevent this elimination. */ | |
55a2c322 VM |
834 | for (ep = reg_eliminate; |
835 | ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
836 | ep++) | |
837 | if (ep->to_rtx == SET_DEST (x) | |
8d49e7ef | 838 | && SET_DEST (x) != hard_frame_pointer_rtx) |
55a2c322 VM |
839 | setup_can_eliminate (ep, false); |
840 | } | |
8d49e7ef VM |
841 | |
842 | mark_not_eliminable (SET_SRC (x), mem_mode); | |
843 | return; | |
55a2c322 | 844 | |
8d49e7ef VM |
845 | case MEM: |
846 | /* Our only special processing is to pass the mode of the MEM to | |
847 | our recursive call. */ | |
848 | mark_not_eliminable (XEXP (x, 0), GET_MODE (x)); | |
55a2c322 VM |
849 | return; |
850 | ||
851 | default: | |
852 | break; | |
853 | } | |
854 | ||
855 | fmt = GET_RTX_FORMAT (code); | |
856 | for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) | |
857 | { | |
858 | if (*fmt == 'e') | |
8d49e7ef | 859 | mark_not_eliminable (XEXP (x, i), mem_mode); |
55a2c322 VM |
860 | else if (*fmt == 'E') |
861 | for (j = 0; j < XVECLEN (x, i); j++) | |
8d49e7ef | 862 | mark_not_eliminable (XVECEXP (x, i, j), mem_mode); |
55a2c322 VM |
863 | } |
864 | } | |
865 | ||
866 | \f | |
867 | ||
868 | /* Scan INSN and eliminate all eliminable hard registers in it. | |
869 | ||
870 | If REPLACE_P is true, do the replacement destructively. Also | |
871 | delete the insn as dead it if it is setting an eliminable register. | |
872 | ||
873 | If REPLACE_P is false, just update the offsets while keeping the | |
8d49e7ef | 874 | base register the same. If FIRST_P, use the sp offset for |
a6af1bf9 VM |
875 | elimination to sp. Otherwise, use UPDATE_SP_OFFSET for this. If |
876 | UPDATE_SP_OFFSET is non-zero, don't use difference of the offset | |
877 | and the previous offset. Attach the note about used elimination | |
878 | for insns setting frame pointer to update elimination easy (without | |
879 | parsing already generated elimination insns to find offset | |
880 | previously used) in future. */ | |
55a2c322 | 881 | |
d9cf932c VM |
882 | void |
883 | eliminate_regs_in_insn (rtx_insn *insn, bool replace_p, bool first_p, | |
73ca989c | 884 | poly_int64 update_sp_offset) |
55a2c322 VM |
885 | { |
886 | int icode = recog_memoized (insn); | |
cf2ac1c3 | 887 | rtx set, old_set = single_set (insn); |
55a2c322 VM |
888 | bool validate_p; |
889 | int i; | |
890 | rtx substed_operand[MAX_RECOG_OPERANDS]; | |
891 | rtx orig_operand[MAX_RECOG_OPERANDS]; | |
99b1c316 | 892 | class lra_elim_table *ep; |
55a2c322 VM |
893 | rtx plus_src, plus_cst_src; |
894 | lra_insn_recog_data_t id; | |
895 | struct lra_static_insn_data *static_id; | |
896 | ||
897 | if (icode < 0 && asm_noperands (PATTERN (insn)) < 0 && ! DEBUG_INSN_P (insn)) | |
898 | { | |
39718607 | 899 | lra_assert (GET_CODE (PATTERN (insn)) == USE |
55a2c322 | 900 | || GET_CODE (PATTERN (insn)) == CLOBBER |
55a2c322 VM |
901 | || GET_CODE (PATTERN (insn)) == ASM_INPUT); |
902 | return; | |
903 | } | |
904 | ||
55a2c322 VM |
905 | /* We allow one special case which happens to work on all machines we |
906 | currently support: a single set with the source or a REG_EQUAL | |
907 | note being a PLUS of an eliminable register and a constant. */ | |
908 | plus_src = plus_cst_src = 0; | |
73ca989c | 909 | poly_int64 offset = 0; |
55a2c322 VM |
910 | if (old_set && REG_P (SET_DEST (old_set))) |
911 | { | |
912 | if (GET_CODE (SET_SRC (old_set)) == PLUS) | |
913 | plus_src = SET_SRC (old_set); | |
914 | /* First see if the source is of the form (plus (...) CST). */ | |
73ca989c | 915 | if (plus_src && poly_int_rtx_p (XEXP (plus_src, 1), &offset)) |
55a2c322 VM |
916 | plus_cst_src = plus_src; |
917 | /* Check that the first operand of the PLUS is a hard reg or | |
918 | the lowpart subreg of one. */ | |
919 | if (plus_cst_src) | |
920 | { | |
921 | rtx reg = XEXP (plus_cst_src, 0); | |
922 | ||
923 | if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg)) | |
924 | reg = SUBREG_REG (reg); | |
925 | ||
926 | if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER) | |
927 | plus_cst_src = 0; | |
928 | } | |
929 | } | |
930 | if (plus_cst_src) | |
931 | { | |
932 | rtx reg = XEXP (plus_cst_src, 0); | |
55a2c322 VM |
933 | |
934 | if (GET_CODE (reg) == SUBREG) | |
935 | reg = SUBREG_REG (reg); | |
936 | ||
937 | if (REG_P (reg) && (ep = get_elimination (reg)) != NULL) | |
938 | { | |
939 | rtx to_rtx = replace_p ? ep->to_rtx : ep->from_rtx; | |
f4eafc30 | 940 | |
55a2c322 VM |
941 | if (! replace_p) |
942 | { | |
73ca989c | 943 | if (known_eq (update_sp_offset, 0)) |
a6af1bf9 | 944 | offset += (ep->offset - ep->previous_offset); |
d9cf932c VM |
945 | if (ep->to_rtx == stack_pointer_rtx) |
946 | { | |
947 | if (first_p) | |
948 | offset -= lra_get_insn_recog_data (insn)->sp_offset; | |
949 | else | |
950 | offset += update_sp_offset; | |
951 | } | |
55a2c322 VM |
952 | offset = trunc_int_for_mode (offset, GET_MODE (plus_cst_src)); |
953 | } | |
f4eafc30 | 954 | |
55a2c322 VM |
955 | if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG) |
956 | to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)), to_rtx); | |
957 | /* If we have a nonzero offset, and the source is already a | |
958 | simple REG, the following transformation would increase | |
959 | the cost of the insn by replacing a simple REG with (plus | |
960 | (reg sp) CST). So try only when we already had a PLUS | |
961 | before. */ | |
73ca989c | 962 | if (known_eq (offset, 0) || plus_src) |
55a2c322 VM |
963 | { |
964 | rtx new_src = plus_constant (GET_MODE (to_rtx), to_rtx, offset); | |
f4eafc30 | 965 | |
55a2c322 VM |
966 | old_set = single_set (insn); |
967 | ||
968 | /* First see if this insn remains valid when we make the | |
969 | change. If not, try to replace the whole pattern | |
970 | with a simple set (this may help if the original insn | |
971 | was a PARALLEL that was only recognized as single_set | |
972 | due to REG_UNUSED notes). If this isn't valid | |
973 | either, keep the INSN_CODE the same and let the | |
974 | constraint pass fix it up. */ | |
975 | if (! validate_change (insn, &SET_SRC (old_set), new_src, 0)) | |
976 | { | |
f7df4a84 | 977 | rtx new_pat = gen_rtx_SET (SET_DEST (old_set), new_src); |
f4eafc30 | 978 | |
55a2c322 VM |
979 | if (! validate_change (insn, &PATTERN (insn), new_pat, 0)) |
980 | SET_SRC (old_set) = new_src; | |
981 | } | |
982 | lra_update_insn_recog_data (insn); | |
983 | /* This can't have an effect on elimination offsets, so skip | |
984 | right to the end. */ | |
985 | return; | |
986 | } | |
987 | } | |
988 | } | |
989 | ||
990 | /* Eliminate all eliminable registers occurring in operands that | |
991 | can be handled by the constraint pass. */ | |
992 | id = lra_get_insn_recog_data (insn); | |
993 | static_id = id->insn_static_data; | |
994 | validate_p = false; | |
995 | for (i = 0; i < static_id->n_operands; i++) | |
996 | { | |
997 | orig_operand[i] = *id->operand_loc[i]; | |
998 | substed_operand[i] = *id->operand_loc[i]; | |
999 | ||
1000 | /* For an asm statement, every operand is eliminable. */ | |
1001 | if (icode < 0 || insn_data[icode].operand[i].eliminable) | |
1002 | { | |
1003 | /* Check for setting a hard register that we know about. */ | |
1004 | if (static_id->operand[i].type != OP_IN | |
1005 | && REG_P (orig_operand[i])) | |
1006 | { | |
1007 | /* If we are assigning to a hard register that can be | |
1008 | eliminated, it must be as part of a PARALLEL, since | |
67914693 | 1009 | the code above handles single SETs. This reg cannot |
55a2c322 VM |
1010 | be longer eliminated -- it is forced by |
1011 | mark_not_eliminable. */ | |
1012 | for (ep = reg_eliminate; | |
1013 | ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
1014 | ep++) | |
1015 | lra_assert (ep->from_rtx != orig_operand[i] | |
1016 | || ! ep->can_eliminate); | |
1017 | } | |
1018 | ||
1019 | /* Companion to the above plus substitution, we can allow | |
1020 | invariants as the source of a plain move. */ | |
1021 | substed_operand[i] | |
8d49e7ef VM |
1022 | = lra_eliminate_regs_1 (insn, *id->operand_loc[i], VOIDmode, |
1023 | replace_p, ! replace_p && ! first_p, | |
d9cf932c | 1024 | update_sp_offset, first_p); |
55a2c322 VM |
1025 | if (substed_operand[i] != orig_operand[i]) |
1026 | validate_p = true; | |
1027 | } | |
1028 | } | |
1029 | ||
2c62cbaa VM |
1030 | if (! validate_p) |
1031 | return; | |
1032 | ||
55a2c322 VM |
1033 | /* Substitute the operands; the new values are in the substed_operand |
1034 | array. */ | |
1035 | for (i = 0; i < static_id->n_operands; i++) | |
1036 | *id->operand_loc[i] = substed_operand[i]; | |
1037 | for (i = 0; i < static_id->n_dups; i++) | |
1038 | *id->dup_loc[i] = substed_operand[(int) static_id->dup_num[i]]; | |
1039 | ||
cf2ac1c3 VM |
1040 | /* Transform plus (plus (hard reg, const), pseudo) to plus (plus (pseudo, |
1041 | const), hard reg) in order to keep insn containing eliminated register | |
1042 | after all reloads calculating its offset. This permits to keep register | |
1043 | pressure under control and helps to avoid LRA cycling in patalogical | |
1044 | cases. */ | |
1045 | if (! replace_p && (set = single_set (insn)) != NULL | |
1046 | && GET_CODE (SET_SRC (set)) == PLUS | |
1047 | && GET_CODE (XEXP (SET_SRC (set), 0)) == PLUS) | |
1048 | { | |
1049 | rtx reg1, reg2, op1, op2; | |
1050 | ||
1051 | reg1 = op1 = XEXP (XEXP (SET_SRC (set), 0), 0); | |
1052 | reg2 = op2 = XEXP (SET_SRC (set), 1); | |
1053 | if (GET_CODE (reg1) == SUBREG) | |
1054 | reg1 = SUBREG_REG (reg1); | |
1055 | if (GET_CODE (reg2) == SUBREG) | |
1056 | reg2 = SUBREG_REG (reg2); | |
1057 | if (REG_P (reg1) && REG_P (reg2) | |
1058 | && REGNO (reg1) < FIRST_PSEUDO_REGISTER | |
4334b524 VM |
1059 | && REGNO (reg2) >= FIRST_PSEUDO_REGISTER |
1060 | && GET_MODE (reg1) == Pmode | |
68ba1039 | 1061 | && !have_addptr3_insn (lra_pmode_pseudo, reg1, |
4334b524 | 1062 | XEXP (XEXP (SET_SRC (set), 0), 1))) |
cf2ac1c3 VM |
1063 | { |
1064 | XEXP (XEXP (SET_SRC (set), 0), 0) = op2; | |
1065 | XEXP (SET_SRC (set), 1) = op1; | |
1066 | } | |
1067 | } | |
1068 | ||
2c62cbaa VM |
1069 | /* If we had a move insn but now we don't, re-recognize it. |
1070 | This will cause spurious re-recognition if the old move had a | |
1071 | PARALLEL since the new one still will, but we can't call | |
1072 | single_set without having put new body into the insn and the | |
1073 | re-recognition won't hurt in this rare case. */ | |
8ba6ea87 | 1074 | lra_update_insn_recog_data (insn); |
55a2c322 VM |
1075 | } |
1076 | ||
1077 | /* Spill pseudos which are assigned to hard registers in SET. Add | |
1078 | affected insns for processing in the subsequent constraint | |
1079 | pass. */ | |
1080 | static void | |
1081 | spill_pseudos (HARD_REG_SET set) | |
1082 | { | |
1083 | int i; | |
1084 | bitmap_head to_process; | |
cfa434f6 | 1085 | rtx_insn *insn; |
55a2c322 VM |
1086 | |
1087 | if (hard_reg_set_empty_p (set)) | |
1088 | return; | |
1089 | if (lra_dump_file != NULL) | |
1090 | { | |
1091 | fprintf (lra_dump_file, " Spilling non-eliminable hard regs:"); | |
1092 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1093 | if (TEST_HARD_REG_BIT (set, i)) | |
1094 | fprintf (lra_dump_file, " %d", i); | |
1095 | fprintf (lra_dump_file, "\n"); | |
1096 | } | |
1097 | bitmap_initialize (&to_process, ®_obstack); | |
1098 | for (i = FIRST_PSEUDO_REGISTER; i < max_reg_num (); i++) | |
1099 | if (lra_reg_info[i].nrefs != 0 && reg_renumber[i] >= 0 | |
1100 | && overlaps_hard_reg_set_p (set, | |
1101 | PSEUDO_REGNO_MODE (i), reg_renumber[i])) | |
1102 | { | |
1103 | if (lra_dump_file != NULL) | |
1104 | fprintf (lra_dump_file, " Spilling r%d(%d)\n", | |
1105 | i, reg_renumber[i]); | |
1106 | reg_renumber[i] = -1; | |
1107 | bitmap_ior_into (&to_process, &lra_reg_info[i].insn_bitmap); | |
1108 | } | |
44942965 | 1109 | lra_no_alloc_regs |= set; |
55a2c322 VM |
1110 | for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn)) |
1111 | if (bitmap_bit_p (&to_process, INSN_UID (insn))) | |
1112 | { | |
1113 | lra_push_insn (insn); | |
7874b7c5 | 1114 | lra_set_used_insn_alternative (insn, LRA_UNKNOWN_ALT); |
55a2c322 VM |
1115 | } |
1116 | bitmap_clear (&to_process); | |
1117 | } | |
1118 | ||
1119 | /* Update all offsets and possibility for elimination on eliminable | |
8d49e7ef | 1120 | registers. Spill pseudos assigned to registers which are |
55a2c322 VM |
1121 | uneliminable, update LRA_NO_ALLOC_REGS and ELIMINABLE_REG_SET. Add |
1122 | insns to INSNS_WITH_CHANGED_OFFSETS containing eliminable hard | |
5a107a0f VM |
1123 | registers whose offsets should be changed. Return true if any |
1124 | elimination offset changed. */ | |
1125 | static bool | |
55a2c322 VM |
1126 | update_reg_eliminate (bitmap insns_with_changed_offsets) |
1127 | { | |
5a107a0f | 1128 | bool prev, result; |
99b1c316 | 1129 | class lra_elim_table *ep, *ep1; |
55a2c322 VM |
1130 | HARD_REG_SET temp_hard_reg_set; |
1131 | ||
29eb9a44 BE |
1132 | targetm.compute_frame_layout (); |
1133 | ||
55a2c322 VM |
1134 | /* Clear self elimination offsets. */ |
1135 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
1136 | self_elim_offsets[ep->from] = 0; | |
55a2c322 VM |
1137 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
1138 | { | |
1139 | /* If it is a currently used elimination: update the previous | |
1140 | offset. */ | |
1141 | if (elimination_map[ep->from] == ep) | |
1142 | ep->previous_offset = ep->offset; | |
1143 | ||
1144 | prev = ep->prev_can_eliminate; | |
1145 | setup_can_eliminate (ep, targetm.can_eliminate (ep->from, ep->to)); | |
1146 | if (ep->can_eliminate && ! prev) | |
1147 | { | |
1148 | /* It is possible that not eliminable register becomes | |
1149 | eliminable because we took other reasons into account to | |
1150 | set up eliminable regs in the initial set up. Just | |
1151 | ignore new eliminable registers. */ | |
1152 | setup_can_eliminate (ep, false); | |
1153 | continue; | |
1154 | } | |
1155 | if (ep->can_eliminate != prev && elimination_map[ep->from] == ep) | |
1156 | { | |
1157 | /* We cannot use this elimination anymore -- find another | |
1158 | one. */ | |
1159 | if (lra_dump_file != NULL) | |
1160 | fprintf (lra_dump_file, | |
1161 | " Elimination %d to %d is not possible anymore\n", | |
1162 | ep->from, ep->to); | |
8d49e7ef | 1163 | /* If after processing RTL we decides that SP can be used as |
67914693 | 1164 | a result of elimination, it cannot be changed. */ |
ddcfa953 JW |
1165 | gcc_assert ((ep->to_rtx != stack_pointer_rtx) |
1166 | || (ep->from < FIRST_PSEUDO_REGISTER | |
1167 | && fixed_regs [ep->from])); | |
55a2c322 VM |
1168 | /* Mark that is not eliminable anymore. */ |
1169 | elimination_map[ep->from] = NULL; | |
1170 | for (ep1 = ep + 1; ep1 < ®_eliminate[NUM_ELIMINABLE_REGS]; ep1++) | |
1171 | if (ep1->can_eliminate && ep1->from == ep->from) | |
1172 | break; | |
1173 | if (ep1 < ®_eliminate[NUM_ELIMINABLE_REGS]) | |
1174 | { | |
1175 | if (lra_dump_file != NULL) | |
1176 | fprintf (lra_dump_file, " Using elimination %d to %d now\n", | |
1177 | ep1->from, ep1->to); | |
73ca989c | 1178 | lra_assert (known_eq (ep1->previous_offset, 0)); |
55a2c322 VM |
1179 | ep1->previous_offset = ep->offset; |
1180 | } | |
1181 | else | |
1182 | { | |
1183 | /* There is no elimination anymore just use the hard | |
1184 | register `from' itself. Setup self elimination | |
1185 | offset to restore the original offset values. */ | |
1186 | if (lra_dump_file != NULL) | |
1187 | fprintf (lra_dump_file, " %d is not eliminable at all\n", | |
1188 | ep->from); | |
1189 | self_elim_offsets[ep->from] = -ep->offset; | |
73ca989c | 1190 | if (maybe_ne (ep->offset, 0)) |
55a2c322 VM |
1191 | bitmap_ior_into (insns_with_changed_offsets, |
1192 | &lra_reg_info[ep->from].insn_bitmap); | |
1193 | } | |
1194 | } | |
1195 | ||
55a2c322 | 1196 | INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->offset); |
55a2c322 | 1197 | } |
55a2c322 | 1198 | setup_elimination_map (); |
5a107a0f | 1199 | result = false; |
8d49e7ef | 1200 | CLEAR_HARD_REG_SET (temp_hard_reg_set); |
55a2c322 | 1201 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
8d49e7ef | 1202 | if (elimination_map[ep->from] == NULL) |
764df76c | 1203 | add_to_hard_reg_set (&temp_hard_reg_set, Pmode, ep->from); |
8d49e7ef | 1204 | else if (elimination_map[ep->from] == ep) |
d70a81dd | 1205 | { |
8d49e7ef VM |
1206 | /* Prevent the hard register into which we eliminate from |
1207 | the usage for pseudos. */ | |
1208 | if (ep->from != ep->to) | |
764df76c | 1209 | add_to_hard_reg_set (&temp_hard_reg_set, Pmode, ep->to); |
73ca989c | 1210 | if (maybe_ne (ep->previous_offset, ep->offset)) |
8d49e7ef VM |
1211 | { |
1212 | bitmap_ior_into (insns_with_changed_offsets, | |
1213 | &lra_reg_info[ep->from].insn_bitmap); | |
1214 | ||
1215 | /* Update offset when the eliminate offset have been | |
1216 | changed. */ | |
1217 | lra_update_reg_val_offset (lra_reg_info[ep->from].val, | |
1218 | ep->offset - ep->previous_offset); | |
1219 | result = true; | |
1220 | } | |
d70a81dd | 1221 | } |
44942965 | 1222 | lra_no_alloc_regs |= temp_hard_reg_set; |
d15e5131 | 1223 | eliminable_regset &= ~temp_hard_reg_set; |
8d49e7ef | 1224 | spill_pseudos (temp_hard_reg_set); |
5a107a0f | 1225 | return result; |
55a2c322 VM |
1226 | } |
1227 | ||
1228 | /* Initialize the table of hard registers to eliminate. | |
1229 | Pre-condition: global flag frame_pointer_needed has been set before | |
1230 | calling this function. */ | |
1231 | static void | |
1232 | init_elim_table (void) | |
1233 | { | |
99b1c316 | 1234 | class lra_elim_table *ep; |
522d4efc | 1235 | bool value_p; |
55a2c322 | 1236 | const struct elim_table_1 *ep1; |
55a2c322 VM |
1237 | |
1238 | if (!reg_eliminate) | |
99b1c316 | 1239 | reg_eliminate = XCNEWVEC (class lra_elim_table, NUM_ELIMINABLE_REGS); |
55a2c322 VM |
1240 | |
1241 | memset (self_elim_offsets, 0, sizeof (self_elim_offsets)); | |
1242 | /* Initiate member values which will be never changed. */ | |
1243 | self_elim_table.can_eliminate = self_elim_table.prev_can_eliminate = true; | |
1244 | self_elim_table.previous_offset = 0; | |
53680238 | 1245 | |
55a2c322 VM |
1246 | for (ep = reg_eliminate, ep1 = reg_eliminate_1; |
1247 | ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++) | |
1248 | { | |
1249 | ep->offset = ep->previous_offset = 0; | |
1250 | ep->from = ep1->from; | |
1251 | ep->to = ep1->to; | |
1252 | value_p = (targetm.can_eliminate (ep->from, ep->to) | |
1253 | && ! (ep->to == STACK_POINTER_REGNUM | |
f4eafc30 | 1254 | && frame_pointer_needed |
55a2c322 VM |
1255 | && (! SUPPORTS_STACK_ALIGNMENT |
1256 | || ! stack_realign_fp))); | |
1257 | setup_can_eliminate (ep, value_p); | |
1258 | } | |
55a2c322 | 1259 | |
8d49e7ef VM |
1260 | /* Build the FROM and TO REG rtx's. Note that code in gen_rtx_REG |
1261 | will cause, e.g., gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to | |
1262 | equal stack_pointer_rtx. We depend on this. Threfore we switch | |
1263 | off that we are in LRA temporarily. */ | |
1264 | lra_in_progress = 0; | |
55a2c322 VM |
1265 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
1266 | { | |
1267 | ep->from_rtx = gen_rtx_REG (Pmode, ep->from); | |
1268 | ep->to_rtx = gen_rtx_REG (Pmode, ep->to); | |
1269 | eliminable_reg_rtx[ep->from] = ep->from_rtx; | |
1270 | } | |
8d49e7ef | 1271 | lra_in_progress = 1; |
55a2c322 VM |
1272 | } |
1273 | ||
8d49e7ef VM |
1274 | /* Function for initialization of elimination once per function. It |
1275 | sets up sp offset for each insn. */ | |
1276 | static void | |
1277 | init_elimination (void) | |
55a2c322 | 1278 | { |
8d49e7ef | 1279 | bool stop_to_sp_elimination_p; |
55a2c322 | 1280 | basic_block bb; |
cfa434f6 | 1281 | rtx_insn *insn; |
99b1c316 | 1282 | class lra_elim_table *ep; |
55a2c322 VM |
1283 | |
1284 | init_elim_table (); | |
11cd3bed | 1285 | FOR_EACH_BB_FN (bb, cfun) |
8d49e7ef VM |
1286 | { |
1287 | curr_sp_change = 0; | |
1288 | stop_to_sp_elimination_p = false; | |
1289 | FOR_BB_INSNS (bb, insn) | |
1290 | if (INSN_P (insn)) | |
1291 | { | |
1292 | lra_get_insn_recog_data (insn)->sp_offset = curr_sp_change; | |
1293 | if (NONDEBUG_INSN_P (insn)) | |
1294 | { | |
1295 | mark_not_eliminable (PATTERN (insn), VOIDmode); | |
73ca989c | 1296 | if (maybe_ne (curr_sp_change, 0) |
8d49e7ef VM |
1297 | && find_reg_note (insn, REG_LABEL_OPERAND, NULL_RTX)) |
1298 | stop_to_sp_elimination_p = true; | |
1299 | } | |
1300 | } | |
1301 | if (! frame_pointer_needed | |
73ca989c | 1302 | && (maybe_ne (curr_sp_change, 0) || stop_to_sp_elimination_p) |
8d49e7ef VM |
1303 | && bb->succs && bb->succs->length () != 0) |
1304 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
1305 | if (ep->to == STACK_POINTER_REGNUM) | |
1306 | setup_can_eliminate (ep, false); | |
1307 | } | |
55a2c322 VM |
1308 | setup_elimination_map (); |
1309 | } | |
1310 | ||
1311 | /* Eliminate hard reg given by its location LOC. */ | |
1312 | void | |
1313 | lra_eliminate_reg_if_possible (rtx *loc) | |
1314 | { | |
1315 | int regno; | |
99b1c316 | 1316 | class lra_elim_table *ep; |
55a2c322 VM |
1317 | |
1318 | lra_assert (REG_P (*loc)); | |
1319 | if ((regno = REGNO (*loc)) >= FIRST_PSEUDO_REGISTER | |
1320 | || ! TEST_HARD_REG_BIT (lra_no_alloc_regs, regno)) | |
1321 | return; | |
1322 | if ((ep = get_elimination (*loc)) != NULL) | |
1323 | *loc = ep->to_rtx; | |
1324 | } | |
1325 | ||
8d49e7ef VM |
1326 | /* Do (final if FINAL_P or first if FIRST_P) elimination in INSN. Add |
1327 | the insn for subsequent processing in the constraint pass, update | |
1328 | the insn info. */ | |
55a2c322 | 1329 | static void |
cfa434f6 | 1330 | process_insn_for_elimination (rtx_insn *insn, bool final_p, bool first_p) |
55a2c322 | 1331 | { |
d9cf932c | 1332 | eliminate_regs_in_insn (insn, final_p, first_p, 0); |
55a2c322 VM |
1333 | if (! final_p) |
1334 | { | |
1335 | /* Check that insn changed its code. This is a case when a move | |
1336 | insn becomes an add insn and we do not want to process the | |
1337 | insn as a move anymore. */ | |
1338 | int icode = recog (PATTERN (insn), insn, 0); | |
1339 | ||
1340 | if (icode >= 0 && icode != INSN_CODE (insn)) | |
1341 | { | |
7436a1c6 VM |
1342 | if (INSN_CODE (insn) >= 0) |
1343 | /* Insn code is changed. It may change its operand type | |
1344 | from IN to INOUT. Inform the subsequent assignment | |
1345 | subpass about this situation. */ | |
1346 | check_and_force_assignment_correctness_p = true; | |
55a2c322 VM |
1347 | INSN_CODE (insn) = icode; |
1348 | lra_update_insn_recog_data (insn); | |
1349 | } | |
1350 | lra_update_insn_regno_info (insn); | |
1351 | lra_push_insn (insn); | |
7874b7c5 | 1352 | lra_set_used_insn_alternative (insn, LRA_UNKNOWN_ALT); |
55a2c322 VM |
1353 | } |
1354 | } | |
1355 | ||
1356 | /* Entry function to do final elimination if FINAL_P or to update | |
8d49e7ef VM |
1357 | elimination register offsets (FIRST_P if we are doing it the first |
1358 | time). */ | |
55a2c322 | 1359 | void |
8d49e7ef | 1360 | lra_eliminate (bool final_p, bool first_p) |
55a2c322 | 1361 | { |
55a2c322 | 1362 | unsigned int uid; |
55a2c322 VM |
1363 | bitmap_head insns_with_changed_offsets; |
1364 | bitmap_iterator bi; | |
99b1c316 | 1365 | class lra_elim_table *ep; |
8d49e7ef VM |
1366 | |
1367 | gcc_assert (! final_p || ! first_p); | |
55a2c322 VM |
1368 | |
1369 | timevar_push (TV_LRA_ELIMINATE); | |
1370 | ||
8d49e7ef VM |
1371 | if (first_p) |
1372 | init_elimination (); | |
1373 | ||
55a2c322 VM |
1374 | bitmap_initialize (&insns_with_changed_offsets, ®_obstack); |
1375 | if (final_p) | |
1376 | { | |
b2b29377 MM |
1377 | if (flag_checking) |
1378 | { | |
1379 | update_reg_eliminate (&insns_with_changed_offsets); | |
1380 | gcc_assert (bitmap_empty_p (&insns_with_changed_offsets)); | |
1381 | } | |
55a2c322 VM |
1382 | /* We change eliminable hard registers in insns so we should do |
1383 | this for all insns containing any eliminable hard | |
1384 | register. */ | |
1385 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
1386 | if (elimination_map[ep->from] != NULL) | |
1387 | bitmap_ior_into (&insns_with_changed_offsets, | |
1388 | &lra_reg_info[ep->from].insn_bitmap); | |
1389 | } | |
5a107a0f VM |
1390 | else if (! update_reg_eliminate (&insns_with_changed_offsets)) |
1391 | goto lra_eliminate_done; | |
55a2c322 VM |
1392 | if (lra_dump_file != NULL) |
1393 | { | |
1394 | fprintf (lra_dump_file, "New elimination table:\n"); | |
1395 | print_elim_table (lra_dump_file); | |
1396 | } | |
55a2c322 | 1397 | EXECUTE_IF_SET_IN_BITMAP (&insns_with_changed_offsets, 0, uid, bi) |
80f466c4 VM |
1398 | /* A dead insn can be deleted in process_insn_for_elimination. */ |
1399 | if (lra_insn_recog_data[uid] != NULL) | |
8d49e7ef VM |
1400 | process_insn_for_elimination (lra_insn_recog_data[uid]->insn, |
1401 | final_p, first_p); | |
55a2c322 VM |
1402 | bitmap_clear (&insns_with_changed_offsets); |
1403 | ||
1404 | lra_eliminate_done: | |
1405 | timevar_pop (TV_LRA_ELIMINATE); | |
1406 | } |