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55a2c322 | 1 | /* Code for RTL register eliminations. |
5624e564 | 2 | Copyright (C) 2010-2015 Free Software Foundation, Inc. |
55a2c322 VM |
3 | Contributed by Vladimir Makarov <vmakarov@redhat.com>. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it under | |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 3, or (at your option) any later | |
10 | version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | /* Eliminable registers (like a soft argument or frame pointer) are | |
22 | widely used in RTL. These eliminable registers should be replaced | |
23 | by real hard registers (like the stack pointer or hard frame | |
24 | pointer) plus some offset. The offsets usually change whenever the | |
25 | stack is expanded. We know the final offsets only at the very end | |
26 | of LRA. | |
27 | ||
28 | Within LRA, we usually keep the RTL in such a state that the | |
29 | eliminable registers can be replaced by just the corresponding hard | |
30 | register (without any offset). To achieve this we should add the | |
31 | initial elimination offset at the beginning of LRA and update the | |
32 | offsets whenever the stack is expanded. We need to do this before | |
33 | every constraint pass because the choice of offset often affects | |
34 | whether a particular address or memory constraint is satisfied. | |
35 | ||
36 | We keep RTL code at most time in such state that the virtual | |
37 | registers can be changed by just the corresponding hard registers | |
38 | (with zero offsets) and we have the right RTL code. To achieve this | |
39 | we should add initial offset at the beginning of LRA work and update | |
40 | offsets after each stack expanding. But actually we update virtual | |
41 | registers to the same virtual registers + corresponding offsets | |
42 | before every constraint pass because it affects constraint | |
43 | satisfaction (e.g. an address displacement became too big for some | |
44 | target). | |
45 | ||
46 | The final change of eliminable registers to the corresponding hard | |
47 | registers are done at the very end of LRA when there were no change | |
48 | in offsets anymore: | |
49 | ||
50 | fp + 42 => sp + 42 | |
51 | ||
52 | */ | |
53 | ||
54 | #include "config.h" | |
55 | #include "system.h" | |
56 | #include "coretypes.h" | |
c7131fb2 | 57 | #include "backend.h" |
957060b5 | 58 | #include "target.h" |
55a2c322 | 59 | #include "rtl.h" |
957060b5 | 60 | #include "tree.h" |
c7131fb2 | 61 | #include "df.h" |
55a2c322 | 62 | #include "tm_p.h" |
957060b5 AM |
63 | #include "expmed.h" |
64 | #include "optabs.h" | |
55a2c322 | 65 | #include "regs.h" |
957060b5 | 66 | #include "ira.h" |
55a2c322 VM |
67 | #include "recog.h" |
68 | #include "output.h" | |
69 | #include "addresses.h" | |
36566b39 | 70 | #include "flags.h" |
36566b39 | 71 | #include "alias.h" |
36566b39 PK |
72 | #include "dojump.h" |
73 | #include "explow.h" | |
74 | #include "calls.h" | |
36566b39 PK |
75 | #include "varasm.h" |
76 | #include "stmt.h" | |
55a2c322 | 77 | #include "expr.h" |
55a2c322 | 78 | #include "except.h" |
55a2c322 | 79 | #include "rtl-error.h" |
c7131fb2 AM |
80 | #include "lra.h" |
81 | #include "insn-attr.h" | |
55a2c322 VM |
82 | #include "lra-int.h" |
83 | ||
84 | /* This structure is used to record information about hard register | |
85 | eliminations. */ | |
11478306 | 86 | struct lra_elim_table |
55a2c322 VM |
87 | { |
88 | /* Hard register number to be eliminated. */ | |
f4eafc30 | 89 | int from; |
55a2c322 | 90 | /* Hard register number used as replacement. */ |
f4eafc30 | 91 | int to; |
55a2c322 VM |
92 | /* Difference between values of the two hard registers above on |
93 | previous iteration. */ | |
94 | HOST_WIDE_INT previous_offset; | |
95 | /* Difference between the values on the current iteration. */ | |
f4eafc30 | 96 | HOST_WIDE_INT offset; |
55a2c322 | 97 | /* Nonzero if this elimination can be done. */ |
f4eafc30 | 98 | bool can_eliminate; |
55a2c322 VM |
99 | /* CAN_ELIMINATE since the last check. */ |
100 | bool prev_can_eliminate; | |
101 | /* REG rtx for the register to be eliminated. We cannot simply | |
102 | compare the number since we might then spuriously replace a hard | |
103 | register corresponding to a pseudo assigned to the reg to be | |
104 | eliminated. */ | |
f4eafc30 | 105 | rtx from_rtx; |
55a2c322 | 106 | /* REG rtx for the replacement. */ |
f4eafc30 | 107 | rtx to_rtx; |
55a2c322 VM |
108 | }; |
109 | ||
110 | /* The elimination table. Each array entry describes one possible way | |
111 | of eliminating a register in favor of another. If there is more | |
112 | than one way of eliminating a particular register, the most | |
113 | preferred should be specified first. */ | |
11478306 | 114 | static struct lra_elim_table *reg_eliminate = 0; |
55a2c322 VM |
115 | |
116 | /* This is an intermediate structure to initialize the table. It has | |
117 | exactly the members provided by ELIMINABLE_REGS. */ | |
118 | static const struct elim_table_1 | |
119 | { | |
120 | const int from; | |
121 | const int to; | |
122 | } reg_eliminate_1[] = | |
123 | ||
124 | /* If a set of eliminable hard registers was specified, define the | |
125 | table from it. Otherwise, default to the normal case of the frame | |
126 | pointer being replaced by the stack pointer. */ | |
127 | ||
128 | #ifdef ELIMINABLE_REGS | |
129 | ELIMINABLE_REGS; | |
130 | #else | |
131 | {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}; | |
132 | #endif | |
133 | ||
134 | #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1) | |
135 | ||
136 | /* Print info about elimination table to file F. */ | |
137 | static void | |
138 | print_elim_table (FILE *f) | |
139 | { | |
11478306 | 140 | struct lra_elim_table *ep; |
55a2c322 VM |
141 | |
142 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
143 | fprintf (f, "%s eliminate %d to %d (offset=" HOST_WIDE_INT_PRINT_DEC | |
144 | ", prev_offset=" HOST_WIDE_INT_PRINT_DEC ")\n", | |
145 | ep->can_eliminate ? "Can" : "Can't", | |
146 | ep->from, ep->to, ep->offset, ep->previous_offset); | |
147 | } | |
148 | ||
149 | /* Print info about elimination table to stderr. */ | |
150 | void | |
151 | lra_debug_elim_table (void) | |
152 | { | |
153 | print_elim_table (stderr); | |
154 | } | |
155 | ||
156 | /* Setup possibility of elimination in elimination table element EP to | |
157 | VALUE. Setup FRAME_POINTER_NEEDED if elimination from frame | |
158 | pointer to stack pointer is not possible anymore. */ | |
159 | static void | |
11478306 | 160 | setup_can_eliminate (struct lra_elim_table *ep, bool value) |
55a2c322 VM |
161 | { |
162 | ep->can_eliminate = ep->prev_can_eliminate = value; | |
163 | if (! value | |
164 | && ep->from == FRAME_POINTER_REGNUM && ep->to == STACK_POINTER_REGNUM) | |
165 | frame_pointer_needed = 1; | |
d303ff97 L |
166 | if (!frame_pointer_needed) |
167 | REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = 0; | |
55a2c322 VM |
168 | } |
169 | ||
170 | /* Map: eliminable "from" register -> its current elimination, | |
171 | or NULL if none. The elimination table may contain more than | |
172 | one elimination for the same hard register, but this map specifies | |
173 | the one that we are currently using. */ | |
11478306 | 174 | static struct lra_elim_table *elimination_map[FIRST_PSEUDO_REGISTER]; |
55a2c322 VM |
175 | |
176 | /* When an eliminable hard register becomes not eliminable, we use the | |
177 | following special structure to restore original offsets for the | |
178 | register. */ | |
11478306 | 179 | static struct lra_elim_table self_elim_table; |
55a2c322 VM |
180 | |
181 | /* Offsets should be used to restore original offsets for eliminable | |
182 | hard register which just became not eliminable. Zero, | |
183 | otherwise. */ | |
184 | static HOST_WIDE_INT self_elim_offsets[FIRST_PSEUDO_REGISTER]; | |
185 | ||
186 | /* Map: hard regno -> RTL presentation. RTL presentations of all | |
187 | potentially eliminable hard registers are stored in the map. */ | |
188 | static rtx eliminable_reg_rtx[FIRST_PSEUDO_REGISTER]; | |
189 | ||
190 | /* Set up ELIMINATION_MAP of the currently used eliminations. */ | |
191 | static void | |
192 | setup_elimination_map (void) | |
193 | { | |
194 | int i; | |
11478306 | 195 | struct lra_elim_table *ep; |
55a2c322 VM |
196 | |
197 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
198 | elimination_map[i] = NULL; | |
199 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
200 | if (ep->can_eliminate && elimination_map[ep->from] == NULL) | |
201 | elimination_map[ep->from] = ep; | |
202 | } | |
203 | ||
204 | \f | |
205 | ||
206 | /* Compute the sum of X and Y, making canonicalizations assumed in an | |
207 | address, namely: sum constant integers, surround the sum of two | |
208 | constants with a CONST, put the constant as the second operand, and | |
209 | group the constant on the outermost sum. | |
210 | ||
211 | This routine assumes both inputs are already in canonical form. */ | |
212 | static rtx | |
213 | form_sum (rtx x, rtx y) | |
214 | { | |
ef4bddc2 | 215 | machine_mode mode = GET_MODE (x); |
55a2c322 VM |
216 | |
217 | if (mode == VOIDmode) | |
218 | mode = GET_MODE (y); | |
219 | ||
220 | if (mode == VOIDmode) | |
221 | mode = Pmode; | |
222 | ||
223 | if (CONST_INT_P (x)) | |
224 | return plus_constant (mode, y, INTVAL (x)); | |
225 | else if (CONST_INT_P (y)) | |
226 | return plus_constant (mode, x, INTVAL (y)); | |
227 | else if (CONSTANT_P (x)) | |
4e1952ab | 228 | std::swap (x, y); |
55a2c322 VM |
229 | |
230 | if (GET_CODE (x) == PLUS && CONSTANT_P (XEXP (x, 1))) | |
231 | return form_sum (XEXP (x, 0), form_sum (XEXP (x, 1), y)); | |
232 | ||
233 | /* Note that if the operands of Y are specified in the opposite | |
234 | order in the recursive calls below, infinite recursion will | |
235 | occur. */ | |
236 | if (GET_CODE (y) == PLUS && CONSTANT_P (XEXP (y, 1))) | |
237 | return form_sum (form_sum (x, XEXP (y, 0)), XEXP (y, 1)); | |
238 | ||
239 | /* If both constant, encapsulate sum. Otherwise, just form sum. A | |
240 | constant will have been placed second. */ | |
241 | if (CONSTANT_P (x) && CONSTANT_P (y)) | |
242 | { | |
243 | if (GET_CODE (x) == CONST) | |
244 | x = XEXP (x, 0); | |
245 | if (GET_CODE (y) == CONST) | |
246 | y = XEXP (y, 0); | |
247 | ||
248 | return gen_rtx_CONST (VOIDmode, gen_rtx_PLUS (mode, x, y)); | |
249 | } | |
250 | ||
251 | return gen_rtx_PLUS (mode, x, y); | |
252 | } | |
253 | ||
254 | /* Return the current substitution hard register of the elimination of | |
255 | HARD_REGNO. If HARD_REGNO is not eliminable, return itself. */ | |
256 | int | |
257 | lra_get_elimination_hard_regno (int hard_regno) | |
258 | { | |
11478306 | 259 | struct lra_elim_table *ep; |
55a2c322 VM |
260 | |
261 | if (hard_regno < 0 || hard_regno >= FIRST_PSEUDO_REGISTER) | |
262 | return hard_regno; | |
263 | if ((ep = elimination_map[hard_regno]) == NULL) | |
264 | return hard_regno; | |
265 | return ep->to; | |
266 | } | |
267 | ||
268 | /* Return elimination which will be used for hard reg REG, NULL | |
269 | otherwise. */ | |
11478306 | 270 | static struct lra_elim_table * |
55a2c322 VM |
271 | get_elimination (rtx reg) |
272 | { | |
273 | int hard_regno; | |
11478306 | 274 | struct lra_elim_table *ep; |
55a2c322 VM |
275 | HOST_WIDE_INT offset; |
276 | ||
277 | lra_assert (REG_P (reg)); | |
278 | if ((hard_regno = REGNO (reg)) < 0 || hard_regno >= FIRST_PSEUDO_REGISTER) | |
279 | return NULL; | |
280 | if ((ep = elimination_map[hard_regno]) != NULL) | |
281 | return ep->from_rtx != reg ? NULL : ep; | |
282 | if ((offset = self_elim_offsets[hard_regno]) == 0) | |
283 | return NULL; | |
284 | /* This is an iteration to restore offsets just after HARD_REGNO | |
285 | stopped to be eliminable. */ | |
286 | self_elim_table.from = self_elim_table.to = hard_regno; | |
287 | self_elim_table.from_rtx | |
288 | = self_elim_table.to_rtx | |
289 | = eliminable_reg_rtx[hard_regno]; | |
290 | lra_assert (self_elim_table.from_rtx != NULL); | |
291 | self_elim_table.offset = offset; | |
292 | return &self_elim_table; | |
293 | } | |
294 | ||
295 | /* Scan X and replace any eliminable registers (such as fp) with a | |
8d49e7ef | 296 | replacement (such as sp) if SUBST_P, plus an offset. The offset is |
55a2c322 VM |
297 | a change in the offset between the eliminable register and its |
298 | substitution if UPDATE_P, or the full offset if FULL_P, or | |
8d49e7ef | 299 | otherwise zero. If FULL_P, we also use the SP offsets for |
d9cf932c | 300 | elimination to SP. If UPDATE_P, use UPDATE_SP_OFFSET for updating |
a6af1bf9 VM |
301 | offsets of register elimnable to SP. If UPDATE_SP_OFFSET is |
302 | non-zero, don't use difference of the offset and the previous | |
303 | offset. | |
55a2c322 VM |
304 | |
305 | MEM_MODE is the mode of an enclosing MEM. We need this to know how | |
306 | much to adjust a register for, e.g., PRE_DEC. Also, if we are | |
307 | inside a MEM, we are allowed to replace a sum of a hard register | |
308 | and the constant zero with the hard register, which we cannot do | |
309 | outside a MEM. In addition, we need to record the fact that a | |
310 | hard register is referenced outside a MEM. | |
311 | ||
8d49e7ef VM |
312 | If we make full substitution to SP for non-null INSN, add the insn |
313 | sp offset. */ | |
55a2c322 | 314 | rtx |
ef4bddc2 | 315 | lra_eliminate_regs_1 (rtx_insn *insn, rtx x, machine_mode mem_mode, |
d9cf932c VM |
316 | bool subst_p, bool update_p, |
317 | HOST_WIDE_INT update_sp_offset, bool full_p) | |
55a2c322 VM |
318 | { |
319 | enum rtx_code code = GET_CODE (x); | |
11478306 | 320 | struct lra_elim_table *ep; |
55a2c322 VM |
321 | rtx new_rtx; |
322 | int i, j; | |
323 | const char *fmt; | |
324 | int copied = 0; | |
325 | ||
a6af1bf9 VM |
326 | lra_assert (!update_p || !full_p); |
327 | lra_assert (update_sp_offset == 0 || (!subst_p && update_p && !full_p)); | |
55a2c322 VM |
328 | if (! current_function_decl) |
329 | return x; | |
330 | ||
331 | switch (code) | |
332 | { | |
333 | CASE_CONST_ANY: | |
334 | case CONST: | |
335 | case SYMBOL_REF: | |
336 | case CODE_LABEL: | |
337 | case PC: | |
338 | case CC0: | |
339 | case ASM_INPUT: | |
340 | case ADDR_VEC: | |
341 | case ADDR_DIFF_VEC: | |
342 | case RETURN: | |
343 | return x; | |
344 | ||
345 | case REG: | |
346 | /* First handle the case where we encounter a bare hard register | |
347 | that is eliminable. Replace it with a PLUS. */ | |
348 | if ((ep = get_elimination (x)) != NULL) | |
349 | { | |
350 | rtx to = subst_p ? ep->to_rtx : ep->from_rtx; | |
f4eafc30 | 351 | |
a6af1bf9 VM |
352 | if (update_sp_offset != 0) |
353 | { | |
354 | if (ep->to_rtx == stack_pointer_rtx) | |
355 | return plus_constant (Pmode, to, update_sp_offset); | |
356 | return to; | |
357 | } | |
358 | else if (update_p) | |
359 | return plus_constant (Pmode, to, ep->offset - ep->previous_offset); | |
55a2c322 | 360 | else if (full_p) |
8d49e7ef VM |
361 | return plus_constant (Pmode, to, |
362 | ep->offset | |
363 | - (insn != NULL_RTX | |
364 | && ep->to_rtx == stack_pointer_rtx | |
365 | ? lra_get_insn_recog_data (insn)->sp_offset | |
366 | : 0)); | |
55a2c322 VM |
367 | else |
368 | return to; | |
369 | } | |
370 | return x; | |
371 | ||
372 | case PLUS: | |
373 | /* If this is the sum of an eliminable register and a constant, rework | |
374 | the sum. */ | |
375 | if (REG_P (XEXP (x, 0)) && CONSTANT_P (XEXP (x, 1))) | |
376 | { | |
377 | if ((ep = get_elimination (XEXP (x, 0))) != NULL) | |
378 | { | |
379 | HOST_WIDE_INT offset; | |
380 | rtx to = subst_p ? ep->to_rtx : ep->from_rtx; | |
f4eafc30 | 381 | |
55a2c322 VM |
382 | if (! update_p && ! full_p) |
383 | return gen_rtx_PLUS (Pmode, to, XEXP (x, 1)); | |
a6af1bf9 VM |
384 | |
385 | if (update_sp_offset != 0) | |
386 | offset = ep->to_rtx == stack_pointer_rtx ? update_sp_offset : 0; | |
387 | else | |
388 | offset = (update_p | |
389 | ? ep->offset - ep->previous_offset : ep->offset); | |
8d49e7ef VM |
390 | if (full_p && insn != NULL_RTX && ep->to_rtx == stack_pointer_rtx) |
391 | offset -= lra_get_insn_recog_data (insn)->sp_offset; | |
a6af1bf9 | 392 | if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) == -offset) |
55a2c322 VM |
393 | return to; |
394 | else | |
395 | return gen_rtx_PLUS (Pmode, to, | |
396 | plus_constant (Pmode, | |
397 | XEXP (x, 1), offset)); | |
398 | } | |
399 | ||
400 | /* If the hard register is not eliminable, we are done since | |
401 | the other operand is a constant. */ | |
402 | return x; | |
403 | } | |
404 | ||
405 | /* If this is part of an address, we want to bring any constant | |
406 | to the outermost PLUS. We will do this by doing hard | |
407 | register replacement in our operands and seeing if a constant | |
408 | shows up in one of them. | |
409 | ||
410 | Note that there is no risk of modifying the structure of the | |
411 | insn, since we only get called for its operands, thus we are | |
412 | either modifying the address inside a MEM, or something like | |
413 | an address operand of a load-address insn. */ | |
414 | ||
415 | { | |
8d49e7ef | 416 | rtx new0 = lra_eliminate_regs_1 (insn, XEXP (x, 0), mem_mode, |
d9cf932c VM |
417 | subst_p, update_p, |
418 | update_sp_offset, full_p); | |
8d49e7ef | 419 | rtx new1 = lra_eliminate_regs_1 (insn, XEXP (x, 1), mem_mode, |
d9cf932c VM |
420 | subst_p, update_p, |
421 | update_sp_offset, full_p); | |
55a2c322 VM |
422 | |
423 | if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)) | |
424 | return form_sum (new0, new1); | |
425 | } | |
426 | return x; | |
427 | ||
428 | case MULT: | |
429 | /* If this is the product of an eliminable hard register and a | |
430 | constant, apply the distribute law and move the constant out | |
431 | so that we have (plus (mult ..) ..). This is needed in order | |
432 | to keep load-address insns valid. This case is pathological. | |
433 | We ignore the possibility of overflow here. */ | |
434 | if (REG_P (XEXP (x, 0)) && CONST_INT_P (XEXP (x, 1)) | |
435 | && (ep = get_elimination (XEXP (x, 0))) != NULL) | |
436 | { | |
437 | rtx to = subst_p ? ep->to_rtx : ep->from_rtx; | |
f4eafc30 | 438 | |
a6af1bf9 VM |
439 | if (update_sp_offset != 0) |
440 | { | |
441 | if (ep->to_rtx == stack_pointer_rtx) | |
442 | return plus_constant (Pmode, | |
443 | gen_rtx_MULT (Pmode, to, XEXP (x, 1)), | |
444 | update_sp_offset * INTVAL (XEXP (x, 1))); | |
445 | return gen_rtx_MULT (Pmode, to, XEXP (x, 1)); | |
446 | } | |
447 | else if (update_p) | |
d9cf932c VM |
448 | return plus_constant (Pmode, |
449 | gen_rtx_MULT (Pmode, to, XEXP (x, 1)), | |
a6af1bf9 | 450 | (ep->offset - ep->previous_offset) |
d9cf932c | 451 | * INTVAL (XEXP (x, 1))); |
55a2c322 | 452 | else if (full_p) |
8d49e7ef VM |
453 | { |
454 | HOST_WIDE_INT offset = ep->offset; | |
455 | ||
456 | if (insn != NULL_RTX && ep->to_rtx == stack_pointer_rtx) | |
457 | offset -= lra_get_insn_recog_data (insn)->sp_offset; | |
458 | return | |
459 | plus_constant (Pmode, | |
460 | gen_rtx_MULT (Pmode, to, XEXP (x, 1)), | |
461 | offset * INTVAL (XEXP (x, 1))); | |
462 | } | |
55a2c322 VM |
463 | else |
464 | return gen_rtx_MULT (Pmode, to, XEXP (x, 1)); | |
465 | } | |
f4eafc30 | 466 | |
55a2c322 VM |
467 | /* ... fall through ... */ |
468 | ||
469 | case CALL: | |
470 | case COMPARE: | |
471 | /* See comments before PLUS about handling MINUS. */ | |
472 | case MINUS: | |
473 | case DIV: case UDIV: | |
474 | case MOD: case UMOD: | |
475 | case AND: case IOR: case XOR: | |
476 | case ROTATERT: case ROTATE: | |
477 | case ASHIFTRT: case LSHIFTRT: case ASHIFT: | |
478 | case NE: case EQ: | |
479 | case GE: case GT: case GEU: case GTU: | |
480 | case LE: case LT: case LEU: case LTU: | |
481 | { | |
8d49e7ef | 482 | rtx new0 = lra_eliminate_regs_1 (insn, XEXP (x, 0), mem_mode, |
d9cf932c VM |
483 | subst_p, update_p, |
484 | update_sp_offset, full_p); | |
55a2c322 | 485 | rtx new1 = XEXP (x, 1) |
8d49e7ef | 486 | ? lra_eliminate_regs_1 (insn, XEXP (x, 1), mem_mode, |
d9cf932c VM |
487 | subst_p, update_p, |
488 | update_sp_offset, full_p) : 0; | |
55a2c322 VM |
489 | |
490 | if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)) | |
491 | return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1); | |
492 | } | |
493 | return x; | |
494 | ||
495 | case EXPR_LIST: | |
496 | /* If we have something in XEXP (x, 0), the usual case, | |
497 | eliminate it. */ | |
498 | if (XEXP (x, 0)) | |
499 | { | |
8d49e7ef | 500 | new_rtx = lra_eliminate_regs_1 (insn, XEXP (x, 0), mem_mode, |
d9cf932c VM |
501 | subst_p, update_p, |
502 | update_sp_offset, full_p); | |
55a2c322 VM |
503 | if (new_rtx != XEXP (x, 0)) |
504 | { | |
505 | /* If this is a REG_DEAD note, it is not valid anymore. | |
506 | Using the eliminated version could result in creating a | |
507 | REG_DEAD note for the stack or frame pointer. */ | |
508 | if (REG_NOTE_KIND (x) == REG_DEAD) | |
509 | return (XEXP (x, 1) | |
8d49e7ef | 510 | ? lra_eliminate_regs_1 (insn, XEXP (x, 1), mem_mode, |
d9cf932c VM |
511 | subst_p, update_p, |
512 | update_sp_offset, full_p) | |
55a2c322 VM |
513 | : NULL_RTX); |
514 | ||
515 | x = alloc_reg_note (REG_NOTE_KIND (x), new_rtx, XEXP (x, 1)); | |
516 | } | |
517 | } | |
518 | ||
519 | /* ... fall through ... */ | |
520 | ||
521 | case INSN_LIST: | |
f91aec98 | 522 | case INT_LIST: |
55a2c322 VM |
523 | /* Now do eliminations in the rest of the chain. If this was |
524 | an EXPR_LIST, this might result in allocating more memory than is | |
525 | strictly needed, but it simplifies the code. */ | |
526 | if (XEXP (x, 1)) | |
527 | { | |
8d49e7ef | 528 | new_rtx = lra_eliminate_regs_1 (insn, XEXP (x, 1), mem_mode, |
d9cf932c VM |
529 | subst_p, update_p, |
530 | update_sp_offset, full_p); | |
55a2c322 VM |
531 | if (new_rtx != XEXP (x, 1)) |
532 | return | |
533 | gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), | |
534 | XEXP (x, 0), new_rtx); | |
535 | } | |
536 | return x; | |
537 | ||
538 | case PRE_INC: | |
539 | case POST_INC: | |
540 | case PRE_DEC: | |
541 | case POST_DEC: | |
542 | /* We do not support elimination of a register that is modified. | |
543 | elimination_effects has already make sure that this does not | |
544 | happen. */ | |
545 | return x; | |
546 | ||
547 | case PRE_MODIFY: | |
548 | case POST_MODIFY: | |
549 | /* We do not support elimination of a hard register that is | |
550 | modified. LRA has already make sure that this does not | |
551 | happen. The only remaining case we need to consider here is | |
552 | that the increment value may be an eliminable register. */ | |
553 | if (GET_CODE (XEXP (x, 1)) == PLUS | |
554 | && XEXP (XEXP (x, 1), 0) == XEXP (x, 0)) | |
555 | { | |
8d49e7ef | 556 | rtx new_rtx = lra_eliminate_regs_1 (insn, XEXP (XEXP (x, 1), 1), |
d9cf932c VM |
557 | mem_mode, subst_p, update_p, |
558 | update_sp_offset, full_p); | |
55a2c322 VM |
559 | |
560 | if (new_rtx != XEXP (XEXP (x, 1), 1)) | |
561 | return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0), | |
562 | gen_rtx_PLUS (GET_MODE (x), | |
563 | XEXP (x, 0), new_rtx)); | |
564 | } | |
565 | return x; | |
566 | ||
567 | case STRICT_LOW_PART: | |
568 | case NEG: case NOT: | |
569 | case SIGN_EXTEND: case ZERO_EXTEND: | |
570 | case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: | |
571 | case FLOAT: case FIX: | |
572 | case UNSIGNED_FIX: case UNSIGNED_FLOAT: | |
573 | case ABS: | |
574 | case SQRT: | |
575 | case FFS: | |
576 | case CLZ: | |
577 | case CTZ: | |
578 | case POPCOUNT: | |
579 | case PARITY: | |
580 | case BSWAP: | |
8d49e7ef | 581 | new_rtx = lra_eliminate_regs_1 (insn, XEXP (x, 0), mem_mode, |
d9cf932c VM |
582 | subst_p, update_p, |
583 | update_sp_offset, full_p); | |
55a2c322 VM |
584 | if (new_rtx != XEXP (x, 0)) |
585 | return gen_rtx_fmt_e (code, GET_MODE (x), new_rtx); | |
586 | return x; | |
587 | ||
588 | case SUBREG: | |
8d49e7ef | 589 | new_rtx = lra_eliminate_regs_1 (insn, SUBREG_REG (x), mem_mode, |
d9cf932c VM |
590 | subst_p, update_p, |
591 | update_sp_offset, full_p); | |
55a2c322 VM |
592 | |
593 | if (new_rtx != SUBREG_REG (x)) | |
594 | { | |
595 | int x_size = GET_MODE_SIZE (GET_MODE (x)); | |
596 | int new_size = GET_MODE_SIZE (GET_MODE (new_rtx)); | |
597 | ||
598 | if (MEM_P (new_rtx) && x_size <= new_size) | |
599 | { | |
600 | SUBREG_REG (x) = new_rtx; | |
601 | alter_subreg (&x, false); | |
602 | return x; | |
603 | } | |
b17ec42d VM |
604 | else if (! subst_p) |
605 | { | |
606 | /* LRA can transform subregs itself. So don't call | |
607 | simplify_gen_subreg until LRA transformations are | |
608 | finished. Function simplify_gen_subreg can do | |
609 | non-trivial transformations (like truncation) which | |
610 | might make LRA work to fail. */ | |
611 | SUBREG_REG (x) = new_rtx; | |
612 | return x; | |
613 | } | |
55a2c322 | 614 | else |
baa061be RS |
615 | return simplify_gen_subreg (GET_MODE (x), new_rtx, |
616 | GET_MODE (new_rtx), SUBREG_BYTE (x)); | |
55a2c322 VM |
617 | } |
618 | ||
619 | return x; | |
620 | ||
621 | case MEM: | |
622 | /* Our only special processing is to pass the mode of the MEM to our | |
623 | recursive call and copy the flags. While we are here, handle this | |
624 | case more efficiently. */ | |
625 | return | |
626 | replace_equiv_address_nv | |
627 | (x, | |
8d49e7ef | 628 | lra_eliminate_regs_1 (insn, XEXP (x, 0), GET_MODE (x), |
d9cf932c | 629 | subst_p, update_p, update_sp_offset, full_p)); |
55a2c322 VM |
630 | |
631 | case USE: | |
632 | /* Handle insn_list USE that a call to a pure function may generate. */ | |
8d49e7ef | 633 | new_rtx = lra_eliminate_regs_1 (insn, XEXP (x, 0), VOIDmode, |
d9cf932c | 634 | subst_p, update_p, update_sp_offset, full_p); |
55a2c322 VM |
635 | if (new_rtx != XEXP (x, 0)) |
636 | return gen_rtx_USE (GET_MODE (x), new_rtx); | |
637 | return x; | |
638 | ||
639 | case CLOBBER: | |
640 | case SET: | |
641 | gcc_unreachable (); | |
642 | ||
643 | default: | |
644 | break; | |
645 | } | |
646 | ||
647 | /* Process each of our operands recursively. If any have changed, make a | |
648 | copy of the rtx. */ | |
649 | fmt = GET_RTX_FORMAT (code); | |
650 | for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) | |
651 | { | |
652 | if (*fmt == 'e') | |
653 | { | |
8d49e7ef | 654 | new_rtx = lra_eliminate_regs_1 (insn, XEXP (x, i), mem_mode, |
d9cf932c VM |
655 | subst_p, update_p, |
656 | update_sp_offset, full_p); | |
55a2c322 VM |
657 | if (new_rtx != XEXP (x, i) && ! copied) |
658 | { | |
659 | x = shallow_copy_rtx (x); | |
660 | copied = 1; | |
661 | } | |
662 | XEXP (x, i) = new_rtx; | |
663 | } | |
664 | else if (*fmt == 'E') | |
665 | { | |
666 | int copied_vec = 0; | |
667 | for (j = 0; j < XVECLEN (x, i); j++) | |
668 | { | |
8d49e7ef | 669 | new_rtx = lra_eliminate_regs_1 (insn, XVECEXP (x, i, j), mem_mode, |
d9cf932c VM |
670 | subst_p, update_p, |
671 | update_sp_offset, full_p); | |
55a2c322 VM |
672 | if (new_rtx != XVECEXP (x, i, j) && ! copied_vec) |
673 | { | |
674 | rtvec new_v = gen_rtvec_v (XVECLEN (x, i), | |
675 | XVEC (x, i)->elem); | |
676 | if (! copied) | |
677 | { | |
678 | x = shallow_copy_rtx (x); | |
679 | copied = 1; | |
680 | } | |
681 | XVEC (x, i) = new_v; | |
682 | copied_vec = 1; | |
683 | } | |
684 | XVECEXP (x, i, j) = new_rtx; | |
685 | } | |
686 | } | |
687 | } | |
688 | ||
689 | return x; | |
690 | } | |
691 | ||
692 | /* This function is used externally in subsequent passes of GCC. It | |
693 | always does a full elimination of X. */ | |
694 | rtx | |
ef4bddc2 | 695 | lra_eliminate_regs (rtx x, machine_mode mem_mode, |
55a2c322 VM |
696 | rtx insn ATTRIBUTE_UNUSED) |
697 | { | |
d9cf932c | 698 | return lra_eliminate_regs_1 (NULL, x, mem_mode, true, false, 0, true); |
55a2c322 VM |
699 | } |
700 | ||
8d49e7ef VM |
701 | /* Stack pointer offset before the current insn relative to one at the |
702 | func start. RTL insns can change SP explicitly. We keep the | |
703 | changes from one insn to another through this variable. */ | |
704 | static HOST_WIDE_INT curr_sp_change; | |
705 | ||
55a2c322 VM |
706 | /* Scan rtx X for references to elimination source or target registers |
707 | in contexts that would prevent the elimination from happening. | |
708 | Update the table of eliminables to reflect the changed state. | |
709 | MEM_MODE is the mode of an enclosing MEM rtx, or VOIDmode if not | |
710 | within a MEM. */ | |
711 | static void | |
ef4bddc2 | 712 | mark_not_eliminable (rtx x, machine_mode mem_mode) |
55a2c322 VM |
713 | { |
714 | enum rtx_code code = GET_CODE (x); | |
11478306 | 715 | struct lra_elim_table *ep; |
55a2c322 VM |
716 | int i, j; |
717 | const char *fmt; | |
718 | ||
719 | switch (code) | |
720 | { | |
721 | case PRE_INC: | |
722 | case POST_INC: | |
723 | case PRE_DEC: | |
724 | case POST_DEC: | |
725 | case POST_MODIFY: | |
726 | case PRE_MODIFY: | |
8d49e7ef VM |
727 | if (XEXP (x, 0) == stack_pointer_rtx |
728 | && ((code != PRE_MODIFY && code != POST_MODIFY) | |
729 | || (GET_CODE (XEXP (x, 1)) == PLUS | |
730 | && XEXP (x, 0) == XEXP (XEXP (x, 1), 0) | |
731 | && CONST_INT_P (XEXP (XEXP (x, 1), 1))))) | |
732 | { | |
733 | int size = GET_MODE_SIZE (mem_mode); | |
734 | ||
735 | #ifdef PUSH_ROUNDING | |
736 | /* If more bytes than MEM_MODE are pushed, account for | |
737 | them. */ | |
738 | size = PUSH_ROUNDING (size); | |
739 | #endif | |
740 | if (code == PRE_DEC || code == POST_DEC) | |
741 | curr_sp_change -= size; | |
742 | else if (code == PRE_INC || code == POST_INC) | |
743 | curr_sp_change += size; | |
744 | else if (code == PRE_MODIFY || code == POST_MODIFY) | |
745 | curr_sp_change += INTVAL (XEXP (XEXP (x, 1), 1)); | |
746 | } | |
747 | else if (REG_P (XEXP (x, 0)) | |
748 | && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER) | |
749 | { | |
750 | /* If we modify the source of an elimination rule, disable | |
751 | it. Do the same if it is the destination and not the | |
752 | hard frame register. */ | |
753 | for (ep = reg_eliminate; | |
754 | ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
55a2c322 | 755 | ep++) |
8d49e7ef VM |
756 | if (ep->from_rtx == XEXP (x, 0) |
757 | || (ep->to_rtx == XEXP (x, 0) | |
758 | && ep->to_rtx != hard_frame_pointer_rtx)) | |
759 | setup_can_eliminate (ep, false); | |
760 | } | |
55a2c322 VM |
761 | return; |
762 | ||
763 | case USE: | |
764 | if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER) | |
765 | /* If using a hard register that is the source of an eliminate | |
766 | we still think can be performed, note it cannot be | |
767 | performed since we don't know how this hard register is | |
768 | used. */ | |
769 | for (ep = reg_eliminate; | |
770 | ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
771 | ep++) | |
772 | if (ep->from_rtx == XEXP (x, 0) | |
773 | && ep->to_rtx != hard_frame_pointer_rtx) | |
774 | setup_can_eliminate (ep, false); | |
775 | return; | |
776 | ||
777 | case CLOBBER: | |
778 | if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER) | |
779 | /* If clobbering a hard register that is the replacement | |
780 | register for an elimination we still think can be | |
781 | performed, note that it cannot be performed. Otherwise, we | |
782 | need not be concerned about it. */ | |
783 | for (ep = reg_eliminate; | |
784 | ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
785 | ep++) | |
786 | if (ep->to_rtx == XEXP (x, 0) | |
787 | && ep->to_rtx != hard_frame_pointer_rtx) | |
788 | setup_can_eliminate (ep, false); | |
789 | return; | |
790 | ||
791 | case SET: | |
8d49e7ef VM |
792 | if (SET_DEST (x) == stack_pointer_rtx |
793 | && GET_CODE (SET_SRC (x)) == PLUS | |
794 | && XEXP (SET_SRC (x), 0) == SET_DEST (x) | |
795 | && CONST_INT_P (XEXP (SET_SRC (x), 1))) | |
796 | { | |
797 | curr_sp_change += INTVAL (XEXP (SET_SRC (x), 1)); | |
798 | return; | |
799 | } | |
800 | if (! REG_P (SET_DEST (x)) | |
801 | || REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER) | |
802 | mark_not_eliminable (SET_DEST (x), mem_mode); | |
803 | else | |
55a2c322 VM |
804 | { |
805 | /* See if this is setting the replacement hard register for | |
806 | an elimination. | |
8d49e7ef | 807 | |
55a2c322 VM |
808 | If DEST is the hard frame pointer, we do nothing because |
809 | we assume that all assignments to the frame pointer are | |
810 | for non-local gotos and are being done at a time when | |
811 | they are valid and do not disturb anything else. Some | |
812 | machines want to eliminate a fake argument pointer (or | |
813 | even a fake frame pointer) with either the real frame | |
814 | pointer or the stack pointer. Assignments to the hard | |
815 | frame pointer must not prevent this elimination. */ | |
55a2c322 VM |
816 | for (ep = reg_eliminate; |
817 | ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
818 | ep++) | |
819 | if (ep->to_rtx == SET_DEST (x) | |
8d49e7ef | 820 | && SET_DEST (x) != hard_frame_pointer_rtx) |
55a2c322 VM |
821 | setup_can_eliminate (ep, false); |
822 | } | |
8d49e7ef VM |
823 | |
824 | mark_not_eliminable (SET_SRC (x), mem_mode); | |
825 | return; | |
55a2c322 | 826 | |
8d49e7ef VM |
827 | case MEM: |
828 | /* Our only special processing is to pass the mode of the MEM to | |
829 | our recursive call. */ | |
830 | mark_not_eliminable (XEXP (x, 0), GET_MODE (x)); | |
55a2c322 VM |
831 | return; |
832 | ||
833 | default: | |
834 | break; | |
835 | } | |
836 | ||
837 | fmt = GET_RTX_FORMAT (code); | |
838 | for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) | |
839 | { | |
840 | if (*fmt == 'e') | |
8d49e7ef | 841 | mark_not_eliminable (XEXP (x, i), mem_mode); |
55a2c322 VM |
842 | else if (*fmt == 'E') |
843 | for (j = 0; j < XVECLEN (x, i); j++) | |
8d49e7ef | 844 | mark_not_eliminable (XVECEXP (x, i, j), mem_mode); |
55a2c322 VM |
845 | } |
846 | } | |
847 | ||
848 | \f | |
849 | ||
ecafcf05 VM |
850 | #ifdef HARD_FRAME_POINTER_REGNUM |
851 | ||
852 | /* Find offset equivalence note for reg WHAT in INSN and return the | |
853 | found elmination offset. If the note is not found, return NULL. | |
854 | Remove the found note. */ | |
855 | static rtx | |
8c797f81 | 856 | remove_reg_equal_offset_note (rtx_insn *insn, rtx what) |
ecafcf05 VM |
857 | { |
858 | rtx link, *link_loc; | |
859 | ||
860 | for (link_loc = ®_NOTES (insn); | |
861 | (link = *link_loc) != NULL_RTX; | |
862 | link_loc = &XEXP (link, 1)) | |
863 | if (REG_NOTE_KIND (link) == REG_EQUAL | |
864 | && GET_CODE (XEXP (link, 0)) == PLUS | |
865 | && XEXP (XEXP (link, 0), 0) == what | |
866 | && CONST_INT_P (XEXP (XEXP (link, 0), 1))) | |
867 | { | |
868 | *link_loc = XEXP (link, 1); | |
869 | return XEXP (XEXP (link, 0), 1); | |
870 | } | |
871 | return NULL_RTX; | |
872 | } | |
873 | ||
874 | #endif | |
875 | ||
55a2c322 VM |
876 | /* Scan INSN and eliminate all eliminable hard registers in it. |
877 | ||
878 | If REPLACE_P is true, do the replacement destructively. Also | |
879 | delete the insn as dead it if it is setting an eliminable register. | |
880 | ||
881 | If REPLACE_P is false, just update the offsets while keeping the | |
8d49e7ef | 882 | base register the same. If FIRST_P, use the sp offset for |
a6af1bf9 VM |
883 | elimination to sp. Otherwise, use UPDATE_SP_OFFSET for this. If |
884 | UPDATE_SP_OFFSET is non-zero, don't use difference of the offset | |
885 | and the previous offset. Attach the note about used elimination | |
886 | for insns setting frame pointer to update elimination easy (without | |
887 | parsing already generated elimination insns to find offset | |
888 | previously used) in future. */ | |
55a2c322 | 889 | |
d9cf932c VM |
890 | void |
891 | eliminate_regs_in_insn (rtx_insn *insn, bool replace_p, bool first_p, | |
892 | HOST_WIDE_INT update_sp_offset) | |
55a2c322 VM |
893 | { |
894 | int icode = recog_memoized (insn); | |
895 | rtx old_set = single_set (insn); | |
896 | bool validate_p; | |
897 | int i; | |
898 | rtx substed_operand[MAX_RECOG_OPERANDS]; | |
899 | rtx orig_operand[MAX_RECOG_OPERANDS]; | |
11478306 | 900 | struct lra_elim_table *ep; |
55a2c322 VM |
901 | rtx plus_src, plus_cst_src; |
902 | lra_insn_recog_data_t id; | |
903 | struct lra_static_insn_data *static_id; | |
904 | ||
905 | if (icode < 0 && asm_noperands (PATTERN (insn)) < 0 && ! DEBUG_INSN_P (insn)) | |
906 | { | |
39718607 | 907 | lra_assert (GET_CODE (PATTERN (insn)) == USE |
55a2c322 | 908 | || GET_CODE (PATTERN (insn)) == CLOBBER |
55a2c322 VM |
909 | || GET_CODE (PATTERN (insn)) == ASM_INPUT); |
910 | return; | |
911 | } | |
912 | ||
913 | /* Check for setting an eliminable register. */ | |
914 | if (old_set != 0 && REG_P (SET_DEST (old_set)) | |
915 | && (ep = get_elimination (SET_DEST (old_set))) != NULL) | |
916 | { | |
80f466c4 VM |
917 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
918 | if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate) | |
919 | { | |
920 | bool delete_p = replace_p; | |
921 | ||
55a2c322 | 922 | #ifdef HARD_FRAME_POINTER_REGNUM |
80f466c4 VM |
923 | if (ep->from == FRAME_POINTER_REGNUM |
924 | && ep->to == HARD_FRAME_POINTER_REGNUM) | |
925 | /* If this is setting the frame pointer register to the | |
926 | hardware frame pointer register and this is an | |
927 | elimination that will be done (tested above), this | |
928 | insn is really adjusting the frame pointer downward | |
929 | to compensate for the adjustment done before a | |
930 | nonlocal goto. */ | |
931 | { | |
932 | rtx src = SET_SRC (old_set); | |
933 | rtx off = remove_reg_equal_offset_note (insn, ep->to_rtx); | |
934 | ||
a6af1bf9 VM |
935 | /* We should never process such insn with non-zero |
936 | UPDATE_SP_OFFSET. */ | |
937 | lra_assert (update_sp_offset == 0); | |
938 | ||
80f466c4 VM |
939 | if (off != NULL_RTX |
940 | || src == ep->to_rtx | |
941 | || (GET_CODE (src) == PLUS | |
942 | && XEXP (src, 0) == ep->to_rtx | |
943 | && CONST_INT_P (XEXP (src, 1)))) | |
944 | { | |
945 | HOST_WIDE_INT offset; | |
946 | ||
947 | if (replace_p) | |
948 | { | |
949 | SET_DEST (old_set) = ep->to_rtx; | |
950 | lra_update_insn_recog_data (insn); | |
951 | return; | |
952 | } | |
953 | offset = (off != NULL_RTX ? INTVAL (off) | |
954 | : src == ep->to_rtx ? 0 : INTVAL (XEXP (src, 1))); | |
955 | offset -= (ep->offset - ep->previous_offset); | |
956 | src = plus_constant (Pmode, ep->to_rtx, offset); | |
957 | ||
958 | /* First see if this insn remains valid when we | |
959 | make the change. If not, keep the INSN_CODE | |
960 | the same and let the constraint pass fit it | |
961 | up. */ | |
962 | validate_change (insn, &SET_SRC (old_set), src, 1); | |
963 | validate_change (insn, &SET_DEST (old_set), | |
964 | ep->from_rtx, 1); | |
965 | if (! apply_change_group ()) | |
966 | { | |
967 | SET_SRC (old_set) = src; | |
968 | SET_DEST (old_set) = ep->from_rtx; | |
969 | } | |
970 | lra_update_insn_recog_data (insn); | |
971 | /* Add offset note for future updates. */ | |
972 | add_reg_note (insn, REG_EQUAL, src); | |
973 | return; | |
974 | } | |
975 | } | |
55a2c322 | 976 | #endif |
80f466c4 VM |
977 | |
978 | /* This insn isn't serving a useful purpose. We delete it | |
979 | when REPLACE is set. */ | |
980 | if (delete_p) | |
981 | lra_delete_dead_insn (insn); | |
982 | return; | |
983 | } | |
55a2c322 VM |
984 | } |
985 | ||
986 | /* We allow one special case which happens to work on all machines we | |
987 | currently support: a single set with the source or a REG_EQUAL | |
988 | note being a PLUS of an eliminable register and a constant. */ | |
989 | plus_src = plus_cst_src = 0; | |
990 | if (old_set && REG_P (SET_DEST (old_set))) | |
991 | { | |
992 | if (GET_CODE (SET_SRC (old_set)) == PLUS) | |
993 | plus_src = SET_SRC (old_set); | |
994 | /* First see if the source is of the form (plus (...) CST). */ | |
995 | if (plus_src | |
996 | && CONST_INT_P (XEXP (plus_src, 1))) | |
997 | plus_cst_src = plus_src; | |
998 | /* Check that the first operand of the PLUS is a hard reg or | |
999 | the lowpart subreg of one. */ | |
1000 | if (plus_cst_src) | |
1001 | { | |
1002 | rtx reg = XEXP (plus_cst_src, 0); | |
1003 | ||
1004 | if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg)) | |
1005 | reg = SUBREG_REG (reg); | |
1006 | ||
1007 | if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER) | |
1008 | plus_cst_src = 0; | |
1009 | } | |
1010 | } | |
1011 | if (plus_cst_src) | |
1012 | { | |
1013 | rtx reg = XEXP (plus_cst_src, 0); | |
1014 | HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1)); | |
1015 | ||
1016 | if (GET_CODE (reg) == SUBREG) | |
1017 | reg = SUBREG_REG (reg); | |
1018 | ||
1019 | if (REG_P (reg) && (ep = get_elimination (reg)) != NULL) | |
1020 | { | |
1021 | rtx to_rtx = replace_p ? ep->to_rtx : ep->from_rtx; | |
f4eafc30 | 1022 | |
55a2c322 VM |
1023 | if (! replace_p) |
1024 | { | |
a6af1bf9 VM |
1025 | if (update_sp_offset == 0) |
1026 | offset += (ep->offset - ep->previous_offset); | |
d9cf932c VM |
1027 | if (ep->to_rtx == stack_pointer_rtx) |
1028 | { | |
1029 | if (first_p) | |
1030 | offset -= lra_get_insn_recog_data (insn)->sp_offset; | |
1031 | else | |
1032 | offset += update_sp_offset; | |
1033 | } | |
55a2c322 VM |
1034 | offset = trunc_int_for_mode (offset, GET_MODE (plus_cst_src)); |
1035 | } | |
f4eafc30 | 1036 | |
55a2c322 VM |
1037 | if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG) |
1038 | to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)), to_rtx); | |
1039 | /* If we have a nonzero offset, and the source is already a | |
1040 | simple REG, the following transformation would increase | |
1041 | the cost of the insn by replacing a simple REG with (plus | |
1042 | (reg sp) CST). So try only when we already had a PLUS | |
1043 | before. */ | |
1044 | if (offset == 0 || plus_src) | |
1045 | { | |
1046 | rtx new_src = plus_constant (GET_MODE (to_rtx), to_rtx, offset); | |
f4eafc30 | 1047 | |
55a2c322 VM |
1048 | old_set = single_set (insn); |
1049 | ||
1050 | /* First see if this insn remains valid when we make the | |
1051 | change. If not, try to replace the whole pattern | |
1052 | with a simple set (this may help if the original insn | |
1053 | was a PARALLEL that was only recognized as single_set | |
1054 | due to REG_UNUSED notes). If this isn't valid | |
1055 | either, keep the INSN_CODE the same and let the | |
1056 | constraint pass fix it up. */ | |
1057 | if (! validate_change (insn, &SET_SRC (old_set), new_src, 0)) | |
1058 | { | |
f7df4a84 | 1059 | rtx new_pat = gen_rtx_SET (SET_DEST (old_set), new_src); |
f4eafc30 | 1060 | |
55a2c322 VM |
1061 | if (! validate_change (insn, &PATTERN (insn), new_pat, 0)) |
1062 | SET_SRC (old_set) = new_src; | |
1063 | } | |
1064 | lra_update_insn_recog_data (insn); | |
1065 | /* This can't have an effect on elimination offsets, so skip | |
1066 | right to the end. */ | |
1067 | return; | |
1068 | } | |
1069 | } | |
1070 | } | |
1071 | ||
1072 | /* Eliminate all eliminable registers occurring in operands that | |
1073 | can be handled by the constraint pass. */ | |
1074 | id = lra_get_insn_recog_data (insn); | |
1075 | static_id = id->insn_static_data; | |
1076 | validate_p = false; | |
1077 | for (i = 0; i < static_id->n_operands; i++) | |
1078 | { | |
1079 | orig_operand[i] = *id->operand_loc[i]; | |
1080 | substed_operand[i] = *id->operand_loc[i]; | |
1081 | ||
1082 | /* For an asm statement, every operand is eliminable. */ | |
1083 | if (icode < 0 || insn_data[icode].operand[i].eliminable) | |
1084 | { | |
1085 | /* Check for setting a hard register that we know about. */ | |
1086 | if (static_id->operand[i].type != OP_IN | |
1087 | && REG_P (orig_operand[i])) | |
1088 | { | |
1089 | /* If we are assigning to a hard register that can be | |
1090 | eliminated, it must be as part of a PARALLEL, since | |
1091 | the code above handles single SETs. This reg can not | |
1092 | be longer eliminated -- it is forced by | |
1093 | mark_not_eliminable. */ | |
1094 | for (ep = reg_eliminate; | |
1095 | ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
1096 | ep++) | |
1097 | lra_assert (ep->from_rtx != orig_operand[i] | |
1098 | || ! ep->can_eliminate); | |
1099 | } | |
1100 | ||
1101 | /* Companion to the above plus substitution, we can allow | |
1102 | invariants as the source of a plain move. */ | |
1103 | substed_operand[i] | |
8d49e7ef VM |
1104 | = lra_eliminate_regs_1 (insn, *id->operand_loc[i], VOIDmode, |
1105 | replace_p, ! replace_p && ! first_p, | |
d9cf932c | 1106 | update_sp_offset, first_p); |
55a2c322 VM |
1107 | if (substed_operand[i] != orig_operand[i]) |
1108 | validate_p = true; | |
1109 | } | |
1110 | } | |
1111 | ||
2c62cbaa VM |
1112 | if (! validate_p) |
1113 | return; | |
1114 | ||
55a2c322 VM |
1115 | /* Substitute the operands; the new values are in the substed_operand |
1116 | array. */ | |
1117 | for (i = 0; i < static_id->n_operands; i++) | |
1118 | *id->operand_loc[i] = substed_operand[i]; | |
1119 | for (i = 0; i < static_id->n_dups; i++) | |
1120 | *id->dup_loc[i] = substed_operand[(int) static_id->dup_num[i]]; | |
1121 | ||
2c62cbaa VM |
1122 | /* If we had a move insn but now we don't, re-recognize it. |
1123 | This will cause spurious re-recognition if the old move had a | |
1124 | PARALLEL since the new one still will, but we can't call | |
1125 | single_set without having put new body into the insn and the | |
1126 | re-recognition won't hurt in this rare case. */ | |
1127 | id = lra_update_insn_recog_data (insn); | |
1128 | static_id = id->insn_static_data; | |
55a2c322 VM |
1129 | } |
1130 | ||
1131 | /* Spill pseudos which are assigned to hard registers in SET. Add | |
1132 | affected insns for processing in the subsequent constraint | |
1133 | pass. */ | |
1134 | static void | |
1135 | spill_pseudos (HARD_REG_SET set) | |
1136 | { | |
1137 | int i; | |
1138 | bitmap_head to_process; | |
cfa434f6 | 1139 | rtx_insn *insn; |
55a2c322 VM |
1140 | |
1141 | if (hard_reg_set_empty_p (set)) | |
1142 | return; | |
1143 | if (lra_dump_file != NULL) | |
1144 | { | |
1145 | fprintf (lra_dump_file, " Spilling non-eliminable hard regs:"); | |
1146 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1147 | if (TEST_HARD_REG_BIT (set, i)) | |
1148 | fprintf (lra_dump_file, " %d", i); | |
1149 | fprintf (lra_dump_file, "\n"); | |
1150 | } | |
1151 | bitmap_initialize (&to_process, ®_obstack); | |
1152 | for (i = FIRST_PSEUDO_REGISTER; i < max_reg_num (); i++) | |
1153 | if (lra_reg_info[i].nrefs != 0 && reg_renumber[i] >= 0 | |
1154 | && overlaps_hard_reg_set_p (set, | |
1155 | PSEUDO_REGNO_MODE (i), reg_renumber[i])) | |
1156 | { | |
1157 | if (lra_dump_file != NULL) | |
1158 | fprintf (lra_dump_file, " Spilling r%d(%d)\n", | |
1159 | i, reg_renumber[i]); | |
1160 | reg_renumber[i] = -1; | |
1161 | bitmap_ior_into (&to_process, &lra_reg_info[i].insn_bitmap); | |
1162 | } | |
1163 | IOR_HARD_REG_SET (lra_no_alloc_regs, set); | |
1164 | for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn)) | |
1165 | if (bitmap_bit_p (&to_process, INSN_UID (insn))) | |
1166 | { | |
1167 | lra_push_insn (insn); | |
1168 | lra_set_used_insn_alternative (insn, -1); | |
1169 | } | |
1170 | bitmap_clear (&to_process); | |
1171 | } | |
1172 | ||
1173 | /* Update all offsets and possibility for elimination on eliminable | |
8d49e7ef | 1174 | registers. Spill pseudos assigned to registers which are |
55a2c322 VM |
1175 | uneliminable, update LRA_NO_ALLOC_REGS and ELIMINABLE_REG_SET. Add |
1176 | insns to INSNS_WITH_CHANGED_OFFSETS containing eliminable hard | |
5a107a0f VM |
1177 | registers whose offsets should be changed. Return true if any |
1178 | elimination offset changed. */ | |
1179 | static bool | |
55a2c322 VM |
1180 | update_reg_eliminate (bitmap insns_with_changed_offsets) |
1181 | { | |
5a107a0f | 1182 | bool prev, result; |
11478306 | 1183 | struct lra_elim_table *ep, *ep1; |
55a2c322 VM |
1184 | HARD_REG_SET temp_hard_reg_set; |
1185 | ||
1186 | /* Clear self elimination offsets. */ | |
1187 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
1188 | self_elim_offsets[ep->from] = 0; | |
55a2c322 VM |
1189 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
1190 | { | |
1191 | /* If it is a currently used elimination: update the previous | |
1192 | offset. */ | |
1193 | if (elimination_map[ep->from] == ep) | |
1194 | ep->previous_offset = ep->offset; | |
1195 | ||
1196 | prev = ep->prev_can_eliminate; | |
1197 | setup_can_eliminate (ep, targetm.can_eliminate (ep->from, ep->to)); | |
1198 | if (ep->can_eliminate && ! prev) | |
1199 | { | |
1200 | /* It is possible that not eliminable register becomes | |
1201 | eliminable because we took other reasons into account to | |
1202 | set up eliminable regs in the initial set up. Just | |
1203 | ignore new eliminable registers. */ | |
1204 | setup_can_eliminate (ep, false); | |
1205 | continue; | |
1206 | } | |
1207 | if (ep->can_eliminate != prev && elimination_map[ep->from] == ep) | |
1208 | { | |
1209 | /* We cannot use this elimination anymore -- find another | |
1210 | one. */ | |
1211 | if (lra_dump_file != NULL) | |
1212 | fprintf (lra_dump_file, | |
1213 | " Elimination %d to %d is not possible anymore\n", | |
1214 | ep->from, ep->to); | |
8d49e7ef VM |
1215 | /* If after processing RTL we decides that SP can be used as |
1216 | a result of elimination, it can not be changed. */ | |
ddcfa953 JW |
1217 | gcc_assert ((ep->to_rtx != stack_pointer_rtx) |
1218 | || (ep->from < FIRST_PSEUDO_REGISTER | |
1219 | && fixed_regs [ep->from])); | |
55a2c322 VM |
1220 | /* Mark that is not eliminable anymore. */ |
1221 | elimination_map[ep->from] = NULL; | |
1222 | for (ep1 = ep + 1; ep1 < ®_eliminate[NUM_ELIMINABLE_REGS]; ep1++) | |
1223 | if (ep1->can_eliminate && ep1->from == ep->from) | |
1224 | break; | |
1225 | if (ep1 < ®_eliminate[NUM_ELIMINABLE_REGS]) | |
1226 | { | |
1227 | if (lra_dump_file != NULL) | |
1228 | fprintf (lra_dump_file, " Using elimination %d to %d now\n", | |
1229 | ep1->from, ep1->to); | |
55a2c322 VM |
1230 | lra_assert (ep1->previous_offset == 0); |
1231 | ep1->previous_offset = ep->offset; | |
1232 | } | |
1233 | else | |
1234 | { | |
1235 | /* There is no elimination anymore just use the hard | |
1236 | register `from' itself. Setup self elimination | |
1237 | offset to restore the original offset values. */ | |
1238 | if (lra_dump_file != NULL) | |
1239 | fprintf (lra_dump_file, " %d is not eliminable at all\n", | |
1240 | ep->from); | |
1241 | self_elim_offsets[ep->from] = -ep->offset; | |
55a2c322 VM |
1242 | if (ep->offset != 0) |
1243 | bitmap_ior_into (insns_with_changed_offsets, | |
1244 | &lra_reg_info[ep->from].insn_bitmap); | |
1245 | } | |
1246 | } | |
1247 | ||
1248 | #ifdef ELIMINABLE_REGS | |
1249 | INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->offset); | |
1250 | #else | |
1251 | INITIAL_FRAME_POINTER_OFFSET (ep->offset); | |
1252 | #endif | |
1253 | } | |
55a2c322 | 1254 | setup_elimination_map (); |
5a107a0f | 1255 | result = false; |
8d49e7ef | 1256 | CLEAR_HARD_REG_SET (temp_hard_reg_set); |
55a2c322 | 1257 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
8d49e7ef VM |
1258 | if (elimination_map[ep->from] == NULL) |
1259 | SET_HARD_REG_BIT (temp_hard_reg_set, ep->from); | |
1260 | else if (elimination_map[ep->from] == ep) | |
d70a81dd | 1261 | { |
8d49e7ef VM |
1262 | /* Prevent the hard register into which we eliminate from |
1263 | the usage for pseudos. */ | |
1264 | if (ep->from != ep->to) | |
1265 | SET_HARD_REG_BIT (temp_hard_reg_set, ep->to); | |
1266 | if (ep->previous_offset != ep->offset) | |
1267 | { | |
1268 | bitmap_ior_into (insns_with_changed_offsets, | |
1269 | &lra_reg_info[ep->from].insn_bitmap); | |
1270 | ||
1271 | /* Update offset when the eliminate offset have been | |
1272 | changed. */ | |
1273 | lra_update_reg_val_offset (lra_reg_info[ep->from].val, | |
1274 | ep->offset - ep->previous_offset); | |
1275 | result = true; | |
1276 | } | |
d70a81dd | 1277 | } |
8d49e7ef VM |
1278 | IOR_HARD_REG_SET (lra_no_alloc_regs, temp_hard_reg_set); |
1279 | AND_COMPL_HARD_REG_SET (eliminable_regset, temp_hard_reg_set); | |
1280 | spill_pseudos (temp_hard_reg_set); | |
5a107a0f | 1281 | return result; |
55a2c322 VM |
1282 | } |
1283 | ||
1284 | /* Initialize the table of hard registers to eliminate. | |
1285 | Pre-condition: global flag frame_pointer_needed has been set before | |
1286 | calling this function. */ | |
1287 | static void | |
1288 | init_elim_table (void) | |
1289 | { | |
11478306 | 1290 | struct lra_elim_table *ep; |
55a2c322 | 1291 | #ifdef ELIMINABLE_REGS |
522d4efc | 1292 | bool value_p; |
55a2c322 VM |
1293 | const struct elim_table_1 *ep1; |
1294 | #endif | |
1295 | ||
1296 | if (!reg_eliminate) | |
11478306 | 1297 | reg_eliminate = XCNEWVEC (struct lra_elim_table, NUM_ELIMINABLE_REGS); |
55a2c322 VM |
1298 | |
1299 | memset (self_elim_offsets, 0, sizeof (self_elim_offsets)); | |
1300 | /* Initiate member values which will be never changed. */ | |
1301 | self_elim_table.can_eliminate = self_elim_table.prev_can_eliminate = true; | |
1302 | self_elim_table.previous_offset = 0; | |
1303 | #ifdef ELIMINABLE_REGS | |
1304 | for (ep = reg_eliminate, ep1 = reg_eliminate_1; | |
1305 | ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++) | |
1306 | { | |
1307 | ep->offset = ep->previous_offset = 0; | |
1308 | ep->from = ep1->from; | |
1309 | ep->to = ep1->to; | |
1310 | value_p = (targetm.can_eliminate (ep->from, ep->to) | |
1311 | && ! (ep->to == STACK_POINTER_REGNUM | |
f4eafc30 | 1312 | && frame_pointer_needed |
55a2c322 VM |
1313 | && (! SUPPORTS_STACK_ALIGNMENT |
1314 | || ! stack_realign_fp))); | |
1315 | setup_can_eliminate (ep, value_p); | |
1316 | } | |
1317 | #else | |
1318 | reg_eliminate[0].offset = reg_eliminate[0].previous_offset = 0; | |
1319 | reg_eliminate[0].from = reg_eliminate_1[0].from; | |
1320 | reg_eliminate[0].to = reg_eliminate_1[0].to; | |
1321 | setup_can_eliminate (®_eliminate[0], ! frame_pointer_needed); | |
1322 | #endif | |
1323 | ||
8d49e7ef VM |
1324 | /* Build the FROM and TO REG rtx's. Note that code in gen_rtx_REG |
1325 | will cause, e.g., gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to | |
1326 | equal stack_pointer_rtx. We depend on this. Threfore we switch | |
1327 | off that we are in LRA temporarily. */ | |
1328 | lra_in_progress = 0; | |
55a2c322 VM |
1329 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
1330 | { | |
1331 | ep->from_rtx = gen_rtx_REG (Pmode, ep->from); | |
1332 | ep->to_rtx = gen_rtx_REG (Pmode, ep->to); | |
1333 | eliminable_reg_rtx[ep->from] = ep->from_rtx; | |
1334 | } | |
8d49e7ef | 1335 | lra_in_progress = 1; |
55a2c322 VM |
1336 | } |
1337 | ||
8d49e7ef VM |
1338 | /* Function for initialization of elimination once per function. It |
1339 | sets up sp offset for each insn. */ | |
1340 | static void | |
1341 | init_elimination (void) | |
55a2c322 | 1342 | { |
8d49e7ef | 1343 | bool stop_to_sp_elimination_p; |
55a2c322 | 1344 | basic_block bb; |
cfa434f6 | 1345 | rtx_insn *insn; |
11478306 | 1346 | struct lra_elim_table *ep; |
55a2c322 VM |
1347 | |
1348 | init_elim_table (); | |
11cd3bed | 1349 | FOR_EACH_BB_FN (bb, cfun) |
8d49e7ef VM |
1350 | { |
1351 | curr_sp_change = 0; | |
1352 | stop_to_sp_elimination_p = false; | |
1353 | FOR_BB_INSNS (bb, insn) | |
1354 | if (INSN_P (insn)) | |
1355 | { | |
1356 | lra_get_insn_recog_data (insn)->sp_offset = curr_sp_change; | |
1357 | if (NONDEBUG_INSN_P (insn)) | |
1358 | { | |
1359 | mark_not_eliminable (PATTERN (insn), VOIDmode); | |
1360 | if (curr_sp_change != 0 | |
1361 | && find_reg_note (insn, REG_LABEL_OPERAND, NULL_RTX)) | |
1362 | stop_to_sp_elimination_p = true; | |
1363 | } | |
1364 | } | |
1365 | if (! frame_pointer_needed | |
1366 | && (curr_sp_change != 0 || stop_to_sp_elimination_p) | |
1367 | && bb->succs && bb->succs->length () != 0) | |
1368 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
1369 | if (ep->to == STACK_POINTER_REGNUM) | |
1370 | setup_can_eliminate (ep, false); | |
1371 | } | |
55a2c322 VM |
1372 | setup_elimination_map (); |
1373 | } | |
1374 | ||
1375 | /* Eliminate hard reg given by its location LOC. */ | |
1376 | void | |
1377 | lra_eliminate_reg_if_possible (rtx *loc) | |
1378 | { | |
1379 | int regno; | |
11478306 | 1380 | struct lra_elim_table *ep; |
55a2c322 VM |
1381 | |
1382 | lra_assert (REG_P (*loc)); | |
1383 | if ((regno = REGNO (*loc)) >= FIRST_PSEUDO_REGISTER | |
1384 | || ! TEST_HARD_REG_BIT (lra_no_alloc_regs, regno)) | |
1385 | return; | |
1386 | if ((ep = get_elimination (*loc)) != NULL) | |
1387 | *loc = ep->to_rtx; | |
1388 | } | |
1389 | ||
8d49e7ef VM |
1390 | /* Do (final if FINAL_P or first if FIRST_P) elimination in INSN. Add |
1391 | the insn for subsequent processing in the constraint pass, update | |
1392 | the insn info. */ | |
55a2c322 | 1393 | static void |
cfa434f6 | 1394 | process_insn_for_elimination (rtx_insn *insn, bool final_p, bool first_p) |
55a2c322 | 1395 | { |
d9cf932c | 1396 | eliminate_regs_in_insn (insn, final_p, first_p, 0); |
55a2c322 VM |
1397 | if (! final_p) |
1398 | { | |
1399 | /* Check that insn changed its code. This is a case when a move | |
1400 | insn becomes an add insn and we do not want to process the | |
1401 | insn as a move anymore. */ | |
1402 | int icode = recog (PATTERN (insn), insn, 0); | |
1403 | ||
1404 | if (icode >= 0 && icode != INSN_CODE (insn)) | |
1405 | { | |
1406 | INSN_CODE (insn) = icode; | |
1407 | lra_update_insn_recog_data (insn); | |
1408 | } | |
1409 | lra_update_insn_regno_info (insn); | |
1410 | lra_push_insn (insn); | |
1411 | lra_set_used_insn_alternative (insn, -1); | |
1412 | } | |
1413 | } | |
1414 | ||
1415 | /* Entry function to do final elimination if FINAL_P or to update | |
8d49e7ef VM |
1416 | elimination register offsets (FIRST_P if we are doing it the first |
1417 | time). */ | |
55a2c322 | 1418 | void |
8d49e7ef | 1419 | lra_eliminate (bool final_p, bool first_p) |
55a2c322 | 1420 | { |
55a2c322 | 1421 | unsigned int uid; |
55a2c322 VM |
1422 | bitmap_head insns_with_changed_offsets; |
1423 | bitmap_iterator bi; | |
11478306 | 1424 | struct lra_elim_table *ep; |
8d49e7ef VM |
1425 | |
1426 | gcc_assert (! final_p || ! first_p); | |
55a2c322 VM |
1427 | |
1428 | timevar_push (TV_LRA_ELIMINATE); | |
1429 | ||
8d49e7ef VM |
1430 | if (first_p) |
1431 | init_elimination (); | |
1432 | ||
55a2c322 VM |
1433 | bitmap_initialize (&insns_with_changed_offsets, ®_obstack); |
1434 | if (final_p) | |
1435 | { | |
b2b29377 MM |
1436 | if (flag_checking) |
1437 | { | |
1438 | update_reg_eliminate (&insns_with_changed_offsets); | |
1439 | gcc_assert (bitmap_empty_p (&insns_with_changed_offsets)); | |
1440 | } | |
55a2c322 VM |
1441 | /* We change eliminable hard registers in insns so we should do |
1442 | this for all insns containing any eliminable hard | |
1443 | register. */ | |
1444 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
1445 | if (elimination_map[ep->from] != NULL) | |
1446 | bitmap_ior_into (&insns_with_changed_offsets, | |
1447 | &lra_reg_info[ep->from].insn_bitmap); | |
1448 | } | |
5a107a0f VM |
1449 | else if (! update_reg_eliminate (&insns_with_changed_offsets)) |
1450 | goto lra_eliminate_done; | |
55a2c322 VM |
1451 | if (lra_dump_file != NULL) |
1452 | { | |
1453 | fprintf (lra_dump_file, "New elimination table:\n"); | |
1454 | print_elim_table (lra_dump_file); | |
1455 | } | |
55a2c322 | 1456 | EXECUTE_IF_SET_IN_BITMAP (&insns_with_changed_offsets, 0, uid, bi) |
80f466c4 VM |
1457 | /* A dead insn can be deleted in process_insn_for_elimination. */ |
1458 | if (lra_insn_recog_data[uid] != NULL) | |
8d49e7ef VM |
1459 | process_insn_for_elimination (lra_insn_recog_data[uid]->insn, |
1460 | final_p, first_p); | |
55a2c322 VM |
1461 | bitmap_clear (&insns_with_changed_offsets); |
1462 | ||
1463 | lra_eliminate_done: | |
1464 | timevar_pop (TV_LRA_ELIMINATE); | |
1465 | } |