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c6a6cdaa | 1 | /* Local Register Allocator (LRA) intercommunication header file. |
fbd26352 | 2 | Copyright (C) 2010-2019 Free Software Foundation, Inc. |
c6a6cdaa | 3 | Contributed by Vladimir Makarov <vmakarov@redhat.com>. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it under | |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 3, or (at your option) any later | |
10 | version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
ce6bb0f3 | 21 | #ifndef GCC_LRA_INT_H |
22 | #define GCC_LRA_INT_H | |
23 | ||
6b58d3cb | 24 | #define lra_assert(c) gcc_checking_assert (c) |
c6a6cdaa | 25 | |
26 | /* The parameter used to prevent infinite reloading for an insn. Each | |
27 | insn operands might require a reload and, if it is a memory, its | |
28 | base and index registers might require a reload too. */ | |
29 | #define LRA_MAX_INSN_RELOADS (MAX_RECOG_OPERANDS * 3) | |
30 | ||
c6a6cdaa | 31 | typedef struct lra_live_range *lra_live_range_t; |
32 | ||
33 | /* The structure describes program points where a given pseudo lives. | |
34 | The live ranges can be used to find conflicts with other pseudos. | |
35 | If the live ranges of two pseudos are intersected, the pseudos are | |
36 | in conflict. */ | |
37 | struct lra_live_range | |
38 | { | |
39 | /* Pseudo regno whose live range is described by given | |
40 | structure. */ | |
41 | int regno; | |
42 | /* Program point range. */ | |
43 | int start, finish; | |
44 | /* Next structure describing program points where the pseudo | |
45 | lives. */ | |
46 | lra_live_range_t next; | |
47 | /* Pointer to structures with the same start. */ | |
48 | lra_live_range_t start_next; | |
49 | }; | |
50 | ||
51 | typedef struct lra_copy *lra_copy_t; | |
52 | ||
53 | /* Copy between pseudos which affects assigning hard registers. */ | |
54 | struct lra_copy | |
55 | { | |
56 | /* True if regno1 is the destination of the copy. */ | |
57 | bool regno1_dest_p; | |
58 | /* Execution frequency of the copy. */ | |
59 | int freq; | |
60 | /* Pseudos connected by the copy. REGNO1 < REGNO2. */ | |
61 | int regno1, regno2; | |
62 | /* Next copy with correspondingly REGNO1 and REGNO2. */ | |
63 | lra_copy_t regno1_next, regno2_next; | |
64 | }; | |
65 | ||
66 | /* Common info about a register (pseudo or hard register). */ | |
251317e4 | 67 | class lra_reg |
c6a6cdaa | 68 | { |
251317e4 | 69 | public: |
c6a6cdaa | 70 | /* Bitmap of UIDs of insns (including debug insns) referring the |
71 | reg. */ | |
72 | bitmap_head insn_bitmap; | |
73 | /* The following fields are defined only for pseudos. */ | |
74 | /* Hard registers with which the pseudo conflicts. */ | |
75 | HARD_REG_SET conflict_hard_regs; | |
f2cc6708 | 76 | /* Call used registers with which the pseudo conflicts, taking into account |
77 | the registers used by functions called from calls which cross the | |
78 | pseudo. */ | |
79 | HARD_REG_SET actual_call_used_reg_set; | |
c6a6cdaa | 80 | /* We assign hard registers to reload pseudos which can occur in few |
81 | places. So two hard register preferences are enough for them. | |
82 | The following fields define the preferred hard registers. If | |
83 | there are no such hard registers the first field value is | |
84 | negative. If there is only one preferred hard register, the 2nd | |
85 | field is negative. */ | |
86 | int preferred_hard_regno1, preferred_hard_regno2; | |
87 | /* Profits to use the corresponding preferred hard registers. If | |
88 | the both hard registers defined, the first hard register has not | |
89 | less profit than the second one. */ | |
90 | int preferred_hard_regno_profit1, preferred_hard_regno_profit2; | |
91 | #ifdef STACK_REGS | |
92 | /* True if the pseudo should not be assigned to a stack register. */ | |
93 | bool no_stack_p; | |
94 | #endif | |
c6a6cdaa | 95 | /* Number of references and execution frequencies of the register in |
96 | *non-debug* insns. */ | |
97 | int nrefs, freq; | |
98 | int last_reload; | |
ab4ea053 | 99 | /* rtx used to undo the inheritance. It can be non-null only |
100 | between subsequent inheritance and undo inheritance passes. */ | |
101 | rtx restore_rtx; | |
c6a6cdaa | 102 | /* Value holding by register. If the pseudos have the same value |
103 | they do not conflict. */ | |
104 | int val; | |
a1064490 | 105 | /* Offset from relative eliminate register to pesudo reg. */ |
a4686d0a | 106 | poly_int64 offset; |
5c62f29a | 107 | /* Call instruction, if any, that may affect this psuedo reg. */ |
108 | rtx_insn *call_insn; | |
c6a6cdaa | 109 | /* These members are set up in lra-lives.c and updated in |
110 | lra-coalesce.c. */ | |
111 | /* The biggest size mode in which each pseudo reg is referred in | |
112 | whole function (possibly via subreg). */ | |
3754d046 | 113 | machine_mode biggest_mode; |
c6a6cdaa | 114 | /* Live ranges of the pseudo. */ |
115 | lra_live_range_t live_ranges; | |
116 | /* This member is set up in lra-lives.c for subsequent | |
117 | assignments. */ | |
118 | lra_copy_t copies; | |
119 | }; | |
120 | ||
121 | /* References to the common info about each register. */ | |
2e966e2a | 122 | extern class lra_reg *lra_reg_info; |
c6a6cdaa | 123 | |
95f18d43 | 124 | extern HARD_REG_SET hard_regs_spilled_into; |
125 | ||
c6a6cdaa | 126 | /* Static info about each insn operand (common for all insns with the |
127 | same ICODE). Warning: if the structure definition is changed, the | |
128 | initializer for debug_operand_data in lra.c should be changed | |
129 | too. */ | |
130 | struct lra_operand_data | |
131 | { | |
132 | /* The machine description constraint string of the operand. */ | |
133 | const char *constraint; | |
3da302c5 | 134 | /* Alternatives for which early_clobber can be true. */ |
135 | alternative_mask early_clobber_alts; | |
c6a6cdaa | 136 | /* It is taken only from machine description (which is different |
137 | from recog_data.operand_mode) and can be of VOIDmode. */ | |
138 | ENUM_BITFIELD(machine_mode) mode : 16; | |
139 | /* The type of the operand (in/out/inout). */ | |
140 | ENUM_BITFIELD (op_type) type : 8; | |
141 | /* Through if accessed through STRICT_LOW. */ | |
142 | unsigned int strict_low : 1; | |
143 | /* True if the operand is an operator. */ | |
144 | unsigned int is_operator : 1; | |
c6a6cdaa | 145 | /* True if the operand is an address. */ |
146 | unsigned int is_address : 1; | |
147 | }; | |
148 | ||
149 | /* Info about register occurrence in an insn. */ | |
150 | struct lra_insn_reg | |
151 | { | |
3da302c5 | 152 | /* Alternatives for which early_clobber can be true. */ |
153 | alternative_mask early_clobber_alts; | |
c6a6cdaa | 154 | /* The biggest mode through which the insn refers to the register |
155 | occurrence (remember the register can be accessed through a | |
156 | subreg in the insn). */ | |
157 | ENUM_BITFIELD(machine_mode) biggest_mode : 16; | |
158 | /* The type of the corresponding operand which is the register. */ | |
159 | ENUM_BITFIELD (op_type) type : 8; | |
160 | /* True if the reg is accessed through a subreg and the subreg is | |
161 | just a part of the register. */ | |
162 | unsigned int subreg_p : 1; | |
0823eb36 | 163 | /* True if the reg is clobber highed by the operand. */ |
164 | unsigned int clobber_high : 1; | |
c6a6cdaa | 165 | /* The corresponding regno of the register. */ |
166 | int regno; | |
167 | /* Next reg info of the same insn. */ | |
168 | struct lra_insn_reg *next; | |
169 | }; | |
170 | ||
171 | /* Static part (common info for insns with the same ICODE) of LRA | |
172 | internal insn info. It exists in at most one exemplar for each | |
173 | non-negative ICODE. There is only one exception. Each asm insn has | |
174 | own structure. Warning: if the structure definition is changed, | |
175 | the initializer for debug_insn_static_data in lra.c should be | |
176 | changed too. */ | |
177 | struct lra_static_insn_data | |
178 | { | |
179 | /* Static info about each insn operand. */ | |
180 | struct lra_operand_data *operand; | |
181 | /* Each duplication refers to the number of the corresponding | |
182 | operand which is duplicated. */ | |
183 | int *dup_num; | |
184 | /* The number of an operand marked as commutative, -1 otherwise. */ | |
185 | int commutative; | |
186 | /* Number of operands, duplications, and alternatives of the | |
187 | insn. */ | |
188 | char n_operands; | |
189 | char n_dups; | |
190 | char n_alternatives; | |
191 | /* Insns in machine description (or clobbers in asm) may contain | |
192 | explicit hard regs which are not operands. The following list | |
193 | describes such hard registers. */ | |
194 | struct lra_insn_reg *hard_regs; | |
195 | /* Array [n_alternatives][n_operand] of static constraint info for | |
196 | given operand in given alternative. This info can be changed if | |
197 | the target reg info is changed. */ | |
92b4b904 | 198 | const struct operand_alternative *operand_alternative; |
c6a6cdaa | 199 | }; |
200 | ||
71d47a14 | 201 | /* Negative insn alternative numbers used for special cases. */ |
202 | #define LRA_UNKNOWN_ALT -1 | |
203 | #define LRA_NON_CLOBBERED_ALT -2 | |
204 | ||
c6a6cdaa | 205 | /* LRA internal info about an insn (LRA internal insn |
206 | representation). */ | |
251317e4 | 207 | class lra_insn_recog_data |
c6a6cdaa | 208 | { |
251317e4 | 209 | public: |
c6a6cdaa | 210 | /* The insn code. */ |
211 | int icode; | |
71d47a14 | 212 | /* The alternative should be used for the insn, LRA_UNKNOWN_ALT if |
213 | unknown, or we should assume any alternative, or the insn is a | |
214 | debug insn. LRA_NON_CLOBBERED_ALT means ignoring any earlier | |
215 | clobbers for the insn. */ | |
3b3a5e5f | 216 | int used_insn_alternative; |
217 | /* SP offset before the insn relative to one at the func start. */ | |
a4686d0a | 218 | poly_int64 sp_offset; |
c6a6cdaa | 219 | /* The insn itself. */ |
7f836b57 | 220 | rtx_insn *insn; |
c6a6cdaa | 221 | /* Common data for insns with the same ICODE. Asm insns (their |
222 | ICODE is negative) do not share such structures. */ | |
223 | struct lra_static_insn_data *insn_static_data; | |
224 | /* Two arrays of size correspondingly equal to the operand and the | |
225 | duplication numbers: */ | |
226 | rtx **operand_loc; /* The operand locations, NULL if no operands. */ | |
227 | rtx **dup_loc; /* The dup locations, NULL if no dups. */ | |
853a01d6 | 228 | /* Number of hard registers implicitly used/clobbered in given call |
229 | insn. The value can be NULL or points to array of the hard | |
230 | register numbers ending with a negative value. To differ | |
231 | clobbered and used hard regs, clobbered hard regs are incremented | |
232 | by FIRST_PSEUDO_REGISTER. */ | |
c6a6cdaa | 233 | int *arg_hard_regs; |
e1a797ad | 234 | /* Cached value of get_preferred_alternatives. */ |
235 | alternative_mask preferred_alternatives; | |
c6a6cdaa | 236 | /* The following member value is always NULL for a debug insn. */ |
237 | struct lra_insn_reg *regs; | |
238 | }; | |
239 | ||
2e966e2a | 240 | typedef class lra_insn_recog_data *lra_insn_recog_data_t; |
c6a6cdaa | 241 | |
ae72d5b2 | 242 | /* Whether the clobber is used temporary in LRA. */ |
243 | #define LRA_TEMP_CLOBBER_P(x) \ | |
244 | (RTL_FLAG_CHECK1 ("TEMP_CLOBBER_P", (x), CLOBBER)->unchanging) | |
245 | ||
4b3aba76 | 246 | /* Cost factor for each additional reload and maximal cost reject for |
247 | insn reloads. One might ask about such strange numbers. Their | |
248 | values occurred historically from former reload pass. */ | |
249 | #define LRA_LOSER_COST_FACTOR 6 | |
250 | #define LRA_MAX_REJECT 600 | |
251 | ||
f95727ee | 252 | /* Maximum allowed number of assignment pass iterations after the |
253 | latest spill pass when any former reload pseudo was spilled. It is | |
254 | for preventing LRA cycling in a bug case. */ | |
255 | #define LRA_MAX_ASSIGNMENT_ITERATION_NUMBER 30 | |
47f6add2 | 256 | |
257 | /* The maximal number of inheritance/split passes in LRA. It should | |
258 | be more 1 in order to perform caller saves transformations and much | |
259 | less MAX_CONSTRAINT_ITERATION_NUMBER to prevent LRA to do as many | |
260 | as permitted constraint passes in some complicated cases. The | |
261 | first inheritance/split pass has a biggest impact on generated code | |
262 | quality. Each subsequent affects generated code in less degree. | |
263 | For example, the 3rd pass does not change generated SPEC2000 code | |
264 | at all on x86-64. */ | |
265 | #define LRA_MAX_INHERITANCE_PASSES 2 | |
266 | ||
267 | #if LRA_MAX_INHERITANCE_PASSES <= 0 \ | |
f95727ee | 268 | || LRA_MAX_INHERITANCE_PASSES >= LRA_MAX_ASSIGNMENT_ITERATION_NUMBER - 8 |
47f6add2 | 269 | #error wrong LRA_MAX_INHERITANCE_PASSES value |
270 | #endif | |
271 | ||
fa4f0b4e | 272 | /* Analogous macro to the above one but for rematerialization. */ |
273 | #define LRA_MAX_REMATERIALIZATION_PASSES 2 | |
274 | ||
275 | #if LRA_MAX_REMATERIALIZATION_PASSES <= 0 \ | |
276 | || LRA_MAX_REMATERIALIZATION_PASSES >= LRA_MAX_ASSIGNMENT_ITERATION_NUMBER - 8 | |
277 | #error wrong LRA_MAX_REMATERIALIZATION_PASSES value | |
278 | #endif | |
279 | ||
c6a6cdaa | 280 | /* lra.c: */ |
281 | ||
282 | extern FILE *lra_dump_file; | |
283 | ||
3923c63e | 284 | extern bool lra_asm_error_p; |
c6a6cdaa | 285 | extern bool lra_reg_spill_p; |
286 | ||
287 | extern HARD_REG_SET lra_no_alloc_regs; | |
288 | ||
289 | extern int lra_insn_recog_data_len; | |
290 | extern lra_insn_recog_data_t *lra_insn_recog_data; | |
291 | ||
292 | extern int lra_curr_reload_num; | |
293 | ||
8c0d01a4 | 294 | extern void lra_dump_bitmap_with_title (const char *, bitmap, int); |
ab4ea053 | 295 | extern hashval_t lra_rtx_hash (rtx x); |
7f836b57 | 296 | extern void lra_push_insn (rtx_insn *); |
c6a6cdaa | 297 | extern void lra_push_insn_by_uid (unsigned int); |
7f836b57 | 298 | extern void lra_push_insn_and_update_insn_regno_info (rtx_insn *); |
299 | extern rtx_insn *lra_pop_insn (void); | |
c6a6cdaa | 300 | extern unsigned int lra_insn_stack_length (void); |
301 | ||
3754d046 | 302 | extern rtx lra_create_new_reg_with_unique_value (machine_mode, rtx, |
c6a6cdaa | 303 | enum reg_class, const char *); |
304 | extern void lra_set_regno_unique_value (int); | |
7f836b57 | 305 | extern void lra_invalidate_insn_data (rtx_insn *); |
306 | extern void lra_set_insn_deleted (rtx_insn *); | |
307 | extern void lra_delete_dead_insn (rtx_insn *); | |
c6a6cdaa | 308 | extern void lra_emit_add (rtx, rtx, rtx); |
309 | extern void lra_emit_move (rtx, rtx); | |
310 | extern void lra_update_dups (lra_insn_recog_data_t, signed char *); | |
311 | ||
7f836b57 | 312 | extern void lra_process_new_insns (rtx_insn *, rtx_insn *, rtx_insn *, |
313 | const char *); | |
c6a6cdaa | 314 | |
d686eece | 315 | extern bool lra_substitute_pseudo (rtx *, int, rtx, bool, bool); |
06072e79 | 316 | extern bool lra_substitute_pseudo_within_insn (rtx_insn *, int, rtx, bool); |
8c0d01a4 | 317 | |
7f836b57 | 318 | extern lra_insn_recog_data_t lra_set_insn_recog_data (rtx_insn *); |
319 | extern lra_insn_recog_data_t lra_update_insn_recog_data (rtx_insn *); | |
320 | extern void lra_set_used_insn_alternative (rtx_insn *, int); | |
c6a6cdaa | 321 | extern void lra_set_used_insn_alternative_by_uid (int, int); |
322 | ||
7f836b57 | 323 | extern void lra_invalidate_insn_regno_info (rtx_insn *); |
324 | extern void lra_update_insn_regno_info (rtx_insn *); | |
c6a6cdaa | 325 | extern struct lra_insn_reg *lra_get_insn_regs (int); |
326 | ||
327 | extern void lra_free_copies (void); | |
328 | extern void lra_create_copy (int, int, int); | |
329 | extern lra_copy_t lra_get_copy (int); | |
330 | extern bool lra_former_scratch_p (int); | |
7f836b57 | 331 | extern bool lra_former_scratch_operand_p (rtx_insn *, int); |
95f61091 | 332 | extern void lra_register_new_scratch_op (rtx_insn *, int, int); |
c6a6cdaa | 333 | |
edfb1d8f | 334 | extern int lra_new_regno_start; |
c6a6cdaa | 335 | extern int lra_constraint_new_regno_start; |
0f7b6a0d | 336 | extern int lra_bad_spill_regno_start; |
c6a6cdaa | 337 | extern bitmap_head lra_inheritance_pseudos; |
338 | extern bitmap_head lra_split_regs; | |
1f3a048a | 339 | extern bitmap_head lra_subreg_reload_pseudos; |
c6a6cdaa | 340 | extern bitmap_head lra_optional_reload_pseudos; |
c6a6cdaa | 341 | |
342 | /* lra-constraints.c: */ | |
343 | ||
61cd3e57 | 344 | extern void lra_init_equiv (void); |
3754d046 | 345 | extern int lra_constraint_offset (int, machine_mode); |
c6a6cdaa | 346 | |
347 | extern int lra_constraint_iter; | |
c6a6cdaa | 348 | extern bool lra_risky_transformations_p; |
349 | extern int lra_inheritance_iter; | |
350 | extern int lra_undo_inheritance_iter; | |
497ba60f | 351 | extern bool lra_constrain_insn (rtx_insn *); |
c6a6cdaa | 352 | extern bool lra_constraints (bool); |
353 | extern void lra_constraints_init (void); | |
354 | extern void lra_constraints_finish (void); | |
6a4bc24e | 355 | extern bool spill_hard_reg_in_range (int, enum reg_class, rtx_insn *, rtx_insn *); |
c6a6cdaa | 356 | extern void lra_inheritance (void); |
357 | extern bool lra_undo_inheritance (void); | |
358 | ||
359 | /* lra-lives.c: */ | |
360 | ||
361 | extern int lra_live_max_point; | |
362 | extern int *lra_point_freq; | |
363 | ||
364 | extern int lra_hard_reg_usage[FIRST_PSEUDO_REGISTER]; | |
365 | ||
366 | extern int lra_live_range_iter; | |
04472658 | 367 | extern void lra_create_live_ranges (bool, bool); |
c6a6cdaa | 368 | extern lra_live_range_t lra_copy_live_range_list (lra_live_range_t); |
369 | extern lra_live_range_t lra_merge_live_ranges (lra_live_range_t, | |
370 | lra_live_range_t); | |
371 | extern bool lra_intersected_live_ranges_p (lra_live_range_t, | |
372 | lra_live_range_t); | |
373 | extern void lra_print_live_range_list (FILE *, lra_live_range_t); | |
c7d89805 | 374 | extern void debug (lra_live_range &ref); |
375 | extern void debug (lra_live_range *ptr); | |
c6a6cdaa | 376 | extern void lra_debug_live_range_list (lra_live_range_t); |
377 | extern void lra_debug_pseudo_live_ranges (int); | |
378 | extern void lra_debug_live_ranges (void); | |
379 | extern void lra_clear_live_ranges (void); | |
380 | extern void lra_live_ranges_init (void); | |
381 | extern void lra_live_ranges_finish (void); | |
382 | extern void lra_setup_reload_pseudo_preferenced_hard_reg (int, int, int); | |
383 | ||
384 | /* lra-assigns.c: */ | |
385 | ||
f95727ee | 386 | extern int lra_assignment_iter; |
387 | extern int lra_assignment_iter_after_spill; | |
c6a6cdaa | 388 | extern void lra_setup_reg_renumber (int, int, bool); |
6a4bc24e | 389 | extern bool lra_assign (bool &); |
390 | extern bool lra_split_hard_reg_for (void); | |
c6a6cdaa | 391 | |
392 | /* lra-coalesce.c: */ | |
393 | ||
394 | extern int lra_coalesce_iter; | |
395 | extern bool lra_coalesce (void); | |
396 | ||
397 | /* lra-spills.c: */ | |
398 | ||
c8b6743f | 399 | extern bool lra_need_for_scratch_reg_p (void); |
c6a6cdaa | 400 | extern bool lra_need_for_spills_p (void); |
401 | extern void lra_spill (void); | |
ae72d5b2 | 402 | extern void lra_final_code_change (void); |
c6a6cdaa | 403 | |
497ba60f | 404 | /* lra-remat.c: */ |
405 | ||
fa4f0b4e | 406 | extern int lra_rematerialization_iter; |
497ba60f | 407 | extern bool lra_remat (void); |
c6a6cdaa | 408 | |
409 | /* lra-elimination.c: */ | |
410 | ||
411 | extern void lra_debug_elim_table (void); | |
412 | extern int lra_get_elimination_hard_regno (int); | |
497ba60f | 413 | extern rtx lra_eliminate_regs_1 (rtx_insn *, rtx, machine_mode, |
a4686d0a | 414 | bool, bool, poly_int64, bool); |
415 | extern void eliminate_regs_in_insn (rtx_insn *insn, bool, bool, poly_int64); | |
3b3a5e5f | 416 | extern void lra_eliminate (bool, bool); |
c6a6cdaa | 417 | |
418 | extern void lra_eliminate_reg_if_possible (rtx *); | |
419 | ||
420 | \f | |
421 | ||
7619e612 | 422 | /* Return the hard register which given pseudo REGNO assigned to. |
423 | Negative value means that the register got memory or we don't know | |
424 | allocation yet. */ | |
425 | static inline int | |
426 | lra_get_regno_hard_regno (int regno) | |
427 | { | |
428 | resize_reg_info (); | |
429 | return reg_renumber[regno]; | |
430 | } | |
431 | ||
432 | /* Change class of pseudo REGNO to NEW_CLASS. Print info about it | |
433 | using TITLE. Output a new line if NL_P. */ | |
434 | static void inline | |
435 | lra_change_class (int regno, enum reg_class new_class, | |
436 | const char *title, bool nl_p) | |
437 | { | |
438 | lra_assert (regno >= FIRST_PSEUDO_REGISTER); | |
439 | if (lra_dump_file != NULL) | |
440 | fprintf (lra_dump_file, "%s class %s for r%d", | |
441 | title, reg_class_names[new_class], regno); | |
442 | setup_reg_classes (regno, new_class, NO_REGS, new_class); | |
443 | if (lra_dump_file != NULL && nl_p) | |
444 | fprintf (lra_dump_file, "\n"); | |
445 | } | |
446 | ||
c6a6cdaa | 447 | /* Update insn operands which are duplication of NOP operand. The |
448 | insn is represented by its LRA internal representation ID. */ | |
449 | static inline void | |
450 | lra_update_dup (lra_insn_recog_data_t id, int nop) | |
451 | { | |
452 | int i; | |
453 | struct lra_static_insn_data *static_id = id->insn_static_data; | |
454 | ||
455 | for (i = 0; i < static_id->n_dups; i++) | |
456 | if (static_id->dup_num[i] == nop) | |
457 | *id->dup_loc[i] = *id->operand_loc[nop]; | |
458 | } | |
459 | ||
460 | /* Process operator duplications in insn with ID. We do it after the | |
461 | operands processing. Generally speaking, we could do this probably | |
462 | simultaneously with operands processing because a common practice | |
463 | is to enumerate the operators after their operands. */ | |
464 | static inline void | |
465 | lra_update_operator_dups (lra_insn_recog_data_t id) | |
466 | { | |
467 | int i; | |
468 | struct lra_static_insn_data *static_id = id->insn_static_data; | |
469 | ||
470 | for (i = 0; i < static_id->n_dups; i++) | |
471 | { | |
472 | int ndup = static_id->dup_num[i]; | |
1a8f8886 | 473 | |
c6a6cdaa | 474 | if (static_id->operand[ndup].is_operator) |
475 | *id->dup_loc[i] = *id->operand_loc[ndup]; | |
476 | } | |
477 | } | |
478 | ||
479 | /* Return info about INSN. Set up the info if it is not done yet. */ | |
480 | static inline lra_insn_recog_data_t | |
7f836b57 | 481 | lra_get_insn_recog_data (rtx_insn *insn) |
c6a6cdaa | 482 | { |
483 | lra_insn_recog_data_t data; | |
484 | unsigned int uid = INSN_UID (insn); | |
485 | ||
486 | if (lra_insn_recog_data_len > (int) uid | |
487 | && (data = lra_insn_recog_data[uid]) != NULL) | |
488 | { | |
489 | /* Check that we did not change insn without updating the insn | |
490 | info. */ | |
491 | lra_assert (data->insn == insn | |
492 | && (INSN_CODE (insn) < 0 | |
493 | || data->icode == INSN_CODE (insn))); | |
494 | return data; | |
495 | } | |
496 | return lra_set_insn_recog_data (insn); | |
497 | } | |
498 | ||
a1064490 | 499 | /* Update offset from pseudos with VAL by INCR. */ |
500 | static inline void | |
a4686d0a | 501 | lra_update_reg_val_offset (int val, poly_int64 incr) |
a1064490 | 502 | { |
503 | int i; | |
504 | ||
505 | for (i = FIRST_PSEUDO_REGISTER; i < max_reg_num (); i++) | |
506 | { | |
507 | if (lra_reg_info[i].val == val) | |
508 | lra_reg_info[i].offset += incr; | |
509 | } | |
510 | } | |
511 | ||
512 | /* Return true if register content is equal to VAL with OFFSET. */ | |
513 | static inline bool | |
a4686d0a | 514 | lra_reg_val_equal_p (int regno, int val, poly_int64 offset) |
a1064490 | 515 | { |
516 | if (lra_reg_info[regno].val == val | |
a4686d0a | 517 | && known_eq (lra_reg_info[regno].offset, offset)) |
a1064490 | 518 | return true; |
519 | ||
520 | return false; | |
521 | } | |
522 | ||
523 | /* Assign value of register FROM to TO. */ | |
524 | static inline void | |
525 | lra_assign_reg_val (int from, int to) | |
526 | { | |
527 | lra_reg_info[to].val = lra_reg_info[from].val; | |
528 | lra_reg_info[to].offset = lra_reg_info[from].offset; | |
529 | } | |
ce6bb0f3 | 530 | |
531 | #endif /* GCC_LRA_INT_H */ |