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c6a6cdaa | 1 | /* Change pseudos by memory. |
fbd26352 | 2 | Copyright (C) 2010-2019 Free Software Foundation, Inc. |
c6a6cdaa | 3 | Contributed by Vladimir Makarov <vmakarov@redhat.com>. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it under | |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 3, or (at your option) any later | |
10 | version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | ||
22 | /* This file contains code for a pass to change spilled pseudos into | |
23 | memory. | |
24 | ||
25 | The pass creates necessary stack slots and assigns spilled pseudos | |
26 | to the stack slots in following way: | |
27 | ||
28 | for all spilled pseudos P most frequently used first do | |
29 | for all stack slots S do | |
30 | if P doesn't conflict with pseudos assigned to S then | |
31 | assign S to P and goto to the next pseudo process | |
32 | end | |
33 | end | |
34 | create new stack slot S and assign P to S | |
35 | end | |
1a8f8886 | 36 | |
c6a6cdaa | 37 | The actual algorithm is bit more complicated because of different |
38 | pseudo sizes. | |
39 | ||
40 | After that the code changes spilled pseudos (except ones created | |
41 | from scratches) by corresponding stack slot memory in RTL. | |
42 | ||
43 | If at least one stack slot was created, we need to run more passes | |
44 | because we have new addresses which should be checked and because | |
45 | the old address displacements might change and address constraints | |
46 | (or insn memory constraints) might not be satisfied any more. | |
47 | ||
48 | For some targets, the pass can spill some pseudos into hard | |
49 | registers of different class (usually into vector registers) | |
50 | instead of spilling them into memory if it is possible and | |
51 | profitable. Spilling GENERAL_REGS pseudo into SSE registers for | |
52 | Intel Corei7 is an example of such optimization. And this is | |
53 | actually recommended by Intel optimization guide. | |
54 | ||
55 | The file also contains code for final change of pseudos on hard | |
56 | regs correspondingly assigned to them. */ | |
57 | ||
58 | #include "config.h" | |
59 | #include "system.h" | |
60 | #include "coretypes.h" | |
9ef16211 | 61 | #include "backend.h" |
7c29e30e | 62 | #include "target.h" |
c6a6cdaa | 63 | #include "rtl.h" |
9ef16211 | 64 | #include "df.h" |
c6a6cdaa | 65 | #include "insn-config.h" |
7c29e30e | 66 | #include "regs.h" |
ad7b10a2 | 67 | #include "memmodel.h" |
7c29e30e | 68 | #include "ira.h" |
c6a6cdaa | 69 | #include "recog.h" |
70 | #include "output.h" | |
94ea8568 | 71 | #include "cfgrtl.h" |
9ef16211 | 72 | #include "lra.h" |
c6a6cdaa | 73 | #include "lra-int.h" |
c6a6cdaa | 74 | |
75 | ||
76 | /* Max regno at the start of the pass. */ | |
77 | static int regs_num; | |
78 | ||
79 | /* Map spilled regno -> hard regno used instead of memory for | |
80 | spilling. */ | |
81 | static rtx *spill_hard_reg; | |
82 | ||
83 | /* The structure describes stack slot of a spilled pseudo. */ | |
84 | struct pseudo_slot | |
85 | { | |
86 | /* Number (0, 1, ...) of the stack slot to which given pseudo | |
87 | belongs. */ | |
88 | int slot_num; | |
89 | /* First or next slot with the same slot number. */ | |
90 | struct pseudo_slot *next, *first; | |
91 | /* Memory representing the spilled pseudo. */ | |
92 | rtx mem; | |
93 | }; | |
94 | ||
95 | /* The stack slots for each spilled pseudo. Indexed by regnos. */ | |
96 | static struct pseudo_slot *pseudo_slots; | |
97 | ||
98 | /* The structure describes a register or a stack slot which can be | |
99 | used for several spilled pseudos. */ | |
251317e4 | 100 | class slot |
c6a6cdaa | 101 | { |
251317e4 | 102 | public: |
c6a6cdaa | 103 | /* First pseudo with given stack slot. */ |
104 | int regno; | |
105 | /* Hard reg into which the slot pseudos are spilled. The value is | |
106 | negative for pseudos spilled into memory. */ | |
107 | int hard_regno; | |
c899a840 | 108 | /* Maximum alignment required by all users of the slot. */ |
109 | unsigned int align; | |
110 | /* Maximum size required by all users of the slot. */ | |
52acb7ae | 111 | poly_int64 size; |
c6a6cdaa | 112 | /* Memory representing the all stack slot. It can be different from |
113 | memory representing a pseudo belonging to give stack slot because | |
114 | pseudo can be placed in a part of the corresponding stack slot. | |
115 | The value is NULL for pseudos spilled into a hard reg. */ | |
116 | rtx mem; | |
117 | /* Combined live ranges of all pseudos belonging to given slot. It | |
118 | is used to figure out that a new spilled pseudo can use given | |
119 | stack slot. */ | |
120 | lra_live_range_t live_ranges; | |
121 | }; | |
122 | ||
123 | /* Array containing info about the stack slots. The array element is | |
124 | indexed by the stack slot number in the range [0..slots_num). */ | |
2e966e2a | 125 | static class slot *slots; |
c6a6cdaa | 126 | /* The number of the stack slots currently existing. */ |
127 | static int slots_num; | |
128 | ||
129 | /* Set up memory of the spilled pseudo I. The function can allocate | |
130 | the corresponding stack slot if it is not done yet. */ | |
131 | static void | |
132 | assign_mem_slot (int i) | |
133 | { | |
134 | rtx x = NULL_RTX; | |
3754d046 | 135 | machine_mode mode = GET_MODE (regno_reg_rtx[i]); |
52acb7ae | 136 | poly_int64 inherent_size = PSEUDO_REGNO_BYTES (i); |
c899a840 | 137 | machine_mode wider_mode |
081c1d32 | 138 | = wider_subreg_mode (mode, lra_reg_info[i].biggest_mode); |
52acb7ae | 139 | poly_int64 total_size = GET_MODE_SIZE (wider_mode); |
9edf7ea8 | 140 | poly_int64 adjust = 0; |
c6a6cdaa | 141 | |
142 | lra_assert (regno_reg_rtx[i] != NULL_RTX && REG_P (regno_reg_rtx[i]) | |
143 | && lra_reg_info[i].nrefs != 0 && reg_renumber[i] < 0); | |
1a8f8886 | 144 | |
c899a840 | 145 | unsigned int slot_num = pseudo_slots[i].slot_num; |
146 | x = slots[slot_num].mem; | |
147 | if (!x) | |
c6a6cdaa | 148 | { |
c899a840 | 149 | x = assign_stack_local (BLKmode, slots[slot_num].size, |
150 | slots[slot_num].align); | |
151 | slots[slot_num].mem = x; | |
c6a6cdaa | 152 | } |
1a8f8886 | 153 | |
c6a6cdaa | 154 | /* On a big endian machine, the "address" of the slot is the address |
155 | of the low part that fits its inherent mode. */ | |
18355707 | 156 | adjust += subreg_size_lowpart_offset (inherent_size, total_size); |
c6a6cdaa | 157 | x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust); |
1a8f8886 | 158 | |
c6a6cdaa | 159 | /* Set all of the memory attributes as appropriate for a spill. */ |
160 | set_mem_attrs_for_spill (x); | |
161 | pseudo_slots[i].mem = x; | |
162 | } | |
163 | ||
164 | /* Sort pseudos according their usage frequencies. */ | |
165 | static int | |
166 | regno_freq_compare (const void *v1p, const void *v2p) | |
167 | { | |
168 | const int regno1 = *(const int *) v1p; | |
169 | const int regno2 = *(const int *) v2p; | |
170 | int diff; | |
171 | ||
172 | if ((diff = lra_reg_info[regno2].freq - lra_reg_info[regno1].freq) != 0) | |
173 | return diff; | |
174 | return regno1 - regno2; | |
175 | } | |
176 | ||
c6a6cdaa | 177 | /* Sort pseudos according to their slots, putting the slots in the order |
48ce740d | 178 | that they should be allocated. |
179 | ||
180 | First prefer to group slots with variable sizes together and slots | |
181 | with constant sizes together, since that usually makes them easier | |
182 | to address from a common anchor point. E.g. loads of polynomial-sized | |
183 | registers tend to take polynomial offsets while loads of constant-sized | |
184 | registers tend to take constant (non-polynomial) offsets. | |
185 | ||
186 | Next, slots with lower numbers have the highest priority and should | |
187 | get the smallest displacement from the stack or frame pointer | |
188 | (whichever is being used). | |
c6a6cdaa | 189 | |
190 | The first allocated slot is always closest to the frame pointer, | |
191 | so prefer lower slot numbers when frame_pointer_needed. If the stack | |
192 | and frame grow in the same direction, then the first allocated slot is | |
193 | always closest to the initial stack pointer and furthest away from the | |
194 | final stack pointer, so allocate higher numbers first when using the | |
195 | stack pointer in that case. The reverse is true if the stack and | |
196 | frame grow in opposite directions. */ | |
197 | static int | |
198 | pseudo_reg_slot_compare (const void *v1p, const void *v2p) | |
199 | { | |
200 | const int regno1 = *(const int *) v1p; | |
201 | const int regno2 = *(const int *) v2p; | |
202 | int diff, slot_num1, slot_num2; | |
c6a6cdaa | 203 | |
204 | slot_num1 = pseudo_slots[regno1].slot_num; | |
205 | slot_num2 = pseudo_slots[regno2].slot_num; | |
48ce740d | 206 | diff = (int (slots[slot_num1].size.is_constant ()) |
207 | - int (slots[slot_num2].size.is_constant ())); | |
208 | if (diff != 0) | |
209 | return diff; | |
c6a6cdaa | 210 | if ((diff = slot_num1 - slot_num2) != 0) |
211 | return (frame_pointer_needed | |
47ed88a3 | 212 | || (!FRAME_GROWS_DOWNWARD) == STACK_GROWS_DOWNWARD ? diff : -diff); |
52acb7ae | 213 | poly_int64 total_size1 = GET_MODE_SIZE (lra_reg_info[regno1].biggest_mode); |
214 | poly_int64 total_size2 = GET_MODE_SIZE (lra_reg_info[regno2].biggest_mode); | |
215 | if ((diff = compare_sizes_for_sort (total_size2, total_size1)) != 0) | |
c6a6cdaa | 216 | return diff; |
217 | return regno1 - regno2; | |
218 | } | |
219 | ||
220 | /* Assign spill hard registers to N pseudos in PSEUDO_REGNOS which is | |
221 | sorted in order of highest frequency first. Put the pseudos which | |
222 | did not get a spill hard register at the beginning of array | |
223 | PSEUDO_REGNOS. Return the number of such pseudos. */ | |
224 | static int | |
225 | assign_spill_hard_regs (int *pseudo_regnos, int n) | |
226 | { | |
227 | int i, k, p, regno, res, spill_class_size, hard_regno, nr; | |
228 | enum reg_class rclass, spill_class; | |
3754d046 | 229 | machine_mode mode; |
c6a6cdaa | 230 | lra_live_range_t r; |
7f836b57 | 231 | rtx_insn *insn; |
232 | rtx set; | |
c6a6cdaa | 233 | basic_block bb; |
234 | HARD_REG_SET conflict_hard_regs; | |
c6a6cdaa | 235 | bitmap setjump_crosses = regstat_get_setjmp_crosses (); |
f4d3c071 | 236 | /* Hard registers which cannot be used for any purpose at given |
c6a6cdaa | 237 | program point because they are unallocatable or already allocated |
1a8f8886 | 238 | for other pseudos. */ |
c6a6cdaa | 239 | HARD_REG_SET *reserved_hard_regs; |
240 | ||
241 | if (! lra_reg_spill_p) | |
242 | return n; | |
243 | /* Set up reserved hard regs for every program point. */ | |
244 | reserved_hard_regs = XNEWVEC (HARD_REG_SET, lra_live_max_point); | |
245 | for (p = 0; p < lra_live_max_point; p++) | |
246 | COPY_HARD_REG_SET (reserved_hard_regs[p], lra_no_alloc_regs); | |
247 | for (i = FIRST_PSEUDO_REGISTER; i < regs_num; i++) | |
248 | if (lra_reg_info[i].nrefs != 0 | |
249 | && (hard_regno = lra_get_regno_hard_regno (i)) >= 0) | |
250 | for (r = lra_reg_info[i].live_ranges; r != NULL; r = r->next) | |
251 | for (p = r->start; p <= r->finish; p++) | |
252 | add_to_hard_reg_set (&reserved_hard_regs[p], | |
253 | lra_reg_info[i].biggest_mode, hard_regno); | |
f6708c36 | 254 | auto_bitmap ok_insn_bitmap (®_obstack); |
fc00614f | 255 | FOR_EACH_BB_FN (bb, cfun) |
c6a6cdaa | 256 | FOR_BB_INSNS (bb, insn) |
257 | if (DEBUG_INSN_P (insn) | |
258 | || ((set = single_set (insn)) != NULL_RTX | |
259 | && REG_P (SET_SRC (set)) && REG_P (SET_DEST (set)))) | |
f6708c36 | 260 | bitmap_set_bit (ok_insn_bitmap, INSN_UID (insn)); |
c6a6cdaa | 261 | for (res = i = 0; i < n; i++) |
262 | { | |
263 | regno = pseudo_regnos[i]; | |
264 | rclass = lra_get_allocno_class (regno); | |
265 | if (bitmap_bit_p (setjump_crosses, regno) | |
266 | || (spill_class | |
267 | = ((enum reg_class) | |
268 | targetm.spill_class ((reg_class_t) rclass, | |
269 | PSEUDO_REGNO_MODE (regno)))) == NO_REGS | |
270 | || bitmap_intersect_compl_p (&lra_reg_info[regno].insn_bitmap, | |
f6708c36 | 271 | ok_insn_bitmap)) |
c6a6cdaa | 272 | { |
273 | pseudo_regnos[res++] = regno; | |
274 | continue; | |
275 | } | |
276 | lra_assert (spill_class != NO_REGS); | |
277 | COPY_HARD_REG_SET (conflict_hard_regs, | |
278 | lra_reg_info[regno].conflict_hard_regs); | |
279 | for (r = lra_reg_info[regno].live_ranges; r != NULL; r = r->next) | |
280 | for (p = r->start; p <= r->finish; p++) | |
281 | IOR_HARD_REG_SET (conflict_hard_regs, reserved_hard_regs[p]); | |
282 | spill_class_size = ira_class_hard_regs_num[spill_class]; | |
283 | mode = lra_reg_info[regno].biggest_mode; | |
284 | for (k = 0; k < spill_class_size; k++) | |
285 | { | |
286 | hard_regno = ira_class_hard_regs[spill_class][k]; | |
287 | if (! overlaps_hard_reg_set_p (conflict_hard_regs, mode, hard_regno)) | |
288 | break; | |
289 | } | |
290 | if (k >= spill_class_size) | |
291 | { | |
292 | /* There is no available regs -- assign memory later. */ | |
293 | pseudo_regnos[res++] = regno; | |
294 | continue; | |
295 | } | |
296 | if (lra_dump_file != NULL) | |
297 | fprintf (lra_dump_file, " Spill r%d into hr%d\n", regno, hard_regno); | |
95f18d43 | 298 | add_to_hard_reg_set (&hard_regs_spilled_into, |
299 | lra_reg_info[regno].biggest_mode, hard_regno); | |
c6a6cdaa | 300 | /* Update reserved_hard_regs. */ |
301 | for (r = lra_reg_info[regno].live_ranges; r != NULL; r = r->next) | |
302 | for (p = r->start; p <= r->finish; p++) | |
303 | add_to_hard_reg_set (&reserved_hard_regs[p], | |
304 | lra_reg_info[regno].biggest_mode, hard_regno); | |
305 | spill_hard_reg[regno] | |
306 | = gen_raw_REG (PSEUDO_REGNO_MODE (regno), hard_regno); | |
307 | for (nr = 0; | |
92d2aec3 | 308 | nr < hard_regno_nregs (hard_regno, |
309 | lra_reg_info[regno].biggest_mode); | |
c6a6cdaa | 310 | nr++) |
fd67653e | 311 | /* Just loop. */ |
312 | df_set_regs_ever_live (hard_regno + nr, true); | |
c6a6cdaa | 313 | } |
c6a6cdaa | 314 | free (reserved_hard_regs); |
315 | return res; | |
316 | } | |
317 | ||
318 | /* Add pseudo REGNO to slot SLOT_NUM. */ | |
319 | static void | |
320 | add_pseudo_to_slot (int regno, int slot_num) | |
321 | { | |
322 | struct pseudo_slot *first; | |
323 | ||
c899a840 | 324 | /* Each pseudo has an inherent size which comes from its own mode, |
325 | and a total size which provides room for paradoxical subregs. | |
326 | We need to make sure the size and alignment of the slot are | |
327 | sufficient for both. */ | |
081c1d32 | 328 | machine_mode mode = wider_subreg_mode (PSEUDO_REGNO_MODE (regno), |
329 | lra_reg_info[regno].biggest_mode); | |
c899a840 | 330 | unsigned int align = spill_slot_alignment (mode); |
331 | slots[slot_num].align = MAX (slots[slot_num].align, align); | |
52acb7ae | 332 | slots[slot_num].size = upper_bound (slots[slot_num].size, |
333 | GET_MODE_SIZE (mode)); | |
c899a840 | 334 | |
c6a6cdaa | 335 | if (slots[slot_num].regno < 0) |
336 | { | |
337 | /* It is the first pseudo in the slot. */ | |
338 | slots[slot_num].regno = regno; | |
339 | pseudo_slots[regno].first = &pseudo_slots[regno]; | |
340 | pseudo_slots[regno].next = NULL; | |
341 | } | |
342 | else | |
343 | { | |
344 | first = pseudo_slots[regno].first = &pseudo_slots[slots[slot_num].regno]; | |
345 | pseudo_slots[regno].next = first->next; | |
346 | first->next = &pseudo_slots[regno]; | |
347 | } | |
348 | pseudo_slots[regno].mem = NULL_RTX; | |
349 | pseudo_slots[regno].slot_num = slot_num; | |
350 | slots[slot_num].live_ranges | |
351 | = lra_merge_live_ranges (slots[slot_num].live_ranges, | |
352 | lra_copy_live_range_list | |
353 | (lra_reg_info[regno].live_ranges)); | |
354 | } | |
355 | ||
356 | /* Assign stack slot numbers to pseudos in array PSEUDO_REGNOS of | |
357 | length N. Sort pseudos in PSEUDO_REGNOS for subsequent assigning | |
358 | memory stack slots. */ | |
359 | static void | |
360 | assign_stack_slot_num_and_sort_pseudos (int *pseudo_regnos, int n) | |
361 | { | |
362 | int i, j, regno; | |
363 | ||
364 | slots_num = 0; | |
365 | /* Assign stack slot numbers to spilled pseudos, use smaller numbers | |
366 | for most frequently used pseudos. */ | |
367 | for (i = 0; i < n; i++) | |
368 | { | |
369 | regno = pseudo_regnos[i]; | |
370 | if (! flag_ira_share_spill_slots) | |
371 | j = slots_num; | |
372 | else | |
373 | { | |
48ce740d | 374 | machine_mode mode |
375 | = wider_subreg_mode (PSEUDO_REGNO_MODE (regno), | |
376 | lra_reg_info[regno].biggest_mode); | |
c6a6cdaa | 377 | for (j = 0; j < slots_num; j++) |
378 | if (slots[j].hard_regno < 0 | |
48ce740d | 379 | /* Although it's possible to share slots between modes |
380 | with constant and non-constant widths, we usually | |
381 | get better spill code by keeping the constant and | |
382 | non-constant areas separate. */ | |
383 | && (GET_MODE_SIZE (mode).is_constant () | |
384 | == slots[j].size.is_constant ()) | |
c6a6cdaa | 385 | && ! (lra_intersected_live_ranges_p |
386 | (slots[j].live_ranges, | |
387 | lra_reg_info[regno].live_ranges))) | |
388 | break; | |
389 | } | |
390 | if (j >= slots_num) | |
391 | { | |
392 | /* New slot. */ | |
393 | slots[j].live_ranges = NULL; | |
c899a840 | 394 | slots[j].size = 0; |
395 | slots[j].align = BITS_PER_UNIT; | |
c6a6cdaa | 396 | slots[j].regno = slots[j].hard_regno = -1; |
397 | slots[j].mem = NULL_RTX; | |
398 | slots_num++; | |
399 | } | |
400 | add_pseudo_to_slot (regno, j); | |
401 | } | |
402 | /* Sort regnos according to their slot numbers. */ | |
403 | qsort (pseudo_regnos, n, sizeof (int), pseudo_reg_slot_compare); | |
404 | } | |
405 | ||
406 | /* Recursively process LOC in INSN and change spilled pseudos to the | |
407 | corresponding memory or spilled hard reg. Ignore spilled pseudos | |
81be349c | 408 | created from the scratches. Return true if the pseudo nrefs equal |
409 | to 0 (don't change the pseudo in this case). Otherwise return false. */ | |
410 | static bool | |
7f836b57 | 411 | remove_pseudos (rtx *loc, rtx_insn *insn) |
c6a6cdaa | 412 | { |
413 | int i; | |
414 | rtx hard_reg; | |
415 | const char *fmt; | |
416 | enum rtx_code code; | |
81be349c | 417 | bool res = false; |
418 | ||
c6a6cdaa | 419 | if (*loc == NULL_RTX) |
81be349c | 420 | return res; |
c6a6cdaa | 421 | code = GET_CODE (*loc); |
422 | if (code == REG && (i = REGNO (*loc)) >= FIRST_PSEUDO_REGISTER | |
423 | && lra_get_regno_hard_regno (i) < 0 | |
424 | /* We do not want to assign memory for former scratches because | |
425 | it might result in an address reload for some targets. In | |
426 | any case we transform such pseudos not getting hard registers | |
427 | into scratches back. */ | |
428 | && ! lra_former_scratch_p (i)) | |
429 | { | |
81be349c | 430 | if (lra_reg_info[i].nrefs == 0 |
431 | && pseudo_slots[i].mem == NULL && spill_hard_reg[i] == NULL) | |
432 | return true; | |
3b3a5e5f | 433 | if ((hard_reg = spill_hard_reg[i]) != NULL_RTX) |
434 | *loc = copy_rtx (hard_reg); | |
435 | else | |
436 | { | |
437 | rtx x = lra_eliminate_regs_1 (insn, pseudo_slots[i].mem, | |
438 | GET_MODE (pseudo_slots[i].mem), | |
99535fab | 439 | false, false, 0, true); |
3b3a5e5f | 440 | *loc = x != pseudo_slots[i].mem ? x : copy_rtx (x); |
441 | } | |
81be349c | 442 | return res; |
c6a6cdaa | 443 | } |
444 | ||
445 | fmt = GET_RTX_FORMAT (code); | |
446 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
447 | { | |
448 | if (fmt[i] == 'e') | |
81be349c | 449 | res = remove_pseudos (&XEXP (*loc, i), insn) || res; |
c6a6cdaa | 450 | else if (fmt[i] == 'E') |
451 | { | |
452 | int j; | |
453 | ||
454 | for (j = XVECLEN (*loc, i) - 1; j >= 0; j--) | |
81be349c | 455 | res = remove_pseudos (&XVECEXP (*loc, i, j), insn) || res; |
c6a6cdaa | 456 | } |
457 | } | |
81be349c | 458 | return res; |
c6a6cdaa | 459 | } |
460 | ||
461 | /* Convert spilled pseudos into their stack slots or spill hard regs, | |
462 | put insns to process on the constraint stack (that is all insns in | |
463 | which pseudos were changed to memory or spill hard regs). */ | |
464 | static void | |
465 | spill_pseudos (void) | |
466 | { | |
467 | basic_block bb; | |
81be349c | 468 | rtx_insn *insn, *curr; |
c6a6cdaa | 469 | int i; |
c6a6cdaa | 470 | |
f6708c36 | 471 | auto_bitmap spilled_pseudos (®_obstack); |
472 | auto_bitmap changed_insns (®_obstack); | |
c6a6cdaa | 473 | for (i = FIRST_PSEUDO_REGISTER; i < regs_num; i++) |
474 | { | |
475 | if (lra_reg_info[i].nrefs != 0 && lra_get_regno_hard_regno (i) < 0 | |
476 | && ! lra_former_scratch_p (i)) | |
477 | { | |
f6708c36 | 478 | bitmap_set_bit (spilled_pseudos, i); |
479 | bitmap_ior_into (changed_insns, &lra_reg_info[i].insn_bitmap); | |
c6a6cdaa | 480 | } |
481 | } | |
fc00614f | 482 | FOR_EACH_BB_FN (bb, cfun) |
c6a6cdaa | 483 | { |
81be349c | 484 | FOR_BB_INSNS_SAFE (bb, insn, curr) |
485 | { | |
486 | bool removed_pseudo_p = false; | |
487 | ||
f6708c36 | 488 | if (bitmap_bit_p (changed_insns, INSN_UID (insn))) |
81be349c | 489 | { |
490 | rtx *link_loc, link; | |
491 | ||
492 | removed_pseudo_p = remove_pseudos (&PATTERN (insn), insn); | |
493 | if (CALL_P (insn) | |
494 | && remove_pseudos (&CALL_INSN_FUNCTION_USAGE (insn), insn)) | |
495 | removed_pseudo_p = true; | |
496 | for (link_loc = ®_NOTES (insn); | |
497 | (link = *link_loc) != NULL_RTX; | |
498 | link_loc = &XEXP (link, 1)) | |
499 | { | |
500 | switch (REG_NOTE_KIND (link)) | |
501 | { | |
502 | case REG_FRAME_RELATED_EXPR: | |
503 | case REG_CFA_DEF_CFA: | |
504 | case REG_CFA_ADJUST_CFA: | |
505 | case REG_CFA_OFFSET: | |
506 | case REG_CFA_REGISTER: | |
507 | case REG_CFA_EXPRESSION: | |
508 | case REG_CFA_RESTORE: | |
509 | case REG_CFA_SET_VDRAP: | |
510 | if (remove_pseudos (&XEXP (link, 0), insn)) | |
511 | removed_pseudo_p = true; | |
512 | break; | |
513 | default: | |
514 | break; | |
515 | } | |
516 | } | |
517 | if (lra_dump_file != NULL) | |
518 | fprintf (lra_dump_file, | |
519 | "Changing spilled pseudos to memory in insn #%u\n", | |
520 | INSN_UID (insn)); | |
521 | lra_push_insn (insn); | |
522 | if (lra_reg_spill_p || targetm.different_addr_displacement_p ()) | |
71d47a14 | 523 | lra_set_used_insn_alternative (insn, LRA_UNKNOWN_ALT); |
81be349c | 524 | } |
525 | else if (CALL_P (insn) | |
526 | /* Presence of any pseudo in CALL_INSN_FUNCTION_USAGE | |
527 | does not affect value of insn_bitmap of the | |
528 | corresponding lra_reg_info. That is because we | |
529 | don't need to reload pseudos in | |
530 | CALL_INSN_FUNCTION_USAGEs. So if we process only | |
531 | insns in the insn_bitmap of given pseudo here, we | |
532 | can miss the pseudo in some | |
533 | CALL_INSN_FUNCTION_USAGEs. */ | |
534 | && remove_pseudos (&CALL_INSN_FUNCTION_USAGE (insn), insn)) | |
535 | removed_pseudo_p = true; | |
536 | if (removed_pseudo_p) | |
537 | { | |
538 | lra_assert (DEBUG_INSN_P (insn)); | |
0b54d964 | 539 | lra_invalidate_insn_data (insn); |
540 | INSN_VAR_LOCATION_LOC (insn) = gen_rtx_UNKNOWN_VAR_LOC (); | |
81be349c | 541 | if (lra_dump_file != NULL) |
542 | fprintf (lra_dump_file, | |
0b54d964 | 543 | "Debug insn #%u is reset because it referenced " |
544 | "removed pseudo\n", INSN_UID (insn)); | |
81be349c | 545 | } |
f6708c36 | 546 | bitmap_and_compl_into (df_get_live_in (bb), spilled_pseudos); |
547 | bitmap_and_compl_into (df_get_live_out (bb), spilled_pseudos); | |
81be349c | 548 | } |
c6a6cdaa | 549 | } |
c6a6cdaa | 550 | } |
551 | ||
c8b6743f | 552 | /* Return true if we need scratch reg assignments. */ |
553 | bool | |
554 | lra_need_for_scratch_reg_p (void) | |
555 | { | |
556 | int i; max_regno = max_reg_num (); | |
557 | ||
558 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
559 | if (lra_reg_info[i].nrefs != 0 && lra_get_regno_hard_regno (i) < 0 | |
560 | && lra_former_scratch_p (i)) | |
561 | return true; | |
562 | return false; | |
563 | } | |
564 | ||
c6a6cdaa | 565 | /* Return true if we need to change some pseudos into memory. */ |
566 | bool | |
567 | lra_need_for_spills_p (void) | |
568 | { | |
569 | int i; max_regno = max_reg_num (); | |
570 | ||
571 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
572 | if (lra_reg_info[i].nrefs != 0 && lra_get_regno_hard_regno (i) < 0 | |
573 | && ! lra_former_scratch_p (i)) | |
574 | return true; | |
575 | return false; | |
576 | } | |
577 | ||
578 | /* Change spilled pseudos into memory or spill hard regs. Put changed | |
579 | insns on the constraint stack (these insns will be considered on | |
580 | the next constraint pass). The changed insns are all insns in | |
581 | which pseudos were changed. */ | |
582 | void | |
583 | lra_spill (void) | |
584 | { | |
585 | int i, n, curr_regno; | |
586 | int *pseudo_regnos; | |
587 | ||
588 | regs_num = max_reg_num (); | |
589 | spill_hard_reg = XNEWVEC (rtx, regs_num); | |
590 | pseudo_regnos = XNEWVEC (int, regs_num); | |
591 | for (n = 0, i = FIRST_PSEUDO_REGISTER; i < regs_num; i++) | |
592 | if (lra_reg_info[i].nrefs != 0 && lra_get_regno_hard_regno (i) < 0 | |
593 | /* We do not want to assign memory for former scratches. */ | |
594 | && ! lra_former_scratch_p (i)) | |
81be349c | 595 | pseudo_regnos[n++] = i; |
c6a6cdaa | 596 | lra_assert (n > 0); |
597 | pseudo_slots = XNEWVEC (struct pseudo_slot, regs_num); | |
81be349c | 598 | for (i = FIRST_PSEUDO_REGISTER; i < regs_num; i++) |
599 | { | |
600 | spill_hard_reg[i] = NULL_RTX; | |
601 | pseudo_slots[i].mem = NULL_RTX; | |
602 | } | |
2e966e2a | 603 | slots = XNEWVEC (class slot, regs_num); |
c6a6cdaa | 604 | /* Sort regnos according their usage frequencies. */ |
605 | qsort (pseudo_regnos, n, sizeof (int), regno_freq_compare); | |
606 | n = assign_spill_hard_regs (pseudo_regnos, n); | |
607 | assign_stack_slot_num_and_sort_pseudos (pseudo_regnos, n); | |
608 | for (i = 0; i < n; i++) | |
609 | if (pseudo_slots[pseudo_regnos[i]].mem == NULL_RTX) | |
610 | assign_mem_slot (pseudo_regnos[i]); | |
ea99c7a1 | 611 | if (n > 0 && crtl->stack_alignment_needed) |
612 | /* If we have a stack frame, we must align it now. The stack size | |
613 | may be a part of the offset computation for register | |
614 | elimination. */ | |
615 | assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed); | |
c6a6cdaa | 616 | if (lra_dump_file != NULL) |
617 | { | |
618 | for (i = 0; i < slots_num; i++) | |
619 | { | |
52acb7ae | 620 | fprintf (lra_dump_file, " Slot %d regnos (width = ", i); |
621 | print_dec (GET_MODE_SIZE (GET_MODE (slots[i].mem)), | |
622 | lra_dump_file, SIGNED); | |
623 | fprintf (lra_dump_file, "):"); | |
c6a6cdaa | 624 | for (curr_regno = slots[i].regno;; |
625 | curr_regno = pseudo_slots[curr_regno].next - pseudo_slots) | |
626 | { | |
627 | fprintf (lra_dump_file, " %d", curr_regno); | |
628 | if (pseudo_slots[curr_regno].next == NULL) | |
629 | break; | |
630 | } | |
631 | fprintf (lra_dump_file, "\n"); | |
632 | } | |
633 | } | |
634 | spill_pseudos (); | |
635 | free (slots); | |
636 | free (pseudo_slots); | |
637 | free (pseudo_regnos); | |
ed8fbc55 | 638 | free (spill_hard_reg); |
c6a6cdaa | 639 | } |
640 | ||
55277a10 | 641 | /* Apply alter_subreg for subregs of regs in *LOC. Use FINAL_P for |
642 | alter_subreg calls. Return true if any subreg of reg is | |
643 | processed. */ | |
644 | static bool | |
645 | alter_subregs (rtx *loc, bool final_p) | |
646 | { | |
647 | int i; | |
648 | rtx x = *loc; | |
649 | bool res; | |
650 | const char *fmt; | |
651 | enum rtx_code code; | |
652 | ||
653 | if (x == NULL_RTX) | |
654 | return false; | |
655 | code = GET_CODE (x); | |
656 | if (code == SUBREG && REG_P (SUBREG_REG (x))) | |
657 | { | |
658 | lra_assert (REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER); | |
659 | alter_subreg (loc, final_p); | |
660 | return true; | |
661 | } | |
662 | fmt = GET_RTX_FORMAT (code); | |
663 | res = false; | |
664 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
665 | { | |
666 | if (fmt[i] == 'e') | |
667 | { | |
668 | if (alter_subregs (&XEXP (x, i), final_p)) | |
669 | res = true; | |
670 | } | |
671 | else if (fmt[i] == 'E') | |
672 | { | |
673 | int j; | |
1a8f8886 | 674 | |
55277a10 | 675 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
676 | if (alter_subregs (&XVECEXP (x, i, j), final_p)) | |
677 | res = true; | |
678 | } | |
679 | } | |
680 | return res; | |
681 | } | |
682 | ||
8dd9f7ce | 683 | /* Return true if REGNO is used for return in the current |
684 | function. */ | |
685 | static bool | |
686 | return_regno_p (unsigned int regno) | |
687 | { | |
688 | rtx outgoing = crtl->return_rtx; | |
689 | ||
690 | if (! outgoing) | |
691 | return false; | |
692 | ||
693 | if (REG_P (outgoing)) | |
694 | return REGNO (outgoing) == regno; | |
695 | else if (GET_CODE (outgoing) == PARALLEL) | |
696 | { | |
697 | int i; | |
698 | ||
699 | for (i = 0; i < XVECLEN (outgoing, 0); i++) | |
700 | { | |
701 | rtx x = XEXP (XVECEXP (outgoing, 0, i), 0); | |
702 | ||
703 | if (REG_P (x) && REGNO (x) == regno) | |
704 | return true; | |
705 | } | |
706 | } | |
707 | return false; | |
708 | } | |
709 | ||
c2a19a33 | 710 | /* Return true if REGNO is in one of subsequent USE after INSN in the |
711 | same BB. */ | |
9b72ac78 | 712 | static bool |
713 | regno_in_use_p (rtx_insn *insn, unsigned int regno) | |
714 | { | |
c2a19a33 | 715 | static lra_insn_recog_data_t id; |
716 | static struct lra_static_insn_data *static_id; | |
717 | struct lra_insn_reg *reg; | |
718 | int i, arg_regno; | |
719 | basic_block bb = BLOCK_FOR_INSN (insn); | |
720 | ||
179ad376 | 721 | while ((insn = next_nondebug_insn (insn)) != NULL_RTX) |
9b72ac78 | 722 | { |
179ad376 | 723 | if (BARRIER_P (insn) || bb != BLOCK_FOR_INSN (insn)) |
724 | return false; | |
c2a19a33 | 725 | if (! INSN_P (insn)) |
726 | continue; | |
727 | if (GET_CODE (PATTERN (insn)) == USE | |
728 | && REG_P (XEXP (PATTERN (insn), 0)) | |
9b72ac78 | 729 | && regno == REGNO (XEXP (PATTERN (insn), 0))) |
c2a19a33 | 730 | return true; |
731 | /* Check that the regno is not modified. */ | |
732 | id = lra_get_insn_recog_data (insn); | |
733 | for (reg = id->regs; reg != NULL; reg = reg->next) | |
734 | if (reg->type != OP_IN && reg->regno == (int) regno) | |
735 | return false; | |
736 | static_id = id->insn_static_data; | |
737 | for (reg = static_id->hard_regs; reg != NULL; reg = reg->next) | |
738 | if (reg->type != OP_IN && reg->regno == (int) regno) | |
739 | return false; | |
740 | if (id->arg_hard_regs != NULL) | |
741 | for (i = 0; (arg_regno = id->arg_hard_regs[i]) >= 0; i++) | |
742 | if ((int) regno == (arg_regno >= FIRST_PSEUDO_REGISTER | |
743 | ? arg_regno : arg_regno - FIRST_PSEUDO_REGISTER)) | |
744 | return false; | |
9b72ac78 | 745 | } |
746 | return false; | |
747 | } | |
748 | ||
c6a6cdaa | 749 | /* Final change of pseudos got hard registers into the corresponding |
ae72d5b2 | 750 | hard registers and removing temporary clobbers. */ |
c6a6cdaa | 751 | void |
ae72d5b2 | 752 | lra_final_code_change (void) |
c6a6cdaa | 753 | { |
754 | int i, hard_regno; | |
755 | basic_block bb; | |
9b72ac78 | 756 | rtx_insn *insn, *curr; |
3114c9f4 | 757 | rtx set; |
c6a6cdaa | 758 | int max_regno = max_reg_num (); |
759 | ||
760 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
761 | if (lra_reg_info[i].nrefs != 0 | |
762 | && (hard_regno = lra_get_regno_hard_regno (i)) >= 0) | |
763 | SET_REGNO (regno_reg_rtx[i], hard_regno); | |
fc00614f | 764 | FOR_EACH_BB_FN (bb, cfun) |
ae72d5b2 | 765 | FOR_BB_INSNS_SAFE (bb, insn, curr) |
c6a6cdaa | 766 | if (INSN_P (insn)) |
767 | { | |
ae72d5b2 | 768 | rtx pat = PATTERN (insn); |
769 | ||
770 | if (GET_CODE (pat) == CLOBBER && LRA_TEMP_CLOBBER_P (pat)) | |
771 | { | |
772 | /* Remove clobbers temporarily created in LRA. We don't | |
773 | need them anymore and don't want to waste compiler | |
774 | time processing them in a few subsequent passes. */ | |
775 | lra_invalidate_insn_data (insn); | |
93ff53d3 | 776 | delete_insn (insn); |
ae72d5b2 | 777 | continue; |
778 | } | |
779 | ||
8dd9f7ce | 780 | /* IRA can generate move insns involving pseudos. It is |
781 | better remove them earlier to speed up compiler a bit. | |
782 | It is also better to do it here as they might not pass | |
783 | final RTL check in LRA, (e.g. insn moving a control | |
784 | register into itself). So remove an useless move insn | |
785 | unless next insn is USE marking the return reg (we should | |
786 | save this as some subsequent optimizations assume that | |
787 | such original insns are saved). */ | |
788 | if (NONJUMP_INSN_P (insn) && GET_CODE (pat) == SET | |
789 | && REG_P (SET_SRC (pat)) && REG_P (SET_DEST (pat)) | |
790 | && REGNO (SET_SRC (pat)) == REGNO (SET_DEST (pat)) | |
ab4ea053 | 791 | && (! return_regno_p (REGNO (SET_SRC (pat))) |
9b72ac78 | 792 | || ! regno_in_use_p (insn, REGNO (SET_SRC (pat))))) |
8dd9f7ce | 793 | { |
794 | lra_invalidate_insn_data (insn); | |
795 | delete_insn (insn); | |
796 | continue; | |
797 | } | |
798 | ||
55277a10 | 799 | lra_insn_recog_data_t id = lra_get_insn_recog_data (insn); |
5f40c956 | 800 | struct lra_insn_reg *reg; |
801 | ||
802 | for (reg = id->regs; reg != NULL; reg = reg->next) | |
803 | if (reg->regno >= FIRST_PSEUDO_REGISTER | |
804 | && lra_reg_info [reg->regno].nrefs == 0) | |
805 | break; | |
806 | ||
807 | if (reg != NULL) | |
808 | { | |
809 | /* Pseudos still can be in debug insns in some very rare | |
810 | and complicated cases, e.g. the pseudo was removed by | |
811 | inheritance and the debug insn is not EBBs where the | |
812 | inheritance happened. It is difficult and time | |
813 | consuming to find what hard register corresponds the | |
814 | pseudo -- so just remove the debug insn. Another | |
815 | solution could be assigning hard reg/memory but it | |
816 | would be a misleading info. It is better not to have | |
817 | info than have it wrong. */ | |
818 | lra_assert (DEBUG_INSN_P (insn)); | |
819 | lra_invalidate_insn_data (insn); | |
820 | delete_insn (insn); | |
821 | continue; | |
822 | } | |
823 | ||
ea99c7a1 | 824 | struct lra_static_insn_data *static_id = id->insn_static_data; |
c6a6cdaa | 825 | bool insn_change_p = false; |
b0d8930a | 826 | |
827 | for (i = id->insn_static_data->n_operands - 1; i >= 0; i--) | |
828 | if ((DEBUG_INSN_P (insn) || ! static_id->operand[i].is_operator) | |
829 | && alter_subregs (id->operand_loc[i], ! DEBUG_INSN_P (insn))) | |
830 | { | |
831 | lra_update_dup (id, i); | |
832 | insn_change_p = true; | |
833 | } | |
c6a6cdaa | 834 | if (insn_change_p) |
835 | lra_update_operator_dups (id); | |
3114c9f4 | 836 | |
837 | if ((set = single_set (insn)) != NULL | |
838 | && REG_P (SET_SRC (set)) && REG_P (SET_DEST (set)) | |
839 | && REGNO (SET_SRC (set)) == REGNO (SET_DEST (set))) | |
840 | { | |
841 | /* Remove an useless move insn. IRA can generate move | |
842 | insns involving pseudos. It is better remove them | |
843 | earlier to speed up compiler a bit. It is also | |
844 | better to do it here as they might not pass final RTL | |
845 | check in LRA, (e.g. insn moving a control register | |
846 | into itself). */ | |
847 | lra_invalidate_insn_data (insn); | |
848 | delete_insn (insn); | |
849 | } | |
c6a6cdaa | 850 | } |
851 | } |