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55a2c322 | 1 | /* Change pseudos by memory. |
85ec4feb | 2 | Copyright (C) 2010-2018 Free Software Foundation, Inc. |
55a2c322 VM |
3 | Contributed by Vladimir Makarov <vmakarov@redhat.com>. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it under | |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 3, or (at your option) any later | |
10 | version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | ||
22 | /* This file contains code for a pass to change spilled pseudos into | |
23 | memory. | |
24 | ||
25 | The pass creates necessary stack slots and assigns spilled pseudos | |
26 | to the stack slots in following way: | |
27 | ||
28 | for all spilled pseudos P most frequently used first do | |
29 | for all stack slots S do | |
30 | if P doesn't conflict with pseudos assigned to S then | |
31 | assign S to P and goto to the next pseudo process | |
32 | end | |
33 | end | |
34 | create new stack slot S and assign P to S | |
35 | end | |
f4eafc30 | 36 | |
55a2c322 VM |
37 | The actual algorithm is bit more complicated because of different |
38 | pseudo sizes. | |
39 | ||
40 | After that the code changes spilled pseudos (except ones created | |
41 | from scratches) by corresponding stack slot memory in RTL. | |
42 | ||
43 | If at least one stack slot was created, we need to run more passes | |
44 | because we have new addresses which should be checked and because | |
45 | the old address displacements might change and address constraints | |
46 | (or insn memory constraints) might not be satisfied any more. | |
47 | ||
48 | For some targets, the pass can spill some pseudos into hard | |
49 | registers of different class (usually into vector registers) | |
50 | instead of spilling them into memory if it is possible and | |
51 | profitable. Spilling GENERAL_REGS pseudo into SSE registers for | |
52 | Intel Corei7 is an example of such optimization. And this is | |
53 | actually recommended by Intel optimization guide. | |
54 | ||
55 | The file also contains code for final change of pseudos on hard | |
56 | regs correspondingly assigned to them. */ | |
57 | ||
58 | #include "config.h" | |
59 | #include "system.h" | |
60 | #include "coretypes.h" | |
c7131fb2 | 61 | #include "backend.h" |
957060b5 | 62 | #include "target.h" |
55a2c322 | 63 | #include "rtl.h" |
c7131fb2 | 64 | #include "df.h" |
55a2c322 | 65 | #include "insn-config.h" |
957060b5 | 66 | #include "regs.h" |
4d0cdd0c | 67 | #include "memmodel.h" |
957060b5 | 68 | #include "ira.h" |
55a2c322 VM |
69 | #include "recog.h" |
70 | #include "output.h" | |
60393bbc | 71 | #include "cfgrtl.h" |
c7131fb2 | 72 | #include "lra.h" |
55a2c322 | 73 | #include "lra-int.h" |
55a2c322 VM |
74 | |
75 | ||
76 | /* Max regno at the start of the pass. */ | |
77 | static int regs_num; | |
78 | ||
79 | /* Map spilled regno -> hard regno used instead of memory for | |
80 | spilling. */ | |
81 | static rtx *spill_hard_reg; | |
82 | ||
83 | /* The structure describes stack slot of a spilled pseudo. */ | |
84 | struct pseudo_slot | |
85 | { | |
86 | /* Number (0, 1, ...) of the stack slot to which given pseudo | |
87 | belongs. */ | |
88 | int slot_num; | |
89 | /* First or next slot with the same slot number. */ | |
90 | struct pseudo_slot *next, *first; | |
91 | /* Memory representing the spilled pseudo. */ | |
92 | rtx mem; | |
93 | }; | |
94 | ||
95 | /* The stack slots for each spilled pseudo. Indexed by regnos. */ | |
96 | static struct pseudo_slot *pseudo_slots; | |
97 | ||
98 | /* The structure describes a register or a stack slot which can be | |
99 | used for several spilled pseudos. */ | |
100 | struct slot | |
101 | { | |
102 | /* First pseudo with given stack slot. */ | |
103 | int regno; | |
104 | /* Hard reg into which the slot pseudos are spilled. The value is | |
105 | negative for pseudos spilled into memory. */ | |
106 | int hard_regno; | |
83d0488b RS |
107 | /* Maximum alignment required by all users of the slot. */ |
108 | unsigned int align; | |
109 | /* Maximum size required by all users of the slot. */ | |
cf098191 | 110 | poly_int64 size; |
55a2c322 VM |
111 | /* Memory representing the all stack slot. It can be different from |
112 | memory representing a pseudo belonging to give stack slot because | |
113 | pseudo can be placed in a part of the corresponding stack slot. | |
114 | The value is NULL for pseudos spilled into a hard reg. */ | |
115 | rtx mem; | |
116 | /* Combined live ranges of all pseudos belonging to given slot. It | |
117 | is used to figure out that a new spilled pseudo can use given | |
118 | stack slot. */ | |
119 | lra_live_range_t live_ranges; | |
120 | }; | |
121 | ||
122 | /* Array containing info about the stack slots. The array element is | |
123 | indexed by the stack slot number in the range [0..slots_num). */ | |
124 | static struct slot *slots; | |
125 | /* The number of the stack slots currently existing. */ | |
126 | static int slots_num; | |
127 | ||
128 | /* Set up memory of the spilled pseudo I. The function can allocate | |
129 | the corresponding stack slot if it is not done yet. */ | |
130 | static void | |
131 | assign_mem_slot (int i) | |
132 | { | |
133 | rtx x = NULL_RTX; | |
ef4bddc2 | 134 | machine_mode mode = GET_MODE (regno_reg_rtx[i]); |
cf098191 | 135 | poly_int64 inherent_size = PSEUDO_REGNO_BYTES (i); |
83d0488b | 136 | machine_mode wider_mode |
bd5a2c67 | 137 | = wider_subreg_mode (mode, lra_reg_info[i].biggest_mode); |
cf098191 | 138 | poly_int64 total_size = GET_MODE_SIZE (wider_mode); |
91914e56 | 139 | poly_int64 adjust = 0; |
55a2c322 VM |
140 | |
141 | lra_assert (regno_reg_rtx[i] != NULL_RTX && REG_P (regno_reg_rtx[i]) | |
142 | && lra_reg_info[i].nrefs != 0 && reg_renumber[i] < 0); | |
f4eafc30 | 143 | |
83d0488b RS |
144 | unsigned int slot_num = pseudo_slots[i].slot_num; |
145 | x = slots[slot_num].mem; | |
146 | if (!x) | |
55a2c322 | 147 | { |
83d0488b RS |
148 | x = assign_stack_local (BLKmode, slots[slot_num].size, |
149 | slots[slot_num].align); | |
150 | slots[slot_num].mem = x; | |
55a2c322 | 151 | } |
f4eafc30 | 152 | |
55a2c322 VM |
153 | /* On a big endian machine, the "address" of the slot is the address |
154 | of the low part that fits its inherent mode. */ | |
e10326ff | 155 | adjust += subreg_size_lowpart_offset (inherent_size, total_size); |
55a2c322 | 156 | x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust); |
f4eafc30 | 157 | |
55a2c322 VM |
158 | /* Set all of the memory attributes as appropriate for a spill. */ |
159 | set_mem_attrs_for_spill (x); | |
160 | pseudo_slots[i].mem = x; | |
161 | } | |
162 | ||
163 | /* Sort pseudos according their usage frequencies. */ | |
164 | static int | |
165 | regno_freq_compare (const void *v1p, const void *v2p) | |
166 | { | |
167 | const int regno1 = *(const int *) v1p; | |
168 | const int regno2 = *(const int *) v2p; | |
169 | int diff; | |
170 | ||
171 | if ((diff = lra_reg_info[regno2].freq - lra_reg_info[regno1].freq) != 0) | |
172 | return diff; | |
173 | return regno1 - regno2; | |
174 | } | |
175 | ||
55a2c322 VM |
176 | /* Sort pseudos according to their slots, putting the slots in the order |
177 | that they should be allocated. Slots with lower numbers have the highest | |
178 | priority and should get the smallest displacement from the stack or | |
179 | frame pointer (whichever is being used). | |
180 | ||
181 | The first allocated slot is always closest to the frame pointer, | |
182 | so prefer lower slot numbers when frame_pointer_needed. If the stack | |
183 | and frame grow in the same direction, then the first allocated slot is | |
184 | always closest to the initial stack pointer and furthest away from the | |
185 | final stack pointer, so allocate higher numbers first when using the | |
186 | stack pointer in that case. The reverse is true if the stack and | |
187 | frame grow in opposite directions. */ | |
188 | static int | |
189 | pseudo_reg_slot_compare (const void *v1p, const void *v2p) | |
190 | { | |
191 | const int regno1 = *(const int *) v1p; | |
192 | const int regno2 = *(const int *) v2p; | |
193 | int diff, slot_num1, slot_num2; | |
55a2c322 VM |
194 | |
195 | slot_num1 = pseudo_slots[regno1].slot_num; | |
196 | slot_num2 = pseudo_slots[regno2].slot_num; | |
197 | if ((diff = slot_num1 - slot_num2) != 0) | |
198 | return (frame_pointer_needed | |
e0bf0dc2 | 199 | || (!FRAME_GROWS_DOWNWARD) == STACK_GROWS_DOWNWARD ? diff : -diff); |
cf098191 RS |
200 | poly_int64 total_size1 = GET_MODE_SIZE (lra_reg_info[regno1].biggest_mode); |
201 | poly_int64 total_size2 = GET_MODE_SIZE (lra_reg_info[regno2].biggest_mode); | |
202 | if ((diff = compare_sizes_for_sort (total_size2, total_size1)) != 0) | |
55a2c322 VM |
203 | return diff; |
204 | return regno1 - regno2; | |
205 | } | |
206 | ||
207 | /* Assign spill hard registers to N pseudos in PSEUDO_REGNOS which is | |
208 | sorted in order of highest frequency first. Put the pseudos which | |
209 | did not get a spill hard register at the beginning of array | |
210 | PSEUDO_REGNOS. Return the number of such pseudos. */ | |
211 | static int | |
212 | assign_spill_hard_regs (int *pseudo_regnos, int n) | |
213 | { | |
214 | int i, k, p, regno, res, spill_class_size, hard_regno, nr; | |
215 | enum reg_class rclass, spill_class; | |
ef4bddc2 | 216 | machine_mode mode; |
55a2c322 | 217 | lra_live_range_t r; |
cfa434f6 DM |
218 | rtx_insn *insn; |
219 | rtx set; | |
55a2c322 VM |
220 | basic_block bb; |
221 | HARD_REG_SET conflict_hard_regs; | |
55a2c322 VM |
222 | bitmap setjump_crosses = regstat_get_setjmp_crosses (); |
223 | /* Hard registers which can not be used for any purpose at given | |
224 | program point because they are unallocatable or already allocated | |
f4eafc30 | 225 | for other pseudos. */ |
55a2c322 VM |
226 | HARD_REG_SET *reserved_hard_regs; |
227 | ||
228 | if (! lra_reg_spill_p) | |
229 | return n; | |
230 | /* Set up reserved hard regs for every program point. */ | |
231 | reserved_hard_regs = XNEWVEC (HARD_REG_SET, lra_live_max_point); | |
232 | for (p = 0; p < lra_live_max_point; p++) | |
233 | COPY_HARD_REG_SET (reserved_hard_regs[p], lra_no_alloc_regs); | |
234 | for (i = FIRST_PSEUDO_REGISTER; i < regs_num; i++) | |
235 | if (lra_reg_info[i].nrefs != 0 | |
236 | && (hard_regno = lra_get_regno_hard_regno (i)) >= 0) | |
237 | for (r = lra_reg_info[i].live_ranges; r != NULL; r = r->next) | |
238 | for (p = r->start; p <= r->finish; p++) | |
239 | add_to_hard_reg_set (&reserved_hard_regs[p], | |
240 | lra_reg_info[i].biggest_mode, hard_regno); | |
d648b5ff | 241 | auto_bitmap ok_insn_bitmap (®_obstack); |
11cd3bed | 242 | FOR_EACH_BB_FN (bb, cfun) |
55a2c322 VM |
243 | FOR_BB_INSNS (bb, insn) |
244 | if (DEBUG_INSN_P (insn) | |
245 | || ((set = single_set (insn)) != NULL_RTX | |
246 | && REG_P (SET_SRC (set)) && REG_P (SET_DEST (set)))) | |
d648b5ff | 247 | bitmap_set_bit (ok_insn_bitmap, INSN_UID (insn)); |
55a2c322 VM |
248 | for (res = i = 0; i < n; i++) |
249 | { | |
250 | regno = pseudo_regnos[i]; | |
251 | rclass = lra_get_allocno_class (regno); | |
252 | if (bitmap_bit_p (setjump_crosses, regno) | |
253 | || (spill_class | |
254 | = ((enum reg_class) | |
255 | targetm.spill_class ((reg_class_t) rclass, | |
256 | PSEUDO_REGNO_MODE (regno)))) == NO_REGS | |
257 | || bitmap_intersect_compl_p (&lra_reg_info[regno].insn_bitmap, | |
d648b5ff | 258 | ok_insn_bitmap)) |
55a2c322 VM |
259 | { |
260 | pseudo_regnos[res++] = regno; | |
261 | continue; | |
262 | } | |
263 | lra_assert (spill_class != NO_REGS); | |
264 | COPY_HARD_REG_SET (conflict_hard_regs, | |
265 | lra_reg_info[regno].conflict_hard_regs); | |
266 | for (r = lra_reg_info[regno].live_ranges; r != NULL; r = r->next) | |
267 | for (p = r->start; p <= r->finish; p++) | |
268 | IOR_HARD_REG_SET (conflict_hard_regs, reserved_hard_regs[p]); | |
269 | spill_class_size = ira_class_hard_regs_num[spill_class]; | |
270 | mode = lra_reg_info[regno].biggest_mode; | |
271 | for (k = 0; k < spill_class_size; k++) | |
272 | { | |
273 | hard_regno = ira_class_hard_regs[spill_class][k]; | |
274 | if (! overlaps_hard_reg_set_p (conflict_hard_regs, mode, hard_regno)) | |
275 | break; | |
276 | } | |
277 | if (k >= spill_class_size) | |
278 | { | |
279 | /* There is no available regs -- assign memory later. */ | |
280 | pseudo_regnos[res++] = regno; | |
281 | continue; | |
282 | } | |
283 | if (lra_dump_file != NULL) | |
284 | fprintf (lra_dump_file, " Spill r%d into hr%d\n", regno, hard_regno); | |
285 | /* Update reserved_hard_regs. */ | |
286 | for (r = lra_reg_info[regno].live_ranges; r != NULL; r = r->next) | |
287 | for (p = r->start; p <= r->finish; p++) | |
288 | add_to_hard_reg_set (&reserved_hard_regs[p], | |
289 | lra_reg_info[regno].biggest_mode, hard_regno); | |
290 | spill_hard_reg[regno] | |
291 | = gen_raw_REG (PSEUDO_REGNO_MODE (regno), hard_regno); | |
292 | for (nr = 0; | |
ad474626 RS |
293 | nr < hard_regno_nregs (hard_regno, |
294 | lra_reg_info[regno].biggest_mode); | |
55a2c322 | 295 | nr++) |
7a59fa3a RS |
296 | /* Just loop. */ |
297 | df_set_regs_ever_live (hard_regno + nr, true); | |
55a2c322 | 298 | } |
55a2c322 VM |
299 | free (reserved_hard_regs); |
300 | return res; | |
301 | } | |
302 | ||
303 | /* Add pseudo REGNO to slot SLOT_NUM. */ | |
304 | static void | |
305 | add_pseudo_to_slot (int regno, int slot_num) | |
306 | { | |
307 | struct pseudo_slot *first; | |
308 | ||
83d0488b RS |
309 | /* Each pseudo has an inherent size which comes from its own mode, |
310 | and a total size which provides room for paradoxical subregs. | |
311 | We need to make sure the size and alignment of the slot are | |
312 | sufficient for both. */ | |
bd5a2c67 RS |
313 | machine_mode mode = wider_subreg_mode (PSEUDO_REGNO_MODE (regno), |
314 | lra_reg_info[regno].biggest_mode); | |
83d0488b RS |
315 | unsigned int align = spill_slot_alignment (mode); |
316 | slots[slot_num].align = MAX (slots[slot_num].align, align); | |
cf098191 RS |
317 | slots[slot_num].size = upper_bound (slots[slot_num].size, |
318 | GET_MODE_SIZE (mode)); | |
83d0488b | 319 | |
55a2c322 VM |
320 | if (slots[slot_num].regno < 0) |
321 | { | |
322 | /* It is the first pseudo in the slot. */ | |
323 | slots[slot_num].regno = regno; | |
324 | pseudo_slots[regno].first = &pseudo_slots[regno]; | |
325 | pseudo_slots[regno].next = NULL; | |
326 | } | |
327 | else | |
328 | { | |
329 | first = pseudo_slots[regno].first = &pseudo_slots[slots[slot_num].regno]; | |
330 | pseudo_slots[regno].next = first->next; | |
331 | first->next = &pseudo_slots[regno]; | |
332 | } | |
333 | pseudo_slots[regno].mem = NULL_RTX; | |
334 | pseudo_slots[regno].slot_num = slot_num; | |
335 | slots[slot_num].live_ranges | |
336 | = lra_merge_live_ranges (slots[slot_num].live_ranges, | |
337 | lra_copy_live_range_list | |
338 | (lra_reg_info[regno].live_ranges)); | |
339 | } | |
340 | ||
341 | /* Assign stack slot numbers to pseudos in array PSEUDO_REGNOS of | |
342 | length N. Sort pseudos in PSEUDO_REGNOS for subsequent assigning | |
343 | memory stack slots. */ | |
344 | static void | |
345 | assign_stack_slot_num_and_sort_pseudos (int *pseudo_regnos, int n) | |
346 | { | |
347 | int i, j, regno; | |
348 | ||
349 | slots_num = 0; | |
350 | /* Assign stack slot numbers to spilled pseudos, use smaller numbers | |
351 | for most frequently used pseudos. */ | |
352 | for (i = 0; i < n; i++) | |
353 | { | |
354 | regno = pseudo_regnos[i]; | |
355 | if (! flag_ira_share_spill_slots) | |
356 | j = slots_num; | |
357 | else | |
358 | { | |
359 | for (j = 0; j < slots_num; j++) | |
360 | if (slots[j].hard_regno < 0 | |
361 | && ! (lra_intersected_live_ranges_p | |
362 | (slots[j].live_ranges, | |
363 | lra_reg_info[regno].live_ranges))) | |
364 | break; | |
365 | } | |
366 | if (j >= slots_num) | |
367 | { | |
368 | /* New slot. */ | |
369 | slots[j].live_ranges = NULL; | |
83d0488b RS |
370 | slots[j].size = 0; |
371 | slots[j].align = BITS_PER_UNIT; | |
55a2c322 VM |
372 | slots[j].regno = slots[j].hard_regno = -1; |
373 | slots[j].mem = NULL_RTX; | |
374 | slots_num++; | |
375 | } | |
376 | add_pseudo_to_slot (regno, j); | |
377 | } | |
378 | /* Sort regnos according to their slot numbers. */ | |
379 | qsort (pseudo_regnos, n, sizeof (int), pseudo_reg_slot_compare); | |
380 | } | |
381 | ||
382 | /* Recursively process LOC in INSN and change spilled pseudos to the | |
383 | corresponding memory or spilled hard reg. Ignore spilled pseudos | |
49abe076 VM |
384 | created from the scratches. Return true if the pseudo nrefs equal |
385 | to 0 (don't change the pseudo in this case). Otherwise return false. */ | |
386 | static bool | |
cfa434f6 | 387 | remove_pseudos (rtx *loc, rtx_insn *insn) |
55a2c322 VM |
388 | { |
389 | int i; | |
390 | rtx hard_reg; | |
391 | const char *fmt; | |
392 | enum rtx_code code; | |
49abe076 VM |
393 | bool res = false; |
394 | ||
55a2c322 | 395 | if (*loc == NULL_RTX) |
49abe076 | 396 | return res; |
55a2c322 VM |
397 | code = GET_CODE (*loc); |
398 | if (code == REG && (i = REGNO (*loc)) >= FIRST_PSEUDO_REGISTER | |
399 | && lra_get_regno_hard_regno (i) < 0 | |
400 | /* We do not want to assign memory for former scratches because | |
401 | it might result in an address reload for some targets. In | |
402 | any case we transform such pseudos not getting hard registers | |
403 | into scratches back. */ | |
404 | && ! lra_former_scratch_p (i)) | |
405 | { | |
49abe076 VM |
406 | if (lra_reg_info[i].nrefs == 0 |
407 | && pseudo_slots[i].mem == NULL && spill_hard_reg[i] == NULL) | |
408 | return true; | |
8d49e7ef VM |
409 | if ((hard_reg = spill_hard_reg[i]) != NULL_RTX) |
410 | *loc = copy_rtx (hard_reg); | |
411 | else | |
412 | { | |
413 | rtx x = lra_eliminate_regs_1 (insn, pseudo_slots[i].mem, | |
414 | GET_MODE (pseudo_slots[i].mem), | |
a6af1bf9 | 415 | false, false, 0, true); |
8d49e7ef VM |
416 | *loc = x != pseudo_slots[i].mem ? x : copy_rtx (x); |
417 | } | |
49abe076 | 418 | return res; |
55a2c322 VM |
419 | } |
420 | ||
421 | fmt = GET_RTX_FORMAT (code); | |
422 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
423 | { | |
424 | if (fmt[i] == 'e') | |
49abe076 | 425 | res = remove_pseudos (&XEXP (*loc, i), insn) || res; |
55a2c322 VM |
426 | else if (fmt[i] == 'E') |
427 | { | |
428 | int j; | |
429 | ||
430 | for (j = XVECLEN (*loc, i) - 1; j >= 0; j--) | |
49abe076 | 431 | res = remove_pseudos (&XVECEXP (*loc, i, j), insn) || res; |
55a2c322 VM |
432 | } |
433 | } | |
49abe076 | 434 | return res; |
55a2c322 VM |
435 | } |
436 | ||
437 | /* Convert spilled pseudos into their stack slots or spill hard regs, | |
438 | put insns to process on the constraint stack (that is all insns in | |
439 | which pseudos were changed to memory or spill hard regs). */ | |
440 | static void | |
441 | spill_pseudos (void) | |
442 | { | |
443 | basic_block bb; | |
49abe076 | 444 | rtx_insn *insn, *curr; |
55a2c322 | 445 | int i; |
55a2c322 | 446 | |
d648b5ff TS |
447 | auto_bitmap spilled_pseudos (®_obstack); |
448 | auto_bitmap changed_insns (®_obstack); | |
55a2c322 VM |
449 | for (i = FIRST_PSEUDO_REGISTER; i < regs_num; i++) |
450 | { | |
451 | if (lra_reg_info[i].nrefs != 0 && lra_get_regno_hard_regno (i) < 0 | |
452 | && ! lra_former_scratch_p (i)) | |
453 | { | |
d648b5ff TS |
454 | bitmap_set_bit (spilled_pseudos, i); |
455 | bitmap_ior_into (changed_insns, &lra_reg_info[i].insn_bitmap); | |
55a2c322 VM |
456 | } |
457 | } | |
11cd3bed | 458 | FOR_EACH_BB_FN (bb, cfun) |
55a2c322 | 459 | { |
49abe076 VM |
460 | FOR_BB_INSNS_SAFE (bb, insn, curr) |
461 | { | |
462 | bool removed_pseudo_p = false; | |
463 | ||
d648b5ff | 464 | if (bitmap_bit_p (changed_insns, INSN_UID (insn))) |
49abe076 VM |
465 | { |
466 | rtx *link_loc, link; | |
467 | ||
468 | removed_pseudo_p = remove_pseudos (&PATTERN (insn), insn); | |
469 | if (CALL_P (insn) | |
470 | && remove_pseudos (&CALL_INSN_FUNCTION_USAGE (insn), insn)) | |
471 | removed_pseudo_p = true; | |
472 | for (link_loc = ®_NOTES (insn); | |
473 | (link = *link_loc) != NULL_RTX; | |
474 | link_loc = &XEXP (link, 1)) | |
475 | { | |
476 | switch (REG_NOTE_KIND (link)) | |
477 | { | |
478 | case REG_FRAME_RELATED_EXPR: | |
479 | case REG_CFA_DEF_CFA: | |
480 | case REG_CFA_ADJUST_CFA: | |
481 | case REG_CFA_OFFSET: | |
482 | case REG_CFA_REGISTER: | |
483 | case REG_CFA_EXPRESSION: | |
484 | case REG_CFA_RESTORE: | |
485 | case REG_CFA_SET_VDRAP: | |
486 | if (remove_pseudos (&XEXP (link, 0), insn)) | |
487 | removed_pseudo_p = true; | |
488 | break; | |
489 | default: | |
490 | break; | |
491 | } | |
492 | } | |
493 | if (lra_dump_file != NULL) | |
494 | fprintf (lra_dump_file, | |
495 | "Changing spilled pseudos to memory in insn #%u\n", | |
496 | INSN_UID (insn)); | |
497 | lra_push_insn (insn); | |
498 | if (lra_reg_spill_p || targetm.different_addr_displacement_p ()) | |
499 | lra_set_used_insn_alternative (insn, -1); | |
500 | } | |
501 | else if (CALL_P (insn) | |
502 | /* Presence of any pseudo in CALL_INSN_FUNCTION_USAGE | |
503 | does not affect value of insn_bitmap of the | |
504 | corresponding lra_reg_info. That is because we | |
505 | don't need to reload pseudos in | |
506 | CALL_INSN_FUNCTION_USAGEs. So if we process only | |
507 | insns in the insn_bitmap of given pseudo here, we | |
508 | can miss the pseudo in some | |
509 | CALL_INSN_FUNCTION_USAGEs. */ | |
510 | && remove_pseudos (&CALL_INSN_FUNCTION_USAGE (insn), insn)) | |
511 | removed_pseudo_p = true; | |
512 | if (removed_pseudo_p) | |
513 | { | |
514 | lra_assert (DEBUG_INSN_P (insn)); | |
5901e56a JJ |
515 | lra_invalidate_insn_data (insn); |
516 | INSN_VAR_LOCATION_LOC (insn) = gen_rtx_UNKNOWN_VAR_LOC (); | |
49abe076 VM |
517 | if (lra_dump_file != NULL) |
518 | fprintf (lra_dump_file, | |
5901e56a JJ |
519 | "Debug insn #%u is reset because it referenced " |
520 | "removed pseudo\n", INSN_UID (insn)); | |
49abe076 | 521 | } |
d648b5ff TS |
522 | bitmap_and_compl_into (df_get_live_in (bb), spilled_pseudos); |
523 | bitmap_and_compl_into (df_get_live_out (bb), spilled_pseudos); | |
49abe076 | 524 | } |
55a2c322 | 525 | } |
55a2c322 VM |
526 | } |
527 | ||
528 | /* Return true if we need to change some pseudos into memory. */ | |
529 | bool | |
530 | lra_need_for_spills_p (void) | |
531 | { | |
532 | int i; max_regno = max_reg_num (); | |
533 | ||
534 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
535 | if (lra_reg_info[i].nrefs != 0 && lra_get_regno_hard_regno (i) < 0 | |
536 | && ! lra_former_scratch_p (i)) | |
537 | return true; | |
538 | return false; | |
539 | } | |
540 | ||
541 | /* Change spilled pseudos into memory or spill hard regs. Put changed | |
542 | insns on the constraint stack (these insns will be considered on | |
543 | the next constraint pass). The changed insns are all insns in | |
544 | which pseudos were changed. */ | |
545 | void | |
546 | lra_spill (void) | |
547 | { | |
548 | int i, n, curr_regno; | |
549 | int *pseudo_regnos; | |
550 | ||
551 | regs_num = max_reg_num (); | |
552 | spill_hard_reg = XNEWVEC (rtx, regs_num); | |
553 | pseudo_regnos = XNEWVEC (int, regs_num); | |
554 | for (n = 0, i = FIRST_PSEUDO_REGISTER; i < regs_num; i++) | |
555 | if (lra_reg_info[i].nrefs != 0 && lra_get_regno_hard_regno (i) < 0 | |
556 | /* We do not want to assign memory for former scratches. */ | |
557 | && ! lra_former_scratch_p (i)) | |
49abe076 | 558 | pseudo_regnos[n++] = i; |
55a2c322 VM |
559 | lra_assert (n > 0); |
560 | pseudo_slots = XNEWVEC (struct pseudo_slot, regs_num); | |
49abe076 VM |
561 | for (i = FIRST_PSEUDO_REGISTER; i < regs_num; i++) |
562 | { | |
563 | spill_hard_reg[i] = NULL_RTX; | |
564 | pseudo_slots[i].mem = NULL_RTX; | |
565 | } | |
55a2c322 VM |
566 | slots = XNEWVEC (struct slot, regs_num); |
567 | /* Sort regnos according their usage frequencies. */ | |
568 | qsort (pseudo_regnos, n, sizeof (int), regno_freq_compare); | |
569 | n = assign_spill_hard_regs (pseudo_regnos, n); | |
570 | assign_stack_slot_num_and_sort_pseudos (pseudo_regnos, n); | |
571 | for (i = 0; i < n; i++) | |
572 | if (pseudo_slots[pseudo_regnos[i]].mem == NULL_RTX) | |
573 | assign_mem_slot (pseudo_regnos[i]); | |
2c62cbaa VM |
574 | if (n > 0 && crtl->stack_alignment_needed) |
575 | /* If we have a stack frame, we must align it now. The stack size | |
576 | may be a part of the offset computation for register | |
577 | elimination. */ | |
578 | assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed); | |
55a2c322 VM |
579 | if (lra_dump_file != NULL) |
580 | { | |
581 | for (i = 0; i < slots_num; i++) | |
582 | { | |
cf098191 RS |
583 | fprintf (lra_dump_file, " Slot %d regnos (width = ", i); |
584 | print_dec (GET_MODE_SIZE (GET_MODE (slots[i].mem)), | |
585 | lra_dump_file, SIGNED); | |
586 | fprintf (lra_dump_file, "):"); | |
55a2c322 VM |
587 | for (curr_regno = slots[i].regno;; |
588 | curr_regno = pseudo_slots[curr_regno].next - pseudo_slots) | |
589 | { | |
590 | fprintf (lra_dump_file, " %d", curr_regno); | |
591 | if (pseudo_slots[curr_regno].next == NULL) | |
592 | break; | |
593 | } | |
594 | fprintf (lra_dump_file, "\n"); | |
595 | } | |
596 | } | |
597 | spill_pseudos (); | |
598 | free (slots); | |
599 | free (pseudo_slots); | |
600 | free (pseudo_regnos); | |
d0163673 | 601 | free (spill_hard_reg); |
55a2c322 VM |
602 | } |
603 | ||
6e5769ce VM |
604 | /* Apply alter_subreg for subregs of regs in *LOC. Use FINAL_P for |
605 | alter_subreg calls. Return true if any subreg of reg is | |
606 | processed. */ | |
607 | static bool | |
608 | alter_subregs (rtx *loc, bool final_p) | |
609 | { | |
610 | int i; | |
611 | rtx x = *loc; | |
612 | bool res; | |
613 | const char *fmt; | |
614 | enum rtx_code code; | |
615 | ||
616 | if (x == NULL_RTX) | |
617 | return false; | |
618 | code = GET_CODE (x); | |
619 | if (code == SUBREG && REG_P (SUBREG_REG (x))) | |
620 | { | |
621 | lra_assert (REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER); | |
622 | alter_subreg (loc, final_p); | |
623 | return true; | |
624 | } | |
625 | fmt = GET_RTX_FORMAT (code); | |
626 | res = false; | |
627 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
628 | { | |
629 | if (fmt[i] == 'e') | |
630 | { | |
631 | if (alter_subregs (&XEXP (x, i), final_p)) | |
632 | res = true; | |
633 | } | |
634 | else if (fmt[i] == 'E') | |
635 | { | |
636 | int j; | |
f4eafc30 | 637 | |
6e5769ce VM |
638 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
639 | if (alter_subregs (&XVECEXP (x, i, j), final_p)) | |
640 | res = true; | |
641 | } | |
642 | } | |
643 | return res; | |
644 | } | |
645 | ||
efaf512c VM |
646 | /* Return true if REGNO is used for return in the current |
647 | function. */ | |
648 | static bool | |
649 | return_regno_p (unsigned int regno) | |
650 | { | |
651 | rtx outgoing = crtl->return_rtx; | |
652 | ||
653 | if (! outgoing) | |
654 | return false; | |
655 | ||
656 | if (REG_P (outgoing)) | |
657 | return REGNO (outgoing) == regno; | |
658 | else if (GET_CODE (outgoing) == PARALLEL) | |
659 | { | |
660 | int i; | |
661 | ||
662 | for (i = 0; i < XVECLEN (outgoing, 0); i++) | |
663 | { | |
664 | rtx x = XEXP (XVECEXP (outgoing, 0, i), 0); | |
665 | ||
666 | if (REG_P (x) && REGNO (x) == regno) | |
667 | return true; | |
668 | } | |
669 | } | |
670 | return false; | |
671 | } | |
672 | ||
73c77563 VM |
673 | /* Return true if REGNO is in one of subsequent USE after INSN in the |
674 | same BB. */ | |
00803109 VM |
675 | static bool |
676 | regno_in_use_p (rtx_insn *insn, unsigned int regno) | |
677 | { | |
73c77563 VM |
678 | static lra_insn_recog_data_t id; |
679 | static struct lra_static_insn_data *static_id; | |
680 | struct lra_insn_reg *reg; | |
681 | int i, arg_regno; | |
682 | basic_block bb = BLOCK_FOR_INSN (insn); | |
683 | ||
5435398d | 684 | while ((insn = next_nondebug_insn (insn)) != NULL_RTX) |
00803109 | 685 | { |
5435398d JJ |
686 | if (BARRIER_P (insn) || bb != BLOCK_FOR_INSN (insn)) |
687 | return false; | |
73c77563 VM |
688 | if (! INSN_P (insn)) |
689 | continue; | |
690 | if (GET_CODE (PATTERN (insn)) == USE | |
691 | && REG_P (XEXP (PATTERN (insn), 0)) | |
00803109 | 692 | && regno == REGNO (XEXP (PATTERN (insn), 0))) |
73c77563 VM |
693 | return true; |
694 | /* Check that the regno is not modified. */ | |
695 | id = lra_get_insn_recog_data (insn); | |
696 | for (reg = id->regs; reg != NULL; reg = reg->next) | |
697 | if (reg->type != OP_IN && reg->regno == (int) regno) | |
698 | return false; | |
699 | static_id = id->insn_static_data; | |
700 | for (reg = static_id->hard_regs; reg != NULL; reg = reg->next) | |
701 | if (reg->type != OP_IN && reg->regno == (int) regno) | |
702 | return false; | |
703 | if (id->arg_hard_regs != NULL) | |
704 | for (i = 0; (arg_regno = id->arg_hard_regs[i]) >= 0; i++) | |
705 | if ((int) regno == (arg_regno >= FIRST_PSEUDO_REGISTER | |
706 | ? arg_regno : arg_regno - FIRST_PSEUDO_REGISTER)) | |
707 | return false; | |
00803109 VM |
708 | } |
709 | return false; | |
710 | } | |
711 | ||
55a2c322 | 712 | /* Final change of pseudos got hard registers into the corresponding |
c5cd5a7e | 713 | hard registers and removing temporary clobbers. */ |
55a2c322 | 714 | void |
c5cd5a7e | 715 | lra_final_code_change (void) |
55a2c322 VM |
716 | { |
717 | int i, hard_regno; | |
718 | basic_block bb; | |
00803109 | 719 | rtx_insn *insn, *curr; |
55a2c322 VM |
720 | int max_regno = max_reg_num (); |
721 | ||
722 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
723 | if (lra_reg_info[i].nrefs != 0 | |
724 | && (hard_regno = lra_get_regno_hard_regno (i)) >= 0) | |
725 | SET_REGNO (regno_reg_rtx[i], hard_regno); | |
11cd3bed | 726 | FOR_EACH_BB_FN (bb, cfun) |
c5cd5a7e | 727 | FOR_BB_INSNS_SAFE (bb, insn, curr) |
55a2c322 VM |
728 | if (INSN_P (insn)) |
729 | { | |
c5cd5a7e VM |
730 | rtx pat = PATTERN (insn); |
731 | ||
732 | if (GET_CODE (pat) == CLOBBER && LRA_TEMP_CLOBBER_P (pat)) | |
733 | { | |
734 | /* Remove clobbers temporarily created in LRA. We don't | |
735 | need them anymore and don't want to waste compiler | |
736 | time processing them in a few subsequent passes. */ | |
737 | lra_invalidate_insn_data (insn); | |
1f397f45 | 738 | delete_insn (insn); |
c5cd5a7e VM |
739 | continue; |
740 | } | |
741 | ||
efaf512c VM |
742 | /* IRA can generate move insns involving pseudos. It is |
743 | better remove them earlier to speed up compiler a bit. | |
744 | It is also better to do it here as they might not pass | |
745 | final RTL check in LRA, (e.g. insn moving a control | |
746 | register into itself). So remove an useless move insn | |
747 | unless next insn is USE marking the return reg (we should | |
748 | save this as some subsequent optimizations assume that | |
749 | such original insns are saved). */ | |
750 | if (NONJUMP_INSN_P (insn) && GET_CODE (pat) == SET | |
751 | && REG_P (SET_SRC (pat)) && REG_P (SET_DEST (pat)) | |
752 | && REGNO (SET_SRC (pat)) == REGNO (SET_DEST (pat)) | |
8a8330b7 | 753 | && (! return_regno_p (REGNO (SET_SRC (pat))) |
00803109 | 754 | || ! regno_in_use_p (insn, REGNO (SET_SRC (pat))))) |
efaf512c VM |
755 | { |
756 | lra_invalidate_insn_data (insn); | |
757 | delete_insn (insn); | |
758 | continue; | |
759 | } | |
760 | ||
6e5769ce | 761 | lra_insn_recog_data_t id = lra_get_insn_recog_data (insn); |
684ffdc9 VM |
762 | struct lra_insn_reg *reg; |
763 | ||
764 | for (reg = id->regs; reg != NULL; reg = reg->next) | |
765 | if (reg->regno >= FIRST_PSEUDO_REGISTER | |
766 | && lra_reg_info [reg->regno].nrefs == 0) | |
767 | break; | |
768 | ||
769 | if (reg != NULL) | |
770 | { | |
771 | /* Pseudos still can be in debug insns in some very rare | |
772 | and complicated cases, e.g. the pseudo was removed by | |
773 | inheritance and the debug insn is not EBBs where the | |
774 | inheritance happened. It is difficult and time | |
775 | consuming to find what hard register corresponds the | |
776 | pseudo -- so just remove the debug insn. Another | |
777 | solution could be assigning hard reg/memory but it | |
778 | would be a misleading info. It is better not to have | |
779 | info than have it wrong. */ | |
780 | lra_assert (DEBUG_INSN_P (insn)); | |
781 | lra_invalidate_insn_data (insn); | |
782 | delete_insn (insn); | |
783 | continue; | |
784 | } | |
785 | ||
2c62cbaa | 786 | struct lra_static_insn_data *static_id = id->insn_static_data; |
55a2c322 | 787 | bool insn_change_p = false; |
6bbacdb5 L |
788 | |
789 | for (i = id->insn_static_data->n_operands - 1; i >= 0; i--) | |
790 | if ((DEBUG_INSN_P (insn) || ! static_id->operand[i].is_operator) | |
791 | && alter_subregs (id->operand_loc[i], ! DEBUG_INSN_P (insn))) | |
792 | { | |
793 | lra_update_dup (id, i); | |
794 | insn_change_p = true; | |
795 | } | |
55a2c322 VM |
796 | if (insn_change_p) |
797 | lra_update_operator_dups (id); | |
798 | } | |
799 | } |