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55a2c322 | 1 | /* LRA (local register allocator) driver and LRA utilities. |
818ab71a | 2 | Copyright (C) 2010-2016 Free Software Foundation, Inc. |
55a2c322 VM |
3 | Contributed by Vladimir Makarov <vmakarov@redhat.com>. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it under | |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 3, or (at your option) any later | |
10 | version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | ||
22 | /* The Local Register Allocator (LRA) is a replacement of former | |
23 | reload pass. It is focused to simplify code solving the reload | |
24 | pass tasks, to make the code maintenance easier, and to implement new | |
25 | perspective optimizations. | |
26 | ||
27 | The major LRA design solutions are: | |
28 | o division small manageable, separated sub-tasks | |
29 | o reflection of all transformations and decisions in RTL as more | |
30 | as possible | |
31 | o insn constraints as a primary source of the info (minimizing | |
32 | number of target-depended macros/hooks) | |
33 | ||
34 | In brief LRA works by iterative insn process with the final goal is | |
35 | to satisfy all insn and address constraints: | |
36 | o New reload insns (in brief reloads) and reload pseudos might be | |
37 | generated; | |
38 | o Some pseudos might be spilled to assign hard registers to | |
39 | new reload pseudos; | |
d9cf932c | 40 | o Recalculating spilled pseudo values (rematerialization); |
55a2c322 VM |
41 | o Changing spilled pseudos to stack memory or their equivalences; |
42 | o Allocation stack memory changes the address displacement and | |
43 | new iteration is needed. | |
44 | ||
45 | Here is block diagram of LRA passes: | |
46 | ||
2b778c9d VM |
47 | ------------------------ |
48 | --------------- | Undo inheritance for | --------------- | |
49 | | Memory-memory | | spilled pseudos, | | New (and old) | | |
50 | | move coalesce |<---| splits for pseudos got |<-- | pseudos | | |
51 | --------------- | the same hard regs, | | assignment | | |
52 | Start | | and optional reloads | --------------- | |
53 | | | ------------------------ ^ | |
f38e1b0a VM |
54 | V | ---------------- | |
55 | ----------- V | Update virtual | | | |
56 | | Remove |----> ------------>| register | | | |
57 | | scratches | ^ | displacements | | | |
58 | ----------- | ---------------- | | |
59 | | | | | |
60 | | V New | | |
d9cf932c VM |
61 | | ------------ pseudos ------------------- |
62 | | |Constraints:| or insns | Inheritance/split | | |
63 | | | RTL |--------->| transformations | | |
64 | | | transfor- | | in EBB scope | | |
65 | | substi- | mations | ------------------- | |
66 | | tutions ------------ | |
67 | | | No change | |
68 | ---------------- V | |
69 | | Spilled pseudo | ------------------- | |
70 | | to memory |<----| Rematerialization | | |
71 | | substitution | ------------------- | |
72 | ---------------- | |
73 | | No susbtitions | |
74 | V | |
75 | ------------------------- | |
76 | | Hard regs substitution, | | |
77 | | devirtalization, and |------> Finish | |
78 | | restoring scratches got | | |
79 | | memory | | |
80 | ------------------------- | |
55a2c322 VM |
81 | |
82 | To speed up the process: | |
83 | o We process only insns affected by changes on previous | |
84 | iterations; | |
85 | o We don't use DFA-infrastructure because it results in much slower | |
86 | compiler speed than a special IR described below does; | |
87 | o We use a special insn representation for quick access to insn | |
88 | info which is always *synchronized* with the current RTL; | |
89 | o Insn IR is minimized by memory. It is divided on three parts: | |
90 | o one specific for each insn in RTL (only operand locations); | |
91 | o one common for all insns in RTL with the same insn code | |
92 | (different operand attributes from machine descriptions); | |
93 | o one oriented for maintenance of live info (list of pseudos). | |
94 | o Pseudo data: | |
95 | o all insns where the pseudo is referenced; | |
96 | o live info (conflicting hard regs, live ranges, # of | |
97 | references etc); | |
98 | o data used for assigning (preferred hard regs, costs etc). | |
99 | ||
100 | This file contains LRA driver, LRA utility functions and data, and | |
101 | code for dealing with scratches. */ | |
102 | ||
103 | #include "config.h" | |
104 | #include "system.h" | |
105 | #include "coretypes.h" | |
c7131fb2 | 106 | #include "backend.h" |
957060b5 | 107 | #include "target.h" |
55a2c322 | 108 | #include "rtl.h" |
957060b5 AM |
109 | #include "tree.h" |
110 | #include "predict.h" | |
c7131fb2 | 111 | #include "df.h" |
55a2c322 | 112 | #include "tm_p.h" |
957060b5 | 113 | #include "optabs.h" |
55a2c322 | 114 | #include "regs.h" |
957060b5 | 115 | #include "ira.h" |
55a2c322 | 116 | #include "recog.h" |
55a2c322 | 117 | #include "expr.h" |
60393bbc AM |
118 | #include "cfgrtl.h" |
119 | #include "cfgbuild.h" | |
c7131fb2 | 120 | #include "lra.h" |
55a2c322 | 121 | #include "lra-int.h" |
013a8899 | 122 | #include "print-rtl.h" |
55a2c322 | 123 | |
8160cd3e VM |
124 | /* Dump bitmap SET with TITLE and BB INDEX. */ |
125 | void | |
126 | lra_dump_bitmap_with_title (const char *title, bitmap set, int index) | |
127 | { | |
128 | unsigned int i; | |
129 | int count; | |
130 | bitmap_iterator bi; | |
131 | static const int max_nums_on_line = 10; | |
132 | ||
133 | if (bitmap_empty_p (set)) | |
134 | return; | |
135 | fprintf (lra_dump_file, " %s %d:", title, index); | |
136 | fprintf (lra_dump_file, "\n"); | |
137 | count = max_nums_on_line + 1; | |
138 | EXECUTE_IF_SET_IN_BITMAP (set, 0, i, bi) | |
139 | { | |
140 | if (count > max_nums_on_line) | |
141 | { | |
142 | fprintf (lra_dump_file, "\n "); | |
143 | count = 0; | |
144 | } | |
145 | fprintf (lra_dump_file, " %4u", i); | |
146 | count++; | |
147 | } | |
148 | fprintf (lra_dump_file, "\n"); | |
149 | } | |
150 | ||
55a2c322 VM |
151 | /* Hard registers currently not available for allocation. It can |
152 | changed after some hard registers become not eliminable. */ | |
153 | HARD_REG_SET lra_no_alloc_regs; | |
154 | ||
155 | static int get_new_reg_value (void); | |
156 | static void expand_reg_info (void); | |
157 | static void invalidate_insn_recog_data (int); | |
cfa434f6 DM |
158 | static int get_insn_freq (rtx_insn *); |
159 | static void invalidate_insn_data_regno_info (lra_insn_recog_data_t, | |
160 | rtx_insn *, int); | |
55a2c322 VM |
161 | |
162 | /* Expand all regno related info needed for LRA. */ | |
163 | static void | |
a2d0d374 | 164 | expand_reg_data (int old) |
55a2c322 VM |
165 | { |
166 | resize_reg_info (); | |
167 | expand_reg_info (); | |
168 | ira_expand_reg_equiv (); | |
a2d0d374 VM |
169 | for (int i = (int) max_reg_num () - 1; i >= old; i--) |
170 | lra_change_class (i, ALL_REGS, " Set", true); | |
55a2c322 VM |
171 | } |
172 | ||
173 | /* Create and return a new reg of ORIGINAL mode. If ORIGINAL is NULL | |
174 | or of VOIDmode, use MD_MODE for the new reg. Initialize its | |
175 | register class to RCLASS. Print message about assigning class | |
176 | RCLASS containing new register name TITLE unless it is NULL. Use | |
177 | attributes of ORIGINAL if it is a register. The created register | |
178 | will have unique held value. */ | |
179 | rtx | |
ef4bddc2 | 180 | lra_create_new_reg_with_unique_value (machine_mode md_mode, rtx original, |
55a2c322 VM |
181 | enum reg_class rclass, const char *title) |
182 | { | |
ef4bddc2 | 183 | machine_mode mode; |
55a2c322 VM |
184 | rtx new_reg; |
185 | ||
186 | if (original == NULL_RTX || (mode = GET_MODE (original)) == VOIDmode) | |
187 | mode = md_mode; | |
188 | lra_assert (mode != VOIDmode); | |
189 | new_reg = gen_reg_rtx (mode); | |
190 | if (original == NULL_RTX || ! REG_P (original)) | |
191 | { | |
192 | if (lra_dump_file != NULL) | |
193 | fprintf (lra_dump_file, " Creating newreg=%i", REGNO (new_reg)); | |
194 | } | |
195 | else | |
196 | { | |
197 | if (ORIGINAL_REGNO (original) >= FIRST_PSEUDO_REGISTER) | |
198 | ORIGINAL_REGNO (new_reg) = ORIGINAL_REGNO (original); | |
199 | REG_USERVAR_P (new_reg) = REG_USERVAR_P (original); | |
200 | REG_POINTER (new_reg) = REG_POINTER (original); | |
201 | REG_ATTRS (new_reg) = REG_ATTRS (original); | |
202 | if (lra_dump_file != NULL) | |
203 | fprintf (lra_dump_file, " Creating newreg=%i from oldreg=%i", | |
204 | REGNO (new_reg), REGNO (original)); | |
205 | } | |
206 | if (lra_dump_file != NULL) | |
207 | { | |
208 | if (title != NULL) | |
209 | fprintf (lra_dump_file, ", assigning class %s to%s%s r%d", | |
210 | reg_class_names[rclass], *title == '\0' ? "" : " ", | |
211 | title, REGNO (new_reg)); | |
212 | fprintf (lra_dump_file, "\n"); | |
213 | } | |
a2d0d374 | 214 | expand_reg_data (max_reg_num ()); |
55a2c322 VM |
215 | setup_reg_classes (REGNO (new_reg), rclass, NO_REGS, rclass); |
216 | return new_reg; | |
217 | } | |
218 | ||
219 | /* Analogous to the previous function but also inherits value of | |
220 | ORIGINAL. */ | |
221 | rtx | |
ef4bddc2 | 222 | lra_create_new_reg (machine_mode md_mode, rtx original, |
55a2c322 VM |
223 | enum reg_class rclass, const char *title) |
224 | { | |
225 | rtx new_reg; | |
226 | ||
227 | new_reg | |
228 | = lra_create_new_reg_with_unique_value (md_mode, original, rclass, title); | |
229 | if (original != NULL_RTX && REG_P (original)) | |
d70a81dd | 230 | lra_assign_reg_val (REGNO (original), REGNO (new_reg)); |
55a2c322 VM |
231 | return new_reg; |
232 | } | |
233 | ||
234 | /* Set up for REGNO unique hold value. */ | |
235 | void | |
236 | lra_set_regno_unique_value (int regno) | |
237 | { | |
238 | lra_reg_info[regno].val = get_new_reg_value (); | |
239 | } | |
240 | ||
8d49e7ef VM |
241 | /* Invalidate INSN related info used by LRA. The info should never be |
242 | used after that. */ | |
55a2c322 | 243 | void |
cfa434f6 | 244 | lra_invalidate_insn_data (rtx_insn *insn) |
55a2c322 VM |
245 | { |
246 | lra_invalidate_insn_regno_info (insn); | |
247 | invalidate_insn_recog_data (INSN_UID (insn)); | |
248 | } | |
249 | ||
250 | /* Mark INSN deleted and invalidate the insn related info used by | |
251 | LRA. */ | |
252 | void | |
cfa434f6 | 253 | lra_set_insn_deleted (rtx_insn *insn) |
55a2c322 VM |
254 | { |
255 | lra_invalidate_insn_data (insn); | |
256 | SET_INSN_DELETED (insn); | |
257 | } | |
258 | ||
259 | /* Delete an unneeded INSN and any previous insns who sole purpose is | |
260 | loading data that is dead in INSN. */ | |
261 | void | |
cfa434f6 | 262 | lra_delete_dead_insn (rtx_insn *insn) |
55a2c322 | 263 | { |
cfa434f6 | 264 | rtx_insn *prev = prev_real_insn (insn); |
55a2c322 VM |
265 | rtx prev_dest; |
266 | ||
267 | /* If the previous insn sets a register that dies in our insn, | |
268 | delete it too. */ | |
269 | if (prev && GET_CODE (PATTERN (prev)) == SET | |
270 | && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest)) | |
271 | && reg_mentioned_p (prev_dest, PATTERN (insn)) | |
272 | && find_regno_note (insn, REG_DEAD, REGNO (prev_dest)) | |
273 | && ! side_effects_p (SET_SRC (PATTERN (prev)))) | |
274 | lra_delete_dead_insn (prev); | |
275 | ||
276 | lra_set_insn_deleted (insn); | |
277 | } | |
278 | ||
11f5b71a VM |
279 | /* Emit insn x = y + z. Return NULL if we failed to do it. |
280 | Otherwise, return the insn. We don't use gen_add3_insn as it might | |
281 | clobber CC. */ | |
e67d1102 | 282 | static rtx_insn * |
11f5b71a VM |
283 | emit_add3_insn (rtx x, rtx y, rtx z) |
284 | { | |
fee3e72c | 285 | rtx_insn *last; |
11f5b71a VM |
286 | |
287 | last = get_last_insn (); | |
72a4ddf2 AK |
288 | |
289 | if (have_addptr3_insn (x, y, z)) | |
290 | { | |
e67d1102 | 291 | rtx_insn *insn = gen_addptr3_insn (x, y, z); |
72a4ddf2 AK |
292 | |
293 | /* If the target provides an "addptr" pattern it hopefully does | |
294 | for a reason. So falling back to the normal add would be | |
295 | a bug. */ | |
296 | lra_assert (insn != NULL_RTX); | |
297 | emit_insn (insn); | |
298 | return insn; | |
299 | } | |
300 | ||
f7df4a84 RS |
301 | rtx_insn *insn = emit_insn (gen_rtx_SET (x, gen_rtx_PLUS (GET_MODE (y), |
302 | y, z))); | |
11f5b71a VM |
303 | if (recog_memoized (insn) < 0) |
304 | { | |
305 | delete_insns_since (last); | |
647d790d | 306 | insn = NULL; |
11f5b71a VM |
307 | } |
308 | return insn; | |
309 | } | |
310 | ||
311 | /* Emit insn x = x + y. Return the insn. We use gen_add2_insn as the | |
312 | last resort. */ | |
e67d1102 | 313 | static rtx_insn * |
11f5b71a VM |
314 | emit_add2_insn (rtx x, rtx y) |
315 | { | |
e67d1102 | 316 | rtx_insn *insn = emit_add3_insn (x, x, y); |
11f5b71a VM |
317 | if (insn == NULL_RTX) |
318 | { | |
319 | insn = gen_add2_insn (x, y); | |
320 | if (insn != NULL_RTX) | |
321 | emit_insn (insn); | |
322 | } | |
323 | return insn; | |
324 | } | |
325 | ||
55a2c322 VM |
326 | /* Target checks operands through operand predicates to recognize an |
327 | insn. We should have a special precaution to generate add insns | |
328 | which are frequent results of elimination. | |
329 | ||
330 | Emit insns for x = y + z. X can be used to store intermediate | |
331 | values and should be not in Y and Z when we use X to store an | |
332 | intermediate value. Y + Z should form [base] [+ index[ * scale]] [ | |
333 | + disp] where base and index are registers, disp and scale are | |
334 | constants. Y should contain base if it is present, Z should | |
335 | contain disp if any. index[*scale] can be part of Y or Z. */ | |
336 | void | |
337 | lra_emit_add (rtx x, rtx y, rtx z) | |
338 | { | |
339 | int old; | |
fee3e72c | 340 | rtx_insn *last; |
55a2c322 VM |
341 | rtx a1, a2, base, index, disp, scale, index_scale; |
342 | bool ok_p; | |
343 | ||
e67d1102 | 344 | rtx_insn *add3_insn = emit_add3_insn (x, y, z); |
55a2c322 | 345 | old = max_reg_num (); |
647d790d | 346 | if (add3_insn != NULL) |
11f5b71a | 347 | ; |
55a2c322 VM |
348 | else |
349 | { | |
350 | disp = a2 = NULL_RTX; | |
351 | if (GET_CODE (y) == PLUS) | |
352 | { | |
353 | a1 = XEXP (y, 0); | |
354 | a2 = XEXP (y, 1); | |
355 | disp = z; | |
356 | } | |
357 | else | |
358 | { | |
359 | a1 = y; | |
360 | if (CONSTANT_P (z)) | |
361 | disp = z; | |
362 | else | |
363 | a2 = z; | |
364 | } | |
365 | index_scale = scale = NULL_RTX; | |
366 | if (GET_CODE (a1) == MULT) | |
367 | { | |
368 | index_scale = a1; | |
369 | index = XEXP (a1, 0); | |
370 | scale = XEXP (a1, 1); | |
371 | base = a2; | |
372 | } | |
373 | else if (a2 != NULL_RTX && GET_CODE (a2) == MULT) | |
374 | { | |
375 | index_scale = a2; | |
376 | index = XEXP (a2, 0); | |
377 | scale = XEXP (a2, 1); | |
378 | base = a1; | |
379 | } | |
380 | else | |
381 | { | |
382 | base = a1; | |
383 | index = a2; | |
384 | } | |
0b87be09 | 385 | if ((base != NULL_RTX && ! (REG_P (base) || GET_CODE (base) == SUBREG)) |
93aaa05d VM |
386 | || (index != NULL_RTX |
387 | && ! (REG_P (index) || GET_CODE (index) == SUBREG)) | |
55a2c322 VM |
388 | || (disp != NULL_RTX && ! CONSTANT_P (disp)) |
389 | || (scale != NULL_RTX && ! CONSTANT_P (scale))) | |
390 | { | |
11f5b71a VM |
391 | /* Probably we have no 3 op add. Last chance is to use 2-op |
392 | add insn. To succeed, don't move Z to X as an address | |
393 | segment always comes in Y. Otherwise, we might fail when | |
394 | adding the address segment to register. */ | |
55a2c322 | 395 | lra_assert (x != y && x != z); |
ed52a84e | 396 | emit_move_insn (x, y); |
e67d1102 | 397 | rtx_insn *insn = emit_add2_insn (x, z); |
11f5b71a | 398 | lra_assert (insn != NULL_RTX); |
55a2c322 VM |
399 | } |
400 | else | |
401 | { | |
402 | if (index_scale == NULL_RTX) | |
403 | index_scale = index; | |
404 | if (disp == NULL_RTX) | |
405 | { | |
406 | /* Generate x = index_scale; x = x + base. */ | |
407 | lra_assert (index_scale != NULL_RTX && base != NULL_RTX); | |
408 | emit_move_insn (x, index_scale); | |
e67d1102 | 409 | rtx_insn *insn = emit_add2_insn (x, base); |
11f5b71a | 410 | lra_assert (insn != NULL_RTX); |
55a2c322 VM |
411 | } |
412 | else if (scale == NULL_RTX) | |
413 | { | |
414 | /* Try x = base + disp. */ | |
415 | lra_assert (base != NULL_RTX); | |
416 | last = get_last_insn (); | |
647d790d DM |
417 | rtx_insn *move_insn = |
418 | emit_move_insn (x, gen_rtx_PLUS (GET_MODE (base), base, disp)); | |
419 | if (recog_memoized (move_insn) < 0) | |
55a2c322 VM |
420 | { |
421 | delete_insns_since (last); | |
422 | /* Generate x = disp; x = x + base. */ | |
423 | emit_move_insn (x, disp); | |
e67d1102 | 424 | rtx_insn *add2_insn = emit_add2_insn (x, base); |
647d790d | 425 | lra_assert (add2_insn != NULL_RTX); |
55a2c322 VM |
426 | } |
427 | /* Generate x = x + index. */ | |
428 | if (index != NULL_RTX) | |
429 | { | |
e67d1102 | 430 | rtx_insn *insn = emit_add2_insn (x, index); |
11f5b71a | 431 | lra_assert (insn != NULL_RTX); |
55a2c322 VM |
432 | } |
433 | } | |
434 | else | |
435 | { | |
436 | /* Try x = index_scale; x = x + disp; x = x + base. */ | |
437 | last = get_last_insn (); | |
647d790d | 438 | rtx_insn *move_insn = emit_move_insn (x, index_scale); |
55a2c322 | 439 | ok_p = false; |
647d790d | 440 | if (recog_memoized (move_insn) >= 0) |
55a2c322 | 441 | { |
e67d1102 | 442 | rtx_insn *insn = emit_add2_insn (x, disp); |
55a2c322 VM |
443 | if (insn != NULL_RTX) |
444 | { | |
0b87be09 | 445 | if (base == NULL_RTX) |
11f5b71a | 446 | ok_p = true; |
0b87be09 VM |
447 | else |
448 | { | |
449 | insn = emit_add2_insn (x, base); | |
450 | if (insn != NULL_RTX) | |
451 | ok_p = true; | |
452 | } | |
55a2c322 VM |
453 | } |
454 | } | |
455 | if (! ok_p) | |
456 | { | |
0b87be09 VM |
457 | rtx_insn *insn; |
458 | ||
55a2c322 VM |
459 | delete_insns_since (last); |
460 | /* Generate x = disp; x = x + base; x = x + index_scale. */ | |
461 | emit_move_insn (x, disp); | |
0b87be09 VM |
462 | if (base != NULL_RTX) |
463 | { | |
464 | insn = emit_add2_insn (x, base); | |
465 | lra_assert (insn != NULL_RTX); | |
466 | } | |
11f5b71a VM |
467 | insn = emit_add2_insn (x, index_scale); |
468 | lra_assert (insn != NULL_RTX); | |
55a2c322 VM |
469 | } |
470 | } | |
471 | } | |
472 | } | |
473 | /* Functions emit_... can create pseudos -- so expand the pseudo | |
474 | data. */ | |
475 | if (old != max_reg_num ()) | |
a2d0d374 | 476 | expand_reg_data (old); |
55a2c322 VM |
477 | } |
478 | ||
479 | /* The number of emitted reload insns so far. */ | |
480 | int lra_curr_reload_num; | |
481 | ||
482 | /* Emit x := y, processing special case when y = u + v or y = u + v * | |
483 | scale + w through emit_add (Y can be an address which is base + | |
484 | index reg * scale + displacement in general case). X may be used | |
485 | as intermediate result therefore it should be not in Y. */ | |
486 | void | |
487 | lra_emit_move (rtx x, rtx y) | |
488 | { | |
489 | int old; | |
490 | ||
491 | if (GET_CODE (y) != PLUS) | |
492 | { | |
493 | if (rtx_equal_p (x, y)) | |
494 | return; | |
495 | old = max_reg_num (); | |
496 | emit_move_insn (x, y); | |
497 | if (REG_P (x)) | |
498 | lra_reg_info[ORIGINAL_REGNO (x)].last_reload = ++lra_curr_reload_num; | |
499 | /* Function emit_move can create pseudos -- so expand the pseudo | |
500 | data. */ | |
501 | if (old != max_reg_num ()) | |
a2d0d374 | 502 | expand_reg_data (old); |
55a2c322 VM |
503 | return; |
504 | } | |
505 | lra_emit_add (x, XEXP (y, 0), XEXP (y, 1)); | |
506 | } | |
507 | ||
508 | /* Update insn operands which are duplication of operands whose | |
509 | numbers are in array of NOPS (with end marker -1). The insn is | |
510 | represented by its LRA internal representation ID. */ | |
511 | void | |
512 | lra_update_dups (lra_insn_recog_data_t id, signed char *nops) | |
513 | { | |
514 | int i, j, nop; | |
515 | struct lra_static_insn_data *static_id = id->insn_static_data; | |
516 | ||
517 | for (i = 0; i < static_id->n_dups; i++) | |
518 | for (j = 0; (nop = nops[j]) >= 0; j++) | |
519 | if (static_id->dup_num[i] == nop) | |
520 | *id->dup_loc[i] = *id->operand_loc[nop]; | |
521 | } | |
522 | ||
523 | \f | |
524 | ||
525 | /* This page contains code dealing with info about registers in the | |
526 | insns. */ | |
527 | ||
528 | /* Pools for insn reg info. */ | |
fcb87c50 | 529 | object_allocator<lra_insn_reg> lra_insn_reg_pool ("insn regs"); |
55a2c322 | 530 | |
c34c46dd RS |
531 | /* Create LRA insn related info about a reference to REGNO in INSN with |
532 | TYPE (in/out/inout), biggest reference mode MODE, flag that it is | |
55a2c322 VM |
533 | reference through subreg (SUBREG_P), flag that is early clobbered |
534 | in the insn (EARLY_CLOBBER), and reference to the next insn reg | |
535 | info (NEXT). */ | |
536 | static struct lra_insn_reg * | |
cfa434f6 | 537 | new_insn_reg (rtx_insn *insn, int regno, enum op_type type, |
ef4bddc2 | 538 | machine_mode mode, |
55a2c322 VM |
539 | bool subreg_p, bool early_clobber, struct lra_insn_reg *next) |
540 | { | |
fb0b2914 | 541 | lra_insn_reg *ir = lra_insn_reg_pool.allocate (); |
55a2c322 VM |
542 | ir->type = type; |
543 | ir->biggest_mode = mode; | |
c34c46dd RS |
544 | if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (lra_reg_info[regno].biggest_mode) |
545 | && NONDEBUG_INSN_P (insn)) | |
b28ece32 | 546 | lra_reg_info[regno].biggest_mode = mode; |
55a2c322 VM |
547 | ir->subreg_p = subreg_p; |
548 | ir->early_clobber = early_clobber; | |
549 | ir->regno = regno; | |
550 | ir->next = next; | |
551 | return ir; | |
552 | } | |
553 | ||
55a2c322 VM |
554 | /* Free insn reg info list IR. */ |
555 | static void | |
556 | free_insn_regs (struct lra_insn_reg *ir) | |
557 | { | |
558 | struct lra_insn_reg *next_ir; | |
559 | ||
560 | for (; ir != NULL; ir = next_ir) | |
561 | { | |
562 | next_ir = ir->next; | |
fb0b2914 | 563 | lra_insn_reg_pool.remove (ir); |
55a2c322 VM |
564 | } |
565 | } | |
566 | ||
567 | /* Finish pool for insn reg info. */ | |
568 | static void | |
569 | finish_insn_regs (void) | |
570 | { | |
fb0b2914 | 571 | lra_insn_reg_pool.release (); |
55a2c322 VM |
572 | } |
573 | ||
574 | \f | |
575 | ||
576 | /* This page contains code dealing LRA insn info (or in other words | |
577 | LRA internal insn representation). */ | |
578 | ||
55a2c322 VM |
579 | /* Map INSN_CODE -> the static insn data. This info is valid during |
580 | all translation unit. */ | |
523ba738 | 581 | struct lra_static_insn_data *insn_code_data[NUM_INSN_CODES]; |
55a2c322 VM |
582 | |
583 | /* Debug insns are represented as a special insn with one input | |
584 | operand which is RTL expression in var_location. */ | |
585 | ||
586 | /* The following data are used as static insn operand data for all | |
587 | debug insns. If structure lra_operand_data is changed, the | |
588 | initializer should be changed too. */ | |
589 | static struct lra_operand_data debug_operand_data = | |
590 | { | |
591 | NULL, /* alternative */ | |
592 | VOIDmode, /* We are not interesting in the operand mode. */ | |
593 | OP_IN, | |
594 | 0, 0, 0, 0 | |
595 | }; | |
596 | ||
597 | /* The following data are used as static insn data for all debug | |
598 | insns. If structure lra_static_insn_data is changed, the | |
599 | initializer should be changed too. */ | |
600 | static struct lra_static_insn_data debug_insn_static_data = | |
601 | { | |
602 | &debug_operand_data, | |
603 | 0, /* Duplication operands #. */ | |
604 | -1, /* Commutative operand #. */ | |
605 | 1, /* Operands #. There is only one operand which is debug RTL | |
606 | expression. */ | |
607 | 0, /* Duplications #. */ | |
608 | 0, /* Alternatives #. We are not interesting in alternatives | |
609 | because we does not proceed debug_insns for reloads. */ | |
610 | NULL, /* Hard registers referenced in machine description. */ | |
611 | NULL /* Descriptions of operands in alternatives. */ | |
612 | }; | |
613 | ||
614 | /* Called once per compiler work to initialize some LRA data related | |
615 | to insns. */ | |
616 | static void | |
617 | init_insn_code_data_once (void) | |
618 | { | |
619 | memset (insn_code_data, 0, sizeof (insn_code_data)); | |
55a2c322 VM |
620 | } |
621 | ||
622 | /* Called once per compiler work to finalize some LRA data related to | |
623 | insns. */ | |
624 | static void | |
625 | finish_insn_code_data_once (void) | |
626 | { | |
523ba738 | 627 | for (unsigned int i = 0; i < NUM_INSN_CODES; i++) |
55a2c322 VM |
628 | { |
629 | if (insn_code_data[i] != NULL) | |
630 | free (insn_code_data[i]); | |
55a2c322 VM |
631 | } |
632 | } | |
633 | ||
55a2c322 VM |
634 | /* Return static insn data, allocate and setup if necessary. Although |
635 | dup_num is static data (it depends only on icode), to set it up we | |
636 | need to extract insn first. So recog_data should be valid for | |
637 | normal insn (ICODE >= 0) before the call. */ | |
638 | static struct lra_static_insn_data * | |
639 | get_static_insn_data (int icode, int nop, int ndup, int nalt) | |
640 | { | |
641 | struct lra_static_insn_data *data; | |
642 | size_t n_bytes; | |
643 | ||
523ba738 | 644 | lra_assert (icode < (int) NUM_INSN_CODES); |
55a2c322 VM |
645 | if (icode >= 0 && (data = insn_code_data[icode]) != NULL) |
646 | return data; | |
647 | lra_assert (nop >= 0 && ndup >= 0 && nalt >= 0); | |
648 | n_bytes = sizeof (struct lra_static_insn_data) | |
649 | + sizeof (struct lra_operand_data) * nop | |
650 | + sizeof (int) * ndup; | |
651 | data = XNEWVAR (struct lra_static_insn_data, n_bytes); | |
0c331756 | 652 | data->operand_alternative = NULL; |
55a2c322 VM |
653 | data->n_operands = nop; |
654 | data->n_dups = ndup; | |
655 | data->n_alternatives = nalt; | |
656 | data->operand = ((struct lra_operand_data *) | |
657 | ((char *) data + sizeof (struct lra_static_insn_data))); | |
658 | data->dup_num = ((int *) ((char *) data->operand | |
659 | + sizeof (struct lra_operand_data) * nop)); | |
660 | if (icode >= 0) | |
661 | { | |
662 | int i; | |
663 | ||
664 | insn_code_data[icode] = data; | |
665 | for (i = 0; i < nop; i++) | |
666 | { | |
667 | data->operand[i].constraint | |
668 | = insn_data[icode].operand[i].constraint; | |
669 | data->operand[i].mode = insn_data[icode].operand[i].mode; | |
670 | data->operand[i].strict_low = insn_data[icode].operand[i].strict_low; | |
671 | data->operand[i].is_operator | |
672 | = insn_data[icode].operand[i].is_operator; | |
673 | data->operand[i].type | |
674 | = (data->operand[i].constraint[0] == '=' ? OP_OUT | |
675 | : data->operand[i].constraint[0] == '+' ? OP_INOUT | |
676 | : OP_IN); | |
677 | data->operand[i].is_address = false; | |
678 | } | |
679 | for (i = 0; i < ndup; i++) | |
680 | data->dup_num[i] = recog_data.dup_num[i]; | |
681 | } | |
682 | return data; | |
683 | } | |
684 | ||
685 | /* The current length of the following array. */ | |
686 | int lra_insn_recog_data_len; | |
687 | ||
688 | /* Map INSN_UID -> the insn recog data (NULL if unknown). */ | |
689 | lra_insn_recog_data_t *lra_insn_recog_data; | |
690 | ||
691 | /* Initialize LRA data about insns. */ | |
692 | static void | |
693 | init_insn_recog_data (void) | |
694 | { | |
695 | lra_insn_recog_data_len = 0; | |
696 | lra_insn_recog_data = NULL; | |
55a2c322 VM |
697 | } |
698 | ||
699 | /* Expand, if necessary, LRA data about insns. */ | |
700 | static void | |
701 | check_and_expand_insn_recog_data (int index) | |
702 | { | |
703 | int i, old; | |
704 | ||
705 | if (lra_insn_recog_data_len > index) | |
706 | return; | |
707 | old = lra_insn_recog_data_len; | |
708 | lra_insn_recog_data_len = index * 3 / 2 + 1; | |
709 | lra_insn_recog_data = XRESIZEVEC (lra_insn_recog_data_t, | |
710 | lra_insn_recog_data, | |
711 | lra_insn_recog_data_len); | |
712 | for (i = old; i < lra_insn_recog_data_len; i++) | |
713 | lra_insn_recog_data[i] = NULL; | |
714 | } | |
715 | ||
716 | /* Finish LRA DATA about insn. */ | |
717 | static void | |
718 | free_insn_recog_data (lra_insn_recog_data_t data) | |
719 | { | |
720 | if (data->operand_loc != NULL) | |
721 | free (data->operand_loc); | |
722 | if (data->dup_loc != NULL) | |
723 | free (data->dup_loc); | |
724 | if (data->arg_hard_regs != NULL) | |
725 | free (data->arg_hard_regs); | |
55a2c322 VM |
726 | if (data->icode < 0 && NONDEBUG_INSN_P (data->insn)) |
727 | { | |
728 | if (data->insn_static_data->operand_alternative != NULL) | |
0c331756 RS |
729 | free (const_cast <operand_alternative *> |
730 | (data->insn_static_data->operand_alternative)); | |
55a2c322 VM |
731 | free_insn_regs (data->insn_static_data->hard_regs); |
732 | free (data->insn_static_data); | |
733 | } | |
734 | free_insn_regs (data->regs); | |
735 | data->regs = NULL; | |
736 | free (data); | |
737 | } | |
738 | ||
fb0b2914 | 739 | /* Pools for copies. */ |
fcb87c50 | 740 | static object_allocator<lra_copy> lra_copy_pool ("lra copies"); |
fb0b2914 | 741 | |
55a2c322 VM |
742 | /* Finish LRA data about all insns. */ |
743 | static void | |
744 | finish_insn_recog_data (void) | |
745 | { | |
746 | int i; | |
747 | lra_insn_recog_data_t data; | |
748 | ||
749 | for (i = 0; i < lra_insn_recog_data_len; i++) | |
750 | if ((data = lra_insn_recog_data[i]) != NULL) | |
751 | free_insn_recog_data (data); | |
752 | finish_insn_regs (); | |
fb0b2914 ML |
753 | lra_copy_pool.release (); |
754 | lra_insn_reg_pool.release (); | |
55a2c322 VM |
755 | free (lra_insn_recog_data); |
756 | } | |
757 | ||
758 | /* Setup info about operands in alternatives of LRA DATA of insn. */ | |
759 | static void | |
0c331756 RS |
760 | setup_operand_alternative (lra_insn_recog_data_t data, |
761 | const operand_alternative *op_alt) | |
55a2c322 | 762 | { |
0c331756 | 763 | int i, j, nop, nalt; |
55a2c322 VM |
764 | int icode = data->icode; |
765 | struct lra_static_insn_data *static_data = data->insn_static_data; | |
766 | ||
55a2c322 VM |
767 | static_data->commutative = -1; |
768 | nop = static_data->n_operands; | |
55a2c322 | 769 | nalt = static_data->n_alternatives; |
0c331756 | 770 | static_data->operand_alternative = op_alt; |
55a2c322 VM |
771 | for (i = 0; i < nop; i++) |
772 | { | |
0c331756 RS |
773 | static_data->operand[i].early_clobber = false; |
774 | static_data->operand[i].is_address = false; | |
775 | if (static_data->operand[i].constraint[0] == '%') | |
55a2c322 | 776 | { |
0c331756 RS |
777 | /* We currently only support one commutative pair of operands. */ |
778 | if (static_data->commutative < 0) | |
779 | static_data->commutative = i; | |
780 | else | |
781 | lra_assert (icode < 0); /* Asm */ | |
782 | /* The last operand should not be marked commutative. */ | |
783 | lra_assert (i != nop - 1); | |
55a2c322 VM |
784 | } |
785 | } | |
0c331756 RS |
786 | for (j = 0; j < nalt; j++) |
787 | for (i = 0; i < nop; i++, op_alt++) | |
788 | { | |
789 | static_data->operand[i].early_clobber |= op_alt->earlyclobber; | |
790 | static_data->operand[i].is_address |= op_alt->is_address; | |
791 | } | |
55a2c322 VM |
792 | } |
793 | ||
794 | /* Recursively process X and collect info about registers, which are | |
795 | not the insn operands, in X with TYPE (in/out/inout) and flag that | |
796 | it is early clobbered in the insn (EARLY_CLOBBER) and add the info | |
797 | to LIST. X is a part of insn given by DATA. Return the result | |
798 | list. */ | |
799 | static struct lra_insn_reg * | |
800 | collect_non_operand_hard_regs (rtx *x, lra_insn_recog_data_t data, | |
801 | struct lra_insn_reg *list, | |
802 | enum op_type type, bool early_clobber) | |
803 | { | |
804 | int i, j, regno, last; | |
805 | bool subreg_p; | |
ef4bddc2 | 806 | machine_mode mode; |
55a2c322 VM |
807 | struct lra_insn_reg *curr; |
808 | rtx op = *x; | |
809 | enum rtx_code code = GET_CODE (op); | |
810 | const char *fmt = GET_RTX_FORMAT (code); | |
811 | ||
812 | for (i = 0; i < data->insn_static_data->n_operands; i++) | |
813 | if (x == data->operand_loc[i]) | |
814 | /* It is an operand loc. Stop here. */ | |
815 | return list; | |
816 | for (i = 0; i < data->insn_static_data->n_dups; i++) | |
817 | if (x == data->dup_loc[i]) | |
818 | /* It is a dup loc. Stop here. */ | |
819 | return list; | |
820 | mode = GET_MODE (op); | |
821 | subreg_p = false; | |
822 | if (code == SUBREG) | |
823 | { | |
824 | op = SUBREG_REG (op); | |
825 | code = GET_CODE (op); | |
826 | if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (op))) | |
827 | { | |
828 | mode = GET_MODE (op); | |
829 | if (GET_MODE_SIZE (mode) > REGMODE_NATURAL_SIZE (mode)) | |
830 | subreg_p = true; | |
831 | } | |
832 | } | |
833 | if (REG_P (op)) | |
834 | { | |
835 | if ((regno = REGNO (op)) >= FIRST_PSEUDO_REGISTER) | |
836 | return list; | |
d9cf932c VM |
837 | /* Process all regs even unallocatable ones as we need info |
838 | about all regs for rematerialization pass. */ | |
55a2c322 VM |
839 | for (last = regno + hard_regno_nregs[regno][mode]; |
840 | regno < last; | |
841 | regno++) | |
d9cf932c VM |
842 | { |
843 | for (curr = list; curr != NULL; curr = curr->next) | |
844 | if (curr->regno == regno && curr->subreg_p == subreg_p | |
845 | && curr->biggest_mode == mode) | |
55a2c322 | 846 | { |
d9cf932c VM |
847 | if (curr->type != type) |
848 | curr->type = OP_INOUT; | |
849 | if (curr->early_clobber != early_clobber) | |
850 | curr->early_clobber = true; | |
851 | break; | |
852 | } | |
853 | if (curr == NULL) | |
854 | { | |
855 | /* This is a new hard regno or the info can not be | |
856 | integrated into the found structure. */ | |
55a2c322 | 857 | #ifdef STACK_REGS |
d9cf932c VM |
858 | early_clobber |
859 | = (early_clobber | |
860 | /* This clobber is to inform popping floating | |
861 | point stack only. */ | |
862 | && ! (FIRST_STACK_REG <= regno | |
863 | && regno <= LAST_STACK_REG)); | |
55a2c322 | 864 | #endif |
d9cf932c VM |
865 | list = new_insn_reg (data->insn, regno, type, mode, subreg_p, |
866 | early_clobber, list); | |
867 | } | |
868 | } | |
55a2c322 VM |
869 | return list; |
870 | } | |
871 | switch (code) | |
872 | { | |
873 | case SET: | |
874 | list = collect_non_operand_hard_regs (&SET_DEST (op), data, | |
875 | list, OP_OUT, false); | |
876 | list = collect_non_operand_hard_regs (&SET_SRC (op), data, | |
877 | list, OP_IN, false); | |
878 | break; | |
879 | case CLOBBER: | |
880 | /* We treat clobber of non-operand hard registers as early | |
f4eafc30 | 881 | clobber (the behavior is expected from asm). */ |
55a2c322 VM |
882 | list = collect_non_operand_hard_regs (&XEXP (op, 0), data, |
883 | list, OP_OUT, true); | |
884 | break; | |
885 | case PRE_INC: case PRE_DEC: case POST_INC: case POST_DEC: | |
886 | list = collect_non_operand_hard_regs (&XEXP (op, 0), data, | |
887 | list, OP_INOUT, false); | |
888 | break; | |
889 | case PRE_MODIFY: case POST_MODIFY: | |
890 | list = collect_non_operand_hard_regs (&XEXP (op, 0), data, | |
891 | list, OP_INOUT, false); | |
892 | list = collect_non_operand_hard_regs (&XEXP (op, 1), data, | |
893 | list, OP_IN, false); | |
894 | break; | |
895 | default: | |
896 | fmt = GET_RTX_FORMAT (code); | |
897 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
898 | { | |
899 | if (fmt[i] == 'e') | |
900 | list = collect_non_operand_hard_regs (&XEXP (op, i), data, | |
901 | list, OP_IN, false); | |
902 | else if (fmt[i] == 'E') | |
903 | for (j = XVECLEN (op, i) - 1; j >= 0; j--) | |
904 | list = collect_non_operand_hard_regs (&XVECEXP (op, i, j), data, | |
905 | list, OP_IN, false); | |
906 | } | |
907 | } | |
908 | return list; | |
909 | } | |
910 | ||
911 | /* Set up and return info about INSN. Set up the info if it is not set up | |
912 | yet. */ | |
913 | lra_insn_recog_data_t | |
cfa434f6 | 914 | lra_set_insn_recog_data (rtx_insn *insn) |
55a2c322 VM |
915 | { |
916 | lra_insn_recog_data_t data; | |
917 | int i, n, icode; | |
918 | rtx **locs; | |
919 | unsigned int uid = INSN_UID (insn); | |
920 | struct lra_static_insn_data *insn_static_data; | |
921 | ||
922 | check_and_expand_insn_recog_data (uid); | |
923 | if (DEBUG_INSN_P (insn)) | |
924 | icode = -1; | |
925 | else | |
926 | { | |
927 | icode = INSN_CODE (insn); | |
928 | if (icode < 0) | |
929 | /* It might be a new simple insn which is not recognized yet. */ | |
930 | INSN_CODE (insn) = icode = recog_memoized (insn); | |
931 | } | |
932 | data = XNEW (struct lra_insn_recog_data); | |
933 | lra_insn_recog_data[uid] = data; | |
934 | data->insn = insn; | |
935 | data->used_insn_alternative = -1; | |
936 | data->icode = icode; | |
937 | data->regs = NULL; | |
938 | if (DEBUG_INSN_P (insn)) | |
939 | { | |
940 | data->insn_static_data = &debug_insn_static_data; | |
941 | data->dup_loc = NULL; | |
942 | data->arg_hard_regs = NULL; | |
9840b2fa | 943 | data->preferred_alternatives = ALL_ALTERNATIVES; |
55a2c322 VM |
944 | data->operand_loc = XNEWVEC (rtx *, 1); |
945 | data->operand_loc[0] = &INSN_VAR_LOCATION_LOC (insn); | |
946 | return data; | |
947 | } | |
948 | if (icode < 0) | |
949 | { | |
0c331756 | 950 | int nop, nalt; |
ef4bddc2 | 951 | machine_mode operand_mode[MAX_RECOG_OPERANDS]; |
55a2c322 VM |
952 | const char *constraints[MAX_RECOG_OPERANDS]; |
953 | ||
954 | nop = asm_noperands (PATTERN (insn)); | |
955 | data->operand_loc = data->dup_loc = NULL; | |
0c331756 | 956 | nalt = 1; |
55a2c322 | 957 | if (nop < 0) |
91c5ee5b | 958 | { |
0e9e0a21 | 959 | /* It is a special insn like USE or CLOBBER. We should |
91c5ee5b VM |
960 | recognize any regular insn otherwise LRA can do nothing |
961 | with this insn. */ | |
962 | gcc_assert (GET_CODE (PATTERN (insn)) == USE | |
963 | || GET_CODE (PATTERN (insn)) == CLOBBER | |
964 | || GET_CODE (PATTERN (insn)) == ASM_INPUT); | |
965 | data->insn_static_data = insn_static_data | |
0c331756 | 966 | = get_static_insn_data (-1, 0, 0, nalt); |
91c5ee5b | 967 | } |
55a2c322 VM |
968 | else |
969 | { | |
970 | /* expand_asm_operands makes sure there aren't too many | |
971 | operands. */ | |
972 | lra_assert (nop <= MAX_RECOG_OPERANDS); | |
973 | if (nop != 0) | |
974 | data->operand_loc = XNEWVEC (rtx *, nop); | |
975 | /* Now get the operand values and constraints out of the | |
976 | insn. */ | |
977 | decode_asm_operands (PATTERN (insn), NULL, | |
978 | data->operand_loc, | |
979 | constraints, operand_mode, NULL); | |
55a2c322 VM |
980 | if (nop > 0) |
981 | { | |
982 | const char *p = recog_data.constraints[0]; | |
f4eafc30 | 983 | |
55a2c322 | 984 | for (p = constraints[0]; *p; p++) |
0c331756 | 985 | nalt += *p == ','; |
55a2c322 VM |
986 | } |
987 | data->insn_static_data = insn_static_data | |
0c331756 | 988 | = get_static_insn_data (-1, nop, 0, nalt); |
55a2c322 VM |
989 | for (i = 0; i < nop; i++) |
990 | { | |
991 | insn_static_data->operand[i].mode = operand_mode[i]; | |
992 | insn_static_data->operand[i].constraint = constraints[i]; | |
993 | insn_static_data->operand[i].strict_low = false; | |
994 | insn_static_data->operand[i].is_operator = false; | |
995 | insn_static_data->operand[i].is_address = false; | |
996 | } | |
997 | } | |
998 | for (i = 0; i < insn_static_data->n_operands; i++) | |
999 | insn_static_data->operand[i].type | |
1000 | = (insn_static_data->operand[i].constraint[0] == '=' ? OP_OUT | |
1001 | : insn_static_data->operand[i].constraint[0] == '+' ? OP_INOUT | |
1002 | : OP_IN); | |
9840b2fa | 1003 | data->preferred_alternatives = ALL_ALTERNATIVES; |
0c331756 RS |
1004 | if (nop > 0) |
1005 | { | |
1006 | operand_alternative *op_alt = XCNEWVEC (operand_alternative, | |
1007 | nalt * nop); | |
1008 | preprocess_constraints (nop, nalt, constraints, op_alt); | |
1009 | setup_operand_alternative (data, op_alt); | |
1010 | } | |
55a2c322 VM |
1011 | } |
1012 | else | |
1013 | { | |
1014 | insn_extract (insn); | |
1015 | data->insn_static_data = insn_static_data | |
1016 | = get_static_insn_data (icode, insn_data[icode].n_operands, | |
1017 | insn_data[icode].n_dups, | |
1018 | insn_data[icode].n_alternatives); | |
1019 | n = insn_static_data->n_operands; | |
1020 | if (n == 0) | |
1021 | locs = NULL; | |
1022 | else | |
1023 | { | |
1024 | locs = XNEWVEC (rtx *, n); | |
1025 | memcpy (locs, recog_data.operand_loc, n * sizeof (rtx *)); | |
1026 | } | |
1027 | data->operand_loc = locs; | |
1028 | n = insn_static_data->n_dups; | |
1029 | if (n == 0) | |
1030 | locs = NULL; | |
1031 | else | |
1032 | { | |
1033 | locs = XNEWVEC (rtx *, n); | |
1034 | memcpy (locs, recog_data.dup_loc, n * sizeof (rtx *)); | |
1035 | } | |
1036 | data->dup_loc = locs; | |
9840b2fa | 1037 | data->preferred_alternatives = get_preferred_alternatives (insn); |
0c331756 RS |
1038 | const operand_alternative *op_alt = preprocess_insn_constraints (icode); |
1039 | if (!insn_static_data->operand_alternative) | |
1040 | setup_operand_alternative (data, op_alt); | |
1041 | else if (op_alt != insn_static_data->operand_alternative) | |
1042 | insn_static_data->operand_alternative = op_alt; | |
55a2c322 VM |
1043 | } |
1044 | if (GET_CODE (PATTERN (insn)) == CLOBBER || GET_CODE (PATTERN (insn)) == USE) | |
1045 | insn_static_data->hard_regs = NULL; | |
1046 | else | |
1047 | insn_static_data->hard_regs | |
1048 | = collect_non_operand_hard_regs (&PATTERN (insn), data, | |
1049 | NULL, OP_IN, false); | |
55a2c322 VM |
1050 | data->arg_hard_regs = NULL; |
1051 | if (CALL_P (insn)) | |
1052 | { | |
9d86e84e | 1053 | bool use_p; |
55a2c322 VM |
1054 | rtx link; |
1055 | int n_hard_regs, regno, arg_hard_regs[FIRST_PSEUDO_REGISTER]; | |
1056 | ||
1057 | n_hard_regs = 0; | |
1058 | /* Finding implicit hard register usage. We believe it will be | |
1059 | not changed whatever transformations are used. Call insns | |
1060 | are such example. */ | |
1061 | for (link = CALL_INSN_FUNCTION_USAGE (insn); | |
1062 | link != NULL_RTX; | |
1063 | link = XEXP (link, 1)) | |
9d86e84e VM |
1064 | if (((use_p = GET_CODE (XEXP (link, 0)) == USE) |
1065 | || GET_CODE (XEXP (link, 0)) == CLOBBER) | |
55a2c322 VM |
1066 | && REG_P (XEXP (XEXP (link, 0), 0))) |
1067 | { | |
1068 | regno = REGNO (XEXP (XEXP (link, 0), 0)); | |
1069 | lra_assert (regno < FIRST_PSEUDO_REGISTER); | |
1070 | /* It is an argument register. */ | |
dc8afb70 | 1071 | for (i = REG_NREGS (XEXP (XEXP (link, 0), 0)) - 1; i >= 0; i--) |
9d86e84e VM |
1072 | arg_hard_regs[n_hard_regs++] |
1073 | = regno + i + (use_p ? 0 : FIRST_PSEUDO_REGISTER); | |
55a2c322 VM |
1074 | } |
1075 | if (n_hard_regs != 0) | |
1076 | { | |
1077 | arg_hard_regs[n_hard_regs++] = -1; | |
1078 | data->arg_hard_regs = XNEWVEC (int, n_hard_regs); | |
1079 | memcpy (data->arg_hard_regs, arg_hard_regs, | |
1080 | sizeof (int) * n_hard_regs); | |
1081 | } | |
1082 | } | |
1083 | /* Some output operand can be recognized only from the context not | |
1084 | from the constraints which are empty in this case. Call insn may | |
1085 | contain a hard register in set destination with empty constraint | |
1086 | and extract_insn treats them as an input. */ | |
1087 | for (i = 0; i < insn_static_data->n_operands; i++) | |
1088 | { | |
1089 | int j; | |
1090 | rtx pat, set; | |
1091 | struct lra_operand_data *operand = &insn_static_data->operand[i]; | |
1092 | ||
1093 | /* ??? Should we treat 'X' the same way. It looks to me that | |
1094 | 'X' means anything and empty constraint means we do not | |
1095 | care. */ | |
1096 | if (operand->type != OP_IN || *operand->constraint != '\0' | |
1097 | || operand->is_operator) | |
1098 | continue; | |
1099 | pat = PATTERN (insn); | |
1100 | if (GET_CODE (pat) == SET) | |
1101 | { | |
1102 | if (data->operand_loc[i] != &SET_DEST (pat)) | |
1103 | continue; | |
1104 | } | |
1105 | else if (GET_CODE (pat) == PARALLEL) | |
1106 | { | |
1107 | for (j = XVECLEN (pat, 0) - 1; j >= 0; j--) | |
1108 | { | |
1109 | set = XVECEXP (PATTERN (insn), 0, j); | |
1110 | if (GET_CODE (set) == SET | |
1111 | && &SET_DEST (set) == data->operand_loc[i]) | |
1112 | break; | |
1113 | } | |
1114 | if (j < 0) | |
1115 | continue; | |
1116 | } | |
1117 | else | |
1118 | continue; | |
1119 | operand->type = OP_OUT; | |
1120 | } | |
1121 | return data; | |
1122 | } | |
1123 | ||
1124 | /* Return info about insn give by UID. The info should be already set | |
1125 | up. */ | |
1126 | static lra_insn_recog_data_t | |
1127 | get_insn_recog_data_by_uid (int uid) | |
1128 | { | |
1129 | lra_insn_recog_data_t data; | |
1130 | ||
1131 | data = lra_insn_recog_data[uid]; | |
1132 | lra_assert (data != NULL); | |
1133 | return data; | |
1134 | } | |
1135 | ||
1136 | /* Invalidate all info about insn given by its UID. */ | |
1137 | static void | |
1138 | invalidate_insn_recog_data (int uid) | |
1139 | { | |
1140 | lra_insn_recog_data_t data; | |
1141 | ||
1142 | data = lra_insn_recog_data[uid]; | |
1143 | lra_assert (data != NULL); | |
1144 | free_insn_recog_data (data); | |
1145 | lra_insn_recog_data[uid] = NULL; | |
1146 | } | |
1147 | ||
1148 | /* Update all the insn info about INSN. It is usually called when | |
1149 | something in the insn was changed. Return the updated info. */ | |
1150 | lra_insn_recog_data_t | |
cfa434f6 | 1151 | lra_update_insn_recog_data (rtx_insn *insn) |
55a2c322 VM |
1152 | { |
1153 | lra_insn_recog_data_t data; | |
1154 | int n; | |
1155 | unsigned int uid = INSN_UID (insn); | |
1156 | struct lra_static_insn_data *insn_static_data; | |
8d49e7ef | 1157 | HOST_WIDE_INT sp_offset = 0; |
f4eafc30 | 1158 | |
55a2c322 VM |
1159 | check_and_expand_insn_recog_data (uid); |
1160 | if ((data = lra_insn_recog_data[uid]) != NULL | |
1161 | && data->icode != INSN_CODE (insn)) | |
1162 | { | |
8d49e7ef | 1163 | sp_offset = data->sp_offset; |
55a2c322 VM |
1164 | invalidate_insn_data_regno_info (data, insn, get_insn_freq (insn)); |
1165 | invalidate_insn_recog_data (uid); | |
1166 | data = NULL; | |
1167 | } | |
1168 | if (data == NULL) | |
8d49e7ef VM |
1169 | { |
1170 | data = lra_get_insn_recog_data (insn); | |
1171 | /* Initiate or restore SP offset. */ | |
1172 | data->sp_offset = sp_offset; | |
1173 | return data; | |
1174 | } | |
55a2c322 VM |
1175 | insn_static_data = data->insn_static_data; |
1176 | data->used_insn_alternative = -1; | |
1177 | if (DEBUG_INSN_P (insn)) | |
1178 | return data; | |
1179 | if (data->icode < 0) | |
1180 | { | |
1181 | int nop; | |
ef4bddc2 | 1182 | machine_mode operand_mode[MAX_RECOG_OPERANDS]; |
55a2c322 VM |
1183 | const char *constraints[MAX_RECOG_OPERANDS]; |
1184 | ||
1185 | nop = asm_noperands (PATTERN (insn)); | |
1186 | if (nop >= 0) | |
1187 | { | |
1188 | lra_assert (nop == data->insn_static_data->n_operands); | |
1189 | /* Now get the operand values and constraints out of the | |
1190 | insn. */ | |
1191 | decode_asm_operands (PATTERN (insn), NULL, | |
1192 | data->operand_loc, | |
1193 | constraints, operand_mode, NULL); | |
55a2c322 | 1194 | |
b2b29377 MM |
1195 | if (flag_checking) |
1196 | for (int i = 0; i < nop; i++) | |
55a2c322 VM |
1197 | lra_assert |
1198 | (insn_static_data->operand[i].mode == operand_mode[i] | |
1199 | && insn_static_data->operand[i].constraint == constraints[i] | |
1200 | && ! insn_static_data->operand[i].is_operator); | |
55a2c322 | 1201 | } |
55a2c322 | 1202 | |
b2b29377 MM |
1203 | if (flag_checking) |
1204 | for (int i = 0; i < insn_static_data->n_operands; i++) | |
55a2c322 VM |
1205 | lra_assert |
1206 | (insn_static_data->operand[i].type | |
1207 | == (insn_static_data->operand[i].constraint[0] == '=' ? OP_OUT | |
1208 | : insn_static_data->operand[i].constraint[0] == '+' ? OP_INOUT | |
1209 | : OP_IN)); | |
55a2c322 VM |
1210 | } |
1211 | else | |
1212 | { | |
1213 | insn_extract (insn); | |
1214 | n = insn_static_data->n_operands; | |
1215 | if (n != 0) | |
1216 | memcpy (data->operand_loc, recog_data.operand_loc, n * sizeof (rtx *)); | |
1217 | n = insn_static_data->n_dups; | |
1218 | if (n != 0) | |
1219 | memcpy (data->dup_loc, recog_data.dup_loc, n * sizeof (rtx *)); | |
9840b2fa | 1220 | lra_assert (check_bool_attrs (insn)); |
55a2c322 VM |
1221 | } |
1222 | return data; | |
1223 | } | |
1224 | ||
1225 | /* Set up that INSN is using alternative ALT now. */ | |
1226 | void | |
cfa434f6 | 1227 | lra_set_used_insn_alternative (rtx_insn *insn, int alt) |
55a2c322 VM |
1228 | { |
1229 | lra_insn_recog_data_t data; | |
1230 | ||
1231 | data = lra_get_insn_recog_data (insn); | |
1232 | data->used_insn_alternative = alt; | |
1233 | } | |
1234 | ||
1235 | /* Set up that insn with UID is using alternative ALT now. The insn | |
1236 | info should be already set up. */ | |
1237 | void | |
1238 | lra_set_used_insn_alternative_by_uid (int uid, int alt) | |
1239 | { | |
1240 | lra_insn_recog_data_t data; | |
1241 | ||
1242 | check_and_expand_insn_recog_data (uid); | |
1243 | data = lra_insn_recog_data[uid]; | |
1244 | lra_assert (data != NULL); | |
1245 | data->used_insn_alternative = alt; | |
1246 | } | |
1247 | ||
1248 | \f | |
1249 | ||
1250 | /* This page contains code dealing with common register info and | |
1251 | pseudo copies. */ | |
1252 | ||
1253 | /* The size of the following array. */ | |
1254 | static int reg_info_size; | |
1255 | /* Common info about each register. */ | |
1256 | struct lra_reg *lra_reg_info; | |
1257 | ||
1258 | /* Last register value. */ | |
1259 | static int last_reg_value; | |
1260 | ||
1261 | /* Return new register value. */ | |
1262 | static int | |
1263 | get_new_reg_value (void) | |
1264 | { | |
1265 | return ++last_reg_value; | |
1266 | } | |
1267 | ||
55a2c322 | 1268 | /* Vec referring to pseudo copies. */ |
9771b263 | 1269 | static vec<lra_copy_t> copy_vec; |
55a2c322 VM |
1270 | |
1271 | /* Initialize I-th element of lra_reg_info. */ | |
1272 | static inline void | |
1273 | initialize_lra_reg_info_element (int i) | |
1274 | { | |
1275 | bitmap_initialize (&lra_reg_info[i].insn_bitmap, ®_obstack); | |
1276 | #ifdef STACK_REGS | |
1277 | lra_reg_info[i].no_stack_p = false; | |
1278 | #endif | |
1279 | CLEAR_HARD_REG_SET (lra_reg_info[i].conflict_hard_regs); | |
10e1bdb2 | 1280 | CLEAR_HARD_REG_SET (lra_reg_info[i].actual_call_used_reg_set); |
55a2c322 VM |
1281 | lra_reg_info[i].preferred_hard_regno1 = -1; |
1282 | lra_reg_info[i].preferred_hard_regno2 = -1; | |
1283 | lra_reg_info[i].preferred_hard_regno_profit1 = 0; | |
1284 | lra_reg_info[i].preferred_hard_regno_profit2 = 0; | |
b28ece32 | 1285 | lra_reg_info[i].biggest_mode = VOIDmode; |
55a2c322 VM |
1286 | lra_reg_info[i].live_ranges = NULL; |
1287 | lra_reg_info[i].nrefs = lra_reg_info[i].freq = 0; | |
1288 | lra_reg_info[i].last_reload = 0; | |
1289 | lra_reg_info[i].restore_regno = -1; | |
1290 | lra_reg_info[i].val = get_new_reg_value (); | |
d70a81dd | 1291 | lra_reg_info[i].offset = 0; |
55a2c322 VM |
1292 | lra_reg_info[i].copies = NULL; |
1293 | } | |
1294 | ||
1295 | /* Initialize common reg info and copies. */ | |
1296 | static void | |
1297 | init_reg_info (void) | |
1298 | { | |
1299 | int i; | |
1300 | ||
1301 | last_reg_value = 0; | |
1302 | reg_info_size = max_reg_num () * 3 / 2 + 1; | |
1303 | lra_reg_info = XNEWVEC (struct lra_reg, reg_info_size); | |
1304 | for (i = 0; i < reg_info_size; i++) | |
1305 | initialize_lra_reg_info_element (i); | |
ff569744 | 1306 | copy_vec.truncate (0); |
55a2c322 VM |
1307 | } |
1308 | ||
1309 | ||
1310 | /* Finish common reg info and copies. */ | |
1311 | static void | |
1312 | finish_reg_info (void) | |
1313 | { | |
1314 | int i; | |
1315 | ||
1316 | for (i = 0; i < reg_info_size; i++) | |
1317 | bitmap_clear (&lra_reg_info[i].insn_bitmap); | |
1318 | free (lra_reg_info); | |
1319 | reg_info_size = 0; | |
55a2c322 VM |
1320 | } |
1321 | ||
1322 | /* Expand common reg info if it is necessary. */ | |
1323 | static void | |
1324 | expand_reg_info (void) | |
1325 | { | |
1326 | int i, old = reg_info_size; | |
1327 | ||
1328 | if (reg_info_size > max_reg_num ()) | |
1329 | return; | |
1330 | reg_info_size = max_reg_num () * 3 / 2 + 1; | |
1331 | lra_reg_info = XRESIZEVEC (struct lra_reg, lra_reg_info, reg_info_size); | |
1332 | for (i = old; i < reg_info_size; i++) | |
1333 | initialize_lra_reg_info_element (i); | |
1334 | } | |
1335 | ||
1336 | /* Free all copies. */ | |
1337 | void | |
1338 | lra_free_copies (void) | |
1339 | { | |
1340 | lra_copy_t cp; | |
1341 | ||
9771b263 | 1342 | while (copy_vec.length () != 0) |
55a2c322 | 1343 | { |
9771b263 | 1344 | cp = copy_vec.pop (); |
55a2c322 | 1345 | lra_reg_info[cp->regno1].copies = lra_reg_info[cp->regno2].copies = NULL; |
fb0b2914 | 1346 | lra_copy_pool.remove (cp); |
55a2c322 VM |
1347 | } |
1348 | } | |
1349 | ||
1350 | /* Create copy of two pseudos REGNO1 and REGNO2. The copy execution | |
1351 | frequency is FREQ. */ | |
1352 | void | |
1353 | lra_create_copy (int regno1, int regno2, int freq) | |
1354 | { | |
1355 | bool regno1_dest_p; | |
1356 | lra_copy_t cp; | |
1357 | ||
1358 | lra_assert (regno1 != regno2); | |
1359 | regno1_dest_p = true; | |
1360 | if (regno1 > regno2) | |
1361 | { | |
6b4db501 | 1362 | std::swap (regno1, regno2); |
55a2c322 | 1363 | regno1_dest_p = false; |
55a2c322 | 1364 | } |
fb0b2914 | 1365 | cp = lra_copy_pool.allocate (); |
9771b263 | 1366 | copy_vec.safe_push (cp); |
55a2c322 VM |
1367 | cp->regno1_dest_p = regno1_dest_p; |
1368 | cp->freq = freq; | |
1369 | cp->regno1 = regno1; | |
1370 | cp->regno2 = regno2; | |
1371 | cp->regno1_next = lra_reg_info[regno1].copies; | |
1372 | lra_reg_info[regno1].copies = cp; | |
1373 | cp->regno2_next = lra_reg_info[regno2].copies; | |
1374 | lra_reg_info[regno2].copies = cp; | |
1375 | if (lra_dump_file != NULL) | |
1376 | fprintf (lra_dump_file, " Creating copy r%d%sr%d@%d\n", | |
1377 | regno1, regno1_dest_p ? "<-" : "->", regno2, freq); | |
1378 | } | |
1379 | ||
1380 | /* Return N-th (0, 1, ...) copy. If there is no copy, return | |
1381 | NULL. */ | |
1382 | lra_copy_t | |
1383 | lra_get_copy (int n) | |
1384 | { | |
9771b263 | 1385 | if (n >= (int) copy_vec.length ()) |
55a2c322 | 1386 | return NULL; |
9771b263 | 1387 | return copy_vec[n]; |
55a2c322 VM |
1388 | } |
1389 | ||
1390 | \f | |
1391 | ||
1392 | /* This page contains code dealing with info about registers in | |
1393 | insns. */ | |
1394 | ||
1395 | /* Process X of insn UID recursively and add info (operand type is | |
1396 | given by TYPE, flag of that it is early clobber is EARLY_CLOBBER) | |
1397 | about registers in X to the insn DATA. */ | |
1398 | static void | |
1399 | add_regs_to_insn_regno_info (lra_insn_recog_data_t data, rtx x, int uid, | |
1400 | enum op_type type, bool early_clobber) | |
1401 | { | |
1402 | int i, j, regno; | |
1403 | bool subreg_p; | |
ef4bddc2 | 1404 | machine_mode mode; |
55a2c322 VM |
1405 | const char *fmt; |
1406 | enum rtx_code code; | |
1407 | struct lra_insn_reg *curr; | |
1408 | ||
1409 | code = GET_CODE (x); | |
1410 | mode = GET_MODE (x); | |
1411 | subreg_p = false; | |
1412 | if (GET_CODE (x) == SUBREG) | |
1413 | { | |
1414 | x = SUBREG_REG (x); | |
1415 | code = GET_CODE (x); | |
1416 | if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))) | |
1417 | { | |
1418 | mode = GET_MODE (x); | |
1419 | if (GET_MODE_SIZE (mode) > REGMODE_NATURAL_SIZE (mode)) | |
1420 | subreg_p = true; | |
1421 | } | |
1422 | } | |
1423 | if (REG_P (x)) | |
1424 | { | |
1425 | regno = REGNO (x); | |
d9cf932c VM |
1426 | /* Process all regs even unallocatable ones as we need info about |
1427 | all regs for rematerialization pass. */ | |
55a2c322 VM |
1428 | expand_reg_info (); |
1429 | if (bitmap_set_bit (&lra_reg_info[regno].insn_bitmap, uid)) | |
1430 | { | |
c34c46dd | 1431 | data->regs = new_insn_reg (data->insn, regno, type, mode, subreg_p, |
55a2c322 VM |
1432 | early_clobber, data->regs); |
1433 | return; | |
1434 | } | |
1435 | else | |
1436 | { | |
1437 | for (curr = data->regs; curr != NULL; curr = curr->next) | |
1438 | if (curr->regno == regno) | |
1439 | { | |
1440 | if (curr->subreg_p != subreg_p || curr->biggest_mode != mode) | |
1441 | /* The info can not be integrated into the found | |
1442 | structure. */ | |
c34c46dd RS |
1443 | data->regs = new_insn_reg (data->insn, regno, type, mode, |
1444 | subreg_p, early_clobber, | |
1445 | data->regs); | |
55a2c322 VM |
1446 | else |
1447 | { | |
1448 | if (curr->type != type) | |
1449 | curr->type = OP_INOUT; | |
1450 | if (curr->early_clobber != early_clobber) | |
1451 | curr->early_clobber = true; | |
1452 | } | |
1453 | return; | |
1454 | } | |
1455 | gcc_unreachable (); | |
1456 | } | |
1457 | } | |
1458 | ||
1459 | switch (code) | |
1460 | { | |
1461 | case SET: | |
1462 | add_regs_to_insn_regno_info (data, SET_DEST (x), uid, OP_OUT, false); | |
1463 | add_regs_to_insn_regno_info (data, SET_SRC (x), uid, OP_IN, false); | |
1464 | break; | |
1465 | case CLOBBER: | |
1466 | /* We treat clobber of non-operand hard registers as early | |
f4eafc30 | 1467 | clobber (the behavior is expected from asm). */ |
55a2c322 VM |
1468 | add_regs_to_insn_regno_info (data, XEXP (x, 0), uid, OP_OUT, true); |
1469 | break; | |
1470 | case PRE_INC: case PRE_DEC: case POST_INC: case POST_DEC: | |
1471 | add_regs_to_insn_regno_info (data, XEXP (x, 0), uid, OP_INOUT, false); | |
1472 | break; | |
1473 | case PRE_MODIFY: case POST_MODIFY: | |
1474 | add_regs_to_insn_regno_info (data, XEXP (x, 0), uid, OP_INOUT, false); | |
1475 | add_regs_to_insn_regno_info (data, XEXP (x, 1), uid, OP_IN, false); | |
1476 | break; | |
1477 | default: | |
1478 | if ((code != PARALLEL && code != EXPR_LIST) || type != OP_OUT) | |
1479 | /* Some targets place small structures in registers for return | |
1480 | values of functions, and those registers are wrapped in | |
1481 | PARALLEL that we may see as the destination of a SET. Here | |
1482 | is an example: | |
1483 | ||
1484 | (call_insn 13 12 14 2 (set (parallel:BLK [ | |
1485 | (expr_list:REG_DEP_TRUE (reg:DI 0 ax) | |
1486 | (const_int 0 [0])) | |
1487 | (expr_list:REG_DEP_TRUE (reg:DI 1 dx) | |
1488 | (const_int 8 [0x8])) | |
1489 | ]) | |
1490 | (call (mem:QI (symbol_ref:DI (... */ | |
1491 | type = OP_IN; | |
1492 | fmt = GET_RTX_FORMAT (code); | |
1493 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1494 | { | |
1495 | if (fmt[i] == 'e') | |
1496 | add_regs_to_insn_regno_info (data, XEXP (x, i), uid, type, false); | |
1497 | else if (fmt[i] == 'E') | |
1498 | { | |
1499 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
1500 | add_regs_to_insn_regno_info (data, XVECEXP (x, i, j), uid, | |
1501 | type, false); | |
1502 | } | |
1503 | } | |
1504 | } | |
1505 | } | |
1506 | ||
1507 | /* Return execution frequency of INSN. */ | |
1508 | static int | |
cfa434f6 | 1509 | get_insn_freq (rtx_insn *insn) |
55a2c322 | 1510 | { |
39718607 | 1511 | basic_block bb = BLOCK_FOR_INSN (insn); |
55a2c322 | 1512 | |
39718607 SB |
1513 | gcc_checking_assert (bb != NULL); |
1514 | return REG_FREQ_FROM_BB (bb); | |
55a2c322 VM |
1515 | } |
1516 | ||
1517 | /* Invalidate all reg info of INSN with DATA and execution frequency | |
1518 | FREQ. Update common info about the invalidated registers. */ | |
1519 | static void | |
cfa434f6 | 1520 | invalidate_insn_data_regno_info (lra_insn_recog_data_t data, rtx_insn *insn, |
55a2c322 VM |
1521 | int freq) |
1522 | { | |
1523 | int uid; | |
1524 | bool debug_p; | |
1525 | unsigned int i; | |
1526 | struct lra_insn_reg *ir, *next_ir; | |
1527 | ||
1528 | uid = INSN_UID (insn); | |
1529 | debug_p = DEBUG_INSN_P (insn); | |
1530 | for (ir = data->regs; ir != NULL; ir = next_ir) | |
1531 | { | |
1532 | i = ir->regno; | |
1533 | next_ir = ir->next; | |
fb0b2914 | 1534 | lra_insn_reg_pool.remove (ir); |
55a2c322 VM |
1535 | bitmap_clear_bit (&lra_reg_info[i].insn_bitmap, uid); |
1536 | if (i >= FIRST_PSEUDO_REGISTER && ! debug_p) | |
1537 | { | |
1538 | lra_reg_info[i].nrefs--; | |
1539 | lra_reg_info[i].freq -= freq; | |
1540 | lra_assert (lra_reg_info[i].nrefs >= 0 && lra_reg_info[i].freq >= 0); | |
1541 | } | |
1542 | } | |
1543 | data->regs = NULL; | |
1544 | } | |
1545 | ||
1546 | /* Invalidate all reg info of INSN. Update common info about the | |
1547 | invalidated registers. */ | |
1548 | void | |
cfa434f6 | 1549 | lra_invalidate_insn_regno_info (rtx_insn *insn) |
55a2c322 VM |
1550 | { |
1551 | invalidate_insn_data_regno_info (lra_get_insn_recog_data (insn), insn, | |
1552 | get_insn_freq (insn)); | |
1553 | } | |
1554 | ||
1555 | /* Update common reg info from reg info of insn given by its DATA and | |
1556 | execution frequency FREQ. */ | |
1557 | static void | |
1558 | setup_insn_reg_info (lra_insn_recog_data_t data, int freq) | |
1559 | { | |
1560 | unsigned int i; | |
1561 | struct lra_insn_reg *ir; | |
1562 | ||
1563 | for (ir = data->regs; ir != NULL; ir = ir->next) | |
1564 | if ((i = ir->regno) >= FIRST_PSEUDO_REGISTER) | |
1565 | { | |
1566 | lra_reg_info[i].nrefs++; | |
1567 | lra_reg_info[i].freq += freq; | |
1568 | } | |
1569 | } | |
1570 | ||
1571 | /* Set up insn reg info of INSN. Update common reg info from reg info | |
1572 | of INSN. */ | |
1573 | void | |
cfa434f6 | 1574 | lra_update_insn_regno_info (rtx_insn *insn) |
55a2c322 VM |
1575 | { |
1576 | int i, uid, freq; | |
1577 | lra_insn_recog_data_t data; | |
1578 | struct lra_static_insn_data *static_data; | |
1579 | enum rtx_code code; | |
05f23918 VM |
1580 | rtx link; |
1581 | ||
55a2c322 VM |
1582 | if (! INSN_P (insn)) |
1583 | return; | |
1584 | data = lra_get_insn_recog_data (insn); | |
1585 | static_data = data->insn_static_data; | |
1586 | freq = get_insn_freq (insn); | |
1587 | invalidate_insn_data_regno_info (data, insn, freq); | |
1588 | uid = INSN_UID (insn); | |
1589 | for (i = static_data->n_operands - 1; i >= 0; i--) | |
1590 | add_regs_to_insn_regno_info (data, *data->operand_loc[i], uid, | |
1591 | static_data->operand[i].type, | |
1592 | static_data->operand[i].early_clobber); | |
1593 | if ((code = GET_CODE (PATTERN (insn))) == CLOBBER || code == USE) | |
1594 | add_regs_to_insn_regno_info (data, XEXP (PATTERN (insn), 0), uid, | |
1595 | code == USE ? OP_IN : OP_OUT, false); | |
05f23918 VM |
1596 | if (CALL_P (insn)) |
1597 | /* On some targets call insns can refer to pseudos in memory in | |
1598 | CALL_INSN_FUNCTION_USAGE list. Process them in order to | |
1599 | consider their occurrences in calls for different | |
1600 | transformations (e.g. inheritance) with given pseudos. */ | |
1601 | for (link = CALL_INSN_FUNCTION_USAGE (insn); | |
1602 | link != NULL_RTX; | |
1603 | link = XEXP (link, 1)) | |
1604 | if (((code = GET_CODE (XEXP (link, 0))) == USE || code == CLOBBER) | |
1605 | && MEM_P (XEXP (XEXP (link, 0), 0))) | |
1606 | add_regs_to_insn_regno_info (data, XEXP (XEXP (link, 0), 0), uid, | |
1607 | code == USE ? OP_IN : OP_OUT, false); | |
55a2c322 VM |
1608 | if (NONDEBUG_INSN_P (insn)) |
1609 | setup_insn_reg_info (data, freq); | |
1610 | } | |
1611 | ||
1612 | /* Return reg info of insn given by it UID. */ | |
1613 | struct lra_insn_reg * | |
1614 | lra_get_insn_regs (int uid) | |
1615 | { | |
1616 | lra_insn_recog_data_t data; | |
1617 | ||
1618 | data = get_insn_recog_data_by_uid (uid); | |
1619 | return data->regs; | |
1620 | } | |
1621 | ||
1622 | \f | |
1623 | ||
1624 | /* This page contains code dealing with stack of the insns which | |
1625 | should be processed by the next constraint pass. */ | |
1626 | ||
1627 | /* Bitmap used to put an insn on the stack only in one exemplar. */ | |
1628 | static sbitmap lra_constraint_insn_stack_bitmap; | |
1629 | ||
1630 | /* The stack itself. */ | |
cfa434f6 | 1631 | vec<rtx_insn *> lra_constraint_insn_stack; |
55a2c322 VM |
1632 | |
1633 | /* Put INSN on the stack. If ALWAYS_UPDATE is true, always update the reg | |
1634 | info for INSN, otherwise only update it if INSN is not already on the | |
1635 | stack. */ | |
1636 | static inline void | |
cfa434f6 | 1637 | lra_push_insn_1 (rtx_insn *insn, bool always_update) |
55a2c322 VM |
1638 | { |
1639 | unsigned int uid = INSN_UID (insn); | |
1640 | if (always_update) | |
1641 | lra_update_insn_regno_info (insn); | |
1642 | if (uid >= SBITMAP_SIZE (lra_constraint_insn_stack_bitmap)) | |
1643 | lra_constraint_insn_stack_bitmap = | |
1644 | sbitmap_resize (lra_constraint_insn_stack_bitmap, 3 * uid / 2, 0); | |
d7c028c0 | 1645 | if (bitmap_bit_p (lra_constraint_insn_stack_bitmap, uid)) |
55a2c322 | 1646 | return; |
d7c028c0 | 1647 | bitmap_set_bit (lra_constraint_insn_stack_bitmap, uid); |
55a2c322 VM |
1648 | if (! always_update) |
1649 | lra_update_insn_regno_info (insn); | |
9771b263 | 1650 | lra_constraint_insn_stack.safe_push (insn); |
55a2c322 VM |
1651 | } |
1652 | ||
1653 | /* Put INSN on the stack. */ | |
1654 | void | |
cfa434f6 | 1655 | lra_push_insn (rtx_insn *insn) |
55a2c322 VM |
1656 | { |
1657 | lra_push_insn_1 (insn, false); | |
1658 | } | |
1659 | ||
1660 | /* Put INSN on the stack and update its reg info. */ | |
1661 | void | |
cfa434f6 | 1662 | lra_push_insn_and_update_insn_regno_info (rtx_insn *insn) |
55a2c322 VM |
1663 | { |
1664 | lra_push_insn_1 (insn, true); | |
1665 | } | |
1666 | ||
1667 | /* Put insn with UID on the stack. */ | |
1668 | void | |
1669 | lra_push_insn_by_uid (unsigned int uid) | |
1670 | { | |
1671 | lra_push_insn (lra_insn_recog_data[uid]->insn); | |
1672 | } | |
1673 | ||
1674 | /* Take the last-inserted insns off the stack and return it. */ | |
cfa434f6 | 1675 | rtx_insn * |
55a2c322 VM |
1676 | lra_pop_insn (void) |
1677 | { | |
cfa434f6 | 1678 | rtx_insn *insn = lra_constraint_insn_stack.pop (); |
d7c028c0 | 1679 | bitmap_clear_bit (lra_constraint_insn_stack_bitmap, INSN_UID (insn)); |
55a2c322 VM |
1680 | return insn; |
1681 | } | |
1682 | ||
1683 | /* Return the current size of the insn stack. */ | |
1684 | unsigned int | |
1685 | lra_insn_stack_length (void) | |
1686 | { | |
9771b263 | 1687 | return lra_constraint_insn_stack.length (); |
55a2c322 VM |
1688 | } |
1689 | ||
1690 | /* Push insns FROM to TO (excluding it) going in reverse order. */ | |
1691 | static void | |
cfa434f6 | 1692 | push_insns (rtx_insn *from, rtx_insn *to) |
55a2c322 | 1693 | { |
cfa434f6 | 1694 | rtx_insn *insn; |
55a2c322 VM |
1695 | |
1696 | if (from == NULL_RTX) | |
1697 | return; | |
1698 | for (insn = from; insn != to; insn = PREV_INSN (insn)) | |
1699 | if (INSN_P (insn)) | |
1700 | lra_push_insn (insn); | |
1701 | } | |
1702 | ||
8d49e7ef VM |
1703 | /* Set up sp offset for insn in range [FROM, LAST]. The offset is |
1704 | taken from the next BB insn after LAST or zero if there in such | |
1705 | insn. */ | |
1706 | static void | |
cfa434f6 | 1707 | setup_sp_offset (rtx_insn *from, rtx_insn *last) |
8d49e7ef | 1708 | { |
cfa434f6 | 1709 | rtx_insn *before = next_nonnote_insn_bb (last); |
8d49e7ef VM |
1710 | HOST_WIDE_INT offset = (before == NULL_RTX || ! INSN_P (before) |
1711 | ? 0 : lra_get_insn_recog_data (before)->sp_offset); | |
1712 | ||
cfa434f6 | 1713 | for (rtx_insn *insn = from; insn != NEXT_INSN (last); insn = NEXT_INSN (insn)) |
8d49e7ef VM |
1714 | lra_get_insn_recog_data (insn)->sp_offset = offset; |
1715 | } | |
1716 | ||
55a2c322 VM |
1717 | /* Emit insns BEFORE before INSN and insns AFTER after INSN. Put the |
1718 | insns onto the stack. Print about emitting the insns with | |
1719 | TITLE. */ | |
1720 | void | |
cfa434f6 DM |
1721 | lra_process_new_insns (rtx_insn *insn, rtx_insn *before, rtx_insn *after, |
1722 | const char *title) | |
55a2c322 | 1723 | { |
cfa434f6 | 1724 | rtx_insn *last; |
55a2c322 | 1725 | |
8d49e7ef VM |
1726 | if (before == NULL_RTX && after == NULL_RTX) |
1727 | return; | |
1728 | if (lra_dump_file != NULL) | |
55a2c322 | 1729 | { |
cfbeaedf | 1730 | dump_insn_slim (lra_dump_file, insn); |
55a2c322 VM |
1731 | if (before != NULL_RTX) |
1732 | { | |
1733 | fprintf (lra_dump_file," %s before:\n", title); | |
dc01c3d1 | 1734 | dump_rtl_slim (lra_dump_file, before, NULL, -1, 0); |
55a2c322 VM |
1735 | } |
1736 | if (after != NULL_RTX) | |
1737 | { | |
1738 | fprintf (lra_dump_file, " %s after:\n", title); | |
dc01c3d1 | 1739 | dump_rtl_slim (lra_dump_file, after, NULL, -1, 0); |
55a2c322 VM |
1740 | } |
1741 | fprintf (lra_dump_file, "\n"); | |
1742 | } | |
1743 | if (before != NULL_RTX) | |
1744 | { | |
1745 | emit_insn_before (before, insn); | |
1746 | push_insns (PREV_INSN (insn), PREV_INSN (before)); | |
8d49e7ef | 1747 | setup_sp_offset (before, PREV_INSN (insn)); |
55a2c322 VM |
1748 | } |
1749 | if (after != NULL_RTX) | |
1750 | { | |
1751 | for (last = after; NEXT_INSN (last) != NULL_RTX; last = NEXT_INSN (last)) | |
1752 | ; | |
1753 | emit_insn_after (after, insn); | |
1754 | push_insns (last, insn); | |
8d49e7ef | 1755 | setup_sp_offset (after, last); |
55a2c322 VM |
1756 | } |
1757 | } | |
1758 | ||
1759 | \f | |
1760 | ||
8160cd3e | 1761 | /* Replace all references to register OLD_REGNO in *LOC with pseudo |
ef87312e VM |
1762 | register NEW_REG. Try to simplify subreg of constant if SUBREG_P. |
1763 | Return true if any change was made. */ | |
8160cd3e | 1764 | bool |
ef87312e | 1765 | lra_substitute_pseudo (rtx *loc, int old_regno, rtx new_reg, bool subreg_p) |
8160cd3e VM |
1766 | { |
1767 | rtx x = *loc; | |
1768 | bool result = false; | |
1769 | enum rtx_code code; | |
1770 | const char *fmt; | |
1771 | int i, j; | |
1772 | ||
1773 | if (x == NULL_RTX) | |
1774 | return false; | |
1775 | ||
1776 | code = GET_CODE (x); | |
ef87312e | 1777 | if (code == SUBREG && subreg_p) |
8160cd3e | 1778 | { |
ef87312e VM |
1779 | rtx subst, inner = SUBREG_REG (x); |
1780 | /* Transform subreg of constant while we still have inner mode | |
1781 | of the subreg. The subreg internal should not be an insn | |
1782 | operand. */ | |
1783 | if (REG_P (inner) && (int) REGNO (inner) == old_regno | |
1784 | && CONSTANT_P (new_reg) | |
1785 | && (subst = simplify_subreg (GET_MODE (x), new_reg, GET_MODE (inner), | |
1786 | SUBREG_BYTE (x))) != NULL_RTX) | |
1787 | { | |
1788 | *loc = subst; | |
1789 | return true; | |
1790 | } | |
1791 | ||
1792 | } | |
1793 | else if (code == REG && (int) REGNO (x) == old_regno) | |
1794 | { | |
1795 | machine_mode mode = GET_MODE (x); | |
8160cd3e VM |
1796 | machine_mode inner_mode = GET_MODE (new_reg); |
1797 | ||
eef7b18c VM |
1798 | if (mode != inner_mode |
1799 | && ! (CONST_INT_P (new_reg) && SCALAR_INT_MODE_P (mode))) | |
8160cd3e VM |
1800 | { |
1801 | if (GET_MODE_SIZE (mode) >= GET_MODE_SIZE (inner_mode) | |
1802 | || ! SCALAR_INT_MODE_P (inner_mode)) | |
1803 | new_reg = gen_rtx_SUBREG (mode, new_reg, 0); | |
1804 | else | |
1805 | new_reg = gen_lowpart_SUBREG (mode, new_reg); | |
1806 | } | |
1807 | *loc = new_reg; | |
1808 | return true; | |
1809 | } | |
1810 | ||
1811 | /* Scan all the operand sub-expressions. */ | |
1812 | fmt = GET_RTX_FORMAT (code); | |
1813 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1814 | { | |
1815 | if (fmt[i] == 'e') | |
1816 | { | |
ef87312e VM |
1817 | if (lra_substitute_pseudo (&XEXP (x, i), old_regno, |
1818 | new_reg, subreg_p)) | |
8160cd3e VM |
1819 | result = true; |
1820 | } | |
1821 | else if (fmt[i] == 'E') | |
1822 | { | |
1823 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
ef87312e VM |
1824 | if (lra_substitute_pseudo (&XVECEXP (x, i, j), old_regno, |
1825 | new_reg, subreg_p)) | |
8160cd3e VM |
1826 | result = true; |
1827 | } | |
1828 | } | |
1829 | return result; | |
1830 | } | |
1831 | ||
ef87312e VM |
1832 | /* Call lra_substitute_pseudo within an insn. Try to simplify subreg |
1833 | of constant if SUBREG_P. This won't update the insn ptr, just the | |
1834 | contents of the insn. */ | |
8160cd3e | 1835 | bool |
ef87312e VM |
1836 | lra_substitute_pseudo_within_insn (rtx_insn *insn, int old_regno, |
1837 | rtx new_reg, bool subreg_p) | |
8160cd3e VM |
1838 | { |
1839 | rtx loc = insn; | |
ef87312e | 1840 | return lra_substitute_pseudo (&loc, old_regno, new_reg, subreg_p); |
8160cd3e VM |
1841 | } |
1842 | ||
1843 | \f | |
1844 | ||
55a2c322 VM |
1845 | /* This page contains code dealing with scratches (changing them onto |
1846 | pseudos and restoring them from the pseudos). | |
1847 | ||
1848 | We change scratches into pseudos at the beginning of LRA to | |
1849 | simplify dealing with them (conflicts, hard register assignments). | |
1850 | ||
1851 | If the pseudo denoting scratch was spilled it means that we do need | |
1852 | a hard register for it. Such pseudos are transformed back to | |
1853 | scratches at the end of LRA. */ | |
1854 | ||
1855 | /* Description of location of a former scratch operand. */ | |
926cd61f | 1856 | struct sloc |
55a2c322 | 1857 | { |
cfa434f6 | 1858 | rtx_insn *insn; /* Insn where the scratch was. */ |
55a2c322 VM |
1859 | int nop; /* Number of the operand which was a scratch. */ |
1860 | }; | |
1861 | ||
926cd61f | 1862 | typedef struct sloc *sloc_t; |
55a2c322 | 1863 | |
55a2c322 | 1864 | /* Locations of the former scratches. */ |
9771b263 | 1865 | static vec<sloc_t> scratches; |
55a2c322 VM |
1866 | |
1867 | /* Bitmap of scratch regnos. */ | |
1868 | static bitmap_head scratch_bitmap; | |
1869 | ||
1870 | /* Bitmap of scratch operands. */ | |
1871 | static bitmap_head scratch_operand_bitmap; | |
1872 | ||
1873 | /* Return true if pseudo REGNO is made of SCRATCH. */ | |
1874 | bool | |
1875 | lra_former_scratch_p (int regno) | |
1876 | { | |
1877 | return bitmap_bit_p (&scratch_bitmap, regno); | |
1878 | } | |
1879 | ||
1880 | /* Return true if the operand NOP of INSN is a former scratch. */ | |
1881 | bool | |
cfa434f6 | 1882 | lra_former_scratch_operand_p (rtx_insn *insn, int nop) |
55a2c322 VM |
1883 | { |
1884 | return bitmap_bit_p (&scratch_operand_bitmap, | |
1885 | INSN_UID (insn) * MAX_RECOG_OPERANDS + nop) != 0; | |
1886 | } | |
1887 | ||
892927b7 VM |
1888 | /* Register operand NOP in INSN as a former scratch. It will be |
1889 | changed to scratch back, if it is necessary, at the LRA end. */ | |
1890 | void | |
1891 | lra_register_new_scratch_op (rtx_insn *insn, int nop) | |
1892 | { | |
1893 | lra_insn_recog_data_t id = lra_get_insn_recog_data (insn); | |
1894 | rtx op = *id->operand_loc[nop]; | |
1895 | sloc_t loc = XNEW (struct sloc); | |
1896 | lra_assert (REG_P (op)); | |
1897 | loc->insn = insn; | |
1898 | loc->nop = nop; | |
1899 | scratches.safe_push (loc); | |
1900 | bitmap_set_bit (&scratch_bitmap, REGNO (op)); | |
1901 | bitmap_set_bit (&scratch_operand_bitmap, | |
1902 | INSN_UID (insn) * MAX_RECOG_OPERANDS + nop); | |
1903 | add_reg_note (insn, REG_UNUSED, op); | |
1904 | } | |
1905 | ||
55a2c322 VM |
1906 | /* Change scratches onto pseudos and save their location. */ |
1907 | static void | |
1908 | remove_scratches (void) | |
1909 | { | |
1910 | int i; | |
1911 | bool insn_changed_p; | |
1912 | basic_block bb; | |
cfa434f6 DM |
1913 | rtx_insn *insn; |
1914 | rtx reg; | |
55a2c322 VM |
1915 | lra_insn_recog_data_t id; |
1916 | struct lra_static_insn_data *static_id; | |
1917 | ||
9771b263 | 1918 | scratches.create (get_max_uid ()); |
55a2c322 VM |
1919 | bitmap_initialize (&scratch_bitmap, ®_obstack); |
1920 | bitmap_initialize (&scratch_operand_bitmap, ®_obstack); | |
11cd3bed | 1921 | FOR_EACH_BB_FN (bb, cfun) |
55a2c322 VM |
1922 | FOR_BB_INSNS (bb, insn) |
1923 | if (INSN_P (insn)) | |
1924 | { | |
1925 | id = lra_get_insn_recog_data (insn); | |
1926 | static_id = id->insn_static_data; | |
1927 | insn_changed_p = false; | |
1928 | for (i = 0; i < static_id->n_operands; i++) | |
1929 | if (GET_CODE (*id->operand_loc[i]) == SCRATCH | |
1930 | && GET_MODE (*id->operand_loc[i]) != VOIDmode) | |
1931 | { | |
1932 | insn_changed_p = true; | |
1933 | *id->operand_loc[i] = reg | |
1934 | = lra_create_new_reg (static_id->operand[i].mode, | |
1935 | *id->operand_loc[i], ALL_REGS, NULL); | |
892927b7 | 1936 | lra_register_new_scratch_op (insn, i); |
55a2c322 VM |
1937 | if (lra_dump_file != NULL) |
1938 | fprintf (lra_dump_file, | |
1939 | "Removing SCRATCH in insn #%u (nop %d)\n", | |
1940 | INSN_UID (insn), i); | |
1941 | } | |
1942 | if (insn_changed_p) | |
1943 | /* Because we might use DF right after caller-saves sub-pass | |
1944 | we need to keep DF info up to date. */ | |
1945 | df_insn_rescan (insn); | |
1946 | } | |
1947 | } | |
1948 | ||
1949 | /* Changes pseudos created by function remove_scratches onto scratches. */ | |
1950 | static void | |
1951 | restore_scratches (void) | |
1952 | { | |
9771b263 DN |
1953 | int regno; |
1954 | unsigned i; | |
926cd61f | 1955 | sloc_t loc; |
cfa434f6 | 1956 | rtx_insn *last = NULL; |
55a2c322 VM |
1957 | lra_insn_recog_data_t id = NULL; |
1958 | ||
9771b263 | 1959 | for (i = 0; scratches.iterate (i, &loc); i++) |
55a2c322 VM |
1960 | { |
1961 | if (last != loc->insn) | |
1962 | { | |
1963 | last = loc->insn; | |
1964 | id = lra_get_insn_recog_data (last); | |
1965 | } | |
1966 | if (REG_P (*id->operand_loc[loc->nop]) | |
1967 | && ((regno = REGNO (*id->operand_loc[loc->nop])) | |
1968 | >= FIRST_PSEUDO_REGISTER) | |
1969 | && lra_get_regno_hard_regno (regno) < 0) | |
1970 | { | |
1971 | /* It should be only case when scratch register with chosen | |
1972 | constraint 'X' did not get memory or hard register. */ | |
1973 | lra_assert (lra_former_scratch_p (regno)); | |
1974 | *id->operand_loc[loc->nop] | |
1975 | = gen_rtx_SCRATCH (GET_MODE (*id->operand_loc[loc->nop])); | |
1976 | lra_update_dup (id, loc->nop); | |
1977 | if (lra_dump_file != NULL) | |
1978 | fprintf (lra_dump_file, "Restoring SCRATCH in insn #%u(nop %d)\n", | |
1979 | INSN_UID (loc->insn), loc->nop); | |
1980 | } | |
1981 | } | |
9771b263 | 1982 | for (i = 0; scratches.iterate (i, &loc); i++) |
55a2c322 | 1983 | free (loc); |
9771b263 | 1984 | scratches.release (); |
55a2c322 VM |
1985 | bitmap_clear (&scratch_bitmap); |
1986 | bitmap_clear (&scratch_operand_bitmap); | |
1987 | } | |
1988 | ||
1989 | \f | |
1990 | ||
55a2c322 VM |
1991 | /* Function checks RTL for correctness. If FINAL_P is true, it is |
1992 | done at the end of LRA and the check is more rigorous. */ | |
1993 | static void | |
1994 | check_rtl (bool final_p) | |
1995 | { | |
55a2c322 | 1996 | basic_block bb; |
cfa434f6 | 1997 | rtx_insn *insn; |
55a2c322 VM |
1998 | |
1999 | lra_assert (! final_p || reload_completed); | |
11cd3bed | 2000 | FOR_EACH_BB_FN (bb, cfun) |
55a2c322 VM |
2001 | FOR_BB_INSNS (bb, insn) |
2002 | if (NONDEBUG_INSN_P (insn) | |
2003 | && GET_CODE (PATTERN (insn)) != USE | |
2004 | && GET_CODE (PATTERN (insn)) != CLOBBER | |
55a2c322 VM |
2005 | && GET_CODE (PATTERN (insn)) != ASM_INPUT) |
2006 | { | |
2007 | if (final_p) | |
2008 | { | |
75d25a02 | 2009 | extract_constrain_insn (insn); |
55a2c322 VM |
2010 | continue; |
2011 | } | |
a26891f4 VM |
2012 | /* LRA code is based on assumption that all addresses can be |
2013 | correctly decomposed. LRA can generate reloads for | |
2014 | decomposable addresses. The decomposition code checks the | |
2015 | correctness of the addresses. So we don't need to check | |
49f5efa5 VM |
2016 | the addresses here. Don't call insn_invalid_p here, it can |
2017 | change the code at this stage. */ | |
2018 | if (recog_memoized (insn) < 0 && asm_noperands (PATTERN (insn)) < 0) | |
55a2c322 | 2019 | fatal_insn_not_found (insn); |
55a2c322 VM |
2020 | } |
2021 | } | |
55a2c322 VM |
2022 | |
2023 | /* Determine if the current function has an exception receiver block | |
2024 | that reaches the exit block via non-exceptional edges */ | |
2025 | static bool | |
2026 | has_nonexceptional_receiver (void) | |
2027 | { | |
2028 | edge e; | |
2029 | edge_iterator ei; | |
2030 | basic_block *tos, *worklist, bb; | |
2031 | ||
2032 | /* If we're not optimizing, then just err on the safe side. */ | |
2033 | if (!optimize) | |
2034 | return true; | |
f4eafc30 | 2035 | |
55a2c322 | 2036 | /* First determine which blocks can reach exit via normal paths. */ |
0cae8d31 | 2037 | tos = worklist = XNEWVEC (basic_block, n_basic_blocks_for_fn (cfun) + 1); |
55a2c322 | 2038 | |
11cd3bed | 2039 | FOR_EACH_BB_FN (bb, cfun) |
55a2c322 VM |
2040 | bb->flags &= ~BB_REACHABLE; |
2041 | ||
2042 | /* Place the exit block on our worklist. */ | |
fefa31b5 DM |
2043 | EXIT_BLOCK_PTR_FOR_FN (cfun)->flags |= BB_REACHABLE; |
2044 | *tos++ = EXIT_BLOCK_PTR_FOR_FN (cfun); | |
f4eafc30 | 2045 | |
55a2c322 VM |
2046 | /* Iterate: find everything reachable from what we've already seen. */ |
2047 | while (tos != worklist) | |
2048 | { | |
2049 | bb = *--tos; | |
2050 | ||
2051 | FOR_EACH_EDGE (e, ei, bb->preds) | |
2052 | if (e->flags & EDGE_ABNORMAL) | |
2053 | { | |
2054 | free (worklist); | |
2055 | return true; | |
2056 | } | |
2057 | else | |
2058 | { | |
2059 | basic_block src = e->src; | |
2060 | ||
2061 | if (!(src->flags & BB_REACHABLE)) | |
2062 | { | |
2063 | src->flags |= BB_REACHABLE; | |
2064 | *tos++ = src; | |
2065 | } | |
2066 | } | |
2067 | } | |
2068 | free (worklist); | |
2069 | /* No exceptional block reached exit unexceptionally. */ | |
2070 | return false; | |
2071 | } | |
2072 | ||
55a2c322 VM |
2073 | |
2074 | /* Process recursively X of INSN and add REG_INC notes if necessary. */ | |
2075 | static void | |
cfa434f6 | 2076 | add_auto_inc_notes (rtx_insn *insn, rtx x) |
55a2c322 VM |
2077 | { |
2078 | enum rtx_code code = GET_CODE (x); | |
2079 | const char *fmt; | |
2080 | int i, j; | |
2081 | ||
2082 | if (code == MEM && auto_inc_p (XEXP (x, 0))) | |
2083 | { | |
2084 | add_reg_note (insn, REG_INC, XEXP (XEXP (x, 0), 0)); | |
2085 | return; | |
2086 | } | |
2087 | ||
2088 | /* Scan all X sub-expressions. */ | |
2089 | fmt = GET_RTX_FORMAT (code); | |
2090 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2091 | { | |
2092 | if (fmt[i] == 'e') | |
2093 | add_auto_inc_notes (insn, XEXP (x, i)); | |
2094 | else if (fmt[i] == 'E') | |
2095 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
2096 | add_auto_inc_notes (insn, XVECEXP (x, i, j)); | |
2097 | } | |
2098 | } | |
2099 | ||
55a2c322 VM |
2100 | |
2101 | /* Remove all REG_DEAD and REG_UNUSED notes and regenerate REG_INC. | |
2102 | We change pseudos by hard registers without notification of DF and | |
2103 | that can make the notes obsolete. DF-infrastructure does not deal | |
2104 | with REG_INC notes -- so we should regenerate them here. */ | |
2105 | static void | |
2106 | update_inc_notes (void) | |
2107 | { | |
2108 | rtx *pnote; | |
2109 | basic_block bb; | |
cfa434f6 | 2110 | rtx_insn *insn; |
55a2c322 | 2111 | |
11cd3bed | 2112 | FOR_EACH_BB_FN (bb, cfun) |
55a2c322 VM |
2113 | FOR_BB_INSNS (bb, insn) |
2114 | if (NONDEBUG_INSN_P (insn)) | |
2115 | { | |
2116 | pnote = ®_NOTES (insn); | |
2117 | while (*pnote != 0) | |
2118 | { | |
20f114a3 YR |
2119 | if (REG_NOTE_KIND (*pnote) == REG_DEAD |
2120 | || REG_NOTE_KIND (*pnote) == REG_UNUSED | |
2121 | || REG_NOTE_KIND (*pnote) == REG_INC) | |
55a2c322 VM |
2122 | *pnote = XEXP (*pnote, 1); |
2123 | else | |
2124 | pnote = &XEXP (*pnote, 1); | |
2125 | } | |
760edf20 TS |
2126 | |
2127 | if (AUTO_INC_DEC) | |
2128 | add_auto_inc_notes (insn, PATTERN (insn)); | |
55a2c322 VM |
2129 | } |
2130 | } | |
2131 | ||
2132 | /* Set to 1 while in lra. */ | |
2133 | int lra_in_progress; | |
2134 | ||
f681cf95 VM |
2135 | /* Start of pseudo regnos before the LRA. */ |
2136 | int lra_new_regno_start; | |
2137 | ||
f4eafc30 | 2138 | /* Start of reload pseudo regnos before the new spill pass. */ |
55a2c322 VM |
2139 | int lra_constraint_new_regno_start; |
2140 | ||
8fd827b8 VM |
2141 | /* Avoid spilling pseudos with regno more than the following value if |
2142 | it is possible. */ | |
2143 | int lra_bad_spill_regno_start; | |
2144 | ||
f4eafc30 | 2145 | /* Inheritance pseudo regnos before the new spill pass. */ |
55a2c322 VM |
2146 | bitmap_head lra_inheritance_pseudos; |
2147 | ||
f4eafc30 | 2148 | /* Split regnos before the new spill pass. */ |
55a2c322 VM |
2149 | bitmap_head lra_split_regs; |
2150 | ||
2b778c9d VM |
2151 | /* Reload pseudo regnos before the new assignmnet pass which still can |
2152 | be spilled after the assinment pass as memory is also accepted in | |
2153 | insns for the reload pseudos. */ | |
55a2c322 VM |
2154 | bitmap_head lra_optional_reload_pseudos; |
2155 | ||
2b778c9d VM |
2156 | /* Pseudo regnos used for subreg reloads before the new assignment |
2157 | pass. Such pseudos still can be spilled after the assinment | |
2158 | pass. */ | |
2159 | bitmap_head lra_subreg_reload_pseudos; | |
2160 | ||
55a2c322 VM |
2161 | /* File used for output of LRA debug information. */ |
2162 | FILE *lra_dump_file; | |
2163 | ||
2164 | /* True if we should try spill into registers of different classes | |
2165 | instead of memory. */ | |
2166 | bool lra_reg_spill_p; | |
2167 | ||
2168 | /* Set up value LRA_REG_SPILL_P. */ | |
2169 | static void | |
2170 | setup_reg_spill_flag (void) | |
2171 | { | |
2172 | int cl, mode; | |
2173 | ||
2174 | if (targetm.spill_class != NULL) | |
2175 | for (cl = 0; cl < (int) LIM_REG_CLASSES; cl++) | |
2176 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
2177 | if (targetm.spill_class ((enum reg_class) cl, | |
ef4bddc2 | 2178 | (machine_mode) mode) != NO_REGS) |
55a2c322 VM |
2179 | { |
2180 | lra_reg_spill_p = true; | |
2181 | return; | |
2182 | } | |
2183 | lra_reg_spill_p = false; | |
2184 | } | |
2185 | ||
2186 | /* True if the current function is too big to use regular algorithms | |
2187 | in LRA. In other words, we should use simpler and faster algorithms | |
2188 | in LRA. It also means we should not worry about generation code | |
2189 | for caller saves. The value is set up in IRA. */ | |
2190 | bool lra_simple_p; | |
2191 | ||
2192 | /* Major LRA entry function. F is a file should be used to dump LRA | |
2193 | debug info. */ | |
2194 | void | |
2195 | lra (FILE *f) | |
2196 | { | |
2197 | int i; | |
2198 | bool live_p, scratch_p, inserted_p; | |
2199 | ||
2200 | lra_dump_file = f; | |
2201 | ||
2202 | timevar_push (TV_LRA); | |
2203 | ||
2c62cbaa VM |
2204 | /* Make sure that the last insn is a note. Some subsequent passes |
2205 | need it. */ | |
2206 | emit_note (NOTE_INSN_DELETED); | |
2207 | ||
b28ece32 VM |
2208 | COPY_HARD_REG_SET (lra_no_alloc_regs, ira_no_alloc_regs); |
2209 | ||
afa22e29 VM |
2210 | init_reg_info (); |
2211 | expand_reg_info (); | |
2212 | ||
55a2c322 VM |
2213 | init_insn_recog_data (); |
2214 | ||
49f5efa5 | 2215 | /* Some quick check on RTL generated by previous passes. */ |
b2b29377 MM |
2216 | if (flag_checking) |
2217 | check_rtl (false); | |
55a2c322 | 2218 | |
49f5efa5 VM |
2219 | lra_in_progress = 1; |
2220 | ||
f54437d5 VM |
2221 | lra_live_range_iter = lra_coalesce_iter = lra_constraint_iter = 0; |
2222 | lra_assignment_iter = lra_assignment_iter_after_spill = 0; | |
55a2c322 | 2223 | lra_inheritance_iter = lra_undo_inheritance_iter = 0; |
94446928 | 2224 | lra_rematerialization_iter = 0; |
55a2c322 VM |
2225 | |
2226 | setup_reg_spill_flag (); | |
2227 | ||
55a2c322 VM |
2228 | /* Function remove_scratches can creates new pseudos for clobbers -- |
2229 | so set up lra_constraint_new_regno_start before its call to | |
2230 | permit changing reg classes for pseudos created by this | |
2231 | simplification. */ | |
f681cf95 | 2232 | lra_constraint_new_regno_start = lra_new_regno_start = max_reg_num (); |
8fd827b8 | 2233 | lra_bad_spill_regno_start = INT_MAX; |
55a2c322 VM |
2234 | remove_scratches (); |
2235 | scratch_p = lra_constraint_new_regno_start != max_reg_num (); | |
2236 | ||
2237 | /* A function that has a non-local label that can reach the exit | |
2238 | block via non-exceptional paths must save all call-saved | |
2239 | registers. */ | |
2240 | if (cfun->has_nonlocal_label && has_nonexceptional_receiver ()) | |
2241 | crtl->saves_all_registers = 1; | |
2242 | ||
2243 | if (crtl->saves_all_registers) | |
2244 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
2245 | if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i)) | |
2246 | df_set_regs_ever_live (i, true); | |
2247 | ||
2248 | /* We don't DF from now and avoid its using because it is to | |
2249 | expensive when a lot of RTL changes are made. */ | |
2250 | df_set_flags (DF_NO_INSN_RESCAN); | |
9771b263 | 2251 | lra_constraint_insn_stack.create (get_max_uid ()); |
55a2c322 | 2252 | lra_constraint_insn_stack_bitmap = sbitmap_alloc (get_max_uid ()); |
f61e445a | 2253 | bitmap_clear (lra_constraint_insn_stack_bitmap); |
55a2c322 VM |
2254 | lra_live_ranges_init (); |
2255 | lra_constraints_init (); | |
2256 | lra_curr_reload_num = 0; | |
cfa434f6 | 2257 | push_insns (get_last_insn (), NULL); |
55a2c322 | 2258 | /* It is needed for the 1st coalescing. */ |
55a2c322 VM |
2259 | bitmap_initialize (&lra_inheritance_pseudos, ®_obstack); |
2260 | bitmap_initialize (&lra_split_regs, ®_obstack); | |
2261 | bitmap_initialize (&lra_optional_reload_pseudos, ®_obstack); | |
2b778c9d | 2262 | bitmap_initialize (&lra_subreg_reload_pseudos, ®_obstack); |
55a2c322 | 2263 | live_p = false; |
2c62cbaa VM |
2264 | if (get_frame_size () != 0 && crtl->stack_alignment_needed) |
2265 | /* If we have a stack frame, we must align it now. The stack size | |
2266 | may be a part of the offset computation for register | |
2267 | elimination. */ | |
2268 | assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed); | |
4c2b2d79 | 2269 | lra_init_equiv (); |
55a2c322 VM |
2270 | for (;;) |
2271 | { | |
2272 | for (;;) | |
2273 | { | |
55a2c322 VM |
2274 | /* We should try to assign hard registers to scratches even |
2275 | if there were no RTL transformations in | |
2276 | lra_constraints. */ | |
2277 | if (! lra_constraints (lra_constraint_iter == 0) | |
2278 | && (lra_constraint_iter > 1 | |
2279 | || (! scratch_p && ! caller_save_needed))) | |
2280 | break; | |
2281 | /* Constraint transformations may result in that eliminable | |
2282 | hard regs become uneliminable and pseudos which use them | |
2283 | should be spilled. It is better to do it before pseudo | |
2284 | assignments. | |
2285 | ||
2286 | For example, rs6000 can make | |
2287 | RS6000_PIC_OFFSET_TABLE_REGNUM uneliminable if we started | |
2288 | to use a constant pool. */ | |
8d49e7ef | 2289 | lra_eliminate (false, false); |
55a2c322 VM |
2290 | /* Do inheritance only for regular algorithms. */ |
2291 | if (! lra_simple_p) | |
10e1bdb2 | 2292 | { |
1e288103 | 2293 | if (flag_ipa_ra) |
10e1bdb2 TV |
2294 | { |
2295 | if (live_p) | |
2296 | lra_clear_live_ranges (); | |
2297 | /* As a side-effect of lra_create_live_ranges, we calculate | |
2298 | actual_call_used_reg_set, which is needed during | |
2299 | lra_inheritance. */ | |
4ab74a01 | 2300 | lra_create_live_ranges (true, true); |
8f047f6c | 2301 | live_p = true; |
10e1bdb2 TV |
2302 | } |
2303 | lra_inheritance (); | |
2304 | } | |
4ccf8f43 JJ |
2305 | if (live_p) |
2306 | lra_clear_live_ranges (); | |
4ab74a01 VM |
2307 | /* We need live ranges for lra_assign -- so build them. But |
2308 | don't remove dead insns or change global live info as we | |
2309 | can undo inheritance transformations after inheritance | |
2310 | pseudo assigning. */ | |
2311 | lra_create_live_ranges (true, false); | |
55a2c322 VM |
2312 | live_p = true; |
2313 | /* If we don't spill non-reload and non-inheritance pseudos, | |
2314 | there is no sense to run memory-memory move coalescing. | |
2315 | If inheritance pseudos were spilled, the memory-memory | |
2316 | moves involving them will be removed by pass undoing | |
2317 | inheritance. */ | |
2318 | if (lra_simple_p) | |
2319 | lra_assign (); | |
2320 | else | |
2321 | { | |
72ea0d47 VM |
2322 | bool spill_p = !lra_assign (); |
2323 | ||
55a2c322 VM |
2324 | if (lra_undo_inheritance ()) |
2325 | live_p = false; | |
72ea0d47 VM |
2326 | if (spill_p) |
2327 | { | |
2328 | if (! live_p) | |
2329 | { | |
4ab74a01 | 2330 | lra_create_live_ranges (true, true); |
72ea0d47 VM |
2331 | live_p = true; |
2332 | } | |
2333 | if (lra_coalesce ()) | |
2334 | live_p = false; | |
2335 | } | |
4ccf8f43 JJ |
2336 | if (! live_p) |
2337 | lra_clear_live_ranges (); | |
55a2c322 VM |
2338 | } |
2339 | } | |
080cbf9e VM |
2340 | /* Don't clear optional reloads bitmap until all constraints are |
2341 | satisfied as we need to differ them from regular reloads. */ | |
2342 | bitmap_clear (&lra_optional_reload_pseudos); | |
2b778c9d | 2343 | bitmap_clear (&lra_subreg_reload_pseudos); |
55a2c322 VM |
2344 | bitmap_clear (&lra_inheritance_pseudos); |
2345 | bitmap_clear (&lra_split_regs); | |
55a2c322 VM |
2346 | if (! live_p) |
2347 | { | |
2348 | /* We need full live info for spilling pseudos into | |
2349 | registers instead of memory. */ | |
4ab74a01 | 2350 | lra_create_live_ranges (lra_reg_spill_p, true); |
55a2c322 VM |
2351 | live_p = true; |
2352 | } | |
4ab74a01 VM |
2353 | /* We should check necessity for spilling here as the above live |
2354 | range pass can remove spilled pseudos. */ | |
2355 | if (! lra_need_for_spills_p ()) | |
2356 | break; | |
d9cf932c VM |
2357 | /* Now we know what pseudos should be spilled. Try to |
2358 | rematerialize them first. */ | |
f607c5c4 | 2359 | if (lra_remat ()) |
d9cf932c VM |
2360 | { |
2361 | /* We need full live info -- see the comment above. */ | |
4ab74a01 | 2362 | lra_create_live_ranges (lra_reg_spill_p, true); |
d9cf932c VM |
2363 | live_p = true; |
2364 | if (! lra_need_for_spills_p ()) | |
2365 | break; | |
2366 | } | |
55a2c322 VM |
2367 | lra_spill (); |
2368 | /* Assignment of stack slots changes elimination offsets for | |
2369 | some eliminations. So update the offsets here. */ | |
8d49e7ef | 2370 | lra_eliminate (false, false); |
8fd827b8 VM |
2371 | lra_constraint_new_regno_start = max_reg_num (); |
2372 | if (lra_bad_spill_regno_start == INT_MAX | |
2373 | && lra_inheritance_iter > LRA_MAX_INHERITANCE_PASSES | |
2374 | && lra_rematerialization_iter > LRA_MAX_REMATERIALIZATION_PASSES) | |
2375 | /* After switching off inheritance and rematerialization | |
2376 | passes, avoid spilling reload pseudos will be created to | |
2377 | prevent LRA cycling in some complicated cases. */ | |
2378 | lra_bad_spill_regno_start = lra_constraint_new_regno_start; | |
f54437d5 | 2379 | lra_assignment_iter_after_spill = 0; |
55a2c322 VM |
2380 | } |
2381 | restore_scratches (); | |
8d49e7ef | 2382 | lra_eliminate (true, false); |
c5cd5a7e | 2383 | lra_final_code_change (); |
55a2c322 | 2384 | lra_in_progress = 0; |
4ccf8f43 JJ |
2385 | if (live_p) |
2386 | lra_clear_live_ranges (); | |
55a2c322 VM |
2387 | lra_live_ranges_finish (); |
2388 | lra_constraints_finish (); | |
2389 | finish_reg_info (); | |
2390 | sbitmap_free (lra_constraint_insn_stack_bitmap); | |
9771b263 | 2391 | lra_constraint_insn_stack.release (); |
55a2c322 VM |
2392 | finish_insn_recog_data (); |
2393 | regstat_free_n_sets_and_refs (); | |
2394 | regstat_free_ri (); | |
2395 | reload_completed = 1; | |
2396 | update_inc_notes (); | |
2397 | ||
2398 | inserted_p = fixup_abnormal_edges (); | |
2399 | ||
2400 | /* We've possibly turned single trapping insn into multiple ones. */ | |
2401 | if (cfun->can_throw_non_call_exceptions) | |
2402 | { | |
2403 | sbitmap blocks; | |
8b1c6fd7 | 2404 | blocks = sbitmap_alloc (last_basic_block_for_fn (cfun)); |
f61e445a | 2405 | bitmap_ones (blocks); |
55a2c322 VM |
2406 | find_many_sub_basic_blocks (blocks); |
2407 | sbitmap_free (blocks); | |
2408 | } | |
2409 | ||
2410 | if (inserted_p) | |
2411 | commit_edge_insertions (); | |
2412 | ||
2413 | /* Replacing pseudos with their memory equivalents might have | |
2414 | created shared rtx. Subsequent passes would get confused | |
2415 | by this, so unshare everything here. */ | |
2416 | unshare_all_rtl_again (get_insns ()); | |
2417 | ||
b2b29377 MM |
2418 | if (flag_checking) |
2419 | check_rtl (true); | |
55a2c322 VM |
2420 | |
2421 | timevar_pop (TV_LRA); | |
2422 | } | |
2423 | ||
2424 | /* Called once per compiler to initialize LRA data once. */ | |
2425 | void | |
2426 | lra_init_once (void) | |
2427 | { | |
2428 | init_insn_code_data_once (); | |
2429 | } | |
2430 | ||
55a2c322 VM |
2431 | /* Called once per compiler to finish LRA data which are initialize |
2432 | once. */ | |
2433 | void | |
2434 | lra_finish_once (void) | |
2435 | { | |
2436 | finish_insn_code_data_once (); | |
2437 | } |