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c6a6cdaa | 1 | /* LRA (local register allocator) driver and LRA utilities. |
711789cc | 2 | Copyright (C) 2010-2013 Free Software Foundation, Inc. |
c6a6cdaa | 3 | Contributed by Vladimir Makarov <vmakarov@redhat.com>. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it under | |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 3, or (at your option) any later | |
10 | version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | ||
22 | /* The Local Register Allocator (LRA) is a replacement of former | |
23 | reload pass. It is focused to simplify code solving the reload | |
24 | pass tasks, to make the code maintenance easier, and to implement new | |
25 | perspective optimizations. | |
26 | ||
27 | The major LRA design solutions are: | |
28 | o division small manageable, separated sub-tasks | |
29 | o reflection of all transformations and decisions in RTL as more | |
30 | as possible | |
31 | o insn constraints as a primary source of the info (minimizing | |
32 | number of target-depended macros/hooks) | |
33 | ||
34 | In brief LRA works by iterative insn process with the final goal is | |
35 | to satisfy all insn and address constraints: | |
36 | o New reload insns (in brief reloads) and reload pseudos might be | |
37 | generated; | |
38 | o Some pseudos might be spilled to assign hard registers to | |
39 | new reload pseudos; | |
40 | o Changing spilled pseudos to stack memory or their equivalences; | |
41 | o Allocation stack memory changes the address displacement and | |
42 | new iteration is needed. | |
43 | ||
44 | Here is block diagram of LRA passes: | |
45 | ||
1f3a048a | 46 | ------------------------ |
47 | --------------- | Undo inheritance for | --------------- | |
48 | | Memory-memory | | spilled pseudos, | | New (and old) | | |
49 | | move coalesce |<---| splits for pseudos got |<-- | pseudos | | |
50 | --------------- | the same hard regs, | | assignment | | |
51 | Start | | and optional reloads | --------------- | |
52 | | | ------------------------ ^ | |
b28ae2d4 | 53 | V | ---------------- | |
54 | ----------- V | Update virtual | | | |
55 | | Remove |----> ------------>| register | | | |
56 | | scratches | ^ | displacements | | | |
57 | ----------- | ---------------- | | |
58 | | | | | |
59 | | V New | | |
60 | ---------------- No ------------ pseudos ------------------- | |
61 | | Spilled pseudo | change |Constraints:| or insns | Inheritance/split | | |
62 | | to memory |<-------| RTL |--------->| transformations | | |
63 | | substitution | | transfor- | | in EBB scope | | |
64 | ---------------- | mations | ------------------- | |
65 | | ------------ | |
66 | V | |
c6a6cdaa | 67 | ------------------------- |
68 | | Hard regs substitution, | | |
69 | | devirtalization, and |------> Finish | |
70 | | restoring scratches got | | |
b28ae2d4 | 71 | | memory | |
c6a6cdaa | 72 | ------------------------- |
73 | ||
74 | To speed up the process: | |
75 | o We process only insns affected by changes on previous | |
76 | iterations; | |
77 | o We don't use DFA-infrastructure because it results in much slower | |
78 | compiler speed than a special IR described below does; | |
79 | o We use a special insn representation for quick access to insn | |
80 | info which is always *synchronized* with the current RTL; | |
81 | o Insn IR is minimized by memory. It is divided on three parts: | |
82 | o one specific for each insn in RTL (only operand locations); | |
83 | o one common for all insns in RTL with the same insn code | |
84 | (different operand attributes from machine descriptions); | |
85 | o one oriented for maintenance of live info (list of pseudos). | |
86 | o Pseudo data: | |
87 | o all insns where the pseudo is referenced; | |
88 | o live info (conflicting hard regs, live ranges, # of | |
89 | references etc); | |
90 | o data used for assigning (preferred hard regs, costs etc). | |
91 | ||
92 | This file contains LRA driver, LRA utility functions and data, and | |
93 | code for dealing with scratches. */ | |
94 | ||
95 | #include "config.h" | |
96 | #include "system.h" | |
97 | #include "coretypes.h" | |
98 | #include "tm.h" | |
fc8a0f60 | 99 | #include "hard-reg-set.h" |
c6a6cdaa | 100 | #include "rtl.h" |
101 | #include "tm_p.h" | |
102 | #include "regs.h" | |
103 | #include "insn-config.h" | |
104 | #include "insn-codes.h" | |
105 | #include "recog.h" | |
106 | #include "output.h" | |
107 | #include "addresses.h" | |
c6a6cdaa | 108 | #include "flags.h" |
109 | #include "function.h" | |
110 | #include "expr.h" | |
111 | #include "basic-block.h" | |
112 | #include "except.h" | |
113 | #include "tree-pass.h" | |
114 | #include "timevar.h" | |
115 | #include "target.h" | |
116 | #include "vec.h" | |
117 | #include "ira.h" | |
118 | #include "lra-int.h" | |
119 | #include "df.h" | |
120 | ||
121 | /* Hard registers currently not available for allocation. It can | |
122 | changed after some hard registers become not eliminable. */ | |
123 | HARD_REG_SET lra_no_alloc_regs; | |
124 | ||
125 | static int get_new_reg_value (void); | |
126 | static void expand_reg_info (void); | |
127 | static void invalidate_insn_recog_data (int); | |
128 | static int get_insn_freq (rtx); | |
129 | static void invalidate_insn_data_regno_info (lra_insn_recog_data_t, rtx, int); | |
130 | ||
131 | /* Expand all regno related info needed for LRA. */ | |
132 | static void | |
7619e612 | 133 | expand_reg_data (int old) |
c6a6cdaa | 134 | { |
135 | resize_reg_info (); | |
136 | expand_reg_info (); | |
137 | ira_expand_reg_equiv (); | |
7619e612 | 138 | for (int i = (int) max_reg_num () - 1; i >= old; i--) |
139 | lra_change_class (i, ALL_REGS, " Set", true); | |
c6a6cdaa | 140 | } |
141 | ||
142 | /* Create and return a new reg of ORIGINAL mode. If ORIGINAL is NULL | |
143 | or of VOIDmode, use MD_MODE for the new reg. Initialize its | |
144 | register class to RCLASS. Print message about assigning class | |
145 | RCLASS containing new register name TITLE unless it is NULL. Use | |
146 | attributes of ORIGINAL if it is a register. The created register | |
147 | will have unique held value. */ | |
148 | rtx | |
149 | lra_create_new_reg_with_unique_value (enum machine_mode md_mode, rtx original, | |
150 | enum reg_class rclass, const char *title) | |
151 | { | |
152 | enum machine_mode mode; | |
153 | rtx new_reg; | |
154 | ||
155 | if (original == NULL_RTX || (mode = GET_MODE (original)) == VOIDmode) | |
156 | mode = md_mode; | |
157 | lra_assert (mode != VOIDmode); | |
158 | new_reg = gen_reg_rtx (mode); | |
159 | if (original == NULL_RTX || ! REG_P (original)) | |
160 | { | |
161 | if (lra_dump_file != NULL) | |
162 | fprintf (lra_dump_file, " Creating newreg=%i", REGNO (new_reg)); | |
163 | } | |
164 | else | |
165 | { | |
166 | if (ORIGINAL_REGNO (original) >= FIRST_PSEUDO_REGISTER) | |
167 | ORIGINAL_REGNO (new_reg) = ORIGINAL_REGNO (original); | |
168 | REG_USERVAR_P (new_reg) = REG_USERVAR_P (original); | |
169 | REG_POINTER (new_reg) = REG_POINTER (original); | |
170 | REG_ATTRS (new_reg) = REG_ATTRS (original); | |
171 | if (lra_dump_file != NULL) | |
172 | fprintf (lra_dump_file, " Creating newreg=%i from oldreg=%i", | |
173 | REGNO (new_reg), REGNO (original)); | |
174 | } | |
175 | if (lra_dump_file != NULL) | |
176 | { | |
177 | if (title != NULL) | |
178 | fprintf (lra_dump_file, ", assigning class %s to%s%s r%d", | |
179 | reg_class_names[rclass], *title == '\0' ? "" : " ", | |
180 | title, REGNO (new_reg)); | |
181 | fprintf (lra_dump_file, "\n"); | |
182 | } | |
7619e612 | 183 | expand_reg_data (max_reg_num ()); |
c6a6cdaa | 184 | setup_reg_classes (REGNO (new_reg), rclass, NO_REGS, rclass); |
185 | return new_reg; | |
186 | } | |
187 | ||
188 | /* Analogous to the previous function but also inherits value of | |
189 | ORIGINAL. */ | |
190 | rtx | |
191 | lra_create_new_reg (enum machine_mode md_mode, rtx original, | |
192 | enum reg_class rclass, const char *title) | |
193 | { | |
194 | rtx new_reg; | |
195 | ||
196 | new_reg | |
197 | = lra_create_new_reg_with_unique_value (md_mode, original, rclass, title); | |
198 | if (original != NULL_RTX && REG_P (original)) | |
a1064490 | 199 | lra_assign_reg_val (REGNO (original), REGNO (new_reg)); |
c6a6cdaa | 200 | return new_reg; |
201 | } | |
202 | ||
203 | /* Set up for REGNO unique hold value. */ | |
204 | void | |
205 | lra_set_regno_unique_value (int regno) | |
206 | { | |
207 | lra_reg_info[regno].val = get_new_reg_value (); | |
208 | } | |
209 | ||
3b3a5e5f | 210 | /* Invalidate INSN related info used by LRA. The info should never be |
211 | used after that. */ | |
c6a6cdaa | 212 | void |
213 | lra_invalidate_insn_data (rtx insn) | |
214 | { | |
215 | lra_invalidate_insn_regno_info (insn); | |
216 | invalidate_insn_recog_data (INSN_UID (insn)); | |
217 | } | |
218 | ||
219 | /* Mark INSN deleted and invalidate the insn related info used by | |
220 | LRA. */ | |
221 | void | |
222 | lra_set_insn_deleted (rtx insn) | |
223 | { | |
224 | lra_invalidate_insn_data (insn); | |
225 | SET_INSN_DELETED (insn); | |
226 | } | |
227 | ||
228 | /* Delete an unneeded INSN and any previous insns who sole purpose is | |
229 | loading data that is dead in INSN. */ | |
230 | void | |
231 | lra_delete_dead_insn (rtx insn) | |
232 | { | |
233 | rtx prev = prev_real_insn (insn); | |
234 | rtx prev_dest; | |
235 | ||
236 | /* If the previous insn sets a register that dies in our insn, | |
237 | delete it too. */ | |
238 | if (prev && GET_CODE (PATTERN (prev)) == SET | |
239 | && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest)) | |
240 | && reg_mentioned_p (prev_dest, PATTERN (insn)) | |
241 | && find_regno_note (insn, REG_DEAD, REGNO (prev_dest)) | |
242 | && ! side_effects_p (SET_SRC (PATTERN (prev)))) | |
243 | lra_delete_dead_insn (prev); | |
244 | ||
245 | lra_set_insn_deleted (insn); | |
246 | } | |
247 | ||
6c397456 | 248 | /* Emit insn x = y + z. Return NULL if we failed to do it. |
249 | Otherwise, return the insn. We don't use gen_add3_insn as it might | |
250 | clobber CC. */ | |
251 | static rtx | |
252 | emit_add3_insn (rtx x, rtx y, rtx z) | |
253 | { | |
254 | rtx insn, last; | |
255 | ||
256 | last = get_last_insn (); | |
257 | insn = emit_insn (gen_rtx_SET (VOIDmode, x, | |
258 | gen_rtx_PLUS (GET_MODE (y), y, z))); | |
259 | if (recog_memoized (insn) < 0) | |
260 | { | |
261 | delete_insns_since (last); | |
262 | insn = NULL_RTX; | |
263 | } | |
264 | return insn; | |
265 | } | |
266 | ||
267 | /* Emit insn x = x + y. Return the insn. We use gen_add2_insn as the | |
268 | last resort. */ | |
269 | static rtx | |
270 | emit_add2_insn (rtx x, rtx y) | |
271 | { | |
272 | rtx insn; | |
273 | ||
274 | insn = emit_add3_insn (x, x, y); | |
275 | if (insn == NULL_RTX) | |
276 | { | |
277 | insn = gen_add2_insn (x, y); | |
278 | if (insn != NULL_RTX) | |
279 | emit_insn (insn); | |
280 | } | |
281 | return insn; | |
282 | } | |
283 | ||
c6a6cdaa | 284 | /* Target checks operands through operand predicates to recognize an |
285 | insn. We should have a special precaution to generate add insns | |
286 | which are frequent results of elimination. | |
287 | ||
288 | Emit insns for x = y + z. X can be used to store intermediate | |
289 | values and should be not in Y and Z when we use X to store an | |
290 | intermediate value. Y + Z should form [base] [+ index[ * scale]] [ | |
291 | + disp] where base and index are registers, disp and scale are | |
292 | constants. Y should contain base if it is present, Z should | |
293 | contain disp if any. index[*scale] can be part of Y or Z. */ | |
294 | void | |
295 | lra_emit_add (rtx x, rtx y, rtx z) | |
296 | { | |
297 | int old; | |
298 | rtx insn, last; | |
299 | rtx a1, a2, base, index, disp, scale, index_scale; | |
300 | bool ok_p; | |
301 | ||
6c397456 | 302 | insn = emit_add3_insn (x, y, z); |
c6a6cdaa | 303 | old = max_reg_num (); |
304 | if (insn != NULL_RTX) | |
6c397456 | 305 | ; |
c6a6cdaa | 306 | else |
307 | { | |
308 | disp = a2 = NULL_RTX; | |
309 | if (GET_CODE (y) == PLUS) | |
310 | { | |
311 | a1 = XEXP (y, 0); | |
312 | a2 = XEXP (y, 1); | |
313 | disp = z; | |
314 | } | |
315 | else | |
316 | { | |
317 | a1 = y; | |
318 | if (CONSTANT_P (z)) | |
319 | disp = z; | |
320 | else | |
321 | a2 = z; | |
322 | } | |
323 | index_scale = scale = NULL_RTX; | |
324 | if (GET_CODE (a1) == MULT) | |
325 | { | |
326 | index_scale = a1; | |
327 | index = XEXP (a1, 0); | |
328 | scale = XEXP (a1, 1); | |
329 | base = a2; | |
330 | } | |
331 | else if (a2 != NULL_RTX && GET_CODE (a2) == MULT) | |
332 | { | |
333 | index_scale = a2; | |
334 | index = XEXP (a2, 0); | |
335 | scale = XEXP (a2, 1); | |
336 | base = a1; | |
337 | } | |
338 | else | |
339 | { | |
340 | base = a1; | |
341 | index = a2; | |
342 | } | |
343 | if (! REG_P (base) | |
344 | || (index != NULL_RTX && ! REG_P (index)) | |
345 | || (disp != NULL_RTX && ! CONSTANT_P (disp)) | |
346 | || (scale != NULL_RTX && ! CONSTANT_P (scale))) | |
347 | { | |
6c397456 | 348 | /* Probably we have no 3 op add. Last chance is to use 2-op |
349 | add insn. To succeed, don't move Z to X as an address | |
350 | segment always comes in Y. Otherwise, we might fail when | |
351 | adding the address segment to register. */ | |
c6a6cdaa | 352 | lra_assert (x != y && x != z); |
0178c26e | 353 | emit_move_insn (x, y); |
6c397456 | 354 | insn = emit_add2_insn (x, z); |
355 | lra_assert (insn != NULL_RTX); | |
c6a6cdaa | 356 | } |
357 | else | |
358 | { | |
359 | if (index_scale == NULL_RTX) | |
360 | index_scale = index; | |
361 | if (disp == NULL_RTX) | |
362 | { | |
363 | /* Generate x = index_scale; x = x + base. */ | |
364 | lra_assert (index_scale != NULL_RTX && base != NULL_RTX); | |
365 | emit_move_insn (x, index_scale); | |
6c397456 | 366 | insn = emit_add2_insn (x, base); |
367 | lra_assert (insn != NULL_RTX); | |
c6a6cdaa | 368 | } |
369 | else if (scale == NULL_RTX) | |
370 | { | |
371 | /* Try x = base + disp. */ | |
372 | lra_assert (base != NULL_RTX); | |
373 | last = get_last_insn (); | |
374 | insn = emit_move_insn (x, gen_rtx_PLUS (GET_MODE (base), | |
375 | base, disp)); | |
376 | if (recog_memoized (insn) < 0) | |
377 | { | |
378 | delete_insns_since (last); | |
379 | /* Generate x = disp; x = x + base. */ | |
380 | emit_move_insn (x, disp); | |
6c397456 | 381 | insn = emit_add2_insn (x, base); |
382 | lra_assert (insn != NULL_RTX); | |
c6a6cdaa | 383 | } |
384 | /* Generate x = x + index. */ | |
385 | if (index != NULL_RTX) | |
386 | { | |
6c397456 | 387 | insn = emit_add2_insn (x, index); |
388 | lra_assert (insn != NULL_RTX); | |
c6a6cdaa | 389 | } |
390 | } | |
391 | else | |
392 | { | |
393 | /* Try x = index_scale; x = x + disp; x = x + base. */ | |
394 | last = get_last_insn (); | |
395 | insn = emit_move_insn (x, index_scale); | |
396 | ok_p = false; | |
397 | if (recog_memoized (insn) >= 0) | |
398 | { | |
6c397456 | 399 | insn = emit_add2_insn (x, disp); |
c6a6cdaa | 400 | if (insn != NULL_RTX) |
401 | { | |
6c397456 | 402 | insn = emit_add2_insn (x, disp); |
c6a6cdaa | 403 | if (insn != NULL_RTX) |
6c397456 | 404 | ok_p = true; |
c6a6cdaa | 405 | } |
406 | } | |
407 | if (! ok_p) | |
408 | { | |
409 | delete_insns_since (last); | |
410 | /* Generate x = disp; x = x + base; x = x + index_scale. */ | |
411 | emit_move_insn (x, disp); | |
6c397456 | 412 | insn = emit_add2_insn (x, base); |
413 | lra_assert (insn != NULL_RTX); | |
414 | insn = emit_add2_insn (x, index_scale); | |
415 | lra_assert (insn != NULL_RTX); | |
c6a6cdaa | 416 | } |
417 | } | |
418 | } | |
419 | } | |
420 | /* Functions emit_... can create pseudos -- so expand the pseudo | |
421 | data. */ | |
422 | if (old != max_reg_num ()) | |
7619e612 | 423 | expand_reg_data (old); |
c6a6cdaa | 424 | } |
425 | ||
426 | /* The number of emitted reload insns so far. */ | |
427 | int lra_curr_reload_num; | |
428 | ||
429 | /* Emit x := y, processing special case when y = u + v or y = u + v * | |
430 | scale + w through emit_add (Y can be an address which is base + | |
431 | index reg * scale + displacement in general case). X may be used | |
432 | as intermediate result therefore it should be not in Y. */ | |
433 | void | |
434 | lra_emit_move (rtx x, rtx y) | |
435 | { | |
436 | int old; | |
437 | ||
438 | if (GET_CODE (y) != PLUS) | |
439 | { | |
440 | if (rtx_equal_p (x, y)) | |
441 | return; | |
442 | old = max_reg_num (); | |
443 | emit_move_insn (x, y); | |
444 | if (REG_P (x)) | |
445 | lra_reg_info[ORIGINAL_REGNO (x)].last_reload = ++lra_curr_reload_num; | |
446 | /* Function emit_move can create pseudos -- so expand the pseudo | |
447 | data. */ | |
448 | if (old != max_reg_num ()) | |
7619e612 | 449 | expand_reg_data (old); |
c6a6cdaa | 450 | return; |
451 | } | |
452 | lra_emit_add (x, XEXP (y, 0), XEXP (y, 1)); | |
453 | } | |
454 | ||
455 | /* Update insn operands which are duplication of operands whose | |
456 | numbers are in array of NOPS (with end marker -1). The insn is | |
457 | represented by its LRA internal representation ID. */ | |
458 | void | |
459 | lra_update_dups (lra_insn_recog_data_t id, signed char *nops) | |
460 | { | |
461 | int i, j, nop; | |
462 | struct lra_static_insn_data *static_id = id->insn_static_data; | |
463 | ||
464 | for (i = 0; i < static_id->n_dups; i++) | |
465 | for (j = 0; (nop = nops[j]) >= 0; j++) | |
466 | if (static_id->dup_num[i] == nop) | |
467 | *id->dup_loc[i] = *id->operand_loc[nop]; | |
468 | } | |
469 | ||
470 | \f | |
471 | ||
472 | /* This page contains code dealing with info about registers in the | |
473 | insns. */ | |
474 | ||
475 | /* Pools for insn reg info. */ | |
476 | static alloc_pool insn_reg_pool; | |
477 | ||
478 | /* Initiate pool for insn reg info. */ | |
479 | static void | |
480 | init_insn_regs (void) | |
481 | { | |
482 | insn_reg_pool | |
483 | = create_alloc_pool ("insn regs", sizeof (struct lra_insn_reg), 100); | |
484 | } | |
485 | ||
40cec44a | 486 | /* Create LRA insn related info about a reference to REGNO in INSN with |
487 | TYPE (in/out/inout), biggest reference mode MODE, flag that it is | |
c6a6cdaa | 488 | reference through subreg (SUBREG_P), flag that is early clobbered |
489 | in the insn (EARLY_CLOBBER), and reference to the next insn reg | |
490 | info (NEXT). */ | |
491 | static struct lra_insn_reg * | |
40cec44a | 492 | new_insn_reg (rtx insn, int regno, enum op_type type, enum machine_mode mode, |
c6a6cdaa | 493 | bool subreg_p, bool early_clobber, struct lra_insn_reg *next) |
494 | { | |
495 | struct lra_insn_reg *ir; | |
496 | ||
497 | ir = (struct lra_insn_reg *) pool_alloc (insn_reg_pool); | |
498 | ir->type = type; | |
499 | ir->biggest_mode = mode; | |
40cec44a | 500 | if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (lra_reg_info[regno].biggest_mode) |
501 | && NONDEBUG_INSN_P (insn)) | |
fc8a0f60 | 502 | lra_reg_info[regno].biggest_mode = mode; |
c6a6cdaa | 503 | ir->subreg_p = subreg_p; |
504 | ir->early_clobber = early_clobber; | |
505 | ir->regno = regno; | |
506 | ir->next = next; | |
507 | return ir; | |
508 | } | |
509 | ||
510 | /* Free insn reg info IR. */ | |
511 | static void | |
512 | free_insn_reg (struct lra_insn_reg *ir) | |
513 | { | |
514 | pool_free (insn_reg_pool, ir); | |
515 | } | |
516 | ||
517 | /* Free insn reg info list IR. */ | |
518 | static void | |
519 | free_insn_regs (struct lra_insn_reg *ir) | |
520 | { | |
521 | struct lra_insn_reg *next_ir; | |
522 | ||
523 | for (; ir != NULL; ir = next_ir) | |
524 | { | |
525 | next_ir = ir->next; | |
526 | free_insn_reg (ir); | |
527 | } | |
528 | } | |
529 | ||
530 | /* Finish pool for insn reg info. */ | |
531 | static void | |
532 | finish_insn_regs (void) | |
533 | { | |
534 | free_alloc_pool (insn_reg_pool); | |
535 | } | |
536 | ||
537 | \f | |
538 | ||
539 | /* This page contains code dealing LRA insn info (or in other words | |
540 | LRA internal insn representation). */ | |
541 | ||
542 | struct target_lra_int default_target_lra_int; | |
543 | #if SWITCHABLE_TARGET | |
544 | struct target_lra_int *this_target_lra_int = &default_target_lra_int; | |
545 | #endif | |
546 | ||
547 | /* Map INSN_CODE -> the static insn data. This info is valid during | |
548 | all translation unit. */ | |
549 | struct lra_static_insn_data *insn_code_data[LAST_INSN_CODE]; | |
550 | ||
551 | /* Debug insns are represented as a special insn with one input | |
552 | operand which is RTL expression in var_location. */ | |
553 | ||
554 | /* The following data are used as static insn operand data for all | |
555 | debug insns. If structure lra_operand_data is changed, the | |
556 | initializer should be changed too. */ | |
557 | static struct lra_operand_data debug_operand_data = | |
558 | { | |
559 | NULL, /* alternative */ | |
560 | VOIDmode, /* We are not interesting in the operand mode. */ | |
561 | OP_IN, | |
562 | 0, 0, 0, 0 | |
563 | }; | |
564 | ||
565 | /* The following data are used as static insn data for all debug | |
566 | insns. If structure lra_static_insn_data is changed, the | |
567 | initializer should be changed too. */ | |
568 | static struct lra_static_insn_data debug_insn_static_data = | |
569 | { | |
570 | &debug_operand_data, | |
571 | 0, /* Duplication operands #. */ | |
572 | -1, /* Commutative operand #. */ | |
573 | 1, /* Operands #. There is only one operand which is debug RTL | |
574 | expression. */ | |
575 | 0, /* Duplications #. */ | |
576 | 0, /* Alternatives #. We are not interesting in alternatives | |
577 | because we does not proceed debug_insns for reloads. */ | |
578 | NULL, /* Hard registers referenced in machine description. */ | |
579 | NULL /* Descriptions of operands in alternatives. */ | |
580 | }; | |
581 | ||
582 | /* Called once per compiler work to initialize some LRA data related | |
583 | to insns. */ | |
584 | static void | |
585 | init_insn_code_data_once (void) | |
586 | { | |
587 | memset (insn_code_data, 0, sizeof (insn_code_data)); | |
588 | memset (op_alt_data, 0, sizeof (op_alt_data)); | |
589 | } | |
590 | ||
591 | /* Called once per compiler work to finalize some LRA data related to | |
592 | insns. */ | |
593 | static void | |
594 | finish_insn_code_data_once (void) | |
595 | { | |
596 | int i; | |
597 | ||
598 | for (i = 0; i < LAST_INSN_CODE; i++) | |
599 | { | |
600 | if (insn_code_data[i] != NULL) | |
601 | free (insn_code_data[i]); | |
602 | if (op_alt_data[i] != NULL) | |
603 | free (op_alt_data[i]); | |
604 | } | |
605 | } | |
606 | ||
607 | /* Initialize LRA info about operands in insn alternatives. */ | |
608 | static void | |
609 | init_op_alt_data (void) | |
610 | { | |
611 | int i; | |
612 | ||
613 | for (i = 0; i < LAST_INSN_CODE; i++) | |
614 | if (op_alt_data[i] != NULL) | |
615 | { | |
616 | free (op_alt_data[i]); | |
617 | op_alt_data[i] = NULL; | |
618 | } | |
619 | } | |
620 | ||
621 | /* Return static insn data, allocate and setup if necessary. Although | |
622 | dup_num is static data (it depends only on icode), to set it up we | |
623 | need to extract insn first. So recog_data should be valid for | |
624 | normal insn (ICODE >= 0) before the call. */ | |
625 | static struct lra_static_insn_data * | |
626 | get_static_insn_data (int icode, int nop, int ndup, int nalt) | |
627 | { | |
628 | struct lra_static_insn_data *data; | |
629 | size_t n_bytes; | |
630 | ||
631 | lra_assert (icode < LAST_INSN_CODE); | |
632 | if (icode >= 0 && (data = insn_code_data[icode]) != NULL) | |
633 | return data; | |
634 | lra_assert (nop >= 0 && ndup >= 0 && nalt >= 0); | |
635 | n_bytes = sizeof (struct lra_static_insn_data) | |
636 | + sizeof (struct lra_operand_data) * nop | |
637 | + sizeof (int) * ndup; | |
638 | data = XNEWVAR (struct lra_static_insn_data, n_bytes); | |
639 | data->n_operands = nop; | |
640 | data->n_dups = ndup; | |
641 | data->n_alternatives = nalt; | |
642 | data->operand = ((struct lra_operand_data *) | |
643 | ((char *) data + sizeof (struct lra_static_insn_data))); | |
644 | data->dup_num = ((int *) ((char *) data->operand | |
645 | + sizeof (struct lra_operand_data) * nop)); | |
646 | if (icode >= 0) | |
647 | { | |
648 | int i; | |
649 | ||
650 | insn_code_data[icode] = data; | |
651 | for (i = 0; i < nop; i++) | |
652 | { | |
653 | data->operand[i].constraint | |
654 | = insn_data[icode].operand[i].constraint; | |
655 | data->operand[i].mode = insn_data[icode].operand[i].mode; | |
656 | data->operand[i].strict_low = insn_data[icode].operand[i].strict_low; | |
657 | data->operand[i].is_operator | |
658 | = insn_data[icode].operand[i].is_operator; | |
659 | data->operand[i].type | |
660 | = (data->operand[i].constraint[0] == '=' ? OP_OUT | |
661 | : data->operand[i].constraint[0] == '+' ? OP_INOUT | |
662 | : OP_IN); | |
663 | data->operand[i].is_address = false; | |
664 | } | |
665 | for (i = 0; i < ndup; i++) | |
666 | data->dup_num[i] = recog_data.dup_num[i]; | |
667 | } | |
668 | return data; | |
669 | } | |
670 | ||
671 | /* The current length of the following array. */ | |
672 | int lra_insn_recog_data_len; | |
673 | ||
674 | /* Map INSN_UID -> the insn recog data (NULL if unknown). */ | |
675 | lra_insn_recog_data_t *lra_insn_recog_data; | |
676 | ||
677 | /* Initialize LRA data about insns. */ | |
678 | static void | |
679 | init_insn_recog_data (void) | |
680 | { | |
681 | lra_insn_recog_data_len = 0; | |
682 | lra_insn_recog_data = NULL; | |
683 | init_insn_regs (); | |
684 | } | |
685 | ||
686 | /* Expand, if necessary, LRA data about insns. */ | |
687 | static void | |
688 | check_and_expand_insn_recog_data (int index) | |
689 | { | |
690 | int i, old; | |
691 | ||
692 | if (lra_insn_recog_data_len > index) | |
693 | return; | |
694 | old = lra_insn_recog_data_len; | |
695 | lra_insn_recog_data_len = index * 3 / 2 + 1; | |
696 | lra_insn_recog_data = XRESIZEVEC (lra_insn_recog_data_t, | |
697 | lra_insn_recog_data, | |
698 | lra_insn_recog_data_len); | |
699 | for (i = old; i < lra_insn_recog_data_len; i++) | |
700 | lra_insn_recog_data[i] = NULL; | |
701 | } | |
702 | ||
703 | /* Finish LRA DATA about insn. */ | |
704 | static void | |
705 | free_insn_recog_data (lra_insn_recog_data_t data) | |
706 | { | |
707 | if (data->operand_loc != NULL) | |
708 | free (data->operand_loc); | |
709 | if (data->dup_loc != NULL) | |
710 | free (data->dup_loc); | |
711 | if (data->arg_hard_regs != NULL) | |
712 | free (data->arg_hard_regs); | |
f2d92d7a | 713 | if (HAVE_ATTR_enabled && data->alternative_enabled_p != NULL) |
c6a6cdaa | 714 | free (data->alternative_enabled_p); |
c6a6cdaa | 715 | if (data->icode < 0 && NONDEBUG_INSN_P (data->insn)) |
716 | { | |
717 | if (data->insn_static_data->operand_alternative != NULL) | |
718 | free (data->insn_static_data->operand_alternative); | |
719 | free_insn_regs (data->insn_static_data->hard_regs); | |
720 | free (data->insn_static_data); | |
721 | } | |
722 | free_insn_regs (data->regs); | |
723 | data->regs = NULL; | |
724 | free (data); | |
725 | } | |
726 | ||
727 | /* Finish LRA data about all insns. */ | |
728 | static void | |
729 | finish_insn_recog_data (void) | |
730 | { | |
731 | int i; | |
732 | lra_insn_recog_data_t data; | |
733 | ||
734 | for (i = 0; i < lra_insn_recog_data_len; i++) | |
735 | if ((data = lra_insn_recog_data[i]) != NULL) | |
736 | free_insn_recog_data (data); | |
737 | finish_insn_regs (); | |
738 | free (lra_insn_recog_data); | |
739 | } | |
740 | ||
741 | /* Setup info about operands in alternatives of LRA DATA of insn. */ | |
742 | static void | |
743 | setup_operand_alternative (lra_insn_recog_data_t data) | |
744 | { | |
745 | int i, nop, nalt; | |
746 | int icode = data->icode; | |
747 | struct lra_static_insn_data *static_data = data->insn_static_data; | |
748 | ||
749 | if (icode >= 0 | |
750 | && (static_data->operand_alternative = op_alt_data[icode]) != NULL) | |
751 | return; | |
752 | static_data->commutative = -1; | |
753 | nop = static_data->n_operands; | |
754 | if (nop == 0) | |
755 | { | |
756 | static_data->operand_alternative = NULL; | |
757 | return; | |
758 | } | |
759 | nalt = static_data->n_alternatives; | |
760 | static_data->operand_alternative = XNEWVEC (struct operand_alternative, | |
761 | nalt * nop); | |
762 | memset (static_data->operand_alternative, 0, | |
763 | nalt * nop * sizeof (struct operand_alternative)); | |
764 | if (icode >= 0) | |
765 | op_alt_data[icode] = static_data->operand_alternative; | |
766 | for (i = 0; i < nop; i++) | |
767 | { | |
768 | int j; | |
769 | struct operand_alternative *op_alt_start, *op_alt; | |
770 | const char *p = static_data->operand[i].constraint; | |
771 | ||
772 | static_data->operand[i].early_clobber = 0; | |
773 | op_alt_start = &static_data->operand_alternative[i]; | |
774 | ||
775 | for (j = 0; j < nalt; j++) | |
776 | { | |
777 | op_alt = op_alt_start + j * nop; | |
778 | op_alt->cl = NO_REGS; | |
779 | op_alt->constraint = p; | |
780 | op_alt->matches = -1; | |
781 | op_alt->matched = -1; | |
782 | ||
783 | if (*p == '\0' || *p == ',') | |
784 | { | |
785 | op_alt->anything_ok = 1; | |
786 | continue; | |
787 | } | |
788 | ||
789 | for (;;) | |
790 | { | |
791 | char c = *p; | |
792 | if (c == '#') | |
793 | do | |
794 | c = *++p; | |
795 | while (c != ',' && c != '\0'); | |
796 | if (c == ',' || c == '\0') | |
797 | { | |
798 | p++; | |
799 | break; | |
800 | } | |
801 | ||
802 | switch (c) | |
803 | { | |
804 | case '=': case '+': case '*': | |
805 | case 'E': case 'F': case 'G': case 'H': | |
806 | case 's': case 'i': case 'n': | |
807 | case 'I': case 'J': case 'K': case 'L': | |
808 | case 'M': case 'N': case 'O': case 'P': | |
809 | /* These don't say anything we care about. */ | |
810 | break; | |
811 | ||
812 | case '%': | |
813 | /* We currently only support one commutative pair of | |
814 | operands. */ | |
815 | if (static_data->commutative < 0) | |
816 | static_data->commutative = i; | |
817 | else | |
818 | lra_assert (data->icode < 0); /* Asm */ | |
819 | ||
820 | /* The last operand should not be marked | |
821 | commutative. */ | |
822 | lra_assert (i != nop - 1); | |
823 | break; | |
824 | ||
825 | case '?': | |
4b3aba76 | 826 | op_alt->reject += LRA_LOSER_COST_FACTOR; |
c6a6cdaa | 827 | break; |
828 | case '!': | |
4b3aba76 | 829 | op_alt->reject += LRA_MAX_REJECT; |
c6a6cdaa | 830 | break; |
831 | case '&': | |
832 | op_alt->earlyclobber = 1; | |
833 | static_data->operand[i].early_clobber = 1; | |
834 | break; | |
835 | ||
836 | case '0': case '1': case '2': case '3': case '4': | |
837 | case '5': case '6': case '7': case '8': case '9': | |
838 | { | |
839 | char *end; | |
840 | op_alt->matches = strtoul (p, &end, 10); | |
841 | static_data->operand_alternative | |
842 | [j * nop + op_alt->matches].matched = i; | |
843 | p = end; | |
844 | } | |
845 | continue; | |
846 | ||
847 | case TARGET_MEM_CONSTRAINT: | |
848 | op_alt->memory_ok = 1; | |
849 | break; | |
850 | case '<': | |
851 | op_alt->decmem_ok = 1; | |
852 | break; | |
853 | case '>': | |
854 | op_alt->incmem_ok = 1; | |
855 | break; | |
856 | case 'V': | |
857 | op_alt->nonoffmem_ok = 1; | |
858 | break; | |
859 | case 'o': | |
860 | op_alt->offmem_ok = 1; | |
861 | break; | |
862 | case 'X': | |
863 | op_alt->anything_ok = 1; | |
864 | break; | |
865 | ||
866 | case 'p': | |
867 | static_data->operand[i].is_address = true; | |
868 | op_alt->is_address = 1; | |
869 | op_alt->cl = (reg_class_subunion[(int) op_alt->cl] | |
870 | [(int) base_reg_class (VOIDmode, | |
871 | ADDR_SPACE_GENERIC, | |
872 | ADDRESS, SCRATCH)]); | |
873 | break; | |
874 | ||
875 | case 'g': | |
876 | case 'r': | |
877 | op_alt->cl = | |
878 | reg_class_subunion[(int) op_alt->cl][(int) GENERAL_REGS]; | |
879 | break; | |
880 | ||
881 | default: | |
882 | if (EXTRA_MEMORY_CONSTRAINT (c, p)) | |
883 | { | |
884 | op_alt->memory_ok = 1; | |
885 | break; | |
886 | } | |
887 | if (EXTRA_ADDRESS_CONSTRAINT (c, p)) | |
888 | { | |
889 | static_data->operand[i].is_address = true; | |
890 | op_alt->is_address = 1; | |
891 | op_alt->cl | |
892 | = (reg_class_subunion | |
893 | [(int) op_alt->cl] | |
894 | [(int) base_reg_class (VOIDmode, ADDR_SPACE_GENERIC, | |
895 | ADDRESS, SCRATCH)]); | |
896 | break; | |
897 | } | |
898 | ||
899 | op_alt->cl | |
900 | = (reg_class_subunion | |
901 | [(int) op_alt->cl] | |
902 | [(int) | |
903 | REG_CLASS_FROM_CONSTRAINT ((unsigned char) c, p)]); | |
904 | break; | |
905 | } | |
906 | p += CONSTRAINT_LEN (c, p); | |
907 | } | |
908 | } | |
909 | } | |
910 | } | |
911 | ||
912 | /* Recursively process X and collect info about registers, which are | |
913 | not the insn operands, in X with TYPE (in/out/inout) and flag that | |
914 | it is early clobbered in the insn (EARLY_CLOBBER) and add the info | |
915 | to LIST. X is a part of insn given by DATA. Return the result | |
916 | list. */ | |
917 | static struct lra_insn_reg * | |
918 | collect_non_operand_hard_regs (rtx *x, lra_insn_recog_data_t data, | |
919 | struct lra_insn_reg *list, | |
920 | enum op_type type, bool early_clobber) | |
921 | { | |
922 | int i, j, regno, last; | |
923 | bool subreg_p; | |
924 | enum machine_mode mode; | |
925 | struct lra_insn_reg *curr; | |
926 | rtx op = *x; | |
927 | enum rtx_code code = GET_CODE (op); | |
928 | const char *fmt = GET_RTX_FORMAT (code); | |
929 | ||
930 | for (i = 0; i < data->insn_static_data->n_operands; i++) | |
931 | if (x == data->operand_loc[i]) | |
932 | /* It is an operand loc. Stop here. */ | |
933 | return list; | |
934 | for (i = 0; i < data->insn_static_data->n_dups; i++) | |
935 | if (x == data->dup_loc[i]) | |
936 | /* It is a dup loc. Stop here. */ | |
937 | return list; | |
938 | mode = GET_MODE (op); | |
939 | subreg_p = false; | |
940 | if (code == SUBREG) | |
941 | { | |
942 | op = SUBREG_REG (op); | |
943 | code = GET_CODE (op); | |
944 | if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (op))) | |
945 | { | |
946 | mode = GET_MODE (op); | |
947 | if (GET_MODE_SIZE (mode) > REGMODE_NATURAL_SIZE (mode)) | |
948 | subreg_p = true; | |
949 | } | |
950 | } | |
951 | if (REG_P (op)) | |
952 | { | |
953 | if ((regno = REGNO (op)) >= FIRST_PSEUDO_REGISTER) | |
954 | return list; | |
955 | for (last = regno + hard_regno_nregs[regno][mode]; | |
956 | regno < last; | |
957 | regno++) | |
fc8a0f60 | 958 | if (! TEST_HARD_REG_BIT (lra_no_alloc_regs, regno) |
959 | || TEST_HARD_REG_BIT (eliminable_regset, regno)) | |
c6a6cdaa | 960 | { |
961 | for (curr = list; curr != NULL; curr = curr->next) | |
962 | if (curr->regno == regno && curr->subreg_p == subreg_p | |
963 | && curr->biggest_mode == mode) | |
964 | { | |
965 | if (curr->type != type) | |
966 | curr->type = OP_INOUT; | |
967 | if (curr->early_clobber != early_clobber) | |
968 | curr->early_clobber = true; | |
969 | break; | |
970 | } | |
971 | if (curr == NULL) | |
972 | { | |
973 | /* This is a new hard regno or the info can not be | |
974 | integrated into the found structure. */ | |
975 | #ifdef STACK_REGS | |
976 | early_clobber | |
977 | = (early_clobber | |
978 | /* This clobber is to inform popping floating | |
979 | point stack only. */ | |
980 | && ! (FIRST_STACK_REG <= regno | |
981 | && regno <= LAST_STACK_REG)); | |
982 | #endif | |
40cec44a | 983 | list = new_insn_reg (data->insn, regno, type, mode, subreg_p, |
c6a6cdaa | 984 | early_clobber, list); |
985 | } | |
986 | } | |
987 | return list; | |
988 | } | |
989 | switch (code) | |
990 | { | |
991 | case SET: | |
992 | list = collect_non_operand_hard_regs (&SET_DEST (op), data, | |
993 | list, OP_OUT, false); | |
994 | list = collect_non_operand_hard_regs (&SET_SRC (op), data, | |
995 | list, OP_IN, false); | |
996 | break; | |
997 | case CLOBBER: | |
998 | /* We treat clobber of non-operand hard registers as early | |
1a8f8886 | 999 | clobber (the behavior is expected from asm). */ |
c6a6cdaa | 1000 | list = collect_non_operand_hard_regs (&XEXP (op, 0), data, |
1001 | list, OP_OUT, true); | |
1002 | break; | |
1003 | case PRE_INC: case PRE_DEC: case POST_INC: case POST_DEC: | |
1004 | list = collect_non_operand_hard_regs (&XEXP (op, 0), data, | |
1005 | list, OP_INOUT, false); | |
1006 | break; | |
1007 | case PRE_MODIFY: case POST_MODIFY: | |
1008 | list = collect_non_operand_hard_regs (&XEXP (op, 0), data, | |
1009 | list, OP_INOUT, false); | |
1010 | list = collect_non_operand_hard_regs (&XEXP (op, 1), data, | |
1011 | list, OP_IN, false); | |
1012 | break; | |
1013 | default: | |
1014 | fmt = GET_RTX_FORMAT (code); | |
1015 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1016 | { | |
1017 | if (fmt[i] == 'e') | |
1018 | list = collect_non_operand_hard_regs (&XEXP (op, i), data, | |
1019 | list, OP_IN, false); | |
1020 | else if (fmt[i] == 'E') | |
1021 | for (j = XVECLEN (op, i) - 1; j >= 0; j--) | |
1022 | list = collect_non_operand_hard_regs (&XVECEXP (op, i, j), data, | |
1023 | list, OP_IN, false); | |
1024 | } | |
1025 | } | |
1026 | return list; | |
1027 | } | |
1028 | ||
1029 | /* Set up and return info about INSN. Set up the info if it is not set up | |
1030 | yet. */ | |
1031 | lra_insn_recog_data_t | |
1032 | lra_set_insn_recog_data (rtx insn) | |
1033 | { | |
1034 | lra_insn_recog_data_t data; | |
1035 | int i, n, icode; | |
1036 | rtx **locs; | |
1037 | unsigned int uid = INSN_UID (insn); | |
1038 | struct lra_static_insn_data *insn_static_data; | |
1039 | ||
1040 | check_and_expand_insn_recog_data (uid); | |
1041 | if (DEBUG_INSN_P (insn)) | |
1042 | icode = -1; | |
1043 | else | |
1044 | { | |
1045 | icode = INSN_CODE (insn); | |
1046 | if (icode < 0) | |
1047 | /* It might be a new simple insn which is not recognized yet. */ | |
1048 | INSN_CODE (insn) = icode = recog_memoized (insn); | |
1049 | } | |
1050 | data = XNEW (struct lra_insn_recog_data); | |
1051 | lra_insn_recog_data[uid] = data; | |
1052 | data->insn = insn; | |
1053 | data->used_insn_alternative = -1; | |
1054 | data->icode = icode; | |
1055 | data->regs = NULL; | |
1056 | if (DEBUG_INSN_P (insn)) | |
1057 | { | |
1058 | data->insn_static_data = &debug_insn_static_data; | |
1059 | data->dup_loc = NULL; | |
1060 | data->arg_hard_regs = NULL; | |
c6a6cdaa | 1061 | data->alternative_enabled_p = NULL; |
c6a6cdaa | 1062 | data->operand_loc = XNEWVEC (rtx *, 1); |
1063 | data->operand_loc[0] = &INSN_VAR_LOCATION_LOC (insn); | |
1064 | return data; | |
1065 | } | |
1066 | if (icode < 0) | |
1067 | { | |
1068 | int nop; | |
1069 | enum machine_mode operand_mode[MAX_RECOG_OPERANDS]; | |
1070 | const char *constraints[MAX_RECOG_OPERANDS]; | |
1071 | ||
1072 | nop = asm_noperands (PATTERN (insn)); | |
1073 | data->operand_loc = data->dup_loc = NULL; | |
1074 | if (nop < 0) | |
1075 | /* Its is a special insn like USE or CLOBBER. */ | |
1076 | data->insn_static_data = insn_static_data | |
1077 | = get_static_insn_data (-1, 0, 0, 1); | |
1078 | else | |
1079 | { | |
1080 | /* expand_asm_operands makes sure there aren't too many | |
1081 | operands. */ | |
1082 | lra_assert (nop <= MAX_RECOG_OPERANDS); | |
1083 | if (nop != 0) | |
1084 | data->operand_loc = XNEWVEC (rtx *, nop); | |
1085 | /* Now get the operand values and constraints out of the | |
1086 | insn. */ | |
1087 | decode_asm_operands (PATTERN (insn), NULL, | |
1088 | data->operand_loc, | |
1089 | constraints, operand_mode, NULL); | |
1090 | n = 1; | |
1091 | if (nop > 0) | |
1092 | { | |
1093 | const char *p = recog_data.constraints[0]; | |
1a8f8886 | 1094 | |
c6a6cdaa | 1095 | for (p = constraints[0]; *p; p++) |
1096 | n += *p == ','; | |
1097 | } | |
1098 | data->insn_static_data = insn_static_data | |
1099 | = get_static_insn_data (-1, nop, 0, n); | |
1100 | for (i = 0; i < nop; i++) | |
1101 | { | |
1102 | insn_static_data->operand[i].mode = operand_mode[i]; | |
1103 | insn_static_data->operand[i].constraint = constraints[i]; | |
1104 | insn_static_data->operand[i].strict_low = false; | |
1105 | insn_static_data->operand[i].is_operator = false; | |
1106 | insn_static_data->operand[i].is_address = false; | |
1107 | } | |
1108 | } | |
1109 | for (i = 0; i < insn_static_data->n_operands; i++) | |
1110 | insn_static_data->operand[i].type | |
1111 | = (insn_static_data->operand[i].constraint[0] == '=' ? OP_OUT | |
1112 | : insn_static_data->operand[i].constraint[0] == '+' ? OP_INOUT | |
1113 | : OP_IN); | |
c6a6cdaa | 1114 | data->alternative_enabled_p = NULL; |
c6a6cdaa | 1115 | } |
1116 | else | |
1117 | { | |
1118 | insn_extract (insn); | |
1119 | data->insn_static_data = insn_static_data | |
1120 | = get_static_insn_data (icode, insn_data[icode].n_operands, | |
1121 | insn_data[icode].n_dups, | |
1122 | insn_data[icode].n_alternatives); | |
1123 | n = insn_static_data->n_operands; | |
1124 | if (n == 0) | |
1125 | locs = NULL; | |
1126 | else | |
1127 | { | |
1128 | locs = XNEWVEC (rtx *, n); | |
1129 | memcpy (locs, recog_data.operand_loc, n * sizeof (rtx *)); | |
1130 | } | |
1131 | data->operand_loc = locs; | |
1132 | n = insn_static_data->n_dups; | |
1133 | if (n == 0) | |
1134 | locs = NULL; | |
1135 | else | |
1136 | { | |
1137 | locs = XNEWVEC (rtx *, n); | |
1138 | memcpy (locs, recog_data.dup_loc, n * sizeof (rtx *)); | |
1139 | } | |
1140 | data->dup_loc = locs; | |
f2d92d7a | 1141 | if (HAVE_ATTR_enabled) |
1142 | { | |
1143 | bool *bp; | |
1144 | ||
1145 | n = insn_static_data->n_alternatives; | |
1146 | lra_assert (n >= 0); | |
1147 | data->alternative_enabled_p = bp = XNEWVEC (bool, n); | |
1148 | /* Cache the insn because we don't want to call extract_insn | |
1149 | from get_attr_enabled as extract_insn modifies | |
1150 | which_alternative. The attribute enabled should not depend | |
1151 | on insn operands, operand modes, operand types, and operand | |
1152 | constraints. It should depend on the architecture. If it | |
1153 | is not true, we should rewrite this file code to use | |
1154 | extract_insn instead of less expensive insn_extract. */ | |
1155 | recog_data.insn = insn; | |
1156 | for (i = 0; i < n; i++) | |
1157 | { | |
1158 | which_alternative = i; | |
1159 | bp[i] = get_attr_enabled (insn); | |
1160 | } | |
1161 | } | |
c6a6cdaa | 1162 | } |
1163 | if (GET_CODE (PATTERN (insn)) == CLOBBER || GET_CODE (PATTERN (insn)) == USE) | |
1164 | insn_static_data->hard_regs = NULL; | |
1165 | else | |
1166 | insn_static_data->hard_regs | |
1167 | = collect_non_operand_hard_regs (&PATTERN (insn), data, | |
1168 | NULL, OP_IN, false); | |
1169 | setup_operand_alternative (data); | |
1170 | data->arg_hard_regs = NULL; | |
1171 | if (CALL_P (insn)) | |
1172 | { | |
1173 | rtx link; | |
1174 | int n_hard_regs, regno, arg_hard_regs[FIRST_PSEUDO_REGISTER]; | |
1175 | ||
1176 | n_hard_regs = 0; | |
1177 | /* Finding implicit hard register usage. We believe it will be | |
1178 | not changed whatever transformations are used. Call insns | |
1179 | are such example. */ | |
1180 | for (link = CALL_INSN_FUNCTION_USAGE (insn); | |
1181 | link != NULL_RTX; | |
1182 | link = XEXP (link, 1)) | |
1183 | if (GET_CODE (XEXP (link, 0)) == USE | |
1184 | && REG_P (XEXP (XEXP (link, 0), 0))) | |
1185 | { | |
1186 | regno = REGNO (XEXP (XEXP (link, 0), 0)); | |
1187 | lra_assert (regno < FIRST_PSEUDO_REGISTER); | |
1188 | /* It is an argument register. */ | |
1189 | for (i = (hard_regno_nregs | |
1190 | [regno][GET_MODE (XEXP (XEXP (link, 0), 0))]) - 1; | |
1191 | i >= 0; | |
1192 | i--) | |
1193 | arg_hard_regs[n_hard_regs++] = regno + i; | |
1194 | } | |
1195 | if (n_hard_regs != 0) | |
1196 | { | |
1197 | arg_hard_regs[n_hard_regs++] = -1; | |
1198 | data->arg_hard_regs = XNEWVEC (int, n_hard_regs); | |
1199 | memcpy (data->arg_hard_regs, arg_hard_regs, | |
1200 | sizeof (int) * n_hard_regs); | |
1201 | } | |
1202 | } | |
1203 | /* Some output operand can be recognized only from the context not | |
1204 | from the constraints which are empty in this case. Call insn may | |
1205 | contain a hard register in set destination with empty constraint | |
1206 | and extract_insn treats them as an input. */ | |
1207 | for (i = 0; i < insn_static_data->n_operands; i++) | |
1208 | { | |
1209 | int j; | |
1210 | rtx pat, set; | |
1211 | struct lra_operand_data *operand = &insn_static_data->operand[i]; | |
1212 | ||
1213 | /* ??? Should we treat 'X' the same way. It looks to me that | |
1214 | 'X' means anything and empty constraint means we do not | |
1215 | care. */ | |
1216 | if (operand->type != OP_IN || *operand->constraint != '\0' | |
1217 | || operand->is_operator) | |
1218 | continue; | |
1219 | pat = PATTERN (insn); | |
1220 | if (GET_CODE (pat) == SET) | |
1221 | { | |
1222 | if (data->operand_loc[i] != &SET_DEST (pat)) | |
1223 | continue; | |
1224 | } | |
1225 | else if (GET_CODE (pat) == PARALLEL) | |
1226 | { | |
1227 | for (j = XVECLEN (pat, 0) - 1; j >= 0; j--) | |
1228 | { | |
1229 | set = XVECEXP (PATTERN (insn), 0, j); | |
1230 | if (GET_CODE (set) == SET | |
1231 | && &SET_DEST (set) == data->operand_loc[i]) | |
1232 | break; | |
1233 | } | |
1234 | if (j < 0) | |
1235 | continue; | |
1236 | } | |
1237 | else | |
1238 | continue; | |
1239 | operand->type = OP_OUT; | |
1240 | } | |
1241 | return data; | |
1242 | } | |
1243 | ||
1244 | /* Return info about insn give by UID. The info should be already set | |
1245 | up. */ | |
1246 | static lra_insn_recog_data_t | |
1247 | get_insn_recog_data_by_uid (int uid) | |
1248 | { | |
1249 | lra_insn_recog_data_t data; | |
1250 | ||
1251 | data = lra_insn_recog_data[uid]; | |
1252 | lra_assert (data != NULL); | |
1253 | return data; | |
1254 | } | |
1255 | ||
1256 | /* Invalidate all info about insn given by its UID. */ | |
1257 | static void | |
1258 | invalidate_insn_recog_data (int uid) | |
1259 | { | |
1260 | lra_insn_recog_data_t data; | |
1261 | ||
1262 | data = lra_insn_recog_data[uid]; | |
1263 | lra_assert (data != NULL); | |
1264 | free_insn_recog_data (data); | |
1265 | lra_insn_recog_data[uid] = NULL; | |
1266 | } | |
1267 | ||
1268 | /* Update all the insn info about INSN. It is usually called when | |
1269 | something in the insn was changed. Return the updated info. */ | |
1270 | lra_insn_recog_data_t | |
1271 | lra_update_insn_recog_data (rtx insn) | |
1272 | { | |
1273 | lra_insn_recog_data_t data; | |
1274 | int n; | |
1275 | unsigned int uid = INSN_UID (insn); | |
1276 | struct lra_static_insn_data *insn_static_data; | |
3b3a5e5f | 1277 | HOST_WIDE_INT sp_offset = 0; |
1a8f8886 | 1278 | |
c6a6cdaa | 1279 | check_and_expand_insn_recog_data (uid); |
1280 | if ((data = lra_insn_recog_data[uid]) != NULL | |
1281 | && data->icode != INSN_CODE (insn)) | |
1282 | { | |
3b3a5e5f | 1283 | sp_offset = data->sp_offset; |
c6a6cdaa | 1284 | invalidate_insn_data_regno_info (data, insn, get_insn_freq (insn)); |
1285 | invalidate_insn_recog_data (uid); | |
1286 | data = NULL; | |
1287 | } | |
1288 | if (data == NULL) | |
3b3a5e5f | 1289 | { |
1290 | data = lra_get_insn_recog_data (insn); | |
1291 | /* Initiate or restore SP offset. */ | |
1292 | data->sp_offset = sp_offset; | |
1293 | return data; | |
1294 | } | |
c6a6cdaa | 1295 | insn_static_data = data->insn_static_data; |
1296 | data->used_insn_alternative = -1; | |
1297 | if (DEBUG_INSN_P (insn)) | |
1298 | return data; | |
1299 | if (data->icode < 0) | |
1300 | { | |
1301 | int nop; | |
1302 | enum machine_mode operand_mode[MAX_RECOG_OPERANDS]; | |
1303 | const char *constraints[MAX_RECOG_OPERANDS]; | |
1304 | ||
1305 | nop = asm_noperands (PATTERN (insn)); | |
1306 | if (nop >= 0) | |
1307 | { | |
1308 | lra_assert (nop == data->insn_static_data->n_operands); | |
1309 | /* Now get the operand values and constraints out of the | |
1310 | insn. */ | |
1311 | decode_asm_operands (PATTERN (insn), NULL, | |
1312 | data->operand_loc, | |
1313 | constraints, operand_mode, NULL); | |
1314 | #ifdef ENABLE_CHECKING | |
1315 | { | |
1316 | int i; | |
1317 | ||
1318 | for (i = 0; i < nop; i++) | |
1319 | lra_assert | |
1320 | (insn_static_data->operand[i].mode == operand_mode[i] | |
1321 | && insn_static_data->operand[i].constraint == constraints[i] | |
1322 | && ! insn_static_data->operand[i].is_operator); | |
1323 | } | |
1324 | #endif | |
1325 | } | |
1326 | #ifdef ENABLE_CHECKING | |
1327 | { | |
1328 | int i; | |
1329 | ||
1330 | for (i = 0; i < insn_static_data->n_operands; i++) | |
1331 | lra_assert | |
1332 | (insn_static_data->operand[i].type | |
1333 | == (insn_static_data->operand[i].constraint[0] == '=' ? OP_OUT | |
1334 | : insn_static_data->operand[i].constraint[0] == '+' ? OP_INOUT | |
1335 | : OP_IN)); | |
1336 | } | |
1337 | #endif | |
1338 | } | |
1339 | else | |
1340 | { | |
1341 | insn_extract (insn); | |
1342 | n = insn_static_data->n_operands; | |
1343 | if (n != 0) | |
1344 | memcpy (data->operand_loc, recog_data.operand_loc, n * sizeof (rtx *)); | |
1345 | n = insn_static_data->n_dups; | |
1346 | if (n != 0) | |
1347 | memcpy (data->dup_loc, recog_data.dup_loc, n * sizeof (rtx *)); | |
f2d92d7a | 1348 | #if HAVE_ATTR_enabled |
c6a6cdaa | 1349 | #ifdef ENABLE_CHECKING |
1350 | { | |
1351 | int i; | |
1352 | bool *bp; | |
1a8f8886 | 1353 | |
c6a6cdaa | 1354 | n = insn_static_data->n_alternatives; |
1355 | bp = data->alternative_enabled_p; | |
1356 | lra_assert (n >= 0 && bp != NULL); | |
1357 | /* Cache the insn to prevent extract_insn call from | |
1358 | get_attr_enabled. */ | |
1359 | recog_data.insn = insn; | |
1360 | for (i = 0; i < n; i++) | |
1361 | { | |
1362 | which_alternative = i; | |
1363 | lra_assert (bp[i] == get_attr_enabled (insn)); | |
1364 | } | |
1365 | } | |
1366 | #endif | |
1367 | #endif | |
1368 | } | |
1369 | return data; | |
1370 | } | |
1371 | ||
1372 | /* Set up that INSN is using alternative ALT now. */ | |
1373 | void | |
1374 | lra_set_used_insn_alternative (rtx insn, int alt) | |
1375 | { | |
1376 | lra_insn_recog_data_t data; | |
1377 | ||
1378 | data = lra_get_insn_recog_data (insn); | |
1379 | data->used_insn_alternative = alt; | |
1380 | } | |
1381 | ||
1382 | /* Set up that insn with UID is using alternative ALT now. The insn | |
1383 | info should be already set up. */ | |
1384 | void | |
1385 | lra_set_used_insn_alternative_by_uid (int uid, int alt) | |
1386 | { | |
1387 | lra_insn_recog_data_t data; | |
1388 | ||
1389 | check_and_expand_insn_recog_data (uid); | |
1390 | data = lra_insn_recog_data[uid]; | |
1391 | lra_assert (data != NULL); | |
1392 | data->used_insn_alternative = alt; | |
1393 | } | |
1394 | ||
1395 | \f | |
1396 | ||
1397 | /* This page contains code dealing with common register info and | |
1398 | pseudo copies. */ | |
1399 | ||
1400 | /* The size of the following array. */ | |
1401 | static int reg_info_size; | |
1402 | /* Common info about each register. */ | |
1403 | struct lra_reg *lra_reg_info; | |
1404 | ||
1405 | /* Last register value. */ | |
1406 | static int last_reg_value; | |
1407 | ||
1408 | /* Return new register value. */ | |
1409 | static int | |
1410 | get_new_reg_value (void) | |
1411 | { | |
1412 | return ++last_reg_value; | |
1413 | } | |
1414 | ||
1415 | /* Pools for copies. */ | |
1416 | static alloc_pool copy_pool; | |
1417 | ||
c6a6cdaa | 1418 | /* Vec referring to pseudo copies. */ |
f1f41a6c | 1419 | static vec<lra_copy_t> copy_vec; |
c6a6cdaa | 1420 | |
1421 | /* Initialize I-th element of lra_reg_info. */ | |
1422 | static inline void | |
1423 | initialize_lra_reg_info_element (int i) | |
1424 | { | |
1425 | bitmap_initialize (&lra_reg_info[i].insn_bitmap, ®_obstack); | |
1426 | #ifdef STACK_REGS | |
1427 | lra_reg_info[i].no_stack_p = false; | |
1428 | #endif | |
1429 | CLEAR_HARD_REG_SET (lra_reg_info[i].conflict_hard_regs); | |
1430 | lra_reg_info[i].preferred_hard_regno1 = -1; | |
1431 | lra_reg_info[i].preferred_hard_regno2 = -1; | |
1432 | lra_reg_info[i].preferred_hard_regno_profit1 = 0; | |
1433 | lra_reg_info[i].preferred_hard_regno_profit2 = 0; | |
fc8a0f60 | 1434 | lra_reg_info[i].biggest_mode = VOIDmode; |
c6a6cdaa | 1435 | lra_reg_info[i].live_ranges = NULL; |
1436 | lra_reg_info[i].nrefs = lra_reg_info[i].freq = 0; | |
1437 | lra_reg_info[i].last_reload = 0; | |
1438 | lra_reg_info[i].restore_regno = -1; | |
1439 | lra_reg_info[i].val = get_new_reg_value (); | |
a1064490 | 1440 | lra_reg_info[i].offset = 0; |
c6a6cdaa | 1441 | lra_reg_info[i].copies = NULL; |
1442 | } | |
1443 | ||
1444 | /* Initialize common reg info and copies. */ | |
1445 | static void | |
1446 | init_reg_info (void) | |
1447 | { | |
1448 | int i; | |
1449 | ||
1450 | last_reg_value = 0; | |
1451 | reg_info_size = max_reg_num () * 3 / 2 + 1; | |
1452 | lra_reg_info = XNEWVEC (struct lra_reg, reg_info_size); | |
1453 | for (i = 0; i < reg_info_size; i++) | |
1454 | initialize_lra_reg_info_element (i); | |
1455 | copy_pool | |
1456 | = create_alloc_pool ("lra copies", sizeof (struct lra_copy), 100); | |
f1f41a6c | 1457 | copy_vec.create (100); |
c6a6cdaa | 1458 | } |
1459 | ||
1460 | ||
1461 | /* Finish common reg info and copies. */ | |
1462 | static void | |
1463 | finish_reg_info (void) | |
1464 | { | |
1465 | int i; | |
1466 | ||
1467 | for (i = 0; i < reg_info_size; i++) | |
1468 | bitmap_clear (&lra_reg_info[i].insn_bitmap); | |
1469 | free (lra_reg_info); | |
1470 | reg_info_size = 0; | |
1471 | free_alloc_pool (copy_pool); | |
f1f41a6c | 1472 | copy_vec.release (); |
c6a6cdaa | 1473 | } |
1474 | ||
1475 | /* Expand common reg info if it is necessary. */ | |
1476 | static void | |
1477 | expand_reg_info (void) | |
1478 | { | |
1479 | int i, old = reg_info_size; | |
1480 | ||
1481 | if (reg_info_size > max_reg_num ()) | |
1482 | return; | |
1483 | reg_info_size = max_reg_num () * 3 / 2 + 1; | |
1484 | lra_reg_info = XRESIZEVEC (struct lra_reg, lra_reg_info, reg_info_size); | |
1485 | for (i = old; i < reg_info_size; i++) | |
1486 | initialize_lra_reg_info_element (i); | |
1487 | } | |
1488 | ||
1489 | /* Free all copies. */ | |
1490 | void | |
1491 | lra_free_copies (void) | |
1492 | { | |
1493 | lra_copy_t cp; | |
1494 | ||
f1f41a6c | 1495 | while (copy_vec.length () != 0) |
c6a6cdaa | 1496 | { |
f1f41a6c | 1497 | cp = copy_vec.pop (); |
c6a6cdaa | 1498 | lra_reg_info[cp->regno1].copies = lra_reg_info[cp->regno2].copies = NULL; |
1499 | pool_free (copy_pool, cp); | |
1500 | } | |
1501 | } | |
1502 | ||
1503 | /* Create copy of two pseudos REGNO1 and REGNO2. The copy execution | |
1504 | frequency is FREQ. */ | |
1505 | void | |
1506 | lra_create_copy (int regno1, int regno2, int freq) | |
1507 | { | |
1508 | bool regno1_dest_p; | |
1509 | lra_copy_t cp; | |
1510 | ||
1511 | lra_assert (regno1 != regno2); | |
1512 | regno1_dest_p = true; | |
1513 | if (regno1 > regno2) | |
1514 | { | |
1515 | int temp = regno2; | |
1516 | ||
1517 | regno1_dest_p = false; | |
1518 | regno2 = regno1; | |
1519 | regno1 = temp; | |
1520 | } | |
1521 | cp = (lra_copy_t) pool_alloc (copy_pool); | |
f1f41a6c | 1522 | copy_vec.safe_push (cp); |
c6a6cdaa | 1523 | cp->regno1_dest_p = regno1_dest_p; |
1524 | cp->freq = freq; | |
1525 | cp->regno1 = regno1; | |
1526 | cp->regno2 = regno2; | |
1527 | cp->regno1_next = lra_reg_info[regno1].copies; | |
1528 | lra_reg_info[regno1].copies = cp; | |
1529 | cp->regno2_next = lra_reg_info[regno2].copies; | |
1530 | lra_reg_info[regno2].copies = cp; | |
1531 | if (lra_dump_file != NULL) | |
1532 | fprintf (lra_dump_file, " Creating copy r%d%sr%d@%d\n", | |
1533 | regno1, regno1_dest_p ? "<-" : "->", regno2, freq); | |
1534 | } | |
1535 | ||
1536 | /* Return N-th (0, 1, ...) copy. If there is no copy, return | |
1537 | NULL. */ | |
1538 | lra_copy_t | |
1539 | lra_get_copy (int n) | |
1540 | { | |
f1f41a6c | 1541 | if (n >= (int) copy_vec.length ()) |
c6a6cdaa | 1542 | return NULL; |
f1f41a6c | 1543 | return copy_vec[n]; |
c6a6cdaa | 1544 | } |
1545 | ||
1546 | \f | |
1547 | ||
1548 | /* This page contains code dealing with info about registers in | |
1549 | insns. */ | |
1550 | ||
1551 | /* Process X of insn UID recursively and add info (operand type is | |
1552 | given by TYPE, flag of that it is early clobber is EARLY_CLOBBER) | |
1553 | about registers in X to the insn DATA. */ | |
1554 | static void | |
1555 | add_regs_to_insn_regno_info (lra_insn_recog_data_t data, rtx x, int uid, | |
1556 | enum op_type type, bool early_clobber) | |
1557 | { | |
1558 | int i, j, regno; | |
1559 | bool subreg_p; | |
1560 | enum machine_mode mode; | |
1561 | const char *fmt; | |
1562 | enum rtx_code code; | |
1563 | struct lra_insn_reg *curr; | |
1564 | ||
1565 | code = GET_CODE (x); | |
1566 | mode = GET_MODE (x); | |
1567 | subreg_p = false; | |
1568 | if (GET_CODE (x) == SUBREG) | |
1569 | { | |
1570 | x = SUBREG_REG (x); | |
1571 | code = GET_CODE (x); | |
1572 | if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))) | |
1573 | { | |
1574 | mode = GET_MODE (x); | |
1575 | if (GET_MODE_SIZE (mode) > REGMODE_NATURAL_SIZE (mode)) | |
1576 | subreg_p = true; | |
1577 | } | |
1578 | } | |
1579 | if (REG_P (x)) | |
1580 | { | |
1581 | regno = REGNO (x); | |
fc8a0f60 | 1582 | if (regno < FIRST_PSEUDO_REGISTER |
1583 | && TEST_HARD_REG_BIT (lra_no_alloc_regs, regno) | |
1584 | && ! TEST_HARD_REG_BIT (eliminable_regset, regno)) | |
1585 | return; | |
c6a6cdaa | 1586 | expand_reg_info (); |
1587 | if (bitmap_set_bit (&lra_reg_info[regno].insn_bitmap, uid)) | |
1588 | { | |
40cec44a | 1589 | data->regs = new_insn_reg (data->insn, regno, type, mode, subreg_p, |
c6a6cdaa | 1590 | early_clobber, data->regs); |
1591 | return; | |
1592 | } | |
1593 | else | |
1594 | { | |
1595 | for (curr = data->regs; curr != NULL; curr = curr->next) | |
1596 | if (curr->regno == regno) | |
1597 | { | |
1598 | if (curr->subreg_p != subreg_p || curr->biggest_mode != mode) | |
1599 | /* The info can not be integrated into the found | |
1600 | structure. */ | |
40cec44a | 1601 | data->regs = new_insn_reg (data->insn, regno, type, mode, |
1602 | subreg_p, early_clobber, | |
1603 | data->regs); | |
c6a6cdaa | 1604 | else |
1605 | { | |
1606 | if (curr->type != type) | |
1607 | curr->type = OP_INOUT; | |
1608 | if (curr->early_clobber != early_clobber) | |
1609 | curr->early_clobber = true; | |
1610 | } | |
1611 | return; | |
1612 | } | |
1613 | gcc_unreachable (); | |
1614 | } | |
1615 | } | |
1616 | ||
1617 | switch (code) | |
1618 | { | |
1619 | case SET: | |
1620 | add_regs_to_insn_regno_info (data, SET_DEST (x), uid, OP_OUT, false); | |
1621 | add_regs_to_insn_regno_info (data, SET_SRC (x), uid, OP_IN, false); | |
1622 | break; | |
1623 | case CLOBBER: | |
1624 | /* We treat clobber of non-operand hard registers as early | |
1a8f8886 | 1625 | clobber (the behavior is expected from asm). */ |
c6a6cdaa | 1626 | add_regs_to_insn_regno_info (data, XEXP (x, 0), uid, OP_OUT, true); |
1627 | break; | |
1628 | case PRE_INC: case PRE_DEC: case POST_INC: case POST_DEC: | |
1629 | add_regs_to_insn_regno_info (data, XEXP (x, 0), uid, OP_INOUT, false); | |
1630 | break; | |
1631 | case PRE_MODIFY: case POST_MODIFY: | |
1632 | add_regs_to_insn_regno_info (data, XEXP (x, 0), uid, OP_INOUT, false); | |
1633 | add_regs_to_insn_regno_info (data, XEXP (x, 1), uid, OP_IN, false); | |
1634 | break; | |
1635 | default: | |
1636 | if ((code != PARALLEL && code != EXPR_LIST) || type != OP_OUT) | |
1637 | /* Some targets place small structures in registers for return | |
1638 | values of functions, and those registers are wrapped in | |
1639 | PARALLEL that we may see as the destination of a SET. Here | |
1640 | is an example: | |
1641 | ||
1642 | (call_insn 13 12 14 2 (set (parallel:BLK [ | |
1643 | (expr_list:REG_DEP_TRUE (reg:DI 0 ax) | |
1644 | (const_int 0 [0])) | |
1645 | (expr_list:REG_DEP_TRUE (reg:DI 1 dx) | |
1646 | (const_int 8 [0x8])) | |
1647 | ]) | |
1648 | (call (mem:QI (symbol_ref:DI (... */ | |
1649 | type = OP_IN; | |
1650 | fmt = GET_RTX_FORMAT (code); | |
1651 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1652 | { | |
1653 | if (fmt[i] == 'e') | |
1654 | add_regs_to_insn_regno_info (data, XEXP (x, i), uid, type, false); | |
1655 | else if (fmt[i] == 'E') | |
1656 | { | |
1657 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
1658 | add_regs_to_insn_regno_info (data, XVECEXP (x, i, j), uid, | |
1659 | type, false); | |
1660 | } | |
1661 | } | |
1662 | } | |
1663 | } | |
1664 | ||
1665 | /* Return execution frequency of INSN. */ | |
1666 | static int | |
1667 | get_insn_freq (rtx insn) | |
1668 | { | |
91f71fa3 | 1669 | basic_block bb = BLOCK_FOR_INSN (insn); |
c6a6cdaa | 1670 | |
91f71fa3 | 1671 | gcc_checking_assert (bb != NULL); |
1672 | return REG_FREQ_FROM_BB (bb); | |
c6a6cdaa | 1673 | } |
1674 | ||
1675 | /* Invalidate all reg info of INSN with DATA and execution frequency | |
1676 | FREQ. Update common info about the invalidated registers. */ | |
1677 | static void | |
1678 | invalidate_insn_data_regno_info (lra_insn_recog_data_t data, rtx insn, | |
1679 | int freq) | |
1680 | { | |
1681 | int uid; | |
1682 | bool debug_p; | |
1683 | unsigned int i; | |
1684 | struct lra_insn_reg *ir, *next_ir; | |
1685 | ||
1686 | uid = INSN_UID (insn); | |
1687 | debug_p = DEBUG_INSN_P (insn); | |
1688 | for (ir = data->regs; ir != NULL; ir = next_ir) | |
1689 | { | |
1690 | i = ir->regno; | |
1691 | next_ir = ir->next; | |
1692 | free_insn_reg (ir); | |
1693 | bitmap_clear_bit (&lra_reg_info[i].insn_bitmap, uid); | |
1694 | if (i >= FIRST_PSEUDO_REGISTER && ! debug_p) | |
1695 | { | |
1696 | lra_reg_info[i].nrefs--; | |
1697 | lra_reg_info[i].freq -= freq; | |
1698 | lra_assert (lra_reg_info[i].nrefs >= 0 && lra_reg_info[i].freq >= 0); | |
1699 | } | |
1700 | } | |
1701 | data->regs = NULL; | |
1702 | } | |
1703 | ||
1704 | /* Invalidate all reg info of INSN. Update common info about the | |
1705 | invalidated registers. */ | |
1706 | void | |
1707 | lra_invalidate_insn_regno_info (rtx insn) | |
1708 | { | |
1709 | invalidate_insn_data_regno_info (lra_get_insn_recog_data (insn), insn, | |
1710 | get_insn_freq (insn)); | |
1711 | } | |
1712 | ||
1713 | /* Update common reg info from reg info of insn given by its DATA and | |
1714 | execution frequency FREQ. */ | |
1715 | static void | |
1716 | setup_insn_reg_info (lra_insn_recog_data_t data, int freq) | |
1717 | { | |
1718 | unsigned int i; | |
1719 | struct lra_insn_reg *ir; | |
1720 | ||
1721 | for (ir = data->regs; ir != NULL; ir = ir->next) | |
1722 | if ((i = ir->regno) >= FIRST_PSEUDO_REGISTER) | |
1723 | { | |
1724 | lra_reg_info[i].nrefs++; | |
1725 | lra_reg_info[i].freq += freq; | |
1726 | } | |
1727 | } | |
1728 | ||
1729 | /* Set up insn reg info of INSN. Update common reg info from reg info | |
1730 | of INSN. */ | |
1731 | void | |
1732 | lra_update_insn_regno_info (rtx insn) | |
1733 | { | |
1734 | int i, uid, freq; | |
1735 | lra_insn_recog_data_t data; | |
1736 | struct lra_static_insn_data *static_data; | |
1737 | enum rtx_code code; | |
1738 | ||
1739 | if (! INSN_P (insn)) | |
1740 | return; | |
1741 | data = lra_get_insn_recog_data (insn); | |
1742 | static_data = data->insn_static_data; | |
1743 | freq = get_insn_freq (insn); | |
1744 | invalidate_insn_data_regno_info (data, insn, freq); | |
1745 | uid = INSN_UID (insn); | |
1746 | for (i = static_data->n_operands - 1; i >= 0; i--) | |
1747 | add_regs_to_insn_regno_info (data, *data->operand_loc[i], uid, | |
1748 | static_data->operand[i].type, | |
1749 | static_data->operand[i].early_clobber); | |
1750 | if ((code = GET_CODE (PATTERN (insn))) == CLOBBER || code == USE) | |
1751 | add_regs_to_insn_regno_info (data, XEXP (PATTERN (insn), 0), uid, | |
1752 | code == USE ? OP_IN : OP_OUT, false); | |
1753 | if (NONDEBUG_INSN_P (insn)) | |
1754 | setup_insn_reg_info (data, freq); | |
1755 | } | |
1756 | ||
1757 | /* Return reg info of insn given by it UID. */ | |
1758 | struct lra_insn_reg * | |
1759 | lra_get_insn_regs (int uid) | |
1760 | { | |
1761 | lra_insn_recog_data_t data; | |
1762 | ||
1763 | data = get_insn_recog_data_by_uid (uid); | |
1764 | return data->regs; | |
1765 | } | |
1766 | ||
1767 | \f | |
1768 | ||
1769 | /* This page contains code dealing with stack of the insns which | |
1770 | should be processed by the next constraint pass. */ | |
1771 | ||
1772 | /* Bitmap used to put an insn on the stack only in one exemplar. */ | |
1773 | static sbitmap lra_constraint_insn_stack_bitmap; | |
1774 | ||
1775 | /* The stack itself. */ | |
f1f41a6c | 1776 | vec<rtx> lra_constraint_insn_stack; |
c6a6cdaa | 1777 | |
1778 | /* Put INSN on the stack. If ALWAYS_UPDATE is true, always update the reg | |
1779 | info for INSN, otherwise only update it if INSN is not already on the | |
1780 | stack. */ | |
1781 | static inline void | |
1782 | lra_push_insn_1 (rtx insn, bool always_update) | |
1783 | { | |
1784 | unsigned int uid = INSN_UID (insn); | |
1785 | if (always_update) | |
1786 | lra_update_insn_regno_info (insn); | |
1787 | if (uid >= SBITMAP_SIZE (lra_constraint_insn_stack_bitmap)) | |
1788 | lra_constraint_insn_stack_bitmap = | |
1789 | sbitmap_resize (lra_constraint_insn_stack_bitmap, 3 * uid / 2, 0); | |
08b7917c | 1790 | if (bitmap_bit_p (lra_constraint_insn_stack_bitmap, uid)) |
c6a6cdaa | 1791 | return; |
08b7917c | 1792 | bitmap_set_bit (lra_constraint_insn_stack_bitmap, uid); |
c6a6cdaa | 1793 | if (! always_update) |
1794 | lra_update_insn_regno_info (insn); | |
f1f41a6c | 1795 | lra_constraint_insn_stack.safe_push (insn); |
c6a6cdaa | 1796 | } |
1797 | ||
1798 | /* Put INSN on the stack. */ | |
1799 | void | |
1800 | lra_push_insn (rtx insn) | |
1801 | { | |
1802 | lra_push_insn_1 (insn, false); | |
1803 | } | |
1804 | ||
1805 | /* Put INSN on the stack and update its reg info. */ | |
1806 | void | |
1807 | lra_push_insn_and_update_insn_regno_info (rtx insn) | |
1808 | { | |
1809 | lra_push_insn_1 (insn, true); | |
1810 | } | |
1811 | ||
1812 | /* Put insn with UID on the stack. */ | |
1813 | void | |
1814 | lra_push_insn_by_uid (unsigned int uid) | |
1815 | { | |
1816 | lra_push_insn (lra_insn_recog_data[uid]->insn); | |
1817 | } | |
1818 | ||
1819 | /* Take the last-inserted insns off the stack and return it. */ | |
1820 | rtx | |
1821 | lra_pop_insn (void) | |
1822 | { | |
f1f41a6c | 1823 | rtx insn = lra_constraint_insn_stack.pop (); |
08b7917c | 1824 | bitmap_clear_bit (lra_constraint_insn_stack_bitmap, INSN_UID (insn)); |
c6a6cdaa | 1825 | return insn; |
1826 | } | |
1827 | ||
1828 | /* Return the current size of the insn stack. */ | |
1829 | unsigned int | |
1830 | lra_insn_stack_length (void) | |
1831 | { | |
f1f41a6c | 1832 | return lra_constraint_insn_stack.length (); |
c6a6cdaa | 1833 | } |
1834 | ||
1835 | /* Push insns FROM to TO (excluding it) going in reverse order. */ | |
1836 | static void | |
1837 | push_insns (rtx from, rtx to) | |
1838 | { | |
1839 | rtx insn; | |
1840 | ||
1841 | if (from == NULL_RTX) | |
1842 | return; | |
1843 | for (insn = from; insn != to; insn = PREV_INSN (insn)) | |
1844 | if (INSN_P (insn)) | |
1845 | lra_push_insn (insn); | |
1846 | } | |
1847 | ||
3b3a5e5f | 1848 | /* Set up sp offset for insn in range [FROM, LAST]. The offset is |
1849 | taken from the next BB insn after LAST or zero if there in such | |
1850 | insn. */ | |
1851 | static void | |
1852 | setup_sp_offset (rtx from, rtx last) | |
1853 | { | |
1854 | rtx before = next_nonnote_insn_bb (last); | |
1855 | HOST_WIDE_INT offset = (before == NULL_RTX || ! INSN_P (before) | |
1856 | ? 0 : lra_get_insn_recog_data (before)->sp_offset); | |
1857 | ||
1858 | for (rtx insn = from; insn != NEXT_INSN (last); insn = NEXT_INSN (insn)) | |
1859 | lra_get_insn_recog_data (insn)->sp_offset = offset; | |
1860 | } | |
1861 | ||
c6a6cdaa | 1862 | /* Emit insns BEFORE before INSN and insns AFTER after INSN. Put the |
1863 | insns onto the stack. Print about emitting the insns with | |
1864 | TITLE. */ | |
1865 | void | |
1866 | lra_process_new_insns (rtx insn, rtx before, rtx after, const char *title) | |
1867 | { | |
1868 | rtx last; | |
1869 | ||
3b3a5e5f | 1870 | if (before == NULL_RTX && after == NULL_RTX) |
1871 | return; | |
1872 | if (lra_dump_file != NULL) | |
c6a6cdaa | 1873 | { |
6dde9719 | 1874 | dump_insn_slim (lra_dump_file, insn); |
c6a6cdaa | 1875 | if (before != NULL_RTX) |
1876 | { | |
1877 | fprintf (lra_dump_file," %s before:\n", title); | |
6dde9719 | 1878 | dump_rtl_slim (lra_dump_file, before, NULL_RTX, -1, 0); |
c6a6cdaa | 1879 | } |
1880 | if (after != NULL_RTX) | |
1881 | { | |
1882 | fprintf (lra_dump_file, " %s after:\n", title); | |
6dde9719 | 1883 | dump_rtl_slim (lra_dump_file, after, NULL_RTX, -1, 0); |
c6a6cdaa | 1884 | } |
1885 | fprintf (lra_dump_file, "\n"); | |
1886 | } | |
1887 | if (before != NULL_RTX) | |
1888 | { | |
1889 | emit_insn_before (before, insn); | |
1890 | push_insns (PREV_INSN (insn), PREV_INSN (before)); | |
3b3a5e5f | 1891 | setup_sp_offset (before, PREV_INSN (insn)); |
c6a6cdaa | 1892 | } |
1893 | if (after != NULL_RTX) | |
1894 | { | |
1895 | for (last = after; NEXT_INSN (last) != NULL_RTX; last = NEXT_INSN (last)) | |
1896 | ; | |
1897 | emit_insn_after (after, insn); | |
1898 | push_insns (last, insn); | |
3b3a5e5f | 1899 | setup_sp_offset (after, last); |
c6a6cdaa | 1900 | } |
1901 | } | |
1902 | ||
1903 | \f | |
1904 | ||
1905 | /* This page contains code dealing with scratches (changing them onto | |
1906 | pseudos and restoring them from the pseudos). | |
1907 | ||
1908 | We change scratches into pseudos at the beginning of LRA to | |
1909 | simplify dealing with them (conflicts, hard register assignments). | |
1910 | ||
1911 | If the pseudo denoting scratch was spilled it means that we do need | |
1912 | a hard register for it. Such pseudos are transformed back to | |
1913 | scratches at the end of LRA. */ | |
1914 | ||
1915 | /* Description of location of a former scratch operand. */ | |
453f1a8c | 1916 | struct sloc |
c6a6cdaa | 1917 | { |
1918 | rtx insn; /* Insn where the scratch was. */ | |
1919 | int nop; /* Number of the operand which was a scratch. */ | |
1920 | }; | |
1921 | ||
453f1a8c | 1922 | typedef struct sloc *sloc_t; |
c6a6cdaa | 1923 | |
c6a6cdaa | 1924 | /* Locations of the former scratches. */ |
f1f41a6c | 1925 | static vec<sloc_t> scratches; |
c6a6cdaa | 1926 | |
1927 | /* Bitmap of scratch regnos. */ | |
1928 | static bitmap_head scratch_bitmap; | |
1929 | ||
1930 | /* Bitmap of scratch operands. */ | |
1931 | static bitmap_head scratch_operand_bitmap; | |
1932 | ||
1933 | /* Return true if pseudo REGNO is made of SCRATCH. */ | |
1934 | bool | |
1935 | lra_former_scratch_p (int regno) | |
1936 | { | |
1937 | return bitmap_bit_p (&scratch_bitmap, regno); | |
1938 | } | |
1939 | ||
1940 | /* Return true if the operand NOP of INSN is a former scratch. */ | |
1941 | bool | |
1942 | lra_former_scratch_operand_p (rtx insn, int nop) | |
1943 | { | |
1944 | return bitmap_bit_p (&scratch_operand_bitmap, | |
1945 | INSN_UID (insn) * MAX_RECOG_OPERANDS + nop) != 0; | |
1946 | } | |
1947 | ||
1948 | /* Change scratches onto pseudos and save their location. */ | |
1949 | static void | |
1950 | remove_scratches (void) | |
1951 | { | |
1952 | int i; | |
1953 | bool insn_changed_p; | |
1954 | basic_block bb; | |
1955 | rtx insn, reg; | |
453f1a8c | 1956 | sloc_t loc; |
c6a6cdaa | 1957 | lra_insn_recog_data_t id; |
1958 | struct lra_static_insn_data *static_id; | |
1959 | ||
f1f41a6c | 1960 | scratches.create (get_max_uid ()); |
c6a6cdaa | 1961 | bitmap_initialize (&scratch_bitmap, ®_obstack); |
1962 | bitmap_initialize (&scratch_operand_bitmap, ®_obstack); | |
1963 | FOR_EACH_BB (bb) | |
1964 | FOR_BB_INSNS (bb, insn) | |
1965 | if (INSN_P (insn)) | |
1966 | { | |
1967 | id = lra_get_insn_recog_data (insn); | |
1968 | static_id = id->insn_static_data; | |
1969 | insn_changed_p = false; | |
1970 | for (i = 0; i < static_id->n_operands; i++) | |
1971 | if (GET_CODE (*id->operand_loc[i]) == SCRATCH | |
1972 | && GET_MODE (*id->operand_loc[i]) != VOIDmode) | |
1973 | { | |
1974 | insn_changed_p = true; | |
1975 | *id->operand_loc[i] = reg | |
1976 | = lra_create_new_reg (static_id->operand[i].mode, | |
1977 | *id->operand_loc[i], ALL_REGS, NULL); | |
1978 | add_reg_note (insn, REG_UNUSED, reg); | |
1979 | lra_update_dup (id, i); | |
453f1a8c | 1980 | loc = XNEW (struct sloc); |
c6a6cdaa | 1981 | loc->insn = insn; |
1982 | loc->nop = i; | |
f1f41a6c | 1983 | scratches.safe_push (loc); |
c6a6cdaa | 1984 | bitmap_set_bit (&scratch_bitmap, REGNO (*id->operand_loc[i])); |
1985 | bitmap_set_bit (&scratch_operand_bitmap, | |
1986 | INSN_UID (insn) * MAX_RECOG_OPERANDS + i); | |
1987 | if (lra_dump_file != NULL) | |
1988 | fprintf (lra_dump_file, | |
1989 | "Removing SCRATCH in insn #%u (nop %d)\n", | |
1990 | INSN_UID (insn), i); | |
1991 | } | |
1992 | if (insn_changed_p) | |
1993 | /* Because we might use DF right after caller-saves sub-pass | |
1994 | we need to keep DF info up to date. */ | |
1995 | df_insn_rescan (insn); | |
1996 | } | |
1997 | } | |
1998 | ||
1999 | /* Changes pseudos created by function remove_scratches onto scratches. */ | |
2000 | static void | |
2001 | restore_scratches (void) | |
2002 | { | |
f1f41a6c | 2003 | int regno; |
2004 | unsigned i; | |
453f1a8c | 2005 | sloc_t loc; |
c6a6cdaa | 2006 | rtx last = NULL_RTX; |
2007 | lra_insn_recog_data_t id = NULL; | |
2008 | ||
f1f41a6c | 2009 | for (i = 0; scratches.iterate (i, &loc); i++) |
c6a6cdaa | 2010 | { |
2011 | if (last != loc->insn) | |
2012 | { | |
2013 | last = loc->insn; | |
2014 | id = lra_get_insn_recog_data (last); | |
2015 | } | |
2016 | if (REG_P (*id->operand_loc[loc->nop]) | |
2017 | && ((regno = REGNO (*id->operand_loc[loc->nop])) | |
2018 | >= FIRST_PSEUDO_REGISTER) | |
2019 | && lra_get_regno_hard_regno (regno) < 0) | |
2020 | { | |
2021 | /* It should be only case when scratch register with chosen | |
2022 | constraint 'X' did not get memory or hard register. */ | |
2023 | lra_assert (lra_former_scratch_p (regno)); | |
2024 | *id->operand_loc[loc->nop] | |
2025 | = gen_rtx_SCRATCH (GET_MODE (*id->operand_loc[loc->nop])); | |
2026 | lra_update_dup (id, loc->nop); | |
2027 | if (lra_dump_file != NULL) | |
2028 | fprintf (lra_dump_file, "Restoring SCRATCH in insn #%u(nop %d)\n", | |
2029 | INSN_UID (loc->insn), loc->nop); | |
2030 | } | |
2031 | } | |
f1f41a6c | 2032 | for (i = 0; scratches.iterate (i, &loc); i++) |
c6a6cdaa | 2033 | free (loc); |
f1f41a6c | 2034 | scratches.release (); |
c6a6cdaa | 2035 | bitmap_clear (&scratch_bitmap); |
2036 | bitmap_clear (&scratch_operand_bitmap); | |
2037 | } | |
2038 | ||
2039 | \f | |
2040 | ||
2041 | #ifdef ENABLE_CHECKING | |
2042 | ||
2043 | /* Function checks RTL for correctness. If FINAL_P is true, it is | |
2044 | done at the end of LRA and the check is more rigorous. */ | |
2045 | static void | |
2046 | check_rtl (bool final_p) | |
2047 | { | |
c6a6cdaa | 2048 | basic_block bb; |
2049 | rtx insn; | |
c6a6cdaa | 2050 | |
2051 | lra_assert (! final_p || reload_completed); | |
2052 | FOR_EACH_BB (bb) | |
2053 | FOR_BB_INSNS (bb, insn) | |
2054 | if (NONDEBUG_INSN_P (insn) | |
2055 | && GET_CODE (PATTERN (insn)) != USE | |
2056 | && GET_CODE (PATTERN (insn)) != CLOBBER | |
c6a6cdaa | 2057 | && GET_CODE (PATTERN (insn)) != ASM_INPUT) |
2058 | { | |
2059 | if (final_p) | |
2060 | { | |
2061 | extract_insn (insn); | |
2062 | lra_assert (constrain_operands (1)); | |
2063 | continue; | |
2064 | } | |
cba8c2e6 | 2065 | /* LRA code is based on assumption that all addresses can be |
2066 | correctly decomposed. LRA can generate reloads for | |
2067 | decomposable addresses. The decomposition code checks the | |
2068 | correctness of the addresses. So we don't need to check | |
2069 | the addresses here. */ | |
c6a6cdaa | 2070 | if (insn_invalid_p (insn, false)) |
2071 | fatal_insn_not_found (insn); | |
c6a6cdaa | 2072 | } |
2073 | } | |
2074 | #endif /* #ifdef ENABLE_CHECKING */ | |
2075 | ||
2076 | /* Determine if the current function has an exception receiver block | |
2077 | that reaches the exit block via non-exceptional edges */ | |
2078 | static bool | |
2079 | has_nonexceptional_receiver (void) | |
2080 | { | |
2081 | edge e; | |
2082 | edge_iterator ei; | |
2083 | basic_block *tos, *worklist, bb; | |
2084 | ||
2085 | /* If we're not optimizing, then just err on the safe side. */ | |
2086 | if (!optimize) | |
2087 | return true; | |
1a8f8886 | 2088 | |
c6a6cdaa | 2089 | /* First determine which blocks can reach exit via normal paths. */ |
a28770e1 | 2090 | tos = worklist = XNEWVEC (basic_block, n_basic_blocks_for_fn (cfun) + 1); |
c6a6cdaa | 2091 | |
2092 | FOR_EACH_BB (bb) | |
2093 | bb->flags &= ~BB_REACHABLE; | |
2094 | ||
2095 | /* Place the exit block on our worklist. */ | |
34154e27 | 2096 | EXIT_BLOCK_PTR_FOR_FN (cfun)->flags |= BB_REACHABLE; |
2097 | *tos++ = EXIT_BLOCK_PTR_FOR_FN (cfun); | |
1a8f8886 | 2098 | |
c6a6cdaa | 2099 | /* Iterate: find everything reachable from what we've already seen. */ |
2100 | while (tos != worklist) | |
2101 | { | |
2102 | bb = *--tos; | |
2103 | ||
2104 | FOR_EACH_EDGE (e, ei, bb->preds) | |
2105 | if (e->flags & EDGE_ABNORMAL) | |
2106 | { | |
2107 | free (worklist); | |
2108 | return true; | |
2109 | } | |
2110 | else | |
2111 | { | |
2112 | basic_block src = e->src; | |
2113 | ||
2114 | if (!(src->flags & BB_REACHABLE)) | |
2115 | { | |
2116 | src->flags |= BB_REACHABLE; | |
2117 | *tos++ = src; | |
2118 | } | |
2119 | } | |
2120 | } | |
2121 | free (worklist); | |
2122 | /* No exceptional block reached exit unexceptionally. */ | |
2123 | return false; | |
2124 | } | |
2125 | ||
2126 | #ifdef AUTO_INC_DEC | |
2127 | ||
2128 | /* Process recursively X of INSN and add REG_INC notes if necessary. */ | |
2129 | static void | |
2130 | add_auto_inc_notes (rtx insn, rtx x) | |
2131 | { | |
2132 | enum rtx_code code = GET_CODE (x); | |
2133 | const char *fmt; | |
2134 | int i, j; | |
2135 | ||
2136 | if (code == MEM && auto_inc_p (XEXP (x, 0))) | |
2137 | { | |
2138 | add_reg_note (insn, REG_INC, XEXP (XEXP (x, 0), 0)); | |
2139 | return; | |
2140 | } | |
2141 | ||
2142 | /* Scan all X sub-expressions. */ | |
2143 | fmt = GET_RTX_FORMAT (code); | |
2144 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2145 | { | |
2146 | if (fmt[i] == 'e') | |
2147 | add_auto_inc_notes (insn, XEXP (x, i)); | |
2148 | else if (fmt[i] == 'E') | |
2149 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
2150 | add_auto_inc_notes (insn, XVECEXP (x, i, j)); | |
2151 | } | |
2152 | } | |
2153 | ||
2154 | #endif | |
2155 | ||
2156 | /* Remove all REG_DEAD and REG_UNUSED notes and regenerate REG_INC. | |
2157 | We change pseudos by hard registers without notification of DF and | |
2158 | that can make the notes obsolete. DF-infrastructure does not deal | |
2159 | with REG_INC notes -- so we should regenerate them here. */ | |
2160 | static void | |
2161 | update_inc_notes (void) | |
2162 | { | |
2163 | rtx *pnote; | |
2164 | basic_block bb; | |
2165 | rtx insn; | |
2166 | ||
2167 | FOR_EACH_BB (bb) | |
2168 | FOR_BB_INSNS (bb, insn) | |
2169 | if (NONDEBUG_INSN_P (insn)) | |
2170 | { | |
2171 | pnote = ®_NOTES (insn); | |
2172 | while (*pnote != 0) | |
2173 | { | |
e2ca76ac | 2174 | if (REG_NOTE_KIND (*pnote) == REG_DEAD |
2175 | || REG_NOTE_KIND (*pnote) == REG_UNUSED | |
2176 | || REG_NOTE_KIND (*pnote) == REG_INC) | |
c6a6cdaa | 2177 | *pnote = XEXP (*pnote, 1); |
2178 | else | |
2179 | pnote = &XEXP (*pnote, 1); | |
2180 | } | |
2181 | #ifdef AUTO_INC_DEC | |
2182 | add_auto_inc_notes (insn, PATTERN (insn)); | |
2183 | #endif | |
2184 | } | |
2185 | } | |
2186 | ||
2187 | /* Set to 1 while in lra. */ | |
2188 | int lra_in_progress; | |
2189 | ||
edfb1d8f | 2190 | /* Start of pseudo regnos before the LRA. */ |
2191 | int lra_new_regno_start; | |
2192 | ||
1a8f8886 | 2193 | /* Start of reload pseudo regnos before the new spill pass. */ |
c6a6cdaa | 2194 | int lra_constraint_new_regno_start; |
2195 | ||
1a8f8886 | 2196 | /* Inheritance pseudo regnos before the new spill pass. */ |
c6a6cdaa | 2197 | bitmap_head lra_inheritance_pseudos; |
2198 | ||
1a8f8886 | 2199 | /* Split regnos before the new spill pass. */ |
c6a6cdaa | 2200 | bitmap_head lra_split_regs; |
2201 | ||
1f3a048a | 2202 | /* Reload pseudo regnos before the new assignmnet pass which still can |
2203 | be spilled after the assinment pass as memory is also accepted in | |
2204 | insns for the reload pseudos. */ | |
c6a6cdaa | 2205 | bitmap_head lra_optional_reload_pseudos; |
2206 | ||
1f3a048a | 2207 | /* Pseudo regnos used for subreg reloads before the new assignment |
2208 | pass. Such pseudos still can be spilled after the assinment | |
2209 | pass. */ | |
2210 | bitmap_head lra_subreg_reload_pseudos; | |
2211 | ||
c6a6cdaa | 2212 | /* First UID of insns generated before a new spill pass. */ |
2213 | int lra_constraint_new_insn_uid_start; | |
2214 | ||
2215 | /* File used for output of LRA debug information. */ | |
2216 | FILE *lra_dump_file; | |
2217 | ||
2218 | /* True if we should try spill into registers of different classes | |
2219 | instead of memory. */ | |
2220 | bool lra_reg_spill_p; | |
2221 | ||
2222 | /* Set up value LRA_REG_SPILL_P. */ | |
2223 | static void | |
2224 | setup_reg_spill_flag (void) | |
2225 | { | |
2226 | int cl, mode; | |
2227 | ||
2228 | if (targetm.spill_class != NULL) | |
2229 | for (cl = 0; cl < (int) LIM_REG_CLASSES; cl++) | |
2230 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
2231 | if (targetm.spill_class ((enum reg_class) cl, | |
2232 | (enum machine_mode) mode) != NO_REGS) | |
2233 | { | |
2234 | lra_reg_spill_p = true; | |
2235 | return; | |
2236 | } | |
2237 | lra_reg_spill_p = false; | |
2238 | } | |
2239 | ||
2240 | /* True if the current function is too big to use regular algorithms | |
2241 | in LRA. In other words, we should use simpler and faster algorithms | |
2242 | in LRA. It also means we should not worry about generation code | |
2243 | for caller saves. The value is set up in IRA. */ | |
2244 | bool lra_simple_p; | |
2245 | ||
2246 | /* Major LRA entry function. F is a file should be used to dump LRA | |
2247 | debug info. */ | |
2248 | void | |
2249 | lra (FILE *f) | |
2250 | { | |
2251 | int i; | |
2252 | bool live_p, scratch_p, inserted_p; | |
2253 | ||
2254 | lra_dump_file = f; | |
2255 | ||
2256 | timevar_push (TV_LRA); | |
2257 | ||
ea99c7a1 | 2258 | /* Make sure that the last insn is a note. Some subsequent passes |
2259 | need it. */ | |
2260 | emit_note (NOTE_INSN_DELETED); | |
2261 | ||
fc8a0f60 | 2262 | COPY_HARD_REG_SET (lra_no_alloc_regs, ira_no_alloc_regs); |
2263 | ||
b85cafd3 | 2264 | init_reg_info (); |
2265 | expand_reg_info (); | |
2266 | ||
c6a6cdaa | 2267 | init_insn_recog_data (); |
2268 | ||
250f439b | 2269 | /* We can not set up reload_in_progress because it prevents new |
2270 | pseudo creation. */ | |
2271 | lra_in_progress = 1; | |
2272 | ||
c6a6cdaa | 2273 | #ifdef ENABLE_CHECKING |
2274 | check_rtl (false); | |
2275 | #endif | |
2276 | ||
c6a6cdaa | 2277 | lra_live_range_iter = lra_coalesce_iter = 0; |
2278 | lra_constraint_iter = lra_constraint_iter_after_spill = 0; | |
2279 | lra_inheritance_iter = lra_undo_inheritance_iter = 0; | |
2280 | ||
2281 | setup_reg_spill_flag (); | |
2282 | ||
c6a6cdaa | 2283 | /* Function remove_scratches can creates new pseudos for clobbers -- |
2284 | so set up lra_constraint_new_regno_start before its call to | |
2285 | permit changing reg classes for pseudos created by this | |
2286 | simplification. */ | |
edfb1d8f | 2287 | lra_constraint_new_regno_start = lra_new_regno_start = max_reg_num (); |
c6a6cdaa | 2288 | remove_scratches (); |
2289 | scratch_p = lra_constraint_new_regno_start != max_reg_num (); | |
2290 | ||
2291 | /* A function that has a non-local label that can reach the exit | |
2292 | block via non-exceptional paths must save all call-saved | |
2293 | registers. */ | |
2294 | if (cfun->has_nonlocal_label && has_nonexceptional_receiver ()) | |
2295 | crtl->saves_all_registers = 1; | |
2296 | ||
2297 | if (crtl->saves_all_registers) | |
2298 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
2299 | if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i)) | |
2300 | df_set_regs_ever_live (i, true); | |
2301 | ||
2302 | /* We don't DF from now and avoid its using because it is to | |
2303 | expensive when a lot of RTL changes are made. */ | |
2304 | df_set_flags (DF_NO_INSN_RESCAN); | |
f1f41a6c | 2305 | lra_constraint_insn_stack.create (get_max_uid ()); |
c6a6cdaa | 2306 | lra_constraint_insn_stack_bitmap = sbitmap_alloc (get_max_uid ()); |
53c5d9d4 | 2307 | bitmap_clear (lra_constraint_insn_stack_bitmap); |
c6a6cdaa | 2308 | lra_live_ranges_init (); |
2309 | lra_constraints_init (); | |
2310 | lra_curr_reload_num = 0; | |
2311 | push_insns (get_last_insn (), NULL_RTX); | |
2312 | /* It is needed for the 1st coalescing. */ | |
2313 | lra_constraint_new_insn_uid_start = get_max_uid (); | |
2314 | bitmap_initialize (&lra_inheritance_pseudos, ®_obstack); | |
2315 | bitmap_initialize (&lra_split_regs, ®_obstack); | |
2316 | bitmap_initialize (&lra_optional_reload_pseudos, ®_obstack); | |
1f3a048a | 2317 | bitmap_initialize (&lra_subreg_reload_pseudos, ®_obstack); |
c6a6cdaa | 2318 | live_p = false; |
ea99c7a1 | 2319 | if (get_frame_size () != 0 && crtl->stack_alignment_needed) |
2320 | /* If we have a stack frame, we must align it now. The stack size | |
2321 | may be a part of the offset computation for register | |
2322 | elimination. */ | |
2323 | assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed); | |
c6a6cdaa | 2324 | for (;;) |
2325 | { | |
2326 | for (;;) | |
2327 | { | |
c6a6cdaa | 2328 | /* We should try to assign hard registers to scratches even |
2329 | if there were no RTL transformations in | |
2330 | lra_constraints. */ | |
2331 | if (! lra_constraints (lra_constraint_iter == 0) | |
2332 | && (lra_constraint_iter > 1 | |
2333 | || (! scratch_p && ! caller_save_needed))) | |
2334 | break; | |
2335 | /* Constraint transformations may result in that eliminable | |
2336 | hard regs become uneliminable and pseudos which use them | |
2337 | should be spilled. It is better to do it before pseudo | |
2338 | assignments. | |
2339 | ||
2340 | For example, rs6000 can make | |
2341 | RS6000_PIC_OFFSET_TABLE_REGNUM uneliminable if we started | |
2342 | to use a constant pool. */ | |
3b3a5e5f | 2343 | lra_eliminate (false, false); |
c6a6cdaa | 2344 | /* Do inheritance only for regular algorithms. */ |
2345 | if (! lra_simple_p) | |
2346 | lra_inheritance (); | |
d3d0b390 | 2347 | if (live_p) |
2348 | lra_clear_live_ranges (); | |
c6a6cdaa | 2349 | /* We need live ranges for lra_assign -- so build them. */ |
2350 | lra_create_live_ranges (true); | |
2351 | live_p = true; | |
2352 | /* If we don't spill non-reload and non-inheritance pseudos, | |
2353 | there is no sense to run memory-memory move coalescing. | |
2354 | If inheritance pseudos were spilled, the memory-memory | |
2355 | moves involving them will be removed by pass undoing | |
2356 | inheritance. */ | |
2357 | if (lra_simple_p) | |
2358 | lra_assign (); | |
2359 | else | |
2360 | { | |
638e746e | 2361 | bool spill_p = !lra_assign (); |
2362 | ||
c6a6cdaa | 2363 | if (lra_undo_inheritance ()) |
2364 | live_p = false; | |
638e746e | 2365 | if (spill_p) |
2366 | { | |
2367 | if (! live_p) | |
2368 | { | |
2369 | lra_create_live_ranges (true); | |
2370 | live_p = true; | |
2371 | } | |
2372 | if (lra_coalesce ()) | |
2373 | live_p = false; | |
2374 | } | |
d3d0b390 | 2375 | if (! live_p) |
2376 | lra_clear_live_ranges (); | |
c6a6cdaa | 2377 | } |
2378 | } | |
95563487 | 2379 | /* Don't clear optional reloads bitmap until all constraints are |
2380 | satisfied as we need to differ them from regular reloads. */ | |
2381 | bitmap_clear (&lra_optional_reload_pseudos); | |
1f3a048a | 2382 | bitmap_clear (&lra_subreg_reload_pseudos); |
c6a6cdaa | 2383 | bitmap_clear (&lra_inheritance_pseudos); |
2384 | bitmap_clear (&lra_split_regs); | |
2385 | if (! lra_need_for_spills_p ()) | |
2386 | break; | |
2387 | if (! live_p) | |
2388 | { | |
2389 | /* We need full live info for spilling pseudos into | |
2390 | registers instead of memory. */ | |
2391 | lra_create_live_ranges (lra_reg_spill_p); | |
2392 | live_p = true; | |
2393 | } | |
2394 | lra_spill (); | |
2395 | /* Assignment of stack slots changes elimination offsets for | |
2396 | some eliminations. So update the offsets here. */ | |
3b3a5e5f | 2397 | lra_eliminate (false, false); |
c6a6cdaa | 2398 | lra_constraint_new_regno_start = max_reg_num (); |
2399 | lra_constraint_new_insn_uid_start = get_max_uid (); | |
2400 | lra_constraint_iter_after_spill = 0; | |
2401 | } | |
2402 | restore_scratches (); | |
3b3a5e5f | 2403 | lra_eliminate (true, false); |
ae72d5b2 | 2404 | lra_final_code_change (); |
c6a6cdaa | 2405 | lra_in_progress = 0; |
d3d0b390 | 2406 | if (live_p) |
2407 | lra_clear_live_ranges (); | |
c6a6cdaa | 2408 | lra_live_ranges_finish (); |
2409 | lra_constraints_finish (); | |
2410 | finish_reg_info (); | |
2411 | sbitmap_free (lra_constraint_insn_stack_bitmap); | |
f1f41a6c | 2412 | lra_constraint_insn_stack.release (); |
c6a6cdaa | 2413 | finish_insn_recog_data (); |
2414 | regstat_free_n_sets_and_refs (); | |
2415 | regstat_free_ri (); | |
2416 | reload_completed = 1; | |
2417 | update_inc_notes (); | |
2418 | ||
2419 | inserted_p = fixup_abnormal_edges (); | |
2420 | ||
2421 | /* We've possibly turned single trapping insn into multiple ones. */ | |
2422 | if (cfun->can_throw_non_call_exceptions) | |
2423 | { | |
2424 | sbitmap blocks; | |
2425 | blocks = sbitmap_alloc (last_basic_block); | |
53c5d9d4 | 2426 | bitmap_ones (blocks); |
c6a6cdaa | 2427 | find_many_sub_basic_blocks (blocks); |
2428 | sbitmap_free (blocks); | |
2429 | } | |
2430 | ||
2431 | if (inserted_p) | |
2432 | commit_edge_insertions (); | |
2433 | ||
2434 | /* Replacing pseudos with their memory equivalents might have | |
2435 | created shared rtx. Subsequent passes would get confused | |
2436 | by this, so unshare everything here. */ | |
2437 | unshare_all_rtl_again (get_insns ()); | |
2438 | ||
2439 | #ifdef ENABLE_CHECKING | |
2440 | check_rtl (true); | |
2441 | #endif | |
2442 | ||
2443 | timevar_pop (TV_LRA); | |
2444 | } | |
2445 | ||
2446 | /* Called once per compiler to initialize LRA data once. */ | |
2447 | void | |
2448 | lra_init_once (void) | |
2449 | { | |
2450 | init_insn_code_data_once (); | |
2451 | } | |
2452 | ||
2453 | /* Initialize LRA whenever register-related information is changed. */ | |
2454 | void | |
2455 | lra_init (void) | |
2456 | { | |
2457 | init_op_alt_data (); | |
2458 | } | |
2459 | ||
2460 | /* Called once per compiler to finish LRA data which are initialize | |
2461 | once. */ | |
2462 | void | |
2463 | lra_finish_once (void) | |
2464 | { | |
2465 | finish_insn_code_data_once (); | |
2466 | } |