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c6a6cdaa | 1 | /* LRA (local register allocator) driver and LRA utilities. |
aad93da1 | 2 | Copyright (C) 2010-2017 Free Software Foundation, Inc. |
c6a6cdaa | 3 | Contributed by Vladimir Makarov <vmakarov@redhat.com>. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it under | |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 3, or (at your option) any later | |
10 | version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | ||
22 | /* The Local Register Allocator (LRA) is a replacement of former | |
23 | reload pass. It is focused to simplify code solving the reload | |
24 | pass tasks, to make the code maintenance easier, and to implement new | |
25 | perspective optimizations. | |
26 | ||
27 | The major LRA design solutions are: | |
28 | o division small manageable, separated sub-tasks | |
29 | o reflection of all transformations and decisions in RTL as more | |
30 | as possible | |
31 | o insn constraints as a primary source of the info (minimizing | |
32 | number of target-depended macros/hooks) | |
33 | ||
34 | In brief LRA works by iterative insn process with the final goal is | |
35 | to satisfy all insn and address constraints: | |
36 | o New reload insns (in brief reloads) and reload pseudos might be | |
37 | generated; | |
38 | o Some pseudos might be spilled to assign hard registers to | |
39 | new reload pseudos; | |
497ba60f | 40 | o Recalculating spilled pseudo values (rematerialization); |
c6a6cdaa | 41 | o Changing spilled pseudos to stack memory or their equivalences; |
42 | o Allocation stack memory changes the address displacement and | |
43 | new iteration is needed. | |
44 | ||
45 | Here is block diagram of LRA passes: | |
46 | ||
1f3a048a | 47 | ------------------------ |
48 | --------------- | Undo inheritance for | --------------- | |
49 | | Memory-memory | | spilled pseudos, | | New (and old) | | |
50 | | move coalesce |<---| splits for pseudos got |<-- | pseudos | | |
51 | --------------- | the same hard regs, | | assignment | | |
52 | Start | | and optional reloads | --------------- | |
53 | | | ------------------------ ^ | |
b28ae2d4 | 54 | V | ---------------- | |
55 | ----------- V | Update virtual | | | |
56 | | Remove |----> ------------>| register | | | |
57 | | scratches | ^ | displacements | | | |
58 | ----------- | ---------------- | | |
59 | | | | | |
60 | | V New | | |
497ba60f | 61 | | ------------ pseudos ------------------- |
62 | | |Constraints:| or insns | Inheritance/split | | |
63 | | | RTL |--------->| transformations | | |
64 | | | transfor- | | in EBB scope | | |
65 | | substi- | mations | ------------------- | |
66 | | tutions ------------ | |
67 | | | No change | |
68 | ---------------- V | |
69 | | Spilled pseudo | ------------------- | |
70 | | to memory |<----| Rematerialization | | |
71 | | substitution | ------------------- | |
72 | ---------------- | |
73 | | No susbtitions | |
74 | V | |
75 | ------------------------- | |
76 | | Hard regs substitution, | | |
77 | | devirtalization, and |------> Finish | |
78 | | restoring scratches got | | |
79 | | memory | | |
80 | ------------------------- | |
c6a6cdaa | 81 | |
82 | To speed up the process: | |
83 | o We process only insns affected by changes on previous | |
84 | iterations; | |
85 | o We don't use DFA-infrastructure because it results in much slower | |
86 | compiler speed than a special IR described below does; | |
87 | o We use a special insn representation for quick access to insn | |
88 | info which is always *synchronized* with the current RTL; | |
89 | o Insn IR is minimized by memory. It is divided on three parts: | |
90 | o one specific for each insn in RTL (only operand locations); | |
91 | o one common for all insns in RTL with the same insn code | |
92 | (different operand attributes from machine descriptions); | |
93 | o one oriented for maintenance of live info (list of pseudos). | |
94 | o Pseudo data: | |
95 | o all insns where the pseudo is referenced; | |
96 | o live info (conflicting hard regs, live ranges, # of | |
97 | references etc); | |
98 | o data used for assigning (preferred hard regs, costs etc). | |
99 | ||
100 | This file contains LRA driver, LRA utility functions and data, and | |
101 | code for dealing with scratches. */ | |
102 | ||
103 | #include "config.h" | |
104 | #include "system.h" | |
105 | #include "coretypes.h" | |
9ef16211 | 106 | #include "backend.h" |
7c29e30e | 107 | #include "target.h" |
c6a6cdaa | 108 | #include "rtl.h" |
7c29e30e | 109 | #include "tree.h" |
110 | #include "predict.h" | |
9ef16211 | 111 | #include "df.h" |
ad7b10a2 | 112 | #include "memmodel.h" |
c6a6cdaa | 113 | #include "tm_p.h" |
7c29e30e | 114 | #include "optabs.h" |
c6a6cdaa | 115 | #include "regs.h" |
7c29e30e | 116 | #include "ira.h" |
c6a6cdaa | 117 | #include "recog.h" |
c6a6cdaa | 118 | #include "expr.h" |
94ea8568 | 119 | #include "cfgrtl.h" |
120 | #include "cfgbuild.h" | |
9ef16211 | 121 | #include "lra.h" |
c6a6cdaa | 122 | #include "lra-int.h" |
397881d3 | 123 | #include "print-rtl.h" |
c6a6cdaa | 124 | |
8c0d01a4 | 125 | /* Dump bitmap SET with TITLE and BB INDEX. */ |
126 | void | |
127 | lra_dump_bitmap_with_title (const char *title, bitmap set, int index) | |
128 | { | |
129 | unsigned int i; | |
130 | int count; | |
131 | bitmap_iterator bi; | |
132 | static const int max_nums_on_line = 10; | |
133 | ||
134 | if (bitmap_empty_p (set)) | |
135 | return; | |
136 | fprintf (lra_dump_file, " %s %d:", title, index); | |
137 | fprintf (lra_dump_file, "\n"); | |
138 | count = max_nums_on_line + 1; | |
139 | EXECUTE_IF_SET_IN_BITMAP (set, 0, i, bi) | |
140 | { | |
141 | if (count > max_nums_on_line) | |
142 | { | |
143 | fprintf (lra_dump_file, "\n "); | |
144 | count = 0; | |
145 | } | |
146 | fprintf (lra_dump_file, " %4u", i); | |
147 | count++; | |
148 | } | |
149 | fprintf (lra_dump_file, "\n"); | |
150 | } | |
151 | ||
c6a6cdaa | 152 | /* Hard registers currently not available for allocation. It can |
153 | changed after some hard registers become not eliminable. */ | |
154 | HARD_REG_SET lra_no_alloc_regs; | |
155 | ||
156 | static int get_new_reg_value (void); | |
157 | static void expand_reg_info (void); | |
158 | static void invalidate_insn_recog_data (int); | |
7f836b57 | 159 | static int get_insn_freq (rtx_insn *); |
160 | static void invalidate_insn_data_regno_info (lra_insn_recog_data_t, | |
161 | rtx_insn *, int); | |
c6a6cdaa | 162 | |
163 | /* Expand all regno related info needed for LRA. */ | |
164 | static void | |
7619e612 | 165 | expand_reg_data (int old) |
c6a6cdaa | 166 | { |
167 | resize_reg_info (); | |
168 | expand_reg_info (); | |
169 | ira_expand_reg_equiv (); | |
7619e612 | 170 | for (int i = (int) max_reg_num () - 1; i >= old; i--) |
171 | lra_change_class (i, ALL_REGS, " Set", true); | |
c6a6cdaa | 172 | } |
173 | ||
174 | /* Create and return a new reg of ORIGINAL mode. If ORIGINAL is NULL | |
175 | or of VOIDmode, use MD_MODE for the new reg. Initialize its | |
176 | register class to RCLASS. Print message about assigning class | |
177 | RCLASS containing new register name TITLE unless it is NULL. Use | |
178 | attributes of ORIGINAL if it is a register. The created register | |
179 | will have unique held value. */ | |
180 | rtx | |
3754d046 | 181 | lra_create_new_reg_with_unique_value (machine_mode md_mode, rtx original, |
c6a6cdaa | 182 | enum reg_class rclass, const char *title) |
183 | { | |
3754d046 | 184 | machine_mode mode; |
c6a6cdaa | 185 | rtx new_reg; |
186 | ||
187 | if (original == NULL_RTX || (mode = GET_MODE (original)) == VOIDmode) | |
188 | mode = md_mode; | |
189 | lra_assert (mode != VOIDmode); | |
190 | new_reg = gen_reg_rtx (mode); | |
191 | if (original == NULL_RTX || ! REG_P (original)) | |
192 | { | |
193 | if (lra_dump_file != NULL) | |
194 | fprintf (lra_dump_file, " Creating newreg=%i", REGNO (new_reg)); | |
195 | } | |
196 | else | |
197 | { | |
198 | if (ORIGINAL_REGNO (original) >= FIRST_PSEUDO_REGISTER) | |
199 | ORIGINAL_REGNO (new_reg) = ORIGINAL_REGNO (original); | |
200 | REG_USERVAR_P (new_reg) = REG_USERVAR_P (original); | |
201 | REG_POINTER (new_reg) = REG_POINTER (original); | |
202 | REG_ATTRS (new_reg) = REG_ATTRS (original); | |
203 | if (lra_dump_file != NULL) | |
204 | fprintf (lra_dump_file, " Creating newreg=%i from oldreg=%i", | |
205 | REGNO (new_reg), REGNO (original)); | |
206 | } | |
207 | if (lra_dump_file != NULL) | |
208 | { | |
209 | if (title != NULL) | |
210 | fprintf (lra_dump_file, ", assigning class %s to%s%s r%d", | |
211 | reg_class_names[rclass], *title == '\0' ? "" : " ", | |
212 | title, REGNO (new_reg)); | |
213 | fprintf (lra_dump_file, "\n"); | |
214 | } | |
7619e612 | 215 | expand_reg_data (max_reg_num ()); |
c6a6cdaa | 216 | setup_reg_classes (REGNO (new_reg), rclass, NO_REGS, rclass); |
217 | return new_reg; | |
218 | } | |
219 | ||
220 | /* Analogous to the previous function but also inherits value of | |
221 | ORIGINAL. */ | |
222 | rtx | |
3754d046 | 223 | lra_create_new_reg (machine_mode md_mode, rtx original, |
c6a6cdaa | 224 | enum reg_class rclass, const char *title) |
225 | { | |
226 | rtx new_reg; | |
227 | ||
228 | new_reg | |
229 | = lra_create_new_reg_with_unique_value (md_mode, original, rclass, title); | |
230 | if (original != NULL_RTX && REG_P (original)) | |
a1064490 | 231 | lra_assign_reg_val (REGNO (original), REGNO (new_reg)); |
c6a6cdaa | 232 | return new_reg; |
233 | } | |
234 | ||
235 | /* Set up for REGNO unique hold value. */ | |
236 | void | |
237 | lra_set_regno_unique_value (int regno) | |
238 | { | |
239 | lra_reg_info[regno].val = get_new_reg_value (); | |
240 | } | |
241 | ||
3b3a5e5f | 242 | /* Invalidate INSN related info used by LRA. The info should never be |
243 | used after that. */ | |
c6a6cdaa | 244 | void |
7f836b57 | 245 | lra_invalidate_insn_data (rtx_insn *insn) |
c6a6cdaa | 246 | { |
247 | lra_invalidate_insn_regno_info (insn); | |
248 | invalidate_insn_recog_data (INSN_UID (insn)); | |
249 | } | |
250 | ||
251 | /* Mark INSN deleted and invalidate the insn related info used by | |
252 | LRA. */ | |
253 | void | |
7f836b57 | 254 | lra_set_insn_deleted (rtx_insn *insn) |
c6a6cdaa | 255 | { |
256 | lra_invalidate_insn_data (insn); | |
257 | SET_INSN_DELETED (insn); | |
258 | } | |
259 | ||
260 | /* Delete an unneeded INSN and any previous insns who sole purpose is | |
261 | loading data that is dead in INSN. */ | |
262 | void | |
7f836b57 | 263 | lra_delete_dead_insn (rtx_insn *insn) |
c6a6cdaa | 264 | { |
7f836b57 | 265 | rtx_insn *prev = prev_real_insn (insn); |
c6a6cdaa | 266 | rtx prev_dest; |
267 | ||
268 | /* If the previous insn sets a register that dies in our insn, | |
269 | delete it too. */ | |
270 | if (prev && GET_CODE (PATTERN (prev)) == SET | |
271 | && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest)) | |
272 | && reg_mentioned_p (prev_dest, PATTERN (insn)) | |
273 | && find_regno_note (insn, REG_DEAD, REGNO (prev_dest)) | |
274 | && ! side_effects_p (SET_SRC (PATTERN (prev)))) | |
275 | lra_delete_dead_insn (prev); | |
276 | ||
277 | lra_set_insn_deleted (insn); | |
278 | } | |
279 | ||
6c397456 | 280 | /* Emit insn x = y + z. Return NULL if we failed to do it. |
281 | Otherwise, return the insn. We don't use gen_add3_insn as it might | |
282 | clobber CC. */ | |
9ed997be | 283 | static rtx_insn * |
6c397456 | 284 | emit_add3_insn (rtx x, rtx y, rtx z) |
285 | { | |
57c26b3a | 286 | rtx_insn *last; |
6c397456 | 287 | |
288 | last = get_last_insn (); | |
79127ad5 | 289 | |
290 | if (have_addptr3_insn (x, y, z)) | |
291 | { | |
9ed997be | 292 | rtx_insn *insn = gen_addptr3_insn (x, y, z); |
79127ad5 | 293 | |
294 | /* If the target provides an "addptr" pattern it hopefully does | |
295 | for a reason. So falling back to the normal add would be | |
296 | a bug. */ | |
297 | lra_assert (insn != NULL_RTX); | |
298 | emit_insn (insn); | |
299 | return insn; | |
300 | } | |
301 | ||
d1f9b275 | 302 | rtx_insn *insn = emit_insn (gen_rtx_SET (x, gen_rtx_PLUS (GET_MODE (y), |
303 | y, z))); | |
6c397456 | 304 | if (recog_memoized (insn) < 0) |
305 | { | |
306 | delete_insns_since (last); | |
ed3e6e5d | 307 | insn = NULL; |
6c397456 | 308 | } |
309 | return insn; | |
310 | } | |
311 | ||
312 | /* Emit insn x = x + y. Return the insn. We use gen_add2_insn as the | |
313 | last resort. */ | |
9ed997be | 314 | static rtx_insn * |
6c397456 | 315 | emit_add2_insn (rtx x, rtx y) |
316 | { | |
9ed997be | 317 | rtx_insn *insn = emit_add3_insn (x, x, y); |
6c397456 | 318 | if (insn == NULL_RTX) |
319 | { | |
320 | insn = gen_add2_insn (x, y); | |
321 | if (insn != NULL_RTX) | |
322 | emit_insn (insn); | |
323 | } | |
324 | return insn; | |
325 | } | |
326 | ||
c6a6cdaa | 327 | /* Target checks operands through operand predicates to recognize an |
328 | insn. We should have a special precaution to generate add insns | |
329 | which are frequent results of elimination. | |
330 | ||
331 | Emit insns for x = y + z. X can be used to store intermediate | |
332 | values and should be not in Y and Z when we use X to store an | |
333 | intermediate value. Y + Z should form [base] [+ index[ * scale]] [ | |
334 | + disp] where base and index are registers, disp and scale are | |
335 | constants. Y should contain base if it is present, Z should | |
336 | contain disp if any. index[*scale] can be part of Y or Z. */ | |
337 | void | |
338 | lra_emit_add (rtx x, rtx y, rtx z) | |
339 | { | |
340 | int old; | |
57c26b3a | 341 | rtx_insn *last; |
c6a6cdaa | 342 | rtx a1, a2, base, index, disp, scale, index_scale; |
343 | bool ok_p; | |
344 | ||
9ed997be | 345 | rtx_insn *add3_insn = emit_add3_insn (x, y, z); |
c6a6cdaa | 346 | old = max_reg_num (); |
ed3e6e5d | 347 | if (add3_insn != NULL) |
6c397456 | 348 | ; |
c6a6cdaa | 349 | else |
350 | { | |
351 | disp = a2 = NULL_RTX; | |
352 | if (GET_CODE (y) == PLUS) | |
353 | { | |
354 | a1 = XEXP (y, 0); | |
355 | a2 = XEXP (y, 1); | |
356 | disp = z; | |
357 | } | |
358 | else | |
359 | { | |
360 | a1 = y; | |
361 | if (CONSTANT_P (z)) | |
362 | disp = z; | |
363 | else | |
364 | a2 = z; | |
365 | } | |
366 | index_scale = scale = NULL_RTX; | |
367 | if (GET_CODE (a1) == MULT) | |
368 | { | |
369 | index_scale = a1; | |
370 | index = XEXP (a1, 0); | |
371 | scale = XEXP (a1, 1); | |
372 | base = a2; | |
373 | } | |
374 | else if (a2 != NULL_RTX && GET_CODE (a2) == MULT) | |
375 | { | |
376 | index_scale = a2; | |
377 | index = XEXP (a2, 0); | |
378 | scale = XEXP (a2, 1); | |
379 | base = a1; | |
380 | } | |
381 | else | |
382 | { | |
383 | base = a1; | |
384 | index = a2; | |
385 | } | |
af121a86 | 386 | if ((base != NULL_RTX && ! (REG_P (base) || GET_CODE (base) == SUBREG)) |
1c1417f1 | 387 | || (index != NULL_RTX |
388 | && ! (REG_P (index) || GET_CODE (index) == SUBREG)) | |
c6a6cdaa | 389 | || (disp != NULL_RTX && ! CONSTANT_P (disp)) |
390 | || (scale != NULL_RTX && ! CONSTANT_P (scale))) | |
391 | { | |
6c397456 | 392 | /* Probably we have no 3 op add. Last chance is to use 2-op |
393 | add insn. To succeed, don't move Z to X as an address | |
394 | segment always comes in Y. Otherwise, we might fail when | |
395 | adding the address segment to register. */ | |
c6a6cdaa | 396 | lra_assert (x != y && x != z); |
0178c26e | 397 | emit_move_insn (x, y); |
9ed997be | 398 | rtx_insn *insn = emit_add2_insn (x, z); |
6c397456 | 399 | lra_assert (insn != NULL_RTX); |
c6a6cdaa | 400 | } |
401 | else | |
402 | { | |
403 | if (index_scale == NULL_RTX) | |
404 | index_scale = index; | |
405 | if (disp == NULL_RTX) | |
406 | { | |
407 | /* Generate x = index_scale; x = x + base. */ | |
408 | lra_assert (index_scale != NULL_RTX && base != NULL_RTX); | |
409 | emit_move_insn (x, index_scale); | |
9ed997be | 410 | rtx_insn *insn = emit_add2_insn (x, base); |
6c397456 | 411 | lra_assert (insn != NULL_RTX); |
c6a6cdaa | 412 | } |
413 | else if (scale == NULL_RTX) | |
414 | { | |
415 | /* Try x = base + disp. */ | |
416 | lra_assert (base != NULL_RTX); | |
417 | last = get_last_insn (); | |
ed3e6e5d | 418 | rtx_insn *move_insn = |
419 | emit_move_insn (x, gen_rtx_PLUS (GET_MODE (base), base, disp)); | |
420 | if (recog_memoized (move_insn) < 0) | |
c6a6cdaa | 421 | { |
422 | delete_insns_since (last); | |
423 | /* Generate x = disp; x = x + base. */ | |
424 | emit_move_insn (x, disp); | |
9ed997be | 425 | rtx_insn *add2_insn = emit_add2_insn (x, base); |
ed3e6e5d | 426 | lra_assert (add2_insn != NULL_RTX); |
c6a6cdaa | 427 | } |
428 | /* Generate x = x + index. */ | |
429 | if (index != NULL_RTX) | |
430 | { | |
9ed997be | 431 | rtx_insn *insn = emit_add2_insn (x, index); |
6c397456 | 432 | lra_assert (insn != NULL_RTX); |
c6a6cdaa | 433 | } |
434 | } | |
435 | else | |
436 | { | |
437 | /* Try x = index_scale; x = x + disp; x = x + base. */ | |
438 | last = get_last_insn (); | |
ed3e6e5d | 439 | rtx_insn *move_insn = emit_move_insn (x, index_scale); |
c6a6cdaa | 440 | ok_p = false; |
ed3e6e5d | 441 | if (recog_memoized (move_insn) >= 0) |
c6a6cdaa | 442 | { |
9ed997be | 443 | rtx_insn *insn = emit_add2_insn (x, disp); |
c6a6cdaa | 444 | if (insn != NULL_RTX) |
445 | { | |
af121a86 | 446 | if (base == NULL_RTX) |
6c397456 | 447 | ok_p = true; |
af121a86 | 448 | else |
449 | { | |
450 | insn = emit_add2_insn (x, base); | |
451 | if (insn != NULL_RTX) | |
452 | ok_p = true; | |
453 | } | |
c6a6cdaa | 454 | } |
455 | } | |
456 | if (! ok_p) | |
457 | { | |
af121a86 | 458 | rtx_insn *insn; |
459 | ||
c6a6cdaa | 460 | delete_insns_since (last); |
461 | /* Generate x = disp; x = x + base; x = x + index_scale. */ | |
462 | emit_move_insn (x, disp); | |
af121a86 | 463 | if (base != NULL_RTX) |
464 | { | |
465 | insn = emit_add2_insn (x, base); | |
466 | lra_assert (insn != NULL_RTX); | |
467 | } | |
6c397456 | 468 | insn = emit_add2_insn (x, index_scale); |
469 | lra_assert (insn != NULL_RTX); | |
c6a6cdaa | 470 | } |
471 | } | |
472 | } | |
473 | } | |
474 | /* Functions emit_... can create pseudos -- so expand the pseudo | |
475 | data. */ | |
476 | if (old != max_reg_num ()) | |
7619e612 | 477 | expand_reg_data (old); |
c6a6cdaa | 478 | } |
479 | ||
480 | /* The number of emitted reload insns so far. */ | |
481 | int lra_curr_reload_num; | |
482 | ||
483 | /* Emit x := y, processing special case when y = u + v or y = u + v * | |
484 | scale + w through emit_add (Y can be an address which is base + | |
485 | index reg * scale + displacement in general case). X may be used | |
486 | as intermediate result therefore it should be not in Y. */ | |
487 | void | |
488 | lra_emit_move (rtx x, rtx y) | |
489 | { | |
490 | int old; | |
491 | ||
492 | if (GET_CODE (y) != PLUS) | |
493 | { | |
494 | if (rtx_equal_p (x, y)) | |
495 | return; | |
496 | old = max_reg_num (); | |
497 | emit_move_insn (x, y); | |
498 | if (REG_P (x)) | |
499 | lra_reg_info[ORIGINAL_REGNO (x)].last_reload = ++lra_curr_reload_num; | |
500 | /* Function emit_move can create pseudos -- so expand the pseudo | |
501 | data. */ | |
502 | if (old != max_reg_num ()) | |
7619e612 | 503 | expand_reg_data (old); |
c6a6cdaa | 504 | return; |
505 | } | |
506 | lra_emit_add (x, XEXP (y, 0), XEXP (y, 1)); | |
507 | } | |
508 | ||
509 | /* Update insn operands which are duplication of operands whose | |
510 | numbers are in array of NOPS (with end marker -1). The insn is | |
511 | represented by its LRA internal representation ID. */ | |
512 | void | |
513 | lra_update_dups (lra_insn_recog_data_t id, signed char *nops) | |
514 | { | |
515 | int i, j, nop; | |
516 | struct lra_static_insn_data *static_id = id->insn_static_data; | |
517 | ||
518 | for (i = 0; i < static_id->n_dups; i++) | |
519 | for (j = 0; (nop = nops[j]) >= 0; j++) | |
520 | if (static_id->dup_num[i] == nop) | |
521 | *id->dup_loc[i] = *id->operand_loc[nop]; | |
522 | } | |
523 | ||
524 | \f | |
525 | ||
526 | /* This page contains code dealing with info about registers in the | |
527 | insns. */ | |
528 | ||
529 | /* Pools for insn reg info. */ | |
1dc6c44d | 530 | object_allocator<lra_insn_reg> lra_insn_reg_pool ("insn regs"); |
c6a6cdaa | 531 | |
40cec44a | 532 | /* Create LRA insn related info about a reference to REGNO in INSN with |
533 | TYPE (in/out/inout), biggest reference mode MODE, flag that it is | |
c6a6cdaa | 534 | reference through subreg (SUBREG_P), flag that is early clobbered |
535 | in the insn (EARLY_CLOBBER), and reference to the next insn reg | |
536 | info (NEXT). */ | |
537 | static struct lra_insn_reg * | |
7f836b57 | 538 | new_insn_reg (rtx_insn *insn, int regno, enum op_type type, |
3754d046 | 539 | machine_mode mode, |
c6a6cdaa | 540 | bool subreg_p, bool early_clobber, struct lra_insn_reg *next) |
541 | { | |
e16712b1 | 542 | lra_insn_reg *ir = lra_insn_reg_pool.allocate (); |
c6a6cdaa | 543 | ir->type = type; |
544 | ir->biggest_mode = mode; | |
40cec44a | 545 | if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (lra_reg_info[regno].biggest_mode) |
546 | && NONDEBUG_INSN_P (insn)) | |
fc8a0f60 | 547 | lra_reg_info[regno].biggest_mode = mode; |
c6a6cdaa | 548 | ir->subreg_p = subreg_p; |
549 | ir->early_clobber = early_clobber; | |
550 | ir->regno = regno; | |
551 | ir->next = next; | |
552 | return ir; | |
553 | } | |
554 | ||
c6a6cdaa | 555 | /* Free insn reg info list IR. */ |
556 | static void | |
557 | free_insn_regs (struct lra_insn_reg *ir) | |
558 | { | |
559 | struct lra_insn_reg *next_ir; | |
560 | ||
561 | for (; ir != NULL; ir = next_ir) | |
562 | { | |
563 | next_ir = ir->next; | |
e16712b1 | 564 | lra_insn_reg_pool.remove (ir); |
c6a6cdaa | 565 | } |
566 | } | |
567 | ||
568 | /* Finish pool for insn reg info. */ | |
569 | static void | |
570 | finish_insn_regs (void) | |
571 | { | |
e16712b1 | 572 | lra_insn_reg_pool.release (); |
c6a6cdaa | 573 | } |
574 | ||
575 | \f | |
576 | ||
577 | /* This page contains code dealing LRA insn info (or in other words | |
578 | LRA internal insn representation). */ | |
579 | ||
c6a6cdaa | 580 | /* Map INSN_CODE -> the static insn data. This info is valid during |
581 | all translation unit. */ | |
9fdbc432 | 582 | struct lra_static_insn_data *insn_code_data[NUM_INSN_CODES]; |
c6a6cdaa | 583 | |
584 | /* Debug insns are represented as a special insn with one input | |
585 | operand which is RTL expression in var_location. */ | |
586 | ||
587 | /* The following data are used as static insn operand data for all | |
588 | debug insns. If structure lra_operand_data is changed, the | |
589 | initializer should be changed too. */ | |
590 | static struct lra_operand_data debug_operand_data = | |
591 | { | |
592 | NULL, /* alternative */ | |
593 | VOIDmode, /* We are not interesting in the operand mode. */ | |
594 | OP_IN, | |
595 | 0, 0, 0, 0 | |
596 | }; | |
597 | ||
598 | /* The following data are used as static insn data for all debug | |
599 | insns. If structure lra_static_insn_data is changed, the | |
600 | initializer should be changed too. */ | |
601 | static struct lra_static_insn_data debug_insn_static_data = | |
602 | { | |
603 | &debug_operand_data, | |
604 | 0, /* Duplication operands #. */ | |
605 | -1, /* Commutative operand #. */ | |
606 | 1, /* Operands #. There is only one operand which is debug RTL | |
607 | expression. */ | |
608 | 0, /* Duplications #. */ | |
609 | 0, /* Alternatives #. We are not interesting in alternatives | |
610 | because we does not proceed debug_insns for reloads. */ | |
611 | NULL, /* Hard registers referenced in machine description. */ | |
612 | NULL /* Descriptions of operands in alternatives. */ | |
613 | }; | |
614 | ||
615 | /* Called once per compiler work to initialize some LRA data related | |
616 | to insns. */ | |
617 | static void | |
618 | init_insn_code_data_once (void) | |
619 | { | |
620 | memset (insn_code_data, 0, sizeof (insn_code_data)); | |
c6a6cdaa | 621 | } |
622 | ||
623 | /* Called once per compiler work to finalize some LRA data related to | |
624 | insns. */ | |
625 | static void | |
626 | finish_insn_code_data_once (void) | |
627 | { | |
9fdbc432 | 628 | for (unsigned int i = 0; i < NUM_INSN_CODES; i++) |
c6a6cdaa | 629 | { |
630 | if (insn_code_data[i] != NULL) | |
631 | free (insn_code_data[i]); | |
c6a6cdaa | 632 | } |
633 | } | |
634 | ||
c6a6cdaa | 635 | /* Return static insn data, allocate and setup if necessary. Although |
636 | dup_num is static data (it depends only on icode), to set it up we | |
637 | need to extract insn first. So recog_data should be valid for | |
638 | normal insn (ICODE >= 0) before the call. */ | |
639 | static struct lra_static_insn_data * | |
640 | get_static_insn_data (int icode, int nop, int ndup, int nalt) | |
641 | { | |
642 | struct lra_static_insn_data *data; | |
643 | size_t n_bytes; | |
644 | ||
9fdbc432 | 645 | lra_assert (icode < (int) NUM_INSN_CODES); |
c6a6cdaa | 646 | if (icode >= 0 && (data = insn_code_data[icode]) != NULL) |
647 | return data; | |
648 | lra_assert (nop >= 0 && ndup >= 0 && nalt >= 0); | |
649 | n_bytes = sizeof (struct lra_static_insn_data) | |
650 | + sizeof (struct lra_operand_data) * nop | |
651 | + sizeof (int) * ndup; | |
652 | data = XNEWVAR (struct lra_static_insn_data, n_bytes); | |
92b4b904 | 653 | data->operand_alternative = NULL; |
c6a6cdaa | 654 | data->n_operands = nop; |
655 | data->n_dups = ndup; | |
656 | data->n_alternatives = nalt; | |
657 | data->operand = ((struct lra_operand_data *) | |
658 | ((char *) data + sizeof (struct lra_static_insn_data))); | |
659 | data->dup_num = ((int *) ((char *) data->operand | |
660 | + sizeof (struct lra_operand_data) * nop)); | |
661 | if (icode >= 0) | |
662 | { | |
663 | int i; | |
664 | ||
665 | insn_code_data[icode] = data; | |
666 | for (i = 0; i < nop; i++) | |
667 | { | |
668 | data->operand[i].constraint | |
669 | = insn_data[icode].operand[i].constraint; | |
670 | data->operand[i].mode = insn_data[icode].operand[i].mode; | |
671 | data->operand[i].strict_low = insn_data[icode].operand[i].strict_low; | |
672 | data->operand[i].is_operator | |
673 | = insn_data[icode].operand[i].is_operator; | |
674 | data->operand[i].type | |
675 | = (data->operand[i].constraint[0] == '=' ? OP_OUT | |
676 | : data->operand[i].constraint[0] == '+' ? OP_INOUT | |
677 | : OP_IN); | |
678 | data->operand[i].is_address = false; | |
679 | } | |
680 | for (i = 0; i < ndup; i++) | |
681 | data->dup_num[i] = recog_data.dup_num[i]; | |
682 | } | |
683 | return data; | |
684 | } | |
685 | ||
686 | /* The current length of the following array. */ | |
687 | int lra_insn_recog_data_len; | |
688 | ||
689 | /* Map INSN_UID -> the insn recog data (NULL if unknown). */ | |
690 | lra_insn_recog_data_t *lra_insn_recog_data; | |
691 | ||
692 | /* Initialize LRA data about insns. */ | |
693 | static void | |
694 | init_insn_recog_data (void) | |
695 | { | |
696 | lra_insn_recog_data_len = 0; | |
697 | lra_insn_recog_data = NULL; | |
c6a6cdaa | 698 | } |
699 | ||
700 | /* Expand, if necessary, LRA data about insns. */ | |
701 | static void | |
702 | check_and_expand_insn_recog_data (int index) | |
703 | { | |
704 | int i, old; | |
705 | ||
706 | if (lra_insn_recog_data_len > index) | |
707 | return; | |
708 | old = lra_insn_recog_data_len; | |
709 | lra_insn_recog_data_len = index * 3 / 2 + 1; | |
710 | lra_insn_recog_data = XRESIZEVEC (lra_insn_recog_data_t, | |
711 | lra_insn_recog_data, | |
712 | lra_insn_recog_data_len); | |
713 | for (i = old; i < lra_insn_recog_data_len; i++) | |
714 | lra_insn_recog_data[i] = NULL; | |
715 | } | |
716 | ||
717 | /* Finish LRA DATA about insn. */ | |
718 | static void | |
719 | free_insn_recog_data (lra_insn_recog_data_t data) | |
720 | { | |
721 | if (data->operand_loc != NULL) | |
722 | free (data->operand_loc); | |
723 | if (data->dup_loc != NULL) | |
724 | free (data->dup_loc); | |
725 | if (data->arg_hard_regs != NULL) | |
726 | free (data->arg_hard_regs); | |
c6a6cdaa | 727 | if (data->icode < 0 && NONDEBUG_INSN_P (data->insn)) |
728 | { | |
729 | if (data->insn_static_data->operand_alternative != NULL) | |
92b4b904 | 730 | free (const_cast <operand_alternative *> |
731 | (data->insn_static_data->operand_alternative)); | |
c6a6cdaa | 732 | free_insn_regs (data->insn_static_data->hard_regs); |
733 | free (data->insn_static_data); | |
734 | } | |
735 | free_insn_regs (data->regs); | |
736 | data->regs = NULL; | |
737 | free (data); | |
738 | } | |
739 | ||
e16712b1 | 740 | /* Pools for copies. */ |
1dc6c44d | 741 | static object_allocator<lra_copy> lra_copy_pool ("lra copies"); |
e16712b1 | 742 | |
c6a6cdaa | 743 | /* Finish LRA data about all insns. */ |
744 | static void | |
745 | finish_insn_recog_data (void) | |
746 | { | |
747 | int i; | |
748 | lra_insn_recog_data_t data; | |
749 | ||
750 | for (i = 0; i < lra_insn_recog_data_len; i++) | |
751 | if ((data = lra_insn_recog_data[i]) != NULL) | |
752 | free_insn_recog_data (data); | |
753 | finish_insn_regs (); | |
e16712b1 | 754 | lra_copy_pool.release (); |
755 | lra_insn_reg_pool.release (); | |
c6a6cdaa | 756 | free (lra_insn_recog_data); |
757 | } | |
758 | ||
759 | /* Setup info about operands in alternatives of LRA DATA of insn. */ | |
760 | static void | |
92b4b904 | 761 | setup_operand_alternative (lra_insn_recog_data_t data, |
762 | const operand_alternative *op_alt) | |
c6a6cdaa | 763 | { |
92b4b904 | 764 | int i, j, nop, nalt; |
c6a6cdaa | 765 | int icode = data->icode; |
766 | struct lra_static_insn_data *static_data = data->insn_static_data; | |
767 | ||
c6a6cdaa | 768 | static_data->commutative = -1; |
769 | nop = static_data->n_operands; | |
c6a6cdaa | 770 | nalt = static_data->n_alternatives; |
92b4b904 | 771 | static_data->operand_alternative = op_alt; |
c6a6cdaa | 772 | for (i = 0; i < nop; i++) |
773 | { | |
92b4b904 | 774 | static_data->operand[i].early_clobber = false; |
775 | static_data->operand[i].is_address = false; | |
776 | if (static_data->operand[i].constraint[0] == '%') | |
c6a6cdaa | 777 | { |
92b4b904 | 778 | /* We currently only support one commutative pair of operands. */ |
779 | if (static_data->commutative < 0) | |
780 | static_data->commutative = i; | |
781 | else | |
782 | lra_assert (icode < 0); /* Asm */ | |
783 | /* The last operand should not be marked commutative. */ | |
784 | lra_assert (i != nop - 1); | |
c6a6cdaa | 785 | } |
786 | } | |
92b4b904 | 787 | for (j = 0; j < nalt; j++) |
788 | for (i = 0; i < nop; i++, op_alt++) | |
789 | { | |
790 | static_data->operand[i].early_clobber |= op_alt->earlyclobber; | |
791 | static_data->operand[i].is_address |= op_alt->is_address; | |
792 | } | |
c6a6cdaa | 793 | } |
794 | ||
795 | /* Recursively process X and collect info about registers, which are | |
796 | not the insn operands, in X with TYPE (in/out/inout) and flag that | |
797 | it is early clobbered in the insn (EARLY_CLOBBER) and add the info | |
798 | to LIST. X is a part of insn given by DATA. Return the result | |
799 | list. */ | |
800 | static struct lra_insn_reg * | |
801 | collect_non_operand_hard_regs (rtx *x, lra_insn_recog_data_t data, | |
802 | struct lra_insn_reg *list, | |
803 | enum op_type type, bool early_clobber) | |
804 | { | |
805 | int i, j, regno, last; | |
806 | bool subreg_p; | |
3754d046 | 807 | machine_mode mode; |
c6a6cdaa | 808 | struct lra_insn_reg *curr; |
809 | rtx op = *x; | |
810 | enum rtx_code code = GET_CODE (op); | |
811 | const char *fmt = GET_RTX_FORMAT (code); | |
812 | ||
813 | for (i = 0; i < data->insn_static_data->n_operands; i++) | |
814 | if (x == data->operand_loc[i]) | |
815 | /* It is an operand loc. Stop here. */ | |
816 | return list; | |
817 | for (i = 0; i < data->insn_static_data->n_dups; i++) | |
818 | if (x == data->dup_loc[i]) | |
819 | /* It is a dup loc. Stop here. */ | |
820 | return list; | |
821 | mode = GET_MODE (op); | |
822 | subreg_p = false; | |
823 | if (code == SUBREG) | |
824 | { | |
825 | op = SUBREG_REG (op); | |
826 | code = GET_CODE (op); | |
827 | if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (op))) | |
828 | { | |
829 | mode = GET_MODE (op); | |
830 | if (GET_MODE_SIZE (mode) > REGMODE_NATURAL_SIZE (mode)) | |
831 | subreg_p = true; | |
832 | } | |
833 | } | |
834 | if (REG_P (op)) | |
835 | { | |
836 | if ((regno = REGNO (op)) >= FIRST_PSEUDO_REGISTER) | |
837 | return list; | |
497ba60f | 838 | /* Process all regs even unallocatable ones as we need info |
839 | about all regs for rematerialization pass. */ | |
c6a6cdaa | 840 | for (last = regno + hard_regno_nregs[regno][mode]; |
841 | regno < last; | |
842 | regno++) | |
497ba60f | 843 | { |
844 | for (curr = list; curr != NULL; curr = curr->next) | |
845 | if (curr->regno == regno && curr->subreg_p == subreg_p | |
846 | && curr->biggest_mode == mode) | |
c6a6cdaa | 847 | { |
497ba60f | 848 | if (curr->type != type) |
849 | curr->type = OP_INOUT; | |
850 | if (curr->early_clobber != early_clobber) | |
851 | curr->early_clobber = true; | |
852 | break; | |
853 | } | |
854 | if (curr == NULL) | |
855 | { | |
856 | /* This is a new hard regno or the info can not be | |
857 | integrated into the found structure. */ | |
c6a6cdaa | 858 | #ifdef STACK_REGS |
497ba60f | 859 | early_clobber |
860 | = (early_clobber | |
861 | /* This clobber is to inform popping floating | |
862 | point stack only. */ | |
863 | && ! (FIRST_STACK_REG <= regno | |
864 | && regno <= LAST_STACK_REG)); | |
c6a6cdaa | 865 | #endif |
497ba60f | 866 | list = new_insn_reg (data->insn, regno, type, mode, subreg_p, |
867 | early_clobber, list); | |
868 | } | |
869 | } | |
c6a6cdaa | 870 | return list; |
871 | } | |
872 | switch (code) | |
873 | { | |
874 | case SET: | |
875 | list = collect_non_operand_hard_regs (&SET_DEST (op), data, | |
876 | list, OP_OUT, false); | |
877 | list = collect_non_operand_hard_regs (&SET_SRC (op), data, | |
878 | list, OP_IN, false); | |
879 | break; | |
880 | case CLOBBER: | |
881 | /* We treat clobber of non-operand hard registers as early | |
1a8f8886 | 882 | clobber (the behavior is expected from asm). */ |
c6a6cdaa | 883 | list = collect_non_operand_hard_regs (&XEXP (op, 0), data, |
884 | list, OP_OUT, true); | |
885 | break; | |
886 | case PRE_INC: case PRE_DEC: case POST_INC: case POST_DEC: | |
887 | list = collect_non_operand_hard_regs (&XEXP (op, 0), data, | |
888 | list, OP_INOUT, false); | |
889 | break; | |
890 | case PRE_MODIFY: case POST_MODIFY: | |
891 | list = collect_non_operand_hard_regs (&XEXP (op, 0), data, | |
892 | list, OP_INOUT, false); | |
893 | list = collect_non_operand_hard_regs (&XEXP (op, 1), data, | |
894 | list, OP_IN, false); | |
895 | break; | |
896 | default: | |
897 | fmt = GET_RTX_FORMAT (code); | |
898 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
899 | { | |
900 | if (fmt[i] == 'e') | |
901 | list = collect_non_operand_hard_regs (&XEXP (op, i), data, | |
902 | list, OP_IN, false); | |
903 | else if (fmt[i] == 'E') | |
904 | for (j = XVECLEN (op, i) - 1; j >= 0; j--) | |
905 | list = collect_non_operand_hard_regs (&XVECEXP (op, i, j), data, | |
906 | list, OP_IN, false); | |
907 | } | |
908 | } | |
909 | return list; | |
910 | } | |
911 | ||
912 | /* Set up and return info about INSN. Set up the info if it is not set up | |
913 | yet. */ | |
914 | lra_insn_recog_data_t | |
7f836b57 | 915 | lra_set_insn_recog_data (rtx_insn *insn) |
c6a6cdaa | 916 | { |
917 | lra_insn_recog_data_t data; | |
918 | int i, n, icode; | |
919 | rtx **locs; | |
920 | unsigned int uid = INSN_UID (insn); | |
921 | struct lra_static_insn_data *insn_static_data; | |
922 | ||
923 | check_and_expand_insn_recog_data (uid); | |
924 | if (DEBUG_INSN_P (insn)) | |
925 | icode = -1; | |
926 | else | |
927 | { | |
928 | icode = INSN_CODE (insn); | |
929 | if (icode < 0) | |
930 | /* It might be a new simple insn which is not recognized yet. */ | |
931 | INSN_CODE (insn) = icode = recog_memoized (insn); | |
932 | } | |
933 | data = XNEW (struct lra_insn_recog_data); | |
934 | lra_insn_recog_data[uid] = data; | |
935 | data->insn = insn; | |
936 | data->used_insn_alternative = -1; | |
937 | data->icode = icode; | |
938 | data->regs = NULL; | |
939 | if (DEBUG_INSN_P (insn)) | |
940 | { | |
941 | data->insn_static_data = &debug_insn_static_data; | |
942 | data->dup_loc = NULL; | |
943 | data->arg_hard_regs = NULL; | |
e1a797ad | 944 | data->preferred_alternatives = ALL_ALTERNATIVES; |
c6a6cdaa | 945 | data->operand_loc = XNEWVEC (rtx *, 1); |
946 | data->operand_loc[0] = &INSN_VAR_LOCATION_LOC (insn); | |
947 | return data; | |
948 | } | |
949 | if (icode < 0) | |
950 | { | |
92b4b904 | 951 | int nop, nalt; |
3754d046 | 952 | machine_mode operand_mode[MAX_RECOG_OPERANDS]; |
c6a6cdaa | 953 | const char *constraints[MAX_RECOG_OPERANDS]; |
954 | ||
955 | nop = asm_noperands (PATTERN (insn)); | |
956 | data->operand_loc = data->dup_loc = NULL; | |
92b4b904 | 957 | nalt = 1; |
c6a6cdaa | 958 | if (nop < 0) |
73a18f44 | 959 | { |
150967ab | 960 | /* It is a special insn like USE or CLOBBER. We should |
73a18f44 | 961 | recognize any regular insn otherwise LRA can do nothing |
962 | with this insn. */ | |
963 | gcc_assert (GET_CODE (PATTERN (insn)) == USE | |
964 | || GET_CODE (PATTERN (insn)) == CLOBBER | |
965 | || GET_CODE (PATTERN (insn)) == ASM_INPUT); | |
966 | data->insn_static_data = insn_static_data | |
92b4b904 | 967 | = get_static_insn_data (-1, 0, 0, nalt); |
73a18f44 | 968 | } |
c6a6cdaa | 969 | else |
970 | { | |
971 | /* expand_asm_operands makes sure there aren't too many | |
972 | operands. */ | |
973 | lra_assert (nop <= MAX_RECOG_OPERANDS); | |
974 | if (nop != 0) | |
975 | data->operand_loc = XNEWVEC (rtx *, nop); | |
976 | /* Now get the operand values and constraints out of the | |
977 | insn. */ | |
978 | decode_asm_operands (PATTERN (insn), NULL, | |
979 | data->operand_loc, | |
980 | constraints, operand_mode, NULL); | |
c6a6cdaa | 981 | if (nop > 0) |
982 | { | |
983 | const char *p = recog_data.constraints[0]; | |
1a8f8886 | 984 | |
c6a6cdaa | 985 | for (p = constraints[0]; *p; p++) |
92b4b904 | 986 | nalt += *p == ','; |
c6a6cdaa | 987 | } |
988 | data->insn_static_data = insn_static_data | |
92b4b904 | 989 | = get_static_insn_data (-1, nop, 0, nalt); |
c6a6cdaa | 990 | for (i = 0; i < nop; i++) |
991 | { | |
992 | insn_static_data->operand[i].mode = operand_mode[i]; | |
993 | insn_static_data->operand[i].constraint = constraints[i]; | |
994 | insn_static_data->operand[i].strict_low = false; | |
995 | insn_static_data->operand[i].is_operator = false; | |
996 | insn_static_data->operand[i].is_address = false; | |
997 | } | |
998 | } | |
999 | for (i = 0; i < insn_static_data->n_operands; i++) | |
1000 | insn_static_data->operand[i].type | |
1001 | = (insn_static_data->operand[i].constraint[0] == '=' ? OP_OUT | |
1002 | : insn_static_data->operand[i].constraint[0] == '+' ? OP_INOUT | |
1003 | : OP_IN); | |
e1a797ad | 1004 | data->preferred_alternatives = ALL_ALTERNATIVES; |
92b4b904 | 1005 | if (nop > 0) |
1006 | { | |
1007 | operand_alternative *op_alt = XCNEWVEC (operand_alternative, | |
1008 | nalt * nop); | |
1009 | preprocess_constraints (nop, nalt, constraints, op_alt); | |
1010 | setup_operand_alternative (data, op_alt); | |
1011 | } | |
c6a6cdaa | 1012 | } |
1013 | else | |
1014 | { | |
1015 | insn_extract (insn); | |
1016 | data->insn_static_data = insn_static_data | |
1017 | = get_static_insn_data (icode, insn_data[icode].n_operands, | |
1018 | insn_data[icode].n_dups, | |
1019 | insn_data[icode].n_alternatives); | |
1020 | n = insn_static_data->n_operands; | |
1021 | if (n == 0) | |
1022 | locs = NULL; | |
1023 | else | |
1024 | { | |
1025 | locs = XNEWVEC (rtx *, n); | |
1026 | memcpy (locs, recog_data.operand_loc, n * sizeof (rtx *)); | |
1027 | } | |
1028 | data->operand_loc = locs; | |
1029 | n = insn_static_data->n_dups; | |
1030 | if (n == 0) | |
1031 | locs = NULL; | |
1032 | else | |
1033 | { | |
1034 | locs = XNEWVEC (rtx *, n); | |
1035 | memcpy (locs, recog_data.dup_loc, n * sizeof (rtx *)); | |
1036 | } | |
1037 | data->dup_loc = locs; | |
e1a797ad | 1038 | data->preferred_alternatives = get_preferred_alternatives (insn); |
92b4b904 | 1039 | const operand_alternative *op_alt = preprocess_insn_constraints (icode); |
1040 | if (!insn_static_data->operand_alternative) | |
1041 | setup_operand_alternative (data, op_alt); | |
1042 | else if (op_alt != insn_static_data->operand_alternative) | |
1043 | insn_static_data->operand_alternative = op_alt; | |
c6a6cdaa | 1044 | } |
1045 | if (GET_CODE (PATTERN (insn)) == CLOBBER || GET_CODE (PATTERN (insn)) == USE) | |
1046 | insn_static_data->hard_regs = NULL; | |
1047 | else | |
1048 | insn_static_data->hard_regs | |
1049 | = collect_non_operand_hard_regs (&PATTERN (insn), data, | |
1050 | NULL, OP_IN, false); | |
c6a6cdaa | 1051 | data->arg_hard_regs = NULL; |
1052 | if (CALL_P (insn)) | |
1053 | { | |
853a01d6 | 1054 | bool use_p; |
c6a6cdaa | 1055 | rtx link; |
1056 | int n_hard_regs, regno, arg_hard_regs[FIRST_PSEUDO_REGISTER]; | |
1057 | ||
1058 | n_hard_regs = 0; | |
1059 | /* Finding implicit hard register usage. We believe it will be | |
1060 | not changed whatever transformations are used. Call insns | |
1061 | are such example. */ | |
1062 | for (link = CALL_INSN_FUNCTION_USAGE (insn); | |
1063 | link != NULL_RTX; | |
1064 | link = XEXP (link, 1)) | |
853a01d6 | 1065 | if (((use_p = GET_CODE (XEXP (link, 0)) == USE) |
1066 | || GET_CODE (XEXP (link, 0)) == CLOBBER) | |
c6a6cdaa | 1067 | && REG_P (XEXP (XEXP (link, 0), 0))) |
1068 | { | |
1069 | regno = REGNO (XEXP (XEXP (link, 0), 0)); | |
1070 | lra_assert (regno < FIRST_PSEUDO_REGISTER); | |
1071 | /* It is an argument register. */ | |
0933f1d9 | 1072 | for (i = REG_NREGS (XEXP (XEXP (link, 0), 0)) - 1; i >= 0; i--) |
853a01d6 | 1073 | arg_hard_regs[n_hard_regs++] |
1074 | = regno + i + (use_p ? 0 : FIRST_PSEUDO_REGISTER); | |
c6a6cdaa | 1075 | } |
1076 | if (n_hard_regs != 0) | |
1077 | { | |
1078 | arg_hard_regs[n_hard_regs++] = -1; | |
1079 | data->arg_hard_regs = XNEWVEC (int, n_hard_regs); | |
1080 | memcpy (data->arg_hard_regs, arg_hard_regs, | |
1081 | sizeof (int) * n_hard_regs); | |
1082 | } | |
1083 | } | |
1084 | /* Some output operand can be recognized only from the context not | |
1085 | from the constraints which are empty in this case. Call insn may | |
1086 | contain a hard register in set destination with empty constraint | |
1087 | and extract_insn treats them as an input. */ | |
1088 | for (i = 0; i < insn_static_data->n_operands; i++) | |
1089 | { | |
1090 | int j; | |
1091 | rtx pat, set; | |
1092 | struct lra_operand_data *operand = &insn_static_data->operand[i]; | |
1093 | ||
1094 | /* ??? Should we treat 'X' the same way. It looks to me that | |
1095 | 'X' means anything and empty constraint means we do not | |
1096 | care. */ | |
1097 | if (operand->type != OP_IN || *operand->constraint != '\0' | |
1098 | || operand->is_operator) | |
1099 | continue; | |
1100 | pat = PATTERN (insn); | |
1101 | if (GET_CODE (pat) == SET) | |
1102 | { | |
1103 | if (data->operand_loc[i] != &SET_DEST (pat)) | |
1104 | continue; | |
1105 | } | |
1106 | else if (GET_CODE (pat) == PARALLEL) | |
1107 | { | |
1108 | for (j = XVECLEN (pat, 0) - 1; j >= 0; j--) | |
1109 | { | |
1110 | set = XVECEXP (PATTERN (insn), 0, j); | |
1111 | if (GET_CODE (set) == SET | |
1112 | && &SET_DEST (set) == data->operand_loc[i]) | |
1113 | break; | |
1114 | } | |
1115 | if (j < 0) | |
1116 | continue; | |
1117 | } | |
1118 | else | |
1119 | continue; | |
1120 | operand->type = OP_OUT; | |
1121 | } | |
1122 | return data; | |
1123 | } | |
1124 | ||
1125 | /* Return info about insn give by UID. The info should be already set | |
1126 | up. */ | |
1127 | static lra_insn_recog_data_t | |
1128 | get_insn_recog_data_by_uid (int uid) | |
1129 | { | |
1130 | lra_insn_recog_data_t data; | |
1131 | ||
1132 | data = lra_insn_recog_data[uid]; | |
1133 | lra_assert (data != NULL); | |
1134 | return data; | |
1135 | } | |
1136 | ||
1137 | /* Invalidate all info about insn given by its UID. */ | |
1138 | static void | |
1139 | invalidate_insn_recog_data (int uid) | |
1140 | { | |
1141 | lra_insn_recog_data_t data; | |
1142 | ||
1143 | data = lra_insn_recog_data[uid]; | |
1144 | lra_assert (data != NULL); | |
1145 | free_insn_recog_data (data); | |
1146 | lra_insn_recog_data[uid] = NULL; | |
1147 | } | |
1148 | ||
1149 | /* Update all the insn info about INSN. It is usually called when | |
1150 | something in the insn was changed. Return the updated info. */ | |
1151 | lra_insn_recog_data_t | |
7f836b57 | 1152 | lra_update_insn_recog_data (rtx_insn *insn) |
c6a6cdaa | 1153 | { |
1154 | lra_insn_recog_data_t data; | |
1155 | int n; | |
1156 | unsigned int uid = INSN_UID (insn); | |
1157 | struct lra_static_insn_data *insn_static_data; | |
3b3a5e5f | 1158 | HOST_WIDE_INT sp_offset = 0; |
1a8f8886 | 1159 | |
c6a6cdaa | 1160 | check_and_expand_insn_recog_data (uid); |
1161 | if ((data = lra_insn_recog_data[uid]) != NULL | |
1162 | && data->icode != INSN_CODE (insn)) | |
1163 | { | |
3b3a5e5f | 1164 | sp_offset = data->sp_offset; |
c6a6cdaa | 1165 | invalidate_insn_data_regno_info (data, insn, get_insn_freq (insn)); |
1166 | invalidate_insn_recog_data (uid); | |
1167 | data = NULL; | |
1168 | } | |
1169 | if (data == NULL) | |
3b3a5e5f | 1170 | { |
1171 | data = lra_get_insn_recog_data (insn); | |
1172 | /* Initiate or restore SP offset. */ | |
1173 | data->sp_offset = sp_offset; | |
1174 | return data; | |
1175 | } | |
c6a6cdaa | 1176 | insn_static_data = data->insn_static_data; |
1177 | data->used_insn_alternative = -1; | |
1178 | if (DEBUG_INSN_P (insn)) | |
1179 | return data; | |
1180 | if (data->icode < 0) | |
1181 | { | |
1182 | int nop; | |
3754d046 | 1183 | machine_mode operand_mode[MAX_RECOG_OPERANDS]; |
c6a6cdaa | 1184 | const char *constraints[MAX_RECOG_OPERANDS]; |
1185 | ||
1186 | nop = asm_noperands (PATTERN (insn)); | |
1187 | if (nop >= 0) | |
1188 | { | |
1189 | lra_assert (nop == data->insn_static_data->n_operands); | |
1190 | /* Now get the operand values and constraints out of the | |
1191 | insn. */ | |
1192 | decode_asm_operands (PATTERN (insn), NULL, | |
1193 | data->operand_loc, | |
1194 | constraints, operand_mode, NULL); | |
c6a6cdaa | 1195 | |
382ecba7 | 1196 | if (flag_checking) |
1197 | for (int i = 0; i < nop; i++) | |
c6a6cdaa | 1198 | lra_assert |
1199 | (insn_static_data->operand[i].mode == operand_mode[i] | |
1200 | && insn_static_data->operand[i].constraint == constraints[i] | |
1201 | && ! insn_static_data->operand[i].is_operator); | |
c6a6cdaa | 1202 | } |
c6a6cdaa | 1203 | |
382ecba7 | 1204 | if (flag_checking) |
1205 | for (int i = 0; i < insn_static_data->n_operands; i++) | |
c6a6cdaa | 1206 | lra_assert |
1207 | (insn_static_data->operand[i].type | |
1208 | == (insn_static_data->operand[i].constraint[0] == '=' ? OP_OUT | |
1209 | : insn_static_data->operand[i].constraint[0] == '+' ? OP_INOUT | |
1210 | : OP_IN)); | |
c6a6cdaa | 1211 | } |
1212 | else | |
1213 | { | |
1214 | insn_extract (insn); | |
1215 | n = insn_static_data->n_operands; | |
1216 | if (n != 0) | |
1217 | memcpy (data->operand_loc, recog_data.operand_loc, n * sizeof (rtx *)); | |
1218 | n = insn_static_data->n_dups; | |
1219 | if (n != 0) | |
1220 | memcpy (data->dup_loc, recog_data.dup_loc, n * sizeof (rtx *)); | |
e1a797ad | 1221 | lra_assert (check_bool_attrs (insn)); |
c6a6cdaa | 1222 | } |
1223 | return data; | |
1224 | } | |
1225 | ||
1226 | /* Set up that INSN is using alternative ALT now. */ | |
1227 | void | |
7f836b57 | 1228 | lra_set_used_insn_alternative (rtx_insn *insn, int alt) |
c6a6cdaa | 1229 | { |
1230 | lra_insn_recog_data_t data; | |
1231 | ||
1232 | data = lra_get_insn_recog_data (insn); | |
1233 | data->used_insn_alternative = alt; | |
1234 | } | |
1235 | ||
1236 | /* Set up that insn with UID is using alternative ALT now. The insn | |
1237 | info should be already set up. */ | |
1238 | void | |
1239 | lra_set_used_insn_alternative_by_uid (int uid, int alt) | |
1240 | { | |
1241 | lra_insn_recog_data_t data; | |
1242 | ||
1243 | check_and_expand_insn_recog_data (uid); | |
1244 | data = lra_insn_recog_data[uid]; | |
1245 | lra_assert (data != NULL); | |
1246 | data->used_insn_alternative = alt; | |
1247 | } | |
1248 | ||
1249 | \f | |
1250 | ||
1251 | /* This page contains code dealing with common register info and | |
1252 | pseudo copies. */ | |
1253 | ||
1254 | /* The size of the following array. */ | |
1255 | static int reg_info_size; | |
1256 | /* Common info about each register. */ | |
1257 | struct lra_reg *lra_reg_info; | |
1258 | ||
1259 | /* Last register value. */ | |
1260 | static int last_reg_value; | |
1261 | ||
1262 | /* Return new register value. */ | |
1263 | static int | |
1264 | get_new_reg_value (void) | |
1265 | { | |
1266 | return ++last_reg_value; | |
1267 | } | |
1268 | ||
c6a6cdaa | 1269 | /* Vec referring to pseudo copies. */ |
f1f41a6c | 1270 | static vec<lra_copy_t> copy_vec; |
c6a6cdaa | 1271 | |
1272 | /* Initialize I-th element of lra_reg_info. */ | |
1273 | static inline void | |
1274 | initialize_lra_reg_info_element (int i) | |
1275 | { | |
1276 | bitmap_initialize (&lra_reg_info[i].insn_bitmap, ®_obstack); | |
1277 | #ifdef STACK_REGS | |
1278 | lra_reg_info[i].no_stack_p = false; | |
1279 | #endif | |
1280 | CLEAR_HARD_REG_SET (lra_reg_info[i].conflict_hard_regs); | |
f2cc6708 | 1281 | CLEAR_HARD_REG_SET (lra_reg_info[i].actual_call_used_reg_set); |
c6a6cdaa | 1282 | lra_reg_info[i].preferred_hard_regno1 = -1; |
1283 | lra_reg_info[i].preferred_hard_regno2 = -1; | |
1284 | lra_reg_info[i].preferred_hard_regno_profit1 = 0; | |
1285 | lra_reg_info[i].preferred_hard_regno_profit2 = 0; | |
fc8a0f60 | 1286 | lra_reg_info[i].biggest_mode = VOIDmode; |
c6a6cdaa | 1287 | lra_reg_info[i].live_ranges = NULL; |
1288 | lra_reg_info[i].nrefs = lra_reg_info[i].freq = 0; | |
1289 | lra_reg_info[i].last_reload = 0; | |
ab4ea053 | 1290 | lra_reg_info[i].restore_rtx = NULL_RTX; |
c6a6cdaa | 1291 | lra_reg_info[i].val = get_new_reg_value (); |
a1064490 | 1292 | lra_reg_info[i].offset = 0; |
c6a6cdaa | 1293 | lra_reg_info[i].copies = NULL; |
1294 | } | |
1295 | ||
1296 | /* Initialize common reg info and copies. */ | |
1297 | static void | |
1298 | init_reg_info (void) | |
1299 | { | |
1300 | int i; | |
1301 | ||
1302 | last_reg_value = 0; | |
1303 | reg_info_size = max_reg_num () * 3 / 2 + 1; | |
1304 | lra_reg_info = XNEWVEC (struct lra_reg, reg_info_size); | |
1305 | for (i = 0; i < reg_info_size; i++) | |
1306 | initialize_lra_reg_info_element (i); | |
c45ca67d | 1307 | copy_vec.truncate (0); |
c6a6cdaa | 1308 | } |
1309 | ||
1310 | ||
1311 | /* Finish common reg info and copies. */ | |
1312 | static void | |
1313 | finish_reg_info (void) | |
1314 | { | |
1315 | int i; | |
1316 | ||
1317 | for (i = 0; i < reg_info_size; i++) | |
1318 | bitmap_clear (&lra_reg_info[i].insn_bitmap); | |
1319 | free (lra_reg_info); | |
1320 | reg_info_size = 0; | |
c6a6cdaa | 1321 | } |
1322 | ||
1323 | /* Expand common reg info if it is necessary. */ | |
1324 | static void | |
1325 | expand_reg_info (void) | |
1326 | { | |
1327 | int i, old = reg_info_size; | |
1328 | ||
1329 | if (reg_info_size > max_reg_num ()) | |
1330 | return; | |
1331 | reg_info_size = max_reg_num () * 3 / 2 + 1; | |
1332 | lra_reg_info = XRESIZEVEC (struct lra_reg, lra_reg_info, reg_info_size); | |
1333 | for (i = old; i < reg_info_size; i++) | |
1334 | initialize_lra_reg_info_element (i); | |
1335 | } | |
1336 | ||
1337 | /* Free all copies. */ | |
1338 | void | |
1339 | lra_free_copies (void) | |
1340 | { | |
1341 | lra_copy_t cp; | |
1342 | ||
f1f41a6c | 1343 | while (copy_vec.length () != 0) |
c6a6cdaa | 1344 | { |
f1f41a6c | 1345 | cp = copy_vec.pop (); |
c6a6cdaa | 1346 | lra_reg_info[cp->regno1].copies = lra_reg_info[cp->regno2].copies = NULL; |
e16712b1 | 1347 | lra_copy_pool.remove (cp); |
c6a6cdaa | 1348 | } |
1349 | } | |
1350 | ||
1351 | /* Create copy of two pseudos REGNO1 and REGNO2. The copy execution | |
1352 | frequency is FREQ. */ | |
1353 | void | |
1354 | lra_create_copy (int regno1, int regno2, int freq) | |
1355 | { | |
1356 | bool regno1_dest_p; | |
1357 | lra_copy_t cp; | |
1358 | ||
1359 | lra_assert (regno1 != regno2); | |
1360 | regno1_dest_p = true; | |
1361 | if (regno1 > regno2) | |
1362 | { | |
a4f59596 | 1363 | std::swap (regno1, regno2); |
c6a6cdaa | 1364 | regno1_dest_p = false; |
c6a6cdaa | 1365 | } |
e16712b1 | 1366 | cp = lra_copy_pool.allocate (); |
f1f41a6c | 1367 | copy_vec.safe_push (cp); |
c6a6cdaa | 1368 | cp->regno1_dest_p = regno1_dest_p; |
1369 | cp->freq = freq; | |
1370 | cp->regno1 = regno1; | |
1371 | cp->regno2 = regno2; | |
1372 | cp->regno1_next = lra_reg_info[regno1].copies; | |
1373 | lra_reg_info[regno1].copies = cp; | |
1374 | cp->regno2_next = lra_reg_info[regno2].copies; | |
1375 | lra_reg_info[regno2].copies = cp; | |
1376 | if (lra_dump_file != NULL) | |
1377 | fprintf (lra_dump_file, " Creating copy r%d%sr%d@%d\n", | |
1378 | regno1, regno1_dest_p ? "<-" : "->", regno2, freq); | |
1379 | } | |
1380 | ||
1381 | /* Return N-th (0, 1, ...) copy. If there is no copy, return | |
1382 | NULL. */ | |
1383 | lra_copy_t | |
1384 | lra_get_copy (int n) | |
1385 | { | |
f1f41a6c | 1386 | if (n >= (int) copy_vec.length ()) |
c6a6cdaa | 1387 | return NULL; |
f1f41a6c | 1388 | return copy_vec[n]; |
c6a6cdaa | 1389 | } |
1390 | ||
1391 | \f | |
1392 | ||
1393 | /* This page contains code dealing with info about registers in | |
1394 | insns. */ | |
1395 | ||
1396 | /* Process X of insn UID recursively and add info (operand type is | |
1397 | given by TYPE, flag of that it is early clobber is EARLY_CLOBBER) | |
1398 | about registers in X to the insn DATA. */ | |
1399 | static void | |
1400 | add_regs_to_insn_regno_info (lra_insn_recog_data_t data, rtx x, int uid, | |
1401 | enum op_type type, bool early_clobber) | |
1402 | { | |
1403 | int i, j, regno; | |
1404 | bool subreg_p; | |
3754d046 | 1405 | machine_mode mode; |
c6a6cdaa | 1406 | const char *fmt; |
1407 | enum rtx_code code; | |
1408 | struct lra_insn_reg *curr; | |
1409 | ||
1410 | code = GET_CODE (x); | |
1411 | mode = GET_MODE (x); | |
1412 | subreg_p = false; | |
1413 | if (GET_CODE (x) == SUBREG) | |
1414 | { | |
1415 | x = SUBREG_REG (x); | |
1416 | code = GET_CODE (x); | |
1417 | if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))) | |
1418 | { | |
1419 | mode = GET_MODE (x); | |
1420 | if (GET_MODE_SIZE (mode) > REGMODE_NATURAL_SIZE (mode)) | |
1421 | subreg_p = true; | |
1422 | } | |
1423 | } | |
1424 | if (REG_P (x)) | |
1425 | { | |
1426 | regno = REGNO (x); | |
497ba60f | 1427 | /* Process all regs even unallocatable ones as we need info about |
1428 | all regs for rematerialization pass. */ | |
c6a6cdaa | 1429 | expand_reg_info (); |
1430 | if (bitmap_set_bit (&lra_reg_info[regno].insn_bitmap, uid)) | |
1431 | { | |
40cec44a | 1432 | data->regs = new_insn_reg (data->insn, regno, type, mode, subreg_p, |
c6a6cdaa | 1433 | early_clobber, data->regs); |
1434 | return; | |
1435 | } | |
1436 | else | |
1437 | { | |
1438 | for (curr = data->regs; curr != NULL; curr = curr->next) | |
1439 | if (curr->regno == regno) | |
1440 | { | |
1441 | if (curr->subreg_p != subreg_p || curr->biggest_mode != mode) | |
1442 | /* The info can not be integrated into the found | |
1443 | structure. */ | |
40cec44a | 1444 | data->regs = new_insn_reg (data->insn, regno, type, mode, |
1445 | subreg_p, early_clobber, | |
1446 | data->regs); | |
c6a6cdaa | 1447 | else |
1448 | { | |
1449 | if (curr->type != type) | |
1450 | curr->type = OP_INOUT; | |
1451 | if (curr->early_clobber != early_clobber) | |
1452 | curr->early_clobber = true; | |
1453 | } | |
1454 | return; | |
1455 | } | |
1456 | gcc_unreachable (); | |
1457 | } | |
1458 | } | |
1459 | ||
1460 | switch (code) | |
1461 | { | |
1462 | case SET: | |
1463 | add_regs_to_insn_regno_info (data, SET_DEST (x), uid, OP_OUT, false); | |
1464 | add_regs_to_insn_regno_info (data, SET_SRC (x), uid, OP_IN, false); | |
1465 | break; | |
1466 | case CLOBBER: | |
1467 | /* We treat clobber of non-operand hard registers as early | |
1a8f8886 | 1468 | clobber (the behavior is expected from asm). */ |
c6a6cdaa | 1469 | add_regs_to_insn_regno_info (data, XEXP (x, 0), uid, OP_OUT, true); |
1470 | break; | |
1471 | case PRE_INC: case PRE_DEC: case POST_INC: case POST_DEC: | |
1472 | add_regs_to_insn_regno_info (data, XEXP (x, 0), uid, OP_INOUT, false); | |
1473 | break; | |
1474 | case PRE_MODIFY: case POST_MODIFY: | |
1475 | add_regs_to_insn_regno_info (data, XEXP (x, 0), uid, OP_INOUT, false); | |
1476 | add_regs_to_insn_regno_info (data, XEXP (x, 1), uid, OP_IN, false); | |
1477 | break; | |
1478 | default: | |
1479 | if ((code != PARALLEL && code != EXPR_LIST) || type != OP_OUT) | |
1480 | /* Some targets place small structures in registers for return | |
1481 | values of functions, and those registers are wrapped in | |
1482 | PARALLEL that we may see as the destination of a SET. Here | |
1483 | is an example: | |
1484 | ||
1485 | (call_insn 13 12 14 2 (set (parallel:BLK [ | |
1486 | (expr_list:REG_DEP_TRUE (reg:DI 0 ax) | |
1487 | (const_int 0 [0])) | |
1488 | (expr_list:REG_DEP_TRUE (reg:DI 1 dx) | |
1489 | (const_int 8 [0x8])) | |
1490 | ]) | |
1491 | (call (mem:QI (symbol_ref:DI (... */ | |
1492 | type = OP_IN; | |
1493 | fmt = GET_RTX_FORMAT (code); | |
1494 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1495 | { | |
1496 | if (fmt[i] == 'e') | |
1497 | add_regs_to_insn_regno_info (data, XEXP (x, i), uid, type, false); | |
1498 | else if (fmt[i] == 'E') | |
1499 | { | |
1500 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
1501 | add_regs_to_insn_regno_info (data, XVECEXP (x, i, j), uid, | |
1502 | type, false); | |
1503 | } | |
1504 | } | |
1505 | } | |
1506 | } | |
1507 | ||
1508 | /* Return execution frequency of INSN. */ | |
1509 | static int | |
7f836b57 | 1510 | get_insn_freq (rtx_insn *insn) |
c6a6cdaa | 1511 | { |
91f71fa3 | 1512 | basic_block bb = BLOCK_FOR_INSN (insn); |
c6a6cdaa | 1513 | |
91f71fa3 | 1514 | gcc_checking_assert (bb != NULL); |
1515 | return REG_FREQ_FROM_BB (bb); | |
c6a6cdaa | 1516 | } |
1517 | ||
1518 | /* Invalidate all reg info of INSN with DATA and execution frequency | |
1519 | FREQ. Update common info about the invalidated registers. */ | |
1520 | static void | |
7f836b57 | 1521 | invalidate_insn_data_regno_info (lra_insn_recog_data_t data, rtx_insn *insn, |
c6a6cdaa | 1522 | int freq) |
1523 | { | |
1524 | int uid; | |
1525 | bool debug_p; | |
1526 | unsigned int i; | |
1527 | struct lra_insn_reg *ir, *next_ir; | |
1528 | ||
1529 | uid = INSN_UID (insn); | |
1530 | debug_p = DEBUG_INSN_P (insn); | |
1531 | for (ir = data->regs; ir != NULL; ir = next_ir) | |
1532 | { | |
1533 | i = ir->regno; | |
1534 | next_ir = ir->next; | |
e16712b1 | 1535 | lra_insn_reg_pool.remove (ir); |
c6a6cdaa | 1536 | bitmap_clear_bit (&lra_reg_info[i].insn_bitmap, uid); |
1537 | if (i >= FIRST_PSEUDO_REGISTER && ! debug_p) | |
1538 | { | |
1539 | lra_reg_info[i].nrefs--; | |
1540 | lra_reg_info[i].freq -= freq; | |
1541 | lra_assert (lra_reg_info[i].nrefs >= 0 && lra_reg_info[i].freq >= 0); | |
1542 | } | |
1543 | } | |
1544 | data->regs = NULL; | |
1545 | } | |
1546 | ||
1547 | /* Invalidate all reg info of INSN. Update common info about the | |
1548 | invalidated registers. */ | |
1549 | void | |
7f836b57 | 1550 | lra_invalidate_insn_regno_info (rtx_insn *insn) |
c6a6cdaa | 1551 | { |
1552 | invalidate_insn_data_regno_info (lra_get_insn_recog_data (insn), insn, | |
1553 | get_insn_freq (insn)); | |
1554 | } | |
1555 | ||
1556 | /* Update common reg info from reg info of insn given by its DATA and | |
1557 | execution frequency FREQ. */ | |
1558 | static void | |
1559 | setup_insn_reg_info (lra_insn_recog_data_t data, int freq) | |
1560 | { | |
1561 | unsigned int i; | |
1562 | struct lra_insn_reg *ir; | |
1563 | ||
1564 | for (ir = data->regs; ir != NULL; ir = ir->next) | |
1565 | if ((i = ir->regno) >= FIRST_PSEUDO_REGISTER) | |
1566 | { | |
1567 | lra_reg_info[i].nrefs++; | |
1568 | lra_reg_info[i].freq += freq; | |
1569 | } | |
1570 | } | |
1571 | ||
1572 | /* Set up insn reg info of INSN. Update common reg info from reg info | |
1573 | of INSN. */ | |
1574 | void | |
7f836b57 | 1575 | lra_update_insn_regno_info (rtx_insn *insn) |
c6a6cdaa | 1576 | { |
1577 | int i, uid, freq; | |
1578 | lra_insn_recog_data_t data; | |
1579 | struct lra_static_insn_data *static_data; | |
1580 | enum rtx_code code; | |
70ae5dc6 | 1581 | rtx link; |
1582 | ||
c6a6cdaa | 1583 | if (! INSN_P (insn)) |
1584 | return; | |
1585 | data = lra_get_insn_recog_data (insn); | |
1586 | static_data = data->insn_static_data; | |
1587 | freq = get_insn_freq (insn); | |
1588 | invalidate_insn_data_regno_info (data, insn, freq); | |
1589 | uid = INSN_UID (insn); | |
1590 | for (i = static_data->n_operands - 1; i >= 0; i--) | |
1591 | add_regs_to_insn_regno_info (data, *data->operand_loc[i], uid, | |
1592 | static_data->operand[i].type, | |
1593 | static_data->operand[i].early_clobber); | |
1594 | if ((code = GET_CODE (PATTERN (insn))) == CLOBBER || code == USE) | |
1595 | add_regs_to_insn_regno_info (data, XEXP (PATTERN (insn), 0), uid, | |
1596 | code == USE ? OP_IN : OP_OUT, false); | |
70ae5dc6 | 1597 | if (CALL_P (insn)) |
1598 | /* On some targets call insns can refer to pseudos in memory in | |
1599 | CALL_INSN_FUNCTION_USAGE list. Process them in order to | |
1600 | consider their occurrences in calls for different | |
1601 | transformations (e.g. inheritance) with given pseudos. */ | |
1602 | for (link = CALL_INSN_FUNCTION_USAGE (insn); | |
1603 | link != NULL_RTX; | |
1604 | link = XEXP (link, 1)) | |
1605 | if (((code = GET_CODE (XEXP (link, 0))) == USE || code == CLOBBER) | |
1606 | && MEM_P (XEXP (XEXP (link, 0), 0))) | |
1607 | add_regs_to_insn_regno_info (data, XEXP (XEXP (link, 0), 0), uid, | |
1608 | code == USE ? OP_IN : OP_OUT, false); | |
c6a6cdaa | 1609 | if (NONDEBUG_INSN_P (insn)) |
1610 | setup_insn_reg_info (data, freq); | |
1611 | } | |
1612 | ||
1613 | /* Return reg info of insn given by it UID. */ | |
1614 | struct lra_insn_reg * | |
1615 | lra_get_insn_regs (int uid) | |
1616 | { | |
1617 | lra_insn_recog_data_t data; | |
1618 | ||
1619 | data = get_insn_recog_data_by_uid (uid); | |
1620 | return data->regs; | |
1621 | } | |
1622 | ||
1623 | \f | |
1624 | ||
ab4ea053 | 1625 | /* Recursive hash function for RTL X. */ |
1626 | hashval_t | |
1627 | lra_rtx_hash (rtx x) | |
1628 | { | |
1629 | int i, j; | |
1630 | enum rtx_code code; | |
1631 | const char *fmt; | |
1632 | hashval_t val = 0; | |
1633 | ||
1634 | if (x == 0) | |
1635 | return val; | |
1636 | ||
1637 | code = GET_CODE (x); | |
1638 | val += (int) code + 4095; | |
1639 | ||
1640 | /* Some RTL can be compared nonrecursively. */ | |
1641 | switch (code) | |
1642 | { | |
1643 | case REG: | |
1644 | return val + REGNO (x); | |
1645 | ||
1646 | case LABEL_REF: | |
1647 | return iterative_hash_object (XEXP (x, 0), val); | |
1648 | ||
1649 | case SYMBOL_REF: | |
1650 | return iterative_hash_object (XSTR (x, 0), val); | |
1651 | ||
1652 | case SCRATCH: | |
1653 | case CONST_DOUBLE: | |
1654 | case CONST_INT: | |
1655 | case CONST_VECTOR: | |
1656 | return val; | |
1657 | ||
1658 | default: | |
1659 | break; | |
1660 | } | |
1661 | ||
1662 | /* Hash the elements. */ | |
1663 | fmt = GET_RTX_FORMAT (code); | |
1664 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1665 | { | |
1666 | switch (fmt[i]) | |
1667 | { | |
1668 | case 'w': | |
1669 | val += XWINT (x, i); | |
1670 | break; | |
1671 | ||
1672 | case 'n': | |
1673 | case 'i': | |
1674 | val += XINT (x, i); | |
1675 | break; | |
1676 | ||
1677 | case 'V': | |
1678 | case 'E': | |
1679 | val += XVECLEN (x, i); | |
1680 | ||
1681 | for (j = 0; j < XVECLEN (x, i); j++) | |
1682 | val += lra_rtx_hash (XVECEXP (x, i, j)); | |
1683 | break; | |
1684 | ||
1685 | case 'e': | |
1686 | val += lra_rtx_hash (XEXP (x, i)); | |
1687 | break; | |
1688 | ||
1689 | case 'S': | |
1690 | case 's': | |
1691 | val += htab_hash_string (XSTR (x, i)); | |
1692 | break; | |
1693 | ||
1694 | case 'u': | |
1695 | case '0': | |
1696 | case 't': | |
1697 | break; | |
1698 | ||
1699 | /* It is believed that rtx's at this level will never | |
1700 | contain anything but integers and other rtx's, except for | |
1701 | within LABEL_REFs and SYMBOL_REFs. */ | |
1702 | default: | |
1703 | abort (); | |
1704 | } | |
1705 | } | |
1706 | return val; | |
1707 | } | |
1708 | ||
1709 | \f | |
1710 | ||
c6a6cdaa | 1711 | /* This page contains code dealing with stack of the insns which |
1712 | should be processed by the next constraint pass. */ | |
1713 | ||
1714 | /* Bitmap used to put an insn on the stack only in one exemplar. */ | |
1715 | static sbitmap lra_constraint_insn_stack_bitmap; | |
1716 | ||
1717 | /* The stack itself. */ | |
7f836b57 | 1718 | vec<rtx_insn *> lra_constraint_insn_stack; |
c6a6cdaa | 1719 | |
1720 | /* Put INSN on the stack. If ALWAYS_UPDATE is true, always update the reg | |
1721 | info for INSN, otherwise only update it if INSN is not already on the | |
1722 | stack. */ | |
1723 | static inline void | |
7f836b57 | 1724 | lra_push_insn_1 (rtx_insn *insn, bool always_update) |
c6a6cdaa | 1725 | { |
1726 | unsigned int uid = INSN_UID (insn); | |
1727 | if (always_update) | |
1728 | lra_update_insn_regno_info (insn); | |
1729 | if (uid >= SBITMAP_SIZE (lra_constraint_insn_stack_bitmap)) | |
1730 | lra_constraint_insn_stack_bitmap = | |
1731 | sbitmap_resize (lra_constraint_insn_stack_bitmap, 3 * uid / 2, 0); | |
08b7917c | 1732 | if (bitmap_bit_p (lra_constraint_insn_stack_bitmap, uid)) |
c6a6cdaa | 1733 | return; |
08b7917c | 1734 | bitmap_set_bit (lra_constraint_insn_stack_bitmap, uid); |
c6a6cdaa | 1735 | if (! always_update) |
1736 | lra_update_insn_regno_info (insn); | |
f1f41a6c | 1737 | lra_constraint_insn_stack.safe_push (insn); |
c6a6cdaa | 1738 | } |
1739 | ||
1740 | /* Put INSN on the stack. */ | |
1741 | void | |
7f836b57 | 1742 | lra_push_insn (rtx_insn *insn) |
c6a6cdaa | 1743 | { |
1744 | lra_push_insn_1 (insn, false); | |
1745 | } | |
1746 | ||
1747 | /* Put INSN on the stack and update its reg info. */ | |
1748 | void | |
7f836b57 | 1749 | lra_push_insn_and_update_insn_regno_info (rtx_insn *insn) |
c6a6cdaa | 1750 | { |
1751 | lra_push_insn_1 (insn, true); | |
1752 | } | |
1753 | ||
1754 | /* Put insn with UID on the stack. */ | |
1755 | void | |
1756 | lra_push_insn_by_uid (unsigned int uid) | |
1757 | { | |
1758 | lra_push_insn (lra_insn_recog_data[uid]->insn); | |
1759 | } | |
1760 | ||
1761 | /* Take the last-inserted insns off the stack and return it. */ | |
7f836b57 | 1762 | rtx_insn * |
c6a6cdaa | 1763 | lra_pop_insn (void) |
1764 | { | |
7f836b57 | 1765 | rtx_insn *insn = lra_constraint_insn_stack.pop (); |
08b7917c | 1766 | bitmap_clear_bit (lra_constraint_insn_stack_bitmap, INSN_UID (insn)); |
c6a6cdaa | 1767 | return insn; |
1768 | } | |
1769 | ||
1770 | /* Return the current size of the insn stack. */ | |
1771 | unsigned int | |
1772 | lra_insn_stack_length (void) | |
1773 | { | |
f1f41a6c | 1774 | return lra_constraint_insn_stack.length (); |
c6a6cdaa | 1775 | } |
1776 | ||
1777 | /* Push insns FROM to TO (excluding it) going in reverse order. */ | |
1778 | static void | |
7f836b57 | 1779 | push_insns (rtx_insn *from, rtx_insn *to) |
c6a6cdaa | 1780 | { |
7f836b57 | 1781 | rtx_insn *insn; |
c6a6cdaa | 1782 | |
1783 | if (from == NULL_RTX) | |
1784 | return; | |
1785 | for (insn = from; insn != to; insn = PREV_INSN (insn)) | |
1786 | if (INSN_P (insn)) | |
1787 | lra_push_insn (insn); | |
1788 | } | |
1789 | ||
3b3a5e5f | 1790 | /* Set up sp offset for insn in range [FROM, LAST]. The offset is |
1791 | taken from the next BB insn after LAST or zero if there in such | |
1792 | insn. */ | |
1793 | static void | |
7f836b57 | 1794 | setup_sp_offset (rtx_insn *from, rtx_insn *last) |
3b3a5e5f | 1795 | { |
7f836b57 | 1796 | rtx_insn *before = next_nonnote_insn_bb (last); |
3b3a5e5f | 1797 | HOST_WIDE_INT offset = (before == NULL_RTX || ! INSN_P (before) |
1798 | ? 0 : lra_get_insn_recog_data (before)->sp_offset); | |
1799 | ||
7f836b57 | 1800 | for (rtx_insn *insn = from; insn != NEXT_INSN (last); insn = NEXT_INSN (insn)) |
3b3a5e5f | 1801 | lra_get_insn_recog_data (insn)->sp_offset = offset; |
1802 | } | |
1803 | ||
c6a6cdaa | 1804 | /* Emit insns BEFORE before INSN and insns AFTER after INSN. Put the |
1805 | insns onto the stack. Print about emitting the insns with | |
1806 | TITLE. */ | |
1807 | void | |
7f836b57 | 1808 | lra_process_new_insns (rtx_insn *insn, rtx_insn *before, rtx_insn *after, |
1809 | const char *title) | |
c6a6cdaa | 1810 | { |
7f836b57 | 1811 | rtx_insn *last; |
c6a6cdaa | 1812 | |
3b3a5e5f | 1813 | if (before == NULL_RTX && after == NULL_RTX) |
1814 | return; | |
1815 | if (lra_dump_file != NULL) | |
c6a6cdaa | 1816 | { |
6dde9719 | 1817 | dump_insn_slim (lra_dump_file, insn); |
c6a6cdaa | 1818 | if (before != NULL_RTX) |
1819 | { | |
1820 | fprintf (lra_dump_file," %s before:\n", title); | |
4cd001d5 | 1821 | dump_rtl_slim (lra_dump_file, before, NULL, -1, 0); |
c6a6cdaa | 1822 | } |
1823 | if (after != NULL_RTX) | |
1824 | { | |
1825 | fprintf (lra_dump_file, " %s after:\n", title); | |
4cd001d5 | 1826 | dump_rtl_slim (lra_dump_file, after, NULL, -1, 0); |
c6a6cdaa | 1827 | } |
1828 | fprintf (lra_dump_file, "\n"); | |
1829 | } | |
1830 | if (before != NULL_RTX) | |
1831 | { | |
743d9602 | 1832 | if (cfun->can_throw_non_call_exceptions) |
1833 | copy_reg_eh_region_note_forward (insn, before, NULL); | |
c6a6cdaa | 1834 | emit_insn_before (before, insn); |
1835 | push_insns (PREV_INSN (insn), PREV_INSN (before)); | |
3b3a5e5f | 1836 | setup_sp_offset (before, PREV_INSN (insn)); |
c6a6cdaa | 1837 | } |
1838 | if (after != NULL_RTX) | |
1839 | { | |
743d9602 | 1840 | if (cfun->can_throw_non_call_exceptions) |
1841 | copy_reg_eh_region_note_forward (insn, after, NULL); | |
c6a6cdaa | 1842 | for (last = after; NEXT_INSN (last) != NULL_RTX; last = NEXT_INSN (last)) |
1843 | ; | |
1844 | emit_insn_after (after, insn); | |
1845 | push_insns (last, insn); | |
3b3a5e5f | 1846 | setup_sp_offset (after, last); |
c6a6cdaa | 1847 | } |
743d9602 | 1848 | if (cfun->can_throw_non_call_exceptions) |
1849 | { | |
1850 | rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX); | |
1851 | if (note && !insn_could_throw_p (insn)) | |
1852 | remove_note (insn, note); | |
1853 | } | |
c6a6cdaa | 1854 | } |
c6a6cdaa | 1855 | \f |
1856 | ||
8c0d01a4 | 1857 | /* Replace all references to register OLD_REGNO in *LOC with pseudo |
06072e79 | 1858 | register NEW_REG. Try to simplify subreg of constant if SUBREG_P. |
1859 | Return true if any change was made. */ | |
8c0d01a4 | 1860 | bool |
06072e79 | 1861 | lra_substitute_pseudo (rtx *loc, int old_regno, rtx new_reg, bool subreg_p) |
8c0d01a4 | 1862 | { |
1863 | rtx x = *loc; | |
1864 | bool result = false; | |
1865 | enum rtx_code code; | |
1866 | const char *fmt; | |
1867 | int i, j; | |
1868 | ||
1869 | if (x == NULL_RTX) | |
1870 | return false; | |
1871 | ||
1872 | code = GET_CODE (x); | |
06072e79 | 1873 | if (code == SUBREG && subreg_p) |
8c0d01a4 | 1874 | { |
06072e79 | 1875 | rtx subst, inner = SUBREG_REG (x); |
1876 | /* Transform subreg of constant while we still have inner mode | |
1877 | of the subreg. The subreg internal should not be an insn | |
1878 | operand. */ | |
1879 | if (REG_P (inner) && (int) REGNO (inner) == old_regno | |
1880 | && CONSTANT_P (new_reg) | |
1881 | && (subst = simplify_subreg (GET_MODE (x), new_reg, GET_MODE (inner), | |
1882 | SUBREG_BYTE (x))) != NULL_RTX) | |
1883 | { | |
1884 | *loc = subst; | |
1885 | return true; | |
1886 | } | |
1887 | ||
1888 | } | |
1889 | else if (code == REG && (int) REGNO (x) == old_regno) | |
1890 | { | |
1891 | machine_mode mode = GET_MODE (x); | |
8c0d01a4 | 1892 | machine_mode inner_mode = GET_MODE (new_reg); |
1893 | ||
c77a06af | 1894 | if (mode != inner_mode |
1895 | && ! (CONST_INT_P (new_reg) && SCALAR_INT_MODE_P (mode))) | |
8c0d01a4 | 1896 | { |
1897 | if (GET_MODE_SIZE (mode) >= GET_MODE_SIZE (inner_mode) | |
1898 | || ! SCALAR_INT_MODE_P (inner_mode)) | |
1899 | new_reg = gen_rtx_SUBREG (mode, new_reg, 0); | |
1900 | else | |
1901 | new_reg = gen_lowpart_SUBREG (mode, new_reg); | |
1902 | } | |
1903 | *loc = new_reg; | |
1904 | return true; | |
1905 | } | |
1906 | ||
1907 | /* Scan all the operand sub-expressions. */ | |
1908 | fmt = GET_RTX_FORMAT (code); | |
1909 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1910 | { | |
1911 | if (fmt[i] == 'e') | |
1912 | { | |
06072e79 | 1913 | if (lra_substitute_pseudo (&XEXP (x, i), old_regno, |
1914 | new_reg, subreg_p)) | |
8c0d01a4 | 1915 | result = true; |
1916 | } | |
1917 | else if (fmt[i] == 'E') | |
1918 | { | |
1919 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
06072e79 | 1920 | if (lra_substitute_pseudo (&XVECEXP (x, i, j), old_regno, |
1921 | new_reg, subreg_p)) | |
8c0d01a4 | 1922 | result = true; |
1923 | } | |
1924 | } | |
1925 | return result; | |
1926 | } | |
1927 | ||
06072e79 | 1928 | /* Call lra_substitute_pseudo within an insn. Try to simplify subreg |
1929 | of constant if SUBREG_P. This won't update the insn ptr, just the | |
1930 | contents of the insn. */ | |
8c0d01a4 | 1931 | bool |
06072e79 | 1932 | lra_substitute_pseudo_within_insn (rtx_insn *insn, int old_regno, |
1933 | rtx new_reg, bool subreg_p) | |
8c0d01a4 | 1934 | { |
1935 | rtx loc = insn; | |
06072e79 | 1936 | return lra_substitute_pseudo (&loc, old_regno, new_reg, subreg_p); |
8c0d01a4 | 1937 | } |
1938 | ||
1939 | \f | |
1940 | ||
c6a6cdaa | 1941 | /* This page contains code dealing with scratches (changing them onto |
1942 | pseudos and restoring them from the pseudos). | |
1943 | ||
1944 | We change scratches into pseudos at the beginning of LRA to | |
1945 | simplify dealing with them (conflicts, hard register assignments). | |
1946 | ||
1947 | If the pseudo denoting scratch was spilled it means that we do need | |
1948 | a hard register for it. Such pseudos are transformed back to | |
1949 | scratches at the end of LRA. */ | |
1950 | ||
1951 | /* Description of location of a former scratch operand. */ | |
453f1a8c | 1952 | struct sloc |
c6a6cdaa | 1953 | { |
7f836b57 | 1954 | rtx_insn *insn; /* Insn where the scratch was. */ |
c6a6cdaa | 1955 | int nop; /* Number of the operand which was a scratch. */ |
1956 | }; | |
1957 | ||
453f1a8c | 1958 | typedef struct sloc *sloc_t; |
c6a6cdaa | 1959 | |
c6a6cdaa | 1960 | /* Locations of the former scratches. */ |
f1f41a6c | 1961 | static vec<sloc_t> scratches; |
c6a6cdaa | 1962 | |
1963 | /* Bitmap of scratch regnos. */ | |
1964 | static bitmap_head scratch_bitmap; | |
1965 | ||
1966 | /* Bitmap of scratch operands. */ | |
1967 | static bitmap_head scratch_operand_bitmap; | |
1968 | ||
1969 | /* Return true if pseudo REGNO is made of SCRATCH. */ | |
1970 | bool | |
1971 | lra_former_scratch_p (int regno) | |
1972 | { | |
1973 | return bitmap_bit_p (&scratch_bitmap, regno); | |
1974 | } | |
1975 | ||
1976 | /* Return true if the operand NOP of INSN is a former scratch. */ | |
1977 | bool | |
7f836b57 | 1978 | lra_former_scratch_operand_p (rtx_insn *insn, int nop) |
c6a6cdaa | 1979 | { |
1980 | return bitmap_bit_p (&scratch_operand_bitmap, | |
1981 | INSN_UID (insn) * MAX_RECOG_OPERANDS + nop) != 0; | |
1982 | } | |
1983 | ||
fb87313e | 1984 | /* Register operand NOP in INSN as a former scratch. It will be |
1985 | changed to scratch back, if it is necessary, at the LRA end. */ | |
1986 | void | |
1987 | lra_register_new_scratch_op (rtx_insn *insn, int nop) | |
1988 | { | |
1989 | lra_insn_recog_data_t id = lra_get_insn_recog_data (insn); | |
1990 | rtx op = *id->operand_loc[nop]; | |
1991 | sloc_t loc = XNEW (struct sloc); | |
1992 | lra_assert (REG_P (op)); | |
1993 | loc->insn = insn; | |
1994 | loc->nop = nop; | |
1995 | scratches.safe_push (loc); | |
1996 | bitmap_set_bit (&scratch_bitmap, REGNO (op)); | |
1997 | bitmap_set_bit (&scratch_operand_bitmap, | |
1998 | INSN_UID (insn) * MAX_RECOG_OPERANDS + nop); | |
1999 | add_reg_note (insn, REG_UNUSED, op); | |
2000 | } | |
2001 | ||
c6a6cdaa | 2002 | /* Change scratches onto pseudos and save their location. */ |
2003 | static void | |
2004 | remove_scratches (void) | |
2005 | { | |
2006 | int i; | |
2007 | bool insn_changed_p; | |
2008 | basic_block bb; | |
7f836b57 | 2009 | rtx_insn *insn; |
2010 | rtx reg; | |
c6a6cdaa | 2011 | lra_insn_recog_data_t id; |
2012 | struct lra_static_insn_data *static_id; | |
2013 | ||
f1f41a6c | 2014 | scratches.create (get_max_uid ()); |
c6a6cdaa | 2015 | bitmap_initialize (&scratch_bitmap, ®_obstack); |
2016 | bitmap_initialize (&scratch_operand_bitmap, ®_obstack); | |
fc00614f | 2017 | FOR_EACH_BB_FN (bb, cfun) |
c6a6cdaa | 2018 | FOR_BB_INSNS (bb, insn) |
2019 | if (INSN_P (insn)) | |
2020 | { | |
2021 | id = lra_get_insn_recog_data (insn); | |
2022 | static_id = id->insn_static_data; | |
2023 | insn_changed_p = false; | |
2024 | for (i = 0; i < static_id->n_operands; i++) | |
2025 | if (GET_CODE (*id->operand_loc[i]) == SCRATCH | |
2026 | && GET_MODE (*id->operand_loc[i]) != VOIDmode) | |
2027 | { | |
2028 | insn_changed_p = true; | |
2029 | *id->operand_loc[i] = reg | |
2030 | = lra_create_new_reg (static_id->operand[i].mode, | |
2031 | *id->operand_loc[i], ALL_REGS, NULL); | |
fb87313e | 2032 | lra_register_new_scratch_op (insn, i); |
c6a6cdaa | 2033 | if (lra_dump_file != NULL) |
2034 | fprintf (lra_dump_file, | |
2035 | "Removing SCRATCH in insn #%u (nop %d)\n", | |
2036 | INSN_UID (insn), i); | |
2037 | } | |
2038 | if (insn_changed_p) | |
2039 | /* Because we might use DF right after caller-saves sub-pass | |
2040 | we need to keep DF info up to date. */ | |
2041 | df_insn_rescan (insn); | |
2042 | } | |
2043 | } | |
2044 | ||
2045 | /* Changes pseudos created by function remove_scratches onto scratches. */ | |
2046 | static void | |
2047 | restore_scratches (void) | |
2048 | { | |
f1f41a6c | 2049 | int regno; |
2050 | unsigned i; | |
453f1a8c | 2051 | sloc_t loc; |
7f836b57 | 2052 | rtx_insn *last = NULL; |
c6a6cdaa | 2053 | lra_insn_recog_data_t id = NULL; |
2054 | ||
f1f41a6c | 2055 | for (i = 0; scratches.iterate (i, &loc); i++) |
c6a6cdaa | 2056 | { |
2715f63a | 2057 | /* Ignore already deleted insns. */ |
2058 | if (NOTE_P (loc->insn) | |
2059 | && NOTE_KIND (loc->insn) == NOTE_INSN_DELETED) | |
2060 | continue; | |
c6a6cdaa | 2061 | if (last != loc->insn) |
2062 | { | |
2063 | last = loc->insn; | |
2064 | id = lra_get_insn_recog_data (last); | |
2065 | } | |
2066 | if (REG_P (*id->operand_loc[loc->nop]) | |
2067 | && ((regno = REGNO (*id->operand_loc[loc->nop])) | |
2068 | >= FIRST_PSEUDO_REGISTER) | |
2069 | && lra_get_regno_hard_regno (regno) < 0) | |
2070 | { | |
2071 | /* It should be only case when scratch register with chosen | |
2072 | constraint 'X' did not get memory or hard register. */ | |
2073 | lra_assert (lra_former_scratch_p (regno)); | |
2074 | *id->operand_loc[loc->nop] | |
2075 | = gen_rtx_SCRATCH (GET_MODE (*id->operand_loc[loc->nop])); | |
2076 | lra_update_dup (id, loc->nop); | |
2077 | if (lra_dump_file != NULL) | |
2078 | fprintf (lra_dump_file, "Restoring SCRATCH in insn #%u(nop %d)\n", | |
2079 | INSN_UID (loc->insn), loc->nop); | |
2080 | } | |
2081 | } | |
f1f41a6c | 2082 | for (i = 0; scratches.iterate (i, &loc); i++) |
c6a6cdaa | 2083 | free (loc); |
f1f41a6c | 2084 | scratches.release (); |
c6a6cdaa | 2085 | bitmap_clear (&scratch_bitmap); |
2086 | bitmap_clear (&scratch_operand_bitmap); | |
2087 | } | |
2088 | ||
2089 | \f | |
2090 | ||
c6a6cdaa | 2091 | /* Function checks RTL for correctness. If FINAL_P is true, it is |
2092 | done at the end of LRA and the check is more rigorous. */ | |
2093 | static void | |
2094 | check_rtl (bool final_p) | |
2095 | { | |
c6a6cdaa | 2096 | basic_block bb; |
7f836b57 | 2097 | rtx_insn *insn; |
c6a6cdaa | 2098 | |
2099 | lra_assert (! final_p || reload_completed); | |
fc00614f | 2100 | FOR_EACH_BB_FN (bb, cfun) |
c6a6cdaa | 2101 | FOR_BB_INSNS (bb, insn) |
2102 | if (NONDEBUG_INSN_P (insn) | |
2103 | && GET_CODE (PATTERN (insn)) != USE | |
2104 | && GET_CODE (PATTERN (insn)) != CLOBBER | |
c6a6cdaa | 2105 | && GET_CODE (PATTERN (insn)) != ASM_INPUT) |
2106 | { | |
2107 | if (final_p) | |
2108 | { | |
835b8178 | 2109 | extract_constrain_insn (insn); |
c6a6cdaa | 2110 | continue; |
2111 | } | |
cba8c2e6 | 2112 | /* LRA code is based on assumption that all addresses can be |
2113 | correctly decomposed. LRA can generate reloads for | |
2114 | decomposable addresses. The decomposition code checks the | |
2115 | correctness of the addresses. So we don't need to check | |
76f778fd | 2116 | the addresses here. Don't call insn_invalid_p here, it can |
2117 | change the code at this stage. */ | |
2118 | if (recog_memoized (insn) < 0 && asm_noperands (PATTERN (insn)) < 0) | |
c6a6cdaa | 2119 | fatal_insn_not_found (insn); |
c6a6cdaa | 2120 | } |
2121 | } | |
c6a6cdaa | 2122 | |
2123 | /* Determine if the current function has an exception receiver block | |
2124 | that reaches the exit block via non-exceptional edges */ | |
2125 | static bool | |
2126 | has_nonexceptional_receiver (void) | |
2127 | { | |
2128 | edge e; | |
2129 | edge_iterator ei; | |
2130 | basic_block *tos, *worklist, bb; | |
2131 | ||
2132 | /* If we're not optimizing, then just err on the safe side. */ | |
2133 | if (!optimize) | |
2134 | return true; | |
1a8f8886 | 2135 | |
c6a6cdaa | 2136 | /* First determine which blocks can reach exit via normal paths. */ |
a28770e1 | 2137 | tos = worklist = XNEWVEC (basic_block, n_basic_blocks_for_fn (cfun) + 1); |
c6a6cdaa | 2138 | |
fc00614f | 2139 | FOR_EACH_BB_FN (bb, cfun) |
c6a6cdaa | 2140 | bb->flags &= ~BB_REACHABLE; |
2141 | ||
2142 | /* Place the exit block on our worklist. */ | |
34154e27 | 2143 | EXIT_BLOCK_PTR_FOR_FN (cfun)->flags |= BB_REACHABLE; |
2144 | *tos++ = EXIT_BLOCK_PTR_FOR_FN (cfun); | |
1a8f8886 | 2145 | |
c6a6cdaa | 2146 | /* Iterate: find everything reachable from what we've already seen. */ |
2147 | while (tos != worklist) | |
2148 | { | |
2149 | bb = *--tos; | |
2150 | ||
2151 | FOR_EACH_EDGE (e, ei, bb->preds) | |
2152 | if (e->flags & EDGE_ABNORMAL) | |
2153 | { | |
2154 | free (worklist); | |
2155 | return true; | |
2156 | } | |
2157 | else | |
2158 | { | |
2159 | basic_block src = e->src; | |
2160 | ||
2161 | if (!(src->flags & BB_REACHABLE)) | |
2162 | { | |
2163 | src->flags |= BB_REACHABLE; | |
2164 | *tos++ = src; | |
2165 | } | |
2166 | } | |
2167 | } | |
2168 | free (worklist); | |
2169 | /* No exceptional block reached exit unexceptionally. */ | |
2170 | return false; | |
2171 | } | |
2172 | ||
c6a6cdaa | 2173 | |
2174 | /* Process recursively X of INSN and add REG_INC notes if necessary. */ | |
2175 | static void | |
7f836b57 | 2176 | add_auto_inc_notes (rtx_insn *insn, rtx x) |
c6a6cdaa | 2177 | { |
2178 | enum rtx_code code = GET_CODE (x); | |
2179 | const char *fmt; | |
2180 | int i, j; | |
2181 | ||
2182 | if (code == MEM && auto_inc_p (XEXP (x, 0))) | |
2183 | { | |
2184 | add_reg_note (insn, REG_INC, XEXP (XEXP (x, 0), 0)); | |
2185 | return; | |
2186 | } | |
2187 | ||
2188 | /* Scan all X sub-expressions. */ | |
2189 | fmt = GET_RTX_FORMAT (code); | |
2190 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2191 | { | |
2192 | if (fmt[i] == 'e') | |
2193 | add_auto_inc_notes (insn, XEXP (x, i)); | |
2194 | else if (fmt[i] == 'E') | |
2195 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
2196 | add_auto_inc_notes (insn, XVECEXP (x, i, j)); | |
2197 | } | |
2198 | } | |
2199 | ||
c6a6cdaa | 2200 | |
2201 | /* Remove all REG_DEAD and REG_UNUSED notes and regenerate REG_INC. | |
2202 | We change pseudos by hard registers without notification of DF and | |
2203 | that can make the notes obsolete. DF-infrastructure does not deal | |
2204 | with REG_INC notes -- so we should regenerate them here. */ | |
2205 | static void | |
2206 | update_inc_notes (void) | |
2207 | { | |
2208 | rtx *pnote; | |
2209 | basic_block bb; | |
7f836b57 | 2210 | rtx_insn *insn; |
c6a6cdaa | 2211 | |
fc00614f | 2212 | FOR_EACH_BB_FN (bb, cfun) |
c6a6cdaa | 2213 | FOR_BB_INSNS (bb, insn) |
2214 | if (NONDEBUG_INSN_P (insn)) | |
2215 | { | |
2216 | pnote = ®_NOTES (insn); | |
2217 | while (*pnote != 0) | |
2218 | { | |
e2ca76ac | 2219 | if (REG_NOTE_KIND (*pnote) == REG_DEAD |
2220 | || REG_NOTE_KIND (*pnote) == REG_UNUSED | |
2221 | || REG_NOTE_KIND (*pnote) == REG_INC) | |
c6a6cdaa | 2222 | *pnote = XEXP (*pnote, 1); |
2223 | else | |
2224 | pnote = &XEXP (*pnote, 1); | |
2225 | } | |
32aa77d9 | 2226 | |
2227 | if (AUTO_INC_DEC) | |
2228 | add_auto_inc_notes (insn, PATTERN (insn)); | |
c6a6cdaa | 2229 | } |
2230 | } | |
2231 | ||
2232 | /* Set to 1 while in lra. */ | |
2233 | int lra_in_progress; | |
2234 | ||
edfb1d8f | 2235 | /* Start of pseudo regnos before the LRA. */ |
2236 | int lra_new_regno_start; | |
2237 | ||
1a8f8886 | 2238 | /* Start of reload pseudo regnos before the new spill pass. */ |
c6a6cdaa | 2239 | int lra_constraint_new_regno_start; |
2240 | ||
0f7b6a0d | 2241 | /* Avoid spilling pseudos with regno more than the following value if |
2242 | it is possible. */ | |
2243 | int lra_bad_spill_regno_start; | |
2244 | ||
1a8f8886 | 2245 | /* Inheritance pseudo regnos before the new spill pass. */ |
c6a6cdaa | 2246 | bitmap_head lra_inheritance_pseudos; |
2247 | ||
1a8f8886 | 2248 | /* Split regnos before the new spill pass. */ |
c6a6cdaa | 2249 | bitmap_head lra_split_regs; |
2250 | ||
1f3a048a | 2251 | /* Reload pseudo regnos before the new assignmnet pass which still can |
2252 | be spilled after the assinment pass as memory is also accepted in | |
2253 | insns for the reload pseudos. */ | |
c6a6cdaa | 2254 | bitmap_head lra_optional_reload_pseudos; |
2255 | ||
1f3a048a | 2256 | /* Pseudo regnos used for subreg reloads before the new assignment |
2257 | pass. Such pseudos still can be spilled after the assinment | |
2258 | pass. */ | |
2259 | bitmap_head lra_subreg_reload_pseudos; | |
2260 | ||
c6a6cdaa | 2261 | /* File used for output of LRA debug information. */ |
2262 | FILE *lra_dump_file; | |
2263 | ||
2264 | /* True if we should try spill into registers of different classes | |
2265 | instead of memory. */ | |
2266 | bool lra_reg_spill_p; | |
2267 | ||
2268 | /* Set up value LRA_REG_SPILL_P. */ | |
2269 | static void | |
2270 | setup_reg_spill_flag (void) | |
2271 | { | |
2272 | int cl, mode; | |
2273 | ||
2274 | if (targetm.spill_class != NULL) | |
2275 | for (cl = 0; cl < (int) LIM_REG_CLASSES; cl++) | |
2276 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
2277 | if (targetm.spill_class ((enum reg_class) cl, | |
3754d046 | 2278 | (machine_mode) mode) != NO_REGS) |
c6a6cdaa | 2279 | { |
2280 | lra_reg_spill_p = true; | |
2281 | return; | |
2282 | } | |
2283 | lra_reg_spill_p = false; | |
2284 | } | |
2285 | ||
2286 | /* True if the current function is too big to use regular algorithms | |
2287 | in LRA. In other words, we should use simpler and faster algorithms | |
2288 | in LRA. It also means we should not worry about generation code | |
2289 | for caller saves. The value is set up in IRA. */ | |
2290 | bool lra_simple_p; | |
2291 | ||
2292 | /* Major LRA entry function. F is a file should be used to dump LRA | |
2293 | debug info. */ | |
2294 | void | |
2295 | lra (FILE *f) | |
2296 | { | |
2297 | int i; | |
9628978f | 2298 | bool live_p, inserted_p; |
c6a6cdaa | 2299 | |
2300 | lra_dump_file = f; | |
2301 | ||
2302 | timevar_push (TV_LRA); | |
2303 | ||
ea99c7a1 | 2304 | /* Make sure that the last insn is a note. Some subsequent passes |
2305 | need it. */ | |
2306 | emit_note (NOTE_INSN_DELETED); | |
2307 | ||
fc8a0f60 | 2308 | COPY_HARD_REG_SET (lra_no_alloc_regs, ira_no_alloc_regs); |
2309 | ||
b85cafd3 | 2310 | init_reg_info (); |
2311 | expand_reg_info (); | |
2312 | ||
c6a6cdaa | 2313 | init_insn_recog_data (); |
2314 | ||
76f778fd | 2315 | /* Some quick check on RTL generated by previous passes. */ |
382ecba7 | 2316 | if (flag_checking) |
2317 | check_rtl (false); | |
c6a6cdaa | 2318 | |
76f778fd | 2319 | lra_in_progress = 1; |
2320 | ||
f95727ee | 2321 | lra_live_range_iter = lra_coalesce_iter = lra_constraint_iter = 0; |
2322 | lra_assignment_iter = lra_assignment_iter_after_spill = 0; | |
c6a6cdaa | 2323 | lra_inheritance_iter = lra_undo_inheritance_iter = 0; |
fa4f0b4e | 2324 | lra_rematerialization_iter = 0; |
c6a6cdaa | 2325 | |
2326 | setup_reg_spill_flag (); | |
2327 | ||
c6a6cdaa | 2328 | /* Function remove_scratches can creates new pseudos for clobbers -- |
2329 | so set up lra_constraint_new_regno_start before its call to | |
2330 | permit changing reg classes for pseudos created by this | |
2331 | simplification. */ | |
edfb1d8f | 2332 | lra_constraint_new_regno_start = lra_new_regno_start = max_reg_num (); |
0f7b6a0d | 2333 | lra_bad_spill_regno_start = INT_MAX; |
c6a6cdaa | 2334 | remove_scratches (); |
c6a6cdaa | 2335 | |
2336 | /* A function that has a non-local label that can reach the exit | |
2337 | block via non-exceptional paths must save all call-saved | |
2338 | registers. */ | |
2339 | if (cfun->has_nonlocal_label && has_nonexceptional_receiver ()) | |
2340 | crtl->saves_all_registers = 1; | |
2341 | ||
2342 | if (crtl->saves_all_registers) | |
2343 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
2344 | if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i)) | |
2345 | df_set_regs_ever_live (i, true); | |
2346 | ||
2347 | /* We don't DF from now and avoid its using because it is to | |
2348 | expensive when a lot of RTL changes are made. */ | |
2349 | df_set_flags (DF_NO_INSN_RESCAN); | |
f1f41a6c | 2350 | lra_constraint_insn_stack.create (get_max_uid ()); |
c6a6cdaa | 2351 | lra_constraint_insn_stack_bitmap = sbitmap_alloc (get_max_uid ()); |
53c5d9d4 | 2352 | bitmap_clear (lra_constraint_insn_stack_bitmap); |
c6a6cdaa | 2353 | lra_live_ranges_init (); |
2354 | lra_constraints_init (); | |
2355 | lra_curr_reload_num = 0; | |
7f836b57 | 2356 | push_insns (get_last_insn (), NULL); |
c6a6cdaa | 2357 | /* It is needed for the 1st coalescing. */ |
c6a6cdaa | 2358 | bitmap_initialize (&lra_inheritance_pseudos, ®_obstack); |
2359 | bitmap_initialize (&lra_split_regs, ®_obstack); | |
2360 | bitmap_initialize (&lra_optional_reload_pseudos, ®_obstack); | |
1f3a048a | 2361 | bitmap_initialize (&lra_subreg_reload_pseudos, ®_obstack); |
c6a6cdaa | 2362 | live_p = false; |
ea99c7a1 | 2363 | if (get_frame_size () != 0 && crtl->stack_alignment_needed) |
2364 | /* If we have a stack frame, we must align it now. The stack size | |
2365 | may be a part of the offset computation for register | |
2366 | elimination. */ | |
2367 | assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed); | |
61cd3e57 | 2368 | lra_init_equiv (); |
c6a6cdaa | 2369 | for (;;) |
2370 | { | |
2371 | for (;;) | |
2372 | { | |
c6a6cdaa | 2373 | /* We should try to assign hard registers to scratches even |
9628978f | 2374 | if there were no RTL transformations in lra_constraints. |
2375 | Also we should check IRA assignments on the first | |
2376 | iteration as they can be wrong because of early clobbers | |
2377 | operands which are ignored in IRA. */ | |
c6a6cdaa | 2378 | if (! lra_constraints (lra_constraint_iter == 0) |
9628978f | 2379 | && lra_constraint_iter > 1) |
c6a6cdaa | 2380 | break; |
2381 | /* Constraint transformations may result in that eliminable | |
2382 | hard regs become uneliminable and pseudos which use them | |
2383 | should be spilled. It is better to do it before pseudo | |
2384 | assignments. | |
2385 | ||
2386 | For example, rs6000 can make | |
2387 | RS6000_PIC_OFFSET_TABLE_REGNUM uneliminable if we started | |
2388 | to use a constant pool. */ | |
3b3a5e5f | 2389 | lra_eliminate (false, false); |
c6a6cdaa | 2390 | /* Do inheritance only for regular algorithms. */ |
2391 | if (! lra_simple_p) | |
f2cc6708 | 2392 | { |
fcf56aaf | 2393 | if (flag_ipa_ra) |
f2cc6708 | 2394 | { |
2395 | if (live_p) | |
2396 | lra_clear_live_ranges (); | |
2397 | /* As a side-effect of lra_create_live_ranges, we calculate | |
2398 | actual_call_used_reg_set, which is needed during | |
2399 | lra_inheritance. */ | |
04472658 | 2400 | lra_create_live_ranges (true, true); |
2045f87a | 2401 | live_p = true; |
f2cc6708 | 2402 | } |
2403 | lra_inheritance (); | |
2404 | } | |
d3d0b390 | 2405 | if (live_p) |
2406 | lra_clear_live_ranges (); | |
04472658 | 2407 | /* We need live ranges for lra_assign -- so build them. But |
2408 | don't remove dead insns or change global live info as we | |
2409 | can undo inheritance transformations after inheritance | |
2410 | pseudo assigning. */ | |
2411 | lra_create_live_ranges (true, false); | |
c6a6cdaa | 2412 | live_p = true; |
2413 | /* If we don't spill non-reload and non-inheritance pseudos, | |
2414 | there is no sense to run memory-memory move coalescing. | |
2415 | If inheritance pseudos were spilled, the memory-memory | |
2416 | moves involving them will be removed by pass undoing | |
2417 | inheritance. */ | |
2418 | if (lra_simple_p) | |
2419 | lra_assign (); | |
2420 | else | |
2421 | { | |
638e746e | 2422 | bool spill_p = !lra_assign (); |
2423 | ||
c6a6cdaa | 2424 | if (lra_undo_inheritance ()) |
2425 | live_p = false; | |
638e746e | 2426 | if (spill_p) |
2427 | { | |
2428 | if (! live_p) | |
2429 | { | |
04472658 | 2430 | lra_create_live_ranges (true, true); |
638e746e | 2431 | live_p = true; |
2432 | } | |
2433 | if (lra_coalesce ()) | |
2434 | live_p = false; | |
2435 | } | |
d3d0b390 | 2436 | if (! live_p) |
2437 | lra_clear_live_ranges (); | |
c6a6cdaa | 2438 | } |
2439 | } | |
95563487 | 2440 | /* Don't clear optional reloads bitmap until all constraints are |
2441 | satisfied as we need to differ them from regular reloads. */ | |
2442 | bitmap_clear (&lra_optional_reload_pseudos); | |
1f3a048a | 2443 | bitmap_clear (&lra_subreg_reload_pseudos); |
c6a6cdaa | 2444 | bitmap_clear (&lra_inheritance_pseudos); |
2445 | bitmap_clear (&lra_split_regs); | |
c6a6cdaa | 2446 | if (! live_p) |
2447 | { | |
2448 | /* We need full live info for spilling pseudos into | |
2449 | registers instead of memory. */ | |
04472658 | 2450 | lra_create_live_ranges (lra_reg_spill_p, true); |
c6a6cdaa | 2451 | live_p = true; |
2452 | } | |
04472658 | 2453 | /* We should check necessity for spilling here as the above live |
2454 | range pass can remove spilled pseudos. */ | |
2455 | if (! lra_need_for_spills_p ()) | |
2456 | break; | |
497ba60f | 2457 | /* Now we know what pseudos should be spilled. Try to |
2458 | rematerialize them first. */ | |
68474cd7 | 2459 | if (lra_remat ()) |
497ba60f | 2460 | { |
2461 | /* We need full live info -- see the comment above. */ | |
04472658 | 2462 | lra_create_live_ranges (lra_reg_spill_p, true); |
497ba60f | 2463 | live_p = true; |
2464 | if (! lra_need_for_spills_p ()) | |
2465 | break; | |
2466 | } | |
c6a6cdaa | 2467 | lra_spill (); |
2468 | /* Assignment of stack slots changes elimination offsets for | |
2469 | some eliminations. So update the offsets here. */ | |
3b3a5e5f | 2470 | lra_eliminate (false, false); |
0f7b6a0d | 2471 | lra_constraint_new_regno_start = max_reg_num (); |
2472 | if (lra_bad_spill_regno_start == INT_MAX | |
2473 | && lra_inheritance_iter > LRA_MAX_INHERITANCE_PASSES | |
2474 | && lra_rematerialization_iter > LRA_MAX_REMATERIALIZATION_PASSES) | |
2475 | /* After switching off inheritance and rematerialization | |
2476 | passes, avoid spilling reload pseudos will be created to | |
2477 | prevent LRA cycling in some complicated cases. */ | |
2478 | lra_bad_spill_regno_start = lra_constraint_new_regno_start; | |
f95727ee | 2479 | lra_assignment_iter_after_spill = 0; |
c6a6cdaa | 2480 | } |
2481 | restore_scratches (); | |
3b3a5e5f | 2482 | lra_eliminate (true, false); |
ae72d5b2 | 2483 | lra_final_code_change (); |
c6a6cdaa | 2484 | lra_in_progress = 0; |
d3d0b390 | 2485 | if (live_p) |
2486 | lra_clear_live_ranges (); | |
c6a6cdaa | 2487 | lra_live_ranges_finish (); |
2488 | lra_constraints_finish (); | |
2489 | finish_reg_info (); | |
2490 | sbitmap_free (lra_constraint_insn_stack_bitmap); | |
f1f41a6c | 2491 | lra_constraint_insn_stack.release (); |
c6a6cdaa | 2492 | finish_insn_recog_data (); |
2493 | regstat_free_n_sets_and_refs (); | |
2494 | regstat_free_ri (); | |
2495 | reload_completed = 1; | |
2496 | update_inc_notes (); | |
2497 | ||
2498 | inserted_p = fixup_abnormal_edges (); | |
2499 | ||
2500 | /* We've possibly turned single trapping insn into multiple ones. */ | |
2501 | if (cfun->can_throw_non_call_exceptions) | |
2502 | { | |
3c6549f8 | 2503 | auto_sbitmap blocks (last_basic_block_for_fn (cfun)); |
53c5d9d4 | 2504 | bitmap_ones (blocks); |
c6a6cdaa | 2505 | find_many_sub_basic_blocks (blocks); |
c6a6cdaa | 2506 | } |
2507 | ||
2508 | if (inserted_p) | |
2509 | commit_edge_insertions (); | |
2510 | ||
2511 | /* Replacing pseudos with their memory equivalents might have | |
2512 | created shared rtx. Subsequent passes would get confused | |
2513 | by this, so unshare everything here. */ | |
2514 | unshare_all_rtl_again (get_insns ()); | |
2515 | ||
382ecba7 | 2516 | if (flag_checking) |
2517 | check_rtl (true); | |
c6a6cdaa | 2518 | |
2519 | timevar_pop (TV_LRA); | |
2520 | } | |
2521 | ||
2522 | /* Called once per compiler to initialize LRA data once. */ | |
2523 | void | |
2524 | lra_init_once (void) | |
2525 | { | |
2526 | init_insn_code_data_once (); | |
2527 | } | |
2528 | ||
c6a6cdaa | 2529 | /* Called once per compiler to finish LRA data which are initialize |
2530 | once. */ | |
2531 | void | |
2532 | lra_finish_once (void) | |
2533 | { | |
2534 | finish_insn_code_data_once (); | |
2535 | } |