]>
Commit | Line | Data |
---|---|---|
c6a6cdaa | 1 | /* LRA (local register allocator) driver and LRA utilities. |
d353bf18 | 2 | Copyright (C) 2010-2015 Free Software Foundation, Inc. |
c6a6cdaa | 3 | Contributed by Vladimir Makarov <vmakarov@redhat.com>. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it under | |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 3, or (at your option) any later | |
10 | version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | ||
22 | /* The Local Register Allocator (LRA) is a replacement of former | |
23 | reload pass. It is focused to simplify code solving the reload | |
24 | pass tasks, to make the code maintenance easier, and to implement new | |
25 | perspective optimizations. | |
26 | ||
27 | The major LRA design solutions are: | |
28 | o division small manageable, separated sub-tasks | |
29 | o reflection of all transformations and decisions in RTL as more | |
30 | as possible | |
31 | o insn constraints as a primary source of the info (minimizing | |
32 | number of target-depended macros/hooks) | |
33 | ||
34 | In brief LRA works by iterative insn process with the final goal is | |
35 | to satisfy all insn and address constraints: | |
36 | o New reload insns (in brief reloads) and reload pseudos might be | |
37 | generated; | |
38 | o Some pseudos might be spilled to assign hard registers to | |
39 | new reload pseudos; | |
497ba60f | 40 | o Recalculating spilled pseudo values (rematerialization); |
c6a6cdaa | 41 | o Changing spilled pseudos to stack memory or their equivalences; |
42 | o Allocation stack memory changes the address displacement and | |
43 | new iteration is needed. | |
44 | ||
45 | Here is block diagram of LRA passes: | |
46 | ||
1f3a048a | 47 | ------------------------ |
48 | --------------- | Undo inheritance for | --------------- | |
49 | | Memory-memory | | spilled pseudos, | | New (and old) | | |
50 | | move coalesce |<---| splits for pseudos got |<-- | pseudos | | |
51 | --------------- | the same hard regs, | | assignment | | |
52 | Start | | and optional reloads | --------------- | |
53 | | | ------------------------ ^ | |
b28ae2d4 | 54 | V | ---------------- | |
55 | ----------- V | Update virtual | | | |
56 | | Remove |----> ------------>| register | | | |
57 | | scratches | ^ | displacements | | | |
58 | ----------- | ---------------- | | |
59 | | | | | |
60 | | V New | | |
497ba60f | 61 | | ------------ pseudos ------------------- |
62 | | |Constraints:| or insns | Inheritance/split | | |
63 | | | RTL |--------->| transformations | | |
64 | | | transfor- | | in EBB scope | | |
65 | | substi- | mations | ------------------- | |
66 | | tutions ------------ | |
67 | | | No change | |
68 | ---------------- V | |
69 | | Spilled pseudo | ------------------- | |
70 | | to memory |<----| Rematerialization | | |
71 | | substitution | ------------------- | |
72 | ---------------- | |
73 | | No susbtitions | |
74 | V | |
75 | ------------------------- | |
76 | | Hard regs substitution, | | |
77 | | devirtalization, and |------> Finish | |
78 | | restoring scratches got | | |
79 | | memory | | |
80 | ------------------------- | |
c6a6cdaa | 81 | |
82 | To speed up the process: | |
83 | o We process only insns affected by changes on previous | |
84 | iterations; | |
85 | o We don't use DFA-infrastructure because it results in much slower | |
86 | compiler speed than a special IR described below does; | |
87 | o We use a special insn representation for quick access to insn | |
88 | info which is always *synchronized* with the current RTL; | |
89 | o Insn IR is minimized by memory. It is divided on three parts: | |
90 | o one specific for each insn in RTL (only operand locations); | |
91 | o one common for all insns in RTL with the same insn code | |
92 | (different operand attributes from machine descriptions); | |
93 | o one oriented for maintenance of live info (list of pseudos). | |
94 | o Pseudo data: | |
95 | o all insns where the pseudo is referenced; | |
96 | o live info (conflicting hard regs, live ranges, # of | |
97 | references etc); | |
98 | o data used for assigning (preferred hard regs, costs etc). | |
99 | ||
100 | This file contains LRA driver, LRA utility functions and data, and | |
101 | code for dealing with scratches. */ | |
102 | ||
103 | #include "config.h" | |
104 | #include "system.h" | |
105 | #include "coretypes.h" | |
9ef16211 | 106 | #include "backend.h" |
107 | #include "tree.h" | |
c6a6cdaa | 108 | #include "rtl.h" |
9ef16211 | 109 | #include "df.h" |
c6a6cdaa | 110 | #include "tm_p.h" |
111 | #include "regs.h" | |
112 | #include "insn-config.h" | |
113 | #include "insn-codes.h" | |
114 | #include "recog.h" | |
115 | #include "output.h" | |
116 | #include "addresses.h" | |
c6a6cdaa | 117 | #include "flags.h" |
34517c64 | 118 | #include "optabs.h" |
d53441c8 | 119 | #include "alias.h" |
120 | #include "expmed.h" | |
121 | #include "dojump.h" | |
122 | #include "explow.h" | |
123 | #include "calls.h" | |
124 | #include "emit-rtl.h" | |
125 | #include "varasm.h" | |
126 | #include "stmt.h" | |
c6a6cdaa | 127 | #include "expr.h" |
94ea8568 | 128 | #include "cfgrtl.h" |
129 | #include "cfgbuild.h" | |
c6a6cdaa | 130 | #include "except.h" |
131 | #include "tree-pass.h" | |
132 | #include "timevar.h" | |
133 | #include "target.h" | |
c6a6cdaa | 134 | #include "ira.h" |
a940269d | 135 | #include "alloc-pool.h" |
9ef16211 | 136 | #include "lra.h" |
137 | #include "insn-attr.h" | |
c6a6cdaa | 138 | #include "lra-int.h" |
c6a6cdaa | 139 | |
8c0d01a4 | 140 | /* Dump bitmap SET with TITLE and BB INDEX. */ |
141 | void | |
142 | lra_dump_bitmap_with_title (const char *title, bitmap set, int index) | |
143 | { | |
144 | unsigned int i; | |
145 | int count; | |
146 | bitmap_iterator bi; | |
147 | static const int max_nums_on_line = 10; | |
148 | ||
149 | if (bitmap_empty_p (set)) | |
150 | return; | |
151 | fprintf (lra_dump_file, " %s %d:", title, index); | |
152 | fprintf (lra_dump_file, "\n"); | |
153 | count = max_nums_on_line + 1; | |
154 | EXECUTE_IF_SET_IN_BITMAP (set, 0, i, bi) | |
155 | { | |
156 | if (count > max_nums_on_line) | |
157 | { | |
158 | fprintf (lra_dump_file, "\n "); | |
159 | count = 0; | |
160 | } | |
161 | fprintf (lra_dump_file, " %4u", i); | |
162 | count++; | |
163 | } | |
164 | fprintf (lra_dump_file, "\n"); | |
165 | } | |
166 | ||
c6a6cdaa | 167 | /* Hard registers currently not available for allocation. It can |
168 | changed after some hard registers become not eliminable. */ | |
169 | HARD_REG_SET lra_no_alloc_regs; | |
170 | ||
171 | static int get_new_reg_value (void); | |
172 | static void expand_reg_info (void); | |
173 | static void invalidate_insn_recog_data (int); | |
7f836b57 | 174 | static int get_insn_freq (rtx_insn *); |
175 | static void invalidate_insn_data_regno_info (lra_insn_recog_data_t, | |
176 | rtx_insn *, int); | |
c6a6cdaa | 177 | |
178 | /* Expand all regno related info needed for LRA. */ | |
179 | static void | |
7619e612 | 180 | expand_reg_data (int old) |
c6a6cdaa | 181 | { |
182 | resize_reg_info (); | |
183 | expand_reg_info (); | |
184 | ira_expand_reg_equiv (); | |
7619e612 | 185 | for (int i = (int) max_reg_num () - 1; i >= old; i--) |
186 | lra_change_class (i, ALL_REGS, " Set", true); | |
c6a6cdaa | 187 | } |
188 | ||
189 | /* Create and return a new reg of ORIGINAL mode. If ORIGINAL is NULL | |
190 | or of VOIDmode, use MD_MODE for the new reg. Initialize its | |
191 | register class to RCLASS. Print message about assigning class | |
192 | RCLASS containing new register name TITLE unless it is NULL. Use | |
193 | attributes of ORIGINAL if it is a register. The created register | |
194 | will have unique held value. */ | |
195 | rtx | |
3754d046 | 196 | lra_create_new_reg_with_unique_value (machine_mode md_mode, rtx original, |
c6a6cdaa | 197 | enum reg_class rclass, const char *title) |
198 | { | |
3754d046 | 199 | machine_mode mode; |
c6a6cdaa | 200 | rtx new_reg; |
201 | ||
202 | if (original == NULL_RTX || (mode = GET_MODE (original)) == VOIDmode) | |
203 | mode = md_mode; | |
204 | lra_assert (mode != VOIDmode); | |
205 | new_reg = gen_reg_rtx (mode); | |
206 | if (original == NULL_RTX || ! REG_P (original)) | |
207 | { | |
208 | if (lra_dump_file != NULL) | |
209 | fprintf (lra_dump_file, " Creating newreg=%i", REGNO (new_reg)); | |
210 | } | |
211 | else | |
212 | { | |
213 | if (ORIGINAL_REGNO (original) >= FIRST_PSEUDO_REGISTER) | |
214 | ORIGINAL_REGNO (new_reg) = ORIGINAL_REGNO (original); | |
215 | REG_USERVAR_P (new_reg) = REG_USERVAR_P (original); | |
216 | REG_POINTER (new_reg) = REG_POINTER (original); | |
217 | REG_ATTRS (new_reg) = REG_ATTRS (original); | |
218 | if (lra_dump_file != NULL) | |
219 | fprintf (lra_dump_file, " Creating newreg=%i from oldreg=%i", | |
220 | REGNO (new_reg), REGNO (original)); | |
221 | } | |
222 | if (lra_dump_file != NULL) | |
223 | { | |
224 | if (title != NULL) | |
225 | fprintf (lra_dump_file, ", assigning class %s to%s%s r%d", | |
226 | reg_class_names[rclass], *title == '\0' ? "" : " ", | |
227 | title, REGNO (new_reg)); | |
228 | fprintf (lra_dump_file, "\n"); | |
229 | } | |
7619e612 | 230 | expand_reg_data (max_reg_num ()); |
c6a6cdaa | 231 | setup_reg_classes (REGNO (new_reg), rclass, NO_REGS, rclass); |
232 | return new_reg; | |
233 | } | |
234 | ||
235 | /* Analogous to the previous function but also inherits value of | |
236 | ORIGINAL. */ | |
237 | rtx | |
3754d046 | 238 | lra_create_new_reg (machine_mode md_mode, rtx original, |
c6a6cdaa | 239 | enum reg_class rclass, const char *title) |
240 | { | |
241 | rtx new_reg; | |
242 | ||
243 | new_reg | |
244 | = lra_create_new_reg_with_unique_value (md_mode, original, rclass, title); | |
245 | if (original != NULL_RTX && REG_P (original)) | |
a1064490 | 246 | lra_assign_reg_val (REGNO (original), REGNO (new_reg)); |
c6a6cdaa | 247 | return new_reg; |
248 | } | |
249 | ||
250 | /* Set up for REGNO unique hold value. */ | |
251 | void | |
252 | lra_set_regno_unique_value (int regno) | |
253 | { | |
254 | lra_reg_info[regno].val = get_new_reg_value (); | |
255 | } | |
256 | ||
3b3a5e5f | 257 | /* Invalidate INSN related info used by LRA. The info should never be |
258 | used after that. */ | |
c6a6cdaa | 259 | void |
7f836b57 | 260 | lra_invalidate_insn_data (rtx_insn *insn) |
c6a6cdaa | 261 | { |
262 | lra_invalidate_insn_regno_info (insn); | |
263 | invalidate_insn_recog_data (INSN_UID (insn)); | |
264 | } | |
265 | ||
266 | /* Mark INSN deleted and invalidate the insn related info used by | |
267 | LRA. */ | |
268 | void | |
7f836b57 | 269 | lra_set_insn_deleted (rtx_insn *insn) |
c6a6cdaa | 270 | { |
271 | lra_invalidate_insn_data (insn); | |
272 | SET_INSN_DELETED (insn); | |
273 | } | |
274 | ||
275 | /* Delete an unneeded INSN and any previous insns who sole purpose is | |
276 | loading data that is dead in INSN. */ | |
277 | void | |
7f836b57 | 278 | lra_delete_dead_insn (rtx_insn *insn) |
c6a6cdaa | 279 | { |
7f836b57 | 280 | rtx_insn *prev = prev_real_insn (insn); |
c6a6cdaa | 281 | rtx prev_dest; |
282 | ||
283 | /* If the previous insn sets a register that dies in our insn, | |
284 | delete it too. */ | |
285 | if (prev && GET_CODE (PATTERN (prev)) == SET | |
286 | && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest)) | |
287 | && reg_mentioned_p (prev_dest, PATTERN (insn)) | |
288 | && find_regno_note (insn, REG_DEAD, REGNO (prev_dest)) | |
289 | && ! side_effects_p (SET_SRC (PATTERN (prev)))) | |
290 | lra_delete_dead_insn (prev); | |
291 | ||
292 | lra_set_insn_deleted (insn); | |
293 | } | |
294 | ||
6c397456 | 295 | /* Emit insn x = y + z. Return NULL if we failed to do it. |
296 | Otherwise, return the insn. We don't use gen_add3_insn as it might | |
297 | clobber CC. */ | |
9ed997be | 298 | static rtx_insn * |
6c397456 | 299 | emit_add3_insn (rtx x, rtx y, rtx z) |
300 | { | |
57c26b3a | 301 | rtx_insn *last; |
6c397456 | 302 | |
303 | last = get_last_insn (); | |
79127ad5 | 304 | |
305 | if (have_addptr3_insn (x, y, z)) | |
306 | { | |
9ed997be | 307 | rtx_insn *insn = gen_addptr3_insn (x, y, z); |
79127ad5 | 308 | |
309 | /* If the target provides an "addptr" pattern it hopefully does | |
310 | for a reason. So falling back to the normal add would be | |
311 | a bug. */ | |
312 | lra_assert (insn != NULL_RTX); | |
313 | emit_insn (insn); | |
314 | return insn; | |
315 | } | |
316 | ||
d1f9b275 | 317 | rtx_insn *insn = emit_insn (gen_rtx_SET (x, gen_rtx_PLUS (GET_MODE (y), |
318 | y, z))); | |
6c397456 | 319 | if (recog_memoized (insn) < 0) |
320 | { | |
321 | delete_insns_since (last); | |
ed3e6e5d | 322 | insn = NULL; |
6c397456 | 323 | } |
324 | return insn; | |
325 | } | |
326 | ||
327 | /* Emit insn x = x + y. Return the insn. We use gen_add2_insn as the | |
328 | last resort. */ | |
9ed997be | 329 | static rtx_insn * |
6c397456 | 330 | emit_add2_insn (rtx x, rtx y) |
331 | { | |
9ed997be | 332 | rtx_insn *insn = emit_add3_insn (x, x, y); |
6c397456 | 333 | if (insn == NULL_RTX) |
334 | { | |
335 | insn = gen_add2_insn (x, y); | |
336 | if (insn != NULL_RTX) | |
337 | emit_insn (insn); | |
338 | } | |
339 | return insn; | |
340 | } | |
341 | ||
c6a6cdaa | 342 | /* Target checks operands through operand predicates to recognize an |
343 | insn. We should have a special precaution to generate add insns | |
344 | which are frequent results of elimination. | |
345 | ||
346 | Emit insns for x = y + z. X can be used to store intermediate | |
347 | values and should be not in Y and Z when we use X to store an | |
348 | intermediate value. Y + Z should form [base] [+ index[ * scale]] [ | |
349 | + disp] where base and index are registers, disp and scale are | |
350 | constants. Y should contain base if it is present, Z should | |
351 | contain disp if any. index[*scale] can be part of Y or Z. */ | |
352 | void | |
353 | lra_emit_add (rtx x, rtx y, rtx z) | |
354 | { | |
355 | int old; | |
57c26b3a | 356 | rtx_insn *last; |
c6a6cdaa | 357 | rtx a1, a2, base, index, disp, scale, index_scale; |
358 | bool ok_p; | |
359 | ||
9ed997be | 360 | rtx_insn *add3_insn = emit_add3_insn (x, y, z); |
c6a6cdaa | 361 | old = max_reg_num (); |
ed3e6e5d | 362 | if (add3_insn != NULL) |
6c397456 | 363 | ; |
c6a6cdaa | 364 | else |
365 | { | |
366 | disp = a2 = NULL_RTX; | |
367 | if (GET_CODE (y) == PLUS) | |
368 | { | |
369 | a1 = XEXP (y, 0); | |
370 | a2 = XEXP (y, 1); | |
371 | disp = z; | |
372 | } | |
373 | else | |
374 | { | |
375 | a1 = y; | |
376 | if (CONSTANT_P (z)) | |
377 | disp = z; | |
378 | else | |
379 | a2 = z; | |
380 | } | |
381 | index_scale = scale = NULL_RTX; | |
382 | if (GET_CODE (a1) == MULT) | |
383 | { | |
384 | index_scale = a1; | |
385 | index = XEXP (a1, 0); | |
386 | scale = XEXP (a1, 1); | |
387 | base = a2; | |
388 | } | |
389 | else if (a2 != NULL_RTX && GET_CODE (a2) == MULT) | |
390 | { | |
391 | index_scale = a2; | |
392 | index = XEXP (a2, 0); | |
393 | scale = XEXP (a2, 1); | |
394 | base = a1; | |
395 | } | |
396 | else | |
397 | { | |
398 | base = a1; | |
399 | index = a2; | |
400 | } | |
1c1417f1 | 401 | if (! (REG_P (base) || GET_CODE (base) == SUBREG) |
402 | || (index != NULL_RTX | |
403 | && ! (REG_P (index) || GET_CODE (index) == SUBREG)) | |
c6a6cdaa | 404 | || (disp != NULL_RTX && ! CONSTANT_P (disp)) |
405 | || (scale != NULL_RTX && ! CONSTANT_P (scale))) | |
406 | { | |
6c397456 | 407 | /* Probably we have no 3 op add. Last chance is to use 2-op |
408 | add insn. To succeed, don't move Z to X as an address | |
409 | segment always comes in Y. Otherwise, we might fail when | |
410 | adding the address segment to register. */ | |
c6a6cdaa | 411 | lra_assert (x != y && x != z); |
0178c26e | 412 | emit_move_insn (x, y); |
9ed997be | 413 | rtx_insn *insn = emit_add2_insn (x, z); |
6c397456 | 414 | lra_assert (insn != NULL_RTX); |
c6a6cdaa | 415 | } |
416 | else | |
417 | { | |
418 | if (index_scale == NULL_RTX) | |
419 | index_scale = index; | |
420 | if (disp == NULL_RTX) | |
421 | { | |
422 | /* Generate x = index_scale; x = x + base. */ | |
423 | lra_assert (index_scale != NULL_RTX && base != NULL_RTX); | |
424 | emit_move_insn (x, index_scale); | |
9ed997be | 425 | rtx_insn *insn = emit_add2_insn (x, base); |
6c397456 | 426 | lra_assert (insn != NULL_RTX); |
c6a6cdaa | 427 | } |
428 | else if (scale == NULL_RTX) | |
429 | { | |
430 | /* Try x = base + disp. */ | |
431 | lra_assert (base != NULL_RTX); | |
432 | last = get_last_insn (); | |
ed3e6e5d | 433 | rtx_insn *move_insn = |
434 | emit_move_insn (x, gen_rtx_PLUS (GET_MODE (base), base, disp)); | |
435 | if (recog_memoized (move_insn) < 0) | |
c6a6cdaa | 436 | { |
437 | delete_insns_since (last); | |
438 | /* Generate x = disp; x = x + base. */ | |
439 | emit_move_insn (x, disp); | |
9ed997be | 440 | rtx_insn *add2_insn = emit_add2_insn (x, base); |
ed3e6e5d | 441 | lra_assert (add2_insn != NULL_RTX); |
c6a6cdaa | 442 | } |
443 | /* Generate x = x + index. */ | |
444 | if (index != NULL_RTX) | |
445 | { | |
9ed997be | 446 | rtx_insn *insn = emit_add2_insn (x, index); |
6c397456 | 447 | lra_assert (insn != NULL_RTX); |
c6a6cdaa | 448 | } |
449 | } | |
450 | else | |
451 | { | |
452 | /* Try x = index_scale; x = x + disp; x = x + base. */ | |
453 | last = get_last_insn (); | |
ed3e6e5d | 454 | rtx_insn *move_insn = emit_move_insn (x, index_scale); |
c6a6cdaa | 455 | ok_p = false; |
ed3e6e5d | 456 | if (recog_memoized (move_insn) >= 0) |
c6a6cdaa | 457 | { |
9ed997be | 458 | rtx_insn *insn = emit_add2_insn (x, disp); |
c6a6cdaa | 459 | if (insn != NULL_RTX) |
460 | { | |
ee61ca2e | 461 | insn = emit_add2_insn (x, base); |
c6a6cdaa | 462 | if (insn != NULL_RTX) |
6c397456 | 463 | ok_p = true; |
c6a6cdaa | 464 | } |
465 | } | |
466 | if (! ok_p) | |
467 | { | |
468 | delete_insns_since (last); | |
469 | /* Generate x = disp; x = x + base; x = x + index_scale. */ | |
470 | emit_move_insn (x, disp); | |
9ed997be | 471 | rtx_insn *insn = emit_add2_insn (x, base); |
6c397456 | 472 | lra_assert (insn != NULL_RTX); |
473 | insn = emit_add2_insn (x, index_scale); | |
474 | lra_assert (insn != NULL_RTX); | |
c6a6cdaa | 475 | } |
476 | } | |
477 | } | |
478 | } | |
479 | /* Functions emit_... can create pseudos -- so expand the pseudo | |
480 | data. */ | |
481 | if (old != max_reg_num ()) | |
7619e612 | 482 | expand_reg_data (old); |
c6a6cdaa | 483 | } |
484 | ||
485 | /* The number of emitted reload insns so far. */ | |
486 | int lra_curr_reload_num; | |
487 | ||
488 | /* Emit x := y, processing special case when y = u + v or y = u + v * | |
489 | scale + w through emit_add (Y can be an address which is base + | |
490 | index reg * scale + displacement in general case). X may be used | |
491 | as intermediate result therefore it should be not in Y. */ | |
492 | void | |
493 | lra_emit_move (rtx x, rtx y) | |
494 | { | |
495 | int old; | |
496 | ||
497 | if (GET_CODE (y) != PLUS) | |
498 | { | |
499 | if (rtx_equal_p (x, y)) | |
500 | return; | |
501 | old = max_reg_num (); | |
502 | emit_move_insn (x, y); | |
503 | if (REG_P (x)) | |
504 | lra_reg_info[ORIGINAL_REGNO (x)].last_reload = ++lra_curr_reload_num; | |
505 | /* Function emit_move can create pseudos -- so expand the pseudo | |
506 | data. */ | |
507 | if (old != max_reg_num ()) | |
7619e612 | 508 | expand_reg_data (old); |
c6a6cdaa | 509 | return; |
510 | } | |
511 | lra_emit_add (x, XEXP (y, 0), XEXP (y, 1)); | |
512 | } | |
513 | ||
514 | /* Update insn operands which are duplication of operands whose | |
515 | numbers are in array of NOPS (with end marker -1). The insn is | |
516 | represented by its LRA internal representation ID. */ | |
517 | void | |
518 | lra_update_dups (lra_insn_recog_data_t id, signed char *nops) | |
519 | { | |
520 | int i, j, nop; | |
521 | struct lra_static_insn_data *static_id = id->insn_static_data; | |
522 | ||
523 | for (i = 0; i < static_id->n_dups; i++) | |
524 | for (j = 0; (nop = nops[j]) >= 0; j++) | |
525 | if (static_id->dup_num[i] == nop) | |
526 | *id->dup_loc[i] = *id->operand_loc[nop]; | |
527 | } | |
528 | ||
529 | \f | |
530 | ||
531 | /* This page contains code dealing with info about registers in the | |
532 | insns. */ | |
533 | ||
534 | /* Pools for insn reg info. */ | |
16f90944 | 535 | pool_allocator<lra_insn_reg> lra_insn_reg::pool ("insn regs", 100); |
c6a6cdaa | 536 | |
40cec44a | 537 | /* Create LRA insn related info about a reference to REGNO in INSN with |
538 | TYPE (in/out/inout), biggest reference mode MODE, flag that it is | |
c6a6cdaa | 539 | reference through subreg (SUBREG_P), flag that is early clobbered |
540 | in the insn (EARLY_CLOBBER), and reference to the next insn reg | |
541 | info (NEXT). */ | |
542 | static struct lra_insn_reg * | |
7f836b57 | 543 | new_insn_reg (rtx_insn *insn, int regno, enum op_type type, |
3754d046 | 544 | machine_mode mode, |
c6a6cdaa | 545 | bool subreg_p, bool early_clobber, struct lra_insn_reg *next) |
546 | { | |
16f90944 | 547 | lra_insn_reg *ir = new lra_insn_reg (); |
c6a6cdaa | 548 | ir->type = type; |
549 | ir->biggest_mode = mode; | |
40cec44a | 550 | if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (lra_reg_info[regno].biggest_mode) |
551 | && NONDEBUG_INSN_P (insn)) | |
fc8a0f60 | 552 | lra_reg_info[regno].biggest_mode = mode; |
c6a6cdaa | 553 | ir->subreg_p = subreg_p; |
554 | ir->early_clobber = early_clobber; | |
555 | ir->regno = regno; | |
556 | ir->next = next; | |
557 | return ir; | |
558 | } | |
559 | ||
c6a6cdaa | 560 | /* Free insn reg info list IR. */ |
561 | static void | |
562 | free_insn_regs (struct lra_insn_reg *ir) | |
563 | { | |
564 | struct lra_insn_reg *next_ir; | |
565 | ||
566 | for (; ir != NULL; ir = next_ir) | |
567 | { | |
568 | next_ir = ir->next; | |
16f90944 | 569 | delete ir; |
c6a6cdaa | 570 | } |
571 | } | |
572 | ||
573 | /* Finish pool for insn reg info. */ | |
574 | static void | |
575 | finish_insn_regs (void) | |
576 | { | |
16f90944 | 577 | lra_insn_reg::pool.release (); |
c6a6cdaa | 578 | } |
579 | ||
580 | \f | |
581 | ||
582 | /* This page contains code dealing LRA insn info (or in other words | |
583 | LRA internal insn representation). */ | |
584 | ||
c6a6cdaa | 585 | /* Map INSN_CODE -> the static insn data. This info is valid during |
586 | all translation unit. */ | |
587 | struct lra_static_insn_data *insn_code_data[LAST_INSN_CODE]; | |
588 | ||
589 | /* Debug insns are represented as a special insn with one input | |
590 | operand which is RTL expression in var_location. */ | |
591 | ||
592 | /* The following data are used as static insn operand data for all | |
593 | debug insns. If structure lra_operand_data is changed, the | |
594 | initializer should be changed too. */ | |
595 | static struct lra_operand_data debug_operand_data = | |
596 | { | |
597 | NULL, /* alternative */ | |
598 | VOIDmode, /* We are not interesting in the operand mode. */ | |
599 | OP_IN, | |
600 | 0, 0, 0, 0 | |
601 | }; | |
602 | ||
603 | /* The following data are used as static insn data for all debug | |
604 | insns. If structure lra_static_insn_data is changed, the | |
605 | initializer should be changed too. */ | |
606 | static struct lra_static_insn_data debug_insn_static_data = | |
607 | { | |
608 | &debug_operand_data, | |
609 | 0, /* Duplication operands #. */ | |
610 | -1, /* Commutative operand #. */ | |
611 | 1, /* Operands #. There is only one operand which is debug RTL | |
612 | expression. */ | |
613 | 0, /* Duplications #. */ | |
614 | 0, /* Alternatives #. We are not interesting in alternatives | |
615 | because we does not proceed debug_insns for reloads. */ | |
616 | NULL, /* Hard registers referenced in machine description. */ | |
617 | NULL /* Descriptions of operands in alternatives. */ | |
618 | }; | |
619 | ||
620 | /* Called once per compiler work to initialize some LRA data related | |
621 | to insns. */ | |
622 | static void | |
623 | init_insn_code_data_once (void) | |
624 | { | |
625 | memset (insn_code_data, 0, sizeof (insn_code_data)); | |
c6a6cdaa | 626 | } |
627 | ||
628 | /* Called once per compiler work to finalize some LRA data related to | |
629 | insns. */ | |
630 | static void | |
631 | finish_insn_code_data_once (void) | |
632 | { | |
633 | int i; | |
634 | ||
635 | for (i = 0; i < LAST_INSN_CODE; i++) | |
636 | { | |
637 | if (insn_code_data[i] != NULL) | |
638 | free (insn_code_data[i]); | |
c6a6cdaa | 639 | } |
640 | } | |
641 | ||
c6a6cdaa | 642 | /* Return static insn data, allocate and setup if necessary. Although |
643 | dup_num is static data (it depends only on icode), to set it up we | |
644 | need to extract insn first. So recog_data should be valid for | |
645 | normal insn (ICODE >= 0) before the call. */ | |
646 | static struct lra_static_insn_data * | |
647 | get_static_insn_data (int icode, int nop, int ndup, int nalt) | |
648 | { | |
649 | struct lra_static_insn_data *data; | |
650 | size_t n_bytes; | |
651 | ||
652 | lra_assert (icode < LAST_INSN_CODE); | |
653 | if (icode >= 0 && (data = insn_code_data[icode]) != NULL) | |
654 | return data; | |
655 | lra_assert (nop >= 0 && ndup >= 0 && nalt >= 0); | |
656 | n_bytes = sizeof (struct lra_static_insn_data) | |
657 | + sizeof (struct lra_operand_data) * nop | |
658 | + sizeof (int) * ndup; | |
659 | data = XNEWVAR (struct lra_static_insn_data, n_bytes); | |
92b4b904 | 660 | data->operand_alternative = NULL; |
c6a6cdaa | 661 | data->n_operands = nop; |
662 | data->n_dups = ndup; | |
663 | data->n_alternatives = nalt; | |
664 | data->operand = ((struct lra_operand_data *) | |
665 | ((char *) data + sizeof (struct lra_static_insn_data))); | |
666 | data->dup_num = ((int *) ((char *) data->operand | |
667 | + sizeof (struct lra_operand_data) * nop)); | |
668 | if (icode >= 0) | |
669 | { | |
670 | int i; | |
671 | ||
672 | insn_code_data[icode] = data; | |
673 | for (i = 0; i < nop; i++) | |
674 | { | |
675 | data->operand[i].constraint | |
676 | = insn_data[icode].operand[i].constraint; | |
677 | data->operand[i].mode = insn_data[icode].operand[i].mode; | |
678 | data->operand[i].strict_low = insn_data[icode].operand[i].strict_low; | |
679 | data->operand[i].is_operator | |
680 | = insn_data[icode].operand[i].is_operator; | |
681 | data->operand[i].type | |
682 | = (data->operand[i].constraint[0] == '=' ? OP_OUT | |
683 | : data->operand[i].constraint[0] == '+' ? OP_INOUT | |
684 | : OP_IN); | |
685 | data->operand[i].is_address = false; | |
686 | } | |
687 | for (i = 0; i < ndup; i++) | |
688 | data->dup_num[i] = recog_data.dup_num[i]; | |
689 | } | |
690 | return data; | |
691 | } | |
692 | ||
693 | /* The current length of the following array. */ | |
694 | int lra_insn_recog_data_len; | |
695 | ||
696 | /* Map INSN_UID -> the insn recog data (NULL if unknown). */ | |
697 | lra_insn_recog_data_t *lra_insn_recog_data; | |
698 | ||
699 | /* Initialize LRA data about insns. */ | |
700 | static void | |
701 | init_insn_recog_data (void) | |
702 | { | |
703 | lra_insn_recog_data_len = 0; | |
704 | lra_insn_recog_data = NULL; | |
c6a6cdaa | 705 | } |
706 | ||
707 | /* Expand, if necessary, LRA data about insns. */ | |
708 | static void | |
709 | check_and_expand_insn_recog_data (int index) | |
710 | { | |
711 | int i, old; | |
712 | ||
713 | if (lra_insn_recog_data_len > index) | |
714 | return; | |
715 | old = lra_insn_recog_data_len; | |
716 | lra_insn_recog_data_len = index * 3 / 2 + 1; | |
717 | lra_insn_recog_data = XRESIZEVEC (lra_insn_recog_data_t, | |
718 | lra_insn_recog_data, | |
719 | lra_insn_recog_data_len); | |
720 | for (i = old; i < lra_insn_recog_data_len; i++) | |
721 | lra_insn_recog_data[i] = NULL; | |
722 | } | |
723 | ||
724 | /* Finish LRA DATA about insn. */ | |
725 | static void | |
726 | free_insn_recog_data (lra_insn_recog_data_t data) | |
727 | { | |
728 | if (data->operand_loc != NULL) | |
729 | free (data->operand_loc); | |
730 | if (data->dup_loc != NULL) | |
731 | free (data->dup_loc); | |
732 | if (data->arg_hard_regs != NULL) | |
733 | free (data->arg_hard_regs); | |
c6a6cdaa | 734 | if (data->icode < 0 && NONDEBUG_INSN_P (data->insn)) |
735 | { | |
736 | if (data->insn_static_data->operand_alternative != NULL) | |
92b4b904 | 737 | free (const_cast <operand_alternative *> |
738 | (data->insn_static_data->operand_alternative)); | |
c6a6cdaa | 739 | free_insn_regs (data->insn_static_data->hard_regs); |
740 | free (data->insn_static_data); | |
741 | } | |
742 | free_insn_regs (data->regs); | |
743 | data->regs = NULL; | |
744 | free (data); | |
745 | } | |
746 | ||
747 | /* Finish LRA data about all insns. */ | |
748 | static void | |
749 | finish_insn_recog_data (void) | |
750 | { | |
751 | int i; | |
752 | lra_insn_recog_data_t data; | |
753 | ||
754 | for (i = 0; i < lra_insn_recog_data_len; i++) | |
755 | if ((data = lra_insn_recog_data[i]) != NULL) | |
756 | free_insn_recog_data (data); | |
757 | finish_insn_regs (); | |
16f90944 | 758 | lra_copy::pool.release (); |
759 | lra_insn_reg::pool.release (); | |
c6a6cdaa | 760 | free (lra_insn_recog_data); |
761 | } | |
762 | ||
763 | /* Setup info about operands in alternatives of LRA DATA of insn. */ | |
764 | static void | |
92b4b904 | 765 | setup_operand_alternative (lra_insn_recog_data_t data, |
766 | const operand_alternative *op_alt) | |
c6a6cdaa | 767 | { |
92b4b904 | 768 | int i, j, nop, nalt; |
c6a6cdaa | 769 | int icode = data->icode; |
770 | struct lra_static_insn_data *static_data = data->insn_static_data; | |
771 | ||
c6a6cdaa | 772 | static_data->commutative = -1; |
773 | nop = static_data->n_operands; | |
c6a6cdaa | 774 | nalt = static_data->n_alternatives; |
92b4b904 | 775 | static_data->operand_alternative = op_alt; |
c6a6cdaa | 776 | for (i = 0; i < nop; i++) |
777 | { | |
92b4b904 | 778 | static_data->operand[i].early_clobber = false; |
779 | static_data->operand[i].is_address = false; | |
780 | if (static_data->operand[i].constraint[0] == '%') | |
c6a6cdaa | 781 | { |
92b4b904 | 782 | /* We currently only support one commutative pair of operands. */ |
783 | if (static_data->commutative < 0) | |
784 | static_data->commutative = i; | |
785 | else | |
786 | lra_assert (icode < 0); /* Asm */ | |
787 | /* The last operand should not be marked commutative. */ | |
788 | lra_assert (i != nop - 1); | |
c6a6cdaa | 789 | } |
790 | } | |
92b4b904 | 791 | for (j = 0; j < nalt; j++) |
792 | for (i = 0; i < nop; i++, op_alt++) | |
793 | { | |
794 | static_data->operand[i].early_clobber |= op_alt->earlyclobber; | |
795 | static_data->operand[i].is_address |= op_alt->is_address; | |
796 | } | |
c6a6cdaa | 797 | } |
798 | ||
799 | /* Recursively process X and collect info about registers, which are | |
800 | not the insn operands, in X with TYPE (in/out/inout) and flag that | |
801 | it is early clobbered in the insn (EARLY_CLOBBER) and add the info | |
802 | to LIST. X is a part of insn given by DATA. Return the result | |
803 | list. */ | |
804 | static struct lra_insn_reg * | |
805 | collect_non_operand_hard_regs (rtx *x, lra_insn_recog_data_t data, | |
806 | struct lra_insn_reg *list, | |
807 | enum op_type type, bool early_clobber) | |
808 | { | |
809 | int i, j, regno, last; | |
810 | bool subreg_p; | |
3754d046 | 811 | machine_mode mode; |
c6a6cdaa | 812 | struct lra_insn_reg *curr; |
813 | rtx op = *x; | |
814 | enum rtx_code code = GET_CODE (op); | |
815 | const char *fmt = GET_RTX_FORMAT (code); | |
816 | ||
817 | for (i = 0; i < data->insn_static_data->n_operands; i++) | |
818 | if (x == data->operand_loc[i]) | |
819 | /* It is an operand loc. Stop here. */ | |
820 | return list; | |
821 | for (i = 0; i < data->insn_static_data->n_dups; i++) | |
822 | if (x == data->dup_loc[i]) | |
823 | /* It is a dup loc. Stop here. */ | |
824 | return list; | |
825 | mode = GET_MODE (op); | |
826 | subreg_p = false; | |
827 | if (code == SUBREG) | |
828 | { | |
829 | op = SUBREG_REG (op); | |
830 | code = GET_CODE (op); | |
831 | if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (op))) | |
832 | { | |
833 | mode = GET_MODE (op); | |
834 | if (GET_MODE_SIZE (mode) > REGMODE_NATURAL_SIZE (mode)) | |
835 | subreg_p = true; | |
836 | } | |
837 | } | |
838 | if (REG_P (op)) | |
839 | { | |
840 | if ((regno = REGNO (op)) >= FIRST_PSEUDO_REGISTER) | |
841 | return list; | |
497ba60f | 842 | /* Process all regs even unallocatable ones as we need info |
843 | about all regs for rematerialization pass. */ | |
c6a6cdaa | 844 | for (last = regno + hard_regno_nregs[regno][mode]; |
845 | regno < last; | |
846 | regno++) | |
497ba60f | 847 | { |
848 | for (curr = list; curr != NULL; curr = curr->next) | |
849 | if (curr->regno == regno && curr->subreg_p == subreg_p | |
850 | && curr->biggest_mode == mode) | |
c6a6cdaa | 851 | { |
497ba60f | 852 | if (curr->type != type) |
853 | curr->type = OP_INOUT; | |
854 | if (curr->early_clobber != early_clobber) | |
855 | curr->early_clobber = true; | |
856 | break; | |
857 | } | |
858 | if (curr == NULL) | |
859 | { | |
860 | /* This is a new hard regno or the info can not be | |
861 | integrated into the found structure. */ | |
c6a6cdaa | 862 | #ifdef STACK_REGS |
497ba60f | 863 | early_clobber |
864 | = (early_clobber | |
865 | /* This clobber is to inform popping floating | |
866 | point stack only. */ | |
867 | && ! (FIRST_STACK_REG <= regno | |
868 | && regno <= LAST_STACK_REG)); | |
c6a6cdaa | 869 | #endif |
497ba60f | 870 | list = new_insn_reg (data->insn, regno, type, mode, subreg_p, |
871 | early_clobber, list); | |
872 | } | |
873 | } | |
c6a6cdaa | 874 | return list; |
875 | } | |
876 | switch (code) | |
877 | { | |
878 | case SET: | |
879 | list = collect_non_operand_hard_regs (&SET_DEST (op), data, | |
880 | list, OP_OUT, false); | |
881 | list = collect_non_operand_hard_regs (&SET_SRC (op), data, | |
882 | list, OP_IN, false); | |
883 | break; | |
884 | case CLOBBER: | |
885 | /* We treat clobber of non-operand hard registers as early | |
1a8f8886 | 886 | clobber (the behavior is expected from asm). */ |
c6a6cdaa | 887 | list = collect_non_operand_hard_regs (&XEXP (op, 0), data, |
888 | list, OP_OUT, true); | |
889 | break; | |
890 | case PRE_INC: case PRE_DEC: case POST_INC: case POST_DEC: | |
891 | list = collect_non_operand_hard_regs (&XEXP (op, 0), data, | |
892 | list, OP_INOUT, false); | |
893 | break; | |
894 | case PRE_MODIFY: case POST_MODIFY: | |
895 | list = collect_non_operand_hard_regs (&XEXP (op, 0), data, | |
896 | list, OP_INOUT, false); | |
897 | list = collect_non_operand_hard_regs (&XEXP (op, 1), data, | |
898 | list, OP_IN, false); | |
899 | break; | |
900 | default: | |
901 | fmt = GET_RTX_FORMAT (code); | |
902 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
903 | { | |
904 | if (fmt[i] == 'e') | |
905 | list = collect_non_operand_hard_regs (&XEXP (op, i), data, | |
906 | list, OP_IN, false); | |
907 | else if (fmt[i] == 'E') | |
908 | for (j = XVECLEN (op, i) - 1; j >= 0; j--) | |
909 | list = collect_non_operand_hard_regs (&XVECEXP (op, i, j), data, | |
910 | list, OP_IN, false); | |
911 | } | |
912 | } | |
913 | return list; | |
914 | } | |
915 | ||
916 | /* Set up and return info about INSN. Set up the info if it is not set up | |
917 | yet. */ | |
918 | lra_insn_recog_data_t | |
7f836b57 | 919 | lra_set_insn_recog_data (rtx_insn *insn) |
c6a6cdaa | 920 | { |
921 | lra_insn_recog_data_t data; | |
922 | int i, n, icode; | |
923 | rtx **locs; | |
924 | unsigned int uid = INSN_UID (insn); | |
925 | struct lra_static_insn_data *insn_static_data; | |
926 | ||
927 | check_and_expand_insn_recog_data (uid); | |
928 | if (DEBUG_INSN_P (insn)) | |
929 | icode = -1; | |
930 | else | |
931 | { | |
932 | icode = INSN_CODE (insn); | |
933 | if (icode < 0) | |
934 | /* It might be a new simple insn which is not recognized yet. */ | |
935 | INSN_CODE (insn) = icode = recog_memoized (insn); | |
936 | } | |
937 | data = XNEW (struct lra_insn_recog_data); | |
938 | lra_insn_recog_data[uid] = data; | |
939 | data->insn = insn; | |
940 | data->used_insn_alternative = -1; | |
941 | data->icode = icode; | |
942 | data->regs = NULL; | |
943 | if (DEBUG_INSN_P (insn)) | |
944 | { | |
945 | data->insn_static_data = &debug_insn_static_data; | |
946 | data->dup_loc = NULL; | |
947 | data->arg_hard_regs = NULL; | |
e1a797ad | 948 | data->preferred_alternatives = ALL_ALTERNATIVES; |
c6a6cdaa | 949 | data->operand_loc = XNEWVEC (rtx *, 1); |
950 | data->operand_loc[0] = &INSN_VAR_LOCATION_LOC (insn); | |
951 | return data; | |
952 | } | |
953 | if (icode < 0) | |
954 | { | |
92b4b904 | 955 | int nop, nalt; |
3754d046 | 956 | machine_mode operand_mode[MAX_RECOG_OPERANDS]; |
c6a6cdaa | 957 | const char *constraints[MAX_RECOG_OPERANDS]; |
958 | ||
959 | nop = asm_noperands (PATTERN (insn)); | |
960 | data->operand_loc = data->dup_loc = NULL; | |
92b4b904 | 961 | nalt = 1; |
c6a6cdaa | 962 | if (nop < 0) |
73a18f44 | 963 | { |
150967ab | 964 | /* It is a special insn like USE or CLOBBER. We should |
73a18f44 | 965 | recognize any regular insn otherwise LRA can do nothing |
966 | with this insn. */ | |
967 | gcc_assert (GET_CODE (PATTERN (insn)) == USE | |
968 | || GET_CODE (PATTERN (insn)) == CLOBBER | |
969 | || GET_CODE (PATTERN (insn)) == ASM_INPUT); | |
970 | data->insn_static_data = insn_static_data | |
92b4b904 | 971 | = get_static_insn_data (-1, 0, 0, nalt); |
73a18f44 | 972 | } |
c6a6cdaa | 973 | else |
974 | { | |
975 | /* expand_asm_operands makes sure there aren't too many | |
976 | operands. */ | |
977 | lra_assert (nop <= MAX_RECOG_OPERANDS); | |
978 | if (nop != 0) | |
979 | data->operand_loc = XNEWVEC (rtx *, nop); | |
980 | /* Now get the operand values and constraints out of the | |
981 | insn. */ | |
982 | decode_asm_operands (PATTERN (insn), NULL, | |
983 | data->operand_loc, | |
984 | constraints, operand_mode, NULL); | |
c6a6cdaa | 985 | if (nop > 0) |
986 | { | |
987 | const char *p = recog_data.constraints[0]; | |
1a8f8886 | 988 | |
c6a6cdaa | 989 | for (p = constraints[0]; *p; p++) |
92b4b904 | 990 | nalt += *p == ','; |
c6a6cdaa | 991 | } |
992 | data->insn_static_data = insn_static_data | |
92b4b904 | 993 | = get_static_insn_data (-1, nop, 0, nalt); |
c6a6cdaa | 994 | for (i = 0; i < nop; i++) |
995 | { | |
996 | insn_static_data->operand[i].mode = operand_mode[i]; | |
997 | insn_static_data->operand[i].constraint = constraints[i]; | |
998 | insn_static_data->operand[i].strict_low = false; | |
999 | insn_static_data->operand[i].is_operator = false; | |
1000 | insn_static_data->operand[i].is_address = false; | |
1001 | } | |
1002 | } | |
1003 | for (i = 0; i < insn_static_data->n_operands; i++) | |
1004 | insn_static_data->operand[i].type | |
1005 | = (insn_static_data->operand[i].constraint[0] == '=' ? OP_OUT | |
1006 | : insn_static_data->operand[i].constraint[0] == '+' ? OP_INOUT | |
1007 | : OP_IN); | |
e1a797ad | 1008 | data->preferred_alternatives = ALL_ALTERNATIVES; |
92b4b904 | 1009 | if (nop > 0) |
1010 | { | |
1011 | operand_alternative *op_alt = XCNEWVEC (operand_alternative, | |
1012 | nalt * nop); | |
1013 | preprocess_constraints (nop, nalt, constraints, op_alt); | |
1014 | setup_operand_alternative (data, op_alt); | |
1015 | } | |
c6a6cdaa | 1016 | } |
1017 | else | |
1018 | { | |
1019 | insn_extract (insn); | |
1020 | data->insn_static_data = insn_static_data | |
1021 | = get_static_insn_data (icode, insn_data[icode].n_operands, | |
1022 | insn_data[icode].n_dups, | |
1023 | insn_data[icode].n_alternatives); | |
1024 | n = insn_static_data->n_operands; | |
1025 | if (n == 0) | |
1026 | locs = NULL; | |
1027 | else | |
1028 | { | |
1029 | locs = XNEWVEC (rtx *, n); | |
1030 | memcpy (locs, recog_data.operand_loc, n * sizeof (rtx *)); | |
1031 | } | |
1032 | data->operand_loc = locs; | |
1033 | n = insn_static_data->n_dups; | |
1034 | if (n == 0) | |
1035 | locs = NULL; | |
1036 | else | |
1037 | { | |
1038 | locs = XNEWVEC (rtx *, n); | |
1039 | memcpy (locs, recog_data.dup_loc, n * sizeof (rtx *)); | |
1040 | } | |
1041 | data->dup_loc = locs; | |
e1a797ad | 1042 | data->preferred_alternatives = get_preferred_alternatives (insn); |
92b4b904 | 1043 | const operand_alternative *op_alt = preprocess_insn_constraints (icode); |
1044 | if (!insn_static_data->operand_alternative) | |
1045 | setup_operand_alternative (data, op_alt); | |
1046 | else if (op_alt != insn_static_data->operand_alternative) | |
1047 | insn_static_data->operand_alternative = op_alt; | |
c6a6cdaa | 1048 | } |
1049 | if (GET_CODE (PATTERN (insn)) == CLOBBER || GET_CODE (PATTERN (insn)) == USE) | |
1050 | insn_static_data->hard_regs = NULL; | |
1051 | else | |
1052 | insn_static_data->hard_regs | |
1053 | = collect_non_operand_hard_regs (&PATTERN (insn), data, | |
1054 | NULL, OP_IN, false); | |
c6a6cdaa | 1055 | data->arg_hard_regs = NULL; |
1056 | if (CALL_P (insn)) | |
1057 | { | |
1058 | rtx link; | |
1059 | int n_hard_regs, regno, arg_hard_regs[FIRST_PSEUDO_REGISTER]; | |
1060 | ||
1061 | n_hard_regs = 0; | |
1062 | /* Finding implicit hard register usage. We believe it will be | |
1063 | not changed whatever transformations are used. Call insns | |
1064 | are such example. */ | |
1065 | for (link = CALL_INSN_FUNCTION_USAGE (insn); | |
1066 | link != NULL_RTX; | |
1067 | link = XEXP (link, 1)) | |
1068 | if (GET_CODE (XEXP (link, 0)) == USE | |
1069 | && REG_P (XEXP (XEXP (link, 0), 0))) | |
1070 | { | |
1071 | regno = REGNO (XEXP (XEXP (link, 0), 0)); | |
1072 | lra_assert (regno < FIRST_PSEUDO_REGISTER); | |
1073 | /* It is an argument register. */ | |
0933f1d9 | 1074 | for (i = REG_NREGS (XEXP (XEXP (link, 0), 0)) - 1; i >= 0; i--) |
c6a6cdaa | 1075 | arg_hard_regs[n_hard_regs++] = regno + i; |
1076 | } | |
1077 | if (n_hard_regs != 0) | |
1078 | { | |
1079 | arg_hard_regs[n_hard_regs++] = -1; | |
1080 | data->arg_hard_regs = XNEWVEC (int, n_hard_regs); | |
1081 | memcpy (data->arg_hard_regs, arg_hard_regs, | |
1082 | sizeof (int) * n_hard_regs); | |
1083 | } | |
1084 | } | |
1085 | /* Some output operand can be recognized only from the context not | |
1086 | from the constraints which are empty in this case. Call insn may | |
1087 | contain a hard register in set destination with empty constraint | |
1088 | and extract_insn treats them as an input. */ | |
1089 | for (i = 0; i < insn_static_data->n_operands; i++) | |
1090 | { | |
1091 | int j; | |
1092 | rtx pat, set; | |
1093 | struct lra_operand_data *operand = &insn_static_data->operand[i]; | |
1094 | ||
1095 | /* ??? Should we treat 'X' the same way. It looks to me that | |
1096 | 'X' means anything and empty constraint means we do not | |
1097 | care. */ | |
1098 | if (operand->type != OP_IN || *operand->constraint != '\0' | |
1099 | || operand->is_operator) | |
1100 | continue; | |
1101 | pat = PATTERN (insn); | |
1102 | if (GET_CODE (pat) == SET) | |
1103 | { | |
1104 | if (data->operand_loc[i] != &SET_DEST (pat)) | |
1105 | continue; | |
1106 | } | |
1107 | else if (GET_CODE (pat) == PARALLEL) | |
1108 | { | |
1109 | for (j = XVECLEN (pat, 0) - 1; j >= 0; j--) | |
1110 | { | |
1111 | set = XVECEXP (PATTERN (insn), 0, j); | |
1112 | if (GET_CODE (set) == SET | |
1113 | && &SET_DEST (set) == data->operand_loc[i]) | |
1114 | break; | |
1115 | } | |
1116 | if (j < 0) | |
1117 | continue; | |
1118 | } | |
1119 | else | |
1120 | continue; | |
1121 | operand->type = OP_OUT; | |
1122 | } | |
1123 | return data; | |
1124 | } | |
1125 | ||
1126 | /* Return info about insn give by UID. The info should be already set | |
1127 | up. */ | |
1128 | static lra_insn_recog_data_t | |
1129 | get_insn_recog_data_by_uid (int uid) | |
1130 | { | |
1131 | lra_insn_recog_data_t data; | |
1132 | ||
1133 | data = lra_insn_recog_data[uid]; | |
1134 | lra_assert (data != NULL); | |
1135 | return data; | |
1136 | } | |
1137 | ||
1138 | /* Invalidate all info about insn given by its UID. */ | |
1139 | static void | |
1140 | invalidate_insn_recog_data (int uid) | |
1141 | { | |
1142 | lra_insn_recog_data_t data; | |
1143 | ||
1144 | data = lra_insn_recog_data[uid]; | |
1145 | lra_assert (data != NULL); | |
1146 | free_insn_recog_data (data); | |
1147 | lra_insn_recog_data[uid] = NULL; | |
1148 | } | |
1149 | ||
1150 | /* Update all the insn info about INSN. It is usually called when | |
1151 | something in the insn was changed. Return the updated info. */ | |
1152 | lra_insn_recog_data_t | |
7f836b57 | 1153 | lra_update_insn_recog_data (rtx_insn *insn) |
c6a6cdaa | 1154 | { |
1155 | lra_insn_recog_data_t data; | |
1156 | int n; | |
1157 | unsigned int uid = INSN_UID (insn); | |
1158 | struct lra_static_insn_data *insn_static_data; | |
3b3a5e5f | 1159 | HOST_WIDE_INT sp_offset = 0; |
1a8f8886 | 1160 | |
c6a6cdaa | 1161 | check_and_expand_insn_recog_data (uid); |
1162 | if ((data = lra_insn_recog_data[uid]) != NULL | |
1163 | && data->icode != INSN_CODE (insn)) | |
1164 | { | |
3b3a5e5f | 1165 | sp_offset = data->sp_offset; |
c6a6cdaa | 1166 | invalidate_insn_data_regno_info (data, insn, get_insn_freq (insn)); |
1167 | invalidate_insn_recog_data (uid); | |
1168 | data = NULL; | |
1169 | } | |
1170 | if (data == NULL) | |
3b3a5e5f | 1171 | { |
1172 | data = lra_get_insn_recog_data (insn); | |
1173 | /* Initiate or restore SP offset. */ | |
1174 | data->sp_offset = sp_offset; | |
1175 | return data; | |
1176 | } | |
c6a6cdaa | 1177 | insn_static_data = data->insn_static_data; |
1178 | data->used_insn_alternative = -1; | |
1179 | if (DEBUG_INSN_P (insn)) | |
1180 | return data; | |
1181 | if (data->icode < 0) | |
1182 | { | |
1183 | int nop; | |
3754d046 | 1184 | machine_mode operand_mode[MAX_RECOG_OPERANDS]; |
c6a6cdaa | 1185 | const char *constraints[MAX_RECOG_OPERANDS]; |
1186 | ||
1187 | nop = asm_noperands (PATTERN (insn)); | |
1188 | if (nop >= 0) | |
1189 | { | |
1190 | lra_assert (nop == data->insn_static_data->n_operands); | |
1191 | /* Now get the operand values and constraints out of the | |
1192 | insn. */ | |
1193 | decode_asm_operands (PATTERN (insn), NULL, | |
1194 | data->operand_loc, | |
1195 | constraints, operand_mode, NULL); | |
1196 | #ifdef ENABLE_CHECKING | |
1197 | { | |
1198 | int i; | |
1199 | ||
1200 | for (i = 0; i < nop; i++) | |
1201 | lra_assert | |
1202 | (insn_static_data->operand[i].mode == operand_mode[i] | |
1203 | && insn_static_data->operand[i].constraint == constraints[i] | |
1204 | && ! insn_static_data->operand[i].is_operator); | |
1205 | } | |
1206 | #endif | |
1207 | } | |
1208 | #ifdef ENABLE_CHECKING | |
1209 | { | |
1210 | int i; | |
1211 | ||
1212 | for (i = 0; i < insn_static_data->n_operands; i++) | |
1213 | lra_assert | |
1214 | (insn_static_data->operand[i].type | |
1215 | == (insn_static_data->operand[i].constraint[0] == '=' ? OP_OUT | |
1216 | : insn_static_data->operand[i].constraint[0] == '+' ? OP_INOUT | |
1217 | : OP_IN)); | |
1218 | } | |
1219 | #endif | |
1220 | } | |
1221 | else | |
1222 | { | |
1223 | insn_extract (insn); | |
1224 | n = insn_static_data->n_operands; | |
1225 | if (n != 0) | |
1226 | memcpy (data->operand_loc, recog_data.operand_loc, n * sizeof (rtx *)); | |
1227 | n = insn_static_data->n_dups; | |
1228 | if (n != 0) | |
1229 | memcpy (data->dup_loc, recog_data.dup_loc, n * sizeof (rtx *)); | |
e1a797ad | 1230 | lra_assert (check_bool_attrs (insn)); |
c6a6cdaa | 1231 | } |
1232 | return data; | |
1233 | } | |
1234 | ||
1235 | /* Set up that INSN is using alternative ALT now. */ | |
1236 | void | |
7f836b57 | 1237 | lra_set_used_insn_alternative (rtx_insn *insn, int alt) |
c6a6cdaa | 1238 | { |
1239 | lra_insn_recog_data_t data; | |
1240 | ||
1241 | data = lra_get_insn_recog_data (insn); | |
1242 | data->used_insn_alternative = alt; | |
1243 | } | |
1244 | ||
1245 | /* Set up that insn with UID is using alternative ALT now. The insn | |
1246 | info should be already set up. */ | |
1247 | void | |
1248 | lra_set_used_insn_alternative_by_uid (int uid, int alt) | |
1249 | { | |
1250 | lra_insn_recog_data_t data; | |
1251 | ||
1252 | check_and_expand_insn_recog_data (uid); | |
1253 | data = lra_insn_recog_data[uid]; | |
1254 | lra_assert (data != NULL); | |
1255 | data->used_insn_alternative = alt; | |
1256 | } | |
1257 | ||
1258 | \f | |
1259 | ||
1260 | /* This page contains code dealing with common register info and | |
1261 | pseudo copies. */ | |
1262 | ||
1263 | /* The size of the following array. */ | |
1264 | static int reg_info_size; | |
1265 | /* Common info about each register. */ | |
1266 | struct lra_reg *lra_reg_info; | |
1267 | ||
1268 | /* Last register value. */ | |
1269 | static int last_reg_value; | |
1270 | ||
1271 | /* Return new register value. */ | |
1272 | static int | |
1273 | get_new_reg_value (void) | |
1274 | { | |
1275 | return ++last_reg_value; | |
1276 | } | |
1277 | ||
1278 | /* Pools for copies. */ | |
16f90944 | 1279 | pool_allocator<lra_copy> lra_copy::pool ("lra copies", 100); |
c6a6cdaa | 1280 | |
c6a6cdaa | 1281 | /* Vec referring to pseudo copies. */ |
f1f41a6c | 1282 | static vec<lra_copy_t> copy_vec; |
c6a6cdaa | 1283 | |
1284 | /* Initialize I-th element of lra_reg_info. */ | |
1285 | static inline void | |
1286 | initialize_lra_reg_info_element (int i) | |
1287 | { | |
1288 | bitmap_initialize (&lra_reg_info[i].insn_bitmap, ®_obstack); | |
1289 | #ifdef STACK_REGS | |
1290 | lra_reg_info[i].no_stack_p = false; | |
1291 | #endif | |
1292 | CLEAR_HARD_REG_SET (lra_reg_info[i].conflict_hard_regs); | |
f2cc6708 | 1293 | CLEAR_HARD_REG_SET (lra_reg_info[i].actual_call_used_reg_set); |
c6a6cdaa | 1294 | lra_reg_info[i].preferred_hard_regno1 = -1; |
1295 | lra_reg_info[i].preferred_hard_regno2 = -1; | |
1296 | lra_reg_info[i].preferred_hard_regno_profit1 = 0; | |
1297 | lra_reg_info[i].preferred_hard_regno_profit2 = 0; | |
fc8a0f60 | 1298 | lra_reg_info[i].biggest_mode = VOIDmode; |
c6a6cdaa | 1299 | lra_reg_info[i].live_ranges = NULL; |
1300 | lra_reg_info[i].nrefs = lra_reg_info[i].freq = 0; | |
1301 | lra_reg_info[i].last_reload = 0; | |
1302 | lra_reg_info[i].restore_regno = -1; | |
1303 | lra_reg_info[i].val = get_new_reg_value (); | |
a1064490 | 1304 | lra_reg_info[i].offset = 0; |
c6a6cdaa | 1305 | lra_reg_info[i].copies = NULL; |
1306 | } | |
1307 | ||
1308 | /* Initialize common reg info and copies. */ | |
1309 | static void | |
1310 | init_reg_info (void) | |
1311 | { | |
1312 | int i; | |
1313 | ||
1314 | last_reg_value = 0; | |
1315 | reg_info_size = max_reg_num () * 3 / 2 + 1; | |
1316 | lra_reg_info = XNEWVEC (struct lra_reg, reg_info_size); | |
1317 | for (i = 0; i < reg_info_size; i++) | |
1318 | initialize_lra_reg_info_element (i); | |
f1f41a6c | 1319 | copy_vec.create (100); |
c6a6cdaa | 1320 | } |
1321 | ||
1322 | ||
1323 | /* Finish common reg info and copies. */ | |
1324 | static void | |
1325 | finish_reg_info (void) | |
1326 | { | |
1327 | int i; | |
1328 | ||
1329 | for (i = 0; i < reg_info_size; i++) | |
1330 | bitmap_clear (&lra_reg_info[i].insn_bitmap); | |
1331 | free (lra_reg_info); | |
1332 | reg_info_size = 0; | |
c6a6cdaa | 1333 | } |
1334 | ||
1335 | /* Expand common reg info if it is necessary. */ | |
1336 | static void | |
1337 | expand_reg_info (void) | |
1338 | { | |
1339 | int i, old = reg_info_size; | |
1340 | ||
1341 | if (reg_info_size > max_reg_num ()) | |
1342 | return; | |
1343 | reg_info_size = max_reg_num () * 3 / 2 + 1; | |
1344 | lra_reg_info = XRESIZEVEC (struct lra_reg, lra_reg_info, reg_info_size); | |
1345 | for (i = old; i < reg_info_size; i++) | |
1346 | initialize_lra_reg_info_element (i); | |
1347 | } | |
1348 | ||
1349 | /* Free all copies. */ | |
1350 | void | |
1351 | lra_free_copies (void) | |
1352 | { | |
1353 | lra_copy_t cp; | |
1354 | ||
f1f41a6c | 1355 | while (copy_vec.length () != 0) |
c6a6cdaa | 1356 | { |
f1f41a6c | 1357 | cp = copy_vec.pop (); |
c6a6cdaa | 1358 | lra_reg_info[cp->regno1].copies = lra_reg_info[cp->regno2].copies = NULL; |
16f90944 | 1359 | delete cp; |
c6a6cdaa | 1360 | } |
1361 | } | |
1362 | ||
1363 | /* Create copy of two pseudos REGNO1 and REGNO2. The copy execution | |
1364 | frequency is FREQ. */ | |
1365 | void | |
1366 | lra_create_copy (int regno1, int regno2, int freq) | |
1367 | { | |
1368 | bool regno1_dest_p; | |
1369 | lra_copy_t cp; | |
1370 | ||
1371 | lra_assert (regno1 != regno2); | |
1372 | regno1_dest_p = true; | |
1373 | if (regno1 > regno2) | |
1374 | { | |
a4f59596 | 1375 | std::swap (regno1, regno2); |
c6a6cdaa | 1376 | regno1_dest_p = false; |
c6a6cdaa | 1377 | } |
16f90944 | 1378 | cp = new lra_copy (); |
f1f41a6c | 1379 | copy_vec.safe_push (cp); |
c6a6cdaa | 1380 | cp->regno1_dest_p = regno1_dest_p; |
1381 | cp->freq = freq; | |
1382 | cp->regno1 = regno1; | |
1383 | cp->regno2 = regno2; | |
1384 | cp->regno1_next = lra_reg_info[regno1].copies; | |
1385 | lra_reg_info[regno1].copies = cp; | |
1386 | cp->regno2_next = lra_reg_info[regno2].copies; | |
1387 | lra_reg_info[regno2].copies = cp; | |
1388 | if (lra_dump_file != NULL) | |
1389 | fprintf (lra_dump_file, " Creating copy r%d%sr%d@%d\n", | |
1390 | regno1, regno1_dest_p ? "<-" : "->", regno2, freq); | |
1391 | } | |
1392 | ||
1393 | /* Return N-th (0, 1, ...) copy. If there is no copy, return | |
1394 | NULL. */ | |
1395 | lra_copy_t | |
1396 | lra_get_copy (int n) | |
1397 | { | |
f1f41a6c | 1398 | if (n >= (int) copy_vec.length ()) |
c6a6cdaa | 1399 | return NULL; |
f1f41a6c | 1400 | return copy_vec[n]; |
c6a6cdaa | 1401 | } |
1402 | ||
1403 | \f | |
1404 | ||
1405 | /* This page contains code dealing with info about registers in | |
1406 | insns. */ | |
1407 | ||
1408 | /* Process X of insn UID recursively and add info (operand type is | |
1409 | given by TYPE, flag of that it is early clobber is EARLY_CLOBBER) | |
1410 | about registers in X to the insn DATA. */ | |
1411 | static void | |
1412 | add_regs_to_insn_regno_info (lra_insn_recog_data_t data, rtx x, int uid, | |
1413 | enum op_type type, bool early_clobber) | |
1414 | { | |
1415 | int i, j, regno; | |
1416 | bool subreg_p; | |
3754d046 | 1417 | machine_mode mode; |
c6a6cdaa | 1418 | const char *fmt; |
1419 | enum rtx_code code; | |
1420 | struct lra_insn_reg *curr; | |
1421 | ||
1422 | code = GET_CODE (x); | |
1423 | mode = GET_MODE (x); | |
1424 | subreg_p = false; | |
1425 | if (GET_CODE (x) == SUBREG) | |
1426 | { | |
1427 | x = SUBREG_REG (x); | |
1428 | code = GET_CODE (x); | |
1429 | if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))) | |
1430 | { | |
1431 | mode = GET_MODE (x); | |
1432 | if (GET_MODE_SIZE (mode) > REGMODE_NATURAL_SIZE (mode)) | |
1433 | subreg_p = true; | |
1434 | } | |
1435 | } | |
1436 | if (REG_P (x)) | |
1437 | { | |
1438 | regno = REGNO (x); | |
497ba60f | 1439 | /* Process all regs even unallocatable ones as we need info about |
1440 | all regs for rematerialization pass. */ | |
c6a6cdaa | 1441 | expand_reg_info (); |
1442 | if (bitmap_set_bit (&lra_reg_info[regno].insn_bitmap, uid)) | |
1443 | { | |
40cec44a | 1444 | data->regs = new_insn_reg (data->insn, regno, type, mode, subreg_p, |
c6a6cdaa | 1445 | early_clobber, data->regs); |
1446 | return; | |
1447 | } | |
1448 | else | |
1449 | { | |
1450 | for (curr = data->regs; curr != NULL; curr = curr->next) | |
1451 | if (curr->regno == regno) | |
1452 | { | |
1453 | if (curr->subreg_p != subreg_p || curr->biggest_mode != mode) | |
1454 | /* The info can not be integrated into the found | |
1455 | structure. */ | |
40cec44a | 1456 | data->regs = new_insn_reg (data->insn, regno, type, mode, |
1457 | subreg_p, early_clobber, | |
1458 | data->regs); | |
c6a6cdaa | 1459 | else |
1460 | { | |
1461 | if (curr->type != type) | |
1462 | curr->type = OP_INOUT; | |
1463 | if (curr->early_clobber != early_clobber) | |
1464 | curr->early_clobber = true; | |
1465 | } | |
1466 | return; | |
1467 | } | |
1468 | gcc_unreachable (); | |
1469 | } | |
1470 | } | |
1471 | ||
1472 | switch (code) | |
1473 | { | |
1474 | case SET: | |
1475 | add_regs_to_insn_regno_info (data, SET_DEST (x), uid, OP_OUT, false); | |
1476 | add_regs_to_insn_regno_info (data, SET_SRC (x), uid, OP_IN, false); | |
1477 | break; | |
1478 | case CLOBBER: | |
1479 | /* We treat clobber of non-operand hard registers as early | |
1a8f8886 | 1480 | clobber (the behavior is expected from asm). */ |
c6a6cdaa | 1481 | add_regs_to_insn_regno_info (data, XEXP (x, 0), uid, OP_OUT, true); |
1482 | break; | |
1483 | case PRE_INC: case PRE_DEC: case POST_INC: case POST_DEC: | |
1484 | add_regs_to_insn_regno_info (data, XEXP (x, 0), uid, OP_INOUT, false); | |
1485 | break; | |
1486 | case PRE_MODIFY: case POST_MODIFY: | |
1487 | add_regs_to_insn_regno_info (data, XEXP (x, 0), uid, OP_INOUT, false); | |
1488 | add_regs_to_insn_regno_info (data, XEXP (x, 1), uid, OP_IN, false); | |
1489 | break; | |
1490 | default: | |
1491 | if ((code != PARALLEL && code != EXPR_LIST) || type != OP_OUT) | |
1492 | /* Some targets place small structures in registers for return | |
1493 | values of functions, and those registers are wrapped in | |
1494 | PARALLEL that we may see as the destination of a SET. Here | |
1495 | is an example: | |
1496 | ||
1497 | (call_insn 13 12 14 2 (set (parallel:BLK [ | |
1498 | (expr_list:REG_DEP_TRUE (reg:DI 0 ax) | |
1499 | (const_int 0 [0])) | |
1500 | (expr_list:REG_DEP_TRUE (reg:DI 1 dx) | |
1501 | (const_int 8 [0x8])) | |
1502 | ]) | |
1503 | (call (mem:QI (symbol_ref:DI (... */ | |
1504 | type = OP_IN; | |
1505 | fmt = GET_RTX_FORMAT (code); | |
1506 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1507 | { | |
1508 | if (fmt[i] == 'e') | |
1509 | add_regs_to_insn_regno_info (data, XEXP (x, i), uid, type, false); | |
1510 | else if (fmt[i] == 'E') | |
1511 | { | |
1512 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
1513 | add_regs_to_insn_regno_info (data, XVECEXP (x, i, j), uid, | |
1514 | type, false); | |
1515 | } | |
1516 | } | |
1517 | } | |
1518 | } | |
1519 | ||
1520 | /* Return execution frequency of INSN. */ | |
1521 | static int | |
7f836b57 | 1522 | get_insn_freq (rtx_insn *insn) |
c6a6cdaa | 1523 | { |
91f71fa3 | 1524 | basic_block bb = BLOCK_FOR_INSN (insn); |
c6a6cdaa | 1525 | |
91f71fa3 | 1526 | gcc_checking_assert (bb != NULL); |
1527 | return REG_FREQ_FROM_BB (bb); | |
c6a6cdaa | 1528 | } |
1529 | ||
1530 | /* Invalidate all reg info of INSN with DATA and execution frequency | |
1531 | FREQ. Update common info about the invalidated registers. */ | |
1532 | static void | |
7f836b57 | 1533 | invalidate_insn_data_regno_info (lra_insn_recog_data_t data, rtx_insn *insn, |
c6a6cdaa | 1534 | int freq) |
1535 | { | |
1536 | int uid; | |
1537 | bool debug_p; | |
1538 | unsigned int i; | |
1539 | struct lra_insn_reg *ir, *next_ir; | |
1540 | ||
1541 | uid = INSN_UID (insn); | |
1542 | debug_p = DEBUG_INSN_P (insn); | |
1543 | for (ir = data->regs; ir != NULL; ir = next_ir) | |
1544 | { | |
1545 | i = ir->regno; | |
1546 | next_ir = ir->next; | |
16f90944 | 1547 | delete ir; |
c6a6cdaa | 1548 | bitmap_clear_bit (&lra_reg_info[i].insn_bitmap, uid); |
1549 | if (i >= FIRST_PSEUDO_REGISTER && ! debug_p) | |
1550 | { | |
1551 | lra_reg_info[i].nrefs--; | |
1552 | lra_reg_info[i].freq -= freq; | |
1553 | lra_assert (lra_reg_info[i].nrefs >= 0 && lra_reg_info[i].freq >= 0); | |
1554 | } | |
1555 | } | |
1556 | data->regs = NULL; | |
1557 | } | |
1558 | ||
1559 | /* Invalidate all reg info of INSN. Update common info about the | |
1560 | invalidated registers. */ | |
1561 | void | |
7f836b57 | 1562 | lra_invalidate_insn_regno_info (rtx_insn *insn) |
c6a6cdaa | 1563 | { |
1564 | invalidate_insn_data_regno_info (lra_get_insn_recog_data (insn), insn, | |
1565 | get_insn_freq (insn)); | |
1566 | } | |
1567 | ||
1568 | /* Update common reg info from reg info of insn given by its DATA and | |
1569 | execution frequency FREQ. */ | |
1570 | static void | |
1571 | setup_insn_reg_info (lra_insn_recog_data_t data, int freq) | |
1572 | { | |
1573 | unsigned int i; | |
1574 | struct lra_insn_reg *ir; | |
1575 | ||
1576 | for (ir = data->regs; ir != NULL; ir = ir->next) | |
1577 | if ((i = ir->regno) >= FIRST_PSEUDO_REGISTER) | |
1578 | { | |
1579 | lra_reg_info[i].nrefs++; | |
1580 | lra_reg_info[i].freq += freq; | |
1581 | } | |
1582 | } | |
1583 | ||
1584 | /* Set up insn reg info of INSN. Update common reg info from reg info | |
1585 | of INSN. */ | |
1586 | void | |
7f836b57 | 1587 | lra_update_insn_regno_info (rtx_insn *insn) |
c6a6cdaa | 1588 | { |
1589 | int i, uid, freq; | |
1590 | lra_insn_recog_data_t data; | |
1591 | struct lra_static_insn_data *static_data; | |
1592 | enum rtx_code code; | |
70ae5dc6 | 1593 | rtx link; |
1594 | ||
c6a6cdaa | 1595 | if (! INSN_P (insn)) |
1596 | return; | |
1597 | data = lra_get_insn_recog_data (insn); | |
1598 | static_data = data->insn_static_data; | |
1599 | freq = get_insn_freq (insn); | |
1600 | invalidate_insn_data_regno_info (data, insn, freq); | |
1601 | uid = INSN_UID (insn); | |
1602 | for (i = static_data->n_operands - 1; i >= 0; i--) | |
1603 | add_regs_to_insn_regno_info (data, *data->operand_loc[i], uid, | |
1604 | static_data->operand[i].type, | |
1605 | static_data->operand[i].early_clobber); | |
1606 | if ((code = GET_CODE (PATTERN (insn))) == CLOBBER || code == USE) | |
1607 | add_regs_to_insn_regno_info (data, XEXP (PATTERN (insn), 0), uid, | |
1608 | code == USE ? OP_IN : OP_OUT, false); | |
70ae5dc6 | 1609 | if (CALL_P (insn)) |
1610 | /* On some targets call insns can refer to pseudos in memory in | |
1611 | CALL_INSN_FUNCTION_USAGE list. Process them in order to | |
1612 | consider their occurrences in calls for different | |
1613 | transformations (e.g. inheritance) with given pseudos. */ | |
1614 | for (link = CALL_INSN_FUNCTION_USAGE (insn); | |
1615 | link != NULL_RTX; | |
1616 | link = XEXP (link, 1)) | |
1617 | if (((code = GET_CODE (XEXP (link, 0))) == USE || code == CLOBBER) | |
1618 | && MEM_P (XEXP (XEXP (link, 0), 0))) | |
1619 | add_regs_to_insn_regno_info (data, XEXP (XEXP (link, 0), 0), uid, | |
1620 | code == USE ? OP_IN : OP_OUT, false); | |
c6a6cdaa | 1621 | if (NONDEBUG_INSN_P (insn)) |
1622 | setup_insn_reg_info (data, freq); | |
1623 | } | |
1624 | ||
1625 | /* Return reg info of insn given by it UID. */ | |
1626 | struct lra_insn_reg * | |
1627 | lra_get_insn_regs (int uid) | |
1628 | { | |
1629 | lra_insn_recog_data_t data; | |
1630 | ||
1631 | data = get_insn_recog_data_by_uid (uid); | |
1632 | return data->regs; | |
1633 | } | |
1634 | ||
1635 | \f | |
1636 | ||
1637 | /* This page contains code dealing with stack of the insns which | |
1638 | should be processed by the next constraint pass. */ | |
1639 | ||
1640 | /* Bitmap used to put an insn on the stack only in one exemplar. */ | |
1641 | static sbitmap lra_constraint_insn_stack_bitmap; | |
1642 | ||
1643 | /* The stack itself. */ | |
7f836b57 | 1644 | vec<rtx_insn *> lra_constraint_insn_stack; |
c6a6cdaa | 1645 | |
1646 | /* Put INSN on the stack. If ALWAYS_UPDATE is true, always update the reg | |
1647 | info for INSN, otherwise only update it if INSN is not already on the | |
1648 | stack. */ | |
1649 | static inline void | |
7f836b57 | 1650 | lra_push_insn_1 (rtx_insn *insn, bool always_update) |
c6a6cdaa | 1651 | { |
1652 | unsigned int uid = INSN_UID (insn); | |
1653 | if (always_update) | |
1654 | lra_update_insn_regno_info (insn); | |
1655 | if (uid >= SBITMAP_SIZE (lra_constraint_insn_stack_bitmap)) | |
1656 | lra_constraint_insn_stack_bitmap = | |
1657 | sbitmap_resize (lra_constraint_insn_stack_bitmap, 3 * uid / 2, 0); | |
08b7917c | 1658 | if (bitmap_bit_p (lra_constraint_insn_stack_bitmap, uid)) |
c6a6cdaa | 1659 | return; |
08b7917c | 1660 | bitmap_set_bit (lra_constraint_insn_stack_bitmap, uid); |
c6a6cdaa | 1661 | if (! always_update) |
1662 | lra_update_insn_regno_info (insn); | |
f1f41a6c | 1663 | lra_constraint_insn_stack.safe_push (insn); |
c6a6cdaa | 1664 | } |
1665 | ||
1666 | /* Put INSN on the stack. */ | |
1667 | void | |
7f836b57 | 1668 | lra_push_insn (rtx_insn *insn) |
c6a6cdaa | 1669 | { |
1670 | lra_push_insn_1 (insn, false); | |
1671 | } | |
1672 | ||
1673 | /* Put INSN on the stack and update its reg info. */ | |
1674 | void | |
7f836b57 | 1675 | lra_push_insn_and_update_insn_regno_info (rtx_insn *insn) |
c6a6cdaa | 1676 | { |
1677 | lra_push_insn_1 (insn, true); | |
1678 | } | |
1679 | ||
1680 | /* Put insn with UID on the stack. */ | |
1681 | void | |
1682 | lra_push_insn_by_uid (unsigned int uid) | |
1683 | { | |
1684 | lra_push_insn (lra_insn_recog_data[uid]->insn); | |
1685 | } | |
1686 | ||
1687 | /* Take the last-inserted insns off the stack and return it. */ | |
7f836b57 | 1688 | rtx_insn * |
c6a6cdaa | 1689 | lra_pop_insn (void) |
1690 | { | |
7f836b57 | 1691 | rtx_insn *insn = lra_constraint_insn_stack.pop (); |
08b7917c | 1692 | bitmap_clear_bit (lra_constraint_insn_stack_bitmap, INSN_UID (insn)); |
c6a6cdaa | 1693 | return insn; |
1694 | } | |
1695 | ||
1696 | /* Return the current size of the insn stack. */ | |
1697 | unsigned int | |
1698 | lra_insn_stack_length (void) | |
1699 | { | |
f1f41a6c | 1700 | return lra_constraint_insn_stack.length (); |
c6a6cdaa | 1701 | } |
1702 | ||
1703 | /* Push insns FROM to TO (excluding it) going in reverse order. */ | |
1704 | static void | |
7f836b57 | 1705 | push_insns (rtx_insn *from, rtx_insn *to) |
c6a6cdaa | 1706 | { |
7f836b57 | 1707 | rtx_insn *insn; |
c6a6cdaa | 1708 | |
1709 | if (from == NULL_RTX) | |
1710 | return; | |
1711 | for (insn = from; insn != to; insn = PREV_INSN (insn)) | |
1712 | if (INSN_P (insn)) | |
1713 | lra_push_insn (insn); | |
1714 | } | |
1715 | ||
3b3a5e5f | 1716 | /* Set up sp offset for insn in range [FROM, LAST]. The offset is |
1717 | taken from the next BB insn after LAST or zero if there in such | |
1718 | insn. */ | |
1719 | static void | |
7f836b57 | 1720 | setup_sp_offset (rtx_insn *from, rtx_insn *last) |
3b3a5e5f | 1721 | { |
7f836b57 | 1722 | rtx_insn *before = next_nonnote_insn_bb (last); |
3b3a5e5f | 1723 | HOST_WIDE_INT offset = (before == NULL_RTX || ! INSN_P (before) |
1724 | ? 0 : lra_get_insn_recog_data (before)->sp_offset); | |
1725 | ||
7f836b57 | 1726 | for (rtx_insn *insn = from; insn != NEXT_INSN (last); insn = NEXT_INSN (insn)) |
3b3a5e5f | 1727 | lra_get_insn_recog_data (insn)->sp_offset = offset; |
1728 | } | |
1729 | ||
c6a6cdaa | 1730 | /* Emit insns BEFORE before INSN and insns AFTER after INSN. Put the |
1731 | insns onto the stack. Print about emitting the insns with | |
1732 | TITLE. */ | |
1733 | void | |
7f836b57 | 1734 | lra_process_new_insns (rtx_insn *insn, rtx_insn *before, rtx_insn *after, |
1735 | const char *title) | |
c6a6cdaa | 1736 | { |
7f836b57 | 1737 | rtx_insn *last; |
c6a6cdaa | 1738 | |
3b3a5e5f | 1739 | if (before == NULL_RTX && after == NULL_RTX) |
1740 | return; | |
1741 | if (lra_dump_file != NULL) | |
c6a6cdaa | 1742 | { |
6dde9719 | 1743 | dump_insn_slim (lra_dump_file, insn); |
c6a6cdaa | 1744 | if (before != NULL_RTX) |
1745 | { | |
1746 | fprintf (lra_dump_file," %s before:\n", title); | |
4cd001d5 | 1747 | dump_rtl_slim (lra_dump_file, before, NULL, -1, 0); |
c6a6cdaa | 1748 | } |
1749 | if (after != NULL_RTX) | |
1750 | { | |
1751 | fprintf (lra_dump_file, " %s after:\n", title); | |
4cd001d5 | 1752 | dump_rtl_slim (lra_dump_file, after, NULL, -1, 0); |
c6a6cdaa | 1753 | } |
1754 | fprintf (lra_dump_file, "\n"); | |
1755 | } | |
1756 | if (before != NULL_RTX) | |
1757 | { | |
1758 | emit_insn_before (before, insn); | |
1759 | push_insns (PREV_INSN (insn), PREV_INSN (before)); | |
3b3a5e5f | 1760 | setup_sp_offset (before, PREV_INSN (insn)); |
c6a6cdaa | 1761 | } |
1762 | if (after != NULL_RTX) | |
1763 | { | |
1764 | for (last = after; NEXT_INSN (last) != NULL_RTX; last = NEXT_INSN (last)) | |
1765 | ; | |
1766 | emit_insn_after (after, insn); | |
1767 | push_insns (last, insn); | |
3b3a5e5f | 1768 | setup_sp_offset (after, last); |
c6a6cdaa | 1769 | } |
1770 | } | |
1771 | ||
1772 | \f | |
1773 | ||
8c0d01a4 | 1774 | /* Replace all references to register OLD_REGNO in *LOC with pseudo |
06072e79 | 1775 | register NEW_REG. Try to simplify subreg of constant if SUBREG_P. |
1776 | Return true if any change was made. */ | |
8c0d01a4 | 1777 | bool |
06072e79 | 1778 | lra_substitute_pseudo (rtx *loc, int old_regno, rtx new_reg, bool subreg_p) |
8c0d01a4 | 1779 | { |
1780 | rtx x = *loc; | |
1781 | bool result = false; | |
1782 | enum rtx_code code; | |
1783 | const char *fmt; | |
1784 | int i, j; | |
1785 | ||
1786 | if (x == NULL_RTX) | |
1787 | return false; | |
1788 | ||
1789 | code = GET_CODE (x); | |
06072e79 | 1790 | if (code == SUBREG && subreg_p) |
8c0d01a4 | 1791 | { |
06072e79 | 1792 | rtx subst, inner = SUBREG_REG (x); |
1793 | /* Transform subreg of constant while we still have inner mode | |
1794 | of the subreg. The subreg internal should not be an insn | |
1795 | operand. */ | |
1796 | if (REG_P (inner) && (int) REGNO (inner) == old_regno | |
1797 | && CONSTANT_P (new_reg) | |
1798 | && (subst = simplify_subreg (GET_MODE (x), new_reg, GET_MODE (inner), | |
1799 | SUBREG_BYTE (x))) != NULL_RTX) | |
1800 | { | |
1801 | *loc = subst; | |
1802 | return true; | |
1803 | } | |
1804 | ||
1805 | } | |
1806 | else if (code == REG && (int) REGNO (x) == old_regno) | |
1807 | { | |
1808 | machine_mode mode = GET_MODE (x); | |
8c0d01a4 | 1809 | machine_mode inner_mode = GET_MODE (new_reg); |
1810 | ||
c77a06af | 1811 | if (mode != inner_mode |
1812 | && ! (CONST_INT_P (new_reg) && SCALAR_INT_MODE_P (mode))) | |
8c0d01a4 | 1813 | { |
1814 | if (GET_MODE_SIZE (mode) >= GET_MODE_SIZE (inner_mode) | |
1815 | || ! SCALAR_INT_MODE_P (inner_mode)) | |
1816 | new_reg = gen_rtx_SUBREG (mode, new_reg, 0); | |
1817 | else | |
1818 | new_reg = gen_lowpart_SUBREG (mode, new_reg); | |
1819 | } | |
1820 | *loc = new_reg; | |
1821 | return true; | |
1822 | } | |
1823 | ||
1824 | /* Scan all the operand sub-expressions. */ | |
1825 | fmt = GET_RTX_FORMAT (code); | |
1826 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1827 | { | |
1828 | if (fmt[i] == 'e') | |
1829 | { | |
06072e79 | 1830 | if (lra_substitute_pseudo (&XEXP (x, i), old_regno, |
1831 | new_reg, subreg_p)) | |
8c0d01a4 | 1832 | result = true; |
1833 | } | |
1834 | else if (fmt[i] == 'E') | |
1835 | { | |
1836 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
06072e79 | 1837 | if (lra_substitute_pseudo (&XVECEXP (x, i, j), old_regno, |
1838 | new_reg, subreg_p)) | |
8c0d01a4 | 1839 | result = true; |
1840 | } | |
1841 | } | |
1842 | return result; | |
1843 | } | |
1844 | ||
06072e79 | 1845 | /* Call lra_substitute_pseudo within an insn. Try to simplify subreg |
1846 | of constant if SUBREG_P. This won't update the insn ptr, just the | |
1847 | contents of the insn. */ | |
8c0d01a4 | 1848 | bool |
06072e79 | 1849 | lra_substitute_pseudo_within_insn (rtx_insn *insn, int old_regno, |
1850 | rtx new_reg, bool subreg_p) | |
8c0d01a4 | 1851 | { |
1852 | rtx loc = insn; | |
06072e79 | 1853 | return lra_substitute_pseudo (&loc, old_regno, new_reg, subreg_p); |
8c0d01a4 | 1854 | } |
1855 | ||
1856 | \f | |
1857 | ||
c6a6cdaa | 1858 | /* This page contains code dealing with scratches (changing them onto |
1859 | pseudos and restoring them from the pseudos). | |
1860 | ||
1861 | We change scratches into pseudos at the beginning of LRA to | |
1862 | simplify dealing with them (conflicts, hard register assignments). | |
1863 | ||
1864 | If the pseudo denoting scratch was spilled it means that we do need | |
1865 | a hard register for it. Such pseudos are transformed back to | |
1866 | scratches at the end of LRA. */ | |
1867 | ||
1868 | /* Description of location of a former scratch operand. */ | |
453f1a8c | 1869 | struct sloc |
c6a6cdaa | 1870 | { |
7f836b57 | 1871 | rtx_insn *insn; /* Insn where the scratch was. */ |
c6a6cdaa | 1872 | int nop; /* Number of the operand which was a scratch. */ |
1873 | }; | |
1874 | ||
453f1a8c | 1875 | typedef struct sloc *sloc_t; |
c6a6cdaa | 1876 | |
c6a6cdaa | 1877 | /* Locations of the former scratches. */ |
f1f41a6c | 1878 | static vec<sloc_t> scratches; |
c6a6cdaa | 1879 | |
1880 | /* Bitmap of scratch regnos. */ | |
1881 | static bitmap_head scratch_bitmap; | |
1882 | ||
1883 | /* Bitmap of scratch operands. */ | |
1884 | static bitmap_head scratch_operand_bitmap; | |
1885 | ||
1886 | /* Return true if pseudo REGNO is made of SCRATCH. */ | |
1887 | bool | |
1888 | lra_former_scratch_p (int regno) | |
1889 | { | |
1890 | return bitmap_bit_p (&scratch_bitmap, regno); | |
1891 | } | |
1892 | ||
1893 | /* Return true if the operand NOP of INSN is a former scratch. */ | |
1894 | bool | |
7f836b57 | 1895 | lra_former_scratch_operand_p (rtx_insn *insn, int nop) |
c6a6cdaa | 1896 | { |
1897 | return bitmap_bit_p (&scratch_operand_bitmap, | |
1898 | INSN_UID (insn) * MAX_RECOG_OPERANDS + nop) != 0; | |
1899 | } | |
1900 | ||
fb87313e | 1901 | /* Register operand NOP in INSN as a former scratch. It will be |
1902 | changed to scratch back, if it is necessary, at the LRA end. */ | |
1903 | void | |
1904 | lra_register_new_scratch_op (rtx_insn *insn, int nop) | |
1905 | { | |
1906 | lra_insn_recog_data_t id = lra_get_insn_recog_data (insn); | |
1907 | rtx op = *id->operand_loc[nop]; | |
1908 | sloc_t loc = XNEW (struct sloc); | |
1909 | lra_assert (REG_P (op)); | |
1910 | loc->insn = insn; | |
1911 | loc->nop = nop; | |
1912 | scratches.safe_push (loc); | |
1913 | bitmap_set_bit (&scratch_bitmap, REGNO (op)); | |
1914 | bitmap_set_bit (&scratch_operand_bitmap, | |
1915 | INSN_UID (insn) * MAX_RECOG_OPERANDS + nop); | |
1916 | add_reg_note (insn, REG_UNUSED, op); | |
1917 | } | |
1918 | ||
c6a6cdaa | 1919 | /* Change scratches onto pseudos and save their location. */ |
1920 | static void | |
1921 | remove_scratches (void) | |
1922 | { | |
1923 | int i; | |
1924 | bool insn_changed_p; | |
1925 | basic_block bb; | |
7f836b57 | 1926 | rtx_insn *insn; |
1927 | rtx reg; | |
c6a6cdaa | 1928 | lra_insn_recog_data_t id; |
1929 | struct lra_static_insn_data *static_id; | |
1930 | ||
f1f41a6c | 1931 | scratches.create (get_max_uid ()); |
c6a6cdaa | 1932 | bitmap_initialize (&scratch_bitmap, ®_obstack); |
1933 | bitmap_initialize (&scratch_operand_bitmap, ®_obstack); | |
fc00614f | 1934 | FOR_EACH_BB_FN (bb, cfun) |
c6a6cdaa | 1935 | FOR_BB_INSNS (bb, insn) |
1936 | if (INSN_P (insn)) | |
1937 | { | |
1938 | id = lra_get_insn_recog_data (insn); | |
1939 | static_id = id->insn_static_data; | |
1940 | insn_changed_p = false; | |
1941 | for (i = 0; i < static_id->n_operands; i++) | |
1942 | if (GET_CODE (*id->operand_loc[i]) == SCRATCH | |
1943 | && GET_MODE (*id->operand_loc[i]) != VOIDmode) | |
1944 | { | |
1945 | insn_changed_p = true; | |
1946 | *id->operand_loc[i] = reg | |
1947 | = lra_create_new_reg (static_id->operand[i].mode, | |
1948 | *id->operand_loc[i], ALL_REGS, NULL); | |
fb87313e | 1949 | lra_register_new_scratch_op (insn, i); |
c6a6cdaa | 1950 | if (lra_dump_file != NULL) |
1951 | fprintf (lra_dump_file, | |
1952 | "Removing SCRATCH in insn #%u (nop %d)\n", | |
1953 | INSN_UID (insn), i); | |
1954 | } | |
1955 | if (insn_changed_p) | |
1956 | /* Because we might use DF right after caller-saves sub-pass | |
1957 | we need to keep DF info up to date. */ | |
1958 | df_insn_rescan (insn); | |
1959 | } | |
1960 | } | |
1961 | ||
1962 | /* Changes pseudos created by function remove_scratches onto scratches. */ | |
1963 | static void | |
1964 | restore_scratches (void) | |
1965 | { | |
f1f41a6c | 1966 | int regno; |
1967 | unsigned i; | |
453f1a8c | 1968 | sloc_t loc; |
7f836b57 | 1969 | rtx_insn *last = NULL; |
c6a6cdaa | 1970 | lra_insn_recog_data_t id = NULL; |
1971 | ||
f1f41a6c | 1972 | for (i = 0; scratches.iterate (i, &loc); i++) |
c6a6cdaa | 1973 | { |
1974 | if (last != loc->insn) | |
1975 | { | |
1976 | last = loc->insn; | |
1977 | id = lra_get_insn_recog_data (last); | |
1978 | } | |
1979 | if (REG_P (*id->operand_loc[loc->nop]) | |
1980 | && ((regno = REGNO (*id->operand_loc[loc->nop])) | |
1981 | >= FIRST_PSEUDO_REGISTER) | |
1982 | && lra_get_regno_hard_regno (regno) < 0) | |
1983 | { | |
1984 | /* It should be only case when scratch register with chosen | |
1985 | constraint 'X' did not get memory or hard register. */ | |
1986 | lra_assert (lra_former_scratch_p (regno)); | |
1987 | *id->operand_loc[loc->nop] | |
1988 | = gen_rtx_SCRATCH (GET_MODE (*id->operand_loc[loc->nop])); | |
1989 | lra_update_dup (id, loc->nop); | |
1990 | if (lra_dump_file != NULL) | |
1991 | fprintf (lra_dump_file, "Restoring SCRATCH in insn #%u(nop %d)\n", | |
1992 | INSN_UID (loc->insn), loc->nop); | |
1993 | } | |
1994 | } | |
f1f41a6c | 1995 | for (i = 0; scratches.iterate (i, &loc); i++) |
c6a6cdaa | 1996 | free (loc); |
f1f41a6c | 1997 | scratches.release (); |
c6a6cdaa | 1998 | bitmap_clear (&scratch_bitmap); |
1999 | bitmap_clear (&scratch_operand_bitmap); | |
2000 | } | |
2001 | ||
2002 | \f | |
2003 | ||
2004 | #ifdef ENABLE_CHECKING | |
2005 | ||
2006 | /* Function checks RTL for correctness. If FINAL_P is true, it is | |
2007 | done at the end of LRA and the check is more rigorous. */ | |
2008 | static void | |
2009 | check_rtl (bool final_p) | |
2010 | { | |
c6a6cdaa | 2011 | basic_block bb; |
7f836b57 | 2012 | rtx_insn *insn; |
c6a6cdaa | 2013 | |
2014 | lra_assert (! final_p || reload_completed); | |
fc00614f | 2015 | FOR_EACH_BB_FN (bb, cfun) |
c6a6cdaa | 2016 | FOR_BB_INSNS (bb, insn) |
2017 | if (NONDEBUG_INSN_P (insn) | |
2018 | && GET_CODE (PATTERN (insn)) != USE | |
2019 | && GET_CODE (PATTERN (insn)) != CLOBBER | |
c6a6cdaa | 2020 | && GET_CODE (PATTERN (insn)) != ASM_INPUT) |
2021 | { | |
2022 | if (final_p) | |
2023 | { | |
835b8178 | 2024 | #ifdef ENABLED_CHECKING |
2025 | extract_constrain_insn (insn); | |
2026 | #endif | |
c6a6cdaa | 2027 | continue; |
2028 | } | |
cba8c2e6 | 2029 | /* LRA code is based on assumption that all addresses can be |
2030 | correctly decomposed. LRA can generate reloads for | |
2031 | decomposable addresses. The decomposition code checks the | |
2032 | correctness of the addresses. So we don't need to check | |
76f778fd | 2033 | the addresses here. Don't call insn_invalid_p here, it can |
2034 | change the code at this stage. */ | |
2035 | if (recog_memoized (insn) < 0 && asm_noperands (PATTERN (insn)) < 0) | |
c6a6cdaa | 2036 | fatal_insn_not_found (insn); |
c6a6cdaa | 2037 | } |
2038 | } | |
2039 | #endif /* #ifdef ENABLE_CHECKING */ | |
2040 | ||
2041 | /* Determine if the current function has an exception receiver block | |
2042 | that reaches the exit block via non-exceptional edges */ | |
2043 | static bool | |
2044 | has_nonexceptional_receiver (void) | |
2045 | { | |
2046 | edge e; | |
2047 | edge_iterator ei; | |
2048 | basic_block *tos, *worklist, bb; | |
2049 | ||
2050 | /* If we're not optimizing, then just err on the safe side. */ | |
2051 | if (!optimize) | |
2052 | return true; | |
1a8f8886 | 2053 | |
c6a6cdaa | 2054 | /* First determine which blocks can reach exit via normal paths. */ |
a28770e1 | 2055 | tos = worklist = XNEWVEC (basic_block, n_basic_blocks_for_fn (cfun) + 1); |
c6a6cdaa | 2056 | |
fc00614f | 2057 | FOR_EACH_BB_FN (bb, cfun) |
c6a6cdaa | 2058 | bb->flags &= ~BB_REACHABLE; |
2059 | ||
2060 | /* Place the exit block on our worklist. */ | |
34154e27 | 2061 | EXIT_BLOCK_PTR_FOR_FN (cfun)->flags |= BB_REACHABLE; |
2062 | *tos++ = EXIT_BLOCK_PTR_FOR_FN (cfun); | |
1a8f8886 | 2063 | |
c6a6cdaa | 2064 | /* Iterate: find everything reachable from what we've already seen. */ |
2065 | while (tos != worklist) | |
2066 | { | |
2067 | bb = *--tos; | |
2068 | ||
2069 | FOR_EACH_EDGE (e, ei, bb->preds) | |
2070 | if (e->flags & EDGE_ABNORMAL) | |
2071 | { | |
2072 | free (worklist); | |
2073 | return true; | |
2074 | } | |
2075 | else | |
2076 | { | |
2077 | basic_block src = e->src; | |
2078 | ||
2079 | if (!(src->flags & BB_REACHABLE)) | |
2080 | { | |
2081 | src->flags |= BB_REACHABLE; | |
2082 | *tos++ = src; | |
2083 | } | |
2084 | } | |
2085 | } | |
2086 | free (worklist); | |
2087 | /* No exceptional block reached exit unexceptionally. */ | |
2088 | return false; | |
2089 | } | |
2090 | ||
2091 | #ifdef AUTO_INC_DEC | |
2092 | ||
2093 | /* Process recursively X of INSN and add REG_INC notes if necessary. */ | |
2094 | static void | |
7f836b57 | 2095 | add_auto_inc_notes (rtx_insn *insn, rtx x) |
c6a6cdaa | 2096 | { |
2097 | enum rtx_code code = GET_CODE (x); | |
2098 | const char *fmt; | |
2099 | int i, j; | |
2100 | ||
2101 | if (code == MEM && auto_inc_p (XEXP (x, 0))) | |
2102 | { | |
2103 | add_reg_note (insn, REG_INC, XEXP (XEXP (x, 0), 0)); | |
2104 | return; | |
2105 | } | |
2106 | ||
2107 | /* Scan all X sub-expressions. */ | |
2108 | fmt = GET_RTX_FORMAT (code); | |
2109 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2110 | { | |
2111 | if (fmt[i] == 'e') | |
2112 | add_auto_inc_notes (insn, XEXP (x, i)); | |
2113 | else if (fmt[i] == 'E') | |
2114 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
2115 | add_auto_inc_notes (insn, XVECEXP (x, i, j)); | |
2116 | } | |
2117 | } | |
2118 | ||
2119 | #endif | |
2120 | ||
2121 | /* Remove all REG_DEAD and REG_UNUSED notes and regenerate REG_INC. | |
2122 | We change pseudos by hard registers without notification of DF and | |
2123 | that can make the notes obsolete. DF-infrastructure does not deal | |
2124 | with REG_INC notes -- so we should regenerate them here. */ | |
2125 | static void | |
2126 | update_inc_notes (void) | |
2127 | { | |
2128 | rtx *pnote; | |
2129 | basic_block bb; | |
7f836b57 | 2130 | rtx_insn *insn; |
c6a6cdaa | 2131 | |
fc00614f | 2132 | FOR_EACH_BB_FN (bb, cfun) |
c6a6cdaa | 2133 | FOR_BB_INSNS (bb, insn) |
2134 | if (NONDEBUG_INSN_P (insn)) | |
2135 | { | |
2136 | pnote = ®_NOTES (insn); | |
2137 | while (*pnote != 0) | |
2138 | { | |
e2ca76ac | 2139 | if (REG_NOTE_KIND (*pnote) == REG_DEAD |
2140 | || REG_NOTE_KIND (*pnote) == REG_UNUSED | |
2141 | || REG_NOTE_KIND (*pnote) == REG_INC) | |
c6a6cdaa | 2142 | *pnote = XEXP (*pnote, 1); |
2143 | else | |
2144 | pnote = &XEXP (*pnote, 1); | |
2145 | } | |
2146 | #ifdef AUTO_INC_DEC | |
2147 | add_auto_inc_notes (insn, PATTERN (insn)); | |
2148 | #endif | |
2149 | } | |
2150 | } | |
2151 | ||
2152 | /* Set to 1 while in lra. */ | |
2153 | int lra_in_progress; | |
2154 | ||
edfb1d8f | 2155 | /* Start of pseudo regnos before the LRA. */ |
2156 | int lra_new_regno_start; | |
2157 | ||
1a8f8886 | 2158 | /* Start of reload pseudo regnos before the new spill pass. */ |
c6a6cdaa | 2159 | int lra_constraint_new_regno_start; |
2160 | ||
0f7b6a0d | 2161 | /* Avoid spilling pseudos with regno more than the following value if |
2162 | it is possible. */ | |
2163 | int lra_bad_spill_regno_start; | |
2164 | ||
1a8f8886 | 2165 | /* Inheritance pseudo regnos before the new spill pass. */ |
c6a6cdaa | 2166 | bitmap_head lra_inheritance_pseudos; |
2167 | ||
1a8f8886 | 2168 | /* Split regnos before the new spill pass. */ |
c6a6cdaa | 2169 | bitmap_head lra_split_regs; |
2170 | ||
1f3a048a | 2171 | /* Reload pseudo regnos before the new assignmnet pass which still can |
2172 | be spilled after the assinment pass as memory is also accepted in | |
2173 | insns for the reload pseudos. */ | |
c6a6cdaa | 2174 | bitmap_head lra_optional_reload_pseudos; |
2175 | ||
1f3a048a | 2176 | /* Pseudo regnos used for subreg reloads before the new assignment |
2177 | pass. Such pseudos still can be spilled after the assinment | |
2178 | pass. */ | |
2179 | bitmap_head lra_subreg_reload_pseudos; | |
2180 | ||
c6a6cdaa | 2181 | /* File used for output of LRA debug information. */ |
2182 | FILE *lra_dump_file; | |
2183 | ||
2184 | /* True if we should try spill into registers of different classes | |
2185 | instead of memory. */ | |
2186 | bool lra_reg_spill_p; | |
2187 | ||
2188 | /* Set up value LRA_REG_SPILL_P. */ | |
2189 | static void | |
2190 | setup_reg_spill_flag (void) | |
2191 | { | |
2192 | int cl, mode; | |
2193 | ||
2194 | if (targetm.spill_class != NULL) | |
2195 | for (cl = 0; cl < (int) LIM_REG_CLASSES; cl++) | |
2196 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
2197 | if (targetm.spill_class ((enum reg_class) cl, | |
3754d046 | 2198 | (machine_mode) mode) != NO_REGS) |
c6a6cdaa | 2199 | { |
2200 | lra_reg_spill_p = true; | |
2201 | return; | |
2202 | } | |
2203 | lra_reg_spill_p = false; | |
2204 | } | |
2205 | ||
2206 | /* True if the current function is too big to use regular algorithms | |
2207 | in LRA. In other words, we should use simpler and faster algorithms | |
2208 | in LRA. It also means we should not worry about generation code | |
2209 | for caller saves. The value is set up in IRA. */ | |
2210 | bool lra_simple_p; | |
2211 | ||
2212 | /* Major LRA entry function. F is a file should be used to dump LRA | |
2213 | debug info. */ | |
2214 | void | |
2215 | lra (FILE *f) | |
2216 | { | |
2217 | int i; | |
2218 | bool live_p, scratch_p, inserted_p; | |
2219 | ||
2220 | lra_dump_file = f; | |
2221 | ||
2222 | timevar_push (TV_LRA); | |
2223 | ||
ea99c7a1 | 2224 | /* Make sure that the last insn is a note. Some subsequent passes |
2225 | need it. */ | |
2226 | emit_note (NOTE_INSN_DELETED); | |
2227 | ||
fc8a0f60 | 2228 | COPY_HARD_REG_SET (lra_no_alloc_regs, ira_no_alloc_regs); |
2229 | ||
b85cafd3 | 2230 | init_reg_info (); |
2231 | expand_reg_info (); | |
2232 | ||
c6a6cdaa | 2233 | init_insn_recog_data (); |
2234 | ||
2235 | #ifdef ENABLE_CHECKING | |
76f778fd | 2236 | /* Some quick check on RTL generated by previous passes. */ |
c6a6cdaa | 2237 | check_rtl (false); |
2238 | #endif | |
2239 | ||
76f778fd | 2240 | lra_in_progress = 1; |
2241 | ||
f95727ee | 2242 | lra_live_range_iter = lra_coalesce_iter = lra_constraint_iter = 0; |
2243 | lra_assignment_iter = lra_assignment_iter_after_spill = 0; | |
c6a6cdaa | 2244 | lra_inheritance_iter = lra_undo_inheritance_iter = 0; |
fa4f0b4e | 2245 | lra_rematerialization_iter = 0; |
c6a6cdaa | 2246 | |
2247 | setup_reg_spill_flag (); | |
2248 | ||
c6a6cdaa | 2249 | /* Function remove_scratches can creates new pseudos for clobbers -- |
2250 | so set up lra_constraint_new_regno_start before its call to | |
2251 | permit changing reg classes for pseudos created by this | |
2252 | simplification. */ | |
edfb1d8f | 2253 | lra_constraint_new_regno_start = lra_new_regno_start = max_reg_num (); |
0f7b6a0d | 2254 | lra_bad_spill_regno_start = INT_MAX; |
c6a6cdaa | 2255 | remove_scratches (); |
2256 | scratch_p = lra_constraint_new_regno_start != max_reg_num (); | |
2257 | ||
2258 | /* A function that has a non-local label that can reach the exit | |
2259 | block via non-exceptional paths must save all call-saved | |
2260 | registers. */ | |
2261 | if (cfun->has_nonlocal_label && has_nonexceptional_receiver ()) | |
2262 | crtl->saves_all_registers = 1; | |
2263 | ||
2264 | if (crtl->saves_all_registers) | |
2265 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
2266 | if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i)) | |
2267 | df_set_regs_ever_live (i, true); | |
2268 | ||
2269 | /* We don't DF from now and avoid its using because it is to | |
2270 | expensive when a lot of RTL changes are made. */ | |
2271 | df_set_flags (DF_NO_INSN_RESCAN); | |
f1f41a6c | 2272 | lra_constraint_insn_stack.create (get_max_uid ()); |
c6a6cdaa | 2273 | lra_constraint_insn_stack_bitmap = sbitmap_alloc (get_max_uid ()); |
53c5d9d4 | 2274 | bitmap_clear (lra_constraint_insn_stack_bitmap); |
c6a6cdaa | 2275 | lra_live_ranges_init (); |
2276 | lra_constraints_init (); | |
2277 | lra_curr_reload_num = 0; | |
7f836b57 | 2278 | push_insns (get_last_insn (), NULL); |
c6a6cdaa | 2279 | /* It is needed for the 1st coalescing. */ |
c6a6cdaa | 2280 | bitmap_initialize (&lra_inheritance_pseudos, ®_obstack); |
2281 | bitmap_initialize (&lra_split_regs, ®_obstack); | |
2282 | bitmap_initialize (&lra_optional_reload_pseudos, ®_obstack); | |
1f3a048a | 2283 | bitmap_initialize (&lra_subreg_reload_pseudos, ®_obstack); |
c6a6cdaa | 2284 | live_p = false; |
ea99c7a1 | 2285 | if (get_frame_size () != 0 && crtl->stack_alignment_needed) |
2286 | /* If we have a stack frame, we must align it now. The stack size | |
2287 | may be a part of the offset computation for register | |
2288 | elimination. */ | |
2289 | assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed); | |
61cd3e57 | 2290 | lra_init_equiv (); |
c6a6cdaa | 2291 | for (;;) |
2292 | { | |
2293 | for (;;) | |
2294 | { | |
c6a6cdaa | 2295 | /* We should try to assign hard registers to scratches even |
2296 | if there were no RTL transformations in | |
2297 | lra_constraints. */ | |
2298 | if (! lra_constraints (lra_constraint_iter == 0) | |
2299 | && (lra_constraint_iter > 1 | |
2300 | || (! scratch_p && ! caller_save_needed))) | |
2301 | break; | |
2302 | /* Constraint transformations may result in that eliminable | |
2303 | hard regs become uneliminable and pseudos which use them | |
2304 | should be spilled. It is better to do it before pseudo | |
2305 | assignments. | |
2306 | ||
2307 | For example, rs6000 can make | |
2308 | RS6000_PIC_OFFSET_TABLE_REGNUM uneliminable if we started | |
2309 | to use a constant pool. */ | |
3b3a5e5f | 2310 | lra_eliminate (false, false); |
c6a6cdaa | 2311 | /* Do inheritance only for regular algorithms. */ |
2312 | if (! lra_simple_p) | |
f2cc6708 | 2313 | { |
fcf56aaf | 2314 | if (flag_ipa_ra) |
f2cc6708 | 2315 | { |
2316 | if (live_p) | |
2317 | lra_clear_live_ranges (); | |
2318 | /* As a side-effect of lra_create_live_ranges, we calculate | |
2319 | actual_call_used_reg_set, which is needed during | |
2320 | lra_inheritance. */ | |
04472658 | 2321 | lra_create_live_ranges (true, true); |
2045f87a | 2322 | live_p = true; |
f2cc6708 | 2323 | } |
2324 | lra_inheritance (); | |
2325 | } | |
d3d0b390 | 2326 | if (live_p) |
2327 | lra_clear_live_ranges (); | |
04472658 | 2328 | /* We need live ranges for lra_assign -- so build them. But |
2329 | don't remove dead insns or change global live info as we | |
2330 | can undo inheritance transformations after inheritance | |
2331 | pseudo assigning. */ | |
2332 | lra_create_live_ranges (true, false); | |
c6a6cdaa | 2333 | live_p = true; |
2334 | /* If we don't spill non-reload and non-inheritance pseudos, | |
2335 | there is no sense to run memory-memory move coalescing. | |
2336 | If inheritance pseudos were spilled, the memory-memory | |
2337 | moves involving them will be removed by pass undoing | |
2338 | inheritance. */ | |
2339 | if (lra_simple_p) | |
2340 | lra_assign (); | |
2341 | else | |
2342 | { | |
638e746e | 2343 | bool spill_p = !lra_assign (); |
2344 | ||
c6a6cdaa | 2345 | if (lra_undo_inheritance ()) |
2346 | live_p = false; | |
638e746e | 2347 | if (spill_p) |
2348 | { | |
2349 | if (! live_p) | |
2350 | { | |
04472658 | 2351 | lra_create_live_ranges (true, true); |
638e746e | 2352 | live_p = true; |
2353 | } | |
2354 | if (lra_coalesce ()) | |
2355 | live_p = false; | |
2356 | } | |
d3d0b390 | 2357 | if (! live_p) |
2358 | lra_clear_live_ranges (); | |
c6a6cdaa | 2359 | } |
2360 | } | |
95563487 | 2361 | /* Don't clear optional reloads bitmap until all constraints are |
2362 | satisfied as we need to differ them from regular reloads. */ | |
2363 | bitmap_clear (&lra_optional_reload_pseudos); | |
1f3a048a | 2364 | bitmap_clear (&lra_subreg_reload_pseudos); |
c6a6cdaa | 2365 | bitmap_clear (&lra_inheritance_pseudos); |
2366 | bitmap_clear (&lra_split_regs); | |
c6a6cdaa | 2367 | if (! live_p) |
2368 | { | |
2369 | /* We need full live info for spilling pseudos into | |
2370 | registers instead of memory. */ | |
04472658 | 2371 | lra_create_live_ranges (lra_reg_spill_p, true); |
c6a6cdaa | 2372 | live_p = true; |
2373 | } | |
04472658 | 2374 | /* We should check necessity for spilling here as the above live |
2375 | range pass can remove spilled pseudos. */ | |
2376 | if (! lra_need_for_spills_p ()) | |
2377 | break; | |
497ba60f | 2378 | /* Now we know what pseudos should be spilled. Try to |
2379 | rematerialize them first. */ | |
68474cd7 | 2380 | if (lra_remat ()) |
497ba60f | 2381 | { |
2382 | /* We need full live info -- see the comment above. */ | |
04472658 | 2383 | lra_create_live_ranges (lra_reg_spill_p, true); |
497ba60f | 2384 | live_p = true; |
2385 | if (! lra_need_for_spills_p ()) | |
2386 | break; | |
2387 | } | |
c6a6cdaa | 2388 | lra_spill (); |
2389 | /* Assignment of stack slots changes elimination offsets for | |
2390 | some eliminations. So update the offsets here. */ | |
3b3a5e5f | 2391 | lra_eliminate (false, false); |
0f7b6a0d | 2392 | lra_constraint_new_regno_start = max_reg_num (); |
2393 | if (lra_bad_spill_regno_start == INT_MAX | |
2394 | && lra_inheritance_iter > LRA_MAX_INHERITANCE_PASSES | |
2395 | && lra_rematerialization_iter > LRA_MAX_REMATERIALIZATION_PASSES) | |
2396 | /* After switching off inheritance and rematerialization | |
2397 | passes, avoid spilling reload pseudos will be created to | |
2398 | prevent LRA cycling in some complicated cases. */ | |
2399 | lra_bad_spill_regno_start = lra_constraint_new_regno_start; | |
f95727ee | 2400 | lra_assignment_iter_after_spill = 0; |
c6a6cdaa | 2401 | } |
2402 | restore_scratches (); | |
3b3a5e5f | 2403 | lra_eliminate (true, false); |
ae72d5b2 | 2404 | lra_final_code_change (); |
c6a6cdaa | 2405 | lra_in_progress = 0; |
d3d0b390 | 2406 | if (live_p) |
2407 | lra_clear_live_ranges (); | |
c6a6cdaa | 2408 | lra_live_ranges_finish (); |
2409 | lra_constraints_finish (); | |
2410 | finish_reg_info (); | |
2411 | sbitmap_free (lra_constraint_insn_stack_bitmap); | |
f1f41a6c | 2412 | lra_constraint_insn_stack.release (); |
c6a6cdaa | 2413 | finish_insn_recog_data (); |
2414 | regstat_free_n_sets_and_refs (); | |
2415 | regstat_free_ri (); | |
2416 | reload_completed = 1; | |
2417 | update_inc_notes (); | |
2418 | ||
2419 | inserted_p = fixup_abnormal_edges (); | |
2420 | ||
2421 | /* We've possibly turned single trapping insn into multiple ones. */ | |
2422 | if (cfun->can_throw_non_call_exceptions) | |
2423 | { | |
2424 | sbitmap blocks; | |
fe672ac0 | 2425 | blocks = sbitmap_alloc (last_basic_block_for_fn (cfun)); |
53c5d9d4 | 2426 | bitmap_ones (blocks); |
c6a6cdaa | 2427 | find_many_sub_basic_blocks (blocks); |
2428 | sbitmap_free (blocks); | |
2429 | } | |
2430 | ||
2431 | if (inserted_p) | |
2432 | commit_edge_insertions (); | |
2433 | ||
2434 | /* Replacing pseudos with their memory equivalents might have | |
2435 | created shared rtx. Subsequent passes would get confused | |
2436 | by this, so unshare everything here. */ | |
2437 | unshare_all_rtl_again (get_insns ()); | |
2438 | ||
2439 | #ifdef ENABLE_CHECKING | |
2440 | check_rtl (true); | |
2441 | #endif | |
2442 | ||
2443 | timevar_pop (TV_LRA); | |
2444 | } | |
2445 | ||
2446 | /* Called once per compiler to initialize LRA data once. */ | |
2447 | void | |
2448 | lra_init_once (void) | |
2449 | { | |
2450 | init_insn_code_data_once (); | |
2451 | } | |
2452 | ||
c6a6cdaa | 2453 | /* Called once per compiler to finish LRA data which are initialize |
2454 | once. */ | |
2455 | void | |
2456 | lra_finish_once (void) | |
2457 | { | |
2458 | finish_insn_code_data_once (); | |
2459 | } |