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610d2478 | 1 | /* CPU mode switching |
23a5b65a | 2 | Copyright (C) 1998-2014 Free Software Foundation, Inc. |
610d2478 SB |
3 | |
4 | This file is part of GCC. | |
5 | ||
6 | GCC is free software; you can redistribute it and/or modify it under | |
7 | the terms of the GNU General Public License as published by the Free | |
9dcd6f09 | 8 | Software Foundation; either version 3, or (at your option) any later |
610d2478 SB |
9 | version. |
10 | ||
11 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
12 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
14 | for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
9dcd6f09 NC |
17 | along with GCC; see the file COPYING3. If not see |
18 | <http://www.gnu.org/licenses/>. */ | |
610d2478 SB |
19 | |
20 | #include "config.h" | |
21 | #include "system.h" | |
22 | #include "coretypes.h" | |
23 | #include "tm.h" | |
82f81f18 | 24 | #include "target.h" |
610d2478 SB |
25 | #include "rtl.h" |
26 | #include "regs.h" | |
27 | #include "hard-reg-set.h" | |
28 | #include "flags.h" | |
610d2478 SB |
29 | #include "insn-config.h" |
30 | #include "recog.h" | |
31 | #include "basic-block.h" | |
610d2478 | 32 | #include "tm_p.h" |
83685514 AM |
33 | #include "hashtab.h" |
34 | #include "hash-set.h" | |
35 | #include "vec.h" | |
36 | #include "machmode.h" | |
37 | #include "input.h" | |
610d2478 | 38 | #include "function.h" |
ef330312 | 39 | #include "tree-pass.h" |
6fb5fa3c | 40 | #include "df.h" |
5936d944 | 41 | #include "emit-rtl.h" |
610d2478 SB |
42 | |
43 | /* We want target macros for the mode switching code to be able to refer | |
44 | to instruction attribute values. */ | |
45 | #include "insn-attr.h" | |
46 | ||
47 | #ifdef OPTIMIZE_MODE_SWITCHING | |
48 | ||
49 | /* The algorithm for setting the modes consists of scanning the insn list | |
50 | and finding all the insns which require a specific mode. Each insn gets | |
51 | a unique struct seginfo element. These structures are inserted into a list | |
52 | for each basic block. For each entity, there is an array of bb_info over | |
cee9defb | 53 | the flow graph basic blocks (local var 'bb_info'), which contains a list |
610d2478 SB |
54 | of all insns within that basic block, in the order they are encountered. |
55 | ||
56 | For each entity, any basic block WITHOUT any insns requiring a specific | |
cee9defb EB |
57 | mode are given a single entry without a mode (each basic block in the |
58 | flow graph must have at least one entry in the segment table). | |
610d2478 SB |
59 | |
60 | The LCM algorithm is then run over the flow graph to determine where to | |
cee9defb | 61 | place the sets to the highest-priority mode with respect to the first |
610d2478 SB |
62 | insn in any one block. Any adjustments required to the transparency |
63 | vectors are made, then the next iteration starts for the next-lower | |
64 | priority mode, till for each entity all modes are exhausted. | |
65 | ||
cee9defb | 66 | More details can be found in the code of optimize_mode_switching. */ |
610d2478 SB |
67 | \f |
68 | /* This structure contains the information for each insn which requires | |
69 | either single or double mode to be set. | |
70 | MODE is the mode this insn must be executed in. | |
71 | INSN_PTR is the insn to be executed (may be the note that marks the | |
72 | beginning of a basic block). | |
73 | BBNUM is the flow graph basic block this insn occurs in. | |
74 | NEXT is the next insn in the same basic block. */ | |
75 | struct seginfo | |
76 | { | |
77 | int mode; | |
1d455520 | 78 | rtx_insn *insn_ptr; |
610d2478 SB |
79 | int bbnum; |
80 | struct seginfo *next; | |
81 | HARD_REG_SET regs_live; | |
82 | }; | |
83 | ||
84 | struct bb_info | |
85 | { | |
86 | struct seginfo *seginfo; | |
87 | int computing; | |
cbb1e3d9 CB |
88 | int mode_out; |
89 | int mode_in; | |
610d2478 SB |
90 | }; |
91 | ||
1d455520 | 92 | static struct seginfo * new_seginfo (int, rtx_insn *, int, HARD_REG_SET); |
610d2478 | 93 | static void add_seginfo (struct bb_info *, struct seginfo *); |
408bed3c | 94 | static void reg_dies (rtx, HARD_REG_SET *); |
7bc980e1 | 95 | static void reg_becomes_live (rtx, const_rtx, void *); |
610d2478 | 96 | |
cbb1e3d9 CB |
97 | /* Clear ode I from entity J in bitmap B. */ |
98 | #define clear_mode_bit(b, j, i) \ | |
99 | bitmap_clear_bit (b, (j * max_num_modes) + i) | |
100 | ||
101 | /* Test mode I from entity J in bitmap B. */ | |
102 | #define mode_bit_p(b, j, i) \ | |
103 | bitmap_bit_p (b, (j * max_num_modes) + i) | |
104 | ||
105 | /* Set mode I from entity J in bitmal B. */ | |
106 | #define set_mode_bit(b, j, i) \ | |
107 | bitmap_set_bit (b, (j * max_num_modes) + i) | |
108 | ||
109 | /* Emit modes segments from EDGE_LIST associated with entity E. | |
110 | INFO gives mode availability for each mode. */ | |
111 | ||
112 | static bool | |
113 | commit_mode_sets (struct edge_list *edge_list, int e, struct bb_info *info) | |
114 | { | |
115 | bool need_commit = false; | |
116 | ||
117 | for (int ed = NUM_EDGES (edge_list) - 1; ed >= 0; ed--) | |
118 | { | |
119 | edge eg = INDEX_EDGE (edge_list, ed); | |
120 | int mode; | |
121 | ||
122 | if ((mode = (int)(intptr_t)(eg->aux)) != -1) | |
123 | { | |
124 | HARD_REG_SET live_at_edge; | |
125 | basic_block src_bb = eg->src; | |
126 | int cur_mode = info[src_bb->index].mode_out; | |
127 | rtx mode_set; | |
128 | ||
129 | REG_SET_TO_HARD_REG_SET (live_at_edge, df_get_live_out (src_bb)); | |
130 | ||
131 | rtl_profile_for_edge (eg); | |
132 | start_sequence (); | |
133 | ||
134 | targetm.mode_switching.emit (e, mode, cur_mode, live_at_edge); | |
135 | ||
136 | mode_set = get_insns (); | |
137 | end_sequence (); | |
138 | default_rtl_profile (); | |
139 | ||
140 | /* Do not bother to insert empty sequence. */ | |
141 | if (mode_set == NULL_RTX) | |
142 | continue; | |
143 | ||
144 | /* We should not get an abnormal edge here. */ | |
145 | gcc_assert (! (eg->flags & EDGE_ABNORMAL)); | |
146 | ||
147 | need_commit = true; | |
148 | insert_insn_on_edge (mode_set, eg); | |
149 | } | |
150 | } | |
151 | ||
152 | return need_commit; | |
153 | } | |
154 | ||
155 | /* Allocate a new BBINFO structure, initialized with the MODE, INSN, | |
156 | and basic block BB parameters. | |
473fd99a JR |
157 | INSN may not be a NOTE_INSN_BASIC_BLOCK, unless it is an empty |
158 | basic block; that allows us later to insert instructions in a FIFO-like | |
159 | manner. */ | |
610d2478 SB |
160 | |
161 | static struct seginfo * | |
1d455520 | 162 | new_seginfo (int mode, rtx_insn *insn, int bb, HARD_REG_SET regs_live) |
610d2478 SB |
163 | { |
164 | struct seginfo *ptr; | |
473fd99a JR |
165 | |
166 | gcc_assert (!NOTE_INSN_BASIC_BLOCK_P (insn) | |
167 | || insn == BB_END (NOTE_BASIC_BLOCK (insn))); | |
5ed6ace5 | 168 | ptr = XNEW (struct seginfo); |
610d2478 SB |
169 | ptr->mode = mode; |
170 | ptr->insn_ptr = insn; | |
171 | ptr->bbnum = bb; | |
172 | ptr->next = NULL; | |
173 | COPY_HARD_REG_SET (ptr->regs_live, regs_live); | |
174 | return ptr; | |
175 | } | |
176 | ||
177 | /* Add a seginfo element to the end of a list. | |
178 | HEAD is a pointer to the list beginning. | |
179 | INFO is the structure to be linked in. */ | |
180 | ||
181 | static void | |
182 | add_seginfo (struct bb_info *head, struct seginfo *info) | |
183 | { | |
184 | struct seginfo *ptr; | |
185 | ||
186 | if (head->seginfo == NULL) | |
187 | head->seginfo = info; | |
188 | else | |
189 | { | |
190 | ptr = head->seginfo; | |
191 | while (ptr->next != NULL) | |
192 | ptr = ptr->next; | |
193 | ptr->next = info; | |
194 | } | |
195 | } | |
196 | ||
610d2478 SB |
197 | /* Record in LIVE that register REG died. */ |
198 | ||
199 | static void | |
408bed3c | 200 | reg_dies (rtx reg, HARD_REG_SET *live) |
610d2478 | 201 | { |
09e18274 | 202 | int regno; |
610d2478 SB |
203 | |
204 | if (!REG_P (reg)) | |
205 | return; | |
206 | ||
207 | regno = REGNO (reg); | |
208 | if (regno < FIRST_PSEUDO_REGISTER) | |
09e18274 | 209 | remove_from_hard_reg_set (live, GET_MODE (reg), regno); |
610d2478 SB |
210 | } |
211 | ||
212 | /* Record in LIVE that register REG became live. | |
213 | This is called via note_stores. */ | |
214 | ||
215 | static void | |
7bc980e1 | 216 | reg_becomes_live (rtx reg, const_rtx setter ATTRIBUTE_UNUSED, void *live) |
610d2478 | 217 | { |
09e18274 | 218 | int regno; |
610d2478 SB |
219 | |
220 | if (GET_CODE (reg) == SUBREG) | |
221 | reg = SUBREG_REG (reg); | |
222 | ||
223 | if (!REG_P (reg)) | |
224 | return; | |
225 | ||
226 | regno = REGNO (reg); | |
227 | if (regno < FIRST_PSEUDO_REGISTER) | |
09e18274 | 228 | add_to_hard_reg_set ((HARD_REG_SET *) live, GET_MODE (reg), regno); |
610d2478 SB |
229 | } |
230 | ||
610d2478 SB |
231 | /* Split the fallthrough edge to the exit block, so that we can note |
232 | that there NORMAL_MODE is required. Return the new block if it's | |
233 | inserted before the exit block. Otherwise return null. */ | |
234 | ||
235 | static basic_block | |
236 | create_pre_exit (int n_entities, int *entity_map, const int *num_modes) | |
237 | { | |
238 | edge eg; | |
239 | edge_iterator ei; | |
240 | basic_block pre_exit; | |
241 | ||
242 | /* The only non-call predecessor at this stage is a block with a | |
243 | fallthrough edge; there can be at most one, but there could be | |
244 | none at all, e.g. when exit is called. */ | |
245 | pre_exit = 0; | |
fefa31b5 | 246 | FOR_EACH_EDGE (eg, ei, EXIT_BLOCK_PTR_FOR_FN (cfun)->preds) |
610d2478 SB |
247 | if (eg->flags & EDGE_FALLTHRU) |
248 | { | |
249 | basic_block src_bb = eg->src; | |
1d455520 DM |
250 | rtx_insn *last_insn; |
251 | rtx ret_reg; | |
610d2478 SB |
252 | |
253 | gcc_assert (!pre_exit); | |
254 | /* If this function returns a value at the end, we have to | |
255 | insert the final mode switch before the return value copy | |
256 | to its hard register. */ | |
fefa31b5 | 257 | if (EDGE_COUNT (EXIT_BLOCK_PTR_FOR_FN (cfun)->preds) == 1 |
610d2478 SB |
258 | && NONJUMP_INSN_P ((last_insn = BB_END (src_bb))) |
259 | && GET_CODE (PATTERN (last_insn)) == USE | |
260 | && GET_CODE ((ret_reg = XEXP (PATTERN (last_insn), 0))) == REG) | |
261 | { | |
262 | int ret_start = REGNO (ret_reg); | |
263 | int nregs = hard_regno_nregs[ret_start][GET_MODE (ret_reg)]; | |
264 | int ret_end = ret_start + nregs; | |
c07757e5 UB |
265 | bool short_block = false; |
266 | bool multi_reg_return = false; | |
267 | bool forced_late_switch = false; | |
1d455520 | 268 | rtx_insn *before_return_copy; |
610d2478 SB |
269 | |
270 | do | |
271 | { | |
1d455520 | 272 | rtx_insn *return_copy = PREV_INSN (last_insn); |
610d2478 SB |
273 | rtx return_copy_pat, copy_reg; |
274 | int copy_start, copy_num; | |
275 | int j; | |
276 | ||
141a9e06 | 277 | if (NONDEBUG_INSN_P (return_copy)) |
610d2478 | 278 | { |
2bde7ae9 RS |
279 | /* When using SJLJ exceptions, the call to the |
280 | unregister function is inserted between the | |
281 | clobber of the return value and the copy. | |
282 | We do not want to split the block before this | |
283 | or any other call; if we have not found the | |
284 | copy yet, the copy must have been deleted. */ | |
285 | if (CALL_P (return_copy)) | |
286 | { | |
c07757e5 | 287 | short_block = true; |
2bde7ae9 RS |
288 | break; |
289 | } | |
89ab4659 KK |
290 | return_copy_pat = PATTERN (return_copy); |
291 | switch (GET_CODE (return_copy_pat)) | |
07288ab0 | 292 | { |
89ab4659 | 293 | case USE: |
c07757e5 UB |
294 | /* Skip USEs of multiple return registers. |
295 | __builtin_apply pattern is also handled here. */ | |
89ab4659 | 296 | if (GET_CODE (XEXP (return_copy_pat, 0)) == REG |
82f81f18 | 297 | && (targetm.calls.function_value_regno_p |
89ab4659 KK |
298 | (REGNO (XEXP (return_copy_pat, 0))))) |
299 | { | |
c07757e5 | 300 | multi_reg_return = true; |
89ab4659 KK |
301 | last_insn = return_copy; |
302 | continue; | |
303 | } | |
304 | break; | |
305 | ||
306 | case ASM_OPERANDS: | |
307 | /* Skip barrier insns. */ | |
308 | if (!MEM_VOLATILE_P (return_copy_pat)) | |
309 | break; | |
310 | ||
311 | /* Fall through. */ | |
312 | ||
313 | case ASM_INPUT: | |
314 | case UNSPEC_VOLATILE: | |
07288ab0 KK |
315 | last_insn = return_copy; |
316 | continue; | |
89ab4659 KK |
317 | |
318 | default: | |
319 | break; | |
07288ab0 | 320 | } |
89ab4659 | 321 | |
610d2478 SB |
322 | /* If the return register is not (in its entirety) |
323 | likely spilled, the return copy might be | |
324 | partially or completely optimized away. */ | |
325 | return_copy_pat = single_set (return_copy); | |
326 | if (!return_copy_pat) | |
327 | { | |
328 | return_copy_pat = PATTERN (return_copy); | |
329 | if (GET_CODE (return_copy_pat) != CLOBBER) | |
330 | break; | |
6fb5fa3c DB |
331 | else if (!optimize) |
332 | { | |
333 | /* This might be (clobber (reg [<result>])) | |
334 | when not optimizing. Then check if | |
335 | the previous insn is the clobber for | |
336 | the return register. */ | |
337 | copy_reg = SET_DEST (return_copy_pat); | |
338 | if (GET_CODE (copy_reg) == REG | |
339 | && !HARD_REGISTER_NUM_P (REGNO (copy_reg))) | |
340 | { | |
341 | if (INSN_P (PREV_INSN (return_copy))) | |
342 | { | |
343 | return_copy = PREV_INSN (return_copy); | |
344 | return_copy_pat = PATTERN (return_copy); | |
345 | if (GET_CODE (return_copy_pat) != CLOBBER) | |
346 | break; | |
347 | } | |
348 | } | |
349 | } | |
610d2478 SB |
350 | } |
351 | copy_reg = SET_DEST (return_copy_pat); | |
352 | if (GET_CODE (copy_reg) == REG) | |
353 | copy_start = REGNO (copy_reg); | |
354 | else if (GET_CODE (copy_reg) == SUBREG | |
355 | && GET_CODE (SUBREG_REG (copy_reg)) == REG) | |
356 | copy_start = REGNO (SUBREG_REG (copy_reg)); | |
357 | else | |
d78e64db KK |
358 | { |
359 | /* When control reaches end of non-void function, | |
360 | there are no return copy insns at all. This | |
361 | avoids an ice on that invalid function. */ | |
362 | if (ret_start + nregs == ret_end) | |
c07757e5 | 363 | short_block = true; |
d78e64db KK |
364 | break; |
365 | } | |
ffbbfaba | 366 | if (!targetm.calls.function_value_regno_p (copy_start)) |
ce4a9422 JR |
367 | copy_num = 0; |
368 | else | |
369 | copy_num | |
370 | = hard_regno_nregs[copy_start][GET_MODE (copy_reg)]; | |
610d2478 SB |
371 | |
372 | /* If the return register is not likely spilled, - as is | |
373 | the case for floating point on SH4 - then it might | |
374 | be set by an arithmetic operation that needs a | |
375 | different mode than the exit block. */ | |
376 | for (j = n_entities - 1; j >= 0; j--) | |
377 | { | |
378 | int e = entity_map[j]; | |
06b90602 CB |
379 | int mode = |
380 | targetm.mode_switching.needed (e, return_copy); | |
610d2478 | 381 | |
06b90602 CB |
382 | if (mode != num_modes[e] |
383 | && mode != targetm.mode_switching.exit (e)) | |
610d2478 SB |
384 | break; |
385 | } | |
386 | if (j >= 0) | |
387 | { | |
b8435aa9 UB |
388 | /* __builtin_return emits a sequence of loads to all |
389 | return registers. One of them might require | |
390 | another mode than MODE_EXIT, even if it is | |
391 | unrelated to the return value, so we want to put | |
392 | the final mode switch after it. */ | |
c07757e5 | 393 | if (multi_reg_return |
b8435aa9 UB |
394 | && targetm.calls.function_value_regno_p |
395 | (copy_start)) | |
c07757e5 | 396 | forced_late_switch = true; |
b8435aa9 | 397 | |
610d2478 SB |
398 | /* For the SH4, floating point loads depend on fpscr, |
399 | thus we might need to put the final mode switch | |
400 | after the return value copy. That is still OK, | |
401 | because a floating point return value does not | |
402 | conflict with address reloads. */ | |
403 | if (copy_start >= ret_start | |
404 | && copy_start + copy_num <= ret_end | |
405 | && OBJECT_P (SET_SRC (return_copy_pat))) | |
c07757e5 | 406 | forced_late_switch = true; |
610d2478 SB |
407 | break; |
408 | } | |
ce4a9422 JR |
409 | if (copy_num == 0) |
410 | { | |
411 | last_insn = return_copy; | |
412 | continue; | |
413 | } | |
610d2478 SB |
414 | |
415 | if (copy_start >= ret_start | |
416 | && copy_start + copy_num <= ret_end) | |
417 | nregs -= copy_num; | |
c07757e5 | 418 | else if (!multi_reg_return |
82f81f18 AS |
419 | || !targetm.calls.function_value_regno_p |
420 | (copy_start)) | |
610d2478 SB |
421 | break; |
422 | last_insn = return_copy; | |
423 | } | |
424 | /* ??? Exception handling can lead to the return value | |
425 | copy being already separated from the return value use, | |
426 | as in unwind-dw2.c . | |
427 | Similarly, conditionally returning without a value, | |
428 | and conditionally using builtin_return can lead to an | |
429 | isolated use. */ | |
430 | if (return_copy == BB_HEAD (src_bb)) | |
431 | { | |
c07757e5 | 432 | short_block = true; |
610d2478 SB |
433 | break; |
434 | } | |
435 | last_insn = return_copy; | |
436 | } | |
437 | while (nregs); | |
b8698a0f | 438 | |
610d2478 SB |
439 | /* If we didn't see a full return value copy, verify that there |
440 | is a plausible reason for this. If some, but not all of the | |
441 | return register is likely spilled, we can expect that there | |
442 | is a copy for the likely spilled part. */ | |
443 | gcc_assert (!nregs | |
444 | || forced_late_switch | |
445 | || short_block | |
07b8f0a8 | 446 | || !(targetm.class_likely_spilled_p |
610d2478 SB |
447 | (REGNO_REG_CLASS (ret_start))) |
448 | || (nregs | |
449 | != hard_regno_nregs[ret_start][GET_MODE (ret_reg)]) | |
450 | /* For multi-hard-register floating point | |
451 | values, sometimes the likely-spilled part | |
452 | is ordinarily copied first, then the other | |
453 | part is set with an arithmetic operation. | |
454 | This doesn't actually cause reload | |
455 | failures, so let it pass. */ | |
456 | || (GET_MODE_CLASS (GET_MODE (ret_reg)) != MODE_INT | |
457 | && nregs != 1)); | |
b8698a0f | 458 | |
bba33211 | 459 | if (!NOTE_INSN_BASIC_BLOCK_P (last_insn)) |
610d2478 SB |
460 | { |
461 | before_return_copy | |
462 | = emit_note_before (NOTE_INSN_DELETED, last_insn); | |
463 | /* Instructions preceding LAST_INSN in the same block might | |
464 | require a different mode than MODE_EXIT, so if we might | |
465 | have such instructions, keep them in a separate block | |
466 | from pre_exit. */ | |
bba33211 JR |
467 | src_bb = split_block (src_bb, |
468 | PREV_INSN (before_return_copy))->dest; | |
610d2478 SB |
469 | } |
470 | else | |
471 | before_return_copy = last_insn; | |
472 | pre_exit = split_block (src_bb, before_return_copy)->src; | |
473 | } | |
474 | else | |
475 | { | |
476 | pre_exit = split_edge (eg); | |
610d2478 SB |
477 | } |
478 | } | |
479 | ||
480 | return pre_exit; | |
481 | } | |
610d2478 SB |
482 | |
483 | /* Find all insns that need a particular mode setting, and insert the | |
484 | necessary mode switches. Return true if we did work. */ | |
485 | ||
7399bcb0 | 486 | static int |
10d22567 | 487 | optimize_mode_switching (void) |
610d2478 | 488 | { |
610d2478 SB |
489 | int e; |
490 | basic_block bb; | |
cbb1e3d9 | 491 | bool need_commit = false; |
610d2478 SB |
492 | static const int num_modes[] = NUM_MODES_FOR_MODE_SWITCHING; |
493 | #define N_ENTITIES ARRAY_SIZE (num_modes) | |
494 | int entity_map[N_ENTITIES]; | |
495 | struct bb_info *bb_info[N_ENTITIES]; | |
496 | int i, j; | |
cbb1e3d9 | 497 | int n_entities = 0; |
610d2478 | 498 | int max_num_modes = 0; |
073a8998 | 499 | bool emitted ATTRIBUTE_UNUSED = false; |
06b90602 CB |
500 | basic_block post_entry = 0; |
501 | basic_block pre_exit = 0; | |
cbb1e3d9 CB |
502 | struct edge_list *edge_list = 0; |
503 | ||
504 | /* These bitmaps are used for the LCM algorithm. */ | |
505 | sbitmap *kill, *del, *insert, *antic, *transp, *comp; | |
506 | sbitmap *avin, *avout; | |
610d2478 | 507 | |
cbb1e3d9 | 508 | for (e = N_ENTITIES - 1; e >= 0; e--) |
610d2478 SB |
509 | if (OPTIMIZE_MODE_SWITCHING (e)) |
510 | { | |
511 | int entry_exit_extra = 0; | |
512 | ||
513 | /* Create the list of segments within each basic block. | |
514 | If NORMAL_MODE is defined, allow for two extra | |
515 | blocks split from the entry and exit block. */ | |
06b90602 CB |
516 | if (targetm.mode_switching.entry && targetm.mode_switching.exit) |
517 | entry_exit_extra = 3; | |
518 | ||
610d2478 | 519 | bb_info[n_entities] |
8b1c6fd7 DM |
520 | = XCNEWVEC (struct bb_info, |
521 | last_basic_block_for_fn (cfun) + entry_exit_extra); | |
610d2478 SB |
522 | entity_map[n_entities++] = e; |
523 | if (num_modes[e] > max_num_modes) | |
524 | max_num_modes = num_modes[e]; | |
525 | } | |
526 | ||
527 | if (! n_entities) | |
528 | return 0; | |
529 | ||
cbb1e3d9 | 530 | /* Make sure if MODE_ENTRY is defined MODE_EXIT is defined. */ |
06b90602 | 531 | gcc_assert ((targetm.mode_switching.entry && targetm.mode_switching.exit) |
cbb1e3d9 CB |
532 | || (!targetm.mode_switching.entry |
533 | && !targetm.mode_switching.exit)); | |
06b90602 CB |
534 | |
535 | if (targetm.mode_switching.entry && targetm.mode_switching.exit) | |
536 | { | |
537 | /* Split the edge from the entry block, so that we can note that | |
538 | there NORMAL_MODE is supplied. */ | |
539 | post_entry = split_edge (single_succ_edge (ENTRY_BLOCK_PTR_FOR_FN (cfun))); | |
540 | pre_exit = create_pre_exit (n_entities, entity_map, num_modes); | |
541 | } | |
610d2478 | 542 | |
6fb5fa3c DB |
543 | df_analyze (); |
544 | ||
610d2478 | 545 | /* Create the bitmap vectors. */ |
cbb1e3d9 CB |
546 | antic = sbitmap_vector_alloc (last_basic_block_for_fn (cfun), |
547 | n_entities * max_num_modes); | |
548 | transp = sbitmap_vector_alloc (last_basic_block_for_fn (cfun), | |
549 | n_entities * max_num_modes); | |
550 | comp = sbitmap_vector_alloc (last_basic_block_for_fn (cfun), | |
551 | n_entities * max_num_modes); | |
552 | avin = sbitmap_vector_alloc (last_basic_block_for_fn (cfun), | |
553 | n_entities * max_num_modes); | |
554 | avout = sbitmap_vector_alloc (last_basic_block_for_fn (cfun), | |
555 | n_entities * max_num_modes); | |
556 | kill = sbitmap_vector_alloc (last_basic_block_for_fn (cfun), | |
557 | n_entities * max_num_modes); | |
610d2478 | 558 | |
8b1c6fd7 | 559 | bitmap_vector_ones (transp, last_basic_block_for_fn (cfun)); |
cbb1e3d9 CB |
560 | bitmap_vector_clear (antic, last_basic_block_for_fn (cfun)); |
561 | bitmap_vector_clear (comp, last_basic_block_for_fn (cfun)); | |
610d2478 SB |
562 | |
563 | for (j = n_entities - 1; j >= 0; j--) | |
564 | { | |
565 | int e = entity_map[j]; | |
566 | int no_mode = num_modes[e]; | |
567 | struct bb_info *info = bb_info[j]; | |
1d455520 | 568 | rtx_insn *insn; |
610d2478 SB |
569 | |
570 | /* Determine what the first use (if any) need for a mode of entity E is. | |
571 | This will be the mode that is anticipatable for this block. | |
572 | Also compute the initial transparency settings. */ | |
11cd3bed | 573 | FOR_EACH_BB_FN (bb, cfun) |
610d2478 SB |
574 | { |
575 | struct seginfo *ptr; | |
576 | int last_mode = no_mode; | |
a44250f4 | 577 | bool any_set_required = false; |
610d2478 SB |
578 | HARD_REG_SET live_now; |
579 | ||
cbb1e3d9 CB |
580 | info[bb->index].mode_out = info[bb->index].mode_in = no_mode; |
581 | ||
6fb5fa3c | 582 | REG_SET_TO_HARD_REG_SET (live_now, df_get_live_in (bb)); |
24c2fde2 RH |
583 | |
584 | /* Pretend the mode is clobbered across abnormal edges. */ | |
585 | { | |
586 | edge_iterator ei; | |
cbb1e3d9 CB |
587 | edge eg; |
588 | FOR_EACH_EDGE (eg, ei, bb->preds) | |
589 | if (eg->flags & EDGE_COMPLEX) | |
24c2fde2 | 590 | break; |
cbb1e3d9 | 591 | if (eg) |
650a59ef | 592 | { |
1d455520 | 593 | rtx_insn *ins_pos = BB_HEAD (bb); |
473fd99a JR |
594 | if (LABEL_P (ins_pos)) |
595 | ins_pos = NEXT_INSN (ins_pos); | |
596 | gcc_assert (NOTE_INSN_BASIC_BLOCK_P (ins_pos)); | |
597 | if (ins_pos != BB_END (bb)) | |
598 | ins_pos = NEXT_INSN (ins_pos); | |
599 | ptr = new_seginfo (no_mode, ins_pos, bb->index, live_now); | |
650a59ef | 600 | add_seginfo (info + bb->index, ptr); |
cbb1e3d9 CB |
601 | for (i = 0; i < no_mode; i++) |
602 | clear_mode_bit (transp[bb->index], j, i); | |
650a59ef | 603 | } |
24c2fde2 RH |
604 | } |
605 | ||
0f346928 | 606 | FOR_BB_INSNS (bb, insn) |
610d2478 SB |
607 | { |
608 | if (INSN_P (insn)) | |
609 | { | |
06b90602 | 610 | int mode = targetm.mode_switching.needed (e, insn); |
610d2478 SB |
611 | rtx link; |
612 | ||
613 | if (mode != no_mode && mode != last_mode) | |
614 | { | |
a44250f4 | 615 | any_set_required = true; |
610d2478 SB |
616 | last_mode = mode; |
617 | ptr = new_seginfo (mode, insn, bb->index, live_now); | |
618 | add_seginfo (info + bb->index, ptr); | |
cbb1e3d9 CB |
619 | for (i = 0; i < no_mode; i++) |
620 | clear_mode_bit (transp[bb->index], j, i); | |
610d2478 | 621 | } |
06b90602 CB |
622 | |
623 | if (targetm.mode_switching.after) | |
cbb1e3d9 CB |
624 | last_mode = targetm.mode_switching.after (e, last_mode, |
625 | insn); | |
06b90602 | 626 | |
610d2478 SB |
627 | /* Update LIVE_NOW. */ |
628 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | |
629 | if (REG_NOTE_KIND (link) == REG_DEAD) | |
408bed3c | 630 | reg_dies (XEXP (link, 0), &live_now); |
610d2478 SB |
631 | |
632 | note_stores (PATTERN (insn), reg_becomes_live, &live_now); | |
633 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | |
634 | if (REG_NOTE_KIND (link) == REG_UNUSED) | |
408bed3c | 635 | reg_dies (XEXP (link, 0), &live_now); |
610d2478 SB |
636 | } |
637 | } | |
638 | ||
639 | info[bb->index].computing = last_mode; | |
a44250f4 | 640 | /* Check for blocks without ANY mode requirements. |
611a4849 UB |
641 | N.B. because of MODE_AFTER, last_mode might still |
642 | be different from no_mode, in which case we need to | |
643 | mark the block as nontransparent. */ | |
a44250f4 | 644 | if (!any_set_required) |
610d2478 SB |
645 | { |
646 | ptr = new_seginfo (no_mode, BB_END (bb), bb->index, live_now); | |
647 | add_seginfo (info + bb->index, ptr); | |
611a4849 | 648 | if (last_mode != no_mode) |
cbb1e3d9 CB |
649 | for (i = 0; i < no_mode; i++) |
650 | clear_mode_bit (transp[bb->index], j, i); | |
610d2478 SB |
651 | } |
652 | } | |
06b90602 CB |
653 | if (targetm.mode_switching.entry && targetm.mode_switching.exit) |
654 | { | |
655 | int mode = targetm.mode_switching.entry (e); | |
610d2478 | 656 | |
cbb1e3d9 CB |
657 | info[post_entry->index].mode_out = |
658 | info[post_entry->index].mode_in = no_mode; | |
659 | if (pre_exit) | |
660 | { | |
661 | info[pre_exit->index].mode_out = | |
662 | info[pre_exit->index].mode_in = no_mode; | |
663 | } | |
664 | ||
06b90602 CB |
665 | if (mode != no_mode) |
666 | { | |
667 | bb = post_entry; | |
668 | ||
669 | /* By always making this nontransparent, we save | |
670 | an extra check in make_preds_opaque. We also | |
671 | need this to avoid confusing pre_edge_lcm when | |
672 | antic is cleared but transp and comp are set. */ | |
cbb1e3d9 CB |
673 | for (i = 0; i < no_mode; i++) |
674 | clear_mode_bit (transp[bb->index], j, i); | |
06b90602 CB |
675 | |
676 | /* Insert a fake computing definition of MODE into entry | |
677 | blocks which compute no mode. This represents the mode on | |
678 | entry. */ | |
679 | info[bb->index].computing = mode; | |
680 | ||
681 | if (pre_exit) | |
682 | info[pre_exit->index].seginfo->mode = | |
683 | targetm.mode_switching.exit (e); | |
684 | } | |
685 | } | |
610d2478 SB |
686 | |
687 | /* Set the anticipatable and computing arrays. */ | |
cbb1e3d9 | 688 | for (i = 0; i < no_mode; i++) |
610d2478 | 689 | { |
cbb1e3d9 | 690 | int m = targetm.mode_switching.priority (entity_map[j], i); |
610d2478 | 691 | |
11cd3bed | 692 | FOR_EACH_BB_FN (bb, cfun) |
610d2478 SB |
693 | { |
694 | if (info[bb->index].seginfo->mode == m) | |
cbb1e3d9 | 695 | set_mode_bit (antic[bb->index], j, m); |
610d2478 SB |
696 | |
697 | if (info[bb->index].computing == m) | |
cbb1e3d9 | 698 | set_mode_bit (comp[bb->index], j, m); |
610d2478 SB |
699 | } |
700 | } | |
cbb1e3d9 | 701 | } |
610d2478 | 702 | |
cbb1e3d9 CB |
703 | /* Calculate the optimal locations for the |
704 | placement mode switches to modes with priority I. */ | |
610d2478 | 705 | |
cbb1e3d9 CB |
706 | FOR_EACH_BB_FN (bb, cfun) |
707 | bitmap_not (kill[bb->index], transp[bb->index]); | |
610d2478 | 708 | |
cbb1e3d9 CB |
709 | edge_list = pre_edge_lcm_avs (n_entities * max_num_modes, transp, comp, antic, |
710 | kill, avin, avout, &insert, &del); | |
610d2478 | 711 | |
cbb1e3d9 CB |
712 | for (j = n_entities - 1; j >= 0; j--) |
713 | { | |
714 | int no_mode = num_modes[entity_map[j]]; | |
610d2478 | 715 | |
cbb1e3d9 | 716 | /* Insert all mode sets that have been inserted by lcm. */ |
610d2478 | 717 | |
cbb1e3d9 CB |
718 | for (int ed = NUM_EDGES (edge_list) - 1; ed >= 0; ed--) |
719 | { | |
720 | edge eg = INDEX_EDGE (edge_list, ed); | |
610d2478 | 721 | |
cbb1e3d9 | 722 | eg->aux = (void *)(intptr_t)-1; |
610d2478 | 723 | |
cbb1e3d9 CB |
724 | for (i = 0; i < no_mode; i++) |
725 | { | |
726 | int m = targetm.mode_switching.priority (entity_map[j], i); | |
727 | if (mode_bit_p (insert[ed], j, m)) | |
728 | { | |
729 | eg->aux = (void *)(intptr_t)m; | |
730 | break; | |
731 | } | |
732 | } | |
733 | } | |
610d2478 | 734 | |
cbb1e3d9 CB |
735 | FOR_EACH_BB_FN (bb, cfun) |
736 | { | |
737 | struct bb_info *info = bb_info[j]; | |
738 | int last_mode = no_mode; | |
650a59ef | 739 | |
cbb1e3d9 CB |
740 | /* intialize mode in availability for bb. */ |
741 | for (i = 0; i < no_mode; i++) | |
742 | if (mode_bit_p (avout[bb->index], j, i)) | |
743 | { | |
744 | if (last_mode == no_mode) | |
745 | last_mode = i; | |
746 | if (last_mode != i) | |
747 | { | |
748 | last_mode = no_mode; | |
749 | break; | |
750 | } | |
751 | } | |
752 | info[bb->index].mode_out = last_mode; | |
610d2478 | 753 | |
cbb1e3d9 CB |
754 | /* intialize mode out availability for bb. */ |
755 | last_mode = no_mode; | |
756 | for (i = 0; i < no_mode; i++) | |
757 | if (mode_bit_p (avin[bb->index], j, i)) | |
610d2478 | 758 | { |
cbb1e3d9 CB |
759 | if (last_mode == no_mode) |
760 | last_mode = i; | |
761 | if (last_mode != i) | |
762 | { | |
763 | last_mode = no_mode; | |
764 | break; | |
765 | } | |
610d2478 | 766 | } |
cbb1e3d9 CB |
767 | info[bb->index].mode_in = last_mode; |
768 | ||
769 | for (i = 0; i < no_mode; i++) | |
770 | if (mode_bit_p (del[bb->index], j, i)) | |
771 | info[bb->index].seginfo->mode = no_mode; | |
610d2478 SB |
772 | } |
773 | ||
cbb1e3d9 | 774 | /* Now output the remaining mode sets in all the segments. */ |
610d2478 | 775 | |
cbb1e3d9 CB |
776 | /* In case there was no mode inserted. the mode information on the edge |
777 | might not be complete. | |
778 | Update mode info on edges and commit pending mode sets. */ | |
779 | need_commit |= commit_mode_sets (edge_list, entity_map[j], bb_info[j]); | |
780 | ||
781 | /* Reset modes for next entity. */ | |
782 | clear_aux_for_edges (); | |
610d2478 | 783 | |
cbb1e3d9 | 784 | FOR_EACH_BB_FN (bb, cfun) |
610d2478 SB |
785 | { |
786 | struct seginfo *ptr, *next; | |
cbb1e3d9 CB |
787 | int cur_mode = bb_info[j][bb->index].mode_in; |
788 | ||
610d2478 SB |
789 | for (ptr = bb_info[j][bb->index].seginfo; ptr; ptr = next) |
790 | { | |
791 | next = ptr->next; | |
792 | if (ptr->mode != no_mode) | |
793 | { | |
1d455520 | 794 | rtx_insn *mode_set; |
610d2478 | 795 | |
5f28524a | 796 | rtl_profile_for_bb (bb); |
610d2478 | 797 | start_sequence (); |
cbb1e3d9 CB |
798 | |
799 | targetm.mode_switching.emit (entity_map[j], ptr->mode, | |
800 | cur_mode, ptr->regs_live); | |
610d2478 SB |
801 | mode_set = get_insns (); |
802 | end_sequence (); | |
803 | ||
cbb1e3d9 CB |
804 | /* modes kill each other inside a basic block. */ |
805 | cur_mode = ptr->mode; | |
806 | ||
610d2478 SB |
807 | /* Insert MODE_SET only if it is nonempty. */ |
808 | if (mode_set != NULL_RTX) | |
809 | { | |
073a8998 | 810 | emitted = true; |
a38e7aa5 | 811 | if (NOTE_INSN_BASIC_BLOCK_P (ptr->insn_ptr)) |
473fd99a JR |
812 | /* We need to emit the insns in a FIFO-like manner, |
813 | i.e. the first to be emitted at our insertion | |
814 | point ends up first in the instruction steam. | |
815 | Because we made sure that NOTE_INSN_BASIC_BLOCK is | |
816 | only used for initially empty basic blocks, we | |
74145685 | 817 | can achieve this by appending at the end of |
473fd99a JR |
818 | the block. */ |
819 | emit_insn_after | |
820 | (mode_set, BB_END (NOTE_BASIC_BLOCK (ptr->insn_ptr))); | |
610d2478 SB |
821 | else |
822 | emit_insn_before (mode_set, ptr->insn_ptr); | |
823 | } | |
5f28524a JH |
824 | |
825 | default_rtl_profile (); | |
610d2478 SB |
826 | } |
827 | ||
828 | free (ptr); | |
829 | } | |
830 | } | |
831 | ||
832 | free (bb_info[j]); | |
833 | } | |
834 | ||
cbb1e3d9 CB |
835 | free_edge_list (edge_list); |
836 | ||
610d2478 | 837 | /* Finished. Free up all the things we've allocated. */ |
cbb1e3d9 CB |
838 | sbitmap_vector_free (del); |
839 | sbitmap_vector_free (insert); | |
610d2478 SB |
840 | sbitmap_vector_free (kill); |
841 | sbitmap_vector_free (antic); | |
842 | sbitmap_vector_free (transp); | |
843 | sbitmap_vector_free (comp); | |
cbb1e3d9 CB |
844 | sbitmap_vector_free (avin); |
845 | sbitmap_vector_free (avout); | |
610d2478 SB |
846 | |
847 | if (need_commit) | |
848 | commit_edge_insertions (); | |
849 | ||
06b90602 CB |
850 | if (targetm.mode_switching.entry && targetm.mode_switching.exit) |
851 | cleanup_cfg (CLEANUP_NO_INSN_DEL); | |
852 | else if (!need_commit && !emitted) | |
610d2478 | 853 | return 0; |
610d2478 | 854 | |
610d2478 SB |
855 | return 1; |
856 | } | |
ef330312 | 857 | |
610d2478 | 858 | #endif /* OPTIMIZE_MODE_SWITCHING */ |
ef330312 | 859 | \f |
27a4cd48 DM |
860 | namespace { |
861 | ||
862 | const pass_data pass_data_mode_switching = | |
ef330312 | 863 | { |
27a4cd48 DM |
864 | RTL_PASS, /* type */ |
865 | "mode_sw", /* name */ | |
866 | OPTGROUP_NONE, /* optinfo_flags */ | |
27a4cd48 DM |
867 | TV_MODE_SWITCH, /* tv_id */ |
868 | 0, /* properties_required */ | |
869 | 0, /* properties_provided */ | |
870 | 0, /* properties_destroyed */ | |
871 | 0, /* todo_flags_start */ | |
3bea341f | 872 | TODO_df_finish, /* todo_flags_finish */ |
ef330312 | 873 | }; |
27a4cd48 DM |
874 | |
875 | class pass_mode_switching : public rtl_opt_pass | |
876 | { | |
877 | public: | |
c3284718 RS |
878 | pass_mode_switching (gcc::context *ctxt) |
879 | : rtl_opt_pass (pass_data_mode_switching, ctxt) | |
27a4cd48 DM |
880 | {} |
881 | ||
882 | /* opt_pass methods: */ | |
05555c4a DM |
883 | /* The epiphany backend creates a second instance of this pass, so we need |
884 | a clone method. */ | |
65d3284b | 885 | opt_pass * clone () { return new pass_mode_switching (m_ctxt); } |
1a3d085c TS |
886 | virtual bool gate (function *) |
887 | { | |
888 | #ifdef OPTIMIZE_MODE_SWITCHING | |
889 | return true; | |
890 | #else | |
891 | return false; | |
892 | #endif | |
893 | } | |
894 | ||
be55bfe6 TS |
895 | virtual unsigned int execute (function *) |
896 | { | |
897 | #ifdef OPTIMIZE_MODE_SWITCHING | |
898 | optimize_mode_switching (); | |
899 | #endif /* OPTIMIZE_MODE_SWITCHING */ | |
900 | return 0; | |
901 | } | |
27a4cd48 DM |
902 | |
903 | }; // class pass_mode_switching | |
904 | ||
905 | } // anon namespace | |
906 | ||
907 | rtl_opt_pass * | |
908 | make_pass_mode_switching (gcc::context *ctxt) | |
909 | { | |
910 | return new pass_mode_switching (ctxt); | |
911 | } |