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2f138c1c | 1 | /* CPU mode switching |
cfaf579d | 2 | Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008, |
168ae443 | 3 | 2009, 2010 Free Software Foundation, Inc. |
2f138c1c | 4 | |
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it under | |
8 | the terms of the GNU General Public License as published by the Free | |
8c4c00c1 | 9 | Software Foundation; either version 3, or (at your option) any later |
2f138c1c | 10 | version. |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
8c4c00c1 | 18 | along with GCC; see the file COPYING3. If not see |
19 | <http://www.gnu.org/licenses/>. */ | |
2f138c1c | 20 | |
21 | #include "config.h" | |
22 | #include "system.h" | |
23 | #include "coretypes.h" | |
24 | #include "tm.h" | |
e1ce1485 | 25 | #include "target.h" |
2f138c1c | 26 | #include "rtl.h" |
27 | #include "regs.h" | |
28 | #include "hard-reg-set.h" | |
29 | #include "flags.h" | |
2f138c1c | 30 | #include "insn-config.h" |
31 | #include "recog.h" | |
32 | #include "basic-block.h" | |
2f138c1c | 33 | #include "tm_p.h" |
34 | #include "function.h" | |
77fce4cd | 35 | #include "tree-pass.h" |
3072d30e | 36 | #include "df.h" |
06f9d6ef | 37 | #include "emit-rtl.h" |
2f138c1c | 38 | |
39 | /* We want target macros for the mode switching code to be able to refer | |
40 | to instruction attribute values. */ | |
41 | #include "insn-attr.h" | |
42 | ||
43 | #ifdef OPTIMIZE_MODE_SWITCHING | |
44 | ||
45 | /* The algorithm for setting the modes consists of scanning the insn list | |
46 | and finding all the insns which require a specific mode. Each insn gets | |
47 | a unique struct seginfo element. These structures are inserted into a list | |
48 | for each basic block. For each entity, there is an array of bb_info over | |
49 | the flow graph basic blocks (local var 'bb_info'), and contains a list | |
50 | of all insns within that basic block, in the order they are encountered. | |
51 | ||
52 | For each entity, any basic block WITHOUT any insns requiring a specific | |
53 | mode are given a single entry, without a mode. (Each basic block | |
54 | in the flow graph must have at least one entry in the segment table.) | |
55 | ||
56 | The LCM algorithm is then run over the flow graph to determine where to | |
57 | place the sets to the highest-priority value in respect of first the first | |
58 | insn in any one block. Any adjustments required to the transparency | |
59 | vectors are made, then the next iteration starts for the next-lower | |
60 | priority mode, till for each entity all modes are exhausted. | |
61 | ||
62 | More details are located in the code for optimize_mode_switching(). */ | |
63 | \f | |
64 | /* This structure contains the information for each insn which requires | |
65 | either single or double mode to be set. | |
66 | MODE is the mode this insn must be executed in. | |
67 | INSN_PTR is the insn to be executed (may be the note that marks the | |
68 | beginning of a basic block). | |
69 | BBNUM is the flow graph basic block this insn occurs in. | |
70 | NEXT is the next insn in the same basic block. */ | |
71 | struct seginfo | |
72 | { | |
73 | int mode; | |
74 | rtx insn_ptr; | |
75 | int bbnum; | |
76 | struct seginfo *next; | |
77 | HARD_REG_SET regs_live; | |
78 | }; | |
79 | ||
80 | struct bb_info | |
81 | { | |
82 | struct seginfo *seginfo; | |
83 | int computing; | |
84 | }; | |
85 | ||
86 | /* These bitmaps are used for the LCM algorithm. */ | |
87 | ||
88 | static sbitmap *antic; | |
89 | static sbitmap *transp; | |
90 | static sbitmap *comp; | |
91 | ||
92 | static struct seginfo * new_seginfo (int, rtx, int, HARD_REG_SET); | |
93 | static void add_seginfo (struct bb_info *, struct seginfo *); | |
0ff4fe1d | 94 | static void reg_dies (rtx, HARD_REG_SET *); |
81a410b1 | 95 | static void reg_becomes_live (rtx, const_rtx, void *); |
2f138c1c | 96 | static void make_preds_opaque (basic_block, int); |
97 | \f | |
98 | ||
99 | /* This function will allocate a new BBINFO structure, initialized | |
100 | with the MODE, INSN, and basic block BB parameters. */ | |
101 | ||
102 | static struct seginfo * | |
103 | new_seginfo (int mode, rtx insn, int bb, HARD_REG_SET regs_live) | |
104 | { | |
105 | struct seginfo *ptr; | |
4c36ffe6 | 106 | ptr = XNEW (struct seginfo); |
2f138c1c | 107 | ptr->mode = mode; |
108 | ptr->insn_ptr = insn; | |
109 | ptr->bbnum = bb; | |
110 | ptr->next = NULL; | |
111 | COPY_HARD_REG_SET (ptr->regs_live, regs_live); | |
112 | return ptr; | |
113 | } | |
114 | ||
115 | /* Add a seginfo element to the end of a list. | |
116 | HEAD is a pointer to the list beginning. | |
117 | INFO is the structure to be linked in. */ | |
118 | ||
119 | static void | |
120 | add_seginfo (struct bb_info *head, struct seginfo *info) | |
121 | { | |
122 | struct seginfo *ptr; | |
123 | ||
124 | if (head->seginfo == NULL) | |
125 | head->seginfo = info; | |
126 | else | |
127 | { | |
128 | ptr = head->seginfo; | |
129 | while (ptr->next != NULL) | |
130 | ptr = ptr->next; | |
131 | ptr->next = info; | |
132 | } | |
133 | } | |
134 | ||
135 | /* Make all predecessors of basic block B opaque, recursively, till we hit | |
136 | some that are already non-transparent, or an edge where aux is set; that | |
137 | denotes that a mode set is to be done on that edge. | |
138 | J is the bit number in the bitmaps that corresponds to the entity that | |
139 | we are currently handling mode-switching for. */ | |
140 | ||
141 | static void | |
142 | make_preds_opaque (basic_block b, int j) | |
143 | { | |
144 | edge e; | |
145 | edge_iterator ei; | |
146 | ||
147 | FOR_EACH_EDGE (e, ei, b->preds) | |
148 | { | |
149 | basic_block pb = e->src; | |
150 | ||
08b7917c | 151 | if (e->aux || ! bitmap_bit_p (transp[pb->index], j)) |
2f138c1c | 152 | continue; |
153 | ||
08b7917c | 154 | bitmap_clear_bit (transp[pb->index], j); |
2f138c1c | 155 | make_preds_opaque (pb, j); |
156 | } | |
157 | } | |
158 | ||
159 | /* Record in LIVE that register REG died. */ | |
160 | ||
161 | static void | |
0ff4fe1d | 162 | reg_dies (rtx reg, HARD_REG_SET *live) |
2f138c1c | 163 | { |
a2c6f0b7 | 164 | int regno; |
2f138c1c | 165 | |
166 | if (!REG_P (reg)) | |
167 | return; | |
168 | ||
169 | regno = REGNO (reg); | |
170 | if (regno < FIRST_PSEUDO_REGISTER) | |
a2c6f0b7 | 171 | remove_from_hard_reg_set (live, GET_MODE (reg), regno); |
2f138c1c | 172 | } |
173 | ||
174 | /* Record in LIVE that register REG became live. | |
175 | This is called via note_stores. */ | |
176 | ||
177 | static void | |
81a410b1 | 178 | reg_becomes_live (rtx reg, const_rtx setter ATTRIBUTE_UNUSED, void *live) |
2f138c1c | 179 | { |
a2c6f0b7 | 180 | int regno; |
2f138c1c | 181 | |
182 | if (GET_CODE (reg) == SUBREG) | |
183 | reg = SUBREG_REG (reg); | |
184 | ||
185 | if (!REG_P (reg)) | |
186 | return; | |
187 | ||
188 | regno = REGNO (reg); | |
189 | if (regno < FIRST_PSEUDO_REGISTER) | |
a2c6f0b7 | 190 | add_to_hard_reg_set ((HARD_REG_SET *) live, GET_MODE (reg), regno); |
2f138c1c | 191 | } |
192 | ||
193 | /* Make sure if MODE_ENTRY is defined the MODE_EXIT is defined | |
194 | and vice versa. */ | |
195 | #if defined (MODE_ENTRY) != defined (MODE_EXIT) | |
196 | #error "Both MODE_ENTRY and MODE_EXIT must be defined" | |
197 | #endif | |
198 | ||
199 | #if defined (MODE_ENTRY) && defined (MODE_EXIT) | |
200 | /* Split the fallthrough edge to the exit block, so that we can note | |
201 | that there NORMAL_MODE is required. Return the new block if it's | |
202 | inserted before the exit block. Otherwise return null. */ | |
203 | ||
204 | static basic_block | |
205 | create_pre_exit (int n_entities, int *entity_map, const int *num_modes) | |
206 | { | |
207 | edge eg; | |
208 | edge_iterator ei; | |
209 | basic_block pre_exit; | |
210 | ||
211 | /* The only non-call predecessor at this stage is a block with a | |
212 | fallthrough edge; there can be at most one, but there could be | |
213 | none at all, e.g. when exit is called. */ | |
214 | pre_exit = 0; | |
215 | FOR_EACH_EDGE (eg, ei, EXIT_BLOCK_PTR->preds) | |
216 | if (eg->flags & EDGE_FALLTHRU) | |
217 | { | |
218 | basic_block src_bb = eg->src; | |
2f138c1c | 219 | rtx last_insn, ret_reg; |
220 | ||
221 | gcc_assert (!pre_exit); | |
222 | /* If this function returns a value at the end, we have to | |
223 | insert the final mode switch before the return value copy | |
224 | to its hard register. */ | |
225 | if (EDGE_COUNT (EXIT_BLOCK_PTR->preds) == 1 | |
226 | && NONJUMP_INSN_P ((last_insn = BB_END (src_bb))) | |
227 | && GET_CODE (PATTERN (last_insn)) == USE | |
228 | && GET_CODE ((ret_reg = XEXP (PATTERN (last_insn), 0))) == REG) | |
229 | { | |
230 | int ret_start = REGNO (ret_reg); | |
231 | int nregs = hard_regno_nregs[ret_start][GET_MODE (ret_reg)]; | |
232 | int ret_end = ret_start + nregs; | |
233 | int short_block = 0; | |
234 | int maybe_builtin_apply = 0; | |
235 | int forced_late_switch = 0; | |
236 | rtx before_return_copy; | |
237 | ||
238 | do | |
239 | { | |
240 | rtx return_copy = PREV_INSN (last_insn); | |
241 | rtx return_copy_pat, copy_reg; | |
242 | int copy_start, copy_num; | |
243 | int j; | |
244 | ||
245 | if (INSN_P (return_copy)) | |
246 | { | |
1915b15f | 247 | /* When using SJLJ exceptions, the call to the |
248 | unregister function is inserted between the | |
249 | clobber of the return value and the copy. | |
250 | We do not want to split the block before this | |
251 | or any other call; if we have not found the | |
252 | copy yet, the copy must have been deleted. */ | |
253 | if (CALL_P (return_copy)) | |
254 | { | |
255 | short_block = 1; | |
256 | break; | |
257 | } | |
646857a5 | 258 | return_copy_pat = PATTERN (return_copy); |
259 | switch (GET_CODE (return_copy_pat)) | |
8801c4fd | 260 | { |
646857a5 | 261 | case USE: |
262 | /* Skip __builtin_apply pattern. */ | |
263 | if (GET_CODE (XEXP (return_copy_pat, 0)) == REG | |
e1ce1485 | 264 | && (targetm.calls.function_value_regno_p |
646857a5 | 265 | (REGNO (XEXP (return_copy_pat, 0))))) |
266 | { | |
267 | maybe_builtin_apply = 1; | |
268 | last_insn = return_copy; | |
269 | continue; | |
270 | } | |
271 | break; | |
272 | ||
273 | case ASM_OPERANDS: | |
274 | /* Skip barrier insns. */ | |
275 | if (!MEM_VOLATILE_P (return_copy_pat)) | |
276 | break; | |
277 | ||
278 | /* Fall through. */ | |
279 | ||
280 | case ASM_INPUT: | |
281 | case UNSPEC_VOLATILE: | |
8801c4fd | 282 | last_insn = return_copy; |
283 | continue; | |
646857a5 | 284 | |
285 | default: | |
286 | break; | |
8801c4fd | 287 | } |
646857a5 | 288 | |
2f138c1c | 289 | /* If the return register is not (in its entirety) |
290 | likely spilled, the return copy might be | |
291 | partially or completely optimized away. */ | |
292 | return_copy_pat = single_set (return_copy); | |
293 | if (!return_copy_pat) | |
294 | { | |
295 | return_copy_pat = PATTERN (return_copy); | |
296 | if (GET_CODE (return_copy_pat) != CLOBBER) | |
297 | break; | |
3072d30e | 298 | else if (!optimize) |
299 | { | |
300 | /* This might be (clobber (reg [<result>])) | |
301 | when not optimizing. Then check if | |
302 | the previous insn is the clobber for | |
303 | the return register. */ | |
304 | copy_reg = SET_DEST (return_copy_pat); | |
305 | if (GET_CODE (copy_reg) == REG | |
306 | && !HARD_REGISTER_NUM_P (REGNO (copy_reg))) | |
307 | { | |
308 | if (INSN_P (PREV_INSN (return_copy))) | |
309 | { | |
310 | return_copy = PREV_INSN (return_copy); | |
311 | return_copy_pat = PATTERN (return_copy); | |
312 | if (GET_CODE (return_copy_pat) != CLOBBER) | |
313 | break; | |
314 | } | |
315 | } | |
316 | } | |
2f138c1c | 317 | } |
318 | copy_reg = SET_DEST (return_copy_pat); | |
319 | if (GET_CODE (copy_reg) == REG) | |
320 | copy_start = REGNO (copy_reg); | |
321 | else if (GET_CODE (copy_reg) == SUBREG | |
322 | && GET_CODE (SUBREG_REG (copy_reg)) == REG) | |
323 | copy_start = REGNO (SUBREG_REG (copy_reg)); | |
324 | else | |
325 | break; | |
326 | if (copy_start >= FIRST_PSEUDO_REGISTER) | |
327 | break; | |
328 | copy_num | |
329 | = hard_regno_nregs[copy_start][GET_MODE (copy_reg)]; | |
330 | ||
331 | /* If the return register is not likely spilled, - as is | |
332 | the case for floating point on SH4 - then it might | |
333 | be set by an arithmetic operation that needs a | |
334 | different mode than the exit block. */ | |
335 | for (j = n_entities - 1; j >= 0; j--) | |
336 | { | |
337 | int e = entity_map[j]; | |
338 | int mode = MODE_NEEDED (e, return_copy); | |
339 | ||
340 | if (mode != num_modes[e] && mode != MODE_EXIT (e)) | |
341 | break; | |
342 | } | |
343 | if (j >= 0) | |
344 | { | |
345 | /* For the SH4, floating point loads depend on fpscr, | |
346 | thus we might need to put the final mode switch | |
347 | after the return value copy. That is still OK, | |
348 | because a floating point return value does not | |
349 | conflict with address reloads. */ | |
350 | if (copy_start >= ret_start | |
351 | && copy_start + copy_num <= ret_end | |
352 | && OBJECT_P (SET_SRC (return_copy_pat))) | |
353 | forced_late_switch = 1; | |
354 | break; | |
355 | } | |
356 | ||
357 | if (copy_start >= ret_start | |
358 | && copy_start + copy_num <= ret_end) | |
359 | nregs -= copy_num; | |
360 | else if (!maybe_builtin_apply | |
e1ce1485 | 361 | || !targetm.calls.function_value_regno_p |
362 | (copy_start)) | |
2f138c1c | 363 | break; |
364 | last_insn = return_copy; | |
365 | } | |
366 | /* ??? Exception handling can lead to the return value | |
367 | copy being already separated from the return value use, | |
368 | as in unwind-dw2.c . | |
369 | Similarly, conditionally returning without a value, | |
370 | and conditionally using builtin_return can lead to an | |
371 | isolated use. */ | |
372 | if (return_copy == BB_HEAD (src_bb)) | |
373 | { | |
374 | short_block = 1; | |
375 | break; | |
376 | } | |
377 | last_insn = return_copy; | |
378 | } | |
379 | while (nregs); | |
48e1416a | 380 | |
2f138c1c | 381 | /* If we didn't see a full return value copy, verify that there |
382 | is a plausible reason for this. If some, but not all of the | |
383 | return register is likely spilled, we can expect that there | |
384 | is a copy for the likely spilled part. */ | |
385 | gcc_assert (!nregs | |
386 | || forced_late_switch | |
387 | || short_block | |
24dd0668 | 388 | || !(targetm.class_likely_spilled_p |
2f138c1c | 389 | (REGNO_REG_CLASS (ret_start))) |
390 | || (nregs | |
391 | != hard_regno_nregs[ret_start][GET_MODE (ret_reg)]) | |
392 | /* For multi-hard-register floating point | |
393 | values, sometimes the likely-spilled part | |
394 | is ordinarily copied first, then the other | |
395 | part is set with an arithmetic operation. | |
396 | This doesn't actually cause reload | |
397 | failures, so let it pass. */ | |
398 | || (GET_MODE_CLASS (GET_MODE (ret_reg)) != MODE_INT | |
399 | && nregs != 1)); | |
48e1416a | 400 | |
2f138c1c | 401 | if (INSN_P (last_insn)) |
402 | { | |
403 | before_return_copy | |
404 | = emit_note_before (NOTE_INSN_DELETED, last_insn); | |
405 | /* Instructions preceding LAST_INSN in the same block might | |
406 | require a different mode than MODE_EXIT, so if we might | |
407 | have such instructions, keep them in a separate block | |
408 | from pre_exit. */ | |
409 | if (last_insn != BB_HEAD (src_bb)) | |
410 | src_bb = split_block (src_bb, | |
411 | PREV_INSN (before_return_copy))->dest; | |
412 | } | |
413 | else | |
414 | before_return_copy = last_insn; | |
415 | pre_exit = split_block (src_bb, before_return_copy)->src; | |
416 | } | |
417 | else | |
418 | { | |
419 | pre_exit = split_edge (eg); | |
2f138c1c | 420 | } |
421 | } | |
422 | ||
423 | return pre_exit; | |
424 | } | |
425 | #endif | |
426 | ||
427 | /* Find all insns that need a particular mode setting, and insert the | |
428 | necessary mode switches. Return true if we did work. */ | |
429 | ||
9d31a126 | 430 | static int |
3f5be5f4 | 431 | optimize_mode_switching (void) |
2f138c1c | 432 | { |
433 | rtx insn; | |
434 | int e; | |
435 | basic_block bb; | |
436 | int need_commit = 0; | |
437 | sbitmap *kill; | |
438 | struct edge_list *edge_list; | |
439 | static const int num_modes[] = NUM_MODES_FOR_MODE_SWITCHING; | |
440 | #define N_ENTITIES ARRAY_SIZE (num_modes) | |
441 | int entity_map[N_ENTITIES]; | |
442 | struct bb_info *bb_info[N_ENTITIES]; | |
443 | int i, j; | |
444 | int n_entities; | |
445 | int max_num_modes = 0; | |
9d75589a | 446 | bool emitted ATTRIBUTE_UNUSED = false; |
2f138c1c | 447 | basic_block post_entry ATTRIBUTE_UNUSED, pre_exit ATTRIBUTE_UNUSED; |
448 | ||
2f138c1c | 449 | for (e = N_ENTITIES - 1, n_entities = 0; e >= 0; e--) |
450 | if (OPTIMIZE_MODE_SWITCHING (e)) | |
451 | { | |
452 | int entry_exit_extra = 0; | |
453 | ||
454 | /* Create the list of segments within each basic block. | |
455 | If NORMAL_MODE is defined, allow for two extra | |
456 | blocks split from the entry and exit block. */ | |
457 | #if defined (MODE_ENTRY) && defined (MODE_EXIT) | |
458 | entry_exit_extra = 3; | |
459 | #endif | |
460 | bb_info[n_entities] | |
613768ea | 461 | = XCNEWVEC (struct bb_info, last_basic_block + entry_exit_extra); |
2f138c1c | 462 | entity_map[n_entities++] = e; |
463 | if (num_modes[e] > max_num_modes) | |
464 | max_num_modes = num_modes[e]; | |
465 | } | |
466 | ||
467 | if (! n_entities) | |
468 | return 0; | |
469 | ||
470 | #if defined (MODE_ENTRY) && defined (MODE_EXIT) | |
471 | /* Split the edge from the entry block, so that we can note that | |
472 | there NORMAL_MODE is supplied. */ | |
473 | post_entry = split_edge (single_succ_edge (ENTRY_BLOCK_PTR)); | |
474 | pre_exit = create_pre_exit (n_entities, entity_map, num_modes); | |
475 | #endif | |
476 | ||
3072d30e | 477 | df_analyze (); |
478 | ||
2f138c1c | 479 | /* Create the bitmap vectors. */ |
480 | ||
481 | antic = sbitmap_vector_alloc (last_basic_block, n_entities); | |
482 | transp = sbitmap_vector_alloc (last_basic_block, n_entities); | |
483 | comp = sbitmap_vector_alloc (last_basic_block, n_entities); | |
484 | ||
53c5d9d4 | 485 | bitmap_vector_ones (transp, last_basic_block); |
2f138c1c | 486 | |
487 | for (j = n_entities - 1; j >= 0; j--) | |
488 | { | |
489 | int e = entity_map[j]; | |
490 | int no_mode = num_modes[e]; | |
491 | struct bb_info *info = bb_info[j]; | |
492 | ||
493 | /* Determine what the first use (if any) need for a mode of entity E is. | |
494 | This will be the mode that is anticipatable for this block. | |
495 | Also compute the initial transparency settings. */ | |
496 | FOR_EACH_BB (bb) | |
497 | { | |
498 | struct seginfo *ptr; | |
499 | int last_mode = no_mode; | |
aadec354 | 500 | bool any_set_required = false; |
2f138c1c | 501 | HARD_REG_SET live_now; |
502 | ||
3072d30e | 503 | REG_SET_TO_HARD_REG_SET (live_now, df_get_live_in (bb)); |
37430745 | 504 | |
505 | /* Pretend the mode is clobbered across abnormal edges. */ | |
506 | { | |
507 | edge_iterator ei; | |
508 | edge e; | |
509 | FOR_EACH_EDGE (e, ei, bb->preds) | |
510 | if (e->flags & EDGE_COMPLEX) | |
511 | break; | |
512 | if (e) | |
9e236a59 | 513 | { |
514 | ptr = new_seginfo (no_mode, BB_HEAD (bb), bb->index, live_now); | |
515 | add_seginfo (info + bb->index, ptr); | |
08b7917c | 516 | bitmap_clear_bit (transp[bb->index], j); |
9e236a59 | 517 | } |
37430745 | 518 | } |
519 | ||
50b15e04 | 520 | FOR_BB_INSNS (bb, insn) |
2f138c1c | 521 | { |
522 | if (INSN_P (insn)) | |
523 | { | |
524 | int mode = MODE_NEEDED (e, insn); | |
525 | rtx link; | |
526 | ||
527 | if (mode != no_mode && mode != last_mode) | |
528 | { | |
aadec354 | 529 | any_set_required = true; |
2f138c1c | 530 | last_mode = mode; |
531 | ptr = new_seginfo (mode, insn, bb->index, live_now); | |
532 | add_seginfo (info + bb->index, ptr); | |
08b7917c | 533 | bitmap_clear_bit (transp[bb->index], j); |
2f138c1c | 534 | } |
535 | #ifdef MODE_AFTER | |
7bc8959a | 536 | last_mode = MODE_AFTER (e, last_mode, insn); |
2f138c1c | 537 | #endif |
538 | /* Update LIVE_NOW. */ | |
539 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | |
540 | if (REG_NOTE_KIND (link) == REG_DEAD) | |
0ff4fe1d | 541 | reg_dies (XEXP (link, 0), &live_now); |
2f138c1c | 542 | |
543 | note_stores (PATTERN (insn), reg_becomes_live, &live_now); | |
544 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | |
545 | if (REG_NOTE_KIND (link) == REG_UNUSED) | |
0ff4fe1d | 546 | reg_dies (XEXP (link, 0), &live_now); |
2f138c1c | 547 | } |
548 | } | |
549 | ||
550 | info[bb->index].computing = last_mode; | |
aadec354 | 551 | /* Check for blocks without ANY mode requirements. |
552 | N.B. because of MODE_AFTER, last_mode might still be different | |
553 | from no_mode. */ | |
554 | if (!any_set_required) | |
2f138c1c | 555 | { |
556 | ptr = new_seginfo (no_mode, BB_END (bb), bb->index, live_now); | |
557 | add_seginfo (info + bb->index, ptr); | |
558 | } | |
559 | } | |
560 | #if defined (MODE_ENTRY) && defined (MODE_EXIT) | |
561 | { | |
562 | int mode = MODE_ENTRY (e); | |
563 | ||
564 | if (mode != no_mode) | |
565 | { | |
566 | bb = post_entry; | |
567 | ||
568 | /* By always making this nontransparent, we save | |
569 | an extra check in make_preds_opaque. We also | |
570 | need this to avoid confusing pre_edge_lcm when | |
571 | antic is cleared but transp and comp are set. */ | |
08b7917c | 572 | bitmap_clear_bit (transp[bb->index], j); |
2f138c1c | 573 | |
574 | /* Insert a fake computing definition of MODE into entry | |
575 | blocks which compute no mode. This represents the mode on | |
576 | entry. */ | |
577 | info[bb->index].computing = mode; | |
578 | ||
579 | if (pre_exit) | |
580 | info[pre_exit->index].seginfo->mode = MODE_EXIT (e); | |
581 | } | |
582 | } | |
583 | #endif /* NORMAL_MODE */ | |
584 | } | |
585 | ||
586 | kill = sbitmap_vector_alloc (last_basic_block, n_entities); | |
587 | for (i = 0; i < max_num_modes; i++) | |
588 | { | |
589 | int current_mode[N_ENTITIES]; | |
9ce37fa7 | 590 | sbitmap *del; |
2f138c1c | 591 | sbitmap *insert; |
592 | ||
593 | /* Set the anticipatable and computing arrays. */ | |
53c5d9d4 | 594 | bitmap_vector_clear (antic, last_basic_block); |
595 | bitmap_vector_clear (comp, last_basic_block); | |
2f138c1c | 596 | for (j = n_entities - 1; j >= 0; j--) |
597 | { | |
598 | int m = current_mode[j] = MODE_PRIORITY_TO_MODE (entity_map[j], i); | |
599 | struct bb_info *info = bb_info[j]; | |
600 | ||
601 | FOR_EACH_BB (bb) | |
602 | { | |
603 | if (info[bb->index].seginfo->mode == m) | |
08b7917c | 604 | bitmap_set_bit (antic[bb->index], j); |
2f138c1c | 605 | |
606 | if (info[bb->index].computing == m) | |
08b7917c | 607 | bitmap_set_bit (comp[bb->index], j); |
2f138c1c | 608 | } |
609 | } | |
610 | ||
611 | /* Calculate the optimal locations for the | |
612 | placement mode switches to modes with priority I. */ | |
613 | ||
614 | FOR_EACH_BB (bb) | |
53c5d9d4 | 615 | bitmap_not (kill[bb->index], transp[bb->index]); |
3f5be5f4 | 616 | edge_list = pre_edge_lcm (n_entities, transp, comp, antic, |
9ce37fa7 | 617 | kill, &insert, &del); |
2f138c1c | 618 | |
619 | for (j = n_entities - 1; j >= 0; j--) | |
620 | { | |
621 | /* Insert all mode sets that have been inserted by lcm. */ | |
622 | int no_mode = num_modes[entity_map[j]]; | |
623 | ||
624 | /* Wherever we have moved a mode setting upwards in the flow graph, | |
625 | the blocks between the new setting site and the now redundant | |
626 | computation ceases to be transparent for any lower-priority | |
627 | mode of the same entity. First set the aux field of each | |
628 | insertion site edge non-transparent, then propagate the new | |
629 | non-transparency from the redundant computation upwards till | |
630 | we hit an insertion site or an already non-transparent block. */ | |
631 | for (e = NUM_EDGES (edge_list) - 1; e >= 0; e--) | |
632 | { | |
633 | edge eg = INDEX_EDGE (edge_list, e); | |
634 | int mode; | |
635 | basic_block src_bb; | |
636 | HARD_REG_SET live_at_edge; | |
637 | rtx mode_set; | |
638 | ||
639 | eg->aux = 0; | |
640 | ||
08b7917c | 641 | if (! bitmap_bit_p (insert[e], j)) |
2f138c1c | 642 | continue; |
643 | ||
644 | eg->aux = (void *)1; | |
645 | ||
646 | mode = current_mode[j]; | |
647 | src_bb = eg->src; | |
648 | ||
3072d30e | 649 | REG_SET_TO_HARD_REG_SET (live_at_edge, df_get_live_out (src_bb)); |
2f138c1c | 650 | |
651 | start_sequence (); | |
652 | EMIT_MODE_SET (entity_map[j], mode, live_at_edge); | |
653 | mode_set = get_insns (); | |
654 | end_sequence (); | |
655 | ||
656 | /* Do not bother to insert empty sequence. */ | |
657 | if (mode_set == NULL_RTX) | |
658 | continue; | |
659 | ||
9e236a59 | 660 | /* We should not get an abnormal edge here. */ |
661 | gcc_assert (! (eg->flags & EDGE_ABNORMAL)); | |
662 | ||
663 | need_commit = 1; | |
664 | insert_insn_on_edge (mode_set, eg); | |
2f138c1c | 665 | } |
666 | ||
667 | FOR_EACH_BB_REVERSE (bb) | |
08b7917c | 668 | if (bitmap_bit_p (del[bb->index], j)) |
2f138c1c | 669 | { |
670 | make_preds_opaque (bb, j); | |
671 | /* Cancel the 'deleted' mode set. */ | |
672 | bb_info[j][bb->index].seginfo->mode = no_mode; | |
673 | } | |
674 | } | |
675 | ||
9ce37fa7 | 676 | sbitmap_vector_free (del); |
2f138c1c | 677 | sbitmap_vector_free (insert); |
678 | clear_aux_for_edges (); | |
679 | free_edge_list (edge_list); | |
680 | } | |
681 | ||
682 | /* Now output the remaining mode sets in all the segments. */ | |
683 | for (j = n_entities - 1; j >= 0; j--) | |
684 | { | |
685 | int no_mode = num_modes[entity_map[j]]; | |
686 | ||
687 | FOR_EACH_BB_REVERSE (bb) | |
688 | { | |
689 | struct seginfo *ptr, *next; | |
690 | for (ptr = bb_info[j][bb->index].seginfo; ptr; ptr = next) | |
691 | { | |
692 | next = ptr->next; | |
693 | if (ptr->mode != no_mode) | |
694 | { | |
695 | rtx mode_set; | |
696 | ||
697 | start_sequence (); | |
698 | EMIT_MODE_SET (entity_map[j], ptr->mode, ptr->regs_live); | |
699 | mode_set = get_insns (); | |
700 | end_sequence (); | |
701 | ||
702 | /* Insert MODE_SET only if it is nonempty. */ | |
703 | if (mode_set != NULL_RTX) | |
704 | { | |
9d75589a | 705 | emitted = true; |
ad4583d9 | 706 | if (NOTE_INSN_BASIC_BLOCK_P (ptr->insn_ptr)) |
2f138c1c | 707 | emit_insn_after (mode_set, ptr->insn_ptr); |
708 | else | |
709 | emit_insn_before (mode_set, ptr->insn_ptr); | |
710 | } | |
711 | } | |
712 | ||
713 | free (ptr); | |
714 | } | |
715 | } | |
716 | ||
717 | free (bb_info[j]); | |
718 | } | |
719 | ||
720 | /* Finished. Free up all the things we've allocated. */ | |
2f138c1c | 721 | sbitmap_vector_free (kill); |
722 | sbitmap_vector_free (antic); | |
723 | sbitmap_vector_free (transp); | |
724 | sbitmap_vector_free (comp); | |
725 | ||
726 | if (need_commit) | |
727 | commit_edge_insertions (); | |
728 | ||
729 | #if defined (MODE_ENTRY) && defined (MODE_EXIT) | |
730 | cleanup_cfg (CLEANUP_NO_INSN_DEL); | |
731 | #else | |
9d75589a | 732 | if (!need_commit && !emitted) |
2f138c1c | 733 | return 0; |
734 | #endif | |
735 | ||
2f138c1c | 736 | return 1; |
737 | } | |
77fce4cd | 738 | |
2f138c1c | 739 | #endif /* OPTIMIZE_MODE_SWITCHING */ |
77fce4cd | 740 | \f |
741 | static bool | |
742 | gate_mode_switching (void) | |
743 | { | |
744 | #ifdef OPTIMIZE_MODE_SWITCHING | |
745 | return true; | |
746 | #else | |
747 | return false; | |
748 | #endif | |
749 | } | |
750 | ||
2a1990e9 | 751 | static unsigned int |
77fce4cd | 752 | rest_of_handle_mode_switching (void) |
753 | { | |
754 | #ifdef OPTIMIZE_MODE_SWITCHING | |
3f5be5f4 | 755 | optimize_mode_switching (); |
77fce4cd | 756 | #endif /* OPTIMIZE_MODE_SWITCHING */ |
2a1990e9 | 757 | return 0; |
77fce4cd | 758 | } |
759 | ||
760 | ||
20099e35 | 761 | struct rtl_opt_pass pass_mode_switching = |
77fce4cd | 762 | { |
20099e35 | 763 | { |
764 | RTL_PASS, | |
b85ccd2c | 765 | "mode_sw", /* name */ |
c7875731 | 766 | OPTGROUP_NONE, /* optinfo_flags */ |
77fce4cd | 767 | gate_mode_switching, /* gate */ |
768 | rest_of_handle_mode_switching, /* execute */ | |
769 | NULL, /* sub */ | |
770 | NULL, /* next */ | |
771 | 0, /* static_pass_number */ | |
772 | TV_MODE_SWITCH, /* tv_id */ | |
773 | 0, /* properties_required */ | |
774 | 0, /* properties_provided */ | |
775 | 0, /* properties_destroyed */ | |
776 | 0, /* todo_flags_start */ | |
0806b508 | 777 | TODO_df_finish | TODO_verify_rtl_sharing | |
771e2890 | 778 | 0 /* todo_flags_finish */ |
20099e35 | 779 | } |
77fce4cd | 780 | }; |