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2f138c1c | 1 | /* CPU mode switching |
cfaf579d | 2 | Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008, |
168ae443 | 3 | 2009, 2010 Free Software Foundation, Inc. |
2f138c1c | 4 | |
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it under | |
8 | the terms of the GNU General Public License as published by the Free | |
8c4c00c1 | 9 | Software Foundation; either version 3, or (at your option) any later |
2f138c1c | 10 | version. |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
8c4c00c1 | 18 | along with GCC; see the file COPYING3. If not see |
19 | <http://www.gnu.org/licenses/>. */ | |
2f138c1c | 20 | |
21 | #include "config.h" | |
22 | #include "system.h" | |
23 | #include "coretypes.h" | |
24 | #include "tm.h" | |
e1ce1485 | 25 | #include "target.h" |
2f138c1c | 26 | #include "rtl.h" |
27 | #include "regs.h" | |
28 | #include "hard-reg-set.h" | |
29 | #include "flags.h" | |
2f138c1c | 30 | #include "insn-config.h" |
31 | #include "recog.h" | |
32 | #include "basic-block.h" | |
33 | #include "output.h" | |
34 | #include "tm_p.h" | |
35 | #include "function.h" | |
77fce4cd | 36 | #include "tree-pass.h" |
37 | #include "timevar.h" | |
3072d30e | 38 | #include "df.h" |
06f9d6ef | 39 | #include "emit-rtl.h" |
2f138c1c | 40 | |
41 | /* We want target macros for the mode switching code to be able to refer | |
42 | to instruction attribute values. */ | |
43 | #include "insn-attr.h" | |
44 | ||
45 | #ifdef OPTIMIZE_MODE_SWITCHING | |
46 | ||
47 | /* The algorithm for setting the modes consists of scanning the insn list | |
48 | and finding all the insns which require a specific mode. Each insn gets | |
49 | a unique struct seginfo element. These structures are inserted into a list | |
50 | for each basic block. For each entity, there is an array of bb_info over | |
51 | the flow graph basic blocks (local var 'bb_info'), and contains a list | |
52 | of all insns within that basic block, in the order they are encountered. | |
53 | ||
54 | For each entity, any basic block WITHOUT any insns requiring a specific | |
55 | mode are given a single entry, without a mode. (Each basic block | |
56 | in the flow graph must have at least one entry in the segment table.) | |
57 | ||
58 | The LCM algorithm is then run over the flow graph to determine where to | |
59 | place the sets to the highest-priority value in respect of first the first | |
60 | insn in any one block. Any adjustments required to the transparency | |
61 | vectors are made, then the next iteration starts for the next-lower | |
62 | priority mode, till for each entity all modes are exhausted. | |
63 | ||
64 | More details are located in the code for optimize_mode_switching(). */ | |
65 | \f | |
66 | /* This structure contains the information for each insn which requires | |
67 | either single or double mode to be set. | |
68 | MODE is the mode this insn must be executed in. | |
69 | INSN_PTR is the insn to be executed (may be the note that marks the | |
70 | beginning of a basic block). | |
71 | BBNUM is the flow graph basic block this insn occurs in. | |
72 | NEXT is the next insn in the same basic block. */ | |
73 | struct seginfo | |
74 | { | |
75 | int mode; | |
76 | rtx insn_ptr; | |
77 | int bbnum; | |
78 | struct seginfo *next; | |
79 | HARD_REG_SET regs_live; | |
80 | }; | |
81 | ||
82 | struct bb_info | |
83 | { | |
84 | struct seginfo *seginfo; | |
85 | int computing; | |
86 | }; | |
87 | ||
88 | /* These bitmaps are used for the LCM algorithm. */ | |
89 | ||
90 | static sbitmap *antic; | |
91 | static sbitmap *transp; | |
92 | static sbitmap *comp; | |
93 | ||
94 | static struct seginfo * new_seginfo (int, rtx, int, HARD_REG_SET); | |
95 | static void add_seginfo (struct bb_info *, struct seginfo *); | |
0ff4fe1d | 96 | static void reg_dies (rtx, HARD_REG_SET *); |
81a410b1 | 97 | static void reg_becomes_live (rtx, const_rtx, void *); |
2f138c1c | 98 | static void make_preds_opaque (basic_block, int); |
99 | \f | |
100 | ||
101 | /* This function will allocate a new BBINFO structure, initialized | |
102 | with the MODE, INSN, and basic block BB parameters. */ | |
103 | ||
104 | static struct seginfo * | |
105 | new_seginfo (int mode, rtx insn, int bb, HARD_REG_SET regs_live) | |
106 | { | |
107 | struct seginfo *ptr; | |
4c36ffe6 | 108 | ptr = XNEW (struct seginfo); |
2f138c1c | 109 | ptr->mode = mode; |
110 | ptr->insn_ptr = insn; | |
111 | ptr->bbnum = bb; | |
112 | ptr->next = NULL; | |
113 | COPY_HARD_REG_SET (ptr->regs_live, regs_live); | |
114 | return ptr; | |
115 | } | |
116 | ||
117 | /* Add a seginfo element to the end of a list. | |
118 | HEAD is a pointer to the list beginning. | |
119 | INFO is the structure to be linked in. */ | |
120 | ||
121 | static void | |
122 | add_seginfo (struct bb_info *head, struct seginfo *info) | |
123 | { | |
124 | struct seginfo *ptr; | |
125 | ||
126 | if (head->seginfo == NULL) | |
127 | head->seginfo = info; | |
128 | else | |
129 | { | |
130 | ptr = head->seginfo; | |
131 | while (ptr->next != NULL) | |
132 | ptr = ptr->next; | |
133 | ptr->next = info; | |
134 | } | |
135 | } | |
136 | ||
137 | /* Make all predecessors of basic block B opaque, recursively, till we hit | |
138 | some that are already non-transparent, or an edge where aux is set; that | |
139 | denotes that a mode set is to be done on that edge. | |
140 | J is the bit number in the bitmaps that corresponds to the entity that | |
141 | we are currently handling mode-switching for. */ | |
142 | ||
143 | static void | |
144 | make_preds_opaque (basic_block b, int j) | |
145 | { | |
146 | edge e; | |
147 | edge_iterator ei; | |
148 | ||
149 | FOR_EACH_EDGE (e, ei, b->preds) | |
150 | { | |
151 | basic_block pb = e->src; | |
152 | ||
153 | if (e->aux || ! TEST_BIT (transp[pb->index], j)) | |
154 | continue; | |
155 | ||
156 | RESET_BIT (transp[pb->index], j); | |
157 | make_preds_opaque (pb, j); | |
158 | } | |
159 | } | |
160 | ||
161 | /* Record in LIVE that register REG died. */ | |
162 | ||
163 | static void | |
0ff4fe1d | 164 | reg_dies (rtx reg, HARD_REG_SET *live) |
2f138c1c | 165 | { |
a2c6f0b7 | 166 | int regno; |
2f138c1c | 167 | |
168 | if (!REG_P (reg)) | |
169 | return; | |
170 | ||
171 | regno = REGNO (reg); | |
172 | if (regno < FIRST_PSEUDO_REGISTER) | |
a2c6f0b7 | 173 | remove_from_hard_reg_set (live, GET_MODE (reg), regno); |
2f138c1c | 174 | } |
175 | ||
176 | /* Record in LIVE that register REG became live. | |
177 | This is called via note_stores. */ | |
178 | ||
179 | static void | |
81a410b1 | 180 | reg_becomes_live (rtx reg, const_rtx setter ATTRIBUTE_UNUSED, void *live) |
2f138c1c | 181 | { |
a2c6f0b7 | 182 | int regno; |
2f138c1c | 183 | |
184 | if (GET_CODE (reg) == SUBREG) | |
185 | reg = SUBREG_REG (reg); | |
186 | ||
187 | if (!REG_P (reg)) | |
188 | return; | |
189 | ||
190 | regno = REGNO (reg); | |
191 | if (regno < FIRST_PSEUDO_REGISTER) | |
a2c6f0b7 | 192 | add_to_hard_reg_set ((HARD_REG_SET *) live, GET_MODE (reg), regno); |
2f138c1c | 193 | } |
194 | ||
195 | /* Make sure if MODE_ENTRY is defined the MODE_EXIT is defined | |
196 | and vice versa. */ | |
197 | #if defined (MODE_ENTRY) != defined (MODE_EXIT) | |
198 | #error "Both MODE_ENTRY and MODE_EXIT must be defined" | |
199 | #endif | |
200 | ||
201 | #if defined (MODE_ENTRY) && defined (MODE_EXIT) | |
202 | /* Split the fallthrough edge to the exit block, so that we can note | |
203 | that there NORMAL_MODE is required. Return the new block if it's | |
204 | inserted before the exit block. Otherwise return null. */ | |
205 | ||
206 | static basic_block | |
207 | create_pre_exit (int n_entities, int *entity_map, const int *num_modes) | |
208 | { | |
209 | edge eg; | |
210 | edge_iterator ei; | |
211 | basic_block pre_exit; | |
212 | ||
213 | /* The only non-call predecessor at this stage is a block with a | |
214 | fallthrough edge; there can be at most one, but there could be | |
215 | none at all, e.g. when exit is called. */ | |
216 | pre_exit = 0; | |
217 | FOR_EACH_EDGE (eg, ei, EXIT_BLOCK_PTR->preds) | |
218 | if (eg->flags & EDGE_FALLTHRU) | |
219 | { | |
220 | basic_block src_bb = eg->src; | |
2f138c1c | 221 | rtx last_insn, ret_reg; |
222 | ||
223 | gcc_assert (!pre_exit); | |
224 | /* If this function returns a value at the end, we have to | |
225 | insert the final mode switch before the return value copy | |
226 | to its hard register. */ | |
227 | if (EDGE_COUNT (EXIT_BLOCK_PTR->preds) == 1 | |
228 | && NONJUMP_INSN_P ((last_insn = BB_END (src_bb))) | |
229 | && GET_CODE (PATTERN (last_insn)) == USE | |
230 | && GET_CODE ((ret_reg = XEXP (PATTERN (last_insn), 0))) == REG) | |
231 | { | |
232 | int ret_start = REGNO (ret_reg); | |
233 | int nregs = hard_regno_nregs[ret_start][GET_MODE (ret_reg)]; | |
234 | int ret_end = ret_start + nregs; | |
235 | int short_block = 0; | |
236 | int maybe_builtin_apply = 0; | |
237 | int forced_late_switch = 0; | |
238 | rtx before_return_copy; | |
239 | ||
240 | do | |
241 | { | |
242 | rtx return_copy = PREV_INSN (last_insn); | |
243 | rtx return_copy_pat, copy_reg; | |
244 | int copy_start, copy_num; | |
245 | int j; | |
246 | ||
247 | if (INSN_P (return_copy)) | |
248 | { | |
1915b15f | 249 | /* When using SJLJ exceptions, the call to the |
250 | unregister function is inserted between the | |
251 | clobber of the return value and the copy. | |
252 | We do not want to split the block before this | |
253 | or any other call; if we have not found the | |
254 | copy yet, the copy must have been deleted. */ | |
255 | if (CALL_P (return_copy)) | |
256 | { | |
257 | short_block = 1; | |
258 | break; | |
259 | } | |
646857a5 | 260 | return_copy_pat = PATTERN (return_copy); |
261 | switch (GET_CODE (return_copy_pat)) | |
8801c4fd | 262 | { |
646857a5 | 263 | case USE: |
264 | /* Skip __builtin_apply pattern. */ | |
265 | if (GET_CODE (XEXP (return_copy_pat, 0)) == REG | |
e1ce1485 | 266 | && (targetm.calls.function_value_regno_p |
646857a5 | 267 | (REGNO (XEXP (return_copy_pat, 0))))) |
268 | { | |
269 | maybe_builtin_apply = 1; | |
270 | last_insn = return_copy; | |
271 | continue; | |
272 | } | |
273 | break; | |
274 | ||
275 | case ASM_OPERANDS: | |
276 | /* Skip barrier insns. */ | |
277 | if (!MEM_VOLATILE_P (return_copy_pat)) | |
278 | break; | |
279 | ||
280 | /* Fall through. */ | |
281 | ||
282 | case ASM_INPUT: | |
283 | case UNSPEC_VOLATILE: | |
8801c4fd | 284 | last_insn = return_copy; |
285 | continue; | |
646857a5 | 286 | |
287 | default: | |
288 | break; | |
8801c4fd | 289 | } |
646857a5 | 290 | |
2f138c1c | 291 | /* If the return register is not (in its entirety) |
292 | likely spilled, the return copy might be | |
293 | partially or completely optimized away. */ | |
294 | return_copy_pat = single_set (return_copy); | |
295 | if (!return_copy_pat) | |
296 | { | |
297 | return_copy_pat = PATTERN (return_copy); | |
298 | if (GET_CODE (return_copy_pat) != CLOBBER) | |
299 | break; | |
3072d30e | 300 | else if (!optimize) |
301 | { | |
302 | /* This might be (clobber (reg [<result>])) | |
303 | when not optimizing. Then check if | |
304 | the previous insn is the clobber for | |
305 | the return register. */ | |
306 | copy_reg = SET_DEST (return_copy_pat); | |
307 | if (GET_CODE (copy_reg) == REG | |
308 | && !HARD_REGISTER_NUM_P (REGNO (copy_reg))) | |
309 | { | |
310 | if (INSN_P (PREV_INSN (return_copy))) | |
311 | { | |
312 | return_copy = PREV_INSN (return_copy); | |
313 | return_copy_pat = PATTERN (return_copy); | |
314 | if (GET_CODE (return_copy_pat) != CLOBBER) | |
315 | break; | |
316 | } | |
317 | } | |
318 | } | |
2f138c1c | 319 | } |
320 | copy_reg = SET_DEST (return_copy_pat); | |
321 | if (GET_CODE (copy_reg) == REG) | |
322 | copy_start = REGNO (copy_reg); | |
323 | else if (GET_CODE (copy_reg) == SUBREG | |
324 | && GET_CODE (SUBREG_REG (copy_reg)) == REG) | |
325 | copy_start = REGNO (SUBREG_REG (copy_reg)); | |
326 | else | |
327 | break; | |
328 | if (copy_start >= FIRST_PSEUDO_REGISTER) | |
329 | break; | |
330 | copy_num | |
331 | = hard_regno_nregs[copy_start][GET_MODE (copy_reg)]; | |
332 | ||
333 | /* If the return register is not likely spilled, - as is | |
334 | the case for floating point on SH4 - then it might | |
335 | be set by an arithmetic operation that needs a | |
336 | different mode than the exit block. */ | |
337 | for (j = n_entities - 1; j >= 0; j--) | |
338 | { | |
339 | int e = entity_map[j]; | |
340 | int mode = MODE_NEEDED (e, return_copy); | |
341 | ||
342 | if (mode != num_modes[e] && mode != MODE_EXIT (e)) | |
343 | break; | |
344 | } | |
345 | if (j >= 0) | |
346 | { | |
347 | /* For the SH4, floating point loads depend on fpscr, | |
348 | thus we might need to put the final mode switch | |
349 | after the return value copy. That is still OK, | |
350 | because a floating point return value does not | |
351 | conflict with address reloads. */ | |
352 | if (copy_start >= ret_start | |
353 | && copy_start + copy_num <= ret_end | |
354 | && OBJECT_P (SET_SRC (return_copy_pat))) | |
355 | forced_late_switch = 1; | |
356 | break; | |
357 | } | |
358 | ||
359 | if (copy_start >= ret_start | |
360 | && copy_start + copy_num <= ret_end) | |
361 | nregs -= copy_num; | |
362 | else if (!maybe_builtin_apply | |
e1ce1485 | 363 | || !targetm.calls.function_value_regno_p |
364 | (copy_start)) | |
2f138c1c | 365 | break; |
366 | last_insn = return_copy; | |
367 | } | |
368 | /* ??? Exception handling can lead to the return value | |
369 | copy being already separated from the return value use, | |
370 | as in unwind-dw2.c . | |
371 | Similarly, conditionally returning without a value, | |
372 | and conditionally using builtin_return can lead to an | |
373 | isolated use. */ | |
374 | if (return_copy == BB_HEAD (src_bb)) | |
375 | { | |
376 | short_block = 1; | |
377 | break; | |
378 | } | |
379 | last_insn = return_copy; | |
380 | } | |
381 | while (nregs); | |
48e1416a | 382 | |
2f138c1c | 383 | /* If we didn't see a full return value copy, verify that there |
384 | is a plausible reason for this. If some, but not all of the | |
385 | return register is likely spilled, we can expect that there | |
386 | is a copy for the likely spilled part. */ | |
387 | gcc_assert (!nregs | |
388 | || forced_late_switch | |
389 | || short_block | |
390 | || !(CLASS_LIKELY_SPILLED_P | |
391 | (REGNO_REG_CLASS (ret_start))) | |
392 | || (nregs | |
393 | != hard_regno_nregs[ret_start][GET_MODE (ret_reg)]) | |
394 | /* For multi-hard-register floating point | |
395 | values, sometimes the likely-spilled part | |
396 | is ordinarily copied first, then the other | |
397 | part is set with an arithmetic operation. | |
398 | This doesn't actually cause reload | |
399 | failures, so let it pass. */ | |
400 | || (GET_MODE_CLASS (GET_MODE (ret_reg)) != MODE_INT | |
401 | && nregs != 1)); | |
48e1416a | 402 | |
2f138c1c | 403 | if (INSN_P (last_insn)) |
404 | { | |
405 | before_return_copy | |
406 | = emit_note_before (NOTE_INSN_DELETED, last_insn); | |
407 | /* Instructions preceding LAST_INSN in the same block might | |
408 | require a different mode than MODE_EXIT, so if we might | |
409 | have such instructions, keep them in a separate block | |
410 | from pre_exit. */ | |
411 | if (last_insn != BB_HEAD (src_bb)) | |
412 | src_bb = split_block (src_bb, | |
413 | PREV_INSN (before_return_copy))->dest; | |
414 | } | |
415 | else | |
416 | before_return_copy = last_insn; | |
417 | pre_exit = split_block (src_bb, before_return_copy)->src; | |
418 | } | |
419 | else | |
420 | { | |
421 | pre_exit = split_edge (eg); | |
2f138c1c | 422 | } |
423 | } | |
424 | ||
425 | return pre_exit; | |
426 | } | |
427 | #endif | |
428 | ||
429 | /* Find all insns that need a particular mode setting, and insert the | |
430 | necessary mode switches. Return true if we did work. */ | |
431 | ||
9d31a126 | 432 | static int |
3f5be5f4 | 433 | optimize_mode_switching (void) |
2f138c1c | 434 | { |
435 | rtx insn; | |
436 | int e; | |
437 | basic_block bb; | |
438 | int need_commit = 0; | |
439 | sbitmap *kill; | |
440 | struct edge_list *edge_list; | |
441 | static const int num_modes[] = NUM_MODES_FOR_MODE_SWITCHING; | |
442 | #define N_ENTITIES ARRAY_SIZE (num_modes) | |
443 | int entity_map[N_ENTITIES]; | |
444 | struct bb_info *bb_info[N_ENTITIES]; | |
445 | int i, j; | |
446 | int n_entities; | |
447 | int max_num_modes = 0; | |
168ae443 | 448 | bool emited ATTRIBUTE_UNUSED = false; |
2f138c1c | 449 | basic_block post_entry ATTRIBUTE_UNUSED, pre_exit ATTRIBUTE_UNUSED; |
450 | ||
2f138c1c | 451 | for (e = N_ENTITIES - 1, n_entities = 0; e >= 0; e--) |
452 | if (OPTIMIZE_MODE_SWITCHING (e)) | |
453 | { | |
454 | int entry_exit_extra = 0; | |
455 | ||
456 | /* Create the list of segments within each basic block. | |
457 | If NORMAL_MODE is defined, allow for two extra | |
458 | blocks split from the entry and exit block. */ | |
459 | #if defined (MODE_ENTRY) && defined (MODE_EXIT) | |
460 | entry_exit_extra = 3; | |
461 | #endif | |
462 | bb_info[n_entities] | |
613768ea | 463 | = XCNEWVEC (struct bb_info, last_basic_block + entry_exit_extra); |
2f138c1c | 464 | entity_map[n_entities++] = e; |
465 | if (num_modes[e] > max_num_modes) | |
466 | max_num_modes = num_modes[e]; | |
467 | } | |
468 | ||
469 | if (! n_entities) | |
470 | return 0; | |
471 | ||
472 | #if defined (MODE_ENTRY) && defined (MODE_EXIT) | |
473 | /* Split the edge from the entry block, so that we can note that | |
474 | there NORMAL_MODE is supplied. */ | |
475 | post_entry = split_edge (single_succ_edge (ENTRY_BLOCK_PTR)); | |
476 | pre_exit = create_pre_exit (n_entities, entity_map, num_modes); | |
477 | #endif | |
478 | ||
3072d30e | 479 | df_analyze (); |
480 | ||
2f138c1c | 481 | /* Create the bitmap vectors. */ |
482 | ||
483 | antic = sbitmap_vector_alloc (last_basic_block, n_entities); | |
484 | transp = sbitmap_vector_alloc (last_basic_block, n_entities); | |
485 | comp = sbitmap_vector_alloc (last_basic_block, n_entities); | |
486 | ||
487 | sbitmap_vector_ones (transp, last_basic_block); | |
488 | ||
489 | for (j = n_entities - 1; j >= 0; j--) | |
490 | { | |
491 | int e = entity_map[j]; | |
492 | int no_mode = num_modes[e]; | |
493 | struct bb_info *info = bb_info[j]; | |
494 | ||
495 | /* Determine what the first use (if any) need for a mode of entity E is. | |
496 | This will be the mode that is anticipatable for this block. | |
497 | Also compute the initial transparency settings. */ | |
498 | FOR_EACH_BB (bb) | |
499 | { | |
500 | struct seginfo *ptr; | |
501 | int last_mode = no_mode; | |
502 | HARD_REG_SET live_now; | |
503 | ||
3072d30e | 504 | REG_SET_TO_HARD_REG_SET (live_now, df_get_live_in (bb)); |
37430745 | 505 | |
506 | /* Pretend the mode is clobbered across abnormal edges. */ | |
507 | { | |
508 | edge_iterator ei; | |
509 | edge e; | |
510 | FOR_EACH_EDGE (e, ei, bb->preds) | |
511 | if (e->flags & EDGE_COMPLEX) | |
512 | break; | |
513 | if (e) | |
9e236a59 | 514 | { |
515 | ptr = new_seginfo (no_mode, BB_HEAD (bb), bb->index, live_now); | |
516 | add_seginfo (info + bb->index, ptr); | |
517 | RESET_BIT (transp[bb->index], j); | |
518 | } | |
37430745 | 519 | } |
520 | ||
2f138c1c | 521 | for (insn = BB_HEAD (bb); |
522 | insn != NULL && insn != NEXT_INSN (BB_END (bb)); | |
523 | insn = NEXT_INSN (insn)) | |
524 | { | |
525 | if (INSN_P (insn)) | |
526 | { | |
527 | int mode = MODE_NEEDED (e, insn); | |
528 | rtx link; | |
529 | ||
530 | if (mode != no_mode && mode != last_mode) | |
531 | { | |
532 | last_mode = mode; | |
533 | ptr = new_seginfo (mode, insn, bb->index, live_now); | |
534 | add_seginfo (info + bb->index, ptr); | |
535 | RESET_BIT (transp[bb->index], j); | |
536 | } | |
537 | #ifdef MODE_AFTER | |
538 | last_mode = MODE_AFTER (last_mode, insn); | |
539 | #endif | |
540 | /* Update LIVE_NOW. */ | |
541 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | |
542 | if (REG_NOTE_KIND (link) == REG_DEAD) | |
0ff4fe1d | 543 | reg_dies (XEXP (link, 0), &live_now); |
2f138c1c | 544 | |
545 | note_stores (PATTERN (insn), reg_becomes_live, &live_now); | |
546 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | |
547 | if (REG_NOTE_KIND (link) == REG_UNUSED) | |
0ff4fe1d | 548 | reg_dies (XEXP (link, 0), &live_now); |
2f138c1c | 549 | } |
550 | } | |
551 | ||
552 | info[bb->index].computing = last_mode; | |
553 | /* Check for blocks without ANY mode requirements. */ | |
554 | if (last_mode == no_mode) | |
555 | { | |
556 | ptr = new_seginfo (no_mode, BB_END (bb), bb->index, live_now); | |
557 | add_seginfo (info + bb->index, ptr); | |
558 | } | |
559 | } | |
560 | #if defined (MODE_ENTRY) && defined (MODE_EXIT) | |
561 | { | |
562 | int mode = MODE_ENTRY (e); | |
563 | ||
564 | if (mode != no_mode) | |
565 | { | |
566 | bb = post_entry; | |
567 | ||
568 | /* By always making this nontransparent, we save | |
569 | an extra check in make_preds_opaque. We also | |
570 | need this to avoid confusing pre_edge_lcm when | |
571 | antic is cleared but transp and comp are set. */ | |
572 | RESET_BIT (transp[bb->index], j); | |
573 | ||
574 | /* Insert a fake computing definition of MODE into entry | |
575 | blocks which compute no mode. This represents the mode on | |
576 | entry. */ | |
577 | info[bb->index].computing = mode; | |
578 | ||
579 | if (pre_exit) | |
580 | info[pre_exit->index].seginfo->mode = MODE_EXIT (e); | |
581 | } | |
582 | } | |
583 | #endif /* NORMAL_MODE */ | |
584 | } | |
585 | ||
586 | kill = sbitmap_vector_alloc (last_basic_block, n_entities); | |
587 | for (i = 0; i < max_num_modes; i++) | |
588 | { | |
589 | int current_mode[N_ENTITIES]; | |
9ce37fa7 | 590 | sbitmap *del; |
2f138c1c | 591 | sbitmap *insert; |
592 | ||
593 | /* Set the anticipatable and computing arrays. */ | |
594 | sbitmap_vector_zero (antic, last_basic_block); | |
595 | sbitmap_vector_zero (comp, last_basic_block); | |
596 | for (j = n_entities - 1; j >= 0; j--) | |
597 | { | |
598 | int m = current_mode[j] = MODE_PRIORITY_TO_MODE (entity_map[j], i); | |
599 | struct bb_info *info = bb_info[j]; | |
600 | ||
601 | FOR_EACH_BB (bb) | |
602 | { | |
603 | if (info[bb->index].seginfo->mode == m) | |
604 | SET_BIT (antic[bb->index], j); | |
605 | ||
606 | if (info[bb->index].computing == m) | |
607 | SET_BIT (comp[bb->index], j); | |
608 | } | |
609 | } | |
610 | ||
611 | /* Calculate the optimal locations for the | |
612 | placement mode switches to modes with priority I. */ | |
613 | ||
614 | FOR_EACH_BB (bb) | |
615 | sbitmap_not (kill[bb->index], transp[bb->index]); | |
3f5be5f4 | 616 | edge_list = pre_edge_lcm (n_entities, transp, comp, antic, |
9ce37fa7 | 617 | kill, &insert, &del); |
2f138c1c | 618 | |
619 | for (j = n_entities - 1; j >= 0; j--) | |
620 | { | |
621 | /* Insert all mode sets that have been inserted by lcm. */ | |
622 | int no_mode = num_modes[entity_map[j]]; | |
623 | ||
624 | /* Wherever we have moved a mode setting upwards in the flow graph, | |
625 | the blocks between the new setting site and the now redundant | |
626 | computation ceases to be transparent for any lower-priority | |
627 | mode of the same entity. First set the aux field of each | |
628 | insertion site edge non-transparent, then propagate the new | |
629 | non-transparency from the redundant computation upwards till | |
630 | we hit an insertion site or an already non-transparent block. */ | |
631 | for (e = NUM_EDGES (edge_list) - 1; e >= 0; e--) | |
632 | { | |
633 | edge eg = INDEX_EDGE (edge_list, e); | |
634 | int mode; | |
635 | basic_block src_bb; | |
636 | HARD_REG_SET live_at_edge; | |
637 | rtx mode_set; | |
638 | ||
639 | eg->aux = 0; | |
640 | ||
641 | if (! TEST_BIT (insert[e], j)) | |
642 | continue; | |
643 | ||
644 | eg->aux = (void *)1; | |
645 | ||
646 | mode = current_mode[j]; | |
647 | src_bb = eg->src; | |
648 | ||
3072d30e | 649 | REG_SET_TO_HARD_REG_SET (live_at_edge, df_get_live_out (src_bb)); |
2f138c1c | 650 | |
651 | start_sequence (); | |
652 | EMIT_MODE_SET (entity_map[j], mode, live_at_edge); | |
653 | mode_set = get_insns (); | |
654 | end_sequence (); | |
655 | ||
656 | /* Do not bother to insert empty sequence. */ | |
657 | if (mode_set == NULL_RTX) | |
658 | continue; | |
659 | ||
9e236a59 | 660 | /* We should not get an abnormal edge here. */ |
661 | gcc_assert (! (eg->flags & EDGE_ABNORMAL)); | |
662 | ||
663 | need_commit = 1; | |
664 | insert_insn_on_edge (mode_set, eg); | |
2f138c1c | 665 | } |
666 | ||
667 | FOR_EACH_BB_REVERSE (bb) | |
9ce37fa7 | 668 | if (TEST_BIT (del[bb->index], j)) |
2f138c1c | 669 | { |
670 | make_preds_opaque (bb, j); | |
671 | /* Cancel the 'deleted' mode set. */ | |
672 | bb_info[j][bb->index].seginfo->mode = no_mode; | |
673 | } | |
674 | } | |
675 | ||
9ce37fa7 | 676 | sbitmap_vector_free (del); |
2f138c1c | 677 | sbitmap_vector_free (insert); |
678 | clear_aux_for_edges (); | |
679 | free_edge_list (edge_list); | |
680 | } | |
681 | ||
682 | /* Now output the remaining mode sets in all the segments. */ | |
683 | for (j = n_entities - 1; j >= 0; j--) | |
684 | { | |
685 | int no_mode = num_modes[entity_map[j]]; | |
686 | ||
687 | FOR_EACH_BB_REVERSE (bb) | |
688 | { | |
689 | struct seginfo *ptr, *next; | |
690 | for (ptr = bb_info[j][bb->index].seginfo; ptr; ptr = next) | |
691 | { | |
692 | next = ptr->next; | |
693 | if (ptr->mode != no_mode) | |
694 | { | |
695 | rtx mode_set; | |
696 | ||
697 | start_sequence (); | |
698 | EMIT_MODE_SET (entity_map[j], ptr->mode, ptr->regs_live); | |
699 | mode_set = get_insns (); | |
700 | end_sequence (); | |
701 | ||
702 | /* Insert MODE_SET only if it is nonempty. */ | |
703 | if (mode_set != NULL_RTX) | |
704 | { | |
705 | emited = true; | |
ad4583d9 | 706 | if (NOTE_INSN_BASIC_BLOCK_P (ptr->insn_ptr)) |
2f138c1c | 707 | emit_insn_after (mode_set, ptr->insn_ptr); |
708 | else | |
709 | emit_insn_before (mode_set, ptr->insn_ptr); | |
710 | } | |
711 | } | |
712 | ||
713 | free (ptr); | |
714 | } | |
715 | } | |
716 | ||
717 | free (bb_info[j]); | |
718 | } | |
719 | ||
720 | /* Finished. Free up all the things we've allocated. */ | |
2f138c1c | 721 | sbitmap_vector_free (kill); |
722 | sbitmap_vector_free (antic); | |
723 | sbitmap_vector_free (transp); | |
724 | sbitmap_vector_free (comp); | |
725 | ||
726 | if (need_commit) | |
727 | commit_edge_insertions (); | |
728 | ||
729 | #if defined (MODE_ENTRY) && defined (MODE_EXIT) | |
730 | cleanup_cfg (CLEANUP_NO_INSN_DEL); | |
731 | #else | |
732 | if (!need_commit && !emited) | |
733 | return 0; | |
734 | #endif | |
735 | ||
2f138c1c | 736 | return 1; |
737 | } | |
77fce4cd | 738 | |
2f138c1c | 739 | #endif /* OPTIMIZE_MODE_SWITCHING */ |
77fce4cd | 740 | \f |
741 | static bool | |
742 | gate_mode_switching (void) | |
743 | { | |
744 | #ifdef OPTIMIZE_MODE_SWITCHING | |
745 | return true; | |
746 | #else | |
747 | return false; | |
748 | #endif | |
749 | } | |
750 | ||
2a1990e9 | 751 | static unsigned int |
77fce4cd | 752 | rest_of_handle_mode_switching (void) |
753 | { | |
754 | #ifdef OPTIMIZE_MODE_SWITCHING | |
3f5be5f4 | 755 | optimize_mode_switching (); |
77fce4cd | 756 | #endif /* OPTIMIZE_MODE_SWITCHING */ |
2a1990e9 | 757 | return 0; |
77fce4cd | 758 | } |
759 | ||
760 | ||
20099e35 | 761 | struct rtl_opt_pass pass_mode_switching = |
77fce4cd | 762 | { |
20099e35 | 763 | { |
764 | RTL_PASS, | |
b85ccd2c | 765 | "mode_sw", /* name */ |
77fce4cd | 766 | gate_mode_switching, /* gate */ |
767 | rest_of_handle_mode_switching, /* execute */ | |
768 | NULL, /* sub */ | |
769 | NULL, /* next */ | |
770 | 0, /* static_pass_number */ | |
771 | TV_MODE_SWITCH, /* tv_id */ | |
772 | 0, /* properties_required */ | |
773 | 0, /* properties_provided */ | |
774 | 0, /* properties_destroyed */ | |
775 | 0, /* todo_flags_start */ | |
0806b508 | 776 | TODO_df_finish | TODO_verify_rtl_sharing | |
20099e35 | 777 | TODO_dump_func /* todo_flags_finish */ |
778 | } | |
77fce4cd | 779 | }; |