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77c9c6c2 | 1 | /* Expand the basic unary and binary arithmetic operations, for GNU compiler. |
d050d723 | 2 | Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
146aef0b JJ |
3 | 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, |
4 | 2011 Free Software Foundation, Inc. | |
77c9c6c2 | 5 | |
1322177d | 6 | This file is part of GCC. |
77c9c6c2 | 7 | |
1322177d LB |
8 | GCC is free software; you can redistribute it and/or modify it under |
9 | the terms of the GNU General Public License as published by the Free | |
9dcd6f09 | 10 | Software Foundation; either version 3, or (at your option) any later |
1322177d | 11 | version. |
77c9c6c2 | 12 | |
1322177d LB |
13 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
14 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | for more details. | |
77c9c6c2 RK |
17 | |
18 | You should have received a copy of the GNU General Public License | |
9dcd6f09 NC |
19 | along with GCC; see the file COPYING3. If not see |
20 | <http://www.gnu.org/licenses/>. */ | |
77c9c6c2 RK |
21 | |
22 | ||
23 | #include "config.h" | |
670ee920 | 24 | #include "system.h" |
4977bab6 ZW |
25 | #include "coretypes.h" |
26 | #include "tm.h" | |
718f9c0f | 27 | #include "diagnostic-core.h" |
dff01034 KG |
28 | |
29 | /* Include insn-config.h before expr.h so that HAVE_conditional_move | |
dc297297 | 30 | is properly defined. */ |
dff01034 | 31 | #include "insn-config.h" |
77c9c6c2 RK |
32 | #include "rtl.h" |
33 | #include "tree.h" | |
6baf1cc8 | 34 | #include "tm_p.h" |
77c9c6c2 | 35 | #include "flags.h" |
49ad7cfa | 36 | #include "function.h" |
52a11cbf | 37 | #include "except.h" |
77c9c6c2 | 38 | #include "expr.h" |
e78d8e51 ZW |
39 | #include "optabs.h" |
40 | #include "libfuncs.h" | |
77c9c6c2 | 41 | #include "recog.h" |
2829c155 | 42 | #include "reload.h" |
87ff9c8e | 43 | #include "ggc.h" |
4a69cf79 | 44 | #include "basic-block.h" |
c15c90bb | 45 | #include "target.h" |
77c9c6c2 | 46 | |
4bcbfa03 | 47 | struct target_optabs default_target_optabs; |
3e9c326a | 48 | struct target_libfuncs default_target_libfuncs; |
4bcbfa03 RS |
49 | #if SWITCHABLE_TARGET |
50 | struct target_optabs *this_target_optabs = &default_target_optabs; | |
3e9c326a | 51 | struct target_libfuncs *this_target_libfuncs = &default_target_libfuncs; |
4bcbfa03 | 52 | #endif |
34220a12 | 53 | |
3e9c326a RS |
54 | #define libfunc_hash \ |
55 | (this_target_libfuncs->x_libfunc_hash) | |
19c3fc24 | 56 | |
377017c4 RK |
57 | /* Contains the optab used for each rtx code. */ |
58 | optab code_to_optab[NUM_RTX_CODE + 1]; | |
59 | ||
f90b7a5a PB |
60 | static void prepare_float_lib_cmp (rtx, rtx, enum rtx_code, rtx *, |
61 | enum machine_mode *); | |
9cce5b20 | 62 | static rtx expand_unop_direct (enum machine_mode, optab, rtx, rtx, int); |
842a431a | 63 | |
8a33f100 JH |
64 | /* Debug facility for use in GDB. */ |
65 | void debug_optab_libfuncs (void); | |
66 | ||
79b87c74 MM |
67 | /* Prefixes for the current version of decimal floating point (BID vs. DPD) */ |
68 | #if ENABLE_DECIMAL_BID_FORMAT | |
69 | #define DECIMAL_PREFIX "bid_" | |
70 | #else | |
71 | #define DECIMAL_PREFIX "dpd_" | |
72 | #endif | |
8a33f100 | 73 | \f |
3e9c326a | 74 | /* Used for libfunc_hash. */ |
8a33f100 JH |
75 | |
76 | static hashval_t | |
77 | hash_libfunc (const void *p) | |
78 | { | |
79 | const struct libfunc_entry *const e = (const struct libfunc_entry *) p; | |
80 | ||
81 | return (((int) e->mode1 + (int) e->mode2 * NUM_MACHINE_MODES) | |
a48b501c | 82 | ^ e->optab); |
8a33f100 JH |
83 | } |
84 | ||
3e9c326a | 85 | /* Used for libfunc_hash. */ |
8a33f100 JH |
86 | |
87 | static int | |
88 | eq_libfunc (const void *p, const void *q) | |
89 | { | |
90 | const struct libfunc_entry *const e1 = (const struct libfunc_entry *) p; | |
91 | const struct libfunc_entry *const e2 = (const struct libfunc_entry *) q; | |
92 | ||
93 | return (e1->optab == e2->optab | |
94 | && e1->mode1 == e2->mode1 | |
95 | && e1->mode2 == e2->mode2); | |
96 | } | |
97 | ||
98 | /* Return libfunc corresponding operation defined by OPTAB converting | |
99 | from MODE2 to MODE1. Trigger lazy initialization if needed, return NULL | |
100 | if no libfunc is available. */ | |
101 | rtx | |
102 | convert_optab_libfunc (convert_optab optab, enum machine_mode mode1, | |
103 | enum machine_mode mode2) | |
104 | { | |
105 | struct libfunc_entry e; | |
106 | struct libfunc_entry **slot; | |
107 | ||
33727b5e | 108 | e.optab = (size_t) (optab - &convert_optab_table[0]); |
8a33f100 JH |
109 | e.mode1 = mode1; |
110 | e.mode2 = mode2; | |
111 | slot = (struct libfunc_entry **) htab_find_slot (libfunc_hash, &e, NO_INSERT); | |
112 | if (!slot) | |
113 | { | |
114 | if (optab->libcall_gen) | |
115 | { | |
116 | optab->libcall_gen (optab, optab->libcall_basename, mode1, mode2); | |
117 | slot = (struct libfunc_entry **) htab_find_slot (libfunc_hash, &e, NO_INSERT); | |
118 | if (slot) | |
119 | return (*slot)->libfunc; | |
120 | else | |
121 | return NULL; | |
122 | } | |
123 | return NULL; | |
124 | } | |
125 | return (*slot)->libfunc; | |
126 | } | |
127 | ||
128 | /* Return libfunc corresponding operation defined by OPTAB in MODE. | |
129 | Trigger lazy initialization if needed, return NULL if no libfunc is | |
130 | available. */ | |
131 | rtx | |
132 | optab_libfunc (optab optab, enum machine_mode mode) | |
133 | { | |
134 | struct libfunc_entry e; | |
135 | struct libfunc_entry **slot; | |
136 | ||
33727b5e | 137 | e.optab = (size_t) (optab - &optab_table[0]); |
8a33f100 JH |
138 | e.mode1 = mode; |
139 | e.mode2 = VOIDmode; | |
140 | slot = (struct libfunc_entry **) htab_find_slot (libfunc_hash, &e, NO_INSERT); | |
141 | if (!slot) | |
142 | { | |
143 | if (optab->libcall_gen) | |
144 | { | |
145 | optab->libcall_gen (optab, optab->libcall_basename, | |
146 | optab->libcall_suffix, mode); | |
147 | slot = (struct libfunc_entry **) htab_find_slot (libfunc_hash, | |
148 | &e, NO_INSERT); | |
149 | if (slot) | |
150 | return (*slot)->libfunc; | |
151 | else | |
152 | return NULL; | |
153 | } | |
154 | return NULL; | |
155 | } | |
156 | return (*slot)->libfunc; | |
157 | } | |
79b87c74 | 158 | |
77c9c6c2 | 159 | \f |
2f937369 | 160 | /* Add a REG_EQUAL note to the last insn in INSNS. TARGET is being set to |
77c9c6c2 RK |
161 | the result of operation CODE applied to OP0 (and OP1 if it is a binary |
162 | operation). | |
163 | ||
164 | If the last insn does not set TARGET, don't do anything, but return 1. | |
165 | ||
166 | If a previous insn sets TARGET and TARGET is one of OP0 or OP1, | |
167 | don't add the REG_EQUAL note but return 0. Our caller can then try | |
168 | again, ensuring that TARGET is not one of the operands. */ | |
169 | ||
170 | static int | |
0c20a65f | 171 | add_equal_note (rtx insns, rtx target, enum rtx_code code, rtx op0, rtx op1) |
77c9c6c2 | 172 | { |
2f937369 | 173 | rtx last_insn, insn, set; |
77c9c6c2 RK |
174 | rtx note; |
175 | ||
e3feb571 | 176 | gcc_assert (insns && INSN_P (insns) && NEXT_INSN (insns)); |
2f937369 | 177 | |
ec8e098d PB |
178 | if (GET_RTX_CLASS (code) != RTX_COMM_ARITH |
179 | && GET_RTX_CLASS (code) != RTX_BIN_ARITH | |
180 | && GET_RTX_CLASS (code) != RTX_COMM_COMPARE | |
181 | && GET_RTX_CLASS (code) != RTX_COMPARE | |
182 | && GET_RTX_CLASS (code) != RTX_UNARY) | |
2f937369 DM |
183 | return 1; |
184 | ||
185 | if (GET_CODE (target) == ZERO_EXTRACT) | |
186 | return 1; | |
187 | ||
188 | for (last_insn = insns; | |
189 | NEXT_INSN (last_insn) != NULL_RTX; | |
190 | last_insn = NEXT_INSN (last_insn)) | |
191 | ; | |
192 | ||
193 | set = single_set (last_insn); | |
194 | if (set == NULL_RTX) | |
195 | return 1; | |
196 | ||
197 | if (! rtx_equal_p (SET_DEST (set), target) | |
f9d36a92 | 198 | /* For a STRICT_LOW_PART, the REG_NOTE applies to what is inside it. */ |
2f937369 | 199 | && (GET_CODE (SET_DEST (set)) != STRICT_LOW_PART |
f9d36a92 | 200 | || ! rtx_equal_p (XEXP (SET_DEST (set), 0), target))) |
77c9c6c2 RK |
201 | return 1; |
202 | ||
203 | /* If TARGET is in OP0 or OP1, check if anything in SEQ sets TARGET | |
204 | besides the last insn. */ | |
205 | if (reg_overlap_mentioned_p (target, op0) | |
206 | || (op1 && reg_overlap_mentioned_p (target, op1))) | |
2f937369 DM |
207 | { |
208 | insn = PREV_INSN (last_insn); | |
209 | while (insn != NULL_RTX) | |
210 | { | |
211 | if (reg_set_p (target, insn)) | |
212 | return 0; | |
213 | ||
214 | insn = PREV_INSN (insn); | |
215 | } | |
216 | } | |
77c9c6c2 | 217 | |
ec8e098d | 218 | if (GET_RTX_CLASS (code) == RTX_UNARY) |
9e6a5703 | 219 | note = gen_rtx_fmt_e (code, GET_MODE (target), copy_rtx (op0)); |
77c9c6c2 | 220 | else |
9e6a5703 | 221 | note = gen_rtx_fmt_ee (code, GET_MODE (target), copy_rtx (op0), copy_rtx (op1)); |
77c9c6c2 | 222 | |
2f937369 | 223 | set_unique_reg_note (last_insn, REG_EQUAL, note); |
77c9c6c2 RK |
224 | |
225 | return 1; | |
226 | } | |
227 | \f | |
835532b8 RK |
228 | /* Widen OP to MODE and return the rtx for the widened operand. UNSIGNEDP |
229 | says whether OP is signed or unsigned. NO_EXTEND is nonzero if we need | |
0c20a65f | 230 | not actually do a sign-extend or zero-extend, but can leave the |
835532b8 RK |
231 | higher-order bits of the result rtx undefined, for example, in the case |
232 | of logical operations, but not right shifts. */ | |
233 | ||
234 | static rtx | |
0c20a65f AJ |
235 | widen_operand (rtx op, enum machine_mode mode, enum machine_mode oldmode, |
236 | int unsignedp, int no_extend) | |
835532b8 RK |
237 | { |
238 | rtx result; | |
239 | ||
8041889f RK |
240 | /* If we don't have to extend and this is a constant, return it. */ |
241 | if (no_extend && GET_MODE (op) == VOIDmode) | |
242 | return op; | |
243 | ||
244 | /* If we must extend do so. If OP is a SUBREG for a promoted object, also | |
245 | extend since it will be more efficient to do so unless the signedness of | |
246 | a promoted object differs from our extension. */ | |
835532b8 | 247 | if (! no_extend |
cb8f73be RK |
248 | || (GET_CODE (op) == SUBREG && SUBREG_PROMOTED_VAR_P (op) |
249 | && SUBREG_PROMOTED_UNSIGNED_P (op) == unsignedp)) | |
0661a3de | 250 | return convert_modes (mode, oldmode, op, unsignedp); |
835532b8 RK |
251 | |
252 | /* If MODE is no wider than a single word, we return a paradoxical | |
253 | SUBREG. */ | |
254 | if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD) | |
9e6a5703 | 255 | return gen_rtx_SUBREG (mode, force_reg (GET_MODE (op), op), 0); |
835532b8 RK |
256 | |
257 | /* Otherwise, get an object of MODE, clobber it, and set the low-order | |
258 | part to OP. */ | |
259 | ||
260 | result = gen_reg_rtx (mode); | |
c41c1387 | 261 | emit_clobber (result); |
835532b8 RK |
262 | emit_move_insn (gen_lowpart (GET_MODE (op), result), op); |
263 | return result; | |
264 | } | |
265 | \f | |
71d46ca5 MM |
266 | /* Return the optab used for computing the operation given by the tree code, |
267 | CODE and the tree EXP. This function is not always usable (for example, it | |
268 | cannot give complete results for multiplication or division) but probably | |
269 | ought to be relied on more widely throughout the expander. */ | |
26277d41 | 270 | optab |
71d46ca5 MM |
271 | optab_for_tree_code (enum tree_code code, const_tree type, |
272 | enum optab_subtype subtype) | |
26277d41 PB |
273 | { |
274 | bool trapv; | |
275 | switch (code) | |
276 | { | |
277 | case BIT_AND_EXPR: | |
278 | return and_optab; | |
279 | ||
280 | case BIT_IOR_EXPR: | |
281 | return ior_optab; | |
282 | ||
283 | case BIT_NOT_EXPR: | |
284 | return one_cmpl_optab; | |
285 | ||
286 | case BIT_XOR_EXPR: | |
287 | return xor_optab; | |
288 | ||
289 | case TRUNC_MOD_EXPR: | |
290 | case CEIL_MOD_EXPR: | |
291 | case FLOOR_MOD_EXPR: | |
292 | case ROUND_MOD_EXPR: | |
293 | return TYPE_UNSIGNED (type) ? umod_optab : smod_optab; | |
294 | ||
295 | case RDIV_EXPR: | |
296 | case TRUNC_DIV_EXPR: | |
297 | case CEIL_DIV_EXPR: | |
298 | case FLOOR_DIV_EXPR: | |
299 | case ROUND_DIV_EXPR: | |
300 | case EXACT_DIV_EXPR: | |
0f996086 CF |
301 | if (TYPE_SATURATING(type)) |
302 | return TYPE_UNSIGNED(type) ? usdiv_optab : ssdiv_optab; | |
26277d41 PB |
303 | return TYPE_UNSIGNED (type) ? udiv_optab : sdiv_optab; |
304 | ||
305 | case LSHIFT_EXPR: | |
8750672f | 306 | if (TREE_CODE (type) == VECTOR_TYPE) |
71d46ca5 MM |
307 | { |
308 | if (subtype == optab_vector) | |
309 | return TYPE_SATURATING (type) ? NULL : vashl_optab; | |
310 | ||
311 | gcc_assert (subtype == optab_scalar); | |
312 | } | |
0f996086 CF |
313 | if (TYPE_SATURATING(type)) |
314 | return TYPE_UNSIGNED(type) ? usashl_optab : ssashl_optab; | |
26277d41 PB |
315 | return ashl_optab; |
316 | ||
317 | case RSHIFT_EXPR: | |
8750672f | 318 | if (TREE_CODE (type) == VECTOR_TYPE) |
71d46ca5 MM |
319 | { |
320 | if (subtype == optab_vector) | |
321 | return TYPE_UNSIGNED (type) ? vlshr_optab : vashr_optab; | |
322 | ||
323 | gcc_assert (subtype == optab_scalar); | |
324 | } | |
26277d41 PB |
325 | return TYPE_UNSIGNED (type) ? lshr_optab : ashr_optab; |
326 | ||
327 | case LROTATE_EXPR: | |
8750672f | 328 | if (TREE_CODE (type) == VECTOR_TYPE) |
71d46ca5 MM |
329 | { |
330 | if (subtype == optab_vector) | |
331 | return vrotl_optab; | |
332 | ||
333 | gcc_assert (subtype == optab_scalar); | |
334 | } | |
26277d41 PB |
335 | return rotl_optab; |
336 | ||
337 | case RROTATE_EXPR: | |
8750672f | 338 | if (TREE_CODE (type) == VECTOR_TYPE) |
71d46ca5 MM |
339 | { |
340 | if (subtype == optab_vector) | |
341 | return vrotr_optab; | |
342 | ||
343 | gcc_assert (subtype == optab_scalar); | |
344 | } | |
26277d41 PB |
345 | return rotr_optab; |
346 | ||
347 | case MAX_EXPR: | |
348 | return TYPE_UNSIGNED (type) ? umax_optab : smax_optab; | |
349 | ||
350 | case MIN_EXPR: | |
351 | return TYPE_UNSIGNED (type) ? umin_optab : smin_optab; | |
352 | ||
7ccf35ed DN |
353 | case REALIGN_LOAD_EXPR: |
354 | return vec_realign_load_optab; | |
355 | ||
20f06221 DN |
356 | case WIDEN_SUM_EXPR: |
357 | return TYPE_UNSIGNED (type) ? usum_widen_optab : ssum_widen_optab; | |
358 | ||
359 | case DOT_PROD_EXPR: | |
360 | return TYPE_UNSIGNED (type) ? udot_prod_optab : sdot_prod_optab; | |
361 | ||
0354c0c7 BS |
362 | case WIDEN_MULT_PLUS_EXPR: |
363 | return (TYPE_UNSIGNED (type) | |
364 | ? (TYPE_SATURATING (type) | |
365 | ? usmadd_widen_optab : umadd_widen_optab) | |
366 | : (TYPE_SATURATING (type) | |
367 | ? ssmadd_widen_optab : smadd_widen_optab)); | |
368 | ||
369 | case WIDEN_MULT_MINUS_EXPR: | |
370 | return (TYPE_UNSIGNED (type) | |
371 | ? (TYPE_SATURATING (type) | |
372 | ? usmsub_widen_optab : umsub_widen_optab) | |
373 | : (TYPE_SATURATING (type) | |
374 | ? ssmsub_widen_optab : smsub_widen_optab)); | |
375 | ||
16949072 RG |
376 | case FMA_EXPR: |
377 | return fma_optab; | |
378 | ||
61d3cdbb DN |
379 | case REDUC_MAX_EXPR: |
380 | return TYPE_UNSIGNED (type) ? reduc_umax_optab : reduc_smax_optab; | |
381 | ||
382 | case REDUC_MIN_EXPR: | |
383 | return TYPE_UNSIGNED (type) ? reduc_umin_optab : reduc_smin_optab; | |
384 | ||
385 | case REDUC_PLUS_EXPR: | |
a6b46ba2 DN |
386 | return TYPE_UNSIGNED (type) ? reduc_uplus_optab : reduc_splus_optab; |
387 | ||
388 | case VEC_LSHIFT_EXPR: | |
389 | return vec_shl_optab; | |
390 | ||
391 | case VEC_RSHIFT_EXPR: | |
392 | return vec_shr_optab; | |
61d3cdbb | 393 | |
89d67cca | 394 | case VEC_WIDEN_MULT_HI_EXPR: |
b8698a0f | 395 | return TYPE_UNSIGNED (type) ? |
89d67cca DN |
396 | vec_widen_umult_hi_optab : vec_widen_smult_hi_optab; |
397 | ||
398 | case VEC_WIDEN_MULT_LO_EXPR: | |
b8698a0f | 399 | return TYPE_UNSIGNED (type) ? |
89d67cca DN |
400 | vec_widen_umult_lo_optab : vec_widen_smult_lo_optab; |
401 | ||
402 | case VEC_UNPACK_HI_EXPR: | |
8115817b | 403 | return TYPE_UNSIGNED (type) ? |
89d67cca DN |
404 | vec_unpacku_hi_optab : vec_unpacks_hi_optab; |
405 | ||
406 | case VEC_UNPACK_LO_EXPR: | |
b8698a0f | 407 | return TYPE_UNSIGNED (type) ? |
89d67cca DN |
408 | vec_unpacku_lo_optab : vec_unpacks_lo_optab; |
409 | ||
d9987fb4 UB |
410 | case VEC_UNPACK_FLOAT_HI_EXPR: |
411 | /* The signedness is determined from input operand. */ | |
412 | return TYPE_UNSIGNED (type) ? | |
413 | vec_unpacku_float_hi_optab : vec_unpacks_float_hi_optab; | |
414 | ||
415 | case VEC_UNPACK_FLOAT_LO_EXPR: | |
416 | /* The signedness is determined from input operand. */ | |
b8698a0f | 417 | return TYPE_UNSIGNED (type) ? |
d9987fb4 UB |
418 | vec_unpacku_float_lo_optab : vec_unpacks_float_lo_optab; |
419 | ||
8115817b UB |
420 | case VEC_PACK_TRUNC_EXPR: |
421 | return vec_pack_trunc_optab; | |
422 | ||
89d67cca DN |
423 | case VEC_PACK_SAT_EXPR: |
424 | return TYPE_UNSIGNED (type) ? vec_pack_usat_optab : vec_pack_ssat_optab; | |
8115817b | 425 | |
d9987fb4 | 426 | case VEC_PACK_FIX_TRUNC_EXPR: |
9f106823 | 427 | /* The signedness is determined from output operand. */ |
d9987fb4 UB |
428 | return TYPE_UNSIGNED (type) ? |
429 | vec_pack_ufix_trunc_optab : vec_pack_sfix_trunc_optab; | |
430 | ||
26277d41 PB |
431 | default: |
432 | break; | |
433 | } | |
434 | ||
eeef0e45 | 435 | trapv = INTEGRAL_TYPE_P (type) && TYPE_OVERFLOW_TRAPS (type); |
26277d41 PB |
436 | switch (code) |
437 | { | |
5be014d5 | 438 | case POINTER_PLUS_EXPR: |
26277d41 | 439 | case PLUS_EXPR: |
0f996086 CF |
440 | if (TYPE_SATURATING(type)) |
441 | return TYPE_UNSIGNED(type) ? usadd_optab : ssadd_optab; | |
26277d41 PB |
442 | return trapv ? addv_optab : add_optab; |
443 | ||
444 | case MINUS_EXPR: | |
0f996086 CF |
445 | if (TYPE_SATURATING(type)) |
446 | return TYPE_UNSIGNED(type) ? ussub_optab : sssub_optab; | |
26277d41 PB |
447 | return trapv ? subv_optab : sub_optab; |
448 | ||
449 | case MULT_EXPR: | |
0f996086 CF |
450 | if (TYPE_SATURATING(type)) |
451 | return TYPE_UNSIGNED(type) ? usmul_optab : ssmul_optab; | |
26277d41 PB |
452 | return trapv ? smulv_optab : smul_optab; |
453 | ||
454 | case NEGATE_EXPR: | |
0f996086 CF |
455 | if (TYPE_SATURATING(type)) |
456 | return TYPE_UNSIGNED(type) ? usneg_optab : ssneg_optab; | |
26277d41 PB |
457 | return trapv ? negv_optab : neg_optab; |
458 | ||
459 | case ABS_EXPR: | |
460 | return trapv ? absv_optab : abs_optab; | |
461 | ||
98b44b0e IR |
462 | case VEC_EXTRACT_EVEN_EXPR: |
463 | return vec_extract_even_optab; | |
464 | ||
465 | case VEC_EXTRACT_ODD_EXPR: | |
466 | return vec_extract_odd_optab; | |
467 | ||
468 | case VEC_INTERLEAVE_HIGH_EXPR: | |
469 | return vec_interleave_high_optab; | |
470 | ||
471 | case VEC_INTERLEAVE_LOW_EXPR: | |
472 | return vec_interleave_low_optab; | |
473 | ||
26277d41 PB |
474 | default: |
475 | return NULL; | |
476 | } | |
477 | } | |
273a2526 | 478 | \f |
7ccf35ed | 479 | |
20f06221 DN |
480 | /* Expand vector widening operations. |
481 | ||
482 | There are two different classes of operations handled here: | |
483 | 1) Operations whose result is wider than all the arguments to the operation. | |
484 | Examples: VEC_UNPACK_HI/LO_EXPR, VEC_WIDEN_MULT_HI/LO_EXPR | |
485 | In this case OP0 and optionally OP1 would be initialized, | |
486 | but WIDE_OP wouldn't (not relevant for this case). | |
487 | 2) Operations whose result is of the same size as the last argument to the | |
488 | operation, but wider than all the other arguments to the operation. | |
489 | Examples: WIDEN_SUM_EXPR, VEC_DOT_PROD_EXPR. | |
490 | In the case WIDE_OP, OP0 and optionally OP1 would be initialized. | |
491 | ||
492 | E.g, when called to expand the following operations, this is how | |
493 | the arguments will be initialized: | |
494 | nops OP0 OP1 WIDE_OP | |
b8698a0f | 495 | widening-sum 2 oprnd0 - oprnd1 |
20f06221 DN |
496 | widening-dot-product 3 oprnd0 oprnd1 oprnd2 |
497 | widening-mult 2 oprnd0 oprnd1 - | |
498 | type-promotion (vec-unpack) 1 oprnd0 - - */ | |
499 | ||
500 | rtx | |
8e7aa1f9 MM |
501 | expand_widen_pattern_expr (sepops ops, rtx op0, rtx op1, rtx wide_op, |
502 | rtx target, int unsignedp) | |
b8698a0f | 503 | { |
a5c7d693 | 504 | struct expand_operand eops[4]; |
20f06221 | 505 | tree oprnd0, oprnd1, oprnd2; |
81f40b79 | 506 | enum machine_mode wmode = VOIDmode, tmode0, tmode1 = VOIDmode; |
20f06221 | 507 | optab widen_pattern_optab; |
a5c7d693 | 508 | enum insn_code icode; |
8e7aa1f9 | 509 | int nops = TREE_CODE_LENGTH (ops->code); |
a5c7d693 | 510 | int op; |
20f06221 | 511 | |
8e7aa1f9 | 512 | oprnd0 = ops->op0; |
20f06221 DN |
513 | tmode0 = TYPE_MODE (TREE_TYPE (oprnd0)); |
514 | widen_pattern_optab = | |
8e7aa1f9 | 515 | optab_for_tree_code (ops->code, TREE_TYPE (oprnd0), optab_default); |
0354c0c7 BS |
516 | if (ops->code == WIDEN_MULT_PLUS_EXPR |
517 | || ops->code == WIDEN_MULT_MINUS_EXPR) | |
a5c7d693 RS |
518 | icode = optab_handler (widen_pattern_optab, |
519 | TYPE_MODE (TREE_TYPE (ops->op2))); | |
0354c0c7 | 520 | else |
a5c7d693 | 521 | icode = optab_handler (widen_pattern_optab, tmode0); |
20f06221 | 522 | gcc_assert (icode != CODE_FOR_nothing); |
20f06221 DN |
523 | |
524 | if (nops >= 2) | |
525 | { | |
8e7aa1f9 | 526 | oprnd1 = ops->op1; |
20f06221 | 527 | tmode1 = TYPE_MODE (TREE_TYPE (oprnd1)); |
20f06221 DN |
528 | } |
529 | ||
530 | /* The last operand is of a wider mode than the rest of the operands. */ | |
531 | if (nops == 2) | |
a5c7d693 | 532 | wmode = tmode1; |
20f06221 DN |
533 | else if (nops == 3) |
534 | { | |
535 | gcc_assert (tmode1 == tmode0); | |
536 | gcc_assert (op1); | |
8e7aa1f9 | 537 | oprnd2 = ops->op2; |
20f06221 | 538 | wmode = TYPE_MODE (TREE_TYPE (oprnd2)); |
20f06221 DN |
539 | } |
540 | ||
a5c7d693 RS |
541 | op = 0; |
542 | create_output_operand (&eops[op++], target, TYPE_MODE (ops->type)); | |
543 | create_convert_operand_from (&eops[op++], op0, tmode0, unsignedp); | |
20f06221 | 544 | if (op1) |
a5c7d693 | 545 | create_convert_operand_from (&eops[op++], op1, tmode1, unsignedp); |
20f06221 | 546 | if (wide_op) |
a5c7d693 RS |
547 | create_convert_operand_from (&eops[op++], wide_op, wmode, unsignedp); |
548 | expand_insn (icode, op, eops); | |
549 | return eops[0].value; | |
20f06221 DN |
550 | } |
551 | ||
7ccf35ed DN |
552 | /* Generate code to perform an operation specified by TERNARY_OPTAB |
553 | on operands OP0, OP1 and OP2, with result having machine-mode MODE. | |
554 | ||
555 | UNSIGNEDP is for the case where we have to widen the operands | |
556 | to perform the operation. It says to use zero-extension. | |
557 | ||
558 | If TARGET is nonzero, the value | |
559 | is generated there, if it is convenient to do so. | |
560 | In all cases an rtx is returned for the locus of the value; | |
561 | this may or may not be TARGET. */ | |
562 | ||
563 | rtx | |
c414ac1d EC |
564 | expand_ternary_op (enum machine_mode mode, optab ternary_optab, rtx op0, |
565 | rtx op1, rtx op2, rtx target, int unsignedp) | |
7ccf35ed | 566 | { |
a5c7d693 RS |
567 | struct expand_operand ops[4]; |
568 | enum insn_code icode = optab_handler (ternary_optab, mode); | |
7ccf35ed | 569 | |
947131ba | 570 | gcc_assert (optab_handler (ternary_optab, mode) != CODE_FOR_nothing); |
7ccf35ed | 571 | |
a5c7d693 RS |
572 | create_output_operand (&ops[0], target, mode); |
573 | create_convert_operand_from (&ops[1], op0, mode, unsignedp); | |
574 | create_convert_operand_from (&ops[2], op1, mode, unsignedp); | |
575 | create_convert_operand_from (&ops[3], op2, mode, unsignedp); | |
576 | expand_insn (icode, 4, ops); | |
577 | return ops[0].value; | |
7ccf35ed DN |
578 | } |
579 | ||
580 | ||
273a2526 RS |
581 | /* Like expand_binop, but return a constant rtx if the result can be |
582 | calculated at compile time. The arguments and return value are | |
583 | otherwise the same as for expand_binop. */ | |
584 | ||
585 | static rtx | |
586 | simplify_expand_binop (enum machine_mode mode, optab binoptab, | |
587 | rtx op0, rtx op1, rtx target, int unsignedp, | |
588 | enum optab_methods methods) | |
589 | { | |
590 | if (CONSTANT_P (op0) && CONSTANT_P (op1)) | |
68162a97 ILT |
591 | { |
592 | rtx x = simplify_binary_operation (binoptab->code, mode, op0, op1); | |
593 | ||
594 | if (x) | |
595 | return x; | |
596 | } | |
597 | ||
598 | return expand_binop (mode, binoptab, op0, op1, target, unsignedp, methods); | |
273a2526 RS |
599 | } |
600 | ||
601 | /* Like simplify_expand_binop, but always put the result in TARGET. | |
602 | Return true if the expansion succeeded. */ | |
603 | ||
bef5d8b6 | 604 | bool |
273a2526 RS |
605 | force_expand_binop (enum machine_mode mode, optab binoptab, |
606 | rtx op0, rtx op1, rtx target, int unsignedp, | |
607 | enum optab_methods methods) | |
608 | { | |
609 | rtx x = simplify_expand_binop (mode, binoptab, op0, op1, | |
610 | target, unsignedp, methods); | |
611 | if (x == 0) | |
612 | return false; | |
613 | if (x != target) | |
614 | emit_move_insn (target, x); | |
615 | return true; | |
616 | } | |
617 | ||
a6b46ba2 DN |
618 | /* Generate insns for VEC_LSHIFT_EXPR, VEC_RSHIFT_EXPR. */ |
619 | ||
620 | rtx | |
8e7aa1f9 | 621 | expand_vec_shift_expr (sepops ops, rtx target) |
a6b46ba2 | 622 | { |
a5c7d693 | 623 | struct expand_operand eops[3]; |
a6b46ba2 DN |
624 | enum insn_code icode; |
625 | rtx rtx_op1, rtx_op2; | |
8e7aa1f9 MM |
626 | enum machine_mode mode = TYPE_MODE (ops->type); |
627 | tree vec_oprnd = ops->op0; | |
628 | tree shift_oprnd = ops->op1; | |
a6b46ba2 | 629 | optab shift_optab; |
a6b46ba2 | 630 | |
8e7aa1f9 | 631 | switch (ops->code) |
a6b46ba2 DN |
632 | { |
633 | case VEC_RSHIFT_EXPR: | |
634 | shift_optab = vec_shr_optab; | |
635 | break; | |
636 | case VEC_LSHIFT_EXPR: | |
637 | shift_optab = vec_shl_optab; | |
638 | break; | |
639 | default: | |
640 | gcc_unreachable (); | |
641 | } | |
642 | ||
947131ba | 643 | icode = optab_handler (shift_optab, mode); |
a6b46ba2 DN |
644 | gcc_assert (icode != CODE_FOR_nothing); |
645 | ||
49452c07 | 646 | rtx_op1 = expand_normal (vec_oprnd); |
49452c07 | 647 | rtx_op2 = expand_normal (shift_oprnd); |
a6b46ba2 | 648 | |
a5c7d693 RS |
649 | create_output_operand (&eops[0], target, mode); |
650 | create_input_operand (&eops[1], rtx_op1, GET_MODE (rtx_op1)); | |
651 | create_convert_operand_from_type (&eops[2], rtx_op2, TREE_TYPE (shift_oprnd)); | |
652 | expand_insn (icode, 3, eops); | |
a6b46ba2 | 653 | |
a5c7d693 | 654 | return eops[0].value; |
a6b46ba2 DN |
655 | } |
656 | ||
273a2526 RS |
657 | /* This subroutine of expand_doubleword_shift handles the cases in which |
658 | the effective shift value is >= BITS_PER_WORD. The arguments and return | |
659 | value are the same as for the parent routine, except that SUPERWORD_OP1 | |
660 | is the shift count to use when shifting OUTOF_INPUT into INTO_TARGET. | |
661 | INTO_TARGET may be null if the caller has decided to calculate it. */ | |
662 | ||
663 | static bool | |
664 | expand_superword_shift (optab binoptab, rtx outof_input, rtx superword_op1, | |
665 | rtx outof_target, rtx into_target, | |
666 | int unsignedp, enum optab_methods methods) | |
667 | { | |
668 | if (into_target != 0) | |
669 | if (!force_expand_binop (word_mode, binoptab, outof_input, superword_op1, | |
670 | into_target, unsignedp, methods)) | |
671 | return false; | |
672 | ||
673 | if (outof_target != 0) | |
674 | { | |
675 | /* For a signed right shift, we must fill OUTOF_TARGET with copies | |
676 | of the sign bit, otherwise we must fill it with zeros. */ | |
677 | if (binoptab != ashr_optab) | |
678 | emit_move_insn (outof_target, CONST0_RTX (word_mode)); | |
679 | else | |
680 | if (!force_expand_binop (word_mode, binoptab, | |
681 | outof_input, GEN_INT (BITS_PER_WORD - 1), | |
682 | outof_target, unsignedp, methods)) | |
683 | return false; | |
684 | } | |
685 | return true; | |
686 | } | |
687 | ||
688 | /* This subroutine of expand_doubleword_shift handles the cases in which | |
689 | the effective shift value is < BITS_PER_WORD. The arguments and return | |
690 | value are the same as for the parent routine. */ | |
691 | ||
692 | static bool | |
693 | expand_subword_shift (enum machine_mode op1_mode, optab binoptab, | |
694 | rtx outof_input, rtx into_input, rtx op1, | |
695 | rtx outof_target, rtx into_target, | |
696 | int unsignedp, enum optab_methods methods, | |
697 | unsigned HOST_WIDE_INT shift_mask) | |
698 | { | |
699 | optab reverse_unsigned_shift, unsigned_shift; | |
700 | rtx tmp, carries; | |
701 | ||
702 | reverse_unsigned_shift = (binoptab == ashl_optab ? lshr_optab : ashl_optab); | |
703 | unsigned_shift = (binoptab == ashl_optab ? ashl_optab : lshr_optab); | |
704 | ||
705 | /* The low OP1 bits of INTO_TARGET come from the high bits of OUTOF_INPUT. | |
706 | We therefore need to shift OUTOF_INPUT by (BITS_PER_WORD - OP1) bits in | |
707 | the opposite direction to BINOPTAB. */ | |
708 | if (CONSTANT_P (op1) || shift_mask >= BITS_PER_WORD) | |
709 | { | |
710 | carries = outof_input; | |
711 | tmp = immed_double_const (BITS_PER_WORD, 0, op1_mode); | |
712 | tmp = simplify_expand_binop (op1_mode, sub_optab, tmp, op1, | |
713 | 0, true, methods); | |
714 | } | |
715 | else | |
716 | { | |
717 | /* We must avoid shifting by BITS_PER_WORD bits since that is either | |
718 | the same as a zero shift (if shift_mask == BITS_PER_WORD - 1) or | |
b01d837f | 719 | has unknown behavior. Do a single shift first, then shift by the |
273a2526 RS |
720 | remainder. It's OK to use ~OP1 as the remainder if shift counts |
721 | are truncated to the mode size. */ | |
722 | carries = expand_binop (word_mode, reverse_unsigned_shift, | |
723 | outof_input, const1_rtx, 0, unsignedp, methods); | |
724 | if (shift_mask == BITS_PER_WORD - 1) | |
725 | { | |
726 | tmp = immed_double_const (-1, -1, op1_mode); | |
727 | tmp = simplify_expand_binop (op1_mode, xor_optab, op1, tmp, | |
728 | 0, true, methods); | |
729 | } | |
730 | else | |
731 | { | |
732 | tmp = immed_double_const (BITS_PER_WORD - 1, 0, op1_mode); | |
733 | tmp = simplify_expand_binop (op1_mode, sub_optab, tmp, op1, | |
734 | 0, true, methods); | |
735 | } | |
736 | } | |
737 | if (tmp == 0 || carries == 0) | |
738 | return false; | |
739 | carries = expand_binop (word_mode, reverse_unsigned_shift, | |
740 | carries, tmp, 0, unsignedp, methods); | |
741 | if (carries == 0) | |
742 | return false; | |
743 | ||
744 | /* Shift INTO_INPUT logically by OP1. This is the last use of INTO_INPUT | |
745 | so the result can go directly into INTO_TARGET if convenient. */ | |
746 | tmp = expand_binop (word_mode, unsigned_shift, into_input, op1, | |
747 | into_target, unsignedp, methods); | |
748 | if (tmp == 0) | |
749 | return false; | |
750 | ||
751 | /* Now OR in the bits carried over from OUTOF_INPUT. */ | |
752 | if (!force_expand_binop (word_mode, ior_optab, tmp, carries, | |
753 | into_target, unsignedp, methods)) | |
754 | return false; | |
755 | ||
756 | /* Use a standard word_mode shift for the out-of half. */ | |
757 | if (outof_target != 0) | |
758 | if (!force_expand_binop (word_mode, binoptab, outof_input, op1, | |
759 | outof_target, unsignedp, methods)) | |
760 | return false; | |
761 | ||
762 | return true; | |
763 | } | |
764 | ||
765 | ||
766 | #ifdef HAVE_conditional_move | |
767 | /* Try implementing expand_doubleword_shift using conditional moves. | |
768 | The shift is by < BITS_PER_WORD if (CMP_CODE CMP1 CMP2) is true, | |
769 | otherwise it is by >= BITS_PER_WORD. SUBWORD_OP1 and SUPERWORD_OP1 | |
770 | are the shift counts to use in the former and latter case. All other | |
771 | arguments are the same as the parent routine. */ | |
772 | ||
773 | static bool | |
774 | expand_doubleword_shift_condmove (enum machine_mode op1_mode, optab binoptab, | |
775 | enum rtx_code cmp_code, rtx cmp1, rtx cmp2, | |
776 | rtx outof_input, rtx into_input, | |
777 | rtx subword_op1, rtx superword_op1, | |
778 | rtx outof_target, rtx into_target, | |
779 | int unsignedp, enum optab_methods methods, | |
780 | unsigned HOST_WIDE_INT shift_mask) | |
781 | { | |
782 | rtx outof_superword, into_superword; | |
783 | ||
784 | /* Put the superword version of the output into OUTOF_SUPERWORD and | |
785 | INTO_SUPERWORD. */ | |
786 | outof_superword = outof_target != 0 ? gen_reg_rtx (word_mode) : 0; | |
787 | if (outof_target != 0 && subword_op1 == superword_op1) | |
788 | { | |
789 | /* The value INTO_TARGET >> SUBWORD_OP1, which we later store in | |
790 | OUTOF_TARGET, is the same as the value of INTO_SUPERWORD. */ | |
791 | into_superword = outof_target; | |
792 | if (!expand_superword_shift (binoptab, outof_input, superword_op1, | |
793 | outof_superword, 0, unsignedp, methods)) | |
794 | return false; | |
795 | } | |
796 | else | |
797 | { | |
798 | into_superword = gen_reg_rtx (word_mode); | |
799 | if (!expand_superword_shift (binoptab, outof_input, superword_op1, | |
800 | outof_superword, into_superword, | |
801 | unsignedp, methods)) | |
802 | return false; | |
803 | } | |
26277d41 | 804 | |
273a2526 RS |
805 | /* Put the subword version directly in OUTOF_TARGET and INTO_TARGET. */ |
806 | if (!expand_subword_shift (op1_mode, binoptab, | |
807 | outof_input, into_input, subword_op1, | |
808 | outof_target, into_target, | |
809 | unsignedp, methods, shift_mask)) | |
810 | return false; | |
811 | ||
812 | /* Select between them. Do the INTO half first because INTO_SUPERWORD | |
813 | might be the current value of OUTOF_TARGET. */ | |
814 | if (!emit_conditional_move (into_target, cmp_code, cmp1, cmp2, op1_mode, | |
815 | into_target, into_superword, word_mode, false)) | |
816 | return false; | |
817 | ||
818 | if (outof_target != 0) | |
819 | if (!emit_conditional_move (outof_target, cmp_code, cmp1, cmp2, op1_mode, | |
820 | outof_target, outof_superword, | |
821 | word_mode, false)) | |
822 | return false; | |
823 | ||
824 | return true; | |
825 | } | |
826 | #endif | |
827 | ||
828 | /* Expand a doubleword shift (ashl, ashr or lshr) using word-mode shifts. | |
829 | OUTOF_INPUT and INTO_INPUT are the two word-sized halves of the first | |
830 | input operand; the shift moves bits in the direction OUTOF_INPUT-> | |
831 | INTO_TARGET. OUTOF_TARGET and INTO_TARGET are the equivalent words | |
832 | of the target. OP1 is the shift count and OP1_MODE is its mode. | |
833 | If OP1 is constant, it will have been truncated as appropriate | |
834 | and is known to be nonzero. | |
835 | ||
836 | If SHIFT_MASK is zero, the result of word shifts is undefined when the | |
837 | shift count is outside the range [0, BITS_PER_WORD). This routine must | |
838 | avoid generating such shifts for OP1s in the range [0, BITS_PER_WORD * 2). | |
839 | ||
840 | If SHIFT_MASK is nonzero, all word-mode shift counts are effectively | |
841 | masked by it and shifts in the range [BITS_PER_WORD, SHIFT_MASK) will | |
842 | fill with zeros or sign bits as appropriate. | |
843 | ||
2a7e31df | 844 | If SHIFT_MASK is BITS_PER_WORD - 1, this routine will synthesize |
273a2526 RS |
845 | a doubleword shift whose equivalent mask is BITS_PER_WORD * 2 - 1. |
846 | Doing this preserves semantics required by SHIFT_COUNT_TRUNCATED. | |
847 | In all other cases, shifts by values outside [0, BITS_PER_UNIT * 2) | |
848 | are undefined. | |
849 | ||
850 | BINOPTAB, UNSIGNEDP and METHODS are as for expand_binop. This function | |
851 | may not use INTO_INPUT after modifying INTO_TARGET, and similarly for | |
852 | OUTOF_INPUT and OUTOF_TARGET. OUTOF_TARGET can be null if the parent | |
853 | function wants to calculate it itself. | |
854 | ||
855 | Return true if the shift could be successfully synthesized. */ | |
856 | ||
857 | static bool | |
858 | expand_doubleword_shift (enum machine_mode op1_mode, optab binoptab, | |
859 | rtx outof_input, rtx into_input, rtx op1, | |
860 | rtx outof_target, rtx into_target, | |
861 | int unsignedp, enum optab_methods methods, | |
862 | unsigned HOST_WIDE_INT shift_mask) | |
863 | { | |
864 | rtx superword_op1, tmp, cmp1, cmp2; | |
865 | rtx subword_label, done_label; | |
866 | enum rtx_code cmp_code; | |
867 | ||
868 | /* See if word-mode shifts by BITS_PER_WORD...BITS_PER_WORD * 2 - 1 will | |
869 | fill the result with sign or zero bits as appropriate. If so, the value | |
870 | of OUTOF_TARGET will always be (SHIFT OUTOF_INPUT OP1). Recursively call | |
871 | this routine to calculate INTO_TARGET (which depends on both OUTOF_INPUT | |
872 | and INTO_INPUT), then emit code to set up OUTOF_TARGET. | |
873 | ||
874 | This isn't worthwhile for constant shifts since the optimizers will | |
875 | cope better with in-range shift counts. */ | |
876 | if (shift_mask >= BITS_PER_WORD | |
877 | && outof_target != 0 | |
878 | && !CONSTANT_P (op1)) | |
879 | { | |
880 | if (!expand_doubleword_shift (op1_mode, binoptab, | |
881 | outof_input, into_input, op1, | |
882 | 0, into_target, | |
883 | unsignedp, methods, shift_mask)) | |
884 | return false; | |
885 | if (!force_expand_binop (word_mode, binoptab, outof_input, op1, | |
886 | outof_target, unsignedp, methods)) | |
887 | return false; | |
888 | return true; | |
889 | } | |
890 | ||
891 | /* Set CMP_CODE, CMP1 and CMP2 so that the rtx (CMP_CODE CMP1 CMP2) | |
892 | is true when the effective shift value is less than BITS_PER_WORD. | |
893 | Set SUPERWORD_OP1 to the shift count that should be used to shift | |
894 | OUTOF_INPUT into INTO_TARGET when the condition is false. */ | |
895 | tmp = immed_double_const (BITS_PER_WORD, 0, op1_mode); | |
896 | if (!CONSTANT_P (op1) && shift_mask == BITS_PER_WORD - 1) | |
897 | { | |
898 | /* Set CMP1 to OP1 & BITS_PER_WORD. The result is zero iff OP1 | |
899 | is a subword shift count. */ | |
900 | cmp1 = simplify_expand_binop (op1_mode, and_optab, op1, tmp, | |
901 | 0, true, methods); | |
902 | cmp2 = CONST0_RTX (op1_mode); | |
903 | cmp_code = EQ; | |
904 | superword_op1 = op1; | |
905 | } | |
906 | else | |
907 | { | |
908 | /* Set CMP1 to OP1 - BITS_PER_WORD. */ | |
909 | cmp1 = simplify_expand_binop (op1_mode, sub_optab, op1, tmp, | |
910 | 0, true, methods); | |
911 | cmp2 = CONST0_RTX (op1_mode); | |
912 | cmp_code = LT; | |
913 | superword_op1 = cmp1; | |
914 | } | |
915 | if (cmp1 == 0) | |
916 | return false; | |
917 | ||
918 | /* If we can compute the condition at compile time, pick the | |
919 | appropriate subroutine. */ | |
920 | tmp = simplify_relational_operation (cmp_code, SImode, op1_mode, cmp1, cmp2); | |
481683e1 | 921 | if (tmp != 0 && CONST_INT_P (tmp)) |
273a2526 RS |
922 | { |
923 | if (tmp == const0_rtx) | |
924 | return expand_superword_shift (binoptab, outof_input, superword_op1, | |
925 | outof_target, into_target, | |
926 | unsignedp, methods); | |
927 | else | |
928 | return expand_subword_shift (op1_mode, binoptab, | |
929 | outof_input, into_input, op1, | |
930 | outof_target, into_target, | |
931 | unsignedp, methods, shift_mask); | |
932 | } | |
933 | ||
934 | #ifdef HAVE_conditional_move | |
935 | /* Try using conditional moves to generate straight-line code. */ | |
936 | { | |
937 | rtx start = get_last_insn (); | |
938 | if (expand_doubleword_shift_condmove (op1_mode, binoptab, | |
939 | cmp_code, cmp1, cmp2, | |
940 | outof_input, into_input, | |
941 | op1, superword_op1, | |
942 | outof_target, into_target, | |
943 | unsignedp, methods, shift_mask)) | |
944 | return true; | |
945 | delete_insns_since (start); | |
946 | } | |
947 | #endif | |
948 | ||
949 | /* As a last resort, use branches to select the correct alternative. */ | |
950 | subword_label = gen_label_rtx (); | |
951 | done_label = gen_label_rtx (); | |
952 | ||
2763a67e | 953 | NO_DEFER_POP; |
273a2526 | 954 | do_compare_rtx_and_jump (cmp1, cmp2, cmp_code, false, op1_mode, |
40e90eac | 955 | 0, 0, subword_label, -1); |
2763a67e | 956 | OK_DEFER_POP; |
273a2526 RS |
957 | |
958 | if (!expand_superword_shift (binoptab, outof_input, superword_op1, | |
959 | outof_target, into_target, | |
960 | unsignedp, methods)) | |
961 | return false; | |
962 | ||
963 | emit_jump_insn (gen_jump (done_label)); | |
964 | emit_barrier (); | |
965 | emit_label (subword_label); | |
966 | ||
967 | if (!expand_subword_shift (op1_mode, binoptab, | |
968 | outof_input, into_input, op1, | |
969 | outof_target, into_target, | |
970 | unsignedp, methods, shift_mask)) | |
971 | return false; | |
972 | ||
973 | emit_label (done_label); | |
974 | return true; | |
975 | } | |
c64f913e | 976 | \f |
f927760b RS |
977 | /* Subroutine of expand_binop. Perform a double word multiplication of |
978 | operands OP0 and OP1 both of mode MODE, which is exactly twice as wide | |
979 | as the target's word_mode. This function return NULL_RTX if anything | |
980 | goes wrong, in which case it may have already emitted instructions | |
981 | which need to be deleted. | |
982 | ||
983 | If we want to multiply two two-word values and have normal and widening | |
984 | multiplies of single-word values, we can do this with three smaller | |
d70dcf29 | 985 | multiplications. |
f927760b RS |
986 | |
987 | The multiplication proceeds as follows: | |
988 | _______________________ | |
989 | [__op0_high_|__op0_low__] | |
990 | _______________________ | |
991 | * [__op1_high_|__op1_low__] | |
992 | _______________________________________________ | |
993 | _______________________ | |
994 | (1) [__op0_low__*__op1_low__] | |
995 | _______________________ | |
996 | (2a) [__op0_low__*__op1_high_] | |
997 | _______________________ | |
998 | (2b) [__op0_high_*__op1_low__] | |
999 | _______________________ | |
1000 | (3) [__op0_high_*__op1_high_] | |
1001 | ||
1002 | ||
1003 | This gives a 4-word result. Since we are only interested in the | |
1004 | lower 2 words, partial result (3) and the upper words of (2a) and | |
1005 | (2b) don't need to be calculated. Hence (2a) and (2b) can be | |
1006 | calculated using non-widening multiplication. | |
1007 | ||
1008 | (1), however, needs to be calculated with an unsigned widening | |
1009 | multiplication. If this operation is not directly supported we | |
1010 | try using a signed widening multiplication and adjust the result. | |
1011 | This adjustment works as follows: | |
1012 | ||
1013 | If both operands are positive then no adjustment is needed. | |
1014 | ||
1015 | If the operands have different signs, for example op0_low < 0 and | |
1016 | op1_low >= 0, the instruction treats the most significant bit of | |
1017 | op0_low as a sign bit instead of a bit with significance | |
1018 | 2**(BITS_PER_WORD-1), i.e. the instruction multiplies op1_low | |
1019 | with 2**BITS_PER_WORD - op0_low, and two's complements the | |
1020 | result. Conclusion: We need to add op1_low * 2**BITS_PER_WORD to | |
1021 | the result. | |
1022 | ||
1023 | Similarly, if both operands are negative, we need to add | |
1024 | (op0_low + op1_low) * 2**BITS_PER_WORD. | |
1025 | ||
1026 | We use a trick to adjust quickly. We logically shift op0_low right | |
1027 | (op1_low) BITS_PER_WORD-1 steps to get 0 or 1, and add this to | |
1028 | op0_high (op1_high) before it is used to calculate 2b (2a). If no | |
1029 | logical shift exists, we do an arithmetic right shift and subtract | |
1030 | the 0 or -1. */ | |
1031 | ||
1032 | static rtx | |
1033 | expand_doubleword_mult (enum machine_mode mode, rtx op0, rtx op1, rtx target, | |
1034 | bool umulp, enum optab_methods methods) | |
1035 | { | |
1036 | int low = (WORDS_BIG_ENDIAN ? 1 : 0); | |
1037 | int high = (WORDS_BIG_ENDIAN ? 0 : 1); | |
1038 | rtx wordm1 = umulp ? NULL_RTX : GEN_INT (BITS_PER_WORD - 1); | |
1039 | rtx product, adjust, product_high, temp; | |
1040 | ||
1041 | rtx op0_high = operand_subword_force (op0, high, mode); | |
1042 | rtx op0_low = operand_subword_force (op0, low, mode); | |
1043 | rtx op1_high = operand_subword_force (op1, high, mode); | |
1044 | rtx op1_low = operand_subword_force (op1, low, mode); | |
1045 | ||
1046 | /* If we're using an unsigned multiply to directly compute the product | |
1047 | of the low-order words of the operands and perform any required | |
1048 | adjustments of the operands, we begin by trying two more multiplications | |
1049 | and then computing the appropriate sum. | |
1050 | ||
1051 | We have checked above that the required addition is provided. | |
1052 | Full-word addition will normally always succeed, especially if | |
1053 | it is provided at all, so we don't worry about its failure. The | |
1054 | multiplication may well fail, however, so we do handle that. */ | |
1055 | ||
1056 | if (!umulp) | |
1057 | { | |
1058 | /* ??? This could be done with emit_store_flag where available. */ | |
1059 | temp = expand_binop (word_mode, lshr_optab, op0_low, wordm1, | |
1060 | NULL_RTX, 1, methods); | |
1061 | if (temp) | |
1062 | op0_high = expand_binop (word_mode, add_optab, op0_high, temp, | |
69f39b11 | 1063 | NULL_RTX, 0, OPTAB_DIRECT); |
f927760b RS |
1064 | else |
1065 | { | |
1066 | temp = expand_binop (word_mode, ashr_optab, op0_low, wordm1, | |
1067 | NULL_RTX, 0, methods); | |
1068 | if (!temp) | |
1069 | return NULL_RTX; | |
1070 | op0_high = expand_binop (word_mode, sub_optab, op0_high, temp, | |
69f39b11 | 1071 | NULL_RTX, 0, OPTAB_DIRECT); |
f927760b RS |
1072 | } |
1073 | ||
1074 | if (!op0_high) | |
1075 | return NULL_RTX; | |
1076 | } | |
1077 | ||
1078 | adjust = expand_binop (word_mode, smul_optab, op0_high, op1_low, | |
1079 | NULL_RTX, 0, OPTAB_DIRECT); | |
1080 | if (!adjust) | |
1081 | return NULL_RTX; | |
1082 | ||
1083 | /* OP0_HIGH should now be dead. */ | |
1084 | ||
1085 | if (!umulp) | |
1086 | { | |
1087 | /* ??? This could be done with emit_store_flag where available. */ | |
1088 | temp = expand_binop (word_mode, lshr_optab, op1_low, wordm1, | |
1089 | NULL_RTX, 1, methods); | |
1090 | if (temp) | |
1091 | op1_high = expand_binop (word_mode, add_optab, op1_high, temp, | |
69f39b11 | 1092 | NULL_RTX, 0, OPTAB_DIRECT); |
f927760b RS |
1093 | else |
1094 | { | |
1095 | temp = expand_binop (word_mode, ashr_optab, op1_low, wordm1, | |
1096 | NULL_RTX, 0, methods); | |
1097 | if (!temp) | |
1098 | return NULL_RTX; | |
1099 | op1_high = expand_binop (word_mode, sub_optab, op1_high, temp, | |
69f39b11 | 1100 | NULL_RTX, 0, OPTAB_DIRECT); |
f927760b RS |
1101 | } |
1102 | ||
1103 | if (!op1_high) | |
1104 | return NULL_RTX; | |
1105 | } | |
1106 | ||
1107 | temp = expand_binop (word_mode, smul_optab, op1_high, op0_low, | |
1108 | NULL_RTX, 0, OPTAB_DIRECT); | |
1109 | if (!temp) | |
1110 | return NULL_RTX; | |
1111 | ||
1112 | /* OP1_HIGH should now be dead. */ | |
1113 | ||
1114 | adjust = expand_binop (word_mode, add_optab, adjust, temp, | |
c701e857 | 1115 | NULL_RTX, 0, OPTAB_DIRECT); |
f927760b RS |
1116 | |
1117 | if (target && !REG_P (target)) | |
1118 | target = NULL_RTX; | |
1119 | ||
1120 | if (umulp) | |
1121 | product = expand_binop (mode, umul_widen_optab, op0_low, op1_low, | |
1122 | target, 1, OPTAB_DIRECT); | |
1123 | else | |
1124 | product = expand_binop (mode, smul_widen_optab, op0_low, op1_low, | |
1125 | target, 1, OPTAB_DIRECT); | |
1126 | ||
1127 | if (!product) | |
1128 | return NULL_RTX; | |
1129 | ||
1130 | product_high = operand_subword (product, high, 1, mode); | |
1131 | adjust = expand_binop (word_mode, add_optab, product_high, adjust, | |
c701e857 | 1132 | NULL_RTX, 0, OPTAB_DIRECT); |
f927760b RS |
1133 | emit_move_insn (product_high, adjust); |
1134 | return product; | |
1135 | } | |
1136 | \f | |
ef89d648 ZW |
1137 | /* Wrapper around expand_binop which takes an rtx code to specify |
1138 | the operation to perform, not an optab pointer. All other | |
1139 | arguments are the same. */ | |
1140 | rtx | |
0c20a65f AJ |
1141 | expand_simple_binop (enum machine_mode mode, enum rtx_code code, rtx op0, |
1142 | rtx op1, rtx target, int unsignedp, | |
1143 | enum optab_methods methods) | |
ef89d648 | 1144 | { |
7e1a450d | 1145 | optab binop = code_to_optab[(int) code]; |
e3feb571 | 1146 | gcc_assert (binop); |
ef89d648 ZW |
1147 | |
1148 | return expand_binop (mode, binop, op0, op1, target, unsignedp, methods); | |
1149 | } | |
1150 | ||
665d18c6 PB |
1151 | /* Return whether OP0 and OP1 should be swapped when expanding a commutative |
1152 | binop. Order them according to commutative_operand_precedence and, if | |
1153 | possible, try to put TARGET or a pseudo first. */ | |
1154 | static bool | |
1155 | swap_commutative_operands_with_target (rtx target, rtx op0, rtx op1) | |
1156 | { | |
1157 | int op0_prec = commutative_operand_precedence (op0); | |
1158 | int op1_prec = commutative_operand_precedence (op1); | |
1159 | ||
1160 | if (op0_prec < op1_prec) | |
1161 | return true; | |
1162 | ||
1163 | if (op0_prec > op1_prec) | |
1164 | return false; | |
1165 | ||
1166 | /* With equal precedence, both orders are ok, but it is better if the | |
1167 | first operand is TARGET, or if both TARGET and OP0 are pseudos. */ | |
1168 | if (target == 0 || REG_P (target)) | |
1169 | return (REG_P (op1) && !REG_P (op0)) || target == op1; | |
1170 | else | |
1171 | return rtx_equal_p (op1, target); | |
1172 | } | |
1173 | ||
62442ab9 RS |
1174 | /* Return true if BINOPTAB implements a shift operation. */ |
1175 | ||
1176 | static bool | |
1177 | shift_optab_p (optab binoptab) | |
1178 | { | |
1179 | switch (binoptab->code) | |
1180 | { | |
1181 | case ASHIFT: | |
0f996086 CF |
1182 | case SS_ASHIFT: |
1183 | case US_ASHIFT: | |
62442ab9 RS |
1184 | case ASHIFTRT: |
1185 | case LSHIFTRT: | |
1186 | case ROTATE: | |
1187 | case ROTATERT: | |
1188 | return true; | |
1189 | ||
1190 | default: | |
1191 | return false; | |
1192 | } | |
1193 | } | |
1194 | ||
15dc95cb | 1195 | /* Return true if BINOPTAB implements a commutative binary operation. */ |
62442ab9 RS |
1196 | |
1197 | static bool | |
1198 | commutative_optab_p (optab binoptab) | |
1199 | { | |
1200 | return (GET_RTX_CLASS (binoptab->code) == RTX_COMM_ARITH | |
1201 | || binoptab == smul_widen_optab | |
1202 | || binoptab == umul_widen_optab | |
1203 | || binoptab == smul_highpart_optab | |
1204 | || binoptab == umul_highpart_optab); | |
1205 | } | |
1206 | ||
1207 | /* X is to be used in mode MODE as an operand to BINOPTAB. If we're | |
1208 | optimizing, and if the operand is a constant that costs more than | |
1209 | 1 instruction, force the constant into a register and return that | |
1210 | register. Return X otherwise. UNSIGNEDP says whether X is unsigned. */ | |
1211 | ||
1212 | static rtx | |
1213 | avoid_expensive_constant (enum machine_mode mode, optab binoptab, | |
1214 | rtx x, bool unsignedp) | |
1215 | { | |
c99102b8 | 1216 | bool speed = optimize_insn_for_speed_p (); |
fdb2c684 | 1217 | |
47de45c6 RS |
1218 | if (mode != VOIDmode |
1219 | && optimize | |
62442ab9 | 1220 | && CONSTANT_P (x) |
c99102b8 | 1221 | && rtx_cost (x, binoptab->code, speed) > rtx_cost (x, SET, speed)) |
62442ab9 | 1222 | { |
481683e1 | 1223 | if (CONST_INT_P (x)) |
c722c7da RS |
1224 | { |
1225 | HOST_WIDE_INT intval = trunc_int_for_mode (INTVAL (x), mode); | |
1226 | if (intval != INTVAL (x)) | |
1227 | x = GEN_INT (intval); | |
1228 | } | |
1229 | else | |
62442ab9 RS |
1230 | x = convert_modes (mode, VOIDmode, x, unsignedp); |
1231 | x = force_reg (mode, x); | |
1232 | } | |
1233 | return x; | |
1234 | } | |
665d18c6 | 1235 | |
0aa222d1 SL |
1236 | /* Helper function for expand_binop: handle the case where there |
1237 | is an insn that directly implements the indicated operation. | |
1238 | Returns null if this is not possible. */ | |
1239 | static rtx | |
1240 | expand_binop_directly (enum machine_mode mode, optab binoptab, | |
1241 | rtx op0, rtx op1, | |
1242 | rtx target, int unsignedp, enum optab_methods methods, | |
62442ab9 | 1243 | rtx last) |
0aa222d1 | 1244 | { |
a5c7d693 | 1245 | enum insn_code icode = optab_handler (binoptab, mode); |
4f431835 RS |
1246 | enum machine_mode xmode0 = insn_data[(int) icode].operand[1].mode; |
1247 | enum machine_mode xmode1 = insn_data[(int) icode].operand[2].mode; | |
1248 | enum machine_mode mode0, mode1, tmp_mode; | |
a5c7d693 | 1249 | struct expand_operand ops[3]; |
62442ab9 | 1250 | bool commutative_p; |
0aa222d1 SL |
1251 | rtx pat; |
1252 | rtx xop0 = op0, xop1 = op1; | |
62442ab9 | 1253 | rtx swap; |
b8698a0f | 1254 | |
0aa222d1 SL |
1255 | /* If it is a commutative operator and the modes would match |
1256 | if we would swap the operands, we can save the conversions. */ | |
62442ab9 RS |
1257 | commutative_p = commutative_optab_p (binoptab); |
1258 | if (commutative_p | |
4f431835 RS |
1259 | && GET_MODE (xop0) != xmode0 && GET_MODE (xop1) != xmode1 |
1260 | && GET_MODE (xop0) == xmode1 && GET_MODE (xop1) == xmode1) | |
0aa222d1 | 1261 | { |
62442ab9 RS |
1262 | swap = xop0; |
1263 | xop0 = xop1; | |
1264 | xop1 = swap; | |
0aa222d1 | 1265 | } |
b8698a0f | 1266 | |
62442ab9 | 1267 | /* If we are optimizing, force expensive constants into a register. */ |
4f431835 | 1268 | xop0 = avoid_expensive_constant (xmode0, binoptab, xop0, unsignedp); |
62442ab9 | 1269 | if (!shift_optab_p (binoptab)) |
4f431835 | 1270 | xop1 = avoid_expensive_constant (xmode1, binoptab, xop1, unsignedp); |
62442ab9 | 1271 | |
2b99b2b8 RS |
1272 | /* In case the insn wants input operands in modes different from |
1273 | those of the actual operands, convert the operands. It would | |
1274 | seem that we don't need to convert CONST_INTs, but we do, so | |
1275 | that they're properly zero-extended, sign-extended or truncated | |
1276 | for their mode. */ | |
1277 | ||
4f431835 RS |
1278 | mode0 = GET_MODE (xop0) != VOIDmode ? GET_MODE (xop0) : mode; |
1279 | if (xmode0 != VOIDmode && xmode0 != mode0) | |
1280 | { | |
1281 | xop0 = convert_modes (xmode0, mode0, xop0, unsignedp); | |
1282 | mode0 = xmode0; | |
1283 | } | |
1284 | ||
1285 | mode1 = GET_MODE (xop1) != VOIDmode ? GET_MODE (xop1) : mode; | |
1286 | if (xmode1 != VOIDmode && xmode1 != mode1) | |
1287 | { | |
1288 | xop1 = convert_modes (xmode1, mode1, xop1, unsignedp); | |
1289 | mode1 = xmode1; | |
1290 | } | |
2b99b2b8 RS |
1291 | |
1292 | /* If operation is commutative, | |
1293 | try to make the first operand a register. | |
1294 | Even better, try to make it the same as the target. | |
1295 | Also try to make the last operand a constant. */ | |
1296 | if (commutative_p | |
1297 | && swap_commutative_operands_with_target (target, xop0, xop1)) | |
1298 | { | |
1299 | swap = xop1; | |
1300 | xop1 = xop0; | |
1301 | xop0 = swap; | |
1302 | } | |
1303 | ||
0aa222d1 SL |
1304 | /* Now, if insn's predicates don't allow our operands, put them into |
1305 | pseudo regs. */ | |
b8698a0f | 1306 | |
b8698a0f | 1307 | if (binoptab == vec_pack_trunc_optab |
0aa222d1 SL |
1308 | || binoptab == vec_pack_usat_optab |
1309 | || binoptab == vec_pack_ssat_optab | |
1310 | || binoptab == vec_pack_ufix_trunc_optab | |
1311 | || binoptab == vec_pack_sfix_trunc_optab) | |
1312 | { | |
1313 | /* The mode of the result is different then the mode of the | |
1314 | arguments. */ | |
a5c7d693 | 1315 | tmp_mode = insn_data[(int) icode].operand[0].mode; |
0aa222d1 | 1316 | if (GET_MODE_NUNITS (tmp_mode) != 2 * GET_MODE_NUNITS (mode)) |
a5c7d693 RS |
1317 | { |
1318 | delete_insns_since (last); | |
1319 | return NULL_RTX; | |
1320 | } | |
0aa222d1 SL |
1321 | } |
1322 | else | |
1323 | tmp_mode = mode; | |
1324 | ||
a5c7d693 | 1325 | create_output_operand (&ops[0], target, tmp_mode); |
2b99b2b8 RS |
1326 | create_input_operand (&ops[1], xop0, mode0); |
1327 | create_input_operand (&ops[2], xop1, mode1); | |
1328 | pat = maybe_gen_insn (icode, 3, ops); | |
1329 | if (pat) | |
a5c7d693 | 1330 | { |
2b99b2b8 RS |
1331 | /* If PAT is composed of more than one insn, try to add an appropriate |
1332 | REG_EQUAL note to it. If we can't because TEMP conflicts with an | |
1333 | operand, call expand_binop again, this time without a target. */ | |
1334 | if (INSN_P (pat) && NEXT_INSN (pat) != NULL_RTX | |
1335 | && ! add_equal_note (pat, ops[0].value, binoptab->code, | |
1336 | ops[1].value, ops[2].value)) | |
0aa222d1 | 1337 | { |
2b99b2b8 RS |
1338 | delete_insns_since (last); |
1339 | return expand_binop (mode, binoptab, op0, op1, NULL_RTX, | |
1340 | unsignedp, methods); | |
0aa222d1 | 1341 | } |
b8698a0f | 1342 | |
2b99b2b8 RS |
1343 | emit_insn (pat); |
1344 | return ops[0].value; | |
a5c7d693 | 1345 | } |
0aa222d1 SL |
1346 | delete_insns_since (last); |
1347 | return NULL_RTX; | |
1348 | } | |
1349 | ||
77c9c6c2 RK |
1350 | /* Generate code to perform an operation specified by BINOPTAB |
1351 | on operands OP0 and OP1, with result having machine-mode MODE. | |
1352 | ||
1353 | UNSIGNEDP is for the case where we have to widen the operands | |
1354 | to perform the operation. It says to use zero-extension. | |
1355 | ||
1356 | If TARGET is nonzero, the value | |
1357 | is generated there, if it is convenient to do so. | |
1358 | In all cases an rtx is returned for the locus of the value; | |
1359 | this may or may not be TARGET. */ | |
1360 | ||
1361 | rtx | |
0c20a65f AJ |
1362 | expand_binop (enum machine_mode mode, optab binoptab, rtx op0, rtx op1, |
1363 | rtx target, int unsignedp, enum optab_methods methods) | |
77c9c6c2 | 1364 | { |
70864443 RK |
1365 | enum optab_methods next_methods |
1366 | = (methods == OPTAB_LIB || methods == OPTAB_LIB_WIDEN | |
1367 | ? OPTAB_WIDEN : methods); | |
d858f359 | 1368 | enum mode_class mclass; |
77c9c6c2 | 1369 | enum machine_mode wider_mode; |
8a33f100 | 1370 | rtx libfunc; |
b3694847 | 1371 | rtx temp; |
abd418d3 | 1372 | rtx entry_last = get_last_insn (); |
77c9c6c2 RK |
1373 | rtx last; |
1374 | ||
d858f359 | 1375 | mclass = GET_MODE_CLASS (mode); |
77c9c6c2 | 1376 | |
8aecce0a RK |
1377 | /* If subtracting an integer constant, convert this into an addition of |
1378 | the negated constant. */ | |
1379 | ||
481683e1 | 1380 | if (binoptab == sub_optab && CONST_INT_P (op1)) |
8aecce0a RK |
1381 | { |
1382 | op1 = negate_rtx (mode, op1); | |
1383 | binoptab = add_optab; | |
1384 | } | |
1385 | ||
77c9c6c2 RK |
1386 | /* Record where to delete back to if we backtrack. */ |
1387 | last = get_last_insn (); | |
1388 | ||
77c9c6c2 RK |
1389 | /* If we can do it with a three-operand insn, do so. */ |
1390 | ||
1391 | if (methods != OPTAB_MUST_WIDEN | |
947131ba | 1392 | && optab_handler (binoptab, mode) != CODE_FOR_nothing) |
77c9c6c2 | 1393 | { |
0aa222d1 | 1394 | temp = expand_binop_directly (mode, binoptab, op0, op1, target, |
62442ab9 | 1395 | unsignedp, methods, last); |
0aa222d1 SL |
1396 | if (temp) |
1397 | return temp; | |
77c9c6c2 RK |
1398 | } |
1399 | ||
0aa222d1 SL |
1400 | /* If we were trying to rotate, and that didn't work, try rotating |
1401 | the other direction before falling back to shifts and bitwise-or. */ | |
1402 | if (((binoptab == rotl_optab | |
947131ba | 1403 | && optab_handler (rotr_optab, mode) != CODE_FOR_nothing) |
0aa222d1 | 1404 | || (binoptab == rotr_optab |
947131ba | 1405 | && optab_handler (rotl_optab, mode) != CODE_FOR_nothing)) |
d858f359 | 1406 | && mclass == MODE_INT) |
0f8594ee | 1407 | { |
0aa222d1 SL |
1408 | optab otheroptab = (binoptab == rotl_optab ? rotr_optab : rotl_optab); |
1409 | rtx newop1; | |
69660a70 | 1410 | unsigned int bits = GET_MODE_PRECISION (mode); |
0aa222d1 | 1411 | |
481683e1 | 1412 | if (CONST_INT_P (op1)) |
db826dae | 1413 | newop1 = GEN_INT (bits - INTVAL (op1)); |
0aa222d1 | 1414 | else if (targetm.shift_truncation_mask (mode) == bits - 1) |
db826dae | 1415 | newop1 = negate_rtx (GET_MODE (op1), op1); |
0aa222d1 | 1416 | else |
db826dae | 1417 | newop1 = expand_binop (GET_MODE (op1), sub_optab, |
0aa222d1 SL |
1418 | GEN_INT (bits), op1, |
1419 | NULL_RTX, unsignedp, OPTAB_DIRECT); | |
b8698a0f | 1420 | |
0aa222d1 | 1421 | temp = expand_binop_directly (mode, otheroptab, op0, newop1, |
62442ab9 | 1422 | target, unsignedp, methods, last); |
0aa222d1 SL |
1423 | if (temp) |
1424 | return temp; | |
0f8594ee MM |
1425 | } |
1426 | ||
5a5064dc RK |
1427 | /* If this is a multiply, see if we can do a widening operation that |
1428 | takes operands of this mode and makes a wider mode. */ | |
1429 | ||
86556d87 BE |
1430 | if (binoptab == smul_optab |
1431 | && GET_MODE_WIDER_MODE (mode) != VOIDmode | |
947131ba RS |
1432 | && (optab_handler ((unsignedp ? umul_widen_optab : smul_widen_optab), |
1433 | GET_MODE_WIDER_MODE (mode)) | |
5a5064dc RK |
1434 | != CODE_FOR_nothing)) |
1435 | { | |
1436 | temp = expand_binop (GET_MODE_WIDER_MODE (mode), | |
1437 | unsignedp ? umul_widen_optab : smul_widen_optab, | |
73d9a835 | 1438 | op0, op1, NULL_RTX, unsignedp, OPTAB_DIRECT); |
5a5064dc | 1439 | |
70864443 RK |
1440 | if (temp != 0) |
1441 | { | |
28f52a4d | 1442 | if (GET_MODE_CLASS (mode) == MODE_INT |
d0edd768 | 1443 | && TRULY_NOOP_TRUNCATION_MODES_P (mode, GET_MODE (temp))) |
70864443 RK |
1444 | return gen_lowpart (mode, temp); |
1445 | else | |
1446 | return convert_to_mode (mode, temp, unsignedp); | |
1447 | } | |
5a5064dc RK |
1448 | } |
1449 | ||
9a856ec7 | 1450 | /* Look for a wider mode of the same class for which we think we |
5a5064dc RK |
1451 | can open-code the operation. Check for a widening multiply at the |
1452 | wider mode as well. */ | |
9a856ec7 | 1453 | |
d858f359 | 1454 | if (CLASS_HAS_WIDER_MODES_P (mclass) |
6f43c157 | 1455 | && methods != OPTAB_DIRECT && methods != OPTAB_LIB) |
86556d87 BE |
1456 | for (wider_mode = GET_MODE_WIDER_MODE (mode); |
1457 | wider_mode != VOIDmode; | |
9a856ec7 RK |
1458 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) |
1459 | { | |
947131ba | 1460 | if (optab_handler (binoptab, wider_mode) != CODE_FOR_nothing |
5a5064dc RK |
1461 | || (binoptab == smul_optab |
1462 | && GET_MODE_WIDER_MODE (wider_mode) != VOIDmode | |
947131ba RS |
1463 | && (optab_handler ((unsignedp ? umul_widen_optab |
1464 | : smul_widen_optab), | |
1465 | GET_MODE_WIDER_MODE (wider_mode)) | |
5a5064dc | 1466 | != CODE_FOR_nothing))) |
9a856ec7 RK |
1467 | { |
1468 | rtx xop0 = op0, xop1 = op1; | |
1469 | int no_extend = 0; | |
1470 | ||
1471 | /* For certain integer operations, we need not actually extend | |
1472 | the narrow operands, as long as we will truncate | |
6d2f8887 | 1473 | the results to the same narrowness. */ |
9a856ec7 RK |
1474 | |
1475 | if ((binoptab == ior_optab || binoptab == and_optab | |
1476 | || binoptab == xor_optab | |
1477 | || binoptab == add_optab || binoptab == sub_optab | |
e5df894b | 1478 | || binoptab == smul_optab || binoptab == ashl_optab) |
d858f359 | 1479 | && mclass == MODE_INT) |
62442ab9 RS |
1480 | { |
1481 | no_extend = 1; | |
1482 | xop0 = avoid_expensive_constant (mode, binoptab, | |
1483 | xop0, unsignedp); | |
1484 | if (binoptab != ashl_optab) | |
1485 | xop1 = avoid_expensive_constant (mode, binoptab, | |
1486 | xop1, unsignedp); | |
1487 | } | |
9a856ec7 | 1488 | |
0661a3de | 1489 | xop0 = widen_operand (xop0, wider_mode, mode, unsignedp, no_extend); |
943cc242 RK |
1490 | |
1491 | /* The second operand of a shift must always be extended. */ | |
0661a3de | 1492 | xop1 = widen_operand (xop1, wider_mode, mode, unsignedp, |
e5df894b | 1493 | no_extend && binoptab != ashl_optab); |
943cc242 | 1494 | |
b1ec3c92 | 1495 | temp = expand_binop (wider_mode, binoptab, xop0, xop1, NULL_RTX, |
9a856ec7 RK |
1496 | unsignedp, OPTAB_DIRECT); |
1497 | if (temp) | |
1498 | { | |
d858f359 | 1499 | if (mclass != MODE_INT |
d0edd768 | 1500 | || !TRULY_NOOP_TRUNCATION_MODES_P (mode, wider_mode)) |
9a856ec7 RK |
1501 | { |
1502 | if (target == 0) | |
1503 | target = gen_reg_rtx (mode); | |
1504 | convert_move (target, temp, 0); | |
1505 | return target; | |
1506 | } | |
1507 | else | |
1508 | return gen_lowpart (mode, temp); | |
1509 | } | |
1510 | else | |
1511 | delete_insns_since (last); | |
1512 | } | |
1513 | } | |
1514 | ||
62442ab9 RS |
1515 | /* If operation is commutative, |
1516 | try to make the first operand a register. | |
1517 | Even better, try to make it the same as the target. | |
1518 | Also try to make the last operand a constant. */ | |
1519 | if (commutative_optab_p (binoptab) | |
1520 | && swap_commutative_operands_with_target (target, op0, op1)) | |
1521 | { | |
1522 | temp = op1; | |
1523 | op1 = op0; | |
1524 | op0 = temp; | |
1525 | } | |
1526 | ||
77c9c6c2 RK |
1527 | /* These can be done a word at a time. */ |
1528 | if ((binoptab == and_optab || binoptab == ior_optab || binoptab == xor_optab) | |
d858f359 | 1529 | && mclass == MODE_INT |
77c9c6c2 | 1530 | && GET_MODE_SIZE (mode) > UNITS_PER_WORD |
947131ba | 1531 | && optab_handler (binoptab, word_mode) != CODE_FOR_nothing) |
77c9c6c2 | 1532 | { |
bb93b973 | 1533 | int i; |
77c9c6c2 | 1534 | rtx insns; |
77c9c6c2 RK |
1535 | |
1536 | /* If TARGET is the same as one of the operands, the REG_EQUAL note | |
1537 | won't be accurate, so use a new target. */ | |
02972eaf RS |
1538 | if (target == 0 |
1539 | || target == op0 | |
1540 | || target == op1 | |
1541 | || !valid_multiword_target_p (target)) | |
77c9c6c2 RK |
1542 | target = gen_reg_rtx (mode); |
1543 | ||
1544 | start_sequence (); | |
1545 | ||
1546 | /* Do the actual arithmetic. */ | |
1547 | for (i = 0; i < GET_MODE_BITSIZE (mode) / BITS_PER_WORD; i++) | |
1548 | { | |
1549 | rtx target_piece = operand_subword (target, i, 1, mode); | |
34e56753 | 1550 | rtx x = expand_binop (word_mode, binoptab, |
77c9c6c2 RK |
1551 | operand_subword_force (op0, i, mode), |
1552 | operand_subword_force (op1, i, mode), | |
70864443 RK |
1553 | target_piece, unsignedp, next_methods); |
1554 | ||
1555 | if (x == 0) | |
1556 | break; | |
1557 | ||
77c9c6c2 RK |
1558 | if (target_piece != x) |
1559 | emit_move_insn (target_piece, x); | |
1560 | } | |
1561 | ||
1562 | insns = get_insns (); | |
1563 | end_sequence (); | |
1564 | ||
70864443 RK |
1565 | if (i == GET_MODE_BITSIZE (mode) / BITS_PER_WORD) |
1566 | { | |
d70dcf29 | 1567 | emit_insn (insns); |
70864443 RK |
1568 | return target; |
1569 | } | |
77c9c6c2 RK |
1570 | } |
1571 | ||
8c597270 | 1572 | /* Synthesize double word shifts from single word shifts. */ |
e5df894b RK |
1573 | if ((binoptab == lshr_optab || binoptab == ashl_optab |
1574 | || binoptab == ashr_optab) | |
d858f359 | 1575 | && mclass == MODE_INT |
481683e1 | 1576 | && (CONST_INT_P (op1) || optimize_insn_for_speed_p ()) |
8c597270 | 1577 | && GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD |
947131ba RS |
1578 | && optab_handler (binoptab, word_mode) != CODE_FOR_nothing |
1579 | && optab_handler (ashl_optab, word_mode) != CODE_FOR_nothing | |
1580 | && optab_handler (lshr_optab, word_mode) != CODE_FOR_nothing) | |
8c597270 | 1581 | { |
273a2526 RS |
1582 | unsigned HOST_WIDE_INT shift_mask, double_shift_mask; |
1583 | enum machine_mode op1_mode; | |
8c597270 | 1584 | |
273a2526 RS |
1585 | double_shift_mask = targetm.shift_truncation_mask (mode); |
1586 | shift_mask = targetm.shift_truncation_mask (word_mode); | |
1587 | op1_mode = GET_MODE (op1) != VOIDmode ? GET_MODE (op1) : word_mode; | |
8c597270 | 1588 | |
273a2526 | 1589 | /* Apply the truncation to constant shifts. */ |
481683e1 | 1590 | if (double_shift_mask > 0 && CONST_INT_P (op1)) |
273a2526 | 1591 | op1 = GEN_INT (INTVAL (op1) & double_shift_mask); |
8c597270 | 1592 | |
273a2526 RS |
1593 | if (op1 == CONST0_RTX (op1_mode)) |
1594 | return op0; | |
8c597270 | 1595 | |
273a2526 RS |
1596 | /* Make sure that this is a combination that expand_doubleword_shift |
1597 | can handle. See the comments there for details. */ | |
1598 | if (double_shift_mask == 0 | |
1599 | || (shift_mask == BITS_PER_WORD - 1 | |
1600 | && double_shift_mask == BITS_PER_WORD * 2 - 1)) | |
8c597270 | 1601 | { |
d70dcf29 | 1602 | rtx insns; |
273a2526 RS |
1603 | rtx into_target, outof_target; |
1604 | rtx into_input, outof_input; | |
1605 | int left_shift, outof_word; | |
8c597270 | 1606 | |
273a2526 RS |
1607 | /* If TARGET is the same as one of the operands, the REG_EQUAL note |
1608 | won't be accurate, so use a new target. */ | |
02972eaf RS |
1609 | if (target == 0 |
1610 | || target == op0 | |
1611 | || target == op1 | |
1612 | || !valid_multiword_target_p (target)) | |
273a2526 | 1613 | target = gen_reg_rtx (mode); |
8c597270 | 1614 | |
273a2526 | 1615 | start_sequence (); |
8c597270 | 1616 | |
273a2526 RS |
1617 | /* OUTOF_* is the word we are shifting bits away from, and |
1618 | INTO_* is the word that we are shifting bits towards, thus | |
1619 | they differ depending on the direction of the shift and | |
1620 | WORDS_BIG_ENDIAN. */ | |
70864443 | 1621 | |
273a2526 RS |
1622 | left_shift = binoptab == ashl_optab; |
1623 | outof_word = left_shift ^ ! WORDS_BIG_ENDIAN; | |
70864443 | 1624 | |
273a2526 RS |
1625 | outof_target = operand_subword (target, outof_word, 1, mode); |
1626 | into_target = operand_subword (target, 1 - outof_word, 1, mode); | |
cf2f7113 | 1627 | |
273a2526 RS |
1628 | outof_input = operand_subword_force (op0, outof_word, mode); |
1629 | into_input = operand_subword_force (op0, 1 - outof_word, mode); | |
0c20a65f | 1630 | |
273a2526 RS |
1631 | if (expand_doubleword_shift (op1_mode, binoptab, |
1632 | outof_input, into_input, op1, | |
1633 | outof_target, into_target, | |
f8bdb931 | 1634 | unsignedp, next_methods, shift_mask)) |
273a2526 RS |
1635 | { |
1636 | insns = get_insns (); | |
1637 | end_sequence (); | |
8c597270 | 1638 | |
d70dcf29 | 1639 | emit_insn (insns); |
273a2526 RS |
1640 | return target; |
1641 | } | |
1642 | end_sequence (); | |
70864443 | 1643 | } |
8c597270 JW |
1644 | } |
1645 | ||
1646 | /* Synthesize double word rotates from single word shifts. */ | |
1647 | if ((binoptab == rotl_optab || binoptab == rotr_optab) | |
d858f359 | 1648 | && mclass == MODE_INT |
481683e1 | 1649 | && CONST_INT_P (op1) |
8c597270 | 1650 | && GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD |
947131ba RS |
1651 | && optab_handler (ashl_optab, word_mode) != CODE_FOR_nothing |
1652 | && optab_handler (lshr_optab, word_mode) != CODE_FOR_nothing) | |
8c597270 | 1653 | { |
ebd8b60d | 1654 | rtx insns; |
8c597270 JW |
1655 | rtx into_target, outof_target; |
1656 | rtx into_input, outof_input; | |
70864443 | 1657 | rtx inter; |
8c597270 JW |
1658 | int shift_count, left_shift, outof_word; |
1659 | ||
1660 | /* If TARGET is the same as one of the operands, the REG_EQUAL note | |
0c0ab0f1 OH |
1661 | won't be accurate, so use a new target. Do this also if target is not |
1662 | a REG, first because having a register instead may open optimization | |
1ae58c30 | 1663 | opportunities, and second because if target and op0 happen to be MEMs |
0c0ab0f1 OH |
1664 | designating the same location, we would risk clobbering it too early |
1665 | in the code sequence we generate below. */ | |
02972eaf RS |
1666 | if (target == 0 |
1667 | || target == op0 | |
1668 | || target == op1 | |
1669 | || !REG_P (target) | |
1670 | || !valid_multiword_target_p (target)) | |
8c597270 JW |
1671 | target = gen_reg_rtx (mode); |
1672 | ||
1673 | start_sequence (); | |
1674 | ||
1675 | shift_count = INTVAL (op1); | |
1676 | ||
1677 | /* OUTOF_* is the word we are shifting bits away from, and | |
1678 | INTO_* is the word that we are shifting bits towards, thus | |
1679 | they differ depending on the direction of the shift and | |
1680 | WORDS_BIG_ENDIAN. */ | |
1681 | ||
1682 | left_shift = (binoptab == rotl_optab); | |
1683 | outof_word = left_shift ^ ! WORDS_BIG_ENDIAN; | |
1684 | ||
1685 | outof_target = operand_subword (target, outof_word, 1, mode); | |
1686 | into_target = operand_subword (target, 1 - outof_word, 1, mode); | |
1687 | ||
1688 | outof_input = operand_subword_force (op0, outof_word, mode); | |
1689 | into_input = operand_subword_force (op0, 1 - outof_word, mode); | |
1690 | ||
1691 | if (shift_count == BITS_PER_WORD) | |
1692 | { | |
1693 | /* This is just a word swap. */ | |
1694 | emit_move_insn (outof_target, into_input); | |
1695 | emit_move_insn (into_target, outof_input); | |
70864443 | 1696 | inter = const0_rtx; |
8c597270 JW |
1697 | } |
1698 | else | |
1699 | { | |
1700 | rtx into_temp1, into_temp2, outof_temp1, outof_temp2; | |
1701 | rtx first_shift_count, second_shift_count; | |
1702 | optab reverse_unsigned_shift, unsigned_shift; | |
1703 | ||
1704 | reverse_unsigned_shift = (left_shift ^ (shift_count < BITS_PER_WORD) | |
1705 | ? lshr_optab : ashl_optab); | |
1706 | ||
1707 | unsigned_shift = (left_shift ^ (shift_count < BITS_PER_WORD) | |
1708 | ? ashl_optab : lshr_optab); | |
1709 | ||
1710 | if (shift_count > BITS_PER_WORD) | |
1711 | { | |
1712 | first_shift_count = GEN_INT (shift_count - BITS_PER_WORD); | |
7e1a450d | 1713 | second_shift_count = GEN_INT (2 * BITS_PER_WORD - shift_count); |
8c597270 JW |
1714 | } |
1715 | else | |
1716 | { | |
1717 | first_shift_count = GEN_INT (BITS_PER_WORD - shift_count); | |
1718 | second_shift_count = GEN_INT (shift_count); | |
1719 | } | |
1720 | ||
1721 | into_temp1 = expand_binop (word_mode, unsigned_shift, | |
1722 | outof_input, first_shift_count, | |
70864443 | 1723 | NULL_RTX, unsignedp, next_methods); |
8c597270 JW |
1724 | into_temp2 = expand_binop (word_mode, reverse_unsigned_shift, |
1725 | into_input, second_shift_count, | |
5be5c8d4 | 1726 | NULL_RTX, unsignedp, next_methods); |
70864443 RK |
1727 | |
1728 | if (into_temp1 != 0 && into_temp2 != 0) | |
1729 | inter = expand_binop (word_mode, ior_optab, into_temp1, into_temp2, | |
1730 | into_target, unsignedp, next_methods); | |
1731 | else | |
1732 | inter = 0; | |
1733 | ||
cb5b00cf | 1734 | if (inter != 0 && inter != into_target) |
70864443 | 1735 | emit_move_insn (into_target, inter); |
8c597270 JW |
1736 | |
1737 | outof_temp1 = expand_binop (word_mode, unsigned_shift, | |
1738 | into_input, first_shift_count, | |
70864443 | 1739 | NULL_RTX, unsignedp, next_methods); |
8c597270 JW |
1740 | outof_temp2 = expand_binop (word_mode, reverse_unsigned_shift, |
1741 | outof_input, second_shift_count, | |
5be5c8d4 | 1742 | NULL_RTX, unsignedp, next_methods); |
70864443 RK |
1743 | |
1744 | if (inter != 0 && outof_temp1 != 0 && outof_temp2 != 0) | |
1745 | inter = expand_binop (word_mode, ior_optab, | |
1746 | outof_temp1, outof_temp2, | |
1747 | outof_target, unsignedp, next_methods); | |
1748 | ||
cb5b00cf | 1749 | if (inter != 0 && inter != outof_target) |
70864443 | 1750 | emit_move_insn (outof_target, inter); |
8c597270 JW |
1751 | } |
1752 | ||
1753 | insns = get_insns (); | |
1754 | end_sequence (); | |
1755 | ||
70864443 RK |
1756 | if (inter != 0) |
1757 | { | |
ebd8b60d | 1758 | emit_insn (insns); |
70864443 RK |
1759 | return target; |
1760 | } | |
8c597270 JW |
1761 | } |
1762 | ||
77c9c6c2 RK |
1763 | /* These can be done a word at a time by propagating carries. */ |
1764 | if ((binoptab == add_optab || binoptab == sub_optab) | |
d858f359 | 1765 | && mclass == MODE_INT |
77c9c6c2 | 1766 | && GET_MODE_SIZE (mode) >= 2 * UNITS_PER_WORD |
947131ba | 1767 | && optab_handler (binoptab, word_mode) != CODE_FOR_nothing) |
77c9c6c2 | 1768 | { |
e2500fed | 1769 | unsigned int i; |
77c9c6c2 | 1770 | optab otheroptab = binoptab == add_optab ? sub_optab : add_optab; |
a4b5414c | 1771 | const unsigned int nwords = GET_MODE_BITSIZE (mode) / BITS_PER_WORD; |
07444f1d | 1772 | rtx carry_in = NULL_RTX, carry_out = NULL_RTX; |
64de6c0a | 1773 | rtx xop0, xop1, xtarget; |
77c9c6c2 RK |
1774 | |
1775 | /* We can handle either a 1 or -1 value for the carry. If STORE_FLAG | |
1776 | value is one of those, use it. Otherwise, use 1 since it is the | |
1777 | one easiest to get. */ | |
1778 | #if STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1 | |
1779 | int normalizep = STORE_FLAG_VALUE; | |
1780 | #else | |
1781 | int normalizep = 1; | |
1782 | #endif | |
1783 | ||
1784 | /* Prepare the operands. */ | |
cee85023 RS |
1785 | xop0 = force_reg (mode, op0); |
1786 | xop1 = force_reg (mode, op1); | |
77c9c6c2 | 1787 | |
64de6c0a DE |
1788 | xtarget = gen_reg_rtx (mode); |
1789 | ||
02972eaf | 1790 | if (target == 0 || !REG_P (target) || !valid_multiword_target_p (target)) |
64de6c0a | 1791 | target = xtarget; |
77c9c6c2 | 1792 | |
af2cc4dd | 1793 | /* Indicate for flow that the entire target reg is being set. */ |
f8cfc6aa | 1794 | if (REG_P (target)) |
c41c1387 | 1795 | emit_clobber (xtarget); |
af2cc4dd | 1796 | |
77c9c6c2 RK |
1797 | /* Do the actual arithmetic. */ |
1798 | for (i = 0; i < nwords; i++) | |
1799 | { | |
1800 | int index = (WORDS_BIG_ENDIAN ? nwords - i - 1 : i); | |
64de6c0a | 1801 | rtx target_piece = operand_subword (xtarget, index, 1, mode); |
cee85023 RS |
1802 | rtx op0_piece = operand_subword_force (xop0, index, mode); |
1803 | rtx op1_piece = operand_subword_force (xop1, index, mode); | |
77c9c6c2 RK |
1804 | rtx x; |
1805 | ||
1806 | /* Main add/subtract of the input operands. */ | |
34e56753 | 1807 | x = expand_binop (word_mode, binoptab, |
77c9c6c2 | 1808 | op0_piece, op1_piece, |
70864443 | 1809 | target_piece, unsignedp, next_methods); |
77c9c6c2 RK |
1810 | if (x == 0) |
1811 | break; | |
1812 | ||
1813 | if (i + 1 < nwords) | |
1814 | { | |
1815 | /* Store carry from main add/subtract. */ | |
34e56753 | 1816 | carry_out = gen_reg_rtx (word_mode); |
23357404 TG |
1817 | carry_out = emit_store_flag_force (carry_out, |
1818 | (binoptab == add_optab | |
b30f05db | 1819 | ? LT : GT), |
23357404 TG |
1820 | x, op0_piece, |
1821 | word_mode, 1, normalizep); | |
77c9c6c2 RK |
1822 | } |
1823 | ||
1824 | if (i > 0) | |
1825 | { | |
859cb4d8 | 1826 | rtx newx; |
0c20a65f | 1827 | |
77c9c6c2 | 1828 | /* Add/subtract previous carry to main result. */ |
859cb4d8 GK |
1829 | newx = expand_binop (word_mode, |
1830 | normalizep == 1 ? binoptab : otheroptab, | |
1831 | x, carry_in, | |
1832 | NULL_RTX, 1, next_methods); | |
77c9c6c2 RK |
1833 | |
1834 | if (i + 1 < nwords) | |
1835 | { | |
77c9c6c2 | 1836 | /* Get out carry from adding/subtracting carry in. */ |
859cb4d8 | 1837 | rtx carry_tmp = gen_reg_rtx (word_mode); |
23357404 | 1838 | carry_tmp = emit_store_flag_force (carry_tmp, |
859cb4d8 GK |
1839 | (binoptab == add_optab |
1840 | ? LT : GT), | |
1841 | newx, x, | |
23357404 | 1842 | word_mode, 1, normalizep); |
70864443 | 1843 | |
77c9c6c2 | 1844 | /* Logical-ior the two poss. carry together. */ |
34e56753 | 1845 | carry_out = expand_binop (word_mode, ior_optab, |
77c9c6c2 | 1846 | carry_out, carry_tmp, |
70864443 RK |
1847 | carry_out, 0, next_methods); |
1848 | if (carry_out == 0) | |
77c9c6c2 RK |
1849 | break; |
1850 | } | |
859cb4d8 | 1851 | emit_move_insn (target_piece, newx); |
77c9c6c2 | 1852 | } |
06cd9d72 DD |
1853 | else |
1854 | { | |
1855 | if (x != target_piece) | |
1856 | emit_move_insn (target_piece, x); | |
1857 | } | |
77c9c6c2 RK |
1858 | |
1859 | carry_in = carry_out; | |
0c20a65f | 1860 | } |
77c9c6c2 | 1861 | |
e2500fed | 1862 | if (i == GET_MODE_BITSIZE (mode) / (unsigned) BITS_PER_WORD) |
77c9c6c2 | 1863 | { |
947131ba | 1864 | if (optab_handler (mov_optab, mode) != CODE_FOR_nothing |
d0ccc658 | 1865 | || ! rtx_equal_p (target, xtarget)) |
02214a5c | 1866 | { |
64de6c0a | 1867 | rtx temp = emit_move_insn (target, xtarget); |
70864443 | 1868 | |
5fa671cf | 1869 | set_unique_reg_note (temp, |
0c20a65f | 1870 | REG_EQUAL, |
5fa671cf AM |
1871 | gen_rtx_fmt_ee (binoptab->code, mode, |
1872 | copy_rtx (xop0), | |
1873 | copy_rtx (xop1))); | |
02214a5c | 1874 | } |
2cd622c3 AO |
1875 | else |
1876 | target = xtarget; | |
c5c76735 | 1877 | |
77c9c6c2 RK |
1878 | return target; |
1879 | } | |
c5c76735 | 1880 | |
77c9c6c2 RK |
1881 | else |
1882 | delete_insns_since (last); | |
1883 | } | |
1884 | ||
f927760b RS |
1885 | /* Attempt to synthesize double word multiplies using a sequence of word |
1886 | mode multiplications. We first attempt to generate a sequence using a | |
1887 | more efficient unsigned widening multiply, and if that fails we then | |
1888 | try using a signed widening multiply. */ | |
77c9c6c2 RK |
1889 | |
1890 | if (binoptab == smul_optab | |
d858f359 | 1891 | && mclass == MODE_INT |
77c9c6c2 | 1892 | && GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD |
947131ba RS |
1893 | && optab_handler (smul_optab, word_mode) != CODE_FOR_nothing |
1894 | && optab_handler (add_optab, word_mode) != CODE_FOR_nothing) | |
77c9c6c2 | 1895 | { |
f927760b | 1896 | rtx product = NULL_RTX; |
77c9c6c2 | 1897 | |
947131ba | 1898 | if (optab_handler (umul_widen_optab, mode) != CODE_FOR_nothing) |
f927760b RS |
1899 | { |
1900 | product = expand_doubleword_mult (mode, op0, op1, target, | |
1901 | true, methods); | |
1902 | if (!product) | |
77c9c6c2 | 1903 | delete_insns_since (last); |
77c9c6c2 RK |
1904 | } |
1905 | ||
f927760b | 1906 | if (product == NULL_RTX |
947131ba | 1907 | && optab_handler (smul_widen_optab, mode) != CODE_FOR_nothing) |
77c9c6c2 | 1908 | { |
f927760b RS |
1909 | product = expand_doubleword_mult (mode, op0, op1, target, |
1910 | false, methods); | |
1911 | if (!product) | |
1912 | delete_insns_since (last); | |
77c9c6c2 RK |
1913 | } |
1914 | ||
f927760b | 1915 | if (product != NULL_RTX) |
77c9c6c2 | 1916 | { |
947131ba | 1917 | if (optab_handler (mov_optab, mode) != CODE_FOR_nothing) |
70864443 | 1918 | { |
f927760b RS |
1919 | temp = emit_move_insn (target ? target : product, product); |
1920 | set_unique_reg_note (temp, | |
1921 | REG_EQUAL, | |
1922 | gen_rtx_fmt_ee (MULT, mode, | |
1923 | copy_rtx (op0), | |
1924 | copy_rtx (op1))); | |
77c9c6c2 | 1925 | } |
f927760b | 1926 | return product; |
77c9c6c2 | 1927 | } |
77c9c6c2 RK |
1928 | } |
1929 | ||
1930 | /* It can't be open-coded in this mode. | |
1931 | Use a library call if one is available and caller says that's ok. */ | |
1932 | ||
8a33f100 JH |
1933 | libfunc = optab_libfunc (binoptab, mode); |
1934 | if (libfunc | |
77c9c6c2 RK |
1935 | && (methods == OPTAB_LIB || methods == OPTAB_LIB_WIDEN)) |
1936 | { | |
1937 | rtx insns; | |
0bbb7f4d RS |
1938 | rtx op1x = op1; |
1939 | enum machine_mode op1_mode = mode; | |
9a7f678c | 1940 | rtx value; |
77c9c6c2 RK |
1941 | |
1942 | start_sequence (); | |
1943 | ||
62442ab9 | 1944 | if (shift_optab_p (binoptab)) |
0bbb7f4d | 1945 | { |
c7ff6e7a | 1946 | op1_mode = targetm.libgcc_shift_count_mode (); |
0bbb7f4d RS |
1947 | /* Specify unsigned here, |
1948 | since negative shift counts are meaningless. */ | |
c7ff6e7a | 1949 | op1x = convert_to_mode (op1_mode, op1, 1); |
0bbb7f4d RS |
1950 | } |
1951 | ||
82f0e2cc RK |
1952 | if (GET_MODE (op0) != VOIDmode |
1953 | && GET_MODE (op0) != mode) | |
5035bbfe TG |
1954 | op0 = convert_to_mode (mode, op0, unsignedp); |
1955 | ||
77c9c6c2 RK |
1956 | /* Pass 1 for NO_QUEUE so we don't lose any increments |
1957 | if the libcall is cse'd or moved. */ | |
8a33f100 | 1958 | value = emit_library_call_value (libfunc, |
ebb1b59a | 1959 | NULL_RTX, LCT_CONST, mode, 2, |
9a7f678c | 1960 | op0, mode, op1x, op1_mode); |
77c9c6c2 RK |
1961 | |
1962 | insns = get_insns (); | |
1963 | end_sequence (); | |
1964 | ||
1965 | target = gen_reg_rtx (mode); | |
9a7f678c | 1966 | emit_libcall_block (insns, target, value, |
9e6a5703 | 1967 | gen_rtx_fmt_ee (binoptab->code, mode, op0, op1)); |
77c9c6c2 RK |
1968 | |
1969 | return target; | |
1970 | } | |
1971 | ||
1972 | delete_insns_since (last); | |
1973 | ||
1974 | /* It can't be done in this mode. Can we do it in a wider mode? */ | |
1975 | ||
1976 | if (! (methods == OPTAB_WIDEN || methods == OPTAB_LIB_WIDEN | |
1977 | || methods == OPTAB_MUST_WIDEN)) | |
abd418d3 RS |
1978 | { |
1979 | /* Caller says, don't even try. */ | |
1980 | delete_insns_since (entry_last); | |
1981 | return 0; | |
1982 | } | |
77c9c6c2 RK |
1983 | |
1984 | /* Compute the value of METHODS to pass to recursive calls. | |
1985 | Don't allow widening to be tried recursively. */ | |
1986 | ||
1987 | methods = (methods == OPTAB_LIB_WIDEN ? OPTAB_LIB : OPTAB_DIRECT); | |
1988 | ||
34e56753 RS |
1989 | /* Look for a wider mode of the same class for which it appears we can do |
1990 | the operation. */ | |
77c9c6c2 | 1991 | |
d858f359 | 1992 | if (CLASS_HAS_WIDER_MODES_P (mclass)) |
77c9c6c2 | 1993 | { |
86556d87 BE |
1994 | for (wider_mode = GET_MODE_WIDER_MODE (mode); |
1995 | wider_mode != VOIDmode; | |
77c9c6c2 RK |
1996 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) |
1997 | { | |
947131ba | 1998 | if (optab_handler (binoptab, wider_mode) != CODE_FOR_nothing |
77c9c6c2 | 1999 | || (methods == OPTAB_LIB |
8a33f100 | 2000 | && optab_libfunc (binoptab, wider_mode))) |
77c9c6c2 RK |
2001 | { |
2002 | rtx xop0 = op0, xop1 = op1; | |
2003 | int no_extend = 0; | |
2004 | ||
34e56753 | 2005 | /* For certain integer operations, we need not actually extend |
77c9c6c2 | 2006 | the narrow operands, as long as we will truncate |
835532b8 | 2007 | the results to the same narrowness. */ |
77c9c6c2 | 2008 | |
34e56753 RS |
2009 | if ((binoptab == ior_optab || binoptab == and_optab |
2010 | || binoptab == xor_optab | |
2011 | || binoptab == add_optab || binoptab == sub_optab | |
e5df894b | 2012 | || binoptab == smul_optab || binoptab == ashl_optab) |
d858f359 | 2013 | && mclass == MODE_INT) |
77c9c6c2 RK |
2014 | no_extend = 1; |
2015 | ||
0661a3de RS |
2016 | xop0 = widen_operand (xop0, wider_mode, mode, |
2017 | unsignedp, no_extend); | |
943cc242 RK |
2018 | |
2019 | /* The second operand of a shift must always be extended. */ | |
0661a3de | 2020 | xop1 = widen_operand (xop1, wider_mode, mode, unsignedp, |
e5df894b | 2021 | no_extend && binoptab != ashl_optab); |
77c9c6c2 | 2022 | |
b1ec3c92 | 2023 | temp = expand_binop (wider_mode, binoptab, xop0, xop1, NULL_RTX, |
77c9c6c2 RK |
2024 | unsignedp, methods); |
2025 | if (temp) | |
2026 | { | |
d858f359 | 2027 | if (mclass != MODE_INT |
d0edd768 | 2028 | || !TRULY_NOOP_TRUNCATION_MODES_P (mode, wider_mode)) |
77c9c6c2 RK |
2029 | { |
2030 | if (target == 0) | |
2031 | target = gen_reg_rtx (mode); | |
2032 | convert_move (target, temp, 0); | |
2033 | return target; | |
2034 | } | |
2035 | else | |
2036 | return gen_lowpart (mode, temp); | |
2037 | } | |
2038 | else | |
2039 | delete_insns_since (last); | |
2040 | } | |
2041 | } | |
2042 | } | |
2043 | ||
abd418d3 | 2044 | delete_insns_since (entry_last); |
77c9c6c2 RK |
2045 | return 0; |
2046 | } | |
2047 | \f | |
2048 | /* Expand a binary operator which has both signed and unsigned forms. | |
2049 | UOPTAB is the optab for unsigned operations, and SOPTAB is for | |
2050 | signed operations. | |
2051 | ||
2052 | If we widen unsigned operands, we may use a signed wider operation instead | |
2053 | of an unsigned wider operation, since the result would be the same. */ | |
2054 | ||
2055 | rtx | |
0c20a65f AJ |
2056 | sign_expand_binop (enum machine_mode mode, optab uoptab, optab soptab, |
2057 | rtx op0, rtx op1, rtx target, int unsignedp, | |
2058 | enum optab_methods methods) | |
77c9c6c2 | 2059 | { |
b3694847 | 2060 | rtx temp; |
77c9c6c2 | 2061 | optab direct_optab = unsignedp ? uoptab : soptab; |
7e5487a2 | 2062 | struct optab_d wide_soptab; |
77c9c6c2 RK |
2063 | |
2064 | /* Do it without widening, if possible. */ | |
2065 | temp = expand_binop (mode, direct_optab, op0, op1, target, | |
2066 | unsignedp, OPTAB_DIRECT); | |
2067 | if (temp || methods == OPTAB_DIRECT) | |
2068 | return temp; | |
2069 | ||
2070 | /* Try widening to a signed int. Make a fake signed optab that | |
2071 | hides any signed insn for direct use. */ | |
2072 | wide_soptab = *soptab; | |
947131ba | 2073 | set_optab_handler (&wide_soptab, mode, CODE_FOR_nothing); |
ae2bd7d2 AH |
2074 | /* We don't want to generate new hash table entries from this fake |
2075 | optab. */ | |
2076 | wide_soptab.libcall_gen = NULL; | |
77c9c6c2 RK |
2077 | |
2078 | temp = expand_binop (mode, &wide_soptab, op0, op1, target, | |
2079 | unsignedp, OPTAB_WIDEN); | |
2080 | ||
2081 | /* For unsigned operands, try widening to an unsigned int. */ | |
2082 | if (temp == 0 && unsignedp) | |
2083 | temp = expand_binop (mode, uoptab, op0, op1, target, | |
2084 | unsignedp, OPTAB_WIDEN); | |
2085 | if (temp || methods == OPTAB_WIDEN) | |
2086 | return temp; | |
2087 | ||
f90b7a5a | 2088 | /* Use the right width libcall if that exists. */ |
77c9c6c2 RK |
2089 | temp = expand_binop (mode, direct_optab, op0, op1, target, unsignedp, OPTAB_LIB); |
2090 | if (temp || methods == OPTAB_LIB) | |
2091 | return temp; | |
2092 | ||
f90b7a5a | 2093 | /* Must widen and use a libcall, use either signed or unsigned. */ |
77c9c6c2 RK |
2094 | temp = expand_binop (mode, &wide_soptab, op0, op1, target, |
2095 | unsignedp, methods); | |
2096 | if (temp != 0) | |
2097 | return temp; | |
2098 | if (unsignedp) | |
2099 | return expand_binop (mode, uoptab, op0, op1, target, | |
2100 | unsignedp, methods); | |
2101 | return 0; | |
2102 | } | |
2103 | \f | |
6c7cf1f0 UB |
2104 | /* Generate code to perform an operation specified by UNOPPTAB |
2105 | on operand OP0, with two results to TARG0 and TARG1. | |
2106 | We assume that the order of the operands for the instruction | |
2107 | is TARG0, TARG1, OP0. | |
2108 | ||
2109 | Either TARG0 or TARG1 may be zero, but what that means is that | |
2110 | the result is not actually wanted. We will generate it into | |
2111 | a dummy pseudo-reg and discard it. They may not both be zero. | |
2112 | ||
2113 | Returns 1 if this operation can be performed; 0 if not. */ | |
2114 | ||
2115 | int | |
a072d43b | 2116 | expand_twoval_unop (optab unoptab, rtx op0, rtx targ0, rtx targ1, |
6c7cf1f0 UB |
2117 | int unsignedp) |
2118 | { | |
2119 | enum machine_mode mode = GET_MODE (targ0 ? targ0 : targ1); | |
d858f359 | 2120 | enum mode_class mclass; |
6c7cf1f0 UB |
2121 | enum machine_mode wider_mode; |
2122 | rtx entry_last = get_last_insn (); | |
2123 | rtx last; | |
2124 | ||
d858f359 | 2125 | mclass = GET_MODE_CLASS (mode); |
6c7cf1f0 | 2126 | |
ad76cef8 | 2127 | if (!targ0) |
6c7cf1f0 | 2128 | targ0 = gen_reg_rtx (mode); |
ad76cef8 | 2129 | if (!targ1) |
6c7cf1f0 UB |
2130 | targ1 = gen_reg_rtx (mode); |
2131 | ||
2132 | /* Record where to go back to if we fail. */ | |
2133 | last = get_last_insn (); | |
2134 | ||
947131ba | 2135 | if (optab_handler (unoptab, mode) != CODE_FOR_nothing) |
6c7cf1f0 | 2136 | { |
a5c7d693 RS |
2137 | struct expand_operand ops[3]; |
2138 | enum insn_code icode = optab_handler (unoptab, mode); | |
6c7cf1f0 | 2139 | |
a5c7d693 RS |
2140 | create_fixed_operand (&ops[0], targ0); |
2141 | create_fixed_operand (&ops[1], targ1); | |
2142 | create_convert_operand_from (&ops[2], op0, mode, unsignedp); | |
2143 | if (maybe_expand_insn (icode, 3, ops)) | |
2144 | return 1; | |
6c7cf1f0 UB |
2145 | } |
2146 | ||
2147 | /* It can't be done in this mode. Can we do it in a wider mode? */ | |
2148 | ||
d858f359 | 2149 | if (CLASS_HAS_WIDER_MODES_P (mclass)) |
6c7cf1f0 | 2150 | { |
86556d87 BE |
2151 | for (wider_mode = GET_MODE_WIDER_MODE (mode); |
2152 | wider_mode != VOIDmode; | |
6c7cf1f0 UB |
2153 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) |
2154 | { | |
947131ba | 2155 | if (optab_handler (unoptab, wider_mode) != CODE_FOR_nothing) |
6c7cf1f0 UB |
2156 | { |
2157 | rtx t0 = gen_reg_rtx (wider_mode); | |
2158 | rtx t1 = gen_reg_rtx (wider_mode); | |
2159 | rtx cop0 = convert_modes (wider_mode, mode, op0, unsignedp); | |
2160 | ||
a072d43b | 2161 | if (expand_twoval_unop (unoptab, cop0, t0, t1, unsignedp)) |
6c7cf1f0 UB |
2162 | { |
2163 | convert_move (targ0, t0, unsignedp); | |
2164 | convert_move (targ1, t1, unsignedp); | |
2165 | return 1; | |
2166 | } | |
2167 | else | |
2168 | delete_insns_since (last); | |
2169 | } | |
2170 | } | |
2171 | } | |
2172 | ||
2173 | delete_insns_since (entry_last); | |
2174 | return 0; | |
2175 | } | |
2176 | \f | |
77c9c6c2 RK |
2177 | /* Generate code to perform an operation specified by BINOPTAB |
2178 | on operands OP0 and OP1, with two results to TARG1 and TARG2. | |
2179 | We assume that the order of the operands for the instruction | |
2180 | is TARG0, OP0, OP1, TARG1, which would fit a pattern like | |
2181 | [(set TARG0 (operate OP0 OP1)) (set TARG1 (operate ...))]. | |
2182 | ||
2183 | Either TARG0 or TARG1 may be zero, but what that means is that | |
38e01259 | 2184 | the result is not actually wanted. We will generate it into |
77c9c6c2 RK |
2185 | a dummy pseudo-reg and discard it. They may not both be zero. |
2186 | ||
2187 | Returns 1 if this operation can be performed; 0 if not. */ | |
2188 | ||
2189 | int | |
0c20a65f AJ |
2190 | expand_twoval_binop (optab binoptab, rtx op0, rtx op1, rtx targ0, rtx targ1, |
2191 | int unsignedp) | |
77c9c6c2 RK |
2192 | { |
2193 | enum machine_mode mode = GET_MODE (targ0 ? targ0 : targ1); | |
d858f359 | 2194 | enum mode_class mclass; |
77c9c6c2 | 2195 | enum machine_mode wider_mode; |
abd418d3 | 2196 | rtx entry_last = get_last_insn (); |
77c9c6c2 RK |
2197 | rtx last; |
2198 | ||
d858f359 | 2199 | mclass = GET_MODE_CLASS (mode); |
77c9c6c2 | 2200 | |
ad76cef8 | 2201 | if (!targ0) |
77c9c6c2 | 2202 | targ0 = gen_reg_rtx (mode); |
ad76cef8 | 2203 | if (!targ1) |
77c9c6c2 RK |
2204 | targ1 = gen_reg_rtx (mode); |
2205 | ||
2206 | /* Record where to go back to if we fail. */ | |
2207 | last = get_last_insn (); | |
2208 | ||
947131ba | 2209 | if (optab_handler (binoptab, mode) != CODE_FOR_nothing) |
77c9c6c2 | 2210 | { |
a5c7d693 RS |
2211 | struct expand_operand ops[4]; |
2212 | enum insn_code icode = optab_handler (binoptab, mode); | |
a995e389 RH |
2213 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; |
2214 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
77c9c6c2 RK |
2215 | rtx xop0 = op0, xop1 = op1; |
2216 | ||
62442ab9 RS |
2217 | /* If we are optimizing, force expensive constants into a register. */ |
2218 | xop0 = avoid_expensive_constant (mode0, binoptab, xop0, unsignedp); | |
2219 | xop1 = avoid_expensive_constant (mode1, binoptab, xop1, unsignedp); | |
2220 | ||
a5c7d693 RS |
2221 | create_fixed_operand (&ops[0], targ0); |
2222 | create_convert_operand_from (&ops[1], op0, mode, unsignedp); | |
2223 | create_convert_operand_from (&ops[2], op1, mode, unsignedp); | |
2224 | create_fixed_operand (&ops[3], targ1); | |
2225 | if (maybe_expand_insn (icode, 4, ops)) | |
2226 | return 1; | |
2227 | delete_insns_since (last); | |
77c9c6c2 RK |
2228 | } |
2229 | ||
2230 | /* It can't be done in this mode. Can we do it in a wider mode? */ | |
2231 | ||
d858f359 | 2232 | if (CLASS_HAS_WIDER_MODES_P (mclass)) |
77c9c6c2 | 2233 | { |
86556d87 BE |
2234 | for (wider_mode = GET_MODE_WIDER_MODE (mode); |
2235 | wider_mode != VOIDmode; | |
77c9c6c2 RK |
2236 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) |
2237 | { | |
947131ba | 2238 | if (optab_handler (binoptab, wider_mode) != CODE_FOR_nothing) |
77c9c6c2 | 2239 | { |
b3694847 SS |
2240 | rtx t0 = gen_reg_rtx (wider_mode); |
2241 | rtx t1 = gen_reg_rtx (wider_mode); | |
76791f3d JH |
2242 | rtx cop0 = convert_modes (wider_mode, mode, op0, unsignedp); |
2243 | rtx cop1 = convert_modes (wider_mode, mode, op1, unsignedp); | |
77c9c6c2 | 2244 | |
76791f3d | 2245 | if (expand_twoval_binop (binoptab, cop0, cop1, |
77c9c6c2 RK |
2246 | t0, t1, unsignedp)) |
2247 | { | |
2248 | convert_move (targ0, t0, unsignedp); | |
2249 | convert_move (targ1, t1, unsignedp); | |
2250 | return 1; | |
2251 | } | |
2252 | else | |
2253 | delete_insns_since (last); | |
2254 | } | |
2255 | } | |
2256 | } | |
2257 | ||
abd418d3 | 2258 | delete_insns_since (entry_last); |
77c9c6c2 RK |
2259 | return 0; |
2260 | } | |
b3f8d95d MM |
2261 | |
2262 | /* Expand the two-valued library call indicated by BINOPTAB, but | |
2263 | preserve only one of the values. If TARG0 is non-NULL, the first | |
2264 | value is placed into TARG0; otherwise the second value is placed | |
2265 | into TARG1. Exactly one of TARG0 and TARG1 must be non-NULL. The | |
2266 | value stored into TARG0 or TARG1 is equivalent to (CODE OP0 OP1). | |
2267 | This routine assumes that the value returned by the library call is | |
2268 | as if the return value was of an integral mode twice as wide as the | |
2269 | mode of OP0. Returns 1 if the call was successful. */ | |
2270 | ||
2271 | bool | |
5906d013 | 2272 | expand_twoval_binop_libfunc (optab binoptab, rtx op0, rtx op1, |
b3f8d95d MM |
2273 | rtx targ0, rtx targ1, enum rtx_code code) |
2274 | { | |
2275 | enum machine_mode mode; | |
2276 | enum machine_mode libval_mode; | |
2277 | rtx libval; | |
2278 | rtx insns; | |
8a33f100 | 2279 | rtx libfunc; |
5906d013 | 2280 | |
b3f8d95d | 2281 | /* Exactly one of TARG0 or TARG1 should be non-NULL. */ |
e3feb571 | 2282 | gcc_assert (!targ0 != !targ1); |
b3f8d95d MM |
2283 | |
2284 | mode = GET_MODE (op0); | |
8a33f100 JH |
2285 | libfunc = optab_libfunc (binoptab, mode); |
2286 | if (!libfunc) | |
b3f8d95d MM |
2287 | return false; |
2288 | ||
2289 | /* The value returned by the library function will have twice as | |
2290 | many bits as the nominal MODE. */ | |
5906d013 | 2291 | libval_mode = smallest_mode_for_size (2 * GET_MODE_BITSIZE (mode), |
b3f8d95d MM |
2292 | MODE_INT); |
2293 | start_sequence (); | |
8a33f100 | 2294 | libval = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST, |
b3f8d95d | 2295 | libval_mode, 2, |
5906d013 | 2296 | op0, mode, |
b3f8d95d MM |
2297 | op1, mode); |
2298 | /* Get the part of VAL containing the value that we want. */ | |
2299 | libval = simplify_gen_subreg (mode, libval, libval_mode, | |
2300 | targ0 ? 0 : GET_MODE_SIZE (mode)); | |
2301 | insns = get_insns (); | |
2302 | end_sequence (); | |
2303 | /* Move the into the desired location. */ | |
5906d013 | 2304 | emit_libcall_block (insns, targ0 ? targ0 : targ1, libval, |
b3f8d95d | 2305 | gen_rtx_fmt_ee (code, mode, op0, op1)); |
5906d013 | 2306 | |
b3f8d95d MM |
2307 | return true; |
2308 | } | |
2309 | ||
77c9c6c2 | 2310 | \f |
ef89d648 ZW |
2311 | /* Wrapper around expand_unop which takes an rtx code to specify |
2312 | the operation to perform, not an optab pointer. All other | |
2313 | arguments are the same. */ | |
2314 | rtx | |
0c20a65f AJ |
2315 | expand_simple_unop (enum machine_mode mode, enum rtx_code code, rtx op0, |
2316 | rtx target, int unsignedp) | |
ef89d648 | 2317 | { |
7e1a450d | 2318 | optab unop = code_to_optab[(int) code]; |
e3feb571 | 2319 | gcc_assert (unop); |
ef89d648 ZW |
2320 | |
2321 | return expand_unop (mode, unop, op0, target, unsignedp); | |
2322 | } | |
2323 | ||
2928cd7a RH |
2324 | /* Try calculating |
2325 | (clz:narrow x) | |
2326 | as | |
3801c801 BS |
2327 | (clz:wide (zero_extend:wide x)) - ((width wide) - (width narrow)). |
2328 | ||
2329 | A similar operation can be used for clrsb. UNOPTAB says which operation | |
2330 | we are trying to expand. */ | |
2928cd7a | 2331 | static rtx |
3801c801 | 2332 | widen_leading (enum machine_mode mode, rtx op0, rtx target, optab unoptab) |
2928cd7a | 2333 | { |
d858f359 KG |
2334 | enum mode_class mclass = GET_MODE_CLASS (mode); |
2335 | if (CLASS_HAS_WIDER_MODES_P (mclass)) | |
2928cd7a RH |
2336 | { |
2337 | enum machine_mode wider_mode; | |
86556d87 BE |
2338 | for (wider_mode = GET_MODE_WIDER_MODE (mode); |
2339 | wider_mode != VOIDmode; | |
2928cd7a RH |
2340 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) |
2341 | { | |
3801c801 | 2342 | if (optab_handler (unoptab, wider_mode) != CODE_FOR_nothing) |
2928cd7a RH |
2343 | { |
2344 | rtx xop0, temp, last; | |
2345 | ||
2346 | last = get_last_insn (); | |
2347 | ||
2348 | if (target == 0) | |
2349 | target = gen_reg_rtx (mode); | |
146aef0b JJ |
2350 | xop0 = widen_operand (op0, wider_mode, mode, |
2351 | unoptab != clrsb_optab, false); | |
2352 | temp = expand_unop (wider_mode, unoptab, xop0, NULL_RTX, | |
2353 | unoptab != clrsb_optab); | |
2928cd7a RH |
2354 | if (temp != 0) |
2355 | temp = expand_binop (wider_mode, sub_optab, temp, | |
69660a70 BS |
2356 | GEN_INT (GET_MODE_PRECISION (wider_mode) |
2357 | - GET_MODE_PRECISION (mode)), | |
2928cd7a RH |
2358 | target, true, OPTAB_DIRECT); |
2359 | if (temp == 0) | |
2360 | delete_insns_since (last); | |
2361 | ||
2362 | return temp; | |
2363 | } | |
2364 | } | |
2365 | } | |
2366 | return 0; | |
2367 | } | |
2368 | ||
9cce5b20 ZW |
2369 | /* Try calculating clz of a double-word quantity as two clz's of word-sized |
2370 | quantities, choosing which based on whether the high word is nonzero. */ | |
2371 | static rtx | |
2372 | expand_doubleword_clz (enum machine_mode mode, rtx op0, rtx target) | |
2373 | { | |
2374 | rtx xop0 = force_reg (mode, op0); | |
2375 | rtx subhi = gen_highpart (word_mode, xop0); | |
2376 | rtx sublo = gen_lowpart (word_mode, xop0); | |
2377 | rtx hi0_label = gen_label_rtx (); | |
2378 | rtx after_label = gen_label_rtx (); | |
2379 | rtx seq, temp, result; | |
2380 | ||
2381 | /* If we were not given a target, use a word_mode register, not a | |
2382 | 'mode' register. The result will fit, and nobody is expecting | |
2383 | anything bigger (the return type of __builtin_clz* is int). */ | |
2384 | if (!target) | |
2385 | target = gen_reg_rtx (word_mode); | |
2386 | ||
2387 | /* In any case, write to a word_mode scratch in both branches of the | |
2388 | conditional, so we can ensure there is a single move insn setting | |
2389 | 'target' to tag a REG_EQUAL note on. */ | |
2390 | result = gen_reg_rtx (word_mode); | |
2391 | ||
2392 | start_sequence (); | |
2393 | ||
2394 | /* If the high word is not equal to zero, | |
2395 | then clz of the full value is clz of the high word. */ | |
2396 | emit_cmp_and_jump_insns (subhi, CONST0_RTX (word_mode), EQ, 0, | |
2397 | word_mode, true, hi0_label); | |
2398 | ||
2399 | temp = expand_unop_direct (word_mode, clz_optab, subhi, result, true); | |
2400 | if (!temp) | |
2401 | goto fail; | |
2402 | ||
2403 | if (temp != result) | |
2404 | convert_move (result, temp, true); | |
2405 | ||
2406 | emit_jump_insn (gen_jump (after_label)); | |
2407 | emit_barrier (); | |
2408 | ||
2409 | /* Else clz of the full value is clz of the low word plus the number | |
2410 | of bits in the high word. */ | |
2411 | emit_label (hi0_label); | |
2412 | ||
2413 | temp = expand_unop_direct (word_mode, clz_optab, sublo, 0, true); | |
2414 | if (!temp) | |
2415 | goto fail; | |
2416 | temp = expand_binop (word_mode, add_optab, temp, | |
2417 | GEN_INT (GET_MODE_BITSIZE (word_mode)), | |
2418 | result, true, OPTAB_DIRECT); | |
2419 | if (!temp) | |
2420 | goto fail; | |
2421 | if (temp != result) | |
2422 | convert_move (result, temp, true); | |
2423 | ||
2424 | emit_label (after_label); | |
2425 | convert_move (target, result, true); | |
2426 | ||
2427 | seq = get_insns (); | |
2428 | end_sequence (); | |
2429 | ||
2430 | add_equal_note (seq, target, CLZ, xop0, 0); | |
2431 | emit_insn (seq); | |
2432 | return target; | |
2433 | ||
2434 | fail: | |
2435 | end_sequence (); | |
2436 | return 0; | |
2437 | } | |
2438 | ||
2e6834d3 RH |
2439 | /* Try calculating |
2440 | (bswap:narrow x) | |
2441 | as | |
2442 | (lshiftrt:wide (bswap:wide x) ((width wide) - (width narrow))). */ | |
2443 | static rtx | |
2444 | widen_bswap (enum machine_mode mode, rtx op0, rtx target) | |
2445 | { | |
d858f359 | 2446 | enum mode_class mclass = GET_MODE_CLASS (mode); |
2e6834d3 RH |
2447 | enum machine_mode wider_mode; |
2448 | rtx x, last; | |
2449 | ||
d858f359 | 2450 | if (!CLASS_HAS_WIDER_MODES_P (mclass)) |
2e6834d3 RH |
2451 | return NULL_RTX; |
2452 | ||
2453 | for (wider_mode = GET_MODE_WIDER_MODE (mode); | |
2454 | wider_mode != VOIDmode; | |
2455 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) | |
947131ba | 2456 | if (optab_handler (bswap_optab, wider_mode) != CODE_FOR_nothing) |
2e6834d3 RH |
2457 | goto found; |
2458 | return NULL_RTX; | |
2459 | ||
2460 | found: | |
2461 | last = get_last_insn (); | |
2462 | ||
2463 | x = widen_operand (op0, wider_mode, mode, true, true); | |
2464 | x = expand_unop (wider_mode, bswap_optab, x, NULL_RTX, true); | |
2465 | ||
2466 | if (x != 0) | |
2467 | x = expand_shift (RSHIFT_EXPR, wider_mode, x, | |
eb6c3df1 RG |
2468 | GET_MODE_BITSIZE (wider_mode) |
2469 | - GET_MODE_BITSIZE (mode), | |
2e6834d3 RH |
2470 | NULL_RTX, true); |
2471 | ||
2472 | if (x != 0) | |
2473 | { | |
2474 | if (target == 0) | |
2475 | target = gen_reg_rtx (mode); | |
2476 | emit_move_insn (target, gen_lowpart (mode, x)); | |
2477 | } | |
2478 | else | |
2479 | delete_insns_since (last); | |
2480 | ||
2481 | return target; | |
2482 | } | |
2483 | ||
2484 | /* Try calculating bswap as two bswaps of two word-sized operands. */ | |
2485 | ||
2486 | static rtx | |
2487 | expand_doubleword_bswap (enum machine_mode mode, rtx op, rtx target) | |
2488 | { | |
2489 | rtx t0, t1; | |
2490 | ||
2491 | t1 = expand_unop (word_mode, bswap_optab, | |
2492 | operand_subword_force (op, 0, mode), NULL_RTX, true); | |
2493 | t0 = expand_unop (word_mode, bswap_optab, | |
2494 | operand_subword_force (op, 1, mode), NULL_RTX, true); | |
2495 | ||
02972eaf | 2496 | if (target == 0 || !valid_multiword_target_p (target)) |
2e6834d3 RH |
2497 | target = gen_reg_rtx (mode); |
2498 | if (REG_P (target)) | |
c41c1387 | 2499 | emit_clobber (target); |
2e6834d3 RH |
2500 | emit_move_insn (operand_subword (target, 0, 1, mode), t0); |
2501 | emit_move_insn (operand_subword (target, 1, 1, mode), t1); | |
2502 | ||
2503 | return target; | |
2504 | } | |
2505 | ||
2928cd7a RH |
2506 | /* Try calculating (parity x) as (and (popcount x) 1), where |
2507 | popcount can also be done in a wider mode. */ | |
2508 | static rtx | |
0c20a65f | 2509 | expand_parity (enum machine_mode mode, rtx op0, rtx target) |
2928cd7a | 2510 | { |
d858f359 KG |
2511 | enum mode_class mclass = GET_MODE_CLASS (mode); |
2512 | if (CLASS_HAS_WIDER_MODES_P (mclass)) | |
2928cd7a RH |
2513 | { |
2514 | enum machine_mode wider_mode; | |
2515 | for (wider_mode = mode; wider_mode != VOIDmode; | |
2516 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) | |
2517 | { | |
947131ba | 2518 | if (optab_handler (popcount_optab, wider_mode) != CODE_FOR_nothing) |
2928cd7a RH |
2519 | { |
2520 | rtx xop0, temp, last; | |
2521 | ||
2522 | last = get_last_insn (); | |
2523 | ||
2524 | if (target == 0) | |
2525 | target = gen_reg_rtx (mode); | |
2526 | xop0 = widen_operand (op0, wider_mode, mode, true, false); | |
2527 | temp = expand_unop (wider_mode, popcount_optab, xop0, NULL_RTX, | |
2528 | true); | |
2529 | if (temp != 0) | |
60c81c89 | 2530 | temp = expand_binop (wider_mode, and_optab, temp, const1_rtx, |
2928cd7a RH |
2531 | target, true, OPTAB_DIRECT); |
2532 | if (temp == 0) | |
2533 | delete_insns_since (last); | |
2534 | ||
2535 | return temp; | |
2536 | } | |
2537 | } | |
2538 | } | |
2539 | return 0; | |
2540 | } | |
2541 | ||
9cce5b20 | 2542 | /* Try calculating ctz(x) as K - clz(x & -x) , |
69660a70 | 2543 | where K is GET_MODE_PRECISION(mode) - 1. |
9cce5b20 ZW |
2544 | |
2545 | Both __builtin_ctz and __builtin_clz are undefined at zero, so we | |
2546 | don't have to worry about what the hardware does in that case. (If | |
2547 | the clz instruction produces the usual value at 0, which is K, the | |
2548 | result of this code sequence will be -1; expand_ffs, below, relies | |
2549 | on this. It might be nice to have it be K instead, for consistency | |
2550 | with the (very few) processors that provide a ctz with a defined | |
2551 | value, but that would take one more instruction, and it would be | |
2552 | less convenient for expand_ffs anyway. */ | |
2553 | ||
14670a74 | 2554 | static rtx |
9cce5b20 | 2555 | expand_ctz (enum machine_mode mode, rtx op0, rtx target) |
14670a74 | 2556 | { |
9cce5b20 | 2557 | rtx seq, temp; |
b8698a0f | 2558 | |
947131ba | 2559 | if (optab_handler (clz_optab, mode) == CODE_FOR_nothing) |
9cce5b20 | 2560 | return 0; |
b8698a0f | 2561 | |
9cce5b20 | 2562 | start_sequence (); |
14670a74 | 2563 | |
9cce5b20 ZW |
2564 | temp = expand_unop_direct (mode, neg_optab, op0, NULL_RTX, true); |
2565 | if (temp) | |
2566 | temp = expand_binop (mode, and_optab, op0, temp, NULL_RTX, | |
2567 | true, OPTAB_DIRECT); | |
2568 | if (temp) | |
2569 | temp = expand_unop_direct (mode, clz_optab, temp, NULL_RTX, true); | |
2570 | if (temp) | |
69660a70 | 2571 | temp = expand_binop (mode, sub_optab, GEN_INT (GET_MODE_PRECISION (mode) - 1), |
9cce5b20 ZW |
2572 | temp, target, |
2573 | true, OPTAB_DIRECT); | |
2574 | if (temp == 0) | |
2575 | { | |
2576 | end_sequence (); | |
2577 | return 0; | |
14670a74 | 2578 | } |
9cce5b20 ZW |
2579 | |
2580 | seq = get_insns (); | |
2581 | end_sequence (); | |
2582 | ||
2583 | add_equal_note (seq, temp, CTZ, op0, 0); | |
2584 | emit_insn (seq); | |
2585 | return temp; | |
14670a74 SL |
2586 | } |
2587 | ||
9cce5b20 ZW |
2588 | |
2589 | /* Try calculating ffs(x) using ctz(x) if we have that instruction, or | |
2590 | else with the sequence used by expand_clz. | |
b8698a0f | 2591 | |
9cce5b20 ZW |
2592 | The ffs builtin promises to return zero for a zero value and ctz/clz |
2593 | may have an undefined value in that case. If they do not give us a | |
2594 | convenient value, we have to generate a test and branch. */ | |
14670a74 | 2595 | static rtx |
9cce5b20 | 2596 | expand_ffs (enum machine_mode mode, rtx op0, rtx target) |
14670a74 | 2597 | { |
a3324f26 ZW |
2598 | HOST_WIDE_INT val = 0; |
2599 | bool defined_at_zero = false; | |
9cce5b20 ZW |
2600 | rtx temp, seq; |
2601 | ||
947131ba | 2602 | if (optab_handler (ctz_optab, mode) != CODE_FOR_nothing) |
14670a74 | 2603 | { |
9cce5b20 | 2604 | start_sequence (); |
14670a74 | 2605 | |
9cce5b20 ZW |
2606 | temp = expand_unop_direct (mode, ctz_optab, op0, 0, true); |
2607 | if (!temp) | |
2608 | goto fail; | |
2609 | ||
2610 | defined_at_zero = (CTZ_DEFINED_VALUE_AT_ZERO (mode, val) == 2); | |
14670a74 | 2611 | } |
947131ba | 2612 | else if (optab_handler (clz_optab, mode) != CODE_FOR_nothing) |
9cce5b20 ZW |
2613 | { |
2614 | start_sequence (); | |
2615 | temp = expand_ctz (mode, op0, 0); | |
2616 | if (!temp) | |
2617 | goto fail; | |
2618 | ||
2619 | if (CLZ_DEFINED_VALUE_AT_ZERO (mode, val) == 2) | |
2620 | { | |
2621 | defined_at_zero = true; | |
69660a70 | 2622 | val = (GET_MODE_PRECISION (mode) - 1) - val; |
9cce5b20 ZW |
2623 | } |
2624 | } | |
2625 | else | |
2626 | return 0; | |
2627 | ||
2628 | if (defined_at_zero && val == -1) | |
2629 | /* No correction needed at zero. */; | |
b8698a0f | 2630 | else |
9cce5b20 ZW |
2631 | { |
2632 | /* We don't try to do anything clever with the situation found | |
2633 | on some processors (eg Alpha) where ctz(0:mode) == | |
2634 | bitsize(mode). If someone can think of a way to send N to -1 | |
2635 | and leave alone all values in the range 0..N-1 (where N is a | |
2636 | power of two), cheaper than this test-and-branch, please add it. | |
2637 | ||
2638 | The test-and-branch is done after the operation itself, in case | |
2639 | the operation sets condition codes that can be recycled for this. | |
2640 | (This is true on i386, for instance.) */ | |
2641 | ||
2642 | rtx nonzero_label = gen_label_rtx (); | |
2643 | emit_cmp_and_jump_insns (op0, CONST0_RTX (mode), NE, 0, | |
2644 | mode, true, nonzero_label); | |
2645 | ||
2646 | convert_move (temp, GEN_INT (-1), false); | |
2647 | emit_label (nonzero_label); | |
2648 | } | |
2649 | ||
2650 | /* temp now has a value in the range -1..bitsize-1. ffs is supposed | |
2651 | to produce a value in the range 0..bitsize. */ | |
2652 | temp = expand_binop (mode, add_optab, temp, GEN_INT (1), | |
2653 | target, false, OPTAB_DIRECT); | |
2654 | if (!temp) | |
2655 | goto fail; | |
2656 | ||
2657 | seq = get_insns (); | |
2658 | end_sequence (); | |
2659 | ||
2660 | add_equal_note (seq, temp, FFS, op0, 0); | |
2661 | emit_insn (seq); | |
2662 | return temp; | |
2663 | ||
2664 | fail: | |
2665 | end_sequence (); | |
14670a74 SL |
2666 | return 0; |
2667 | } | |
2668 | ||
c414ac1d | 2669 | /* Extract the OMODE lowpart from VAL, which has IMODE. Under certain |
6b132673 RH |
2670 | conditions, VAL may already be a SUBREG against which we cannot generate |
2671 | a further SUBREG. In this case, we expect forcing the value into a | |
2672 | register will work around the situation. */ | |
2673 | ||
2674 | static rtx | |
2675 | lowpart_subreg_maybe_copy (enum machine_mode omode, rtx val, | |
2676 | enum machine_mode imode) | |
2677 | { | |
2678 | rtx ret; | |
2679 | ret = lowpart_subreg (omode, val, imode); | |
2680 | if (ret == NULL) | |
2681 | { | |
2682 | val = force_reg (imode, val); | |
2683 | ret = lowpart_subreg (omode, val, imode); | |
2684 | gcc_assert (ret != NULL); | |
2685 | } | |
2686 | return ret; | |
2687 | } | |
2688 | ||
8c55a142 RH |
2689 | /* Expand a floating point absolute value or negation operation via a |
2690 | logical operation on the sign bit. */ | |
2691 | ||
2692 | static rtx | |
2693 | expand_absneg_bit (enum rtx_code code, enum machine_mode mode, | |
2694 | rtx op0, rtx target) | |
2695 | { | |
2696 | const struct real_format *fmt; | |
2697 | int bitpos, word, nwords, i; | |
2698 | enum machine_mode imode; | |
54fb1ae0 | 2699 | double_int mask; |
8c55a142 RH |
2700 | rtx temp, insns; |
2701 | ||
2702 | /* The format has to have a simple sign bit. */ | |
2703 | fmt = REAL_MODE_FORMAT (mode); | |
2704 | if (fmt == NULL) | |
2705 | return NULL_RTX; | |
2706 | ||
b87a0206 | 2707 | bitpos = fmt->signbit_rw; |
8c55a142 RH |
2708 | if (bitpos < 0) |
2709 | return NULL_RTX; | |
2710 | ||
2711 | /* Don't create negative zeros if the format doesn't support them. */ | |
2712 | if (code == NEG && !fmt->has_signed_zero) | |
2713 | return NULL_RTX; | |
2714 | ||
2715 | if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD) | |
2716 | { | |
2717 | imode = int_mode_for_mode (mode); | |
2718 | if (imode == BLKmode) | |
2719 | return NULL_RTX; | |
2720 | word = 0; | |
2721 | nwords = 1; | |
2722 | } | |
2723 | else | |
2724 | { | |
2725 | imode = word_mode; | |
2726 | ||
2727 | if (FLOAT_WORDS_BIG_ENDIAN) | |
2728 | word = (GET_MODE_BITSIZE (mode) - bitpos) / BITS_PER_WORD; | |
2729 | else | |
2730 | word = bitpos / BITS_PER_WORD; | |
2731 | bitpos = bitpos % BITS_PER_WORD; | |
2732 | nwords = (GET_MODE_BITSIZE (mode) + BITS_PER_WORD - 1) / BITS_PER_WORD; | |
2733 | } | |
2734 | ||
54fb1ae0 | 2735 | mask = double_int_setbit (double_int_zero, bitpos); |
8c55a142 | 2736 | if (code == ABS) |
54fb1ae0 | 2737 | mask = double_int_not (mask); |
8c55a142 | 2738 | |
02972eaf RS |
2739 | if (target == 0 |
2740 | || target == op0 | |
2741 | || (nwords > 1 && !valid_multiword_target_p (target))) | |
8c55a142 RH |
2742 | target = gen_reg_rtx (mode); |
2743 | ||
2744 | if (nwords > 1) | |
2745 | { | |
2746 | start_sequence (); | |
2747 | ||
2748 | for (i = 0; i < nwords; ++i) | |
2749 | { | |
2750 | rtx targ_piece = operand_subword (target, i, 1, mode); | |
2751 | rtx op0_piece = operand_subword_force (op0, i, mode); | |
c414ac1d | 2752 | |
8c55a142 RH |
2753 | if (i == word) |
2754 | { | |
2755 | temp = expand_binop (imode, code == ABS ? and_optab : xor_optab, | |
2756 | op0_piece, | |
54fb1ae0 | 2757 | immed_double_int_const (mask, imode), |
8c55a142 RH |
2758 | targ_piece, 1, OPTAB_LIB_WIDEN); |
2759 | if (temp != targ_piece) | |
2760 | emit_move_insn (targ_piece, temp); | |
2761 | } | |
2762 | else | |
2763 | emit_move_insn (targ_piece, op0_piece); | |
2764 | } | |
2765 | ||
2766 | insns = get_insns (); | |
2767 | end_sequence (); | |
2768 | ||
d70dcf29 | 2769 | emit_insn (insns); |
8c55a142 RH |
2770 | } |
2771 | else | |
2772 | { | |
2773 | temp = expand_binop (imode, code == ABS ? and_optab : xor_optab, | |
2774 | gen_lowpart (imode, op0), | |
54fb1ae0 | 2775 | immed_double_int_const (mask, imode), |
8c55a142 RH |
2776 | gen_lowpart (imode, target), 1, OPTAB_LIB_WIDEN); |
2777 | target = lowpart_subreg_maybe_copy (mode, temp, imode); | |
2778 | ||
2779 | set_unique_reg_note (get_last_insn (), REG_EQUAL, | |
2780 | gen_rtx_fmt_e (code, mode, copy_rtx (op0))); | |
2781 | } | |
2782 | ||
2783 | return target; | |
2784 | } | |
2785 | ||
9cce5b20 ZW |
2786 | /* As expand_unop, but will fail rather than attempt the operation in a |
2787 | different mode or with a libcall. */ | |
2788 | static rtx | |
2789 | expand_unop_direct (enum machine_mode mode, optab unoptab, rtx op0, rtx target, | |
0c20a65f | 2790 | int unsignedp) |
77c9c6c2 | 2791 | { |
947131ba | 2792 | if (optab_handler (unoptab, mode) != CODE_FOR_nothing) |
77c9c6c2 | 2793 | { |
a5c7d693 RS |
2794 | struct expand_operand ops[2]; |
2795 | enum insn_code icode = optab_handler (unoptab, mode); | |
9cce5b20 | 2796 | rtx last = get_last_insn (); |
a5c7d693 | 2797 | rtx pat; |
77c9c6c2 | 2798 | |
a5c7d693 RS |
2799 | create_output_operand (&ops[0], target, mode); |
2800 | create_convert_operand_from (&ops[1], op0, mode, unsignedp); | |
2801 | pat = maybe_gen_insn (icode, 2, ops); | |
77c9c6c2 RK |
2802 | if (pat) |
2803 | { | |
2f937369 | 2804 | if (INSN_P (pat) && NEXT_INSN (pat) != NULL_RTX |
a5c7d693 RS |
2805 | && ! add_equal_note (pat, ops[0].value, unoptab->code, |
2806 | ops[1].value, NULL_RTX)) | |
77c9c6c2 RK |
2807 | { |
2808 | delete_insns_since (last); | |
b1ec3c92 | 2809 | return expand_unop (mode, unoptab, op0, NULL_RTX, unsignedp); |
77c9c6c2 RK |
2810 | } |
2811 | ||
2812 | emit_insn (pat); | |
0c20a65f | 2813 | |
a5c7d693 | 2814 | return ops[0].value; |
77c9c6c2 | 2815 | } |
77c9c6c2 | 2816 | } |
9cce5b20 ZW |
2817 | return 0; |
2818 | } | |
2819 | ||
2820 | /* Generate code to perform an operation specified by UNOPTAB | |
2821 | on operand OP0, with result having machine-mode MODE. | |
2822 | ||
2823 | UNSIGNEDP is for the case where we have to widen the operands | |
2824 | to perform the operation. It says to use zero-extension. | |
2825 | ||
2826 | If TARGET is nonzero, the value | |
2827 | is generated there, if it is convenient to do so. | |
2828 | In all cases an rtx is returned for the locus of the value; | |
2829 | this may or may not be TARGET. */ | |
2830 | ||
2831 | rtx | |
2832 | expand_unop (enum machine_mode mode, optab unoptab, rtx op0, rtx target, | |
2833 | int unsignedp) | |
2834 | { | |
d858f359 | 2835 | enum mode_class mclass = GET_MODE_CLASS (mode); |
9cce5b20 ZW |
2836 | enum machine_mode wider_mode; |
2837 | rtx temp; | |
8a33f100 | 2838 | rtx libfunc; |
9cce5b20 ZW |
2839 | |
2840 | temp = expand_unop_direct (mode, unoptab, op0, target, unsignedp); | |
2841 | if (temp) | |
2842 | return temp; | |
77c9c6c2 | 2843 | |
9a856ec7 RK |
2844 | /* It can't be done in this mode. Can we open-code it in a wider mode? */ |
2845 | ||
9cce5b20 | 2846 | /* Widening (or narrowing) clz needs special treatment. */ |
2928cd7a RH |
2847 | if (unoptab == clz_optab) |
2848 | { | |
3801c801 | 2849 | temp = widen_leading (mode, op0, target, unoptab); |
2928cd7a RH |
2850 | if (temp) |
2851 | return temp; | |
9cce5b20 ZW |
2852 | |
2853 | if (GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD | |
947131ba | 2854 | && optab_handler (unoptab, word_mode) != CODE_FOR_nothing) |
9cce5b20 ZW |
2855 | { |
2856 | temp = expand_doubleword_clz (mode, op0, target); | |
2857 | if (temp) | |
2858 | return temp; | |
2859 | } | |
2860 | ||
3801c801 BS |
2861 | goto try_libcall; |
2862 | } | |
2863 | ||
2864 | if (unoptab == clrsb_optab) | |
2865 | { | |
2866 | temp = widen_leading (mode, op0, target, unoptab); | |
2867 | if (temp) | |
2868 | return temp; | |
2869 | goto try_libcall; | |
2928cd7a RH |
2870 | } |
2871 | ||
2e6834d3 | 2872 | /* Widening (or narrowing) bswap needs special treatment. */ |
167fa32c | 2873 | if (unoptab == bswap_optab) |
2e6834d3 RH |
2874 | { |
2875 | temp = widen_bswap (mode, op0, target); | |
2876 | if (temp) | |
2877 | return temp; | |
2878 | ||
2879 | if (GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD | |
947131ba | 2880 | && optab_handler (unoptab, word_mode) != CODE_FOR_nothing) |
2e6834d3 RH |
2881 | { |
2882 | temp = expand_doubleword_bswap (mode, op0, target); | |
2883 | if (temp) | |
2884 | return temp; | |
2885 | } | |
2886 | ||
2887 | goto try_libcall; | |
2888 | } | |
167fa32c | 2889 | |
d858f359 | 2890 | if (CLASS_HAS_WIDER_MODES_P (mclass)) |
86556d87 BE |
2891 | for (wider_mode = GET_MODE_WIDER_MODE (mode); |
2892 | wider_mode != VOIDmode; | |
9a856ec7 RK |
2893 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) |
2894 | { | |
947131ba | 2895 | if (optab_handler (unoptab, wider_mode) != CODE_FOR_nothing) |
9a856ec7 RK |
2896 | { |
2897 | rtx xop0 = op0; | |
9cce5b20 | 2898 | rtx last = get_last_insn (); |
9a856ec7 RK |
2899 | |
2900 | /* For certain operations, we need not actually extend | |
2901 | the narrow operand, as long as we will truncate the | |
835532b8 RK |
2902 | results to the same narrowness. */ |
2903 | ||
0661a3de | 2904 | xop0 = widen_operand (xop0, wider_mode, mode, unsignedp, |
835532b8 RK |
2905 | (unoptab == neg_optab |
2906 | || unoptab == one_cmpl_optab) | |
d858f359 | 2907 | && mclass == MODE_INT); |
0c20a65f | 2908 | |
b1ec3c92 CH |
2909 | temp = expand_unop (wider_mode, unoptab, xop0, NULL_RTX, |
2910 | unsignedp); | |
9a856ec7 RK |
2911 | |
2912 | if (temp) | |
2913 | { | |
d858f359 | 2914 | if (mclass != MODE_INT |
d0edd768 | 2915 | || !TRULY_NOOP_TRUNCATION_MODES_P (mode, wider_mode)) |
9a856ec7 RK |
2916 | { |
2917 | if (target == 0) | |
2918 | target = gen_reg_rtx (mode); | |
2919 | convert_move (target, temp, 0); | |
2920 | return target; | |
2921 | } | |
2922 | else | |
2923 | return gen_lowpart (mode, temp); | |
2924 | } | |
2925 | else | |
2926 | delete_insns_since (last); | |
2927 | } | |
2928 | } | |
2929 | ||
77c9c6c2 RK |
2930 | /* These can be done a word at a time. */ |
2931 | if (unoptab == one_cmpl_optab | |
d858f359 | 2932 | && mclass == MODE_INT |
77c9c6c2 | 2933 | && GET_MODE_SIZE (mode) > UNITS_PER_WORD |
947131ba | 2934 | && optab_handler (unoptab, word_mode) != CODE_FOR_nothing) |
77c9c6c2 | 2935 | { |
bb93b973 | 2936 | int i; |
77c9c6c2 RK |
2937 | rtx insns; |
2938 | ||
02972eaf | 2939 | if (target == 0 || target == op0 || !valid_multiword_target_p (target)) |
77c9c6c2 RK |
2940 | target = gen_reg_rtx (mode); |
2941 | ||
2942 | start_sequence (); | |
2943 | ||
2944 | /* Do the actual arithmetic. */ | |
2945 | for (i = 0; i < GET_MODE_BITSIZE (mode) / BITS_PER_WORD; i++) | |
2946 | { | |
2947 | rtx target_piece = operand_subword (target, i, 1, mode); | |
34e56753 | 2948 | rtx x = expand_unop (word_mode, unoptab, |
77c9c6c2 RK |
2949 | operand_subword_force (op0, i, mode), |
2950 | target_piece, unsignedp); | |
bb93b973 | 2951 | |
77c9c6c2 RK |
2952 | if (target_piece != x) |
2953 | emit_move_insn (target_piece, x); | |
2954 | } | |
2955 | ||
2956 | insns = get_insns (); | |
2957 | end_sequence (); | |
2958 | ||
d70dcf29 | 2959 | emit_insn (insns); |
77c9c6c2 RK |
2960 | return target; |
2961 | } | |
2962 | ||
8c55a142 | 2963 | if (unoptab->code == NEG) |
4977bab6 | 2964 | { |
8c55a142 | 2965 | /* Try negating floating point values by flipping the sign bit. */ |
74b14698 | 2966 | if (SCALAR_FLOAT_MODE_P (mode)) |
4977bab6 | 2967 | { |
8c55a142 RH |
2968 | temp = expand_absneg_bit (NEG, mode, op0, target); |
2969 | if (temp) | |
2970 | return temp; | |
2971 | } | |
9ee0a442 | 2972 | |
8c55a142 RH |
2973 | /* If there is no negation pattern, and we have no negative zero, |
2974 | try subtracting from zero. */ | |
2975 | if (!HONOR_SIGNED_ZEROS (mode)) | |
2976 | { | |
2977 | temp = expand_binop (mode, (unoptab == negv_optab | |
2978 | ? subv_optab : sub_optab), | |
2979 | CONST0_RTX (mode), op0, target, | |
2980 | unsignedp, OPTAB_DIRECT); | |
2981 | if (temp) | |
2982 | return temp; | |
2983 | } | |
4977bab6 ZW |
2984 | } |
2985 | ||
2928cd7a RH |
2986 | /* Try calculating parity (x) as popcount (x) % 2. */ |
2987 | if (unoptab == parity_optab) | |
2988 | { | |
2989 | temp = expand_parity (mode, op0, target); | |
2990 | if (temp) | |
2991 | return temp; | |
2992 | } | |
2993 | ||
14670a74 SL |
2994 | /* Try implementing ffs (x) in terms of clz (x). */ |
2995 | if (unoptab == ffs_optab) | |
2996 | { | |
2997 | temp = expand_ffs (mode, op0, target); | |
2998 | if (temp) | |
2999 | return temp; | |
3000 | } | |
3001 | ||
3002 | /* Try implementing ctz (x) in terms of clz (x). */ | |
3003 | if (unoptab == ctz_optab) | |
3004 | { | |
3005 | temp = expand_ctz (mode, op0, target); | |
3006 | if (temp) | |
3007 | return temp; | |
3008 | } | |
3009 | ||
2928cd7a | 3010 | try_libcall: |
139e5e08 | 3011 | /* Now try a library call in this mode. */ |
8a33f100 JH |
3012 | libfunc = optab_libfunc (unoptab, mode); |
3013 | if (libfunc) | |
77c9c6c2 RK |
3014 | { |
3015 | rtx insns; | |
9a7f678c | 3016 | rtx value; |
1230d7f8 | 3017 | rtx eq_value; |
2928cd7a RH |
3018 | enum machine_mode outmode = mode; |
3019 | ||
3020 | /* All of these functions return small values. Thus we choose to | |
3021 | have them return something that isn't a double-word. */ | |
3022 | if (unoptab == ffs_optab || unoptab == clz_optab || unoptab == ctz_optab | |
3801c801 BS |
3023 | || unoptab == clrsb_optab || unoptab == popcount_optab |
3024 | || unoptab == parity_optab) | |
cd2ac05b | 3025 | outmode |
390b17c2 RE |
3026 | = GET_MODE (hard_libcall_value (TYPE_MODE (integer_type_node), |
3027 | optab_libfunc (unoptab, mode))); | |
77c9c6c2 RK |
3028 | |
3029 | start_sequence (); | |
3030 | ||
3031 | /* Pass 1 for NO_QUEUE so we don't lose any increments | |
3032 | if the libcall is cse'd or moved. */ | |
8a33f100 | 3033 | value = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST, outmode, |
2928cd7a | 3034 | 1, op0, mode); |
77c9c6c2 RK |
3035 | insns = get_insns (); |
3036 | end_sequence (); | |
3037 | ||
2928cd7a | 3038 | target = gen_reg_rtx (outmode); |
1230d7f8 RS |
3039 | eq_value = gen_rtx_fmt_e (unoptab->code, mode, op0); |
3040 | if (GET_MODE_SIZE (outmode) < GET_MODE_SIZE (mode)) | |
3041 | eq_value = simplify_gen_unary (TRUNCATE, outmode, eq_value, mode); | |
3042 | else if (GET_MODE_SIZE (outmode) > GET_MODE_SIZE (mode)) | |
3043 | eq_value = simplify_gen_unary (ZERO_EXTEND, outmode, eq_value, mode); | |
3044 | emit_libcall_block (insns, target, value, eq_value); | |
77c9c6c2 RK |
3045 | |
3046 | return target; | |
3047 | } | |
3048 | ||
3049 | /* It can't be done in this mode. Can we do it in a wider mode? */ | |
3050 | ||
d858f359 | 3051 | if (CLASS_HAS_WIDER_MODES_P (mclass)) |
77c9c6c2 | 3052 | { |
86556d87 BE |
3053 | for (wider_mode = GET_MODE_WIDER_MODE (mode); |
3054 | wider_mode != VOIDmode; | |
77c9c6c2 RK |
3055 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) |
3056 | { | |
947131ba | 3057 | if (optab_handler (unoptab, wider_mode) != CODE_FOR_nothing |
8a33f100 | 3058 | || optab_libfunc (unoptab, wider_mode)) |
77c9c6c2 | 3059 | { |
34e56753 | 3060 | rtx xop0 = op0; |
9cce5b20 | 3061 | rtx last = get_last_insn (); |
34e56753 RS |
3062 | |
3063 | /* For certain operations, we need not actually extend | |
3064 | the narrow operand, as long as we will truncate the | |
3065 | results to the same narrowness. */ | |
3066 | ||
0661a3de | 3067 | xop0 = widen_operand (xop0, wider_mode, mode, unsignedp, |
835532b8 RK |
3068 | (unoptab == neg_optab |
3069 | || unoptab == one_cmpl_optab) | |
d858f359 | 3070 | && mclass == MODE_INT); |
0c20a65f | 3071 | |
b1ec3c92 CH |
3072 | temp = expand_unop (wider_mode, unoptab, xop0, NULL_RTX, |
3073 | unsignedp); | |
34e56753 | 3074 | |
c117dddc | 3075 | /* If we are generating clz using wider mode, adjust the |
146aef0b JJ |
3076 | result. Similarly for clrsb. */ |
3077 | if ((unoptab == clz_optab || unoptab == clrsb_optab) | |
3078 | && temp != 0) | |
c117dddc | 3079 | temp = expand_binop (wider_mode, sub_optab, temp, |
69660a70 BS |
3080 | GEN_INT (GET_MODE_PRECISION (wider_mode) |
3081 | - GET_MODE_PRECISION (mode)), | |
c117dddc KH |
3082 | target, true, OPTAB_DIRECT); |
3083 | ||
34e56753 | 3084 | if (temp) |
77c9c6c2 | 3085 | { |
d858f359 | 3086 | if (mclass != MODE_INT) |
34e56753 RS |
3087 | { |
3088 | if (target == 0) | |
3089 | target = gen_reg_rtx (mode); | |
3090 | convert_move (target, temp, 0); | |
3091 | return target; | |
3092 | } | |
3093 | else | |
3094 | return gen_lowpart (mode, temp); | |
77c9c6c2 RK |
3095 | } |
3096 | else | |
34e56753 | 3097 | delete_insns_since (last); |
77c9c6c2 RK |
3098 | } |
3099 | } | |
3100 | } | |
3101 | ||
8c55a142 RH |
3102 | /* One final attempt at implementing negation via subtraction, |
3103 | this time allowing widening of the operand. */ | |
3104 | if (unoptab->code == NEG && !HONOR_SIGNED_ZEROS (mode)) | |
0c20a65f | 3105 | { |
b82b6eea | 3106 | rtx temp; |
91ce572a CC |
3107 | temp = expand_binop (mode, |
3108 | unoptab == negv_optab ? subv_optab : sub_optab, | |
3109 | CONST0_RTX (mode), op0, | |
3110 | target, unsignedp, OPTAB_LIB_WIDEN); | |
b82b6eea | 3111 | if (temp) |
8c55a142 | 3112 | return temp; |
b82b6eea | 3113 | } |
0c20a65f | 3114 | |
77c9c6c2 RK |
3115 | return 0; |
3116 | } | |
3117 | \f | |
decdfa82 RS |
3118 | /* Emit code to compute the absolute value of OP0, with result to |
3119 | TARGET if convenient. (TARGET may be 0.) The return value says | |
3120 | where the result actually is to be found. | |
3121 | ||
3122 | MODE is the mode of the operand; the mode of the result is | |
3123 | different but can be deduced from MODE. | |
3124 | ||
91813b28 | 3125 | */ |
7fd01431 RK |
3126 | |
3127 | rtx | |
0c20a65f AJ |
3128 | expand_abs_nojump (enum machine_mode mode, rtx op0, rtx target, |
3129 | int result_unsignedp) | |
7fd01431 | 3130 | { |
2ef0a555 | 3131 | rtx temp; |
7fd01431 | 3132 | |
91ce572a CC |
3133 | if (! flag_trapv) |
3134 | result_unsignedp = 1; | |
3135 | ||
7fd01431 | 3136 | /* First try to do it with a special abs instruction. */ |
91ce572a CC |
3137 | temp = expand_unop (mode, result_unsignedp ? abs_optab : absv_optab, |
3138 | op0, target, 0); | |
7fd01431 RK |
3139 | if (temp != 0) |
3140 | return temp; | |
3141 | ||
4977bab6 | 3142 | /* For floating point modes, try clearing the sign bit. */ |
3d8bf70f | 3143 | if (SCALAR_FLOAT_MODE_P (mode)) |
4977bab6 | 3144 | { |
8c55a142 RH |
3145 | temp = expand_absneg_bit (ABS, mode, op0, target); |
3146 | if (temp) | |
3147 | return temp; | |
4977bab6 ZW |
3148 | } |
3149 | ||
14a774a9 | 3150 | /* If we have a MAX insn, we can do this as MAX (x, -x). */ |
947131ba | 3151 | if (optab_handler (smax_optab, mode) != CODE_FOR_nothing |
8c55a142 | 3152 | && !HONOR_SIGNED_ZEROS (mode)) |
14a774a9 RK |
3153 | { |
3154 | rtx last = get_last_insn (); | |
3155 | ||
3156 | temp = expand_unop (mode, neg_optab, op0, NULL_RTX, 0); | |
3157 | if (temp != 0) | |
3158 | temp = expand_binop (mode, smax_optab, op0, temp, target, 0, | |
3159 | OPTAB_WIDEN); | |
3160 | ||
3161 | if (temp != 0) | |
3162 | return temp; | |
3163 | ||
3164 | delete_insns_since (last); | |
3165 | } | |
3166 | ||
7fd01431 RK |
3167 | /* If this machine has expensive jumps, we can do integer absolute |
3168 | value of X as (((signed) x >> (W-1)) ^ x) - ((signed) x >> (W-1)), | |
e1078cfc | 3169 | where W is the width of MODE. */ |
7fd01431 | 3170 | |
3a4fd356 JH |
3171 | if (GET_MODE_CLASS (mode) == MODE_INT |
3172 | && BRANCH_COST (optimize_insn_for_speed_p (), | |
3173 | false) >= 2) | |
7fd01431 RK |
3174 | { |
3175 | rtx extended = expand_shift (RSHIFT_EXPR, mode, op0, | |
69660a70 | 3176 | GET_MODE_PRECISION (mode) - 1, |
7fd01431 RK |
3177 | NULL_RTX, 0); |
3178 | ||
3179 | temp = expand_binop (mode, xor_optab, extended, op0, target, 0, | |
3180 | OPTAB_LIB_WIDEN); | |
3181 | if (temp != 0) | |
91ce572a CC |
3182 | temp = expand_binop (mode, result_unsignedp ? sub_optab : subv_optab, |
3183 | temp, extended, target, 0, OPTAB_LIB_WIDEN); | |
7fd01431 RK |
3184 | |
3185 | if (temp != 0) | |
3186 | return temp; | |
3187 | } | |
3188 | ||
2ef0a555 RH |
3189 | return NULL_RTX; |
3190 | } | |
3191 | ||
3192 | rtx | |
0c20a65f AJ |
3193 | expand_abs (enum machine_mode mode, rtx op0, rtx target, |
3194 | int result_unsignedp, int safe) | |
2ef0a555 RH |
3195 | { |
3196 | rtx temp, op1; | |
3197 | ||
77173bbe KH |
3198 | if (! flag_trapv) |
3199 | result_unsignedp = 1; | |
3200 | ||
2ef0a555 RH |
3201 | temp = expand_abs_nojump (mode, op0, target, result_unsignedp); |
3202 | if (temp != 0) | |
3203 | return temp; | |
3204 | ||
7fd01431 | 3205 | /* If that does not win, use conditional jump and negate. */ |
5c0bf747 RK |
3206 | |
3207 | /* It is safe to use the target if it is the same | |
3208 | as the source if this is also a pseudo register */ | |
f8cfc6aa | 3209 | if (op0 == target && REG_P (op0) |
5c0bf747 RK |
3210 | && REGNO (op0) >= FIRST_PSEUDO_REGISTER) |
3211 | safe = 1; | |
3212 | ||
7fd01431 RK |
3213 | op1 = gen_label_rtx (); |
3214 | if (target == 0 || ! safe | |
3215 | || GET_MODE (target) != mode | |
3c0cb5de | 3216 | || (MEM_P (target) && MEM_VOLATILE_P (target)) |
f8cfc6aa | 3217 | || (REG_P (target) |
7fd01431 RK |
3218 | && REGNO (target) < FIRST_PSEUDO_REGISTER)) |
3219 | target = gen_reg_rtx (mode); | |
3220 | ||
3221 | emit_move_insn (target, op0); | |
3222 | NO_DEFER_POP; | |
3223 | ||
3bf78d3b | 3224 | do_compare_rtx_and_jump (target, CONST0_RTX (mode), GE, 0, mode, |
40e90eac | 3225 | NULL_RTX, NULL_RTX, op1, -1); |
7fd01431 | 3226 | |
91ce572a CC |
3227 | op0 = expand_unop (mode, result_unsignedp ? neg_optab : negv_optab, |
3228 | target, target, 0); | |
7fd01431 RK |
3229 | if (op0 != target) |
3230 | emit_move_insn (target, op0); | |
3231 | emit_label (op1); | |
3232 | OK_DEFER_POP; | |
3233 | return target; | |
3234 | } | |
046625fa | 3235 | |
65026047 ER |
3236 | /* Emit code to compute the one's complement absolute value of OP0 |
3237 | (if (OP0 < 0) OP0 = ~OP0), with result to TARGET if convenient. | |
3238 | (TARGET may be NULL_RTX.) The return value says where the result | |
3239 | actually is to be found. | |
3240 | ||
3241 | MODE is the mode of the operand; the mode of the result is | |
3242 | different but can be deduced from MODE. */ | |
3243 | ||
3244 | rtx | |
3245 | expand_one_cmpl_abs_nojump (enum machine_mode mode, rtx op0, rtx target) | |
3246 | { | |
3247 | rtx temp; | |
3248 | ||
3249 | /* Not applicable for floating point modes. */ | |
3250 | if (FLOAT_MODE_P (mode)) | |
3251 | return NULL_RTX; | |
3252 | ||
3253 | /* If we have a MAX insn, we can do this as MAX (x, ~x). */ | |
947131ba | 3254 | if (optab_handler (smax_optab, mode) != CODE_FOR_nothing) |
65026047 ER |
3255 | { |
3256 | rtx last = get_last_insn (); | |
3257 | ||
3258 | temp = expand_unop (mode, one_cmpl_optab, op0, NULL_RTX, 0); | |
3259 | if (temp != 0) | |
3260 | temp = expand_binop (mode, smax_optab, op0, temp, target, 0, | |
3261 | OPTAB_WIDEN); | |
3262 | ||
3263 | if (temp != 0) | |
3264 | return temp; | |
3265 | ||
3266 | delete_insns_since (last); | |
3267 | } | |
3268 | ||
3269 | /* If this machine has expensive jumps, we can do one's complement | |
3270 | absolute value of X as (((signed) x >> (W-1)) ^ x). */ | |
3271 | ||
3272 | if (GET_MODE_CLASS (mode) == MODE_INT | |
3273 | && BRANCH_COST (optimize_insn_for_speed_p (), | |
3274 | false) >= 2) | |
3275 | { | |
3276 | rtx extended = expand_shift (RSHIFT_EXPR, mode, op0, | |
69660a70 | 3277 | GET_MODE_PRECISION (mode) - 1, |
65026047 ER |
3278 | NULL_RTX, 0); |
3279 | ||
3280 | temp = expand_binop (mode, xor_optab, extended, op0, target, 0, | |
3281 | OPTAB_LIB_WIDEN); | |
3282 | ||
3283 | if (temp != 0) | |
3284 | return temp; | |
3285 | } | |
3286 | ||
3287 | return NULL_RTX; | |
3288 | } | |
3289 | ||
ae394659 RH |
3290 | /* A subroutine of expand_copysign, perform the copysign operation using the |
3291 | abs and neg primitives advertised to exist on the target. The assumption | |
3292 | is that we have a split register file, and leaving op0 in fp registers, | |
3293 | and not playing with subregs so much, will help the register allocator. */ | |
046625fa | 3294 | |
9abd1955 | 3295 | static rtx |
ae394659 RH |
3296 | expand_copysign_absneg (enum machine_mode mode, rtx op0, rtx op1, rtx target, |
3297 | int bitpos, bool op0_is_abs) | |
046625fa | 3298 | { |
046625fa | 3299 | enum machine_mode imode; |
a5c7d693 | 3300 | enum insn_code icode; |
d0c9d431 | 3301 | rtx sign, label; |
046625fa | 3302 | |
ae394659 RH |
3303 | if (target == op1) |
3304 | target = NULL_RTX; | |
046625fa | 3305 | |
d0c9d431 UB |
3306 | /* Check if the back end provides an insn that handles signbit for the |
3307 | argument's mode. */ | |
a5c7d693 | 3308 | icode = optab_handler (signbit_optab, mode); |
d0c9d431 | 3309 | if (icode != CODE_FOR_nothing) |
ae394659 | 3310 | { |
a5c7d693 | 3311 | imode = insn_data[(int) icode].operand[0].mode; |
d0c9d431 UB |
3312 | sign = gen_reg_rtx (imode); |
3313 | emit_unop_insn (icode, sign, op1, UNKNOWN); | |
ae394659 RH |
3314 | } |
3315 | else | |
3316 | { | |
54fb1ae0 | 3317 | double_int mask; |
d0c9d431 UB |
3318 | |
3319 | if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD) | |
3320 | { | |
3321 | imode = int_mode_for_mode (mode); | |
3322 | if (imode == BLKmode) | |
3323 | return NULL_RTX; | |
3324 | op1 = gen_lowpart (imode, op1); | |
3325 | } | |
ae394659 | 3326 | else |
d0c9d431 UB |
3327 | { |
3328 | int word; | |
046625fa | 3329 | |
d0c9d431 UB |
3330 | imode = word_mode; |
3331 | if (FLOAT_WORDS_BIG_ENDIAN) | |
3332 | word = (GET_MODE_BITSIZE (mode) - bitpos) / BITS_PER_WORD; | |
3333 | else | |
3334 | word = bitpos / BITS_PER_WORD; | |
3335 | bitpos = bitpos % BITS_PER_WORD; | |
3336 | op1 = operand_subword_force (op1, word, mode); | |
3337 | } | |
3338 | ||
54fb1ae0 | 3339 | mask = double_int_setbit (double_int_zero, bitpos); |
d0c9d431 | 3340 | |
d0c9d431 | 3341 | sign = expand_binop (imode, and_optab, op1, |
54fb1ae0 | 3342 | immed_double_int_const (mask, imode), |
d0c9d431 | 3343 | NULL_RTX, 1, OPTAB_LIB_WIDEN); |
ae394659 | 3344 | } |
046625fa | 3345 | |
d0c9d431 | 3346 | if (!op0_is_abs) |
8c55a142 | 3347 | { |
d0c9d431 UB |
3348 | op0 = expand_unop (mode, abs_optab, op0, target, 0); |
3349 | if (op0 == NULL) | |
3350 | return NULL_RTX; | |
3351 | target = op0; | |
8c55a142 | 3352 | } |
ae394659 RH |
3353 | else |
3354 | { | |
d0c9d431 UB |
3355 | if (target == NULL_RTX) |
3356 | target = copy_to_reg (op0); | |
3357 | else | |
3358 | emit_move_insn (target, op0); | |
ae394659 RH |
3359 | } |
3360 | ||
ae394659 | 3361 | label = gen_label_rtx (); |
d0c9d431 | 3362 | emit_cmp_and_jump_insns (sign, const0_rtx, EQ, NULL_RTX, imode, 1, label); |
ae394659 RH |
3363 | |
3364 | if (GET_CODE (op0) == CONST_DOUBLE) | |
3365 | op0 = simplify_unary_operation (NEG, mode, op0, mode); | |
3366 | else | |
3367 | op0 = expand_unop (mode, neg_optab, op0, target, 0); | |
3368 | if (op0 != target) | |
3369 | emit_move_insn (target, op0); | |
3370 | ||
3371 | emit_label (label); | |
3372 | ||
3373 | return target; | |
3374 | } | |
3375 | ||
3376 | ||
3377 | /* A subroutine of expand_copysign, perform the entire copysign operation | |
3378 | with integer bitmasks. BITPOS is the position of the sign bit; OP0_IS_ABS | |
3379 | is true if op0 is known to have its sign bit clear. */ | |
3380 | ||
3381 | static rtx | |
3382 | expand_copysign_bit (enum machine_mode mode, rtx op0, rtx op1, rtx target, | |
3383 | int bitpos, bool op0_is_abs) | |
3384 | { | |
3385 | enum machine_mode imode; | |
54fb1ae0 | 3386 | double_int mask; |
ae394659 RH |
3387 | int word, nwords, i; |
3388 | rtx temp, insns; | |
046625fa | 3389 | |
8c55a142 | 3390 | if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD) |
046625fa | 3391 | { |
8c55a142 RH |
3392 | imode = int_mode_for_mode (mode); |
3393 | if (imode == BLKmode) | |
3394 | return NULL_RTX; | |
3395 | word = 0; | |
3396 | nwords = 1; | |
3397 | } | |
3398 | else | |
3399 | { | |
3400 | imode = word_mode; | |
3401 | ||
3402 | if (FLOAT_WORDS_BIG_ENDIAN) | |
3403 | word = (GET_MODE_BITSIZE (mode) - bitpos) / BITS_PER_WORD; | |
3404 | else | |
3405 | word = bitpos / BITS_PER_WORD; | |
3406 | bitpos = bitpos % BITS_PER_WORD; | |
3407 | nwords = (GET_MODE_BITSIZE (mode) + BITS_PER_WORD - 1) / BITS_PER_WORD; | |
046625fa RH |
3408 | } |
3409 | ||
54fb1ae0 | 3410 | mask = double_int_setbit (double_int_zero, bitpos); |
046625fa | 3411 | |
02972eaf RS |
3412 | if (target == 0 |
3413 | || target == op0 | |
3414 | || target == op1 | |
3415 | || (nwords > 1 && !valid_multiword_target_p (target))) | |
8c55a142 RH |
3416 | target = gen_reg_rtx (mode); |
3417 | ||
3418 | if (nwords > 1) | |
046625fa | 3419 | { |
8c55a142 RH |
3420 | start_sequence (); |
3421 | ||
3422 | for (i = 0; i < nwords; ++i) | |
046625fa | 3423 | { |
8c55a142 RH |
3424 | rtx targ_piece = operand_subword (target, i, 1, mode); |
3425 | rtx op0_piece = operand_subword_force (op0, i, mode); | |
c414ac1d | 3426 | |
8c55a142 RH |
3427 | if (i == word) |
3428 | { | |
ae394659 | 3429 | if (!op0_is_abs) |
54fb1ae0 AS |
3430 | op0_piece |
3431 | = expand_binop (imode, and_optab, op0_piece, | |
3432 | immed_double_int_const (double_int_not (mask), | |
3433 | imode), | |
3434 | NULL_RTX, 1, OPTAB_LIB_WIDEN); | |
8c55a142 RH |
3435 | |
3436 | op1 = expand_binop (imode, and_optab, | |
3437 | operand_subword_force (op1, i, mode), | |
54fb1ae0 | 3438 | immed_double_int_const (mask, imode), |
8c55a142 RH |
3439 | NULL_RTX, 1, OPTAB_LIB_WIDEN); |
3440 | ||
3441 | temp = expand_binop (imode, ior_optab, op0_piece, op1, | |
3442 | targ_piece, 1, OPTAB_LIB_WIDEN); | |
3443 | if (temp != targ_piece) | |
3444 | emit_move_insn (targ_piece, temp); | |
3445 | } | |
3446 | else | |
3447 | emit_move_insn (targ_piece, op0_piece); | |
046625fa | 3448 | } |
8c55a142 RH |
3449 | |
3450 | insns = get_insns (); | |
3451 | end_sequence (); | |
3452 | ||
d70dcf29 | 3453 | emit_insn (insns); |
046625fa RH |
3454 | } |
3455 | else | |
8c55a142 RH |
3456 | { |
3457 | op1 = expand_binop (imode, and_optab, gen_lowpart (imode, op1), | |
54fb1ae0 | 3458 | immed_double_int_const (mask, imode), |
8c55a142 RH |
3459 | NULL_RTX, 1, OPTAB_LIB_WIDEN); |
3460 | ||
3461 | op0 = gen_lowpart (imode, op0); | |
ae394659 | 3462 | if (!op0_is_abs) |
8c55a142 | 3463 | op0 = expand_binop (imode, and_optab, op0, |
54fb1ae0 AS |
3464 | immed_double_int_const (double_int_not (mask), |
3465 | imode), | |
8c55a142 RH |
3466 | NULL_RTX, 1, OPTAB_LIB_WIDEN); |
3467 | ||
3468 | temp = expand_binop (imode, ior_optab, op0, op1, | |
3469 | gen_lowpart (imode, target), 1, OPTAB_LIB_WIDEN); | |
3470 | target = lowpart_subreg_maybe_copy (mode, temp, imode); | |
3471 | } | |
046625fa RH |
3472 | |
3473 | return target; | |
3474 | } | |
ae394659 | 3475 | |
c414ac1d | 3476 | /* Expand the C99 copysign operation. OP0 and OP1 must be the same |
ae394659 RH |
3477 | scalar floating point mode. Return NULL if we do not know how to |
3478 | expand the operation inline. */ | |
3479 | ||
3480 | rtx | |
3481 | expand_copysign (rtx op0, rtx op1, rtx target) | |
3482 | { | |
3483 | enum machine_mode mode = GET_MODE (op0); | |
3484 | const struct real_format *fmt; | |
ae394659 RH |
3485 | bool op0_is_abs; |
3486 | rtx temp; | |
3487 | ||
3488 | gcc_assert (SCALAR_FLOAT_MODE_P (mode)); | |
3489 | gcc_assert (GET_MODE (op1) == mode); | |
3490 | ||
3491 | /* First try to do it with a special instruction. */ | |
3492 | temp = expand_binop (mode, copysign_optab, op0, op1, | |
3493 | target, 0, OPTAB_DIRECT); | |
3494 | if (temp) | |
3495 | return temp; | |
3496 | ||
3497 | fmt = REAL_MODE_FORMAT (mode); | |
3498 | if (fmt == NULL || !fmt->has_signed_zero) | |
3499 | return NULL_RTX; | |
3500 | ||
ae394659 RH |
3501 | op0_is_abs = false; |
3502 | if (GET_CODE (op0) == CONST_DOUBLE) | |
3503 | { | |
3504 | if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0))) | |
3505 | op0 = simplify_unary_operation (ABS, mode, op0, mode); | |
3506 | op0_is_abs = true; | |
3507 | } | |
3508 | ||
c064fde5 RS |
3509 | if (fmt->signbit_ro >= 0 |
3510 | && (GET_CODE (op0) == CONST_DOUBLE | |
947131ba RS |
3511 | || (optab_handler (neg_optab, mode) != CODE_FOR_nothing |
3512 | && optab_handler (abs_optab, mode) != CODE_FOR_nothing))) | |
ae394659 RH |
3513 | { |
3514 | temp = expand_copysign_absneg (mode, op0, op1, target, | |
c064fde5 | 3515 | fmt->signbit_ro, op0_is_abs); |
ae394659 RH |
3516 | if (temp) |
3517 | return temp; | |
3518 | } | |
3519 | ||
c064fde5 RS |
3520 | if (fmt->signbit_rw < 0) |
3521 | return NULL_RTX; | |
3522 | return expand_copysign_bit (mode, op0, op1, target, | |
3523 | fmt->signbit_rw, op0_is_abs); | |
ae394659 | 3524 | } |
7fd01431 | 3525 | \f |
77c9c6c2 RK |
3526 | /* Generate an instruction whose insn-code is INSN_CODE, |
3527 | with two operands: an output TARGET and an input OP0. | |
3528 | TARGET *must* be nonzero, and the output is always stored there. | |
3529 | CODE is an rtx code such that (CODE OP0) is an rtx that describes | |
b8698a0f | 3530 | the value that is stored into TARGET. |
77c9c6c2 | 3531 | |
18bd082d JH |
3532 | Return false if expansion failed. */ |
3533 | ||
3534 | bool | |
a5c7d693 RS |
3535 | maybe_emit_unop_insn (enum insn_code icode, rtx target, rtx op0, |
3536 | enum rtx_code code) | |
77c9c6c2 | 3537 | { |
a5c7d693 | 3538 | struct expand_operand ops[2]; |
77c9c6c2 | 3539 | rtx pat; |
77c9c6c2 | 3540 | |
a5c7d693 RS |
3541 | create_output_operand (&ops[0], target, GET_MODE (target)); |
3542 | create_input_operand (&ops[1], op0, GET_MODE (op0)); | |
3543 | pat = maybe_gen_insn (icode, 2, ops); | |
18bd082d | 3544 | if (!pat) |
a5c7d693 | 3545 | return false; |
77c9c6c2 | 3546 | |
2f937369 | 3547 | if (INSN_P (pat) && NEXT_INSN (pat) != NULL_RTX && code != UNKNOWN) |
a5c7d693 | 3548 | add_equal_note (pat, ops[0].value, code, ops[1].value, NULL_RTX); |
0c20a65f | 3549 | |
77c9c6c2 RK |
3550 | emit_insn (pat); |
3551 | ||
a5c7d693 RS |
3552 | if (ops[0].value != target) |
3553 | emit_move_insn (target, ops[0].value); | |
18bd082d JH |
3554 | return true; |
3555 | } | |
3556 | /* Generate an instruction whose insn-code is INSN_CODE, | |
3557 | with two operands: an output TARGET and an input OP0. | |
3558 | TARGET *must* be nonzero, and the output is always stored there. | |
3559 | CODE is an rtx code such that (CODE OP0) is an rtx that describes | |
3560 | the value that is stored into TARGET. */ | |
3561 | ||
3562 | void | |
a5c7d693 | 3563 | emit_unop_insn (enum insn_code icode, rtx target, rtx op0, enum rtx_code code) |
18bd082d JH |
3564 | { |
3565 | bool ok = maybe_emit_unop_insn (icode, target, op0, code); | |
3566 | gcc_assert (ok); | |
77c9c6c2 RK |
3567 | } |
3568 | \f | |
326a31e9 R |
3569 | struct no_conflict_data |
3570 | { | |
3571 | rtx target, first, insn; | |
3572 | bool must_stay; | |
3573 | }; | |
3574 | ||
d70dcf29 KZ |
3575 | /* Called via note_stores by emit_libcall_block. Set P->must_stay if |
3576 | the currently examined clobber / store has to stay in the list of | |
3577 | insns that constitute the actual libcall block. */ | |
326a31e9 | 3578 | static void |
7bc980e1 | 3579 | no_conflict_move_test (rtx dest, const_rtx set, void *p0) |
326a31e9 | 3580 | { |
d3bfe4de | 3581 | struct no_conflict_data *p= (struct no_conflict_data *) p0; |
326a31e9 R |
3582 | |
3583 | /* If this inns directly contributes to setting the target, it must stay. */ | |
3584 | if (reg_overlap_mentioned_p (p->target, dest)) | |
3585 | p->must_stay = true; | |
3586 | /* If we haven't committed to keeping any other insns in the list yet, | |
3587 | there is nothing more to check. */ | |
3588 | else if (p->insn == p->first) | |
3589 | return; | |
3590 | /* If this insn sets / clobbers a register that feeds one of the insns | |
3591 | already in the list, this insn has to stay too. */ | |
9617ccfd R |
3592 | else if (reg_overlap_mentioned_p (dest, PATTERN (p->first)) |
3593 | || (CALL_P (p->first) && (find_reg_fusage (p->first, USE, dest))) | |
326a31e9 R |
3594 | || reg_used_between_p (dest, p->first, p->insn) |
3595 | /* Likewise if this insn depends on a register set by a previous | |
ca7a5aec R |
3596 | insn in the list, or if it sets a result (presumably a hard |
3597 | register) that is set or clobbered by a previous insn. | |
3598 | N.B. the modified_*_p (SET_DEST...) tests applied to a MEM | |
3599 | SET_DEST perform the former check on the address, and the latter | |
3600 | check on the MEM. */ | |
326a31e9 R |
3601 | || (GET_CODE (set) == SET |
3602 | && (modified_in_p (SET_SRC (set), p->first) | |
ca7a5aec R |
3603 | || modified_in_p (SET_DEST (set), p->first) |
3604 | || modified_between_p (SET_SRC (set), p->first, p->insn) | |
3605 | || modified_between_p (SET_DEST (set), p->first, p->insn)))) | |
326a31e9 R |
3606 | p->must_stay = true; |
3607 | } | |
3608 | ||
77c9c6c2 RK |
3609 | \f |
3610 | /* Emit code to make a call to a constant function or a library call. | |
3611 | ||
3612 | INSNS is a list containing all insns emitted in the call. | |
3613 | These insns leave the result in RESULT. Our block is to copy RESULT | |
3614 | to TARGET, which is logically equivalent to EQUIV. | |
3615 | ||
3616 | We first emit any insns that set a pseudo on the assumption that these are | |
3617 | loading constants into registers; doing so allows them to be safely cse'ed | |
3618 | between blocks. Then we emit all the other insns in the block, followed by | |
3619 | an insn to move RESULT to TARGET. This last insn will have a REQ_EQUAL | |
856905c2 SB |
3620 | note with an operand of EQUIV. */ |
3621 | ||
77c9c6c2 | 3622 | void |
0c20a65f | 3623 | emit_libcall_block (rtx insns, rtx target, rtx result, rtx equiv) |
77c9c6c2 | 3624 | { |
aff2c2d3 | 3625 | rtx final_dest = target; |
0f900dfa | 3626 | rtx next, last, insn; |
77c9c6c2 | 3627 | |
aff2c2d3 BS |
3628 | /* If this is a reg with REG_USERVAR_P set, then it could possibly turn |
3629 | into a MEM later. Protect the libcall block from this change. */ | |
3630 | if (! REG_P (target) || REG_USERVAR_P (target)) | |
3631 | target = gen_reg_rtx (GET_MODE (target)); | |
0c20a65f | 3632 | |
5154e79a AH |
3633 | /* If we're using non-call exceptions, a libcall corresponding to an |
3634 | operation that may trap may also trap. */ | |
1d65f45c | 3635 | /* ??? See the comment in front of make_reg_eh_region_note. */ |
8f4f502f | 3636 | if (cfun->can_throw_non_call_exceptions && may_trap_p (equiv)) |
5154e79a AH |
3637 | { |
3638 | for (insn = insns; insn; insn = NEXT_INSN (insn)) | |
4b4bf941 | 3639 | if (CALL_P (insn)) |
5154e79a AH |
3640 | { |
3641 | rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX); | |
1d65f45c RH |
3642 | if (note) |
3643 | { | |
3644 | int lp_nr = INTVAL (XEXP (note, 0)); | |
3645 | if (lp_nr == 0 || lp_nr == INT_MIN) | |
3646 | remove_note (insn, note); | |
3647 | } | |
5154e79a AH |
3648 | } |
3649 | } | |
3650 | else | |
1d65f45c RH |
3651 | { |
3652 | /* Look for any CALL_INSNs in this sequence, and attach a REG_EH_REGION | |
3653 | reg note to indicate that this call cannot throw or execute a nonlocal | |
3654 | goto (unless there is already a REG_EH_REGION note, in which case | |
3655 | we update it). */ | |
3656 | for (insn = insns; insn; insn = NEXT_INSN (insn)) | |
3657 | if (CALL_P (insn)) | |
3658 | make_reg_eh_region_note_nothrow_nononlocal (insn); | |
3659 | } | |
b472794d | 3660 | |
77c9c6c2 | 3661 | /* First emit all insns that set pseudos. Remove them from the list as |
ccf5f342 | 3662 | we go. Avoid insns that set pseudos which were referenced in previous |
29ebe69a | 3663 | insns. These can be generated by move_by_pieces, for example, |
ccf5f342 RK |
3664 | to update an address. Similarly, avoid insns that reference things |
3665 | set in previous insns. */ | |
77c9c6c2 RK |
3666 | |
3667 | for (insn = insns; insn; insn = next) | |
3668 | { | |
3669 | rtx set = single_set (insn); | |
3670 | ||
3671 | next = NEXT_INSN (insn); | |
3672 | ||
f8cfc6aa | 3673 | if (set != 0 && REG_P (SET_DEST (set)) |
748ebfc7 | 3674 | && REGNO (SET_DEST (set)) >= FIRST_PSEUDO_REGISTER) |
77c9c6c2 | 3675 | { |
748ebfc7 R |
3676 | struct no_conflict_data data; |
3677 | ||
3678 | data.target = const0_rtx; | |
3679 | data.first = insns; | |
3680 | data.insn = insn; | |
3681 | data.must_stay = 0; | |
3682 | note_stores (PATTERN (insn), no_conflict_move_test, &data); | |
3683 | if (! data.must_stay) | |
3684 | { | |
3685 | if (PREV_INSN (insn)) | |
3686 | NEXT_INSN (PREV_INSN (insn)) = next; | |
3687 | else | |
3688 | insns = next; | |
77c9c6c2 | 3689 | |
748ebfc7 R |
3690 | if (next) |
3691 | PREV_INSN (next) = PREV_INSN (insn); | |
77c9c6c2 | 3692 | |
748ebfc7 R |
3693 | add_insn (insn); |
3694 | } | |
77c9c6c2 | 3695 | } |
695a94b3 RS |
3696 | |
3697 | /* Some ports use a loop to copy large arguments onto the stack. | |
3698 | Don't move anything outside such a loop. */ | |
4b4bf941 | 3699 | if (LABEL_P (insn)) |
695a94b3 | 3700 | break; |
77c9c6c2 RK |
3701 | } |
3702 | ||
77c9c6c2 | 3703 | /* Write the remaining insns followed by the final copy. */ |
77c9c6c2 RK |
3704 | for (insn = insns; insn; insn = next) |
3705 | { | |
3706 | next = NEXT_INSN (insn); | |
3707 | ||
3708 | add_insn (insn); | |
3709 | } | |
3710 | ||
3711 | last = emit_move_insn (target, result); | |
947131ba | 3712 | if (optab_handler (mov_optab, GET_MODE (target)) != CODE_FOR_nothing) |
5fa671cf | 3713 | set_unique_reg_note (last, REG_EQUAL, copy_rtx (equiv)); |
77c9c6c2 | 3714 | |
e85427f9 BS |
3715 | if (final_dest != target) |
3716 | emit_move_insn (final_dest, target); | |
77c9c6c2 RK |
3717 | } |
3718 | \f | |
1c0290ea | 3719 | /* Nonzero if we can perform a comparison of mode MODE straightforwardly. |
1eb8759b RH |
3720 | PURPOSE describes how this comparison will be used. CODE is the rtx |
3721 | comparison code we will be using. | |
3722 | ||
3723 | ??? Actually, CODE is slightly weaker than that. A target is still | |
0c20a65f | 3724 | required to implement all of the normal bcc operations, but not |
1eb8759b | 3725 | required to implement all (or any) of the unordered bcc operations. */ |
0c20a65f | 3726 | |
1c0290ea | 3727 | int |
0c20a65f AJ |
3728 | can_compare_p (enum rtx_code code, enum machine_mode mode, |
3729 | enum can_compare_purpose purpose) | |
b30f05db | 3730 | { |
c3c64f50 PB |
3731 | rtx test; |
3732 | test = gen_rtx_fmt_ee (code, mode, const0_rtx, const0_rtx); | |
b30f05db BS |
3733 | do |
3734 | { | |
2ef6ce06 | 3735 | enum insn_code icode; |
c3c64f50 | 3736 | |
1c0290ea | 3737 | if (purpose == ccp_jump |
947131ba | 3738 | && (icode = optab_handler (cbranch_optab, mode)) != CODE_FOR_nothing |
2ef6ce06 | 3739 | && insn_operand_matches (icode, 0, test)) |
c3c64f50 PB |
3740 | return 1; |
3741 | if (purpose == ccp_store_flag | |
947131ba | 3742 | && (icode = optab_handler (cstore_optab, mode)) != CODE_FOR_nothing |
2ef6ce06 | 3743 | && insn_operand_matches (icode, 1, test)) |
c3c64f50 | 3744 | return 1; |
1c0290ea | 3745 | if (purpose == ccp_cmov |
947131ba | 3746 | && optab_handler (cmov_optab, mode) != CODE_FOR_nothing) |
1c0290ea | 3747 | return 1; |
c3c64f50 | 3748 | |
b30f05db | 3749 | mode = GET_MODE_WIDER_MODE (mode); |
c3c64f50 | 3750 | PUT_MODE (test, mode); |
1c0290ea BS |
3751 | } |
3752 | while (mode != VOIDmode); | |
b30f05db BS |
3753 | |
3754 | return 0; | |
3755 | } | |
3756 | ||
3757 | /* This function is called when we are going to emit a compare instruction that | |
3758 | compares the values found in *PX and *PY, using the rtl operator COMPARISON. | |
3759 | ||
3760 | *PMODE is the mode of the inputs (in case they are const_int). | |
3761 | *PUNSIGNEDP nonzero says that the operands are unsigned; | |
f90b7a5a | 3762 | this matters if they need to be widened (as given by METHODS). |
77c9c6c2 | 3763 | |
a06ef755 | 3764 | If they have mode BLKmode, then SIZE specifies the size of both operands. |
77c9c6c2 | 3765 | |
b30f05db BS |
3766 | This function performs all the setup necessary so that the caller only has |
3767 | to emit a single comparison insn. This setup can involve doing a BLKmode | |
3768 | comparison or emitting a library call to perform the comparison if no insn | |
3769 | is available to handle it. | |
3770 | The values which are passed in through pointers can be modified; the caller | |
0e61db61 NS |
3771 | should perform the comparison on the modified values. Constant |
3772 | comparisons must have already been folded. */ | |
77c9c6c2 | 3773 | |
a06ef755 | 3774 | static void |
f90b7a5a PB |
3775 | prepare_cmp_insn (rtx x, rtx y, enum rtx_code comparison, rtx size, |
3776 | int unsignedp, enum optab_methods methods, | |
3777 | rtx *ptest, enum machine_mode *pmode) | |
77c9c6c2 | 3778 | { |
b30f05db | 3779 | enum machine_mode mode = *pmode; |
f90b7a5a PB |
3780 | rtx libfunc, test; |
3781 | enum machine_mode cmp_mode; | |
3782 | enum mode_class mclass; | |
3783 | ||
3784 | /* The other methods are not needed. */ | |
3785 | gcc_assert (methods == OPTAB_DIRECT || methods == OPTAB_WIDEN | |
3786 | || methods == OPTAB_LIB_WIDEN); | |
77c9c6c2 | 3787 | |
5e8d1826 PB |
3788 | /* If we are optimizing, force expensive constants into a register. */ |
3789 | if (CONSTANT_P (x) && optimize | |
3790 | && (rtx_cost (x, COMPARE, optimize_insn_for_speed_p ()) | |
3791 | > COSTS_N_INSNS (1))) | |
3792 | x = force_reg (mode, x); | |
3793 | ||
3794 | if (CONSTANT_P (y) && optimize | |
3795 | && (rtx_cost (y, COMPARE, optimize_insn_for_speed_p ()) | |
3796 | > COSTS_N_INSNS (1))) | |
3797 | y = force_reg (mode, y); | |
3798 | ||
362cc3d4 | 3799 | #ifdef HAVE_cc0 |
0e61db61 NS |
3800 | /* Make sure if we have a canonical comparison. The RTL |
3801 | documentation states that canonical comparisons are required only | |
3802 | for targets which have cc0. */ | |
e3feb571 | 3803 | gcc_assert (!CONSTANT_P (x) || CONSTANT_P (y)); |
362cc3d4 MH |
3804 | #endif |
3805 | ||
77c9c6c2 RK |
3806 | /* Don't let both operands fail to indicate the mode. */ |
3807 | if (GET_MODE (x) == VOIDmode && GET_MODE (y) == VOIDmode) | |
3808 | x = force_reg (mode, x); | |
f90b7a5a PB |
3809 | if (mode == VOIDmode) |
3810 | mode = GET_MODE (x) != VOIDmode ? GET_MODE (x) : GET_MODE (y); | |
77c9c6c2 RK |
3811 | |
3812 | /* Handle all BLKmode compares. */ | |
3813 | ||
3814 | if (mode == BLKmode) | |
3815 | { | |
f90b7a5a | 3816 | enum machine_mode result_mode; |
118355a0 ZW |
3817 | enum insn_code cmp_code; |
3818 | tree length_type; | |
3819 | rtx libfunc; | |
b30f05db | 3820 | rtx result; |
118355a0 | 3821 | rtx opalign |
f4dc10d1 | 3822 | = GEN_INT (MIN (MEM_ALIGN (x), MEM_ALIGN (y)) / BITS_PER_UNIT); |
b30f05db | 3823 | |
e3feb571 | 3824 | gcc_assert (size); |
118355a0 | 3825 | |
118355a0 ZW |
3826 | /* Try to use a memory block compare insn - either cmpstr |
3827 | or cmpmem will do. */ | |
3828 | for (cmp_mode = GET_CLASS_NARROWEST_MODE (MODE_INT); | |
3829 | cmp_mode != VOIDmode; | |
3830 | cmp_mode = GET_MODE_WIDER_MODE (cmp_mode)) | |
358b8f01 | 3831 | { |
f9621cc4 | 3832 | cmp_code = direct_optab_handler (cmpmem_optab, cmp_mode); |
118355a0 | 3833 | if (cmp_code == CODE_FOR_nothing) |
f9621cc4 | 3834 | cmp_code = direct_optab_handler (cmpstr_optab, cmp_mode); |
40c1d5f8 | 3835 | if (cmp_code == CODE_FOR_nothing) |
f9621cc4 | 3836 | cmp_code = direct_optab_handler (cmpstrn_optab, cmp_mode); |
118355a0 ZW |
3837 | if (cmp_code == CODE_FOR_nothing) |
3838 | continue; | |
3839 | ||
3840 | /* Must make sure the size fits the insn's mode. */ | |
481683e1 | 3841 | if ((CONST_INT_P (size) |
118355a0 ZW |
3842 | && INTVAL (size) >= (1 << GET_MODE_BITSIZE (cmp_mode))) |
3843 | || (GET_MODE_BITSIZE (GET_MODE (size)) | |
3844 | > GET_MODE_BITSIZE (cmp_mode))) | |
3845 | continue; | |
3846 | ||
3847 | result_mode = insn_data[cmp_code].operand[0].mode; | |
358b8f01 | 3848 | result = gen_reg_rtx (result_mode); |
118355a0 ZW |
3849 | size = convert_to_mode (cmp_mode, size, 1); |
3850 | emit_insn (GEN_FCN (cmp_code) (result, x, y, size, opalign)); | |
3851 | ||
f90b7a5a PB |
3852 | *ptest = gen_rtx_fmt_ee (comparison, VOIDmode, result, const0_rtx); |
3853 | *pmode = result_mode; | |
118355a0 | 3854 | return; |
77c9c6c2 | 3855 | } |
118355a0 | 3856 | |
f90b7a5a PB |
3857 | if (methods != OPTAB_LIB && methods != OPTAB_LIB_WIDEN) |
3858 | goto fail; | |
3859 | ||
8f99553f | 3860 | /* Otherwise call a library function, memcmp. */ |
118355a0 ZW |
3861 | libfunc = memcmp_libfunc; |
3862 | length_type = sizetype; | |
118355a0 ZW |
3863 | result_mode = TYPE_MODE (integer_type_node); |
3864 | cmp_mode = TYPE_MODE (length_type); | |
3865 | size = convert_to_mode (TYPE_MODE (length_type), size, | |
8df83eae | 3866 | TYPE_UNSIGNED (length_type)); |
118355a0 | 3867 | |
84b8030f | 3868 | result = emit_library_call_value (libfunc, 0, LCT_PURE, |
118355a0 ZW |
3869 | result_mode, 3, |
3870 | XEXP (x, 0), Pmode, | |
3871 | XEXP (y, 0), Pmode, | |
3872 | size, cmp_mode); | |
f90b7a5a PB |
3873 | |
3874 | *ptest = gen_rtx_fmt_ee (comparison, VOIDmode, result, const0_rtx); | |
b30f05db | 3875 | *pmode = result_mode; |
77c9c6c2 RK |
3876 | return; |
3877 | } | |
3878 | ||
27ab3e91 RH |
3879 | /* Don't allow operands to the compare to trap, as that can put the |
3880 | compare and branch in different basic blocks. */ | |
8f4f502f | 3881 | if (cfun->can_throw_non_call_exceptions) |
27ab3e91 RH |
3882 | { |
3883 | if (may_trap_p (x)) | |
3884 | x = force_reg (mode, x); | |
3885 | if (may_trap_p (y)) | |
3886 | y = force_reg (mode, y); | |
3887 | } | |
3888 | ||
4a77c72b PB |
3889 | if (GET_MODE_CLASS (mode) == MODE_CC) |
3890 | { | |
f90b7a5a PB |
3891 | gcc_assert (can_compare_p (comparison, CCmode, ccp_jump)); |
3892 | *ptest = gen_rtx_fmt_ee (comparison, VOIDmode, x, y); | |
4a77c72b PB |
3893 | return; |
3894 | } | |
77c9c6c2 | 3895 | |
f90b7a5a PB |
3896 | mclass = GET_MODE_CLASS (mode); |
3897 | test = gen_rtx_fmt_ee (comparison, VOIDmode, x, y); | |
3898 | cmp_mode = mode; | |
3899 | do | |
3900 | { | |
3901 | enum insn_code icode; | |
947131ba | 3902 | icode = optab_handler (cbranch_optab, cmp_mode); |
f90b7a5a | 3903 | if (icode != CODE_FOR_nothing |
2ef6ce06 | 3904 | && insn_operand_matches (icode, 0, test)) |
f90b7a5a PB |
3905 | { |
3906 | rtx last = get_last_insn (); | |
3907 | rtx op0 = prepare_operand (icode, x, 1, mode, cmp_mode, unsignedp); | |
3908 | rtx op1 = prepare_operand (icode, y, 2, mode, cmp_mode, unsignedp); | |
3909 | if (op0 && op1 | |
2ef6ce06 RS |
3910 | && insn_operand_matches (icode, 1, op0) |
3911 | && insn_operand_matches (icode, 2, op1)) | |
f90b7a5a PB |
3912 | { |
3913 | XEXP (test, 0) = op0; | |
3914 | XEXP (test, 1) = op1; | |
3915 | *ptest = test; | |
3916 | *pmode = cmp_mode; | |
3917 | return; | |
3918 | } | |
3919 | delete_insns_since (last); | |
3920 | } | |
3921 | ||
3922 | if (methods == OPTAB_DIRECT || !CLASS_HAS_WIDER_MODES_P (mclass)) | |
3923 | break; | |
3924 | cmp_mode = GET_MODE_WIDER_MODE (cmp_mode); | |
3925 | } | |
3926 | while (cmp_mode != VOIDmode); | |
3927 | ||
3928 | if (methods != OPTAB_LIB_WIDEN) | |
3929 | goto fail; | |
3930 | ||
3931 | if (!SCALAR_FLOAT_MODE_P (mode)) | |
77c9c6c2 | 3932 | { |
9725066d JL |
3933 | rtx result; |
3934 | ||
f90b7a5a PB |
3935 | /* Handle a libcall just for the mode we are using. */ |
3936 | libfunc = optab_libfunc (cmp_optab, mode); | |
3937 | gcc_assert (libfunc); | |
3938 | ||
77c9c6c2 RK |
3939 | /* If we want unsigned, and this mode has a distinct unsigned |
3940 | comparison routine, use that. */ | |
8a33f100 JH |
3941 | if (unsignedp) |
3942 | { | |
ba8a73e9 EB |
3943 | rtx ulibfunc = optab_libfunc (ucmp_optab, mode); |
3944 | if (ulibfunc) | |
3945 | libfunc = ulibfunc; | |
8a33f100 | 3946 | } |
77c9c6c2 | 3947 | |
84b8030f | 3948 | result = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST, |
c7ff6e7a AK |
3949 | targetm.libgcc_cmp_return_mode (), |
3950 | 2, x, mode, y, mode); | |
9725066d | 3951 | |
f34312c2 CD |
3952 | /* There are two kinds of comparison routines. Biased routines |
3953 | return 0/1/2, and unbiased routines return -1/0/1. Other parts | |
3954 | of gcc expect that the comparison operation is equivalent | |
b8698a0f | 3955 | to the modified comparison. For signed comparisons compare the |
f34312c2 CD |
3956 | result against 1 in the biased case, and zero in the unbiased |
3957 | case. For unsigned comparisons always compare against 1 after | |
917f1b7e | 3958 | biasing the unbiased result by adding 1. This gives us a way to |
f34312c2 | 3959 | represent LTU. */ |
f90b7a5a PB |
3960 | x = result; |
3961 | y = const1_rtx; | |
f34312c2 CD |
3962 | |
3963 | if (!TARGET_LIB_INT_CMP_BIASED) | |
b3f8d95d | 3964 | { |
f90b7a5a | 3965 | if (unsignedp) |
b8698a0f | 3966 | x = plus_constant (result, 1); |
f34312c2 | 3967 | else |
f90b7a5a | 3968 | y = const0_rtx; |
b3f8d95d | 3969 | } |
f90b7a5a PB |
3970 | |
3971 | *pmode = word_mode; | |
3972 | prepare_cmp_insn (x, y, comparison, NULL_RTX, unsignedp, methods, | |
3973 | ptest, pmode); | |
77c9c6c2 | 3974 | } |
b8698a0f | 3975 | else |
f90b7a5a | 3976 | prepare_float_lib_cmp (x, y, comparison, ptest, pmode); |
77c9c6c2 | 3977 | |
f90b7a5a PB |
3978 | return; |
3979 | ||
3980 | fail: | |
3981 | *ptest = NULL_RTX; | |
77c9c6c2 RK |
3982 | } |
3983 | ||
b30f05db BS |
3984 | /* Before emitting an insn with code ICODE, make sure that X, which is going |
3985 | to be used for operand OPNUM of the insn, is converted from mode MODE to | |
4fe9b91c | 3986 | WIDER_MODE (UNSIGNEDP determines whether it is an unsigned conversion), and |
b30f05db | 3987 | that it is accepted by the operand predicate. Return the new value. */ |
749a2da1 | 3988 | |
f90b7a5a | 3989 | rtx |
2ef6ce06 | 3990 | prepare_operand (enum insn_code icode, rtx x, int opnum, enum machine_mode mode, |
0c20a65f | 3991 | enum machine_mode wider_mode, int unsignedp) |
b30f05db | 3992 | { |
b30f05db BS |
3993 | if (mode != wider_mode) |
3994 | x = convert_modes (wider_mode, mode, x, unsignedp); | |
3995 | ||
2ef6ce06 | 3996 | if (!insn_operand_matches (icode, opnum, x)) |
d893ccde | 3997 | { |
ef4375b2 | 3998 | if (reload_completed) |
d893ccde | 3999 | return NULL_RTX; |
2ef6ce06 | 4000 | x = copy_to_mode_reg (insn_data[(int) icode].operand[opnum].mode, x); |
d893ccde RH |
4001 | } |
4002 | ||
b30f05db BS |
4003 | return x; |
4004 | } | |
4005 | ||
4006 | /* Subroutine of emit_cmp_and_jump_insns; this function is called when we know | |
f90b7a5a | 4007 | we can do the branch. */ |
b30f05db BS |
4008 | |
4009 | static void | |
f90b7a5a | 4010 | emit_cmp_and_jump_insn_1 (rtx test, enum machine_mode mode, rtx label) |
b30f05db | 4011 | { |
f90b7a5a PB |
4012 | enum machine_mode optab_mode; |
4013 | enum mode_class mclass; | |
4014 | enum insn_code icode; | |
b30f05db | 4015 | |
f90b7a5a PB |
4016 | mclass = GET_MODE_CLASS (mode); |
4017 | optab_mode = (mclass == MODE_CC) ? CCmode : mode; | |
947131ba | 4018 | icode = optab_handler (cbranch_optab, optab_mode); |
8127d0e0 | 4019 | |
f90b7a5a | 4020 | gcc_assert (icode != CODE_FOR_nothing); |
2ef6ce06 | 4021 | gcc_assert (insn_operand_matches (icode, 0, test)); |
f90b7a5a | 4022 | emit_jump_insn (GEN_FCN (icode) (test, XEXP (test, 0), XEXP (test, 1), label)); |
b30f05db BS |
4023 | } |
4024 | ||
362cc3d4 MH |
4025 | /* Generate code to compare X with Y so that the condition codes are |
4026 | set and to jump to LABEL if the condition is true. If X is a | |
4027 | constant and Y is not a constant, then the comparison is swapped to | |
4028 | ensure that the comparison RTL has the canonical form. | |
4029 | ||
c5d5d461 | 4030 | UNSIGNEDP nonzero says that X and Y are unsigned; this matters if they |
f90b7a5a PB |
4031 | need to be widened. UNSIGNEDP is also used to select the proper |
4032 | branch condition code. | |
362cc3d4 | 4033 | |
a06ef755 | 4034 | If X and Y have mode BLKmode, then SIZE specifies the size of both X and Y. |
362cc3d4 | 4035 | |
c5d5d461 JL |
4036 | MODE is the mode of the inputs (in case they are const_int). |
4037 | ||
f90b7a5a PB |
4038 | COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.). |
4039 | It will be potentially converted into an unsigned variant based on | |
4040 | UNSIGNEDP to select a proper jump instruction. */ | |
362cc3d4 MH |
4041 | |
4042 | void | |
0c20a65f AJ |
4043 | emit_cmp_and_jump_insns (rtx x, rtx y, enum rtx_code comparison, rtx size, |
4044 | enum machine_mode mode, int unsignedp, rtx label) | |
362cc3d4 | 4045 | { |
8c9864f3 | 4046 | rtx op0 = x, op1 = y; |
f90b7a5a | 4047 | rtx test; |
8c9864f3 JH |
4048 | |
4049 | /* Swap operands and condition to ensure canonical RTL. */ | |
45475a3f PB |
4050 | if (swap_commutative_operands_p (x, y) |
4051 | && can_compare_p (swap_condition (comparison), mode, ccp_jump)) | |
362cc3d4 | 4052 | { |
8c9864f3 JH |
4053 | op0 = y, op1 = x; |
4054 | comparison = swap_condition (comparison); | |
362cc3d4 | 4055 | } |
0ca40216 | 4056 | |
45475a3f PB |
4057 | /* If OP0 is still a constant, then both X and Y must be constants |
4058 | or the opposite comparison is not supported. Force X into a register | |
4059 | to create canonical RTL. */ | |
0ca40216 JL |
4060 | if (CONSTANT_P (op0)) |
4061 | op0 = force_reg (mode, op0); | |
0ca40216 | 4062 | |
c5d5d461 JL |
4063 | if (unsignedp) |
4064 | comparison = unsigned_condition (comparison); | |
a06ef755 | 4065 | |
f90b7a5a PB |
4066 | prepare_cmp_insn (op0, op1, comparison, size, unsignedp, OPTAB_LIB_WIDEN, |
4067 | &test, &mode); | |
4068 | emit_cmp_and_jump_insn_1 (test, mode, label); | |
b30f05db BS |
4069 | } |
4070 | ||
77c9c6c2 RK |
4071 | \f |
4072 | /* Emit a library call comparison between floating point X and Y. | |
4073 | COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.). */ | |
4074 | ||
c5c60e15 | 4075 | static void |
f90b7a5a PB |
4076 | prepare_float_lib_cmp (rtx x, rtx y, enum rtx_code comparison, |
4077 | rtx *ptest, enum machine_mode *pmode) | |
77c9c6c2 | 4078 | { |
c9034561 | 4079 | enum rtx_code swapped = swap_condition (comparison); |
b3f8d95d | 4080 | enum rtx_code reversed = reverse_condition_maybe_unordered (comparison); |
c9034561 | 4081 | enum machine_mode orig_mode = GET_MODE (x); |
7fecf2c7 | 4082 | enum machine_mode mode, cmp_mode; |
6597fd0b | 4083 | rtx true_rtx, false_rtx; |
37bf20ee | 4084 | rtx value, target, insns, equiv; |
0a300065 | 4085 | rtx libfunc = 0; |
b3f8d95d | 4086 | bool reversed_p = false; |
7fecf2c7 | 4087 | cmp_mode = targetm.libgcc_cmp_return_mode (); |
77c9c6c2 | 4088 | |
86556d87 BE |
4089 | for (mode = orig_mode; |
4090 | mode != VOIDmode; | |
4091 | mode = GET_MODE_WIDER_MODE (mode)) | |
77c9c6c2 | 4092 | { |
1bd74ad9 SL |
4093 | if (code_to_optab[comparison] |
4094 | && (libfunc = optab_libfunc (code_to_optab[comparison], mode))) | |
c9034561 | 4095 | break; |
77c9c6c2 | 4096 | |
1bd74ad9 SL |
4097 | if (code_to_optab[swapped] |
4098 | && (libfunc = optab_libfunc (code_to_optab[swapped], mode))) | |
77c9c6c2 | 4099 | { |
c9034561 ZW |
4100 | rtx tmp; |
4101 | tmp = x; x = y; y = tmp; | |
4102 | comparison = swapped; | |
4103 | break; | |
77c9c6c2 | 4104 | } |
77c9c6c2 | 4105 | |
1bd74ad9 | 4106 | if (code_to_optab[reversed] |
6597fd0b | 4107 | && (libfunc = optab_libfunc (code_to_optab[reversed], mode))) |
b3f8d95d MM |
4108 | { |
4109 | comparison = reversed; | |
4110 | reversed_p = true; | |
4111 | break; | |
4112 | } | |
4113 | } | |
5906d013 | 4114 | |
e3feb571 | 4115 | gcc_assert (mode != VOIDmode); |
0a300065 | 4116 | |
c9034561 ZW |
4117 | if (mode != orig_mode) |
4118 | { | |
4119 | x = convert_to_mode (mode, x, 0); | |
4120 | y = convert_to_mode (mode, y, 0); | |
4121 | } | |
4122 | ||
17796a89 RS |
4123 | /* Attach a REG_EQUAL note describing the semantics of the libcall to |
4124 | the RTL. The allows the RTL optimizers to delete the libcall if the | |
4125 | condition can be determined at compile-time. */ | |
6597fd0b PB |
4126 | if (comparison == UNORDERED |
4127 | || FLOAT_LIB_COMPARE_RETURNS_BOOL (mode, comparison)) | |
4128 | { | |
4129 | true_rtx = const_true_rtx; | |
4130 | false_rtx = const0_rtx; | |
4131 | } | |
4132 | else | |
4133 | { | |
4134 | switch (comparison) | |
4135 | { | |
4136 | case EQ: | |
4137 | true_rtx = const0_rtx; | |
4138 | false_rtx = const_true_rtx; | |
4139 | break; | |
4140 | ||
4141 | case NE: | |
4142 | true_rtx = const_true_rtx; | |
4143 | false_rtx = const0_rtx; | |
4144 | break; | |
4145 | ||
4146 | case GT: | |
4147 | true_rtx = const1_rtx; | |
4148 | false_rtx = const0_rtx; | |
4149 | break; | |
4150 | ||
4151 | case GE: | |
4152 | true_rtx = const0_rtx; | |
4153 | false_rtx = constm1_rtx; | |
4154 | break; | |
4155 | ||
4156 | case LT: | |
4157 | true_rtx = constm1_rtx; | |
4158 | false_rtx = const0_rtx; | |
4159 | break; | |
4160 | ||
4161 | case LE: | |
4162 | true_rtx = const0_rtx; | |
4163 | false_rtx = const1_rtx; | |
4164 | break; | |
4165 | ||
4166 | default: | |
4167 | gcc_unreachable (); | |
4168 | } | |
4169 | } | |
4170 | ||
17796a89 RS |
4171 | if (comparison == UNORDERED) |
4172 | { | |
7fecf2c7 AP |
4173 | rtx temp = simplify_gen_relational (NE, cmp_mode, mode, x, x); |
4174 | equiv = simplify_gen_relational (NE, cmp_mode, mode, y, y); | |
4175 | equiv = simplify_gen_ternary (IF_THEN_ELSE, cmp_mode, cmp_mode, | |
17796a89 RS |
4176 | temp, const_true_rtx, equiv); |
4177 | } | |
4178 | else | |
4179 | { | |
7fecf2c7 | 4180 | equiv = simplify_gen_relational (comparison, cmp_mode, mode, x, y); |
17796a89 | 4181 | if (! FLOAT_LIB_COMPARE_RETURNS_BOOL (mode, comparison)) |
6597fd0b PB |
4182 | equiv = simplify_gen_ternary (IF_THEN_ELSE, cmp_mode, cmp_mode, |
4183 | equiv, true_rtx, false_rtx); | |
bd831d5c | 4184 | } |
37bf20ee RS |
4185 | |
4186 | start_sequence (); | |
4187 | value = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST, | |
7fecf2c7 | 4188 | cmp_mode, 2, x, mode, y, mode); |
37bf20ee RS |
4189 | insns = get_insns (); |
4190 | end_sequence (); | |
4191 | ||
7fecf2c7 | 4192 | target = gen_reg_rtx (cmp_mode); |
37bf20ee RS |
4193 | emit_libcall_block (insns, target, value, equiv); |
4194 | ||
c9034561 | 4195 | if (comparison == UNORDERED |
6597fd0b PB |
4196 | || FLOAT_LIB_COMPARE_RETURNS_BOOL (mode, comparison) |
4197 | || reversed_p) | |
4198 | *ptest = gen_rtx_fmt_ee (reversed_p ? EQ : NE, VOIDmode, target, false_rtx); | |
4199 | else | |
4200 | *ptest = gen_rtx_fmt_ee (comparison, VOIDmode, target, const0_rtx); | |
c9034561 | 4201 | |
7fecf2c7 | 4202 | *pmode = cmp_mode; |
77c9c6c2 RK |
4203 | } |
4204 | \f | |
4205 | /* Generate code to indirectly jump to a location given in the rtx LOC. */ | |
4206 | ||
4207 | void | |
0c20a65f | 4208 | emit_indirect_jump (rtx loc) |
77c9c6c2 | 4209 | { |
a5c7d693 | 4210 | struct expand_operand ops[1]; |
77c9c6c2 | 4211 | |
a5c7d693 RS |
4212 | create_address_operand (&ops[0], loc); |
4213 | expand_jump_insn (CODE_FOR_indirect_jump, 1, ops); | |
9649fb4d | 4214 | emit_barrier (); |
77c9c6c2 RK |
4215 | } |
4216 | \f | |
49c4584c DE |
4217 | #ifdef HAVE_conditional_move |
4218 | ||
4219 | /* Emit a conditional move instruction if the machine supports one for that | |
4220 | condition and machine mode. | |
4221 | ||
4222 | OP0 and OP1 are the operands that should be compared using CODE. CMODE is | |
4223 | the mode to use should they be constants. If it is VOIDmode, they cannot | |
4224 | both be constants. | |
4225 | ||
4226 | OP2 should be stored in TARGET if the comparison is true, otherwise OP3 | |
4227 | should be stored there. MODE is the mode to use should they be constants. | |
4228 | If it is VOIDmode, they cannot both be constants. | |
4229 | ||
4230 | The result is either TARGET (perhaps modified) or NULL_RTX if the operation | |
4231 | is not supported. */ | |
4232 | ||
4233 | rtx | |
0c20a65f AJ |
4234 | emit_conditional_move (rtx target, enum rtx_code code, rtx op0, rtx op1, |
4235 | enum machine_mode cmode, rtx op2, rtx op3, | |
4236 | enum machine_mode mode, int unsignedp) | |
49c4584c | 4237 | { |
a5c7d693 | 4238 | rtx tem, comparison, last; |
49c4584c | 4239 | enum insn_code icode; |
e5c56fd9 | 4240 | enum rtx_code reversed; |
49c4584c DE |
4241 | |
4242 | /* If one operand is constant, make it the second one. Only do this | |
4243 | if the other operand is not constant as well. */ | |
4244 | ||
e5c56fd9 | 4245 | if (swap_commutative_operands_p (op0, op1)) |
49c4584c DE |
4246 | { |
4247 | tem = op0; | |
4248 | op0 = op1; | |
4249 | op1 = tem; | |
4250 | code = swap_condition (code); | |
4251 | } | |
4252 | ||
c5c76735 JL |
4253 | /* get_condition will prefer to generate LT and GT even if the old |
4254 | comparison was against zero, so undo that canonicalization here since | |
4255 | comparisons against zero are cheaper. */ | |
87d9741e | 4256 | if (code == LT && op1 == const1_rtx) |
c5c76735 | 4257 | code = LE, op1 = const0_rtx; |
87d9741e | 4258 | else if (code == GT && op1 == constm1_rtx) |
c5c76735 JL |
4259 | code = GE, op1 = const0_rtx; |
4260 | ||
49c4584c DE |
4261 | if (cmode == VOIDmode) |
4262 | cmode = GET_MODE (op0); | |
4263 | ||
e5c56fd9 JH |
4264 | if (swap_commutative_operands_p (op2, op3) |
4265 | && ((reversed = reversed_comparison_code_parts (code, op0, op1, NULL)) | |
4266 | != UNKNOWN)) | |
49c4584c DE |
4267 | { |
4268 | tem = op2; | |
4269 | op2 = op3; | |
4270 | op3 = tem; | |
e5c56fd9 | 4271 | code = reversed; |
49c4584c DE |
4272 | } |
4273 | ||
4274 | if (mode == VOIDmode) | |
4275 | mode = GET_MODE (op2); | |
4276 | ||
f9621cc4 | 4277 | icode = direct_optab_handler (movcc_optab, mode); |
49c4584c DE |
4278 | |
4279 | if (icode == CODE_FOR_nothing) | |
4280 | return 0; | |
4281 | ||
ad76cef8 | 4282 | if (!target) |
49c4584c DE |
4283 | target = gen_reg_rtx (mode); |
4284 | ||
f90b7a5a PB |
4285 | code = unsignedp ? unsigned_condition (code) : code; |
4286 | comparison = simplify_gen_relational (code, VOIDmode, cmode, op0, op1); | |
49c4584c | 4287 | |
144a5f9d JL |
4288 | /* We can get const0_rtx or const_true_rtx in some circumstances. Just |
4289 | return NULL and let the caller figure out how best to deal with this | |
4290 | situation. */ | |
f90b7a5a | 4291 | if (!COMPARISON_P (comparison)) |
144a5f9d | 4292 | return NULL_RTX; |
0c20a65f | 4293 | |
f90b7a5a | 4294 | do_pending_stack_adjust (); |
a5c7d693 | 4295 | last = get_last_insn (); |
f90b7a5a PB |
4296 | prepare_cmp_insn (XEXP (comparison, 0), XEXP (comparison, 1), |
4297 | GET_CODE (comparison), NULL_RTX, unsignedp, OPTAB_WIDEN, | |
4298 | &comparison, &cmode); | |
a5c7d693 | 4299 | if (comparison) |
f90b7a5a | 4300 | { |
a5c7d693 | 4301 | struct expand_operand ops[4]; |
49c4584c | 4302 | |
a5c7d693 RS |
4303 | create_output_operand (&ops[0], target, mode); |
4304 | create_fixed_operand (&ops[1], comparison); | |
4305 | create_input_operand (&ops[2], op2, mode); | |
4306 | create_input_operand (&ops[3], op3, mode); | |
4307 | if (maybe_expand_insn (icode, 4, ops)) | |
4308 | { | |
4309 | if (ops[0].value != target) | |
4310 | convert_move (target, ops[0].value, false); | |
4311 | return target; | |
4312 | } | |
4313 | } | |
4314 | delete_insns_since (last); | |
4315 | return NULL_RTX; | |
49c4584c DE |
4316 | } |
4317 | ||
40f03658 | 4318 | /* Return nonzero if a conditional move of mode MODE is supported. |
49c4584c DE |
4319 | |
4320 | This function is for combine so it can tell whether an insn that looks | |
4321 | like a conditional move is actually supported by the hardware. If we | |
4322 | guess wrong we lose a bit on optimization, but that's it. */ | |
4323 | /* ??? sparc64 supports conditionally moving integers values based on fp | |
4324 | comparisons, and vice versa. How do we handle them? */ | |
4325 | ||
4326 | int | |
0c20a65f | 4327 | can_conditionally_move_p (enum machine_mode mode) |
49c4584c | 4328 | { |
f9621cc4 | 4329 | if (direct_optab_handler (movcc_optab, mode) != CODE_FOR_nothing) |
49c4584c DE |
4330 | return 1; |
4331 | ||
4332 | return 0; | |
4333 | } | |
4334 | ||
4335 | #endif /* HAVE_conditional_move */ | |
068f5dea JH |
4336 | |
4337 | /* Emit a conditional addition instruction if the machine supports one for that | |
4338 | condition and machine mode. | |
4339 | ||
4340 | OP0 and OP1 are the operands that should be compared using CODE. CMODE is | |
4341 | the mode to use should they be constants. If it is VOIDmode, they cannot | |
4342 | both be constants. | |
4343 | ||
4344 | OP2 should be stored in TARGET if the comparison is true, otherwise OP2+OP3 | |
4345 | should be stored there. MODE is the mode to use should they be constants. | |
4346 | If it is VOIDmode, they cannot both be constants. | |
4347 | ||
4348 | The result is either TARGET (perhaps modified) or NULL_RTX if the operation | |
4349 | is not supported. */ | |
4350 | ||
4351 | rtx | |
0c20a65f AJ |
4352 | emit_conditional_add (rtx target, enum rtx_code code, rtx op0, rtx op1, |
4353 | enum machine_mode cmode, rtx op2, rtx op3, | |
4354 | enum machine_mode mode, int unsignedp) | |
068f5dea | 4355 | { |
a5c7d693 | 4356 | rtx tem, comparison, last; |
068f5dea JH |
4357 | enum insn_code icode; |
4358 | enum rtx_code reversed; | |
4359 | ||
4360 | /* If one operand is constant, make it the second one. Only do this | |
4361 | if the other operand is not constant as well. */ | |
4362 | ||
4363 | if (swap_commutative_operands_p (op0, op1)) | |
4364 | { | |
4365 | tem = op0; | |
4366 | op0 = op1; | |
4367 | op1 = tem; | |
4368 | code = swap_condition (code); | |
4369 | } | |
4370 | ||
4371 | /* get_condition will prefer to generate LT and GT even if the old | |
4372 | comparison was against zero, so undo that canonicalization here since | |
4373 | comparisons against zero are cheaper. */ | |
87d9741e | 4374 | if (code == LT && op1 == const1_rtx) |
068f5dea | 4375 | code = LE, op1 = const0_rtx; |
87d9741e | 4376 | else if (code == GT && op1 == constm1_rtx) |
068f5dea JH |
4377 | code = GE, op1 = const0_rtx; |
4378 | ||
4379 | if (cmode == VOIDmode) | |
4380 | cmode = GET_MODE (op0); | |
4381 | ||
4382 | if (swap_commutative_operands_p (op2, op3) | |
4383 | && ((reversed = reversed_comparison_code_parts (code, op0, op1, NULL)) | |
4384 | != UNKNOWN)) | |
4385 | { | |
4386 | tem = op2; | |
4387 | op2 = op3; | |
4388 | op3 = tem; | |
4389 | code = reversed; | |
4390 | } | |
4391 | ||
4392 | if (mode == VOIDmode) | |
4393 | mode = GET_MODE (op2); | |
4394 | ||
947131ba | 4395 | icode = optab_handler (addcc_optab, mode); |
068f5dea JH |
4396 | |
4397 | if (icode == CODE_FOR_nothing) | |
4398 | return 0; | |
4399 | ||
ad76cef8 | 4400 | if (!target) |
068f5dea JH |
4401 | target = gen_reg_rtx (mode); |
4402 | ||
f90b7a5a PB |
4403 | code = unsignedp ? unsigned_condition (code) : code; |
4404 | comparison = simplify_gen_relational (code, VOIDmode, cmode, op0, op1); | |
068f5dea | 4405 | |
068f5dea JH |
4406 | /* We can get const0_rtx or const_true_rtx in some circumstances. Just |
4407 | return NULL and let the caller figure out how best to deal with this | |
4408 | situation. */ | |
f90b7a5a | 4409 | if (!COMPARISON_P (comparison)) |
068f5dea | 4410 | return NULL_RTX; |
0c20a65f | 4411 | |
f90b7a5a | 4412 | do_pending_stack_adjust (); |
a5c7d693 | 4413 | last = get_last_insn (); |
f90b7a5a PB |
4414 | prepare_cmp_insn (XEXP (comparison, 0), XEXP (comparison, 1), |
4415 | GET_CODE (comparison), NULL_RTX, unsignedp, OPTAB_WIDEN, | |
4416 | &comparison, &cmode); | |
a5c7d693 | 4417 | if (comparison) |
f90b7a5a | 4418 | { |
a5c7d693 | 4419 | struct expand_operand ops[4]; |
068f5dea | 4420 | |
a5c7d693 RS |
4421 | create_output_operand (&ops[0], target, mode); |
4422 | create_fixed_operand (&ops[1], comparison); | |
4423 | create_input_operand (&ops[2], op2, mode); | |
4424 | create_input_operand (&ops[3], op3, mode); | |
4425 | if (maybe_expand_insn (icode, 4, ops)) | |
4426 | { | |
4427 | if (ops[0].value != target) | |
4428 | convert_move (target, ops[0].value, false); | |
4429 | return target; | |
4430 | } | |
4431 | } | |
4432 | delete_insns_since (last); | |
4433 | return NULL_RTX; | |
068f5dea | 4434 | } |
49c4584c | 4435 | \f |
0913e4b4 AO |
4436 | /* These functions attempt to generate an insn body, rather than |
4437 | emitting the insn, but if the gen function already emits them, we | |
ad76cef8 | 4438 | make no attempt to turn them back into naked patterns. */ |
77c9c6c2 RK |
4439 | |
4440 | /* Generate and return an insn body to add Y to X. */ | |
4441 | ||
4442 | rtx | |
0c20a65f | 4443 | gen_add2_insn (rtx x, rtx y) |
77c9c6c2 | 4444 | { |
2ef6ce06 | 4445 | enum insn_code icode = optab_handler (add_optab, GET_MODE (x)); |
77c9c6c2 | 4446 | |
2ef6ce06 RS |
4447 | gcc_assert (insn_operand_matches (icode, 0, x)); |
4448 | gcc_assert (insn_operand_matches (icode, 1, x)); | |
4449 | gcc_assert (insn_operand_matches (icode, 2, y)); | |
77c9c6c2 | 4450 | |
e3feb571 | 4451 | return GEN_FCN (icode) (x, x, y); |
77c9c6c2 RK |
4452 | } |
4453 | ||
e78d8e51 ZW |
4454 | /* Generate and return an insn body to add r1 and c, |
4455 | storing the result in r0. */ | |
8a33f100 | 4456 | |
e78d8e51 | 4457 | rtx |
0c20a65f | 4458 | gen_add3_insn (rtx r0, rtx r1, rtx c) |
e78d8e51 | 4459 | { |
2ef6ce06 | 4460 | enum insn_code icode = optab_handler (add_optab, GET_MODE (r0)); |
e78d8e51 | 4461 | |
7e1a450d | 4462 | if (icode == CODE_FOR_nothing |
2ef6ce06 RS |
4463 | || !insn_operand_matches (icode, 0, r0) |
4464 | || !insn_operand_matches (icode, 1, r1) | |
4465 | || !insn_operand_matches (icode, 2, c)) | |
e78d8e51 ZW |
4466 | return NULL_RTX; |
4467 | ||
e3feb571 | 4468 | return GEN_FCN (icode) (r0, r1, c); |
e78d8e51 ZW |
4469 | } |
4470 | ||
77c9c6c2 | 4471 | int |
0c20a65f | 4472 | have_add2_insn (rtx x, rtx y) |
77c9c6c2 | 4473 | { |
2ef6ce06 | 4474 | enum insn_code icode; |
fb7e77d7 | 4475 | |
e3feb571 | 4476 | gcc_assert (GET_MODE (x) != VOIDmode); |
fb7e77d7 | 4477 | |
2ef6ce06 | 4478 | icode = optab_handler (add_optab, GET_MODE (x)); |
fb7e77d7 TM |
4479 | |
4480 | if (icode == CODE_FOR_nothing) | |
4481 | return 0; | |
4482 | ||
2ef6ce06 RS |
4483 | if (!insn_operand_matches (icode, 0, x) |
4484 | || !insn_operand_matches (icode, 1, x) | |
4485 | || !insn_operand_matches (icode, 2, y)) | |
fb7e77d7 TM |
4486 | return 0; |
4487 | ||
4488 | return 1; | |
77c9c6c2 RK |
4489 | } |
4490 | ||
4491 | /* Generate and return an insn body to subtract Y from X. */ | |
4492 | ||
4493 | rtx | |
0c20a65f | 4494 | gen_sub2_insn (rtx x, rtx y) |
77c9c6c2 | 4495 | { |
2ef6ce06 | 4496 | enum insn_code icode = optab_handler (sub_optab, GET_MODE (x)); |
77c9c6c2 | 4497 | |
2ef6ce06 RS |
4498 | gcc_assert (insn_operand_matches (icode, 0, x)); |
4499 | gcc_assert (insn_operand_matches (icode, 1, x)); | |
4500 | gcc_assert (insn_operand_matches (icode, 2, y)); | |
77c9c6c2 | 4501 | |
e3feb571 | 4502 | return GEN_FCN (icode) (x, x, y); |
77c9c6c2 RK |
4503 | } |
4504 | ||
ef89d648 ZW |
4505 | /* Generate and return an insn body to subtract r1 and c, |
4506 | storing the result in r0. */ | |
8a33f100 | 4507 | |
ef89d648 | 4508 | rtx |
0c20a65f | 4509 | gen_sub3_insn (rtx r0, rtx r1, rtx c) |
ef89d648 | 4510 | { |
2ef6ce06 | 4511 | enum insn_code icode = optab_handler (sub_optab, GET_MODE (r0)); |
ef89d648 | 4512 | |
7e1a450d | 4513 | if (icode == CODE_FOR_nothing |
2ef6ce06 RS |
4514 | || !insn_operand_matches (icode, 0, r0) |
4515 | || !insn_operand_matches (icode, 1, r1) | |
4516 | || !insn_operand_matches (icode, 2, c)) | |
ef89d648 ZW |
4517 | return NULL_RTX; |
4518 | ||
e3feb571 | 4519 | return GEN_FCN (icode) (r0, r1, c); |
ef89d648 ZW |
4520 | } |
4521 | ||
77c9c6c2 | 4522 | int |
0c20a65f | 4523 | have_sub2_insn (rtx x, rtx y) |
77c9c6c2 | 4524 | { |
2ef6ce06 | 4525 | enum insn_code icode; |
fb7e77d7 | 4526 | |
e3feb571 | 4527 | gcc_assert (GET_MODE (x) != VOIDmode); |
fb7e77d7 | 4528 | |
2ef6ce06 | 4529 | icode = optab_handler (sub_optab, GET_MODE (x)); |
fb7e77d7 TM |
4530 | |
4531 | if (icode == CODE_FOR_nothing) | |
4532 | return 0; | |
4533 | ||
2ef6ce06 RS |
4534 | if (!insn_operand_matches (icode, 0, x) |
4535 | || !insn_operand_matches (icode, 1, x) | |
4536 | || !insn_operand_matches (icode, 2, y)) | |
fb7e77d7 TM |
4537 | return 0; |
4538 | ||
4539 | return 1; | |
77c9c6c2 RK |
4540 | } |
4541 | ||
e3654226 | 4542 | /* Generate the body of an instruction to copy Y into X. |
2f937369 | 4543 | It may be a list of insns, if one insn isn't enough. */ |
77c9c6c2 RK |
4544 | |
4545 | rtx | |
0c20a65f | 4546 | gen_move_insn (rtx x, rtx y) |
77c9c6c2 | 4547 | { |
e3654226 | 4548 | rtx seq; |
77c9c6c2 | 4549 | |
e3654226 RS |
4550 | start_sequence (); |
4551 | emit_move_insn_1 (x, y); | |
2f937369 | 4552 | seq = get_insns (); |
e3654226 RS |
4553 | end_sequence (); |
4554 | return seq; | |
77c9c6c2 RK |
4555 | } |
4556 | \f | |
34e56753 RS |
4557 | /* Return the insn code used to extend FROM_MODE to TO_MODE. |
4558 | UNSIGNEDP specifies zero-extension instead of sign-extension. If | |
4559 | no such operation exists, CODE_FOR_nothing will be returned. */ | |
77c9c6c2 | 4560 | |
34e56753 | 4561 | enum insn_code |
0c20a65f AJ |
4562 | can_extend_p (enum machine_mode to_mode, enum machine_mode from_mode, |
4563 | int unsignedp) | |
77c9c6c2 | 4564 | { |
85363ca0 | 4565 | convert_optab tab; |
6dd12198 SE |
4566 | #ifdef HAVE_ptr_extend |
4567 | if (unsignedp < 0) | |
4568 | return CODE_FOR_ptr_extend; | |
6dd12198 | 4569 | #endif |
85363ca0 ZW |
4570 | |
4571 | tab = unsignedp ? zext_optab : sext_optab; | |
947131ba | 4572 | return convert_optab_handler (tab, to_mode, from_mode); |
77c9c6c2 RK |
4573 | } |
4574 | ||
4575 | /* Generate the body of an insn to extend Y (with mode MFROM) | |
4576 | into X (with mode MTO). Do zero-extension if UNSIGNEDP is nonzero. */ | |
4577 | ||
4578 | rtx | |
0c20a65f AJ |
4579 | gen_extend_insn (rtx x, rtx y, enum machine_mode mto, |
4580 | enum machine_mode mfrom, int unsignedp) | |
77c9c6c2 | 4581 | { |
85363ca0 ZW |
4582 | enum insn_code icode = can_extend_p (mto, mfrom, unsignedp); |
4583 | return GEN_FCN (icode) (x, y); | |
77c9c6c2 | 4584 | } |
77c9c6c2 RK |
4585 | \f |
4586 | /* can_fix_p and can_float_p say whether the target machine | |
4587 | can directly convert a given fixed point type to | |
4588 | a given floating point type, or vice versa. | |
4589 | The returned value is the CODE_FOR_... value to use, | |
5d81dc5b | 4590 | or CODE_FOR_nothing if these modes cannot be directly converted. |
77c9c6c2 | 4591 | |
5d81dc5b | 4592 | *TRUNCP_PTR is set to 1 if it is necessary to output |
77c9c6c2 RK |
4593 | an explicit FTRUNC insn before the fix insn; otherwise 0. */ |
4594 | ||
4595 | static enum insn_code | |
0c20a65f AJ |
4596 | can_fix_p (enum machine_mode fixmode, enum machine_mode fltmode, |
4597 | int unsignedp, int *truncp_ptr) | |
77c9c6c2 | 4598 | { |
85363ca0 ZW |
4599 | convert_optab tab; |
4600 | enum insn_code icode; | |
4601 | ||
4602 | tab = unsignedp ? ufixtrunc_optab : sfixtrunc_optab; | |
947131ba | 4603 | icode = convert_optab_handler (tab, fixmode, fltmode); |
85363ca0 ZW |
4604 | if (icode != CODE_FOR_nothing) |
4605 | { | |
4606 | *truncp_ptr = 0; | |
4607 | return icode; | |
4608 | } | |
77c9c6c2 | 4609 | |
0e1d7f32 AH |
4610 | /* FIXME: This requires a port to define both FIX and FTRUNC pattern |
4611 | for this to work. We need to rework the fix* and ftrunc* patterns | |
4612 | and documentation. */ | |
85363ca0 | 4613 | tab = unsignedp ? ufix_optab : sfix_optab; |
947131ba | 4614 | icode = convert_optab_handler (tab, fixmode, fltmode); |
85363ca0 | 4615 | if (icode != CODE_FOR_nothing |
947131ba | 4616 | && optab_handler (ftrunc_optab, fltmode) != CODE_FOR_nothing) |
77c9c6c2 RK |
4617 | { |
4618 | *truncp_ptr = 1; | |
85363ca0 | 4619 | return icode; |
77c9c6c2 | 4620 | } |
85363ca0 ZW |
4621 | |
4622 | *truncp_ptr = 0; | |
77c9c6c2 RK |
4623 | return CODE_FOR_nothing; |
4624 | } | |
4625 | ||
4626 | static enum insn_code | |
0c20a65f AJ |
4627 | can_float_p (enum machine_mode fltmode, enum machine_mode fixmode, |
4628 | int unsignedp) | |
77c9c6c2 | 4629 | { |
85363ca0 ZW |
4630 | convert_optab tab; |
4631 | ||
4632 | tab = unsignedp ? ufloat_optab : sfloat_optab; | |
947131ba | 4633 | return convert_optab_handler (tab, fltmode, fixmode); |
77c9c6c2 | 4634 | } |
77c9c6c2 RK |
4635 | \f |
4636 | /* Generate code to convert FROM to floating point | |
34e56753 | 4637 | and store in TO. FROM must be fixed point and not VOIDmode. |
77c9c6c2 RK |
4638 | UNSIGNEDP nonzero means regard FROM as unsigned. |
4639 | Normally this is done by correcting the final value | |
4640 | if it is negative. */ | |
4641 | ||
4642 | void | |
0c20a65f | 4643 | expand_float (rtx to, rtx from, int unsignedp) |
77c9c6c2 RK |
4644 | { |
4645 | enum insn_code icode; | |
b3694847 | 4646 | rtx target = to; |
77c9c6c2 | 4647 | enum machine_mode fmode, imode; |
d7735880 | 4648 | bool can_do_signed = false; |
77c9c6c2 | 4649 | |
34e56753 | 4650 | /* Crash now, because we won't be able to decide which mode to use. */ |
e3feb571 | 4651 | gcc_assert (GET_MODE (from) != VOIDmode); |
34e56753 | 4652 | |
77c9c6c2 RK |
4653 | /* Look for an insn to do the conversion. Do it in the specified |
4654 | modes if possible; otherwise convert either input, output or both to | |
4655 | wider mode. If the integer mode is wider than the mode of FROM, | |
4656 | we can do the conversion signed even if the input is unsigned. */ | |
4657 | ||
7bf0a593 AP |
4658 | for (fmode = GET_MODE (to); fmode != VOIDmode; |
4659 | fmode = GET_MODE_WIDER_MODE (fmode)) | |
4660 | for (imode = GET_MODE (from); imode != VOIDmode; | |
4661 | imode = GET_MODE_WIDER_MODE (imode)) | |
77c9c6c2 RK |
4662 | { |
4663 | int doing_unsigned = unsignedp; | |
4664 | ||
5ba02ca6 | 4665 | if (fmode != GET_MODE (to) |
69660a70 | 4666 | && significand_size (fmode) < GET_MODE_PRECISION (GET_MODE (from))) |
5ba02ca6 GK |
4667 | continue; |
4668 | ||
77c9c6c2 | 4669 | icode = can_float_p (fmode, imode, unsignedp); |
d7735880 JM |
4670 | if (icode == CODE_FOR_nothing && unsignedp) |
4671 | { | |
4672 | enum insn_code scode = can_float_p (fmode, imode, 0); | |
4673 | if (scode != CODE_FOR_nothing) | |
4674 | can_do_signed = true; | |
4675 | if (imode != GET_MODE (from)) | |
4676 | icode = scode, doing_unsigned = 0; | |
4677 | } | |
77c9c6c2 RK |
4678 | |
4679 | if (icode != CODE_FOR_nothing) | |
4680 | { | |
77c9c6c2 RK |
4681 | if (imode != GET_MODE (from)) |
4682 | from = convert_to_mode (imode, from, unsignedp); | |
77c9c6c2 RK |
4683 | |
4684 | if (fmode != GET_MODE (to)) | |
4685 | target = gen_reg_rtx (fmode); | |
4686 | ||
4687 | emit_unop_insn (icode, target, from, | |
4688 | doing_unsigned ? UNSIGNED_FLOAT : FLOAT); | |
4689 | ||
4690 | if (target != to) | |
4691 | convert_move (to, target, 0); | |
4692 | return; | |
4693 | } | |
7e1a450d | 4694 | } |
77c9c6c2 | 4695 | |
6ef9a246 | 4696 | /* Unsigned integer, and no way to convert directly. Convert as signed, |
cc8d36a1 UB |
4697 | then unconditionally adjust the result. */ |
4698 | if (unsignedp && can_do_signed) | |
77c9c6c2 RK |
4699 | { |
4700 | rtx label = gen_label_rtx (); | |
4701 | rtx temp; | |
4702 | REAL_VALUE_TYPE offset; | |
4703 | ||
c95c47f3 PE |
4704 | /* Look for a usable floating mode FMODE wider than the source and at |
4705 | least as wide as the target. Using FMODE will avoid rounding woes | |
4706 | with unsigned values greater than the signed maximum value. */ | |
70864443 | 4707 | |
c95c47f3 PE |
4708 | for (fmode = GET_MODE (to); fmode != VOIDmode; |
4709 | fmode = GET_MODE_WIDER_MODE (fmode)) | |
69660a70 | 4710 | if (GET_MODE_PRECISION (GET_MODE (from)) < GET_MODE_BITSIZE (fmode) |
c95c47f3 PE |
4711 | && can_float_p (fmode, GET_MODE (from), 0) != CODE_FOR_nothing) |
4712 | break; | |
a48fb61b | 4713 | |
c95c47f3 PE |
4714 | if (fmode == VOIDmode) |
4715 | { | |
a48fb61b | 4716 | /* There is no such mode. Pretend the target is wide enough. */ |
c95c47f3 | 4717 | fmode = GET_MODE (to); |
a48fb61b | 4718 | |
0f41302f | 4719 | /* Avoid double-rounding when TO is narrower than FROM. */ |
a48fb61b | 4720 | if ((significand_size (fmode) + 1) |
69660a70 | 4721 | < GET_MODE_PRECISION (GET_MODE (from))) |
a48fb61b RK |
4722 | { |
4723 | rtx temp1; | |
4724 | rtx neglabel = gen_label_rtx (); | |
4725 | ||
0c20a65f | 4726 | /* Don't use TARGET if it isn't a register, is a hard register, |
70864443 | 4727 | or is the wrong mode. */ |
f8cfc6aa | 4728 | if (!REG_P (target) |
70864443 RK |
4729 | || REGNO (target) < FIRST_PSEUDO_REGISTER |
4730 | || GET_MODE (target) != fmode) | |
44f51d4a RK |
4731 | target = gen_reg_rtx (fmode); |
4732 | ||
a48fb61b RK |
4733 | imode = GET_MODE (from); |
4734 | do_pending_stack_adjust (); | |
4735 | ||
4736 | /* Test whether the sign bit is set. */ | |
1c0290ea | 4737 | emit_cmp_and_jump_insns (from, const0_rtx, LT, NULL_RTX, imode, |
a06ef755 | 4738 | 0, neglabel); |
a48fb61b RK |
4739 | |
4740 | /* The sign bit is not set. Convert as signed. */ | |
4741 | expand_float (target, from, 0); | |
4742 | emit_jump_insn (gen_jump (label)); | |
2ad79487 | 4743 | emit_barrier (); |
a48fb61b RK |
4744 | |
4745 | /* The sign bit is set. | |
4746 | Convert to a usable (positive signed) value by shifting right | |
4747 | one bit, while remembering if a nonzero bit was shifted | |
4748 | out; i.e., compute (from & 1) | (from >> 1). */ | |
4749 | ||
4750 | emit_label (neglabel); | |
4751 | temp = expand_binop (imode, and_optab, from, const1_rtx, | |
70864443 | 4752 | NULL_RTX, 1, OPTAB_LIB_WIDEN); |
eb6c3df1 | 4753 | temp1 = expand_shift (RSHIFT_EXPR, imode, from, 1, NULL_RTX, 1); |
0c20a65f | 4754 | temp = expand_binop (imode, ior_optab, temp, temp1, temp, 1, |
70864443 | 4755 | OPTAB_LIB_WIDEN); |
a48fb61b RK |
4756 | expand_float (target, temp, 0); |
4757 | ||
4758 | /* Multiply by 2 to undo the shift above. */ | |
a93738eb | 4759 | temp = expand_binop (fmode, add_optab, target, target, |
7e1a450d | 4760 | target, 0, OPTAB_LIB_WIDEN); |
a93738eb RK |
4761 | if (temp != target) |
4762 | emit_move_insn (target, temp); | |
4763 | ||
a48fb61b RK |
4764 | do_pending_stack_adjust (); |
4765 | emit_label (label); | |
4766 | goto done; | |
4767 | } | |
c95c47f3 PE |
4768 | } |
4769 | ||
77c9c6c2 RK |
4770 | /* If we are about to do some arithmetic to correct for an |
4771 | unsigned operand, do it in a pseudo-register. */ | |
4772 | ||
c95c47f3 | 4773 | if (GET_MODE (to) != fmode |
f8cfc6aa | 4774 | || !REG_P (to) || REGNO (to) < FIRST_PSEUDO_REGISTER) |
c95c47f3 | 4775 | target = gen_reg_rtx (fmode); |
77c9c6c2 RK |
4776 | |
4777 | /* Convert as signed integer to floating. */ | |
4778 | expand_float (target, from, 0); | |
4779 | ||
4780 | /* If FROM is negative (and therefore TO is negative), | |
4781 | correct its value by 2**bitwidth. */ | |
4782 | ||
4783 | do_pending_stack_adjust (); | |
c5d5d461 | 4784 | emit_cmp_and_jump_insns (from, const0_rtx, GE, NULL_RTX, GET_MODE (from), |
a06ef755 | 4785 | 0, label); |
70864443 | 4786 | |
0c20a65f | 4787 | |
69660a70 | 4788 | real_2expN (&offset, GET_MODE_PRECISION (GET_MODE (from)), fmode); |
c95c47f3 | 4789 | temp = expand_binop (fmode, add_optab, target, |
30d88916 | 4790 | CONST_DOUBLE_FROM_REAL_VALUE (offset, fmode), |
77c9c6c2 RK |
4791 | target, 0, OPTAB_LIB_WIDEN); |
4792 | if (temp != target) | |
4793 | emit_move_insn (target, temp); | |
a48fb61b | 4794 | |
77c9c6c2 RK |
4795 | do_pending_stack_adjust (); |
4796 | emit_label (label); | |
70864443 | 4797 | goto done; |
77c9c6c2 | 4798 | } |
77c9c6c2 | 4799 | |
85363ca0 | 4800 | /* No hardware instruction available; call a library routine. */ |
77c9c6c2 | 4801 | { |
85363ca0 | 4802 | rtx libfunc; |
77c9c6c2 | 4803 | rtx insns; |
9a7f678c | 4804 | rtx value; |
85363ca0 | 4805 | convert_optab tab = unsignedp ? ufloat_optab : sfloat_optab; |
77c9c6c2 | 4806 | |
77c9c6c2 RK |
4807 | if (GET_MODE_SIZE (GET_MODE (from)) < GET_MODE_SIZE (SImode)) |
4808 | from = convert_to_mode (SImode, from, unsignedp); | |
77c9c6c2 | 4809 | |
8a33f100 | 4810 | libfunc = convert_optab_libfunc (tab, GET_MODE (to), GET_MODE (from)); |
e3feb571 | 4811 | gcc_assert (libfunc); |
77c9c6c2 RK |
4812 | |
4813 | start_sequence (); | |
4814 | ||
85363ca0 | 4815 | value = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST, |
ebb1b59a BS |
4816 | GET_MODE (to), 1, from, |
4817 | GET_MODE (from)); | |
77c9c6c2 RK |
4818 | insns = get_insns (); |
4819 | end_sequence (); | |
4820 | ||
9a7f678c | 4821 | emit_libcall_block (insns, target, value, |
d1163987 BW |
4822 | gen_rtx_fmt_e (unsignedp ? UNSIGNED_FLOAT : FLOAT, |
4823 | GET_MODE (to), from)); | |
77c9c6c2 RK |
4824 | } |
4825 | ||
a48fb61b RK |
4826 | done: |
4827 | ||
77c9c6c2 RK |
4828 | /* Copy result to requested destination |
4829 | if we have been computing in a temp location. */ | |
4830 | ||
4831 | if (target != to) | |
4832 | { | |
4833 | if (GET_MODE (target) == GET_MODE (to)) | |
4834 | emit_move_insn (to, target); | |
4835 | else | |
4836 | convert_move (to, target, 0); | |
4837 | } | |
4838 | } | |
4839 | \f | |
0e1d7f32 AH |
4840 | /* Generate code to convert FROM to fixed point and store in TO. FROM |
4841 | must be floating point. */ | |
77c9c6c2 RK |
4842 | |
4843 | void | |
0c20a65f | 4844 | expand_fix (rtx to, rtx from, int unsignedp) |
77c9c6c2 RK |
4845 | { |
4846 | enum insn_code icode; | |
b3694847 | 4847 | rtx target = to; |
77c9c6c2 RK |
4848 | enum machine_mode fmode, imode; |
4849 | int must_trunc = 0; | |
77c9c6c2 RK |
4850 | |
4851 | /* We first try to find a pair of modes, one real and one integer, at | |
4852 | least as wide as FROM and TO, respectively, in which we can open-code | |
4853 | this conversion. If the integer mode is wider than the mode of TO, | |
4854 | we can do the conversion either signed or unsigned. */ | |
4855 | ||
3987b9db JH |
4856 | for (fmode = GET_MODE (from); fmode != VOIDmode; |
4857 | fmode = GET_MODE_WIDER_MODE (fmode)) | |
4858 | for (imode = GET_MODE (to); imode != VOIDmode; | |
4859 | imode = GET_MODE_WIDER_MODE (imode)) | |
77c9c6c2 RK |
4860 | { |
4861 | int doing_unsigned = unsignedp; | |
4862 | ||
4863 | icode = can_fix_p (imode, fmode, unsignedp, &must_trunc); | |
4864 | if (icode == CODE_FOR_nothing && imode != GET_MODE (to) && unsignedp) | |
4865 | icode = can_fix_p (imode, fmode, 0, &must_trunc), doing_unsigned = 0; | |
4866 | ||
4867 | if (icode != CODE_FOR_nothing) | |
4868 | { | |
5e04ef8f | 4869 | rtx last = get_last_insn (); |
77c9c6c2 RK |
4870 | if (fmode != GET_MODE (from)) |
4871 | from = convert_to_mode (fmode, from, 0); | |
77c9c6c2 RK |
4872 | |
4873 | if (must_trunc) | |
0e1d7f32 AH |
4874 | { |
4875 | rtx temp = gen_reg_rtx (GET_MODE (from)); | |
4876 | from = expand_unop (GET_MODE (from), ftrunc_optab, from, | |
4877 | temp, 0); | |
4878 | } | |
77c9c6c2 RK |
4879 | |
4880 | if (imode != GET_MODE (to)) | |
4881 | target = gen_reg_rtx (imode); | |
4882 | ||
5e04ef8f JH |
4883 | if (maybe_emit_unop_insn (icode, target, from, |
4884 | doing_unsigned ? UNSIGNED_FIX : FIX)) | |
4885 | { | |
4886 | if (target != to) | |
4887 | convert_move (to, target, unsignedp); | |
4888 | return; | |
4889 | } | |
4890 | delete_insns_since (last); | |
77c9c6c2 RK |
4891 | } |
4892 | } | |
4893 | ||
77c9c6c2 RK |
4894 | /* For an unsigned conversion, there is one more way to do it. |
4895 | If we have a signed conversion, we generate code that compares | |
4896 | the real value to the largest representable positive number. If if | |
4897 | is smaller, the conversion is done normally. Otherwise, subtract | |
4898 | one plus the highest signed number, convert, and add it back. | |
4899 | ||
4900 | We only need to check all real modes, since we know we didn't find | |
0c20a65f | 4901 | anything with a wider integer mode. |
0d446150 JH |
4902 | |
4903 | This code used to extend FP value into mode wider than the destination. | |
6ef9a246 JJ |
4904 | This is needed for decimal float modes which cannot accurately |
4905 | represent one plus the highest signed number of the same size, but | |
4906 | not for binary modes. Consider, for instance conversion from SFmode | |
0d446150 JH |
4907 | into DImode. |
4908 | ||
6fc0bb99 | 4909 | The hot path through the code is dealing with inputs smaller than 2^63 |
0d446150 JH |
4910 | and doing just the conversion, so there is no bits to lose. |
4911 | ||
4912 | In the other path we know the value is positive in the range 2^63..2^64-1 | |
6ef9a246 | 4913 | inclusive. (as for other input overflow happens and result is undefined) |
e0bb17a8 | 4914 | So we know that the most important bit set in mantissa corresponds to |
0d446150 JH |
4915 | 2^63. The subtraction of 2^63 should not generate any rounding as it |
4916 | simply clears out that bit. The rest is trivial. */ | |
77c9c6c2 | 4917 | |
69660a70 | 4918 | if (unsignedp && GET_MODE_PRECISION (GET_MODE (to)) <= HOST_BITS_PER_WIDE_INT) |
77c9c6c2 RK |
4919 | for (fmode = GET_MODE (from); fmode != VOIDmode; |
4920 | fmode = GET_MODE_WIDER_MODE (fmode)) | |
6ef9a246 JJ |
4921 | if (CODE_FOR_nothing != can_fix_p (GET_MODE (to), fmode, 0, &must_trunc) |
4922 | && (!DECIMAL_FLOAT_MODE_P (fmode) | |
69660a70 | 4923 | || GET_MODE_BITSIZE (fmode) > GET_MODE_PRECISION (GET_MODE (to)))) |
77c9c6c2 | 4924 | { |
e9f7ae44 RS |
4925 | int bitsize; |
4926 | REAL_VALUE_TYPE offset; | |
4927 | rtx limit, lab1, lab2, insn; | |
4928 | ||
69660a70 | 4929 | bitsize = GET_MODE_PRECISION (GET_MODE (to)); |
6ef9a246 | 4930 | real_2expN (&offset, bitsize - 1, fmode); |
30d88916 | 4931 | limit = CONST_DOUBLE_FROM_REAL_VALUE (offset, fmode); |
e9f7ae44 RS |
4932 | lab1 = gen_label_rtx (); |
4933 | lab2 = gen_label_rtx (); | |
77c9c6c2 | 4934 | |
77c9c6c2 RK |
4935 | if (fmode != GET_MODE (from)) |
4936 | from = convert_to_mode (fmode, from, 0); | |
4937 | ||
4938 | /* See if we need to do the subtraction. */ | |
4939 | do_pending_stack_adjust (); | |
c5d5d461 | 4940 | emit_cmp_and_jump_insns (from, limit, GE, NULL_RTX, GET_MODE (from), |
a06ef755 | 4941 | 0, lab1); |
77c9c6c2 RK |
4942 | |
4943 | /* If not, do the signed "fix" and branch around fixup code. */ | |
4944 | expand_fix (to, from, 0); | |
4945 | emit_jump_insn (gen_jump (lab2)); | |
4946 | emit_barrier (); | |
4947 | ||
4948 | /* Otherwise, subtract 2**(N-1), convert to signed number, | |
4949 | then add 2**(N-1). Do the addition using XOR since this | |
4950 | will often generate better code. */ | |
4951 | emit_label (lab1); | |
4952 | target = expand_binop (GET_MODE (from), sub_optab, from, limit, | |
b1ec3c92 | 4953 | NULL_RTX, 0, OPTAB_LIB_WIDEN); |
77c9c6c2 RK |
4954 | expand_fix (to, target, 0); |
4955 | target = expand_binop (GET_MODE (to), xor_optab, to, | |
2496c7bd LB |
4956 | gen_int_mode |
4957 | ((HOST_WIDE_INT) 1 << (bitsize - 1), | |
4958 | GET_MODE (to)), | |
77c9c6c2 RK |
4959 | to, 1, OPTAB_LIB_WIDEN); |
4960 | ||
4961 | if (target != to) | |
4962 | emit_move_insn (to, target); | |
4963 | ||
4964 | emit_label (lab2); | |
4965 | ||
947131ba | 4966 | if (optab_handler (mov_optab, GET_MODE (to)) != CODE_FOR_nothing) |
02214a5c RK |
4967 | { |
4968 | /* Make a place for a REG_NOTE and add it. */ | |
4969 | insn = emit_move_insn (to, to); | |
5fa671cf AM |
4970 | set_unique_reg_note (insn, |
4971 | REG_EQUAL, | |
4972 | gen_rtx_fmt_e (UNSIGNED_FIX, | |
4973 | GET_MODE (to), | |
4974 | copy_rtx (from))); | |
02214a5c | 4975 | } |
c5c76735 | 4976 | |
77c9c6c2 RK |
4977 | return; |
4978 | } | |
77c9c6c2 RK |
4979 | |
4980 | /* We can't do it with an insn, so use a library call. But first ensure | |
4981 | that the mode of TO is at least as wide as SImode, since those are the | |
4982 | only library calls we know about. */ | |
4983 | ||
4984 | if (GET_MODE_SIZE (GET_MODE (to)) < GET_MODE_SIZE (SImode)) | |
4985 | { | |
4986 | target = gen_reg_rtx (SImode); | |
4987 | ||
4988 | expand_fix (target, from, unsignedp); | |
4989 | } | |
77c9c6c2 | 4990 | else |
77c9c6c2 RK |
4991 | { |
4992 | rtx insns; | |
560f3f8a | 4993 | rtx value; |
85363ca0 | 4994 | rtx libfunc; |
5906d013 | 4995 | |
85363ca0 | 4996 | convert_optab tab = unsignedp ? ufix_optab : sfix_optab; |
8a33f100 | 4997 | libfunc = convert_optab_libfunc (tab, GET_MODE (to), GET_MODE (from)); |
e3feb571 | 4998 | gcc_assert (libfunc); |
77c9c6c2 | 4999 | |
77c9c6c2 RK |
5000 | start_sequence (); |
5001 | ||
85363ca0 | 5002 | value = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST, |
ebb1b59a BS |
5003 | GET_MODE (to), 1, from, |
5004 | GET_MODE (from)); | |
77c9c6c2 RK |
5005 | insns = get_insns (); |
5006 | end_sequence (); | |
5007 | ||
560f3f8a | 5008 | emit_libcall_block (insns, target, value, |
9e6a5703 JC |
5009 | gen_rtx_fmt_e (unsignedp ? UNSIGNED_FIX : FIX, |
5010 | GET_MODE (to), from)); | |
77c9c6c2 | 5011 | } |
0c20a65f | 5012 | |
3e53ea48 RK |
5013 | if (target != to) |
5014 | { | |
5015 | if (GET_MODE (to) == GET_MODE (target)) | |
5016 | emit_move_insn (to, target); | |
5017 | else | |
5018 | convert_move (to, target, 0); | |
5019 | } | |
77c9c6c2 | 5020 | } |
bb7f0423 | 5021 | |
0f996086 CF |
5022 | /* Generate code to convert FROM or TO a fixed-point. |
5023 | If UINTP is true, either TO or FROM is an unsigned integer. | |
5024 | If SATP is true, we need to saturate the result. */ | |
5025 | ||
5026 | void | |
5027 | expand_fixed_convert (rtx to, rtx from, int uintp, int satp) | |
5028 | { | |
5029 | enum machine_mode to_mode = GET_MODE (to); | |
5030 | enum machine_mode from_mode = GET_MODE (from); | |
5031 | convert_optab tab; | |
5032 | enum rtx_code this_code; | |
5033 | enum insn_code code; | |
5034 | rtx insns, value; | |
5035 | rtx libfunc; | |
5036 | ||
5037 | if (to_mode == from_mode) | |
5038 | { | |
5039 | emit_move_insn (to, from); | |
5040 | return; | |
5041 | } | |
5042 | ||
5043 | if (uintp) | |
5044 | { | |
5045 | tab = satp ? satfractuns_optab : fractuns_optab; | |
5046 | this_code = satp ? UNSIGNED_SAT_FRACT : UNSIGNED_FRACT_CONVERT; | |
5047 | } | |
5048 | else | |
5049 | { | |
5050 | tab = satp ? satfract_optab : fract_optab; | |
5051 | this_code = satp ? SAT_FRACT : FRACT_CONVERT; | |
5052 | } | |
947131ba | 5053 | code = convert_optab_handler (tab, to_mode, from_mode); |
0f996086 CF |
5054 | if (code != CODE_FOR_nothing) |
5055 | { | |
5056 | emit_unop_insn (code, to, from, this_code); | |
5057 | return; | |
5058 | } | |
5059 | ||
5060 | libfunc = convert_optab_libfunc (tab, to_mode, from_mode); | |
5061 | gcc_assert (libfunc); | |
5062 | ||
5063 | start_sequence (); | |
5064 | value = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST, to_mode, | |
5065 | 1, from, from_mode); | |
5066 | insns = get_insns (); | |
5067 | end_sequence (); | |
5068 | ||
5069 | emit_libcall_block (insns, to, value, | |
5070 | gen_rtx_fmt_e (tab->code, to_mode, from)); | |
5071 | } | |
5072 | ||
bb7f0423 RG |
5073 | /* Generate code to convert FROM to fixed point and store in TO. FROM |
5074 | must be floating point, TO must be signed. Use the conversion optab | |
5075 | TAB to do the conversion. */ | |
5076 | ||
5077 | bool | |
5078 | expand_sfix_optab (rtx to, rtx from, convert_optab tab) | |
5079 | { | |
5080 | enum insn_code icode; | |
5081 | rtx target = to; | |
5082 | enum machine_mode fmode, imode; | |
5083 | ||
5084 | /* We first try to find a pair of modes, one real and one integer, at | |
5085 | least as wide as FROM and TO, respectively, in which we can open-code | |
5086 | this conversion. If the integer mode is wider than the mode of TO, | |
5087 | we can do the conversion either signed or unsigned. */ | |
5088 | ||
5089 | for (fmode = GET_MODE (from); fmode != VOIDmode; | |
5090 | fmode = GET_MODE_WIDER_MODE (fmode)) | |
5091 | for (imode = GET_MODE (to); imode != VOIDmode; | |
5092 | imode = GET_MODE_WIDER_MODE (imode)) | |
5093 | { | |
947131ba | 5094 | icode = convert_optab_handler (tab, imode, fmode); |
bb7f0423 RG |
5095 | if (icode != CODE_FOR_nothing) |
5096 | { | |
5e04ef8f | 5097 | rtx last = get_last_insn (); |
bb7f0423 RG |
5098 | if (fmode != GET_MODE (from)) |
5099 | from = convert_to_mode (fmode, from, 0); | |
5100 | ||
5101 | if (imode != GET_MODE (to)) | |
5102 | target = gen_reg_rtx (imode); | |
5103 | ||
18bd082d | 5104 | if (!maybe_emit_unop_insn (icode, target, from, UNKNOWN)) |
5e04ef8f JH |
5105 | { |
5106 | delete_insns_since (last); | |
5107 | continue; | |
5108 | } | |
bb7f0423 RG |
5109 | if (target != to) |
5110 | convert_move (to, target, 0); | |
5111 | return true; | |
5112 | } | |
5113 | } | |
5114 | ||
5115 | return false; | |
5116 | } | |
77c9c6c2 | 5117 | \f |
ef89d648 ZW |
5118 | /* Report whether we have an instruction to perform the operation |
5119 | specified by CODE on operands of mode MODE. */ | |
5120 | int | |
0c20a65f | 5121 | have_insn_for (enum rtx_code code, enum machine_mode mode) |
ef89d648 ZW |
5122 | { |
5123 | return (code_to_optab[(int) code] != 0 | |
947131ba | 5124 | && (optab_handler (code_to_optab[(int) code], mode) |
ef89d648 ZW |
5125 | != CODE_FOR_nothing)); |
5126 | } | |
5127 | ||
c0742514 JJ |
5128 | /* Set all insn_code fields to CODE_FOR_nothing. */ |
5129 | ||
33727b5e | 5130 | static void |
c0742514 | 5131 | init_insn_codes (void) |
85363ca0 | 5132 | { |
596455ce RS |
5133 | memset (optab_table, 0, sizeof (optab_table)); |
5134 | memset (convert_optab_table, 0, sizeof (convert_optab_table)); | |
f9621cc4 | 5135 | memset (direct_optab_table, 0, sizeof (direct_optab_table)); |
85363ca0 ZW |
5136 | } |
5137 | ||
c0742514 | 5138 | /* Initialize OP's code to CODE, and write it into the code_to_optab table. */ |
33727b5e JJ |
5139 | static inline void |
5140 | init_optab (optab op, enum rtx_code code) | |
ef89d648 | 5141 | { |
ef89d648 ZW |
5142 | op->code = code; |
5143 | code_to_optab[(int) code] = op; | |
ef89d648 ZW |
5144 | } |
5145 | ||
5146 | /* Same, but fill in its code as CODE, and do _not_ write it into | |
5147 | the code_to_optab table. */ | |
33727b5e JJ |
5148 | static inline void |
5149 | init_optabv (optab op, enum rtx_code code) | |
ef89d648 | 5150 | { |
ef89d648 | 5151 | op->code = code; |
77c9c6c2 RK |
5152 | } |
5153 | ||
85363ca0 | 5154 | /* Conversion optabs never go in the code_to_optab table. */ |
33727b5e JJ |
5155 | static void |
5156 | init_convert_optab (convert_optab op, enum rtx_code code) | |
85363ca0 | 5157 | { |
85363ca0 | 5158 | op->code = code; |
85363ca0 ZW |
5159 | } |
5160 | ||
b092b471 JW |
5161 | /* Initialize the libfunc fields of an entire group of entries in some |
5162 | optab. Each entry is set equal to a string consisting of a leading | |
5163 | pair of underscores followed by a generic operation name followed by | |
7ef0daad | 5164 | a mode name (downshifted to lowercase) followed by a single character |
b092b471 JW |
5165 | representing the number of operands for the given operation (which is |
5166 | usually one of the characters '2', '3', or '4'). | |
5167 | ||
5168 | OPTABLE is the table in which libfunc fields are to be initialized. | |
b092b471 JW |
5169 | OPNAME is the generic (string) name of the operation. |
5170 | SUFFIX is the character which specifies the number of operands for | |
5171 | the given generic operation. | |
8a33f100 | 5172 | MODE is the mode to generate for. |
b092b471 JW |
5173 | */ |
5174 | ||
5175 | static void | |
8a33f100 | 5176 | gen_libfunc (optab optable, const char *opname, int suffix, enum machine_mode mode) |
b092b471 | 5177 | { |
b3694847 | 5178 | unsigned opname_len = strlen (opname); |
8a33f100 JH |
5179 | const char *mname = GET_MODE_NAME (mode); |
5180 | unsigned mname_len = strlen (mname); | |
cdbf4541 BS |
5181 | int prefix_len = targetm.libfunc_gnu_prefix ? 6 : 2; |
5182 | int len = prefix_len + opname_len + mname_len + 1 + 1; | |
5183 | char *libfunc_name = XALLOCAVEC (char, len); | |
8a33f100 JH |
5184 | char *p; |
5185 | const char *q; | |
b092b471 | 5186 | |
8a33f100 JH |
5187 | p = libfunc_name; |
5188 | *p++ = '_'; | |
5189 | *p++ = '_'; | |
cdbf4541 BS |
5190 | if (targetm.libfunc_gnu_prefix) |
5191 | { | |
5192 | *p++ = 'g'; | |
5193 | *p++ = 'n'; | |
5194 | *p++ = 'u'; | |
5195 | *p++ = '_'; | |
5196 | } | |
8a33f100 JH |
5197 | for (q = opname; *q; ) |
5198 | *p++ = *q++; | |
5199 | for (q = mname; *q; q++) | |
5200 | *p++ = TOLOWER (*q); | |
5201 | *p++ = suffix; | |
5202 | *p = '\0'; | |
5203 | ||
5204 | set_optab_libfunc (optable, mode, | |
5205 | ggc_alloc_string (libfunc_name, p - libfunc_name)); | |
b092b471 JW |
5206 | } |
5207 | ||
8a33f100 | 5208 | /* Like gen_libfunc, but verify that integer operation is involved. */ |
b092b471 JW |
5209 | |
5210 | static void | |
8a33f100 JH |
5211 | gen_int_libfunc (optab optable, const char *opname, char suffix, |
5212 | enum machine_mode mode) | |
b092b471 | 5213 | { |
8a33f100 JH |
5214 | int maxsize = 2 * BITS_PER_WORD; |
5215 | ||
5216 | if (GET_MODE_CLASS (mode) != MODE_INT) | |
5217 | return; | |
c0510d84 DD |
5218 | if (maxsize < LONG_LONG_TYPE_SIZE) |
5219 | maxsize = LONG_LONG_TYPE_SIZE; | |
8a33f100 JH |
5220 | if (GET_MODE_CLASS (mode) != MODE_INT |
5221 | || mode < word_mode || GET_MODE_BITSIZE (mode) > maxsize) | |
5222 | return; | |
5223 | gen_libfunc (optable, opname, suffix, mode); | |
b092b471 JW |
5224 | } |
5225 | ||
8a33f100 | 5226 | /* Like gen_libfunc, but verify that FP and set decimal prefix if needed. */ |
b092b471 JW |
5227 | |
5228 | static void | |
8a33f100 JH |
5229 | gen_fp_libfunc (optab optable, const char *opname, char suffix, |
5230 | enum machine_mode mode) | |
b092b471 | 5231 | { |
8a33f100 | 5232 | char *dec_opname; |
79b87c74 | 5233 | |
8a33f100 JH |
5234 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) |
5235 | gen_libfunc (optable, opname, suffix, mode); | |
5236 | if (DECIMAL_FLOAT_MODE_P (mode)) | |
5237 | { | |
d3bfe4de | 5238 | dec_opname = XALLOCAVEC (char, sizeof (DECIMAL_PREFIX) + strlen (opname)); |
8a33f100 JH |
5239 | /* For BID support, change the name to have either a bid_ or dpd_ prefix |
5240 | depending on the low level floating format used. */ | |
5241 | memcpy (dec_opname, DECIMAL_PREFIX, sizeof (DECIMAL_PREFIX) - 1); | |
5242 | strcpy (dec_opname + sizeof (DECIMAL_PREFIX) - 1, opname); | |
5243 | gen_libfunc (optable, dec_opname, suffix, mode); | |
5244 | } | |
5245 | } | |
79b87c74 | 5246 | |
0f996086 CF |
5247 | /* Like gen_libfunc, but verify that fixed-point operation is involved. */ |
5248 | ||
5249 | static void | |
5250 | gen_fixed_libfunc (optab optable, const char *opname, char suffix, | |
5251 | enum machine_mode mode) | |
5252 | { | |
5253 | if (!ALL_FIXED_POINT_MODE_P (mode)) | |
5254 | return; | |
5255 | gen_libfunc (optable, opname, suffix, mode); | |
5256 | } | |
5257 | ||
5258 | /* Like gen_libfunc, but verify that signed fixed-point operation is | |
5259 | involved. */ | |
5260 | ||
5261 | static void | |
5262 | gen_signed_fixed_libfunc (optab optable, const char *opname, char suffix, | |
5263 | enum machine_mode mode) | |
5264 | { | |
5265 | if (!SIGNED_FIXED_POINT_MODE_P (mode)) | |
5266 | return; | |
5267 | gen_libfunc (optable, opname, suffix, mode); | |
5268 | } | |
5269 | ||
5270 | /* Like gen_libfunc, but verify that unsigned fixed-point operation is | |
5271 | involved. */ | |
5272 | ||
5273 | static void | |
5274 | gen_unsigned_fixed_libfunc (optab optable, const char *opname, char suffix, | |
5275 | enum machine_mode mode) | |
5276 | { | |
5277 | if (!UNSIGNED_FIXED_POINT_MODE_P (mode)) | |
5278 | return; | |
5279 | gen_libfunc (optable, opname, suffix, mode); | |
5280 | } | |
5281 | ||
8a33f100 JH |
5282 | /* Like gen_libfunc, but verify that FP or INT operation is involved. */ |
5283 | ||
5284 | static void | |
5285 | gen_int_fp_libfunc (optab optable, const char *name, char suffix, | |
5286 | enum machine_mode mode) | |
5287 | { | |
5288 | if (DECIMAL_FLOAT_MODE_P (mode) || GET_MODE_CLASS (mode) == MODE_FLOAT) | |
5289 | gen_fp_libfunc (optable, name, suffix, mode); | |
5290 | if (INTEGRAL_MODE_P (mode)) | |
5291 | gen_int_libfunc (optable, name, suffix, mode); | |
5292 | } | |
5293 | ||
5294 | /* Like gen_libfunc, but verify that FP or INT operation is involved | |
5295 | and add 'v' suffix for integer operation. */ | |
5296 | ||
5297 | static void | |
5298 | gen_intv_fp_libfunc (optab optable, const char *name, char suffix, | |
5299 | enum machine_mode mode) | |
5300 | { | |
5301 | if (DECIMAL_FLOAT_MODE_P (mode) || GET_MODE_CLASS (mode) == MODE_FLOAT) | |
5302 | gen_fp_libfunc (optable, name, suffix, mode); | |
5303 | if (GET_MODE_CLASS (mode) == MODE_INT) | |
5304 | { | |
5305 | int len = strlen (name); | |
d3bfe4de | 5306 | char *v_name = XALLOCAVEC (char, len + 2); |
8a33f100 JH |
5307 | strcpy (v_name, name); |
5308 | v_name[len] = 'v'; | |
5309 | v_name[len + 1] = 0; | |
5310 | gen_int_libfunc (optable, v_name, suffix, mode); | |
5311 | } | |
b092b471 JW |
5312 | } |
5313 | ||
0f996086 CF |
5314 | /* Like gen_libfunc, but verify that FP or INT or FIXED operation is |
5315 | involved. */ | |
5316 | ||
5317 | static void | |
5318 | gen_int_fp_fixed_libfunc (optab optable, const char *name, char suffix, | |
5319 | enum machine_mode mode) | |
5320 | { | |
5321 | if (DECIMAL_FLOAT_MODE_P (mode) || GET_MODE_CLASS (mode) == MODE_FLOAT) | |
5322 | gen_fp_libfunc (optable, name, suffix, mode); | |
5323 | if (INTEGRAL_MODE_P (mode)) | |
5324 | gen_int_libfunc (optable, name, suffix, mode); | |
5325 | if (ALL_FIXED_POINT_MODE_P (mode)) | |
5326 | gen_fixed_libfunc (optable, name, suffix, mode); | |
5327 | } | |
5328 | ||
5329 | /* Like gen_libfunc, but verify that FP or INT or signed FIXED operation is | |
5330 | involved. */ | |
5331 | ||
5332 | static void | |
5333 | gen_int_fp_signed_fixed_libfunc (optab optable, const char *name, char suffix, | |
5334 | enum machine_mode mode) | |
5335 | { | |
5336 | if (DECIMAL_FLOAT_MODE_P (mode) || GET_MODE_CLASS (mode) == MODE_FLOAT) | |
5337 | gen_fp_libfunc (optable, name, suffix, mode); | |
5338 | if (INTEGRAL_MODE_P (mode)) | |
5339 | gen_int_libfunc (optable, name, suffix, mode); | |
5340 | if (SIGNED_FIXED_POINT_MODE_P (mode)) | |
5341 | gen_signed_fixed_libfunc (optable, name, suffix, mode); | |
5342 | } | |
5343 | ||
5344 | /* Like gen_libfunc, but verify that INT or FIXED operation is | |
5345 | involved. */ | |
5346 | ||
5347 | static void | |
5348 | gen_int_fixed_libfunc (optab optable, const char *name, char suffix, | |
5349 | enum machine_mode mode) | |
5350 | { | |
5351 | if (INTEGRAL_MODE_P (mode)) | |
5352 | gen_int_libfunc (optable, name, suffix, mode); | |
5353 | if (ALL_FIXED_POINT_MODE_P (mode)) | |
5354 | gen_fixed_libfunc (optable, name, suffix, mode); | |
5355 | } | |
5356 | ||
5357 | /* Like gen_libfunc, but verify that INT or signed FIXED operation is | |
5358 | involved. */ | |
5359 | ||
5360 | static void | |
5361 | gen_int_signed_fixed_libfunc (optab optable, const char *name, char suffix, | |
5362 | enum machine_mode mode) | |
5363 | { | |
5364 | if (INTEGRAL_MODE_P (mode)) | |
5365 | gen_int_libfunc (optable, name, suffix, mode); | |
5366 | if (SIGNED_FIXED_POINT_MODE_P (mode)) | |
5367 | gen_signed_fixed_libfunc (optable, name, suffix, mode); | |
5368 | } | |
5369 | ||
5370 | /* Like gen_libfunc, but verify that INT or unsigned FIXED operation is | |
5371 | involved. */ | |
5372 | ||
5373 | static void | |
5374 | gen_int_unsigned_fixed_libfunc (optab optable, const char *name, char suffix, | |
5375 | enum machine_mode mode) | |
5376 | { | |
5377 | if (INTEGRAL_MODE_P (mode)) | |
5378 | gen_int_libfunc (optable, name, suffix, mode); | |
5379 | if (UNSIGNED_FIXED_POINT_MODE_P (mode)) | |
5380 | gen_unsigned_fixed_libfunc (optable, name, suffix, mode); | |
5381 | } | |
5382 | ||
85363ca0 ZW |
5383 | /* Initialize the libfunc fields of an entire group of entries of an |
5384 | inter-mode-class conversion optab. The string formation rules are | |
5385 | similar to the ones for init_libfuncs, above, but instead of having | |
5386 | a mode name and an operand count these functions have two mode names | |
5387 | and no operand count. */ | |
8a33f100 | 5388 | |
85363ca0 | 5389 | static void |
8a33f100 JH |
5390 | gen_interclass_conv_libfunc (convert_optab tab, |
5391 | const char *opname, | |
5392 | enum machine_mode tmode, | |
5393 | enum machine_mode fmode) | |
85363ca0 | 5394 | { |
85363ca0 | 5395 | size_t opname_len = strlen (opname); |
8a33f100 | 5396 | size_t mname_len = 0; |
85363ca0 | 5397 | |
85363ca0 ZW |
5398 | const char *fname, *tname; |
5399 | const char *q; | |
cdbf4541 | 5400 | int prefix_len = targetm.libfunc_gnu_prefix ? 6 : 2; |
85363ca0 | 5401 | char *libfunc_name, *suffix; |
79b87c74 | 5402 | char *nondec_name, *dec_name, *nondec_suffix, *dec_suffix; |
85363ca0 ZW |
5403 | char *p; |
5404 | ||
79b87c74 MM |
5405 | /* If this is a decimal conversion, add the current BID vs. DPD prefix that |
5406 | depends on which underlying decimal floating point format is used. */ | |
5407 | const size_t dec_len = sizeof (DECIMAL_PREFIX) - 1; | |
5408 | ||
8a33f100 | 5409 | mname_len = strlen (GET_MODE_NAME (tmode)) + strlen (GET_MODE_NAME (fmode)); |
85363ca0 | 5410 | |
cdbf4541 | 5411 | nondec_name = XALLOCAVEC (char, prefix_len + opname_len + mname_len + 1 + 1); |
79b87c74 MM |
5412 | nondec_name[0] = '_'; |
5413 | nondec_name[1] = '_'; | |
cdbf4541 BS |
5414 | if (targetm.libfunc_gnu_prefix) |
5415 | { | |
5416 | nondec_name[2] = 'g'; | |
5417 | nondec_name[3] = 'n'; | |
5418 | nondec_name[4] = 'u'; | |
5419 | nondec_name[5] = '_'; | |
5420 | } | |
5421 | ||
5422 | memcpy (&nondec_name[prefix_len], opname, opname_len); | |
5423 | nondec_suffix = nondec_name + opname_len + prefix_len; | |
79b87c74 | 5424 | |
d3bfe4de | 5425 | dec_name = XALLOCAVEC (char, 2 + dec_len + opname_len + mname_len + 1 + 1); |
79b87c74 MM |
5426 | dec_name[0] = '_'; |
5427 | dec_name[1] = '_'; | |
5428 | memcpy (&dec_name[2], DECIMAL_PREFIX, dec_len); | |
5429 | memcpy (&dec_name[2+dec_len], opname, opname_len); | |
5430 | dec_suffix = dec_name + dec_len + opname_len + 2; | |
85363ca0 | 5431 | |
8a33f100 JH |
5432 | fname = GET_MODE_NAME (fmode); |
5433 | tname = GET_MODE_NAME (tmode); | |
85363ca0 | 5434 | |
8a33f100 JH |
5435 | if (DECIMAL_FLOAT_MODE_P(fmode) || DECIMAL_FLOAT_MODE_P(tmode)) |
5436 | { | |
5437 | libfunc_name = dec_name; | |
5438 | suffix = dec_suffix; | |
5439 | } | |
5440 | else | |
5441 | { | |
5442 | libfunc_name = nondec_name; | |
5443 | suffix = nondec_suffix; | |
5444 | } | |
79b87c74 | 5445 | |
8a33f100 JH |
5446 | p = suffix; |
5447 | for (q = fname; *q; p++, q++) | |
5448 | *p = TOLOWER (*q); | |
5449 | for (q = tname; *q; p++, q++) | |
5450 | *p = TOLOWER (*q); | |
85363ca0 | 5451 | |
8a33f100 | 5452 | *p = '\0'; |
85363ca0 | 5453 | |
8a33f100 JH |
5454 | set_conv_libfunc (tab, tmode, fmode, |
5455 | ggc_alloc_string (libfunc_name, p - libfunc_name)); | |
85363ca0 ZW |
5456 | } |
5457 | ||
8a33f100 JH |
5458 | /* Same as gen_interclass_conv_libfunc but verify that we are producing |
5459 | int->fp conversion. */ | |
5460 | ||
85363ca0 | 5461 | static void |
8a33f100 JH |
5462 | gen_int_to_fp_conv_libfunc (convert_optab tab, |
5463 | const char *opname, | |
5464 | enum machine_mode tmode, | |
5465 | enum machine_mode fmode) | |
5466 | { | |
5467 | if (GET_MODE_CLASS (fmode) != MODE_INT) | |
5468 | return; | |
5469 | if (GET_MODE_CLASS (tmode) != MODE_FLOAT && !DECIMAL_FLOAT_MODE_P (tmode)) | |
5470 | return; | |
5471 | gen_interclass_conv_libfunc (tab, opname, tmode, fmode); | |
5472 | } | |
5473 | ||
5474 | /* ufloat_optab is special by using floatun for FP and floatuns decimal fp | |
5475 | naming scheme. */ | |
5476 | ||
5477 | static void | |
5478 | gen_ufloat_conv_libfunc (convert_optab tab, | |
5479 | const char *opname ATTRIBUTE_UNUSED, | |
5480 | enum machine_mode tmode, | |
5481 | enum machine_mode fmode) | |
5482 | { | |
5483 | if (DECIMAL_FLOAT_MODE_P (tmode)) | |
5484 | gen_int_to_fp_conv_libfunc (tab, "floatuns", tmode, fmode); | |
5485 | else | |
5486 | gen_int_to_fp_conv_libfunc (tab, "floatun", tmode, fmode); | |
5487 | } | |
5488 | ||
5489 | /* Same as gen_interclass_conv_libfunc but verify that we are producing | |
5490 | fp->int conversion. */ | |
5491 | ||
5492 | static void | |
5493 | gen_int_to_fp_nondecimal_conv_libfunc (convert_optab tab, | |
5494 | const char *opname, | |
5495 | enum machine_mode tmode, | |
5496 | enum machine_mode fmode) | |
5497 | { | |
5498 | if (GET_MODE_CLASS (fmode) != MODE_INT) | |
5499 | return; | |
5500 | if (GET_MODE_CLASS (tmode) != MODE_FLOAT) | |
5501 | return; | |
5502 | gen_interclass_conv_libfunc (tab, opname, tmode, fmode); | |
5503 | } | |
5504 | ||
5505 | /* Same as gen_interclass_conv_libfunc but verify that we are producing | |
5506 | fp->int conversion with no decimal floating point involved. */ | |
5507 | ||
5508 | static void | |
5509 | gen_fp_to_int_conv_libfunc (convert_optab tab, | |
5510 | const char *opname, | |
5511 | enum machine_mode tmode, | |
5512 | enum machine_mode fmode) | |
5513 | { | |
5514 | if (GET_MODE_CLASS (fmode) != MODE_FLOAT && !DECIMAL_FLOAT_MODE_P (fmode)) | |
5515 | return; | |
5516 | if (GET_MODE_CLASS (tmode) != MODE_INT) | |
5517 | return; | |
5518 | gen_interclass_conv_libfunc (tab, opname, tmode, fmode); | |
5519 | } | |
5520 | ||
fa10beec | 5521 | /* Initialize the libfunc fields of an of an intra-mode-class conversion optab. |
8a33f100 JH |
5522 | The string formation rules are |
5523 | similar to the ones for init_libfunc, above. */ | |
5524 | ||
5525 | static void | |
5526 | gen_intraclass_conv_libfunc (convert_optab tab, const char *opname, | |
5527 | enum machine_mode tmode, enum machine_mode fmode) | |
85363ca0 | 5528 | { |
85363ca0 | 5529 | size_t opname_len = strlen (opname); |
8a33f100 | 5530 | size_t mname_len = 0; |
85363ca0 | 5531 | |
8a33f100 | 5532 | const char *fname, *tname; |
85363ca0 | 5533 | const char *q; |
cdbf4541 | 5534 | int prefix_len = targetm.libfunc_gnu_prefix ? 6 : 2; |
79b87c74 | 5535 | char *nondec_name, *dec_name, *nondec_suffix, *dec_suffix; |
85363ca0 ZW |
5536 | char *libfunc_name, *suffix; |
5537 | char *p; | |
5538 | ||
79b87c74 MM |
5539 | /* If this is a decimal conversion, add the current BID vs. DPD prefix that |
5540 | depends on which underlying decimal floating point format is used. */ | |
5541 | const size_t dec_len = sizeof (DECIMAL_PREFIX) - 1; | |
5542 | ||
8a33f100 | 5543 | mname_len = strlen (GET_MODE_NAME (tmode)) + strlen (GET_MODE_NAME (fmode)); |
85363ca0 | 5544 | |
d3bfe4de | 5545 | nondec_name = XALLOCAVEC (char, 2 + opname_len + mname_len + 1 + 1); |
79b87c74 MM |
5546 | nondec_name[0] = '_'; |
5547 | nondec_name[1] = '_'; | |
cdbf4541 BS |
5548 | if (targetm.libfunc_gnu_prefix) |
5549 | { | |
5550 | nondec_name[2] = 'g'; | |
5551 | nondec_name[3] = 'n'; | |
5552 | nondec_name[4] = 'u'; | |
5553 | nondec_name[5] = '_'; | |
5554 | } | |
5555 | memcpy (&nondec_name[prefix_len], opname, opname_len); | |
5556 | nondec_suffix = nondec_name + opname_len + prefix_len; | |
79b87c74 | 5557 | |
d3bfe4de | 5558 | dec_name = XALLOCAVEC (char, 2 + dec_len + opname_len + mname_len + 1 + 1); |
79b87c74 MM |
5559 | dec_name[0] = '_'; |
5560 | dec_name[1] = '_'; | |
5561 | memcpy (&dec_name[2], DECIMAL_PREFIX, dec_len); | |
5562 | memcpy (&dec_name[2 + dec_len], opname, opname_len); | |
5563 | dec_suffix = dec_name + dec_len + opname_len + 2; | |
85363ca0 | 5564 | |
8a33f100 JH |
5565 | fname = GET_MODE_NAME (fmode); |
5566 | tname = GET_MODE_NAME (tmode); | |
85363ca0 | 5567 | |
8a33f100 JH |
5568 | if (DECIMAL_FLOAT_MODE_P(fmode) || DECIMAL_FLOAT_MODE_P(tmode)) |
5569 | { | |
5570 | libfunc_name = dec_name; | |
5571 | suffix = dec_suffix; | |
5572 | } | |
5573 | else | |
5574 | { | |
5575 | libfunc_name = nondec_name; | |
5576 | suffix = nondec_suffix; | |
5577 | } | |
79b87c74 | 5578 | |
8a33f100 JH |
5579 | p = suffix; |
5580 | for (q = fname; *q; p++, q++) | |
5581 | *p = TOLOWER (*q); | |
5582 | for (q = tname; *q; p++, q++) | |
5583 | *p = TOLOWER (*q); | |
85363ca0 | 5584 | |
8a33f100 JH |
5585 | *p++ = '2'; |
5586 | *p = '\0'; | |
85363ca0 | 5587 | |
8a33f100 JH |
5588 | set_conv_libfunc (tab, tmode, fmode, |
5589 | ggc_alloc_string (libfunc_name, p - libfunc_name)); | |
85363ca0 ZW |
5590 | } |
5591 | ||
8a33f100 JH |
5592 | /* Pick proper libcall for trunc_optab. We need to chose if we do |
5593 | truncation or extension and interclass or intraclass. */ | |
5594 | ||
5595 | static void | |
5596 | gen_trunc_conv_libfunc (convert_optab tab, | |
5597 | const char *opname, | |
5598 | enum machine_mode tmode, | |
5599 | enum machine_mode fmode) | |
5600 | { | |
5601 | if (GET_MODE_CLASS (tmode) != MODE_FLOAT && !DECIMAL_FLOAT_MODE_P (tmode)) | |
5602 | return; | |
5603 | if (GET_MODE_CLASS (fmode) != MODE_FLOAT && !DECIMAL_FLOAT_MODE_P (fmode)) | |
5604 | return; | |
5605 | if (tmode == fmode) | |
5606 | return; | |
5607 | ||
5608 | if ((GET_MODE_CLASS (tmode) == MODE_FLOAT && DECIMAL_FLOAT_MODE_P (fmode)) | |
5609 | || (GET_MODE_CLASS (fmode) == MODE_FLOAT && DECIMAL_FLOAT_MODE_P (tmode))) | |
5610 | gen_interclass_conv_libfunc (tab, opname, tmode, fmode); | |
b8698a0f | 5611 | |
8a33f100 JH |
5612 | if (GET_MODE_PRECISION (fmode) <= GET_MODE_PRECISION (tmode)) |
5613 | return; | |
5614 | ||
5615 | if ((GET_MODE_CLASS (tmode) == MODE_FLOAT | |
5616 | && GET_MODE_CLASS (fmode) == MODE_FLOAT) | |
5617 | || (DECIMAL_FLOAT_MODE_P (fmode) && DECIMAL_FLOAT_MODE_P (tmode))) | |
5618 | gen_intraclass_conv_libfunc (tab, opname, tmode, fmode); | |
5619 | } | |
5620 | ||
5621 | /* Pick proper libcall for extend_optab. We need to chose if we do | |
5622 | truncation or extension and interclass or intraclass. */ | |
5623 | ||
5624 | static void | |
5625 | gen_extend_conv_libfunc (convert_optab tab, | |
5626 | const char *opname ATTRIBUTE_UNUSED, | |
5627 | enum machine_mode tmode, | |
5628 | enum machine_mode fmode) | |
5629 | { | |
5630 | if (GET_MODE_CLASS (tmode) != MODE_FLOAT && !DECIMAL_FLOAT_MODE_P (tmode)) | |
5631 | return; | |
5632 | if (GET_MODE_CLASS (fmode) != MODE_FLOAT && !DECIMAL_FLOAT_MODE_P (fmode)) | |
5633 | return; | |
5634 | if (tmode == fmode) | |
5635 | return; | |
5636 | ||
5637 | if ((GET_MODE_CLASS (tmode) == MODE_FLOAT && DECIMAL_FLOAT_MODE_P (fmode)) | |
5638 | || (GET_MODE_CLASS (fmode) == MODE_FLOAT && DECIMAL_FLOAT_MODE_P (tmode))) | |
5639 | gen_interclass_conv_libfunc (tab, opname, tmode, fmode); | |
b8698a0f | 5640 | |
8a33f100 JH |
5641 | if (GET_MODE_PRECISION (fmode) > GET_MODE_PRECISION (tmode)) |
5642 | return; | |
5643 | ||
5644 | if ((GET_MODE_CLASS (tmode) == MODE_FLOAT | |
5645 | && GET_MODE_CLASS (fmode) == MODE_FLOAT) | |
5646 | || (DECIMAL_FLOAT_MODE_P (fmode) && DECIMAL_FLOAT_MODE_P (tmode))) | |
5647 | gen_intraclass_conv_libfunc (tab, opname, tmode, fmode); | |
5648 | } | |
85363ca0 | 5649 | |
0f996086 CF |
5650 | /* Pick proper libcall for fract_optab. We need to chose if we do |
5651 | interclass or intraclass. */ | |
5652 | ||
5653 | static void | |
5654 | gen_fract_conv_libfunc (convert_optab tab, | |
5655 | const char *opname, | |
5656 | enum machine_mode tmode, | |
5657 | enum machine_mode fmode) | |
5658 | { | |
5659 | if (tmode == fmode) | |
5660 | return; | |
5661 | if (!(ALL_FIXED_POINT_MODE_P (tmode) || ALL_FIXED_POINT_MODE_P (fmode))) | |
5662 | return; | |
5663 | ||
5664 | if (GET_MODE_CLASS (tmode) == GET_MODE_CLASS (fmode)) | |
5665 | gen_intraclass_conv_libfunc (tab, opname, tmode, fmode); | |
5666 | else | |
5667 | gen_interclass_conv_libfunc (tab, opname, tmode, fmode); | |
5668 | } | |
5669 | ||
5670 | /* Pick proper libcall for fractuns_optab. */ | |
5671 | ||
5672 | static void | |
5673 | gen_fractuns_conv_libfunc (convert_optab tab, | |
5674 | const char *opname, | |
5675 | enum machine_mode tmode, | |
5676 | enum machine_mode fmode) | |
5677 | { | |
5678 | if (tmode == fmode) | |
5679 | return; | |
5680 | /* One mode must be a fixed-point mode, and the other must be an integer | |
5681 | mode. */ | |
5682 | if (!((ALL_FIXED_POINT_MODE_P (tmode) && GET_MODE_CLASS (fmode) == MODE_INT) | |
5683 | || (ALL_FIXED_POINT_MODE_P (fmode) | |
5684 | && GET_MODE_CLASS (tmode) == MODE_INT))) | |
5685 | return; | |
5686 | ||
5687 | gen_interclass_conv_libfunc (tab, opname, tmode, fmode); | |
5688 | } | |
5689 | ||
5690 | /* Pick proper libcall for satfract_optab. We need to chose if we do | |
5691 | interclass or intraclass. */ | |
5692 | ||
5693 | static void | |
5694 | gen_satfract_conv_libfunc (convert_optab tab, | |
5695 | const char *opname, | |
5696 | enum machine_mode tmode, | |
5697 | enum machine_mode fmode) | |
5698 | { | |
5699 | if (tmode == fmode) | |
5700 | return; | |
5701 | /* TMODE must be a fixed-point mode. */ | |
5702 | if (!ALL_FIXED_POINT_MODE_P (tmode)) | |
5703 | return; | |
5704 | ||
5705 | if (GET_MODE_CLASS (tmode) == GET_MODE_CLASS (fmode)) | |
5706 | gen_intraclass_conv_libfunc (tab, opname, tmode, fmode); | |
5707 | else | |
5708 | gen_interclass_conv_libfunc (tab, opname, tmode, fmode); | |
5709 | } | |
5710 | ||
5711 | /* Pick proper libcall for satfractuns_optab. */ | |
5712 | ||
5713 | static void | |
5714 | gen_satfractuns_conv_libfunc (convert_optab tab, | |
5715 | const char *opname, | |
5716 | enum machine_mode tmode, | |
5717 | enum machine_mode fmode) | |
5718 | { | |
5719 | if (tmode == fmode) | |
5720 | return; | |
5721 | /* TMODE must be a fixed-point mode, and FMODE must be an integer mode. */ | |
5722 | if (!(ALL_FIXED_POINT_MODE_P (tmode) && GET_MODE_CLASS (fmode) == MODE_INT)) | |
5723 | return; | |
5724 | ||
5725 | gen_interclass_conv_libfunc (tab, opname, tmode, fmode); | |
5726 | } | |
5727 | ||
61698f54 RS |
5728 | /* A table of previously-created libfuncs, hashed by name. */ |
5729 | static GTY ((param_is (union tree_node))) htab_t libfunc_decls; | |
52859c77 | 5730 | |
61698f54 | 5731 | /* Hashtable callbacks for libfunc_decls. */ |
ee1315aa | 5732 | |
61698f54 RS |
5733 | static hashval_t |
5734 | libfunc_decl_hash (const void *entry) | |
5735 | { | |
6456e26e | 5736 | return IDENTIFIER_HASH_VALUE (DECL_NAME ((const_tree) entry)); |
61698f54 | 5737 | } |
52859c77 | 5738 | |
61698f54 RS |
5739 | static int |
5740 | libfunc_decl_eq (const void *entry1, const void *entry2) | |
5741 | { | |
572e5ae3 | 5742 | return DECL_NAME ((const_tree) entry1) == (const_tree) entry2; |
61698f54 | 5743 | } |
52859c77 | 5744 | |
f9417da1 RG |
5745 | /* Build a decl for a libfunc named NAME. */ |
5746 | ||
5747 | tree | |
5748 | build_libfunc_function (const char *name) | |
5749 | { | |
5750 | tree decl = build_decl (UNKNOWN_LOCATION, FUNCTION_DECL, | |
5751 | get_identifier (name), | |
5752 | build_function_type (integer_type_node, NULL_TREE)); | |
5753 | /* ??? We don't have any type information except for this is | |
5754 | a function. Pretend this is "int foo()". */ | |
5755 | DECL_ARTIFICIAL (decl) = 1; | |
5756 | DECL_EXTERNAL (decl) = 1; | |
5757 | TREE_PUBLIC (decl) = 1; | |
5758 | gcc_assert (DECL_ASSEMBLER_NAME (decl)); | |
5759 | ||
5760 | /* Zap the nonsensical SYMBOL_REF_DECL for this. What we're left with | |
5761 | are the flags assigned by targetm.encode_section_info. */ | |
5762 | SET_SYMBOL_REF_DECL (XEXP (DECL_RTL (decl), 0), NULL); | |
5763 | ||
5764 | return decl; | |
5765 | } | |
5766 | ||
61698f54 RS |
5767 | rtx |
5768 | init_one_libfunc (const char *name) | |
5769 | { | |
5770 | tree id, decl; | |
5771 | void **slot; | |
5772 | hashval_t hash; | |
5773 | ||
5774 | if (libfunc_decls == NULL) | |
5775 | libfunc_decls = htab_create_ggc (37, libfunc_decl_hash, | |
5776 | libfunc_decl_eq, NULL); | |
5777 | ||
5778 | /* See if we have already created a libfunc decl for this function. */ | |
5779 | id = get_identifier (name); | |
eef4a603 | 5780 | hash = IDENTIFIER_HASH_VALUE (id); |
61698f54 RS |
5781 | slot = htab_find_slot_with_hash (libfunc_decls, id, hash, INSERT); |
5782 | decl = (tree) *slot; | |
5783 | if (decl == NULL) | |
5784 | { | |
5785 | /* Create a new decl, so that it can be passed to | |
5786 | targetm.encode_section_info. */ | |
f9417da1 | 5787 | decl = build_libfunc_function (name); |
61698f54 RS |
5788 | *slot = decl; |
5789 | } | |
5790 | return XEXP (DECL_RTL (decl), 0); | |
76095e2f RH |
5791 | } |
5792 | ||
6b2b8871 JJ |
5793 | /* Adjust the assembler name of libfunc NAME to ASMSPEC. */ |
5794 | ||
5795 | rtx | |
5796 | set_user_assembler_libfunc (const char *name, const char *asmspec) | |
5797 | { | |
5798 | tree id, decl; | |
5799 | void **slot; | |
5800 | hashval_t hash; | |
5801 | ||
5802 | id = get_identifier (name); | |
eef4a603 | 5803 | hash = IDENTIFIER_HASH_VALUE (id); |
6b2b8871 JJ |
5804 | slot = htab_find_slot_with_hash (libfunc_decls, id, hash, NO_INSERT); |
5805 | gcc_assert (slot); | |
5806 | decl = (tree) *slot; | |
5807 | set_user_assembler_name (decl, asmspec); | |
5808 | return XEXP (DECL_RTL (decl), 0); | |
5809 | } | |
5810 | ||
c15c90bb ZW |
5811 | /* Call this to reset the function entry for one optab (OPTABLE) in mode |
5812 | MODE to NAME, which should be either 0 or a string constant. */ | |
5813 | void | |
5814 | set_optab_libfunc (optab optable, enum machine_mode mode, const char *name) | |
5815 | { | |
8a33f100 JH |
5816 | rtx val; |
5817 | struct libfunc_entry e; | |
5818 | struct libfunc_entry **slot; | |
33727b5e | 5819 | e.optab = (size_t) (optable - &optab_table[0]); |
8a33f100 JH |
5820 | e.mode1 = mode; |
5821 | e.mode2 = VOIDmode; | |
5822 | ||
c15c90bb | 5823 | if (name) |
8a33f100 | 5824 | val = init_one_libfunc (name); |
c15c90bb | 5825 | else |
8a33f100 JH |
5826 | val = 0; |
5827 | slot = (struct libfunc_entry **) htab_find_slot (libfunc_hash, &e, INSERT); | |
5828 | if (*slot == NULL) | |
a9429e29 | 5829 | *slot = ggc_alloc_libfunc_entry (); |
33727b5e | 5830 | (*slot)->optab = (size_t) (optable - &optab_table[0]); |
8a33f100 JH |
5831 | (*slot)->mode1 = mode; |
5832 | (*slot)->mode2 = VOIDmode; | |
5833 | (*slot)->libfunc = val; | |
c15c90bb ZW |
5834 | } |
5835 | ||
85363ca0 ZW |
5836 | /* Call this to reset the function entry for one conversion optab |
5837 | (OPTABLE) from mode FMODE to mode TMODE to NAME, which should be | |
5838 | either 0 or a string constant. */ | |
5839 | void | |
5840 | set_conv_libfunc (convert_optab optable, enum machine_mode tmode, | |
5841 | enum machine_mode fmode, const char *name) | |
5842 | { | |
8a33f100 JH |
5843 | rtx val; |
5844 | struct libfunc_entry e; | |
5845 | struct libfunc_entry **slot; | |
33727b5e | 5846 | e.optab = (size_t) (optable - &convert_optab_table[0]); |
8a33f100 JH |
5847 | e.mode1 = tmode; |
5848 | e.mode2 = fmode; | |
5849 | ||
85363ca0 | 5850 | if (name) |
8a33f100 | 5851 | val = init_one_libfunc (name); |
85363ca0 | 5852 | else |
8a33f100 JH |
5853 | val = 0; |
5854 | slot = (struct libfunc_entry **) htab_find_slot (libfunc_hash, &e, INSERT); | |
5855 | if (*slot == NULL) | |
a9429e29 | 5856 | *slot = ggc_alloc_libfunc_entry (); |
33727b5e | 5857 | (*slot)->optab = (size_t) (optable - &convert_optab_table[0]); |
8a33f100 JH |
5858 | (*slot)->mode1 = tmode; |
5859 | (*slot)->mode2 = fmode; | |
5860 | (*slot)->libfunc = val; | |
85363ca0 ZW |
5861 | } |
5862 | ||
b5deb7b6 | 5863 | /* Call this to initialize the contents of the optabs |
77c9c6c2 RK |
5864 | appropriately for the current target machine. */ |
5865 | ||
5866 | void | |
0c20a65f | 5867 | init_optabs (void) |
77c9c6c2 | 5868 | { |
3e9c326a RS |
5869 | if (libfunc_hash) |
5870 | { | |
5871 | htab_empty (libfunc_hash); | |
5872 | /* We statically initialize the insn_codes with the equivalent of | |
5873 | CODE_FOR_nothing. Repeat the process if reinitialising. */ | |
5874 | init_insn_codes (); | |
5875 | } | |
5876 | else | |
5877 | libfunc_hash = htab_create_ggc (10, hash_libfunc, eq_libfunc, NULL); | |
c0742514 | 5878 | |
33727b5e JJ |
5879 | init_optab (add_optab, PLUS); |
5880 | init_optabv (addv_optab, PLUS); | |
5881 | init_optab (sub_optab, MINUS); | |
5882 | init_optabv (subv_optab, MINUS); | |
5883 | init_optab (ssadd_optab, SS_PLUS); | |
5884 | init_optab (usadd_optab, US_PLUS); | |
5885 | init_optab (sssub_optab, SS_MINUS); | |
5886 | init_optab (ussub_optab, US_MINUS); | |
5887 | init_optab (smul_optab, MULT); | |
5888 | init_optab (ssmul_optab, SS_MULT); | |
5889 | init_optab (usmul_optab, US_MULT); | |
5890 | init_optabv (smulv_optab, MULT); | |
5891 | init_optab (smul_highpart_optab, UNKNOWN); | |
5892 | init_optab (umul_highpart_optab, UNKNOWN); | |
5893 | init_optab (smul_widen_optab, UNKNOWN); | |
5894 | init_optab (umul_widen_optab, UNKNOWN); | |
5895 | init_optab (usmul_widen_optab, UNKNOWN); | |
5896 | init_optab (smadd_widen_optab, UNKNOWN); | |
5897 | init_optab (umadd_widen_optab, UNKNOWN); | |
5898 | init_optab (ssmadd_widen_optab, UNKNOWN); | |
5899 | init_optab (usmadd_widen_optab, UNKNOWN); | |
5900 | init_optab (smsub_widen_optab, UNKNOWN); | |
5901 | init_optab (umsub_widen_optab, UNKNOWN); | |
5902 | init_optab (ssmsub_widen_optab, UNKNOWN); | |
5903 | init_optab (usmsub_widen_optab, UNKNOWN); | |
5904 | init_optab (sdiv_optab, DIV); | |
5905 | init_optab (ssdiv_optab, SS_DIV); | |
5906 | init_optab (usdiv_optab, US_DIV); | |
5907 | init_optabv (sdivv_optab, DIV); | |
5908 | init_optab (sdivmod_optab, UNKNOWN); | |
5909 | init_optab (udiv_optab, UDIV); | |
5910 | init_optab (udivmod_optab, UNKNOWN); | |
5911 | init_optab (smod_optab, MOD); | |
5912 | init_optab (umod_optab, UMOD); | |
5913 | init_optab (fmod_optab, UNKNOWN); | |
5914 | init_optab (remainder_optab, UNKNOWN); | |
5915 | init_optab (ftrunc_optab, UNKNOWN); | |
5916 | init_optab (and_optab, AND); | |
5917 | init_optab (ior_optab, IOR); | |
5918 | init_optab (xor_optab, XOR); | |
5919 | init_optab (ashl_optab, ASHIFT); | |
5920 | init_optab (ssashl_optab, SS_ASHIFT); | |
5921 | init_optab (usashl_optab, US_ASHIFT); | |
5922 | init_optab (ashr_optab, ASHIFTRT); | |
5923 | init_optab (lshr_optab, LSHIFTRT); | |
31a0c825 DP |
5924 | init_optabv (vashl_optab, ASHIFT); |
5925 | init_optabv (vashr_optab, ASHIFTRT); | |
5926 | init_optabv (vlshr_optab, LSHIFTRT); | |
33727b5e JJ |
5927 | init_optab (rotl_optab, ROTATE); |
5928 | init_optab (rotr_optab, ROTATERT); | |
5929 | init_optab (smin_optab, SMIN); | |
5930 | init_optab (smax_optab, SMAX); | |
5931 | init_optab (umin_optab, UMIN); | |
5932 | init_optab (umax_optab, UMAX); | |
5933 | init_optab (pow_optab, UNKNOWN); | |
5934 | init_optab (atan2_optab, UNKNOWN); | |
f03d897a RH |
5935 | init_optab (fma_optab, FMA); |
5936 | init_optab (fms_optab, UNKNOWN); | |
5937 | init_optab (fnma_optab, UNKNOWN); | |
5938 | init_optab (fnms_optab, UNKNOWN); | |
ef89d648 ZW |
5939 | |
5940 | /* These three have codes assigned exclusively for the sake of | |
5941 | have_insn_for. */ | |
33727b5e JJ |
5942 | init_optab (mov_optab, SET); |
5943 | init_optab (movstrict_optab, STRICT_LOW_PART); | |
f90b7a5a PB |
5944 | init_optab (cbranch_optab, COMPARE); |
5945 | ||
5946 | init_optab (cmov_optab, UNKNOWN); | |
5947 | init_optab (cstore_optab, UNKNOWN); | |
5948 | init_optab (ctrap_optab, UNKNOWN); | |
33727b5e JJ |
5949 | |
5950 | init_optab (storent_optab, UNKNOWN); | |
5951 | ||
f90b7a5a | 5952 | init_optab (cmp_optab, UNKNOWN); |
33727b5e | 5953 | init_optab (ucmp_optab, UNKNOWN); |
33727b5e JJ |
5954 | |
5955 | init_optab (eq_optab, EQ); | |
5956 | init_optab (ne_optab, NE); | |
5957 | init_optab (gt_optab, GT); | |
5958 | init_optab (ge_optab, GE); | |
5959 | init_optab (lt_optab, LT); | |
5960 | init_optab (le_optab, LE); | |
5961 | init_optab (unord_optab, UNORDERED); | |
5962 | ||
5963 | init_optab (neg_optab, NEG); | |
5964 | init_optab (ssneg_optab, SS_NEG); | |
5965 | init_optab (usneg_optab, US_NEG); | |
5966 | init_optabv (negv_optab, NEG); | |
5967 | init_optab (abs_optab, ABS); | |
5968 | init_optabv (absv_optab, ABS); | |
5969 | init_optab (addcc_optab, UNKNOWN); | |
5970 | init_optab (one_cmpl_optab, NOT); | |
5971 | init_optab (bswap_optab, BSWAP); | |
5972 | init_optab (ffs_optab, FFS); | |
5973 | init_optab (clz_optab, CLZ); | |
5974 | init_optab (ctz_optab, CTZ); | |
3801c801 | 5975 | init_optab (clrsb_optab, CLRSB); |
33727b5e JJ |
5976 | init_optab (popcount_optab, POPCOUNT); |
5977 | init_optab (parity_optab, PARITY); | |
5978 | init_optab (sqrt_optab, SQRT); | |
5979 | init_optab (floor_optab, UNKNOWN); | |
5980 | init_optab (ceil_optab, UNKNOWN); | |
5981 | init_optab (round_optab, UNKNOWN); | |
5982 | init_optab (btrunc_optab, UNKNOWN); | |
5983 | init_optab (nearbyint_optab, UNKNOWN); | |
5984 | init_optab (rint_optab, UNKNOWN); | |
5985 | init_optab (sincos_optab, UNKNOWN); | |
5986 | init_optab (sin_optab, UNKNOWN); | |
5987 | init_optab (asin_optab, UNKNOWN); | |
5988 | init_optab (cos_optab, UNKNOWN); | |
5989 | init_optab (acos_optab, UNKNOWN); | |
5990 | init_optab (exp_optab, UNKNOWN); | |
5991 | init_optab (exp10_optab, UNKNOWN); | |
5992 | init_optab (exp2_optab, UNKNOWN); | |
5993 | init_optab (expm1_optab, UNKNOWN); | |
5994 | init_optab (ldexp_optab, UNKNOWN); | |
5995 | init_optab (scalb_optab, UNKNOWN); | |
dc6707b8 | 5996 | init_optab (significand_optab, UNKNOWN); |
33727b5e JJ |
5997 | init_optab (logb_optab, UNKNOWN); |
5998 | init_optab (ilogb_optab, UNKNOWN); | |
5999 | init_optab (log_optab, UNKNOWN); | |
6000 | init_optab (log10_optab, UNKNOWN); | |
6001 | init_optab (log2_optab, UNKNOWN); | |
6002 | init_optab (log1p_optab, UNKNOWN); | |
6003 | init_optab (tan_optab, UNKNOWN); | |
6004 | init_optab (atan_optab, UNKNOWN); | |
6005 | init_optab (copysign_optab, UNKNOWN); | |
6006 | init_optab (signbit_optab, UNKNOWN); | |
6007 | ||
6008 | init_optab (isinf_optab, UNKNOWN); | |
6009 | ||
6010 | init_optab (strlen_optab, UNKNOWN); | |
33727b5e JJ |
6011 | init_optab (push_optab, UNKNOWN); |
6012 | ||
6013 | init_optab (reduc_smax_optab, UNKNOWN); | |
6014 | init_optab (reduc_umax_optab, UNKNOWN); | |
6015 | init_optab (reduc_smin_optab, UNKNOWN); | |
6016 | init_optab (reduc_umin_optab, UNKNOWN); | |
6017 | init_optab (reduc_splus_optab, UNKNOWN); | |
6018 | init_optab (reduc_uplus_optab, UNKNOWN); | |
6019 | ||
6020 | init_optab (ssum_widen_optab, UNKNOWN); | |
6021 | init_optab (usum_widen_optab, UNKNOWN); | |
b8698a0f | 6022 | init_optab (sdot_prod_optab, UNKNOWN); |
33727b5e JJ |
6023 | init_optab (udot_prod_optab, UNKNOWN); |
6024 | ||
6025 | init_optab (vec_extract_optab, UNKNOWN); | |
6026 | init_optab (vec_extract_even_optab, UNKNOWN); | |
6027 | init_optab (vec_extract_odd_optab, UNKNOWN); | |
6028 | init_optab (vec_interleave_high_optab, UNKNOWN); | |
6029 | init_optab (vec_interleave_low_optab, UNKNOWN); | |
6030 | init_optab (vec_set_optab, UNKNOWN); | |
6031 | init_optab (vec_init_optab, UNKNOWN); | |
6032 | init_optab (vec_shl_optab, UNKNOWN); | |
6033 | init_optab (vec_shr_optab, UNKNOWN); | |
6034 | init_optab (vec_realign_load_optab, UNKNOWN); | |
6035 | init_optab (movmisalign_optab, UNKNOWN); | |
6036 | init_optab (vec_widen_umult_hi_optab, UNKNOWN); | |
6037 | init_optab (vec_widen_umult_lo_optab, UNKNOWN); | |
6038 | init_optab (vec_widen_smult_hi_optab, UNKNOWN); | |
6039 | init_optab (vec_widen_smult_lo_optab, UNKNOWN); | |
6040 | init_optab (vec_unpacks_hi_optab, UNKNOWN); | |
6041 | init_optab (vec_unpacks_lo_optab, UNKNOWN); | |
6042 | init_optab (vec_unpacku_hi_optab, UNKNOWN); | |
6043 | init_optab (vec_unpacku_lo_optab, UNKNOWN); | |
6044 | init_optab (vec_unpacks_float_hi_optab, UNKNOWN); | |
6045 | init_optab (vec_unpacks_float_lo_optab, UNKNOWN); | |
6046 | init_optab (vec_unpacku_float_hi_optab, UNKNOWN); | |
6047 | init_optab (vec_unpacku_float_lo_optab, UNKNOWN); | |
6048 | init_optab (vec_pack_trunc_optab, UNKNOWN); | |
6049 | init_optab (vec_pack_usat_optab, UNKNOWN); | |
6050 | init_optab (vec_pack_ssat_optab, UNKNOWN); | |
6051 | init_optab (vec_pack_ufix_trunc_optab, UNKNOWN); | |
6052 | init_optab (vec_pack_sfix_trunc_optab, UNKNOWN); | |
6053 | ||
6054 | init_optab (powi_optab, UNKNOWN); | |
17684d46 | 6055 | |
85363ca0 | 6056 | /* Conversions. */ |
33727b5e JJ |
6057 | init_convert_optab (sext_optab, SIGN_EXTEND); |
6058 | init_convert_optab (zext_optab, ZERO_EXTEND); | |
6059 | init_convert_optab (trunc_optab, TRUNCATE); | |
6060 | init_convert_optab (sfix_optab, FIX); | |
6061 | init_convert_optab (ufix_optab, UNSIGNED_FIX); | |
6062 | init_convert_optab (sfixtrunc_optab, UNKNOWN); | |
6063 | init_convert_optab (ufixtrunc_optab, UNKNOWN); | |
6064 | init_convert_optab (sfloat_optab, FLOAT); | |
6065 | init_convert_optab (ufloat_optab, UNSIGNED_FLOAT); | |
6066 | init_convert_optab (lrint_optab, UNKNOWN); | |
6067 | init_convert_optab (lround_optab, UNKNOWN); | |
6068 | init_convert_optab (lfloor_optab, UNKNOWN); | |
6069 | init_convert_optab (lceil_optab, UNKNOWN); | |
6070 | ||
6071 | init_convert_optab (fract_optab, FRACT_CONVERT); | |
6072 | init_convert_optab (fractuns_optab, UNSIGNED_FRACT_CONVERT); | |
6073 | init_convert_optab (satfract_optab, SAT_FRACT); | |
6074 | init_convert_optab (satfractuns_optab, UNSIGNED_SAT_FRACT); | |
0f996086 | 6075 | |
5d81dc5b RK |
6076 | /* Fill in the optabs with the insns we support. */ |
6077 | init_all_optabs (); | |
6078 | ||
5d81dc5b | 6079 | /* Initialize the optabs with the names of the library functions. */ |
8a33f100 JH |
6080 | add_optab->libcall_basename = "add"; |
6081 | add_optab->libcall_suffix = '3'; | |
0f996086 | 6082 | add_optab->libcall_gen = gen_int_fp_fixed_libfunc; |
8a33f100 JH |
6083 | addv_optab->libcall_basename = "add"; |
6084 | addv_optab->libcall_suffix = '3'; | |
6085 | addv_optab->libcall_gen = gen_intv_fp_libfunc; | |
0f996086 CF |
6086 | ssadd_optab->libcall_basename = "ssadd"; |
6087 | ssadd_optab->libcall_suffix = '3'; | |
6088 | ssadd_optab->libcall_gen = gen_signed_fixed_libfunc; | |
6089 | usadd_optab->libcall_basename = "usadd"; | |
6090 | usadd_optab->libcall_suffix = '3'; | |
6091 | usadd_optab->libcall_gen = gen_unsigned_fixed_libfunc; | |
8a33f100 JH |
6092 | sub_optab->libcall_basename = "sub"; |
6093 | sub_optab->libcall_suffix = '3'; | |
0f996086 | 6094 | sub_optab->libcall_gen = gen_int_fp_fixed_libfunc; |
8a33f100 JH |
6095 | subv_optab->libcall_basename = "sub"; |
6096 | subv_optab->libcall_suffix = '3'; | |
6097 | subv_optab->libcall_gen = gen_intv_fp_libfunc; | |
0f996086 CF |
6098 | sssub_optab->libcall_basename = "sssub"; |
6099 | sssub_optab->libcall_suffix = '3'; | |
6100 | sssub_optab->libcall_gen = gen_signed_fixed_libfunc; | |
6101 | ussub_optab->libcall_basename = "ussub"; | |
6102 | ussub_optab->libcall_suffix = '3'; | |
6103 | ussub_optab->libcall_gen = gen_unsigned_fixed_libfunc; | |
8a33f100 JH |
6104 | smul_optab->libcall_basename = "mul"; |
6105 | smul_optab->libcall_suffix = '3'; | |
0f996086 | 6106 | smul_optab->libcall_gen = gen_int_fp_fixed_libfunc; |
8a33f100 JH |
6107 | smulv_optab->libcall_basename = "mul"; |
6108 | smulv_optab->libcall_suffix = '3'; | |
6109 | smulv_optab->libcall_gen = gen_intv_fp_libfunc; | |
0f996086 CF |
6110 | ssmul_optab->libcall_basename = "ssmul"; |
6111 | ssmul_optab->libcall_suffix = '3'; | |
6112 | ssmul_optab->libcall_gen = gen_signed_fixed_libfunc; | |
6113 | usmul_optab->libcall_basename = "usmul"; | |
6114 | usmul_optab->libcall_suffix = '3'; | |
6115 | usmul_optab->libcall_gen = gen_unsigned_fixed_libfunc; | |
8a33f100 JH |
6116 | sdiv_optab->libcall_basename = "div"; |
6117 | sdiv_optab->libcall_suffix = '3'; | |
0f996086 | 6118 | sdiv_optab->libcall_gen = gen_int_fp_signed_fixed_libfunc; |
8a33f100 JH |
6119 | sdivv_optab->libcall_basename = "divv"; |
6120 | sdivv_optab->libcall_suffix = '3'; | |
6121 | sdivv_optab->libcall_gen = gen_int_libfunc; | |
0f996086 CF |
6122 | ssdiv_optab->libcall_basename = "ssdiv"; |
6123 | ssdiv_optab->libcall_suffix = '3'; | |
6124 | ssdiv_optab->libcall_gen = gen_signed_fixed_libfunc; | |
8a33f100 JH |
6125 | udiv_optab->libcall_basename = "udiv"; |
6126 | udiv_optab->libcall_suffix = '3'; | |
0f996086 CF |
6127 | udiv_optab->libcall_gen = gen_int_unsigned_fixed_libfunc; |
6128 | usdiv_optab->libcall_basename = "usdiv"; | |
6129 | usdiv_optab->libcall_suffix = '3'; | |
6130 | usdiv_optab->libcall_gen = gen_unsigned_fixed_libfunc; | |
8a33f100 JH |
6131 | sdivmod_optab->libcall_basename = "divmod"; |
6132 | sdivmod_optab->libcall_suffix = '4'; | |
6133 | sdivmod_optab->libcall_gen = gen_int_libfunc; | |
6134 | udivmod_optab->libcall_basename = "udivmod"; | |
6135 | udivmod_optab->libcall_suffix = '4'; | |
6136 | udivmod_optab->libcall_gen = gen_int_libfunc; | |
6137 | smod_optab->libcall_basename = "mod"; | |
6138 | smod_optab->libcall_suffix = '3'; | |
6139 | smod_optab->libcall_gen = gen_int_libfunc; | |
6140 | umod_optab->libcall_basename = "umod"; | |
6141 | umod_optab->libcall_suffix = '3'; | |
6142 | umod_optab->libcall_gen = gen_int_libfunc; | |
6143 | ftrunc_optab->libcall_basename = "ftrunc"; | |
6144 | ftrunc_optab->libcall_suffix = '2'; | |
6145 | ftrunc_optab->libcall_gen = gen_fp_libfunc; | |
6146 | and_optab->libcall_basename = "and"; | |
6147 | and_optab->libcall_suffix = '3'; | |
6148 | and_optab->libcall_gen = gen_int_libfunc; | |
6149 | ior_optab->libcall_basename = "ior"; | |
6150 | ior_optab->libcall_suffix = '3'; | |
6151 | ior_optab->libcall_gen = gen_int_libfunc; | |
6152 | xor_optab->libcall_basename = "xor"; | |
6153 | xor_optab->libcall_suffix = '3'; | |
6154 | xor_optab->libcall_gen = gen_int_libfunc; | |
6155 | ashl_optab->libcall_basename = "ashl"; | |
6156 | ashl_optab->libcall_suffix = '3'; | |
0f996086 CF |
6157 | ashl_optab->libcall_gen = gen_int_fixed_libfunc; |
6158 | ssashl_optab->libcall_basename = "ssashl"; | |
6159 | ssashl_optab->libcall_suffix = '3'; | |
6160 | ssashl_optab->libcall_gen = gen_signed_fixed_libfunc; | |
6161 | usashl_optab->libcall_basename = "usashl"; | |
6162 | usashl_optab->libcall_suffix = '3'; | |
6163 | usashl_optab->libcall_gen = gen_unsigned_fixed_libfunc; | |
8a33f100 JH |
6164 | ashr_optab->libcall_basename = "ashr"; |
6165 | ashr_optab->libcall_suffix = '3'; | |
0f996086 | 6166 | ashr_optab->libcall_gen = gen_int_signed_fixed_libfunc; |
8a33f100 JH |
6167 | lshr_optab->libcall_basename = "lshr"; |
6168 | lshr_optab->libcall_suffix = '3'; | |
0f996086 | 6169 | lshr_optab->libcall_gen = gen_int_unsigned_fixed_libfunc; |
8a33f100 JH |
6170 | smin_optab->libcall_basename = "min"; |
6171 | smin_optab->libcall_suffix = '3'; | |
6172 | smin_optab->libcall_gen = gen_int_fp_libfunc; | |
6173 | smax_optab->libcall_basename = "max"; | |
6174 | smax_optab->libcall_suffix = '3'; | |
6175 | smax_optab->libcall_gen = gen_int_fp_libfunc; | |
6176 | umin_optab->libcall_basename = "umin"; | |
6177 | umin_optab->libcall_suffix = '3'; | |
6178 | umin_optab->libcall_gen = gen_int_libfunc; | |
6179 | umax_optab->libcall_basename = "umax"; | |
6180 | umax_optab->libcall_suffix = '3'; | |
6181 | umax_optab->libcall_gen = gen_int_libfunc; | |
6182 | neg_optab->libcall_basename = "neg"; | |
6183 | neg_optab->libcall_suffix = '2'; | |
0f996086 CF |
6184 | neg_optab->libcall_gen = gen_int_fp_fixed_libfunc; |
6185 | ssneg_optab->libcall_basename = "ssneg"; | |
6186 | ssneg_optab->libcall_suffix = '2'; | |
6187 | ssneg_optab->libcall_gen = gen_signed_fixed_libfunc; | |
6188 | usneg_optab->libcall_basename = "usneg"; | |
6189 | usneg_optab->libcall_suffix = '2'; | |
6190 | usneg_optab->libcall_gen = gen_unsigned_fixed_libfunc; | |
8a33f100 JH |
6191 | negv_optab->libcall_basename = "neg"; |
6192 | negv_optab->libcall_suffix = '2'; | |
6193 | negv_optab->libcall_gen = gen_intv_fp_libfunc; | |
6194 | one_cmpl_optab->libcall_basename = "one_cmpl"; | |
6195 | one_cmpl_optab->libcall_suffix = '2'; | |
6196 | one_cmpl_optab->libcall_gen = gen_int_libfunc; | |
6197 | ffs_optab->libcall_basename = "ffs"; | |
6198 | ffs_optab->libcall_suffix = '2'; | |
6199 | ffs_optab->libcall_gen = gen_int_libfunc; | |
6200 | clz_optab->libcall_basename = "clz"; | |
6201 | clz_optab->libcall_suffix = '2'; | |
6202 | clz_optab->libcall_gen = gen_int_libfunc; | |
6203 | ctz_optab->libcall_basename = "ctz"; | |
6204 | ctz_optab->libcall_suffix = '2'; | |
6205 | ctz_optab->libcall_gen = gen_int_libfunc; | |
3801c801 BS |
6206 | clrsb_optab->libcall_basename = "clrsb"; |
6207 | clrsb_optab->libcall_suffix = '2'; | |
6208 | clrsb_optab->libcall_gen = gen_int_libfunc; | |
8a33f100 JH |
6209 | popcount_optab->libcall_basename = "popcount"; |
6210 | popcount_optab->libcall_suffix = '2'; | |
6211 | popcount_optab->libcall_gen = gen_int_libfunc; | |
6212 | parity_optab->libcall_basename = "parity"; | |
6213 | parity_optab->libcall_suffix = '2'; | |
6214 | parity_optab->libcall_gen = gen_int_libfunc; | |
d55ab31d MM |
6215 | |
6216 | /* Comparison libcalls for integers MUST come in pairs, | |
6217 | signed/unsigned. */ | |
8a33f100 JH |
6218 | cmp_optab->libcall_basename = "cmp"; |
6219 | cmp_optab->libcall_suffix = '2'; | |
0f996086 | 6220 | cmp_optab->libcall_gen = gen_int_fp_fixed_libfunc; |
8a33f100 JH |
6221 | ucmp_optab->libcall_basename = "ucmp"; |
6222 | ucmp_optab->libcall_suffix = '2'; | |
6223 | ucmp_optab->libcall_gen = gen_int_libfunc; | |
d55ab31d MM |
6224 | |
6225 | /* EQ etc are floating point only. */ | |
8a33f100 JH |
6226 | eq_optab->libcall_basename = "eq"; |
6227 | eq_optab->libcall_suffix = '2'; | |
6228 | eq_optab->libcall_gen = gen_fp_libfunc; | |
6229 | ne_optab->libcall_basename = "ne"; | |
6230 | ne_optab->libcall_suffix = '2'; | |
6231 | ne_optab->libcall_gen = gen_fp_libfunc; | |
6232 | gt_optab->libcall_basename = "gt"; | |
6233 | gt_optab->libcall_suffix = '2'; | |
6234 | gt_optab->libcall_gen = gen_fp_libfunc; | |
6235 | ge_optab->libcall_basename = "ge"; | |
6236 | ge_optab->libcall_suffix = '2'; | |
6237 | ge_optab->libcall_gen = gen_fp_libfunc; | |
6238 | lt_optab->libcall_basename = "lt"; | |
6239 | lt_optab->libcall_suffix = '2'; | |
6240 | lt_optab->libcall_gen = gen_fp_libfunc; | |
6241 | le_optab->libcall_basename = "le"; | |
6242 | le_optab->libcall_suffix = '2'; | |
6243 | le_optab->libcall_gen = gen_fp_libfunc; | |
6244 | unord_optab->libcall_basename = "unord"; | |
6245 | unord_optab->libcall_suffix = '2'; | |
6246 | unord_optab->libcall_gen = gen_fp_libfunc; | |
6247 | ||
6248 | powi_optab->libcall_basename = "powi"; | |
6249 | powi_optab->libcall_suffix = '2'; | |
6250 | powi_optab->libcall_gen = gen_fp_libfunc; | |
17684d46 | 6251 | |
d55ab31d | 6252 | /* Conversions. */ |
8a33f100 JH |
6253 | sfloat_optab->libcall_basename = "float"; |
6254 | sfloat_optab->libcall_gen = gen_int_to_fp_conv_libfunc; | |
6255 | ufloat_optab->libcall_gen = gen_ufloat_conv_libfunc; | |
6256 | sfix_optab->libcall_basename = "fix"; | |
6257 | sfix_optab->libcall_gen = gen_fp_to_int_conv_libfunc; | |
6258 | ufix_optab->libcall_basename = "fixuns"; | |
6259 | ufix_optab->libcall_gen = gen_fp_to_int_conv_libfunc; | |
6260 | lrint_optab->libcall_basename = "lrint"; | |
6261 | lrint_optab->libcall_gen = gen_int_to_fp_nondecimal_conv_libfunc; | |
6262 | lround_optab->libcall_basename = "lround"; | |
6263 | lround_optab->libcall_gen = gen_int_to_fp_nondecimal_conv_libfunc; | |
6264 | lfloor_optab->libcall_basename = "lfloor"; | |
6265 | lfloor_optab->libcall_gen = gen_int_to_fp_nondecimal_conv_libfunc; | |
6266 | lceil_optab->libcall_basename = "lceil"; | |
6267 | lceil_optab->libcall_gen = gen_int_to_fp_nondecimal_conv_libfunc; | |
6268 | ||
6269 | /* trunc_optab is also used for FLOAT_EXTEND. */ | |
6270 | sext_optab->libcall_basename = "extend"; | |
6271 | sext_optab->libcall_gen = gen_extend_conv_libfunc; | |
6272 | trunc_optab->libcall_basename = "trunc"; | |
6273 | trunc_optab->libcall_gen = gen_trunc_conv_libfunc; | |
6274 | ||
0f996086 CF |
6275 | /* Conversions for fixed-point modes and other modes. */ |
6276 | fract_optab->libcall_basename = "fract"; | |
6277 | fract_optab->libcall_gen = gen_fract_conv_libfunc; | |
6278 | satfract_optab->libcall_basename = "satfract"; | |
6279 | satfract_optab->libcall_gen = gen_satfract_conv_libfunc; | |
6280 | fractuns_optab->libcall_basename = "fractuns"; | |
6281 | fractuns_optab->libcall_gen = gen_fractuns_conv_libfunc; | |
6282 | satfractuns_optab->libcall_basename = "satfractuns"; | |
6283 | satfractuns_optab->libcall_gen = gen_satfractuns_conv_libfunc; | |
6284 | ||
8a33f100 JH |
6285 | /* The ffs function operates on `int'. Fall back on it if we do not |
6286 | have a libgcc2 function for that width. */ | |
6287 | if (INT_TYPE_SIZE < BITS_PER_WORD) | |
0f900dfa JJ |
6288 | set_optab_libfunc (ffs_optab, mode_for_size (INT_TYPE_SIZE, MODE_INT, 0), |
6289 | "ffs"); | |
76095e2f | 6290 | |
167fa32c EC |
6291 | /* Explicitly initialize the bswap libfuncs since we need them to be |
6292 | valid for things other than word_mode. */ | |
cdbf4541 BS |
6293 | if (targetm.libfunc_gnu_prefix) |
6294 | { | |
6295 | set_optab_libfunc (bswap_optab, SImode, "__gnu_bswapsi2"); | |
6296 | set_optab_libfunc (bswap_optab, DImode, "__gnu_bswapdi2"); | |
6297 | } | |
6298 | else | |
6299 | { | |
6300 | set_optab_libfunc (bswap_optab, SImode, "__bswapsi2"); | |
6301 | set_optab_libfunc (bswap_optab, DImode, "__bswapdi2"); | |
6302 | } | |
167fa32c | 6303 | |
85363ca0 ZW |
6304 | /* Use cabs for double complex abs, since systems generally have cabs. |
6305 | Don't define any libcall for float complex, so that cabs will be used. */ | |
6306 | if (complex_double_type_node) | |
8a33f100 | 6307 | set_optab_libfunc (abs_optab, TYPE_MODE (complex_double_type_node), "cabs"); |
76095e2f | 6308 | |
9602f5a0 | 6309 | abort_libfunc = init_one_libfunc ("abort"); |
76095e2f | 6310 | memcpy_libfunc = init_one_libfunc ("memcpy"); |
b215b52e | 6311 | memmove_libfunc = init_one_libfunc ("memmove"); |
76095e2f | 6312 | memcmp_libfunc = init_one_libfunc ("memcmp"); |
76095e2f | 6313 | memset_libfunc = init_one_libfunc ("memset"); |
68d28100 | 6314 | setbits_libfunc = init_one_libfunc ("__setbits"); |
76095e2f | 6315 | |
6e6a07d2 | 6316 | #ifndef DONT_USE_BUILTIN_SETJMP |
76095e2f RH |
6317 | setjmp_libfunc = init_one_libfunc ("__builtin_setjmp"); |
6318 | longjmp_libfunc = init_one_libfunc ("__builtin_longjmp"); | |
27a36778 | 6319 | #else |
76095e2f RH |
6320 | setjmp_libfunc = init_one_libfunc ("setjmp"); |
6321 | longjmp_libfunc = init_one_libfunc ("longjmp"); | |
27a36778 | 6322 | #endif |
52a11cbf RH |
6323 | unwind_sjlj_register_libfunc = init_one_libfunc ("_Unwind_SjLj_Register"); |
6324 | unwind_sjlj_unregister_libfunc | |
6325 | = init_one_libfunc ("_Unwind_SjLj_Unregister"); | |
6adb4e3a | 6326 | |
07417085 KR |
6327 | /* For function entry/exit instrumentation. */ |
6328 | profile_function_entry_libfunc | |
76095e2f | 6329 | = init_one_libfunc ("__cyg_profile_func_enter"); |
07417085 | 6330 | profile_function_exit_libfunc |
76095e2f | 6331 | = init_one_libfunc ("__cyg_profile_func_exit"); |
07417085 | 6332 | |
68d28100 | 6333 | gcov_flush_libfunc = init_one_libfunc ("__gcov_flush"); |
68d28100 | 6334 | |
159c2aed | 6335 | /* Allow the target to add more libcalls or rename some, etc. */ |
c15c90bb | 6336 | targetm.init_libfuncs (); |
77c9c6c2 | 6337 | } |
b3f8d95d | 6338 | |
b3f8d95d MM |
6339 | /* Print information about the current contents of the optabs on |
6340 | STDERR. */ | |
6341 | ||
24e47c76 | 6342 | DEBUG_FUNCTION void |
b3f8d95d MM |
6343 | debug_optab_libfuncs (void) |
6344 | { | |
6345 | int i; | |
6346 | int j; | |
6347 | int k; | |
6348 | ||
6349 | /* Dump the arithmetic optabs. */ | |
5906d013 | 6350 | for (i = 0; i != (int) OTI_MAX; i++) |
b3f8d95d MM |
6351 | for (j = 0; j < NUM_MACHINE_MODES; ++j) |
6352 | { | |
6353 | optab o; | |
8a33f100 | 6354 | rtx l; |
b3f8d95d | 6355 | |
33727b5e | 6356 | o = &optab_table[i]; |
bbbbb16a | 6357 | l = optab_libfunc (o, (enum machine_mode) j); |
8a33f100 | 6358 | if (l) |
b3f8d95d | 6359 | { |
8a33f100 | 6360 | gcc_assert (GET_CODE (l) == SYMBOL_REF); |
5906d013 | 6361 | fprintf (stderr, "%s\t%s:\t%s\n", |
b3f8d95d MM |
6362 | GET_RTX_NAME (o->code), |
6363 | GET_MODE_NAME (j), | |
8a33f100 | 6364 | XSTR (l, 0)); |
b3f8d95d MM |
6365 | } |
6366 | } | |
6367 | ||
6368 | /* Dump the conversion optabs. */ | |
c414ac1d | 6369 | for (i = 0; i < (int) COI_MAX; ++i) |
b3f8d95d MM |
6370 | for (j = 0; j < NUM_MACHINE_MODES; ++j) |
6371 | for (k = 0; k < NUM_MACHINE_MODES; ++k) | |
6372 | { | |
6373 | convert_optab o; | |
8a33f100 | 6374 | rtx l; |
b3f8d95d | 6375 | |
33727b5e | 6376 | o = &convert_optab_table[i]; |
bbbbb16a ILT |
6377 | l = convert_optab_libfunc (o, (enum machine_mode) j, |
6378 | (enum machine_mode) k); | |
8a33f100 | 6379 | if (l) |
b3f8d95d | 6380 | { |
8a33f100 | 6381 | gcc_assert (GET_CODE (l) == SYMBOL_REF); |
5906d013 | 6382 | fprintf (stderr, "%s\t%s\t%s:\t%s\n", |
b3f8d95d MM |
6383 | GET_RTX_NAME (o->code), |
6384 | GET_MODE_NAME (j), | |
6385 | GET_MODE_NAME (k), | |
8a33f100 | 6386 | XSTR (l, 0)); |
b3f8d95d MM |
6387 | } |
6388 | } | |
6389 | } | |
6390 | ||
7e1966ca | 6391 | \f |
e0cd0770 JC |
6392 | /* Generate insns to trap with code TCODE if OP1 and OP2 satisfy condition |
6393 | CODE. Return 0 on failure. */ | |
6394 | ||
6395 | rtx | |
f90b7a5a | 6396 | gen_cond_trap (enum rtx_code code, rtx op1, rtx op2, rtx tcode) |
e0cd0770 JC |
6397 | { |
6398 | enum machine_mode mode = GET_MODE (op1); | |
842a431a DM |
6399 | enum insn_code icode; |
6400 | rtx insn; | |
f90b7a5a | 6401 | rtx trap_rtx; |
e0cd0770 JC |
6402 | |
6403 | if (mode == VOIDmode) | |
6404 | return 0; | |
6405 | ||
947131ba | 6406 | icode = optab_handler (ctrap_optab, mode); |
842a431a DM |
6407 | if (icode == CODE_FOR_nothing) |
6408 | return 0; | |
6409 | ||
f90b7a5a | 6410 | /* Some targets only accept a zero trap code. */ |
2ef6ce06 | 6411 | if (!insn_operand_matches (icode, 3, tcode)) |
f90b7a5a PB |
6412 | return 0; |
6413 | ||
6414 | do_pending_stack_adjust (); | |
842a431a | 6415 | start_sequence (); |
f90b7a5a PB |
6416 | prepare_cmp_insn (op1, op2, code, NULL_RTX, false, OPTAB_DIRECT, |
6417 | &trap_rtx, &mode); | |
6418 | if (!trap_rtx) | |
6419 | insn = NULL_RTX; | |
6420 | else | |
6421 | insn = GEN_FCN (icode) (trap_rtx, XEXP (trap_rtx, 0), XEXP (trap_rtx, 1), | |
6422 | tcode); | |
6423 | ||
6424 | /* If that failed, then give up. */ | |
6425 | if (insn == 0) | |
d893ccde RH |
6426 | { |
6427 | end_sequence (); | |
6428 | return 0; | |
6429 | } | |
842a431a | 6430 | |
f90b7a5a PB |
6431 | emit_insn (insn); |
6432 | insn = get_insns (); | |
842a431a | 6433 | end_sequence (); |
842a431a | 6434 | return insn; |
e0cd0770 | 6435 | } |
e2500fed | 6436 | |
7ce67fbe DP |
6437 | /* Return rtx code for TCODE. Use UNSIGNEDP to select signed |
6438 | or unsigned operation code. */ | |
6439 | ||
6440 | static enum rtx_code | |
6441 | get_rtx_code (enum tree_code tcode, bool unsignedp) | |
6442 | { | |
6443 | enum rtx_code code; | |
6444 | switch (tcode) | |
6445 | { | |
6446 | case EQ_EXPR: | |
6447 | code = EQ; | |
6448 | break; | |
6449 | case NE_EXPR: | |
6450 | code = NE; | |
6451 | break; | |
6452 | case LT_EXPR: | |
6453 | code = unsignedp ? LTU : LT; | |
6454 | break; | |
6455 | case LE_EXPR: | |
6456 | code = unsignedp ? LEU : LE; | |
6457 | break; | |
6458 | case GT_EXPR: | |
6459 | code = unsignedp ? GTU : GT; | |
6460 | break; | |
6461 | case GE_EXPR: | |
6462 | code = unsignedp ? GEU : GE; | |
6463 | break; | |
c414ac1d | 6464 | |
7ce67fbe DP |
6465 | case UNORDERED_EXPR: |
6466 | code = UNORDERED; | |
6467 | break; | |
6468 | case ORDERED_EXPR: | |
6469 | code = ORDERED; | |
6470 | break; | |
6471 | case UNLT_EXPR: | |
6472 | code = UNLT; | |
6473 | break; | |
6474 | case UNLE_EXPR: | |
6475 | code = UNLE; | |
6476 | break; | |
6477 | case UNGT_EXPR: | |
6478 | code = UNGT; | |
6479 | break; | |
6480 | case UNGE_EXPR: | |
6481 | code = UNGE; | |
6482 | break; | |
6483 | case UNEQ_EXPR: | |
6484 | code = UNEQ; | |
6485 | break; | |
6486 | case LTGT_EXPR: | |
6487 | code = LTGT; | |
6488 | break; | |
6489 | ||
6490 | default: | |
e3feb571 | 6491 | gcc_unreachable (); |
7ce67fbe DP |
6492 | } |
6493 | return code; | |
6494 | } | |
6495 | ||
6496 | /* Return comparison rtx for COND. Use UNSIGNEDP to select signed or | |
6497 | unsigned operators. Do not generate compare instruction. */ | |
6498 | ||
6499 | static rtx | |
6500 | vector_compare_rtx (tree cond, bool unsignedp, enum insn_code icode) | |
6501 | { | |
a5c7d693 | 6502 | struct expand_operand ops[2]; |
7ce67fbe DP |
6503 | enum rtx_code rcode; |
6504 | tree t_op0, t_op1; | |
6505 | rtx rtx_op0, rtx_op1; | |
6506 | ||
e3feb571 NS |
6507 | /* This is unlikely. While generating VEC_COND_EXPR, auto vectorizer |
6508 | ensures that condition is a relational operation. */ | |
6509 | gcc_assert (COMPARISON_CLASS_P (cond)); | |
7ce67fbe | 6510 | |
c414ac1d | 6511 | rcode = get_rtx_code (TREE_CODE (cond), unsignedp); |
e3feb571 NS |
6512 | t_op0 = TREE_OPERAND (cond, 0); |
6513 | t_op1 = TREE_OPERAND (cond, 1); | |
c414ac1d | 6514 | |
7ce67fbe | 6515 | /* Expand operands. */ |
49452c07 UB |
6516 | rtx_op0 = expand_expr (t_op0, NULL_RTX, TYPE_MODE (TREE_TYPE (t_op0)), |
6517 | EXPAND_STACK_PARM); | |
6518 | rtx_op1 = expand_expr (t_op1, NULL_RTX, TYPE_MODE (TREE_TYPE (t_op1)), | |
6519 | EXPAND_STACK_PARM); | |
7ce67fbe | 6520 | |
a5c7d693 RS |
6521 | create_input_operand (&ops[0], rtx_op0, GET_MODE (rtx_op0)); |
6522 | create_input_operand (&ops[1], rtx_op1, GET_MODE (rtx_op1)); | |
6523 | if (!maybe_legitimize_operands (icode, 4, 2, ops)) | |
6524 | gcc_unreachable (); | |
6525 | return gen_rtx_fmt_ee (rcode, VOIDmode, ops[0].value, ops[1].value); | |
7ce67fbe DP |
6526 | } |
6527 | ||
8e7aa1f9 | 6528 | /* Return insn code for TYPE, the type of a VEC_COND_EXPR. */ |
c414ac1d EC |
6529 | |
6530 | static inline enum insn_code | |
8e7aa1f9 | 6531 | get_vcond_icode (tree type, enum machine_mode mode) |
7ce67fbe DP |
6532 | { |
6533 | enum insn_code icode = CODE_FOR_nothing; | |
6534 | ||
8e7aa1f9 | 6535 | if (TYPE_UNSIGNED (type)) |
f9621cc4 | 6536 | icode = direct_optab_handler (vcondu_optab, mode); |
7ce67fbe | 6537 | else |
f9621cc4 | 6538 | icode = direct_optab_handler (vcond_optab, mode); |
7ce67fbe DP |
6539 | return icode; |
6540 | } | |
6541 | ||
6542 | /* Return TRUE iff, appropriate vector insns are available | |
8e7aa1f9 | 6543 | for vector cond expr with type TYPE in VMODE mode. */ |
7ce67fbe DP |
6544 | |
6545 | bool | |
8e7aa1f9 | 6546 | expand_vec_cond_expr_p (tree type, enum machine_mode vmode) |
7ce67fbe | 6547 | { |
8e7aa1f9 | 6548 | if (get_vcond_icode (type, vmode) == CODE_FOR_nothing) |
7ce67fbe DP |
6549 | return false; |
6550 | return true; | |
6551 | } | |
6552 | ||
8e7aa1f9 MM |
6553 | /* Generate insns for a VEC_COND_EXPR, given its TYPE and its |
6554 | three operands. */ | |
7ce67fbe DP |
6555 | |
6556 | rtx | |
8e7aa1f9 MM |
6557 | expand_vec_cond_expr (tree vec_cond_type, tree op0, tree op1, tree op2, |
6558 | rtx target) | |
7ce67fbe | 6559 | { |
a5c7d693 | 6560 | struct expand_operand ops[6]; |
7ce67fbe | 6561 | enum insn_code icode; |
a5c7d693 | 6562 | rtx comparison, rtx_op1, rtx_op2; |
8e7aa1f9 MM |
6563 | enum machine_mode mode = TYPE_MODE (vec_cond_type); |
6564 | bool unsignedp = TYPE_UNSIGNED (vec_cond_type); | |
7ce67fbe | 6565 | |
8e7aa1f9 | 6566 | icode = get_vcond_icode (vec_cond_type, mode); |
7ce67fbe DP |
6567 | if (icode == CODE_FOR_nothing) |
6568 | return 0; | |
6569 | ||
a5c7d693 | 6570 | comparison = vector_compare_rtx (op0, unsignedp, icode); |
8e7aa1f9 | 6571 | rtx_op1 = expand_normal (op1); |
8e7aa1f9 | 6572 | rtx_op2 = expand_normal (op2); |
7ce67fbe | 6573 | |
a5c7d693 RS |
6574 | create_output_operand (&ops[0], target, mode); |
6575 | create_input_operand (&ops[1], rtx_op1, mode); | |
6576 | create_input_operand (&ops[2], rtx_op2, mode); | |
6577 | create_fixed_operand (&ops[3], comparison); | |
6578 | create_fixed_operand (&ops[4], XEXP (comparison, 0)); | |
6579 | create_fixed_operand (&ops[5], XEXP (comparison, 1)); | |
6580 | expand_insn (icode, 6, ops); | |
6581 | return ops[0].value; | |
7ce67fbe | 6582 | } |
48ae6c13 RH |
6583 | |
6584 | \f | |
6585 | /* This is an internal subroutine of the other compare_and_swap expanders. | |
6586 | MEM, OLD_VAL and NEW_VAL are as you'd expect for a compare-and-swap | |
6587 | operation. TARGET is an optional place to store the value result of | |
6588 | the operation. ICODE is the particular instruction to expand. Return | |
6589 | the result of the operation. */ | |
6590 | ||
6591 | static rtx | |
6592 | expand_val_compare_and_swap_1 (rtx mem, rtx old_val, rtx new_val, | |
6593 | rtx target, enum insn_code icode) | |
6594 | { | |
a5c7d693 | 6595 | struct expand_operand ops[4]; |
48ae6c13 | 6596 | enum machine_mode mode = GET_MODE (mem); |
48ae6c13 | 6597 | |
a5c7d693 RS |
6598 | create_output_operand (&ops[0], target, mode); |
6599 | create_fixed_operand (&ops[1], mem); | |
6600 | /* OLD_VAL and NEW_VAL may have been promoted to a wider mode. | |
6601 | Shrink them if so. */ | |
6602 | create_convert_operand_to (&ops[2], old_val, mode, true); | |
6603 | create_convert_operand_to (&ops[3], new_val, mode, true); | |
6604 | if (maybe_expand_insn (icode, 4, ops)) | |
6605 | return ops[0].value; | |
6606 | return NULL_RTX; | |
48ae6c13 RH |
6607 | } |
6608 | ||
6609 | /* Expand a compare-and-swap operation and return its value. */ | |
6610 | ||
6611 | rtx | |
6612 | expand_val_compare_and_swap (rtx mem, rtx old_val, rtx new_val, rtx target) | |
6613 | { | |
6614 | enum machine_mode mode = GET_MODE (mem); | |
f9621cc4 RS |
6615 | enum insn_code icode |
6616 | = direct_optab_handler (sync_compare_and_swap_optab, mode); | |
48ae6c13 RH |
6617 | |
6618 | if (icode == CODE_FOR_nothing) | |
6619 | return NULL_RTX; | |
6620 | ||
6621 | return expand_val_compare_and_swap_1 (mem, old_val, new_val, target, icode); | |
6622 | } | |
6623 | ||
4a77c72b PB |
6624 | /* Helper function to find the MODE_CC set in a sync_compare_and_swap |
6625 | pattern. */ | |
6626 | ||
6627 | static void | |
6628 | find_cc_set (rtx x, const_rtx pat, void *data) | |
6629 | { | |
6630 | if (REG_P (x) && GET_MODE_CLASS (GET_MODE (x)) == MODE_CC | |
6631 | && GET_CODE (pat) == SET) | |
6632 | { | |
6633 | rtx *p_cc_reg = (rtx *) data; | |
6634 | gcc_assert (!*p_cc_reg); | |
6635 | *p_cc_reg = x; | |
6636 | } | |
6637 | } | |
6638 | ||
48ae6c13 RH |
6639 | /* Expand a compare-and-swap operation and store true into the result if |
6640 | the operation was successful and false otherwise. Return the result. | |
6641 | Unlike other routines, TARGET is not optional. */ | |
6642 | ||
6643 | rtx | |
6644 | expand_bool_compare_and_swap (rtx mem, rtx old_val, rtx new_val, rtx target) | |
6645 | { | |
6646 | enum machine_mode mode = GET_MODE (mem); | |
6647 | enum insn_code icode; | |
4a77c72b | 6648 | rtx subtarget, seq, cc_reg; |
48ae6c13 RH |
6649 | |
6650 | /* If the target supports a compare-and-swap pattern that simultaneously | |
6651 | sets some flag for success, then use it. Otherwise use the regular | |
6652 | compare-and-swap and follow that immediately with a compare insn. */ | |
f9621cc4 | 6653 | icode = direct_optab_handler (sync_compare_and_swap_optab, mode); |
4a77c72b PB |
6654 | if (icode == CODE_FOR_nothing) |
6655 | return NULL_RTX; | |
f12b785d | 6656 | |
e5f5fa2d | 6657 | do_pending_stack_adjust (); |
4a77c72b PB |
6658 | do |
6659 | { | |
6660 | start_sequence (); | |
48ae6c13 | 6661 | subtarget = expand_val_compare_and_swap_1 (mem, old_val, new_val, |
4a77c72b PB |
6662 | NULL_RTX, icode); |
6663 | cc_reg = NULL_RTX; | |
48ae6c13 | 6664 | if (subtarget == NULL_RTX) |
48ae6c13 | 6665 | { |
4a77c72b PB |
6666 | end_sequence (); |
6667 | return NULL_RTX; | |
48ae6c13 | 6668 | } |
48ae6c13 | 6669 | |
4a77c72b PB |
6670 | if (have_insn_for (COMPARE, CCmode)) |
6671 | note_stores (PATTERN (get_last_insn ()), find_cc_set, &cc_reg); | |
6672 | seq = get_insns (); | |
6673 | end_sequence (); | |
48ae6c13 | 6674 | |
4a77c72b PB |
6675 | /* We might be comparing against an old value. Try again. :-( */ |
6676 | if (!cc_reg && MEM_P (old_val)) | |
6677 | { | |
6678 | seq = NULL_RTX; | |
6679 | old_val = force_reg (mode, old_val); | |
6680 | } | |
6681 | } | |
6682 | while (!seq); | |
48ae6c13 | 6683 | |
4a77c72b PB |
6684 | emit_insn (seq); |
6685 | if (cc_reg) | |
f90b7a5a | 6686 | return emit_store_flag_force (target, EQ, cc_reg, const0_rtx, VOIDmode, 0, 1); |
4a77c72b | 6687 | else |
f90b7a5a | 6688 | return emit_store_flag_force (target, EQ, subtarget, old_val, VOIDmode, 1, 1); |
48ae6c13 RH |
6689 | } |
6690 | ||
6691 | /* This is a helper function for the other atomic operations. This function | |
6692 | emits a loop that contains SEQ that iterates until a compare-and-swap | |
6693 | operation at the end succeeds. MEM is the memory to be modified. SEQ is | |
6694 | a set of instructions that takes a value from OLD_REG as an input and | |
6695 | produces a value in NEW_REG as an output. Before SEQ, OLD_REG will be | |
6696 | set to the current contents of MEM. After SEQ, a compare-and-swap will | |
6697 | attempt to update MEM with NEW_REG. The function returns true when the | |
6698 | loop was generated successfully. */ | |
6699 | ||
6700 | static bool | |
6701 | expand_compare_and_swap_loop (rtx mem, rtx old_reg, rtx new_reg, rtx seq) | |
6702 | { | |
6703 | enum machine_mode mode = GET_MODE (mem); | |
6704 | enum insn_code icode; | |
4a77c72b | 6705 | rtx label, cmp_reg, subtarget, cc_reg; |
48ae6c13 RH |
6706 | |
6707 | /* The loop we want to generate looks like | |
6708 | ||
81ba4f39 | 6709 | cmp_reg = mem; |
48ae6c13 | 6710 | label: |
81ba4f39 | 6711 | old_reg = cmp_reg; |
48ae6c13 | 6712 | seq; |
81ba4f39 RH |
6713 | cmp_reg = compare-and-swap(mem, old_reg, new_reg) |
6714 | if (cmp_reg != old_reg) | |
48ae6c13 RH |
6715 | goto label; |
6716 | ||
6717 | Note that we only do the plain load from memory once. Subsequent | |
6718 | iterations use the value loaded by the compare-and-swap pattern. */ | |
6719 | ||
6720 | label = gen_label_rtx (); | |
81ba4f39 | 6721 | cmp_reg = gen_reg_rtx (mode); |
48ae6c13 | 6722 | |
81ba4f39 | 6723 | emit_move_insn (cmp_reg, mem); |
48ae6c13 | 6724 | emit_label (label); |
81ba4f39 | 6725 | emit_move_insn (old_reg, cmp_reg); |
48ae6c13 RH |
6726 | if (seq) |
6727 | emit_insn (seq); | |
6728 | ||
6729 | /* If the target supports a compare-and-swap pattern that simultaneously | |
6730 | sets some flag for success, then use it. Otherwise use the regular | |
6731 | compare-and-swap and follow that immediately with a compare insn. */ | |
f9621cc4 | 6732 | icode = direct_optab_handler (sync_compare_and_swap_optab, mode); |
4a77c72b PB |
6733 | if (icode == CODE_FOR_nothing) |
6734 | return false; | |
48ae6c13 | 6735 | |
4a77c72b PB |
6736 | subtarget = expand_val_compare_and_swap_1 (mem, old_reg, new_reg, |
6737 | cmp_reg, icode); | |
6738 | if (subtarget == NULL_RTX) | |
6739 | return false; | |
48ae6c13 | 6740 | |
4a77c72b PB |
6741 | cc_reg = NULL_RTX; |
6742 | if (have_insn_for (COMPARE, CCmode)) | |
6743 | note_stores (PATTERN (get_last_insn ()), find_cc_set, &cc_reg); | |
6744 | if (cc_reg) | |
6745 | { | |
6746 | cmp_reg = cc_reg; | |
6747 | old_reg = const0_rtx; | |
6748 | } | |
6749 | else | |
6750 | { | |
81ba4f39 RH |
6751 | if (subtarget != cmp_reg) |
6752 | emit_move_insn (cmp_reg, subtarget); | |
48ae6c13 RH |
6753 | } |
6754 | ||
6755 | /* ??? Mark this jump predicted not taken? */ | |
4a77c72b PB |
6756 | emit_cmp_and_jump_insns (cmp_reg, old_reg, NE, const0_rtx, GET_MODE (cmp_reg), 1, |
6757 | label); | |
48ae6c13 RH |
6758 | return true; |
6759 | } | |
6760 | ||
6761 | /* This function generates the atomic operation MEM CODE= VAL. In this | |
c414ac1d | 6762 | case, we do not care about any resulting value. Returns NULL if we |
48ae6c13 RH |
6763 | cannot generate the operation. */ |
6764 | ||
6765 | rtx | |
6766 | expand_sync_operation (rtx mem, rtx val, enum rtx_code code) | |
6767 | { | |
6768 | enum machine_mode mode = GET_MODE (mem); | |
6769 | enum insn_code icode; | |
6770 | rtx insn; | |
6771 | ||
6772 | /* Look to see if the target supports the operation directly. */ | |
6773 | switch (code) | |
6774 | { | |
6775 | case PLUS: | |
f9621cc4 | 6776 | icode = direct_optab_handler (sync_add_optab, mode); |
48ae6c13 RH |
6777 | break; |
6778 | case IOR: | |
f9621cc4 | 6779 | icode = direct_optab_handler (sync_ior_optab, mode); |
48ae6c13 RH |
6780 | break; |
6781 | case XOR: | |
f9621cc4 | 6782 | icode = direct_optab_handler (sync_xor_optab, mode); |
48ae6c13 RH |
6783 | break; |
6784 | case AND: | |
f9621cc4 | 6785 | icode = direct_optab_handler (sync_and_optab, mode); |
48ae6c13 | 6786 | break; |
f12b785d | 6787 | case NOT: |
f9621cc4 | 6788 | icode = direct_optab_handler (sync_nand_optab, mode); |
f12b785d | 6789 | break; |
48ae6c13 RH |
6790 | |
6791 | case MINUS: | |
f9621cc4 | 6792 | icode = direct_optab_handler (sync_sub_optab, mode); |
3b010fe3 | 6793 | if (icode == CODE_FOR_nothing || CONST_INT_P (val)) |
48ae6c13 | 6794 | { |
f9621cc4 | 6795 | icode = direct_optab_handler (sync_add_optab, mode); |
48ae6c13 RH |
6796 | if (icode != CODE_FOR_nothing) |
6797 | { | |
6798 | val = expand_simple_unop (mode, NEG, val, NULL_RTX, 1); | |
6799 | code = PLUS; | |
6800 | } | |
6801 | } | |
6802 | break; | |
6803 | ||
48ae6c13 RH |
6804 | default: |
6805 | gcc_unreachable (); | |
6806 | } | |
6807 | ||
6808 | /* Generate the direct operation, if present. */ | |
6809 | if (icode != CODE_FOR_nothing) | |
6810 | { | |
a5c7d693 | 6811 | struct expand_operand ops[2]; |
c414ac1d | 6812 | |
a5c7d693 RS |
6813 | create_fixed_operand (&ops[0], mem); |
6814 | /* VAL may have been promoted to a wider mode. Shrink it if so. */ | |
6815 | create_convert_operand_to (&ops[1], val, mode, true); | |
6816 | if (maybe_expand_insn (icode, 2, ops)) | |
6817 | return const0_rtx; | |
48ae6c13 RH |
6818 | } |
6819 | ||
6820 | /* Failing that, generate a compare-and-swap loop in which we perform the | |
6821 | operation with normal arithmetic instructions. */ | |
f9621cc4 RS |
6822 | if (direct_optab_handler (sync_compare_and_swap_optab, mode) |
6823 | != CODE_FOR_nothing) | |
48ae6c13 RH |
6824 | { |
6825 | rtx t0 = gen_reg_rtx (mode), t1; | |
6826 | ||
6827 | start_sequence (); | |
6828 | ||
f12b785d | 6829 | t1 = t0; |
48ae6c13 RH |
6830 | if (code == NOT) |
6831 | { | |
23462d4d UB |
6832 | t1 = expand_simple_binop (mode, AND, t1, val, NULL_RTX, |
6833 | true, OPTAB_LIB_WIDEN); | |
6834 | t1 = expand_simple_unop (mode, code, t1, NULL_RTX, true); | |
48ae6c13 | 6835 | } |
23462d4d UB |
6836 | else |
6837 | t1 = expand_simple_binop (mode, code, t1, val, NULL_RTX, | |
6838 | true, OPTAB_LIB_WIDEN); | |
48ae6c13 RH |
6839 | insn = get_insns (); |
6840 | end_sequence (); | |
6841 | ||
6842 | if (t1 != NULL && expand_compare_and_swap_loop (mem, t0, t1, insn)) | |
6843 | return const0_rtx; | |
6844 | } | |
6845 | ||
6846 | return NULL_RTX; | |
6847 | } | |
6848 | ||
6849 | /* This function generates the atomic operation MEM CODE= VAL. In this | |
6850 | case, we do care about the resulting value: if AFTER is true then | |
c414ac1d | 6851 | return the value MEM holds after the operation, if AFTER is false |
48ae6c13 RH |
6852 | then return the value MEM holds before the operation. TARGET is an |
6853 | optional place for the result value to be stored. */ | |
6854 | ||
6855 | rtx | |
6856 | expand_sync_fetch_operation (rtx mem, rtx val, enum rtx_code code, | |
6857 | bool after, rtx target) | |
6858 | { | |
6859 | enum machine_mode mode = GET_MODE (mem); | |
6860 | enum insn_code old_code, new_code, icode; | |
6861 | bool compensate; | |
6862 | rtx insn; | |
6863 | ||
6864 | /* Look to see if the target supports the operation directly. */ | |
6865 | switch (code) | |
6866 | { | |
6867 | case PLUS: | |
f9621cc4 RS |
6868 | old_code = direct_optab_handler (sync_old_add_optab, mode); |
6869 | new_code = direct_optab_handler (sync_new_add_optab, mode); | |
48ae6c13 RH |
6870 | break; |
6871 | case IOR: | |
f9621cc4 RS |
6872 | old_code = direct_optab_handler (sync_old_ior_optab, mode); |
6873 | new_code = direct_optab_handler (sync_new_ior_optab, mode); | |
48ae6c13 RH |
6874 | break; |
6875 | case XOR: | |
f9621cc4 RS |
6876 | old_code = direct_optab_handler (sync_old_xor_optab, mode); |
6877 | new_code = direct_optab_handler (sync_new_xor_optab, mode); | |
48ae6c13 RH |
6878 | break; |
6879 | case AND: | |
f9621cc4 RS |
6880 | old_code = direct_optab_handler (sync_old_and_optab, mode); |
6881 | new_code = direct_optab_handler (sync_new_and_optab, mode); | |
48ae6c13 | 6882 | break; |
f12b785d | 6883 | case NOT: |
f9621cc4 RS |
6884 | old_code = direct_optab_handler (sync_old_nand_optab, mode); |
6885 | new_code = direct_optab_handler (sync_new_nand_optab, mode); | |
f12b785d | 6886 | break; |
48ae6c13 RH |
6887 | |
6888 | case MINUS: | |
f9621cc4 RS |
6889 | old_code = direct_optab_handler (sync_old_sub_optab, mode); |
6890 | new_code = direct_optab_handler (sync_new_sub_optab, mode); | |
3b010fe3 DD |
6891 | if ((old_code == CODE_FOR_nothing && new_code == CODE_FOR_nothing) |
6892 | || CONST_INT_P (val)) | |
48ae6c13 | 6893 | { |
f9621cc4 RS |
6894 | old_code = direct_optab_handler (sync_old_add_optab, mode); |
6895 | new_code = direct_optab_handler (sync_new_add_optab, mode); | |
48ae6c13 RH |
6896 | if (old_code != CODE_FOR_nothing || new_code != CODE_FOR_nothing) |
6897 | { | |
6898 | val = expand_simple_unop (mode, NEG, val, NULL_RTX, 1); | |
6899 | code = PLUS; | |
6900 | } | |
6901 | } | |
6902 | break; | |
6903 | ||
48ae6c13 RH |
6904 | default: |
6905 | gcc_unreachable (); | |
6906 | } | |
6907 | ||
6908 | /* If the target does supports the proper new/old operation, great. But | |
6909 | if we only support the opposite old/new operation, check to see if we | |
6910 | can compensate. In the case in which the old value is supported, then | |
6911 | we can always perform the operation again with normal arithmetic. In | |
6912 | the case in which the new value is supported, then we can only handle | |
6913 | this in the case the operation is reversible. */ | |
6914 | compensate = false; | |
6915 | if (after) | |
6916 | { | |
6917 | icode = new_code; | |
6918 | if (icode == CODE_FOR_nothing) | |
6919 | { | |
6920 | icode = old_code; | |
6921 | if (icode != CODE_FOR_nothing) | |
6922 | compensate = true; | |
6923 | } | |
6924 | } | |
6925 | else | |
6926 | { | |
6927 | icode = old_code; | |
6928 | if (icode == CODE_FOR_nothing | |
6929 | && (code == PLUS || code == MINUS || code == XOR)) | |
6930 | { | |
6931 | icode = new_code; | |
6932 | if (icode != CODE_FOR_nothing) | |
6933 | compensate = true; | |
6934 | } | |
6935 | } | |
6936 | ||
6937 | /* If we found something supported, great. */ | |
6938 | if (icode != CODE_FOR_nothing) | |
6939 | { | |
a5c7d693 | 6940 | struct expand_operand ops[3]; |
48ae6c13 | 6941 | |
a5c7d693 RS |
6942 | create_output_operand (&ops[0], target, mode); |
6943 | create_fixed_operand (&ops[1], mem); | |
6944 | /* VAL may have been promoted to a wider mode. Shrink it if so. */ | |
6945 | create_convert_operand_to (&ops[2], val, mode, true); | |
6946 | if (maybe_expand_insn (icode, 3, ops)) | |
48ae6c13 | 6947 | { |
a5c7d693 RS |
6948 | target = ops[0].value; |
6949 | val = ops[2].value; | |
48ae6c13 RH |
6950 | /* If we need to compensate for using an operation with the |
6951 | wrong return value, do so now. */ | |
6952 | if (compensate) | |
6953 | { | |
6954 | if (!after) | |
6955 | { | |
6956 | if (code == PLUS) | |
6957 | code = MINUS; | |
6958 | else if (code == MINUS) | |
6959 | code = PLUS; | |
6960 | } | |
f12b785d RH |
6961 | |
6962 | if (code == NOT) | |
23462d4d UB |
6963 | { |
6964 | target = expand_simple_binop (mode, AND, target, val, | |
6965 | NULL_RTX, true, | |
6966 | OPTAB_LIB_WIDEN); | |
6967 | target = expand_simple_unop (mode, code, target, | |
6968 | NULL_RTX, true); | |
6969 | } | |
6970 | else | |
6971 | target = expand_simple_binop (mode, code, target, val, | |
6972 | NULL_RTX, true, | |
6973 | OPTAB_LIB_WIDEN); | |
48ae6c13 RH |
6974 | } |
6975 | ||
6976 | return target; | |
6977 | } | |
6978 | } | |
6979 | ||
6980 | /* Failing that, generate a compare-and-swap loop in which we perform the | |
6981 | operation with normal arithmetic instructions. */ | |
f9621cc4 RS |
6982 | if (direct_optab_handler (sync_compare_and_swap_optab, mode) |
6983 | != CODE_FOR_nothing) | |
48ae6c13 RH |
6984 | { |
6985 | rtx t0 = gen_reg_rtx (mode), t1; | |
6986 | ||
6987 | if (!target || !register_operand (target, mode)) | |
6988 | target = gen_reg_rtx (mode); | |
6989 | ||
6990 | start_sequence (); | |
6991 | ||
f12b785d RH |
6992 | if (!after) |
6993 | emit_move_insn (target, t0); | |
6994 | t1 = t0; | |
48ae6c13 RH |
6995 | if (code == NOT) |
6996 | { | |
23462d4d UB |
6997 | t1 = expand_simple_binop (mode, AND, t1, val, NULL_RTX, |
6998 | true, OPTAB_LIB_WIDEN); | |
6999 | t1 = expand_simple_unop (mode, code, t1, NULL_RTX, true); | |
48ae6c13 | 7000 | } |
23462d4d UB |
7001 | else |
7002 | t1 = expand_simple_binop (mode, code, t1, val, NULL_RTX, | |
7003 | true, OPTAB_LIB_WIDEN); | |
48ae6c13 RH |
7004 | if (after) |
7005 | emit_move_insn (target, t1); | |
7006 | ||
7007 | insn = get_insns (); | |
7008 | end_sequence (); | |
7009 | ||
7010 | if (t1 != NULL && expand_compare_and_swap_loop (mem, t0, t1, insn)) | |
7011 | return target; | |
7012 | } | |
7013 | ||
7014 | return NULL_RTX; | |
7015 | } | |
7016 | ||
7017 | /* This function expands a test-and-set operation. Ideally we atomically | |
7018 | store VAL in MEM and return the previous value in MEM. Some targets | |
7019 | may not support this operation and only support VAL with the constant 1; | |
c414ac1d | 7020 | in this case while the return value will be 0/1, but the exact value |
48ae6c13 RH |
7021 | stored in MEM is target defined. TARGET is an option place to stick |
7022 | the return value. */ | |
7023 | ||
7024 | rtx | |
7025 | expand_sync_lock_test_and_set (rtx mem, rtx val, rtx target) | |
7026 | { | |
7027 | enum machine_mode mode = GET_MODE (mem); | |
7028 | enum insn_code icode; | |
48ae6c13 RH |
7029 | |
7030 | /* If the target supports the test-and-set directly, great. */ | |
f9621cc4 | 7031 | icode = direct_optab_handler (sync_lock_test_and_set_optab, mode); |
48ae6c13 RH |
7032 | if (icode != CODE_FOR_nothing) |
7033 | { | |
a5c7d693 | 7034 | struct expand_operand ops[3]; |
48ae6c13 | 7035 | |
a5c7d693 RS |
7036 | create_output_operand (&ops[0], target, mode); |
7037 | create_fixed_operand (&ops[1], mem); | |
7038 | /* VAL may have been promoted to a wider mode. Shrink it if so. */ | |
7039 | create_convert_operand_to (&ops[2], val, mode, true); | |
7040 | if (maybe_expand_insn (icode, 3, ops)) | |
7041 | return ops[0].value; | |
48ae6c13 RH |
7042 | } |
7043 | ||
7044 | /* Otherwise, use a compare-and-swap loop for the exchange. */ | |
f9621cc4 RS |
7045 | if (direct_optab_handler (sync_compare_and_swap_optab, mode) |
7046 | != CODE_FOR_nothing) | |
48ae6c13 RH |
7047 | { |
7048 | if (!target || !register_operand (target, mode)) | |
7049 | target = gen_reg_rtx (mode); | |
7050 | if (GET_MODE (val) != VOIDmode && GET_MODE (val) != mode) | |
7051 | val = convert_modes (mode, GET_MODE (val), val, 1); | |
7052 | if (expand_compare_and_swap_loop (mem, target, val, NULL_RTX)) | |
7053 | return target; | |
7054 | } | |
7055 | ||
7056 | return NULL_RTX; | |
7057 | } | |
2ef6ce06 RS |
7058 | \f |
7059 | /* Return true if OPERAND is suitable for operand number OPNO of | |
7060 | instruction ICODE. */ | |
7061 | ||
7062 | bool | |
7063 | insn_operand_matches (enum insn_code icode, unsigned int opno, rtx operand) | |
7064 | { | |
7065 | return (!insn_data[(int) icode].operand[opno].predicate | |
7066 | || (insn_data[(int) icode].operand[opno].predicate | |
7067 | (operand, insn_data[(int) icode].operand[opno].mode))); | |
7068 | } | |
a5c7d693 | 7069 | \f |
02972eaf RS |
7070 | /* TARGET is a target of a multiword operation that we are going to |
7071 | implement as a series of word-mode operations. Return true if | |
7072 | TARGET is suitable for this purpose. */ | |
7073 | ||
7074 | bool | |
7075 | valid_multiword_target_p (rtx target) | |
7076 | { | |
7077 | enum machine_mode mode; | |
7078 | int i; | |
7079 | ||
7080 | mode = GET_MODE (target); | |
7081 | for (i = 0; i < GET_MODE_SIZE (mode); i += UNITS_PER_WORD) | |
7082 | if (!validate_subreg (word_mode, mode, target, i)) | |
7083 | return false; | |
7084 | return true; | |
7085 | } | |
7086 | ||
4fd3a105 RS |
7087 | /* Like maybe_legitimize_operand, but do not change the code of the |
7088 | current rtx value. */ | |
7089 | ||
7090 | static bool | |
7091 | maybe_legitimize_operand_same_code (enum insn_code icode, unsigned int opno, | |
7092 | struct expand_operand *op) | |
7093 | { | |
7094 | /* See if the operand matches in its current form. */ | |
7095 | if (insn_operand_matches (icode, opno, op->value)) | |
7096 | return true; | |
7097 | ||
7098 | /* If the operand is a memory whose address has no side effects, | |
7099 | try forcing the address into a register. The check for side | |
7100 | effects is important because force_reg cannot handle things | |
7101 | like auto-modified addresses. */ | |
7102 | if (insn_data[(int) icode].operand[opno].allows_mem | |
7103 | && MEM_P (op->value) | |
7104 | && !side_effects_p (XEXP (op->value, 0))) | |
7105 | { | |
7106 | rtx addr, mem, last; | |
7107 | ||
7108 | last = get_last_insn (); | |
7109 | addr = force_reg (Pmode, XEXP (op->value, 0)); | |
7110 | mem = replace_equiv_address (op->value, addr); | |
7111 | if (insn_operand_matches (icode, opno, mem)) | |
7112 | { | |
7113 | op->value = mem; | |
7114 | return true; | |
7115 | } | |
7116 | delete_insns_since (last); | |
7117 | } | |
7118 | ||
7119 | return false; | |
7120 | } | |
7121 | ||
a5c7d693 RS |
7122 | /* Try to make OP match operand OPNO of instruction ICODE. Return true |
7123 | on success, storing the new operand value back in OP. */ | |
7124 | ||
7125 | static bool | |
7126 | maybe_legitimize_operand (enum insn_code icode, unsigned int opno, | |
7127 | struct expand_operand *op) | |
7128 | { | |
7129 | enum machine_mode mode, imode; | |
7130 | bool old_volatile_ok, result; | |
7131 | ||
a5c7d693 | 7132 | mode = op->mode; |
a5c7d693 RS |
7133 | switch (op->type) |
7134 | { | |
7135 | case EXPAND_FIXED: | |
4fd3a105 | 7136 | old_volatile_ok = volatile_ok; |
a5c7d693 | 7137 | volatile_ok = true; |
4fd3a105 RS |
7138 | result = maybe_legitimize_operand_same_code (icode, opno, op); |
7139 | volatile_ok = old_volatile_ok; | |
7140 | return result; | |
a5c7d693 RS |
7141 | |
7142 | case EXPAND_OUTPUT: | |
7143 | gcc_assert (mode != VOIDmode); | |
4fd3a105 RS |
7144 | if (op->value |
7145 | && op->value != const0_rtx | |
7146 | && GET_MODE (op->value) == mode | |
7147 | && maybe_legitimize_operand_same_code (icode, opno, op)) | |
7148 | return true; | |
7149 | ||
7150 | op->value = gen_reg_rtx (mode); | |
a5c7d693 RS |
7151 | break; |
7152 | ||
7153 | case EXPAND_INPUT: | |
7154 | input: | |
7155 | gcc_assert (mode != VOIDmode); | |
7156 | gcc_assert (GET_MODE (op->value) == VOIDmode | |
7157 | || GET_MODE (op->value) == mode); | |
4fd3a105 RS |
7158 | if (maybe_legitimize_operand_same_code (icode, opno, op)) |
7159 | return true; | |
7160 | ||
7161 | op->value = copy_to_mode_reg (mode, op->value); | |
a5c7d693 RS |
7162 | break; |
7163 | ||
7164 | case EXPAND_CONVERT_TO: | |
7165 | gcc_assert (mode != VOIDmode); | |
7166 | op->value = convert_to_mode (mode, op->value, op->unsigned_p); | |
7167 | goto input; | |
7168 | ||
7169 | case EXPAND_CONVERT_FROM: | |
7170 | if (GET_MODE (op->value) != VOIDmode) | |
7171 | mode = GET_MODE (op->value); | |
7172 | else | |
7173 | /* The caller must tell us what mode this value has. */ | |
7174 | gcc_assert (mode != VOIDmode); | |
7175 | ||
7176 | imode = insn_data[(int) icode].operand[opno].mode; | |
7177 | if (imode != VOIDmode && imode != mode) | |
7178 | { | |
7179 | op->value = convert_modes (imode, mode, op->value, op->unsigned_p); | |
7180 | mode = imode; | |
7181 | } | |
7182 | goto input; | |
7183 | ||
7184 | case EXPAND_ADDRESS: | |
7185 | gcc_assert (mode != VOIDmode); | |
7186 | op->value = convert_memory_address (mode, op->value); | |
7187 | goto input; | |
7188 | ||
7189 | case EXPAND_INTEGER: | |
7190 | mode = insn_data[(int) icode].operand[opno].mode; | |
7191 | if (mode != VOIDmode && const_int_operand (op->value, mode)) | |
7192 | goto input; | |
7193 | break; | |
7194 | } | |
4fd3a105 | 7195 | return insn_operand_matches (icode, opno, op->value); |
a5c7d693 RS |
7196 | } |
7197 | ||
7198 | /* Make OP describe an input operand that should have the same value | |
7199 | as VALUE, after any mode conversion that the target might request. | |
7200 | TYPE is the type of VALUE. */ | |
7201 | ||
7202 | void | |
7203 | create_convert_operand_from_type (struct expand_operand *op, | |
7204 | rtx value, tree type) | |
7205 | { | |
7206 | create_convert_operand_from (op, value, TYPE_MODE (type), | |
7207 | TYPE_UNSIGNED (type)); | |
7208 | } | |
7209 | ||
7210 | /* Try to make operands [OPS, OPS + NOPS) match operands [OPNO, OPNO + NOPS) | |
7211 | of instruction ICODE. Return true on success, leaving the new operand | |
7212 | values in the OPS themselves. Emit no code on failure. */ | |
7213 | ||
7214 | bool | |
7215 | maybe_legitimize_operands (enum insn_code icode, unsigned int opno, | |
7216 | unsigned int nops, struct expand_operand *ops) | |
7217 | { | |
7218 | rtx last; | |
7219 | unsigned int i; | |
7220 | ||
7221 | last = get_last_insn (); | |
7222 | for (i = 0; i < nops; i++) | |
7223 | if (!maybe_legitimize_operand (icode, opno + i, &ops[i])) | |
7224 | { | |
7225 | delete_insns_since (last); | |
7226 | return false; | |
7227 | } | |
7228 | return true; | |
7229 | } | |
7230 | ||
7231 | /* Try to generate instruction ICODE, using operands [OPS, OPS + NOPS) | |
7232 | as its operands. Return the instruction pattern on success, | |
7233 | and emit any necessary set-up code. Return null and emit no | |
7234 | code on failure. */ | |
7235 | ||
7236 | rtx | |
7237 | maybe_gen_insn (enum insn_code icode, unsigned int nops, | |
7238 | struct expand_operand *ops) | |
7239 | { | |
f04713ee | 7240 | gcc_assert (nops == (unsigned int) insn_data[(int) icode].n_generator_args); |
a5c7d693 RS |
7241 | if (!maybe_legitimize_operands (icode, 0, nops, ops)) |
7242 | return NULL_RTX; | |
7243 | ||
7244 | switch (nops) | |
7245 | { | |
7246 | case 1: | |
7247 | return GEN_FCN (icode) (ops[0].value); | |
7248 | case 2: | |
7249 | return GEN_FCN (icode) (ops[0].value, ops[1].value); | |
7250 | case 3: | |
7251 | return GEN_FCN (icode) (ops[0].value, ops[1].value, ops[2].value); | |
7252 | case 4: | |
7253 | return GEN_FCN (icode) (ops[0].value, ops[1].value, ops[2].value, | |
7254 | ops[3].value); | |
7255 | case 5: | |
7256 | return GEN_FCN (icode) (ops[0].value, ops[1].value, ops[2].value, | |
7257 | ops[3].value, ops[4].value); | |
7258 | case 6: | |
7259 | return GEN_FCN (icode) (ops[0].value, ops[1].value, ops[2].value, | |
7260 | ops[3].value, ops[4].value, ops[5].value); | |
7261 | } | |
7262 | gcc_unreachable (); | |
7263 | } | |
7264 | ||
7265 | /* Try to emit instruction ICODE, using operands [OPS, OPS + NOPS) | |
7266 | as its operands. Return true on success and emit no code on failure. */ | |
7267 | ||
7268 | bool | |
7269 | maybe_expand_insn (enum insn_code icode, unsigned int nops, | |
7270 | struct expand_operand *ops) | |
7271 | { | |
7272 | rtx pat = maybe_gen_insn (icode, nops, ops); | |
7273 | if (pat) | |
7274 | { | |
7275 | emit_insn (pat); | |
7276 | return true; | |
7277 | } | |
7278 | return false; | |
7279 | } | |
7280 | ||
7281 | /* Like maybe_expand_insn, but for jumps. */ | |
7282 | ||
7283 | bool | |
7284 | maybe_expand_jump_insn (enum insn_code icode, unsigned int nops, | |
7285 | struct expand_operand *ops) | |
7286 | { | |
7287 | rtx pat = maybe_gen_insn (icode, nops, ops); | |
7288 | if (pat) | |
7289 | { | |
7290 | emit_jump_insn (pat); | |
7291 | return true; | |
7292 | } | |
7293 | return false; | |
7294 | } | |
7295 | ||
7296 | /* Emit instruction ICODE, using operands [OPS, OPS + NOPS) | |
7297 | as its operands. */ | |
7298 | ||
7299 | void | |
7300 | expand_insn (enum insn_code icode, unsigned int nops, | |
7301 | struct expand_operand *ops) | |
7302 | { | |
7303 | if (!maybe_expand_insn (icode, nops, ops)) | |
7304 | gcc_unreachable (); | |
7305 | } | |
7306 | ||
7307 | /* Like expand_insn, but for jumps. */ | |
7308 | ||
7309 | void | |
7310 | expand_jump_insn (enum insn_code icode, unsigned int nops, | |
7311 | struct expand_operand *ops) | |
7312 | { | |
7313 | if (!maybe_expand_jump_insn (icode, nops, ops)) | |
7314 | gcc_unreachable (); | |
7315 | } | |
48ae6c13 | 7316 | |
e2500fed | 7317 | #include "gt-optabs.h" |