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77c9c6c2 | 1 | /* Expand the basic unary and binary arithmetic operations, for GNU compiler. |
d050d723 | 2 | Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
d9221e01 | 3 | 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. |
77c9c6c2 | 4 | |
1322177d | 5 | This file is part of GCC. |
77c9c6c2 | 6 | |
1322177d LB |
7 | GCC is free software; you can redistribute it and/or modify it under |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 2, or (at your option) any later | |
10 | version. | |
77c9c6c2 | 11 | |
1322177d LB |
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
77c9c6c2 RK |
16 | |
17 | You should have received a copy of the GNU General Public License | |
1322177d LB |
18 | along with GCC; see the file COPYING. If not, write to the Free |
19 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
20 | 02111-1307, USA. */ | |
77c9c6c2 RK |
21 | |
22 | ||
23 | #include "config.h" | |
670ee920 | 24 | #include "system.h" |
4977bab6 ZW |
25 | #include "coretypes.h" |
26 | #include "tm.h" | |
01198c2f | 27 | #include "toplev.h" |
dff01034 KG |
28 | |
29 | /* Include insn-config.h before expr.h so that HAVE_conditional_move | |
dc297297 | 30 | is properly defined. */ |
dff01034 | 31 | #include "insn-config.h" |
77c9c6c2 RK |
32 | #include "rtl.h" |
33 | #include "tree.h" | |
6baf1cc8 | 34 | #include "tm_p.h" |
77c9c6c2 | 35 | #include "flags.h" |
49ad7cfa | 36 | #include "function.h" |
52a11cbf | 37 | #include "except.h" |
77c9c6c2 | 38 | #include "expr.h" |
e78d8e51 ZW |
39 | #include "optabs.h" |
40 | #include "libfuncs.h" | |
77c9c6c2 | 41 | #include "recog.h" |
2829c155 | 42 | #include "reload.h" |
87ff9c8e | 43 | #include "ggc.h" |
7bdb32b9 | 44 | #include "real.h" |
4a69cf79 | 45 | #include "basic-block.h" |
c15c90bb | 46 | #include "target.h" |
77c9c6c2 RK |
47 | |
48 | /* Each optab contains info on how this target machine | |
49 | can perform a particular operation | |
50 | for all sizes and kinds of operands. | |
51 | ||
52 | The operation to be performed is often specified | |
53 | by passing one of these optabs as an argument. | |
54 | ||
55 | See expr.h for documentation of these optabs. */ | |
56 | ||
34220a12 BS |
57 | optab optab_table[OTI_MAX]; |
58 | ||
59 | rtx libfunc_table[LTI_MAX]; | |
19c3fc24 | 60 | |
85363ca0 ZW |
61 | /* Tables of patterns for converting one mode to another. */ |
62 | convert_optab convert_optab_table[CTI_MAX]; | |
5d81dc5b | 63 | |
377017c4 RK |
64 | /* Contains the optab used for each rtx code. */ |
65 | optab code_to_optab[NUM_RTX_CODE + 1]; | |
66 | ||
77c9c6c2 RK |
67 | /* Indexed by the rtx-code for a conditional (eg. EQ, LT,...) |
68 | gives the gen_function to make a branch to test that condition. */ | |
69 | ||
70 | rtxfun bcc_gen_fctn[NUM_RTX_CODE]; | |
71 | ||
72 | /* Indexed by the rtx-code for a conditional (eg. EQ, LT,...) | |
73 | gives the insn code to make a store-condition insn | |
74 | to test that condition. */ | |
75 | ||
76 | enum insn_code setcc_gen_code[NUM_RTX_CODE]; | |
77 | ||
49c4584c DE |
78 | #ifdef HAVE_conditional_move |
79 | /* Indexed by the machine mode, gives the insn code to make a conditional | |
80 | move insn. This is not indexed by the rtx-code like bcc_gen_fctn and | |
81 | setcc_gen_code to cut down on the number of named patterns. Consider a day | |
82 | when a lot more rtx codes are conditional (eg: for the ARM). */ | |
83 | ||
84 | enum insn_code movcc_gen_code[NUM_MACHINE_MODES]; | |
85 | #endif | |
86 | ||
842a431a DM |
87 | /* The insn generating function can not take an rtx_code argument. |
88 | TRAP_RTX is used as an rtx argument. Its code is replaced with | |
89 | the code to be used in the trap insn and all other fields are ignored. */ | |
90 | static GTY(()) rtx trap_rtx; | |
91 | ||
0c20a65f AJ |
92 | static int add_equal_note (rtx, rtx, enum rtx_code, rtx, rtx); |
93 | static rtx widen_operand (rtx, enum machine_mode, enum machine_mode, int, | |
94 | int); | |
95 | static int expand_cmplxdiv_straight (rtx, rtx, rtx, rtx, rtx, rtx, | |
96 | enum machine_mode, int, | |
97 | enum optab_methods, enum mode_class, | |
98 | optab); | |
99 | static int expand_cmplxdiv_wide (rtx, rtx, rtx, rtx, rtx, rtx, | |
100 | enum machine_mode, int, enum optab_methods, | |
101 | enum mode_class, optab); | |
102 | static void prepare_cmp_insn (rtx *, rtx *, enum rtx_code *, rtx, | |
103 | enum machine_mode *, int *, | |
104 | enum can_compare_purpose); | |
105 | static enum insn_code can_fix_p (enum machine_mode, enum machine_mode, int, | |
106 | int *); | |
107 | static enum insn_code can_float_p (enum machine_mode, enum machine_mode, int); | |
0c20a65f | 108 | static optab new_optab (void); |
85363ca0 | 109 | static convert_optab new_convert_optab (void); |
0c20a65f AJ |
110 | static inline optab init_optab (enum rtx_code); |
111 | static inline optab init_optabv (enum rtx_code); | |
85363ca0 | 112 | static inline convert_optab init_convert_optab (enum rtx_code); |
0c20a65f AJ |
113 | static void init_libfuncs (optab, int, int, const char *, int); |
114 | static void init_integral_libfuncs (optab, const char *, int); | |
115 | static void init_floating_libfuncs (optab, const char *, int); | |
85363ca0 ZW |
116 | static void init_interclass_conv_libfuncs (convert_optab, const char *, |
117 | enum mode_class, enum mode_class); | |
118 | static void init_intraclass_conv_libfuncs (convert_optab, const char *, | |
119 | enum mode_class, bool); | |
0c20a65f AJ |
120 | static void emit_cmp_and_jump_insn_1 (rtx, rtx, enum machine_mode, |
121 | enum rtx_code, int, rtx); | |
122 | static void prepare_float_lib_cmp (rtx *, rtx *, enum rtx_code *, | |
123 | enum machine_mode *, int *); | |
124 | static rtx expand_vector_binop (enum machine_mode, optab, rtx, rtx, rtx, int, | |
125 | enum optab_methods); | |
126 | static rtx expand_vector_unop (enum machine_mode, optab, rtx, rtx, int); | |
127 | static rtx widen_clz (enum machine_mode, rtx, rtx); | |
128 | static rtx expand_parity (enum machine_mode, rtx, rtx); | |
842a431a DM |
129 | |
130 | #ifndef HAVE_conditional_trap | |
131 | #define HAVE_conditional_trap 0 | |
132 | #define gen_conditional_trap(a,b) (abort (), NULL_RTX) | |
133 | #endif | |
77c9c6c2 | 134 | \f |
2f937369 | 135 | /* Add a REG_EQUAL note to the last insn in INSNS. TARGET is being set to |
77c9c6c2 RK |
136 | the result of operation CODE applied to OP0 (and OP1 if it is a binary |
137 | operation). | |
138 | ||
139 | If the last insn does not set TARGET, don't do anything, but return 1. | |
140 | ||
141 | If a previous insn sets TARGET and TARGET is one of OP0 or OP1, | |
142 | don't add the REG_EQUAL note but return 0. Our caller can then try | |
143 | again, ensuring that TARGET is not one of the operands. */ | |
144 | ||
145 | static int | |
0c20a65f | 146 | add_equal_note (rtx insns, rtx target, enum rtx_code code, rtx op0, rtx op1) |
77c9c6c2 | 147 | { |
2f937369 | 148 | rtx last_insn, insn, set; |
77c9c6c2 RK |
149 | rtx note; |
150 | ||
2f937369 DM |
151 | if (! insns |
152 | || ! INSN_P (insns) | |
153 | || NEXT_INSN (insns) == NULL_RTX) | |
154 | abort (); | |
155 | ||
ec8e098d PB |
156 | if (GET_RTX_CLASS (code) != RTX_COMM_ARITH |
157 | && GET_RTX_CLASS (code) != RTX_BIN_ARITH | |
158 | && GET_RTX_CLASS (code) != RTX_COMM_COMPARE | |
159 | && GET_RTX_CLASS (code) != RTX_COMPARE | |
160 | && GET_RTX_CLASS (code) != RTX_UNARY) | |
2f937369 DM |
161 | return 1; |
162 | ||
163 | if (GET_CODE (target) == ZERO_EXTRACT) | |
164 | return 1; | |
165 | ||
166 | for (last_insn = insns; | |
167 | NEXT_INSN (last_insn) != NULL_RTX; | |
168 | last_insn = NEXT_INSN (last_insn)) | |
169 | ; | |
170 | ||
171 | set = single_set (last_insn); | |
172 | if (set == NULL_RTX) | |
173 | return 1; | |
174 | ||
175 | if (! rtx_equal_p (SET_DEST (set), target) | |
f9d36a92 | 176 | /* For a STRICT_LOW_PART, the REG_NOTE applies to what is inside it. */ |
2f937369 | 177 | && (GET_CODE (SET_DEST (set)) != STRICT_LOW_PART |
f9d36a92 | 178 | || ! rtx_equal_p (XEXP (SET_DEST (set), 0), target))) |
77c9c6c2 RK |
179 | return 1; |
180 | ||
181 | /* If TARGET is in OP0 or OP1, check if anything in SEQ sets TARGET | |
182 | besides the last insn. */ | |
183 | if (reg_overlap_mentioned_p (target, op0) | |
184 | || (op1 && reg_overlap_mentioned_p (target, op1))) | |
2f937369 DM |
185 | { |
186 | insn = PREV_INSN (last_insn); | |
187 | while (insn != NULL_RTX) | |
188 | { | |
189 | if (reg_set_p (target, insn)) | |
190 | return 0; | |
191 | ||
192 | insn = PREV_INSN (insn); | |
193 | } | |
194 | } | |
77c9c6c2 | 195 | |
ec8e098d | 196 | if (GET_RTX_CLASS (code) == RTX_UNARY) |
9e6a5703 | 197 | note = gen_rtx_fmt_e (code, GET_MODE (target), copy_rtx (op0)); |
77c9c6c2 | 198 | else |
9e6a5703 | 199 | note = gen_rtx_fmt_ee (code, GET_MODE (target), copy_rtx (op0), copy_rtx (op1)); |
77c9c6c2 | 200 | |
2f937369 | 201 | set_unique_reg_note (last_insn, REG_EQUAL, note); |
77c9c6c2 RK |
202 | |
203 | return 1; | |
204 | } | |
205 | \f | |
835532b8 RK |
206 | /* Widen OP to MODE and return the rtx for the widened operand. UNSIGNEDP |
207 | says whether OP is signed or unsigned. NO_EXTEND is nonzero if we need | |
0c20a65f | 208 | not actually do a sign-extend or zero-extend, but can leave the |
835532b8 RK |
209 | higher-order bits of the result rtx undefined, for example, in the case |
210 | of logical operations, but not right shifts. */ | |
211 | ||
212 | static rtx | |
0c20a65f AJ |
213 | widen_operand (rtx op, enum machine_mode mode, enum machine_mode oldmode, |
214 | int unsignedp, int no_extend) | |
835532b8 RK |
215 | { |
216 | rtx result; | |
217 | ||
8041889f RK |
218 | /* If we don't have to extend and this is a constant, return it. */ |
219 | if (no_extend && GET_MODE (op) == VOIDmode) | |
220 | return op; | |
221 | ||
222 | /* If we must extend do so. If OP is a SUBREG for a promoted object, also | |
223 | extend since it will be more efficient to do so unless the signedness of | |
224 | a promoted object differs from our extension. */ | |
835532b8 | 225 | if (! no_extend |
cb8f73be RK |
226 | || (GET_CODE (op) == SUBREG && SUBREG_PROMOTED_VAR_P (op) |
227 | && SUBREG_PROMOTED_UNSIGNED_P (op) == unsignedp)) | |
0661a3de | 228 | return convert_modes (mode, oldmode, op, unsignedp); |
835532b8 RK |
229 | |
230 | /* If MODE is no wider than a single word, we return a paradoxical | |
231 | SUBREG. */ | |
232 | if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD) | |
9e6a5703 | 233 | return gen_rtx_SUBREG (mode, force_reg (GET_MODE (op), op), 0); |
835532b8 RK |
234 | |
235 | /* Otherwise, get an object of MODE, clobber it, and set the low-order | |
236 | part to OP. */ | |
237 | ||
238 | result = gen_reg_rtx (mode); | |
9e6a5703 | 239 | emit_insn (gen_rtx_CLOBBER (VOIDmode, result)); |
835532b8 RK |
240 | emit_move_insn (gen_lowpart (GET_MODE (op), result), op); |
241 | return result; | |
242 | } | |
243 | \f | |
c64f913e CB |
244 | /* Generate code to perform a straightforward complex divide. */ |
245 | ||
246 | static int | |
0c20a65f AJ |
247 | expand_cmplxdiv_straight (rtx real0, rtx real1, rtx imag0, rtx imag1, |
248 | rtx realr, rtx imagr, enum machine_mode submode, | |
249 | int unsignedp, enum optab_methods methods, | |
250 | enum mode_class class, optab binoptab) | |
c64f913e CB |
251 | { |
252 | rtx divisor; | |
253 | rtx real_t, imag_t; | |
254 | rtx temp1, temp2; | |
255 | rtx res; | |
91ce572a CC |
256 | optab this_add_optab = add_optab; |
257 | optab this_sub_optab = sub_optab; | |
258 | optab this_neg_optab = neg_optab; | |
259 | optab this_mul_optab = smul_optab; | |
0c20a65f | 260 | |
91ce572a CC |
261 | if (binoptab == sdivv_optab) |
262 | { | |
263 | this_add_optab = addv_optab; | |
264 | this_sub_optab = subv_optab; | |
265 | this_neg_optab = negv_optab; | |
266 | this_mul_optab = smulv_optab; | |
267 | } | |
268 | ||
c64f913e CB |
269 | /* Don't fetch these from memory more than once. */ |
270 | real0 = force_reg (submode, real0); | |
271 | real1 = force_reg (submode, real1); | |
272 | ||
273 | if (imag0 != 0) | |
274 | imag0 = force_reg (submode, imag0); | |
275 | ||
276 | imag1 = force_reg (submode, imag1); | |
277 | ||
278 | /* Divisor: c*c + d*d. */ | |
91ce572a | 279 | temp1 = expand_binop (submode, this_mul_optab, real1, real1, |
c64f913e CB |
280 | NULL_RTX, unsignedp, methods); |
281 | ||
91ce572a | 282 | temp2 = expand_binop (submode, this_mul_optab, imag1, imag1, |
c64f913e CB |
283 | NULL_RTX, unsignedp, methods); |
284 | ||
285 | if (temp1 == 0 || temp2 == 0) | |
286 | return 0; | |
287 | ||
91ce572a | 288 | divisor = expand_binop (submode, this_add_optab, temp1, temp2, |
c64f913e CB |
289 | NULL_RTX, unsignedp, methods); |
290 | if (divisor == 0) | |
291 | return 0; | |
292 | ||
086bbd21 | 293 | if (imag0 == 0) |
c64f913e CB |
294 | { |
295 | /* Mathematically, ((a)(c-id))/divisor. */ | |
296 | /* Computationally, (a+i0) / (c+id) = (ac/(cc+dd)) + i(-ad/(cc+dd)). */ | |
297 | ||
298 | /* Calculate the dividend. */ | |
91ce572a | 299 | real_t = expand_binop (submode, this_mul_optab, real0, real1, |
c64f913e | 300 | NULL_RTX, unsignedp, methods); |
0c20a65f | 301 | |
91ce572a | 302 | imag_t = expand_binop (submode, this_mul_optab, real0, imag1, |
c64f913e CB |
303 | NULL_RTX, unsignedp, methods); |
304 | ||
305 | if (real_t == 0 || imag_t == 0) | |
306 | return 0; | |
307 | ||
91ce572a | 308 | imag_t = expand_unop (submode, this_neg_optab, imag_t, |
c64f913e CB |
309 | NULL_RTX, unsignedp); |
310 | } | |
311 | else | |
312 | { | |
313 | /* Mathematically, ((a+ib)(c-id))/divider. */ | |
314 | /* Calculate the dividend. */ | |
91ce572a | 315 | temp1 = expand_binop (submode, this_mul_optab, real0, real1, |
c64f913e CB |
316 | NULL_RTX, unsignedp, methods); |
317 | ||
91ce572a | 318 | temp2 = expand_binop (submode, this_mul_optab, imag0, imag1, |
c64f913e CB |
319 | NULL_RTX, unsignedp, methods); |
320 | ||
321 | if (temp1 == 0 || temp2 == 0) | |
322 | return 0; | |
323 | ||
91ce572a | 324 | real_t = expand_binop (submode, this_add_optab, temp1, temp2, |
c64f913e | 325 | NULL_RTX, unsignedp, methods); |
0c20a65f | 326 | |
91ce572a | 327 | temp1 = expand_binop (submode, this_mul_optab, imag0, real1, |
c64f913e CB |
328 | NULL_RTX, unsignedp, methods); |
329 | ||
91ce572a | 330 | temp2 = expand_binop (submode, this_mul_optab, real0, imag1, |
c64f913e CB |
331 | NULL_RTX, unsignedp, methods); |
332 | ||
333 | if (temp1 == 0 || temp2 == 0) | |
334 | return 0; | |
335 | ||
91ce572a | 336 | imag_t = expand_binop (submode, this_sub_optab, temp1, temp2, |
c64f913e CB |
337 | NULL_RTX, unsignedp, methods); |
338 | ||
339 | if (real_t == 0 || imag_t == 0) | |
340 | return 0; | |
341 | } | |
342 | ||
343 | if (class == MODE_COMPLEX_FLOAT) | |
344 | res = expand_binop (submode, binoptab, real_t, divisor, | |
345 | realr, unsignedp, methods); | |
346 | else | |
347 | res = expand_divmod (0, TRUNC_DIV_EXPR, submode, | |
348 | real_t, divisor, realr, unsignedp); | |
349 | ||
350 | if (res == 0) | |
351 | return 0; | |
352 | ||
353 | if (res != realr) | |
354 | emit_move_insn (realr, res); | |
355 | ||
356 | if (class == MODE_COMPLEX_FLOAT) | |
357 | res = expand_binop (submode, binoptab, imag_t, divisor, | |
358 | imagr, unsignedp, methods); | |
359 | else | |
360 | res = expand_divmod (0, TRUNC_DIV_EXPR, submode, | |
361 | imag_t, divisor, imagr, unsignedp); | |
362 | ||
363 | if (res == 0) | |
364 | return 0; | |
365 | ||
366 | if (res != imagr) | |
367 | emit_move_insn (imagr, res); | |
368 | ||
369 | return 1; | |
370 | } | |
371 | \f | |
372 | /* Generate code to perform a wide-input-range-acceptable complex divide. */ | |
373 | ||
374 | static int | |
0c20a65f AJ |
375 | expand_cmplxdiv_wide (rtx real0, rtx real1, rtx imag0, rtx imag1, rtx realr, |
376 | rtx imagr, enum machine_mode submode, int unsignedp, | |
377 | enum optab_methods methods, enum mode_class class, | |
378 | optab binoptab) | |
c64f913e CB |
379 | { |
380 | rtx ratio, divisor; | |
381 | rtx real_t, imag_t; | |
382 | rtx temp1, temp2, lab1, lab2; | |
383 | enum machine_mode mode; | |
c64f913e | 384 | rtx res; |
91ce572a CC |
385 | optab this_add_optab = add_optab; |
386 | optab this_sub_optab = sub_optab; | |
387 | optab this_neg_optab = neg_optab; | |
388 | optab this_mul_optab = smul_optab; | |
389 | ||
390 | if (binoptab == sdivv_optab) | |
391 | { | |
392 | this_add_optab = addv_optab; | |
393 | this_sub_optab = subv_optab; | |
394 | this_neg_optab = negv_optab; | |
395 | this_mul_optab = smulv_optab; | |
396 | } | |
0c20a65f | 397 | |
c64f913e CB |
398 | /* Don't fetch these from memory more than once. */ |
399 | real0 = force_reg (submode, real0); | |
400 | real1 = force_reg (submode, real1); | |
401 | ||
402 | if (imag0 != 0) | |
403 | imag0 = force_reg (submode, imag0); | |
404 | ||
405 | imag1 = force_reg (submode, imag1); | |
406 | ||
a59a536c RE |
407 | /* XXX What's an "unsigned" complex number? */ |
408 | if (unsignedp) | |
409 | { | |
410 | temp1 = real1; | |
411 | temp2 = imag1; | |
412 | } | |
413 | else | |
414 | { | |
91ce572a CC |
415 | temp1 = expand_abs (submode, real1, NULL_RTX, unsignedp, 1); |
416 | temp2 = expand_abs (submode, imag1, NULL_RTX, unsignedp, 1); | |
a59a536c | 417 | } |
c64f913e CB |
418 | |
419 | if (temp1 == 0 || temp2 == 0) | |
420 | return 0; | |
421 | ||
422 | mode = GET_MODE (temp1); | |
c64f913e CB |
423 | lab1 = gen_label_rtx (); |
424 | emit_cmp_and_jump_insns (temp1, temp2, LT, NULL_RTX, | |
a06ef755 | 425 | mode, unsignedp, lab1); |
c64f913e CB |
426 | |
427 | /* |c| >= |d|; use ratio d/c to scale dividend and divisor. */ | |
428 | ||
429 | if (class == MODE_COMPLEX_FLOAT) | |
430 | ratio = expand_binop (submode, binoptab, imag1, real1, | |
431 | NULL_RTX, unsignedp, methods); | |
432 | else | |
433 | ratio = expand_divmod (0, TRUNC_DIV_EXPR, submode, | |
434 | imag1, real1, NULL_RTX, unsignedp); | |
435 | ||
436 | if (ratio == 0) | |
437 | return 0; | |
438 | ||
439 | /* Calculate divisor. */ | |
440 | ||
91ce572a | 441 | temp1 = expand_binop (submode, this_mul_optab, imag1, ratio, |
c64f913e CB |
442 | NULL_RTX, unsignedp, methods); |
443 | ||
444 | if (temp1 == 0) | |
445 | return 0; | |
446 | ||
91ce572a | 447 | divisor = expand_binop (submode, this_add_optab, temp1, real1, |
c64f913e CB |
448 | NULL_RTX, unsignedp, methods); |
449 | ||
450 | if (divisor == 0) | |
451 | return 0; | |
452 | ||
453 | /* Calculate dividend. */ | |
454 | ||
086bbd21 | 455 | if (imag0 == 0) |
c64f913e CB |
456 | { |
457 | real_t = real0; | |
458 | ||
459 | /* Compute a / (c+id) as a / (c+d(d/c)) + i (-a(d/c)) / (c+d(d/c)). */ | |
460 | ||
91ce572a | 461 | imag_t = expand_binop (submode, this_mul_optab, real0, ratio, |
c64f913e CB |
462 | NULL_RTX, unsignedp, methods); |
463 | ||
464 | if (imag_t == 0) | |
465 | return 0; | |
466 | ||
91ce572a | 467 | imag_t = expand_unop (submode, this_neg_optab, imag_t, |
c64f913e CB |
468 | NULL_RTX, unsignedp); |
469 | ||
470 | if (real_t == 0 || imag_t == 0) | |
471 | return 0; | |
472 | } | |
473 | else | |
474 | { | |
475 | /* Compute (a+ib)/(c+id) as | |
476 | (a+b(d/c))/(c+d(d/c) + i(b-a(d/c))/(c+d(d/c)). */ | |
477 | ||
91ce572a | 478 | temp1 = expand_binop (submode, this_mul_optab, imag0, ratio, |
c64f913e CB |
479 | NULL_RTX, unsignedp, methods); |
480 | ||
481 | if (temp1 == 0) | |
482 | return 0; | |
483 | ||
91ce572a | 484 | real_t = expand_binop (submode, this_add_optab, temp1, real0, |
c64f913e CB |
485 | NULL_RTX, unsignedp, methods); |
486 | ||
91ce572a | 487 | temp1 = expand_binop (submode, this_mul_optab, real0, ratio, |
c64f913e CB |
488 | NULL_RTX, unsignedp, methods); |
489 | ||
490 | if (temp1 == 0) | |
491 | return 0; | |
492 | ||
91ce572a | 493 | imag_t = expand_binop (submode, this_sub_optab, imag0, temp1, |
c64f913e CB |
494 | NULL_RTX, unsignedp, methods); |
495 | ||
496 | if (real_t == 0 || imag_t == 0) | |
497 | return 0; | |
498 | } | |
499 | ||
500 | if (class == MODE_COMPLEX_FLOAT) | |
501 | res = expand_binop (submode, binoptab, real_t, divisor, | |
502 | realr, unsignedp, methods); | |
503 | else | |
504 | res = expand_divmod (0, TRUNC_DIV_EXPR, submode, | |
505 | real_t, divisor, realr, unsignedp); | |
506 | ||
507 | if (res == 0) | |
508 | return 0; | |
509 | ||
510 | if (res != realr) | |
511 | emit_move_insn (realr, res); | |
512 | ||
513 | if (class == MODE_COMPLEX_FLOAT) | |
514 | res = expand_binop (submode, binoptab, imag_t, divisor, | |
515 | imagr, unsignedp, methods); | |
516 | else | |
517 | res = expand_divmod (0, TRUNC_DIV_EXPR, submode, | |
518 | imag_t, divisor, imagr, unsignedp); | |
519 | ||
520 | if (res == 0) | |
521 | return 0; | |
522 | ||
523 | if (res != imagr) | |
524 | emit_move_insn (imagr, res); | |
525 | ||
526 | lab2 = gen_label_rtx (); | |
527 | emit_jump_insn (gen_jump (lab2)); | |
528 | emit_barrier (); | |
529 | ||
530 | emit_label (lab1); | |
531 | ||
532 | /* |d| > |c|; use ratio c/d to scale dividend and divisor. */ | |
533 | ||
534 | if (class == MODE_COMPLEX_FLOAT) | |
535 | ratio = expand_binop (submode, binoptab, real1, imag1, | |
536 | NULL_RTX, unsignedp, methods); | |
537 | else | |
538 | ratio = expand_divmod (0, TRUNC_DIV_EXPR, submode, | |
539 | real1, imag1, NULL_RTX, unsignedp); | |
540 | ||
541 | if (ratio == 0) | |
542 | return 0; | |
543 | ||
544 | /* Calculate divisor. */ | |
545 | ||
91ce572a | 546 | temp1 = expand_binop (submode, this_mul_optab, real1, ratio, |
c64f913e CB |
547 | NULL_RTX, unsignedp, methods); |
548 | ||
549 | if (temp1 == 0) | |
550 | return 0; | |
551 | ||
91ce572a | 552 | divisor = expand_binop (submode, this_add_optab, temp1, imag1, |
c64f913e CB |
553 | NULL_RTX, unsignedp, methods); |
554 | ||
555 | if (divisor == 0) | |
556 | return 0; | |
557 | ||
558 | /* Calculate dividend. */ | |
559 | ||
086bbd21 | 560 | if (imag0 == 0) |
c64f913e CB |
561 | { |
562 | /* Compute a / (c+id) as a(c/d) / (c(c/d)+d) + i (-a) / (c(c/d)+d). */ | |
563 | ||
91ce572a | 564 | real_t = expand_binop (submode, this_mul_optab, real0, ratio, |
c64f913e CB |
565 | NULL_RTX, unsignedp, methods); |
566 | ||
91ce572a | 567 | imag_t = expand_unop (submode, this_neg_optab, real0, |
c64f913e CB |
568 | NULL_RTX, unsignedp); |
569 | ||
570 | if (real_t == 0 || imag_t == 0) | |
571 | return 0; | |
572 | } | |
573 | else | |
574 | { | |
575 | /* Compute (a+ib)/(c+id) as | |
576 | (a(c/d)+b)/(c(c/d)+d) + i (b(c/d)-a)/(c(c/d)+d). */ | |
577 | ||
91ce572a | 578 | temp1 = expand_binop (submode, this_mul_optab, real0, ratio, |
c64f913e CB |
579 | NULL_RTX, unsignedp, methods); |
580 | ||
581 | if (temp1 == 0) | |
582 | return 0; | |
583 | ||
91ce572a | 584 | real_t = expand_binop (submode, this_add_optab, temp1, imag0, |
c64f913e CB |
585 | NULL_RTX, unsignedp, methods); |
586 | ||
91ce572a | 587 | temp1 = expand_binop (submode, this_mul_optab, imag0, ratio, |
c64f913e CB |
588 | NULL_RTX, unsignedp, methods); |
589 | ||
590 | if (temp1 == 0) | |
591 | return 0; | |
592 | ||
91ce572a | 593 | imag_t = expand_binop (submode, this_sub_optab, temp1, real0, |
c64f913e CB |
594 | NULL_RTX, unsignedp, methods); |
595 | ||
596 | if (real_t == 0 || imag_t == 0) | |
597 | return 0; | |
598 | } | |
599 | ||
600 | if (class == MODE_COMPLEX_FLOAT) | |
601 | res = expand_binop (submode, binoptab, real_t, divisor, | |
602 | realr, unsignedp, methods); | |
603 | else | |
604 | res = expand_divmod (0, TRUNC_DIV_EXPR, submode, | |
605 | real_t, divisor, realr, unsignedp); | |
606 | ||
607 | if (res == 0) | |
608 | return 0; | |
609 | ||
610 | if (res != realr) | |
611 | emit_move_insn (realr, res); | |
612 | ||
613 | if (class == MODE_COMPLEX_FLOAT) | |
614 | res = expand_binop (submode, binoptab, imag_t, divisor, | |
615 | imagr, unsignedp, methods); | |
616 | else | |
617 | res = expand_divmod (0, TRUNC_DIV_EXPR, submode, | |
618 | imag_t, divisor, imagr, unsignedp); | |
619 | ||
620 | if (res == 0) | |
621 | return 0; | |
622 | ||
623 | if (res != imagr) | |
624 | emit_move_insn (imagr, res); | |
625 | ||
626 | emit_label (lab2); | |
627 | ||
628 | return 1; | |
629 | } | |
630 | \f | |
ef89d648 ZW |
631 | /* Wrapper around expand_binop which takes an rtx code to specify |
632 | the operation to perform, not an optab pointer. All other | |
633 | arguments are the same. */ | |
634 | rtx | |
0c20a65f AJ |
635 | expand_simple_binop (enum machine_mode mode, enum rtx_code code, rtx op0, |
636 | rtx op1, rtx target, int unsignedp, | |
637 | enum optab_methods methods) | |
ef89d648 | 638 | { |
7e1a450d | 639 | optab binop = code_to_optab[(int) code]; |
ef89d648 ZW |
640 | if (binop == 0) |
641 | abort (); | |
642 | ||
643 | return expand_binop (mode, binop, op0, op1, target, unsignedp, methods); | |
644 | } | |
645 | ||
77c9c6c2 RK |
646 | /* Generate code to perform an operation specified by BINOPTAB |
647 | on operands OP0 and OP1, with result having machine-mode MODE. | |
648 | ||
649 | UNSIGNEDP is for the case where we have to widen the operands | |
650 | to perform the operation. It says to use zero-extension. | |
651 | ||
652 | If TARGET is nonzero, the value | |
653 | is generated there, if it is convenient to do so. | |
654 | In all cases an rtx is returned for the locus of the value; | |
655 | this may or may not be TARGET. */ | |
656 | ||
657 | rtx | |
0c20a65f AJ |
658 | expand_binop (enum machine_mode mode, optab binoptab, rtx op0, rtx op1, |
659 | rtx target, int unsignedp, enum optab_methods methods) | |
77c9c6c2 | 660 | { |
70864443 RK |
661 | enum optab_methods next_methods |
662 | = (methods == OPTAB_LIB || methods == OPTAB_LIB_WIDEN | |
663 | ? OPTAB_WIDEN : methods); | |
77c9c6c2 RK |
664 | enum mode_class class; |
665 | enum machine_mode wider_mode; | |
b3694847 | 666 | rtx temp; |
77c9c6c2 | 667 | int commutative_op = 0; |
7e1a450d | 668 | int shift_op = (binoptab->code == ASHIFT |
77c9c6c2 | 669 | || binoptab->code == ASHIFTRT |
77c9c6c2 RK |
670 | || binoptab->code == LSHIFTRT |
671 | || binoptab->code == ROTATE | |
672 | || binoptab->code == ROTATERT); | |
abd418d3 | 673 | rtx entry_last = get_last_insn (); |
77c9c6c2 RK |
674 | rtx last; |
675 | ||
676 | class = GET_MODE_CLASS (mode); | |
677 | ||
77c9c6c2 RK |
678 | if (flag_force_mem) |
679 | { | |
894207cf RS |
680 | /* Load duplicate non-volatile operands once. */ |
681 | if (rtx_equal_p (op0, op1) && ! volatile_refs_p (op0)) | |
682 | { | |
683 | op0 = force_not_mem (op0); | |
684 | op1 = op0; | |
685 | } | |
686 | else | |
687 | { | |
688 | op0 = force_not_mem (op0); | |
689 | op1 = force_not_mem (op1); | |
690 | } | |
77c9c6c2 RK |
691 | } |
692 | ||
8aecce0a RK |
693 | /* If subtracting an integer constant, convert this into an addition of |
694 | the negated constant. */ | |
695 | ||
696 | if (binoptab == sub_optab && GET_CODE (op1) == CONST_INT) | |
697 | { | |
698 | op1 = negate_rtx (mode, op1); | |
699 | binoptab = add_optab; | |
700 | } | |
701 | ||
77c9c6c2 RK |
702 | /* If we are inside an appropriately-short loop and one operand is an |
703 | expensive constant, force it into a register. */ | |
aeedc93f | 704 | if (CONSTANT_P (op0) && preserve_subexpressions_p () |
b437f1a7 | 705 | && rtx_cost (op0, binoptab->code) > COSTS_N_INSNS (1)) |
77c9c6c2 RK |
706 | op0 = force_reg (mode, op0); |
707 | ||
aeedc93f | 708 | if (CONSTANT_P (op1) && preserve_subexpressions_p () |
b437f1a7 | 709 | && ! shift_op && rtx_cost (op1, binoptab->code) > COSTS_N_INSNS (1)) |
4074220e | 710 | op1 = force_reg (mode, op1); |
77c9c6c2 | 711 | |
77c9c6c2 RK |
712 | /* Record where to delete back to if we backtrack. */ |
713 | last = get_last_insn (); | |
714 | ||
715 | /* If operation is commutative, | |
716 | try to make the first operand a register. | |
717 | Even better, try to make it the same as the target. | |
718 | Also try to make the last operand a constant. */ | |
ec8e098d | 719 | if (GET_RTX_CLASS (binoptab->code) == RTX_COMM_ARITH |
77c9c6c2 | 720 | || binoptab == smul_widen_optab |
5035bbfe TG |
721 | || binoptab == umul_widen_optab |
722 | || binoptab == smul_highpart_optab | |
723 | || binoptab == umul_highpart_optab) | |
77c9c6c2 RK |
724 | { |
725 | commutative_op = 1; | |
726 | ||
f8cfc6aa JQ |
727 | if (((target == 0 || REG_P (target)) |
728 | ? ((REG_P (op1) | |
729 | && !REG_P (op0)) | |
77c9c6c2 RK |
730 | || target == op1) |
731 | : rtx_equal_p (op1, target)) | |
732 | || GET_CODE (op0) == CONST_INT) | |
733 | { | |
734 | temp = op1; | |
735 | op1 = op0; | |
736 | op0 = temp; | |
737 | } | |
738 | } | |
739 | ||
740 | /* If we can do it with a three-operand insn, do so. */ | |
741 | ||
742 | if (methods != OPTAB_MUST_WIDEN | |
743 | && binoptab->handlers[(int) mode].insn_code != CODE_FOR_nothing) | |
744 | { | |
745 | int icode = (int) binoptab->handlers[(int) mode].insn_code; | |
a995e389 RH |
746 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; |
747 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
77c9c6c2 RK |
748 | rtx pat; |
749 | rtx xop0 = op0, xop1 = op1; | |
750 | ||
751 | if (target) | |
752 | temp = target; | |
753 | else | |
754 | temp = gen_reg_rtx (mode); | |
755 | ||
756 | /* If it is a commutative operator and the modes would match | |
0f41302f | 757 | if we would swap the operands, we can save the conversions. */ |
77c9c6c2 RK |
758 | if (commutative_op) |
759 | { | |
760 | if (GET_MODE (op0) != mode0 && GET_MODE (op1) != mode1 | |
761 | && GET_MODE (op0) == mode1 && GET_MODE (op1) == mode0) | |
762 | { | |
b3694847 | 763 | rtx tmp; |
77c9c6c2 RK |
764 | |
765 | tmp = op0; op0 = op1; op1 = tmp; | |
766 | tmp = xop0; xop0 = xop1; xop1 = tmp; | |
767 | } | |
768 | } | |
769 | ||
770 | /* In case the insn wants input operands in modes different from | |
29984e05 EB |
771 | those of the actual operands, convert the operands. It would |
772 | seem that we don't need to convert CONST_INTs, but we do, so | |
35f1c975 EB |
773 | that they're properly zero-extended, sign-extended or truncated |
774 | for their mode. */ | |
77c9c6c2 | 775 | |
874f6a6d | 776 | if (GET_MODE (op0) != mode0 && mode0 != VOIDmode) |
69107307 AO |
777 | xop0 = convert_modes (mode0, |
778 | GET_MODE (op0) != VOIDmode | |
779 | ? GET_MODE (op0) | |
29984e05 | 780 | : mode, |
69107307 | 781 | xop0, unsignedp); |
77c9c6c2 | 782 | |
874f6a6d | 783 | if (GET_MODE (op1) != mode1 && mode1 != VOIDmode) |
69107307 AO |
784 | xop1 = convert_modes (mode1, |
785 | GET_MODE (op1) != VOIDmode | |
786 | ? GET_MODE (op1) | |
35f1c975 | 787 | : mode, |
69107307 | 788 | xop1, unsignedp); |
77c9c6c2 RK |
789 | |
790 | /* Now, if insn's predicates don't allow our operands, put them into | |
791 | pseudo regs. */ | |
792 | ||
a995e389 | 793 | if (! (*insn_data[icode].operand[1].predicate) (xop0, mode0) |
4074220e | 794 | && mode0 != VOIDmode) |
77c9c6c2 RK |
795 | xop0 = copy_to_mode_reg (mode0, xop0); |
796 | ||
a995e389 | 797 | if (! (*insn_data[icode].operand[2].predicate) (xop1, mode1) |
4074220e | 798 | && mode1 != VOIDmode) |
77c9c6c2 RK |
799 | xop1 = copy_to_mode_reg (mode1, xop1); |
800 | ||
a995e389 | 801 | if (! (*insn_data[icode].operand[0].predicate) (temp, mode)) |
77c9c6c2 RK |
802 | temp = gen_reg_rtx (mode); |
803 | ||
804 | pat = GEN_FCN (icode) (temp, xop0, xop1); | |
805 | if (pat) | |
806 | { | |
2f937369 | 807 | /* If PAT is composed of more than one insn, try to add an appropriate |
77c9c6c2 RK |
808 | REG_EQUAL note to it. If we can't because TEMP conflicts with an |
809 | operand, call ourselves again, this time without a target. */ | |
2f937369 | 810 | if (INSN_P (pat) && NEXT_INSN (pat) != NULL_RTX |
77c9c6c2 RK |
811 | && ! add_equal_note (pat, temp, binoptab->code, xop0, xop1)) |
812 | { | |
813 | delete_insns_since (last); | |
b1ec3c92 CH |
814 | return expand_binop (mode, binoptab, op0, op1, NULL_RTX, |
815 | unsignedp, methods); | |
77c9c6c2 RK |
816 | } |
817 | ||
818 | emit_insn (pat); | |
819 | return temp; | |
820 | } | |
821 | else | |
822 | delete_insns_since (last); | |
823 | } | |
824 | ||
5a5064dc RK |
825 | /* If this is a multiply, see if we can do a widening operation that |
826 | takes operands of this mode and makes a wider mode. */ | |
827 | ||
828 | if (binoptab == smul_optab && GET_MODE_WIDER_MODE (mode) != VOIDmode | |
829 | && (((unsignedp ? umul_widen_optab : smul_widen_optab) | |
830 | ->handlers[(int) GET_MODE_WIDER_MODE (mode)].insn_code) | |
831 | != CODE_FOR_nothing)) | |
832 | { | |
833 | temp = expand_binop (GET_MODE_WIDER_MODE (mode), | |
834 | unsignedp ? umul_widen_optab : smul_widen_optab, | |
73d9a835 | 835 | op0, op1, NULL_RTX, unsignedp, OPTAB_DIRECT); |
5a5064dc | 836 | |
70864443 RK |
837 | if (temp != 0) |
838 | { | |
839 | if (GET_MODE_CLASS (mode) == MODE_INT) | |
840 | return gen_lowpart (mode, temp); | |
841 | else | |
842 | return convert_to_mode (mode, temp, unsignedp); | |
843 | } | |
5a5064dc RK |
844 | } |
845 | ||
9a856ec7 | 846 | /* Look for a wider mode of the same class for which we think we |
5a5064dc RK |
847 | can open-code the operation. Check for a widening multiply at the |
848 | wider mode as well. */ | |
9a856ec7 RK |
849 | |
850 | if ((class == MODE_INT || class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT) | |
6f43c157 | 851 | && methods != OPTAB_DIRECT && methods != OPTAB_LIB) |
9a856ec7 RK |
852 | for (wider_mode = GET_MODE_WIDER_MODE (mode); wider_mode != VOIDmode; |
853 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) | |
854 | { | |
5a5064dc RK |
855 | if (binoptab->handlers[(int) wider_mode].insn_code != CODE_FOR_nothing |
856 | || (binoptab == smul_optab | |
857 | && GET_MODE_WIDER_MODE (wider_mode) != VOIDmode | |
858 | && (((unsignedp ? umul_widen_optab : smul_widen_optab) | |
859 | ->handlers[(int) GET_MODE_WIDER_MODE (wider_mode)].insn_code) | |
860 | != CODE_FOR_nothing))) | |
9a856ec7 RK |
861 | { |
862 | rtx xop0 = op0, xop1 = op1; | |
863 | int no_extend = 0; | |
864 | ||
865 | /* For certain integer operations, we need not actually extend | |
866 | the narrow operands, as long as we will truncate | |
6d2f8887 | 867 | the results to the same narrowness. */ |
9a856ec7 RK |
868 | |
869 | if ((binoptab == ior_optab || binoptab == and_optab | |
870 | || binoptab == xor_optab | |
871 | || binoptab == add_optab || binoptab == sub_optab | |
e5df894b | 872 | || binoptab == smul_optab || binoptab == ashl_optab) |
835532b8 | 873 | && class == MODE_INT) |
9a856ec7 RK |
874 | no_extend = 1; |
875 | ||
0661a3de | 876 | xop0 = widen_operand (xop0, wider_mode, mode, unsignedp, no_extend); |
943cc242 RK |
877 | |
878 | /* The second operand of a shift must always be extended. */ | |
0661a3de | 879 | xop1 = widen_operand (xop1, wider_mode, mode, unsignedp, |
e5df894b | 880 | no_extend && binoptab != ashl_optab); |
943cc242 | 881 | |
b1ec3c92 | 882 | temp = expand_binop (wider_mode, binoptab, xop0, xop1, NULL_RTX, |
9a856ec7 RK |
883 | unsignedp, OPTAB_DIRECT); |
884 | if (temp) | |
885 | { | |
886 | if (class != MODE_INT) | |
887 | { | |
888 | if (target == 0) | |
889 | target = gen_reg_rtx (mode); | |
890 | convert_move (target, temp, 0); | |
891 | return target; | |
892 | } | |
893 | else | |
894 | return gen_lowpart (mode, temp); | |
895 | } | |
896 | else | |
897 | delete_insns_since (last); | |
898 | } | |
899 | } | |
900 | ||
77c9c6c2 RK |
901 | /* These can be done a word at a time. */ |
902 | if ((binoptab == and_optab || binoptab == ior_optab || binoptab == xor_optab) | |
903 | && class == MODE_INT | |
904 | && GET_MODE_SIZE (mode) > UNITS_PER_WORD | |
34e56753 | 905 | && binoptab->handlers[(int) word_mode].insn_code != CODE_FOR_nothing) |
77c9c6c2 | 906 | { |
bb93b973 | 907 | int i; |
77c9c6c2 RK |
908 | rtx insns; |
909 | rtx equiv_value; | |
910 | ||
911 | /* If TARGET is the same as one of the operands, the REG_EQUAL note | |
912 | won't be accurate, so use a new target. */ | |
913 | if (target == 0 || target == op0 || target == op1) | |
914 | target = gen_reg_rtx (mode); | |
915 | ||
916 | start_sequence (); | |
917 | ||
918 | /* Do the actual arithmetic. */ | |
919 | for (i = 0; i < GET_MODE_BITSIZE (mode) / BITS_PER_WORD; i++) | |
920 | { | |
921 | rtx target_piece = operand_subword (target, i, 1, mode); | |
34e56753 | 922 | rtx x = expand_binop (word_mode, binoptab, |
77c9c6c2 RK |
923 | operand_subword_force (op0, i, mode), |
924 | operand_subword_force (op1, i, mode), | |
70864443 RK |
925 | target_piece, unsignedp, next_methods); |
926 | ||
927 | if (x == 0) | |
928 | break; | |
929 | ||
77c9c6c2 RK |
930 | if (target_piece != x) |
931 | emit_move_insn (target_piece, x); | |
932 | } | |
933 | ||
934 | insns = get_insns (); | |
935 | end_sequence (); | |
936 | ||
70864443 RK |
937 | if (i == GET_MODE_BITSIZE (mode) / BITS_PER_WORD) |
938 | { | |
939 | if (binoptab->code != UNKNOWN) | |
940 | equiv_value | |
9e6a5703 JC |
941 | = gen_rtx_fmt_ee (binoptab->code, mode, |
942 | copy_rtx (op0), copy_rtx (op1)); | |
70864443 RK |
943 | else |
944 | equiv_value = 0; | |
77c9c6c2 | 945 | |
70864443 RK |
946 | emit_no_conflict_block (insns, target, op0, op1, equiv_value); |
947 | return target; | |
948 | } | |
77c9c6c2 RK |
949 | } |
950 | ||
8c597270 | 951 | /* Synthesize double word shifts from single word shifts. */ |
e5df894b RK |
952 | if ((binoptab == lshr_optab || binoptab == ashl_optab |
953 | || binoptab == ashr_optab) | |
8c597270 JW |
954 | && class == MODE_INT |
955 | && GET_CODE (op1) == CONST_INT | |
956 | && GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD | |
957 | && binoptab->handlers[(int) word_mode].insn_code != CODE_FOR_nothing | |
958 | && ashl_optab->handlers[(int) word_mode].insn_code != CODE_FOR_nothing | |
959 | && lshr_optab->handlers[(int) word_mode].insn_code != CODE_FOR_nothing) | |
960 | { | |
70864443 | 961 | rtx insns, inter, equiv_value; |
8c597270 JW |
962 | rtx into_target, outof_target; |
963 | rtx into_input, outof_input; | |
964 | int shift_count, left_shift, outof_word; | |
965 | ||
966 | /* If TARGET is the same as one of the operands, the REG_EQUAL note | |
967 | won't be accurate, so use a new target. */ | |
968 | if (target == 0 || target == op0 || target == op1) | |
969 | target = gen_reg_rtx (mode); | |
970 | ||
971 | start_sequence (); | |
972 | ||
973 | shift_count = INTVAL (op1); | |
974 | ||
975 | /* OUTOF_* is the word we are shifting bits away from, and | |
976 | INTO_* is the word that we are shifting bits towards, thus | |
977 | they differ depending on the direction of the shift and | |
978 | WORDS_BIG_ENDIAN. */ | |
979 | ||
e5df894b | 980 | left_shift = binoptab == ashl_optab; |
8c597270 JW |
981 | outof_word = left_shift ^ ! WORDS_BIG_ENDIAN; |
982 | ||
983 | outof_target = operand_subword (target, outof_word, 1, mode); | |
984 | into_target = operand_subword (target, 1 - outof_word, 1, mode); | |
985 | ||
986 | outof_input = operand_subword_force (op0, outof_word, mode); | |
987 | into_input = operand_subword_force (op0, 1 - outof_word, mode); | |
988 | ||
989 | if (shift_count >= BITS_PER_WORD) | |
990 | { | |
70864443 RK |
991 | inter = expand_binop (word_mode, binoptab, |
992 | outof_input, | |
993 | GEN_INT (shift_count - BITS_PER_WORD), | |
994 | into_target, unsignedp, next_methods); | |
995 | ||
cb5b00cf | 996 | if (inter != 0 && inter != into_target) |
70864443 | 997 | emit_move_insn (into_target, inter); |
8c597270 JW |
998 | |
999 | /* For a signed right shift, we must fill the word we are shifting | |
1000 | out of with copies of the sign bit. Otherwise it is zeroed. */ | |
cb5b00cf RK |
1001 | if (inter != 0 && binoptab != ashr_optab) |
1002 | inter = CONST0_RTX (word_mode); | |
70864443 RK |
1003 | else if (inter != 0) |
1004 | inter = expand_binop (word_mode, binoptab, | |
1005 | outof_input, | |
1006 | GEN_INT (BITS_PER_WORD - 1), | |
1007 | outof_target, unsignedp, next_methods); | |
1008 | ||
cb5b00cf | 1009 | if (inter != 0 && inter != outof_target) |
70864443 | 1010 | emit_move_insn (outof_target, inter); |
8c597270 JW |
1011 | } |
1012 | else | |
1013 | { | |
70864443 | 1014 | rtx carries; |
8c597270 JW |
1015 | optab reverse_unsigned_shift, unsigned_shift; |
1016 | ||
1017 | /* For a shift of less then BITS_PER_WORD, to compute the carry, | |
1018 | we must do a logical shift in the opposite direction of the | |
1019 | desired shift. */ | |
1020 | ||
8c597270 JW |
1021 | reverse_unsigned_shift = (left_shift ? lshr_optab : ashl_optab); |
1022 | ||
1023 | /* For a shift of less than BITS_PER_WORD, to compute the word | |
1024 | shifted towards, we need to unsigned shift the orig value of | |
1025 | that word. */ | |
1026 | ||
1027 | unsigned_shift = (left_shift ? ashl_optab : lshr_optab); | |
1028 | ||
1029 | carries = expand_binop (word_mode, reverse_unsigned_shift, | |
1030 | outof_input, | |
1031 | GEN_INT (BITS_PER_WORD - shift_count), | |
70864443 RK |
1032 | 0, unsignedp, next_methods); |
1033 | ||
1034 | if (carries == 0) | |
1035 | inter = 0; | |
1036 | else | |
70864443 RK |
1037 | inter = expand_binop (word_mode, unsigned_shift, into_input, |
1038 | op1, 0, unsignedp, next_methods); | |
1039 | ||
1040 | if (inter != 0) | |
1041 | inter = expand_binop (word_mode, ior_optab, carries, inter, | |
1042 | into_target, unsignedp, next_methods); | |
1043 | ||
cb5b00cf | 1044 | if (inter != 0 && inter != into_target) |
70864443 | 1045 | emit_move_insn (into_target, inter); |
cf2f7113 RE |
1046 | |
1047 | if (inter != 0) | |
1048 | inter = expand_binop (word_mode, binoptab, outof_input, | |
1049 | op1, outof_target, unsignedp, next_methods); | |
0c20a65f | 1050 | |
cf2f7113 RE |
1051 | if (inter != 0 && inter != outof_target) |
1052 | emit_move_insn (outof_target, inter); | |
8c597270 JW |
1053 | } |
1054 | ||
1055 | insns = get_insns (); | |
1056 | end_sequence (); | |
1057 | ||
70864443 RK |
1058 | if (inter != 0) |
1059 | { | |
1060 | if (binoptab->code != UNKNOWN) | |
9e6a5703 | 1061 | equiv_value = gen_rtx_fmt_ee (binoptab->code, mode, op0, op1); |
70864443 RK |
1062 | else |
1063 | equiv_value = 0; | |
8c597270 | 1064 | |
70864443 RK |
1065 | emit_no_conflict_block (insns, target, op0, op1, equiv_value); |
1066 | return target; | |
1067 | } | |
8c597270 JW |
1068 | } |
1069 | ||
1070 | /* Synthesize double word rotates from single word shifts. */ | |
1071 | if ((binoptab == rotl_optab || binoptab == rotr_optab) | |
1072 | && class == MODE_INT | |
1073 | && GET_CODE (op1) == CONST_INT | |
1074 | && GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD | |
1075 | && ashl_optab->handlers[(int) word_mode].insn_code != CODE_FOR_nothing | |
1076 | && lshr_optab->handlers[(int) word_mode].insn_code != CODE_FOR_nothing) | |
1077 | { | |
1078 | rtx insns, equiv_value; | |
1079 | rtx into_target, outof_target; | |
1080 | rtx into_input, outof_input; | |
70864443 | 1081 | rtx inter; |
8c597270 JW |
1082 | int shift_count, left_shift, outof_word; |
1083 | ||
1084 | /* If TARGET is the same as one of the operands, the REG_EQUAL note | |
0c0ab0f1 OH |
1085 | won't be accurate, so use a new target. Do this also if target is not |
1086 | a REG, first because having a register instead may open optimization | |
1ae58c30 | 1087 | opportunities, and second because if target and op0 happen to be MEMs |
0c0ab0f1 OH |
1088 | designating the same location, we would risk clobbering it too early |
1089 | in the code sequence we generate below. */ | |
1090 | if (target == 0 || target == op0 || target == op1 || ! REG_P (target)) | |
8c597270 JW |
1091 | target = gen_reg_rtx (mode); |
1092 | ||
1093 | start_sequence (); | |
1094 | ||
1095 | shift_count = INTVAL (op1); | |
1096 | ||
1097 | /* OUTOF_* is the word we are shifting bits away from, and | |
1098 | INTO_* is the word that we are shifting bits towards, thus | |
1099 | they differ depending on the direction of the shift and | |
1100 | WORDS_BIG_ENDIAN. */ | |
1101 | ||
1102 | left_shift = (binoptab == rotl_optab); | |
1103 | outof_word = left_shift ^ ! WORDS_BIG_ENDIAN; | |
1104 | ||
1105 | outof_target = operand_subword (target, outof_word, 1, mode); | |
1106 | into_target = operand_subword (target, 1 - outof_word, 1, mode); | |
1107 | ||
1108 | outof_input = operand_subword_force (op0, outof_word, mode); | |
1109 | into_input = operand_subword_force (op0, 1 - outof_word, mode); | |
1110 | ||
1111 | if (shift_count == BITS_PER_WORD) | |
1112 | { | |
1113 | /* This is just a word swap. */ | |
1114 | emit_move_insn (outof_target, into_input); | |
1115 | emit_move_insn (into_target, outof_input); | |
70864443 | 1116 | inter = const0_rtx; |
8c597270 JW |
1117 | } |
1118 | else | |
1119 | { | |
1120 | rtx into_temp1, into_temp2, outof_temp1, outof_temp2; | |
1121 | rtx first_shift_count, second_shift_count; | |
1122 | optab reverse_unsigned_shift, unsigned_shift; | |
1123 | ||
1124 | reverse_unsigned_shift = (left_shift ^ (shift_count < BITS_PER_WORD) | |
1125 | ? lshr_optab : ashl_optab); | |
1126 | ||
1127 | unsigned_shift = (left_shift ^ (shift_count < BITS_PER_WORD) | |
1128 | ? ashl_optab : lshr_optab); | |
1129 | ||
1130 | if (shift_count > BITS_PER_WORD) | |
1131 | { | |
1132 | first_shift_count = GEN_INT (shift_count - BITS_PER_WORD); | |
7e1a450d | 1133 | second_shift_count = GEN_INT (2 * BITS_PER_WORD - shift_count); |
8c597270 JW |
1134 | } |
1135 | else | |
1136 | { | |
1137 | first_shift_count = GEN_INT (BITS_PER_WORD - shift_count); | |
1138 | second_shift_count = GEN_INT (shift_count); | |
1139 | } | |
1140 | ||
1141 | into_temp1 = expand_binop (word_mode, unsigned_shift, | |
1142 | outof_input, first_shift_count, | |
70864443 | 1143 | NULL_RTX, unsignedp, next_methods); |
8c597270 JW |
1144 | into_temp2 = expand_binop (word_mode, reverse_unsigned_shift, |
1145 | into_input, second_shift_count, | |
5be5c8d4 | 1146 | NULL_RTX, unsignedp, next_methods); |
70864443 RK |
1147 | |
1148 | if (into_temp1 != 0 && into_temp2 != 0) | |
1149 | inter = expand_binop (word_mode, ior_optab, into_temp1, into_temp2, | |
1150 | into_target, unsignedp, next_methods); | |
1151 | else | |
1152 | inter = 0; | |
1153 | ||
cb5b00cf | 1154 | if (inter != 0 && inter != into_target) |
70864443 | 1155 | emit_move_insn (into_target, inter); |
8c597270 JW |
1156 | |
1157 | outof_temp1 = expand_binop (word_mode, unsigned_shift, | |
1158 | into_input, first_shift_count, | |
70864443 | 1159 | NULL_RTX, unsignedp, next_methods); |
8c597270 JW |
1160 | outof_temp2 = expand_binop (word_mode, reverse_unsigned_shift, |
1161 | outof_input, second_shift_count, | |
5be5c8d4 | 1162 | NULL_RTX, unsignedp, next_methods); |
70864443 RK |
1163 | |
1164 | if (inter != 0 && outof_temp1 != 0 && outof_temp2 != 0) | |
1165 | inter = expand_binop (word_mode, ior_optab, | |
1166 | outof_temp1, outof_temp2, | |
1167 | outof_target, unsignedp, next_methods); | |
1168 | ||
cb5b00cf | 1169 | if (inter != 0 && inter != outof_target) |
70864443 | 1170 | emit_move_insn (outof_target, inter); |
8c597270 JW |
1171 | } |
1172 | ||
1173 | insns = get_insns (); | |
1174 | end_sequence (); | |
1175 | ||
70864443 RK |
1176 | if (inter != 0) |
1177 | { | |
1178 | if (binoptab->code != UNKNOWN) | |
9e6a5703 | 1179 | equiv_value = gen_rtx_fmt_ee (binoptab->code, mode, op0, op1); |
70864443 RK |
1180 | else |
1181 | equiv_value = 0; | |
8c597270 | 1182 | |
70864443 RK |
1183 | /* We can't make this a no conflict block if this is a word swap, |
1184 | because the word swap case fails if the input and output values | |
1185 | are in the same register. */ | |
1186 | if (shift_count != BITS_PER_WORD) | |
1187 | emit_no_conflict_block (insns, target, op0, op1, equiv_value); | |
1188 | else | |
2f937369 | 1189 | emit_insn (insns); |
70864443 RK |
1190 | |
1191 | ||
1192 | return target; | |
1193 | } | |
8c597270 JW |
1194 | } |
1195 | ||
77c9c6c2 RK |
1196 | /* These can be done a word at a time by propagating carries. */ |
1197 | if ((binoptab == add_optab || binoptab == sub_optab) | |
1198 | && class == MODE_INT | |
1199 | && GET_MODE_SIZE (mode) >= 2 * UNITS_PER_WORD | |
34e56753 | 1200 | && binoptab->handlers[(int) word_mode].insn_code != CODE_FOR_nothing) |
77c9c6c2 | 1201 | { |
e2500fed | 1202 | unsigned int i; |
77c9c6c2 | 1203 | optab otheroptab = binoptab == add_optab ? sub_optab : add_optab; |
a4b5414c | 1204 | const unsigned int nwords = GET_MODE_BITSIZE (mode) / BITS_PER_WORD; |
07444f1d | 1205 | rtx carry_in = NULL_RTX, carry_out = NULL_RTX; |
64de6c0a | 1206 | rtx xop0, xop1, xtarget; |
77c9c6c2 RK |
1207 | |
1208 | /* We can handle either a 1 or -1 value for the carry. If STORE_FLAG | |
1209 | value is one of those, use it. Otherwise, use 1 since it is the | |
1210 | one easiest to get. */ | |
1211 | #if STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1 | |
1212 | int normalizep = STORE_FLAG_VALUE; | |
1213 | #else | |
1214 | int normalizep = 1; | |
1215 | #endif | |
1216 | ||
1217 | /* Prepare the operands. */ | |
cee85023 RS |
1218 | xop0 = force_reg (mode, op0); |
1219 | xop1 = force_reg (mode, op1); | |
77c9c6c2 | 1220 | |
64de6c0a DE |
1221 | xtarget = gen_reg_rtx (mode); |
1222 | ||
f8cfc6aa | 1223 | if (target == 0 || !REG_P (target)) |
64de6c0a | 1224 | target = xtarget; |
77c9c6c2 | 1225 | |
af2cc4dd | 1226 | /* Indicate for flow that the entire target reg is being set. */ |
f8cfc6aa | 1227 | if (REG_P (target)) |
64de6c0a | 1228 | emit_insn (gen_rtx_CLOBBER (VOIDmode, xtarget)); |
af2cc4dd | 1229 | |
77c9c6c2 RK |
1230 | /* Do the actual arithmetic. */ |
1231 | for (i = 0; i < nwords; i++) | |
1232 | { | |
1233 | int index = (WORDS_BIG_ENDIAN ? nwords - i - 1 : i); | |
64de6c0a | 1234 | rtx target_piece = operand_subword (xtarget, index, 1, mode); |
cee85023 RS |
1235 | rtx op0_piece = operand_subword_force (xop0, index, mode); |
1236 | rtx op1_piece = operand_subword_force (xop1, index, mode); | |
77c9c6c2 RK |
1237 | rtx x; |
1238 | ||
1239 | /* Main add/subtract of the input operands. */ | |
34e56753 | 1240 | x = expand_binop (word_mode, binoptab, |
77c9c6c2 | 1241 | op0_piece, op1_piece, |
70864443 | 1242 | target_piece, unsignedp, next_methods); |
77c9c6c2 RK |
1243 | if (x == 0) |
1244 | break; | |
1245 | ||
1246 | if (i + 1 < nwords) | |
1247 | { | |
1248 | /* Store carry from main add/subtract. */ | |
34e56753 | 1249 | carry_out = gen_reg_rtx (word_mode); |
23357404 TG |
1250 | carry_out = emit_store_flag_force (carry_out, |
1251 | (binoptab == add_optab | |
b30f05db | 1252 | ? LT : GT), |
23357404 TG |
1253 | x, op0_piece, |
1254 | word_mode, 1, normalizep); | |
77c9c6c2 RK |
1255 | } |
1256 | ||
1257 | if (i > 0) | |
1258 | { | |
859cb4d8 | 1259 | rtx newx; |
0c20a65f | 1260 | |
77c9c6c2 | 1261 | /* Add/subtract previous carry to main result. */ |
859cb4d8 GK |
1262 | newx = expand_binop (word_mode, |
1263 | normalizep == 1 ? binoptab : otheroptab, | |
1264 | x, carry_in, | |
1265 | NULL_RTX, 1, next_methods); | |
77c9c6c2 RK |
1266 | |
1267 | if (i + 1 < nwords) | |
1268 | { | |
77c9c6c2 | 1269 | /* Get out carry from adding/subtracting carry in. */ |
859cb4d8 | 1270 | rtx carry_tmp = gen_reg_rtx (word_mode); |
23357404 | 1271 | carry_tmp = emit_store_flag_force (carry_tmp, |
859cb4d8 GK |
1272 | (binoptab == add_optab |
1273 | ? LT : GT), | |
1274 | newx, x, | |
23357404 | 1275 | word_mode, 1, normalizep); |
70864443 | 1276 | |
77c9c6c2 | 1277 | /* Logical-ior the two poss. carry together. */ |
34e56753 | 1278 | carry_out = expand_binop (word_mode, ior_optab, |
77c9c6c2 | 1279 | carry_out, carry_tmp, |
70864443 RK |
1280 | carry_out, 0, next_methods); |
1281 | if (carry_out == 0) | |
77c9c6c2 RK |
1282 | break; |
1283 | } | |
859cb4d8 | 1284 | emit_move_insn (target_piece, newx); |
77c9c6c2 RK |
1285 | } |
1286 | ||
1287 | carry_in = carry_out; | |
0c20a65f | 1288 | } |
77c9c6c2 | 1289 | |
e2500fed | 1290 | if (i == GET_MODE_BITSIZE (mode) / (unsigned) BITS_PER_WORD) |
77c9c6c2 | 1291 | { |
d0ccc658 RK |
1292 | if (mov_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing |
1293 | || ! rtx_equal_p (target, xtarget)) | |
02214a5c | 1294 | { |
64de6c0a | 1295 | rtx temp = emit_move_insn (target, xtarget); |
70864443 | 1296 | |
5fa671cf | 1297 | set_unique_reg_note (temp, |
0c20a65f | 1298 | REG_EQUAL, |
5fa671cf AM |
1299 | gen_rtx_fmt_ee (binoptab->code, mode, |
1300 | copy_rtx (xop0), | |
1301 | copy_rtx (xop1))); | |
02214a5c | 1302 | } |
2cd622c3 AO |
1303 | else |
1304 | target = xtarget; | |
c5c76735 | 1305 | |
77c9c6c2 RK |
1306 | return target; |
1307 | } | |
c5c76735 | 1308 | |
77c9c6c2 RK |
1309 | else |
1310 | delete_insns_since (last); | |
1311 | } | |
1312 | ||
1313 | /* If we want to multiply two two-word values and have normal and widening | |
1314 | multiplies of single-word values, we can do this with three smaller | |
1315 | multiplications. Note that we do not make a REG_NO_CONFLICT block here | |
0c20a65f | 1316 | because we are not operating on one word at a time. |
77c9c6c2 RK |
1317 | |
1318 | The multiplication proceeds as follows: | |
34e56753 RS |
1319 | _______________________ |
1320 | [__op0_high_|__op0_low__] | |
1321 | _______________________ | |
6ffe0821 | 1322 | * [__op1_high_|__op1_low__] |
34e56753 RS |
1323 | _______________________________________________ |
1324 | _______________________ | |
6ffe0821 | 1325 | (1) [__op0_low__*__op1_low__] |
34e56753 | 1326 | _______________________ |
6ffe0821 | 1327 | (2a) [__op0_low__*__op1_high_] |
34e56753 | 1328 | _______________________ |
6ffe0821 | 1329 | (2b) [__op0_high_*__op1_low__] |
34e56753 RS |
1330 | _______________________ |
1331 | (3) [__op0_high_*__op1_high_] | |
77c9c6c2 RK |
1332 | |
1333 | ||
1334 | This gives a 4-word result. Since we are only interested in the | |
1335 | lower 2 words, partial result (3) and the upper words of (2a) and | |
1336 | (2b) don't need to be calculated. Hence (2a) and (2b) can be | |
1337 | calculated using non-widening multiplication. | |
1338 | ||
1339 | (1), however, needs to be calculated with an unsigned widening | |
1340 | multiplication. If this operation is not directly supported we | |
1341 | try using a signed widening multiplication and adjust the result. | |
1342 | This adjustment works as follows: | |
1343 | ||
1344 | If both operands are positive then no adjustment is needed. | |
1345 | ||
1346 | If the operands have different signs, for example op0_low < 0 and | |
1347 | op1_low >= 0, the instruction treats the most significant bit of | |
1348 | op0_low as a sign bit instead of a bit with significance | |
1349 | 2**(BITS_PER_WORD-1), i.e. the instruction multiplies op1_low | |
1350 | with 2**BITS_PER_WORD - op0_low, and two's complements the | |
1351 | result. Conclusion: We need to add op1_low * 2**BITS_PER_WORD to | |
1352 | the result. | |
1353 | ||
1354 | Similarly, if both operands are negative, we need to add | |
1355 | (op0_low + op1_low) * 2**BITS_PER_WORD. | |
1356 | ||
1357 | We use a trick to adjust quickly. We logically shift op0_low right | |
1358 | (op1_low) BITS_PER_WORD-1 steps to get 0 or 1, and add this to | |
1359 | op0_high (op1_high) before it is used to calculate 2b (2a). If no | |
1360 | logical shift exists, we do an arithmetic right shift and subtract | |
1361 | the 0 or -1. */ | |
1362 | ||
1363 | if (binoptab == smul_optab | |
1364 | && class == MODE_INT | |
1365 | && GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD | |
34e56753 RS |
1366 | && smul_optab->handlers[(int) word_mode].insn_code != CODE_FOR_nothing |
1367 | && add_optab->handlers[(int) word_mode].insn_code != CODE_FOR_nothing | |
77c9c6c2 RK |
1368 | && ((umul_widen_optab->handlers[(int) mode].insn_code |
1369 | != CODE_FOR_nothing) | |
1370 | || (smul_widen_optab->handlers[(int) mode].insn_code | |
1371 | != CODE_FOR_nothing))) | |
1372 | { | |
1373 | int low = (WORDS_BIG_ENDIAN ? 1 : 0); | |
1374 | int high = (WORDS_BIG_ENDIAN ? 0 : 1); | |
1375 | rtx op0_high = operand_subword_force (op0, high, mode); | |
1376 | rtx op0_low = operand_subword_force (op0, low, mode); | |
1377 | rtx op1_high = operand_subword_force (op1, high, mode); | |
1378 | rtx op1_low = operand_subword_force (op1, low, mode); | |
1379 | rtx product = 0; | |
07444f1d TM |
1380 | rtx op0_xhigh = NULL_RTX; |
1381 | rtx op1_xhigh = NULL_RTX; | |
77c9c6c2 RK |
1382 | |
1383 | /* If the target is the same as one of the inputs, don't use it. This | |
1384 | prevents problems with the REG_EQUAL note. */ | |
f96d689c | 1385 | if (target == op0 || target == op1 |
f8cfc6aa | 1386 | || (target != 0 && !REG_P (target))) |
77c9c6c2 RK |
1387 | target = 0; |
1388 | ||
1389 | /* Multiply the two lower words to get a double-word product. | |
1390 | If unsigned widening multiplication is available, use that; | |
1391 | otherwise use the signed form and compensate. */ | |
1392 | ||
1393 | if (umul_widen_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing) | |
1394 | { | |
1395 | product = expand_binop (mode, umul_widen_optab, op0_low, op1_low, | |
1396 | target, 1, OPTAB_DIRECT); | |
1397 | ||
1398 | /* If we didn't succeed, delete everything we did so far. */ | |
1399 | if (product == 0) | |
1400 | delete_insns_since (last); | |
1401 | else | |
1402 | op0_xhigh = op0_high, op1_xhigh = op1_high; | |
1403 | } | |
1404 | ||
1405 | if (product == 0 | |
1406 | && smul_widen_optab->handlers[(int) mode].insn_code | |
1407 | != CODE_FOR_nothing) | |
1408 | { | |
b1ec3c92 | 1409 | rtx wordm1 = GEN_INT (BITS_PER_WORD - 1); |
77c9c6c2 RK |
1410 | product = expand_binop (mode, smul_widen_optab, op0_low, op1_low, |
1411 | target, 1, OPTAB_DIRECT); | |
34e56753 | 1412 | op0_xhigh = expand_binop (word_mode, lshr_optab, op0_low, wordm1, |
70864443 | 1413 | NULL_RTX, 1, next_methods); |
77c9c6c2 | 1414 | if (op0_xhigh) |
34e56753 | 1415 | op0_xhigh = expand_binop (word_mode, add_optab, op0_high, |
70864443 | 1416 | op0_xhigh, op0_xhigh, 0, next_methods); |
77c9c6c2 RK |
1417 | else |
1418 | { | |
34e56753 | 1419 | op0_xhigh = expand_binop (word_mode, ashr_optab, op0_low, wordm1, |
70864443 | 1420 | NULL_RTX, 0, next_methods); |
77c9c6c2 | 1421 | if (op0_xhigh) |
34e56753 | 1422 | op0_xhigh = expand_binop (word_mode, sub_optab, op0_high, |
77c9c6c2 | 1423 | op0_xhigh, op0_xhigh, 0, |
70864443 | 1424 | next_methods); |
77c9c6c2 RK |
1425 | } |
1426 | ||
34e56753 | 1427 | op1_xhigh = expand_binop (word_mode, lshr_optab, op1_low, wordm1, |
70864443 | 1428 | NULL_RTX, 1, next_methods); |
77c9c6c2 | 1429 | if (op1_xhigh) |
34e56753 | 1430 | op1_xhigh = expand_binop (word_mode, add_optab, op1_high, |
70864443 | 1431 | op1_xhigh, op1_xhigh, 0, next_methods); |
77c9c6c2 RK |
1432 | else |
1433 | { | |
34e56753 | 1434 | op1_xhigh = expand_binop (word_mode, ashr_optab, op1_low, wordm1, |
70864443 | 1435 | NULL_RTX, 0, next_methods); |
77c9c6c2 | 1436 | if (op1_xhigh) |
34e56753 | 1437 | op1_xhigh = expand_binop (word_mode, sub_optab, op1_high, |
77c9c6c2 | 1438 | op1_xhigh, op1_xhigh, 0, |
70864443 | 1439 | next_methods); |
77c9c6c2 RK |
1440 | } |
1441 | } | |
1442 | ||
1443 | /* If we have been able to directly compute the product of the | |
1444 | low-order words of the operands and perform any required adjustments | |
1445 | of the operands, we proceed by trying two more multiplications | |
1446 | and then computing the appropriate sum. | |
1447 | ||
1448 | We have checked above that the required addition is provided. | |
1449 | Full-word addition will normally always succeed, especially if | |
1450 | it is provided at all, so we don't worry about its failure. The | |
1451 | multiplication may well fail, however, so we do handle that. */ | |
1452 | ||
1453 | if (product && op0_xhigh && op1_xhigh) | |
1454 | { | |
77c9c6c2 | 1455 | rtx product_high = operand_subword (product, high, 1, mode); |
b1ec3c92 CH |
1456 | rtx temp = expand_binop (word_mode, binoptab, op0_low, op1_xhigh, |
1457 | NULL_RTX, 0, OPTAB_DIRECT); | |
77c9c6c2 | 1458 | |
c7539aa0 JL |
1459 | if (!REG_P (product_high)) |
1460 | product_high = force_reg (word_mode, product_high); | |
1461 | ||
70864443 RK |
1462 | if (temp != 0) |
1463 | temp = expand_binop (word_mode, add_optab, temp, product_high, | |
1464 | product_high, 0, next_methods); | |
77c9c6c2 | 1465 | |
70864443 RK |
1466 | if (temp != 0 && temp != product_high) |
1467 | emit_move_insn (product_high, temp); | |
1468 | ||
1469 | if (temp != 0) | |
0c20a65f | 1470 | temp = expand_binop (word_mode, binoptab, op1_low, op0_xhigh, |
70864443 RK |
1471 | NULL_RTX, 0, OPTAB_DIRECT); |
1472 | ||
1473 | if (temp != 0) | |
1474 | temp = expand_binop (word_mode, add_optab, temp, | |
1475 | product_high, product_high, | |
1476 | 0, next_methods); | |
77c9c6c2 | 1477 | |
70864443 RK |
1478 | if (temp != 0 && temp != product_high) |
1479 | emit_move_insn (product_high, temp); | |
77c9c6c2 | 1480 | |
c7539aa0 JL |
1481 | emit_move_insn (operand_subword (product, high, 1, mode), product_high); |
1482 | ||
70864443 RK |
1483 | if (temp != 0) |
1484 | { | |
02214a5c RK |
1485 | if (mov_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing) |
1486 | { | |
1487 | temp = emit_move_insn (product, product); | |
5fa671cf | 1488 | set_unique_reg_note (temp, |
0c20a65f | 1489 | REG_EQUAL, |
5fa671cf AM |
1490 | gen_rtx_fmt_ee (MULT, mode, |
1491 | copy_rtx (op0), | |
1492 | copy_rtx (op1))); | |
02214a5c | 1493 | } |
c5c76735 | 1494 | |
77c9c6c2 RK |
1495 | return product; |
1496 | } | |
1497 | } | |
1498 | ||
1499 | /* If we get here, we couldn't do it for some reason even though we | |
1500 | originally thought we could. Delete anything we've emitted in | |
1501 | trying to do it. */ | |
1502 | ||
1503 | delete_insns_since (last); | |
1504 | } | |
1505 | ||
cb2a532e AH |
1506 | /* Open-code the vector operations if we have no hardware support |
1507 | for them. */ | |
1508 | if (class == MODE_VECTOR_INT || class == MODE_VECTOR_FLOAT) | |
1509 | return expand_vector_binop (mode, binoptab, op0, op1, target, | |
1510 | unsignedp, methods); | |
1511 | ||
b818abb0 RS |
1512 | /* We need to open-code the complex type operations: '+, -, * and /' */ |
1513 | ||
1514 | /* At this point we allow operations between two similar complex | |
1515 | numbers, and also if one of the operands is not a complex number | |
1516 | but rather of MODE_FLOAT or MODE_INT. However, the caller | |
1517 | must make sure that the MODE of the non-complex operand matches | |
6f43c157 | 1518 | the SUBMODE of the complex operand. */ |
b818abb0 RS |
1519 | |
1520 | if (class == MODE_COMPLEX_FLOAT || class == MODE_COMPLEX_INT) | |
6f43c157 | 1521 | { |
70864443 RK |
1522 | rtx real0 = 0, imag0 = 0; |
1523 | rtx real1 = 0, imag1 = 0; | |
1524 | rtx realr, imagr, res; | |
c7d91a94 | 1525 | rtx seq, result; |
70864443 | 1526 | int ok = 0; |
b818abb0 | 1527 | |
f9da5064 | 1528 | /* Find the correct mode for the real and imaginary parts. */ |
c7d91a94 | 1529 | enum machine_mode submode = GET_MODE_INNER (mode); |
b818abb0 RS |
1530 | |
1531 | if (submode == BLKmode) | |
1532 | abort (); | |
1533 | ||
b818abb0 RS |
1534 | start_sequence (); |
1535 | ||
b818abb0 RS |
1536 | if (GET_MODE (op0) == mode) |
1537 | { | |
c64f913e | 1538 | real0 = gen_realpart (submode, op0); |
decdfa82 | 1539 | imag0 = gen_imagpart (submode, op0); |
b818abb0 RS |
1540 | } |
1541 | else | |
1542 | real0 = op0; | |
1543 | ||
1544 | if (GET_MODE (op1) == mode) | |
1545 | { | |
c64f913e | 1546 | real1 = gen_realpart (submode, op1); |
decdfa82 | 1547 | imag1 = gen_imagpart (submode, op1); |
b818abb0 RS |
1548 | } |
1549 | else | |
1550 | real1 = op1; | |
1551 | ||
c0fe508e | 1552 | if (real0 == 0 || real1 == 0 || ! (imag0 != 0 || imag1 != 0)) |
b818abb0 RS |
1553 | abort (); |
1554 | ||
c7d91a94 RS |
1555 | result = gen_reg_rtx (mode); |
1556 | realr = gen_realpart (submode, result); | |
1557 | imagr = gen_imagpart (submode, result); | |
1558 | ||
6f43c157 RS |
1559 | switch (binoptab->code) |
1560 | { | |
1561 | case PLUS: | |
96f153da | 1562 | /* (a+ib) + (c+id) = (a+c) + i(b+d) */ |
6f43c157 | 1563 | case MINUS: |
96f153da | 1564 | /* (a+ib) - (c+id) = (a-c) + i(b-d) */ |
b818abb0 RS |
1565 | res = expand_binop (submode, binoptab, real0, real1, |
1566 | realr, unsignedp, methods); | |
70864443 RK |
1567 | |
1568 | if (res == 0) | |
1569 | break; | |
1570 | else if (res != realr) | |
b818abb0 RS |
1571 | emit_move_insn (realr, res); |
1572 | ||
086bbd21 | 1573 | if (imag0 != 0 && imag1 != 0) |
b818abb0 RS |
1574 | res = expand_binop (submode, binoptab, imag0, imag1, |
1575 | imagr, unsignedp, methods); | |
086bbd21 | 1576 | else if (imag0 != 0) |
b818abb0 RS |
1577 | res = imag0; |
1578 | else if (binoptab->code == MINUS) | |
91ce572a CC |
1579 | res = expand_unop (submode, |
1580 | binoptab == subv_optab ? negv_optab : neg_optab, | |
1581 | imag1, imagr, unsignedp); | |
b818abb0 RS |
1582 | else |
1583 | res = imag1; | |
1584 | ||
70864443 RK |
1585 | if (res == 0) |
1586 | break; | |
1587 | else if (res != imagr) | |
b818abb0 | 1588 | emit_move_insn (imagr, res); |
70864443 RK |
1589 | |
1590 | ok = 1; | |
b818abb0 | 1591 | break; |
6f43c157 RS |
1592 | |
1593 | case MULT: | |
b818abb0 RS |
1594 | /* (a+ib) * (c+id) = (ac-bd) + i(ad+cb) */ |
1595 | ||
086bbd21 | 1596 | if (imag0 != 0 && imag1 != 0) |
b818abb0 | 1597 | { |
70864443 RK |
1598 | rtx temp1, temp2; |
1599 | ||
54e7b5e6 RS |
1600 | /* Don't fetch these from memory more than once. */ |
1601 | real0 = force_reg (submode, real0); | |
1602 | real1 = force_reg (submode, real1); | |
1603 | imag0 = force_reg (submode, imag0); | |
1604 | imag1 = force_reg (submode, imag1); | |
1605 | ||
70864443 RK |
1606 | temp1 = expand_binop (submode, binoptab, real0, real1, NULL_RTX, |
1607 | unsignedp, methods); | |
1608 | ||
1609 | temp2 = expand_binop (submode, binoptab, imag0, imag1, NULL_RTX, | |
1610 | unsignedp, methods); | |
1611 | ||
1612 | if (temp1 == 0 || temp2 == 0) | |
1613 | break; | |
1614 | ||
91ce572a CC |
1615 | res = (expand_binop |
1616 | (submode, | |
1617 | binoptab == smulv_optab ? subv_optab : sub_optab, | |
1618 | temp1, temp2, realr, unsignedp, methods)); | |
b818abb0 | 1619 | |
70864443 RK |
1620 | if (res == 0) |
1621 | break; | |
1622 | else if (res != realr) | |
54e7b5e6 | 1623 | emit_move_insn (realr, res); |
b818abb0 | 1624 | |
70864443 RK |
1625 | temp1 = expand_binop (submode, binoptab, real0, imag1, |
1626 | NULL_RTX, unsignedp, methods); | |
1627 | ||
df8ca70e RS |
1628 | /* Avoid expanding redundant multiplication for the common |
1629 | case of squaring a complex number. */ | |
1630 | if (rtx_equal_p (real0, real1) && rtx_equal_p (imag0, imag1)) | |
1631 | temp2 = temp1; | |
1632 | else | |
1633 | temp2 = expand_binop (submode, binoptab, real1, imag0, | |
1634 | NULL_RTX, unsignedp, methods); | |
70864443 RK |
1635 | |
1636 | if (temp1 == 0 || temp2 == 0) | |
7e1a450d | 1637 | break; |
1c63cc82 | 1638 | |
91ce572a CC |
1639 | res = (expand_binop |
1640 | (submode, | |
1641 | binoptab == smulv_optab ? addv_optab : add_optab, | |
1642 | temp1, temp2, imagr, unsignedp, methods)); | |
70864443 RK |
1643 | |
1644 | if (res == 0) | |
1645 | break; | |
1646 | else if (res != imagr) | |
b818abb0 | 1647 | emit_move_insn (imagr, res); |
70864443 RK |
1648 | |
1649 | ok = 1; | |
b818abb0 RS |
1650 | } |
1651 | else | |
1652 | { | |
54e7b5e6 RS |
1653 | /* Don't fetch these from memory more than once. */ |
1654 | real0 = force_reg (submode, real0); | |
1655 | real1 = force_reg (submode, real1); | |
1656 | ||
96f153da RS |
1657 | res = expand_binop (submode, binoptab, real0, real1, |
1658 | realr, unsignedp, methods); | |
70864443 RK |
1659 | if (res == 0) |
1660 | break; | |
1661 | else if (res != realr) | |
b818abb0 RS |
1662 | emit_move_insn (realr, res); |
1663 | ||
086bbd21 | 1664 | if (imag0 != 0) |
b818abb0 RS |
1665 | res = expand_binop (submode, binoptab, |
1666 | real1, imag0, imagr, unsignedp, methods); | |
1667 | else | |
1668 | res = expand_binop (submode, binoptab, | |
1669 | real0, imag1, imagr, unsignedp, methods); | |
70864443 RK |
1670 | |
1671 | if (res == 0) | |
1672 | break; | |
1673 | else if (res != imagr) | |
b818abb0 | 1674 | emit_move_insn (imagr, res); |
70864443 RK |
1675 | |
1676 | ok = 1; | |
b818abb0 RS |
1677 | } |
1678 | break; | |
6f43c157 RS |
1679 | |
1680 | case DIV: | |
96f153da | 1681 | /* (a+ib) / (c+id) = ((ac+bd)/(cc+dd)) + i((bc-ad)/(cc+dd)) */ |
0c20a65f | 1682 | |
086bbd21 | 1683 | if (imag1 == 0) |
70864443 RK |
1684 | { |
1685 | /* (a+ib) / (c+i0) = (a/c) + i(b/c) */ | |
54e7b5e6 RS |
1686 | |
1687 | /* Don't fetch these from memory more than once. */ | |
1688 | real1 = force_reg (submode, real1); | |
1689 | ||
96f153da | 1690 | /* Simply divide the real and imaginary parts by `c' */ |
2140ed5b RK |
1691 | if (class == MODE_COMPLEX_FLOAT) |
1692 | res = expand_binop (submode, binoptab, real0, real1, | |
1693 | realr, unsignedp, methods); | |
1694 | else | |
1695 | res = expand_divmod (0, TRUNC_DIV_EXPR, submode, | |
1696 | real0, real1, realr, unsignedp); | |
1697 | ||
70864443 RK |
1698 | if (res == 0) |
1699 | break; | |
1700 | else if (res != realr) | |
b818abb0 RS |
1701 | emit_move_insn (realr, res); |
1702 | ||
2140ed5b RK |
1703 | if (class == MODE_COMPLEX_FLOAT) |
1704 | res = expand_binop (submode, binoptab, imag0, real1, | |
1705 | imagr, unsignedp, methods); | |
1706 | else | |
1707 | res = expand_divmod (0, TRUNC_DIV_EXPR, submode, | |
1708 | imag0, real1, imagr, unsignedp); | |
1709 | ||
70864443 RK |
1710 | if (res == 0) |
1711 | break; | |
1712 | else if (res != imagr) | |
b818abb0 | 1713 | emit_move_insn (imagr, res); |
b818abb0 | 1714 | |
70864443 RK |
1715 | ok = 1; |
1716 | } | |
1717 | else | |
1718 | { | |
c64f913e | 1719 | switch (flag_complex_divide_method) |
70864443 | 1720 | { |
c64f913e CB |
1721 | case 0: |
1722 | ok = expand_cmplxdiv_straight (real0, real1, imag0, imag1, | |
1723 | realr, imagr, submode, | |
1724 | unsignedp, methods, | |
1725 | class, binoptab); | |
1726 | break; | |
41b19f3e | 1727 | |
c64f913e CB |
1728 | case 1: |
1729 | ok = expand_cmplxdiv_wide (real0, real1, imag0, imag1, | |
1730 | realr, imagr, submode, | |
1731 | unsignedp, methods, | |
1732 | class, binoptab); | |
1733 | break; | |
70864443 | 1734 | |
c64f913e CB |
1735 | default: |
1736 | abort (); | |
b818abb0 | 1737 | } |
b818abb0 RS |
1738 | } |
1739 | break; | |
0c20a65f | 1740 | |
b818abb0 RS |
1741 | default: |
1742 | abort (); | |
1743 | } | |
1744 | ||
c15886da | 1745 | seq = get_insns (); |
b818abb0 RS |
1746 | end_sequence (); |
1747 | ||
70864443 RK |
1748 | if (ok) |
1749 | { | |
c7d91a94 RS |
1750 | rtx equiv = gen_rtx_fmt_ee (binoptab->code, mode, |
1751 | copy_rtx (op0), copy_rtx (op1)); | |
1752 | emit_no_conflict_block (seq, result, op0, op1, equiv); | |
1753 | return result; | |
70864443 | 1754 | } |
b818abb0 | 1755 | } |
b818abb0 | 1756 | |
77c9c6c2 RK |
1757 | /* It can't be open-coded in this mode. |
1758 | Use a library call if one is available and caller says that's ok. */ | |
1759 | ||
1760 | if (binoptab->handlers[(int) mode].libfunc | |
1761 | && (methods == OPTAB_LIB || methods == OPTAB_LIB_WIDEN)) | |
1762 | { | |
1763 | rtx insns; | |
0bbb7f4d RS |
1764 | rtx op1x = op1; |
1765 | enum machine_mode op1_mode = mode; | |
9a7f678c | 1766 | rtx value; |
77c9c6c2 RK |
1767 | |
1768 | start_sequence (); | |
1769 | ||
0bbb7f4d RS |
1770 | if (shift_op) |
1771 | { | |
1772 | op1_mode = word_mode; | |
1773 | /* Specify unsigned here, | |
1774 | since negative shift counts are meaningless. */ | |
1775 | op1x = convert_to_mode (word_mode, op1, 1); | |
1776 | } | |
1777 | ||
82f0e2cc RK |
1778 | if (GET_MODE (op0) != VOIDmode |
1779 | && GET_MODE (op0) != mode) | |
5035bbfe TG |
1780 | op0 = convert_to_mode (mode, op0, unsignedp); |
1781 | ||
77c9c6c2 RK |
1782 | /* Pass 1 for NO_QUEUE so we don't lose any increments |
1783 | if the libcall is cse'd or moved. */ | |
9a7f678c | 1784 | value = emit_library_call_value (binoptab->handlers[(int) mode].libfunc, |
ebb1b59a | 1785 | NULL_RTX, LCT_CONST, mode, 2, |
9a7f678c | 1786 | op0, mode, op1x, op1_mode); |
77c9c6c2 RK |
1787 | |
1788 | insns = get_insns (); | |
1789 | end_sequence (); | |
1790 | ||
1791 | target = gen_reg_rtx (mode); | |
9a7f678c | 1792 | emit_libcall_block (insns, target, value, |
9e6a5703 | 1793 | gen_rtx_fmt_ee (binoptab->code, mode, op0, op1)); |
77c9c6c2 RK |
1794 | |
1795 | return target; | |
1796 | } | |
1797 | ||
1798 | delete_insns_since (last); | |
1799 | ||
1800 | /* It can't be done in this mode. Can we do it in a wider mode? */ | |
1801 | ||
1802 | if (! (methods == OPTAB_WIDEN || methods == OPTAB_LIB_WIDEN | |
1803 | || methods == OPTAB_MUST_WIDEN)) | |
abd418d3 RS |
1804 | { |
1805 | /* Caller says, don't even try. */ | |
1806 | delete_insns_since (entry_last); | |
1807 | return 0; | |
1808 | } | |
77c9c6c2 RK |
1809 | |
1810 | /* Compute the value of METHODS to pass to recursive calls. | |
1811 | Don't allow widening to be tried recursively. */ | |
1812 | ||
1813 | methods = (methods == OPTAB_LIB_WIDEN ? OPTAB_LIB : OPTAB_DIRECT); | |
1814 | ||
34e56753 RS |
1815 | /* Look for a wider mode of the same class for which it appears we can do |
1816 | the operation. */ | |
77c9c6c2 RK |
1817 | |
1818 | if (class == MODE_INT || class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT) | |
1819 | { | |
34e56753 | 1820 | for (wider_mode = GET_MODE_WIDER_MODE (mode); wider_mode != VOIDmode; |
77c9c6c2 RK |
1821 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) |
1822 | { | |
1823 | if ((binoptab->handlers[(int) wider_mode].insn_code | |
1824 | != CODE_FOR_nothing) | |
1825 | || (methods == OPTAB_LIB | |
1826 | && binoptab->handlers[(int) wider_mode].libfunc)) | |
1827 | { | |
1828 | rtx xop0 = op0, xop1 = op1; | |
1829 | int no_extend = 0; | |
1830 | ||
34e56753 | 1831 | /* For certain integer operations, we need not actually extend |
77c9c6c2 | 1832 | the narrow operands, as long as we will truncate |
835532b8 | 1833 | the results to the same narrowness. */ |
77c9c6c2 | 1834 | |
34e56753 RS |
1835 | if ((binoptab == ior_optab || binoptab == and_optab |
1836 | || binoptab == xor_optab | |
1837 | || binoptab == add_optab || binoptab == sub_optab | |
e5df894b | 1838 | || binoptab == smul_optab || binoptab == ashl_optab) |
835532b8 | 1839 | && class == MODE_INT) |
77c9c6c2 RK |
1840 | no_extend = 1; |
1841 | ||
0661a3de RS |
1842 | xop0 = widen_operand (xop0, wider_mode, mode, |
1843 | unsignedp, no_extend); | |
943cc242 RK |
1844 | |
1845 | /* The second operand of a shift must always be extended. */ | |
0661a3de | 1846 | xop1 = widen_operand (xop1, wider_mode, mode, unsignedp, |
e5df894b | 1847 | no_extend && binoptab != ashl_optab); |
77c9c6c2 | 1848 | |
b1ec3c92 | 1849 | temp = expand_binop (wider_mode, binoptab, xop0, xop1, NULL_RTX, |
77c9c6c2 RK |
1850 | unsignedp, methods); |
1851 | if (temp) | |
1852 | { | |
34e56753 | 1853 | if (class != MODE_INT) |
77c9c6c2 RK |
1854 | { |
1855 | if (target == 0) | |
1856 | target = gen_reg_rtx (mode); | |
1857 | convert_move (target, temp, 0); | |
1858 | return target; | |
1859 | } | |
1860 | else | |
1861 | return gen_lowpart (mode, temp); | |
1862 | } | |
1863 | else | |
1864 | delete_insns_since (last); | |
1865 | } | |
1866 | } | |
1867 | } | |
1868 | ||
abd418d3 | 1869 | delete_insns_since (entry_last); |
77c9c6c2 RK |
1870 | return 0; |
1871 | } | |
cb2a532e AH |
1872 | |
1873 | /* Like expand_binop, but for open-coding vectors binops. */ | |
1874 | ||
1875 | static rtx | |
0c20a65f AJ |
1876 | expand_vector_binop (enum machine_mode mode, optab binoptab, rtx op0, |
1877 | rtx op1, rtx target, int unsignedp, | |
1878 | enum optab_methods methods) | |
cb2a532e | 1879 | { |
34a80643 R |
1880 | enum machine_mode submode, tmode; |
1881 | int size, elts, subsize, subbitsize, i; | |
cb2a532e AH |
1882 | rtx t, a, b, res, seq; |
1883 | enum mode_class class; | |
1884 | ||
1885 | class = GET_MODE_CLASS (mode); | |
1886 | ||
7e1a450d | 1887 | size = GET_MODE_SIZE (mode); |
cb2a532e | 1888 | submode = GET_MODE_INNER (mode); |
cb2a532e | 1889 | |
34a80643 R |
1890 | /* Search for the widest vector mode with the same inner mode that is |
1891 | still narrower than MODE and that allows to open-code this operator. | |
1892 | Note, if we find such a mode and the handler later decides it can't | |
1893 | do the expansion, we'll be called recursively with the narrower mode. */ | |
1894 | for (tmode = GET_CLASS_NARROWEST_MODE (class); | |
1895 | GET_MODE_SIZE (tmode) < GET_MODE_SIZE (mode); | |
1896 | tmode = GET_MODE_WIDER_MODE (tmode)) | |
1897 | { | |
1898 | if (GET_MODE_INNER (tmode) == GET_MODE_INNER (mode) | |
1899 | && binoptab->handlers[(int) tmode].insn_code != CODE_FOR_nothing) | |
1900 | submode = tmode; | |
1901 | } | |
cb2a532e AH |
1902 | |
1903 | switch (binoptab->code) | |
1904 | { | |
34a80643 R |
1905 | case AND: |
1906 | case IOR: | |
1907 | case XOR: | |
1908 | tmode = int_mode_for_mode (mode); | |
1909 | if (tmode != BLKmode) | |
1910 | submode = tmode; | |
cb2a532e AH |
1911 | case PLUS: |
1912 | case MINUS: | |
1913 | case MULT: | |
1914 | case DIV: | |
34a80643 R |
1915 | subsize = GET_MODE_SIZE (submode); |
1916 | subbitsize = GET_MODE_BITSIZE (submode); | |
1917 | elts = size / subsize; | |
1918 | ||
1919 | /* If METHODS is OPTAB_DIRECT, we don't insist on the exact mode, | |
1920 | but that we operate on more than one element at a time. */ | |
1921 | if (subsize == GET_MODE_UNIT_SIZE (mode) && methods == OPTAB_DIRECT) | |
1922 | return 0; | |
1923 | ||
1924 | start_sequence (); | |
1925 | ||
1926 | /* Errors can leave us with a const0_rtx as operand. */ | |
1927 | if (GET_MODE (op0) != mode) | |
1928 | op0 = copy_to_mode_reg (mode, op0); | |
1929 | if (GET_MODE (op1) != mode) | |
1930 | op1 = copy_to_mode_reg (mode, op1); | |
1931 | ||
1932 | if (!target) | |
1933 | target = gen_reg_rtx (mode); | |
1934 | ||
cb2a532e AH |
1935 | for (i = 0; i < elts; ++i) |
1936 | { | |
34a80643 R |
1937 | /* If this is part of a register, and not the first item in the |
1938 | word, we can't store using a SUBREG - that would clobber | |
1939 | previous results. | |
1940 | And storing with a SUBREG is only possible for the least | |
1941 | significant part, hence we can't do it for big endian | |
1942 | (unless we want to permute the evaluation order. */ | |
f8cfc6aa | 1943 | if (REG_P (target) |
34a80643 R |
1944 | && (BYTES_BIG_ENDIAN |
1945 | ? subsize < UNITS_PER_WORD | |
1946 | : ((i * subsize) % UNITS_PER_WORD) != 0)) | |
1947 | t = NULL_RTX; | |
1948 | else | |
1949 | t = simplify_gen_subreg (submode, target, mode, i * subsize); | |
1950 | if (CONSTANT_P (op0)) | |
1951 | a = simplify_gen_subreg (submode, op0, mode, i * subsize); | |
1952 | else | |
1953 | a = extract_bit_field (op0, subbitsize, i * subbitsize, unsignedp, | |
b3520980 | 1954 | NULL_RTX, submode, submode); |
34a80643 R |
1955 | if (CONSTANT_P (op1)) |
1956 | b = simplify_gen_subreg (submode, op1, mode, i * subsize); | |
1957 | else | |
1958 | b = extract_bit_field (op1, subbitsize, i * subbitsize, unsignedp, | |
b3520980 | 1959 | NULL_RTX, submode, submode); |
cb2a532e AH |
1960 | |
1961 | if (binoptab->code == DIV) | |
1962 | { | |
1963 | if (class == MODE_VECTOR_FLOAT) | |
1964 | res = expand_binop (submode, binoptab, a, b, t, | |
1965 | unsignedp, methods); | |
1966 | else | |
1967 | res = expand_divmod (0, TRUNC_DIV_EXPR, submode, | |
1968 | a, b, t, unsignedp); | |
1969 | } | |
1970 | else | |
1971 | res = expand_binop (submode, binoptab, a, b, t, | |
1972 | unsignedp, methods); | |
1973 | ||
1974 | if (res == 0) | |
1975 | break; | |
1976 | ||
34a80643 R |
1977 | if (t) |
1978 | emit_move_insn (t, res); | |
1979 | else | |
b3520980 | 1980 | store_bit_field (target, subbitsize, i * subbitsize, submode, res); |
cb2a532e AH |
1981 | } |
1982 | break; | |
1983 | ||
1984 | default: | |
1985 | abort (); | |
1986 | } | |
1987 | ||
1988 | seq = get_insns (); | |
1989 | end_sequence (); | |
1990 | emit_insn (seq); | |
1991 | ||
1992 | return target; | |
1993 | } | |
1994 | ||
1995 | /* Like expand_unop but for open-coding vector unops. */ | |
1996 | ||
1997 | static rtx | |
0c20a65f AJ |
1998 | expand_vector_unop (enum machine_mode mode, optab unoptab, rtx op0, |
1999 | rtx target, int unsignedp) | |
cb2a532e | 2000 | { |
34a80643 R |
2001 | enum machine_mode submode, tmode; |
2002 | int size, elts, subsize, subbitsize, i; | |
cb2a532e AH |
2003 | rtx t, a, res, seq; |
2004 | ||
7e1a450d | 2005 | size = GET_MODE_SIZE (mode); |
cb2a532e | 2006 | submode = GET_MODE_INNER (mode); |
34a80643 R |
2007 | |
2008 | /* Search for the widest vector mode with the same inner mode that is | |
2009 | still narrower than MODE and that allows to open-code this operator. | |
2010 | Note, if we find such a mode and the handler later decides it can't | |
2011 | do the expansion, we'll be called recursively with the narrower mode. */ | |
2012 | for (tmode = GET_CLASS_NARROWEST_MODE (GET_MODE_CLASS (mode)); | |
2013 | GET_MODE_SIZE (tmode) < GET_MODE_SIZE (mode); | |
2014 | tmode = GET_MODE_WIDER_MODE (tmode)) | |
2015 | { | |
2016 | if (GET_MODE_INNER (tmode) == GET_MODE_INNER (mode) | |
2017 | && unoptab->handlers[(int) tmode].insn_code != CODE_FOR_nothing) | |
2018 | submode = tmode; | |
2019 | } | |
2020 | /* If there is no negate operation, try doing a subtract from zero. */ | |
0d541696 R |
2021 | if (unoptab == neg_optab && GET_MODE_CLASS (submode) == MODE_INT |
2022 | /* Avoid infinite recursion when an | |
2023 | error has left us with the wrong mode. */ | |
2024 | && GET_MODE (op0) == mode) | |
0c20a65f | 2025 | { |
34a80643 R |
2026 | rtx temp; |
2027 | temp = expand_binop (mode, sub_optab, CONST0_RTX (mode), op0, | |
2028 | target, unsignedp, OPTAB_DIRECT); | |
2029 | if (temp) | |
2030 | return temp; | |
2031 | } | |
2032 | ||
2033 | if (unoptab == one_cmpl_optab) | |
2034 | { | |
2035 | tmode = int_mode_for_mode (mode); | |
2036 | if (tmode != BLKmode) | |
2037 | submode = tmode; | |
2038 | } | |
2039 | ||
2040 | subsize = GET_MODE_SIZE (submode); | |
2041 | subbitsize = GET_MODE_BITSIZE (submode); | |
2042 | elts = size / subsize; | |
2043 | ||
2044 | /* Errors can leave us with a const0_rtx as operand. */ | |
2045 | if (GET_MODE (op0) != mode) | |
2046 | op0 = copy_to_mode_reg (mode, op0); | |
cb2a532e AH |
2047 | |
2048 | if (!target) | |
2049 | target = gen_reg_rtx (mode); | |
2050 | ||
2051 | start_sequence (); | |
2052 | ||
cb2a532e AH |
2053 | for (i = 0; i < elts; ++i) |
2054 | { | |
34a80643 R |
2055 | /* If this is part of a register, and not the first item in the |
2056 | word, we can't store using a SUBREG - that would clobber | |
2057 | previous results. | |
2058 | And storing with a SUBREG is only possible for the least | |
2059 | significant part, hence we can't do it for big endian | |
2060 | (unless we want to permute the evaluation order. */ | |
f8cfc6aa | 2061 | if (REG_P (target) |
34a80643 R |
2062 | && (BYTES_BIG_ENDIAN |
2063 | ? subsize < UNITS_PER_WORD | |
2064 | : ((i * subsize) % UNITS_PER_WORD) != 0)) | |
2065 | t = NULL_RTX; | |
2066 | else | |
2067 | t = simplify_gen_subreg (submode, target, mode, i * subsize); | |
2068 | if (CONSTANT_P (op0)) | |
2069 | a = simplify_gen_subreg (submode, op0, mode, i * subsize); | |
2070 | else | |
2071 | a = extract_bit_field (op0, subbitsize, i * subbitsize, unsignedp, | |
b3520980 | 2072 | t, submode, submode); |
cb2a532e AH |
2073 | |
2074 | res = expand_unop (submode, unoptab, a, t, unsignedp); | |
2075 | ||
34a80643 R |
2076 | if (t) |
2077 | emit_move_insn (t, res); | |
2078 | else | |
b3520980 | 2079 | store_bit_field (target, subbitsize, i * subbitsize, submode, res); |
cb2a532e AH |
2080 | } |
2081 | ||
2082 | seq = get_insns (); | |
2083 | end_sequence (); | |
2084 | emit_insn (seq); | |
2085 | ||
2086 | return target; | |
2087 | } | |
77c9c6c2 RK |
2088 | \f |
2089 | /* Expand a binary operator which has both signed and unsigned forms. | |
2090 | UOPTAB is the optab for unsigned operations, and SOPTAB is for | |
2091 | signed operations. | |
2092 | ||
2093 | If we widen unsigned operands, we may use a signed wider operation instead | |
2094 | of an unsigned wider operation, since the result would be the same. */ | |
2095 | ||
2096 | rtx | |
0c20a65f AJ |
2097 | sign_expand_binop (enum machine_mode mode, optab uoptab, optab soptab, |
2098 | rtx op0, rtx op1, rtx target, int unsignedp, | |
2099 | enum optab_methods methods) | |
77c9c6c2 | 2100 | { |
b3694847 | 2101 | rtx temp; |
77c9c6c2 RK |
2102 | optab direct_optab = unsignedp ? uoptab : soptab; |
2103 | struct optab wide_soptab; | |
2104 | ||
2105 | /* Do it without widening, if possible. */ | |
2106 | temp = expand_binop (mode, direct_optab, op0, op1, target, | |
2107 | unsignedp, OPTAB_DIRECT); | |
2108 | if (temp || methods == OPTAB_DIRECT) | |
2109 | return temp; | |
2110 | ||
2111 | /* Try widening to a signed int. Make a fake signed optab that | |
2112 | hides any signed insn for direct use. */ | |
2113 | wide_soptab = *soptab; | |
2114 | wide_soptab.handlers[(int) mode].insn_code = CODE_FOR_nothing; | |
2115 | wide_soptab.handlers[(int) mode].libfunc = 0; | |
2116 | ||
2117 | temp = expand_binop (mode, &wide_soptab, op0, op1, target, | |
2118 | unsignedp, OPTAB_WIDEN); | |
2119 | ||
2120 | /* For unsigned operands, try widening to an unsigned int. */ | |
2121 | if (temp == 0 && unsignedp) | |
2122 | temp = expand_binop (mode, uoptab, op0, op1, target, | |
2123 | unsignedp, OPTAB_WIDEN); | |
2124 | if (temp || methods == OPTAB_WIDEN) | |
2125 | return temp; | |
2126 | ||
2127 | /* Use the right width lib call if that exists. */ | |
2128 | temp = expand_binop (mode, direct_optab, op0, op1, target, unsignedp, OPTAB_LIB); | |
2129 | if (temp || methods == OPTAB_LIB) | |
2130 | return temp; | |
2131 | ||
2132 | /* Must widen and use a lib call, use either signed or unsigned. */ | |
2133 | temp = expand_binop (mode, &wide_soptab, op0, op1, target, | |
2134 | unsignedp, methods); | |
2135 | if (temp != 0) | |
2136 | return temp; | |
2137 | if (unsignedp) | |
2138 | return expand_binop (mode, uoptab, op0, op1, target, | |
2139 | unsignedp, methods); | |
2140 | return 0; | |
2141 | } | |
2142 | \f | |
6c7cf1f0 UB |
2143 | /* Generate code to perform an operation specified by UNOPPTAB |
2144 | on operand OP0, with two results to TARG0 and TARG1. | |
2145 | We assume that the order of the operands for the instruction | |
2146 | is TARG0, TARG1, OP0. | |
2147 | ||
2148 | Either TARG0 or TARG1 may be zero, but what that means is that | |
2149 | the result is not actually wanted. We will generate it into | |
2150 | a dummy pseudo-reg and discard it. They may not both be zero. | |
2151 | ||
2152 | Returns 1 if this operation can be performed; 0 if not. */ | |
2153 | ||
2154 | int | |
a072d43b | 2155 | expand_twoval_unop (optab unoptab, rtx op0, rtx targ0, rtx targ1, |
6c7cf1f0 UB |
2156 | int unsignedp) |
2157 | { | |
2158 | enum machine_mode mode = GET_MODE (targ0 ? targ0 : targ1); | |
2159 | enum mode_class class; | |
2160 | enum machine_mode wider_mode; | |
2161 | rtx entry_last = get_last_insn (); | |
2162 | rtx last; | |
2163 | ||
2164 | class = GET_MODE_CLASS (mode); | |
2165 | ||
6c7cf1f0 | 2166 | if (flag_force_mem) |
ad76cef8 | 2167 | op0 = force_not_mem (op0); |
6c7cf1f0 | 2168 | |
ad76cef8 | 2169 | if (!targ0) |
6c7cf1f0 | 2170 | targ0 = gen_reg_rtx (mode); |
ad76cef8 | 2171 | if (!targ1) |
6c7cf1f0 UB |
2172 | targ1 = gen_reg_rtx (mode); |
2173 | ||
2174 | /* Record where to go back to if we fail. */ | |
2175 | last = get_last_insn (); | |
2176 | ||
2177 | if (unoptab->handlers[(int) mode].insn_code != CODE_FOR_nothing) | |
2178 | { | |
2179 | int icode = (int) unoptab->handlers[(int) mode].insn_code; | |
2180 | enum machine_mode mode0 = insn_data[icode].operand[2].mode; | |
2181 | rtx pat; | |
2182 | rtx xop0 = op0; | |
2183 | ||
2184 | if (GET_MODE (xop0) != VOIDmode | |
2185 | && GET_MODE (xop0) != mode0) | |
2186 | xop0 = convert_to_mode (mode0, xop0, unsignedp); | |
2187 | ||
2188 | /* Now, if insn doesn't accept these operands, put them into pseudos. */ | |
2189 | if (! (*insn_data[icode].operand[2].predicate) (xop0, mode0)) | |
2190 | xop0 = copy_to_mode_reg (mode0, xop0); | |
2191 | ||
2192 | /* We could handle this, but we should always be called with a pseudo | |
2193 | for our targets and all insns should take them as outputs. */ | |
2194 | if (! (*insn_data[icode].operand[0].predicate) (targ0, mode) | |
2195 | || ! (*insn_data[icode].operand[1].predicate) (targ1, mode)) | |
2196 | abort (); | |
2197 | ||
2198 | pat = GEN_FCN (icode) (targ0, targ1, xop0); | |
2199 | if (pat) | |
2200 | { | |
2201 | emit_insn (pat); | |
2202 | return 1; | |
2203 | } | |
2204 | else | |
2205 | delete_insns_since (last); | |
2206 | } | |
2207 | ||
2208 | /* It can't be done in this mode. Can we do it in a wider mode? */ | |
2209 | ||
2210 | if (class == MODE_INT || class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT) | |
2211 | { | |
2212 | for (wider_mode = GET_MODE_WIDER_MODE (mode); wider_mode != VOIDmode; | |
2213 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) | |
2214 | { | |
2215 | if (unoptab->handlers[(int) wider_mode].insn_code | |
2216 | != CODE_FOR_nothing) | |
2217 | { | |
2218 | rtx t0 = gen_reg_rtx (wider_mode); | |
2219 | rtx t1 = gen_reg_rtx (wider_mode); | |
2220 | rtx cop0 = convert_modes (wider_mode, mode, op0, unsignedp); | |
2221 | ||
a072d43b | 2222 | if (expand_twoval_unop (unoptab, cop0, t0, t1, unsignedp)) |
6c7cf1f0 UB |
2223 | { |
2224 | convert_move (targ0, t0, unsignedp); | |
2225 | convert_move (targ1, t1, unsignedp); | |
2226 | return 1; | |
2227 | } | |
2228 | else | |
2229 | delete_insns_since (last); | |
2230 | } | |
2231 | } | |
2232 | } | |
2233 | ||
2234 | delete_insns_since (entry_last); | |
2235 | return 0; | |
2236 | } | |
2237 | \f | |
77c9c6c2 RK |
2238 | /* Generate code to perform an operation specified by BINOPTAB |
2239 | on operands OP0 and OP1, with two results to TARG1 and TARG2. | |
2240 | We assume that the order of the operands for the instruction | |
2241 | is TARG0, OP0, OP1, TARG1, which would fit a pattern like | |
2242 | [(set TARG0 (operate OP0 OP1)) (set TARG1 (operate ...))]. | |
2243 | ||
2244 | Either TARG0 or TARG1 may be zero, but what that means is that | |
38e01259 | 2245 | the result is not actually wanted. We will generate it into |
77c9c6c2 RK |
2246 | a dummy pseudo-reg and discard it. They may not both be zero. |
2247 | ||
2248 | Returns 1 if this operation can be performed; 0 if not. */ | |
2249 | ||
2250 | int | |
0c20a65f AJ |
2251 | expand_twoval_binop (optab binoptab, rtx op0, rtx op1, rtx targ0, rtx targ1, |
2252 | int unsignedp) | |
77c9c6c2 RK |
2253 | { |
2254 | enum machine_mode mode = GET_MODE (targ0 ? targ0 : targ1); | |
2255 | enum mode_class class; | |
2256 | enum machine_mode wider_mode; | |
abd418d3 | 2257 | rtx entry_last = get_last_insn (); |
77c9c6c2 RK |
2258 | rtx last; |
2259 | ||
2260 | class = GET_MODE_CLASS (mode); | |
2261 | ||
77c9c6c2 RK |
2262 | if (flag_force_mem) |
2263 | { | |
2264 | op0 = force_not_mem (op0); | |
2265 | op1 = force_not_mem (op1); | |
2266 | } | |
2267 | ||
2268 | /* If we are inside an appropriately-short loop and one operand is an | |
2269 | expensive constant, force it into a register. */ | |
aeedc93f | 2270 | if (CONSTANT_P (op0) && preserve_subexpressions_p () |
b437f1a7 | 2271 | && rtx_cost (op0, binoptab->code) > COSTS_N_INSNS (1)) |
77c9c6c2 RK |
2272 | op0 = force_reg (mode, op0); |
2273 | ||
aeedc93f | 2274 | if (CONSTANT_P (op1) && preserve_subexpressions_p () |
b437f1a7 | 2275 | && rtx_cost (op1, binoptab->code) > COSTS_N_INSNS (1)) |
77c9c6c2 RK |
2276 | op1 = force_reg (mode, op1); |
2277 | ||
ad76cef8 | 2278 | if (!targ0) |
77c9c6c2 | 2279 | targ0 = gen_reg_rtx (mode); |
ad76cef8 | 2280 | if (!targ1) |
77c9c6c2 RK |
2281 | targ1 = gen_reg_rtx (mode); |
2282 | ||
2283 | /* Record where to go back to if we fail. */ | |
2284 | last = get_last_insn (); | |
2285 | ||
2286 | if (binoptab->handlers[(int) mode].insn_code != CODE_FOR_nothing) | |
2287 | { | |
2288 | int icode = (int) binoptab->handlers[(int) mode].insn_code; | |
a995e389 RH |
2289 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; |
2290 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
77c9c6c2 RK |
2291 | rtx pat; |
2292 | rtx xop0 = op0, xop1 = op1; | |
2293 | ||
874f6a6d EB |
2294 | /* In case the insn wants input operands in modes different from |
2295 | those of the actual operands, convert the operands. It would | |
2296 | seem that we don't need to convert CONST_INTs, but we do, so | |
35f1c975 EB |
2297 | that they're properly zero-extended, sign-extended or truncated |
2298 | for their mode. */ | |
77c9c6c2 | 2299 | |
874f6a6d EB |
2300 | if (GET_MODE (op0) != mode0 && mode0 != VOIDmode) |
2301 | xop0 = convert_modes (mode0, | |
2302 | GET_MODE (op0) != VOIDmode | |
2303 | ? GET_MODE (op0) | |
2304 | : mode, | |
2305 | xop0, unsignedp); | |
2306 | ||
2307 | if (GET_MODE (op1) != mode1 && mode1 != VOIDmode) | |
2308 | xop1 = convert_modes (mode1, | |
2309 | GET_MODE (op1) != VOIDmode | |
2310 | ? GET_MODE (op1) | |
2311 | : mode, | |
2312 | xop1, unsignedp); | |
77c9c6c2 RK |
2313 | |
2314 | /* Now, if insn doesn't accept these operands, put them into pseudos. */ | |
a995e389 | 2315 | if (! (*insn_data[icode].operand[1].predicate) (xop0, mode0)) |
77c9c6c2 RK |
2316 | xop0 = copy_to_mode_reg (mode0, xop0); |
2317 | ||
a995e389 | 2318 | if (! (*insn_data[icode].operand[2].predicate) (xop1, mode1)) |
77c9c6c2 RK |
2319 | xop1 = copy_to_mode_reg (mode1, xop1); |
2320 | ||
2321 | /* We could handle this, but we should always be called with a pseudo | |
2322 | for our targets and all insns should take them as outputs. */ | |
a995e389 RH |
2323 | if (! (*insn_data[icode].operand[0].predicate) (targ0, mode) |
2324 | || ! (*insn_data[icode].operand[3].predicate) (targ1, mode)) | |
77c9c6c2 | 2325 | abort (); |
0c20a65f | 2326 | |
77c9c6c2 RK |
2327 | pat = GEN_FCN (icode) (targ0, xop0, xop1, targ1); |
2328 | if (pat) | |
2329 | { | |
2330 | emit_insn (pat); | |
2331 | return 1; | |
2332 | } | |
2333 | else | |
2334 | delete_insns_since (last); | |
2335 | } | |
2336 | ||
2337 | /* It can't be done in this mode. Can we do it in a wider mode? */ | |
2338 | ||
2339 | if (class == MODE_INT || class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT) | |
2340 | { | |
34e56753 | 2341 | for (wider_mode = GET_MODE_WIDER_MODE (mode); wider_mode != VOIDmode; |
77c9c6c2 RK |
2342 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) |
2343 | { | |
2344 | if (binoptab->handlers[(int) wider_mode].insn_code | |
2345 | != CODE_FOR_nothing) | |
2346 | { | |
b3694847 SS |
2347 | rtx t0 = gen_reg_rtx (wider_mode); |
2348 | rtx t1 = gen_reg_rtx (wider_mode); | |
76791f3d JH |
2349 | rtx cop0 = convert_modes (wider_mode, mode, op0, unsignedp); |
2350 | rtx cop1 = convert_modes (wider_mode, mode, op1, unsignedp); | |
77c9c6c2 | 2351 | |
76791f3d | 2352 | if (expand_twoval_binop (binoptab, cop0, cop1, |
77c9c6c2 RK |
2353 | t0, t1, unsignedp)) |
2354 | { | |
2355 | convert_move (targ0, t0, unsignedp); | |
2356 | convert_move (targ1, t1, unsignedp); | |
2357 | return 1; | |
2358 | } | |
2359 | else | |
2360 | delete_insns_since (last); | |
2361 | } | |
2362 | } | |
2363 | } | |
2364 | ||
abd418d3 | 2365 | delete_insns_since (entry_last); |
77c9c6c2 RK |
2366 | return 0; |
2367 | } | |
2368 | \f | |
ef89d648 ZW |
2369 | /* Wrapper around expand_unop which takes an rtx code to specify |
2370 | the operation to perform, not an optab pointer. All other | |
2371 | arguments are the same. */ | |
2372 | rtx | |
0c20a65f AJ |
2373 | expand_simple_unop (enum machine_mode mode, enum rtx_code code, rtx op0, |
2374 | rtx target, int unsignedp) | |
ef89d648 | 2375 | { |
7e1a450d | 2376 | optab unop = code_to_optab[(int) code]; |
ef89d648 ZW |
2377 | if (unop == 0) |
2378 | abort (); | |
2379 | ||
2380 | return expand_unop (mode, unop, op0, target, unsignedp); | |
2381 | } | |
2382 | ||
2928cd7a RH |
2383 | /* Try calculating |
2384 | (clz:narrow x) | |
2385 | as | |
2386 | (clz:wide (zero_extend:wide x)) - ((width wide) - (width narrow)). */ | |
2387 | static rtx | |
0c20a65f | 2388 | widen_clz (enum machine_mode mode, rtx op0, rtx target) |
2928cd7a RH |
2389 | { |
2390 | enum mode_class class = GET_MODE_CLASS (mode); | |
2391 | if (class == MODE_INT || class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT) | |
2392 | { | |
2393 | enum machine_mode wider_mode; | |
2394 | for (wider_mode = GET_MODE_WIDER_MODE (mode); wider_mode != VOIDmode; | |
2395 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) | |
2396 | { | |
2397 | if (clz_optab->handlers[(int) wider_mode].insn_code | |
2398 | != CODE_FOR_nothing) | |
2399 | { | |
2400 | rtx xop0, temp, last; | |
2401 | ||
2402 | last = get_last_insn (); | |
2403 | ||
2404 | if (target == 0) | |
2405 | target = gen_reg_rtx (mode); | |
2406 | xop0 = widen_operand (op0, wider_mode, mode, true, false); | |
2407 | temp = expand_unop (wider_mode, clz_optab, xop0, NULL_RTX, true); | |
2408 | if (temp != 0) | |
2409 | temp = expand_binop (wider_mode, sub_optab, temp, | |
2410 | GEN_INT (GET_MODE_BITSIZE (wider_mode) | |
2411 | - GET_MODE_BITSIZE (mode)), | |
2412 | target, true, OPTAB_DIRECT); | |
2413 | if (temp == 0) | |
2414 | delete_insns_since (last); | |
2415 | ||
2416 | return temp; | |
2417 | } | |
2418 | } | |
2419 | } | |
2420 | return 0; | |
2421 | } | |
2422 | ||
2423 | /* Try calculating (parity x) as (and (popcount x) 1), where | |
2424 | popcount can also be done in a wider mode. */ | |
2425 | static rtx | |
0c20a65f | 2426 | expand_parity (enum machine_mode mode, rtx op0, rtx target) |
2928cd7a RH |
2427 | { |
2428 | enum mode_class class = GET_MODE_CLASS (mode); | |
2429 | if (class == MODE_INT || class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT) | |
2430 | { | |
2431 | enum machine_mode wider_mode; | |
2432 | for (wider_mode = mode; wider_mode != VOIDmode; | |
2433 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) | |
2434 | { | |
2435 | if (popcount_optab->handlers[(int) wider_mode].insn_code | |
2436 | != CODE_FOR_nothing) | |
2437 | { | |
2438 | rtx xop0, temp, last; | |
2439 | ||
2440 | last = get_last_insn (); | |
2441 | ||
2442 | if (target == 0) | |
2443 | target = gen_reg_rtx (mode); | |
2444 | xop0 = widen_operand (op0, wider_mode, mode, true, false); | |
2445 | temp = expand_unop (wider_mode, popcount_optab, xop0, NULL_RTX, | |
2446 | true); | |
2447 | if (temp != 0) | |
60c81c89 | 2448 | temp = expand_binop (wider_mode, and_optab, temp, const1_rtx, |
2928cd7a RH |
2449 | target, true, OPTAB_DIRECT); |
2450 | if (temp == 0) | |
2451 | delete_insns_since (last); | |
2452 | ||
2453 | return temp; | |
2454 | } | |
2455 | } | |
2456 | } | |
2457 | return 0; | |
2458 | } | |
2459 | ||
77c9c6c2 RK |
2460 | /* Generate code to perform an operation specified by UNOPTAB |
2461 | on operand OP0, with result having machine-mode MODE. | |
2462 | ||
2463 | UNSIGNEDP is for the case where we have to widen the operands | |
2464 | to perform the operation. It says to use zero-extension. | |
2465 | ||
2466 | If TARGET is nonzero, the value | |
2467 | is generated there, if it is convenient to do so. | |
2468 | In all cases an rtx is returned for the locus of the value; | |
2469 | this may or may not be TARGET. */ | |
2470 | ||
2471 | rtx | |
0c20a65f AJ |
2472 | expand_unop (enum machine_mode mode, optab unoptab, rtx op0, rtx target, |
2473 | int unsignedp) | |
77c9c6c2 RK |
2474 | { |
2475 | enum mode_class class; | |
2476 | enum machine_mode wider_mode; | |
b3694847 | 2477 | rtx temp; |
77c9c6c2 RK |
2478 | rtx last = get_last_insn (); |
2479 | rtx pat; | |
2480 | ||
2481 | class = GET_MODE_CLASS (mode); | |
2482 | ||
77c9c6c2 | 2483 | if (flag_force_mem) |
ad76cef8 | 2484 | op0 = force_not_mem (op0); |
77c9c6c2 RK |
2485 | |
2486 | if (unoptab->handlers[(int) mode].insn_code != CODE_FOR_nothing) | |
2487 | { | |
2488 | int icode = (int) unoptab->handlers[(int) mode].insn_code; | |
a995e389 | 2489 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; |
77c9c6c2 RK |
2490 | rtx xop0 = op0; |
2491 | ||
2492 | if (target) | |
2493 | temp = target; | |
2494 | else | |
2495 | temp = gen_reg_rtx (mode); | |
2496 | ||
2497 | if (GET_MODE (xop0) != VOIDmode | |
2498 | && GET_MODE (xop0) != mode0) | |
2499 | xop0 = convert_to_mode (mode0, xop0, unsignedp); | |
2500 | ||
2501 | /* Now, if insn doesn't accept our operand, put it into a pseudo. */ | |
2502 | ||
a995e389 | 2503 | if (! (*insn_data[icode].operand[1].predicate) (xop0, mode0)) |
77c9c6c2 RK |
2504 | xop0 = copy_to_mode_reg (mode0, xop0); |
2505 | ||
a995e389 | 2506 | if (! (*insn_data[icode].operand[0].predicate) (temp, mode)) |
77c9c6c2 RK |
2507 | temp = gen_reg_rtx (mode); |
2508 | ||
2509 | pat = GEN_FCN (icode) (temp, xop0); | |
2510 | if (pat) | |
2511 | { | |
2f937369 | 2512 | if (INSN_P (pat) && NEXT_INSN (pat) != NULL_RTX |
b1ec3c92 | 2513 | && ! add_equal_note (pat, temp, unoptab->code, xop0, NULL_RTX)) |
77c9c6c2 RK |
2514 | { |
2515 | delete_insns_since (last); | |
b1ec3c92 | 2516 | return expand_unop (mode, unoptab, op0, NULL_RTX, unsignedp); |
77c9c6c2 RK |
2517 | } |
2518 | ||
2519 | emit_insn (pat); | |
0c20a65f | 2520 | |
77c9c6c2 RK |
2521 | return temp; |
2522 | } | |
2523 | else | |
2524 | delete_insns_since (last); | |
2525 | } | |
2526 | ||
9a856ec7 RK |
2527 | /* It can't be done in this mode. Can we open-code it in a wider mode? */ |
2528 | ||
2928cd7a RH |
2529 | /* Widening clz needs special treatment. */ |
2530 | if (unoptab == clz_optab) | |
2531 | { | |
2532 | temp = widen_clz (mode, op0, target); | |
2533 | if (temp) | |
2534 | return temp; | |
2535 | else | |
2536 | goto try_libcall; | |
2537 | } | |
2538 | ||
9a856ec7 RK |
2539 | if (class == MODE_INT || class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT) |
2540 | for (wider_mode = GET_MODE_WIDER_MODE (mode); wider_mode != VOIDmode; | |
2541 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) | |
2542 | { | |
2543 | if (unoptab->handlers[(int) wider_mode].insn_code != CODE_FOR_nothing) | |
2544 | { | |
2545 | rtx xop0 = op0; | |
2546 | ||
2547 | /* For certain operations, we need not actually extend | |
2548 | the narrow operand, as long as we will truncate the | |
835532b8 RK |
2549 | results to the same narrowness. */ |
2550 | ||
0661a3de | 2551 | xop0 = widen_operand (xop0, wider_mode, mode, unsignedp, |
835532b8 RK |
2552 | (unoptab == neg_optab |
2553 | || unoptab == one_cmpl_optab) | |
2554 | && class == MODE_INT); | |
0c20a65f | 2555 | |
b1ec3c92 CH |
2556 | temp = expand_unop (wider_mode, unoptab, xop0, NULL_RTX, |
2557 | unsignedp); | |
9a856ec7 RK |
2558 | |
2559 | if (temp) | |
2560 | { | |
2561 | if (class != MODE_INT) | |
2562 | { | |
2563 | if (target == 0) | |
2564 | target = gen_reg_rtx (mode); | |
2565 | convert_move (target, temp, 0); | |
2566 | return target; | |
2567 | } | |
2568 | else | |
2569 | return gen_lowpart (mode, temp); | |
2570 | } | |
2571 | else | |
2572 | delete_insns_since (last); | |
2573 | } | |
2574 | } | |
2575 | ||
77c9c6c2 RK |
2576 | /* These can be done a word at a time. */ |
2577 | if (unoptab == one_cmpl_optab | |
2578 | && class == MODE_INT | |
2579 | && GET_MODE_SIZE (mode) > UNITS_PER_WORD | |
34e56753 | 2580 | && unoptab->handlers[(int) word_mode].insn_code != CODE_FOR_nothing) |
77c9c6c2 | 2581 | { |
bb93b973 | 2582 | int i; |
77c9c6c2 RK |
2583 | rtx insns; |
2584 | ||
2585 | if (target == 0 || target == op0) | |
2586 | target = gen_reg_rtx (mode); | |
2587 | ||
2588 | start_sequence (); | |
2589 | ||
2590 | /* Do the actual arithmetic. */ | |
2591 | for (i = 0; i < GET_MODE_BITSIZE (mode) / BITS_PER_WORD; i++) | |
2592 | { | |
2593 | rtx target_piece = operand_subword (target, i, 1, mode); | |
34e56753 | 2594 | rtx x = expand_unop (word_mode, unoptab, |
77c9c6c2 RK |
2595 | operand_subword_force (op0, i, mode), |
2596 | target_piece, unsignedp); | |
bb93b973 | 2597 | |
77c9c6c2 RK |
2598 | if (target_piece != x) |
2599 | emit_move_insn (target_piece, x); | |
2600 | } | |
2601 | ||
2602 | insns = get_insns (); | |
2603 | end_sequence (); | |
2604 | ||
b1ec3c92 | 2605 | emit_no_conflict_block (insns, target, op0, NULL_RTX, |
9e6a5703 JC |
2606 | gen_rtx_fmt_e (unoptab->code, mode, |
2607 | copy_rtx (op0))); | |
77c9c6c2 RK |
2608 | return target; |
2609 | } | |
2610 | ||
139e5e08 | 2611 | /* Open-code the complex negation operation. */ |
91ce572a | 2612 | else if (unoptab->code == NEG |
139e5e08 RS |
2613 | && (class == MODE_COMPLEX_FLOAT || class == MODE_COMPLEX_INT)) |
2614 | { | |
2615 | rtx target_piece; | |
2616 | rtx x; | |
2617 | rtx seq; | |
2618 | ||
f9da5064 | 2619 | /* Find the correct mode for the real and imaginary parts. */ |
27e58a70 | 2620 | enum machine_mode submode = GET_MODE_INNER (mode); |
139e5e08 RS |
2621 | |
2622 | if (submode == BLKmode) | |
2623 | abort (); | |
2624 | ||
2625 | if (target == 0) | |
2626 | target = gen_reg_rtx (mode); | |
0c20a65f | 2627 | |
139e5e08 RS |
2628 | start_sequence (); |
2629 | ||
decdfa82 | 2630 | target_piece = gen_imagpart (submode, target); |
139e5e08 | 2631 | x = expand_unop (submode, unoptab, |
decdfa82 | 2632 | gen_imagpart (submode, op0), |
139e5e08 RS |
2633 | target_piece, unsignedp); |
2634 | if (target_piece != x) | |
2635 | emit_move_insn (target_piece, x); | |
2636 | ||
decdfa82 | 2637 | target_piece = gen_realpart (submode, target); |
139e5e08 | 2638 | x = expand_unop (submode, unoptab, |
decdfa82 | 2639 | gen_realpart (submode, op0), |
139e5e08 RS |
2640 | target_piece, unsignedp); |
2641 | if (target_piece != x) | |
2642 | emit_move_insn (target_piece, x); | |
2643 | ||
a29b481b | 2644 | seq = get_insns (); |
139e5e08 RS |
2645 | end_sequence (); |
2646 | ||
2647 | emit_no_conflict_block (seq, target, op0, 0, | |
9e6a5703 JC |
2648 | gen_rtx_fmt_e (unoptab->code, mode, |
2649 | copy_rtx (op0))); | |
139e5e08 RS |
2650 | return target; |
2651 | } | |
2652 | ||
4977bab6 ZW |
2653 | /* Try negating floating point values by flipping the sign bit. */ |
2654 | if (unoptab->code == NEG && class == MODE_FLOAT | |
2655 | && GET_MODE_BITSIZE (mode) <= 2 * HOST_BITS_PER_WIDE_INT) | |
2656 | { | |
70a01792 | 2657 | const struct real_format *fmt = REAL_MODE_FORMAT (mode); |
4977bab6 ZW |
2658 | enum machine_mode imode = int_mode_for_mode (mode); |
2659 | int bitpos = (fmt != 0) ? fmt->signbit : -1; | |
2660 | ||
2661 | if (imode != BLKmode && bitpos >= 0 && fmt->has_signed_zero) | |
2662 | { | |
2663 | HOST_WIDE_INT hi, lo; | |
2664 | rtx last = get_last_insn (); | |
2665 | ||
9ee0a442 RS |
2666 | /* Handle targets with different FP word orders. */ |
2667 | if (FLOAT_WORDS_BIG_ENDIAN != WORDS_BIG_ENDIAN) | |
2668 | { | |
2669 | int nwords = GET_MODE_BITSIZE (mode) / BITS_PER_WORD; | |
2670 | int word = nwords - (bitpos / BITS_PER_WORD) - 1; | |
2671 | bitpos = word * BITS_PER_WORD + bitpos % BITS_PER_WORD; | |
2672 | } | |
2673 | ||
4977bab6 ZW |
2674 | if (bitpos < HOST_BITS_PER_WIDE_INT) |
2675 | { | |
2676 | hi = 0; | |
2677 | lo = (HOST_WIDE_INT) 1 << bitpos; | |
2678 | } | |
2679 | else | |
2680 | { | |
2681 | hi = (HOST_WIDE_INT) 1 << (bitpos - HOST_BITS_PER_WIDE_INT); | |
2682 | lo = 0; | |
2683 | } | |
2684 | temp = expand_binop (imode, xor_optab, | |
2685 | gen_lowpart (imode, op0), | |
2686 | immed_double_const (lo, hi, imode), | |
2687 | NULL_RTX, 1, OPTAB_LIB_WIDEN); | |
2688 | if (temp != 0) | |
dd0ba281 RS |
2689 | { |
2690 | rtx insn; | |
2691 | if (target == 0) | |
2692 | target = gen_reg_rtx (mode); | |
2693 | insn = emit_move_insn (target, gen_lowpart (mode, temp)); | |
2694 | set_unique_reg_note (insn, REG_EQUAL, | |
2695 | gen_rtx_fmt_e (NEG, mode, | |
2696 | copy_rtx (op0))); | |
2697 | return target; | |
2698 | } | |
4977bab6 ZW |
2699 | delete_insns_since (last); |
2700 | } | |
2701 | } | |
2702 | ||
2928cd7a RH |
2703 | /* Try calculating parity (x) as popcount (x) % 2. */ |
2704 | if (unoptab == parity_optab) | |
2705 | { | |
2706 | temp = expand_parity (mode, op0, target); | |
2707 | if (temp) | |
2708 | return temp; | |
2709 | } | |
2710 | ||
d83aba0f RS |
2711 | /* If there is no negation pattern, try subtracting from zero. */ |
2712 | if (unoptab == neg_optab && class == MODE_INT) | |
2713 | { | |
2714 | temp = expand_binop (mode, sub_optab, CONST0_RTX (mode), op0, | |
2715 | target, unsignedp, OPTAB_DIRECT); | |
2716 | if (temp) | |
2717 | return temp; | |
2718 | } | |
2719 | ||
2928cd7a | 2720 | try_libcall: |
139e5e08 | 2721 | /* Now try a library call in this mode. */ |
77c9c6c2 RK |
2722 | if (unoptab->handlers[(int) mode].libfunc) |
2723 | { | |
2724 | rtx insns; | |
9a7f678c | 2725 | rtx value; |
2928cd7a RH |
2726 | enum machine_mode outmode = mode; |
2727 | ||
2728 | /* All of these functions return small values. Thus we choose to | |
2729 | have them return something that isn't a double-word. */ | |
2730 | if (unoptab == ffs_optab || unoptab == clz_optab || unoptab == ctz_optab | |
2731 | || unoptab == popcount_optab || unoptab == parity_optab) | |
cd2ac05b FH |
2732 | outmode |
2733 | = GET_MODE (hard_libcall_value (TYPE_MODE (integer_type_node))); | |
77c9c6c2 RK |
2734 | |
2735 | start_sequence (); | |
2736 | ||
2737 | /* Pass 1 for NO_QUEUE so we don't lose any increments | |
2738 | if the libcall is cse'd or moved. */ | |
9a7f678c | 2739 | value = emit_library_call_value (unoptab->handlers[(int) mode].libfunc, |
2928cd7a RH |
2740 | NULL_RTX, LCT_CONST, outmode, |
2741 | 1, op0, mode); | |
77c9c6c2 RK |
2742 | insns = get_insns (); |
2743 | end_sequence (); | |
2744 | ||
2928cd7a | 2745 | target = gen_reg_rtx (outmode); |
9a7f678c | 2746 | emit_libcall_block (insns, target, value, |
9e6a5703 | 2747 | gen_rtx_fmt_e (unoptab->code, mode, op0)); |
77c9c6c2 RK |
2748 | |
2749 | return target; | |
2750 | } | |
2751 | ||
cb2a532e AH |
2752 | if (class == MODE_VECTOR_FLOAT || class == MODE_VECTOR_INT) |
2753 | return expand_vector_unop (mode, unoptab, op0, target, unsignedp); | |
2754 | ||
77c9c6c2 RK |
2755 | /* It can't be done in this mode. Can we do it in a wider mode? */ |
2756 | ||
2757 | if (class == MODE_INT || class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT) | |
2758 | { | |
34e56753 | 2759 | for (wider_mode = GET_MODE_WIDER_MODE (mode); wider_mode != VOIDmode; |
77c9c6c2 RK |
2760 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) |
2761 | { | |
2762 | if ((unoptab->handlers[(int) wider_mode].insn_code | |
2763 | != CODE_FOR_nothing) | |
2764 | || unoptab->handlers[(int) wider_mode].libfunc) | |
2765 | { | |
34e56753 RS |
2766 | rtx xop0 = op0; |
2767 | ||
2768 | /* For certain operations, we need not actually extend | |
2769 | the narrow operand, as long as we will truncate the | |
2770 | results to the same narrowness. */ | |
2771 | ||
0661a3de | 2772 | xop0 = widen_operand (xop0, wider_mode, mode, unsignedp, |
835532b8 RK |
2773 | (unoptab == neg_optab |
2774 | || unoptab == one_cmpl_optab) | |
2775 | && class == MODE_INT); | |
0c20a65f | 2776 | |
b1ec3c92 CH |
2777 | temp = expand_unop (wider_mode, unoptab, xop0, NULL_RTX, |
2778 | unsignedp); | |
34e56753 | 2779 | |
c117dddc KH |
2780 | /* If we are generating clz using wider mode, adjust the |
2781 | result. */ | |
2782 | if (unoptab == clz_optab && temp != 0) | |
2783 | temp = expand_binop (wider_mode, sub_optab, temp, | |
2784 | GEN_INT (GET_MODE_BITSIZE (wider_mode) | |
2785 | - GET_MODE_BITSIZE (mode)), | |
2786 | target, true, OPTAB_DIRECT); | |
2787 | ||
34e56753 | 2788 | if (temp) |
77c9c6c2 | 2789 | { |
34e56753 RS |
2790 | if (class != MODE_INT) |
2791 | { | |
2792 | if (target == 0) | |
2793 | target = gen_reg_rtx (mode); | |
2794 | convert_move (target, temp, 0); | |
2795 | return target; | |
2796 | } | |
2797 | else | |
2798 | return gen_lowpart (mode, temp); | |
77c9c6c2 RK |
2799 | } |
2800 | else | |
34e56753 | 2801 | delete_insns_since (last); |
77c9c6c2 RK |
2802 | } |
2803 | } | |
2804 | } | |
2805 | ||
b82b6eea DE |
2806 | /* If there is no negate operation, try doing a subtract from zero. |
2807 | The US Software GOFAST library needs this. */ | |
91ce572a | 2808 | if (unoptab->code == NEG) |
0c20a65f | 2809 | { |
b82b6eea | 2810 | rtx temp; |
91ce572a CC |
2811 | temp = expand_binop (mode, |
2812 | unoptab == negv_optab ? subv_optab : sub_optab, | |
2813 | CONST0_RTX (mode), op0, | |
2814 | target, unsignedp, OPTAB_LIB_WIDEN); | |
b82b6eea DE |
2815 | if (temp) |
2816 | return temp; | |
2817 | } | |
0c20a65f | 2818 | |
77c9c6c2 RK |
2819 | return 0; |
2820 | } | |
2821 | \f | |
decdfa82 RS |
2822 | /* Emit code to compute the absolute value of OP0, with result to |
2823 | TARGET if convenient. (TARGET may be 0.) The return value says | |
2824 | where the result actually is to be found. | |
2825 | ||
2826 | MODE is the mode of the operand; the mode of the result is | |
2827 | different but can be deduced from MODE. | |
2828 | ||
91813b28 | 2829 | */ |
7fd01431 RK |
2830 | |
2831 | rtx | |
0c20a65f AJ |
2832 | expand_abs_nojump (enum machine_mode mode, rtx op0, rtx target, |
2833 | int result_unsignedp) | |
7fd01431 | 2834 | { |
2ef0a555 | 2835 | rtx temp; |
7fd01431 | 2836 | |
91ce572a CC |
2837 | if (! flag_trapv) |
2838 | result_unsignedp = 1; | |
2839 | ||
7fd01431 | 2840 | /* First try to do it with a special abs instruction. */ |
91ce572a CC |
2841 | temp = expand_unop (mode, result_unsignedp ? abs_optab : absv_optab, |
2842 | op0, target, 0); | |
7fd01431 RK |
2843 | if (temp != 0) |
2844 | return temp; | |
2845 | ||
4977bab6 ZW |
2846 | /* For floating point modes, try clearing the sign bit. */ |
2847 | if (GET_MODE_CLASS (mode) == MODE_FLOAT | |
2848 | && GET_MODE_BITSIZE (mode) <= 2 * HOST_BITS_PER_WIDE_INT) | |
2849 | { | |
70a01792 | 2850 | const struct real_format *fmt = REAL_MODE_FORMAT (mode); |
4977bab6 ZW |
2851 | enum machine_mode imode = int_mode_for_mode (mode); |
2852 | int bitpos = (fmt != 0) ? fmt->signbit : -1; | |
2853 | ||
2854 | if (imode != BLKmode && bitpos >= 0) | |
2855 | { | |
2856 | HOST_WIDE_INT hi, lo; | |
2857 | rtx last = get_last_insn (); | |
2858 | ||
9ee0a442 RS |
2859 | /* Handle targets with different FP word orders. */ |
2860 | if (FLOAT_WORDS_BIG_ENDIAN != WORDS_BIG_ENDIAN) | |
2861 | { | |
2862 | int nwords = GET_MODE_BITSIZE (mode) / BITS_PER_WORD; | |
2863 | int word = nwords - (bitpos / BITS_PER_WORD) - 1; | |
2864 | bitpos = word * BITS_PER_WORD + bitpos % BITS_PER_WORD; | |
2865 | } | |
2866 | ||
4977bab6 ZW |
2867 | if (bitpos < HOST_BITS_PER_WIDE_INT) |
2868 | { | |
2869 | hi = 0; | |
2870 | lo = (HOST_WIDE_INT) 1 << bitpos; | |
2871 | } | |
2872 | else | |
2873 | { | |
2874 | hi = (HOST_WIDE_INT) 1 << (bitpos - HOST_BITS_PER_WIDE_INT); | |
2875 | lo = 0; | |
2876 | } | |
2877 | temp = expand_binop (imode, and_optab, | |
2878 | gen_lowpart (imode, op0), | |
2879 | immed_double_const (~lo, ~hi, imode), | |
2880 | NULL_RTX, 1, OPTAB_LIB_WIDEN); | |
2881 | if (temp != 0) | |
dd0ba281 RS |
2882 | { |
2883 | rtx insn; | |
2884 | if (target == 0) | |
2885 | target = gen_reg_rtx (mode); | |
2886 | insn = emit_move_insn (target, gen_lowpart (mode, temp)); | |
2887 | set_unique_reg_note (insn, REG_EQUAL, | |
2888 | gen_rtx_fmt_e (ABS, mode, | |
2889 | copy_rtx (op0))); | |
2890 | return target; | |
2891 | } | |
4977bab6 ZW |
2892 | delete_insns_since (last); |
2893 | } | |
2894 | } | |
2895 | ||
14a774a9 RK |
2896 | /* If we have a MAX insn, we can do this as MAX (x, -x). */ |
2897 | if (smax_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing) | |
2898 | { | |
2899 | rtx last = get_last_insn (); | |
2900 | ||
2901 | temp = expand_unop (mode, neg_optab, op0, NULL_RTX, 0); | |
2902 | if (temp != 0) | |
2903 | temp = expand_binop (mode, smax_optab, op0, temp, target, 0, | |
2904 | OPTAB_WIDEN); | |
2905 | ||
2906 | if (temp != 0) | |
2907 | return temp; | |
2908 | ||
2909 | delete_insns_since (last); | |
2910 | } | |
2911 | ||
7fd01431 RK |
2912 | /* If this machine has expensive jumps, we can do integer absolute |
2913 | value of X as (((signed) x >> (W-1)) ^ x) - ((signed) x >> (W-1)), | |
e1078cfc | 2914 | where W is the width of MODE. */ |
7fd01431 RK |
2915 | |
2916 | if (GET_MODE_CLASS (mode) == MODE_INT && BRANCH_COST >= 2) | |
2917 | { | |
2918 | rtx extended = expand_shift (RSHIFT_EXPR, mode, op0, | |
2919 | size_int (GET_MODE_BITSIZE (mode) - 1), | |
2920 | NULL_RTX, 0); | |
2921 | ||
2922 | temp = expand_binop (mode, xor_optab, extended, op0, target, 0, | |
2923 | OPTAB_LIB_WIDEN); | |
2924 | if (temp != 0) | |
91ce572a CC |
2925 | temp = expand_binop (mode, result_unsignedp ? sub_optab : subv_optab, |
2926 | temp, extended, target, 0, OPTAB_LIB_WIDEN); | |
7fd01431 RK |
2927 | |
2928 | if (temp != 0) | |
2929 | return temp; | |
2930 | } | |
2931 | ||
2ef0a555 RH |
2932 | return NULL_RTX; |
2933 | } | |
2934 | ||
2935 | rtx | |
0c20a65f AJ |
2936 | expand_abs (enum machine_mode mode, rtx op0, rtx target, |
2937 | int result_unsignedp, int safe) | |
2ef0a555 RH |
2938 | { |
2939 | rtx temp, op1; | |
2940 | ||
77173bbe KH |
2941 | if (! flag_trapv) |
2942 | result_unsignedp = 1; | |
2943 | ||
2ef0a555 RH |
2944 | temp = expand_abs_nojump (mode, op0, target, result_unsignedp); |
2945 | if (temp != 0) | |
2946 | return temp; | |
2947 | ||
7fd01431 | 2948 | /* If that does not win, use conditional jump and negate. */ |
5c0bf747 RK |
2949 | |
2950 | /* It is safe to use the target if it is the same | |
2951 | as the source if this is also a pseudo register */ | |
f8cfc6aa | 2952 | if (op0 == target && REG_P (op0) |
5c0bf747 RK |
2953 | && REGNO (op0) >= FIRST_PSEUDO_REGISTER) |
2954 | safe = 1; | |
2955 | ||
7fd01431 RK |
2956 | op1 = gen_label_rtx (); |
2957 | if (target == 0 || ! safe | |
2958 | || GET_MODE (target) != mode | |
3c0cb5de | 2959 | || (MEM_P (target) && MEM_VOLATILE_P (target)) |
f8cfc6aa | 2960 | || (REG_P (target) |
7fd01431 RK |
2961 | && REGNO (target) < FIRST_PSEUDO_REGISTER)) |
2962 | target = gen_reg_rtx (mode); | |
2963 | ||
2964 | emit_move_insn (target, op0); | |
2965 | NO_DEFER_POP; | |
2966 | ||
2967 | /* If this mode is an integer too wide to compare properly, | |
2968 | compare word by word. Rely on CSE to optimize constant cases. */ | |
1eb8759b RH |
2969 | if (GET_MODE_CLASS (mode) == MODE_INT |
2970 | && ! can_compare_p (GE, mode, ccp_jump)) | |
0c20a65f | 2971 | do_jump_by_parts_greater_rtx (mode, 0, target, const0_rtx, |
7fd01431 RK |
2972 | NULL_RTX, op1); |
2973 | else | |
b30f05db | 2974 | do_compare_rtx_and_jump (target, CONST0_RTX (mode), GE, 0, mode, |
a06ef755 | 2975 | NULL_RTX, NULL_RTX, op1); |
7fd01431 | 2976 | |
91ce572a CC |
2977 | op0 = expand_unop (mode, result_unsignedp ? neg_optab : negv_optab, |
2978 | target, target, 0); | |
7fd01431 RK |
2979 | if (op0 != target) |
2980 | emit_move_insn (target, op0); | |
2981 | emit_label (op1); | |
2982 | OK_DEFER_POP; | |
2983 | return target; | |
2984 | } | |
2985 | \f | |
2986 | /* Emit code to compute the absolute value of OP0, with result to | |
2987 | TARGET if convenient. (TARGET may be 0.) The return value says | |
2988 | where the result actually is to be found. | |
2989 | ||
2990 | MODE is the mode of the operand; the mode of the result is | |
2991 | different but can be deduced from MODE. | |
2992 | ||
decdfa82 RS |
2993 | UNSIGNEDP is relevant for complex integer modes. */ |
2994 | ||
2995 | rtx | |
0c20a65f AJ |
2996 | expand_complex_abs (enum machine_mode mode, rtx op0, rtx target, |
2997 | int unsignedp) | |
decdfa82 RS |
2998 | { |
2999 | enum mode_class class = GET_MODE_CLASS (mode); | |
3000 | enum machine_mode wider_mode; | |
b3694847 | 3001 | rtx temp; |
abd418d3 RS |
3002 | rtx entry_last = get_last_insn (); |
3003 | rtx last; | |
decdfa82 | 3004 | rtx pat; |
91ce572a | 3005 | optab this_abs_optab; |
decdfa82 RS |
3006 | |
3007 | /* Find the correct mode for the real and imaginary parts. */ | |
27e58a70 | 3008 | enum machine_mode submode = GET_MODE_INNER (mode); |
decdfa82 RS |
3009 | |
3010 | if (submode == BLKmode) | |
3011 | abort (); | |
3012 | ||
decdfa82 | 3013 | if (flag_force_mem) |
ad76cef8 | 3014 | op0 = force_not_mem (op0); |
decdfa82 | 3015 | |
abd418d3 RS |
3016 | last = get_last_insn (); |
3017 | ||
91ce572a CC |
3018 | this_abs_optab = ! unsignedp && flag_trapv |
3019 | && (GET_MODE_CLASS(mode) == MODE_INT) | |
3020 | ? absv_optab : abs_optab; | |
3021 | ||
3022 | if (this_abs_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing) | |
decdfa82 | 3023 | { |
91ce572a | 3024 | int icode = (int) this_abs_optab->handlers[(int) mode].insn_code; |
a995e389 | 3025 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; |
decdfa82 RS |
3026 | rtx xop0 = op0; |
3027 | ||
3028 | if (target) | |
3029 | temp = target; | |
3030 | else | |
3031 | temp = gen_reg_rtx (submode); | |
3032 | ||
3033 | if (GET_MODE (xop0) != VOIDmode | |
3034 | && GET_MODE (xop0) != mode0) | |
3035 | xop0 = convert_to_mode (mode0, xop0, unsignedp); | |
3036 | ||
3037 | /* Now, if insn doesn't accept our operand, put it into a pseudo. */ | |
3038 | ||
a995e389 | 3039 | if (! (*insn_data[icode].operand[1].predicate) (xop0, mode0)) |
decdfa82 RS |
3040 | xop0 = copy_to_mode_reg (mode0, xop0); |
3041 | ||
a995e389 | 3042 | if (! (*insn_data[icode].operand[0].predicate) (temp, submode)) |
decdfa82 RS |
3043 | temp = gen_reg_rtx (submode); |
3044 | ||
3045 | pat = GEN_FCN (icode) (temp, xop0); | |
3046 | if (pat) | |
3047 | { | |
2f937369 | 3048 | if (INSN_P (pat) && NEXT_INSN (pat) != NULL_RTX |
0c20a65f | 3049 | && ! add_equal_note (pat, temp, this_abs_optab->code, xop0, |
91ce572a | 3050 | NULL_RTX)) |
decdfa82 RS |
3051 | { |
3052 | delete_insns_since (last); | |
0c20a65f | 3053 | return expand_unop (mode, this_abs_optab, op0, NULL_RTX, |
91ce572a | 3054 | unsignedp); |
decdfa82 RS |
3055 | } |
3056 | ||
3057 | emit_insn (pat); | |
0c20a65f | 3058 | |
decdfa82 RS |
3059 | return temp; |
3060 | } | |
3061 | else | |
3062 | delete_insns_since (last); | |
3063 | } | |
3064 | ||
3065 | /* It can't be done in this mode. Can we open-code it in a wider mode? */ | |
3066 | ||
3067 | for (wider_mode = GET_MODE_WIDER_MODE (mode); wider_mode != VOIDmode; | |
3068 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) | |
3069 | { | |
0c20a65f | 3070 | if (this_abs_optab->handlers[(int) wider_mode].insn_code |
91ce572a | 3071 | != CODE_FOR_nothing) |
decdfa82 RS |
3072 | { |
3073 | rtx xop0 = op0; | |
3074 | ||
0661a3de | 3075 | xop0 = convert_modes (wider_mode, mode, xop0, unsignedp); |
decdfa82 RS |
3076 | temp = expand_complex_abs (wider_mode, xop0, NULL_RTX, unsignedp); |
3077 | ||
3078 | if (temp) | |
3079 | { | |
3080 | if (class != MODE_COMPLEX_INT) | |
3081 | { | |
3082 | if (target == 0) | |
3083 | target = gen_reg_rtx (submode); | |
3084 | convert_move (target, temp, 0); | |
3085 | return target; | |
3086 | } | |
3087 | else | |
3088 | return gen_lowpart (submode, temp); | |
3089 | } | |
3090 | else | |
3091 | delete_insns_since (last); | |
3092 | } | |
3093 | } | |
3094 | ||
3095 | /* Open-code the complex absolute-value operation | |
3096 | if we can open-code sqrt. Otherwise it's not worth while. */ | |
10e927ef CC |
3097 | if (sqrt_optab->handlers[(int) submode].insn_code != CODE_FOR_nothing |
3098 | && ! flag_trapv) | |
decdfa82 RS |
3099 | { |
3100 | rtx real, imag, total; | |
3101 | ||
3102 | real = gen_realpart (submode, op0); | |
3103 | imag = gen_imagpart (submode, op0); | |
9061e4cd | 3104 | |
decdfa82 | 3105 | /* Square both parts. */ |
9061e4cd RK |
3106 | real = expand_mult (submode, real, real, NULL_RTX, 0); |
3107 | imag = expand_mult (submode, imag, imag, NULL_RTX, 0); | |
3108 | ||
decdfa82 | 3109 | /* Sum the parts. */ |
73d9a835 | 3110 | total = expand_binop (submode, add_optab, real, imag, NULL_RTX, |
decdfa82 | 3111 | 0, OPTAB_LIB_WIDEN); |
9061e4cd | 3112 | |
decdfa82 RS |
3113 | /* Get sqrt in TARGET. Set TARGET to where the result is. */ |
3114 | target = expand_unop (submode, sqrt_optab, total, target, 0); | |
3115 | if (target == 0) | |
3116 | delete_insns_since (last); | |
3117 | else | |
3118 | return target; | |
3119 | } | |
3120 | ||
3121 | /* Now try a library call in this mode. */ | |
91ce572a | 3122 | if (this_abs_optab->handlers[(int) mode].libfunc) |
decdfa82 RS |
3123 | { |
3124 | rtx insns; | |
a0bc0933 | 3125 | rtx value; |
decdfa82 RS |
3126 | |
3127 | start_sequence (); | |
3128 | ||
3129 | /* Pass 1 for NO_QUEUE so we don't lose any increments | |
3130 | if the libcall is cse'd or moved. */ | |
9a7f678c | 3131 | value = emit_library_call_value (abs_optab->handlers[(int) mode].libfunc, |
ebb1b59a | 3132 | NULL_RTX, LCT_CONST, submode, 1, op0, mode); |
decdfa82 RS |
3133 | insns = get_insns (); |
3134 | end_sequence (); | |
3135 | ||
3136 | target = gen_reg_rtx (submode); | |
9a7f678c | 3137 | emit_libcall_block (insns, target, value, |
91ce572a | 3138 | gen_rtx_fmt_e (this_abs_optab->code, mode, op0)); |
decdfa82 RS |
3139 | |
3140 | return target; | |
3141 | } | |
3142 | ||
3143 | /* It can't be done in this mode. Can we do it in a wider mode? */ | |
3144 | ||
3145 | for (wider_mode = GET_MODE_WIDER_MODE (mode); wider_mode != VOIDmode; | |
3146 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) | |
3147 | { | |
91ce572a | 3148 | if ((this_abs_optab->handlers[(int) wider_mode].insn_code |
decdfa82 | 3149 | != CODE_FOR_nothing) |
91ce572a | 3150 | || this_abs_optab->handlers[(int) wider_mode].libfunc) |
decdfa82 RS |
3151 | { |
3152 | rtx xop0 = op0; | |
3153 | ||
0661a3de | 3154 | xop0 = convert_modes (wider_mode, mode, xop0, unsignedp); |
decdfa82 RS |
3155 | |
3156 | temp = expand_complex_abs (wider_mode, xop0, NULL_RTX, unsignedp); | |
3157 | ||
3158 | if (temp) | |
3159 | { | |
3160 | if (class != MODE_COMPLEX_INT) | |
3161 | { | |
3162 | if (target == 0) | |
3163 | target = gen_reg_rtx (submode); | |
3164 | convert_move (target, temp, 0); | |
3165 | return target; | |
3166 | } | |
3167 | else | |
3168 | return gen_lowpart (submode, temp); | |
3169 | } | |
3170 | else | |
3171 | delete_insns_since (last); | |
3172 | } | |
3173 | } | |
3174 | ||
abd418d3 | 3175 | delete_insns_since (entry_last); |
decdfa82 RS |
3176 | return 0; |
3177 | } | |
3178 | \f | |
77c9c6c2 RK |
3179 | /* Generate an instruction whose insn-code is INSN_CODE, |
3180 | with two operands: an output TARGET and an input OP0. | |
3181 | TARGET *must* be nonzero, and the output is always stored there. | |
3182 | CODE is an rtx code such that (CODE OP0) is an rtx that describes | |
3183 | the value that is stored into TARGET. */ | |
3184 | ||
3185 | void | |
0c20a65f | 3186 | emit_unop_insn (int icode, rtx target, rtx op0, enum rtx_code code) |
77c9c6c2 | 3187 | { |
b3694847 | 3188 | rtx temp; |
a995e389 | 3189 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; |
77c9c6c2 RK |
3190 | rtx pat; |
3191 | ||
ad76cef8 | 3192 | temp = target; |
77c9c6c2 | 3193 | |
bd8c4b14 ILT |
3194 | /* Sign and zero extension from memory is often done specially on |
3195 | RISC machines, so forcing into a register here can pessimize | |
3196 | code. */ | |
3197 | if (flag_force_mem && code != SIGN_EXTEND && code != ZERO_EXTEND) | |
77c9c6c2 RK |
3198 | op0 = force_not_mem (op0); |
3199 | ||
3200 | /* Now, if insn does not accept our operands, put them into pseudos. */ | |
3201 | ||
a995e389 | 3202 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) |
77c9c6c2 RK |
3203 | op0 = copy_to_mode_reg (mode0, op0); |
3204 | ||
a995e389 | 3205 | if (! (*insn_data[icode].operand[0].predicate) (temp, GET_MODE (temp)) |
3c0cb5de | 3206 | || (flag_force_mem && MEM_P (temp))) |
77c9c6c2 RK |
3207 | temp = gen_reg_rtx (GET_MODE (temp)); |
3208 | ||
3209 | pat = GEN_FCN (icode) (temp, op0); | |
3210 | ||
2f937369 | 3211 | if (INSN_P (pat) && NEXT_INSN (pat) != NULL_RTX && code != UNKNOWN) |
b1ec3c92 | 3212 | add_equal_note (pat, temp, code, op0, NULL_RTX); |
0c20a65f | 3213 | |
77c9c6c2 RK |
3214 | emit_insn (pat); |
3215 | ||
3216 | if (temp != target) | |
3217 | emit_move_insn (target, temp); | |
3218 | } | |
3219 | \f | |
3220 | /* Emit code to perform a series of operations on a multi-word quantity, one | |
3221 | word at a time. | |
3222 | ||
d45cf215 | 3223 | Such a block is preceded by a CLOBBER of the output, consists of multiple |
77c9c6c2 RK |
3224 | insns, each setting one word of the output, and followed by a SET copying |
3225 | the output to itself. | |
3226 | ||
3227 | Each of the insns setting words of the output receives a REG_NO_CONFLICT | |
3228 | note indicating that it doesn't conflict with the (also multi-word) | |
3229 | inputs. The entire block is surrounded by REG_LIBCALL and REG_RETVAL | |
3230 | notes. | |
3231 | ||
3232 | INSNS is a block of code generated to perform the operation, not including | |
3233 | the CLOBBER and final copy. All insns that compute intermediate values | |
0c20a65f | 3234 | are first emitted, followed by the block as described above. |
77c9c6c2 RK |
3235 | |
3236 | TARGET, OP0, and OP1 are the output and inputs of the operations, | |
3237 | respectively. OP1 may be zero for a unary operation. | |
3238 | ||
40f03658 | 3239 | EQUIV, if nonzero, is an expression to be placed into a REG_EQUAL note |
77c9c6c2 RK |
3240 | on the last insn. |
3241 | ||
3242 | If TARGET is not a register, INSNS is simply emitted with no special | |
dce39da6 RK |
3243 | processing. Likewise if anything in INSNS is not an INSN or if |
3244 | there is a libcall block inside INSNS. | |
77c9c6c2 RK |
3245 | |
3246 | The final insn emitted is returned. */ | |
3247 | ||
3248 | rtx | |
0c20a65f | 3249 | emit_no_conflict_block (rtx insns, rtx target, rtx op0, rtx op1, rtx equiv) |
77c9c6c2 RK |
3250 | { |
3251 | rtx prev, next, first, last, insn; | |
3252 | ||
f8cfc6aa | 3253 | if (!REG_P (target) || reload_in_progress) |
2f937369 | 3254 | return emit_insn (insns); |
dce39da6 RK |
3255 | else |
3256 | for (insn = insns; insn; insn = NEXT_INSN (insn)) | |
4b4bf941 | 3257 | if (!NONJUMP_INSN_P (insn) |
dce39da6 | 3258 | || find_reg_note (insn, REG_LIBCALL, NULL_RTX)) |
2f937369 | 3259 | return emit_insn (insns); |
77c9c6c2 RK |
3260 | |
3261 | /* First emit all insns that do not store into words of the output and remove | |
3262 | these from the list. */ | |
3263 | for (insn = insns; insn; insn = next) | |
3264 | { | |
218aa620 | 3265 | rtx set = 0, note; |
77c9c6c2 RK |
3266 | int i; |
3267 | ||
3268 | next = NEXT_INSN (insn); | |
3269 | ||
dcc24678 | 3270 | /* Some ports (cris) create a libcall regions at their own. We must |
218aa620 JH |
3271 | avoid any potential nesting of LIBCALLs. */ |
3272 | if ((note = find_reg_note (insn, REG_LIBCALL, NULL)) != NULL) | |
3273 | remove_note (insn, note); | |
3274 | if ((note = find_reg_note (insn, REG_RETVAL, NULL)) != NULL) | |
3275 | remove_note (insn, note); | |
3276 | ||
c5c76735 JL |
3277 | if (GET_CODE (PATTERN (insn)) == SET || GET_CODE (PATTERN (insn)) == USE |
3278 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
77c9c6c2 RK |
3279 | set = PATTERN (insn); |
3280 | else if (GET_CODE (PATTERN (insn)) == PARALLEL) | |
3281 | { | |
3282 | for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++) | |
3283 | if (GET_CODE (XVECEXP (PATTERN (insn), 0, i)) == SET) | |
3284 | { | |
3285 | set = XVECEXP (PATTERN (insn), 0, i); | |
3286 | break; | |
3287 | } | |
3288 | } | |
3289 | ||
3290 | if (set == 0) | |
3291 | abort (); | |
3292 | ||
3293 | if (! reg_overlap_mentioned_p (target, SET_DEST (set))) | |
3294 | { | |
3295 | if (PREV_INSN (insn)) | |
3296 | NEXT_INSN (PREV_INSN (insn)) = next; | |
3297 | else | |
3298 | insns = next; | |
3299 | ||
3300 | if (next) | |
3301 | PREV_INSN (next) = PREV_INSN (insn); | |
3302 | ||
3303 | add_insn (insn); | |
3304 | } | |
3305 | } | |
3306 | ||
3307 | prev = get_last_insn (); | |
3308 | ||
3309 | /* Now write the CLOBBER of the output, followed by the setting of each | |
3310 | of the words, followed by the final copy. */ | |
3311 | if (target != op0 && target != op1) | |
9e6a5703 | 3312 | emit_insn (gen_rtx_CLOBBER (VOIDmode, target)); |
77c9c6c2 RK |
3313 | |
3314 | for (insn = insns; insn; insn = next) | |
3315 | { | |
3316 | next = NEXT_INSN (insn); | |
3317 | add_insn (insn); | |
3318 | ||
f8cfc6aa | 3319 | if (op1 && REG_P (op1)) |
9e6a5703 JC |
3320 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_NO_CONFLICT, op1, |
3321 | REG_NOTES (insn)); | |
77c9c6c2 | 3322 | |
f8cfc6aa | 3323 | if (op0 && REG_P (op0)) |
9e6a5703 JC |
3324 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_NO_CONFLICT, op0, |
3325 | REG_NOTES (insn)); | |
77c9c6c2 RK |
3326 | } |
3327 | ||
54e7b5e6 RS |
3328 | if (mov_optab->handlers[(int) GET_MODE (target)].insn_code |
3329 | != CODE_FOR_nothing) | |
3330 | { | |
3331 | last = emit_move_insn (target, target); | |
3332 | if (equiv) | |
5fa671cf | 3333 | set_unique_reg_note (last, REG_EQUAL, equiv); |
54e7b5e6 RS |
3334 | } |
3335 | else | |
07edd4c5 HPN |
3336 | { |
3337 | last = get_last_insn (); | |
3338 | ||
3339 | /* Remove any existing REG_EQUAL note from "last", or else it will | |
3340 | be mistaken for a note referring to the full contents of the | |
3341 | alleged libcall value when found together with the REG_RETVAL | |
3342 | note added below. An existing note can come from an insn | |
3343 | expansion at "last". */ | |
3344 | remove_note (last, find_reg_note (last, REG_EQUAL, NULL_RTX)); | |
3345 | } | |
77c9c6c2 RK |
3346 | |
3347 | if (prev == 0) | |
3348 | first = get_insns (); | |
3349 | else | |
3350 | first = NEXT_INSN (prev); | |
3351 | ||
3352 | /* Encapsulate the block so it gets manipulated as a unit. */ | |
9e6a5703 JC |
3353 | REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, |
3354 | REG_NOTES (first)); | |
3355 | REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last)); | |
77c9c6c2 RK |
3356 | |
3357 | return last; | |
3358 | } | |
3359 | \f | |
3360 | /* Emit code to make a call to a constant function or a library call. | |
3361 | ||
3362 | INSNS is a list containing all insns emitted in the call. | |
3363 | These insns leave the result in RESULT. Our block is to copy RESULT | |
3364 | to TARGET, which is logically equivalent to EQUIV. | |
3365 | ||
3366 | We first emit any insns that set a pseudo on the assumption that these are | |
3367 | loading constants into registers; doing so allows them to be safely cse'ed | |
3368 | between blocks. Then we emit all the other insns in the block, followed by | |
3369 | an insn to move RESULT to TARGET. This last insn will have a REQ_EQUAL | |
3370 | note with an operand of EQUIV. | |
3371 | ||
29ebe69a RK |
3372 | Moving assignments to pseudos outside of the block is done to improve |
3373 | the generated code, but is not required to generate correct code, | |
3374 | hence being unable to move an assignment is not grounds for not making | |
3375 | a libcall block. There are two reasons why it is safe to leave these | |
3376 | insns inside the block: First, we know that these pseudos cannot be | |
3377 | used in generated RTL outside the block since they are created for | |
3378 | temporary purposes within the block. Second, CSE will not record the | |
3379 | values of anything set inside a libcall block, so we know they must | |
3380 | be dead at the end of the block. | |
3381 | ||
77c9c6c2 RK |
3382 | Except for the first group of insns (the ones setting pseudos), the |
3383 | block is delimited by REG_RETVAL and REG_LIBCALL notes. */ | |
3384 | ||
3385 | void | |
0c20a65f | 3386 | emit_libcall_block (rtx insns, rtx target, rtx result, rtx equiv) |
77c9c6c2 | 3387 | { |
aff2c2d3 | 3388 | rtx final_dest = target; |
77c9c6c2 RK |
3389 | rtx prev, next, first, last, insn; |
3390 | ||
aff2c2d3 BS |
3391 | /* If this is a reg with REG_USERVAR_P set, then it could possibly turn |
3392 | into a MEM later. Protect the libcall block from this change. */ | |
3393 | if (! REG_P (target) || REG_USERVAR_P (target)) | |
3394 | target = gen_reg_rtx (GET_MODE (target)); | |
0c20a65f | 3395 | |
5154e79a AH |
3396 | /* If we're using non-call exceptions, a libcall corresponding to an |
3397 | operation that may trap may also trap. */ | |
3398 | if (flag_non_call_exceptions && may_trap_p (equiv)) | |
3399 | { | |
3400 | for (insn = insns; insn; insn = NEXT_INSN (insn)) | |
4b4bf941 | 3401 | if (CALL_P (insn)) |
5154e79a AH |
3402 | { |
3403 | rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX); | |
0c20a65f | 3404 | |
5154e79a AH |
3405 | if (note != 0 && INTVAL (XEXP (note, 0)) <= 0) |
3406 | remove_note (insn, note); | |
3407 | } | |
3408 | } | |
3409 | else | |
b472794d | 3410 | /* look for any CALL_INSNs in this sequence, and attach a REG_EH_REGION |
c29ea88a | 3411 | reg note to indicate that this call cannot throw or execute a nonlocal |
cf67d231 | 3412 | goto (unless there is already a REG_EH_REGION note, in which case |
897aa57f | 3413 | we update it). */ |
5154e79a | 3414 | for (insn = insns; insn; insn = NEXT_INSN (insn)) |
4b4bf941 | 3415 | if (CALL_P (insn)) |
5154e79a AH |
3416 | { |
3417 | rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX); | |
0c20a65f | 3418 | |
5154e79a | 3419 | if (note != 0) |
60c81c89 | 3420 | XEXP (note, 0) = constm1_rtx; |
5154e79a | 3421 | else |
60c81c89 | 3422 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EH_REGION, constm1_rtx, |
5154e79a AH |
3423 | REG_NOTES (insn)); |
3424 | } | |
b472794d | 3425 | |
77c9c6c2 | 3426 | /* First emit all insns that set pseudos. Remove them from the list as |
ccf5f342 | 3427 | we go. Avoid insns that set pseudos which were referenced in previous |
29ebe69a | 3428 | insns. These can be generated by move_by_pieces, for example, |
ccf5f342 RK |
3429 | to update an address. Similarly, avoid insns that reference things |
3430 | set in previous insns. */ | |
77c9c6c2 RK |
3431 | |
3432 | for (insn = insns; insn; insn = next) | |
3433 | { | |
3434 | rtx set = single_set (insn); | |
218aa620 JH |
3435 | rtx note; |
3436 | ||
dcc24678 | 3437 | /* Some ports (cris) create a libcall regions at their own. We must |
218aa620 JH |
3438 | avoid any potential nesting of LIBCALLs. */ |
3439 | if ((note = find_reg_note (insn, REG_LIBCALL, NULL)) != NULL) | |
3440 | remove_note (insn, note); | |
3441 | if ((note = find_reg_note (insn, REG_RETVAL, NULL)) != NULL) | |
3442 | remove_note (insn, note); | |
77c9c6c2 RK |
3443 | |
3444 | next = NEXT_INSN (insn); | |
3445 | ||
f8cfc6aa | 3446 | if (set != 0 && REG_P (SET_DEST (set)) |
29ebe69a | 3447 | && REGNO (SET_DEST (set)) >= FIRST_PSEUDO_REGISTER |
8d9e73cc | 3448 | && (insn == insns |
9485c46e DM |
3449 | || ((! INSN_P(insns) |
3450 | || ! reg_mentioned_p (SET_DEST (set), PATTERN (insns))) | |
ccf5f342 RK |
3451 | && ! reg_used_between_p (SET_DEST (set), insns, insn) |
3452 | && ! modified_in_p (SET_SRC (set), insns) | |
3453 | && ! modified_between_p (SET_SRC (set), insns, insn)))) | |
77c9c6c2 RK |
3454 | { |
3455 | if (PREV_INSN (insn)) | |
3456 | NEXT_INSN (PREV_INSN (insn)) = next; | |
3457 | else | |
3458 | insns = next; | |
3459 | ||
3460 | if (next) | |
3461 | PREV_INSN (next) = PREV_INSN (insn); | |
3462 | ||
3463 | add_insn (insn); | |
3464 | } | |
695a94b3 RS |
3465 | |
3466 | /* Some ports use a loop to copy large arguments onto the stack. | |
3467 | Don't move anything outside such a loop. */ | |
4b4bf941 | 3468 | if (LABEL_P (insn)) |
695a94b3 | 3469 | break; |
77c9c6c2 RK |
3470 | } |
3471 | ||
3472 | prev = get_last_insn (); | |
3473 | ||
3474 | /* Write the remaining insns followed by the final copy. */ | |
3475 | ||
3476 | for (insn = insns; insn; insn = next) | |
3477 | { | |
3478 | next = NEXT_INSN (insn); | |
3479 | ||
3480 | add_insn (insn); | |
3481 | } | |
3482 | ||
3483 | last = emit_move_insn (target, result); | |
02214a5c RK |
3484 | if (mov_optab->handlers[(int) GET_MODE (target)].insn_code |
3485 | != CODE_FOR_nothing) | |
5fa671cf | 3486 | set_unique_reg_note (last, REG_EQUAL, copy_rtx (equiv)); |
07edd4c5 HPN |
3487 | else |
3488 | { | |
3489 | /* Remove any existing REG_EQUAL note from "last", or else it will | |
3490 | be mistaken for a note referring to the full contents of the | |
3491 | libcall value when found together with the REG_RETVAL note added | |
3492 | below. An existing note can come from an insn expansion at | |
3493 | "last". */ | |
3494 | remove_note (last, find_reg_note (last, REG_EQUAL, NULL_RTX)); | |
3495 | } | |
77c9c6c2 | 3496 | |
e85427f9 BS |
3497 | if (final_dest != target) |
3498 | emit_move_insn (final_dest, target); | |
aff2c2d3 | 3499 | |
77c9c6c2 RK |
3500 | if (prev == 0) |
3501 | first = get_insns (); | |
3502 | else | |
3503 | first = NEXT_INSN (prev); | |
3504 | ||
3505 | /* Encapsulate the block so it gets manipulated as a unit. */ | |
11e9ecc5 HB |
3506 | if (!flag_non_call_exceptions || !may_trap_p (equiv)) |
3507 | { | |
4a69cf79 JZ |
3508 | /* We can't attach the REG_LIBCALL and REG_RETVAL notes |
3509 | when the encapsulated region would not be in one basic block, | |
3510 | i.e. when there is a control_flow_insn_p insn between FIRST and LAST. | |
3511 | */ | |
3512 | bool attach_libcall_retval_notes = true; | |
3513 | next = NEXT_INSN (last); | |
3514 | for (insn = first; insn != next; insn = NEXT_INSN (insn)) | |
3515 | if (control_flow_insn_p (insn)) | |
3516 | { | |
3517 | attach_libcall_retval_notes = false; | |
3518 | break; | |
3519 | } | |
3520 | ||
3521 | if (attach_libcall_retval_notes) | |
3522 | { | |
3523 | REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, | |
3524 | REG_NOTES (first)); | |
3525 | REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, | |
3526 | REG_NOTES (last)); | |
3527 | } | |
11e9ecc5 | 3528 | } |
77c9c6c2 RK |
3529 | } |
3530 | \f | |
3531 | /* Generate code to store zero in X. */ | |
3532 | ||
3533 | void | |
0c20a65f | 3534 | emit_clr_insn (rtx x) |
77c9c6c2 RK |
3535 | { |
3536 | emit_move_insn (x, const0_rtx); | |
3537 | } | |
3538 | ||
3539 | /* Generate code to store 1 in X | |
3540 | assuming it contains zero beforehand. */ | |
3541 | ||
3542 | void | |
0c20a65f | 3543 | emit_0_to_1_insn (rtx x) |
77c9c6c2 RK |
3544 | { |
3545 | emit_move_insn (x, const1_rtx); | |
3546 | } | |
3547 | ||
1c0290ea | 3548 | /* Nonzero if we can perform a comparison of mode MODE straightforwardly. |
1eb8759b RH |
3549 | PURPOSE describes how this comparison will be used. CODE is the rtx |
3550 | comparison code we will be using. | |
3551 | ||
3552 | ??? Actually, CODE is slightly weaker than that. A target is still | |
0c20a65f | 3553 | required to implement all of the normal bcc operations, but not |
1eb8759b | 3554 | required to implement all (or any) of the unordered bcc operations. */ |
0c20a65f | 3555 | |
1c0290ea | 3556 | int |
0c20a65f AJ |
3557 | can_compare_p (enum rtx_code code, enum machine_mode mode, |
3558 | enum can_compare_purpose purpose) | |
b30f05db BS |
3559 | { |
3560 | do | |
3561 | { | |
7e1a450d | 3562 | if (cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing) |
1eb8759b RH |
3563 | { |
3564 | if (purpose == ccp_jump) | |
7e1a450d | 3565 | return bcc_gen_fctn[(int) code] != NULL; |
1eb8759b | 3566 | else if (purpose == ccp_store_flag) |
7e1a450d | 3567 | return setcc_gen_code[(int) code] != CODE_FOR_nothing; |
1eb8759b RH |
3568 | else |
3569 | /* There's only one cmov entry point, and it's allowed to fail. */ | |
3570 | return 1; | |
3571 | } | |
1c0290ea | 3572 | if (purpose == ccp_jump |
7e1a450d | 3573 | && cbranch_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing) |
1c0290ea BS |
3574 | return 1; |
3575 | if (purpose == ccp_cmov | |
7e1a450d | 3576 | && cmov_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing) |
1c0290ea BS |
3577 | return 1; |
3578 | if (purpose == ccp_store_flag | |
7e1a450d | 3579 | && cstore_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing) |
1c0290ea BS |
3580 | return 1; |
3581 | ||
b30f05db | 3582 | mode = GET_MODE_WIDER_MODE (mode); |
1c0290ea BS |
3583 | } |
3584 | while (mode != VOIDmode); | |
b30f05db BS |
3585 | |
3586 | return 0; | |
3587 | } | |
3588 | ||
3589 | /* This function is called when we are going to emit a compare instruction that | |
3590 | compares the values found in *PX and *PY, using the rtl operator COMPARISON. | |
3591 | ||
3592 | *PMODE is the mode of the inputs (in case they are const_int). | |
3593 | *PUNSIGNEDP nonzero says that the operands are unsigned; | |
77c9c6c2 RK |
3594 | this matters if they need to be widened. |
3595 | ||
a06ef755 | 3596 | If they have mode BLKmode, then SIZE specifies the size of both operands. |
77c9c6c2 | 3597 | |
b30f05db BS |
3598 | This function performs all the setup necessary so that the caller only has |
3599 | to emit a single comparison insn. This setup can involve doing a BLKmode | |
3600 | comparison or emitting a library call to perform the comparison if no insn | |
3601 | is available to handle it. | |
3602 | The values which are passed in through pointers can be modified; the caller | |
3603 | should perform the comparison on the modified values. */ | |
77c9c6c2 | 3604 | |
a06ef755 | 3605 | static void |
0c20a65f AJ |
3606 | prepare_cmp_insn (rtx *px, rtx *py, enum rtx_code *pcomparison, rtx size, |
3607 | enum machine_mode *pmode, int *punsignedp, | |
3608 | enum can_compare_purpose purpose) | |
77c9c6c2 | 3609 | { |
b30f05db BS |
3610 | enum machine_mode mode = *pmode; |
3611 | rtx x = *px, y = *py; | |
3612 | int unsignedp = *punsignedp; | |
77c9c6c2 | 3613 | enum mode_class class; |
77c9c6c2 RK |
3614 | |
3615 | class = GET_MODE_CLASS (mode); | |
3616 | ||
3617 | /* They could both be VOIDmode if both args are immediate constants, | |
3618 | but we should fold that at an earlier stage. | |
3619 | With no special code here, this will call abort, | |
3620 | reminding the programmer to implement such folding. */ | |
3621 | ||
3622 | if (mode != BLKmode && flag_force_mem) | |
3623 | { | |
894207cf RS |
3624 | /* Load duplicate non-volatile operands once. */ |
3625 | if (rtx_equal_p (x, y) && ! volatile_refs_p (x)) | |
3626 | { | |
3627 | x = force_not_mem (x); | |
3628 | y = x; | |
3629 | } | |
3630 | else | |
3631 | { | |
3632 | x = force_not_mem (x); | |
3633 | y = force_not_mem (y); | |
3634 | } | |
77c9c6c2 RK |
3635 | } |
3636 | ||
3637 | /* If we are inside an appropriately-short loop and one operand is an | |
3638 | expensive constant, force it into a register. */ | |
19caa751 | 3639 | if (CONSTANT_P (x) && preserve_subexpressions_p () |
b437f1a7 | 3640 | && rtx_cost (x, COMPARE) > COSTS_N_INSNS (1)) |
77c9c6c2 RK |
3641 | x = force_reg (mode, x); |
3642 | ||
19caa751 | 3643 | if (CONSTANT_P (y) && preserve_subexpressions_p () |
b437f1a7 | 3644 | && rtx_cost (y, COMPARE) > COSTS_N_INSNS (1)) |
77c9c6c2 RK |
3645 | y = force_reg (mode, y); |
3646 | ||
362cc3d4 MH |
3647 | #ifdef HAVE_cc0 |
3648 | /* Abort if we have a non-canonical comparison. The RTL documentation | |
3649 | states that canonical comparisons are required only for targets which | |
3650 | have cc0. */ | |
3651 | if (CONSTANT_P (x) && ! CONSTANT_P (y)) | |
7e1a450d | 3652 | abort (); |
362cc3d4 MH |
3653 | #endif |
3654 | ||
77c9c6c2 RK |
3655 | /* Don't let both operands fail to indicate the mode. */ |
3656 | if (GET_MODE (x) == VOIDmode && GET_MODE (y) == VOIDmode) | |
3657 | x = force_reg (mode, x); | |
3658 | ||
3659 | /* Handle all BLKmode compares. */ | |
3660 | ||
3661 | if (mode == BLKmode) | |
3662 | { | |
118355a0 ZW |
3663 | enum machine_mode cmp_mode, result_mode; |
3664 | enum insn_code cmp_code; | |
3665 | tree length_type; | |
3666 | rtx libfunc; | |
b30f05db | 3667 | rtx result; |
118355a0 | 3668 | rtx opalign |
f4dc10d1 | 3669 | = GEN_INT (MIN (MEM_ALIGN (x), MEM_ALIGN (y)) / BITS_PER_UNIT); |
b30f05db | 3670 | |
118355a0 ZW |
3671 | if (size == 0) |
3672 | abort (); | |
3673 | ||
118355a0 ZW |
3674 | /* Try to use a memory block compare insn - either cmpstr |
3675 | or cmpmem will do. */ | |
3676 | for (cmp_mode = GET_CLASS_NARROWEST_MODE (MODE_INT); | |
3677 | cmp_mode != VOIDmode; | |
3678 | cmp_mode = GET_MODE_WIDER_MODE (cmp_mode)) | |
358b8f01 | 3679 | { |
118355a0 ZW |
3680 | cmp_code = cmpmem_optab[cmp_mode]; |
3681 | if (cmp_code == CODE_FOR_nothing) | |
3682 | cmp_code = cmpstr_optab[cmp_mode]; | |
3683 | if (cmp_code == CODE_FOR_nothing) | |
3684 | continue; | |
3685 | ||
3686 | /* Must make sure the size fits the insn's mode. */ | |
3687 | if ((GET_CODE (size) == CONST_INT | |
3688 | && INTVAL (size) >= (1 << GET_MODE_BITSIZE (cmp_mode))) | |
3689 | || (GET_MODE_BITSIZE (GET_MODE (size)) | |
3690 | > GET_MODE_BITSIZE (cmp_mode))) | |
3691 | continue; | |
3692 | ||
3693 | result_mode = insn_data[cmp_code].operand[0].mode; | |
358b8f01 | 3694 | result = gen_reg_rtx (result_mode); |
118355a0 ZW |
3695 | size = convert_to_mode (cmp_mode, size, 1); |
3696 | emit_insn (GEN_FCN (cmp_code) (result, x, y, size, opalign)); | |
3697 | ||
3698 | *px = result; | |
3699 | *py = const0_rtx; | |
3700 | *pmode = result_mode; | |
3701 | return; | |
77c9c6c2 | 3702 | } |
118355a0 | 3703 | |
8f99553f | 3704 | /* Otherwise call a library function, memcmp. */ |
118355a0 ZW |
3705 | libfunc = memcmp_libfunc; |
3706 | length_type = sizetype; | |
118355a0 ZW |
3707 | result_mode = TYPE_MODE (integer_type_node); |
3708 | cmp_mode = TYPE_MODE (length_type); | |
3709 | size = convert_to_mode (TYPE_MODE (length_type), size, | |
8df83eae | 3710 | TYPE_UNSIGNED (length_type)); |
118355a0 ZW |
3711 | |
3712 | result = emit_library_call_value (libfunc, 0, LCT_PURE_MAKE_BLOCK, | |
3713 | result_mode, 3, | |
3714 | XEXP (x, 0), Pmode, | |
3715 | XEXP (y, 0), Pmode, | |
3716 | size, cmp_mode); | |
b30f05db BS |
3717 | *px = result; |
3718 | *py = const0_rtx; | |
3719 | *pmode = result_mode; | |
77c9c6c2 RK |
3720 | return; |
3721 | } | |
3722 | ||
27ab3e91 RH |
3723 | /* Don't allow operands to the compare to trap, as that can put the |
3724 | compare and branch in different basic blocks. */ | |
3725 | if (flag_non_call_exceptions) | |
3726 | { | |
3727 | if (may_trap_p (x)) | |
3728 | x = force_reg (mode, x); | |
3729 | if (may_trap_p (y)) | |
3730 | y = force_reg (mode, y); | |
3731 | } | |
3732 | ||
b30f05db BS |
3733 | *px = x; |
3734 | *py = y; | |
1eb8759b | 3735 | if (can_compare_p (*pcomparison, mode, purpose)) |
b30f05db | 3736 | return; |
77c9c6c2 RK |
3737 | |
3738 | /* Handle a lib call just for the mode we are using. */ | |
3739 | ||
b30f05db | 3740 | if (cmp_optab->handlers[(int) mode].libfunc && class != MODE_FLOAT) |
77c9c6c2 RK |
3741 | { |
3742 | rtx libfunc = cmp_optab->handlers[(int) mode].libfunc; | |
9725066d JL |
3743 | rtx result; |
3744 | ||
77c9c6c2 RK |
3745 | /* If we want unsigned, and this mode has a distinct unsigned |
3746 | comparison routine, use that. */ | |
3747 | if (unsignedp && ucmp_optab->handlers[(int) mode].libfunc) | |
3748 | libfunc = ucmp_optab->handlers[(int) mode].libfunc; | |
3749 | ||
24491a09 KH |
3750 | result = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST_MAKE_BLOCK, |
3751 | word_mode, 2, x, mode, y, mode); | |
9725066d | 3752 | |
77c9c6c2 RK |
3753 | /* Integer comparison returns a result that must be compared against 1, |
3754 | so that even if we do an unsigned compare afterward, | |
3755 | there is still a value that can represent the result "less than". */ | |
b30f05db BS |
3756 | *px = result; |
3757 | *py = const1_rtx; | |
3758 | *pmode = word_mode; | |
77c9c6c2 RK |
3759 | return; |
3760 | } | |
3761 | ||
3762 | if (class == MODE_FLOAT) | |
c5c60e15 | 3763 | prepare_float_lib_cmp (px, py, pcomparison, pmode, punsignedp); |
77c9c6c2 RK |
3764 | |
3765 | else | |
3766 | abort (); | |
3767 | } | |
3768 | ||
b30f05db BS |
3769 | /* Before emitting an insn with code ICODE, make sure that X, which is going |
3770 | to be used for operand OPNUM of the insn, is converted from mode MODE to | |
4fe9b91c | 3771 | WIDER_MODE (UNSIGNEDP determines whether it is an unsigned conversion), and |
b30f05db | 3772 | that it is accepted by the operand predicate. Return the new value. */ |
749a2da1 | 3773 | |
1c0290ea | 3774 | rtx |
0c20a65f AJ |
3775 | prepare_operand (int icode, rtx x, int opnum, enum machine_mode mode, |
3776 | enum machine_mode wider_mode, int unsignedp) | |
b30f05db | 3777 | { |
b30f05db BS |
3778 | if (mode != wider_mode) |
3779 | x = convert_modes (wider_mode, mode, x, unsignedp); | |
3780 | ||
a995e389 RH |
3781 | if (! (*insn_data[icode].operand[opnum].predicate) |
3782 | (x, insn_data[icode].operand[opnum].mode)) | |
d893ccde RH |
3783 | { |
3784 | if (no_new_pseudos) | |
3785 | return NULL_RTX; | |
3786 | x = copy_to_mode_reg (insn_data[icode].operand[opnum].mode, x); | |
3787 | } | |
3788 | ||
b30f05db BS |
3789 | return x; |
3790 | } | |
3791 | ||
3792 | /* Subroutine of emit_cmp_and_jump_insns; this function is called when we know | |
3793 | we can do the comparison. | |
3794 | The arguments are the same as for emit_cmp_and_jump_insns; but LABEL may | |
3795 | be NULL_RTX which indicates that only a comparison is to be generated. */ | |
3796 | ||
3797 | static void | |
0c20a65f AJ |
3798 | emit_cmp_and_jump_insn_1 (rtx x, rtx y, enum machine_mode mode, |
3799 | enum rtx_code comparison, int unsignedp, rtx label) | |
b30f05db BS |
3800 | { |
3801 | rtx test = gen_rtx_fmt_ee (comparison, mode, x, y); | |
3802 | enum mode_class class = GET_MODE_CLASS (mode); | |
3803 | enum machine_mode wider_mode = mode; | |
3804 | ||
3805 | /* Try combined insns first. */ | |
3806 | do | |
3807 | { | |
3808 | enum insn_code icode; | |
3809 | PUT_MODE (test, wider_mode); | |
3810 | ||
1c0290ea | 3811 | if (label) |
0c20a65f | 3812 | { |
7e1a450d | 3813 | icode = cbranch_optab->handlers[(int) wider_mode].insn_code; |
0c20a65f | 3814 | |
1c0290ea BS |
3815 | if (icode != CODE_FOR_nothing |
3816 | && (*insn_data[icode].operand[0].predicate) (test, wider_mode)) | |
3817 | { | |
3818 | x = prepare_operand (icode, x, 1, mode, wider_mode, unsignedp); | |
3819 | y = prepare_operand (icode, y, 2, mode, wider_mode, unsignedp); | |
3820 | emit_jump_insn (GEN_FCN (icode) (test, x, y, label)); | |
3821 | return; | |
3822 | } | |
3823 | } | |
3824 | ||
b30f05db BS |
3825 | /* Handle some compares against zero. */ |
3826 | icode = (int) tst_optab->handlers[(int) wider_mode].insn_code; | |
3827 | if (y == CONST0_RTX (mode) && icode != CODE_FOR_nothing) | |
3828 | { | |
3829 | x = prepare_operand (icode, x, 0, mode, wider_mode, unsignedp); | |
3830 | emit_insn (GEN_FCN (icode) (x)); | |
3831 | if (label) | |
3832 | emit_jump_insn ((*bcc_gen_fctn[(int) comparison]) (label)); | |
3833 | return; | |
3834 | } | |
3835 | ||
3836 | /* Handle compares for which there is a directly suitable insn. */ | |
3837 | ||
3838 | icode = (int) cmp_optab->handlers[(int) wider_mode].insn_code; | |
3839 | if (icode != CODE_FOR_nothing) | |
3840 | { | |
3841 | x = prepare_operand (icode, x, 0, mode, wider_mode, unsignedp); | |
3842 | y = prepare_operand (icode, y, 1, mode, wider_mode, unsignedp); | |
3843 | emit_insn (GEN_FCN (icode) (x, y)); | |
3844 | if (label) | |
3845 | emit_jump_insn ((*bcc_gen_fctn[(int) comparison]) (label)); | |
3846 | return; | |
3847 | } | |
3848 | ||
3849 | if (class != MODE_INT && class != MODE_FLOAT | |
3850 | && class != MODE_COMPLEX_FLOAT) | |
3851 | break; | |
3852 | ||
3853 | wider_mode = GET_MODE_WIDER_MODE (wider_mode); | |
7e1a450d KH |
3854 | } |
3855 | while (wider_mode != VOIDmode); | |
b30f05db BS |
3856 | |
3857 | abort (); | |
3858 | } | |
3859 | ||
362cc3d4 MH |
3860 | /* Generate code to compare X with Y so that the condition codes are |
3861 | set and to jump to LABEL if the condition is true. If X is a | |
3862 | constant and Y is not a constant, then the comparison is swapped to | |
3863 | ensure that the comparison RTL has the canonical form. | |
3864 | ||
c5d5d461 JL |
3865 | UNSIGNEDP nonzero says that X and Y are unsigned; this matters if they |
3866 | need to be widened by emit_cmp_insn. UNSIGNEDP is also used to select | |
3867 | the proper branch condition code. | |
362cc3d4 | 3868 | |
a06ef755 | 3869 | If X and Y have mode BLKmode, then SIZE specifies the size of both X and Y. |
362cc3d4 | 3870 | |
c5d5d461 JL |
3871 | MODE is the mode of the inputs (in case they are const_int). |
3872 | ||
3873 | COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.). It will | |
3874 | be passed unchanged to emit_cmp_insn, then potentially converted into an | |
3875 | unsigned variant based on UNSIGNEDP to select a proper jump instruction. */ | |
362cc3d4 MH |
3876 | |
3877 | void | |
0c20a65f AJ |
3878 | emit_cmp_and_jump_insns (rtx x, rtx y, enum rtx_code comparison, rtx size, |
3879 | enum machine_mode mode, int unsignedp, rtx label) | |
362cc3d4 | 3880 | { |
8c9864f3 JH |
3881 | rtx op0 = x, op1 = y; |
3882 | ||
3883 | /* Swap operands and condition to ensure canonical RTL. */ | |
3884 | if (swap_commutative_operands_p (x, y)) | |
362cc3d4 | 3885 | { |
8c9864f3 JH |
3886 | /* If we're not emitting a branch, this means some caller |
3887 | is out of sync. */ | |
3888 | if (! label) | |
3889 | abort (); | |
3890 | ||
3891 | op0 = y, op1 = x; | |
3892 | comparison = swap_condition (comparison); | |
362cc3d4 | 3893 | } |
0ca40216 JL |
3894 | |
3895 | #ifdef HAVE_cc0 | |
3896 | /* If OP0 is still a constant, then both X and Y must be constants. Force | |
3897 | X into a register to avoid aborting in emit_cmp_insn due to non-canonical | |
3898 | RTL. */ | |
3899 | if (CONSTANT_P (op0)) | |
3900 | op0 = force_reg (mode, op0); | |
3901 | #endif | |
3902 | ||
c5d5d461 JL |
3903 | if (unsignedp) |
3904 | comparison = unsigned_condition (comparison); | |
a06ef755 RK |
3905 | |
3906 | prepare_cmp_insn (&op0, &op1, &comparison, size, &mode, &unsignedp, | |
1c0290ea | 3907 | ccp_jump); |
b30f05db BS |
3908 | emit_cmp_and_jump_insn_1 (op0, op1, mode, comparison, unsignedp, label); |
3909 | } | |
3910 | ||
3911 | /* Like emit_cmp_and_jump_insns, but generate only the comparison. */ | |
19caa751 | 3912 | |
b30f05db | 3913 | void |
0c20a65f AJ |
3914 | emit_cmp_insn (rtx x, rtx y, enum rtx_code comparison, rtx size, |
3915 | enum machine_mode mode, int unsignedp) | |
b30f05db | 3916 | { |
a06ef755 | 3917 | emit_cmp_and_jump_insns (x, y, comparison, size, mode, unsignedp, 0); |
362cc3d4 | 3918 | } |
77c9c6c2 RK |
3919 | \f |
3920 | /* Emit a library call comparison between floating point X and Y. | |
3921 | COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.). */ | |
3922 | ||
c5c60e15 | 3923 | static void |
0c20a65f AJ |
3924 | prepare_float_lib_cmp (rtx *px, rtx *py, enum rtx_code *pcomparison, |
3925 | enum machine_mode *pmode, int *punsignedp) | |
77c9c6c2 | 3926 | { |
c5c60e15 | 3927 | enum rtx_code comparison = *pcomparison; |
c9034561 | 3928 | enum rtx_code swapped = swap_condition (comparison); |
ad76cef8 PB |
3929 | rtx x = *px; |
3930 | rtx y = *py; | |
c9034561 ZW |
3931 | enum machine_mode orig_mode = GET_MODE (x); |
3932 | enum machine_mode mode; | |
37bf20ee | 3933 | rtx value, target, insns, equiv; |
0a300065 | 3934 | rtx libfunc = 0; |
77c9c6c2 | 3935 | |
c9034561 | 3936 | for (mode = orig_mode; mode != VOIDmode; mode = GET_MODE_WIDER_MODE (mode)) |
77c9c6c2 | 3937 | { |
c9034561 ZW |
3938 | if ((libfunc = code_to_optab[comparison]->handlers[mode].libfunc)) |
3939 | break; | |
77c9c6c2 | 3940 | |
c9034561 | 3941 | if ((libfunc = code_to_optab[swapped]->handlers[mode].libfunc)) |
77c9c6c2 | 3942 | { |
c9034561 ZW |
3943 | rtx tmp; |
3944 | tmp = x; x = y; y = tmp; | |
3945 | comparison = swapped; | |
3946 | break; | |
77c9c6c2 | 3947 | } |
77c9c6c2 RK |
3948 | } |
3949 | ||
c9034561 | 3950 | if (mode == VOIDmode) |
0a300065 RK |
3951 | abort (); |
3952 | ||
c9034561 ZW |
3953 | if (mode != orig_mode) |
3954 | { | |
3955 | x = convert_to_mode (mode, x, 0); | |
3956 | y = convert_to_mode (mode, y, 0); | |
3957 | } | |
3958 | ||
17796a89 RS |
3959 | /* Attach a REG_EQUAL note describing the semantics of the libcall to |
3960 | the RTL. The allows the RTL optimizers to delete the libcall if the | |
3961 | condition can be determined at compile-time. */ | |
3962 | if (comparison == UNORDERED) | |
3963 | { | |
3964 | rtx temp = simplify_gen_relational (NE, word_mode, mode, x, x); | |
3965 | equiv = simplify_gen_relational (NE, word_mode, mode, y, y); | |
3966 | equiv = simplify_gen_ternary (IF_THEN_ELSE, word_mode, word_mode, | |
3967 | temp, const_true_rtx, equiv); | |
3968 | } | |
3969 | else | |
3970 | { | |
3971 | equiv = simplify_gen_relational (comparison, word_mode, mode, x, y); | |
3972 | if (! FLOAT_LIB_COMPARE_RETURNS_BOOL (mode, comparison)) | |
bd831d5c | 3973 | { |
17796a89 | 3974 | rtx true_rtx, false_rtx; |
37bf20ee | 3975 | |
17796a89 RS |
3976 | switch (comparison) |
3977 | { | |
3978 | case EQ: | |
3979 | true_rtx = const0_rtx; | |
3980 | false_rtx = const_true_rtx; | |
3981 | break; | |
3982 | ||
3983 | case NE: | |
3984 | true_rtx = const_true_rtx; | |
3985 | false_rtx = const0_rtx; | |
3986 | break; | |
3987 | ||
3988 | case GT: | |
3989 | true_rtx = const1_rtx; | |
3990 | false_rtx = const0_rtx; | |
3991 | break; | |
3992 | ||
3993 | case GE: | |
3994 | true_rtx = const0_rtx; | |
3995 | false_rtx = constm1_rtx; | |
3996 | break; | |
3997 | ||
3998 | case LT: | |
3999 | true_rtx = constm1_rtx; | |
4000 | false_rtx = const0_rtx; | |
4001 | break; | |
4002 | ||
4003 | case LE: | |
4004 | true_rtx = const0_rtx; | |
4005 | false_rtx = const1_rtx; | |
4006 | break; | |
4007 | ||
4008 | default: | |
4009 | abort (); | |
bd831d5c | 4010 | } |
17796a89 RS |
4011 | equiv = simplify_gen_ternary (IF_THEN_ELSE, word_mode, word_mode, |
4012 | equiv, true_rtx, false_rtx); | |
bd831d5c RS |
4013 | } |
4014 | } | |
37bf20ee RS |
4015 | |
4016 | start_sequence (); | |
4017 | value = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST, | |
4018 | word_mode, 2, x, mode, y, mode); | |
4019 | insns = get_insns (); | |
4020 | end_sequence (); | |
4021 | ||
4022 | target = gen_reg_rtx (word_mode); | |
4023 | emit_libcall_block (insns, target, value, equiv); | |
4024 | ||
bd831d5c | 4025 | |
c9034561 ZW |
4026 | if (comparison == UNORDERED |
4027 | || FLOAT_LIB_COMPARE_RETURNS_BOOL (mode, comparison)) | |
4028 | comparison = NE; | |
4029 | ||
37bf20ee | 4030 | *px = target; |
b30f05db BS |
4031 | *py = const0_rtx; |
4032 | *pmode = word_mode; | |
c9034561 | 4033 | *pcomparison = comparison; |
b30f05db | 4034 | *punsignedp = 0; |
77c9c6c2 RK |
4035 | } |
4036 | \f | |
4037 | /* Generate code to indirectly jump to a location given in the rtx LOC. */ | |
4038 | ||
4039 | void | |
0c20a65f | 4040 | emit_indirect_jump (rtx loc) |
77c9c6c2 | 4041 | { |
7e1a450d | 4042 | if (! ((*insn_data[(int) CODE_FOR_indirect_jump].operand[0].predicate) |
f2de2775 JW |
4043 | (loc, Pmode))) |
4044 | loc = copy_to_mode_reg (Pmode, loc); | |
77c9c6c2 RK |
4045 | |
4046 | emit_jump_insn (gen_indirect_jump (loc)); | |
9649fb4d | 4047 | emit_barrier (); |
77c9c6c2 RK |
4048 | } |
4049 | \f | |
49c4584c DE |
4050 | #ifdef HAVE_conditional_move |
4051 | ||
4052 | /* Emit a conditional move instruction if the machine supports one for that | |
4053 | condition and machine mode. | |
4054 | ||
4055 | OP0 and OP1 are the operands that should be compared using CODE. CMODE is | |
4056 | the mode to use should they be constants. If it is VOIDmode, they cannot | |
4057 | both be constants. | |
4058 | ||
4059 | OP2 should be stored in TARGET if the comparison is true, otherwise OP3 | |
4060 | should be stored there. MODE is the mode to use should they be constants. | |
4061 | If it is VOIDmode, they cannot both be constants. | |
4062 | ||
4063 | The result is either TARGET (perhaps modified) or NULL_RTX if the operation | |
4064 | is not supported. */ | |
4065 | ||
4066 | rtx | |
0c20a65f AJ |
4067 | emit_conditional_move (rtx target, enum rtx_code code, rtx op0, rtx op1, |
4068 | enum machine_mode cmode, rtx op2, rtx op3, | |
4069 | enum machine_mode mode, int unsignedp) | |
49c4584c DE |
4070 | { |
4071 | rtx tem, subtarget, comparison, insn; | |
4072 | enum insn_code icode; | |
e5c56fd9 | 4073 | enum rtx_code reversed; |
49c4584c DE |
4074 | |
4075 | /* If one operand is constant, make it the second one. Only do this | |
4076 | if the other operand is not constant as well. */ | |
4077 | ||
e5c56fd9 | 4078 | if (swap_commutative_operands_p (op0, op1)) |
49c4584c DE |
4079 | { |
4080 | tem = op0; | |
4081 | op0 = op1; | |
4082 | op1 = tem; | |
4083 | code = swap_condition (code); | |
4084 | } | |
4085 | ||
c5c76735 JL |
4086 | /* get_condition will prefer to generate LT and GT even if the old |
4087 | comparison was against zero, so undo that canonicalization here since | |
4088 | comparisons against zero are cheaper. */ | |
87d9741e | 4089 | if (code == LT && op1 == const1_rtx) |
c5c76735 | 4090 | code = LE, op1 = const0_rtx; |
87d9741e | 4091 | else if (code == GT && op1 == constm1_rtx) |
c5c76735 JL |
4092 | code = GE, op1 = const0_rtx; |
4093 | ||
49c4584c DE |
4094 | if (cmode == VOIDmode) |
4095 | cmode = GET_MODE (op0); | |
4096 | ||
e5c56fd9 JH |
4097 | if (swap_commutative_operands_p (op2, op3) |
4098 | && ((reversed = reversed_comparison_code_parts (code, op0, op1, NULL)) | |
4099 | != UNKNOWN)) | |
49c4584c DE |
4100 | { |
4101 | tem = op2; | |
4102 | op2 = op3; | |
4103 | op3 = tem; | |
e5c56fd9 | 4104 | code = reversed; |
49c4584c DE |
4105 | } |
4106 | ||
4107 | if (mode == VOIDmode) | |
4108 | mode = GET_MODE (op2); | |
4109 | ||
4110 | icode = movcc_gen_code[mode]; | |
4111 | ||
4112 | if (icode == CODE_FOR_nothing) | |
4113 | return 0; | |
4114 | ||
4115 | if (flag_force_mem) | |
4116 | { | |
4117 | op2 = force_not_mem (op2); | |
4118 | op3 = force_not_mem (op3); | |
4119 | } | |
4120 | ||
ad76cef8 | 4121 | if (!target) |
49c4584c DE |
4122 | target = gen_reg_rtx (mode); |
4123 | ||
4124 | subtarget = target; | |
4125 | ||
49c4584c DE |
4126 | /* If the insn doesn't accept these operands, put them in pseudos. */ |
4127 | ||
a995e389 RH |
4128 | if (! (*insn_data[icode].operand[0].predicate) |
4129 | (subtarget, insn_data[icode].operand[0].mode)) | |
4130 | subtarget = gen_reg_rtx (insn_data[icode].operand[0].mode); | |
49c4584c | 4131 | |
a995e389 RH |
4132 | if (! (*insn_data[icode].operand[2].predicate) |
4133 | (op2, insn_data[icode].operand[2].mode)) | |
4134 | op2 = copy_to_mode_reg (insn_data[icode].operand[2].mode, op2); | |
49c4584c | 4135 | |
a995e389 RH |
4136 | if (! (*insn_data[icode].operand[3].predicate) |
4137 | (op3, insn_data[icode].operand[3].mode)) | |
4138 | op3 = copy_to_mode_reg (insn_data[icode].operand[3].mode, op3); | |
49c4584c DE |
4139 | |
4140 | /* Everything should now be in the suitable form, so emit the compare insn | |
4141 | and then the conditional move. */ | |
4142 | ||
0c20a65f | 4143 | comparison |
a06ef755 | 4144 | = compare_from_rtx (op0, op1, code, unsignedp, cmode, NULL_RTX); |
49c4584c DE |
4145 | |
4146 | /* ??? Watch for const0_rtx (nop) and const_true_rtx (unconditional)? */ | |
144a5f9d JL |
4147 | /* We can get const0_rtx or const_true_rtx in some circumstances. Just |
4148 | return NULL and let the caller figure out how best to deal with this | |
4149 | situation. */ | |
49c4584c | 4150 | if (GET_CODE (comparison) != code) |
144a5f9d | 4151 | return NULL_RTX; |
0c20a65f | 4152 | |
49c4584c DE |
4153 | insn = GEN_FCN (icode) (subtarget, comparison, op2, op3); |
4154 | ||
4155 | /* If that failed, then give up. */ | |
4156 | if (insn == 0) | |
4157 | return 0; | |
4158 | ||
4159 | emit_insn (insn); | |
4160 | ||
4161 | if (subtarget != target) | |
4162 | convert_move (target, subtarget, 0); | |
4163 | ||
4164 | return target; | |
4165 | } | |
4166 | ||
40f03658 | 4167 | /* Return nonzero if a conditional move of mode MODE is supported. |
49c4584c DE |
4168 | |
4169 | This function is for combine so it can tell whether an insn that looks | |
4170 | like a conditional move is actually supported by the hardware. If we | |
4171 | guess wrong we lose a bit on optimization, but that's it. */ | |
4172 | /* ??? sparc64 supports conditionally moving integers values based on fp | |
4173 | comparisons, and vice versa. How do we handle them? */ | |
4174 | ||
4175 | int | |
0c20a65f | 4176 | can_conditionally_move_p (enum machine_mode mode) |
49c4584c DE |
4177 | { |
4178 | if (movcc_gen_code[mode] != CODE_FOR_nothing) | |
4179 | return 1; | |
4180 | ||
4181 | return 0; | |
4182 | } | |
4183 | ||
4184 | #endif /* HAVE_conditional_move */ | |
068f5dea JH |
4185 | |
4186 | /* Emit a conditional addition instruction if the machine supports one for that | |
4187 | condition and machine mode. | |
4188 | ||
4189 | OP0 and OP1 are the operands that should be compared using CODE. CMODE is | |
4190 | the mode to use should they be constants. If it is VOIDmode, they cannot | |
4191 | both be constants. | |
4192 | ||
4193 | OP2 should be stored in TARGET if the comparison is true, otherwise OP2+OP3 | |
4194 | should be stored there. MODE is the mode to use should they be constants. | |
4195 | If it is VOIDmode, they cannot both be constants. | |
4196 | ||
4197 | The result is either TARGET (perhaps modified) or NULL_RTX if the operation | |
4198 | is not supported. */ | |
4199 | ||
4200 | rtx | |
0c20a65f AJ |
4201 | emit_conditional_add (rtx target, enum rtx_code code, rtx op0, rtx op1, |
4202 | enum machine_mode cmode, rtx op2, rtx op3, | |
4203 | enum machine_mode mode, int unsignedp) | |
068f5dea JH |
4204 | { |
4205 | rtx tem, subtarget, comparison, insn; | |
4206 | enum insn_code icode; | |
4207 | enum rtx_code reversed; | |
4208 | ||
4209 | /* If one operand is constant, make it the second one. Only do this | |
4210 | if the other operand is not constant as well. */ | |
4211 | ||
4212 | if (swap_commutative_operands_p (op0, op1)) | |
4213 | { | |
4214 | tem = op0; | |
4215 | op0 = op1; | |
4216 | op1 = tem; | |
4217 | code = swap_condition (code); | |
4218 | } | |
4219 | ||
4220 | /* get_condition will prefer to generate LT and GT even if the old | |
4221 | comparison was against zero, so undo that canonicalization here since | |
4222 | comparisons against zero are cheaper. */ | |
87d9741e | 4223 | if (code == LT && op1 == const1_rtx) |
068f5dea | 4224 | code = LE, op1 = const0_rtx; |
87d9741e | 4225 | else if (code == GT && op1 == constm1_rtx) |
068f5dea JH |
4226 | code = GE, op1 = const0_rtx; |
4227 | ||
4228 | if (cmode == VOIDmode) | |
4229 | cmode = GET_MODE (op0); | |
4230 | ||
4231 | if (swap_commutative_operands_p (op2, op3) | |
4232 | && ((reversed = reversed_comparison_code_parts (code, op0, op1, NULL)) | |
4233 | != UNKNOWN)) | |
4234 | { | |
4235 | tem = op2; | |
4236 | op2 = op3; | |
4237 | op3 = tem; | |
4238 | code = reversed; | |
4239 | } | |
4240 | ||
4241 | if (mode == VOIDmode) | |
4242 | mode = GET_MODE (op2); | |
4243 | ||
4244 | icode = addcc_optab->handlers[(int) mode].insn_code; | |
4245 | ||
4246 | if (icode == CODE_FOR_nothing) | |
4247 | return 0; | |
4248 | ||
4249 | if (flag_force_mem) | |
4250 | { | |
4251 | op2 = force_not_mem (op2); | |
4252 | op3 = force_not_mem (op3); | |
4253 | } | |
4254 | ||
ad76cef8 | 4255 | if (!target) |
068f5dea JH |
4256 | target = gen_reg_rtx (mode); |
4257 | ||
068f5dea JH |
4258 | /* If the insn doesn't accept these operands, put them in pseudos. */ |
4259 | ||
4260 | if (! (*insn_data[icode].operand[0].predicate) | |
ad76cef8 | 4261 | (target, insn_data[icode].operand[0].mode)) |
068f5dea | 4262 | subtarget = gen_reg_rtx (insn_data[icode].operand[0].mode); |
ad76cef8 PB |
4263 | else |
4264 | subtarget = target; | |
068f5dea JH |
4265 | |
4266 | if (! (*insn_data[icode].operand[2].predicate) | |
4267 | (op2, insn_data[icode].operand[2].mode)) | |
4268 | op2 = copy_to_mode_reg (insn_data[icode].operand[2].mode, op2); | |
4269 | ||
4270 | if (! (*insn_data[icode].operand[3].predicate) | |
4271 | (op3, insn_data[icode].operand[3].mode)) | |
4272 | op3 = copy_to_mode_reg (insn_data[icode].operand[3].mode, op3); | |
4273 | ||
4274 | /* Everything should now be in the suitable form, so emit the compare insn | |
4275 | and then the conditional move. */ | |
4276 | ||
0c20a65f | 4277 | comparison |
068f5dea JH |
4278 | = compare_from_rtx (op0, op1, code, unsignedp, cmode, NULL_RTX); |
4279 | ||
4280 | /* ??? Watch for const0_rtx (nop) and const_true_rtx (unconditional)? */ | |
4281 | /* We can get const0_rtx or const_true_rtx in some circumstances. Just | |
4282 | return NULL and let the caller figure out how best to deal with this | |
4283 | situation. */ | |
4284 | if (GET_CODE (comparison) != code) | |
4285 | return NULL_RTX; | |
0c20a65f | 4286 | |
068f5dea JH |
4287 | insn = GEN_FCN (icode) (subtarget, comparison, op2, op3); |
4288 | ||
4289 | /* If that failed, then give up. */ | |
4290 | if (insn == 0) | |
4291 | return 0; | |
4292 | ||
4293 | emit_insn (insn); | |
4294 | ||
4295 | if (subtarget != target) | |
4296 | convert_move (target, subtarget, 0); | |
4297 | ||
4298 | return target; | |
4299 | } | |
49c4584c | 4300 | \f |
0913e4b4 AO |
4301 | /* These functions attempt to generate an insn body, rather than |
4302 | emitting the insn, but if the gen function already emits them, we | |
ad76cef8 | 4303 | make no attempt to turn them back into naked patterns. */ |
77c9c6c2 RK |
4304 | |
4305 | /* Generate and return an insn body to add Y to X. */ | |
4306 | ||
4307 | rtx | |
0c20a65f | 4308 | gen_add2_insn (rtx x, rtx y) |
77c9c6c2 | 4309 | { |
0c20a65f | 4310 | int icode = (int) add_optab->handlers[(int) GET_MODE (x)].insn_code; |
77c9c6c2 | 4311 | |
a995e389 RH |
4312 | if (! ((*insn_data[icode].operand[0].predicate) |
4313 | (x, insn_data[icode].operand[0].mode)) | |
4314 | || ! ((*insn_data[icode].operand[1].predicate) | |
4315 | (x, insn_data[icode].operand[1].mode)) | |
4316 | || ! ((*insn_data[icode].operand[2].predicate) | |
4317 | (y, insn_data[icode].operand[2].mode))) | |
77c9c6c2 RK |
4318 | abort (); |
4319 | ||
4320 | return (GEN_FCN (icode) (x, x, y)); | |
4321 | } | |
4322 | ||
e78d8e51 ZW |
4323 | /* Generate and return an insn body to add r1 and c, |
4324 | storing the result in r0. */ | |
4325 | rtx | |
0c20a65f | 4326 | gen_add3_insn (rtx r0, rtx r1, rtx c) |
e78d8e51 ZW |
4327 | { |
4328 | int icode = (int) add_optab->handlers[(int) GET_MODE (r0)].insn_code; | |
4329 | ||
7e1a450d | 4330 | if (icode == CODE_FOR_nothing |
e78d8e51 ZW |
4331 | || ! ((*insn_data[icode].operand[0].predicate) |
4332 | (r0, insn_data[icode].operand[0].mode)) | |
4333 | || ! ((*insn_data[icode].operand[1].predicate) | |
4334 | (r1, insn_data[icode].operand[1].mode)) | |
4335 | || ! ((*insn_data[icode].operand[2].predicate) | |
4336 | (c, insn_data[icode].operand[2].mode))) | |
4337 | return NULL_RTX; | |
4338 | ||
4339 | return (GEN_FCN (icode) (r0, r1, c)); | |
4340 | } | |
4341 | ||
77c9c6c2 | 4342 | int |
0c20a65f | 4343 | have_add2_insn (rtx x, rtx y) |
77c9c6c2 | 4344 | { |
fb7e77d7 TM |
4345 | int icode; |
4346 | ||
4347 | if (GET_MODE (x) == VOIDmode) | |
4348 | abort (); | |
4349 | ||
0c20a65f | 4350 | icode = (int) add_optab->handlers[(int) GET_MODE (x)].insn_code; |
fb7e77d7 TM |
4351 | |
4352 | if (icode == CODE_FOR_nothing) | |
4353 | return 0; | |
4354 | ||
4355 | if (! ((*insn_data[icode].operand[0].predicate) | |
4356 | (x, insn_data[icode].operand[0].mode)) | |
4357 | || ! ((*insn_data[icode].operand[1].predicate) | |
4358 | (x, insn_data[icode].operand[1].mode)) | |
4359 | || ! ((*insn_data[icode].operand[2].predicate) | |
4360 | (y, insn_data[icode].operand[2].mode))) | |
4361 | return 0; | |
4362 | ||
4363 | return 1; | |
77c9c6c2 RK |
4364 | } |
4365 | ||
4366 | /* Generate and return an insn body to subtract Y from X. */ | |
4367 | ||
4368 | rtx | |
0c20a65f | 4369 | gen_sub2_insn (rtx x, rtx y) |
77c9c6c2 | 4370 | { |
0c20a65f | 4371 | int icode = (int) sub_optab->handlers[(int) GET_MODE (x)].insn_code; |
77c9c6c2 | 4372 | |
a995e389 RH |
4373 | if (! ((*insn_data[icode].operand[0].predicate) |
4374 | (x, insn_data[icode].operand[0].mode)) | |
4375 | || ! ((*insn_data[icode].operand[1].predicate) | |
4376 | (x, insn_data[icode].operand[1].mode)) | |
4377 | || ! ((*insn_data[icode].operand[2].predicate) | |
4378 | (y, insn_data[icode].operand[2].mode))) | |
77c9c6c2 RK |
4379 | abort (); |
4380 | ||
4381 | return (GEN_FCN (icode) (x, x, y)); | |
4382 | } | |
4383 | ||
ef89d648 ZW |
4384 | /* Generate and return an insn body to subtract r1 and c, |
4385 | storing the result in r0. */ | |
4386 | rtx | |
0c20a65f | 4387 | gen_sub3_insn (rtx r0, rtx r1, rtx c) |
ef89d648 ZW |
4388 | { |
4389 | int icode = (int) sub_optab->handlers[(int) GET_MODE (r0)].insn_code; | |
4390 | ||
7e1a450d | 4391 | if (icode == CODE_FOR_nothing |
ef89d648 ZW |
4392 | || ! ((*insn_data[icode].operand[0].predicate) |
4393 | (r0, insn_data[icode].operand[0].mode)) | |
4394 | || ! ((*insn_data[icode].operand[1].predicate) | |
4395 | (r1, insn_data[icode].operand[1].mode)) | |
4396 | || ! ((*insn_data[icode].operand[2].predicate) | |
4397 | (c, insn_data[icode].operand[2].mode))) | |
4398 | return NULL_RTX; | |
4399 | ||
4400 | return (GEN_FCN (icode) (r0, r1, c)); | |
4401 | } | |
4402 | ||
77c9c6c2 | 4403 | int |
0c20a65f | 4404 | have_sub2_insn (rtx x, rtx y) |
77c9c6c2 | 4405 | { |
fb7e77d7 TM |
4406 | int icode; |
4407 | ||
4408 | if (GET_MODE (x) == VOIDmode) | |
4409 | abort (); | |
4410 | ||
0c20a65f | 4411 | icode = (int) sub_optab->handlers[(int) GET_MODE (x)].insn_code; |
fb7e77d7 TM |
4412 | |
4413 | if (icode == CODE_FOR_nothing) | |
4414 | return 0; | |
4415 | ||
4416 | if (! ((*insn_data[icode].operand[0].predicate) | |
4417 | (x, insn_data[icode].operand[0].mode)) | |
4418 | || ! ((*insn_data[icode].operand[1].predicate) | |
4419 | (x, insn_data[icode].operand[1].mode)) | |
4420 | || ! ((*insn_data[icode].operand[2].predicate) | |
4421 | (y, insn_data[icode].operand[2].mode))) | |
4422 | return 0; | |
4423 | ||
4424 | return 1; | |
77c9c6c2 RK |
4425 | } |
4426 | ||
e3654226 | 4427 | /* Generate the body of an instruction to copy Y into X. |
2f937369 | 4428 | It may be a list of insns, if one insn isn't enough. */ |
77c9c6c2 RK |
4429 | |
4430 | rtx | |
0c20a65f | 4431 | gen_move_insn (rtx x, rtx y) |
77c9c6c2 | 4432 | { |
e3654226 | 4433 | rtx seq; |
77c9c6c2 | 4434 | |
e3654226 RS |
4435 | start_sequence (); |
4436 | emit_move_insn_1 (x, y); | |
2f937369 | 4437 | seq = get_insns (); |
e3654226 RS |
4438 | end_sequence (); |
4439 | return seq; | |
77c9c6c2 RK |
4440 | } |
4441 | \f | |
34e56753 RS |
4442 | /* Return the insn code used to extend FROM_MODE to TO_MODE. |
4443 | UNSIGNEDP specifies zero-extension instead of sign-extension. If | |
4444 | no such operation exists, CODE_FOR_nothing will be returned. */ | |
77c9c6c2 | 4445 | |
34e56753 | 4446 | enum insn_code |
0c20a65f AJ |
4447 | can_extend_p (enum machine_mode to_mode, enum machine_mode from_mode, |
4448 | int unsignedp) | |
77c9c6c2 | 4449 | { |
85363ca0 | 4450 | convert_optab tab; |
6dd12198 SE |
4451 | #ifdef HAVE_ptr_extend |
4452 | if (unsignedp < 0) | |
4453 | return CODE_FOR_ptr_extend; | |
6dd12198 | 4454 | #endif |
85363ca0 ZW |
4455 | |
4456 | tab = unsignedp ? zext_optab : sext_optab; | |
4457 | return tab->handlers[to_mode][from_mode].insn_code; | |
77c9c6c2 RK |
4458 | } |
4459 | ||
4460 | /* Generate the body of an insn to extend Y (with mode MFROM) | |
4461 | into X (with mode MTO). Do zero-extension if UNSIGNEDP is nonzero. */ | |
4462 | ||
4463 | rtx | |
0c20a65f AJ |
4464 | gen_extend_insn (rtx x, rtx y, enum machine_mode mto, |
4465 | enum machine_mode mfrom, int unsignedp) | |
77c9c6c2 | 4466 | { |
85363ca0 ZW |
4467 | enum insn_code icode = can_extend_p (mto, mfrom, unsignedp); |
4468 | return GEN_FCN (icode) (x, y); | |
77c9c6c2 | 4469 | } |
77c9c6c2 RK |
4470 | \f |
4471 | /* can_fix_p and can_float_p say whether the target machine | |
4472 | can directly convert a given fixed point type to | |
4473 | a given floating point type, or vice versa. | |
4474 | The returned value is the CODE_FOR_... value to use, | |
5d81dc5b | 4475 | or CODE_FOR_nothing if these modes cannot be directly converted. |
77c9c6c2 | 4476 | |
5d81dc5b | 4477 | *TRUNCP_PTR is set to 1 if it is necessary to output |
77c9c6c2 RK |
4478 | an explicit FTRUNC insn before the fix insn; otherwise 0. */ |
4479 | ||
4480 | static enum insn_code | |
0c20a65f AJ |
4481 | can_fix_p (enum machine_mode fixmode, enum machine_mode fltmode, |
4482 | int unsignedp, int *truncp_ptr) | |
77c9c6c2 | 4483 | { |
85363ca0 ZW |
4484 | convert_optab tab; |
4485 | enum insn_code icode; | |
4486 | ||
4487 | tab = unsignedp ? ufixtrunc_optab : sfixtrunc_optab; | |
4488 | icode = tab->handlers[fixmode][fltmode].insn_code; | |
4489 | if (icode != CODE_FOR_nothing) | |
4490 | { | |
4491 | *truncp_ptr = 0; | |
4492 | return icode; | |
4493 | } | |
77c9c6c2 | 4494 | |
0e1d7f32 AH |
4495 | /* FIXME: This requires a port to define both FIX and FTRUNC pattern |
4496 | for this to work. We need to rework the fix* and ftrunc* patterns | |
4497 | and documentation. */ | |
85363ca0 ZW |
4498 | tab = unsignedp ? ufix_optab : sfix_optab; |
4499 | icode = tab->handlers[fixmode][fltmode].insn_code; | |
4500 | if (icode != CODE_FOR_nothing | |
4501 | && ftrunc_optab->handlers[fltmode].insn_code != CODE_FOR_nothing) | |
77c9c6c2 RK |
4502 | { |
4503 | *truncp_ptr = 1; | |
85363ca0 | 4504 | return icode; |
77c9c6c2 | 4505 | } |
85363ca0 ZW |
4506 | |
4507 | *truncp_ptr = 0; | |
77c9c6c2 RK |
4508 | return CODE_FOR_nothing; |
4509 | } | |
4510 | ||
4511 | static enum insn_code | |
0c20a65f AJ |
4512 | can_float_p (enum machine_mode fltmode, enum machine_mode fixmode, |
4513 | int unsignedp) | |
77c9c6c2 | 4514 | { |
85363ca0 ZW |
4515 | convert_optab tab; |
4516 | ||
4517 | tab = unsignedp ? ufloat_optab : sfloat_optab; | |
4518 | return tab->handlers[fltmode][fixmode].insn_code; | |
77c9c6c2 | 4519 | } |
77c9c6c2 RK |
4520 | \f |
4521 | /* Generate code to convert FROM to floating point | |
34e56753 | 4522 | and store in TO. FROM must be fixed point and not VOIDmode. |
77c9c6c2 RK |
4523 | UNSIGNEDP nonzero means regard FROM as unsigned. |
4524 | Normally this is done by correcting the final value | |
4525 | if it is negative. */ | |
4526 | ||
4527 | void | |
0c20a65f | 4528 | expand_float (rtx to, rtx from, int unsignedp) |
77c9c6c2 RK |
4529 | { |
4530 | enum insn_code icode; | |
b3694847 | 4531 | rtx target = to; |
77c9c6c2 RK |
4532 | enum machine_mode fmode, imode; |
4533 | ||
34e56753 RS |
4534 | /* Crash now, because we won't be able to decide which mode to use. */ |
4535 | if (GET_MODE (from) == VOIDmode) | |
4536 | abort (); | |
4537 | ||
77c9c6c2 RK |
4538 | /* Look for an insn to do the conversion. Do it in the specified |
4539 | modes if possible; otherwise convert either input, output or both to | |
4540 | wider mode. If the integer mode is wider than the mode of FROM, | |
4541 | we can do the conversion signed even if the input is unsigned. */ | |
4542 | ||
7bf0a593 AP |
4543 | for (fmode = GET_MODE (to); fmode != VOIDmode; |
4544 | fmode = GET_MODE_WIDER_MODE (fmode)) | |
4545 | for (imode = GET_MODE (from); imode != VOIDmode; | |
4546 | imode = GET_MODE_WIDER_MODE (imode)) | |
77c9c6c2 RK |
4547 | { |
4548 | int doing_unsigned = unsignedp; | |
4549 | ||
5ba02ca6 GK |
4550 | if (fmode != GET_MODE (to) |
4551 | && significand_size (fmode) < GET_MODE_BITSIZE (GET_MODE (from))) | |
4552 | continue; | |
4553 | ||
77c9c6c2 RK |
4554 | icode = can_float_p (fmode, imode, unsignedp); |
4555 | if (icode == CODE_FOR_nothing && imode != GET_MODE (from) && unsignedp) | |
4556 | icode = can_float_p (fmode, imode, 0), doing_unsigned = 0; | |
4557 | ||
4558 | if (icode != CODE_FOR_nothing) | |
4559 | { | |
77c9c6c2 RK |
4560 | if (imode != GET_MODE (from)) |
4561 | from = convert_to_mode (imode, from, unsignedp); | |
77c9c6c2 RK |
4562 | |
4563 | if (fmode != GET_MODE (to)) | |
4564 | target = gen_reg_rtx (fmode); | |
4565 | ||
4566 | emit_unop_insn (icode, target, from, | |
4567 | doing_unsigned ? UNSIGNED_FLOAT : FLOAT); | |
4568 | ||
4569 | if (target != to) | |
4570 | convert_move (to, target, 0); | |
4571 | return; | |
4572 | } | |
7e1a450d | 4573 | } |
77c9c6c2 | 4574 | |
77c9c6c2 RK |
4575 | /* Unsigned integer, and no way to convert directly. |
4576 | Convert as signed, then conditionally adjust the result. */ | |
4577 | if (unsignedp) | |
4578 | { | |
4579 | rtx label = gen_label_rtx (); | |
4580 | rtx temp; | |
4581 | REAL_VALUE_TYPE offset; | |
4582 | ||
77c9c6c2 RK |
4583 | if (flag_force_mem) |
4584 | from = force_not_mem (from); | |
4585 | ||
c95c47f3 PE |
4586 | /* Look for a usable floating mode FMODE wider than the source and at |
4587 | least as wide as the target. Using FMODE will avoid rounding woes | |
4588 | with unsigned values greater than the signed maximum value. */ | |
70864443 | 4589 | |
c95c47f3 PE |
4590 | for (fmode = GET_MODE (to); fmode != VOIDmode; |
4591 | fmode = GET_MODE_WIDER_MODE (fmode)) | |
4592 | if (GET_MODE_BITSIZE (GET_MODE (from)) < GET_MODE_BITSIZE (fmode) | |
4593 | && can_float_p (fmode, GET_MODE (from), 0) != CODE_FOR_nothing) | |
4594 | break; | |
a48fb61b | 4595 | |
c95c47f3 PE |
4596 | if (fmode == VOIDmode) |
4597 | { | |
a48fb61b | 4598 | /* There is no such mode. Pretend the target is wide enough. */ |
c95c47f3 | 4599 | fmode = GET_MODE (to); |
a48fb61b | 4600 | |
0f41302f | 4601 | /* Avoid double-rounding when TO is narrower than FROM. */ |
a48fb61b RK |
4602 | if ((significand_size (fmode) + 1) |
4603 | < GET_MODE_BITSIZE (GET_MODE (from))) | |
4604 | { | |
4605 | rtx temp1; | |
4606 | rtx neglabel = gen_label_rtx (); | |
4607 | ||
0c20a65f | 4608 | /* Don't use TARGET if it isn't a register, is a hard register, |
70864443 | 4609 | or is the wrong mode. */ |
f8cfc6aa | 4610 | if (!REG_P (target) |
70864443 RK |
4611 | || REGNO (target) < FIRST_PSEUDO_REGISTER |
4612 | || GET_MODE (target) != fmode) | |
44f51d4a RK |
4613 | target = gen_reg_rtx (fmode); |
4614 | ||
a48fb61b RK |
4615 | imode = GET_MODE (from); |
4616 | do_pending_stack_adjust (); | |
4617 | ||
4618 | /* Test whether the sign bit is set. */ | |
1c0290ea | 4619 | emit_cmp_and_jump_insns (from, const0_rtx, LT, NULL_RTX, imode, |
a06ef755 | 4620 | 0, neglabel); |
a48fb61b RK |
4621 | |
4622 | /* The sign bit is not set. Convert as signed. */ | |
4623 | expand_float (target, from, 0); | |
4624 | emit_jump_insn (gen_jump (label)); | |
2ad79487 | 4625 | emit_barrier (); |
a48fb61b RK |
4626 | |
4627 | /* The sign bit is set. | |
4628 | Convert to a usable (positive signed) value by shifting right | |
4629 | one bit, while remembering if a nonzero bit was shifted | |
4630 | out; i.e., compute (from & 1) | (from >> 1). */ | |
4631 | ||
4632 | emit_label (neglabel); | |
4633 | temp = expand_binop (imode, and_optab, from, const1_rtx, | |
70864443 | 4634 | NULL_RTX, 1, OPTAB_LIB_WIDEN); |
73d9a835 RK |
4635 | temp1 = expand_shift (RSHIFT_EXPR, imode, from, integer_one_node, |
4636 | NULL_RTX, 1); | |
0c20a65f | 4637 | temp = expand_binop (imode, ior_optab, temp, temp1, temp, 1, |
70864443 | 4638 | OPTAB_LIB_WIDEN); |
a48fb61b RK |
4639 | expand_float (target, temp, 0); |
4640 | ||
4641 | /* Multiply by 2 to undo the shift above. */ | |
a93738eb | 4642 | temp = expand_binop (fmode, add_optab, target, target, |
7e1a450d | 4643 | target, 0, OPTAB_LIB_WIDEN); |
a93738eb RK |
4644 | if (temp != target) |
4645 | emit_move_insn (target, temp); | |
4646 | ||
a48fb61b RK |
4647 | do_pending_stack_adjust (); |
4648 | emit_label (label); | |
4649 | goto done; | |
4650 | } | |
c95c47f3 PE |
4651 | } |
4652 | ||
77c9c6c2 RK |
4653 | /* If we are about to do some arithmetic to correct for an |
4654 | unsigned operand, do it in a pseudo-register. */ | |
4655 | ||
c95c47f3 | 4656 | if (GET_MODE (to) != fmode |
f8cfc6aa | 4657 | || !REG_P (to) || REGNO (to) < FIRST_PSEUDO_REGISTER) |
c95c47f3 | 4658 | target = gen_reg_rtx (fmode); |
77c9c6c2 RK |
4659 | |
4660 | /* Convert as signed integer to floating. */ | |
4661 | expand_float (target, from, 0); | |
4662 | ||
4663 | /* If FROM is negative (and therefore TO is negative), | |
4664 | correct its value by 2**bitwidth. */ | |
4665 | ||
4666 | do_pending_stack_adjust (); | |
c5d5d461 | 4667 | emit_cmp_and_jump_insns (from, const0_rtx, GE, NULL_RTX, GET_MODE (from), |
a06ef755 | 4668 | 0, label); |
70864443 | 4669 | |
0c20a65f | 4670 | |
efdc7e19 | 4671 | real_2expN (&offset, GET_MODE_BITSIZE (GET_MODE (from))); |
c95c47f3 | 4672 | temp = expand_binop (fmode, add_optab, target, |
30d88916 | 4673 | CONST_DOUBLE_FROM_REAL_VALUE (offset, fmode), |
77c9c6c2 RK |
4674 | target, 0, OPTAB_LIB_WIDEN); |
4675 | if (temp != target) | |
4676 | emit_move_insn (target, temp); | |
a48fb61b | 4677 | |
77c9c6c2 RK |
4678 | do_pending_stack_adjust (); |
4679 | emit_label (label); | |
70864443 | 4680 | goto done; |
77c9c6c2 | 4681 | } |
77c9c6c2 | 4682 | |
85363ca0 | 4683 | /* No hardware instruction available; call a library routine. */ |
77c9c6c2 | 4684 | { |
85363ca0 | 4685 | rtx libfunc; |
77c9c6c2 | 4686 | rtx insns; |
9a7f678c | 4687 | rtx value; |
85363ca0 | 4688 | convert_optab tab = unsignedp ? ufloat_optab : sfloat_optab; |
77c9c6c2 | 4689 | |
77c9c6c2 RK |
4690 | if (GET_MODE_SIZE (GET_MODE (from)) < GET_MODE_SIZE (SImode)) |
4691 | from = convert_to_mode (SImode, from, unsignedp); | |
77c9c6c2 RK |
4692 | |
4693 | if (flag_force_mem) | |
4694 | from = force_not_mem (from); | |
4695 | ||
85363ca0 ZW |
4696 | libfunc = tab->handlers[GET_MODE (to)][GET_MODE (from)].libfunc; |
4697 | if (!libfunc) | |
77c9c6c2 RK |
4698 | abort (); |
4699 | ||
4700 | start_sequence (); | |
4701 | ||
85363ca0 | 4702 | value = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST, |
ebb1b59a BS |
4703 | GET_MODE (to), 1, from, |
4704 | GET_MODE (from)); | |
77c9c6c2 RK |
4705 | insns = get_insns (); |
4706 | end_sequence (); | |
4707 | ||
9a7f678c | 4708 | emit_libcall_block (insns, target, value, |
9e6a5703 | 4709 | gen_rtx_FLOAT (GET_MODE (to), from)); |
77c9c6c2 RK |
4710 | } |
4711 | ||
a48fb61b RK |
4712 | done: |
4713 | ||
77c9c6c2 RK |
4714 | /* Copy result to requested destination |
4715 | if we have been computing in a temp location. */ | |
4716 | ||
4717 | if (target != to) | |
4718 | { | |
4719 | if (GET_MODE (target) == GET_MODE (to)) | |
4720 | emit_move_insn (to, target); | |
4721 | else | |
4722 | convert_move (to, target, 0); | |
4723 | } | |
4724 | } | |
4725 | \f | |
0e1d7f32 AH |
4726 | /* Generate code to convert FROM to fixed point and store in TO. FROM |
4727 | must be floating point. */ | |
77c9c6c2 RK |
4728 | |
4729 | void | |
0c20a65f | 4730 | expand_fix (rtx to, rtx from, int unsignedp) |
77c9c6c2 RK |
4731 | { |
4732 | enum insn_code icode; | |
b3694847 | 4733 | rtx target = to; |
77c9c6c2 RK |
4734 | enum machine_mode fmode, imode; |
4735 | int must_trunc = 0; | |
77c9c6c2 RK |
4736 | |
4737 | /* We first try to find a pair of modes, one real and one integer, at | |
4738 | least as wide as FROM and TO, respectively, in which we can open-code | |
4739 | this conversion. If the integer mode is wider than the mode of TO, | |
4740 | we can do the conversion either signed or unsigned. */ | |
4741 | ||
3987b9db JH |
4742 | for (fmode = GET_MODE (from); fmode != VOIDmode; |
4743 | fmode = GET_MODE_WIDER_MODE (fmode)) | |
4744 | for (imode = GET_MODE (to); imode != VOIDmode; | |
4745 | imode = GET_MODE_WIDER_MODE (imode)) | |
77c9c6c2 RK |
4746 | { |
4747 | int doing_unsigned = unsignedp; | |
4748 | ||
4749 | icode = can_fix_p (imode, fmode, unsignedp, &must_trunc); | |
4750 | if (icode == CODE_FOR_nothing && imode != GET_MODE (to) && unsignedp) | |
4751 | icode = can_fix_p (imode, fmode, 0, &must_trunc), doing_unsigned = 0; | |
4752 | ||
4753 | if (icode != CODE_FOR_nothing) | |
4754 | { | |
77c9c6c2 RK |
4755 | if (fmode != GET_MODE (from)) |
4756 | from = convert_to_mode (fmode, from, 0); | |
77c9c6c2 RK |
4757 | |
4758 | if (must_trunc) | |
0e1d7f32 AH |
4759 | { |
4760 | rtx temp = gen_reg_rtx (GET_MODE (from)); | |
4761 | from = expand_unop (GET_MODE (from), ftrunc_optab, from, | |
4762 | temp, 0); | |
4763 | } | |
77c9c6c2 RK |
4764 | |
4765 | if (imode != GET_MODE (to)) | |
4766 | target = gen_reg_rtx (imode); | |
4767 | ||
4768 | emit_unop_insn (icode, target, from, | |
4769 | doing_unsigned ? UNSIGNED_FIX : FIX); | |
4770 | if (target != to) | |
4771 | convert_move (to, target, unsignedp); | |
4772 | return; | |
4773 | } | |
4774 | } | |
4775 | ||
77c9c6c2 RK |
4776 | /* For an unsigned conversion, there is one more way to do it. |
4777 | If we have a signed conversion, we generate code that compares | |
4778 | the real value to the largest representable positive number. If if | |
4779 | is smaller, the conversion is done normally. Otherwise, subtract | |
4780 | one plus the highest signed number, convert, and add it back. | |
4781 | ||
4782 | We only need to check all real modes, since we know we didn't find | |
0c20a65f | 4783 | anything with a wider integer mode. |
0d446150 JH |
4784 | |
4785 | This code used to extend FP value into mode wider than the destination. | |
4786 | This is not needed. Consider, for instance conversion from SFmode | |
4787 | into DImode. | |
4788 | ||
4789 | The hot path trought the code is dealing with inputs smaller than 2^63 | |
4790 | and doing just the conversion, so there is no bits to lose. | |
4791 | ||
4792 | In the other path we know the value is positive in the range 2^63..2^64-1 | |
4793 | inclusive. (as for other imput overflow happens and result is undefined) | |
e0bb17a8 | 4794 | So we know that the most important bit set in mantissa corresponds to |
0d446150 JH |
4795 | 2^63. The subtraction of 2^63 should not generate any rounding as it |
4796 | simply clears out that bit. The rest is trivial. */ | |
77c9c6c2 | 4797 | |
b1ec3c92 | 4798 | if (unsignedp && GET_MODE_BITSIZE (GET_MODE (to)) <= HOST_BITS_PER_WIDE_INT) |
77c9c6c2 RK |
4799 | for (fmode = GET_MODE (from); fmode != VOIDmode; |
4800 | fmode = GET_MODE_WIDER_MODE (fmode)) | |
0d446150 JH |
4801 | if (CODE_FOR_nothing != can_fix_p (GET_MODE (to), fmode, 0, |
4802 | &must_trunc)) | |
77c9c6c2 | 4803 | { |
e9f7ae44 RS |
4804 | int bitsize; |
4805 | REAL_VALUE_TYPE offset; | |
4806 | rtx limit, lab1, lab2, insn; | |
4807 | ||
4808 | bitsize = GET_MODE_BITSIZE (GET_MODE (to)); | |
efdc7e19 | 4809 | real_2expN (&offset, bitsize - 1); |
30d88916 | 4810 | limit = CONST_DOUBLE_FROM_REAL_VALUE (offset, fmode); |
e9f7ae44 RS |
4811 | lab1 = gen_label_rtx (); |
4812 | lab2 = gen_label_rtx (); | |
77c9c6c2 | 4813 | |
77c9c6c2 RK |
4814 | if (flag_force_mem) |
4815 | from = force_not_mem (from); | |
4816 | ||
4817 | if (fmode != GET_MODE (from)) | |
4818 | from = convert_to_mode (fmode, from, 0); | |
4819 | ||
4820 | /* See if we need to do the subtraction. */ | |
4821 | do_pending_stack_adjust (); | |
c5d5d461 | 4822 | emit_cmp_and_jump_insns (from, limit, GE, NULL_RTX, GET_MODE (from), |
a06ef755 | 4823 | 0, lab1); |
77c9c6c2 RK |
4824 | |
4825 | /* If not, do the signed "fix" and branch around fixup code. */ | |
4826 | expand_fix (to, from, 0); | |
4827 | emit_jump_insn (gen_jump (lab2)); | |
4828 | emit_barrier (); | |
4829 | ||
4830 | /* Otherwise, subtract 2**(N-1), convert to signed number, | |
4831 | then add 2**(N-1). Do the addition using XOR since this | |
4832 | will often generate better code. */ | |
4833 | emit_label (lab1); | |
4834 | target = expand_binop (GET_MODE (from), sub_optab, from, limit, | |
b1ec3c92 | 4835 | NULL_RTX, 0, OPTAB_LIB_WIDEN); |
77c9c6c2 RK |
4836 | expand_fix (to, target, 0); |
4837 | target = expand_binop (GET_MODE (to), xor_optab, to, | |
2496c7bd LB |
4838 | gen_int_mode |
4839 | ((HOST_WIDE_INT) 1 << (bitsize - 1), | |
4840 | GET_MODE (to)), | |
77c9c6c2 RK |
4841 | to, 1, OPTAB_LIB_WIDEN); |
4842 | ||
4843 | if (target != to) | |
4844 | emit_move_insn (to, target); | |
4845 | ||
4846 | emit_label (lab2); | |
4847 | ||
02214a5c RK |
4848 | if (mov_optab->handlers[(int) GET_MODE (to)].insn_code |
4849 | != CODE_FOR_nothing) | |
4850 | { | |
4851 | /* Make a place for a REG_NOTE and add it. */ | |
4852 | insn = emit_move_insn (to, to); | |
5fa671cf AM |
4853 | set_unique_reg_note (insn, |
4854 | REG_EQUAL, | |
4855 | gen_rtx_fmt_e (UNSIGNED_FIX, | |
4856 | GET_MODE (to), | |
4857 | copy_rtx (from))); | |
02214a5c | 4858 | } |
c5c76735 | 4859 | |
77c9c6c2 RK |
4860 | return; |
4861 | } | |
77c9c6c2 RK |
4862 | |
4863 | /* We can't do it with an insn, so use a library call. But first ensure | |
4864 | that the mode of TO is at least as wide as SImode, since those are the | |
4865 | only library calls we know about. */ | |
4866 | ||
4867 | if (GET_MODE_SIZE (GET_MODE (to)) < GET_MODE_SIZE (SImode)) | |
4868 | { | |
4869 | target = gen_reg_rtx (SImode); | |
4870 | ||
4871 | expand_fix (target, from, unsignedp); | |
4872 | } | |
77c9c6c2 | 4873 | else |
77c9c6c2 RK |
4874 | { |
4875 | rtx insns; | |
560f3f8a | 4876 | rtx value; |
85363ca0 ZW |
4877 | rtx libfunc; |
4878 | ||
4879 | convert_optab tab = unsignedp ? ufix_optab : sfix_optab; | |
4880 | libfunc = tab->handlers[GET_MODE (to)][GET_MODE (from)].libfunc; | |
4881 | if (!libfunc) | |
4882 | abort (); | |
77c9c6c2 | 4883 | |
77c9c6c2 RK |
4884 | if (flag_force_mem) |
4885 | from = force_not_mem (from); | |
4886 | ||
4887 | start_sequence (); | |
4888 | ||
85363ca0 | 4889 | value = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST, |
ebb1b59a BS |
4890 | GET_MODE (to), 1, from, |
4891 | GET_MODE (from)); | |
77c9c6c2 RK |
4892 | insns = get_insns (); |
4893 | end_sequence (); | |
4894 | ||
560f3f8a | 4895 | emit_libcall_block (insns, target, value, |
9e6a5703 JC |
4896 | gen_rtx_fmt_e (unsignedp ? UNSIGNED_FIX : FIX, |
4897 | GET_MODE (to), from)); | |
77c9c6c2 | 4898 | } |
0c20a65f | 4899 | |
3e53ea48 RK |
4900 | if (target != to) |
4901 | { | |
4902 | if (GET_MODE (to) == GET_MODE (target)) | |
4903 | emit_move_insn (to, target); | |
4904 | else | |
4905 | convert_move (to, target, 0); | |
4906 | } | |
77c9c6c2 RK |
4907 | } |
4908 | \f | |
ef89d648 ZW |
4909 | /* Report whether we have an instruction to perform the operation |
4910 | specified by CODE on operands of mode MODE. */ | |
4911 | int | |
0c20a65f | 4912 | have_insn_for (enum rtx_code code, enum machine_mode mode) |
ef89d648 ZW |
4913 | { |
4914 | return (code_to_optab[(int) code] != 0 | |
4915 | && (code_to_optab[(int) code]->handlers[(int) mode].insn_code | |
4916 | != CODE_FOR_nothing)); | |
4917 | } | |
4918 | ||
4919 | /* Create a blank optab. */ | |
4920 | static optab | |
0c20a65f | 4921 | new_optab (void) |
77c9c6c2 RK |
4922 | { |
4923 | int i; | |
703ad42b | 4924 | optab op = ggc_alloc (sizeof (struct optab)); |
77c9c6c2 RK |
4925 | for (i = 0; i < NUM_MACHINE_MODES; i++) |
4926 | { | |
4927 | op->handlers[i].insn_code = CODE_FOR_nothing; | |
4928 | op->handlers[i].libfunc = 0; | |
4929 | } | |
377017c4 | 4930 | |
ef89d648 ZW |
4931 | return op; |
4932 | } | |
377017c4 | 4933 | |
85363ca0 ZW |
4934 | static convert_optab |
4935 | new_convert_optab (void) | |
4936 | { | |
4937 | int i, j; | |
4938 | convert_optab op = ggc_alloc (sizeof (struct convert_optab)); | |
4939 | for (i = 0; i < NUM_MACHINE_MODES; i++) | |
4940 | for (j = 0; j < NUM_MACHINE_MODES; j++) | |
4941 | { | |
4942 | op->handlers[i][j].insn_code = CODE_FOR_nothing; | |
4943 | op->handlers[i][j].libfunc = 0; | |
4944 | } | |
4945 | return op; | |
4946 | } | |
4947 | ||
ef89d648 ZW |
4948 | /* Same, but fill in its code as CODE, and write it into the |
4949 | code_to_optab table. */ | |
4950 | static inline optab | |
0c20a65f | 4951 | init_optab (enum rtx_code code) |
ef89d648 ZW |
4952 | { |
4953 | optab op = new_optab (); | |
4954 | op->code = code; | |
4955 | code_to_optab[(int) code] = op; | |
4956 | return op; | |
4957 | } | |
4958 | ||
4959 | /* Same, but fill in its code as CODE, and do _not_ write it into | |
4960 | the code_to_optab table. */ | |
4961 | static inline optab | |
0c20a65f | 4962 | init_optabv (enum rtx_code code) |
ef89d648 ZW |
4963 | { |
4964 | optab op = new_optab (); | |
4965 | op->code = code; | |
77c9c6c2 RK |
4966 | return op; |
4967 | } | |
4968 | ||
85363ca0 ZW |
4969 | /* Conversion optabs never go in the code_to_optab table. */ |
4970 | static inline convert_optab | |
4971 | init_convert_optab (enum rtx_code code) | |
4972 | { | |
4973 | convert_optab op = new_convert_optab (); | |
4974 | op->code = code; | |
4975 | return op; | |
4976 | } | |
4977 | ||
b092b471 JW |
4978 | /* Initialize the libfunc fields of an entire group of entries in some |
4979 | optab. Each entry is set equal to a string consisting of a leading | |
4980 | pair of underscores followed by a generic operation name followed by | |
7ef0daad | 4981 | a mode name (downshifted to lowercase) followed by a single character |
b092b471 JW |
4982 | representing the number of operands for the given operation (which is |
4983 | usually one of the characters '2', '3', or '4'). | |
4984 | ||
4985 | OPTABLE is the table in which libfunc fields are to be initialized. | |
4986 | FIRST_MODE is the first machine mode index in the given optab to | |
4987 | initialize. | |
4988 | LAST_MODE is the last machine mode index in the given optab to | |
4989 | initialize. | |
4990 | OPNAME is the generic (string) name of the operation. | |
4991 | SUFFIX is the character which specifies the number of operands for | |
4992 | the given generic operation. | |
4993 | */ | |
4994 | ||
4995 | static void | |
0c20a65f AJ |
4996 | init_libfuncs (optab optable, int first_mode, int last_mode, |
4997 | const char *opname, int suffix) | |
b092b471 | 4998 | { |
b3694847 SS |
4999 | int mode; |
5000 | unsigned opname_len = strlen (opname); | |
b092b471 | 5001 | |
fe0035ff RS |
5002 | for (mode = first_mode; (int) mode <= (int) last_mode; |
5003 | mode = (enum machine_mode) ((int) mode + 1)) | |
b092b471 | 5004 | { |
7e1a450d | 5005 | const char *mname = GET_MODE_NAME (mode); |
b3694847 SS |
5006 | unsigned mname_len = strlen (mname); |
5007 | char *libfunc_name = alloca (2 + opname_len + mname_len + 1 + 1); | |
5008 | char *p; | |
5009 | const char *q; | |
b092b471 JW |
5010 | |
5011 | p = libfunc_name; | |
5012 | *p++ = '_'; | |
5013 | *p++ = '_'; | |
5014 | for (q = opname; *q; ) | |
5015 | *p++ = *q++; | |
5016 | for (q = mname; *q; q++) | |
92a438d1 | 5017 | *p++ = TOLOWER (*q); |
b092b471 | 5018 | *p++ = suffix; |
520a57c8 | 5019 | *p = '\0'; |
76095e2f | 5020 | |
b092b471 | 5021 | optable->handlers[(int) mode].libfunc |
68d28100 | 5022 | = init_one_libfunc (ggc_alloc_string (libfunc_name, p - libfunc_name)); |
b092b471 JW |
5023 | } |
5024 | } | |
5025 | ||
5026 | /* Initialize the libfunc fields of an entire group of entries in some | |
5027 | optab which correspond to all integer mode operations. The parameters | |
5028 | have the same meaning as similarly named ones for the `init_libfuncs' | |
5029 | routine. (See above). */ | |
5030 | ||
5031 | static void | |
0c20a65f | 5032 | init_integral_libfuncs (optab optable, const char *opname, int suffix) |
b092b471 | 5033 | { |
c0510d84 DD |
5034 | int maxsize = 2*BITS_PER_WORD; |
5035 | if (maxsize < LONG_LONG_TYPE_SIZE) | |
5036 | maxsize = LONG_LONG_TYPE_SIZE; | |
8275b011 | 5037 | init_libfuncs (optable, word_mode, |
c0510d84 | 5038 | mode_for_size (maxsize, MODE_INT, 0), |
8275b011 | 5039 | opname, suffix); |
b092b471 JW |
5040 | } |
5041 | ||
5042 | /* Initialize the libfunc fields of an entire group of entries in some | |
5043 | optab which correspond to all real mode operations. The parameters | |
5044 | have the same meaning as similarly named ones for the `init_libfuncs' | |
5045 | routine. (See above). */ | |
5046 | ||
5047 | static void | |
0c20a65f | 5048 | init_floating_libfuncs (optab optable, const char *opname, int suffix) |
b092b471 | 5049 | { |
d1d3865f | 5050 | init_libfuncs (optable, MIN_MODE_FLOAT, MAX_MODE_FLOAT, opname, suffix); |
b092b471 JW |
5051 | } |
5052 | ||
85363ca0 ZW |
5053 | /* Initialize the libfunc fields of an entire group of entries of an |
5054 | inter-mode-class conversion optab. The string formation rules are | |
5055 | similar to the ones for init_libfuncs, above, but instead of having | |
5056 | a mode name and an operand count these functions have two mode names | |
5057 | and no operand count. */ | |
5058 | static void | |
5059 | init_interclass_conv_libfuncs (convert_optab tab, const char *opname, | |
5060 | enum mode_class from_class, | |
5061 | enum mode_class to_class) | |
5062 | { | |
5063 | enum machine_mode first_from_mode = GET_CLASS_NARROWEST_MODE (from_class); | |
5064 | enum machine_mode first_to_mode = GET_CLASS_NARROWEST_MODE (to_class); | |
5065 | size_t opname_len = strlen (opname); | |
5066 | size_t max_mname_len = 0; | |
5067 | ||
5068 | enum machine_mode fmode, tmode; | |
5069 | const char *fname, *tname; | |
5070 | const char *q; | |
5071 | char *libfunc_name, *suffix; | |
5072 | char *p; | |
5073 | ||
5074 | for (fmode = first_from_mode; | |
5075 | fmode != VOIDmode; | |
5076 | fmode = GET_MODE_WIDER_MODE (fmode)) | |
5077 | max_mname_len = MAX (max_mname_len, strlen (GET_MODE_NAME (fmode))); | |
5078 | ||
5079 | for (tmode = first_to_mode; | |
5080 | tmode != VOIDmode; | |
5081 | tmode = GET_MODE_WIDER_MODE (tmode)) | |
5082 | max_mname_len = MAX (max_mname_len, strlen (GET_MODE_NAME (tmode))); | |
5083 | ||
5084 | libfunc_name = alloca (2 + opname_len + 2*max_mname_len + 1 + 1); | |
5085 | libfunc_name[0] = '_'; | |
5086 | libfunc_name[1] = '_'; | |
5087 | memcpy (&libfunc_name[2], opname, opname_len); | |
5088 | suffix = libfunc_name + opname_len + 2; | |
5089 | ||
5090 | for (fmode = first_from_mode; fmode != VOIDmode; | |
5091 | fmode = GET_MODE_WIDER_MODE (fmode)) | |
5092 | for (tmode = first_to_mode; tmode != VOIDmode; | |
5093 | tmode = GET_MODE_WIDER_MODE (tmode)) | |
5094 | { | |
5095 | fname = GET_MODE_NAME (fmode); | |
5096 | tname = GET_MODE_NAME (tmode); | |
5097 | ||
5098 | p = suffix; | |
5099 | for (q = fname; *q; p++, q++) | |
5100 | *p = TOLOWER (*q); | |
5101 | for (q = tname; *q; p++, q++) | |
5102 | *p = TOLOWER (*q); | |
5103 | ||
5104 | *p = '\0'; | |
5105 | ||
5106 | tab->handlers[tmode][fmode].libfunc | |
5107 | = init_one_libfunc (ggc_alloc_string (libfunc_name, | |
5108 | p - libfunc_name)); | |
5109 | } | |
5110 | } | |
5111 | ||
5112 | /* Initialize the libfunc fields of an entire group of entries of an | |
5113 | intra-mode-class conversion optab. The string formation rules are | |
5114 | similar to the ones for init_libfunc, above. WIDENING says whether | |
5115 | the optab goes from narrow to wide modes or vice versa. These functions | |
5116 | have two mode names _and_ an operand count. */ | |
5117 | static void | |
5118 | init_intraclass_conv_libfuncs (convert_optab tab, const char *opname, | |
5119 | enum mode_class class, bool widening) | |
5120 | { | |
5121 | enum machine_mode first_mode = GET_CLASS_NARROWEST_MODE (class); | |
5122 | size_t opname_len = strlen (opname); | |
5123 | size_t max_mname_len = 0; | |
5124 | ||
5125 | enum machine_mode nmode, wmode; | |
5126 | const char *nname, *wname; | |
5127 | const char *q; | |
5128 | char *libfunc_name, *suffix; | |
5129 | char *p; | |
5130 | ||
5131 | for (nmode = first_mode; nmode != VOIDmode; | |
5132 | nmode = GET_MODE_WIDER_MODE (nmode)) | |
5133 | max_mname_len = MAX (max_mname_len, strlen (GET_MODE_NAME (nmode))); | |
5134 | ||
5135 | libfunc_name = alloca (2 + opname_len + 2*max_mname_len + 1 + 1); | |
5136 | libfunc_name[0] = '_'; | |
5137 | libfunc_name[1] = '_'; | |
5138 | memcpy (&libfunc_name[2], opname, opname_len); | |
5139 | suffix = libfunc_name + opname_len + 2; | |
5140 | ||
5141 | for (nmode = first_mode; nmode != VOIDmode; | |
5142 | nmode = GET_MODE_WIDER_MODE (nmode)) | |
5143 | for (wmode = GET_MODE_WIDER_MODE (nmode); wmode != VOIDmode; | |
5144 | wmode = GET_MODE_WIDER_MODE (wmode)) | |
5145 | { | |
5146 | nname = GET_MODE_NAME (nmode); | |
5147 | wname = GET_MODE_NAME (wmode); | |
5148 | ||
5149 | p = suffix; | |
5150 | for (q = widening ? nname : wname; *q; p++, q++) | |
5151 | *p = TOLOWER (*q); | |
5152 | for (q = widening ? wname : nname; *q; p++, q++) | |
5153 | *p = TOLOWER (*q); | |
5154 | ||
5155 | *p++ = '2'; | |
5156 | *p = '\0'; | |
5157 | ||
456bc4bb RE |
5158 | tab->handlers[widening ? wmode : nmode] |
5159 | [widening ? nmode : wmode].libfunc | |
85363ca0 ZW |
5160 | = init_one_libfunc (ggc_alloc_string (libfunc_name, |
5161 | p - libfunc_name)); | |
5162 | } | |
5163 | } | |
5164 | ||
5165 | ||
76095e2f | 5166 | rtx |
0c20a65f | 5167 | init_one_libfunc (const char *name) |
76095e2f | 5168 | { |
52859c77 RH |
5169 | rtx symbol; |
5170 | ||
fb49053f RH |
5171 | /* Create a FUNCTION_DECL that can be passed to |
5172 | targetm.encode_section_info. */ | |
ee1315aa | 5173 | /* ??? We don't have any type information except for this is |
9c2f7166 | 5174 | a function. Pretend this is "int foo()". */ |
ee1315aa | 5175 | tree decl = build_decl (FUNCTION_DECL, get_identifier (name), |
9c2f7166 | 5176 | build_function_type (integer_type_node, NULL_TREE)); |
ee1315aa RH |
5177 | DECL_ARTIFICIAL (decl) = 1; |
5178 | DECL_EXTERNAL (decl) = 1; | |
5179 | TREE_PUBLIC (decl) = 1; | |
5180 | ||
52859c77 RH |
5181 | symbol = XEXP (DECL_RTL (decl), 0); |
5182 | ||
5183 | /* Zap the nonsensical SYMBOL_REF_DECL for this. What we're left with | |
5184 | are the flags assigned by targetm.encode_section_info. */ | |
5185 | SYMBOL_REF_DECL (symbol) = 0; | |
5186 | ||
5187 | return symbol; | |
76095e2f RH |
5188 | } |
5189 | ||
c15c90bb ZW |
5190 | /* Call this to reset the function entry for one optab (OPTABLE) in mode |
5191 | MODE to NAME, which should be either 0 or a string constant. */ | |
5192 | void | |
5193 | set_optab_libfunc (optab optable, enum machine_mode mode, const char *name) | |
5194 | { | |
5195 | if (name) | |
5196 | optable->handlers[mode].libfunc = init_one_libfunc (name); | |
5197 | else | |
5198 | optable->handlers[mode].libfunc = 0; | |
5199 | } | |
5200 | ||
85363ca0 ZW |
5201 | /* Call this to reset the function entry for one conversion optab |
5202 | (OPTABLE) from mode FMODE to mode TMODE to NAME, which should be | |
5203 | either 0 or a string constant. */ | |
5204 | void | |
5205 | set_conv_libfunc (convert_optab optable, enum machine_mode tmode, | |
5206 | enum machine_mode fmode, const char *name) | |
5207 | { | |
5208 | if (name) | |
5209 | optable->handlers[tmode][fmode].libfunc = init_one_libfunc (name); | |
5210 | else | |
5211 | optable->handlers[tmode][fmode].libfunc = 0; | |
5212 | } | |
5213 | ||
77c9c6c2 RK |
5214 | /* Call this once to initialize the contents of the optabs |
5215 | appropriately for the current target machine. */ | |
5216 | ||
5217 | void | |
0c20a65f | 5218 | init_optabs (void) |
77c9c6c2 | 5219 | { |
85363ca0 | 5220 | unsigned int i; |
77c9c6c2 | 5221 | |
5d81dc5b | 5222 | /* Start by initializing all tables to contain CODE_FOR_nothing. */ |
77c9c6c2 | 5223 | |
5d81dc5b RK |
5224 | for (i = 0; i < NUM_RTX_CODE; i++) |
5225 | setcc_gen_code[i] = CODE_FOR_nothing; | |
5226 | ||
49c4584c DE |
5227 | #ifdef HAVE_conditional_move |
5228 | for (i = 0; i < NUM_MACHINE_MODES; i++) | |
5229 | movcc_gen_code[i] = CODE_FOR_nothing; | |
5230 | #endif | |
5231 | ||
5d81dc5b | 5232 | add_optab = init_optab (PLUS); |
ef89d648 | 5233 | addv_optab = init_optabv (PLUS); |
5d81dc5b | 5234 | sub_optab = init_optab (MINUS); |
ef89d648 | 5235 | subv_optab = init_optabv (MINUS); |
5d81dc5b | 5236 | smul_optab = init_optab (MULT); |
ef89d648 | 5237 | smulv_optab = init_optabv (MULT); |
5035bbfe TG |
5238 | smul_highpart_optab = init_optab (UNKNOWN); |
5239 | umul_highpart_optab = init_optab (UNKNOWN); | |
5d81dc5b RK |
5240 | smul_widen_optab = init_optab (UNKNOWN); |
5241 | umul_widen_optab = init_optab (UNKNOWN); | |
5242 | sdiv_optab = init_optab (DIV); | |
ef89d648 | 5243 | sdivv_optab = init_optabv (DIV); |
5d81dc5b RK |
5244 | sdivmod_optab = init_optab (UNKNOWN); |
5245 | udiv_optab = init_optab (UDIV); | |
5246 | udivmod_optab = init_optab (UNKNOWN); | |
5247 | smod_optab = init_optab (MOD); | |
5248 | umod_optab = init_optab (UMOD); | |
5ae27cfa UB |
5249 | fmod_optab = init_optab (UNKNOWN); |
5250 | drem_optab = init_optab (UNKNOWN); | |
77c9c6c2 RK |
5251 | ftrunc_optab = init_optab (UNKNOWN); |
5252 | and_optab = init_optab (AND); | |
5253 | ior_optab = init_optab (IOR); | |
5254 | xor_optab = init_optab (XOR); | |
5255 | ashl_optab = init_optab (ASHIFT); | |
5256 | ashr_optab = init_optab (ASHIFTRT); | |
77c9c6c2 RK |
5257 | lshr_optab = init_optab (LSHIFTRT); |
5258 | rotl_optab = init_optab (ROTATE); | |
5259 | rotr_optab = init_optab (ROTATERT); | |
5260 | smin_optab = init_optab (SMIN); | |
5261 | smax_optab = init_optab (SMAX); | |
5262 | umin_optab = init_optab (UMIN); | |
5263 | umax_optab = init_optab (UMAX); | |
b5e01d4b RS |
5264 | pow_optab = init_optab (UNKNOWN); |
5265 | atan2_optab = init_optab (UNKNOWN); | |
ef89d648 ZW |
5266 | |
5267 | /* These three have codes assigned exclusively for the sake of | |
5268 | have_insn_for. */ | |
5269 | mov_optab = init_optab (SET); | |
5270 | movstrict_optab = init_optab (STRICT_LOW_PART); | |
5271 | cmp_optab = init_optab (COMPARE); | |
5272 | ||
77c9c6c2 RK |
5273 | ucmp_optab = init_optab (UNKNOWN); |
5274 | tst_optab = init_optab (UNKNOWN); | |
c9034561 ZW |
5275 | |
5276 | eq_optab = init_optab (EQ); | |
5277 | ne_optab = init_optab (NE); | |
5278 | gt_optab = init_optab (GT); | |
5279 | ge_optab = init_optab (GE); | |
5280 | lt_optab = init_optab (LT); | |
5281 | le_optab = init_optab (LE); | |
5282 | unord_optab = init_optab (UNORDERED); | |
5283 | ||
77c9c6c2 | 5284 | neg_optab = init_optab (NEG); |
ef89d648 | 5285 | negv_optab = init_optabv (NEG); |
77c9c6c2 | 5286 | abs_optab = init_optab (ABS); |
ef89d648 | 5287 | absv_optab = init_optabv (ABS); |
068f5dea | 5288 | addcc_optab = init_optab (UNKNOWN); |
77c9c6c2 RK |
5289 | one_cmpl_optab = init_optab (NOT); |
5290 | ffs_optab = init_optab (FFS); | |
2928cd7a RH |
5291 | clz_optab = init_optab (CLZ); |
5292 | ctz_optab = init_optab (CTZ); | |
5293 | popcount_optab = init_optab (POPCOUNT); | |
5294 | parity_optab = init_optab (PARITY); | |
d45cf215 | 5295 | sqrt_optab = init_optab (SQRT); |
4977bab6 ZW |
5296 | floor_optab = init_optab (UNKNOWN); |
5297 | ceil_optab = init_optab (UNKNOWN); | |
5298 | round_optab = init_optab (UNKNOWN); | |
85363ca0 | 5299 | btrunc_optab = init_optab (UNKNOWN); |
4977bab6 | 5300 | nearbyint_optab = init_optab (UNKNOWN); |
6c7cf1f0 | 5301 | sincos_optab = init_optab (UNKNOWN); |
28cf078d | 5302 | sin_optab = init_optab (UNKNOWN); |
c56122d8 | 5303 | asin_optab = init_optab (UNKNOWN); |
28cf078d | 5304 | cos_optab = init_optab (UNKNOWN); |
c56122d8 | 5305 | acos_optab = init_optab (UNKNOWN); |
e7b489c8 | 5306 | exp_optab = init_optab (UNKNOWN); |
a251102e UB |
5307 | exp10_optab = init_optab (UNKNOWN); |
5308 | exp2_optab = init_optab (UNKNOWN); | |
7a8e07c7 | 5309 | expm1_optab = init_optab (UNKNOWN); |
88b28a31 UB |
5310 | logb_optab = init_optab (UNKNOWN); |
5311 | ilogb_optab = init_optab (UNKNOWN); | |
e7b489c8 | 5312 | log_optab = init_optab (UNKNOWN); |
3b8e0c91 UB |
5313 | log10_optab = init_optab (UNKNOWN); |
5314 | log2_optab = init_optab (UNKNOWN); | |
c2fcfa4f | 5315 | log1p_optab = init_optab (UNKNOWN); |
82d397c7 RS |
5316 | tan_optab = init_optab (UNKNOWN); |
5317 | atan_optab = init_optab (UNKNOWN); | |
19c3fc24 | 5318 | strlen_optab = init_optab (UNKNOWN); |
1c0290ea BS |
5319 | cbranch_optab = init_optab (UNKNOWN); |
5320 | cmov_optab = init_optab (UNKNOWN); | |
5321 | cstore_optab = init_optab (UNKNOWN); | |
371b8fc0 | 5322 | push_optab = init_optab (UNKNOWN); |
77c9c6c2 | 5323 | |
997404de JH |
5324 | vec_extract_optab = init_optab (UNKNOWN); |
5325 | vec_set_optab = init_optab (UNKNOWN); | |
5326 | vec_init_optab = init_optab (UNKNOWN); | |
85363ca0 ZW |
5327 | /* Conversions. */ |
5328 | sext_optab = init_convert_optab (SIGN_EXTEND); | |
5329 | zext_optab = init_convert_optab (ZERO_EXTEND); | |
5330 | trunc_optab = init_convert_optab (TRUNCATE); | |
5331 | sfix_optab = init_convert_optab (FIX); | |
5332 | ufix_optab = init_convert_optab (UNSIGNED_FIX); | |
5333 | sfixtrunc_optab = init_convert_optab (UNKNOWN); | |
5334 | ufixtrunc_optab = init_convert_optab (UNKNOWN); | |
5335 | sfloat_optab = init_convert_optab (FLOAT); | |
5336 | ufloat_optab = init_convert_optab (UNSIGNED_FLOAT); | |
5337 | ||
5d81dc5b RK |
5338 | for (i = 0; i < NUM_MACHINE_MODES; i++) |
5339 | { | |
70128ad9 AO |
5340 | movmem_optab[i] = CODE_FOR_nothing; |
5341 | clrmem_optab[i] = CODE_FOR_nothing; | |
118355a0 ZW |
5342 | cmpstr_optab[i] = CODE_FOR_nothing; |
5343 | cmpmem_optab[i] = CODE_FOR_nothing; | |
5d81dc5b RK |
5344 | |
5345 | #ifdef HAVE_SECONDARY_RELOADS | |
5346 | reload_in_optab[i] = reload_out_optab[i] = CODE_FOR_nothing; | |
77c9c6c2 | 5347 | #endif |
5d81dc5b RK |
5348 | } |
5349 | ||
5350 | /* Fill in the optabs with the insns we support. */ | |
5351 | init_all_optabs (); | |
5352 | ||
5d81dc5b | 5353 | /* Initialize the optabs with the names of the library functions. */ |
b092b471 JW |
5354 | init_integral_libfuncs (add_optab, "add", '3'); |
5355 | init_floating_libfuncs (add_optab, "add", '3'); | |
91ce572a CC |
5356 | init_integral_libfuncs (addv_optab, "addv", '3'); |
5357 | init_floating_libfuncs (addv_optab, "add", '3'); | |
b092b471 JW |
5358 | init_integral_libfuncs (sub_optab, "sub", '3'); |
5359 | init_floating_libfuncs (sub_optab, "sub", '3'); | |
91ce572a CC |
5360 | init_integral_libfuncs (subv_optab, "subv", '3'); |
5361 | init_floating_libfuncs (subv_optab, "sub", '3'); | |
b092b471 JW |
5362 | init_integral_libfuncs (smul_optab, "mul", '3'); |
5363 | init_floating_libfuncs (smul_optab, "mul", '3'); | |
91ce572a CC |
5364 | init_integral_libfuncs (smulv_optab, "mulv", '3'); |
5365 | init_floating_libfuncs (smulv_optab, "mul", '3'); | |
5d81dc5b | 5366 | init_integral_libfuncs (sdiv_optab, "div", '3'); |
ef89d648 | 5367 | init_floating_libfuncs (sdiv_optab, "div", '3'); |
91ce572a | 5368 | init_integral_libfuncs (sdivv_optab, "divv", '3'); |
5d81dc5b RK |
5369 | init_integral_libfuncs (udiv_optab, "udiv", '3'); |
5370 | init_integral_libfuncs (sdivmod_optab, "divmod", '4'); | |
5371 | init_integral_libfuncs (udivmod_optab, "udivmod", '4'); | |
5372 | init_integral_libfuncs (smod_optab, "mod", '3'); | |
5373 | init_integral_libfuncs (umod_optab, "umod", '3'); | |
5d81dc5b RK |
5374 | init_floating_libfuncs (ftrunc_optab, "ftrunc", '2'); |
5375 | init_integral_libfuncs (and_optab, "and", '3'); | |
5376 | init_integral_libfuncs (ior_optab, "ior", '3'); | |
5377 | init_integral_libfuncs (xor_optab, "xor", '3'); | |
5378 | init_integral_libfuncs (ashl_optab, "ashl", '3'); | |
5379 | init_integral_libfuncs (ashr_optab, "ashr", '3'); | |
5d81dc5b | 5380 | init_integral_libfuncs (lshr_optab, "lshr", '3'); |
5d81dc5b RK |
5381 | init_integral_libfuncs (smin_optab, "min", '3'); |
5382 | init_floating_libfuncs (smin_optab, "min", '3'); | |
5383 | init_integral_libfuncs (smax_optab, "max", '3'); | |
5384 | init_floating_libfuncs (smax_optab, "max", '3'); | |
5385 | init_integral_libfuncs (umin_optab, "umin", '3'); | |
5386 | init_integral_libfuncs (umax_optab, "umax", '3'); | |
5387 | init_integral_libfuncs (neg_optab, "neg", '2'); | |
5388 | init_floating_libfuncs (neg_optab, "neg", '2'); | |
91ce572a CC |
5389 | init_integral_libfuncs (negv_optab, "negv", '2'); |
5390 | init_floating_libfuncs (negv_optab, "neg", '2'); | |
5d81dc5b RK |
5391 | init_integral_libfuncs (one_cmpl_optab, "one_cmpl", '2'); |
5392 | init_integral_libfuncs (ffs_optab, "ffs", '2'); | |
2928cd7a RH |
5393 | init_integral_libfuncs (clz_optab, "clz", '2'); |
5394 | init_integral_libfuncs (ctz_optab, "ctz", '2'); | |
5395 | init_integral_libfuncs (popcount_optab, "popcount", '2'); | |
5396 | init_integral_libfuncs (parity_optab, "parity", '2'); | |
5d81dc5b RK |
5397 | |
5398 | /* Comparison libcalls for integers MUST come in pairs, signed/unsigned. */ | |
5399 | init_integral_libfuncs (cmp_optab, "cmp", '2'); | |
5400 | init_integral_libfuncs (ucmp_optab, "ucmp", '2'); | |
5401 | init_floating_libfuncs (cmp_optab, "cmp", '2'); | |
77c9c6c2 | 5402 | |
c9034561 ZW |
5403 | /* EQ etc are floating point only. */ |
5404 | init_floating_libfuncs (eq_optab, "eq", '2'); | |
5405 | init_floating_libfuncs (ne_optab, "ne", '2'); | |
5406 | init_floating_libfuncs (gt_optab, "gt", '2'); | |
5407 | init_floating_libfuncs (ge_optab, "ge", '2'); | |
5408 | init_floating_libfuncs (lt_optab, "lt", '2'); | |
5409 | init_floating_libfuncs (le_optab, "le", '2'); | |
5410 | init_floating_libfuncs (unord_optab, "unord", '2'); | |
5411 | ||
85363ca0 ZW |
5412 | /* Conversions. */ |
5413 | init_interclass_conv_libfuncs (sfloat_optab, "float", MODE_INT, MODE_FLOAT); | |
5414 | init_interclass_conv_libfuncs (sfix_optab, "fix", MODE_FLOAT, MODE_INT); | |
5415 | init_interclass_conv_libfuncs (ufix_optab, "fixuns", MODE_FLOAT, MODE_INT); | |
77c9c6c2 | 5416 | |
85363ca0 ZW |
5417 | /* sext_optab is also used for FLOAT_EXTEND. */ |
5418 | init_intraclass_conv_libfuncs (sext_optab, "extend", MODE_FLOAT, true); | |
5419 | init_intraclass_conv_libfuncs (trunc_optab, "trunc", MODE_FLOAT, false); | |
76095e2f | 5420 | |
85363ca0 ZW |
5421 | /* Use cabs for double complex abs, since systems generally have cabs. |
5422 | Don't define any libcall for float complex, so that cabs will be used. */ | |
5423 | if (complex_double_type_node) | |
5424 | abs_optab->handlers[TYPE_MODE (complex_double_type_node)].libfunc | |
5425 | = init_one_libfunc ("cabs"); | |
76095e2f | 5426 | |
d91edf86 | 5427 | /* The ffs function operates on `int'. */ |
85363ca0 ZW |
5428 | ffs_optab->handlers[(int) mode_for_size (INT_TYPE_SIZE, MODE_INT, 0)].libfunc |
5429 | = init_one_libfunc ("ffs"); | |
76095e2f | 5430 | |
9602f5a0 | 5431 | abort_libfunc = init_one_libfunc ("abort"); |
76095e2f | 5432 | memcpy_libfunc = init_one_libfunc ("memcpy"); |
b215b52e | 5433 | memmove_libfunc = init_one_libfunc ("memmove"); |
76095e2f | 5434 | memcmp_libfunc = init_one_libfunc ("memcmp"); |
76095e2f | 5435 | memset_libfunc = init_one_libfunc ("memset"); |
68d28100 | 5436 | setbits_libfunc = init_one_libfunc ("__setbits"); |
76095e2f | 5437 | |
52a11cbf RH |
5438 | unwind_resume_libfunc = init_one_libfunc (USING_SJLJ_EXCEPTIONS |
5439 | ? "_Unwind_SjLj_Resume" | |
5440 | : "_Unwind_Resume"); | |
6e6a07d2 | 5441 | #ifndef DONT_USE_BUILTIN_SETJMP |
76095e2f RH |
5442 | setjmp_libfunc = init_one_libfunc ("__builtin_setjmp"); |
5443 | longjmp_libfunc = init_one_libfunc ("__builtin_longjmp"); | |
27a36778 | 5444 | #else |
76095e2f RH |
5445 | setjmp_libfunc = init_one_libfunc ("setjmp"); |
5446 | longjmp_libfunc = init_one_libfunc ("longjmp"); | |
27a36778 | 5447 | #endif |
52a11cbf RH |
5448 | unwind_sjlj_register_libfunc = init_one_libfunc ("_Unwind_SjLj_Register"); |
5449 | unwind_sjlj_unregister_libfunc | |
5450 | = init_one_libfunc ("_Unwind_SjLj_Unregister"); | |
6adb4e3a | 5451 | |
07417085 KR |
5452 | /* For function entry/exit instrumentation. */ |
5453 | profile_function_entry_libfunc | |
76095e2f | 5454 | = init_one_libfunc ("__cyg_profile_func_enter"); |
07417085 | 5455 | profile_function_exit_libfunc |
76095e2f | 5456 | = init_one_libfunc ("__cyg_profile_func_exit"); |
07417085 | 5457 | |
68d28100 | 5458 | gcov_flush_libfunc = init_one_libfunc ("__gcov_flush"); |
68d28100 | 5459 | |
842a431a DM |
5460 | if (HAVE_conditional_trap) |
5461 | trap_rtx = gen_rtx_fmt_ee (EQ, VOIDmode, NULL_RTX, NULL_RTX); | |
e0cd0770 | 5462 | |
159c2aed | 5463 | /* Allow the target to add more libcalls or rename some, etc. */ |
c15c90bb | 5464 | targetm.init_libfuncs (); |
77c9c6c2 | 5465 | } |
7e1966ca | 5466 | \f |
e0cd0770 JC |
5467 | /* Generate insns to trap with code TCODE if OP1 and OP2 satisfy condition |
5468 | CODE. Return 0 on failure. */ | |
5469 | ||
5470 | rtx | |
0c20a65f AJ |
5471 | gen_cond_trap (enum rtx_code code ATTRIBUTE_UNUSED, rtx op1, |
5472 | rtx op2 ATTRIBUTE_UNUSED, rtx tcode ATTRIBUTE_UNUSED) | |
e0cd0770 JC |
5473 | { |
5474 | enum machine_mode mode = GET_MODE (op1); | |
842a431a DM |
5475 | enum insn_code icode; |
5476 | rtx insn; | |
5477 | ||
5478 | if (!HAVE_conditional_trap) | |
5479 | return 0; | |
e0cd0770 JC |
5480 | |
5481 | if (mode == VOIDmode) | |
5482 | return 0; | |
5483 | ||
842a431a DM |
5484 | icode = cmp_optab->handlers[(int) mode].insn_code; |
5485 | if (icode == CODE_FOR_nothing) | |
5486 | return 0; | |
5487 | ||
5488 | start_sequence (); | |
5489 | op1 = prepare_operand (icode, op1, 0, mode, mode, 0); | |
0310c414 | 5490 | op2 = prepare_operand (icode, op2, 1, mode, mode, 0); |
d893ccde RH |
5491 | if (!op1 || !op2) |
5492 | { | |
5493 | end_sequence (); | |
5494 | return 0; | |
5495 | } | |
842a431a DM |
5496 | emit_insn (GEN_FCN (icode) (op1, op2)); |
5497 | ||
5498 | PUT_CODE (trap_rtx, code); | |
5499 | insn = gen_conditional_trap (trap_rtx, tcode); | |
5500 | if (insn) | |
e0cd0770 | 5501 | { |
842a431a DM |
5502 | emit_insn (insn); |
5503 | insn = get_insns (); | |
e0cd0770 | 5504 | } |
842a431a | 5505 | end_sequence (); |
e0cd0770 | 5506 | |
842a431a | 5507 | return insn; |
e0cd0770 | 5508 | } |
e2500fed GK |
5509 | |
5510 | #include "gt-optabs.h" |