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1f215c26 | 1 | /* Expand the basic unary and binary arithmetic operations, for GNU compiler. |
2f791da8 | 2 | Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
b9c74b4d | 3 | 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 |
981eb798 | 4 | Free Software Foundation, Inc. |
1f215c26 | 5 | |
f12b58b3 | 6 | This file is part of GCC. |
1f215c26 | 7 | |
f12b58b3 | 8 | GCC is free software; you can redistribute it and/or modify it under |
9 | the terms of the GNU General Public License as published by the Free | |
8c4c00c1 | 10 | Software Foundation; either version 3, or (at your option) any later |
f12b58b3 | 11 | version. |
1f215c26 | 12 | |
f12b58b3 | 13 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
14 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | for more details. | |
1f215c26 | 17 | |
18 | You should have received a copy of the GNU General Public License | |
8c4c00c1 | 19 | along with GCC; see the file COPYING3. If not see |
20 | <http://www.gnu.org/licenses/>. */ | |
1f215c26 | 21 | |
22 | ||
23 | #include "config.h" | |
405711de | 24 | #include "system.h" |
805e22b2 | 25 | #include "coretypes.h" |
26 | #include "tm.h" | |
d3b64f2d | 27 | #include "toplev.h" |
3eee82c5 | 28 | |
29 | /* Include insn-config.h before expr.h so that HAVE_conditional_move | |
aa40f561 | 30 | is properly defined. */ |
3eee82c5 | 31 | #include "insn-config.h" |
1f215c26 | 32 | #include "rtl.h" |
33 | #include "tree.h" | |
7953c610 | 34 | #include "tm_p.h" |
1f215c26 | 35 | #include "flags.h" |
0a893c29 | 36 | #include "function.h" |
df4b504c | 37 | #include "except.h" |
1f215c26 | 38 | #include "expr.h" |
d8fc4d0b | 39 | #include "optabs.h" |
40 | #include "libfuncs.h" | |
1f215c26 | 41 | #include "recog.h" |
4ed2a1b5 | 42 | #include "reload.h" |
a7b0c170 | 43 | #include "ggc.h" |
d8c9779c | 44 | #include "real.h" |
d16f9b9d | 45 | #include "basic-block.h" |
f2f543a3 | 46 | #include "target.h" |
1f215c26 | 47 | |
48 | /* Each optab contains info on how this target machine | |
49 | can perform a particular operation | |
50 | for all sizes and kinds of operands. | |
51 | ||
52 | The operation to be performed is often specified | |
53 | by passing one of these optabs as an argument. | |
54 | ||
55 | See expr.h for documentation of these optabs. */ | |
56 | ||
423aab86 | 57 | #if GCC_VERSION >= 4000 && HAVE_DESIGNATED_INITIALIZERS |
26dbec0a | 58 | __extension__ struct optab_d optab_table[OTI_MAX] |
be5cecfd | 59 | = { [0 ... OTI_MAX - 1].handlers[0 ... NUM_MACHINE_MODES - 1].insn_code |
60 | = CODE_FOR_nothing }; | |
61 | #else | |
53b14d73 | 62 | /* init_insn_codes will do runtime initialization otherwise. */ |
26dbec0a | 63 | struct optab_d optab_table[OTI_MAX]; |
be5cecfd | 64 | #endif |
f8af7043 | 65 | |
66 | rtx libfunc_table[LTI_MAX]; | |
5eb0d754 | 67 | |
a7cc195f | 68 | /* Tables of patterns for converting one mode to another. */ |
423aab86 | 69 | #if GCC_VERSION >= 4000 && HAVE_DESIGNATED_INITIALIZERS |
26dbec0a | 70 | __extension__ struct convert_optab_d convert_optab_table[COI_MAX] |
be5cecfd | 71 | = { [0 ... COI_MAX - 1].handlers[0 ... NUM_MACHINE_MODES - 1] |
72 | [0 ... NUM_MACHINE_MODES - 1].insn_code | |
73 | = CODE_FOR_nothing }; | |
74 | #else | |
75 | /* init_convert_optab will do runtime initialization otherwise. */ | |
26dbec0a | 76 | struct convert_optab_d convert_optab_table[COI_MAX]; |
be5cecfd | 77 | #endif |
2850b1f2 | 78 | |
94a588c3 | 79 | /* Contains the optab used for each rtx code. */ |
80 | optab code_to_optab[NUM_RTX_CODE + 1]; | |
81 | ||
62528147 | 82 | #ifdef HAVE_conditional_move |
83 | /* Indexed by the machine mode, gives the insn code to make a conditional | |
84 | move insn. This is not indexed by the rtx-code like bcc_gen_fctn and | |
85 | setcc_gen_code to cut down on the number of named patterns. Consider a day | |
86 | when a lot more rtx codes are conditional (eg: for the ARM). */ | |
87 | ||
88 | enum insn_code movcc_gen_code[NUM_MACHINE_MODES]; | |
89 | #endif | |
90 | ||
6b7acc28 | 91 | /* Indexed by the machine mode, gives the insn code for vector conditional |
92 | operation. */ | |
93 | ||
94 | enum insn_code vcond_gen_code[NUM_MACHINE_MODES]; | |
95 | enum insn_code vcondu_gen_code[NUM_MACHINE_MODES]; | |
96 | ||
74f4459c | 97 | static void prepare_float_lib_cmp (rtx, rtx, enum rtx_code, rtx *, |
98 | enum machine_mode *); | |
5e02ce4e | 99 | static rtx expand_unop_direct (enum machine_mode, optab, rtx, rtx, int); |
b3a15ba6 | 100 | |
f36b9f69 | 101 | /* Debug facility for use in GDB. */ |
102 | void debug_optab_libfuncs (void); | |
103 | ||
10de71e1 | 104 | /* Prefixes for the current version of decimal floating point (BID vs. DPD) */ |
105 | #if ENABLE_DECIMAL_BID_FORMAT | |
106 | #define DECIMAL_PREFIX "bid_" | |
107 | #else | |
108 | #define DECIMAL_PREFIX "dpd_" | |
109 | #endif | |
f36b9f69 | 110 | \f |
111 | ||
112 | /* Info about libfunc. We use same hashtable for normal optabs and conversion | |
113 | optab. In the first case mode2 is unused. */ | |
fb1e4f4a | 114 | struct GTY(()) libfunc_entry { |
fec2d214 | 115 | size_t optab; |
f36b9f69 | 116 | enum machine_mode mode1, mode2; |
117 | rtx libfunc; | |
118 | }; | |
119 | ||
120 | /* Hash table used to convert declarations into nodes. */ | |
121 | static GTY((param_is (struct libfunc_entry))) htab_t libfunc_hash; | |
122 | ||
123 | /* Used for attribute_hash. */ | |
124 | ||
125 | static hashval_t | |
126 | hash_libfunc (const void *p) | |
127 | { | |
128 | const struct libfunc_entry *const e = (const struct libfunc_entry *) p; | |
129 | ||
130 | return (((int) e->mode1 + (int) e->mode2 * NUM_MACHINE_MODES) | |
fec2d214 | 131 | ^ e->optab); |
f36b9f69 | 132 | } |
133 | ||
134 | /* Used for optab_hash. */ | |
135 | ||
136 | static int | |
137 | eq_libfunc (const void *p, const void *q) | |
138 | { | |
139 | const struct libfunc_entry *const e1 = (const struct libfunc_entry *) p; | |
140 | const struct libfunc_entry *const e2 = (const struct libfunc_entry *) q; | |
141 | ||
142 | return (e1->optab == e2->optab | |
143 | && e1->mode1 == e2->mode1 | |
144 | && e1->mode2 == e2->mode2); | |
145 | } | |
146 | ||
147 | /* Return libfunc corresponding operation defined by OPTAB converting | |
148 | from MODE2 to MODE1. Trigger lazy initialization if needed, return NULL | |
149 | if no libfunc is available. */ | |
150 | rtx | |
151 | convert_optab_libfunc (convert_optab optab, enum machine_mode mode1, | |
152 | enum machine_mode mode2) | |
153 | { | |
154 | struct libfunc_entry e; | |
155 | struct libfunc_entry **slot; | |
156 | ||
be5cecfd | 157 | e.optab = (size_t) (optab - &convert_optab_table[0]); |
f36b9f69 | 158 | e.mode1 = mode1; |
159 | e.mode2 = mode2; | |
160 | slot = (struct libfunc_entry **) htab_find_slot (libfunc_hash, &e, NO_INSERT); | |
161 | if (!slot) | |
162 | { | |
163 | if (optab->libcall_gen) | |
164 | { | |
165 | optab->libcall_gen (optab, optab->libcall_basename, mode1, mode2); | |
166 | slot = (struct libfunc_entry **) htab_find_slot (libfunc_hash, &e, NO_INSERT); | |
167 | if (slot) | |
168 | return (*slot)->libfunc; | |
169 | else | |
170 | return NULL; | |
171 | } | |
172 | return NULL; | |
173 | } | |
174 | return (*slot)->libfunc; | |
175 | } | |
176 | ||
177 | /* Return libfunc corresponding operation defined by OPTAB in MODE. | |
178 | Trigger lazy initialization if needed, return NULL if no libfunc is | |
179 | available. */ | |
180 | rtx | |
181 | optab_libfunc (optab optab, enum machine_mode mode) | |
182 | { | |
183 | struct libfunc_entry e; | |
184 | struct libfunc_entry **slot; | |
185 | ||
be5cecfd | 186 | e.optab = (size_t) (optab - &optab_table[0]); |
f36b9f69 | 187 | e.mode1 = mode; |
188 | e.mode2 = VOIDmode; | |
189 | slot = (struct libfunc_entry **) htab_find_slot (libfunc_hash, &e, NO_INSERT); | |
190 | if (!slot) | |
191 | { | |
192 | if (optab->libcall_gen) | |
193 | { | |
194 | optab->libcall_gen (optab, optab->libcall_basename, | |
195 | optab->libcall_suffix, mode); | |
196 | slot = (struct libfunc_entry **) htab_find_slot (libfunc_hash, | |
197 | &e, NO_INSERT); | |
198 | if (slot) | |
199 | return (*slot)->libfunc; | |
200 | else | |
201 | return NULL; | |
202 | } | |
203 | return NULL; | |
204 | } | |
205 | return (*slot)->libfunc; | |
206 | } | |
10de71e1 | 207 | |
1f215c26 | 208 | \f |
31d3e01c | 209 | /* Add a REG_EQUAL note to the last insn in INSNS. TARGET is being set to |
1f215c26 | 210 | the result of operation CODE applied to OP0 (and OP1 if it is a binary |
211 | operation). | |
212 | ||
213 | If the last insn does not set TARGET, don't do anything, but return 1. | |
214 | ||
215 | If a previous insn sets TARGET and TARGET is one of OP0 or OP1, | |
216 | don't add the REG_EQUAL note but return 0. Our caller can then try | |
217 | again, ensuring that TARGET is not one of the operands. */ | |
218 | ||
219 | static int | |
3ad4992f | 220 | add_equal_note (rtx insns, rtx target, enum rtx_code code, rtx op0, rtx op1) |
1f215c26 | 221 | { |
31d3e01c | 222 | rtx last_insn, insn, set; |
1f215c26 | 223 | rtx note; |
224 | ||
ce572eff | 225 | gcc_assert (insns && INSN_P (insns) && NEXT_INSN (insns)); |
31d3e01c | 226 | |
6720e96c | 227 | if (GET_RTX_CLASS (code) != RTX_COMM_ARITH |
228 | && GET_RTX_CLASS (code) != RTX_BIN_ARITH | |
229 | && GET_RTX_CLASS (code) != RTX_COMM_COMPARE | |
230 | && GET_RTX_CLASS (code) != RTX_COMPARE | |
231 | && GET_RTX_CLASS (code) != RTX_UNARY) | |
31d3e01c | 232 | return 1; |
233 | ||
234 | if (GET_CODE (target) == ZERO_EXTRACT) | |
235 | return 1; | |
236 | ||
237 | for (last_insn = insns; | |
238 | NEXT_INSN (last_insn) != NULL_RTX; | |
239 | last_insn = NEXT_INSN (last_insn)) | |
240 | ; | |
241 | ||
242 | set = single_set (last_insn); | |
243 | if (set == NULL_RTX) | |
244 | return 1; | |
245 | ||
246 | if (! rtx_equal_p (SET_DEST (set), target) | |
52ce4c9b | 247 | /* For a STRICT_LOW_PART, the REG_NOTE applies to what is inside it. */ |
31d3e01c | 248 | && (GET_CODE (SET_DEST (set)) != STRICT_LOW_PART |
52ce4c9b | 249 | || ! rtx_equal_p (XEXP (SET_DEST (set), 0), target))) |
1f215c26 | 250 | return 1; |
251 | ||
252 | /* If TARGET is in OP0 or OP1, check if anything in SEQ sets TARGET | |
253 | besides the last insn. */ | |
254 | if (reg_overlap_mentioned_p (target, op0) | |
255 | || (op1 && reg_overlap_mentioned_p (target, op1))) | |
31d3e01c | 256 | { |
257 | insn = PREV_INSN (last_insn); | |
258 | while (insn != NULL_RTX) | |
259 | { | |
260 | if (reg_set_p (target, insn)) | |
261 | return 0; | |
262 | ||
263 | insn = PREV_INSN (insn); | |
264 | } | |
265 | } | |
1f215c26 | 266 | |
6720e96c | 267 | if (GET_RTX_CLASS (code) == RTX_UNARY) |
e02c6d1f | 268 | note = gen_rtx_fmt_e (code, GET_MODE (target), copy_rtx (op0)); |
1f215c26 | 269 | else |
e02c6d1f | 270 | note = gen_rtx_fmt_ee (code, GET_MODE (target), copy_rtx (op0), copy_rtx (op1)); |
1f215c26 | 271 | |
31d3e01c | 272 | set_unique_reg_note (last_insn, REG_EQUAL, note); |
1f215c26 | 273 | |
274 | return 1; | |
275 | } | |
276 | \f | |
45282828 | 277 | /* Widen OP to MODE and return the rtx for the widened operand. UNSIGNEDP |
278 | says whether OP is signed or unsigned. NO_EXTEND is nonzero if we need | |
3ad4992f | 279 | not actually do a sign-extend or zero-extend, but can leave the |
45282828 | 280 | higher-order bits of the result rtx undefined, for example, in the case |
281 | of logical operations, but not right shifts. */ | |
282 | ||
283 | static rtx | |
3ad4992f | 284 | widen_operand (rtx op, enum machine_mode mode, enum machine_mode oldmode, |
285 | int unsignedp, int no_extend) | |
45282828 | 286 | { |
287 | rtx result; | |
288 | ||
8b315642 | 289 | /* If we don't have to extend and this is a constant, return it. */ |
290 | if (no_extend && GET_MODE (op) == VOIDmode) | |
291 | return op; | |
292 | ||
293 | /* If we must extend do so. If OP is a SUBREG for a promoted object, also | |
294 | extend since it will be more efficient to do so unless the signedness of | |
295 | a promoted object differs from our extension. */ | |
45282828 | 296 | if (! no_extend |
e99172f2 | 297 | || (GET_CODE (op) == SUBREG && SUBREG_PROMOTED_VAR_P (op) |
298 | && SUBREG_PROMOTED_UNSIGNED_P (op) == unsignedp)) | |
92d67582 | 299 | return convert_modes (mode, oldmode, op, unsignedp); |
45282828 | 300 | |
301 | /* If MODE is no wider than a single word, we return a paradoxical | |
302 | SUBREG. */ | |
303 | if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD) | |
e02c6d1f | 304 | return gen_rtx_SUBREG (mode, force_reg (GET_MODE (op), op), 0); |
45282828 | 305 | |
306 | /* Otherwise, get an object of MODE, clobber it, and set the low-order | |
307 | part to OP. */ | |
308 | ||
309 | result = gen_reg_rtx (mode); | |
18b42941 | 310 | emit_clobber (result); |
45282828 | 311 | emit_move_insn (gen_lowpart (GET_MODE (op), result), op); |
312 | return result; | |
313 | } | |
314 | \f | |
4d54df85 | 315 | /* Return the optab used for computing the operation given by the tree code, |
316 | CODE and the tree EXP. This function is not always usable (for example, it | |
317 | cannot give complete results for multiplication or division) but probably | |
318 | ought to be relied on more widely throughout the expander. */ | |
83e2a11b | 319 | optab |
4d54df85 | 320 | optab_for_tree_code (enum tree_code code, const_tree type, |
321 | enum optab_subtype subtype) | |
83e2a11b | 322 | { |
323 | bool trapv; | |
324 | switch (code) | |
325 | { | |
326 | case BIT_AND_EXPR: | |
327 | return and_optab; | |
328 | ||
329 | case BIT_IOR_EXPR: | |
330 | return ior_optab; | |
331 | ||
332 | case BIT_NOT_EXPR: | |
333 | return one_cmpl_optab; | |
334 | ||
335 | case BIT_XOR_EXPR: | |
336 | return xor_optab; | |
337 | ||
338 | case TRUNC_MOD_EXPR: | |
339 | case CEIL_MOD_EXPR: | |
340 | case FLOOR_MOD_EXPR: | |
341 | case ROUND_MOD_EXPR: | |
342 | return TYPE_UNSIGNED (type) ? umod_optab : smod_optab; | |
343 | ||
344 | case RDIV_EXPR: | |
345 | case TRUNC_DIV_EXPR: | |
346 | case CEIL_DIV_EXPR: | |
347 | case FLOOR_DIV_EXPR: | |
348 | case ROUND_DIV_EXPR: | |
349 | case EXACT_DIV_EXPR: | |
68a556d6 | 350 | if (TYPE_SATURATING(type)) |
351 | return TYPE_UNSIGNED(type) ? usdiv_optab : ssdiv_optab; | |
83e2a11b | 352 | return TYPE_UNSIGNED (type) ? udiv_optab : sdiv_optab; |
353 | ||
354 | case LSHIFT_EXPR: | |
4d54df85 | 355 | if (VECTOR_MODE_P (TYPE_MODE (type))) |
356 | { | |
357 | if (subtype == optab_vector) | |
358 | return TYPE_SATURATING (type) ? NULL : vashl_optab; | |
359 | ||
360 | gcc_assert (subtype == optab_scalar); | |
361 | } | |
68a556d6 | 362 | if (TYPE_SATURATING(type)) |
363 | return TYPE_UNSIGNED(type) ? usashl_optab : ssashl_optab; | |
83e2a11b | 364 | return ashl_optab; |
365 | ||
366 | case RSHIFT_EXPR: | |
4d54df85 | 367 | if (VECTOR_MODE_P (TYPE_MODE (type))) |
368 | { | |
369 | if (subtype == optab_vector) | |
370 | return TYPE_UNSIGNED (type) ? vlshr_optab : vashr_optab; | |
371 | ||
372 | gcc_assert (subtype == optab_scalar); | |
373 | } | |
83e2a11b | 374 | return TYPE_UNSIGNED (type) ? lshr_optab : ashr_optab; |
375 | ||
376 | case LROTATE_EXPR: | |
4d54df85 | 377 | if (VECTOR_MODE_P (TYPE_MODE (type))) |
378 | { | |
379 | if (subtype == optab_vector) | |
380 | return vrotl_optab; | |
381 | ||
382 | gcc_assert (subtype == optab_scalar); | |
383 | } | |
83e2a11b | 384 | return rotl_optab; |
385 | ||
386 | case RROTATE_EXPR: | |
4d54df85 | 387 | if (VECTOR_MODE_P (TYPE_MODE (type))) |
388 | { | |
389 | if (subtype == optab_vector) | |
390 | return vrotr_optab; | |
391 | ||
392 | gcc_assert (subtype == optab_scalar); | |
393 | } | |
83e2a11b | 394 | return rotr_optab; |
395 | ||
396 | case MAX_EXPR: | |
397 | return TYPE_UNSIGNED (type) ? umax_optab : smax_optab; | |
398 | ||
399 | case MIN_EXPR: | |
400 | return TYPE_UNSIGNED (type) ? umin_optab : smin_optab; | |
401 | ||
b056d812 | 402 | case REALIGN_LOAD_EXPR: |
403 | return vec_realign_load_optab; | |
404 | ||
4a61a337 | 405 | case WIDEN_SUM_EXPR: |
406 | return TYPE_UNSIGNED (type) ? usum_widen_optab : ssum_widen_optab; | |
407 | ||
408 | case DOT_PROD_EXPR: | |
409 | return TYPE_UNSIGNED (type) ? udot_prod_optab : sdot_prod_optab; | |
410 | ||
ea8f3370 | 411 | case REDUC_MAX_EXPR: |
412 | return TYPE_UNSIGNED (type) ? reduc_umax_optab : reduc_smax_optab; | |
413 | ||
414 | case REDUC_MIN_EXPR: | |
415 | return TYPE_UNSIGNED (type) ? reduc_umin_optab : reduc_smin_optab; | |
416 | ||
417 | case REDUC_PLUS_EXPR: | |
925c62d4 | 418 | return TYPE_UNSIGNED (type) ? reduc_uplus_optab : reduc_splus_optab; |
419 | ||
420 | case VEC_LSHIFT_EXPR: | |
421 | return vec_shl_optab; | |
422 | ||
423 | case VEC_RSHIFT_EXPR: | |
424 | return vec_shr_optab; | |
ea8f3370 | 425 | |
c6c91d61 | 426 | case VEC_WIDEN_MULT_HI_EXPR: |
427 | return TYPE_UNSIGNED (type) ? | |
428 | vec_widen_umult_hi_optab : vec_widen_smult_hi_optab; | |
429 | ||
430 | case VEC_WIDEN_MULT_LO_EXPR: | |
431 | return TYPE_UNSIGNED (type) ? | |
432 | vec_widen_umult_lo_optab : vec_widen_smult_lo_optab; | |
433 | ||
434 | case VEC_UNPACK_HI_EXPR: | |
bb8107e7 | 435 | return TYPE_UNSIGNED (type) ? |
c6c91d61 | 436 | vec_unpacku_hi_optab : vec_unpacks_hi_optab; |
437 | ||
438 | case VEC_UNPACK_LO_EXPR: | |
439 | return TYPE_UNSIGNED (type) ? | |
440 | vec_unpacku_lo_optab : vec_unpacks_lo_optab; | |
441 | ||
8aa4e142 | 442 | case VEC_UNPACK_FLOAT_HI_EXPR: |
443 | /* The signedness is determined from input operand. */ | |
444 | return TYPE_UNSIGNED (type) ? | |
445 | vec_unpacku_float_hi_optab : vec_unpacks_float_hi_optab; | |
446 | ||
447 | case VEC_UNPACK_FLOAT_LO_EXPR: | |
448 | /* The signedness is determined from input operand. */ | |
449 | return TYPE_UNSIGNED (type) ? | |
450 | vec_unpacku_float_lo_optab : vec_unpacks_float_lo_optab; | |
451 | ||
bb8107e7 | 452 | case VEC_PACK_TRUNC_EXPR: |
453 | return vec_pack_trunc_optab; | |
454 | ||
c6c91d61 | 455 | case VEC_PACK_SAT_EXPR: |
456 | return TYPE_UNSIGNED (type) ? vec_pack_usat_optab : vec_pack_ssat_optab; | |
bb8107e7 | 457 | |
8aa4e142 | 458 | case VEC_PACK_FIX_TRUNC_EXPR: |
bb6c9541 | 459 | /* The signedness is determined from output operand. */ |
8aa4e142 | 460 | return TYPE_UNSIGNED (type) ? |
461 | vec_pack_ufix_trunc_optab : vec_pack_sfix_trunc_optab; | |
462 | ||
83e2a11b | 463 | default: |
464 | break; | |
465 | } | |
466 | ||
981eb798 | 467 | trapv = INTEGRAL_TYPE_P (type) && TYPE_OVERFLOW_TRAPS (type); |
83e2a11b | 468 | switch (code) |
469 | { | |
0de36bdb | 470 | case POINTER_PLUS_EXPR: |
83e2a11b | 471 | case PLUS_EXPR: |
68a556d6 | 472 | if (TYPE_SATURATING(type)) |
473 | return TYPE_UNSIGNED(type) ? usadd_optab : ssadd_optab; | |
83e2a11b | 474 | return trapv ? addv_optab : add_optab; |
475 | ||
476 | case MINUS_EXPR: | |
68a556d6 | 477 | if (TYPE_SATURATING(type)) |
478 | return TYPE_UNSIGNED(type) ? ussub_optab : sssub_optab; | |
83e2a11b | 479 | return trapv ? subv_optab : sub_optab; |
480 | ||
481 | case MULT_EXPR: | |
68a556d6 | 482 | if (TYPE_SATURATING(type)) |
483 | return TYPE_UNSIGNED(type) ? usmul_optab : ssmul_optab; | |
83e2a11b | 484 | return trapv ? smulv_optab : smul_optab; |
485 | ||
486 | case NEGATE_EXPR: | |
68a556d6 | 487 | if (TYPE_SATURATING(type)) |
488 | return TYPE_UNSIGNED(type) ? usneg_optab : ssneg_optab; | |
83e2a11b | 489 | return trapv ? negv_optab : neg_optab; |
490 | ||
491 | case ABS_EXPR: | |
492 | return trapv ? absv_optab : abs_optab; | |
493 | ||
6b8dbb53 | 494 | case VEC_EXTRACT_EVEN_EXPR: |
495 | return vec_extract_even_optab; | |
496 | ||
497 | case VEC_EXTRACT_ODD_EXPR: | |
498 | return vec_extract_odd_optab; | |
499 | ||
500 | case VEC_INTERLEAVE_HIGH_EXPR: | |
501 | return vec_interleave_high_optab; | |
502 | ||
503 | case VEC_INTERLEAVE_LOW_EXPR: | |
504 | return vec_interleave_low_optab; | |
505 | ||
83e2a11b | 506 | default: |
507 | return NULL; | |
508 | } | |
509 | } | |
c49547c4 | 510 | \f |
b056d812 | 511 | |
4a61a337 | 512 | /* Expand vector widening operations. |
513 | ||
514 | There are two different classes of operations handled here: | |
515 | 1) Operations whose result is wider than all the arguments to the operation. | |
516 | Examples: VEC_UNPACK_HI/LO_EXPR, VEC_WIDEN_MULT_HI/LO_EXPR | |
517 | In this case OP0 and optionally OP1 would be initialized, | |
518 | but WIDE_OP wouldn't (not relevant for this case). | |
519 | 2) Operations whose result is of the same size as the last argument to the | |
520 | operation, but wider than all the other arguments to the operation. | |
521 | Examples: WIDEN_SUM_EXPR, VEC_DOT_PROD_EXPR. | |
522 | In the case WIDE_OP, OP0 and optionally OP1 would be initialized. | |
523 | ||
524 | E.g, when called to expand the following operations, this is how | |
525 | the arguments will be initialized: | |
526 | nops OP0 OP1 WIDE_OP | |
527 | widening-sum 2 oprnd0 - oprnd1 | |
528 | widening-dot-product 3 oprnd0 oprnd1 oprnd2 | |
529 | widening-mult 2 oprnd0 oprnd1 - | |
530 | type-promotion (vec-unpack) 1 oprnd0 - - */ | |
531 | ||
532 | rtx | |
533 | expand_widen_pattern_expr (tree exp, rtx op0, rtx op1, rtx wide_op, rtx target, | |
534 | int unsignedp) | |
535 | { | |
536 | tree oprnd0, oprnd1, oprnd2; | |
bc620c5c | 537 | enum machine_mode wmode = VOIDmode, tmode0, tmode1 = VOIDmode; |
4a61a337 | 538 | optab widen_pattern_optab; |
539 | int icode; | |
bc620c5c | 540 | enum machine_mode xmode0, xmode1 = VOIDmode, wxmode = VOIDmode; |
4a61a337 | 541 | rtx temp; |
542 | rtx pat; | |
543 | rtx xop0, xop1, wxop; | |
c2f47e15 | 544 | int nops = TREE_OPERAND_LENGTH (exp); |
4a61a337 | 545 | |
546 | oprnd0 = TREE_OPERAND (exp, 0); | |
547 | tmode0 = TYPE_MODE (TREE_TYPE (oprnd0)); | |
548 | widen_pattern_optab = | |
4d54df85 | 549 | optab_for_tree_code (TREE_CODE (exp), TREE_TYPE (oprnd0), optab_default); |
99bdde56 | 550 | icode = (int) optab_handler (widen_pattern_optab, tmode0)->insn_code; |
4a61a337 | 551 | gcc_assert (icode != CODE_FOR_nothing); |
552 | xmode0 = insn_data[icode].operand[1].mode; | |
553 | ||
554 | if (nops >= 2) | |
555 | { | |
556 | oprnd1 = TREE_OPERAND (exp, 1); | |
557 | tmode1 = TYPE_MODE (TREE_TYPE (oprnd1)); | |
558 | xmode1 = insn_data[icode].operand[2].mode; | |
559 | } | |
560 | ||
561 | /* The last operand is of a wider mode than the rest of the operands. */ | |
562 | if (nops == 2) | |
563 | { | |
564 | wmode = tmode1; | |
565 | wxmode = xmode1; | |
566 | } | |
567 | else if (nops == 3) | |
568 | { | |
569 | gcc_assert (tmode1 == tmode0); | |
570 | gcc_assert (op1); | |
571 | oprnd2 = TREE_OPERAND (exp, 2); | |
572 | wmode = TYPE_MODE (TREE_TYPE (oprnd2)); | |
573 | wxmode = insn_data[icode].operand[3].mode; | |
574 | } | |
575 | ||
576 | if (!wide_op) | |
577 | wmode = wxmode = insn_data[icode].operand[0].mode; | |
578 | ||
579 | if (!target | |
580 | || ! (*insn_data[icode].operand[0].predicate) (target, wmode)) | |
581 | temp = gen_reg_rtx (wmode); | |
582 | else | |
583 | temp = target; | |
584 | ||
585 | xop0 = op0; | |
586 | xop1 = op1; | |
587 | wxop = wide_op; | |
588 | ||
589 | /* In case the insn wants input operands in modes different from | |
590 | those of the actual operands, convert the operands. It would | |
591 | seem that we don't need to convert CONST_INTs, but we do, so | |
592 | that they're properly zero-extended, sign-extended or truncated | |
593 | for their mode. */ | |
594 | ||
595 | if (GET_MODE (op0) != xmode0 && xmode0 != VOIDmode) | |
596 | xop0 = convert_modes (xmode0, | |
597 | GET_MODE (op0) != VOIDmode | |
598 | ? GET_MODE (op0) | |
599 | : tmode0, | |
600 | xop0, unsignedp); | |
601 | ||
602 | if (op1) | |
603 | if (GET_MODE (op1) != xmode1 && xmode1 != VOIDmode) | |
604 | xop1 = convert_modes (xmode1, | |
605 | GET_MODE (op1) != VOIDmode | |
606 | ? GET_MODE (op1) | |
607 | : tmode1, | |
608 | xop1, unsignedp); | |
609 | ||
610 | if (wide_op) | |
611 | if (GET_MODE (wide_op) != wxmode && wxmode != VOIDmode) | |
612 | wxop = convert_modes (wxmode, | |
613 | GET_MODE (wide_op) != VOIDmode | |
614 | ? GET_MODE (wide_op) | |
615 | : wmode, | |
616 | wxop, unsignedp); | |
617 | ||
618 | /* Now, if insn's predicates don't allow our operands, put them into | |
619 | pseudo regs. */ | |
620 | ||
621 | if (! (*insn_data[icode].operand[1].predicate) (xop0, xmode0) | |
622 | && xmode0 != VOIDmode) | |
623 | xop0 = copy_to_mode_reg (xmode0, xop0); | |
624 | ||
625 | if (op1) | |
626 | { | |
627 | if (! (*insn_data[icode].operand[2].predicate) (xop1, xmode1) | |
628 | && xmode1 != VOIDmode) | |
629 | xop1 = copy_to_mode_reg (xmode1, xop1); | |
630 | ||
631 | if (wide_op) | |
632 | { | |
633 | if (! (*insn_data[icode].operand[3].predicate) (wxop, wxmode) | |
634 | && wxmode != VOIDmode) | |
635 | wxop = copy_to_mode_reg (wxmode, wxop); | |
636 | ||
637 | pat = GEN_FCN (icode) (temp, xop0, xop1, wxop); | |
638 | } | |
639 | else | |
640 | pat = GEN_FCN (icode) (temp, xop0, xop1); | |
641 | } | |
642 | else | |
643 | { | |
644 | if (wide_op) | |
645 | { | |
646 | if (! (*insn_data[icode].operand[2].predicate) (wxop, wxmode) | |
647 | && wxmode != VOIDmode) | |
648 | wxop = copy_to_mode_reg (wxmode, wxop); | |
649 | ||
650 | pat = GEN_FCN (icode) (temp, xop0, wxop); | |
651 | } | |
652 | else | |
653 | pat = GEN_FCN (icode) (temp, xop0); | |
654 | } | |
655 | ||
656 | emit_insn (pat); | |
657 | return temp; | |
658 | } | |
659 | ||
b056d812 | 660 | /* Generate code to perform an operation specified by TERNARY_OPTAB |
661 | on operands OP0, OP1 and OP2, with result having machine-mode MODE. | |
662 | ||
663 | UNSIGNEDP is for the case where we have to widen the operands | |
664 | to perform the operation. It says to use zero-extension. | |
665 | ||
666 | If TARGET is nonzero, the value | |
667 | is generated there, if it is convenient to do so. | |
668 | In all cases an rtx is returned for the locus of the value; | |
669 | this may or may not be TARGET. */ | |
670 | ||
671 | rtx | |
26364c07 | 672 | expand_ternary_op (enum machine_mode mode, optab ternary_optab, rtx op0, |
673 | rtx op1, rtx op2, rtx target, int unsignedp) | |
b056d812 | 674 | { |
99bdde56 | 675 | int icode = (int) optab_handler (ternary_optab, mode)->insn_code; |
b056d812 | 676 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; |
677 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
678 | enum machine_mode mode2 = insn_data[icode].operand[3].mode; | |
679 | rtx temp; | |
680 | rtx pat; | |
681 | rtx xop0 = op0, xop1 = op1, xop2 = op2; | |
682 | ||
99bdde56 | 683 | gcc_assert (optab_handler (ternary_optab, mode)->insn_code |
ce572eff | 684 | != CODE_FOR_nothing); |
b056d812 | 685 | |
ce572eff | 686 | if (!target || !insn_data[icode].operand[0].predicate (target, mode)) |
b056d812 | 687 | temp = gen_reg_rtx (mode); |
688 | else | |
689 | temp = target; | |
690 | ||
691 | /* In case the insn wants input operands in modes different from | |
692 | those of the actual operands, convert the operands. It would | |
693 | seem that we don't need to convert CONST_INTs, but we do, so | |
694 | that they're properly zero-extended, sign-extended or truncated | |
695 | for their mode. */ | |
696 | ||
697 | if (GET_MODE (op0) != mode0 && mode0 != VOIDmode) | |
698 | xop0 = convert_modes (mode0, | |
699 | GET_MODE (op0) != VOIDmode | |
26364c07 | 700 | ? GET_MODE (op0) |
b056d812 | 701 | : mode, |
702 | xop0, unsignedp); | |
703 | ||
704 | if (GET_MODE (op1) != mode1 && mode1 != VOIDmode) | |
705 | xop1 = convert_modes (mode1, | |
706 | GET_MODE (op1) != VOIDmode | |
707 | ? GET_MODE (op1) | |
708 | : mode, | |
709 | xop1, unsignedp); | |
710 | ||
711 | if (GET_MODE (op2) != mode2 && mode2 != VOIDmode) | |
712 | xop2 = convert_modes (mode2, | |
713 | GET_MODE (op2) != VOIDmode | |
714 | ? GET_MODE (op2) | |
715 | : mode, | |
716 | xop2, unsignedp); | |
717 | ||
718 | /* Now, if insn's predicates don't allow our operands, put them into | |
719 | pseudo regs. */ | |
26364c07 | 720 | |
ce572eff | 721 | if (!insn_data[icode].operand[1].predicate (xop0, mode0) |
26364c07 | 722 | && mode0 != VOIDmode) |
b056d812 | 723 | xop0 = copy_to_mode_reg (mode0, xop0); |
26364c07 | 724 | |
ce572eff | 725 | if (!insn_data[icode].operand[2].predicate (xop1, mode1) |
b056d812 | 726 | && mode1 != VOIDmode) |
727 | xop1 = copy_to_mode_reg (mode1, xop1); | |
26364c07 | 728 | |
ce572eff | 729 | if (!insn_data[icode].operand[3].predicate (xop2, mode2) |
b056d812 | 730 | && mode2 != VOIDmode) |
731 | xop2 = copy_to_mode_reg (mode2, xop2); | |
26364c07 | 732 | |
b056d812 | 733 | pat = GEN_FCN (icode) (temp, xop0, xop1, xop2); |
26364c07 | 734 | |
b056d812 | 735 | emit_insn (pat); |
26364c07 | 736 | return temp; |
b056d812 | 737 | } |
738 | ||
739 | ||
c49547c4 | 740 | /* Like expand_binop, but return a constant rtx if the result can be |
741 | calculated at compile time. The arguments and return value are | |
742 | otherwise the same as for expand_binop. */ | |
743 | ||
744 | static rtx | |
745 | simplify_expand_binop (enum machine_mode mode, optab binoptab, | |
746 | rtx op0, rtx op1, rtx target, int unsignedp, | |
747 | enum optab_methods methods) | |
748 | { | |
749 | if (CONSTANT_P (op0) && CONSTANT_P (op1)) | |
5f768987 | 750 | { |
751 | rtx x = simplify_binary_operation (binoptab->code, mode, op0, op1); | |
752 | ||
753 | if (x) | |
754 | return x; | |
755 | } | |
756 | ||
757 | return expand_binop (mode, binoptab, op0, op1, target, unsignedp, methods); | |
c49547c4 | 758 | } |
759 | ||
760 | /* Like simplify_expand_binop, but always put the result in TARGET. | |
761 | Return true if the expansion succeeded. */ | |
762 | ||
05d18e8b | 763 | bool |
c49547c4 | 764 | force_expand_binop (enum machine_mode mode, optab binoptab, |
765 | rtx op0, rtx op1, rtx target, int unsignedp, | |
766 | enum optab_methods methods) | |
767 | { | |
768 | rtx x = simplify_expand_binop (mode, binoptab, op0, op1, | |
769 | target, unsignedp, methods); | |
770 | if (x == 0) | |
771 | return false; | |
772 | if (x != target) | |
773 | emit_move_insn (target, x); | |
774 | return true; | |
775 | } | |
776 | ||
925c62d4 | 777 | /* Generate insns for VEC_LSHIFT_EXPR, VEC_RSHIFT_EXPR. */ |
778 | ||
779 | rtx | |
780 | expand_vec_shift_expr (tree vec_shift_expr, rtx target) | |
781 | { | |
782 | enum insn_code icode; | |
783 | rtx rtx_op1, rtx_op2; | |
784 | enum machine_mode mode1; | |
785 | enum machine_mode mode2; | |
786 | enum machine_mode mode = TYPE_MODE (TREE_TYPE (vec_shift_expr)); | |
787 | tree vec_oprnd = TREE_OPERAND (vec_shift_expr, 0); | |
788 | tree shift_oprnd = TREE_OPERAND (vec_shift_expr, 1); | |
789 | optab shift_optab; | |
790 | rtx pat; | |
791 | ||
792 | switch (TREE_CODE (vec_shift_expr)) | |
793 | { | |
794 | case VEC_RSHIFT_EXPR: | |
795 | shift_optab = vec_shr_optab; | |
796 | break; | |
797 | case VEC_LSHIFT_EXPR: | |
798 | shift_optab = vec_shl_optab; | |
799 | break; | |
800 | default: | |
801 | gcc_unreachable (); | |
802 | } | |
803 | ||
8458f4ca | 804 | icode = optab_handler (shift_optab, mode)->insn_code; |
925c62d4 | 805 | gcc_assert (icode != CODE_FOR_nothing); |
806 | ||
807 | mode1 = insn_data[icode].operand[1].mode; | |
808 | mode2 = insn_data[icode].operand[2].mode; | |
809 | ||
1db6d067 | 810 | rtx_op1 = expand_normal (vec_oprnd); |
925c62d4 | 811 | if (!(*insn_data[icode].operand[1].predicate) (rtx_op1, mode1) |
812 | && mode1 != VOIDmode) | |
813 | rtx_op1 = force_reg (mode1, rtx_op1); | |
814 | ||
1db6d067 | 815 | rtx_op2 = expand_normal (shift_oprnd); |
925c62d4 | 816 | if (!(*insn_data[icode].operand[2].predicate) (rtx_op2, mode2) |
817 | && mode2 != VOIDmode) | |
818 | rtx_op2 = force_reg (mode2, rtx_op2); | |
819 | ||
820 | if (!target | |
821 | || ! (*insn_data[icode].operand[0].predicate) (target, mode)) | |
822 | target = gen_reg_rtx (mode); | |
823 | ||
824 | /* Emit instruction */ | |
825 | pat = GEN_FCN (icode) (target, rtx_op1, rtx_op2); | |
826 | gcc_assert (pat); | |
827 | emit_insn (pat); | |
828 | ||
829 | return target; | |
830 | } | |
831 | ||
c49547c4 | 832 | /* This subroutine of expand_doubleword_shift handles the cases in which |
833 | the effective shift value is >= BITS_PER_WORD. The arguments and return | |
834 | value are the same as for the parent routine, except that SUPERWORD_OP1 | |
835 | is the shift count to use when shifting OUTOF_INPUT into INTO_TARGET. | |
836 | INTO_TARGET may be null if the caller has decided to calculate it. */ | |
837 | ||
838 | static bool | |
839 | expand_superword_shift (optab binoptab, rtx outof_input, rtx superword_op1, | |
840 | rtx outof_target, rtx into_target, | |
841 | int unsignedp, enum optab_methods methods) | |
842 | { | |
843 | if (into_target != 0) | |
844 | if (!force_expand_binop (word_mode, binoptab, outof_input, superword_op1, | |
845 | into_target, unsignedp, methods)) | |
846 | return false; | |
847 | ||
848 | if (outof_target != 0) | |
849 | { | |
850 | /* For a signed right shift, we must fill OUTOF_TARGET with copies | |
851 | of the sign bit, otherwise we must fill it with zeros. */ | |
852 | if (binoptab != ashr_optab) | |
853 | emit_move_insn (outof_target, CONST0_RTX (word_mode)); | |
854 | else | |
855 | if (!force_expand_binop (word_mode, binoptab, | |
856 | outof_input, GEN_INT (BITS_PER_WORD - 1), | |
857 | outof_target, unsignedp, methods)) | |
858 | return false; | |
859 | } | |
860 | return true; | |
861 | } | |
862 | ||
863 | /* This subroutine of expand_doubleword_shift handles the cases in which | |
864 | the effective shift value is < BITS_PER_WORD. The arguments and return | |
865 | value are the same as for the parent routine. */ | |
866 | ||
867 | static bool | |
868 | expand_subword_shift (enum machine_mode op1_mode, optab binoptab, | |
869 | rtx outof_input, rtx into_input, rtx op1, | |
870 | rtx outof_target, rtx into_target, | |
871 | int unsignedp, enum optab_methods methods, | |
872 | unsigned HOST_WIDE_INT shift_mask) | |
873 | { | |
874 | optab reverse_unsigned_shift, unsigned_shift; | |
875 | rtx tmp, carries; | |
876 | ||
877 | reverse_unsigned_shift = (binoptab == ashl_optab ? lshr_optab : ashl_optab); | |
878 | unsigned_shift = (binoptab == ashl_optab ? ashl_optab : lshr_optab); | |
879 | ||
880 | /* The low OP1 bits of INTO_TARGET come from the high bits of OUTOF_INPUT. | |
881 | We therefore need to shift OUTOF_INPUT by (BITS_PER_WORD - OP1) bits in | |
882 | the opposite direction to BINOPTAB. */ | |
883 | if (CONSTANT_P (op1) || shift_mask >= BITS_PER_WORD) | |
884 | { | |
885 | carries = outof_input; | |
886 | tmp = immed_double_const (BITS_PER_WORD, 0, op1_mode); | |
887 | tmp = simplify_expand_binop (op1_mode, sub_optab, tmp, op1, | |
888 | 0, true, methods); | |
889 | } | |
890 | else | |
891 | { | |
892 | /* We must avoid shifting by BITS_PER_WORD bits since that is either | |
893 | the same as a zero shift (if shift_mask == BITS_PER_WORD - 1) or | |
c26a6416 | 894 | has unknown behavior. Do a single shift first, then shift by the |
c49547c4 | 895 | remainder. It's OK to use ~OP1 as the remainder if shift counts |
896 | are truncated to the mode size. */ | |
897 | carries = expand_binop (word_mode, reverse_unsigned_shift, | |
898 | outof_input, const1_rtx, 0, unsignedp, methods); | |
899 | if (shift_mask == BITS_PER_WORD - 1) | |
900 | { | |
901 | tmp = immed_double_const (-1, -1, op1_mode); | |
902 | tmp = simplify_expand_binop (op1_mode, xor_optab, op1, tmp, | |
903 | 0, true, methods); | |
904 | } | |
905 | else | |
906 | { | |
907 | tmp = immed_double_const (BITS_PER_WORD - 1, 0, op1_mode); | |
908 | tmp = simplify_expand_binop (op1_mode, sub_optab, tmp, op1, | |
909 | 0, true, methods); | |
910 | } | |
911 | } | |
912 | if (tmp == 0 || carries == 0) | |
913 | return false; | |
914 | carries = expand_binop (word_mode, reverse_unsigned_shift, | |
915 | carries, tmp, 0, unsignedp, methods); | |
916 | if (carries == 0) | |
917 | return false; | |
918 | ||
919 | /* Shift INTO_INPUT logically by OP1. This is the last use of INTO_INPUT | |
920 | so the result can go directly into INTO_TARGET if convenient. */ | |
921 | tmp = expand_binop (word_mode, unsigned_shift, into_input, op1, | |
922 | into_target, unsignedp, methods); | |
923 | if (tmp == 0) | |
924 | return false; | |
925 | ||
926 | /* Now OR in the bits carried over from OUTOF_INPUT. */ | |
927 | if (!force_expand_binop (word_mode, ior_optab, tmp, carries, | |
928 | into_target, unsignedp, methods)) | |
929 | return false; | |
930 | ||
931 | /* Use a standard word_mode shift for the out-of half. */ | |
932 | if (outof_target != 0) | |
933 | if (!force_expand_binop (word_mode, binoptab, outof_input, op1, | |
934 | outof_target, unsignedp, methods)) | |
935 | return false; | |
936 | ||
937 | return true; | |
938 | } | |
939 | ||
940 | ||
941 | #ifdef HAVE_conditional_move | |
942 | /* Try implementing expand_doubleword_shift using conditional moves. | |
943 | The shift is by < BITS_PER_WORD if (CMP_CODE CMP1 CMP2) is true, | |
944 | otherwise it is by >= BITS_PER_WORD. SUBWORD_OP1 and SUPERWORD_OP1 | |
945 | are the shift counts to use in the former and latter case. All other | |
946 | arguments are the same as the parent routine. */ | |
947 | ||
948 | static bool | |
949 | expand_doubleword_shift_condmove (enum machine_mode op1_mode, optab binoptab, | |
950 | enum rtx_code cmp_code, rtx cmp1, rtx cmp2, | |
951 | rtx outof_input, rtx into_input, | |
952 | rtx subword_op1, rtx superword_op1, | |
953 | rtx outof_target, rtx into_target, | |
954 | int unsignedp, enum optab_methods methods, | |
955 | unsigned HOST_WIDE_INT shift_mask) | |
956 | { | |
957 | rtx outof_superword, into_superword; | |
958 | ||
959 | /* Put the superword version of the output into OUTOF_SUPERWORD and | |
960 | INTO_SUPERWORD. */ | |
961 | outof_superword = outof_target != 0 ? gen_reg_rtx (word_mode) : 0; | |
962 | if (outof_target != 0 && subword_op1 == superword_op1) | |
963 | { | |
964 | /* The value INTO_TARGET >> SUBWORD_OP1, which we later store in | |
965 | OUTOF_TARGET, is the same as the value of INTO_SUPERWORD. */ | |
966 | into_superword = outof_target; | |
967 | if (!expand_superword_shift (binoptab, outof_input, superword_op1, | |
968 | outof_superword, 0, unsignedp, methods)) | |
969 | return false; | |
970 | } | |
971 | else | |
972 | { | |
973 | into_superword = gen_reg_rtx (word_mode); | |
974 | if (!expand_superword_shift (binoptab, outof_input, superword_op1, | |
975 | outof_superword, into_superword, | |
976 | unsignedp, methods)) | |
977 | return false; | |
978 | } | |
83e2a11b | 979 | |
c49547c4 | 980 | /* Put the subword version directly in OUTOF_TARGET and INTO_TARGET. */ |
981 | if (!expand_subword_shift (op1_mode, binoptab, | |
982 | outof_input, into_input, subword_op1, | |
983 | outof_target, into_target, | |
984 | unsignedp, methods, shift_mask)) | |
985 | return false; | |
986 | ||
987 | /* Select between them. Do the INTO half first because INTO_SUPERWORD | |
988 | might be the current value of OUTOF_TARGET. */ | |
989 | if (!emit_conditional_move (into_target, cmp_code, cmp1, cmp2, op1_mode, | |
990 | into_target, into_superword, word_mode, false)) | |
991 | return false; | |
992 | ||
993 | if (outof_target != 0) | |
994 | if (!emit_conditional_move (outof_target, cmp_code, cmp1, cmp2, op1_mode, | |
995 | outof_target, outof_superword, | |
996 | word_mode, false)) | |
997 | return false; | |
998 | ||
999 | return true; | |
1000 | } | |
1001 | #endif | |
1002 | ||
1003 | /* Expand a doubleword shift (ashl, ashr or lshr) using word-mode shifts. | |
1004 | OUTOF_INPUT and INTO_INPUT are the two word-sized halves of the first | |
1005 | input operand; the shift moves bits in the direction OUTOF_INPUT-> | |
1006 | INTO_TARGET. OUTOF_TARGET and INTO_TARGET are the equivalent words | |
1007 | of the target. OP1 is the shift count and OP1_MODE is its mode. | |
1008 | If OP1 is constant, it will have been truncated as appropriate | |
1009 | and is known to be nonzero. | |
1010 | ||
1011 | If SHIFT_MASK is zero, the result of word shifts is undefined when the | |
1012 | shift count is outside the range [0, BITS_PER_WORD). This routine must | |
1013 | avoid generating such shifts for OP1s in the range [0, BITS_PER_WORD * 2). | |
1014 | ||
1015 | If SHIFT_MASK is nonzero, all word-mode shift counts are effectively | |
1016 | masked by it and shifts in the range [BITS_PER_WORD, SHIFT_MASK) will | |
1017 | fill with zeros or sign bits as appropriate. | |
1018 | ||
91275768 | 1019 | If SHIFT_MASK is BITS_PER_WORD - 1, this routine will synthesize |
c49547c4 | 1020 | a doubleword shift whose equivalent mask is BITS_PER_WORD * 2 - 1. |
1021 | Doing this preserves semantics required by SHIFT_COUNT_TRUNCATED. | |
1022 | In all other cases, shifts by values outside [0, BITS_PER_UNIT * 2) | |
1023 | are undefined. | |
1024 | ||
1025 | BINOPTAB, UNSIGNEDP and METHODS are as for expand_binop. This function | |
1026 | may not use INTO_INPUT after modifying INTO_TARGET, and similarly for | |
1027 | OUTOF_INPUT and OUTOF_TARGET. OUTOF_TARGET can be null if the parent | |
1028 | function wants to calculate it itself. | |
1029 | ||
1030 | Return true if the shift could be successfully synthesized. */ | |
1031 | ||
1032 | static bool | |
1033 | expand_doubleword_shift (enum machine_mode op1_mode, optab binoptab, | |
1034 | rtx outof_input, rtx into_input, rtx op1, | |
1035 | rtx outof_target, rtx into_target, | |
1036 | int unsignedp, enum optab_methods methods, | |
1037 | unsigned HOST_WIDE_INT shift_mask) | |
1038 | { | |
1039 | rtx superword_op1, tmp, cmp1, cmp2; | |
1040 | rtx subword_label, done_label; | |
1041 | enum rtx_code cmp_code; | |
1042 | ||
1043 | /* See if word-mode shifts by BITS_PER_WORD...BITS_PER_WORD * 2 - 1 will | |
1044 | fill the result with sign or zero bits as appropriate. If so, the value | |
1045 | of OUTOF_TARGET will always be (SHIFT OUTOF_INPUT OP1). Recursively call | |
1046 | this routine to calculate INTO_TARGET (which depends on both OUTOF_INPUT | |
1047 | and INTO_INPUT), then emit code to set up OUTOF_TARGET. | |
1048 | ||
1049 | This isn't worthwhile for constant shifts since the optimizers will | |
1050 | cope better with in-range shift counts. */ | |
1051 | if (shift_mask >= BITS_PER_WORD | |
1052 | && outof_target != 0 | |
1053 | && !CONSTANT_P (op1)) | |
1054 | { | |
1055 | if (!expand_doubleword_shift (op1_mode, binoptab, | |
1056 | outof_input, into_input, op1, | |
1057 | 0, into_target, | |
1058 | unsignedp, methods, shift_mask)) | |
1059 | return false; | |
1060 | if (!force_expand_binop (word_mode, binoptab, outof_input, op1, | |
1061 | outof_target, unsignedp, methods)) | |
1062 | return false; | |
1063 | return true; | |
1064 | } | |
1065 | ||
1066 | /* Set CMP_CODE, CMP1 and CMP2 so that the rtx (CMP_CODE CMP1 CMP2) | |
1067 | is true when the effective shift value is less than BITS_PER_WORD. | |
1068 | Set SUPERWORD_OP1 to the shift count that should be used to shift | |
1069 | OUTOF_INPUT into INTO_TARGET when the condition is false. */ | |
1070 | tmp = immed_double_const (BITS_PER_WORD, 0, op1_mode); | |
1071 | if (!CONSTANT_P (op1) && shift_mask == BITS_PER_WORD - 1) | |
1072 | { | |
1073 | /* Set CMP1 to OP1 & BITS_PER_WORD. The result is zero iff OP1 | |
1074 | is a subword shift count. */ | |
1075 | cmp1 = simplify_expand_binop (op1_mode, and_optab, op1, tmp, | |
1076 | 0, true, methods); | |
1077 | cmp2 = CONST0_RTX (op1_mode); | |
1078 | cmp_code = EQ; | |
1079 | superword_op1 = op1; | |
1080 | } | |
1081 | else | |
1082 | { | |
1083 | /* Set CMP1 to OP1 - BITS_PER_WORD. */ | |
1084 | cmp1 = simplify_expand_binop (op1_mode, sub_optab, op1, tmp, | |
1085 | 0, true, methods); | |
1086 | cmp2 = CONST0_RTX (op1_mode); | |
1087 | cmp_code = LT; | |
1088 | superword_op1 = cmp1; | |
1089 | } | |
1090 | if (cmp1 == 0) | |
1091 | return false; | |
1092 | ||
1093 | /* If we can compute the condition at compile time, pick the | |
1094 | appropriate subroutine. */ | |
1095 | tmp = simplify_relational_operation (cmp_code, SImode, op1_mode, cmp1, cmp2); | |
1096 | if (tmp != 0 && GET_CODE (tmp) == CONST_INT) | |
1097 | { | |
1098 | if (tmp == const0_rtx) | |
1099 | return expand_superword_shift (binoptab, outof_input, superword_op1, | |
1100 | outof_target, into_target, | |
1101 | unsignedp, methods); | |
1102 | else | |
1103 | return expand_subword_shift (op1_mode, binoptab, | |
1104 | outof_input, into_input, op1, | |
1105 | outof_target, into_target, | |
1106 | unsignedp, methods, shift_mask); | |
1107 | } | |
1108 | ||
1109 | #ifdef HAVE_conditional_move | |
1110 | /* Try using conditional moves to generate straight-line code. */ | |
1111 | { | |
1112 | rtx start = get_last_insn (); | |
1113 | if (expand_doubleword_shift_condmove (op1_mode, binoptab, | |
1114 | cmp_code, cmp1, cmp2, | |
1115 | outof_input, into_input, | |
1116 | op1, superword_op1, | |
1117 | outof_target, into_target, | |
1118 | unsignedp, methods, shift_mask)) | |
1119 | return true; | |
1120 | delete_insns_since (start); | |
1121 | } | |
1122 | #endif | |
1123 | ||
1124 | /* As a last resort, use branches to select the correct alternative. */ | |
1125 | subword_label = gen_label_rtx (); | |
1126 | done_label = gen_label_rtx (); | |
1127 | ||
ed4439b1 | 1128 | NO_DEFER_POP; |
c49547c4 | 1129 | do_compare_rtx_and_jump (cmp1, cmp2, cmp_code, false, op1_mode, |
1130 | 0, 0, subword_label); | |
ed4439b1 | 1131 | OK_DEFER_POP; |
c49547c4 | 1132 | |
1133 | if (!expand_superword_shift (binoptab, outof_input, superword_op1, | |
1134 | outof_target, into_target, | |
1135 | unsignedp, methods)) | |
1136 | return false; | |
1137 | ||
1138 | emit_jump_insn (gen_jump (done_label)); | |
1139 | emit_barrier (); | |
1140 | emit_label (subword_label); | |
1141 | ||
1142 | if (!expand_subword_shift (op1_mode, binoptab, | |
1143 | outof_input, into_input, op1, | |
1144 | outof_target, into_target, | |
1145 | unsignedp, methods, shift_mask)) | |
1146 | return false; | |
1147 | ||
1148 | emit_label (done_label); | |
1149 | return true; | |
1150 | } | |
27bc6aee | 1151 | \f |
54eb7a38 | 1152 | /* Subroutine of expand_binop. Perform a double word multiplication of |
1153 | operands OP0 and OP1 both of mode MODE, which is exactly twice as wide | |
1154 | as the target's word_mode. This function return NULL_RTX if anything | |
1155 | goes wrong, in which case it may have already emitted instructions | |
1156 | which need to be deleted. | |
1157 | ||
1158 | If we want to multiply two two-word values and have normal and widening | |
1159 | multiplies of single-word values, we can do this with three smaller | |
e29831db | 1160 | multiplications. |
54eb7a38 | 1161 | |
1162 | The multiplication proceeds as follows: | |
1163 | _______________________ | |
1164 | [__op0_high_|__op0_low__] | |
1165 | _______________________ | |
1166 | * [__op1_high_|__op1_low__] | |
1167 | _______________________________________________ | |
1168 | _______________________ | |
1169 | (1) [__op0_low__*__op1_low__] | |
1170 | _______________________ | |
1171 | (2a) [__op0_low__*__op1_high_] | |
1172 | _______________________ | |
1173 | (2b) [__op0_high_*__op1_low__] | |
1174 | _______________________ | |
1175 | (3) [__op0_high_*__op1_high_] | |
1176 | ||
1177 | ||
1178 | This gives a 4-word result. Since we are only interested in the | |
1179 | lower 2 words, partial result (3) and the upper words of (2a) and | |
1180 | (2b) don't need to be calculated. Hence (2a) and (2b) can be | |
1181 | calculated using non-widening multiplication. | |
1182 | ||
1183 | (1), however, needs to be calculated with an unsigned widening | |
1184 | multiplication. If this operation is not directly supported we | |
1185 | try using a signed widening multiplication and adjust the result. | |
1186 | This adjustment works as follows: | |
1187 | ||
1188 | If both operands are positive then no adjustment is needed. | |
1189 | ||
1190 | If the operands have different signs, for example op0_low < 0 and | |
1191 | op1_low >= 0, the instruction treats the most significant bit of | |
1192 | op0_low as a sign bit instead of a bit with significance | |
1193 | 2**(BITS_PER_WORD-1), i.e. the instruction multiplies op1_low | |
1194 | with 2**BITS_PER_WORD - op0_low, and two's complements the | |
1195 | result. Conclusion: We need to add op1_low * 2**BITS_PER_WORD to | |
1196 | the result. | |
1197 | ||
1198 | Similarly, if both operands are negative, we need to add | |
1199 | (op0_low + op1_low) * 2**BITS_PER_WORD. | |
1200 | ||
1201 | We use a trick to adjust quickly. We logically shift op0_low right | |
1202 | (op1_low) BITS_PER_WORD-1 steps to get 0 or 1, and add this to | |
1203 | op0_high (op1_high) before it is used to calculate 2b (2a). If no | |
1204 | logical shift exists, we do an arithmetic right shift and subtract | |
1205 | the 0 or -1. */ | |
1206 | ||
1207 | static rtx | |
1208 | expand_doubleword_mult (enum machine_mode mode, rtx op0, rtx op1, rtx target, | |
1209 | bool umulp, enum optab_methods methods) | |
1210 | { | |
1211 | int low = (WORDS_BIG_ENDIAN ? 1 : 0); | |
1212 | int high = (WORDS_BIG_ENDIAN ? 0 : 1); | |
1213 | rtx wordm1 = umulp ? NULL_RTX : GEN_INT (BITS_PER_WORD - 1); | |
1214 | rtx product, adjust, product_high, temp; | |
1215 | ||
1216 | rtx op0_high = operand_subword_force (op0, high, mode); | |
1217 | rtx op0_low = operand_subword_force (op0, low, mode); | |
1218 | rtx op1_high = operand_subword_force (op1, high, mode); | |
1219 | rtx op1_low = operand_subword_force (op1, low, mode); | |
1220 | ||
1221 | /* If we're using an unsigned multiply to directly compute the product | |
1222 | of the low-order words of the operands and perform any required | |
1223 | adjustments of the operands, we begin by trying two more multiplications | |
1224 | and then computing the appropriate sum. | |
1225 | ||
1226 | We have checked above that the required addition is provided. | |
1227 | Full-word addition will normally always succeed, especially if | |
1228 | it is provided at all, so we don't worry about its failure. The | |
1229 | multiplication may well fail, however, so we do handle that. */ | |
1230 | ||
1231 | if (!umulp) | |
1232 | { | |
1233 | /* ??? This could be done with emit_store_flag where available. */ | |
1234 | temp = expand_binop (word_mode, lshr_optab, op0_low, wordm1, | |
1235 | NULL_RTX, 1, methods); | |
1236 | if (temp) | |
1237 | op0_high = expand_binop (word_mode, add_optab, op0_high, temp, | |
29a1d14b | 1238 | NULL_RTX, 0, OPTAB_DIRECT); |
54eb7a38 | 1239 | else |
1240 | { | |
1241 | temp = expand_binop (word_mode, ashr_optab, op0_low, wordm1, | |
1242 | NULL_RTX, 0, methods); | |
1243 | if (!temp) | |
1244 | return NULL_RTX; | |
1245 | op0_high = expand_binop (word_mode, sub_optab, op0_high, temp, | |
29a1d14b | 1246 | NULL_RTX, 0, OPTAB_DIRECT); |
54eb7a38 | 1247 | } |
1248 | ||
1249 | if (!op0_high) | |
1250 | return NULL_RTX; | |
1251 | } | |
1252 | ||
1253 | adjust = expand_binop (word_mode, smul_optab, op0_high, op1_low, | |
1254 | NULL_RTX, 0, OPTAB_DIRECT); | |
1255 | if (!adjust) | |
1256 | return NULL_RTX; | |
1257 | ||
1258 | /* OP0_HIGH should now be dead. */ | |
1259 | ||
1260 | if (!umulp) | |
1261 | { | |
1262 | /* ??? This could be done with emit_store_flag where available. */ | |
1263 | temp = expand_binop (word_mode, lshr_optab, op1_low, wordm1, | |
1264 | NULL_RTX, 1, methods); | |
1265 | if (temp) | |
1266 | op1_high = expand_binop (word_mode, add_optab, op1_high, temp, | |
29a1d14b | 1267 | NULL_RTX, 0, OPTAB_DIRECT); |
54eb7a38 | 1268 | else |
1269 | { | |
1270 | temp = expand_binop (word_mode, ashr_optab, op1_low, wordm1, | |
1271 | NULL_RTX, 0, methods); | |
1272 | if (!temp) | |
1273 | return NULL_RTX; | |
1274 | op1_high = expand_binop (word_mode, sub_optab, op1_high, temp, | |
29a1d14b | 1275 | NULL_RTX, 0, OPTAB_DIRECT); |
54eb7a38 | 1276 | } |
1277 | ||
1278 | if (!op1_high) | |
1279 | return NULL_RTX; | |
1280 | } | |
1281 | ||
1282 | temp = expand_binop (word_mode, smul_optab, op1_high, op0_low, | |
1283 | NULL_RTX, 0, OPTAB_DIRECT); | |
1284 | if (!temp) | |
1285 | return NULL_RTX; | |
1286 | ||
1287 | /* OP1_HIGH should now be dead. */ | |
1288 | ||
1289 | adjust = expand_binop (word_mode, add_optab, adjust, temp, | |
1290 | adjust, 0, OPTAB_DIRECT); | |
1291 | ||
1292 | if (target && !REG_P (target)) | |
1293 | target = NULL_RTX; | |
1294 | ||
1295 | if (umulp) | |
1296 | product = expand_binop (mode, umul_widen_optab, op0_low, op1_low, | |
1297 | target, 1, OPTAB_DIRECT); | |
1298 | else | |
1299 | product = expand_binop (mode, smul_widen_optab, op0_low, op1_low, | |
1300 | target, 1, OPTAB_DIRECT); | |
1301 | ||
1302 | if (!product) | |
1303 | return NULL_RTX; | |
1304 | ||
1305 | product_high = operand_subword (product, high, 1, mode); | |
1306 | adjust = expand_binop (word_mode, add_optab, product_high, adjust, | |
1307 | REG_P (product_high) ? product_high : adjust, | |
1308 | 0, OPTAB_DIRECT); | |
1309 | emit_move_insn (product_high, adjust); | |
1310 | return product; | |
1311 | } | |
1312 | \f | |
ad99e708 | 1313 | /* Wrapper around expand_binop which takes an rtx code to specify |
1314 | the operation to perform, not an optab pointer. All other | |
1315 | arguments are the same. */ | |
1316 | rtx | |
3ad4992f | 1317 | expand_simple_binop (enum machine_mode mode, enum rtx_code code, rtx op0, |
1318 | rtx op1, rtx target, int unsignedp, | |
1319 | enum optab_methods methods) | |
ad99e708 | 1320 | { |
2fd3f4b5 | 1321 | optab binop = code_to_optab[(int) code]; |
ce572eff | 1322 | gcc_assert (binop); |
ad99e708 | 1323 | |
1324 | return expand_binop (mode, binop, op0, op1, target, unsignedp, methods); | |
1325 | } | |
1326 | ||
70c2f3ea | 1327 | /* Return whether OP0 and OP1 should be swapped when expanding a commutative |
1328 | binop. Order them according to commutative_operand_precedence and, if | |
1329 | possible, try to put TARGET or a pseudo first. */ | |
1330 | static bool | |
1331 | swap_commutative_operands_with_target (rtx target, rtx op0, rtx op1) | |
1332 | { | |
1333 | int op0_prec = commutative_operand_precedence (op0); | |
1334 | int op1_prec = commutative_operand_precedence (op1); | |
1335 | ||
1336 | if (op0_prec < op1_prec) | |
1337 | return true; | |
1338 | ||
1339 | if (op0_prec > op1_prec) | |
1340 | return false; | |
1341 | ||
1342 | /* With equal precedence, both orders are ok, but it is better if the | |
1343 | first operand is TARGET, or if both TARGET and OP0 are pseudos. */ | |
1344 | if (target == 0 || REG_P (target)) | |
1345 | return (REG_P (op1) && !REG_P (op0)) || target == op1; | |
1346 | else | |
1347 | return rtx_equal_p (op1, target); | |
1348 | } | |
1349 | ||
4f4473ff | 1350 | /* Return true if BINOPTAB implements a shift operation. */ |
1351 | ||
1352 | static bool | |
1353 | shift_optab_p (optab binoptab) | |
1354 | { | |
1355 | switch (binoptab->code) | |
1356 | { | |
1357 | case ASHIFT: | |
68a556d6 | 1358 | case SS_ASHIFT: |
1359 | case US_ASHIFT: | |
4f4473ff | 1360 | case ASHIFTRT: |
1361 | case LSHIFTRT: | |
1362 | case ROTATE: | |
1363 | case ROTATERT: | |
1364 | return true; | |
1365 | ||
1366 | default: | |
1367 | return false; | |
1368 | } | |
1369 | } | |
1370 | ||
becfaa62 | 1371 | /* Return true if BINOPTAB implements a commutative binary operation. */ |
4f4473ff | 1372 | |
1373 | static bool | |
1374 | commutative_optab_p (optab binoptab) | |
1375 | { | |
1376 | return (GET_RTX_CLASS (binoptab->code) == RTX_COMM_ARITH | |
1377 | || binoptab == smul_widen_optab | |
1378 | || binoptab == umul_widen_optab | |
1379 | || binoptab == smul_highpart_optab | |
1380 | || binoptab == umul_highpart_optab); | |
1381 | } | |
1382 | ||
1383 | /* X is to be used in mode MODE as an operand to BINOPTAB. If we're | |
1384 | optimizing, and if the operand is a constant that costs more than | |
1385 | 1 instruction, force the constant into a register and return that | |
1386 | register. Return X otherwise. UNSIGNEDP says whether X is unsigned. */ | |
1387 | ||
1388 | static rtx | |
1389 | avoid_expensive_constant (enum machine_mode mode, optab binoptab, | |
1390 | rtx x, bool unsignedp) | |
1391 | { | |
be738b41 | 1392 | if (mode != VOIDmode |
1393 | && optimize | |
4f4473ff | 1394 | && CONSTANT_P (x) |
f529eb25 | 1395 | && rtx_cost (x, binoptab->code, optimize_insn_for_speed_p ()) |
1396 | > COSTS_N_INSNS (1)) | |
4f4473ff | 1397 | { |
81747544 | 1398 | if (GET_CODE (x) == CONST_INT) |
1399 | { | |
1400 | HOST_WIDE_INT intval = trunc_int_for_mode (INTVAL (x), mode); | |
1401 | if (intval != INTVAL (x)) | |
1402 | x = GEN_INT (intval); | |
1403 | } | |
1404 | else | |
4f4473ff | 1405 | x = convert_modes (mode, VOIDmode, x, unsignedp); |
1406 | x = force_reg (mode, x); | |
1407 | } | |
1408 | return x; | |
1409 | } | |
70c2f3ea | 1410 | |
122a6978 | 1411 | /* Helper function for expand_binop: handle the case where there |
1412 | is an insn that directly implements the indicated operation. | |
1413 | Returns null if this is not possible. */ | |
1414 | static rtx | |
1415 | expand_binop_directly (enum machine_mode mode, optab binoptab, | |
1416 | rtx op0, rtx op1, | |
1417 | rtx target, int unsignedp, enum optab_methods methods, | |
4f4473ff | 1418 | rtx last) |
122a6978 | 1419 | { |
99bdde56 | 1420 | int icode = (int) optab_handler (binoptab, mode)->insn_code; |
122a6978 | 1421 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; |
1422 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
1423 | enum machine_mode tmp_mode; | |
4f4473ff | 1424 | bool commutative_p; |
122a6978 | 1425 | rtx pat; |
1426 | rtx xop0 = op0, xop1 = op1; | |
1427 | rtx temp; | |
4f4473ff | 1428 | rtx swap; |
122a6978 | 1429 | |
1430 | if (target) | |
1431 | temp = target; | |
1432 | else | |
1433 | temp = gen_reg_rtx (mode); | |
4f4473ff | 1434 | |
122a6978 | 1435 | /* If it is a commutative operator and the modes would match |
1436 | if we would swap the operands, we can save the conversions. */ | |
4f4473ff | 1437 | commutative_p = commutative_optab_p (binoptab); |
1438 | if (commutative_p | |
1439 | && GET_MODE (xop0) != mode0 && GET_MODE (xop1) != mode1 | |
1440 | && GET_MODE (xop0) == mode1 && GET_MODE (xop1) == mode1) | |
122a6978 | 1441 | { |
4f4473ff | 1442 | swap = xop0; |
1443 | xop0 = xop1; | |
1444 | xop1 = swap; | |
122a6978 | 1445 | } |
1446 | ||
4f4473ff | 1447 | /* If we are optimizing, force expensive constants into a register. */ |
1448 | xop0 = avoid_expensive_constant (mode0, binoptab, xop0, unsignedp); | |
1449 | if (!shift_optab_p (binoptab)) | |
1450 | xop1 = avoid_expensive_constant (mode1, binoptab, xop1, unsignedp); | |
1451 | ||
122a6978 | 1452 | /* In case the insn wants input operands in modes different from |
1453 | those of the actual operands, convert the operands. It would | |
1454 | seem that we don't need to convert CONST_INTs, but we do, so | |
1455 | that they're properly zero-extended, sign-extended or truncated | |
1456 | for their mode. */ | |
1457 | ||
4f4473ff | 1458 | if (GET_MODE (xop0) != mode0 && mode0 != VOIDmode) |
122a6978 | 1459 | xop0 = convert_modes (mode0, |
4f4473ff | 1460 | GET_MODE (xop0) != VOIDmode |
1461 | ? GET_MODE (xop0) | |
122a6978 | 1462 | : mode, |
1463 | xop0, unsignedp); | |
1464 | ||
4f4473ff | 1465 | if (GET_MODE (xop1) != mode1 && mode1 != VOIDmode) |
122a6978 | 1466 | xop1 = convert_modes (mode1, |
4f4473ff | 1467 | GET_MODE (xop1) != VOIDmode |
1468 | ? GET_MODE (xop1) | |
122a6978 | 1469 | : mode, |
1470 | xop1, unsignedp); | |
1471 | ||
4f4473ff | 1472 | /* If operation is commutative, |
1473 | try to make the first operand a register. | |
1474 | Even better, try to make it the same as the target. | |
1475 | Also try to make the last operand a constant. */ | |
1476 | if (commutative_p | |
1477 | && swap_commutative_operands_with_target (target, xop0, xop1)) | |
1478 | { | |
1479 | swap = xop1; | |
1480 | xop1 = xop0; | |
1481 | xop0 = swap; | |
1482 | } | |
1483 | ||
122a6978 | 1484 | /* Now, if insn's predicates don't allow our operands, put them into |
1485 | pseudo regs. */ | |
1486 | ||
1487 | if (!insn_data[icode].operand[1].predicate (xop0, mode0) | |
1488 | && mode0 != VOIDmode) | |
1489 | xop0 = copy_to_mode_reg (mode0, xop0); | |
1490 | ||
1491 | if (!insn_data[icode].operand[2].predicate (xop1, mode1) | |
1492 | && mode1 != VOIDmode) | |
1493 | xop1 = copy_to_mode_reg (mode1, xop1); | |
1494 | ||
1495 | if (binoptab == vec_pack_trunc_optab | |
1496 | || binoptab == vec_pack_usat_optab | |
1497 | || binoptab == vec_pack_ssat_optab | |
1498 | || binoptab == vec_pack_ufix_trunc_optab | |
1499 | || binoptab == vec_pack_sfix_trunc_optab) | |
1500 | { | |
1501 | /* The mode of the result is different then the mode of the | |
1502 | arguments. */ | |
1503 | tmp_mode = insn_data[icode].operand[0].mode; | |
1504 | if (GET_MODE_NUNITS (tmp_mode) != 2 * GET_MODE_NUNITS (mode)) | |
1505 | return 0; | |
1506 | } | |
1507 | else | |
1508 | tmp_mode = mode; | |
1509 | ||
1510 | if (!insn_data[icode].operand[0].predicate (temp, tmp_mode)) | |
1511 | temp = gen_reg_rtx (tmp_mode); | |
1512 | ||
1513 | pat = GEN_FCN (icode) (temp, xop0, xop1); | |
1514 | if (pat) | |
1515 | { | |
1516 | /* If PAT is composed of more than one insn, try to add an appropriate | |
1517 | REG_EQUAL note to it. If we can't because TEMP conflicts with an | |
1518 | operand, call expand_binop again, this time without a target. */ | |
1519 | if (INSN_P (pat) && NEXT_INSN (pat) != NULL_RTX | |
1520 | && ! add_equal_note (pat, temp, binoptab->code, xop0, xop1)) | |
1521 | { | |
1522 | delete_insns_since (last); | |
1523 | return expand_binop (mode, binoptab, op0, op1, NULL_RTX, | |
1524 | unsignedp, methods); | |
1525 | } | |
1526 | ||
1527 | emit_insn (pat); | |
1528 | return temp; | |
1529 | } | |
1530 | ||
1531 | delete_insns_since (last); | |
1532 | return NULL_RTX; | |
1533 | } | |
1534 | ||
1f215c26 | 1535 | /* Generate code to perform an operation specified by BINOPTAB |
1536 | on operands OP0 and OP1, with result having machine-mode MODE. | |
1537 | ||
1538 | UNSIGNEDP is for the case where we have to widen the operands | |
1539 | to perform the operation. It says to use zero-extension. | |
1540 | ||
1541 | If TARGET is nonzero, the value | |
1542 | is generated there, if it is convenient to do so. | |
1543 | In all cases an rtx is returned for the locus of the value; | |
1544 | this may or may not be TARGET. */ | |
1545 | ||
1546 | rtx | |
3ad4992f | 1547 | expand_binop (enum machine_mode mode, optab binoptab, rtx op0, rtx op1, |
1548 | rtx target, int unsignedp, enum optab_methods methods) | |
1f215c26 | 1549 | { |
caf74f46 | 1550 | enum optab_methods next_methods |
1551 | = (methods == OPTAB_LIB || methods == OPTAB_LIB_WIDEN | |
1552 | ? OPTAB_WIDEN : methods); | |
6659485c | 1553 | enum mode_class mclass; |
1f215c26 | 1554 | enum machine_mode wider_mode; |
f36b9f69 | 1555 | rtx libfunc; |
19cb6b50 | 1556 | rtx temp; |
ea35e69c | 1557 | rtx entry_last = get_last_insn (); |
1f215c26 | 1558 | rtx last; |
1559 | ||
6659485c | 1560 | mclass = GET_MODE_CLASS (mode); |
1f215c26 | 1561 | |
c4edd431 | 1562 | /* If subtracting an integer constant, convert this into an addition of |
1563 | the negated constant. */ | |
1564 | ||
1565 | if (binoptab == sub_optab && GET_CODE (op1) == CONST_INT) | |
1566 | { | |
1567 | op1 = negate_rtx (mode, op1); | |
1568 | binoptab = add_optab; | |
1569 | } | |
1570 | ||
1f215c26 | 1571 | /* Record where to delete back to if we backtrack. */ |
1572 | last = get_last_insn (); | |
1573 | ||
1f215c26 | 1574 | /* If we can do it with a three-operand insn, do so. */ |
1575 | ||
1576 | if (methods != OPTAB_MUST_WIDEN | |
99bdde56 | 1577 | && optab_handler (binoptab, mode)->insn_code != CODE_FOR_nothing) |
1f215c26 | 1578 | { |
122a6978 | 1579 | temp = expand_binop_directly (mode, binoptab, op0, op1, target, |
4f4473ff | 1580 | unsignedp, methods, last); |
122a6978 | 1581 | if (temp) |
1582 | return temp; | |
1f215c26 | 1583 | } |
1584 | ||
122a6978 | 1585 | /* If we were trying to rotate, and that didn't work, try rotating |
1586 | the other direction before falling back to shifts and bitwise-or. */ | |
1587 | if (((binoptab == rotl_optab | |
99bdde56 | 1588 | && optab_handler (rotr_optab, mode)->insn_code != CODE_FOR_nothing) |
122a6978 | 1589 | || (binoptab == rotr_optab |
99bdde56 | 1590 | && optab_handler (rotl_optab, mode)->insn_code != CODE_FOR_nothing)) |
6659485c | 1591 | && mclass == MODE_INT) |
cbb0253a | 1592 | { |
122a6978 | 1593 | optab otheroptab = (binoptab == rotl_optab ? rotr_optab : rotl_optab); |
1594 | rtx newop1; | |
cf53f8ba | 1595 | unsigned int bits = GET_MODE_BITSIZE (mode); |
122a6978 | 1596 | |
1597 | if (GET_CODE (op1) == CONST_INT) | |
1598 | newop1 = GEN_INT (bits - INTVAL (op1)); | |
1599 | else if (targetm.shift_truncation_mask (mode) == bits - 1) | |
1600 | newop1 = negate_rtx (mode, op1); | |
1601 | else | |
1602 | newop1 = expand_binop (mode, sub_optab, | |
1603 | GEN_INT (bits), op1, | |
1604 | NULL_RTX, unsignedp, OPTAB_DIRECT); | |
1605 | ||
1606 | temp = expand_binop_directly (mode, otheroptab, op0, newop1, | |
4f4473ff | 1607 | target, unsignedp, methods, last); |
122a6978 | 1608 | if (temp) |
1609 | return temp; | |
cbb0253a | 1610 | } |
1611 | ||
b6d98622 | 1612 | /* If this is a multiply, see if we can do a widening operation that |
1613 | takes operands of this mode and makes a wider mode. */ | |
1614 | ||
ba592904 | 1615 | if (binoptab == smul_optab |
1616 | && GET_MODE_WIDER_MODE (mode) != VOIDmode | |
99bdde56 | 1617 | && ((optab_handler ((unsignedp ? umul_widen_optab : smul_widen_optab), |
1618 | GET_MODE_WIDER_MODE (mode))->insn_code) | |
b6d98622 | 1619 | != CODE_FOR_nothing)) |
1620 | { | |
1621 | temp = expand_binop (GET_MODE_WIDER_MODE (mode), | |
1622 | unsignedp ? umul_widen_optab : smul_widen_optab, | |
b2bc10f7 | 1623 | op0, op1, NULL_RTX, unsignedp, OPTAB_DIRECT); |
b6d98622 | 1624 | |
caf74f46 | 1625 | if (temp != 0) |
1626 | { | |
60a24002 | 1627 | if (GET_MODE_CLASS (mode) == MODE_INT |
1628 | && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode), | |
1629 | GET_MODE_BITSIZE (GET_MODE (temp)))) | |
caf74f46 | 1630 | return gen_lowpart (mode, temp); |
1631 | else | |
1632 | return convert_to_mode (mode, temp, unsignedp); | |
1633 | } | |
b6d98622 | 1634 | } |
1635 | ||
1dd91d55 | 1636 | /* Look for a wider mode of the same class for which we think we |
b6d98622 | 1637 | can open-code the operation. Check for a widening multiply at the |
1638 | wider mode as well. */ | |
1dd91d55 | 1639 | |
6659485c | 1640 | if (CLASS_HAS_WIDER_MODES_P (mclass) |
b0217ae2 | 1641 | && methods != OPTAB_DIRECT && methods != OPTAB_LIB) |
ba592904 | 1642 | for (wider_mode = GET_MODE_WIDER_MODE (mode); |
1643 | wider_mode != VOIDmode; | |
1dd91d55 | 1644 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) |
1645 | { | |
99bdde56 | 1646 | if (optab_handler (binoptab, wider_mode)->insn_code != CODE_FOR_nothing |
b6d98622 | 1647 | || (binoptab == smul_optab |
1648 | && GET_MODE_WIDER_MODE (wider_mode) != VOIDmode | |
99bdde56 | 1649 | && ((optab_handler ((unsignedp ? umul_widen_optab |
1650 | : smul_widen_optab), | |
1651 | GET_MODE_WIDER_MODE (wider_mode))->insn_code) | |
b6d98622 | 1652 | != CODE_FOR_nothing))) |
1dd91d55 | 1653 | { |
1654 | rtx xop0 = op0, xop1 = op1; | |
1655 | int no_extend = 0; | |
1656 | ||
1657 | /* For certain integer operations, we need not actually extend | |
1658 | the narrow operands, as long as we will truncate | |
1e625a2e | 1659 | the results to the same narrowness. */ |
1dd91d55 | 1660 | |
1661 | if ((binoptab == ior_optab || binoptab == and_optab | |
1662 | || binoptab == xor_optab | |
1663 | || binoptab == add_optab || binoptab == sub_optab | |
80f0c37a | 1664 | || binoptab == smul_optab || binoptab == ashl_optab) |
6659485c | 1665 | && mclass == MODE_INT) |
4f4473ff | 1666 | { |
1667 | no_extend = 1; | |
1668 | xop0 = avoid_expensive_constant (mode, binoptab, | |
1669 | xop0, unsignedp); | |
1670 | if (binoptab != ashl_optab) | |
1671 | xop1 = avoid_expensive_constant (mode, binoptab, | |
1672 | xop1, unsignedp); | |
1673 | } | |
1dd91d55 | 1674 | |
92d67582 | 1675 | xop0 = widen_operand (xop0, wider_mode, mode, unsignedp, no_extend); |
303f6c6c | 1676 | |
1677 | /* The second operand of a shift must always be extended. */ | |
92d67582 | 1678 | xop1 = widen_operand (xop1, wider_mode, mode, unsignedp, |
80f0c37a | 1679 | no_extend && binoptab != ashl_optab); |
303f6c6c | 1680 | |
50b0c9ee | 1681 | temp = expand_binop (wider_mode, binoptab, xop0, xop1, NULL_RTX, |
1dd91d55 | 1682 | unsignedp, OPTAB_DIRECT); |
1683 | if (temp) | |
1684 | { | |
6659485c | 1685 | if (mclass != MODE_INT |
60a24002 | 1686 | || !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode), |
1687 | GET_MODE_BITSIZE (wider_mode))) | |
1dd91d55 | 1688 | { |
1689 | if (target == 0) | |
1690 | target = gen_reg_rtx (mode); | |
1691 | convert_move (target, temp, 0); | |
1692 | return target; | |
1693 | } | |
1694 | else | |
1695 | return gen_lowpart (mode, temp); | |
1696 | } | |
1697 | else | |
1698 | delete_insns_since (last); | |
1699 | } | |
1700 | } | |
1701 | ||
4f4473ff | 1702 | /* If operation is commutative, |
1703 | try to make the first operand a register. | |
1704 | Even better, try to make it the same as the target. | |
1705 | Also try to make the last operand a constant. */ | |
1706 | if (commutative_optab_p (binoptab) | |
1707 | && swap_commutative_operands_with_target (target, op0, op1)) | |
1708 | { | |
1709 | temp = op1; | |
1710 | op1 = op0; | |
1711 | op0 = temp; | |
1712 | } | |
1713 | ||
1f215c26 | 1714 | /* These can be done a word at a time. */ |
1715 | if ((binoptab == and_optab || binoptab == ior_optab || binoptab == xor_optab) | |
6659485c | 1716 | && mclass == MODE_INT |
1f215c26 | 1717 | && GET_MODE_SIZE (mode) > UNITS_PER_WORD |
99bdde56 | 1718 | && optab_handler (binoptab, word_mode)->insn_code != CODE_FOR_nothing) |
1f215c26 | 1719 | { |
76ab50f8 | 1720 | int i; |
1f215c26 | 1721 | rtx insns; |
1722 | rtx equiv_value; | |
1723 | ||
1724 | /* If TARGET is the same as one of the operands, the REG_EQUAL note | |
1725 | won't be accurate, so use a new target. */ | |
1726 | if (target == 0 || target == op0 || target == op1) | |
1727 | target = gen_reg_rtx (mode); | |
1728 | ||
1729 | start_sequence (); | |
1730 | ||
1731 | /* Do the actual arithmetic. */ | |
1732 | for (i = 0; i < GET_MODE_BITSIZE (mode) / BITS_PER_WORD; i++) | |
1733 | { | |
1734 | rtx target_piece = operand_subword (target, i, 1, mode); | |
3b1a9578 | 1735 | rtx x = expand_binop (word_mode, binoptab, |
1f215c26 | 1736 | operand_subword_force (op0, i, mode), |
1737 | operand_subword_force (op1, i, mode), | |
caf74f46 | 1738 | target_piece, unsignedp, next_methods); |
1739 | ||
1740 | if (x == 0) | |
1741 | break; | |
1742 | ||
1f215c26 | 1743 | if (target_piece != x) |
1744 | emit_move_insn (target_piece, x); | |
1745 | } | |
1746 | ||
1747 | insns = get_insns (); | |
1748 | end_sequence (); | |
1749 | ||
caf74f46 | 1750 | if (i == GET_MODE_BITSIZE (mode) / BITS_PER_WORD) |
1751 | { | |
1752 | if (binoptab->code != UNKNOWN) | |
1753 | equiv_value | |
e02c6d1f | 1754 | = gen_rtx_fmt_ee (binoptab->code, mode, |
1755 | copy_rtx (op0), copy_rtx (op1)); | |
caf74f46 | 1756 | else |
1757 | equiv_value = 0; | |
1f215c26 | 1758 | |
e29831db | 1759 | emit_insn (insns); |
caf74f46 | 1760 | return target; |
1761 | } | |
1f215c26 | 1762 | } |
1763 | ||
f1c8fa9b | 1764 | /* Synthesize double word shifts from single word shifts. */ |
80f0c37a | 1765 | if ((binoptab == lshr_optab || binoptab == ashl_optab |
1766 | || binoptab == ashr_optab) | |
6659485c | 1767 | && mclass == MODE_INT |
a0d18cec | 1768 | && (GET_CODE (op1) == CONST_INT || optimize_insn_for_speed_p ()) |
f1c8fa9b | 1769 | && GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD |
99bdde56 | 1770 | && optab_handler (binoptab, word_mode)->insn_code != CODE_FOR_nothing |
1771 | && optab_handler (ashl_optab, word_mode)->insn_code != CODE_FOR_nothing | |
1772 | && optab_handler (lshr_optab, word_mode)->insn_code != CODE_FOR_nothing) | |
f1c8fa9b | 1773 | { |
c49547c4 | 1774 | unsigned HOST_WIDE_INT shift_mask, double_shift_mask; |
1775 | enum machine_mode op1_mode; | |
f1c8fa9b | 1776 | |
c49547c4 | 1777 | double_shift_mask = targetm.shift_truncation_mask (mode); |
1778 | shift_mask = targetm.shift_truncation_mask (word_mode); | |
1779 | op1_mode = GET_MODE (op1) != VOIDmode ? GET_MODE (op1) : word_mode; | |
f1c8fa9b | 1780 | |
c49547c4 | 1781 | /* Apply the truncation to constant shifts. */ |
1782 | if (double_shift_mask > 0 && GET_CODE (op1) == CONST_INT) | |
1783 | op1 = GEN_INT (INTVAL (op1) & double_shift_mask); | |
f1c8fa9b | 1784 | |
c49547c4 | 1785 | if (op1 == CONST0_RTX (op1_mode)) |
1786 | return op0; | |
f1c8fa9b | 1787 | |
c49547c4 | 1788 | /* Make sure that this is a combination that expand_doubleword_shift |
1789 | can handle. See the comments there for details. */ | |
1790 | if (double_shift_mask == 0 | |
1791 | || (shift_mask == BITS_PER_WORD - 1 | |
1792 | && double_shift_mask == BITS_PER_WORD * 2 - 1)) | |
f1c8fa9b | 1793 | { |
e29831db | 1794 | rtx insns; |
c49547c4 | 1795 | rtx into_target, outof_target; |
1796 | rtx into_input, outof_input; | |
1797 | int left_shift, outof_word; | |
f1c8fa9b | 1798 | |
c49547c4 | 1799 | /* If TARGET is the same as one of the operands, the REG_EQUAL note |
1800 | won't be accurate, so use a new target. */ | |
1801 | if (target == 0 || target == op0 || target == op1) | |
1802 | target = gen_reg_rtx (mode); | |
f1c8fa9b | 1803 | |
c49547c4 | 1804 | start_sequence (); |
f1c8fa9b | 1805 | |
c49547c4 | 1806 | /* OUTOF_* is the word we are shifting bits away from, and |
1807 | INTO_* is the word that we are shifting bits towards, thus | |
1808 | they differ depending on the direction of the shift and | |
1809 | WORDS_BIG_ENDIAN. */ | |
caf74f46 | 1810 | |
c49547c4 | 1811 | left_shift = binoptab == ashl_optab; |
1812 | outof_word = left_shift ^ ! WORDS_BIG_ENDIAN; | |
caf74f46 | 1813 | |
c49547c4 | 1814 | outof_target = operand_subword (target, outof_word, 1, mode); |
1815 | into_target = operand_subword (target, 1 - outof_word, 1, mode); | |
b627826d | 1816 | |
c49547c4 | 1817 | outof_input = operand_subword_force (op0, outof_word, mode); |
1818 | into_input = operand_subword_force (op0, 1 - outof_word, mode); | |
3ad4992f | 1819 | |
c49547c4 | 1820 | if (expand_doubleword_shift (op1_mode, binoptab, |
1821 | outof_input, into_input, op1, | |
1822 | outof_target, into_target, | |
36271919 | 1823 | unsignedp, next_methods, shift_mask)) |
c49547c4 | 1824 | { |
1825 | insns = get_insns (); | |
1826 | end_sequence (); | |
f1c8fa9b | 1827 | |
e29831db | 1828 | emit_insn (insns); |
c49547c4 | 1829 | return target; |
1830 | } | |
1831 | end_sequence (); | |
caf74f46 | 1832 | } |
f1c8fa9b | 1833 | } |
1834 | ||
1835 | /* Synthesize double word rotates from single word shifts. */ | |
1836 | if ((binoptab == rotl_optab || binoptab == rotr_optab) | |
6659485c | 1837 | && mclass == MODE_INT |
f1c8fa9b | 1838 | && GET_CODE (op1) == CONST_INT |
1839 | && GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD | |
99bdde56 | 1840 | && optab_handler (ashl_optab, word_mode)->insn_code != CODE_FOR_nothing |
1841 | && optab_handler (lshr_optab, word_mode)->insn_code != CODE_FOR_nothing) | |
f1c8fa9b | 1842 | { |
26cdf093 | 1843 | rtx insns; |
f1c8fa9b | 1844 | rtx into_target, outof_target; |
1845 | rtx into_input, outof_input; | |
caf74f46 | 1846 | rtx inter; |
f1c8fa9b | 1847 | int shift_count, left_shift, outof_word; |
1848 | ||
1849 | /* If TARGET is the same as one of the operands, the REG_EQUAL note | |
209fb753 | 1850 | won't be accurate, so use a new target. Do this also if target is not |
1851 | a REG, first because having a register instead may open optimization | |
7bd28bba | 1852 | opportunities, and second because if target and op0 happen to be MEMs |
209fb753 | 1853 | designating the same location, we would risk clobbering it too early |
1854 | in the code sequence we generate below. */ | |
1855 | if (target == 0 || target == op0 || target == op1 || ! REG_P (target)) | |
f1c8fa9b | 1856 | target = gen_reg_rtx (mode); |
1857 | ||
1858 | start_sequence (); | |
1859 | ||
1860 | shift_count = INTVAL (op1); | |
1861 | ||
1862 | /* OUTOF_* is the word we are shifting bits away from, and | |
1863 | INTO_* is the word that we are shifting bits towards, thus | |
1864 | they differ depending on the direction of the shift and | |
1865 | WORDS_BIG_ENDIAN. */ | |
1866 | ||
1867 | left_shift = (binoptab == rotl_optab); | |
1868 | outof_word = left_shift ^ ! WORDS_BIG_ENDIAN; | |
1869 | ||
1870 | outof_target = operand_subword (target, outof_word, 1, mode); | |
1871 | into_target = operand_subword (target, 1 - outof_word, 1, mode); | |
1872 | ||
1873 | outof_input = operand_subword_force (op0, outof_word, mode); | |
1874 | into_input = operand_subword_force (op0, 1 - outof_word, mode); | |
1875 | ||
1876 | if (shift_count == BITS_PER_WORD) | |
1877 | { | |
1878 | /* This is just a word swap. */ | |
1879 | emit_move_insn (outof_target, into_input); | |
1880 | emit_move_insn (into_target, outof_input); | |
caf74f46 | 1881 | inter = const0_rtx; |
f1c8fa9b | 1882 | } |
1883 | else | |
1884 | { | |
1885 | rtx into_temp1, into_temp2, outof_temp1, outof_temp2; | |
1886 | rtx first_shift_count, second_shift_count; | |
1887 | optab reverse_unsigned_shift, unsigned_shift; | |
1888 | ||
1889 | reverse_unsigned_shift = (left_shift ^ (shift_count < BITS_PER_WORD) | |
1890 | ? lshr_optab : ashl_optab); | |
1891 | ||
1892 | unsigned_shift = (left_shift ^ (shift_count < BITS_PER_WORD) | |
1893 | ? ashl_optab : lshr_optab); | |
1894 | ||
1895 | if (shift_count > BITS_PER_WORD) | |
1896 | { | |
1897 | first_shift_count = GEN_INT (shift_count - BITS_PER_WORD); | |
2fd3f4b5 | 1898 | second_shift_count = GEN_INT (2 * BITS_PER_WORD - shift_count); |
f1c8fa9b | 1899 | } |
1900 | else | |
1901 | { | |
1902 | first_shift_count = GEN_INT (BITS_PER_WORD - shift_count); | |
1903 | second_shift_count = GEN_INT (shift_count); | |
1904 | } | |
1905 | ||
1906 | into_temp1 = expand_binop (word_mode, unsigned_shift, | |
1907 | outof_input, first_shift_count, | |
caf74f46 | 1908 | NULL_RTX, unsignedp, next_methods); |
f1c8fa9b | 1909 | into_temp2 = expand_binop (word_mode, reverse_unsigned_shift, |
1910 | into_input, second_shift_count, | |
a405fd23 | 1911 | NULL_RTX, unsignedp, next_methods); |
caf74f46 | 1912 | |
1913 | if (into_temp1 != 0 && into_temp2 != 0) | |
1914 | inter = expand_binop (word_mode, ior_optab, into_temp1, into_temp2, | |
1915 | into_target, unsignedp, next_methods); | |
1916 | else | |
1917 | inter = 0; | |
1918 | ||
96b899b5 | 1919 | if (inter != 0 && inter != into_target) |
caf74f46 | 1920 | emit_move_insn (into_target, inter); |
f1c8fa9b | 1921 | |
1922 | outof_temp1 = expand_binop (word_mode, unsigned_shift, | |
1923 | into_input, first_shift_count, | |
caf74f46 | 1924 | NULL_RTX, unsignedp, next_methods); |
f1c8fa9b | 1925 | outof_temp2 = expand_binop (word_mode, reverse_unsigned_shift, |
1926 | outof_input, second_shift_count, | |
a405fd23 | 1927 | NULL_RTX, unsignedp, next_methods); |
caf74f46 | 1928 | |
1929 | if (inter != 0 && outof_temp1 != 0 && outof_temp2 != 0) | |
1930 | inter = expand_binop (word_mode, ior_optab, | |
1931 | outof_temp1, outof_temp2, | |
1932 | outof_target, unsignedp, next_methods); | |
1933 | ||
96b899b5 | 1934 | if (inter != 0 && inter != outof_target) |
caf74f46 | 1935 | emit_move_insn (outof_target, inter); |
f1c8fa9b | 1936 | } |
1937 | ||
1938 | insns = get_insns (); | |
1939 | end_sequence (); | |
1940 | ||
caf74f46 | 1941 | if (inter != 0) |
1942 | { | |
26cdf093 | 1943 | emit_insn (insns); |
caf74f46 | 1944 | return target; |
1945 | } | |
f1c8fa9b | 1946 | } |
1947 | ||
1f215c26 | 1948 | /* These can be done a word at a time by propagating carries. */ |
1949 | if ((binoptab == add_optab || binoptab == sub_optab) | |
6659485c | 1950 | && mclass == MODE_INT |
1f215c26 | 1951 | && GET_MODE_SIZE (mode) >= 2 * UNITS_PER_WORD |
99bdde56 | 1952 | && optab_handler (binoptab, word_mode)->insn_code != CODE_FOR_nothing) |
1f215c26 | 1953 | { |
1f3233d1 | 1954 | unsigned int i; |
1f215c26 | 1955 | optab otheroptab = binoptab == add_optab ? sub_optab : add_optab; |
be58ed1d | 1956 | const unsigned int nwords = GET_MODE_BITSIZE (mode) / BITS_PER_WORD; |
5b7dad94 | 1957 | rtx carry_in = NULL_RTX, carry_out = NULL_RTX; |
e4b82a55 | 1958 | rtx xop0, xop1, xtarget; |
1f215c26 | 1959 | |
1960 | /* We can handle either a 1 or -1 value for the carry. If STORE_FLAG | |
1961 | value is one of those, use it. Otherwise, use 1 since it is the | |
1962 | one easiest to get. */ | |
1963 | #if STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1 | |
1964 | int normalizep = STORE_FLAG_VALUE; | |
1965 | #else | |
1966 | int normalizep = 1; | |
1967 | #endif | |
1968 | ||
1969 | /* Prepare the operands. */ | |
bc86d98c | 1970 | xop0 = force_reg (mode, op0); |
1971 | xop1 = force_reg (mode, op1); | |
1f215c26 | 1972 | |
e4b82a55 | 1973 | xtarget = gen_reg_rtx (mode); |
1974 | ||
8ad4c111 | 1975 | if (target == 0 || !REG_P (target)) |
e4b82a55 | 1976 | target = xtarget; |
1f215c26 | 1977 | |
d92701fb | 1978 | /* Indicate for flow that the entire target reg is being set. */ |
8ad4c111 | 1979 | if (REG_P (target)) |
18b42941 | 1980 | emit_clobber (xtarget); |
d92701fb | 1981 | |
1f215c26 | 1982 | /* Do the actual arithmetic. */ |
1983 | for (i = 0; i < nwords; i++) | |
1984 | { | |
1985 | int index = (WORDS_BIG_ENDIAN ? nwords - i - 1 : i); | |
e4b82a55 | 1986 | rtx target_piece = operand_subword (xtarget, index, 1, mode); |
bc86d98c | 1987 | rtx op0_piece = operand_subword_force (xop0, index, mode); |
1988 | rtx op1_piece = operand_subword_force (xop1, index, mode); | |
1f215c26 | 1989 | rtx x; |
1990 | ||
1991 | /* Main add/subtract of the input operands. */ | |
3b1a9578 | 1992 | x = expand_binop (word_mode, binoptab, |
1f215c26 | 1993 | op0_piece, op1_piece, |
caf74f46 | 1994 | target_piece, unsignedp, next_methods); |
1f215c26 | 1995 | if (x == 0) |
1996 | break; | |
1997 | ||
1998 | if (i + 1 < nwords) | |
1999 | { | |
2000 | /* Store carry from main add/subtract. */ | |
3b1a9578 | 2001 | carry_out = gen_reg_rtx (word_mode); |
d736adee | 2002 | carry_out = emit_store_flag_force (carry_out, |
2003 | (binoptab == add_optab | |
1a29b174 | 2004 | ? LT : GT), |
d736adee | 2005 | x, op0_piece, |
2006 | word_mode, 1, normalizep); | |
1f215c26 | 2007 | } |
2008 | ||
2009 | if (i > 0) | |
2010 | { | |
0462eca2 | 2011 | rtx newx; |
3ad4992f | 2012 | |
1f215c26 | 2013 | /* Add/subtract previous carry to main result. */ |
0462eca2 | 2014 | newx = expand_binop (word_mode, |
2015 | normalizep == 1 ? binoptab : otheroptab, | |
2016 | x, carry_in, | |
2017 | NULL_RTX, 1, next_methods); | |
1f215c26 | 2018 | |
2019 | if (i + 1 < nwords) | |
2020 | { | |
1f215c26 | 2021 | /* Get out carry from adding/subtracting carry in. */ |
0462eca2 | 2022 | rtx carry_tmp = gen_reg_rtx (word_mode); |
d736adee | 2023 | carry_tmp = emit_store_flag_force (carry_tmp, |
0462eca2 | 2024 | (binoptab == add_optab |
2025 | ? LT : GT), | |
2026 | newx, x, | |
d736adee | 2027 | word_mode, 1, normalizep); |
caf74f46 | 2028 | |
1f215c26 | 2029 | /* Logical-ior the two poss. carry together. */ |
3b1a9578 | 2030 | carry_out = expand_binop (word_mode, ior_optab, |
1f215c26 | 2031 | carry_out, carry_tmp, |
caf74f46 | 2032 | carry_out, 0, next_methods); |
2033 | if (carry_out == 0) | |
1f215c26 | 2034 | break; |
2035 | } | |
0462eca2 | 2036 | emit_move_insn (target_piece, newx); |
1f215c26 | 2037 | } |
439a6dca | 2038 | else |
2039 | { | |
2040 | if (x != target_piece) | |
2041 | emit_move_insn (target_piece, x); | |
2042 | } | |
1f215c26 | 2043 | |
2044 | carry_in = carry_out; | |
3ad4992f | 2045 | } |
1f215c26 | 2046 | |
1f3233d1 | 2047 | if (i == GET_MODE_BITSIZE (mode) / (unsigned) BITS_PER_WORD) |
1f215c26 | 2048 | { |
99bdde56 | 2049 | if (optab_handler (mov_optab, mode)->insn_code != CODE_FOR_nothing |
629d2471 | 2050 | || ! rtx_equal_p (target, xtarget)) |
3c96cf42 | 2051 | { |
e4b82a55 | 2052 | rtx temp = emit_move_insn (target, xtarget); |
caf74f46 | 2053 | |
e29342dc | 2054 | set_unique_reg_note (temp, |
3ad4992f | 2055 | REG_EQUAL, |
e29342dc | 2056 | gen_rtx_fmt_ee (binoptab->code, mode, |
2057 | copy_rtx (xop0), | |
2058 | copy_rtx (xop1))); | |
3c96cf42 | 2059 | } |
9f4d4b89 | 2060 | else |
2061 | target = xtarget; | |
7014838c | 2062 | |
1f215c26 | 2063 | return target; |
2064 | } | |
7014838c | 2065 | |
1f215c26 | 2066 | else |
2067 | delete_insns_since (last); | |
2068 | } | |
2069 | ||
54eb7a38 | 2070 | /* Attempt to synthesize double word multiplies using a sequence of word |
2071 | mode multiplications. We first attempt to generate a sequence using a | |
2072 | more efficient unsigned widening multiply, and if that fails we then | |
2073 | try using a signed widening multiply. */ | |
1f215c26 | 2074 | |
2075 | if (binoptab == smul_optab | |
6659485c | 2076 | && mclass == MODE_INT |
1f215c26 | 2077 | && GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD |
99bdde56 | 2078 | && optab_handler (smul_optab, word_mode)->insn_code != CODE_FOR_nothing |
2079 | && optab_handler (add_optab, word_mode)->insn_code != CODE_FOR_nothing) | |
1f215c26 | 2080 | { |
54eb7a38 | 2081 | rtx product = NULL_RTX; |
1f215c26 | 2082 | |
99bdde56 | 2083 | if (optab_handler (umul_widen_optab, mode)->insn_code |
54eb7a38 | 2084 | != CODE_FOR_nothing) |
2085 | { | |
2086 | product = expand_doubleword_mult (mode, op0, op1, target, | |
2087 | true, methods); | |
2088 | if (!product) | |
1f215c26 | 2089 | delete_insns_since (last); |
1f215c26 | 2090 | } |
2091 | ||
54eb7a38 | 2092 | if (product == NULL_RTX |
99bdde56 | 2093 | && optab_handler (smul_widen_optab, mode)->insn_code |
54eb7a38 | 2094 | != CODE_FOR_nothing) |
1f215c26 | 2095 | { |
54eb7a38 | 2096 | product = expand_doubleword_mult (mode, op0, op1, target, |
2097 | false, methods); | |
2098 | if (!product) | |
2099 | delete_insns_since (last); | |
1f215c26 | 2100 | } |
2101 | ||
54eb7a38 | 2102 | if (product != NULL_RTX) |
1f215c26 | 2103 | { |
99bdde56 | 2104 | if (optab_handler (mov_optab, mode)->insn_code != CODE_FOR_nothing) |
caf74f46 | 2105 | { |
54eb7a38 | 2106 | temp = emit_move_insn (target ? target : product, product); |
2107 | set_unique_reg_note (temp, | |
2108 | REG_EQUAL, | |
2109 | gen_rtx_fmt_ee (MULT, mode, | |
2110 | copy_rtx (op0), | |
2111 | copy_rtx (op1))); | |
1f215c26 | 2112 | } |
54eb7a38 | 2113 | return product; |
1f215c26 | 2114 | } |
1f215c26 | 2115 | } |
2116 | ||
2117 | /* It can't be open-coded in this mode. | |
2118 | Use a library call if one is available and caller says that's ok. */ | |
2119 | ||
f36b9f69 | 2120 | libfunc = optab_libfunc (binoptab, mode); |
2121 | if (libfunc | |
1f215c26 | 2122 | && (methods == OPTAB_LIB || methods == OPTAB_LIB_WIDEN)) |
2123 | { | |
2124 | rtx insns; | |
7c72e92e | 2125 | rtx op1x = op1; |
2126 | enum machine_mode op1_mode = mode; | |
bc4abce8 | 2127 | rtx value; |
1f215c26 | 2128 | |
2129 | start_sequence (); | |
2130 | ||
4f4473ff | 2131 | if (shift_optab_p (binoptab)) |
7c72e92e | 2132 | { |
0ef89dfd | 2133 | op1_mode = targetm.libgcc_shift_count_mode (); |
7c72e92e | 2134 | /* Specify unsigned here, |
2135 | since negative shift counts are meaningless. */ | |
0ef89dfd | 2136 | op1x = convert_to_mode (op1_mode, op1, 1); |
7c72e92e | 2137 | } |
2138 | ||
5913203b | 2139 | if (GET_MODE (op0) != VOIDmode |
2140 | && GET_MODE (op0) != mode) | |
7e4a644d | 2141 | op0 = convert_to_mode (mode, op0, unsignedp); |
2142 | ||
1f215c26 | 2143 | /* Pass 1 for NO_QUEUE so we don't lose any increments |
2144 | if the libcall is cse'd or moved. */ | |
f36b9f69 | 2145 | value = emit_library_call_value (libfunc, |
2c5d421b | 2146 | NULL_RTX, LCT_CONST, mode, 2, |
bc4abce8 | 2147 | op0, mode, op1x, op1_mode); |
1f215c26 | 2148 | |
2149 | insns = get_insns (); | |
2150 | end_sequence (); | |
2151 | ||
2152 | target = gen_reg_rtx (mode); | |
bc4abce8 | 2153 | emit_libcall_block (insns, target, value, |
e02c6d1f | 2154 | gen_rtx_fmt_ee (binoptab->code, mode, op0, op1)); |
1f215c26 | 2155 | |
2156 | return target; | |
2157 | } | |
2158 | ||
2159 | delete_insns_since (last); | |
2160 | ||
2161 | /* It can't be done in this mode. Can we do it in a wider mode? */ | |
2162 | ||
2163 | if (! (methods == OPTAB_WIDEN || methods == OPTAB_LIB_WIDEN | |
2164 | || methods == OPTAB_MUST_WIDEN)) | |
ea35e69c | 2165 | { |
2166 | /* Caller says, don't even try. */ | |
2167 | delete_insns_since (entry_last); | |
2168 | return 0; | |
2169 | } | |
1f215c26 | 2170 | |
2171 | /* Compute the value of METHODS to pass to recursive calls. | |
2172 | Don't allow widening to be tried recursively. */ | |
2173 | ||
2174 | methods = (methods == OPTAB_LIB_WIDEN ? OPTAB_LIB : OPTAB_DIRECT); | |
2175 | ||
3b1a9578 | 2176 | /* Look for a wider mode of the same class for which it appears we can do |
2177 | the operation. */ | |
1f215c26 | 2178 | |
6659485c | 2179 | if (CLASS_HAS_WIDER_MODES_P (mclass)) |
1f215c26 | 2180 | { |
ba592904 | 2181 | for (wider_mode = GET_MODE_WIDER_MODE (mode); |
2182 | wider_mode != VOIDmode; | |
1f215c26 | 2183 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) |
2184 | { | |
99bdde56 | 2185 | if ((optab_handler (binoptab, wider_mode)->insn_code |
1f215c26 | 2186 | != CODE_FOR_nothing) |
2187 | || (methods == OPTAB_LIB | |
f36b9f69 | 2188 | && optab_libfunc (binoptab, wider_mode))) |
1f215c26 | 2189 | { |
2190 | rtx xop0 = op0, xop1 = op1; | |
2191 | int no_extend = 0; | |
2192 | ||
3b1a9578 | 2193 | /* For certain integer operations, we need not actually extend |
1f215c26 | 2194 | the narrow operands, as long as we will truncate |
45282828 | 2195 | the results to the same narrowness. */ |
1f215c26 | 2196 | |
3b1a9578 | 2197 | if ((binoptab == ior_optab || binoptab == and_optab |
2198 | || binoptab == xor_optab | |
2199 | || binoptab == add_optab || binoptab == sub_optab | |
80f0c37a | 2200 | || binoptab == smul_optab || binoptab == ashl_optab) |
6659485c | 2201 | && mclass == MODE_INT) |
1f215c26 | 2202 | no_extend = 1; |
2203 | ||
92d67582 | 2204 | xop0 = widen_operand (xop0, wider_mode, mode, |
2205 | unsignedp, no_extend); | |
303f6c6c | 2206 | |
2207 | /* The second operand of a shift must always be extended. */ | |
92d67582 | 2208 | xop1 = widen_operand (xop1, wider_mode, mode, unsignedp, |
80f0c37a | 2209 | no_extend && binoptab != ashl_optab); |
1f215c26 | 2210 | |
50b0c9ee | 2211 | temp = expand_binop (wider_mode, binoptab, xop0, xop1, NULL_RTX, |
1f215c26 | 2212 | unsignedp, methods); |
2213 | if (temp) | |
2214 | { | |
6659485c | 2215 | if (mclass != MODE_INT |
60a24002 | 2216 | || !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode), |
2217 | GET_MODE_BITSIZE (wider_mode))) | |
1f215c26 | 2218 | { |
2219 | if (target == 0) | |
2220 | target = gen_reg_rtx (mode); | |
2221 | convert_move (target, temp, 0); | |
2222 | return target; | |
2223 | } | |
2224 | else | |
2225 | return gen_lowpart (mode, temp); | |
2226 | } | |
2227 | else | |
2228 | delete_insns_since (last); | |
2229 | } | |
2230 | } | |
2231 | } | |
2232 | ||
ea35e69c | 2233 | delete_insns_since (entry_last); |
1f215c26 | 2234 | return 0; |
2235 | } | |
2236 | \f | |
2237 | /* Expand a binary operator which has both signed and unsigned forms. | |
2238 | UOPTAB is the optab for unsigned operations, and SOPTAB is for | |
2239 | signed operations. | |
2240 | ||
2241 | If we widen unsigned operands, we may use a signed wider operation instead | |
2242 | of an unsigned wider operation, since the result would be the same. */ | |
2243 | ||
2244 | rtx | |
3ad4992f | 2245 | sign_expand_binop (enum machine_mode mode, optab uoptab, optab soptab, |
2246 | rtx op0, rtx op1, rtx target, int unsignedp, | |
2247 | enum optab_methods methods) | |
1f215c26 | 2248 | { |
19cb6b50 | 2249 | rtx temp; |
1f215c26 | 2250 | optab direct_optab = unsignedp ? uoptab : soptab; |
26dbec0a | 2251 | struct optab_d wide_soptab; |
1f215c26 | 2252 | |
2253 | /* Do it without widening, if possible. */ | |
2254 | temp = expand_binop (mode, direct_optab, op0, op1, target, | |
2255 | unsignedp, OPTAB_DIRECT); | |
2256 | if (temp || methods == OPTAB_DIRECT) | |
2257 | return temp; | |
2258 | ||
2259 | /* Try widening to a signed int. Make a fake signed optab that | |
2260 | hides any signed insn for direct use. */ | |
2261 | wide_soptab = *soptab; | |
99bdde56 | 2262 | optab_handler (&wide_soptab, mode)->insn_code = CODE_FOR_nothing; |
edc91305 | 2263 | /* We don't want to generate new hash table entries from this fake |
2264 | optab. */ | |
2265 | wide_soptab.libcall_gen = NULL; | |
1f215c26 | 2266 | |
2267 | temp = expand_binop (mode, &wide_soptab, op0, op1, target, | |
2268 | unsignedp, OPTAB_WIDEN); | |
2269 | ||
2270 | /* For unsigned operands, try widening to an unsigned int. */ | |
2271 | if (temp == 0 && unsignedp) | |
2272 | temp = expand_binop (mode, uoptab, op0, op1, target, | |
2273 | unsignedp, OPTAB_WIDEN); | |
2274 | if (temp || methods == OPTAB_WIDEN) | |
2275 | return temp; | |
2276 | ||
74f4459c | 2277 | /* Use the right width libcall if that exists. */ |
1f215c26 | 2278 | temp = expand_binop (mode, direct_optab, op0, op1, target, unsignedp, OPTAB_LIB); |
2279 | if (temp || methods == OPTAB_LIB) | |
2280 | return temp; | |
2281 | ||
74f4459c | 2282 | /* Must widen and use a libcall, use either signed or unsigned. */ |
1f215c26 | 2283 | temp = expand_binop (mode, &wide_soptab, op0, op1, target, |
2284 | unsignedp, methods); | |
2285 | if (temp != 0) | |
2286 | return temp; | |
2287 | if (unsignedp) | |
2288 | return expand_binop (mode, uoptab, op0, op1, target, | |
2289 | unsignedp, methods); | |
2290 | return 0; | |
2291 | } | |
2292 | \f | |
6b43bae4 | 2293 | /* Generate code to perform an operation specified by UNOPPTAB |
2294 | on operand OP0, with two results to TARG0 and TARG1. | |
2295 | We assume that the order of the operands for the instruction | |
2296 | is TARG0, TARG1, OP0. | |
2297 | ||
2298 | Either TARG0 or TARG1 may be zero, but what that means is that | |
2299 | the result is not actually wanted. We will generate it into | |
2300 | a dummy pseudo-reg and discard it. They may not both be zero. | |
2301 | ||
2302 | Returns 1 if this operation can be performed; 0 if not. */ | |
2303 | ||
2304 | int | |
616d4baf | 2305 | expand_twoval_unop (optab unoptab, rtx op0, rtx targ0, rtx targ1, |
6b43bae4 | 2306 | int unsignedp) |
2307 | { | |
2308 | enum machine_mode mode = GET_MODE (targ0 ? targ0 : targ1); | |
6659485c | 2309 | enum mode_class mclass; |
6b43bae4 | 2310 | enum machine_mode wider_mode; |
2311 | rtx entry_last = get_last_insn (); | |
2312 | rtx last; | |
2313 | ||
6659485c | 2314 | mclass = GET_MODE_CLASS (mode); |
6b43bae4 | 2315 | |
0a534ba7 | 2316 | if (!targ0) |
6b43bae4 | 2317 | targ0 = gen_reg_rtx (mode); |
0a534ba7 | 2318 | if (!targ1) |
6b43bae4 | 2319 | targ1 = gen_reg_rtx (mode); |
2320 | ||
2321 | /* Record where to go back to if we fail. */ | |
2322 | last = get_last_insn (); | |
2323 | ||
99bdde56 | 2324 | if (optab_handler (unoptab, mode)->insn_code != CODE_FOR_nothing) |
6b43bae4 | 2325 | { |
99bdde56 | 2326 | int icode = (int) optab_handler (unoptab, mode)->insn_code; |
6b43bae4 | 2327 | enum machine_mode mode0 = insn_data[icode].operand[2].mode; |
2328 | rtx pat; | |
2329 | rtx xop0 = op0; | |
2330 | ||
2331 | if (GET_MODE (xop0) != VOIDmode | |
2332 | && GET_MODE (xop0) != mode0) | |
2333 | xop0 = convert_to_mode (mode0, xop0, unsignedp); | |
2334 | ||
2335 | /* Now, if insn doesn't accept these operands, put them into pseudos. */ | |
ce572eff | 2336 | if (!insn_data[icode].operand[2].predicate (xop0, mode0)) |
6b43bae4 | 2337 | xop0 = copy_to_mode_reg (mode0, xop0); |
2338 | ||
2339 | /* We could handle this, but we should always be called with a pseudo | |
2340 | for our targets and all insns should take them as outputs. */ | |
ce572eff | 2341 | gcc_assert (insn_data[icode].operand[0].predicate (targ0, mode)); |
2342 | gcc_assert (insn_data[icode].operand[1].predicate (targ1, mode)); | |
6b43bae4 | 2343 | |
2344 | pat = GEN_FCN (icode) (targ0, targ1, xop0); | |
2345 | if (pat) | |
2346 | { | |
2347 | emit_insn (pat); | |
2348 | return 1; | |
2349 | } | |
2350 | else | |
2351 | delete_insns_since (last); | |
2352 | } | |
2353 | ||
2354 | /* It can't be done in this mode. Can we do it in a wider mode? */ | |
2355 | ||
6659485c | 2356 | if (CLASS_HAS_WIDER_MODES_P (mclass)) |
6b43bae4 | 2357 | { |
ba592904 | 2358 | for (wider_mode = GET_MODE_WIDER_MODE (mode); |
2359 | wider_mode != VOIDmode; | |
6b43bae4 | 2360 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) |
2361 | { | |
99bdde56 | 2362 | if (optab_handler (unoptab, wider_mode)->insn_code |
6b43bae4 | 2363 | != CODE_FOR_nothing) |
2364 | { | |
2365 | rtx t0 = gen_reg_rtx (wider_mode); | |
2366 | rtx t1 = gen_reg_rtx (wider_mode); | |
2367 | rtx cop0 = convert_modes (wider_mode, mode, op0, unsignedp); | |
2368 | ||
616d4baf | 2369 | if (expand_twoval_unop (unoptab, cop0, t0, t1, unsignedp)) |
6b43bae4 | 2370 | { |
2371 | convert_move (targ0, t0, unsignedp); | |
2372 | convert_move (targ1, t1, unsignedp); | |
2373 | return 1; | |
2374 | } | |
2375 | else | |
2376 | delete_insns_since (last); | |
2377 | } | |
2378 | } | |
2379 | } | |
2380 | ||
2381 | delete_insns_since (entry_last); | |
2382 | return 0; | |
2383 | } | |
2384 | \f | |
1f215c26 | 2385 | /* Generate code to perform an operation specified by BINOPTAB |
2386 | on operands OP0 and OP1, with two results to TARG1 and TARG2. | |
2387 | We assume that the order of the operands for the instruction | |
2388 | is TARG0, OP0, OP1, TARG1, which would fit a pattern like | |
2389 | [(set TARG0 (operate OP0 OP1)) (set TARG1 (operate ...))]. | |
2390 | ||
2391 | Either TARG0 or TARG1 may be zero, but what that means is that | |
3398e91d | 2392 | the result is not actually wanted. We will generate it into |
1f215c26 | 2393 | a dummy pseudo-reg and discard it. They may not both be zero. |
2394 | ||
2395 | Returns 1 if this operation can be performed; 0 if not. */ | |
2396 | ||
2397 | int | |
3ad4992f | 2398 | expand_twoval_binop (optab binoptab, rtx op0, rtx op1, rtx targ0, rtx targ1, |
2399 | int unsignedp) | |
1f215c26 | 2400 | { |
2401 | enum machine_mode mode = GET_MODE (targ0 ? targ0 : targ1); | |
6659485c | 2402 | enum mode_class mclass; |
1f215c26 | 2403 | enum machine_mode wider_mode; |
ea35e69c | 2404 | rtx entry_last = get_last_insn (); |
1f215c26 | 2405 | rtx last; |
2406 | ||
6659485c | 2407 | mclass = GET_MODE_CLASS (mode); |
1f215c26 | 2408 | |
0a534ba7 | 2409 | if (!targ0) |
1f215c26 | 2410 | targ0 = gen_reg_rtx (mode); |
0a534ba7 | 2411 | if (!targ1) |
1f215c26 | 2412 | targ1 = gen_reg_rtx (mode); |
2413 | ||
2414 | /* Record where to go back to if we fail. */ | |
2415 | last = get_last_insn (); | |
2416 | ||
99bdde56 | 2417 | if (optab_handler (binoptab, mode)->insn_code != CODE_FOR_nothing) |
1f215c26 | 2418 | { |
99bdde56 | 2419 | int icode = (int) optab_handler (binoptab, mode)->insn_code; |
6357eaae | 2420 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; |
2421 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
1f215c26 | 2422 | rtx pat; |
2423 | rtx xop0 = op0, xop1 = op1; | |
2424 | ||
4f4473ff | 2425 | /* If we are optimizing, force expensive constants into a register. */ |
2426 | xop0 = avoid_expensive_constant (mode0, binoptab, xop0, unsignedp); | |
2427 | xop1 = avoid_expensive_constant (mode1, binoptab, xop1, unsignedp); | |
2428 | ||
e805a0b5 | 2429 | /* In case the insn wants input operands in modes different from |
2430 | those of the actual operands, convert the operands. It would | |
2431 | seem that we don't need to convert CONST_INTs, but we do, so | |
67595860 | 2432 | that they're properly zero-extended, sign-extended or truncated |
2433 | for their mode. */ | |
1f215c26 | 2434 | |
e805a0b5 | 2435 | if (GET_MODE (op0) != mode0 && mode0 != VOIDmode) |
2436 | xop0 = convert_modes (mode0, | |
2437 | GET_MODE (op0) != VOIDmode | |
2438 | ? GET_MODE (op0) | |
2439 | : mode, | |
2440 | xop0, unsignedp); | |
2441 | ||
2442 | if (GET_MODE (op1) != mode1 && mode1 != VOIDmode) | |
2443 | xop1 = convert_modes (mode1, | |
2444 | GET_MODE (op1) != VOIDmode | |
2445 | ? GET_MODE (op1) | |
2446 | : mode, | |
2447 | xop1, unsignedp); | |
1f215c26 | 2448 | |
2449 | /* Now, if insn doesn't accept these operands, put them into pseudos. */ | |
ce572eff | 2450 | if (!insn_data[icode].operand[1].predicate (xop0, mode0)) |
1f215c26 | 2451 | xop0 = copy_to_mode_reg (mode0, xop0); |
2452 | ||
ce572eff | 2453 | if (!insn_data[icode].operand[2].predicate (xop1, mode1)) |
1f215c26 | 2454 | xop1 = copy_to_mode_reg (mode1, xop1); |
2455 | ||
2456 | /* We could handle this, but we should always be called with a pseudo | |
2457 | for our targets and all insns should take them as outputs. */ | |
ce572eff | 2458 | gcc_assert (insn_data[icode].operand[0].predicate (targ0, mode)); |
2459 | gcc_assert (insn_data[icode].operand[3].predicate (targ1, mode)); | |
3ad4992f | 2460 | |
1f215c26 | 2461 | pat = GEN_FCN (icode) (targ0, xop0, xop1, targ1); |
2462 | if (pat) | |
2463 | { | |
2464 | emit_insn (pat); | |
2465 | return 1; | |
2466 | } | |
2467 | else | |
2468 | delete_insns_since (last); | |
2469 | } | |
2470 | ||
2471 | /* It can't be done in this mode. Can we do it in a wider mode? */ | |
2472 | ||
6659485c | 2473 | if (CLASS_HAS_WIDER_MODES_P (mclass)) |
1f215c26 | 2474 | { |
ba592904 | 2475 | for (wider_mode = GET_MODE_WIDER_MODE (mode); |
2476 | wider_mode != VOIDmode; | |
1f215c26 | 2477 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) |
2478 | { | |
99bdde56 | 2479 | if (optab_handler (binoptab, wider_mode)->insn_code |
1f215c26 | 2480 | != CODE_FOR_nothing) |
2481 | { | |
19cb6b50 | 2482 | rtx t0 = gen_reg_rtx (wider_mode); |
2483 | rtx t1 = gen_reg_rtx (wider_mode); | |
4427eb38 | 2484 | rtx cop0 = convert_modes (wider_mode, mode, op0, unsignedp); |
2485 | rtx cop1 = convert_modes (wider_mode, mode, op1, unsignedp); | |
1f215c26 | 2486 | |
4427eb38 | 2487 | if (expand_twoval_binop (binoptab, cop0, cop1, |
1f215c26 | 2488 | t0, t1, unsignedp)) |
2489 | { | |
2490 | convert_move (targ0, t0, unsignedp); | |
2491 | convert_move (targ1, t1, unsignedp); | |
2492 | return 1; | |
2493 | } | |
2494 | else | |
2495 | delete_insns_since (last); | |
2496 | } | |
2497 | } | |
2498 | } | |
2499 | ||
ea35e69c | 2500 | delete_insns_since (entry_last); |
1f215c26 | 2501 | return 0; |
2502 | } | |
30e9913f | 2503 | |
2504 | /* Expand the two-valued library call indicated by BINOPTAB, but | |
2505 | preserve only one of the values. If TARG0 is non-NULL, the first | |
2506 | value is placed into TARG0; otherwise the second value is placed | |
2507 | into TARG1. Exactly one of TARG0 and TARG1 must be non-NULL. The | |
2508 | value stored into TARG0 or TARG1 is equivalent to (CODE OP0 OP1). | |
2509 | This routine assumes that the value returned by the library call is | |
2510 | as if the return value was of an integral mode twice as wide as the | |
2511 | mode of OP0. Returns 1 if the call was successful. */ | |
2512 | ||
2513 | bool | |
7d3f6cc7 | 2514 | expand_twoval_binop_libfunc (optab binoptab, rtx op0, rtx op1, |
30e9913f | 2515 | rtx targ0, rtx targ1, enum rtx_code code) |
2516 | { | |
2517 | enum machine_mode mode; | |
2518 | enum machine_mode libval_mode; | |
2519 | rtx libval; | |
2520 | rtx insns; | |
f36b9f69 | 2521 | rtx libfunc; |
7d3f6cc7 | 2522 | |
30e9913f | 2523 | /* Exactly one of TARG0 or TARG1 should be non-NULL. */ |
ce572eff | 2524 | gcc_assert (!targ0 != !targ1); |
30e9913f | 2525 | |
2526 | mode = GET_MODE (op0); | |
f36b9f69 | 2527 | libfunc = optab_libfunc (binoptab, mode); |
2528 | if (!libfunc) | |
30e9913f | 2529 | return false; |
2530 | ||
2531 | /* The value returned by the library function will have twice as | |
2532 | many bits as the nominal MODE. */ | |
7d3f6cc7 | 2533 | libval_mode = smallest_mode_for_size (2 * GET_MODE_BITSIZE (mode), |
30e9913f | 2534 | MODE_INT); |
2535 | start_sequence (); | |
f36b9f69 | 2536 | libval = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST, |
30e9913f | 2537 | libval_mode, 2, |
7d3f6cc7 | 2538 | op0, mode, |
30e9913f | 2539 | op1, mode); |
2540 | /* Get the part of VAL containing the value that we want. */ | |
2541 | libval = simplify_gen_subreg (mode, libval, libval_mode, | |
2542 | targ0 ? 0 : GET_MODE_SIZE (mode)); | |
2543 | insns = get_insns (); | |
2544 | end_sequence (); | |
2545 | /* Move the into the desired location. */ | |
7d3f6cc7 | 2546 | emit_libcall_block (insns, targ0 ? targ0 : targ1, libval, |
30e9913f | 2547 | gen_rtx_fmt_ee (code, mode, op0, op1)); |
7d3f6cc7 | 2548 | |
30e9913f | 2549 | return true; |
2550 | } | |
2551 | ||
1f215c26 | 2552 | \f |
ad99e708 | 2553 | /* Wrapper around expand_unop which takes an rtx code to specify |
2554 | the operation to perform, not an optab pointer. All other | |
2555 | arguments are the same. */ | |
2556 | rtx | |
3ad4992f | 2557 | expand_simple_unop (enum machine_mode mode, enum rtx_code code, rtx op0, |
2558 | rtx target, int unsignedp) | |
ad99e708 | 2559 | { |
2fd3f4b5 | 2560 | optab unop = code_to_optab[(int) code]; |
ce572eff | 2561 | gcc_assert (unop); |
ad99e708 | 2562 | |
2563 | return expand_unop (mode, unop, op0, target, unsignedp); | |
2564 | } | |
2565 | ||
6a08d0ab | 2566 | /* Try calculating |
2567 | (clz:narrow x) | |
2568 | as | |
2569 | (clz:wide (zero_extend:wide x)) - ((width wide) - (width narrow)). */ | |
2570 | static rtx | |
3ad4992f | 2571 | widen_clz (enum machine_mode mode, rtx op0, rtx target) |
6a08d0ab | 2572 | { |
6659485c | 2573 | enum mode_class mclass = GET_MODE_CLASS (mode); |
2574 | if (CLASS_HAS_WIDER_MODES_P (mclass)) | |
6a08d0ab | 2575 | { |
2576 | enum machine_mode wider_mode; | |
ba592904 | 2577 | for (wider_mode = GET_MODE_WIDER_MODE (mode); |
2578 | wider_mode != VOIDmode; | |
6a08d0ab | 2579 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) |
2580 | { | |
99bdde56 | 2581 | if (optab_handler (clz_optab, wider_mode)->insn_code |
6a08d0ab | 2582 | != CODE_FOR_nothing) |
2583 | { | |
2584 | rtx xop0, temp, last; | |
2585 | ||
2586 | last = get_last_insn (); | |
2587 | ||
2588 | if (target == 0) | |
2589 | target = gen_reg_rtx (mode); | |
2590 | xop0 = widen_operand (op0, wider_mode, mode, true, false); | |
2591 | temp = expand_unop (wider_mode, clz_optab, xop0, NULL_RTX, true); | |
2592 | if (temp != 0) | |
2593 | temp = expand_binop (wider_mode, sub_optab, temp, | |
2594 | GEN_INT (GET_MODE_BITSIZE (wider_mode) | |
2595 | - GET_MODE_BITSIZE (mode)), | |
2596 | target, true, OPTAB_DIRECT); | |
2597 | if (temp == 0) | |
2598 | delete_insns_since (last); | |
2599 | ||
2600 | return temp; | |
2601 | } | |
2602 | } | |
2603 | } | |
2604 | return 0; | |
2605 | } | |
2606 | ||
5e02ce4e | 2607 | /* Try calculating clz of a double-word quantity as two clz's of word-sized |
2608 | quantities, choosing which based on whether the high word is nonzero. */ | |
2609 | static rtx | |
2610 | expand_doubleword_clz (enum machine_mode mode, rtx op0, rtx target) | |
2611 | { | |
2612 | rtx xop0 = force_reg (mode, op0); | |
2613 | rtx subhi = gen_highpart (word_mode, xop0); | |
2614 | rtx sublo = gen_lowpart (word_mode, xop0); | |
2615 | rtx hi0_label = gen_label_rtx (); | |
2616 | rtx after_label = gen_label_rtx (); | |
2617 | rtx seq, temp, result; | |
2618 | ||
2619 | /* If we were not given a target, use a word_mode register, not a | |
2620 | 'mode' register. The result will fit, and nobody is expecting | |
2621 | anything bigger (the return type of __builtin_clz* is int). */ | |
2622 | if (!target) | |
2623 | target = gen_reg_rtx (word_mode); | |
2624 | ||
2625 | /* In any case, write to a word_mode scratch in both branches of the | |
2626 | conditional, so we can ensure there is a single move insn setting | |
2627 | 'target' to tag a REG_EQUAL note on. */ | |
2628 | result = gen_reg_rtx (word_mode); | |
2629 | ||
2630 | start_sequence (); | |
2631 | ||
2632 | /* If the high word is not equal to zero, | |
2633 | then clz of the full value is clz of the high word. */ | |
2634 | emit_cmp_and_jump_insns (subhi, CONST0_RTX (word_mode), EQ, 0, | |
2635 | word_mode, true, hi0_label); | |
2636 | ||
2637 | temp = expand_unop_direct (word_mode, clz_optab, subhi, result, true); | |
2638 | if (!temp) | |
2639 | goto fail; | |
2640 | ||
2641 | if (temp != result) | |
2642 | convert_move (result, temp, true); | |
2643 | ||
2644 | emit_jump_insn (gen_jump (after_label)); | |
2645 | emit_barrier (); | |
2646 | ||
2647 | /* Else clz of the full value is clz of the low word plus the number | |
2648 | of bits in the high word. */ | |
2649 | emit_label (hi0_label); | |
2650 | ||
2651 | temp = expand_unop_direct (word_mode, clz_optab, sublo, 0, true); | |
2652 | if (!temp) | |
2653 | goto fail; | |
2654 | temp = expand_binop (word_mode, add_optab, temp, | |
2655 | GEN_INT (GET_MODE_BITSIZE (word_mode)), | |
2656 | result, true, OPTAB_DIRECT); | |
2657 | if (!temp) | |
2658 | goto fail; | |
2659 | if (temp != result) | |
2660 | convert_move (result, temp, true); | |
2661 | ||
2662 | emit_label (after_label); | |
2663 | convert_move (target, result, true); | |
2664 | ||
2665 | seq = get_insns (); | |
2666 | end_sequence (); | |
2667 | ||
2668 | add_equal_note (seq, target, CLZ, xop0, 0); | |
2669 | emit_insn (seq); | |
2670 | return target; | |
2671 | ||
2672 | fail: | |
2673 | end_sequence (); | |
2674 | return 0; | |
2675 | } | |
2676 | ||
1b5539c8 | 2677 | /* Try calculating |
2678 | (bswap:narrow x) | |
2679 | as | |
2680 | (lshiftrt:wide (bswap:wide x) ((width wide) - (width narrow))). */ | |
2681 | static rtx | |
2682 | widen_bswap (enum machine_mode mode, rtx op0, rtx target) | |
2683 | { | |
6659485c | 2684 | enum mode_class mclass = GET_MODE_CLASS (mode); |
1b5539c8 | 2685 | enum machine_mode wider_mode; |
2686 | rtx x, last; | |
2687 | ||
6659485c | 2688 | if (!CLASS_HAS_WIDER_MODES_P (mclass)) |
1b5539c8 | 2689 | return NULL_RTX; |
2690 | ||
2691 | for (wider_mode = GET_MODE_WIDER_MODE (mode); | |
2692 | wider_mode != VOIDmode; | |
2693 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) | |
99bdde56 | 2694 | if (optab_handler (bswap_optab, wider_mode)->insn_code != CODE_FOR_nothing) |
1b5539c8 | 2695 | goto found; |
2696 | return NULL_RTX; | |
2697 | ||
2698 | found: | |
2699 | last = get_last_insn (); | |
2700 | ||
2701 | x = widen_operand (op0, wider_mode, mode, true, true); | |
2702 | x = expand_unop (wider_mode, bswap_optab, x, NULL_RTX, true); | |
2703 | ||
2704 | if (x != 0) | |
2705 | x = expand_shift (RSHIFT_EXPR, wider_mode, x, | |
2706 | size_int (GET_MODE_BITSIZE (wider_mode) | |
2707 | - GET_MODE_BITSIZE (mode)), | |
2708 | NULL_RTX, true); | |
2709 | ||
2710 | if (x != 0) | |
2711 | { | |
2712 | if (target == 0) | |
2713 | target = gen_reg_rtx (mode); | |
2714 | emit_move_insn (target, gen_lowpart (mode, x)); | |
2715 | } | |
2716 | else | |
2717 | delete_insns_since (last); | |
2718 | ||
2719 | return target; | |
2720 | } | |
2721 | ||
2722 | /* Try calculating bswap as two bswaps of two word-sized operands. */ | |
2723 | ||
2724 | static rtx | |
2725 | expand_doubleword_bswap (enum machine_mode mode, rtx op, rtx target) | |
2726 | { | |
2727 | rtx t0, t1; | |
2728 | ||
2729 | t1 = expand_unop (word_mode, bswap_optab, | |
2730 | operand_subword_force (op, 0, mode), NULL_RTX, true); | |
2731 | t0 = expand_unop (word_mode, bswap_optab, | |
2732 | operand_subword_force (op, 1, mode), NULL_RTX, true); | |
2733 | ||
2734 | if (target == 0) | |
2735 | target = gen_reg_rtx (mode); | |
2736 | if (REG_P (target)) | |
18b42941 | 2737 | emit_clobber (target); |
1b5539c8 | 2738 | emit_move_insn (operand_subword (target, 0, 1, mode), t0); |
2739 | emit_move_insn (operand_subword (target, 1, 1, mode), t1); | |
2740 | ||
2741 | return target; | |
2742 | } | |
2743 | ||
6a08d0ab | 2744 | /* Try calculating (parity x) as (and (popcount x) 1), where |
2745 | popcount can also be done in a wider mode. */ | |
2746 | static rtx | |
3ad4992f | 2747 | expand_parity (enum machine_mode mode, rtx op0, rtx target) |
6a08d0ab | 2748 | { |
6659485c | 2749 | enum mode_class mclass = GET_MODE_CLASS (mode); |
2750 | if (CLASS_HAS_WIDER_MODES_P (mclass)) | |
6a08d0ab | 2751 | { |
2752 | enum machine_mode wider_mode; | |
2753 | for (wider_mode = mode; wider_mode != VOIDmode; | |
2754 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) | |
2755 | { | |
99bdde56 | 2756 | if (optab_handler (popcount_optab, wider_mode)->insn_code |
6a08d0ab | 2757 | != CODE_FOR_nothing) |
2758 | { | |
2759 | rtx xop0, temp, last; | |
2760 | ||
2761 | last = get_last_insn (); | |
2762 | ||
2763 | if (target == 0) | |
2764 | target = gen_reg_rtx (mode); | |
2765 | xop0 = widen_operand (op0, wider_mode, mode, true, false); | |
2766 | temp = expand_unop (wider_mode, popcount_optab, xop0, NULL_RTX, | |
2767 | true); | |
2768 | if (temp != 0) | |
6757f5d6 | 2769 | temp = expand_binop (wider_mode, and_optab, temp, const1_rtx, |
6a08d0ab | 2770 | target, true, OPTAB_DIRECT); |
2771 | if (temp == 0) | |
2772 | delete_insns_since (last); | |
2773 | ||
2774 | return temp; | |
2775 | } | |
2776 | } | |
2777 | } | |
2778 | return 0; | |
2779 | } | |
2780 | ||
5e02ce4e | 2781 | /* Try calculating ctz(x) as K - clz(x & -x) , |
2782 | where K is GET_MODE_BITSIZE(mode) - 1. | |
2783 | ||
2784 | Both __builtin_ctz and __builtin_clz are undefined at zero, so we | |
2785 | don't have to worry about what the hardware does in that case. (If | |
2786 | the clz instruction produces the usual value at 0, which is K, the | |
2787 | result of this code sequence will be -1; expand_ffs, below, relies | |
2788 | on this. It might be nice to have it be K instead, for consistency | |
2789 | with the (very few) processors that provide a ctz with a defined | |
2790 | value, but that would take one more instruction, and it would be | |
2791 | less convenient for expand_ffs anyway. */ | |
2792 | ||
e533b20e | 2793 | static rtx |
5e02ce4e | 2794 | expand_ctz (enum machine_mode mode, rtx op0, rtx target) |
e533b20e | 2795 | { |
5e02ce4e | 2796 | rtx seq, temp; |
2797 | ||
2798 | if (optab_handler (clz_optab, mode)->insn_code == CODE_FOR_nothing) | |
2799 | return 0; | |
2800 | ||
2801 | start_sequence (); | |
e533b20e | 2802 | |
5e02ce4e | 2803 | temp = expand_unop_direct (mode, neg_optab, op0, NULL_RTX, true); |
2804 | if (temp) | |
2805 | temp = expand_binop (mode, and_optab, op0, temp, NULL_RTX, | |
2806 | true, OPTAB_DIRECT); | |
2807 | if (temp) | |
2808 | temp = expand_unop_direct (mode, clz_optab, temp, NULL_RTX, true); | |
2809 | if (temp) | |
2810 | temp = expand_binop (mode, sub_optab, GEN_INT (GET_MODE_BITSIZE (mode) - 1), | |
2811 | temp, target, | |
2812 | true, OPTAB_DIRECT); | |
2813 | if (temp == 0) | |
2814 | { | |
2815 | end_sequence (); | |
2816 | return 0; | |
e533b20e | 2817 | } |
5e02ce4e | 2818 | |
2819 | seq = get_insns (); | |
2820 | end_sequence (); | |
2821 | ||
2822 | add_equal_note (seq, temp, CTZ, op0, 0); | |
2823 | emit_insn (seq); | |
2824 | return temp; | |
e533b20e | 2825 | } |
2826 | ||
5e02ce4e | 2827 | |
2828 | /* Try calculating ffs(x) using ctz(x) if we have that instruction, or | |
2829 | else with the sequence used by expand_clz. | |
2830 | ||
2831 | The ffs builtin promises to return zero for a zero value and ctz/clz | |
2832 | may have an undefined value in that case. If they do not give us a | |
2833 | convenient value, we have to generate a test and branch. */ | |
e533b20e | 2834 | static rtx |
5e02ce4e | 2835 | expand_ffs (enum machine_mode mode, rtx op0, rtx target) |
e533b20e | 2836 | { |
ff845099 | 2837 | HOST_WIDE_INT val = 0; |
2838 | bool defined_at_zero = false; | |
5e02ce4e | 2839 | rtx temp, seq; |
2840 | ||
2841 | if (optab_handler (ctz_optab, mode)->insn_code != CODE_FOR_nothing) | |
e533b20e | 2842 | { |
5e02ce4e | 2843 | start_sequence (); |
e533b20e | 2844 | |
5e02ce4e | 2845 | temp = expand_unop_direct (mode, ctz_optab, op0, 0, true); |
2846 | if (!temp) | |
2847 | goto fail; | |
2848 | ||
2849 | defined_at_zero = (CTZ_DEFINED_VALUE_AT_ZERO (mode, val) == 2); | |
e533b20e | 2850 | } |
5e02ce4e | 2851 | else if (optab_handler (clz_optab, mode)->insn_code != CODE_FOR_nothing) |
2852 | { | |
2853 | start_sequence (); | |
2854 | temp = expand_ctz (mode, op0, 0); | |
2855 | if (!temp) | |
2856 | goto fail; | |
2857 | ||
2858 | if (CLZ_DEFINED_VALUE_AT_ZERO (mode, val) == 2) | |
2859 | { | |
2860 | defined_at_zero = true; | |
2861 | val = (GET_MODE_BITSIZE (mode) - 1) - val; | |
2862 | } | |
2863 | } | |
2864 | else | |
2865 | return 0; | |
2866 | ||
2867 | if (defined_at_zero && val == -1) | |
2868 | /* No correction needed at zero. */; | |
2869 | else | |
2870 | { | |
2871 | /* We don't try to do anything clever with the situation found | |
2872 | on some processors (eg Alpha) where ctz(0:mode) == | |
2873 | bitsize(mode). If someone can think of a way to send N to -1 | |
2874 | and leave alone all values in the range 0..N-1 (where N is a | |
2875 | power of two), cheaper than this test-and-branch, please add it. | |
2876 | ||
2877 | The test-and-branch is done after the operation itself, in case | |
2878 | the operation sets condition codes that can be recycled for this. | |
2879 | (This is true on i386, for instance.) */ | |
2880 | ||
2881 | rtx nonzero_label = gen_label_rtx (); | |
2882 | emit_cmp_and_jump_insns (op0, CONST0_RTX (mode), NE, 0, | |
2883 | mode, true, nonzero_label); | |
2884 | ||
2885 | convert_move (temp, GEN_INT (-1), false); | |
2886 | emit_label (nonzero_label); | |
2887 | } | |
2888 | ||
2889 | /* temp now has a value in the range -1..bitsize-1. ffs is supposed | |
2890 | to produce a value in the range 0..bitsize. */ | |
2891 | temp = expand_binop (mode, add_optab, temp, GEN_INT (1), | |
2892 | target, false, OPTAB_DIRECT); | |
2893 | if (!temp) | |
2894 | goto fail; | |
2895 | ||
2896 | seq = get_insns (); | |
2897 | end_sequence (); | |
2898 | ||
2899 | add_equal_note (seq, temp, FFS, op0, 0); | |
2900 | emit_insn (seq); | |
2901 | return temp; | |
2902 | ||
2903 | fail: | |
2904 | end_sequence (); | |
e533b20e | 2905 | return 0; |
2906 | } | |
2907 | ||
26364c07 | 2908 | /* Extract the OMODE lowpart from VAL, which has IMODE. Under certain |
75c4772a | 2909 | conditions, VAL may already be a SUBREG against which we cannot generate |
2910 | a further SUBREG. In this case, we expect forcing the value into a | |
2911 | register will work around the situation. */ | |
2912 | ||
2913 | static rtx | |
2914 | lowpart_subreg_maybe_copy (enum machine_mode omode, rtx val, | |
2915 | enum machine_mode imode) | |
2916 | { | |
2917 | rtx ret; | |
2918 | ret = lowpart_subreg (omode, val, imode); | |
2919 | if (ret == NULL) | |
2920 | { | |
2921 | val = force_reg (imode, val); | |
2922 | ret = lowpart_subreg (omode, val, imode); | |
2923 | gcc_assert (ret != NULL); | |
2924 | } | |
2925 | return ret; | |
2926 | } | |
2927 | ||
64c41dc1 | 2928 | /* Expand a floating point absolute value or negation operation via a |
2929 | logical operation on the sign bit. */ | |
2930 | ||
2931 | static rtx | |
2932 | expand_absneg_bit (enum rtx_code code, enum machine_mode mode, | |
2933 | rtx op0, rtx target) | |
2934 | { | |
2935 | const struct real_format *fmt; | |
2936 | int bitpos, word, nwords, i; | |
2937 | enum machine_mode imode; | |
2938 | HOST_WIDE_INT hi, lo; | |
2939 | rtx temp, insns; | |
2940 | ||
2941 | /* The format has to have a simple sign bit. */ | |
2942 | fmt = REAL_MODE_FORMAT (mode); | |
2943 | if (fmt == NULL) | |
2944 | return NULL_RTX; | |
2945 | ||
8d564692 | 2946 | bitpos = fmt->signbit_rw; |
64c41dc1 | 2947 | if (bitpos < 0) |
2948 | return NULL_RTX; | |
2949 | ||
2950 | /* Don't create negative zeros if the format doesn't support them. */ | |
2951 | if (code == NEG && !fmt->has_signed_zero) | |
2952 | return NULL_RTX; | |
2953 | ||
2954 | if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD) | |
2955 | { | |
2956 | imode = int_mode_for_mode (mode); | |
2957 | if (imode == BLKmode) | |
2958 | return NULL_RTX; | |
2959 | word = 0; | |
2960 | nwords = 1; | |
2961 | } | |
2962 | else | |
2963 | { | |
2964 | imode = word_mode; | |
2965 | ||
2966 | if (FLOAT_WORDS_BIG_ENDIAN) | |
2967 | word = (GET_MODE_BITSIZE (mode) - bitpos) / BITS_PER_WORD; | |
2968 | else | |
2969 | word = bitpos / BITS_PER_WORD; | |
2970 | bitpos = bitpos % BITS_PER_WORD; | |
2971 | nwords = (GET_MODE_BITSIZE (mode) + BITS_PER_WORD - 1) / BITS_PER_WORD; | |
2972 | } | |
2973 | ||
2974 | if (bitpos < HOST_BITS_PER_WIDE_INT) | |
2975 | { | |
2976 | hi = 0; | |
2977 | lo = (HOST_WIDE_INT) 1 << bitpos; | |
2978 | } | |
2979 | else | |
2980 | { | |
2981 | hi = (HOST_WIDE_INT) 1 << (bitpos - HOST_BITS_PER_WIDE_INT); | |
2982 | lo = 0; | |
2983 | } | |
2984 | if (code == ABS) | |
2985 | lo = ~lo, hi = ~hi; | |
2986 | ||
2987 | if (target == 0 || target == op0) | |
2988 | target = gen_reg_rtx (mode); | |
2989 | ||
2990 | if (nwords > 1) | |
2991 | { | |
2992 | start_sequence (); | |
2993 | ||
2994 | for (i = 0; i < nwords; ++i) | |
2995 | { | |
2996 | rtx targ_piece = operand_subword (target, i, 1, mode); | |
2997 | rtx op0_piece = operand_subword_force (op0, i, mode); | |
26364c07 | 2998 | |
64c41dc1 | 2999 | if (i == word) |
3000 | { | |
3001 | temp = expand_binop (imode, code == ABS ? and_optab : xor_optab, | |
3002 | op0_piece, | |
3003 | immed_double_const (lo, hi, imode), | |
3004 | targ_piece, 1, OPTAB_LIB_WIDEN); | |
3005 | if (temp != targ_piece) | |
3006 | emit_move_insn (targ_piece, temp); | |
3007 | } | |
3008 | else | |
3009 | emit_move_insn (targ_piece, op0_piece); | |
3010 | } | |
3011 | ||
3012 | insns = get_insns (); | |
3013 | end_sequence (); | |
3014 | ||
e29831db | 3015 | emit_insn (insns); |
64c41dc1 | 3016 | } |
3017 | else | |
3018 | { | |
3019 | temp = expand_binop (imode, code == ABS ? and_optab : xor_optab, | |
3020 | gen_lowpart (imode, op0), | |
3021 | immed_double_const (lo, hi, imode), | |
3022 | gen_lowpart (imode, target), 1, OPTAB_LIB_WIDEN); | |
3023 | target = lowpart_subreg_maybe_copy (mode, temp, imode); | |
3024 | ||
3025 | set_unique_reg_note (get_last_insn (), REG_EQUAL, | |
3026 | gen_rtx_fmt_e (code, mode, copy_rtx (op0))); | |
3027 | } | |
3028 | ||
3029 | return target; | |
3030 | } | |
3031 | ||
5e02ce4e | 3032 | /* As expand_unop, but will fail rather than attempt the operation in a |
3033 | different mode or with a libcall. */ | |
3034 | static rtx | |
3035 | expand_unop_direct (enum machine_mode mode, optab unoptab, rtx op0, rtx target, | |
3ad4992f | 3036 | int unsignedp) |
1f215c26 | 3037 | { |
99bdde56 | 3038 | if (optab_handler (unoptab, mode)->insn_code != CODE_FOR_nothing) |
1f215c26 | 3039 | { |
99bdde56 | 3040 | int icode = (int) optab_handler (unoptab, mode)->insn_code; |
6357eaae | 3041 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; |
1f215c26 | 3042 | rtx xop0 = op0; |
5e02ce4e | 3043 | rtx last = get_last_insn (); |
3044 | rtx pat, temp; | |
1f215c26 | 3045 | |
3046 | if (target) | |
3047 | temp = target; | |
3048 | else | |
3049 | temp = gen_reg_rtx (mode); | |
3050 | ||
3051 | if (GET_MODE (xop0) != VOIDmode | |
3052 | && GET_MODE (xop0) != mode0) | |
3053 | xop0 = convert_to_mode (mode0, xop0, unsignedp); | |
3054 | ||
3055 | /* Now, if insn doesn't accept our operand, put it into a pseudo. */ | |
3056 | ||
ce572eff | 3057 | if (!insn_data[icode].operand[1].predicate (xop0, mode0)) |
1f215c26 | 3058 | xop0 = copy_to_mode_reg (mode0, xop0); |
3059 | ||
ce572eff | 3060 | if (!insn_data[icode].operand[0].predicate (temp, mode)) |
1f215c26 | 3061 | temp = gen_reg_rtx (mode); |
3062 | ||
3063 | pat = GEN_FCN (icode) (temp, xop0); | |
3064 | if (pat) | |
3065 | { | |
31d3e01c | 3066 | if (INSN_P (pat) && NEXT_INSN (pat) != NULL_RTX |
50b0c9ee | 3067 | && ! add_equal_note (pat, temp, unoptab->code, xop0, NULL_RTX)) |
1f215c26 | 3068 | { |
3069 | delete_insns_since (last); | |
50b0c9ee | 3070 | return expand_unop (mode, unoptab, op0, NULL_RTX, unsignedp); |
1f215c26 | 3071 | } |
3072 | ||
3073 | emit_insn (pat); | |
3ad4992f | 3074 | |
1f215c26 | 3075 | return temp; |
3076 | } | |
3077 | else | |
3078 | delete_insns_since (last); | |
3079 | } | |
5e02ce4e | 3080 | return 0; |
3081 | } | |
3082 | ||
3083 | /* Generate code to perform an operation specified by UNOPTAB | |
3084 | on operand OP0, with result having machine-mode MODE. | |
3085 | ||
3086 | UNSIGNEDP is for the case where we have to widen the operands | |
3087 | to perform the operation. It says to use zero-extension. | |
3088 | ||
3089 | If TARGET is nonzero, the value | |
3090 | is generated there, if it is convenient to do so. | |
3091 | In all cases an rtx is returned for the locus of the value; | |
3092 | this may or may not be TARGET. */ | |
3093 | ||
3094 | rtx | |
3095 | expand_unop (enum machine_mode mode, optab unoptab, rtx op0, rtx target, | |
3096 | int unsignedp) | |
3097 | { | |
6659485c | 3098 | enum mode_class mclass = GET_MODE_CLASS (mode); |
5e02ce4e | 3099 | enum machine_mode wider_mode; |
3100 | rtx temp; | |
f36b9f69 | 3101 | rtx libfunc; |
5e02ce4e | 3102 | |
3103 | temp = expand_unop_direct (mode, unoptab, op0, target, unsignedp); | |
3104 | if (temp) | |
3105 | return temp; | |
1f215c26 | 3106 | |
1dd91d55 | 3107 | /* It can't be done in this mode. Can we open-code it in a wider mode? */ |
3108 | ||
5e02ce4e | 3109 | /* Widening (or narrowing) clz needs special treatment. */ |
6a08d0ab | 3110 | if (unoptab == clz_optab) |
3111 | { | |
3112 | temp = widen_clz (mode, op0, target); | |
3113 | if (temp) | |
3114 | return temp; | |
5e02ce4e | 3115 | |
3116 | if (GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD | |
3117 | && optab_handler (unoptab, word_mode)->insn_code != CODE_FOR_nothing) | |
3118 | { | |
3119 | temp = expand_doubleword_clz (mode, op0, target); | |
3120 | if (temp) | |
3121 | return temp; | |
3122 | } | |
3123 | ||
6a08d0ab | 3124 | goto try_libcall; |
3125 | } | |
3126 | ||
1b5539c8 | 3127 | /* Widening (or narrowing) bswap needs special treatment. */ |
42791117 | 3128 | if (unoptab == bswap_optab) |
1b5539c8 | 3129 | { |
3130 | temp = widen_bswap (mode, op0, target); | |
3131 | if (temp) | |
3132 | return temp; | |
3133 | ||
3134 | if (GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD | |
99bdde56 | 3135 | && optab_handler (unoptab, word_mode)->insn_code != CODE_FOR_nothing) |
1b5539c8 | 3136 | { |
3137 | temp = expand_doubleword_bswap (mode, op0, target); | |
3138 | if (temp) | |
3139 | return temp; | |
3140 | } | |
3141 | ||
3142 | goto try_libcall; | |
3143 | } | |
42791117 | 3144 | |
6659485c | 3145 | if (CLASS_HAS_WIDER_MODES_P (mclass)) |
ba592904 | 3146 | for (wider_mode = GET_MODE_WIDER_MODE (mode); |
3147 | wider_mode != VOIDmode; | |
1dd91d55 | 3148 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) |
3149 | { | |
99bdde56 | 3150 | if (optab_handler (unoptab, wider_mode)->insn_code != CODE_FOR_nothing) |
1dd91d55 | 3151 | { |
3152 | rtx xop0 = op0; | |
5e02ce4e | 3153 | rtx last = get_last_insn (); |
1dd91d55 | 3154 | |
3155 | /* For certain operations, we need not actually extend | |
3156 | the narrow operand, as long as we will truncate the | |
45282828 | 3157 | results to the same narrowness. */ |
3158 | ||
92d67582 | 3159 | xop0 = widen_operand (xop0, wider_mode, mode, unsignedp, |
45282828 | 3160 | (unoptab == neg_optab |
3161 | || unoptab == one_cmpl_optab) | |
6659485c | 3162 | && mclass == MODE_INT); |
3ad4992f | 3163 | |
50b0c9ee | 3164 | temp = expand_unop (wider_mode, unoptab, xop0, NULL_RTX, |
3165 | unsignedp); | |
1dd91d55 | 3166 | |
3167 | if (temp) | |
3168 | { | |
6659485c | 3169 | if (mclass != MODE_INT |
f0273187 | 3170 | || !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode), |
3171 | GET_MODE_BITSIZE (wider_mode))) | |
1dd91d55 | 3172 | { |
3173 | if (target == 0) | |
3174 | target = gen_reg_rtx (mode); | |
3175 | convert_move (target, temp, 0); | |
3176 | return target; | |
3177 | } | |
3178 | else | |
3179 | return gen_lowpart (mode, temp); | |
3180 | } | |
3181 | else | |
3182 | delete_insns_since (last); | |
3183 | } | |
3184 | } | |
3185 | ||
1f215c26 | 3186 | /* These can be done a word at a time. */ |
3187 | if (unoptab == one_cmpl_optab | |
6659485c | 3188 | && mclass == MODE_INT |
1f215c26 | 3189 | && GET_MODE_SIZE (mode) > UNITS_PER_WORD |
99bdde56 | 3190 | && optab_handler (unoptab, word_mode)->insn_code != CODE_FOR_nothing) |
1f215c26 | 3191 | { |
76ab50f8 | 3192 | int i; |
1f215c26 | 3193 | rtx insns; |
3194 | ||
3195 | if (target == 0 || target == op0) | |
3196 | target = gen_reg_rtx (mode); | |
3197 | ||
3198 | start_sequence (); | |
3199 | ||
3200 | /* Do the actual arithmetic. */ | |
3201 | for (i = 0; i < GET_MODE_BITSIZE (mode) / BITS_PER_WORD; i++) | |
3202 | { | |
3203 | rtx target_piece = operand_subword (target, i, 1, mode); | |
3b1a9578 | 3204 | rtx x = expand_unop (word_mode, unoptab, |
1f215c26 | 3205 | operand_subword_force (op0, i, mode), |
3206 | target_piece, unsignedp); | |
76ab50f8 | 3207 | |
1f215c26 | 3208 | if (target_piece != x) |
3209 | emit_move_insn (target_piece, x); | |
3210 | } | |
3211 | ||
3212 | insns = get_insns (); | |
3213 | end_sequence (); | |
3214 | ||
e29831db | 3215 | emit_insn (insns); |
1f215c26 | 3216 | return target; |
3217 | } | |
3218 | ||
64c41dc1 | 3219 | if (unoptab->code == NEG) |
805e22b2 | 3220 | { |
64c41dc1 | 3221 | /* Try negating floating point values by flipping the sign bit. */ |
0f7f2d29 | 3222 | if (SCALAR_FLOAT_MODE_P (mode)) |
805e22b2 | 3223 | { |
64c41dc1 | 3224 | temp = expand_absneg_bit (NEG, mode, op0, target); |
3225 | if (temp) | |
3226 | return temp; | |
3227 | } | |
89ae05a2 | 3228 | |
64c41dc1 | 3229 | /* If there is no negation pattern, and we have no negative zero, |
3230 | try subtracting from zero. */ | |
3231 | if (!HONOR_SIGNED_ZEROS (mode)) | |
3232 | { | |
3233 | temp = expand_binop (mode, (unoptab == negv_optab | |
3234 | ? subv_optab : sub_optab), | |
3235 | CONST0_RTX (mode), op0, target, | |
3236 | unsignedp, OPTAB_DIRECT); | |
3237 | if (temp) | |
3238 | return temp; | |
3239 | } | |
805e22b2 | 3240 | } |
3241 | ||
6a08d0ab | 3242 | /* Try calculating parity (x) as popcount (x) % 2. */ |
3243 | if (unoptab == parity_optab) | |
3244 | { | |
3245 | temp = expand_parity (mode, op0, target); | |
3246 | if (temp) | |
3247 | return temp; | |
3248 | } | |
3249 | ||
e533b20e | 3250 | /* Try implementing ffs (x) in terms of clz (x). */ |
3251 | if (unoptab == ffs_optab) | |
3252 | { | |
3253 | temp = expand_ffs (mode, op0, target); | |
3254 | if (temp) | |
3255 | return temp; | |
3256 | } | |
3257 | ||
3258 | /* Try implementing ctz (x) in terms of clz (x). */ | |
3259 | if (unoptab == ctz_optab) | |
3260 | { | |
3261 | temp = expand_ctz (mode, op0, target); | |
3262 | if (temp) | |
3263 | return temp; | |
3264 | } | |
3265 | ||
6a08d0ab | 3266 | try_libcall: |
fc7385ae | 3267 | /* Now try a library call in this mode. */ |
f36b9f69 | 3268 | libfunc = optab_libfunc (unoptab, mode); |
3269 | if (libfunc) | |
1f215c26 | 3270 | { |
3271 | rtx insns; | |
bc4abce8 | 3272 | rtx value; |
e03d813f | 3273 | rtx eq_value; |
6a08d0ab | 3274 | enum machine_mode outmode = mode; |
3275 | ||
3276 | /* All of these functions return small values. Thus we choose to | |
3277 | have them return something that isn't a double-word. */ | |
3278 | if (unoptab == ffs_optab || unoptab == clz_optab || unoptab == ctz_optab | |
3279 | || unoptab == popcount_optab || unoptab == parity_optab) | |
22ac1ed3 | 3280 | outmode |
3281 | = GET_MODE (hard_libcall_value (TYPE_MODE (integer_type_node))); | |
1f215c26 | 3282 | |
3283 | start_sequence (); | |
3284 | ||
3285 | /* Pass 1 for NO_QUEUE so we don't lose any increments | |
3286 | if the libcall is cse'd or moved. */ | |
f36b9f69 | 3287 | value = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST, outmode, |
6a08d0ab | 3288 | 1, op0, mode); |
1f215c26 | 3289 | insns = get_insns (); |
3290 | end_sequence (); | |
3291 | ||
6a08d0ab | 3292 | target = gen_reg_rtx (outmode); |
e03d813f | 3293 | eq_value = gen_rtx_fmt_e (unoptab->code, mode, op0); |
3294 | if (GET_MODE_SIZE (outmode) < GET_MODE_SIZE (mode)) | |
3295 | eq_value = simplify_gen_unary (TRUNCATE, outmode, eq_value, mode); | |
3296 | else if (GET_MODE_SIZE (outmode) > GET_MODE_SIZE (mode)) | |
3297 | eq_value = simplify_gen_unary (ZERO_EXTEND, outmode, eq_value, mode); | |
3298 | emit_libcall_block (insns, target, value, eq_value); | |
1f215c26 | 3299 | |
3300 | return target; | |
3301 | } | |
3302 | ||
3303 | /* It can't be done in this mode. Can we do it in a wider mode? */ | |
3304 | ||
6659485c | 3305 | if (CLASS_HAS_WIDER_MODES_P (mclass)) |
1f215c26 | 3306 | { |
ba592904 | 3307 | for (wider_mode = GET_MODE_WIDER_MODE (mode); |
3308 | wider_mode != VOIDmode; | |
1f215c26 | 3309 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) |
3310 | { | |
99bdde56 | 3311 | if ((optab_handler (unoptab, wider_mode)->insn_code |
1f215c26 | 3312 | != CODE_FOR_nothing) |
f36b9f69 | 3313 | || optab_libfunc (unoptab, wider_mode)) |
1f215c26 | 3314 | { |
3b1a9578 | 3315 | rtx xop0 = op0; |
5e02ce4e | 3316 | rtx last = get_last_insn (); |
3b1a9578 | 3317 | |
3318 | /* For certain operations, we need not actually extend | |
3319 | the narrow operand, as long as we will truncate the | |
3320 | results to the same narrowness. */ | |
3321 | ||
92d67582 | 3322 | xop0 = widen_operand (xop0, wider_mode, mode, unsignedp, |
45282828 | 3323 | (unoptab == neg_optab |
3324 | || unoptab == one_cmpl_optab) | |
6659485c | 3325 | && mclass == MODE_INT); |
3ad4992f | 3326 | |
50b0c9ee | 3327 | temp = expand_unop (wider_mode, unoptab, xop0, NULL_RTX, |
3328 | unsignedp); | |
3b1a9578 | 3329 | |
7f10ce85 | 3330 | /* If we are generating clz using wider mode, adjust the |
3331 | result. */ | |
3332 | if (unoptab == clz_optab && temp != 0) | |
3333 | temp = expand_binop (wider_mode, sub_optab, temp, | |
3334 | GEN_INT (GET_MODE_BITSIZE (wider_mode) | |
3335 | - GET_MODE_BITSIZE (mode)), | |
3336 | target, true, OPTAB_DIRECT); | |
3337 | ||
3b1a9578 | 3338 | if (temp) |
1f215c26 | 3339 | { |
6659485c | 3340 | if (mclass != MODE_INT) |
3b1a9578 | 3341 | { |
3342 | if (target == 0) | |
3343 | target = gen_reg_rtx (mode); | |
3344 | convert_move (target, temp, 0); | |
3345 | return target; | |
3346 | } | |
3347 | else | |
3348 | return gen_lowpart (mode, temp); | |
1f215c26 | 3349 | } |
3350 | else | |
3b1a9578 | 3351 | delete_insns_since (last); |
1f215c26 | 3352 | } |
3353 | } | |
3354 | } | |
3355 | ||
64c41dc1 | 3356 | /* One final attempt at implementing negation via subtraction, |
3357 | this time allowing widening of the operand. */ | |
3358 | if (unoptab->code == NEG && !HONOR_SIGNED_ZEROS (mode)) | |
3ad4992f | 3359 | { |
59e6f6ff | 3360 | rtx temp; |
bec2d490 | 3361 | temp = expand_binop (mode, |
3362 | unoptab == negv_optab ? subv_optab : sub_optab, | |
3363 | CONST0_RTX (mode), op0, | |
3364 | target, unsignedp, OPTAB_LIB_WIDEN); | |
59e6f6ff | 3365 | if (temp) |
64c41dc1 | 3366 | return temp; |
59e6f6ff | 3367 | } |
3ad4992f | 3368 | |
1f215c26 | 3369 | return 0; |
3370 | } | |
3371 | \f | |
a00c1647 | 3372 | /* Emit code to compute the absolute value of OP0, with result to |
3373 | TARGET if convenient. (TARGET may be 0.) The return value says | |
3374 | where the result actually is to be found. | |
3375 | ||
3376 | MODE is the mode of the operand; the mode of the result is | |
3377 | different but can be deduced from MODE. | |
3378 | ||
23449318 | 3379 | */ |
b4827f8d | 3380 | |
3381 | rtx | |
3ad4992f | 3382 | expand_abs_nojump (enum machine_mode mode, rtx op0, rtx target, |
3383 | int result_unsignedp) | |
b4827f8d | 3384 | { |
8ed073f5 | 3385 | rtx temp; |
b4827f8d | 3386 | |
bec2d490 | 3387 | if (! flag_trapv) |
3388 | result_unsignedp = 1; | |
3389 | ||
b4827f8d | 3390 | /* First try to do it with a special abs instruction. */ |
bec2d490 | 3391 | temp = expand_unop (mode, result_unsignedp ? abs_optab : absv_optab, |
3392 | op0, target, 0); | |
b4827f8d | 3393 | if (temp != 0) |
3394 | return temp; | |
3395 | ||
805e22b2 | 3396 | /* For floating point modes, try clearing the sign bit. */ |
cee7491d | 3397 | if (SCALAR_FLOAT_MODE_P (mode)) |
805e22b2 | 3398 | { |
64c41dc1 | 3399 | temp = expand_absneg_bit (ABS, mode, op0, target); |
3400 | if (temp) | |
3401 | return temp; | |
805e22b2 | 3402 | } |
3403 | ||
155b05dc | 3404 | /* If we have a MAX insn, we can do this as MAX (x, -x). */ |
99bdde56 | 3405 | if (optab_handler (smax_optab, mode)->insn_code != CODE_FOR_nothing |
64c41dc1 | 3406 | && !HONOR_SIGNED_ZEROS (mode)) |
155b05dc | 3407 | { |
3408 | rtx last = get_last_insn (); | |
3409 | ||
3410 | temp = expand_unop (mode, neg_optab, op0, NULL_RTX, 0); | |
3411 | if (temp != 0) | |
3412 | temp = expand_binop (mode, smax_optab, op0, temp, target, 0, | |
3413 | OPTAB_WIDEN); | |
3414 | ||
3415 | if (temp != 0) | |
3416 | return temp; | |
3417 | ||
3418 | delete_insns_since (last); | |
3419 | } | |
3420 | ||
b4827f8d | 3421 | /* If this machine has expensive jumps, we can do integer absolute |
3422 | value of X as (((signed) x >> (W-1)) ^ x) - ((signed) x >> (W-1)), | |
4e227d41 | 3423 | where W is the width of MODE. */ |
b4827f8d | 3424 | |
4a9d7ef7 | 3425 | if (GET_MODE_CLASS (mode) == MODE_INT |
3426 | && BRANCH_COST (optimize_insn_for_speed_p (), | |
3427 | false) >= 2) | |
b4827f8d | 3428 | { |
3429 | rtx extended = expand_shift (RSHIFT_EXPR, mode, op0, | |
3430 | size_int (GET_MODE_BITSIZE (mode) - 1), | |
3431 | NULL_RTX, 0); | |
3432 | ||
3433 | temp = expand_binop (mode, xor_optab, extended, op0, target, 0, | |
3434 | OPTAB_LIB_WIDEN); | |
3435 | if (temp != 0) | |
bec2d490 | 3436 | temp = expand_binop (mode, result_unsignedp ? sub_optab : subv_optab, |
3437 | temp, extended, target, 0, OPTAB_LIB_WIDEN); | |
b4827f8d | 3438 | |
3439 | if (temp != 0) | |
3440 | return temp; | |
3441 | } | |
3442 | ||
8ed073f5 | 3443 | return NULL_RTX; |
3444 | } | |
3445 | ||
3446 | rtx | |
3ad4992f | 3447 | expand_abs (enum machine_mode mode, rtx op0, rtx target, |
3448 | int result_unsignedp, int safe) | |
8ed073f5 | 3449 | { |
3450 | rtx temp, op1; | |
3451 | ||
91d4c237 | 3452 | if (! flag_trapv) |
3453 | result_unsignedp = 1; | |
3454 | ||
8ed073f5 | 3455 | temp = expand_abs_nojump (mode, op0, target, result_unsignedp); |
3456 | if (temp != 0) | |
3457 | return temp; | |
3458 | ||
b4827f8d | 3459 | /* If that does not win, use conditional jump and negate. */ |
a1870317 | 3460 | |
3461 | /* It is safe to use the target if it is the same | |
3462 | as the source if this is also a pseudo register */ | |
8ad4c111 | 3463 | if (op0 == target && REG_P (op0) |
a1870317 | 3464 | && REGNO (op0) >= FIRST_PSEUDO_REGISTER) |
3465 | safe = 1; | |
3466 | ||
b4827f8d | 3467 | op1 = gen_label_rtx (); |
3468 | if (target == 0 || ! safe | |
3469 | || GET_MODE (target) != mode | |
e16ceb8e | 3470 | || (MEM_P (target) && MEM_VOLATILE_P (target)) |
8ad4c111 | 3471 | || (REG_P (target) |
b4827f8d | 3472 | && REGNO (target) < FIRST_PSEUDO_REGISTER)) |
3473 | target = gen_reg_rtx (mode); | |
3474 | ||
3475 | emit_move_insn (target, op0); | |
3476 | NO_DEFER_POP; | |
3477 | ||
c071a2df | 3478 | do_compare_rtx_and_jump (target, CONST0_RTX (mode), GE, 0, mode, |
3479 | NULL_RTX, NULL_RTX, op1); | |
b4827f8d | 3480 | |
bec2d490 | 3481 | op0 = expand_unop (mode, result_unsignedp ? neg_optab : negv_optab, |
3482 | target, target, 0); | |
b4827f8d | 3483 | if (op0 != target) |
3484 | emit_move_insn (target, op0); | |
3485 | emit_label (op1); | |
3486 | OK_DEFER_POP; | |
3487 | return target; | |
3488 | } | |
270436f3 | 3489 | |
eece650a | 3490 | /* A subroutine of expand_copysign, perform the copysign operation using the |
3491 | abs and neg primitives advertised to exist on the target. The assumption | |
3492 | is that we have a split register file, and leaving op0 in fp registers, | |
3493 | and not playing with subregs so much, will help the register allocator. */ | |
270436f3 | 3494 | |
58667906 | 3495 | static rtx |
eece650a | 3496 | expand_copysign_absneg (enum machine_mode mode, rtx op0, rtx op1, rtx target, |
3497 | int bitpos, bool op0_is_abs) | |
270436f3 | 3498 | { |
270436f3 | 3499 | enum machine_mode imode; |
27eda240 | 3500 | int icode; |
3501 | rtx sign, label; | |
270436f3 | 3502 | |
eece650a | 3503 | if (target == op1) |
3504 | target = NULL_RTX; | |
270436f3 | 3505 | |
27eda240 | 3506 | /* Check if the back end provides an insn that handles signbit for the |
3507 | argument's mode. */ | |
3508 | icode = (int) signbit_optab->handlers [(int) mode].insn_code; | |
3509 | if (icode != CODE_FOR_nothing) | |
eece650a | 3510 | { |
27eda240 | 3511 | imode = insn_data[icode].operand[0].mode; |
3512 | sign = gen_reg_rtx (imode); | |
3513 | emit_unop_insn (icode, sign, op1, UNKNOWN); | |
eece650a | 3514 | } |
3515 | else | |
3516 | { | |
27eda240 | 3517 | HOST_WIDE_INT hi, lo; |
3518 | ||
3519 | if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD) | |
3520 | { | |
3521 | imode = int_mode_for_mode (mode); | |
3522 | if (imode == BLKmode) | |
3523 | return NULL_RTX; | |
3524 | op1 = gen_lowpart (imode, op1); | |
3525 | } | |
eece650a | 3526 | else |
27eda240 | 3527 | { |
3528 | int word; | |
270436f3 | 3529 | |
27eda240 | 3530 | imode = word_mode; |
3531 | if (FLOAT_WORDS_BIG_ENDIAN) | |
3532 | word = (GET_MODE_BITSIZE (mode) - bitpos) / BITS_PER_WORD; | |
3533 | else | |
3534 | word = bitpos / BITS_PER_WORD; | |
3535 | bitpos = bitpos % BITS_PER_WORD; | |
3536 | op1 = operand_subword_force (op1, word, mode); | |
3537 | } | |
3538 | ||
3539 | if (bitpos < HOST_BITS_PER_WIDE_INT) | |
3540 | { | |
3541 | hi = 0; | |
3542 | lo = (HOST_WIDE_INT) 1 << bitpos; | |
3543 | } | |
eece650a | 3544 | else |
27eda240 | 3545 | { |
3546 | hi = (HOST_WIDE_INT) 1 << (bitpos - HOST_BITS_PER_WIDE_INT); | |
3547 | lo = 0; | |
3548 | } | |
3549 | ||
3550 | sign = gen_reg_rtx (imode); | |
3551 | sign = expand_binop (imode, and_optab, op1, | |
3552 | immed_double_const (lo, hi, imode), | |
3553 | NULL_RTX, 1, OPTAB_LIB_WIDEN); | |
eece650a | 3554 | } |
270436f3 | 3555 | |
27eda240 | 3556 | if (!op0_is_abs) |
64c41dc1 | 3557 | { |
27eda240 | 3558 | op0 = expand_unop (mode, abs_optab, op0, target, 0); |
3559 | if (op0 == NULL) | |
3560 | return NULL_RTX; | |
3561 | target = op0; | |
64c41dc1 | 3562 | } |
eece650a | 3563 | else |
3564 | { | |
27eda240 | 3565 | if (target == NULL_RTX) |
3566 | target = copy_to_reg (op0); | |
3567 | else | |
3568 | emit_move_insn (target, op0); | |
eece650a | 3569 | } |
3570 | ||
eece650a | 3571 | label = gen_label_rtx (); |
27eda240 | 3572 | emit_cmp_and_jump_insns (sign, const0_rtx, EQ, NULL_RTX, imode, 1, label); |
eece650a | 3573 | |
3574 | if (GET_CODE (op0) == CONST_DOUBLE) | |
3575 | op0 = simplify_unary_operation (NEG, mode, op0, mode); | |
3576 | else | |
3577 | op0 = expand_unop (mode, neg_optab, op0, target, 0); | |
3578 | if (op0 != target) | |
3579 | emit_move_insn (target, op0); | |
3580 | ||
3581 | emit_label (label); | |
3582 | ||
3583 | return target; | |
3584 | } | |
3585 | ||
3586 | ||
3587 | /* A subroutine of expand_copysign, perform the entire copysign operation | |
3588 | with integer bitmasks. BITPOS is the position of the sign bit; OP0_IS_ABS | |
3589 | is true if op0 is known to have its sign bit clear. */ | |
3590 | ||
3591 | static rtx | |
3592 | expand_copysign_bit (enum machine_mode mode, rtx op0, rtx op1, rtx target, | |
3593 | int bitpos, bool op0_is_abs) | |
3594 | { | |
3595 | enum machine_mode imode; | |
3596 | HOST_WIDE_INT hi, lo; | |
3597 | int word, nwords, i; | |
3598 | rtx temp, insns; | |
270436f3 | 3599 | |
64c41dc1 | 3600 | if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD) |
270436f3 | 3601 | { |
64c41dc1 | 3602 | imode = int_mode_for_mode (mode); |
3603 | if (imode == BLKmode) | |
3604 | return NULL_RTX; | |
3605 | word = 0; | |
3606 | nwords = 1; | |
3607 | } | |
3608 | else | |
3609 | { | |
3610 | imode = word_mode; | |
3611 | ||
3612 | if (FLOAT_WORDS_BIG_ENDIAN) | |
3613 | word = (GET_MODE_BITSIZE (mode) - bitpos) / BITS_PER_WORD; | |
3614 | else | |
3615 | word = bitpos / BITS_PER_WORD; | |
3616 | bitpos = bitpos % BITS_PER_WORD; | |
3617 | nwords = (GET_MODE_BITSIZE (mode) + BITS_PER_WORD - 1) / BITS_PER_WORD; | |
270436f3 | 3618 | } |
3619 | ||
3620 | if (bitpos < HOST_BITS_PER_WIDE_INT) | |
3621 | { | |
3622 | hi = 0; | |
3623 | lo = (HOST_WIDE_INT) 1 << bitpos; | |
3624 | } | |
3625 | else | |
3626 | { | |
3627 | hi = (HOST_WIDE_INT) 1 << (bitpos - HOST_BITS_PER_WIDE_INT); | |
3628 | lo = 0; | |
3629 | } | |
3630 | ||
64c41dc1 | 3631 | if (target == 0 || target == op0 || target == op1) |
3632 | target = gen_reg_rtx (mode); | |
3633 | ||
3634 | if (nwords > 1) | |
270436f3 | 3635 | { |
64c41dc1 | 3636 | start_sequence (); |
3637 | ||
3638 | for (i = 0; i < nwords; ++i) | |
270436f3 | 3639 | { |
64c41dc1 | 3640 | rtx targ_piece = operand_subword (target, i, 1, mode); |
3641 | rtx op0_piece = operand_subword_force (op0, i, mode); | |
26364c07 | 3642 | |
64c41dc1 | 3643 | if (i == word) |
3644 | { | |
eece650a | 3645 | if (!op0_is_abs) |
64c41dc1 | 3646 | op0_piece = expand_binop (imode, and_optab, op0_piece, |
3647 | immed_double_const (~lo, ~hi, imode), | |
3648 | NULL_RTX, 1, OPTAB_LIB_WIDEN); | |
3649 | ||
3650 | op1 = expand_binop (imode, and_optab, | |
3651 | operand_subword_force (op1, i, mode), | |
3652 | immed_double_const (lo, hi, imode), | |
3653 | NULL_RTX, 1, OPTAB_LIB_WIDEN); | |
3654 | ||
3655 | temp = expand_binop (imode, ior_optab, op0_piece, op1, | |
3656 | targ_piece, 1, OPTAB_LIB_WIDEN); | |
3657 | if (temp != targ_piece) | |
3658 | emit_move_insn (targ_piece, temp); | |
3659 | } | |
3660 | else | |
3661 | emit_move_insn (targ_piece, op0_piece); | |
270436f3 | 3662 | } |
64c41dc1 | 3663 | |
3664 | insns = get_insns (); | |
3665 | end_sequence (); | |
3666 | ||
e29831db | 3667 | emit_insn (insns); |
270436f3 | 3668 | } |
3669 | else | |
64c41dc1 | 3670 | { |
3671 | op1 = expand_binop (imode, and_optab, gen_lowpart (imode, op1), | |
3672 | immed_double_const (lo, hi, imode), | |
3673 | NULL_RTX, 1, OPTAB_LIB_WIDEN); | |
3674 | ||
3675 | op0 = gen_lowpart (imode, op0); | |
eece650a | 3676 | if (!op0_is_abs) |
64c41dc1 | 3677 | op0 = expand_binop (imode, and_optab, op0, |
3678 | immed_double_const (~lo, ~hi, imode), | |
3679 | NULL_RTX, 1, OPTAB_LIB_WIDEN); | |
3680 | ||
3681 | temp = expand_binop (imode, ior_optab, op0, op1, | |
3682 | gen_lowpart (imode, target), 1, OPTAB_LIB_WIDEN); | |
3683 | target = lowpart_subreg_maybe_copy (mode, temp, imode); | |
3684 | } | |
270436f3 | 3685 | |
3686 | return target; | |
3687 | } | |
eece650a | 3688 | |
26364c07 | 3689 | /* Expand the C99 copysign operation. OP0 and OP1 must be the same |
eece650a | 3690 | scalar floating point mode. Return NULL if we do not know how to |
3691 | expand the operation inline. */ | |
3692 | ||
3693 | rtx | |
3694 | expand_copysign (rtx op0, rtx op1, rtx target) | |
3695 | { | |
3696 | enum machine_mode mode = GET_MODE (op0); | |
3697 | const struct real_format *fmt; | |
eece650a | 3698 | bool op0_is_abs; |
3699 | rtx temp; | |
3700 | ||
3701 | gcc_assert (SCALAR_FLOAT_MODE_P (mode)); | |
3702 | gcc_assert (GET_MODE (op1) == mode); | |
3703 | ||
3704 | /* First try to do it with a special instruction. */ | |
3705 | temp = expand_binop (mode, copysign_optab, op0, op1, | |
3706 | target, 0, OPTAB_DIRECT); | |
3707 | if (temp) | |
3708 | return temp; | |
3709 | ||
3710 | fmt = REAL_MODE_FORMAT (mode); | |
3711 | if (fmt == NULL || !fmt->has_signed_zero) | |
3712 | return NULL_RTX; | |
3713 | ||
eece650a | 3714 | op0_is_abs = false; |
3715 | if (GET_CODE (op0) == CONST_DOUBLE) | |
3716 | { | |
3717 | if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0))) | |
3718 | op0 = simplify_unary_operation (ABS, mode, op0, mode); | |
3719 | op0_is_abs = true; | |
3720 | } | |
3721 | ||
879363c3 | 3722 | if (fmt->signbit_ro >= 0 |
3723 | && (GET_CODE (op0) == CONST_DOUBLE | |
99bdde56 | 3724 | || (optab_handler (neg_optab, mode)->insn_code != CODE_FOR_nothing |
3725 | && optab_handler (abs_optab, mode)->insn_code != CODE_FOR_nothing))) | |
eece650a | 3726 | { |
3727 | temp = expand_copysign_absneg (mode, op0, op1, target, | |
879363c3 | 3728 | fmt->signbit_ro, op0_is_abs); |
eece650a | 3729 | if (temp) |
3730 | return temp; | |
3731 | } | |
3732 | ||
879363c3 | 3733 | if (fmt->signbit_rw < 0) |
3734 | return NULL_RTX; | |
3735 | return expand_copysign_bit (mode, op0, op1, target, | |
3736 | fmt->signbit_rw, op0_is_abs); | |
eece650a | 3737 | } |
b4827f8d | 3738 | \f |
1f215c26 | 3739 | /* Generate an instruction whose insn-code is INSN_CODE, |
3740 | with two operands: an output TARGET and an input OP0. | |
3741 | TARGET *must* be nonzero, and the output is always stored there. | |
3742 | CODE is an rtx code such that (CODE OP0) is an rtx that describes | |
a1515011 | 3743 | the value that is stored into TARGET. |
1f215c26 | 3744 | |
a1515011 | 3745 | Return false if expansion failed. */ |
3746 | ||
3747 | bool | |
3748 | maybe_emit_unop_insn (int icode, rtx target, rtx op0, enum rtx_code code) | |
1f215c26 | 3749 | { |
19cb6b50 | 3750 | rtx temp; |
6357eaae | 3751 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; |
1f215c26 | 3752 | rtx pat; |
c73ea1cc | 3753 | rtx last = get_last_insn (); |
1f215c26 | 3754 | |
0a534ba7 | 3755 | temp = target; |
1f215c26 | 3756 | |
1f215c26 | 3757 | /* Now, if insn does not accept our operands, put them into pseudos. */ |
3758 | ||
ce572eff | 3759 | if (!insn_data[icode].operand[1].predicate (op0, mode0)) |
1f215c26 | 3760 | op0 = copy_to_mode_reg (mode0, op0); |
3761 | ||
b531302c | 3762 | if (!insn_data[icode].operand[0].predicate (temp, GET_MODE (temp))) |
1f215c26 | 3763 | temp = gen_reg_rtx (GET_MODE (temp)); |
3764 | ||
3765 | pat = GEN_FCN (icode) (temp, op0); | |
a1515011 | 3766 | if (!pat) |
c73ea1cc | 3767 | { |
3768 | delete_insns_since (last); | |
3769 | return false; | |
3770 | } | |
1f215c26 | 3771 | |
31d3e01c | 3772 | if (INSN_P (pat) && NEXT_INSN (pat) != NULL_RTX && code != UNKNOWN) |
50b0c9ee | 3773 | add_equal_note (pat, temp, code, op0, NULL_RTX); |
3ad4992f | 3774 | |
1f215c26 | 3775 | emit_insn (pat); |
3776 | ||
3777 | if (temp != target) | |
3778 | emit_move_insn (target, temp); | |
a1515011 | 3779 | return true; |
3780 | } | |
3781 | /* Generate an instruction whose insn-code is INSN_CODE, | |
3782 | with two operands: an output TARGET and an input OP0. | |
3783 | TARGET *must* be nonzero, and the output is always stored there. | |
3784 | CODE is an rtx code such that (CODE OP0) is an rtx that describes | |
3785 | the value that is stored into TARGET. */ | |
3786 | ||
3787 | void | |
3788 | emit_unop_insn (int icode, rtx target, rtx op0, enum rtx_code code) | |
3789 | { | |
3790 | bool ok = maybe_emit_unop_insn (icode, target, op0, code); | |
3791 | gcc_assert (ok); | |
1f215c26 | 3792 | } |
3793 | \f | |
234ac9e8 | 3794 | struct no_conflict_data |
3795 | { | |
3796 | rtx target, first, insn; | |
3797 | bool must_stay; | |
3798 | }; | |
3799 | ||
e29831db | 3800 | /* Called via note_stores by emit_libcall_block. Set P->must_stay if |
3801 | the currently examined clobber / store has to stay in the list of | |
3802 | insns that constitute the actual libcall block. */ | |
234ac9e8 | 3803 | static void |
81a410b1 | 3804 | no_conflict_move_test (rtx dest, const_rtx set, void *p0) |
234ac9e8 | 3805 | { |
4077bf7a | 3806 | struct no_conflict_data *p= (struct no_conflict_data *) p0; |
234ac9e8 | 3807 | |
3808 | /* If this inns directly contributes to setting the target, it must stay. */ | |
3809 | if (reg_overlap_mentioned_p (p->target, dest)) | |
3810 | p->must_stay = true; | |
3811 | /* If we haven't committed to keeping any other insns in the list yet, | |
3812 | there is nothing more to check. */ | |
3813 | else if (p->insn == p->first) | |
3814 | return; | |
3815 | /* If this insn sets / clobbers a register that feeds one of the insns | |
3816 | already in the list, this insn has to stay too. */ | |
71fceab6 | 3817 | else if (reg_overlap_mentioned_p (dest, PATTERN (p->first)) |
3818 | || (CALL_P (p->first) && (find_reg_fusage (p->first, USE, dest))) | |
234ac9e8 | 3819 | || reg_used_between_p (dest, p->first, p->insn) |
3820 | /* Likewise if this insn depends on a register set by a previous | |
c0edfcc4 | 3821 | insn in the list, or if it sets a result (presumably a hard |
3822 | register) that is set or clobbered by a previous insn. | |
3823 | N.B. the modified_*_p (SET_DEST...) tests applied to a MEM | |
3824 | SET_DEST perform the former check on the address, and the latter | |
3825 | check on the MEM. */ | |
234ac9e8 | 3826 | || (GET_CODE (set) == SET |
3827 | && (modified_in_p (SET_SRC (set), p->first) | |
c0edfcc4 | 3828 | || modified_in_p (SET_DEST (set), p->first) |
3829 | || modified_between_p (SET_SRC (set), p->first, p->insn) | |
3830 | || modified_between_p (SET_DEST (set), p->first, p->insn)))) | |
234ac9e8 | 3831 | p->must_stay = true; |
3832 | } | |
3833 | ||
1f215c26 | 3834 | \f |
3835 | /* Emit code to make a call to a constant function or a library call. | |
3836 | ||
3837 | INSNS is a list containing all insns emitted in the call. | |
3838 | These insns leave the result in RESULT. Our block is to copy RESULT | |
3839 | to TARGET, which is logically equivalent to EQUIV. | |
3840 | ||
3841 | We first emit any insns that set a pseudo on the assumption that these are | |
3842 | loading constants into registers; doing so allows them to be safely cse'ed | |
3843 | between blocks. Then we emit all the other insns in the block, followed by | |
3844 | an insn to move RESULT to TARGET. This last insn will have a REQ_EQUAL | |
b31c801f | 3845 | note with an operand of EQUIV. */ |
3846 | ||
1f215c26 | 3847 | void |
3ad4992f | 3848 | emit_libcall_block (rtx insns, rtx target, rtx result, rtx equiv) |
1f215c26 | 3849 | { |
08852b5f | 3850 | rtx final_dest = target; |
b31c801f | 3851 | rtx prev, next, last, insn; |
1f215c26 | 3852 | |
08852b5f | 3853 | /* If this is a reg with REG_USERVAR_P set, then it could possibly turn |
3854 | into a MEM later. Protect the libcall block from this change. */ | |
3855 | if (! REG_P (target) || REG_USERVAR_P (target)) | |
3856 | target = gen_reg_rtx (GET_MODE (target)); | |
3ad4992f | 3857 | |
9c207309 | 3858 | /* If we're using non-call exceptions, a libcall corresponding to an |
3859 | operation that may trap may also trap. */ | |
3860 | if (flag_non_call_exceptions && may_trap_p (equiv)) | |
3861 | { | |
3862 | for (insn = insns; insn; insn = NEXT_INSN (insn)) | |
6d7dc5b9 | 3863 | if (CALL_P (insn)) |
9c207309 | 3864 | { |
3865 | rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX); | |
3ad4992f | 3866 | |
9c207309 | 3867 | if (note != 0 && INTVAL (XEXP (note, 0)) <= 0) |
3868 | remove_note (insn, note); | |
3869 | } | |
3870 | } | |
3871 | else | |
454c42da | 3872 | /* look for any CALL_INSNs in this sequence, and attach a REG_EH_REGION |
8c8b35e2 | 3873 | reg note to indicate that this call cannot throw or execute a nonlocal |
a0cae1a0 | 3874 | goto (unless there is already a REG_EH_REGION note, in which case |
c198dd74 | 3875 | we update it). */ |
9c207309 | 3876 | for (insn = insns; insn; insn = NEXT_INSN (insn)) |
6d7dc5b9 | 3877 | if (CALL_P (insn)) |
9c207309 | 3878 | { |
3879 | rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX); | |
3ad4992f | 3880 | |
9c207309 | 3881 | if (note != 0) |
6757f5d6 | 3882 | XEXP (note, 0) = constm1_rtx; |
9c207309 | 3883 | else |
a1ddb869 | 3884 | add_reg_note (insn, REG_EH_REGION, constm1_rtx); |
9c207309 | 3885 | } |
454c42da | 3886 | |
1f215c26 | 3887 | /* First emit all insns that set pseudos. Remove them from the list as |
63c77ac7 | 3888 | we go. Avoid insns that set pseudos which were referenced in previous |
13cf6a4c | 3889 | insns. These can be generated by move_by_pieces, for example, |
63c77ac7 | 3890 | to update an address. Similarly, avoid insns that reference things |
3891 | set in previous insns. */ | |
1f215c26 | 3892 | |
3893 | for (insn = insns; insn; insn = next) | |
3894 | { | |
3895 | rtx set = single_set (insn); | |
3896 | ||
3897 | next = NEXT_INSN (insn); | |
3898 | ||
8ad4c111 | 3899 | if (set != 0 && REG_P (SET_DEST (set)) |
536e04fb | 3900 | && REGNO (SET_DEST (set)) >= FIRST_PSEUDO_REGISTER) |
1f215c26 | 3901 | { |
536e04fb | 3902 | struct no_conflict_data data; |
3903 | ||
3904 | data.target = const0_rtx; | |
3905 | data.first = insns; | |
3906 | data.insn = insn; | |
3907 | data.must_stay = 0; | |
3908 | note_stores (PATTERN (insn), no_conflict_move_test, &data); | |
3909 | if (! data.must_stay) | |
3910 | { | |
3911 | if (PREV_INSN (insn)) | |
3912 | NEXT_INSN (PREV_INSN (insn)) = next; | |
3913 | else | |
3914 | insns = next; | |
1f215c26 | 3915 | |
536e04fb | 3916 | if (next) |
3917 | PREV_INSN (next) = PREV_INSN (insn); | |
1f215c26 | 3918 | |
536e04fb | 3919 | add_insn (insn); |
3920 | } | |
1f215c26 | 3921 | } |
227ea566 | 3922 | |
3923 | /* Some ports use a loop to copy large arguments onto the stack. | |
3924 | Don't move anything outside such a loop. */ | |
6d7dc5b9 | 3925 | if (LABEL_P (insn)) |
227ea566 | 3926 | break; |
1f215c26 | 3927 | } |
3928 | ||
3929 | prev = get_last_insn (); | |
3930 | ||
3931 | /* Write the remaining insns followed by the final copy. */ | |
3932 | ||
3933 | for (insn = insns; insn; insn = next) | |
3934 | { | |
3935 | next = NEXT_INSN (insn); | |
3936 | ||
3937 | add_insn (insn); | |
3938 | } | |
3939 | ||
3940 | last = emit_move_insn (target, result); | |
99bdde56 | 3941 | if (optab_handler (mov_optab, GET_MODE (target))->insn_code |
3c96cf42 | 3942 | != CODE_FOR_nothing) |
e29342dc | 3943 | set_unique_reg_note (last, REG_EQUAL, copy_rtx (equiv)); |
1f215c26 | 3944 | |
f6f723c2 | 3945 | if (final_dest != target) |
3946 | emit_move_insn (final_dest, target); | |
1f215c26 | 3947 | } |
3948 | \f | |
10ee3e0f | 3949 | /* Nonzero if we can perform a comparison of mode MODE straightforwardly. |
a4110d9a | 3950 | PURPOSE describes how this comparison will be used. CODE is the rtx |
3951 | comparison code we will be using. | |
3952 | ||
3953 | ??? Actually, CODE is slightly weaker than that. A target is still | |
3ad4992f | 3954 | required to implement all of the normal bcc operations, but not |
a4110d9a | 3955 | required to implement all (or any) of the unordered bcc operations. */ |
3ad4992f | 3956 | |
10ee3e0f | 3957 | int |
3ad4992f | 3958 | can_compare_p (enum rtx_code code, enum machine_mode mode, |
3959 | enum can_compare_purpose purpose) | |
1a29b174 | 3960 | { |
235155da | 3961 | rtx test; |
3962 | test = gen_rtx_fmt_ee (code, mode, const0_rtx, const0_rtx); | |
1a29b174 | 3963 | do |
3964 | { | |
235155da | 3965 | int icode; |
3966 | ||
10ee3e0f | 3967 | if (purpose == ccp_jump |
235155da | 3968 | && (icode = optab_handler (cbranch_optab, mode)->insn_code) != CODE_FOR_nothing |
3969 | && insn_data[icode].operand[0].predicate (test, mode)) | |
3970 | return 1; | |
3971 | if (purpose == ccp_store_flag | |
3972 | && (icode = optab_handler (cstore_optab, mode)->insn_code) != CODE_FOR_nothing | |
3973 | && insn_data[icode].operand[1].predicate (test, mode)) | |
3974 | return 1; | |
10ee3e0f | 3975 | if (purpose == ccp_cmov |
99bdde56 | 3976 | && optab_handler (cmov_optab, mode)->insn_code != CODE_FOR_nothing) |
10ee3e0f | 3977 | return 1; |
235155da | 3978 | |
1a29b174 | 3979 | mode = GET_MODE_WIDER_MODE (mode); |
235155da | 3980 | PUT_MODE (test, mode); |
10ee3e0f | 3981 | } |
3982 | while (mode != VOIDmode); | |
1a29b174 | 3983 | |
3984 | return 0; | |
3985 | } | |
3986 | ||
3987 | /* This function is called when we are going to emit a compare instruction that | |
3988 | compares the values found in *PX and *PY, using the rtl operator COMPARISON. | |
3989 | ||
3990 | *PMODE is the mode of the inputs (in case they are const_int). | |
3991 | *PUNSIGNEDP nonzero says that the operands are unsigned; | |
74f4459c | 3992 | this matters if they need to be widened (as given by METHODS). |
1f215c26 | 3993 | |
2b96c5f6 | 3994 | If they have mode BLKmode, then SIZE specifies the size of both operands. |
1f215c26 | 3995 | |
1a29b174 | 3996 | This function performs all the setup necessary so that the caller only has |
3997 | to emit a single comparison insn. This setup can involve doing a BLKmode | |
3998 | comparison or emitting a library call to perform the comparison if no insn | |
3999 | is available to handle it. | |
4000 | The values which are passed in through pointers can be modified; the caller | |
1fa3a8f6 | 4001 | should perform the comparison on the modified values. Constant |
4002 | comparisons must have already been folded. */ | |
1f215c26 | 4003 | |
2b96c5f6 | 4004 | static void |
74f4459c | 4005 | prepare_cmp_insn (rtx x, rtx y, enum rtx_code comparison, rtx size, |
4006 | int unsignedp, enum optab_methods methods, | |
4007 | rtx *ptest, enum machine_mode *pmode) | |
1f215c26 | 4008 | { |
1a29b174 | 4009 | enum machine_mode mode = *pmode; |
74f4459c | 4010 | rtx libfunc, test; |
4011 | enum machine_mode cmp_mode; | |
4012 | enum mode_class mclass; | |
4013 | ||
4014 | /* The other methods are not needed. */ | |
4015 | gcc_assert (methods == OPTAB_DIRECT || methods == OPTAB_WIDEN | |
4016 | || methods == OPTAB_LIB_WIDEN); | |
1f215c26 | 4017 | |
27f97b12 | 4018 | /* If we are optimizing, force expensive constants into a register. */ |
4019 | if (CONSTANT_P (x) && optimize | |
4020 | && (rtx_cost (x, COMPARE, optimize_insn_for_speed_p ()) | |
4021 | > COSTS_N_INSNS (1))) | |
4022 | x = force_reg (mode, x); | |
4023 | ||
4024 | if (CONSTANT_P (y) && optimize | |
4025 | && (rtx_cost (y, COMPARE, optimize_insn_for_speed_p ()) | |
4026 | > COSTS_N_INSNS (1))) | |
4027 | y = force_reg (mode, y); | |
4028 | ||
989c2a69 | 4029 | #ifdef HAVE_cc0 |
1fa3a8f6 | 4030 | /* Make sure if we have a canonical comparison. The RTL |
4031 | documentation states that canonical comparisons are required only | |
4032 | for targets which have cc0. */ | |
ce572eff | 4033 | gcc_assert (!CONSTANT_P (x) || CONSTANT_P (y)); |
989c2a69 | 4034 | #endif |
4035 | ||
1f215c26 | 4036 | /* Don't let both operands fail to indicate the mode. */ |
4037 | if (GET_MODE (x) == VOIDmode && GET_MODE (y) == VOIDmode) | |
4038 | x = force_reg (mode, x); | |
74f4459c | 4039 | if (mode == VOIDmode) |
4040 | mode = GET_MODE (x) != VOIDmode ? GET_MODE (x) : GET_MODE (y); | |
1f215c26 | 4041 | |
4042 | /* Handle all BLKmode compares. */ | |
4043 | ||
4044 | if (mode == BLKmode) | |
4045 | { | |
74f4459c | 4046 | enum machine_mode result_mode; |
0fbe5a3e | 4047 | enum insn_code cmp_code; |
4048 | tree length_type; | |
4049 | rtx libfunc; | |
1a29b174 | 4050 | rtx result; |
0fbe5a3e | 4051 | rtx opalign |
7a9a4287 | 4052 | = GEN_INT (MIN (MEM_ALIGN (x), MEM_ALIGN (y)) / BITS_PER_UNIT); |
1a29b174 | 4053 | |
ce572eff | 4054 | gcc_assert (size); |
0fbe5a3e | 4055 | |
0fbe5a3e | 4056 | /* Try to use a memory block compare insn - either cmpstr |
4057 | or cmpmem will do. */ | |
4058 | for (cmp_mode = GET_CLASS_NARROWEST_MODE (MODE_INT); | |
4059 | cmp_mode != VOIDmode; | |
4060 | cmp_mode = GET_MODE_WIDER_MODE (cmp_mode)) | |
b428c0a5 | 4061 | { |
0fbe5a3e | 4062 | cmp_code = cmpmem_optab[cmp_mode]; |
4063 | if (cmp_code == CODE_FOR_nothing) | |
4064 | cmp_code = cmpstr_optab[cmp_mode]; | |
6ac5504b | 4065 | if (cmp_code == CODE_FOR_nothing) |
4066 | cmp_code = cmpstrn_optab[cmp_mode]; | |
0fbe5a3e | 4067 | if (cmp_code == CODE_FOR_nothing) |
4068 | continue; | |
4069 | ||
4070 | /* Must make sure the size fits the insn's mode. */ | |
4071 | if ((GET_CODE (size) == CONST_INT | |
4072 | && INTVAL (size) >= (1 << GET_MODE_BITSIZE (cmp_mode))) | |
4073 | || (GET_MODE_BITSIZE (GET_MODE (size)) | |
4074 | > GET_MODE_BITSIZE (cmp_mode))) | |
4075 | continue; | |
4076 | ||
4077 | result_mode = insn_data[cmp_code].operand[0].mode; | |
b428c0a5 | 4078 | result = gen_reg_rtx (result_mode); |
0fbe5a3e | 4079 | size = convert_to_mode (cmp_mode, size, 1); |
4080 | emit_insn (GEN_FCN (cmp_code) (result, x, y, size, opalign)); | |
4081 | ||
74f4459c | 4082 | *ptest = gen_rtx_fmt_ee (comparison, VOIDmode, result, const0_rtx); |
4083 | *pmode = result_mode; | |
0fbe5a3e | 4084 | return; |
1f215c26 | 4085 | } |
0fbe5a3e | 4086 | |
74f4459c | 4087 | if (methods != OPTAB_LIB && methods != OPTAB_LIB_WIDEN) |
4088 | goto fail; | |
4089 | ||
f896c932 | 4090 | /* Otherwise call a library function, memcmp. */ |
0fbe5a3e | 4091 | libfunc = memcmp_libfunc; |
4092 | length_type = sizetype; | |
0fbe5a3e | 4093 | result_mode = TYPE_MODE (integer_type_node); |
4094 | cmp_mode = TYPE_MODE (length_type); | |
4095 | size = convert_to_mode (TYPE_MODE (length_type), size, | |
78a8ed03 | 4096 | TYPE_UNSIGNED (length_type)); |
0fbe5a3e | 4097 | |
2dd6f9ed | 4098 | result = emit_library_call_value (libfunc, 0, LCT_PURE, |
0fbe5a3e | 4099 | result_mode, 3, |
4100 | XEXP (x, 0), Pmode, | |
4101 | XEXP (y, 0), Pmode, | |
4102 | size, cmp_mode); | |
74f4459c | 4103 | |
4104 | *ptest = gen_rtx_fmt_ee (comparison, VOIDmode, result, const0_rtx); | |
1a29b174 | 4105 | *pmode = result_mode; |
1f215c26 | 4106 | return; |
4107 | } | |
4108 | ||
a2b9a662 | 4109 | /* Don't allow operands to the compare to trap, as that can put the |
4110 | compare and branch in different basic blocks. */ | |
4111 | if (flag_non_call_exceptions) | |
4112 | { | |
4113 | if (may_trap_p (x)) | |
4114 | x = force_reg (mode, x); | |
4115 | if (may_trap_p (y)) | |
4116 | y = force_reg (mode, y); | |
4117 | } | |
4118 | ||
8e58aded | 4119 | if (GET_MODE_CLASS (mode) == MODE_CC) |
4120 | { | |
74f4459c | 4121 | gcc_assert (can_compare_p (comparison, CCmode, ccp_jump)); |
4122 | *ptest = gen_rtx_fmt_ee (comparison, VOIDmode, x, y); | |
8e58aded | 4123 | return; |
4124 | } | |
1f215c26 | 4125 | |
74f4459c | 4126 | mclass = GET_MODE_CLASS (mode); |
4127 | test = gen_rtx_fmt_ee (comparison, VOIDmode, x, y); | |
4128 | cmp_mode = mode; | |
4129 | do | |
4130 | { | |
4131 | enum insn_code icode; | |
4132 | icode = optab_handler (cbranch_optab, cmp_mode)->insn_code; | |
4133 | if (icode != CODE_FOR_nothing | |
4134 | && insn_data[icode].operand[0].predicate (test, VOIDmode)) | |
4135 | { | |
4136 | rtx last = get_last_insn (); | |
4137 | rtx op0 = prepare_operand (icode, x, 1, mode, cmp_mode, unsignedp); | |
4138 | rtx op1 = prepare_operand (icode, y, 2, mode, cmp_mode, unsignedp); | |
4139 | if (op0 && op1 | |
4140 | && insn_data[icode].operand[1].predicate | |
4141 | (op0, insn_data[icode].operand[1].mode) | |
4142 | && insn_data[icode].operand[2].predicate | |
4143 | (op1, insn_data[icode].operand[2].mode)) | |
4144 | { | |
4145 | XEXP (test, 0) = op0; | |
4146 | XEXP (test, 1) = op1; | |
4147 | *ptest = test; | |
4148 | *pmode = cmp_mode; | |
4149 | return; | |
4150 | } | |
4151 | delete_insns_since (last); | |
4152 | } | |
4153 | ||
4154 | if (methods == OPTAB_DIRECT || !CLASS_HAS_WIDER_MODES_P (mclass)) | |
4155 | break; | |
4156 | cmp_mode = GET_MODE_WIDER_MODE (cmp_mode); | |
4157 | } | |
4158 | while (cmp_mode != VOIDmode); | |
4159 | ||
4160 | if (methods != OPTAB_LIB_WIDEN) | |
4161 | goto fail; | |
4162 | ||
4163 | if (!SCALAR_FLOAT_MODE_P (mode)) | |
1f215c26 | 4164 | { |
15cd8ddf | 4165 | rtx result; |
4166 | ||
74f4459c | 4167 | /* Handle a libcall just for the mode we are using. */ |
4168 | libfunc = optab_libfunc (cmp_optab, mode); | |
4169 | gcc_assert (libfunc); | |
4170 | ||
1f215c26 | 4171 | /* If we want unsigned, and this mode has a distinct unsigned |
4172 | comparison routine, use that. */ | |
f36b9f69 | 4173 | if (unsignedp) |
4174 | { | |
91020a82 | 4175 | rtx ulibfunc = optab_libfunc (ucmp_optab, mode); |
4176 | if (ulibfunc) | |
4177 | libfunc = ulibfunc; | |
f36b9f69 | 4178 | } |
1f215c26 | 4179 | |
2dd6f9ed | 4180 | result = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST, |
0ef89dfd | 4181 | targetm.libgcc_cmp_return_mode (), |
4182 | 2, x, mode, y, mode); | |
15cd8ddf | 4183 | |
989816a4 | 4184 | /* There are two kinds of comparison routines. Biased routines |
4185 | return 0/1/2, and unbiased routines return -1/0/1. Other parts | |
4186 | of gcc expect that the comparison operation is equivalent | |
4187 | to the modified comparison. For signed comparisons compare the | |
4188 | result against 1 in the biased case, and zero in the unbiased | |
4189 | case. For unsigned comparisons always compare against 1 after | |
9ca2c29a | 4190 | biasing the unbiased result by adding 1. This gives us a way to |
989816a4 | 4191 | represent LTU. */ |
74f4459c | 4192 | x = result; |
4193 | y = const1_rtx; | |
989816a4 | 4194 | |
4195 | if (!TARGET_LIB_INT_CMP_BIASED) | |
30e9913f | 4196 | { |
74f4459c | 4197 | if (unsignedp) |
4198 | x = plus_constant (result, 1); | |
989816a4 | 4199 | else |
74f4459c | 4200 | y = const0_rtx; |
30e9913f | 4201 | } |
74f4459c | 4202 | |
4203 | *pmode = word_mode; | |
4204 | prepare_cmp_insn (x, y, comparison, NULL_RTX, unsignedp, methods, | |
4205 | ptest, pmode); | |
1f215c26 | 4206 | } |
74f4459c | 4207 | else |
4208 | prepare_float_lib_cmp (x, y, comparison, ptest, pmode); | |
1f215c26 | 4209 | |
74f4459c | 4210 | return; |
4211 | ||
4212 | fail: | |
4213 | *ptest = NULL_RTX; | |
1f215c26 | 4214 | } |
4215 | ||
1a29b174 | 4216 | /* Before emitting an insn with code ICODE, make sure that X, which is going |
4217 | to be used for operand OPNUM of the insn, is converted from mode MODE to | |
20dd417a | 4218 | WIDER_MODE (UNSIGNEDP determines whether it is an unsigned conversion), and |
1a29b174 | 4219 | that it is accepted by the operand predicate. Return the new value. */ |
ef6c17ed | 4220 | |
74f4459c | 4221 | rtx |
3ad4992f | 4222 | prepare_operand (int icode, rtx x, int opnum, enum machine_mode mode, |
4223 | enum machine_mode wider_mode, int unsignedp) | |
1a29b174 | 4224 | { |
1a29b174 | 4225 | if (mode != wider_mode) |
4226 | x = convert_modes (wider_mode, mode, x, unsignedp); | |
4227 | ||
ce572eff | 4228 | if (!insn_data[icode].operand[opnum].predicate |
6357eaae | 4229 | (x, insn_data[icode].operand[opnum].mode)) |
e79a81b2 | 4230 | { |
4629257b | 4231 | if (reload_completed) |
e79a81b2 | 4232 | return NULL_RTX; |
4233 | x = copy_to_mode_reg (insn_data[icode].operand[opnum].mode, x); | |
4234 | } | |
4235 | ||
1a29b174 | 4236 | return x; |
4237 | } | |
4238 | ||
4239 | /* Subroutine of emit_cmp_and_jump_insns; this function is called when we know | |
74f4459c | 4240 | we can do the branch. */ |
1a29b174 | 4241 | |
4242 | static void | |
74f4459c | 4243 | emit_cmp_and_jump_insn_1 (rtx test, enum machine_mode mode, rtx label) |
1a29b174 | 4244 | { |
74f4459c | 4245 | enum machine_mode optab_mode; |
4246 | enum mode_class mclass; | |
4247 | enum insn_code icode; | |
1a29b174 | 4248 | |
74f4459c | 4249 | mclass = GET_MODE_CLASS (mode); |
4250 | optab_mode = (mclass == MODE_CC) ? CCmode : mode; | |
4251 | icode = optab_handler (cbranch_optab, optab_mode)->insn_code; | |
2045cdd4 | 4252 | |
74f4459c | 4253 | gcc_assert (icode != CODE_FOR_nothing); |
4254 | gcc_assert (insn_data[icode].operand[0].predicate (test, VOIDmode)); | |
4255 | emit_jump_insn (GEN_FCN (icode) (test, XEXP (test, 0), XEXP (test, 1), label)); | |
1a29b174 | 4256 | } |
4257 | ||
989c2a69 | 4258 | /* Generate code to compare X with Y so that the condition codes are |
4259 | set and to jump to LABEL if the condition is true. If X is a | |
4260 | constant and Y is not a constant, then the comparison is swapped to | |
4261 | ensure that the comparison RTL has the canonical form. | |
4262 | ||
5a894bc6 | 4263 | UNSIGNEDP nonzero says that X and Y are unsigned; this matters if they |
74f4459c | 4264 | need to be widened. UNSIGNEDP is also used to select the proper |
4265 | branch condition code. | |
989c2a69 | 4266 | |
2b96c5f6 | 4267 | If X and Y have mode BLKmode, then SIZE specifies the size of both X and Y. |
989c2a69 | 4268 | |
5a894bc6 | 4269 | MODE is the mode of the inputs (in case they are const_int). |
4270 | ||
74f4459c | 4271 | COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.). |
4272 | It will be potentially converted into an unsigned variant based on | |
4273 | UNSIGNEDP to select a proper jump instruction. */ | |
989c2a69 | 4274 | |
4275 | void | |
3ad4992f | 4276 | emit_cmp_and_jump_insns (rtx x, rtx y, enum rtx_code comparison, rtx size, |
4277 | enum machine_mode mode, int unsignedp, rtx label) | |
989c2a69 | 4278 | { |
f5ef1390 | 4279 | rtx op0 = x, op1 = y; |
74f4459c | 4280 | rtx test; |
f5ef1390 | 4281 | |
4282 | /* Swap operands and condition to ensure canonical RTL. */ | |
4283 | if (swap_commutative_operands_p (x, y)) | |
989c2a69 | 4284 | { |
f5ef1390 | 4285 | op0 = y, op1 = x; |
4286 | comparison = swap_condition (comparison); | |
989c2a69 | 4287 | } |
dfd1e7f2 | 4288 | |
4289 | #ifdef HAVE_cc0 | |
1fa3a8f6 | 4290 | /* If OP0 is still a constant, then both X and Y must be constants. |
4291 | Force X into a register to create canonical RTL. */ | |
dfd1e7f2 | 4292 | if (CONSTANT_P (op0)) |
4293 | op0 = force_reg (mode, op0); | |
4294 | #endif | |
4295 | ||
5a894bc6 | 4296 | if (unsignedp) |
4297 | comparison = unsigned_condition (comparison); | |
2b96c5f6 | 4298 | |
74f4459c | 4299 | prepare_cmp_insn (op0, op1, comparison, size, unsignedp, OPTAB_LIB_WIDEN, |
4300 | &test, &mode); | |
4301 | emit_cmp_and_jump_insn_1 (test, mode, label); | |
1a29b174 | 4302 | } |
4303 | ||
1f215c26 | 4304 | \f |
4305 | /* Emit a library call comparison between floating point X and Y. | |
4306 | COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.). */ | |
4307 | ||
6f71c48d | 4308 | static void |
74f4459c | 4309 | prepare_float_lib_cmp (rtx x, rtx y, enum rtx_code comparison, |
4310 | rtx *ptest, enum machine_mode *pmode) | |
1f215c26 | 4311 | { |
c88a6ebd | 4312 | enum rtx_code swapped = swap_condition (comparison); |
30e9913f | 4313 | enum rtx_code reversed = reverse_condition_maybe_unordered (comparison); |
c88a6ebd | 4314 | enum machine_mode orig_mode = GET_MODE (x); |
ea32e033 | 4315 | enum machine_mode mode, cmp_mode; |
95120276 | 4316 | rtx value, target, insns, equiv; |
460f974d | 4317 | rtx libfunc = 0; |
30e9913f | 4318 | bool reversed_p = false; |
ea32e033 | 4319 | cmp_mode = targetm.libgcc_cmp_return_mode (); |
1f215c26 | 4320 | |
ba592904 | 4321 | for (mode = orig_mode; |
4322 | mode != VOIDmode; | |
4323 | mode = GET_MODE_WIDER_MODE (mode)) | |
1f215c26 | 4324 | { |
d5a9653a | 4325 | if (code_to_optab[comparison] |
4326 | && (libfunc = optab_libfunc (code_to_optab[comparison], mode))) | |
c88a6ebd | 4327 | break; |
1f215c26 | 4328 | |
d5a9653a | 4329 | if (code_to_optab[swapped] |
4330 | && (libfunc = optab_libfunc (code_to_optab[swapped], mode))) | |
1f215c26 | 4331 | { |
c88a6ebd | 4332 | rtx tmp; |
4333 | tmp = x; x = y; y = tmp; | |
4334 | comparison = swapped; | |
4335 | break; | |
1f215c26 | 4336 | } |
1f215c26 | 4337 | |
d5a9653a | 4338 | if (code_to_optab[reversed] |
4339 | && (libfunc = optab_libfunc (code_to_optab[reversed], mode)) | |
30e9913f | 4340 | && FLOAT_LIB_COMPARE_RETURNS_BOOL (mode, reversed)) |
4341 | { | |
4342 | comparison = reversed; | |
4343 | reversed_p = true; | |
4344 | break; | |
4345 | } | |
4346 | } | |
7d3f6cc7 | 4347 | |
ce572eff | 4348 | gcc_assert (mode != VOIDmode); |
460f974d | 4349 | |
c88a6ebd | 4350 | if (mode != orig_mode) |
4351 | { | |
4352 | x = convert_to_mode (mode, x, 0); | |
4353 | y = convert_to_mode (mode, y, 0); | |
4354 | } | |
4355 | ||
ac324f99 | 4356 | /* Attach a REG_EQUAL note describing the semantics of the libcall to |
4357 | the RTL. The allows the RTL optimizers to delete the libcall if the | |
4358 | condition can be determined at compile-time. */ | |
4359 | if (comparison == UNORDERED) | |
4360 | { | |
ea32e033 | 4361 | rtx temp = simplify_gen_relational (NE, cmp_mode, mode, x, x); |
4362 | equiv = simplify_gen_relational (NE, cmp_mode, mode, y, y); | |
4363 | equiv = simplify_gen_ternary (IF_THEN_ELSE, cmp_mode, cmp_mode, | |
ac324f99 | 4364 | temp, const_true_rtx, equiv); |
4365 | } | |
4366 | else | |
4367 | { | |
ea32e033 | 4368 | equiv = simplify_gen_relational (comparison, cmp_mode, mode, x, y); |
ac324f99 | 4369 | if (! FLOAT_LIB_COMPARE_RETURNS_BOOL (mode, comparison)) |
713cb52a | 4370 | { |
ac324f99 | 4371 | rtx true_rtx, false_rtx; |
95120276 | 4372 | |
ac324f99 | 4373 | switch (comparison) |
4374 | { | |
4375 | case EQ: | |
4376 | true_rtx = const0_rtx; | |
4377 | false_rtx = const_true_rtx; | |
4378 | break; | |
4379 | ||
4380 | case NE: | |
4381 | true_rtx = const_true_rtx; | |
4382 | false_rtx = const0_rtx; | |
4383 | break; | |
4384 | ||
4385 | case GT: | |
4386 | true_rtx = const1_rtx; | |
4387 | false_rtx = const0_rtx; | |
4388 | break; | |
4389 | ||
4390 | case GE: | |
4391 | true_rtx = const0_rtx; | |
4392 | false_rtx = constm1_rtx; | |
4393 | break; | |
4394 | ||
4395 | case LT: | |
4396 | true_rtx = constm1_rtx; | |
4397 | false_rtx = const0_rtx; | |
4398 | break; | |
4399 | ||
4400 | case LE: | |
4401 | true_rtx = const0_rtx; | |
4402 | false_rtx = const1_rtx; | |
4403 | break; | |
4404 | ||
4405 | default: | |
ce572eff | 4406 | gcc_unreachable (); |
713cb52a | 4407 | } |
ea32e033 | 4408 | equiv = simplify_gen_ternary (IF_THEN_ELSE, cmp_mode, cmp_mode, |
ac324f99 | 4409 | equiv, true_rtx, false_rtx); |
713cb52a | 4410 | } |
4411 | } | |
95120276 | 4412 | |
4413 | start_sequence (); | |
4414 | value = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST, | |
ea32e033 | 4415 | cmp_mode, 2, x, mode, y, mode); |
95120276 | 4416 | insns = get_insns (); |
4417 | end_sequence (); | |
4418 | ||
ea32e033 | 4419 | target = gen_reg_rtx (cmp_mode); |
95120276 | 4420 | emit_libcall_block (insns, target, value, equiv); |
4421 | ||
c88a6ebd | 4422 | if (comparison == UNORDERED |
4423 | || FLOAT_LIB_COMPARE_RETURNS_BOOL (mode, comparison)) | |
30e9913f | 4424 | comparison = reversed_p ? EQ : NE; |
c88a6ebd | 4425 | |
74f4459c | 4426 | *ptest = gen_rtx_fmt_ee (comparison, VOIDmode, target, const0_rtx); |
ea32e033 | 4427 | *pmode = cmp_mode; |
1f215c26 | 4428 | } |
4429 | \f | |
4430 | /* Generate code to indirectly jump to a location given in the rtx LOC. */ | |
4431 | ||
4432 | void | |
3ad4992f | 4433 | emit_indirect_jump (rtx loc) |
1f215c26 | 4434 | { |
ce572eff | 4435 | if (!insn_data[(int) CODE_FOR_indirect_jump].operand[0].predicate |
4436 | (loc, Pmode)) | |
5d3cfda2 | 4437 | loc = copy_to_mode_reg (Pmode, loc); |
1f215c26 | 4438 | |
4439 | emit_jump_insn (gen_indirect_jump (loc)); | |
5fb13e54 | 4440 | emit_barrier (); |
1f215c26 | 4441 | } |
4442 | \f | |
62528147 | 4443 | #ifdef HAVE_conditional_move |
4444 | ||
4445 | /* Emit a conditional move instruction if the machine supports one for that | |
4446 | condition and machine mode. | |
4447 | ||
4448 | OP0 and OP1 are the operands that should be compared using CODE. CMODE is | |
4449 | the mode to use should they be constants. If it is VOIDmode, they cannot | |
4450 | both be constants. | |
4451 | ||
4452 | OP2 should be stored in TARGET if the comparison is true, otherwise OP3 | |
4453 | should be stored there. MODE is the mode to use should they be constants. | |
4454 | If it is VOIDmode, they cannot both be constants. | |
4455 | ||
4456 | The result is either TARGET (perhaps modified) or NULL_RTX if the operation | |
4457 | is not supported. */ | |
4458 | ||
4459 | rtx | |
3ad4992f | 4460 | emit_conditional_move (rtx target, enum rtx_code code, rtx op0, rtx op1, |
4461 | enum machine_mode cmode, rtx op2, rtx op3, | |
4462 | enum machine_mode mode, int unsignedp) | |
62528147 | 4463 | { |
4464 | rtx tem, subtarget, comparison, insn; | |
4465 | enum insn_code icode; | |
09f800b9 | 4466 | enum rtx_code reversed; |
62528147 | 4467 | |
4468 | /* If one operand is constant, make it the second one. Only do this | |
4469 | if the other operand is not constant as well. */ | |
4470 | ||
09f800b9 | 4471 | if (swap_commutative_operands_p (op0, op1)) |
62528147 | 4472 | { |
4473 | tem = op0; | |
4474 | op0 = op1; | |
4475 | op1 = tem; | |
4476 | code = swap_condition (code); | |
4477 | } | |
4478 | ||
7014838c | 4479 | /* get_condition will prefer to generate LT and GT even if the old |
4480 | comparison was against zero, so undo that canonicalization here since | |
4481 | comparisons against zero are cheaper. */ | |
9a1ec826 | 4482 | if (code == LT && op1 == const1_rtx) |
7014838c | 4483 | code = LE, op1 = const0_rtx; |
9a1ec826 | 4484 | else if (code == GT && op1 == constm1_rtx) |
7014838c | 4485 | code = GE, op1 = const0_rtx; |
4486 | ||
62528147 | 4487 | if (cmode == VOIDmode) |
4488 | cmode = GET_MODE (op0); | |
4489 | ||
09f800b9 | 4490 | if (swap_commutative_operands_p (op2, op3) |
4491 | && ((reversed = reversed_comparison_code_parts (code, op0, op1, NULL)) | |
4492 | != UNKNOWN)) | |
62528147 | 4493 | { |
4494 | tem = op2; | |
4495 | op2 = op3; | |
4496 | op3 = tem; | |
09f800b9 | 4497 | code = reversed; |
62528147 | 4498 | } |
4499 | ||
4500 | if (mode == VOIDmode) | |
4501 | mode = GET_MODE (op2); | |
4502 | ||
4503 | icode = movcc_gen_code[mode]; | |
4504 | ||
4505 | if (icode == CODE_FOR_nothing) | |
4506 | return 0; | |
4507 | ||
0a534ba7 | 4508 | if (!target) |
62528147 | 4509 | target = gen_reg_rtx (mode); |
4510 | ||
4511 | subtarget = target; | |
4512 | ||
62528147 | 4513 | /* If the insn doesn't accept these operands, put them in pseudos. */ |
4514 | ||
ce572eff | 4515 | if (!insn_data[icode].operand[0].predicate |
6357eaae | 4516 | (subtarget, insn_data[icode].operand[0].mode)) |
4517 | subtarget = gen_reg_rtx (insn_data[icode].operand[0].mode); | |
62528147 | 4518 | |
ce572eff | 4519 | if (!insn_data[icode].operand[2].predicate |
6357eaae | 4520 | (op2, insn_data[icode].operand[2].mode)) |
4521 | op2 = copy_to_mode_reg (insn_data[icode].operand[2].mode, op2); | |
62528147 | 4522 | |
ce572eff | 4523 | if (!insn_data[icode].operand[3].predicate |
6357eaae | 4524 | (op3, insn_data[icode].operand[3].mode)) |
4525 | op3 = copy_to_mode_reg (insn_data[icode].operand[3].mode, op3); | |
62528147 | 4526 | |
74f4459c | 4527 | /* Everything should now be in the suitable form. */ |
62528147 | 4528 | |
74f4459c | 4529 | code = unsignedp ? unsigned_condition (code) : code; |
4530 | comparison = simplify_gen_relational (code, VOIDmode, cmode, op0, op1); | |
62528147 | 4531 | |
3cc4218a | 4532 | /* We can get const0_rtx or const_true_rtx in some circumstances. Just |
4533 | return NULL and let the caller figure out how best to deal with this | |
4534 | situation. */ | |
74f4459c | 4535 | if (!COMPARISON_P (comparison)) |
3cc4218a | 4536 | return NULL_RTX; |
3ad4992f | 4537 | |
74f4459c | 4538 | do_pending_stack_adjust (); |
4539 | start_sequence (); | |
4540 | prepare_cmp_insn (XEXP (comparison, 0), XEXP (comparison, 1), | |
4541 | GET_CODE (comparison), NULL_RTX, unsignedp, OPTAB_WIDEN, | |
4542 | &comparison, &cmode); | |
4543 | if (!comparison) | |
4544 | insn = NULL_RTX; | |
4545 | else | |
4546 | insn = GEN_FCN (icode) (subtarget, comparison, op2, op3); | |
62528147 | 4547 | |
4548 | /* If that failed, then give up. */ | |
4549 | if (insn == 0) | |
74f4459c | 4550 | { |
4551 | end_sequence (); | |
4552 | return 0; | |
4553 | } | |
62528147 | 4554 | |
4555 | emit_insn (insn); | |
74f4459c | 4556 | insn = get_insns (); |
4557 | end_sequence (); | |
4558 | emit_insn (insn); | |
62528147 | 4559 | if (subtarget != target) |
4560 | convert_move (target, subtarget, 0); | |
4561 | ||
4562 | return target; | |
4563 | } | |
4564 | ||
7fd957fe | 4565 | /* Return nonzero if a conditional move of mode MODE is supported. |
62528147 | 4566 | |
4567 | This function is for combine so it can tell whether an insn that looks | |
4568 | like a conditional move is actually supported by the hardware. If we | |
4569 | guess wrong we lose a bit on optimization, but that's it. */ | |
4570 | /* ??? sparc64 supports conditionally moving integers values based on fp | |
4571 | comparisons, and vice versa. How do we handle them? */ | |
4572 | ||
4573 | int | |
3ad4992f | 4574 | can_conditionally_move_p (enum machine_mode mode) |
62528147 | 4575 | { |
4576 | if (movcc_gen_code[mode] != CODE_FOR_nothing) | |
4577 | return 1; | |
4578 | ||
4579 | return 0; | |
4580 | } | |
4581 | ||
4582 | #endif /* HAVE_conditional_move */ | |
d3da2ad8 | 4583 | |
4584 | /* Emit a conditional addition instruction if the machine supports one for that | |
4585 | condition and machine mode. | |
4586 | ||
4587 | OP0 and OP1 are the operands that should be compared using CODE. CMODE is | |
4588 | the mode to use should they be constants. If it is VOIDmode, they cannot | |
4589 | both be constants. | |
4590 | ||
4591 | OP2 should be stored in TARGET if the comparison is true, otherwise OP2+OP3 | |
4592 | should be stored there. MODE is the mode to use should they be constants. | |
4593 | If it is VOIDmode, they cannot both be constants. | |
4594 | ||
4595 | The result is either TARGET (perhaps modified) or NULL_RTX if the operation | |
4596 | is not supported. */ | |
4597 | ||
4598 | rtx | |
3ad4992f | 4599 | emit_conditional_add (rtx target, enum rtx_code code, rtx op0, rtx op1, |
4600 | enum machine_mode cmode, rtx op2, rtx op3, | |
4601 | enum machine_mode mode, int unsignedp) | |
d3da2ad8 | 4602 | { |
4603 | rtx tem, subtarget, comparison, insn; | |
4604 | enum insn_code icode; | |
4605 | enum rtx_code reversed; | |
4606 | ||
4607 | /* If one operand is constant, make it the second one. Only do this | |
4608 | if the other operand is not constant as well. */ | |
4609 | ||
4610 | if (swap_commutative_operands_p (op0, op1)) | |
4611 | { | |
4612 | tem = op0; | |
4613 | op0 = op1; | |
4614 | op1 = tem; | |
4615 | code = swap_condition (code); | |
4616 | } | |
4617 | ||
4618 | /* get_condition will prefer to generate LT and GT even if the old | |
4619 | comparison was against zero, so undo that canonicalization here since | |
4620 | comparisons against zero are cheaper. */ | |
9a1ec826 | 4621 | if (code == LT && op1 == const1_rtx) |
d3da2ad8 | 4622 | code = LE, op1 = const0_rtx; |
9a1ec826 | 4623 | else if (code == GT && op1 == constm1_rtx) |
d3da2ad8 | 4624 | code = GE, op1 = const0_rtx; |
4625 | ||
4626 | if (cmode == VOIDmode) | |
4627 | cmode = GET_MODE (op0); | |
4628 | ||
4629 | if (swap_commutative_operands_p (op2, op3) | |
4630 | && ((reversed = reversed_comparison_code_parts (code, op0, op1, NULL)) | |
4631 | != UNKNOWN)) | |
4632 | { | |
4633 | tem = op2; | |
4634 | op2 = op3; | |
4635 | op3 = tem; | |
4636 | code = reversed; | |
4637 | } | |
4638 | ||
4639 | if (mode == VOIDmode) | |
4640 | mode = GET_MODE (op2); | |
4641 | ||
99bdde56 | 4642 | icode = optab_handler (addcc_optab, mode)->insn_code; |
d3da2ad8 | 4643 | |
4644 | if (icode == CODE_FOR_nothing) | |
4645 | return 0; | |
4646 | ||
0a534ba7 | 4647 | if (!target) |
d3da2ad8 | 4648 | target = gen_reg_rtx (mode); |
4649 | ||
d3da2ad8 | 4650 | /* If the insn doesn't accept these operands, put them in pseudos. */ |
4651 | ||
ce572eff | 4652 | if (!insn_data[icode].operand[0].predicate |
0a534ba7 | 4653 | (target, insn_data[icode].operand[0].mode)) |
d3da2ad8 | 4654 | subtarget = gen_reg_rtx (insn_data[icode].operand[0].mode); |
0a534ba7 | 4655 | else |
4656 | subtarget = target; | |
d3da2ad8 | 4657 | |
ce572eff | 4658 | if (!insn_data[icode].operand[2].predicate |
d3da2ad8 | 4659 | (op2, insn_data[icode].operand[2].mode)) |
4660 | op2 = copy_to_mode_reg (insn_data[icode].operand[2].mode, op2); | |
4661 | ||
ce572eff | 4662 | if (!insn_data[icode].operand[3].predicate |
d3da2ad8 | 4663 | (op3, insn_data[icode].operand[3].mode)) |
4664 | op3 = copy_to_mode_reg (insn_data[icode].operand[3].mode, op3); | |
4665 | ||
74f4459c | 4666 | /* Everything should now be in the suitable form. */ |
d3da2ad8 | 4667 | |
74f4459c | 4668 | code = unsignedp ? unsigned_condition (code) : code; |
4669 | comparison = simplify_gen_relational (code, VOIDmode, cmode, op0, op1); | |
d3da2ad8 | 4670 | |
d3da2ad8 | 4671 | /* We can get const0_rtx or const_true_rtx in some circumstances. Just |
4672 | return NULL and let the caller figure out how best to deal with this | |
4673 | situation. */ | |
74f4459c | 4674 | if (!COMPARISON_P (comparison)) |
d3da2ad8 | 4675 | return NULL_RTX; |
3ad4992f | 4676 | |
74f4459c | 4677 | do_pending_stack_adjust (); |
4678 | start_sequence (); | |
4679 | prepare_cmp_insn (XEXP (comparison, 0), XEXP (comparison, 1), | |
4680 | GET_CODE (comparison), NULL_RTX, unsignedp, OPTAB_WIDEN, | |
4681 | &comparison, &cmode); | |
4682 | if (!comparison) | |
4683 | insn = NULL_RTX; | |
4684 | else | |
4685 | insn = GEN_FCN (icode) (subtarget, comparison, op2, op3); | |
d3da2ad8 | 4686 | |
4687 | /* If that failed, then give up. */ | |
4688 | if (insn == 0) | |
74f4459c | 4689 | { |
4690 | end_sequence (); | |
4691 | return 0; | |
4692 | } | |
d3da2ad8 | 4693 | |
4694 | emit_insn (insn); | |
74f4459c | 4695 | insn = get_insns (); |
4696 | end_sequence (); | |
4697 | emit_insn (insn); | |
d3da2ad8 | 4698 | if (subtarget != target) |
4699 | convert_move (target, subtarget, 0); | |
4700 | ||
4701 | return target; | |
4702 | } | |
62528147 | 4703 | \f |
39810676 | 4704 | /* These functions attempt to generate an insn body, rather than |
4705 | emitting the insn, but if the gen function already emits them, we | |
0a534ba7 | 4706 | make no attempt to turn them back into naked patterns. */ |
1f215c26 | 4707 | |
4708 | /* Generate and return an insn body to add Y to X. */ | |
4709 | ||
4710 | rtx | |
3ad4992f | 4711 | gen_add2_insn (rtx x, rtx y) |
1f215c26 | 4712 | { |
99bdde56 | 4713 | int icode = (int) optab_handler (add_optab, GET_MODE (x))->insn_code; |
1f215c26 | 4714 | |
ce572eff | 4715 | gcc_assert (insn_data[icode].operand[0].predicate |
4716 | (x, insn_data[icode].operand[0].mode)); | |
4717 | gcc_assert (insn_data[icode].operand[1].predicate | |
4718 | (x, insn_data[icode].operand[1].mode)); | |
4719 | gcc_assert (insn_data[icode].operand[2].predicate | |
4720 | (y, insn_data[icode].operand[2].mode)); | |
1f215c26 | 4721 | |
ce572eff | 4722 | return GEN_FCN (icode) (x, x, y); |
1f215c26 | 4723 | } |
4724 | ||
d8fc4d0b | 4725 | /* Generate and return an insn body to add r1 and c, |
4726 | storing the result in r0. */ | |
f36b9f69 | 4727 | |
d8fc4d0b | 4728 | rtx |
3ad4992f | 4729 | gen_add3_insn (rtx r0, rtx r1, rtx c) |
d8fc4d0b | 4730 | { |
99bdde56 | 4731 | int icode = (int) optab_handler (add_optab, GET_MODE (r0))->insn_code; |
d8fc4d0b | 4732 | |
2fd3f4b5 | 4733 | if (icode == CODE_FOR_nothing |
ce572eff | 4734 | || !(insn_data[icode].operand[0].predicate |
4735 | (r0, insn_data[icode].operand[0].mode)) | |
4736 | || !(insn_data[icode].operand[1].predicate | |
4737 | (r1, insn_data[icode].operand[1].mode)) | |
4738 | || !(insn_data[icode].operand[2].predicate | |
4739 | (c, insn_data[icode].operand[2].mode))) | |
d8fc4d0b | 4740 | return NULL_RTX; |
4741 | ||
ce572eff | 4742 | return GEN_FCN (icode) (r0, r1, c); |
d8fc4d0b | 4743 | } |
4744 | ||
1f215c26 | 4745 | int |
3ad4992f | 4746 | have_add2_insn (rtx x, rtx y) |
1f215c26 | 4747 | { |
c299d9c8 | 4748 | int icode; |
4749 | ||
ce572eff | 4750 | gcc_assert (GET_MODE (x) != VOIDmode); |
c299d9c8 | 4751 | |
99bdde56 | 4752 | icode = (int) optab_handler (add_optab, GET_MODE (x))->insn_code; |
c299d9c8 | 4753 | |
4754 | if (icode == CODE_FOR_nothing) | |
4755 | return 0; | |
4756 | ||
ce572eff | 4757 | if (!(insn_data[icode].operand[0].predicate |
4758 | (x, insn_data[icode].operand[0].mode)) | |
4759 | || !(insn_data[icode].operand[1].predicate | |
4760 | (x, insn_data[icode].operand[1].mode)) | |
4761 | || !(insn_data[icode].operand[2].predicate | |
4762 | (y, insn_data[icode].operand[2].mode))) | |
c299d9c8 | 4763 | return 0; |
4764 | ||
4765 | return 1; | |
1f215c26 | 4766 | } |
4767 | ||
4768 | /* Generate and return an insn body to subtract Y from X. */ | |
4769 | ||
4770 | rtx | |
3ad4992f | 4771 | gen_sub2_insn (rtx x, rtx y) |
1f215c26 | 4772 | { |
99bdde56 | 4773 | int icode = (int) optab_handler (sub_optab, GET_MODE (x))->insn_code; |
1f215c26 | 4774 | |
ce572eff | 4775 | gcc_assert (insn_data[icode].operand[0].predicate |
4776 | (x, insn_data[icode].operand[0].mode)); | |
4777 | gcc_assert (insn_data[icode].operand[1].predicate | |
4778 | (x, insn_data[icode].operand[1].mode)); | |
4779 | gcc_assert (insn_data[icode].operand[2].predicate | |
4780 | (y, insn_data[icode].operand[2].mode)); | |
1f215c26 | 4781 | |
ce572eff | 4782 | return GEN_FCN (icode) (x, x, y); |
1f215c26 | 4783 | } |
4784 | ||
ad99e708 | 4785 | /* Generate and return an insn body to subtract r1 and c, |
4786 | storing the result in r0. */ | |
f36b9f69 | 4787 | |
ad99e708 | 4788 | rtx |
3ad4992f | 4789 | gen_sub3_insn (rtx r0, rtx r1, rtx c) |
ad99e708 | 4790 | { |
99bdde56 | 4791 | int icode = (int) optab_handler (sub_optab, GET_MODE (r0))->insn_code; |
ad99e708 | 4792 | |
2fd3f4b5 | 4793 | if (icode == CODE_FOR_nothing |
ce572eff | 4794 | || !(insn_data[icode].operand[0].predicate |
4795 | (r0, insn_data[icode].operand[0].mode)) | |
4796 | || !(insn_data[icode].operand[1].predicate | |
4797 | (r1, insn_data[icode].operand[1].mode)) | |
4798 | || !(insn_data[icode].operand[2].predicate | |
4799 | (c, insn_data[icode].operand[2].mode))) | |
ad99e708 | 4800 | return NULL_RTX; |
4801 | ||
ce572eff | 4802 | return GEN_FCN (icode) (r0, r1, c); |
ad99e708 | 4803 | } |
4804 | ||
1f215c26 | 4805 | int |
3ad4992f | 4806 | have_sub2_insn (rtx x, rtx y) |
1f215c26 | 4807 | { |
c299d9c8 | 4808 | int icode; |
4809 | ||
ce572eff | 4810 | gcc_assert (GET_MODE (x) != VOIDmode); |
c299d9c8 | 4811 | |
99bdde56 | 4812 | icode = (int) optab_handler (sub_optab, GET_MODE (x))->insn_code; |
c299d9c8 | 4813 | |
4814 | if (icode == CODE_FOR_nothing) | |
4815 | return 0; | |
4816 | ||
ce572eff | 4817 | if (!(insn_data[icode].operand[0].predicate |
4818 | (x, insn_data[icode].operand[0].mode)) | |
4819 | || !(insn_data[icode].operand[1].predicate | |
4820 | (x, insn_data[icode].operand[1].mode)) | |
4821 | || !(insn_data[icode].operand[2].predicate | |
4822 | (y, insn_data[icode].operand[2].mode))) | |
c299d9c8 | 4823 | return 0; |
4824 | ||
4825 | return 1; | |
1f215c26 | 4826 | } |
4827 | ||
a4463e50 | 4828 | /* Generate the body of an instruction to copy Y into X. |
31d3e01c | 4829 | It may be a list of insns, if one insn isn't enough. */ |
1f215c26 | 4830 | |
4831 | rtx | |
3ad4992f | 4832 | gen_move_insn (rtx x, rtx y) |
1f215c26 | 4833 | { |
a4463e50 | 4834 | rtx seq; |
1f215c26 | 4835 | |
a4463e50 | 4836 | start_sequence (); |
4837 | emit_move_insn_1 (x, y); | |
31d3e01c | 4838 | seq = get_insns (); |
a4463e50 | 4839 | end_sequence (); |
4840 | return seq; | |
1f215c26 | 4841 | } |
4842 | \f | |
3b1a9578 | 4843 | /* Return the insn code used to extend FROM_MODE to TO_MODE. |
4844 | UNSIGNEDP specifies zero-extension instead of sign-extension. If | |
4845 | no such operation exists, CODE_FOR_nothing will be returned. */ | |
1f215c26 | 4846 | |
3b1a9578 | 4847 | enum insn_code |
3ad4992f | 4848 | can_extend_p (enum machine_mode to_mode, enum machine_mode from_mode, |
4849 | int unsignedp) | |
1f215c26 | 4850 | { |
a7cc195f | 4851 | convert_optab tab; |
3cc092f7 | 4852 | #ifdef HAVE_ptr_extend |
4853 | if (unsignedp < 0) | |
4854 | return CODE_FOR_ptr_extend; | |
3cc092f7 | 4855 | #endif |
a7cc195f | 4856 | |
4857 | tab = unsignedp ? zext_optab : sext_optab; | |
99bdde56 | 4858 | return convert_optab_handler (tab, to_mode, from_mode)->insn_code; |
1f215c26 | 4859 | } |
4860 | ||
4861 | /* Generate the body of an insn to extend Y (with mode MFROM) | |
4862 | into X (with mode MTO). Do zero-extension if UNSIGNEDP is nonzero. */ | |
4863 | ||
4864 | rtx | |
3ad4992f | 4865 | gen_extend_insn (rtx x, rtx y, enum machine_mode mto, |
4866 | enum machine_mode mfrom, int unsignedp) | |
1f215c26 | 4867 | { |
a7cc195f | 4868 | enum insn_code icode = can_extend_p (mto, mfrom, unsignedp); |
4869 | return GEN_FCN (icode) (x, y); | |
1f215c26 | 4870 | } |
1f215c26 | 4871 | \f |
4872 | /* can_fix_p and can_float_p say whether the target machine | |
4873 | can directly convert a given fixed point type to | |
4874 | a given floating point type, or vice versa. | |
4875 | The returned value is the CODE_FOR_... value to use, | |
2850b1f2 | 4876 | or CODE_FOR_nothing if these modes cannot be directly converted. |
1f215c26 | 4877 | |
2850b1f2 | 4878 | *TRUNCP_PTR is set to 1 if it is necessary to output |
1f215c26 | 4879 | an explicit FTRUNC insn before the fix insn; otherwise 0. */ |
4880 | ||
4881 | static enum insn_code | |
3ad4992f | 4882 | can_fix_p (enum machine_mode fixmode, enum machine_mode fltmode, |
4883 | int unsignedp, int *truncp_ptr) | |
1f215c26 | 4884 | { |
a7cc195f | 4885 | convert_optab tab; |
4886 | enum insn_code icode; | |
4887 | ||
4888 | tab = unsignedp ? ufixtrunc_optab : sfixtrunc_optab; | |
99bdde56 | 4889 | icode = convert_optab_handler (tab, fixmode, fltmode)->insn_code; |
a7cc195f | 4890 | if (icode != CODE_FOR_nothing) |
4891 | { | |
4892 | *truncp_ptr = 0; | |
4893 | return icode; | |
4894 | } | |
1f215c26 | 4895 | |
43a0013a | 4896 | /* FIXME: This requires a port to define both FIX and FTRUNC pattern |
4897 | for this to work. We need to rework the fix* and ftrunc* patterns | |
4898 | and documentation. */ | |
a7cc195f | 4899 | tab = unsignedp ? ufix_optab : sfix_optab; |
99bdde56 | 4900 | icode = convert_optab_handler (tab, fixmode, fltmode)->insn_code; |
a7cc195f | 4901 | if (icode != CODE_FOR_nothing |
99bdde56 | 4902 | && optab_handler (ftrunc_optab, fltmode)->insn_code != CODE_FOR_nothing) |
1f215c26 | 4903 | { |
4904 | *truncp_ptr = 1; | |
a7cc195f | 4905 | return icode; |
1f215c26 | 4906 | } |
a7cc195f | 4907 | |
4908 | *truncp_ptr = 0; | |
1f215c26 | 4909 | return CODE_FOR_nothing; |
4910 | } | |
4911 | ||
4912 | static enum insn_code | |
3ad4992f | 4913 | can_float_p (enum machine_mode fltmode, enum machine_mode fixmode, |
4914 | int unsignedp) | |
1f215c26 | 4915 | { |
a7cc195f | 4916 | convert_optab tab; |
4917 | ||
4918 | tab = unsignedp ? ufloat_optab : sfloat_optab; | |
99bdde56 | 4919 | return convert_optab_handler (tab, fltmode, fixmode)->insn_code; |
1f215c26 | 4920 | } |
1f215c26 | 4921 | \f |
4922 | /* Generate code to convert FROM to floating point | |
3b1a9578 | 4923 | and store in TO. FROM must be fixed point and not VOIDmode. |
1f215c26 | 4924 | UNSIGNEDP nonzero means regard FROM as unsigned. |
4925 | Normally this is done by correcting the final value | |
4926 | if it is negative. */ | |
4927 | ||
4928 | void | |
3ad4992f | 4929 | expand_float (rtx to, rtx from, int unsignedp) |
1f215c26 | 4930 | { |
4931 | enum insn_code icode; | |
19cb6b50 | 4932 | rtx target = to; |
1f215c26 | 4933 | enum machine_mode fmode, imode; |
4f5bcdbd | 4934 | bool can_do_signed = false; |
1f215c26 | 4935 | |
3b1a9578 | 4936 | /* Crash now, because we won't be able to decide which mode to use. */ |
ce572eff | 4937 | gcc_assert (GET_MODE (from) != VOIDmode); |
3b1a9578 | 4938 | |
1f215c26 | 4939 | /* Look for an insn to do the conversion. Do it in the specified |
4940 | modes if possible; otherwise convert either input, output or both to | |
4941 | wider mode. If the integer mode is wider than the mode of FROM, | |
4942 | we can do the conversion signed even if the input is unsigned. */ | |
4943 | ||
344f3f9e | 4944 | for (fmode = GET_MODE (to); fmode != VOIDmode; |
4945 | fmode = GET_MODE_WIDER_MODE (fmode)) | |
4946 | for (imode = GET_MODE (from); imode != VOIDmode; | |
4947 | imode = GET_MODE_WIDER_MODE (imode)) | |
1f215c26 | 4948 | { |
4949 | int doing_unsigned = unsignedp; | |
4950 | ||
ee90778f | 4951 | if (fmode != GET_MODE (to) |
4952 | && significand_size (fmode) < GET_MODE_BITSIZE (GET_MODE (from))) | |
4953 | continue; | |
4954 | ||
1f215c26 | 4955 | icode = can_float_p (fmode, imode, unsignedp); |
4f5bcdbd | 4956 | if (icode == CODE_FOR_nothing && unsignedp) |
4957 | { | |
4958 | enum insn_code scode = can_float_p (fmode, imode, 0); | |
4959 | if (scode != CODE_FOR_nothing) | |
4960 | can_do_signed = true; | |
4961 | if (imode != GET_MODE (from)) | |
4962 | icode = scode, doing_unsigned = 0; | |
4963 | } | |
1f215c26 | 4964 | |
4965 | if (icode != CODE_FOR_nothing) | |
4966 | { | |
1f215c26 | 4967 | if (imode != GET_MODE (from)) |
4968 | from = convert_to_mode (imode, from, unsignedp); | |
1f215c26 | 4969 | |
4970 | if (fmode != GET_MODE (to)) | |
4971 | target = gen_reg_rtx (fmode); | |
4972 | ||
4973 | emit_unop_insn (icode, target, from, | |
4974 | doing_unsigned ? UNSIGNED_FLOAT : FLOAT); | |
4975 | ||
4976 | if (target != to) | |
4977 | convert_move (to, target, 0); | |
4978 | return; | |
4979 | } | |
2fd3f4b5 | 4980 | } |
1f215c26 | 4981 | |
4e6322c5 | 4982 | /* Unsigned integer, and no way to convert directly. Convert as signed, |
4c8054f4 | 4983 | then unconditionally adjust the result. */ |
4984 | if (unsignedp && can_do_signed) | |
1f215c26 | 4985 | { |
4986 | rtx label = gen_label_rtx (); | |
4987 | rtx temp; | |
4988 | REAL_VALUE_TYPE offset; | |
4989 | ||
8142649d | 4990 | /* Look for a usable floating mode FMODE wider than the source and at |
4991 | least as wide as the target. Using FMODE will avoid rounding woes | |
4992 | with unsigned values greater than the signed maximum value. */ | |
caf74f46 | 4993 | |
8142649d | 4994 | for (fmode = GET_MODE (to); fmode != VOIDmode; |
4995 | fmode = GET_MODE_WIDER_MODE (fmode)) | |
4996 | if (GET_MODE_BITSIZE (GET_MODE (from)) < GET_MODE_BITSIZE (fmode) | |
4997 | && can_float_p (fmode, GET_MODE (from), 0) != CODE_FOR_nothing) | |
4998 | break; | |
144a41c2 | 4999 | |
8142649d | 5000 | if (fmode == VOIDmode) |
5001 | { | |
144a41c2 | 5002 | /* There is no such mode. Pretend the target is wide enough. */ |
8142649d | 5003 | fmode = GET_MODE (to); |
144a41c2 | 5004 | |
a92771b8 | 5005 | /* Avoid double-rounding when TO is narrower than FROM. */ |
144a41c2 | 5006 | if ((significand_size (fmode) + 1) |
5007 | < GET_MODE_BITSIZE (GET_MODE (from))) | |
5008 | { | |
5009 | rtx temp1; | |
5010 | rtx neglabel = gen_label_rtx (); | |
5011 | ||
3ad4992f | 5012 | /* Don't use TARGET if it isn't a register, is a hard register, |
caf74f46 | 5013 | or is the wrong mode. */ |
8ad4c111 | 5014 | if (!REG_P (target) |
caf74f46 | 5015 | || REGNO (target) < FIRST_PSEUDO_REGISTER |
5016 | || GET_MODE (target) != fmode) | |
1d88d298 | 5017 | target = gen_reg_rtx (fmode); |
5018 | ||
144a41c2 | 5019 | imode = GET_MODE (from); |
5020 | do_pending_stack_adjust (); | |
5021 | ||
5022 | /* Test whether the sign bit is set. */ | |
10ee3e0f | 5023 | emit_cmp_and_jump_insns (from, const0_rtx, LT, NULL_RTX, imode, |
2b96c5f6 | 5024 | 0, neglabel); |
144a41c2 | 5025 | |
5026 | /* The sign bit is not set. Convert as signed. */ | |
5027 | expand_float (target, from, 0); | |
5028 | emit_jump_insn (gen_jump (label)); | |
3cdb147b | 5029 | emit_barrier (); |
144a41c2 | 5030 | |
5031 | /* The sign bit is set. | |
5032 | Convert to a usable (positive signed) value by shifting right | |
5033 | one bit, while remembering if a nonzero bit was shifted | |
5034 | out; i.e., compute (from & 1) | (from >> 1). */ | |
5035 | ||
5036 | emit_label (neglabel); | |
5037 | temp = expand_binop (imode, and_optab, from, const1_rtx, | |
caf74f46 | 5038 | NULL_RTX, 1, OPTAB_LIB_WIDEN); |
b2bc10f7 | 5039 | temp1 = expand_shift (RSHIFT_EXPR, imode, from, integer_one_node, |
5040 | NULL_RTX, 1); | |
3ad4992f | 5041 | temp = expand_binop (imode, ior_optab, temp, temp1, temp, 1, |
caf74f46 | 5042 | OPTAB_LIB_WIDEN); |
144a41c2 | 5043 | expand_float (target, temp, 0); |
5044 | ||
5045 | /* Multiply by 2 to undo the shift above. */ | |
98a10a19 | 5046 | temp = expand_binop (fmode, add_optab, target, target, |
2fd3f4b5 | 5047 | target, 0, OPTAB_LIB_WIDEN); |
98a10a19 | 5048 | if (temp != target) |
5049 | emit_move_insn (target, temp); | |
5050 | ||
144a41c2 | 5051 | do_pending_stack_adjust (); |
5052 | emit_label (label); | |
5053 | goto done; | |
5054 | } | |
8142649d | 5055 | } |
5056 | ||
1f215c26 | 5057 | /* If we are about to do some arithmetic to correct for an |
5058 | unsigned operand, do it in a pseudo-register. */ | |
5059 | ||
8142649d | 5060 | if (GET_MODE (to) != fmode |
8ad4c111 | 5061 | || !REG_P (to) || REGNO (to) < FIRST_PSEUDO_REGISTER) |
8142649d | 5062 | target = gen_reg_rtx (fmode); |
1f215c26 | 5063 | |
5064 | /* Convert as signed integer to floating. */ | |
5065 | expand_float (target, from, 0); | |
5066 | ||
5067 | /* If FROM is negative (and therefore TO is negative), | |
5068 | correct its value by 2**bitwidth. */ | |
5069 | ||
5070 | do_pending_stack_adjust (); | |
5a894bc6 | 5071 | emit_cmp_and_jump_insns (from, const0_rtx, GE, NULL_RTX, GET_MODE (from), |
2b96c5f6 | 5072 | 0, label); |
caf74f46 | 5073 | |
3ad4992f | 5074 | |
4e6322c5 | 5075 | real_2expN (&offset, GET_MODE_BITSIZE (GET_MODE (from)), fmode); |
8142649d | 5076 | temp = expand_binop (fmode, add_optab, target, |
7af35cec | 5077 | CONST_DOUBLE_FROM_REAL_VALUE (offset, fmode), |
1f215c26 | 5078 | target, 0, OPTAB_LIB_WIDEN); |
5079 | if (temp != target) | |
5080 | emit_move_insn (target, temp); | |
144a41c2 | 5081 | |
1f215c26 | 5082 | do_pending_stack_adjust (); |
5083 | emit_label (label); | |
caf74f46 | 5084 | goto done; |
1f215c26 | 5085 | } |
1f215c26 | 5086 | |
a7cc195f | 5087 | /* No hardware instruction available; call a library routine. */ |
1f215c26 | 5088 | { |
a7cc195f | 5089 | rtx libfunc; |
1f215c26 | 5090 | rtx insns; |
bc4abce8 | 5091 | rtx value; |
a7cc195f | 5092 | convert_optab tab = unsignedp ? ufloat_optab : sfloat_optab; |
1f215c26 | 5093 | |
1f215c26 | 5094 | if (GET_MODE_SIZE (GET_MODE (from)) < GET_MODE_SIZE (SImode)) |
5095 | from = convert_to_mode (SImode, from, unsignedp); | |
1f215c26 | 5096 | |
f36b9f69 | 5097 | libfunc = convert_optab_libfunc (tab, GET_MODE (to), GET_MODE (from)); |
ce572eff | 5098 | gcc_assert (libfunc); |
1f215c26 | 5099 | |
5100 | start_sequence (); | |
5101 | ||
a7cc195f | 5102 | value = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST, |
2c5d421b | 5103 | GET_MODE (to), 1, from, |
5104 | GET_MODE (from)); | |
1f215c26 | 5105 | insns = get_insns (); |
5106 | end_sequence (); | |
5107 | ||
bc4abce8 | 5108 | emit_libcall_block (insns, target, value, |
9407e9ac | 5109 | gen_rtx_fmt_e (unsignedp ? UNSIGNED_FLOAT : FLOAT, |
5110 | GET_MODE (to), from)); | |
1f215c26 | 5111 | } |
5112 | ||
144a41c2 | 5113 | done: |
5114 | ||
1f215c26 | 5115 | /* Copy result to requested destination |
5116 | if we have been computing in a temp location. */ | |
5117 | ||
5118 | if (target != to) | |
5119 | { | |
5120 | if (GET_MODE (target) == GET_MODE (to)) | |
5121 | emit_move_insn (to, target); | |
5122 | else | |
5123 | convert_move (to, target, 0); | |
5124 | } | |
5125 | } | |
5126 | \f | |
43a0013a | 5127 | /* Generate code to convert FROM to fixed point and store in TO. FROM |
5128 | must be floating point. */ | |
1f215c26 | 5129 | |
5130 | void | |
3ad4992f | 5131 | expand_fix (rtx to, rtx from, int unsignedp) |
1f215c26 | 5132 | { |
5133 | enum insn_code icode; | |
19cb6b50 | 5134 | rtx target = to; |
1f215c26 | 5135 | enum machine_mode fmode, imode; |
5136 | int must_trunc = 0; | |
1f215c26 | 5137 | |
5138 | /* We first try to find a pair of modes, one real and one integer, at | |
5139 | least as wide as FROM and TO, respectively, in which we can open-code | |
5140 | this conversion. If the integer mode is wider than the mode of TO, | |
5141 | we can do the conversion either signed or unsigned. */ | |
5142 | ||
98431bf3 | 5143 | for (fmode = GET_MODE (from); fmode != VOIDmode; |
5144 | fmode = GET_MODE_WIDER_MODE (fmode)) | |
5145 | for (imode = GET_MODE (to); imode != VOIDmode; | |
5146 | imode = GET_MODE_WIDER_MODE (imode)) | |
1f215c26 | 5147 | { |
5148 | int doing_unsigned = unsignedp; | |
5149 | ||
5150 | icode = can_fix_p (imode, fmode, unsignedp, &must_trunc); | |
5151 | if (icode == CODE_FOR_nothing && imode != GET_MODE (to) && unsignedp) | |
5152 | icode = can_fix_p (imode, fmode, 0, &must_trunc), doing_unsigned = 0; | |
5153 | ||
5154 | if (icode != CODE_FOR_nothing) | |
5155 | { | |
c73ea1cc | 5156 | rtx last = get_last_insn (); |
1f215c26 | 5157 | if (fmode != GET_MODE (from)) |
5158 | from = convert_to_mode (fmode, from, 0); | |
1f215c26 | 5159 | |
5160 | if (must_trunc) | |
43a0013a | 5161 | { |
5162 | rtx temp = gen_reg_rtx (GET_MODE (from)); | |
5163 | from = expand_unop (GET_MODE (from), ftrunc_optab, from, | |
5164 | temp, 0); | |
5165 | } | |
1f215c26 | 5166 | |
5167 | if (imode != GET_MODE (to)) | |
5168 | target = gen_reg_rtx (imode); | |
5169 | ||
c73ea1cc | 5170 | if (maybe_emit_unop_insn (icode, target, from, |
5171 | doing_unsigned ? UNSIGNED_FIX : FIX)) | |
5172 | { | |
5173 | if (target != to) | |
5174 | convert_move (to, target, unsignedp); | |
5175 | return; | |
5176 | } | |
5177 | delete_insns_since (last); | |
1f215c26 | 5178 | } |
5179 | } | |
5180 | ||
1f215c26 | 5181 | /* For an unsigned conversion, there is one more way to do it. |
5182 | If we have a signed conversion, we generate code that compares | |
5183 | the real value to the largest representable positive number. If if | |
5184 | is smaller, the conversion is done normally. Otherwise, subtract | |
5185 | one plus the highest signed number, convert, and add it back. | |
5186 | ||
5187 | We only need to check all real modes, since we know we didn't find | |
3ad4992f | 5188 | anything with a wider integer mode. |
376c21d1 | 5189 | |
5190 | This code used to extend FP value into mode wider than the destination. | |
4e6322c5 | 5191 | This is needed for decimal float modes which cannot accurately |
5192 | represent one plus the highest signed number of the same size, but | |
5193 | not for binary modes. Consider, for instance conversion from SFmode | |
376c21d1 | 5194 | into DImode. |
5195 | ||
554f2707 | 5196 | The hot path through the code is dealing with inputs smaller than 2^63 |
376c21d1 | 5197 | and doing just the conversion, so there is no bits to lose. |
5198 | ||
5199 | In the other path we know the value is positive in the range 2^63..2^64-1 | |
4e6322c5 | 5200 | inclusive. (as for other input overflow happens and result is undefined) |
d01481af | 5201 | So we know that the most important bit set in mantissa corresponds to |
376c21d1 | 5202 | 2^63. The subtraction of 2^63 should not generate any rounding as it |
5203 | simply clears out that bit. The rest is trivial. */ | |
1f215c26 | 5204 | |
50b0c9ee | 5205 | if (unsignedp && GET_MODE_BITSIZE (GET_MODE (to)) <= HOST_BITS_PER_WIDE_INT) |
1f215c26 | 5206 | for (fmode = GET_MODE (from); fmode != VOIDmode; |
5207 | fmode = GET_MODE_WIDER_MODE (fmode)) | |
4e6322c5 | 5208 | if (CODE_FOR_nothing != can_fix_p (GET_MODE (to), fmode, 0, &must_trunc) |
5209 | && (!DECIMAL_FLOAT_MODE_P (fmode) | |
5210 | || GET_MODE_BITSIZE (fmode) > GET_MODE_BITSIZE (GET_MODE (to)))) | |
1f215c26 | 5211 | { |
d90797a0 | 5212 | int bitsize; |
5213 | REAL_VALUE_TYPE offset; | |
5214 | rtx limit, lab1, lab2, insn; | |
5215 | ||
5216 | bitsize = GET_MODE_BITSIZE (GET_MODE (to)); | |
4e6322c5 | 5217 | real_2expN (&offset, bitsize - 1, fmode); |
7af35cec | 5218 | limit = CONST_DOUBLE_FROM_REAL_VALUE (offset, fmode); |
d90797a0 | 5219 | lab1 = gen_label_rtx (); |
5220 | lab2 = gen_label_rtx (); | |
1f215c26 | 5221 | |
1f215c26 | 5222 | if (fmode != GET_MODE (from)) |
5223 | from = convert_to_mode (fmode, from, 0); | |
5224 | ||
5225 | /* See if we need to do the subtraction. */ | |
5226 | do_pending_stack_adjust (); | |
5a894bc6 | 5227 | emit_cmp_and_jump_insns (from, limit, GE, NULL_RTX, GET_MODE (from), |
2b96c5f6 | 5228 | 0, lab1); |
1f215c26 | 5229 | |
5230 | /* If not, do the signed "fix" and branch around fixup code. */ | |
5231 | expand_fix (to, from, 0); | |
5232 | emit_jump_insn (gen_jump (lab2)); | |
5233 | emit_barrier (); | |
5234 | ||
5235 | /* Otherwise, subtract 2**(N-1), convert to signed number, | |
5236 | then add 2**(N-1). Do the addition using XOR since this | |
5237 | will often generate better code. */ | |
5238 | emit_label (lab1); | |
5239 | target = expand_binop (GET_MODE (from), sub_optab, from, limit, | |
50b0c9ee | 5240 | NULL_RTX, 0, OPTAB_LIB_WIDEN); |
1f215c26 | 5241 | expand_fix (to, target, 0); |
5242 | target = expand_binop (GET_MODE (to), xor_optab, to, | |
2d232d05 | 5243 | gen_int_mode |
5244 | ((HOST_WIDE_INT) 1 << (bitsize - 1), | |
5245 | GET_MODE (to)), | |
1f215c26 | 5246 | to, 1, OPTAB_LIB_WIDEN); |
5247 | ||
5248 | if (target != to) | |
5249 | emit_move_insn (to, target); | |
5250 | ||
5251 | emit_label (lab2); | |
5252 | ||
99bdde56 | 5253 | if (optab_handler (mov_optab, GET_MODE (to))->insn_code |
3c96cf42 | 5254 | != CODE_FOR_nothing) |
5255 | { | |
5256 | /* Make a place for a REG_NOTE and add it. */ | |
5257 | insn = emit_move_insn (to, to); | |
e29342dc | 5258 | set_unique_reg_note (insn, |
5259 | REG_EQUAL, | |
5260 | gen_rtx_fmt_e (UNSIGNED_FIX, | |
5261 | GET_MODE (to), | |
5262 | copy_rtx (from))); | |
3c96cf42 | 5263 | } |
7014838c | 5264 | |
1f215c26 | 5265 | return; |
5266 | } | |
1f215c26 | 5267 | |
5268 | /* We can't do it with an insn, so use a library call. But first ensure | |
5269 | that the mode of TO is at least as wide as SImode, since those are the | |
5270 | only library calls we know about. */ | |
5271 | ||
5272 | if (GET_MODE_SIZE (GET_MODE (to)) < GET_MODE_SIZE (SImode)) | |
5273 | { | |
5274 | target = gen_reg_rtx (SImode); | |
5275 | ||
5276 | expand_fix (target, from, unsignedp); | |
5277 | } | |
1f215c26 | 5278 | else |
1f215c26 | 5279 | { |
5280 | rtx insns; | |
e7121682 | 5281 | rtx value; |
a7cc195f | 5282 | rtx libfunc; |
7d3f6cc7 | 5283 | |
a7cc195f | 5284 | convert_optab tab = unsignedp ? ufix_optab : sfix_optab; |
f36b9f69 | 5285 | libfunc = convert_optab_libfunc (tab, GET_MODE (to), GET_MODE (from)); |
ce572eff | 5286 | gcc_assert (libfunc); |
1f215c26 | 5287 | |
1f215c26 | 5288 | start_sequence (); |
5289 | ||
a7cc195f | 5290 | value = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST, |
2c5d421b | 5291 | GET_MODE (to), 1, from, |
5292 | GET_MODE (from)); | |
1f215c26 | 5293 | insns = get_insns (); |
5294 | end_sequence (); | |
5295 | ||
e7121682 | 5296 | emit_libcall_block (insns, target, value, |
e02c6d1f | 5297 | gen_rtx_fmt_e (unsignedp ? UNSIGNED_FIX : FIX, |
5298 | GET_MODE (to), from)); | |
1f215c26 | 5299 | } |
3ad4992f | 5300 | |
db60fef7 | 5301 | if (target != to) |
5302 | { | |
5303 | if (GET_MODE (to) == GET_MODE (target)) | |
5304 | emit_move_insn (to, target); | |
5305 | else | |
5306 | convert_move (to, target, 0); | |
5307 | } | |
1f215c26 | 5308 | } |
5f51ee59 | 5309 | |
68a556d6 | 5310 | /* Generate code to convert FROM or TO a fixed-point. |
5311 | If UINTP is true, either TO or FROM is an unsigned integer. | |
5312 | If SATP is true, we need to saturate the result. */ | |
5313 | ||
5314 | void | |
5315 | expand_fixed_convert (rtx to, rtx from, int uintp, int satp) | |
5316 | { | |
5317 | enum machine_mode to_mode = GET_MODE (to); | |
5318 | enum machine_mode from_mode = GET_MODE (from); | |
5319 | convert_optab tab; | |
5320 | enum rtx_code this_code; | |
5321 | enum insn_code code; | |
5322 | rtx insns, value; | |
5323 | rtx libfunc; | |
5324 | ||
5325 | if (to_mode == from_mode) | |
5326 | { | |
5327 | emit_move_insn (to, from); | |
5328 | return; | |
5329 | } | |
5330 | ||
5331 | if (uintp) | |
5332 | { | |
5333 | tab = satp ? satfractuns_optab : fractuns_optab; | |
5334 | this_code = satp ? UNSIGNED_SAT_FRACT : UNSIGNED_FRACT_CONVERT; | |
5335 | } | |
5336 | else | |
5337 | { | |
5338 | tab = satp ? satfract_optab : fract_optab; | |
5339 | this_code = satp ? SAT_FRACT : FRACT_CONVERT; | |
5340 | } | |
5341 | code = tab->handlers[to_mode][from_mode].insn_code; | |
5342 | if (code != CODE_FOR_nothing) | |
5343 | { | |
5344 | emit_unop_insn (code, to, from, this_code); | |
5345 | return; | |
5346 | } | |
5347 | ||
5348 | libfunc = convert_optab_libfunc (tab, to_mode, from_mode); | |
5349 | gcc_assert (libfunc); | |
5350 | ||
5351 | start_sequence (); | |
5352 | value = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST, to_mode, | |
5353 | 1, from, from_mode); | |
5354 | insns = get_insns (); | |
5355 | end_sequence (); | |
5356 | ||
5357 | emit_libcall_block (insns, to, value, | |
5358 | gen_rtx_fmt_e (tab->code, to_mode, from)); | |
5359 | } | |
5360 | ||
5f51ee59 | 5361 | /* Generate code to convert FROM to fixed point and store in TO. FROM |
5362 | must be floating point, TO must be signed. Use the conversion optab | |
5363 | TAB to do the conversion. */ | |
5364 | ||
5365 | bool | |
5366 | expand_sfix_optab (rtx to, rtx from, convert_optab tab) | |
5367 | { | |
5368 | enum insn_code icode; | |
5369 | rtx target = to; | |
5370 | enum machine_mode fmode, imode; | |
5371 | ||
5372 | /* We first try to find a pair of modes, one real and one integer, at | |
5373 | least as wide as FROM and TO, respectively, in which we can open-code | |
5374 | this conversion. If the integer mode is wider than the mode of TO, | |
5375 | we can do the conversion either signed or unsigned. */ | |
5376 | ||
5377 | for (fmode = GET_MODE (from); fmode != VOIDmode; | |
5378 | fmode = GET_MODE_WIDER_MODE (fmode)) | |
5379 | for (imode = GET_MODE (to); imode != VOIDmode; | |
5380 | imode = GET_MODE_WIDER_MODE (imode)) | |
5381 | { | |
99bdde56 | 5382 | icode = convert_optab_handler (tab, imode, fmode)->insn_code; |
5f51ee59 | 5383 | if (icode != CODE_FOR_nothing) |
5384 | { | |
c73ea1cc | 5385 | rtx last = get_last_insn (); |
5f51ee59 | 5386 | if (fmode != GET_MODE (from)) |
5387 | from = convert_to_mode (fmode, from, 0); | |
5388 | ||
5389 | if (imode != GET_MODE (to)) | |
5390 | target = gen_reg_rtx (imode); | |
5391 | ||
a1515011 | 5392 | if (!maybe_emit_unop_insn (icode, target, from, UNKNOWN)) |
c73ea1cc | 5393 | { |
5394 | delete_insns_since (last); | |
5395 | continue; | |
5396 | } | |
5f51ee59 | 5397 | if (target != to) |
5398 | convert_move (to, target, 0); | |
5399 | return true; | |
5400 | } | |
5401 | } | |
5402 | ||
5403 | return false; | |
5404 | } | |
1f215c26 | 5405 | \f |
ad99e708 | 5406 | /* Report whether we have an instruction to perform the operation |
5407 | specified by CODE on operands of mode MODE. */ | |
5408 | int | |
3ad4992f | 5409 | have_insn_for (enum rtx_code code, enum machine_mode mode) |
ad99e708 | 5410 | { |
5411 | return (code_to_optab[(int) code] != 0 | |
99bdde56 | 5412 | && (optab_handler (code_to_optab[(int) code], mode)->insn_code |
ad99e708 | 5413 | != CODE_FOR_nothing)); |
5414 | } | |
5415 | ||
53b14d73 | 5416 | /* Set all insn_code fields to CODE_FOR_nothing. */ |
5417 | ||
be5cecfd | 5418 | static void |
53b14d73 | 5419 | init_insn_codes (void) |
a7cc195f | 5420 | { |
53b14d73 | 5421 | unsigned int i; |
f36b9f69 | 5422 | |
53b14d73 | 5423 | for (i = 0; i < (unsigned int) OTI_MAX; i++) |
5424 | { | |
5425 | unsigned int j; | |
5426 | optab op; | |
5427 | ||
5428 | op = &optab_table[i]; | |
5429 | for (j = 0; j < NUM_MACHINE_MODES; j++) | |
5430 | optab_handler (op, j)->insn_code = CODE_FOR_nothing; | |
5431 | } | |
5432 | for (i = 0; i < (unsigned int) COI_MAX; i++) | |
5433 | { | |
5434 | unsigned int j, k; | |
5435 | convert_optab op; | |
5436 | ||
5437 | op = &convert_optab_table[i]; | |
5438 | for (j = 0; j < NUM_MACHINE_MODES; j++) | |
5439 | for (k = 0; k < NUM_MACHINE_MODES; k++) | |
5440 | convert_optab_handler (op, j, k)->insn_code = CODE_FOR_nothing; | |
5441 | } | |
a7cc195f | 5442 | } |
5443 | ||
53b14d73 | 5444 | /* Initialize OP's code to CODE, and write it into the code_to_optab table. */ |
be5cecfd | 5445 | static inline void |
5446 | init_optab (optab op, enum rtx_code code) | |
ad99e708 | 5447 | { |
ad99e708 | 5448 | op->code = code; |
5449 | code_to_optab[(int) code] = op; | |
ad99e708 | 5450 | } |
5451 | ||
5452 | /* Same, but fill in its code as CODE, and do _not_ write it into | |
5453 | the code_to_optab table. */ | |
be5cecfd | 5454 | static inline void |
5455 | init_optabv (optab op, enum rtx_code code) | |
ad99e708 | 5456 | { |
ad99e708 | 5457 | op->code = code; |
1f215c26 | 5458 | } |
5459 | ||
a7cc195f | 5460 | /* Conversion optabs never go in the code_to_optab table. */ |
be5cecfd | 5461 | static void |
5462 | init_convert_optab (convert_optab op, enum rtx_code code) | |
a7cc195f | 5463 | { |
a7cc195f | 5464 | op->code = code; |
a7cc195f | 5465 | } |
5466 | ||
c2a91a88 | 5467 | /* Initialize the libfunc fields of an entire group of entries in some |
5468 | optab. Each entry is set equal to a string consisting of a leading | |
5469 | pair of underscores followed by a generic operation name followed by | |
de44dcb9 | 5470 | a mode name (downshifted to lowercase) followed by a single character |
c2a91a88 | 5471 | representing the number of operands for the given operation (which is |
5472 | usually one of the characters '2', '3', or '4'). | |
5473 | ||
5474 | OPTABLE is the table in which libfunc fields are to be initialized. | |
c2a91a88 | 5475 | OPNAME is the generic (string) name of the operation. |
5476 | SUFFIX is the character which specifies the number of operands for | |
5477 | the given generic operation. | |
f36b9f69 | 5478 | MODE is the mode to generate for. |
c2a91a88 | 5479 | */ |
5480 | ||
5481 | static void | |
f36b9f69 | 5482 | gen_libfunc (optab optable, const char *opname, int suffix, enum machine_mode mode) |
c2a91a88 | 5483 | { |
19cb6b50 | 5484 | unsigned opname_len = strlen (opname); |
f36b9f69 | 5485 | const char *mname = GET_MODE_NAME (mode); |
5486 | unsigned mname_len = strlen (mname); | |
4077bf7a | 5487 | char *libfunc_name = XALLOCAVEC (char, 2 + opname_len + mname_len + 1 + 1); |
f36b9f69 | 5488 | char *p; |
5489 | const char *q; | |
c2a91a88 | 5490 | |
f36b9f69 | 5491 | p = libfunc_name; |
5492 | *p++ = '_'; | |
5493 | *p++ = '_'; | |
5494 | for (q = opname; *q; ) | |
5495 | *p++ = *q++; | |
5496 | for (q = mname; *q; q++) | |
5497 | *p++ = TOLOWER (*q); | |
5498 | *p++ = suffix; | |
5499 | *p = '\0'; | |
5500 | ||
5501 | set_optab_libfunc (optable, mode, | |
5502 | ggc_alloc_string (libfunc_name, p - libfunc_name)); | |
c2a91a88 | 5503 | } |
5504 | ||
f36b9f69 | 5505 | /* Like gen_libfunc, but verify that integer operation is involved. */ |
c2a91a88 | 5506 | |
5507 | static void | |
f36b9f69 | 5508 | gen_int_libfunc (optab optable, const char *opname, char suffix, |
5509 | enum machine_mode mode) | |
c2a91a88 | 5510 | { |
f36b9f69 | 5511 | int maxsize = 2 * BITS_PER_WORD; |
5512 | ||
5513 | if (GET_MODE_CLASS (mode) != MODE_INT) | |
5514 | return; | |
7f6007b4 | 5515 | if (maxsize < LONG_LONG_TYPE_SIZE) |
5516 | maxsize = LONG_LONG_TYPE_SIZE; | |
f36b9f69 | 5517 | if (GET_MODE_CLASS (mode) != MODE_INT |
5518 | || mode < word_mode || GET_MODE_BITSIZE (mode) > maxsize) | |
5519 | return; | |
5520 | gen_libfunc (optable, opname, suffix, mode); | |
c2a91a88 | 5521 | } |
5522 | ||
f36b9f69 | 5523 | /* Like gen_libfunc, but verify that FP and set decimal prefix if needed. */ |
c2a91a88 | 5524 | |
5525 | static void | |
f36b9f69 | 5526 | gen_fp_libfunc (optab optable, const char *opname, char suffix, |
5527 | enum machine_mode mode) | |
c2a91a88 | 5528 | { |
f36b9f69 | 5529 | char *dec_opname; |
10de71e1 | 5530 | |
f36b9f69 | 5531 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) |
5532 | gen_libfunc (optable, opname, suffix, mode); | |
5533 | if (DECIMAL_FLOAT_MODE_P (mode)) | |
5534 | { | |
4077bf7a | 5535 | dec_opname = XALLOCAVEC (char, sizeof (DECIMAL_PREFIX) + strlen (opname)); |
f36b9f69 | 5536 | /* For BID support, change the name to have either a bid_ or dpd_ prefix |
5537 | depending on the low level floating format used. */ | |
5538 | memcpy (dec_opname, DECIMAL_PREFIX, sizeof (DECIMAL_PREFIX) - 1); | |
5539 | strcpy (dec_opname + sizeof (DECIMAL_PREFIX) - 1, opname); | |
5540 | gen_libfunc (optable, dec_opname, suffix, mode); | |
5541 | } | |
5542 | } | |
10de71e1 | 5543 | |
68a556d6 | 5544 | /* Like gen_libfunc, but verify that fixed-point operation is involved. */ |
5545 | ||
5546 | static void | |
5547 | gen_fixed_libfunc (optab optable, const char *opname, char suffix, | |
5548 | enum machine_mode mode) | |
5549 | { | |
5550 | if (!ALL_FIXED_POINT_MODE_P (mode)) | |
5551 | return; | |
5552 | gen_libfunc (optable, opname, suffix, mode); | |
5553 | } | |
5554 | ||
5555 | /* Like gen_libfunc, but verify that signed fixed-point operation is | |
5556 | involved. */ | |
5557 | ||
5558 | static void | |
5559 | gen_signed_fixed_libfunc (optab optable, const char *opname, char suffix, | |
5560 | enum machine_mode mode) | |
5561 | { | |
5562 | if (!SIGNED_FIXED_POINT_MODE_P (mode)) | |
5563 | return; | |
5564 | gen_libfunc (optable, opname, suffix, mode); | |
5565 | } | |
5566 | ||
5567 | /* Like gen_libfunc, but verify that unsigned fixed-point operation is | |
5568 | involved. */ | |
5569 | ||
5570 | static void | |
5571 | gen_unsigned_fixed_libfunc (optab optable, const char *opname, char suffix, | |
5572 | enum machine_mode mode) | |
5573 | { | |
5574 | if (!UNSIGNED_FIXED_POINT_MODE_P (mode)) | |
5575 | return; | |
5576 | gen_libfunc (optable, opname, suffix, mode); | |
5577 | } | |
5578 | ||
f36b9f69 | 5579 | /* Like gen_libfunc, but verify that FP or INT operation is involved. */ |
5580 | ||
5581 | static void | |
5582 | gen_int_fp_libfunc (optab optable, const char *name, char suffix, | |
5583 | enum machine_mode mode) | |
5584 | { | |
5585 | if (DECIMAL_FLOAT_MODE_P (mode) || GET_MODE_CLASS (mode) == MODE_FLOAT) | |
5586 | gen_fp_libfunc (optable, name, suffix, mode); | |
5587 | if (INTEGRAL_MODE_P (mode)) | |
5588 | gen_int_libfunc (optable, name, suffix, mode); | |
5589 | } | |
5590 | ||
5591 | /* Like gen_libfunc, but verify that FP or INT operation is involved | |
5592 | and add 'v' suffix for integer operation. */ | |
5593 | ||
5594 | static void | |
5595 | gen_intv_fp_libfunc (optab optable, const char *name, char suffix, | |
5596 | enum machine_mode mode) | |
5597 | { | |
5598 | if (DECIMAL_FLOAT_MODE_P (mode) || GET_MODE_CLASS (mode) == MODE_FLOAT) | |
5599 | gen_fp_libfunc (optable, name, suffix, mode); | |
5600 | if (GET_MODE_CLASS (mode) == MODE_INT) | |
5601 | { | |
5602 | int len = strlen (name); | |
4077bf7a | 5603 | char *v_name = XALLOCAVEC (char, len + 2); |
f36b9f69 | 5604 | strcpy (v_name, name); |
5605 | v_name[len] = 'v'; | |
5606 | v_name[len + 1] = 0; | |
5607 | gen_int_libfunc (optable, v_name, suffix, mode); | |
5608 | } | |
c2a91a88 | 5609 | } |
5610 | ||
68a556d6 | 5611 | /* Like gen_libfunc, but verify that FP or INT or FIXED operation is |
5612 | involved. */ | |
5613 | ||
5614 | static void | |
5615 | gen_int_fp_fixed_libfunc (optab optable, const char *name, char suffix, | |
5616 | enum machine_mode mode) | |
5617 | { | |
5618 | if (DECIMAL_FLOAT_MODE_P (mode) || GET_MODE_CLASS (mode) == MODE_FLOAT) | |
5619 | gen_fp_libfunc (optable, name, suffix, mode); | |
5620 | if (INTEGRAL_MODE_P (mode)) | |
5621 | gen_int_libfunc (optable, name, suffix, mode); | |
5622 | if (ALL_FIXED_POINT_MODE_P (mode)) | |
5623 | gen_fixed_libfunc (optable, name, suffix, mode); | |
5624 | } | |
5625 | ||
5626 | /* Like gen_libfunc, but verify that FP or INT or signed FIXED operation is | |
5627 | involved. */ | |
5628 | ||
5629 | static void | |
5630 | gen_int_fp_signed_fixed_libfunc (optab optable, const char *name, char suffix, | |
5631 | enum machine_mode mode) | |
5632 | { | |
5633 | if (DECIMAL_FLOAT_MODE_P (mode) || GET_MODE_CLASS (mode) == MODE_FLOAT) | |
5634 | gen_fp_libfunc (optable, name, suffix, mode); | |
5635 | if (INTEGRAL_MODE_P (mode)) | |
5636 | gen_int_libfunc (optable, name, suffix, mode); | |
5637 | if (SIGNED_FIXED_POINT_MODE_P (mode)) | |
5638 | gen_signed_fixed_libfunc (optable, name, suffix, mode); | |
5639 | } | |
5640 | ||
5641 | /* Like gen_libfunc, but verify that INT or FIXED operation is | |
5642 | involved. */ | |
5643 | ||
5644 | static void | |
5645 | gen_int_fixed_libfunc (optab optable, const char *name, char suffix, | |
5646 | enum machine_mode mode) | |
5647 | { | |
5648 | if (INTEGRAL_MODE_P (mode)) | |
5649 | gen_int_libfunc (optable, name, suffix, mode); | |
5650 | if (ALL_FIXED_POINT_MODE_P (mode)) | |
5651 | gen_fixed_libfunc (optable, name, suffix, mode); | |
5652 | } | |
5653 | ||
5654 | /* Like gen_libfunc, but verify that INT or signed FIXED operation is | |
5655 | involved. */ | |
5656 | ||
5657 | static void | |
5658 | gen_int_signed_fixed_libfunc (optab optable, const char *name, char suffix, | |
5659 | enum machine_mode mode) | |
5660 | { | |
5661 | if (INTEGRAL_MODE_P (mode)) | |
5662 | gen_int_libfunc (optable, name, suffix, mode); | |
5663 | if (SIGNED_FIXED_POINT_MODE_P (mode)) | |
5664 | gen_signed_fixed_libfunc (optable, name, suffix, mode); | |
5665 | } | |
5666 | ||
5667 | /* Like gen_libfunc, but verify that INT or unsigned FIXED operation is | |
5668 | involved. */ | |
5669 | ||
5670 | static void | |
5671 | gen_int_unsigned_fixed_libfunc (optab optable, const char *name, char suffix, | |
5672 | enum machine_mode mode) | |
5673 | { | |
5674 | if (INTEGRAL_MODE_P (mode)) | |
5675 | gen_int_libfunc (optable, name, suffix, mode); | |
5676 | if (UNSIGNED_FIXED_POINT_MODE_P (mode)) | |
5677 | gen_unsigned_fixed_libfunc (optable, name, suffix, mode); | |
5678 | } | |
5679 | ||
a7cc195f | 5680 | /* Initialize the libfunc fields of an entire group of entries of an |
5681 | inter-mode-class conversion optab. The string formation rules are | |
5682 | similar to the ones for init_libfuncs, above, but instead of having | |
5683 | a mode name and an operand count these functions have two mode names | |
5684 | and no operand count. */ | |
f36b9f69 | 5685 | |
a7cc195f | 5686 | static void |
f36b9f69 | 5687 | gen_interclass_conv_libfunc (convert_optab tab, |
5688 | const char *opname, | |
5689 | enum machine_mode tmode, | |
5690 | enum machine_mode fmode) | |
a7cc195f | 5691 | { |
a7cc195f | 5692 | size_t opname_len = strlen (opname); |
f36b9f69 | 5693 | size_t mname_len = 0; |
a7cc195f | 5694 | |
a7cc195f | 5695 | const char *fname, *tname; |
5696 | const char *q; | |
5697 | char *libfunc_name, *suffix; | |
10de71e1 | 5698 | char *nondec_name, *dec_name, *nondec_suffix, *dec_suffix; |
a7cc195f | 5699 | char *p; |
5700 | ||
10de71e1 | 5701 | /* If this is a decimal conversion, add the current BID vs. DPD prefix that |
5702 | depends on which underlying decimal floating point format is used. */ | |
5703 | const size_t dec_len = sizeof (DECIMAL_PREFIX) - 1; | |
5704 | ||
f36b9f69 | 5705 | mname_len = strlen (GET_MODE_NAME (tmode)) + strlen (GET_MODE_NAME (fmode)); |
a7cc195f | 5706 | |
4077bf7a | 5707 | nondec_name = XALLOCAVEC (char, 2 + opname_len + mname_len + 1 + 1); |
10de71e1 | 5708 | nondec_name[0] = '_'; |
5709 | nondec_name[1] = '_'; | |
5710 | memcpy (&nondec_name[2], opname, opname_len); | |
5711 | nondec_suffix = nondec_name + opname_len + 2; | |
5712 | ||
4077bf7a | 5713 | dec_name = XALLOCAVEC (char, 2 + dec_len + opname_len + mname_len + 1 + 1); |
10de71e1 | 5714 | dec_name[0] = '_'; |
5715 | dec_name[1] = '_'; | |
5716 | memcpy (&dec_name[2], DECIMAL_PREFIX, dec_len); | |
5717 | memcpy (&dec_name[2+dec_len], opname, opname_len); | |
5718 | dec_suffix = dec_name + dec_len + opname_len + 2; | |
a7cc195f | 5719 | |
f36b9f69 | 5720 | fname = GET_MODE_NAME (fmode); |
5721 | tname = GET_MODE_NAME (tmode); | |
a7cc195f | 5722 | |
f36b9f69 | 5723 | if (DECIMAL_FLOAT_MODE_P(fmode) || DECIMAL_FLOAT_MODE_P(tmode)) |
5724 | { | |
5725 | libfunc_name = dec_name; | |
5726 | suffix = dec_suffix; | |
5727 | } | |
5728 | else | |
5729 | { | |
5730 | libfunc_name = nondec_name; | |
5731 | suffix = nondec_suffix; | |
5732 | } | |
10de71e1 | 5733 | |
f36b9f69 | 5734 | p = suffix; |
5735 | for (q = fname; *q; p++, q++) | |
5736 | *p = TOLOWER (*q); | |
5737 | for (q = tname; *q; p++, q++) | |
5738 | *p = TOLOWER (*q); | |
a7cc195f | 5739 | |
f36b9f69 | 5740 | *p = '\0'; |
a7cc195f | 5741 | |
f36b9f69 | 5742 | set_conv_libfunc (tab, tmode, fmode, |
5743 | ggc_alloc_string (libfunc_name, p - libfunc_name)); | |
a7cc195f | 5744 | } |
5745 | ||
f36b9f69 | 5746 | /* Same as gen_interclass_conv_libfunc but verify that we are producing |
5747 | int->fp conversion. */ | |
5748 | ||
a7cc195f | 5749 | static void |
f36b9f69 | 5750 | gen_int_to_fp_conv_libfunc (convert_optab tab, |
5751 | const char *opname, | |
5752 | enum machine_mode tmode, | |
5753 | enum machine_mode fmode) | |
5754 | { | |
5755 | if (GET_MODE_CLASS (fmode) != MODE_INT) | |
5756 | return; | |
5757 | if (GET_MODE_CLASS (tmode) != MODE_FLOAT && !DECIMAL_FLOAT_MODE_P (tmode)) | |
5758 | return; | |
5759 | gen_interclass_conv_libfunc (tab, opname, tmode, fmode); | |
5760 | } | |
5761 | ||
5762 | /* ufloat_optab is special by using floatun for FP and floatuns decimal fp | |
5763 | naming scheme. */ | |
5764 | ||
5765 | static void | |
5766 | gen_ufloat_conv_libfunc (convert_optab tab, | |
5767 | const char *opname ATTRIBUTE_UNUSED, | |
5768 | enum machine_mode tmode, | |
5769 | enum machine_mode fmode) | |
5770 | { | |
5771 | if (DECIMAL_FLOAT_MODE_P (tmode)) | |
5772 | gen_int_to_fp_conv_libfunc (tab, "floatuns", tmode, fmode); | |
5773 | else | |
5774 | gen_int_to_fp_conv_libfunc (tab, "floatun", tmode, fmode); | |
5775 | } | |
5776 | ||
5777 | /* Same as gen_interclass_conv_libfunc but verify that we are producing | |
5778 | fp->int conversion. */ | |
5779 | ||
5780 | static void | |
5781 | gen_int_to_fp_nondecimal_conv_libfunc (convert_optab tab, | |
5782 | const char *opname, | |
5783 | enum machine_mode tmode, | |
5784 | enum machine_mode fmode) | |
5785 | { | |
5786 | if (GET_MODE_CLASS (fmode) != MODE_INT) | |
5787 | return; | |
5788 | if (GET_MODE_CLASS (tmode) != MODE_FLOAT) | |
5789 | return; | |
5790 | gen_interclass_conv_libfunc (tab, opname, tmode, fmode); | |
5791 | } | |
5792 | ||
5793 | /* Same as gen_interclass_conv_libfunc but verify that we are producing | |
5794 | fp->int conversion with no decimal floating point involved. */ | |
5795 | ||
5796 | static void | |
5797 | gen_fp_to_int_conv_libfunc (convert_optab tab, | |
5798 | const char *opname, | |
5799 | enum machine_mode tmode, | |
5800 | enum machine_mode fmode) | |
5801 | { | |
5802 | if (GET_MODE_CLASS (fmode) != MODE_FLOAT && !DECIMAL_FLOAT_MODE_P (fmode)) | |
5803 | return; | |
5804 | if (GET_MODE_CLASS (tmode) != MODE_INT) | |
5805 | return; | |
5806 | gen_interclass_conv_libfunc (tab, opname, tmode, fmode); | |
5807 | } | |
5808 | ||
f0b5f617 | 5809 | /* Initialize the libfunc fields of an of an intra-mode-class conversion optab. |
f36b9f69 | 5810 | The string formation rules are |
5811 | similar to the ones for init_libfunc, above. */ | |
5812 | ||
5813 | static void | |
5814 | gen_intraclass_conv_libfunc (convert_optab tab, const char *opname, | |
5815 | enum machine_mode tmode, enum machine_mode fmode) | |
a7cc195f | 5816 | { |
a7cc195f | 5817 | size_t opname_len = strlen (opname); |
f36b9f69 | 5818 | size_t mname_len = 0; |
a7cc195f | 5819 | |
f36b9f69 | 5820 | const char *fname, *tname; |
a7cc195f | 5821 | const char *q; |
10de71e1 | 5822 | char *nondec_name, *dec_name, *nondec_suffix, *dec_suffix; |
a7cc195f | 5823 | char *libfunc_name, *suffix; |
5824 | char *p; | |
5825 | ||
10de71e1 | 5826 | /* If this is a decimal conversion, add the current BID vs. DPD prefix that |
5827 | depends on which underlying decimal floating point format is used. */ | |
5828 | const size_t dec_len = sizeof (DECIMAL_PREFIX) - 1; | |
5829 | ||
f36b9f69 | 5830 | mname_len = strlen (GET_MODE_NAME (tmode)) + strlen (GET_MODE_NAME (fmode)); |
a7cc195f | 5831 | |
4077bf7a | 5832 | nondec_name = XALLOCAVEC (char, 2 + opname_len + mname_len + 1 + 1); |
10de71e1 | 5833 | nondec_name[0] = '_'; |
5834 | nondec_name[1] = '_'; | |
5835 | memcpy (&nondec_name[2], opname, opname_len); | |
5836 | nondec_suffix = nondec_name + opname_len + 2; | |
5837 | ||
4077bf7a | 5838 | dec_name = XALLOCAVEC (char, 2 + dec_len + opname_len + mname_len + 1 + 1); |
10de71e1 | 5839 | dec_name[0] = '_'; |
5840 | dec_name[1] = '_'; | |
5841 | memcpy (&dec_name[2], DECIMAL_PREFIX, dec_len); | |
5842 | memcpy (&dec_name[2 + dec_len], opname, opname_len); | |
5843 | dec_suffix = dec_name + dec_len + opname_len + 2; | |
a7cc195f | 5844 | |
f36b9f69 | 5845 | fname = GET_MODE_NAME (fmode); |
5846 | tname = GET_MODE_NAME (tmode); | |
a7cc195f | 5847 | |
f36b9f69 | 5848 | if (DECIMAL_FLOAT_MODE_P(fmode) || DECIMAL_FLOAT_MODE_P(tmode)) |
5849 | { | |
5850 | libfunc_name = dec_name; | |
5851 | suffix = dec_suffix; | |
5852 | } | |
5853 | else | |
5854 | { | |
5855 | libfunc_name = nondec_name; | |
5856 | suffix = nondec_suffix; | |
5857 | } | |
10de71e1 | 5858 | |
f36b9f69 | 5859 | p = suffix; |
5860 | for (q = fname; *q; p++, q++) | |
5861 | *p = TOLOWER (*q); | |
5862 | for (q = tname; *q; p++, q++) | |
5863 | *p = TOLOWER (*q); | |
a7cc195f | 5864 | |
f36b9f69 | 5865 | *p++ = '2'; |
5866 | *p = '\0'; | |
a7cc195f | 5867 | |
f36b9f69 | 5868 | set_conv_libfunc (tab, tmode, fmode, |
5869 | ggc_alloc_string (libfunc_name, p - libfunc_name)); | |
a7cc195f | 5870 | } |
5871 | ||
f36b9f69 | 5872 | /* Pick proper libcall for trunc_optab. We need to chose if we do |
5873 | truncation or extension and interclass or intraclass. */ | |
5874 | ||
5875 | static void | |
5876 | gen_trunc_conv_libfunc (convert_optab tab, | |
5877 | const char *opname, | |
5878 | enum machine_mode tmode, | |
5879 | enum machine_mode fmode) | |
5880 | { | |
5881 | if (GET_MODE_CLASS (tmode) != MODE_FLOAT && !DECIMAL_FLOAT_MODE_P (tmode)) | |
5882 | return; | |
5883 | if (GET_MODE_CLASS (fmode) != MODE_FLOAT && !DECIMAL_FLOAT_MODE_P (fmode)) | |
5884 | return; | |
5885 | if (tmode == fmode) | |
5886 | return; | |
5887 | ||
5888 | if ((GET_MODE_CLASS (tmode) == MODE_FLOAT && DECIMAL_FLOAT_MODE_P (fmode)) | |
5889 | || (GET_MODE_CLASS (fmode) == MODE_FLOAT && DECIMAL_FLOAT_MODE_P (tmode))) | |
5890 | gen_interclass_conv_libfunc (tab, opname, tmode, fmode); | |
5891 | ||
5892 | if (GET_MODE_PRECISION (fmode) <= GET_MODE_PRECISION (tmode)) | |
5893 | return; | |
5894 | ||
5895 | if ((GET_MODE_CLASS (tmode) == MODE_FLOAT | |
5896 | && GET_MODE_CLASS (fmode) == MODE_FLOAT) | |
5897 | || (DECIMAL_FLOAT_MODE_P (fmode) && DECIMAL_FLOAT_MODE_P (tmode))) | |
5898 | gen_intraclass_conv_libfunc (tab, opname, tmode, fmode); | |
5899 | } | |
5900 | ||
5901 | /* Pick proper libcall for extend_optab. We need to chose if we do | |
5902 | truncation or extension and interclass or intraclass. */ | |
5903 | ||
5904 | static void | |
5905 | gen_extend_conv_libfunc (convert_optab tab, | |
5906 | const char *opname ATTRIBUTE_UNUSED, | |
5907 | enum machine_mode tmode, | |
5908 | enum machine_mode fmode) | |
5909 | { | |
5910 | if (GET_MODE_CLASS (tmode) != MODE_FLOAT && !DECIMAL_FLOAT_MODE_P (tmode)) | |
5911 | return; | |
5912 | if (GET_MODE_CLASS (fmode) != MODE_FLOAT && !DECIMAL_FLOAT_MODE_P (fmode)) | |
5913 | return; | |
5914 | if (tmode == fmode) | |
5915 | return; | |
5916 | ||
5917 | if ((GET_MODE_CLASS (tmode) == MODE_FLOAT && DECIMAL_FLOAT_MODE_P (fmode)) | |
5918 | || (GET_MODE_CLASS (fmode) == MODE_FLOAT && DECIMAL_FLOAT_MODE_P (tmode))) | |
5919 | gen_interclass_conv_libfunc (tab, opname, tmode, fmode); | |
5920 | ||
5921 | if (GET_MODE_PRECISION (fmode) > GET_MODE_PRECISION (tmode)) | |
5922 | return; | |
5923 | ||
5924 | if ((GET_MODE_CLASS (tmode) == MODE_FLOAT | |
5925 | && GET_MODE_CLASS (fmode) == MODE_FLOAT) | |
5926 | || (DECIMAL_FLOAT_MODE_P (fmode) && DECIMAL_FLOAT_MODE_P (tmode))) | |
5927 | gen_intraclass_conv_libfunc (tab, opname, tmode, fmode); | |
5928 | } | |
a7cc195f | 5929 | |
68a556d6 | 5930 | /* Pick proper libcall for fract_optab. We need to chose if we do |
5931 | interclass or intraclass. */ | |
5932 | ||
5933 | static void | |
5934 | gen_fract_conv_libfunc (convert_optab tab, | |
5935 | const char *opname, | |
5936 | enum machine_mode tmode, | |
5937 | enum machine_mode fmode) | |
5938 | { | |
5939 | if (tmode == fmode) | |
5940 | return; | |
5941 | if (!(ALL_FIXED_POINT_MODE_P (tmode) || ALL_FIXED_POINT_MODE_P (fmode))) | |
5942 | return; | |
5943 | ||
5944 | if (GET_MODE_CLASS (tmode) == GET_MODE_CLASS (fmode)) | |
5945 | gen_intraclass_conv_libfunc (tab, opname, tmode, fmode); | |
5946 | else | |
5947 | gen_interclass_conv_libfunc (tab, opname, tmode, fmode); | |
5948 | } | |
5949 | ||
5950 | /* Pick proper libcall for fractuns_optab. */ | |
5951 | ||
5952 | static void | |
5953 | gen_fractuns_conv_libfunc (convert_optab tab, | |
5954 | const char *opname, | |
5955 | enum machine_mode tmode, | |
5956 | enum machine_mode fmode) | |
5957 | { | |
5958 | if (tmode == fmode) | |
5959 | return; | |
5960 | /* One mode must be a fixed-point mode, and the other must be an integer | |
5961 | mode. */ | |
5962 | if (!((ALL_FIXED_POINT_MODE_P (tmode) && GET_MODE_CLASS (fmode) == MODE_INT) | |
5963 | || (ALL_FIXED_POINT_MODE_P (fmode) | |
5964 | && GET_MODE_CLASS (tmode) == MODE_INT))) | |
5965 | return; | |
5966 | ||
5967 | gen_interclass_conv_libfunc (tab, opname, tmode, fmode); | |
5968 | } | |
5969 | ||
5970 | /* Pick proper libcall for satfract_optab. We need to chose if we do | |
5971 | interclass or intraclass. */ | |
5972 | ||
5973 | static void | |
5974 | gen_satfract_conv_libfunc (convert_optab tab, | |
5975 | const char *opname, | |
5976 | enum machine_mode tmode, | |
5977 | enum machine_mode fmode) | |
5978 | { | |
5979 | if (tmode == fmode) | |
5980 | return; | |
5981 | /* TMODE must be a fixed-point mode. */ | |
5982 | if (!ALL_FIXED_POINT_MODE_P (tmode)) | |
5983 | return; | |
5984 | ||
5985 | if (GET_MODE_CLASS (tmode) == GET_MODE_CLASS (fmode)) | |
5986 | gen_intraclass_conv_libfunc (tab, opname, tmode, fmode); | |
5987 | else | |
5988 | gen_interclass_conv_libfunc (tab, opname, tmode, fmode); | |
5989 | } | |
5990 | ||
5991 | /* Pick proper libcall for satfractuns_optab. */ | |
5992 | ||
5993 | static void | |
5994 | gen_satfractuns_conv_libfunc (convert_optab tab, | |
5995 | const char *opname, | |
5996 | enum machine_mode tmode, | |
5997 | enum machine_mode fmode) | |
5998 | { | |
5999 | if (tmode == fmode) | |
6000 | return; | |
6001 | /* TMODE must be a fixed-point mode, and FMODE must be an integer mode. */ | |
6002 | if (!(ALL_FIXED_POINT_MODE_P (tmode) && GET_MODE_CLASS (fmode) == MODE_INT)) | |
6003 | return; | |
6004 | ||
6005 | gen_interclass_conv_libfunc (tab, opname, tmode, fmode); | |
6006 | } | |
6007 | ||
c312b853 | 6008 | /* A table of previously-created libfuncs, hashed by name. */ |
6009 | static GTY ((param_is (union tree_node))) htab_t libfunc_decls; | |
001be062 | 6010 | |
c312b853 | 6011 | /* Hashtable callbacks for libfunc_decls. */ |
87a0fb80 | 6012 | |
c312b853 | 6013 | static hashval_t |
6014 | libfunc_decl_hash (const void *entry) | |
6015 | { | |
9d61b2aa | 6016 | return htab_hash_string (IDENTIFIER_POINTER (DECL_NAME ((const_tree) entry))); |
c312b853 | 6017 | } |
001be062 | 6018 | |
c312b853 | 6019 | static int |
6020 | libfunc_decl_eq (const void *entry1, const void *entry2) | |
6021 | { | |
9d61b2aa | 6022 | return DECL_NAME ((const_tree) entry1) == (const_tree) entry2; |
c312b853 | 6023 | } |
001be062 | 6024 | |
c312b853 | 6025 | rtx |
6026 | init_one_libfunc (const char *name) | |
6027 | { | |
6028 | tree id, decl; | |
6029 | void **slot; | |
6030 | hashval_t hash; | |
6031 | ||
6032 | if (libfunc_decls == NULL) | |
6033 | libfunc_decls = htab_create_ggc (37, libfunc_decl_hash, | |
6034 | libfunc_decl_eq, NULL); | |
6035 | ||
6036 | /* See if we have already created a libfunc decl for this function. */ | |
6037 | id = get_identifier (name); | |
6038 | hash = htab_hash_string (name); | |
6039 | slot = htab_find_slot_with_hash (libfunc_decls, id, hash, INSERT); | |
6040 | decl = (tree) *slot; | |
6041 | if (decl == NULL) | |
6042 | { | |
6043 | /* Create a new decl, so that it can be passed to | |
6044 | targetm.encode_section_info. */ | |
6045 | /* ??? We don't have any type information except for this is | |
6046 | a function. Pretend this is "int foo()". */ | |
e60a6f7b | 6047 | decl = build_decl (UNKNOWN_LOCATION, |
6048 | FUNCTION_DECL, get_identifier (name), | |
c312b853 | 6049 | build_function_type (integer_type_node, NULL_TREE)); |
6050 | DECL_ARTIFICIAL (decl) = 1; | |
6051 | DECL_EXTERNAL (decl) = 1; | |
6052 | TREE_PUBLIC (decl) = 1; | |
6053 | ||
6054 | /* Zap the nonsensical SYMBOL_REF_DECL for this. What we're left with | |
6055 | are the flags assigned by targetm.encode_section_info. */ | |
6056 | SET_SYMBOL_REF_DECL (XEXP (DECL_RTL (decl), 0), NULL); | |
6057 | ||
6058 | *slot = decl; | |
6059 | } | |
6060 | return XEXP (DECL_RTL (decl), 0); | |
2c8daaf1 | 6061 | } |
6062 | ||
979d3efc | 6063 | /* Adjust the assembler name of libfunc NAME to ASMSPEC. */ |
6064 | ||
6065 | rtx | |
6066 | set_user_assembler_libfunc (const char *name, const char *asmspec) | |
6067 | { | |
6068 | tree id, decl; | |
6069 | void **slot; | |
6070 | hashval_t hash; | |
6071 | ||
6072 | id = get_identifier (name); | |
6073 | hash = htab_hash_string (name); | |
6074 | slot = htab_find_slot_with_hash (libfunc_decls, id, hash, NO_INSERT); | |
6075 | gcc_assert (slot); | |
6076 | decl = (tree) *slot; | |
6077 | set_user_assembler_name (decl, asmspec); | |
6078 | return XEXP (DECL_RTL (decl), 0); | |
6079 | } | |
6080 | ||
f2f543a3 | 6081 | /* Call this to reset the function entry for one optab (OPTABLE) in mode |
6082 | MODE to NAME, which should be either 0 or a string constant. */ | |
6083 | void | |
6084 | set_optab_libfunc (optab optable, enum machine_mode mode, const char *name) | |
6085 | { | |
f36b9f69 | 6086 | rtx val; |
6087 | struct libfunc_entry e; | |
6088 | struct libfunc_entry **slot; | |
be5cecfd | 6089 | e.optab = (size_t) (optable - &optab_table[0]); |
f36b9f69 | 6090 | e.mode1 = mode; |
6091 | e.mode2 = VOIDmode; | |
6092 | ||
f2f543a3 | 6093 | if (name) |
f36b9f69 | 6094 | val = init_one_libfunc (name); |
f2f543a3 | 6095 | else |
f36b9f69 | 6096 | val = 0; |
6097 | slot = (struct libfunc_entry **) htab_find_slot (libfunc_hash, &e, INSERT); | |
6098 | if (*slot == NULL) | |
4077bf7a | 6099 | *slot = GGC_NEW (struct libfunc_entry); |
be5cecfd | 6100 | (*slot)->optab = (size_t) (optable - &optab_table[0]); |
f36b9f69 | 6101 | (*slot)->mode1 = mode; |
6102 | (*slot)->mode2 = VOIDmode; | |
6103 | (*slot)->libfunc = val; | |
f2f543a3 | 6104 | } |
6105 | ||
a7cc195f | 6106 | /* Call this to reset the function entry for one conversion optab |
6107 | (OPTABLE) from mode FMODE to mode TMODE to NAME, which should be | |
6108 | either 0 or a string constant. */ | |
6109 | void | |
6110 | set_conv_libfunc (convert_optab optable, enum machine_mode tmode, | |
6111 | enum machine_mode fmode, const char *name) | |
6112 | { | |
f36b9f69 | 6113 | rtx val; |
6114 | struct libfunc_entry e; | |
6115 | struct libfunc_entry **slot; | |
be5cecfd | 6116 | e.optab = (size_t) (optable - &convert_optab_table[0]); |
f36b9f69 | 6117 | e.mode1 = tmode; |
6118 | e.mode2 = fmode; | |
6119 | ||
a7cc195f | 6120 | if (name) |
f36b9f69 | 6121 | val = init_one_libfunc (name); |
a7cc195f | 6122 | else |
f36b9f69 | 6123 | val = 0; |
6124 | slot = (struct libfunc_entry **) htab_find_slot (libfunc_hash, &e, INSERT); | |
6125 | if (*slot == NULL) | |
4077bf7a | 6126 | *slot = GGC_NEW (struct libfunc_entry); |
be5cecfd | 6127 | (*slot)->optab = (size_t) (optable - &convert_optab_table[0]); |
f36b9f69 | 6128 | (*slot)->mode1 = tmode; |
6129 | (*slot)->mode2 = fmode; | |
6130 | (*slot)->libfunc = val; | |
a7cc195f | 6131 | } |
6132 | ||
6d8b68a3 | 6133 | /* Call this to initialize the contents of the optabs |
1f215c26 | 6134 | appropriately for the current target machine. */ |
6135 | ||
6136 | void | |
3ad4992f | 6137 | init_optabs (void) |
1f215c26 | 6138 | { |
a7cc195f | 6139 | unsigned int i; |
02bf340a | 6140 | enum machine_mode int_mode; |
53b14d73 | 6141 | static bool reinit; |
1f215c26 | 6142 | |
f36b9f69 | 6143 | libfunc_hash = htab_create_ggc (10, hash_libfunc, eq_libfunc, NULL); |
2850b1f2 | 6144 | /* Start by initializing all tables to contain CODE_FOR_nothing. */ |
1f215c26 | 6145 | |
62528147 | 6146 | #ifdef HAVE_conditional_move |
6147 | for (i = 0; i < NUM_MACHINE_MODES; i++) | |
6148 | movcc_gen_code[i] = CODE_FOR_nothing; | |
6149 | #endif | |
6150 | ||
6b7acc28 | 6151 | for (i = 0; i < NUM_MACHINE_MODES; i++) |
6152 | { | |
6153 | vcond_gen_code[i] = CODE_FOR_nothing; | |
6154 | vcondu_gen_code[i] = CODE_FOR_nothing; | |
6155 | } | |
6156 | ||
423aab86 | 6157 | #if GCC_VERSION >= 4000 && HAVE_DESIGNATED_INITIALIZERS |
53b14d73 | 6158 | /* We statically initialize the insn_codes with CODE_FOR_nothing. */ |
6159 | if (reinit) | |
6160 | init_insn_codes (); | |
6161 | #else | |
6162 | init_insn_codes (); | |
6163 | #endif | |
6164 | ||
be5cecfd | 6165 | init_optab (add_optab, PLUS); |
6166 | init_optabv (addv_optab, PLUS); | |
6167 | init_optab (sub_optab, MINUS); | |
6168 | init_optabv (subv_optab, MINUS); | |
6169 | init_optab (ssadd_optab, SS_PLUS); | |
6170 | init_optab (usadd_optab, US_PLUS); | |
6171 | init_optab (sssub_optab, SS_MINUS); | |
6172 | init_optab (ussub_optab, US_MINUS); | |
6173 | init_optab (smul_optab, MULT); | |
6174 | init_optab (ssmul_optab, SS_MULT); | |
6175 | init_optab (usmul_optab, US_MULT); | |
6176 | init_optabv (smulv_optab, MULT); | |
6177 | init_optab (smul_highpart_optab, UNKNOWN); | |
6178 | init_optab (umul_highpart_optab, UNKNOWN); | |
6179 | init_optab (smul_widen_optab, UNKNOWN); | |
6180 | init_optab (umul_widen_optab, UNKNOWN); | |
6181 | init_optab (usmul_widen_optab, UNKNOWN); | |
6182 | init_optab (smadd_widen_optab, UNKNOWN); | |
6183 | init_optab (umadd_widen_optab, UNKNOWN); | |
6184 | init_optab (ssmadd_widen_optab, UNKNOWN); | |
6185 | init_optab (usmadd_widen_optab, UNKNOWN); | |
6186 | init_optab (smsub_widen_optab, UNKNOWN); | |
6187 | init_optab (umsub_widen_optab, UNKNOWN); | |
6188 | init_optab (ssmsub_widen_optab, UNKNOWN); | |
6189 | init_optab (usmsub_widen_optab, UNKNOWN); | |
6190 | init_optab (sdiv_optab, DIV); | |
6191 | init_optab (ssdiv_optab, SS_DIV); | |
6192 | init_optab (usdiv_optab, US_DIV); | |
6193 | init_optabv (sdivv_optab, DIV); | |
6194 | init_optab (sdivmod_optab, UNKNOWN); | |
6195 | init_optab (udiv_optab, UDIV); | |
6196 | init_optab (udivmod_optab, UNKNOWN); | |
6197 | init_optab (smod_optab, MOD); | |
6198 | init_optab (umod_optab, UMOD); | |
6199 | init_optab (fmod_optab, UNKNOWN); | |
6200 | init_optab (remainder_optab, UNKNOWN); | |
6201 | init_optab (ftrunc_optab, UNKNOWN); | |
6202 | init_optab (and_optab, AND); | |
6203 | init_optab (ior_optab, IOR); | |
6204 | init_optab (xor_optab, XOR); | |
6205 | init_optab (ashl_optab, ASHIFT); | |
6206 | init_optab (ssashl_optab, SS_ASHIFT); | |
6207 | init_optab (usashl_optab, US_ASHIFT); | |
6208 | init_optab (ashr_optab, ASHIFTRT); | |
6209 | init_optab (lshr_optab, LSHIFTRT); | |
6210 | init_optab (rotl_optab, ROTATE); | |
6211 | init_optab (rotr_optab, ROTATERT); | |
6212 | init_optab (smin_optab, SMIN); | |
6213 | init_optab (smax_optab, SMAX); | |
6214 | init_optab (umin_optab, UMIN); | |
6215 | init_optab (umax_optab, UMAX); | |
6216 | init_optab (pow_optab, UNKNOWN); | |
6217 | init_optab (atan2_optab, UNKNOWN); | |
ad99e708 | 6218 | |
6219 | /* These three have codes assigned exclusively for the sake of | |
6220 | have_insn_for. */ | |
be5cecfd | 6221 | init_optab (mov_optab, SET); |
6222 | init_optab (movstrict_optab, STRICT_LOW_PART); | |
74f4459c | 6223 | init_optab (cbranch_optab, COMPARE); |
6224 | ||
6225 | init_optab (cmov_optab, UNKNOWN); | |
6226 | init_optab (cstore_optab, UNKNOWN); | |
6227 | init_optab (ctrap_optab, UNKNOWN); | |
be5cecfd | 6228 | |
6229 | init_optab (storent_optab, UNKNOWN); | |
6230 | ||
74f4459c | 6231 | init_optab (cmp_optab, UNKNOWN); |
be5cecfd | 6232 | init_optab (ucmp_optab, UNKNOWN); |
be5cecfd | 6233 | |
6234 | init_optab (eq_optab, EQ); | |
6235 | init_optab (ne_optab, NE); | |
6236 | init_optab (gt_optab, GT); | |
6237 | init_optab (ge_optab, GE); | |
6238 | init_optab (lt_optab, LT); | |
6239 | init_optab (le_optab, LE); | |
6240 | init_optab (unord_optab, UNORDERED); | |
6241 | ||
6242 | init_optab (neg_optab, NEG); | |
6243 | init_optab (ssneg_optab, SS_NEG); | |
6244 | init_optab (usneg_optab, US_NEG); | |
6245 | init_optabv (negv_optab, NEG); | |
6246 | init_optab (abs_optab, ABS); | |
6247 | init_optabv (absv_optab, ABS); | |
6248 | init_optab (addcc_optab, UNKNOWN); | |
6249 | init_optab (one_cmpl_optab, NOT); | |
6250 | init_optab (bswap_optab, BSWAP); | |
6251 | init_optab (ffs_optab, FFS); | |
6252 | init_optab (clz_optab, CLZ); | |
6253 | init_optab (ctz_optab, CTZ); | |
6254 | init_optab (popcount_optab, POPCOUNT); | |
6255 | init_optab (parity_optab, PARITY); | |
6256 | init_optab (sqrt_optab, SQRT); | |
6257 | init_optab (floor_optab, UNKNOWN); | |
6258 | init_optab (ceil_optab, UNKNOWN); | |
6259 | init_optab (round_optab, UNKNOWN); | |
6260 | init_optab (btrunc_optab, UNKNOWN); | |
6261 | init_optab (nearbyint_optab, UNKNOWN); | |
6262 | init_optab (rint_optab, UNKNOWN); | |
6263 | init_optab (sincos_optab, UNKNOWN); | |
6264 | init_optab (sin_optab, UNKNOWN); | |
6265 | init_optab (asin_optab, UNKNOWN); | |
6266 | init_optab (cos_optab, UNKNOWN); | |
6267 | init_optab (acos_optab, UNKNOWN); | |
6268 | init_optab (exp_optab, UNKNOWN); | |
6269 | init_optab (exp10_optab, UNKNOWN); | |
6270 | init_optab (exp2_optab, UNKNOWN); | |
6271 | init_optab (expm1_optab, UNKNOWN); | |
6272 | init_optab (ldexp_optab, UNKNOWN); | |
6273 | init_optab (scalb_optab, UNKNOWN); | |
6274 | init_optab (logb_optab, UNKNOWN); | |
6275 | init_optab (ilogb_optab, UNKNOWN); | |
6276 | init_optab (log_optab, UNKNOWN); | |
6277 | init_optab (log10_optab, UNKNOWN); | |
6278 | init_optab (log2_optab, UNKNOWN); | |
6279 | init_optab (log1p_optab, UNKNOWN); | |
6280 | init_optab (tan_optab, UNKNOWN); | |
6281 | init_optab (atan_optab, UNKNOWN); | |
6282 | init_optab (copysign_optab, UNKNOWN); | |
6283 | init_optab (signbit_optab, UNKNOWN); | |
6284 | ||
6285 | init_optab (isinf_optab, UNKNOWN); | |
6286 | ||
6287 | init_optab (strlen_optab, UNKNOWN); | |
be5cecfd | 6288 | init_optab (push_optab, UNKNOWN); |
6289 | ||
6290 | init_optab (reduc_smax_optab, UNKNOWN); | |
6291 | init_optab (reduc_umax_optab, UNKNOWN); | |
6292 | init_optab (reduc_smin_optab, UNKNOWN); | |
6293 | init_optab (reduc_umin_optab, UNKNOWN); | |
6294 | init_optab (reduc_splus_optab, UNKNOWN); | |
6295 | init_optab (reduc_uplus_optab, UNKNOWN); | |
6296 | ||
6297 | init_optab (ssum_widen_optab, UNKNOWN); | |
6298 | init_optab (usum_widen_optab, UNKNOWN); | |
6299 | init_optab (sdot_prod_optab, UNKNOWN); | |
6300 | init_optab (udot_prod_optab, UNKNOWN); | |
6301 | ||
6302 | init_optab (vec_extract_optab, UNKNOWN); | |
6303 | init_optab (vec_extract_even_optab, UNKNOWN); | |
6304 | init_optab (vec_extract_odd_optab, UNKNOWN); | |
6305 | init_optab (vec_interleave_high_optab, UNKNOWN); | |
6306 | init_optab (vec_interleave_low_optab, UNKNOWN); | |
6307 | init_optab (vec_set_optab, UNKNOWN); | |
6308 | init_optab (vec_init_optab, UNKNOWN); | |
6309 | init_optab (vec_shl_optab, UNKNOWN); | |
6310 | init_optab (vec_shr_optab, UNKNOWN); | |
6311 | init_optab (vec_realign_load_optab, UNKNOWN); | |
6312 | init_optab (movmisalign_optab, UNKNOWN); | |
6313 | init_optab (vec_widen_umult_hi_optab, UNKNOWN); | |
6314 | init_optab (vec_widen_umult_lo_optab, UNKNOWN); | |
6315 | init_optab (vec_widen_smult_hi_optab, UNKNOWN); | |
6316 | init_optab (vec_widen_smult_lo_optab, UNKNOWN); | |
6317 | init_optab (vec_unpacks_hi_optab, UNKNOWN); | |
6318 | init_optab (vec_unpacks_lo_optab, UNKNOWN); | |
6319 | init_optab (vec_unpacku_hi_optab, UNKNOWN); | |
6320 | init_optab (vec_unpacku_lo_optab, UNKNOWN); | |
6321 | init_optab (vec_unpacks_float_hi_optab, UNKNOWN); | |
6322 | init_optab (vec_unpacks_float_lo_optab, UNKNOWN); | |
6323 | init_optab (vec_unpacku_float_hi_optab, UNKNOWN); | |
6324 | init_optab (vec_unpacku_float_lo_optab, UNKNOWN); | |
6325 | init_optab (vec_pack_trunc_optab, UNKNOWN); | |
6326 | init_optab (vec_pack_usat_optab, UNKNOWN); | |
6327 | init_optab (vec_pack_ssat_optab, UNKNOWN); | |
6328 | init_optab (vec_pack_ufix_trunc_optab, UNKNOWN); | |
6329 | init_optab (vec_pack_sfix_trunc_optab, UNKNOWN); | |
6330 | ||
6331 | init_optab (powi_optab, UNKNOWN); | |
757c219d | 6332 | |
a7cc195f | 6333 | /* Conversions. */ |
be5cecfd | 6334 | init_convert_optab (sext_optab, SIGN_EXTEND); |
6335 | init_convert_optab (zext_optab, ZERO_EXTEND); | |
6336 | init_convert_optab (trunc_optab, TRUNCATE); | |
6337 | init_convert_optab (sfix_optab, FIX); | |
6338 | init_convert_optab (ufix_optab, UNSIGNED_FIX); | |
6339 | init_convert_optab (sfixtrunc_optab, UNKNOWN); | |
6340 | init_convert_optab (ufixtrunc_optab, UNKNOWN); | |
6341 | init_convert_optab (sfloat_optab, FLOAT); | |
6342 | init_convert_optab (ufloat_optab, UNSIGNED_FLOAT); | |
6343 | init_convert_optab (lrint_optab, UNKNOWN); | |
6344 | init_convert_optab (lround_optab, UNKNOWN); | |
6345 | init_convert_optab (lfloor_optab, UNKNOWN); | |
6346 | init_convert_optab (lceil_optab, UNKNOWN); | |
6347 | ||
6348 | init_convert_optab (fract_optab, FRACT_CONVERT); | |
6349 | init_convert_optab (fractuns_optab, UNSIGNED_FRACT_CONVERT); | |
6350 | init_convert_optab (satfract_optab, SAT_FRACT); | |
6351 | init_convert_optab (satfractuns_optab, UNSIGNED_SAT_FRACT); | |
68a556d6 | 6352 | |
2850b1f2 | 6353 | for (i = 0; i < NUM_MACHINE_MODES; i++) |
6354 | { | |
008c057d | 6355 | movmem_optab[i] = CODE_FOR_nothing; |
0fbe5a3e | 6356 | cmpstr_optab[i] = CODE_FOR_nothing; |
6ac5504b | 6357 | cmpstrn_optab[i] = CODE_FOR_nothing; |
0fbe5a3e | 6358 | cmpmem_optab[i] = CODE_FOR_nothing; |
7a3e5564 | 6359 | setmem_optab[i] = CODE_FOR_nothing; |
2850b1f2 | 6360 | |
b6a5fc45 | 6361 | sync_add_optab[i] = CODE_FOR_nothing; |
6362 | sync_sub_optab[i] = CODE_FOR_nothing; | |
6363 | sync_ior_optab[i] = CODE_FOR_nothing; | |
6364 | sync_and_optab[i] = CODE_FOR_nothing; | |
6365 | sync_xor_optab[i] = CODE_FOR_nothing; | |
6366 | sync_nand_optab[i] = CODE_FOR_nothing; | |
6367 | sync_old_add_optab[i] = CODE_FOR_nothing; | |
6368 | sync_old_sub_optab[i] = CODE_FOR_nothing; | |
6369 | sync_old_ior_optab[i] = CODE_FOR_nothing; | |
6370 | sync_old_and_optab[i] = CODE_FOR_nothing; | |
6371 | sync_old_xor_optab[i] = CODE_FOR_nothing; | |
6372 | sync_old_nand_optab[i] = CODE_FOR_nothing; | |
6373 | sync_new_add_optab[i] = CODE_FOR_nothing; | |
6374 | sync_new_sub_optab[i] = CODE_FOR_nothing; | |
6375 | sync_new_ior_optab[i] = CODE_FOR_nothing; | |
6376 | sync_new_and_optab[i] = CODE_FOR_nothing; | |
6377 | sync_new_xor_optab[i] = CODE_FOR_nothing; | |
6378 | sync_new_nand_optab[i] = CODE_FOR_nothing; | |
6379 | sync_compare_and_swap[i] = CODE_FOR_nothing; | |
b6a5fc45 | 6380 | sync_lock_test_and_set[i] = CODE_FOR_nothing; |
6381 | sync_lock_release[i] = CODE_FOR_nothing; | |
6382 | ||
2850b1f2 | 6383 | reload_in_optab[i] = reload_out_optab[i] = CODE_FOR_nothing; |
2850b1f2 | 6384 | } |
6385 | ||
6386 | /* Fill in the optabs with the insns we support. */ | |
6387 | init_all_optabs (); | |
6388 | ||
2850b1f2 | 6389 | /* Initialize the optabs with the names of the library functions. */ |
f36b9f69 | 6390 | add_optab->libcall_basename = "add"; |
6391 | add_optab->libcall_suffix = '3'; | |
68a556d6 | 6392 | add_optab->libcall_gen = gen_int_fp_fixed_libfunc; |
f36b9f69 | 6393 | addv_optab->libcall_basename = "add"; |
6394 | addv_optab->libcall_suffix = '3'; | |
6395 | addv_optab->libcall_gen = gen_intv_fp_libfunc; | |
68a556d6 | 6396 | ssadd_optab->libcall_basename = "ssadd"; |
6397 | ssadd_optab->libcall_suffix = '3'; | |
6398 | ssadd_optab->libcall_gen = gen_signed_fixed_libfunc; | |
6399 | usadd_optab->libcall_basename = "usadd"; | |
6400 | usadd_optab->libcall_suffix = '3'; | |
6401 | usadd_optab->libcall_gen = gen_unsigned_fixed_libfunc; | |
f36b9f69 | 6402 | sub_optab->libcall_basename = "sub"; |
6403 | sub_optab->libcall_suffix = '3'; | |
68a556d6 | 6404 | sub_optab->libcall_gen = gen_int_fp_fixed_libfunc; |
f36b9f69 | 6405 | subv_optab->libcall_basename = "sub"; |
6406 | subv_optab->libcall_suffix = '3'; | |
6407 | subv_optab->libcall_gen = gen_intv_fp_libfunc; | |
68a556d6 | 6408 | sssub_optab->libcall_basename = "sssub"; |
6409 | sssub_optab->libcall_suffix = '3'; | |
6410 | sssub_optab->libcall_gen = gen_signed_fixed_libfunc; | |
6411 | ussub_optab->libcall_basename = "ussub"; | |
6412 | ussub_optab->libcall_suffix = '3'; | |
6413 | ussub_optab->libcall_gen = gen_unsigned_fixed_libfunc; | |
f36b9f69 | 6414 | smul_optab->libcall_basename = "mul"; |
6415 | smul_optab->libcall_suffix = '3'; | |
68a556d6 | 6416 | smul_optab->libcall_gen = gen_int_fp_fixed_libfunc; |
f36b9f69 | 6417 | smulv_optab->libcall_basename = "mul"; |
6418 | smulv_optab->libcall_suffix = '3'; | |
6419 | smulv_optab->libcall_gen = gen_intv_fp_libfunc; | |
68a556d6 | 6420 | ssmul_optab->libcall_basename = "ssmul"; |
6421 | ssmul_optab->libcall_suffix = '3'; | |
6422 | ssmul_optab->libcall_gen = gen_signed_fixed_libfunc; | |
6423 | usmul_optab->libcall_basename = "usmul"; | |
6424 | usmul_optab->libcall_suffix = '3'; | |
6425 | usmul_optab->libcall_gen = gen_unsigned_fixed_libfunc; | |
f36b9f69 | 6426 | sdiv_optab->libcall_basename = "div"; |
6427 | sdiv_optab->libcall_suffix = '3'; | |
68a556d6 | 6428 | sdiv_optab->libcall_gen = gen_int_fp_signed_fixed_libfunc; |
f36b9f69 | 6429 | sdivv_optab->libcall_basename = "divv"; |
6430 | sdivv_optab->libcall_suffix = '3'; | |
6431 | sdivv_optab->libcall_gen = gen_int_libfunc; | |
68a556d6 | 6432 | ssdiv_optab->libcall_basename = "ssdiv"; |
6433 | ssdiv_optab->libcall_suffix = '3'; | |
6434 | ssdiv_optab->libcall_gen = gen_signed_fixed_libfunc; | |
f36b9f69 | 6435 | udiv_optab->libcall_basename = "udiv"; |
6436 | udiv_optab->libcall_suffix = '3'; | |
68a556d6 | 6437 | udiv_optab->libcall_gen = gen_int_unsigned_fixed_libfunc; |
6438 | usdiv_optab->libcall_basename = "usdiv"; | |
6439 | usdiv_optab->libcall_suffix = '3'; | |
6440 | usdiv_optab->libcall_gen = gen_unsigned_fixed_libfunc; | |
f36b9f69 | 6441 | sdivmod_optab->libcall_basename = "divmod"; |
6442 | sdivmod_optab->libcall_suffix = '4'; | |
6443 | sdivmod_optab->libcall_gen = gen_int_libfunc; | |
6444 | udivmod_optab->libcall_basename = "udivmod"; | |
6445 | udivmod_optab->libcall_suffix = '4'; | |
6446 | udivmod_optab->libcall_gen = gen_int_libfunc; | |
6447 | smod_optab->libcall_basename = "mod"; | |
6448 | smod_optab->libcall_suffix = '3'; | |
6449 | smod_optab->libcall_gen = gen_int_libfunc; | |
6450 | umod_optab->libcall_basename = "umod"; | |
6451 | umod_optab->libcall_suffix = '3'; | |
6452 | umod_optab->libcall_gen = gen_int_libfunc; | |
6453 | ftrunc_optab->libcall_basename = "ftrunc"; | |
6454 | ftrunc_optab->libcall_suffix = '2'; | |
6455 | ftrunc_optab->libcall_gen = gen_fp_libfunc; | |
6456 | and_optab->libcall_basename = "and"; | |
6457 | and_optab->libcall_suffix = '3'; | |
6458 | and_optab->libcall_gen = gen_int_libfunc; | |
6459 | ior_optab->libcall_basename = "ior"; | |
6460 | ior_optab->libcall_suffix = '3'; | |
6461 | ior_optab->libcall_gen = gen_int_libfunc; | |
6462 | xor_optab->libcall_basename = "xor"; | |
6463 | xor_optab->libcall_suffix = '3'; | |
6464 | xor_optab->libcall_gen = gen_int_libfunc; | |
6465 | ashl_optab->libcall_basename = "ashl"; | |
6466 | ashl_optab->libcall_suffix = '3'; | |
68a556d6 | 6467 | ashl_optab->libcall_gen = gen_int_fixed_libfunc; |
6468 | ssashl_optab->libcall_basename = "ssashl"; | |
6469 | ssashl_optab->libcall_suffix = '3'; | |
6470 | ssashl_optab->libcall_gen = gen_signed_fixed_libfunc; | |
6471 | usashl_optab->libcall_basename = "usashl"; | |
6472 | usashl_optab->libcall_suffix = '3'; | |
6473 | usashl_optab->libcall_gen = gen_unsigned_fixed_libfunc; | |
f36b9f69 | 6474 | ashr_optab->libcall_basename = "ashr"; |
6475 | ashr_optab->libcall_suffix = '3'; | |
68a556d6 | 6476 | ashr_optab->libcall_gen = gen_int_signed_fixed_libfunc; |
f36b9f69 | 6477 | lshr_optab->libcall_basename = "lshr"; |
6478 | lshr_optab->libcall_suffix = '3'; | |
68a556d6 | 6479 | lshr_optab->libcall_gen = gen_int_unsigned_fixed_libfunc; |
f36b9f69 | 6480 | smin_optab->libcall_basename = "min"; |
6481 | smin_optab->libcall_suffix = '3'; | |
6482 | smin_optab->libcall_gen = gen_int_fp_libfunc; | |
6483 | smax_optab->libcall_basename = "max"; | |
6484 | smax_optab->libcall_suffix = '3'; | |
6485 | smax_optab->libcall_gen = gen_int_fp_libfunc; | |
6486 | umin_optab->libcall_basename = "umin"; | |
6487 | umin_optab->libcall_suffix = '3'; | |
6488 | umin_optab->libcall_gen = gen_int_libfunc; | |
6489 | umax_optab->libcall_basename = "umax"; | |
6490 | umax_optab->libcall_suffix = '3'; | |
6491 | umax_optab->libcall_gen = gen_int_libfunc; | |
6492 | neg_optab->libcall_basename = "neg"; | |
6493 | neg_optab->libcall_suffix = '2'; | |
68a556d6 | 6494 | neg_optab->libcall_gen = gen_int_fp_fixed_libfunc; |
6495 | ssneg_optab->libcall_basename = "ssneg"; | |
6496 | ssneg_optab->libcall_suffix = '2'; | |
6497 | ssneg_optab->libcall_gen = gen_signed_fixed_libfunc; | |
6498 | usneg_optab->libcall_basename = "usneg"; | |
6499 | usneg_optab->libcall_suffix = '2'; | |
6500 | usneg_optab->libcall_gen = gen_unsigned_fixed_libfunc; | |
f36b9f69 | 6501 | negv_optab->libcall_basename = "neg"; |
6502 | negv_optab->libcall_suffix = '2'; | |
6503 | negv_optab->libcall_gen = gen_intv_fp_libfunc; | |
6504 | one_cmpl_optab->libcall_basename = "one_cmpl"; | |
6505 | one_cmpl_optab->libcall_suffix = '2'; | |
6506 | one_cmpl_optab->libcall_gen = gen_int_libfunc; | |
6507 | ffs_optab->libcall_basename = "ffs"; | |
6508 | ffs_optab->libcall_suffix = '2'; | |
6509 | ffs_optab->libcall_gen = gen_int_libfunc; | |
6510 | clz_optab->libcall_basename = "clz"; | |
6511 | clz_optab->libcall_suffix = '2'; | |
6512 | clz_optab->libcall_gen = gen_int_libfunc; | |
6513 | ctz_optab->libcall_basename = "ctz"; | |
6514 | ctz_optab->libcall_suffix = '2'; | |
6515 | ctz_optab->libcall_gen = gen_int_libfunc; | |
6516 | popcount_optab->libcall_basename = "popcount"; | |
6517 | popcount_optab->libcall_suffix = '2'; | |
6518 | popcount_optab->libcall_gen = gen_int_libfunc; | |
6519 | parity_optab->libcall_basename = "parity"; | |
6520 | parity_optab->libcall_suffix = '2'; | |
6521 | parity_optab->libcall_gen = gen_int_libfunc; | |
d6583d40 | 6522 | |
6523 | /* Comparison libcalls for integers MUST come in pairs, | |
6524 | signed/unsigned. */ | |
f36b9f69 | 6525 | cmp_optab->libcall_basename = "cmp"; |
6526 | cmp_optab->libcall_suffix = '2'; | |
68a556d6 | 6527 | cmp_optab->libcall_gen = gen_int_fp_fixed_libfunc; |
f36b9f69 | 6528 | ucmp_optab->libcall_basename = "ucmp"; |
6529 | ucmp_optab->libcall_suffix = '2'; | |
6530 | ucmp_optab->libcall_gen = gen_int_libfunc; | |
d6583d40 | 6531 | |
6532 | /* EQ etc are floating point only. */ | |
f36b9f69 | 6533 | eq_optab->libcall_basename = "eq"; |
6534 | eq_optab->libcall_suffix = '2'; | |
6535 | eq_optab->libcall_gen = gen_fp_libfunc; | |
6536 | ne_optab->libcall_basename = "ne"; | |
6537 | ne_optab->libcall_suffix = '2'; | |
6538 | ne_optab->libcall_gen = gen_fp_libfunc; | |
6539 | gt_optab->libcall_basename = "gt"; | |
6540 | gt_optab->libcall_suffix = '2'; | |
6541 | gt_optab->libcall_gen = gen_fp_libfunc; | |
6542 | ge_optab->libcall_basename = "ge"; | |
6543 | ge_optab->libcall_suffix = '2'; | |
6544 | ge_optab->libcall_gen = gen_fp_libfunc; | |
6545 | lt_optab->libcall_basename = "lt"; | |
6546 | lt_optab->libcall_suffix = '2'; | |
6547 | lt_optab->libcall_gen = gen_fp_libfunc; | |
6548 | le_optab->libcall_basename = "le"; | |
6549 | le_optab->libcall_suffix = '2'; | |
6550 | le_optab->libcall_gen = gen_fp_libfunc; | |
6551 | unord_optab->libcall_basename = "unord"; | |
6552 | unord_optab->libcall_suffix = '2'; | |
6553 | unord_optab->libcall_gen = gen_fp_libfunc; | |
6554 | ||
6555 | powi_optab->libcall_basename = "powi"; | |
6556 | powi_optab->libcall_suffix = '2'; | |
6557 | powi_optab->libcall_gen = gen_fp_libfunc; | |
757c219d | 6558 | |
d6583d40 | 6559 | /* Conversions. */ |
f36b9f69 | 6560 | sfloat_optab->libcall_basename = "float"; |
6561 | sfloat_optab->libcall_gen = gen_int_to_fp_conv_libfunc; | |
6562 | ufloat_optab->libcall_gen = gen_ufloat_conv_libfunc; | |
6563 | sfix_optab->libcall_basename = "fix"; | |
6564 | sfix_optab->libcall_gen = gen_fp_to_int_conv_libfunc; | |
6565 | ufix_optab->libcall_basename = "fixuns"; | |
6566 | ufix_optab->libcall_gen = gen_fp_to_int_conv_libfunc; | |
6567 | lrint_optab->libcall_basename = "lrint"; | |
6568 | lrint_optab->libcall_gen = gen_int_to_fp_nondecimal_conv_libfunc; | |
6569 | lround_optab->libcall_basename = "lround"; | |
6570 | lround_optab->libcall_gen = gen_int_to_fp_nondecimal_conv_libfunc; | |
6571 | lfloor_optab->libcall_basename = "lfloor"; | |
6572 | lfloor_optab->libcall_gen = gen_int_to_fp_nondecimal_conv_libfunc; | |
6573 | lceil_optab->libcall_basename = "lceil"; | |
6574 | lceil_optab->libcall_gen = gen_int_to_fp_nondecimal_conv_libfunc; | |
6575 | ||
6576 | /* trunc_optab is also used for FLOAT_EXTEND. */ | |
6577 | sext_optab->libcall_basename = "extend"; | |
6578 | sext_optab->libcall_gen = gen_extend_conv_libfunc; | |
6579 | trunc_optab->libcall_basename = "trunc"; | |
6580 | trunc_optab->libcall_gen = gen_trunc_conv_libfunc; | |
6581 | ||
68a556d6 | 6582 | /* Conversions for fixed-point modes and other modes. */ |
6583 | fract_optab->libcall_basename = "fract"; | |
6584 | fract_optab->libcall_gen = gen_fract_conv_libfunc; | |
6585 | satfract_optab->libcall_basename = "satfract"; | |
6586 | satfract_optab->libcall_gen = gen_satfract_conv_libfunc; | |
6587 | fractuns_optab->libcall_basename = "fractuns"; | |
6588 | fractuns_optab->libcall_gen = gen_fractuns_conv_libfunc; | |
6589 | satfractuns_optab->libcall_basename = "satfractuns"; | |
6590 | satfractuns_optab->libcall_gen = gen_satfractuns_conv_libfunc; | |
6591 | ||
f36b9f69 | 6592 | /* The ffs function operates on `int'. Fall back on it if we do not |
6593 | have a libgcc2 function for that width. */ | |
6594 | if (INT_TYPE_SIZE < BITS_PER_WORD) | |
6595 | { | |
6596 | int_mode = mode_for_size (INT_TYPE_SIZE, MODE_INT, 0); | |
6597 | set_optab_libfunc (ffs_optab, mode_for_size (INT_TYPE_SIZE, MODE_INT, 0), | |
6598 | "ffs"); | |
6599 | } | |
2c8daaf1 | 6600 | |
42791117 | 6601 | /* Explicitly initialize the bswap libfuncs since we need them to be |
6602 | valid for things other than word_mode. */ | |
6603 | set_optab_libfunc (bswap_optab, SImode, "__bswapsi2"); | |
6604 | set_optab_libfunc (bswap_optab, DImode, "__bswapdi2"); | |
6605 | ||
a7cc195f | 6606 | /* Use cabs for double complex abs, since systems generally have cabs. |
6607 | Don't define any libcall for float complex, so that cabs will be used. */ | |
6608 | if (complex_double_type_node) | |
f36b9f69 | 6609 | set_optab_libfunc (abs_optab, TYPE_MODE (complex_double_type_node), "cabs"); |
2c8daaf1 | 6610 | |
a0ef1725 | 6611 | abort_libfunc = init_one_libfunc ("abort"); |
2c8daaf1 | 6612 | memcpy_libfunc = init_one_libfunc ("memcpy"); |
d5ff563e | 6613 | memmove_libfunc = init_one_libfunc ("memmove"); |
2c8daaf1 | 6614 | memcmp_libfunc = init_one_libfunc ("memcmp"); |
2c8daaf1 | 6615 | memset_libfunc = init_one_libfunc ("memset"); |
62f615b1 | 6616 | setbits_libfunc = init_one_libfunc ("__setbits"); |
2c8daaf1 | 6617 | |
17785858 | 6618 | #ifndef DONT_USE_BUILTIN_SETJMP |
2c8daaf1 | 6619 | setjmp_libfunc = init_one_libfunc ("__builtin_setjmp"); |
6620 | longjmp_libfunc = init_one_libfunc ("__builtin_longjmp"); | |
8591d03a | 6621 | #else |
2c8daaf1 | 6622 | setjmp_libfunc = init_one_libfunc ("setjmp"); |
6623 | longjmp_libfunc = init_one_libfunc ("longjmp"); | |
8591d03a | 6624 | #endif |
df4b504c | 6625 | unwind_sjlj_register_libfunc = init_one_libfunc ("_Unwind_SjLj_Register"); |
6626 | unwind_sjlj_unregister_libfunc | |
6627 | = init_one_libfunc ("_Unwind_SjLj_Unregister"); | |
485aaaaf | 6628 | |
abd28cef | 6629 | /* For function entry/exit instrumentation. */ |
6630 | profile_function_entry_libfunc | |
2c8daaf1 | 6631 | = init_one_libfunc ("__cyg_profile_func_enter"); |
abd28cef | 6632 | profile_function_exit_libfunc |
2c8daaf1 | 6633 | = init_one_libfunc ("__cyg_profile_func_exit"); |
abd28cef | 6634 | |
62f615b1 | 6635 | gcov_flush_libfunc = init_one_libfunc ("__gcov_flush"); |
62f615b1 | 6636 | |
76915553 | 6637 | /* Allow the target to add more libcalls or rename some, etc. */ |
f2f543a3 | 6638 | targetm.init_libfuncs (); |
53b14d73 | 6639 | |
6640 | reinit = true; | |
1f215c26 | 6641 | } |
30e9913f | 6642 | |
30e9913f | 6643 | /* Print information about the current contents of the optabs on |
6644 | STDERR. */ | |
6645 | ||
f36b9f69 | 6646 | void |
30e9913f | 6647 | debug_optab_libfuncs (void) |
6648 | { | |
6649 | int i; | |
6650 | int j; | |
6651 | int k; | |
6652 | ||
6653 | /* Dump the arithmetic optabs. */ | |
7d3f6cc7 | 6654 | for (i = 0; i != (int) OTI_MAX; i++) |
30e9913f | 6655 | for (j = 0; j < NUM_MACHINE_MODES; ++j) |
6656 | { | |
6657 | optab o; | |
f36b9f69 | 6658 | rtx l; |
30e9913f | 6659 | |
be5cecfd | 6660 | o = &optab_table[i]; |
b9c74b4d | 6661 | l = optab_libfunc (o, (enum machine_mode) j); |
f36b9f69 | 6662 | if (l) |
30e9913f | 6663 | { |
f36b9f69 | 6664 | gcc_assert (GET_CODE (l) == SYMBOL_REF); |
7d3f6cc7 | 6665 | fprintf (stderr, "%s\t%s:\t%s\n", |
30e9913f | 6666 | GET_RTX_NAME (o->code), |
6667 | GET_MODE_NAME (j), | |
f36b9f69 | 6668 | XSTR (l, 0)); |
30e9913f | 6669 | } |
6670 | } | |
6671 | ||
6672 | /* Dump the conversion optabs. */ | |
26364c07 | 6673 | for (i = 0; i < (int) COI_MAX; ++i) |
30e9913f | 6674 | for (j = 0; j < NUM_MACHINE_MODES; ++j) |
6675 | for (k = 0; k < NUM_MACHINE_MODES; ++k) | |
6676 | { | |
6677 | convert_optab o; | |
f36b9f69 | 6678 | rtx l; |
30e9913f | 6679 | |
be5cecfd | 6680 | o = &convert_optab_table[i]; |
b9c74b4d | 6681 | l = convert_optab_libfunc (o, (enum machine_mode) j, |
6682 | (enum machine_mode) k); | |
f36b9f69 | 6683 | if (l) |
30e9913f | 6684 | { |
f36b9f69 | 6685 | gcc_assert (GET_CODE (l) == SYMBOL_REF); |
7d3f6cc7 | 6686 | fprintf (stderr, "%s\t%s\t%s:\t%s\n", |
30e9913f | 6687 | GET_RTX_NAME (o->code), |
6688 | GET_MODE_NAME (j), | |
6689 | GET_MODE_NAME (k), | |
f36b9f69 | 6690 | XSTR (l, 0)); |
30e9913f | 6691 | } |
6692 | } | |
6693 | } | |
6694 | ||
ff5ef762 | 6695 | \f |
9e5192ed | 6696 | /* Generate insns to trap with code TCODE if OP1 and OP2 satisfy condition |
6697 | CODE. Return 0 on failure. */ | |
6698 | ||
6699 | rtx | |
74f4459c | 6700 | gen_cond_trap (enum rtx_code code, rtx op1, rtx op2, rtx tcode) |
9e5192ed | 6701 | { |
6702 | enum machine_mode mode = GET_MODE (op1); | |
b3a15ba6 | 6703 | enum insn_code icode; |
6704 | rtx insn; | |
74f4459c | 6705 | rtx trap_rtx; |
9e5192ed | 6706 | |
6707 | if (mode == VOIDmode) | |
6708 | return 0; | |
6709 | ||
74f4459c | 6710 | icode = optab_handler (ctrap_optab, mode)->insn_code; |
b3a15ba6 | 6711 | if (icode == CODE_FOR_nothing) |
6712 | return 0; | |
6713 | ||
74f4459c | 6714 | /* Some targets only accept a zero trap code. */ |
6715 | if (insn_data[icode].operand[3].predicate | |
6716 | && !insn_data[icode].operand[3].predicate (tcode, VOIDmode)) | |
6717 | return 0; | |
6718 | ||
6719 | do_pending_stack_adjust (); | |
b3a15ba6 | 6720 | start_sequence (); |
74f4459c | 6721 | prepare_cmp_insn (op1, op2, code, NULL_RTX, false, OPTAB_DIRECT, |
6722 | &trap_rtx, &mode); | |
6723 | if (!trap_rtx) | |
6724 | insn = NULL_RTX; | |
6725 | else | |
6726 | insn = GEN_FCN (icode) (trap_rtx, XEXP (trap_rtx, 0), XEXP (trap_rtx, 1), | |
6727 | tcode); | |
6728 | ||
6729 | /* If that failed, then give up. */ | |
6730 | if (insn == 0) | |
e79a81b2 | 6731 | { |
6732 | end_sequence (); | |
6733 | return 0; | |
6734 | } | |
b3a15ba6 | 6735 | |
74f4459c | 6736 | emit_insn (insn); |
6737 | insn = get_insns (); | |
b3a15ba6 | 6738 | end_sequence (); |
b3a15ba6 | 6739 | return insn; |
9e5192ed | 6740 | } |
1f3233d1 | 6741 | |
6b7acc28 | 6742 | /* Return rtx code for TCODE. Use UNSIGNEDP to select signed |
6743 | or unsigned operation code. */ | |
6744 | ||
6745 | static enum rtx_code | |
6746 | get_rtx_code (enum tree_code tcode, bool unsignedp) | |
6747 | { | |
6748 | enum rtx_code code; | |
6749 | switch (tcode) | |
6750 | { | |
6751 | case EQ_EXPR: | |
6752 | code = EQ; | |
6753 | break; | |
6754 | case NE_EXPR: | |
6755 | code = NE; | |
6756 | break; | |
6757 | case LT_EXPR: | |
6758 | code = unsignedp ? LTU : LT; | |
6759 | break; | |
6760 | case LE_EXPR: | |
6761 | code = unsignedp ? LEU : LE; | |
6762 | break; | |
6763 | case GT_EXPR: | |
6764 | code = unsignedp ? GTU : GT; | |
6765 | break; | |
6766 | case GE_EXPR: | |
6767 | code = unsignedp ? GEU : GE; | |
6768 | break; | |
26364c07 | 6769 | |
6b7acc28 | 6770 | case UNORDERED_EXPR: |
6771 | code = UNORDERED; | |
6772 | break; | |
6773 | case ORDERED_EXPR: | |
6774 | code = ORDERED; | |
6775 | break; | |
6776 | case UNLT_EXPR: | |
6777 | code = UNLT; | |
6778 | break; | |
6779 | case UNLE_EXPR: | |
6780 | code = UNLE; | |
6781 | break; | |
6782 | case UNGT_EXPR: | |
6783 | code = UNGT; | |
6784 | break; | |
6785 | case UNGE_EXPR: | |
6786 | code = UNGE; | |
6787 | break; | |
6788 | case UNEQ_EXPR: | |
6789 | code = UNEQ; | |
6790 | break; | |
6791 | case LTGT_EXPR: | |
6792 | code = LTGT; | |
6793 | break; | |
6794 | ||
6795 | default: | |
ce572eff | 6796 | gcc_unreachable (); |
6b7acc28 | 6797 | } |
6798 | return code; | |
6799 | } | |
6800 | ||
6801 | /* Return comparison rtx for COND. Use UNSIGNEDP to select signed or | |
6802 | unsigned operators. Do not generate compare instruction. */ | |
6803 | ||
6804 | static rtx | |
6805 | vector_compare_rtx (tree cond, bool unsignedp, enum insn_code icode) | |
6806 | { | |
6807 | enum rtx_code rcode; | |
6808 | tree t_op0, t_op1; | |
6809 | rtx rtx_op0, rtx_op1; | |
6810 | ||
ce572eff | 6811 | /* This is unlikely. While generating VEC_COND_EXPR, auto vectorizer |
6812 | ensures that condition is a relational operation. */ | |
6813 | gcc_assert (COMPARISON_CLASS_P (cond)); | |
6b7acc28 | 6814 | |
26364c07 | 6815 | rcode = get_rtx_code (TREE_CODE (cond), unsignedp); |
ce572eff | 6816 | t_op0 = TREE_OPERAND (cond, 0); |
6817 | t_op1 = TREE_OPERAND (cond, 1); | |
26364c07 | 6818 | |
6b7acc28 | 6819 | /* Expand operands. */ |
1db6d067 | 6820 | rtx_op0 = expand_expr (t_op0, NULL_RTX, TYPE_MODE (TREE_TYPE (t_op0)), |
6821 | EXPAND_STACK_PARM); | |
6822 | rtx_op1 = expand_expr (t_op1, NULL_RTX, TYPE_MODE (TREE_TYPE (t_op1)), | |
6823 | EXPAND_STACK_PARM); | |
6b7acc28 | 6824 | |
ce572eff | 6825 | if (!insn_data[icode].operand[4].predicate (rtx_op0, GET_MODE (rtx_op0)) |
6b7acc28 | 6826 | && GET_MODE (rtx_op0) != VOIDmode) |
6827 | rtx_op0 = force_reg (GET_MODE (rtx_op0), rtx_op0); | |
26364c07 | 6828 | |
ce572eff | 6829 | if (!insn_data[icode].operand[5].predicate (rtx_op1, GET_MODE (rtx_op1)) |
6b7acc28 | 6830 | && GET_MODE (rtx_op1) != VOIDmode) |
6831 | rtx_op1 = force_reg (GET_MODE (rtx_op1), rtx_op1); | |
6832 | ||
6833 | return gen_rtx_fmt_ee (rcode, VOIDmode, rtx_op0, rtx_op1); | |
6834 | } | |
6835 | ||
6836 | /* Return insn code for VEC_COND_EXPR EXPR. */ | |
26364c07 | 6837 | |
6838 | static inline enum insn_code | |
6b7acc28 | 6839 | get_vcond_icode (tree expr, enum machine_mode mode) |
6840 | { | |
6841 | enum insn_code icode = CODE_FOR_nothing; | |
6842 | ||
6843 | if (TYPE_UNSIGNED (TREE_TYPE (expr))) | |
6844 | icode = vcondu_gen_code[mode]; | |
6845 | else | |
6846 | icode = vcond_gen_code[mode]; | |
6847 | return icode; | |
6848 | } | |
6849 | ||
6850 | /* Return TRUE iff, appropriate vector insns are available | |
6851 | for vector cond expr expr in VMODE mode. */ | |
6852 | ||
6853 | bool | |
6854 | expand_vec_cond_expr_p (tree expr, enum machine_mode vmode) | |
6855 | { | |
6856 | if (get_vcond_icode (expr, vmode) == CODE_FOR_nothing) | |
6857 | return false; | |
6858 | return true; | |
6859 | } | |
6860 | ||
6861 | /* Generate insns for VEC_COND_EXPR. */ | |
6862 | ||
6863 | rtx | |
6864 | expand_vec_cond_expr (tree vec_cond_expr, rtx target) | |
6865 | { | |
6866 | enum insn_code icode; | |
6867 | rtx comparison, rtx_op1, rtx_op2, cc_op0, cc_op1; | |
6868 | enum machine_mode mode = TYPE_MODE (TREE_TYPE (vec_cond_expr)); | |
6869 | bool unsignedp = TYPE_UNSIGNED (TREE_TYPE (vec_cond_expr)); | |
6870 | ||
6871 | icode = get_vcond_icode (vec_cond_expr, mode); | |
6872 | if (icode == CODE_FOR_nothing) | |
6873 | return 0; | |
6874 | ||
c9f7685f | 6875 | if (!target || !insn_data[icode].operand[0].predicate (target, mode)) |
6b7acc28 | 6876 | target = gen_reg_rtx (mode); |
6877 | ||
c1e065f3 | 6878 | /* Get comparison rtx. First expand both cond expr operands. */ |
26364c07 | 6879 | comparison = vector_compare_rtx (TREE_OPERAND (vec_cond_expr, 0), |
6b7acc28 | 6880 | unsignedp, icode); |
6881 | cc_op0 = XEXP (comparison, 0); | |
6882 | cc_op1 = XEXP (comparison, 1); | |
6883 | /* Expand both operands and force them in reg, if required. */ | |
1db6d067 | 6884 | rtx_op1 = expand_normal (TREE_OPERAND (vec_cond_expr, 1)); |
ce572eff | 6885 | if (!insn_data[icode].operand[1].predicate (rtx_op1, mode) |
6b7acc28 | 6886 | && mode != VOIDmode) |
6887 | rtx_op1 = force_reg (mode, rtx_op1); | |
6888 | ||
1db6d067 | 6889 | rtx_op2 = expand_normal (TREE_OPERAND (vec_cond_expr, 2)); |
ce572eff | 6890 | if (!insn_data[icode].operand[2].predicate (rtx_op2, mode) |
6b7acc28 | 6891 | && mode != VOIDmode) |
6892 | rtx_op2 = force_reg (mode, rtx_op2); | |
6893 | ||
6894 | /* Emit instruction! */ | |
26364c07 | 6895 | emit_insn (GEN_FCN (icode) (target, rtx_op1, rtx_op2, |
6b7acc28 | 6896 | comparison, cc_op0, cc_op1)); |
6897 | ||
6898 | return target; | |
6899 | } | |
b6a5fc45 | 6900 | |
6901 | \f | |
6902 | /* This is an internal subroutine of the other compare_and_swap expanders. | |
6903 | MEM, OLD_VAL and NEW_VAL are as you'd expect for a compare-and-swap | |
6904 | operation. TARGET is an optional place to store the value result of | |
6905 | the operation. ICODE is the particular instruction to expand. Return | |
6906 | the result of the operation. */ | |
6907 | ||
6908 | static rtx | |
6909 | expand_val_compare_and_swap_1 (rtx mem, rtx old_val, rtx new_val, | |
6910 | rtx target, enum insn_code icode) | |
6911 | { | |
6912 | enum machine_mode mode = GET_MODE (mem); | |
6913 | rtx insn; | |
6914 | ||
6915 | if (!target || !insn_data[icode].operand[0].predicate (target, mode)) | |
6916 | target = gen_reg_rtx (mode); | |
6917 | ||
6918 | if (GET_MODE (old_val) != VOIDmode && GET_MODE (old_val) != mode) | |
6919 | old_val = convert_modes (mode, GET_MODE (old_val), old_val, 1); | |
6920 | if (!insn_data[icode].operand[2].predicate (old_val, mode)) | |
6921 | old_val = force_reg (mode, old_val); | |
6922 | ||
6923 | if (GET_MODE (new_val) != VOIDmode && GET_MODE (new_val) != mode) | |
6924 | new_val = convert_modes (mode, GET_MODE (new_val), new_val, 1); | |
6925 | if (!insn_data[icode].operand[3].predicate (new_val, mode)) | |
6926 | new_val = force_reg (mode, new_val); | |
6927 | ||
6928 | insn = GEN_FCN (icode) (target, mem, old_val, new_val); | |
6929 | if (insn == NULL_RTX) | |
6930 | return NULL_RTX; | |
6931 | emit_insn (insn); | |
6932 | ||
6933 | return target; | |
6934 | } | |
6935 | ||
6936 | /* Expand a compare-and-swap operation and return its value. */ | |
6937 | ||
6938 | rtx | |
6939 | expand_val_compare_and_swap (rtx mem, rtx old_val, rtx new_val, rtx target) | |
6940 | { | |
6941 | enum machine_mode mode = GET_MODE (mem); | |
6942 | enum insn_code icode = sync_compare_and_swap[mode]; | |
6943 | ||
6944 | if (icode == CODE_FOR_nothing) | |
6945 | return NULL_RTX; | |
6946 | ||
6947 | return expand_val_compare_and_swap_1 (mem, old_val, new_val, target, icode); | |
6948 | } | |
6949 | ||
8e58aded | 6950 | /* Helper function to find the MODE_CC set in a sync_compare_and_swap |
6951 | pattern. */ | |
6952 | ||
6953 | static void | |
6954 | find_cc_set (rtx x, const_rtx pat, void *data) | |
6955 | { | |
6956 | if (REG_P (x) && GET_MODE_CLASS (GET_MODE (x)) == MODE_CC | |
6957 | && GET_CODE (pat) == SET) | |
6958 | { | |
6959 | rtx *p_cc_reg = (rtx *) data; | |
6960 | gcc_assert (!*p_cc_reg); | |
6961 | *p_cc_reg = x; | |
6962 | } | |
6963 | } | |
6964 | ||
b6a5fc45 | 6965 | /* Expand a compare-and-swap operation and store true into the result if |
6966 | the operation was successful and false otherwise. Return the result. | |
6967 | Unlike other routines, TARGET is not optional. */ | |
6968 | ||
6969 | rtx | |
6970 | expand_bool_compare_and_swap (rtx mem, rtx old_val, rtx new_val, rtx target) | |
6971 | { | |
6972 | enum machine_mode mode = GET_MODE (mem); | |
6973 | enum insn_code icode; | |
8e58aded | 6974 | rtx subtarget, seq, cc_reg; |
b6a5fc45 | 6975 | |
6976 | /* If the target supports a compare-and-swap pattern that simultaneously | |
6977 | sets some flag for success, then use it. Otherwise use the regular | |
6978 | compare-and-swap and follow that immediately with a compare insn. */ | |
8e58aded | 6979 | icode = sync_compare_and_swap[mode]; |
6980 | if (icode == CODE_FOR_nothing) | |
6981 | return NULL_RTX; | |
87121034 | 6982 | |
8e58aded | 6983 | do |
6984 | { | |
6985 | start_sequence (); | |
b6a5fc45 | 6986 | subtarget = expand_val_compare_and_swap_1 (mem, old_val, new_val, |
8e58aded | 6987 | NULL_RTX, icode); |
6988 | cc_reg = NULL_RTX; | |
b6a5fc45 | 6989 | if (subtarget == NULL_RTX) |
b6a5fc45 | 6990 | { |
8e58aded | 6991 | end_sequence (); |
6992 | return NULL_RTX; | |
b6a5fc45 | 6993 | } |
b6a5fc45 | 6994 | |
8e58aded | 6995 | if (have_insn_for (COMPARE, CCmode)) |
6996 | note_stores (PATTERN (get_last_insn ()), find_cc_set, &cc_reg); | |
6997 | seq = get_insns (); | |
6998 | end_sequence (); | |
b6a5fc45 | 6999 | |
8e58aded | 7000 | /* We might be comparing against an old value. Try again. :-( */ |
7001 | if (!cc_reg && MEM_P (old_val)) | |
7002 | { | |
7003 | seq = NULL_RTX; | |
7004 | old_val = force_reg (mode, old_val); | |
7005 | } | |
7006 | } | |
7007 | while (!seq); | |
b6a5fc45 | 7008 | |
8e58aded | 7009 | emit_insn (seq); |
7010 | if (cc_reg) | |
74f4459c | 7011 | return emit_store_flag_force (target, EQ, cc_reg, const0_rtx, VOIDmode, 0, 1); |
8e58aded | 7012 | else |
74f4459c | 7013 | return emit_store_flag_force (target, EQ, subtarget, old_val, VOIDmode, 1, 1); |
b6a5fc45 | 7014 | } |
7015 | ||
7016 | /* This is a helper function for the other atomic operations. This function | |
7017 | emits a loop that contains SEQ that iterates until a compare-and-swap | |
7018 | operation at the end succeeds. MEM is the memory to be modified. SEQ is | |
7019 | a set of instructions that takes a value from OLD_REG as an input and | |
7020 | produces a value in NEW_REG as an output. Before SEQ, OLD_REG will be | |
7021 | set to the current contents of MEM. After SEQ, a compare-and-swap will | |
7022 | attempt to update MEM with NEW_REG. The function returns true when the | |
7023 | loop was generated successfully. */ | |
7024 | ||
7025 | static bool | |
7026 | expand_compare_and_swap_loop (rtx mem, rtx old_reg, rtx new_reg, rtx seq) | |
7027 | { | |
7028 | enum machine_mode mode = GET_MODE (mem); | |
7029 | enum insn_code icode; | |
8e58aded | 7030 | rtx label, cmp_reg, subtarget, cc_reg; |
b6a5fc45 | 7031 | |
7032 | /* The loop we want to generate looks like | |
7033 | ||
c0a0647e | 7034 | cmp_reg = mem; |
b6a5fc45 | 7035 | label: |
c0a0647e | 7036 | old_reg = cmp_reg; |
b6a5fc45 | 7037 | seq; |
c0a0647e | 7038 | cmp_reg = compare-and-swap(mem, old_reg, new_reg) |
7039 | if (cmp_reg != old_reg) | |
b6a5fc45 | 7040 | goto label; |
7041 | ||
7042 | Note that we only do the plain load from memory once. Subsequent | |
7043 | iterations use the value loaded by the compare-and-swap pattern. */ | |
7044 | ||
7045 | label = gen_label_rtx (); | |
c0a0647e | 7046 | cmp_reg = gen_reg_rtx (mode); |
b6a5fc45 | 7047 | |
c0a0647e | 7048 | emit_move_insn (cmp_reg, mem); |
b6a5fc45 | 7049 | emit_label (label); |
c0a0647e | 7050 | emit_move_insn (old_reg, cmp_reg); |
b6a5fc45 | 7051 | if (seq) |
7052 | emit_insn (seq); | |
7053 | ||
7054 | /* If the target supports a compare-and-swap pattern that simultaneously | |
7055 | sets some flag for success, then use it. Otherwise use the regular | |
7056 | compare-and-swap and follow that immediately with a compare insn. */ | |
8e58aded | 7057 | icode = sync_compare_and_swap[mode]; |
7058 | if (icode == CODE_FOR_nothing) | |
7059 | return false; | |
b6a5fc45 | 7060 | |
8e58aded | 7061 | subtarget = expand_val_compare_and_swap_1 (mem, old_reg, new_reg, |
7062 | cmp_reg, icode); | |
7063 | if (subtarget == NULL_RTX) | |
7064 | return false; | |
b6a5fc45 | 7065 | |
8e58aded | 7066 | cc_reg = NULL_RTX; |
7067 | if (have_insn_for (COMPARE, CCmode)) | |
7068 | note_stores (PATTERN (get_last_insn ()), find_cc_set, &cc_reg); | |
7069 | if (cc_reg) | |
7070 | { | |
7071 | cmp_reg = cc_reg; | |
7072 | old_reg = const0_rtx; | |
7073 | } | |
7074 | else | |
7075 | { | |
c0a0647e | 7076 | if (subtarget != cmp_reg) |
7077 | emit_move_insn (cmp_reg, subtarget); | |
b6a5fc45 | 7078 | } |
7079 | ||
7080 | /* ??? Mark this jump predicted not taken? */ | |
8e58aded | 7081 | emit_cmp_and_jump_insns (cmp_reg, old_reg, NE, const0_rtx, GET_MODE (cmp_reg), 1, |
7082 | label); | |
b6a5fc45 | 7083 | return true; |
7084 | } | |
7085 | ||
7086 | /* This function generates the atomic operation MEM CODE= VAL. In this | |
26364c07 | 7087 | case, we do not care about any resulting value. Returns NULL if we |
b6a5fc45 | 7088 | cannot generate the operation. */ |
7089 | ||
7090 | rtx | |
7091 | expand_sync_operation (rtx mem, rtx val, enum rtx_code code) | |
7092 | { | |
7093 | enum machine_mode mode = GET_MODE (mem); | |
7094 | enum insn_code icode; | |
7095 | rtx insn; | |
7096 | ||
7097 | /* Look to see if the target supports the operation directly. */ | |
7098 | switch (code) | |
7099 | { | |
7100 | case PLUS: | |
7101 | icode = sync_add_optab[mode]; | |
7102 | break; | |
7103 | case IOR: | |
7104 | icode = sync_ior_optab[mode]; | |
7105 | break; | |
7106 | case XOR: | |
7107 | icode = sync_xor_optab[mode]; | |
7108 | break; | |
7109 | case AND: | |
7110 | icode = sync_and_optab[mode]; | |
7111 | break; | |
87121034 | 7112 | case NOT: |
7113 | icode = sync_nand_optab[mode]; | |
7114 | break; | |
b6a5fc45 | 7115 | |
7116 | case MINUS: | |
7117 | icode = sync_sub_optab[mode]; | |
0310b094 | 7118 | if (icode == CODE_FOR_nothing || CONST_INT_P (val)) |
b6a5fc45 | 7119 | { |
7120 | icode = sync_add_optab[mode]; | |
7121 | if (icode != CODE_FOR_nothing) | |
7122 | { | |
7123 | val = expand_simple_unop (mode, NEG, val, NULL_RTX, 1); | |
7124 | code = PLUS; | |
7125 | } | |
7126 | } | |
7127 | break; | |
7128 | ||
b6a5fc45 | 7129 | default: |
7130 | gcc_unreachable (); | |
7131 | } | |
7132 | ||
7133 | /* Generate the direct operation, if present. */ | |
7134 | if (icode != CODE_FOR_nothing) | |
7135 | { | |
7136 | if (GET_MODE (val) != VOIDmode && GET_MODE (val) != mode) | |
7137 | val = convert_modes (mode, GET_MODE (val), val, 1); | |
7138 | if (!insn_data[icode].operand[1].predicate (val, mode)) | |
7139 | val = force_reg (mode, val); | |
26364c07 | 7140 | |
b6a5fc45 | 7141 | insn = GEN_FCN (icode) (mem, val); |
7142 | if (insn) | |
7143 | { | |
7144 | emit_insn (insn); | |
7145 | return const0_rtx; | |
7146 | } | |
7147 | } | |
7148 | ||
7149 | /* Failing that, generate a compare-and-swap loop in which we perform the | |
7150 | operation with normal arithmetic instructions. */ | |
7151 | if (sync_compare_and_swap[mode] != CODE_FOR_nothing) | |
7152 | { | |
7153 | rtx t0 = gen_reg_rtx (mode), t1; | |
7154 | ||
7155 | start_sequence (); | |
7156 | ||
87121034 | 7157 | t1 = t0; |
b6a5fc45 | 7158 | if (code == NOT) |
7159 | { | |
cf73e559 | 7160 | t1 = expand_simple_binop (mode, AND, t1, val, NULL_RTX, |
7161 | true, OPTAB_LIB_WIDEN); | |
7162 | t1 = expand_simple_unop (mode, code, t1, NULL_RTX, true); | |
b6a5fc45 | 7163 | } |
cf73e559 | 7164 | else |
7165 | t1 = expand_simple_binop (mode, code, t1, val, NULL_RTX, | |
7166 | true, OPTAB_LIB_WIDEN); | |
b6a5fc45 | 7167 | insn = get_insns (); |
7168 | end_sequence (); | |
7169 | ||
7170 | if (t1 != NULL && expand_compare_and_swap_loop (mem, t0, t1, insn)) | |
7171 | return const0_rtx; | |
7172 | } | |
7173 | ||
7174 | return NULL_RTX; | |
7175 | } | |
7176 | ||
7177 | /* This function generates the atomic operation MEM CODE= VAL. In this | |
7178 | case, we do care about the resulting value: if AFTER is true then | |
26364c07 | 7179 | return the value MEM holds after the operation, if AFTER is false |
b6a5fc45 | 7180 | then return the value MEM holds before the operation. TARGET is an |
7181 | optional place for the result value to be stored. */ | |
7182 | ||
7183 | rtx | |
7184 | expand_sync_fetch_operation (rtx mem, rtx val, enum rtx_code code, | |
7185 | bool after, rtx target) | |
7186 | { | |
7187 | enum machine_mode mode = GET_MODE (mem); | |
7188 | enum insn_code old_code, new_code, icode; | |
7189 | bool compensate; | |
7190 | rtx insn; | |
7191 | ||
7192 | /* Look to see if the target supports the operation directly. */ | |
7193 | switch (code) | |
7194 | { | |
7195 | case PLUS: | |
7196 | old_code = sync_old_add_optab[mode]; | |
7197 | new_code = sync_new_add_optab[mode]; | |
7198 | break; | |
7199 | case IOR: | |
7200 | old_code = sync_old_ior_optab[mode]; | |
7201 | new_code = sync_new_ior_optab[mode]; | |
7202 | break; | |
7203 | case XOR: | |
7204 | old_code = sync_old_xor_optab[mode]; | |
7205 | new_code = sync_new_xor_optab[mode]; | |
7206 | break; | |
7207 | case AND: | |
7208 | old_code = sync_old_and_optab[mode]; | |
7209 | new_code = sync_new_and_optab[mode]; | |
7210 | break; | |
87121034 | 7211 | case NOT: |
7212 | old_code = sync_old_nand_optab[mode]; | |
7213 | new_code = sync_new_nand_optab[mode]; | |
7214 | break; | |
b6a5fc45 | 7215 | |
7216 | case MINUS: | |
7217 | old_code = sync_old_sub_optab[mode]; | |
7218 | new_code = sync_new_sub_optab[mode]; | |
0310b094 | 7219 | if ((old_code == CODE_FOR_nothing && new_code == CODE_FOR_nothing) |
7220 | || CONST_INT_P (val)) | |
b6a5fc45 | 7221 | { |
7222 | old_code = sync_old_add_optab[mode]; | |
7223 | new_code = sync_new_add_optab[mode]; | |
7224 | if (old_code != CODE_FOR_nothing || new_code != CODE_FOR_nothing) | |
7225 | { | |
7226 | val = expand_simple_unop (mode, NEG, val, NULL_RTX, 1); | |
7227 | code = PLUS; | |
7228 | } | |
7229 | } | |
7230 | break; | |
7231 | ||
b6a5fc45 | 7232 | default: |
7233 | gcc_unreachable (); | |
7234 | } | |
7235 | ||
7236 | /* If the target does supports the proper new/old operation, great. But | |
7237 | if we only support the opposite old/new operation, check to see if we | |
7238 | can compensate. In the case in which the old value is supported, then | |
7239 | we can always perform the operation again with normal arithmetic. In | |
7240 | the case in which the new value is supported, then we can only handle | |
7241 | this in the case the operation is reversible. */ | |
7242 | compensate = false; | |
7243 | if (after) | |
7244 | { | |
7245 | icode = new_code; | |
7246 | if (icode == CODE_FOR_nothing) | |
7247 | { | |
7248 | icode = old_code; | |
7249 | if (icode != CODE_FOR_nothing) | |
7250 | compensate = true; | |
7251 | } | |
7252 | } | |
7253 | else | |
7254 | { | |
7255 | icode = old_code; | |
7256 | if (icode == CODE_FOR_nothing | |
7257 | && (code == PLUS || code == MINUS || code == XOR)) | |
7258 | { | |
7259 | icode = new_code; | |
7260 | if (icode != CODE_FOR_nothing) | |
7261 | compensate = true; | |
7262 | } | |
7263 | } | |
7264 | ||
7265 | /* If we found something supported, great. */ | |
7266 | if (icode != CODE_FOR_nothing) | |
7267 | { | |
7268 | if (!target || !insn_data[icode].operand[0].predicate (target, mode)) | |
7269 | target = gen_reg_rtx (mode); | |
7270 | ||
7271 | if (GET_MODE (val) != VOIDmode && GET_MODE (val) != mode) | |
7272 | val = convert_modes (mode, GET_MODE (val), val, 1); | |
7273 | if (!insn_data[icode].operand[2].predicate (val, mode)) | |
7274 | val = force_reg (mode, val); | |
26364c07 | 7275 | |
b6a5fc45 | 7276 | insn = GEN_FCN (icode) (target, mem, val); |
7277 | if (insn) | |
7278 | { | |
7279 | emit_insn (insn); | |
7280 | ||
7281 | /* If we need to compensate for using an operation with the | |
7282 | wrong return value, do so now. */ | |
7283 | if (compensate) | |
7284 | { | |
7285 | if (!after) | |
7286 | { | |
7287 | if (code == PLUS) | |
7288 | code = MINUS; | |
7289 | else if (code == MINUS) | |
7290 | code = PLUS; | |
7291 | } | |
87121034 | 7292 | |
7293 | if (code == NOT) | |
cf73e559 | 7294 | { |
7295 | target = expand_simple_binop (mode, AND, target, val, | |
7296 | NULL_RTX, true, | |
7297 | OPTAB_LIB_WIDEN); | |
7298 | target = expand_simple_unop (mode, code, target, | |
7299 | NULL_RTX, true); | |
7300 | } | |
7301 | else | |
7302 | target = expand_simple_binop (mode, code, target, val, | |
7303 | NULL_RTX, true, | |
7304 | OPTAB_LIB_WIDEN); | |
b6a5fc45 | 7305 | } |
7306 | ||
7307 | return target; | |
7308 | } | |
7309 | } | |
7310 | ||
7311 | /* Failing that, generate a compare-and-swap loop in which we perform the | |
7312 | operation with normal arithmetic instructions. */ | |
7313 | if (sync_compare_and_swap[mode] != CODE_FOR_nothing) | |
7314 | { | |
7315 | rtx t0 = gen_reg_rtx (mode), t1; | |
7316 | ||
7317 | if (!target || !register_operand (target, mode)) | |
7318 | target = gen_reg_rtx (mode); | |
7319 | ||
7320 | start_sequence (); | |
7321 | ||
87121034 | 7322 | if (!after) |
7323 | emit_move_insn (target, t0); | |
7324 | t1 = t0; | |
b6a5fc45 | 7325 | if (code == NOT) |
7326 | { | |
cf73e559 | 7327 | t1 = expand_simple_binop (mode, AND, t1, val, NULL_RTX, |
7328 | true, OPTAB_LIB_WIDEN); | |
7329 | t1 = expand_simple_unop (mode, code, t1, NULL_RTX, true); | |
b6a5fc45 | 7330 | } |
cf73e559 | 7331 | else |
7332 | t1 = expand_simple_binop (mode, code, t1, val, NULL_RTX, | |
7333 | true, OPTAB_LIB_WIDEN); | |
b6a5fc45 | 7334 | if (after) |
7335 | emit_move_insn (target, t1); | |
7336 | ||
7337 | insn = get_insns (); | |
7338 | end_sequence (); | |
7339 | ||
7340 | if (t1 != NULL && expand_compare_and_swap_loop (mem, t0, t1, insn)) | |
7341 | return target; | |
7342 | } | |
7343 | ||
7344 | return NULL_RTX; | |
7345 | } | |
7346 | ||
7347 | /* This function expands a test-and-set operation. Ideally we atomically | |
7348 | store VAL in MEM and return the previous value in MEM. Some targets | |
7349 | may not support this operation and only support VAL with the constant 1; | |
26364c07 | 7350 | in this case while the return value will be 0/1, but the exact value |
b6a5fc45 | 7351 | stored in MEM is target defined. TARGET is an option place to stick |
7352 | the return value. */ | |
7353 | ||
7354 | rtx | |
7355 | expand_sync_lock_test_and_set (rtx mem, rtx val, rtx target) | |
7356 | { | |
7357 | enum machine_mode mode = GET_MODE (mem); | |
7358 | enum insn_code icode; | |
7359 | rtx insn; | |
7360 | ||
7361 | /* If the target supports the test-and-set directly, great. */ | |
7362 | icode = sync_lock_test_and_set[mode]; | |
7363 | if (icode != CODE_FOR_nothing) | |
7364 | { | |
7365 | if (!target || !insn_data[icode].operand[0].predicate (target, mode)) | |
7366 | target = gen_reg_rtx (mode); | |
7367 | ||
7368 | if (GET_MODE (val) != VOIDmode && GET_MODE (val) != mode) | |
7369 | val = convert_modes (mode, GET_MODE (val), val, 1); | |
7370 | if (!insn_data[icode].operand[2].predicate (val, mode)) | |
7371 | val = force_reg (mode, val); | |
7372 | ||
7373 | insn = GEN_FCN (icode) (target, mem, val); | |
7374 | if (insn) | |
7375 | { | |
7376 | emit_insn (insn); | |
7377 | return target; | |
7378 | } | |
7379 | } | |
7380 | ||
7381 | /* Otherwise, use a compare-and-swap loop for the exchange. */ | |
7382 | if (sync_compare_and_swap[mode] != CODE_FOR_nothing) | |
7383 | { | |
7384 | if (!target || !register_operand (target, mode)) | |
7385 | target = gen_reg_rtx (mode); | |
7386 | if (GET_MODE (val) != VOIDmode && GET_MODE (val) != mode) | |
7387 | val = convert_modes (mode, GET_MODE (val), val, 1); | |
7388 | if (expand_compare_and_swap_loop (mem, target, val, NULL_RTX)) | |
7389 | return target; | |
7390 | } | |
7391 | ||
7392 | return NULL_RTX; | |
7393 | } | |
7394 | ||
1f3233d1 | 7395 | #include "gt-optabs.h" |