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15e35479 | 1 | /* Perform simple optimizations to clean up the result of reload. |
8d9254fc | 2 | Copyright (C) 1987-2020 Free Software Foundation, Inc. |
15e35479 KH |
3 | |
4 | This file is part of GCC. | |
5 | ||
6 | GCC is free software; you can redistribute it and/or modify it under | |
7 | the terms of the GNU General Public License as published by the Free | |
9dcd6f09 | 8 | Software Foundation; either version 3, or (at your option) any later |
15e35479 KH |
9 | version. |
10 | ||
11 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
12 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
14 | for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
9dcd6f09 NC |
17 | along with GCC; see the file COPYING3. If not see |
18 | <http://www.gnu.org/licenses/>. */ | |
15e35479 KH |
19 | |
20 | #include "config.h" | |
21 | #include "system.h" | |
22 | #include "coretypes.h" | |
c7131fb2 | 23 | #include "backend.h" |
957060b5 | 24 | #include "target.h" |
15e35479 | 25 | #include "rtl.h" |
957060b5 AM |
26 | #include "tree.h" |
27 | #include "predict.h" | |
c7131fb2 | 28 | #include "df.h" |
4d0cdd0c | 29 | #include "memmodel.h" |
15e35479 | 30 | #include "tm_p.h" |
957060b5 AM |
31 | #include "optabs.h" |
32 | #include "regs.h" | |
33 | #include "emit-rtl.h" | |
34 | #include "recog.h" | |
957060b5 | 35 | |
60393bbc AM |
36 | #include "cfgrtl.h" |
37 | #include "cfgbuild.h" | |
38 | #include "cfgcleanup.h" | |
15e35479 | 39 | #include "reload.h" |
15e35479 | 40 | #include "cselib.h" |
ef330312 | 41 | #include "tree-pass.h" |
6fb5fa3c | 42 | #include "dbgcnt.h" |
5a5a3bc5 | 43 | #include "function-abi.h" |
70b55b25 | 44 | #include "rtl-iter.h" |
15e35479 | 45 | |
0c20a65f | 46 | static int reload_cse_noop_set_p (rtx); |
f90af2e0 | 47 | static bool reload_cse_simplify (rtx_insn *, rtx); |
3a15c2cf | 48 | static void reload_cse_regs_1 (void); |
f90af2e0 DM |
49 | static int reload_cse_simplify_set (rtx, rtx_insn *); |
50 | static int reload_cse_simplify_operands (rtx_insn *, rtx); | |
15e35479 | 51 | |
0c20a65f | 52 | static void reload_combine (void); |
f90af2e0 | 53 | static void reload_combine_note_use (rtx *, rtx_insn *, int, rtx); |
7bc980e1 | 54 | static void reload_combine_note_store (rtx, const_rtx, void *); |
15e35479 | 55 | |
f90af2e0 | 56 | static bool reload_cse_move2add (rtx_insn *); |
7bc980e1 | 57 | static void move2add_note_store (rtx, const_rtx, void *); |
15e35479 KH |
58 | |
59 | /* Call cse / combine like post-reload optimization phases. | |
60 | FIRST is the first instruction. */ | |
8bb91f49 SB |
61 | |
62 | static void | |
f90af2e0 | 63 | reload_cse_regs (rtx_insn *first ATTRIBUTE_UNUSED) |
15e35479 | 64 | { |
dc0d5a57 | 65 | bool moves_converted; |
3a15c2cf | 66 | reload_cse_regs_1 (); |
15e35479 | 67 | reload_combine (); |
dc0d5a57 | 68 | moves_converted = reload_cse_move2add (first); |
15e35479 | 69 | if (flag_expensive_optimizations) |
dc0d5a57 BS |
70 | { |
71 | if (moves_converted) | |
72 | reload_combine (); | |
3a15c2cf | 73 | reload_cse_regs_1 (); |
dc0d5a57 | 74 | } |
15e35479 KH |
75 | } |
76 | ||
77 | /* See whether a single set SET is a noop. */ | |
78 | static int | |
0c20a65f | 79 | reload_cse_noop_set_p (rtx set) |
15e35479 KH |
80 | { |
81 | if (cselib_reg_set_mode (SET_DEST (set)) != GET_MODE (SET_DEST (set))) | |
82 | return 0; | |
83 | ||
84 | return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set)); | |
85 | } | |
86 | ||
3a15c2cf SB |
87 | /* Try to simplify INSN. Return true if the CFG may have changed. */ |
88 | static bool | |
f90af2e0 | 89 | reload_cse_simplify (rtx_insn *insn, rtx testreg) |
15e35479 KH |
90 | { |
91 | rtx body = PATTERN (insn); | |
3a15c2cf SB |
92 | basic_block insn_bb = BLOCK_FOR_INSN (insn); |
93 | unsigned insn_bb_succs = EDGE_COUNT (insn_bb->succs); | |
15e35479 | 94 | |
d5a752eb AV |
95 | /* If NO_FUNCTION_CSE has been set by the target, then we should not try |
96 | to cse function calls. */ | |
97 | if (NO_FUNCTION_CSE && CALL_P (insn)) | |
98 | return false; | |
99 | ||
d44f14cc JJ |
100 | /* Remember if this insn has been sp += const_int. */ |
101 | rtx sp_set = set_for_reg_notes (insn); | |
102 | rtx sp_addend = NULL_RTX; | |
103 | if (sp_set | |
104 | && SET_DEST (sp_set) == stack_pointer_rtx | |
105 | && GET_CODE (SET_SRC (sp_set)) == PLUS | |
106 | && XEXP (SET_SRC (sp_set), 0) == stack_pointer_rtx | |
107 | && CONST_INT_P (XEXP (SET_SRC (sp_set), 1))) | |
108 | sp_addend = XEXP (SET_SRC (sp_set), 1); | |
109 | ||
15e35479 KH |
110 | if (GET_CODE (body) == SET) |
111 | { | |
112 | int count = 0; | |
113 | ||
114 | /* Simplify even if we may think it is a no-op. | |
115 | We may think a memory load of a value smaller than WORD_SIZE | |
116 | is redundant because we haven't taken into account possible | |
117 | implicit extension. reload_cse_simplify_set() will bring | |
118 | this out, so it's safer to simplify before we delete. */ | |
119 | count += reload_cse_simplify_set (body, insn); | |
120 | ||
121 | if (!count && reload_cse_noop_set_p (body)) | |
122 | { | |
9e582b1d JR |
123 | if (check_for_inc_dec (insn)) |
124 | delete_insn_and_edges (insn); | |
3a15c2cf SB |
125 | /* We're done with this insn. */ |
126 | goto done; | |
15e35479 KH |
127 | } |
128 | ||
129 | if (count > 0) | |
130 | apply_change_group (); | |
131 | else | |
132 | reload_cse_simplify_operands (insn, testreg); | |
133 | } | |
134 | else if (GET_CODE (body) == PARALLEL) | |
135 | { | |
136 | int i; | |
137 | int count = 0; | |
138 | rtx value = NULL_RTX; | |
139 | ||
0d87c765 RH |
140 | /* Registers mentioned in the clobber list for an asm cannot be reused |
141 | within the body of the asm. Invalidate those registers now so that | |
142 | we don't try to substitute values for them. */ | |
143 | if (asm_noperands (body) >= 0) | |
144 | { | |
145 | for (i = XVECLEN (body, 0) - 1; i >= 0; --i) | |
146 | { | |
147 | rtx part = XVECEXP (body, 0, i); | |
148 | if (GET_CODE (part) == CLOBBER && REG_P (XEXP (part, 0))) | |
149 | cselib_invalidate_rtx (XEXP (part, 0)); | |
150 | } | |
151 | } | |
152 | ||
15e35479 KH |
153 | /* If every action in a PARALLEL is a noop, we can delete |
154 | the entire PARALLEL. */ | |
155 | for (i = XVECLEN (body, 0) - 1; i >= 0; --i) | |
156 | { | |
157 | rtx part = XVECEXP (body, 0, i); | |
158 | if (GET_CODE (part) == SET) | |
159 | { | |
160 | if (! reload_cse_noop_set_p (part)) | |
161 | break; | |
162 | if (REG_P (SET_DEST (part)) | |
163 | && REG_FUNCTION_VALUE_P (SET_DEST (part))) | |
164 | { | |
165 | if (value) | |
166 | break; | |
167 | value = SET_DEST (part); | |
168 | } | |
169 | } | |
17d184e5 | 170 | else if (GET_CODE (part) != CLOBBER && GET_CODE (part) != USE) |
15e35479 KH |
171 | break; |
172 | } | |
173 | ||
174 | if (i < 0) | |
175 | { | |
9e582b1d JR |
176 | if (check_for_inc_dec (insn)) |
177 | delete_insn_and_edges (insn); | |
15e35479 | 178 | /* We're done with this insn. */ |
3a15c2cf | 179 | goto done; |
15e35479 KH |
180 | } |
181 | ||
182 | /* It's not a no-op, but we can try to simplify it. */ | |
183 | for (i = XVECLEN (body, 0) - 1; i >= 0; --i) | |
184 | if (GET_CODE (XVECEXP (body, 0, i)) == SET) | |
185 | count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn); | |
186 | ||
187 | if (count > 0) | |
188 | apply_change_group (); | |
189 | else | |
190 | reload_cse_simplify_operands (insn, testreg); | |
191 | } | |
3a15c2cf | 192 | |
d44f14cc JJ |
193 | /* If sp += const_int insn is changed into sp = reg;, add REG_EQUAL |
194 | note so that the stack_adjustments pass can undo it if beneficial. */ | |
195 | if (sp_addend | |
196 | && SET_DEST (sp_set) == stack_pointer_rtx | |
197 | && REG_P (SET_SRC (sp_set))) | |
198 | set_dst_reg_note (insn, REG_EQUAL, | |
199 | gen_rtx_PLUS (Pmode, stack_pointer_rtx, | |
200 | sp_addend), stack_pointer_rtx); | |
201 | ||
3a15c2cf SB |
202 | done: |
203 | return (EDGE_COUNT (insn_bb->succs) != insn_bb_succs); | |
15e35479 KH |
204 | } |
205 | ||
206 | /* Do a very simple CSE pass over the hard registers. | |
207 | ||
208 | This function detects no-op moves where we happened to assign two | |
209 | different pseudo-registers to the same hard register, and then | |
210 | copied one to the other. Reload will generate a useless | |
211 | instruction copying a register to itself. | |
212 | ||
213 | This function also detects cases where we load a value from memory | |
214 | into two different registers, and (if memory is more expensive than | |
215 | registers) changes it to simply copy the first register into the | |
216 | second register. | |
217 | ||
218 | Another optimization is performed that scans the operands of each | |
219 | instruction to see whether the value is already available in a | |
220 | hard register. It then replaces the operand with the hard register | |
221 | if possible, much like an optional reload would. */ | |
222 | ||
223 | static void | |
3a15c2cf | 224 | reload_cse_regs_1 (void) |
15e35479 | 225 | { |
3a15c2cf SB |
226 | bool cfg_changed = false; |
227 | basic_block bb; | |
f90af2e0 | 228 | rtx_insn *insn; |
c3dc5e66 | 229 | rtx testreg = gen_rtx_REG (word_mode, LAST_VIRTUAL_REGISTER + 1); |
15e35479 | 230 | |
457eeaae | 231 | cselib_init (CSELIB_RECORD_MEMORY); |
15e35479 KH |
232 | init_alias_analysis (); |
233 | ||
11cd3bed | 234 | FOR_EACH_BB_FN (bb, cfun) |
3a15c2cf SB |
235 | FOR_BB_INSNS (bb, insn) |
236 | { | |
237 | if (INSN_P (insn)) | |
238 | cfg_changed |= reload_cse_simplify (insn, testreg); | |
15e35479 | 239 | |
3a15c2cf SB |
240 | cselib_process_insn (insn); |
241 | } | |
15e35479 KH |
242 | |
243 | /* Clean up. */ | |
244 | end_alias_analysis (); | |
245 | cselib_finish (); | |
3a15c2cf SB |
246 | if (cfg_changed) |
247 | cleanup_cfg (0); | |
15e35479 KH |
248 | } |
249 | ||
250 | /* Try to simplify a single SET instruction. SET is the set pattern. | |
251 | INSN is the instruction it came from. | |
252 | This function only handles one case: if we set a register to a value | |
253 | which is not a register, we try to find that value in some other register | |
254 | and change the set into a register copy. */ | |
255 | ||
256 | static int | |
f90af2e0 | 257 | reload_cse_simplify_set (rtx set, rtx_insn *insn) |
15e35479 KH |
258 | { |
259 | int did_change = 0; | |
260 | int dreg; | |
261 | rtx src; | |
6f76a878 | 262 | reg_class_t dclass; |
15e35479 KH |
263 | int old_cost; |
264 | cselib_val *val; | |
265 | struct elt_loc_list *l; | |
f822d252 | 266 | enum rtx_code extend_op = UNKNOWN; |
f40751dd | 267 | bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); |
15e35479 KH |
268 | |
269 | dreg = true_regnum (SET_DEST (set)); | |
270 | if (dreg < 0) | |
271 | return 0; | |
272 | ||
273 | src = SET_SRC (set); | |
274 | if (side_effects_p (src) || true_regnum (src) >= 0) | |
275 | return 0; | |
276 | ||
277 | dclass = REGNO_REG_CLASS (dreg); | |
278 | ||
15e35479 KH |
279 | /* When replacing a memory with a register, we need to honor assumptions |
280 | that combine made wrt the contents of sign bits. We'll do this by | |
281 | generating an extend instruction instead of a reg->reg copy. Thus | |
282 | the destination must be a register that we can widen. */ | |
3c0cb5de | 283 | if (MEM_P (src) |
3712c7a3 | 284 | && (extend_op = load_extend_op (GET_MODE (src))) != UNKNOWN |
f8cfc6aa | 285 | && !REG_P (SET_DEST (set))) |
15e35479 | 286 | return 0; |
15e35479 | 287 | |
4deef538 | 288 | val = cselib_lookup (src, GET_MODE (SET_DEST (set)), 0, VOIDmode); |
b2948a2c KH |
289 | if (! val) |
290 | return 0; | |
291 | ||
15e35479 | 292 | /* If memory loads are cheaper than register copies, don't change them. */ |
3c0cb5de | 293 | if (MEM_P (src)) |
f5c21ef3 | 294 | old_cost = memory_move_cost (GET_MODE (src), dclass, true); |
f8cfc6aa | 295 | else if (REG_P (src)) |
de8f4b07 | 296 | old_cost = register_move_cost (GET_MODE (src), |
15e35479 KH |
297 | REGNO_REG_CLASS (REGNO (src)), dclass); |
298 | else | |
e548c9df | 299 | old_cost = set_src_cost (src, GET_MODE (SET_DEST (set)), speed); |
15e35479 | 300 | |
15e35479 KH |
301 | for (l = val->locs; l; l = l->next) |
302 | { | |
303 | rtx this_rtx = l->loc; | |
304 | int this_cost; | |
305 | ||
306 | if (CONSTANT_P (this_rtx) && ! references_value_p (this_rtx, 0)) | |
307 | { | |
f822d252 | 308 | if (extend_op != UNKNOWN) |
15e35479 | 309 | { |
807e902e | 310 | wide_int result; |
15e35479 | 311 | |
807e902e | 312 | if (!CONST_SCALAR_INT_P (this_rtx)) |
15e35479 KH |
313 | continue; |
314 | ||
15e35479 KH |
315 | switch (extend_op) |
316 | { | |
317 | case ZERO_EXTEND: | |
f079167a RS |
318 | result = wide_int::from (rtx_mode_t (this_rtx, |
319 | GET_MODE (src)), | |
807e902e | 320 | BITS_PER_WORD, UNSIGNED); |
15e35479 KH |
321 | break; |
322 | case SIGN_EXTEND: | |
f079167a RS |
323 | result = wide_int::from (rtx_mode_t (this_rtx, |
324 | GET_MODE (src)), | |
807e902e KZ |
325 | BITS_PER_WORD, SIGNED); |
326 | break; | |
15e35479 | 327 | default: |
e16acfcd | 328 | gcc_unreachable (); |
15e35479 | 329 | } |
807e902e | 330 | this_rtx = immed_wide_int_const (result, word_mode); |
15e35479 | 331 | } |
f1657f05 | 332 | |
e548c9df | 333 | this_cost = set_src_cost (this_rtx, GET_MODE (SET_DEST (set)), speed); |
15e35479 | 334 | } |
f8cfc6aa | 335 | else if (REG_P (this_rtx)) |
15e35479 | 336 | { |
f822d252 | 337 | if (extend_op != UNKNOWN) |
15e35479 KH |
338 | { |
339 | this_rtx = gen_rtx_fmt_e (extend_op, word_mode, this_rtx); | |
e548c9df | 340 | this_cost = set_src_cost (this_rtx, word_mode, speed); |
15e35479 KH |
341 | } |
342 | else | |
de8f4b07 | 343 | this_cost = register_move_cost (GET_MODE (this_rtx), |
15e35479 KH |
344 | REGNO_REG_CLASS (REGNO (this_rtx)), |
345 | dclass); | |
346 | } | |
347 | else | |
348 | continue; | |
349 | ||
350 | /* If equal costs, prefer registers over anything else. That | |
351 | tends to lead to smaller instructions on some machines. */ | |
352 | if (this_cost < old_cost | |
353 | || (this_cost == old_cost | |
f8cfc6aa JQ |
354 | && REG_P (this_rtx) |
355 | && !REG_P (SET_SRC (set)))) | |
15e35479 | 356 | { |
3712c7a3 | 357 | if (extend_op != UNKNOWN |
0d803030 RS |
358 | && REG_CAN_CHANGE_MODE_P (REGNO (SET_DEST (set)), |
359 | GET_MODE (SET_DEST (set)), word_mode)) | |
15e35479 KH |
360 | { |
361 | rtx wide_dest = gen_rtx_REG (word_mode, REGNO (SET_DEST (set))); | |
362 | ORIGINAL_REGNO (wide_dest) = ORIGINAL_REGNO (SET_DEST (set)); | |
363 | validate_change (insn, &SET_DEST (set), wide_dest, 1); | |
364 | } | |
15e35479 | 365 | |
95e88efd | 366 | validate_unshare_change (insn, &SET_SRC (set), this_rtx, 1); |
15e35479 KH |
367 | old_cost = this_cost, did_change = 1; |
368 | } | |
369 | } | |
370 | ||
371 | return did_change; | |
372 | } | |
373 | ||
374 | /* Try to replace operands in INSN with equivalent values that are already | |
375 | in registers. This can be viewed as optional reloading. | |
376 | ||
377 | For each non-register operand in the insn, see if any hard regs are | |
378 | known to be equivalent to that operand. Record the alternatives which | |
379 | can accept these hard registers. Among all alternatives, select the | |
380 | ones which are better or equal to the one currently matching, where | |
381 | "better" is in terms of '?' and '!' constraints. Among the remaining | |
382 | alternatives, select the one which replaces most operands with | |
383 | hard registers. */ | |
384 | ||
385 | static int | |
f90af2e0 | 386 | reload_cse_simplify_operands (rtx_insn *insn, rtx testreg) |
15e35479 KH |
387 | { |
388 | int i, j; | |
389 | ||
390 | /* For each operand, all registers that are equivalent to it. */ | |
391 | HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS]; | |
392 | ||
393 | const char *constraints[MAX_RECOG_OPERANDS]; | |
394 | ||
395 | /* Vector recording how bad an alternative is. */ | |
396 | int *alternative_reject; | |
397 | /* Vector recording how many registers can be introduced by choosing | |
398 | this alternative. */ | |
399 | int *alternative_nregs; | |
400 | /* Array of vectors recording, for each operand and each alternative, | |
401 | which hard register to substitute, or -1 if the operand should be | |
402 | left as it is. */ | |
403 | int *op_alt_regno[MAX_RECOG_OPERANDS]; | |
404 | /* Array of alternatives, sorted in order of decreasing desirability. */ | |
405 | int *alternative_order; | |
406 | ||
75d25a02 | 407 | extract_constrain_insn (insn); |
15e35479 KH |
408 | |
409 | if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0) | |
410 | return 0; | |
411 | ||
d3bfe4de KG |
412 | alternative_reject = XALLOCAVEC (int, recog_data.n_alternatives); |
413 | alternative_nregs = XALLOCAVEC (int, recog_data.n_alternatives); | |
414 | alternative_order = XALLOCAVEC (int, recog_data.n_alternatives); | |
703ad42b KG |
415 | memset (alternative_reject, 0, recog_data.n_alternatives * sizeof (int)); |
416 | memset (alternative_nregs, 0, recog_data.n_alternatives * sizeof (int)); | |
15e35479 KH |
417 | |
418 | /* For each operand, find out which regs are equivalent. */ | |
419 | for (i = 0; i < recog_data.n_operands; i++) | |
420 | { | |
421 | cselib_val *v; | |
422 | struct elt_loc_list *l; | |
115df136 | 423 | rtx op; |
15e35479 KH |
424 | |
425 | CLEAR_HARD_REG_SET (equiv_regs[i]); | |
426 | ||
427 | /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem | |
854dde43 JJ |
428 | right, so avoid the problem here. Similarly NOTE_INSN_DELETED_LABEL. |
429 | Likewise if we have a constant and the insn pattern doesn't tell us | |
430 | the mode we need. */ | |
4b4bf941 | 431 | if (LABEL_P (recog_data.operand[i]) |
854dde43 JJ |
432 | || (NOTE_P (recog_data.operand[i]) |
433 | && NOTE_KIND (recog_data.operand[i]) == NOTE_INSN_DELETED_LABEL) | |
15e35479 KH |
434 | || (CONSTANT_P (recog_data.operand[i]) |
435 | && recog_data.operand_mode[i] == VOIDmode)) | |
436 | continue; | |
437 | ||
115df136 | 438 | op = recog_data.operand[i]; |
3712c7a3 | 439 | if (MEM_P (op) && load_extend_op (GET_MODE (op)) != UNKNOWN) |
115df136 R |
440 | { |
441 | rtx set = single_set (insn); | |
442 | ||
1f52178b | 443 | /* We might have multiple sets, some of which do implicit |
115df136 R |
444 | extension. Punt on this for now. */ |
445 | if (! set) | |
446 | continue; | |
1f838355 | 447 | /* If the destination is also a MEM or a STRICT_LOW_PART, no |
115df136 R |
448 | extension applies. |
449 | Also, if there is an explicit extension, we don't have to | |
450 | worry about an implicit one. */ | |
3c0cb5de | 451 | else if (MEM_P (SET_DEST (set)) |
115df136 R |
452 | || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART |
453 | || GET_CODE (SET_SRC (set)) == ZERO_EXTEND | |
454 | || GET_CODE (SET_SRC (set)) == SIGN_EXTEND) | |
455 | ; /* Continue ordinary processing. */ | |
7be4d808 R |
456 | /* If the register cannot change mode to word_mode, it follows that |
457 | it cannot have been used in word_mode. */ | |
f8cfc6aa | 458 | else if (REG_P (SET_DEST (set)) |
0d803030 RS |
459 | && !REG_CAN_CHANGE_MODE_P (REGNO (SET_DEST (set)), |
460 | GET_MODE (SET_DEST (set)), | |
461 | word_mode)) | |
7be4d808 | 462 | ; /* Continue ordinary processing. */ |
115df136 | 463 | /* If this is a straight load, make the extension explicit. */ |
f8cfc6aa | 464 | else if (REG_P (SET_DEST (set)) |
115df136 R |
465 | && recog_data.n_operands == 2 |
466 | && SET_SRC (set) == op | |
467 | && SET_DEST (set) == recog_data.operand[1-i]) | |
468 | { | |
469 | validate_change (insn, recog_data.operand_loc[i], | |
3712c7a3 | 470 | gen_rtx_fmt_e (load_extend_op (GET_MODE (op)), |
115df136 R |
471 | word_mode, op), |
472 | 1); | |
473 | validate_change (insn, recog_data.operand_loc[1-i], | |
474 | gen_rtx_REG (word_mode, REGNO (SET_DEST (set))), | |
475 | 1); | |
476 | if (! apply_change_group ()) | |
477 | return 0; | |
478 | return reload_cse_simplify_operands (insn, testreg); | |
479 | } | |
480 | else | |
481 | /* ??? There might be arithmetic operations with memory that are | |
482 | safe to optimize, but is it worth the trouble? */ | |
483 | continue; | |
484 | } | |
f1657f05 | 485 | |
3f82421f PH |
486 | if (side_effects_p (op)) |
487 | continue; | |
4deef538 | 488 | v = cselib_lookup (op, recog_data.operand_mode[i], 0, VOIDmode); |
15e35479 KH |
489 | if (! v) |
490 | continue; | |
491 | ||
492 | for (l = v->locs; l; l = l->next) | |
f8cfc6aa | 493 | if (REG_P (l->loc)) |
15e35479 KH |
494 | SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc)); |
495 | } | |
496 | ||
9840b2fa | 497 | alternative_mask preferred = get_preferred_alternatives (insn); |
15e35479 KH |
498 | for (i = 0; i < recog_data.n_operands; i++) |
499 | { | |
ef4bddc2 | 500 | machine_mode mode; |
15e35479 KH |
501 | int regno; |
502 | const char *p; | |
503 | ||
d3bfe4de | 504 | op_alt_regno[i] = XALLOCAVEC (int, recog_data.n_alternatives); |
15e35479 KH |
505 | for (j = 0; j < recog_data.n_alternatives; j++) |
506 | op_alt_regno[i][j] = -1; | |
507 | ||
508 | p = constraints[i] = recog_data.constraints[i]; | |
509 | mode = recog_data.operand_mode[i]; | |
510 | ||
511 | /* Add the reject values for each alternative given by the constraints | |
512 | for this operand. */ | |
513 | j = 0; | |
514 | while (*p != '\0') | |
515 | { | |
516 | char c = *p++; | |
517 | if (c == ',') | |
518 | j++; | |
519 | else if (c == '?') | |
520 | alternative_reject[j] += 3; | |
521 | else if (c == '!') | |
522 | alternative_reject[j] += 300; | |
523 | } | |
524 | ||
525 | /* We won't change operands which are already registers. We | |
526 | also don't want to modify output operands. */ | |
527 | regno = true_regnum (recog_data.operand[i]); | |
528 | if (regno >= 0 | |
529 | || constraints[i][0] == '=' | |
530 | || constraints[i][0] == '+') | |
531 | continue; | |
532 | ||
533 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
534 | { | |
bbbbb16a | 535 | enum reg_class rclass = NO_REGS; |
15e35479 KH |
536 | |
537 | if (! TEST_HARD_REG_BIT (equiv_regs[i], regno)) | |
538 | continue; | |
539 | ||
8deccbb7 | 540 | set_mode_and_regno (testreg, mode, regno); |
15e35479 KH |
541 | |
542 | /* We found a register equal to this operand. Now look for all | |
543 | alternatives that can accept this register and have not been | |
544 | assigned a register they can use yet. */ | |
545 | j = 0; | |
546 | p = constraints[i]; | |
547 | for (;;) | |
548 | { | |
549 | char c = *p; | |
550 | ||
551 | switch (c) | |
552 | { | |
8677664e RS |
553 | case 'g': |
554 | rclass = reg_class_subunion[rclass][GENERAL_REGS]; | |
15e35479 KH |
555 | break; |
556 | ||
557 | default: | |
d858f359 | 558 | rclass |
15e35479 | 559 | = (reg_class_subunion |
777e635f RS |
560 | [rclass] |
561 | [reg_class_for_constraint (lookup_constraint (p))]); | |
15e35479 KH |
562 | break; |
563 | ||
564 | case ',': case '\0': | |
565 | /* See if REGNO fits this alternative, and set it up as the | |
566 | replacement register if we don't have one for this | |
567 | alternative yet and the operand being replaced is not | |
568 | a cheap CONST_INT. */ | |
569 | if (op_alt_regno[i][j] == -1 | |
9840b2fa | 570 | && TEST_BIT (preferred, j) |
d858f359 | 571 | && reg_fits_class_p (testreg, rclass, 0, mode) |
481683e1 | 572 | && (!CONST_INT_P (recog_data.operand[i]) |
e548c9df | 573 | || (set_src_cost (recog_data.operand[i], mode, |
5e8f01f4 RS |
574 | optimize_bb_for_speed_p |
575 | (BLOCK_FOR_INSN (insn))) | |
e548c9df | 576 | > set_src_cost (testreg, mode, |
5e8f01f4 RS |
577 | optimize_bb_for_speed_p |
578 | (BLOCK_FOR_INSN (insn)))))) | |
15e35479 KH |
579 | { |
580 | alternative_nregs[j]++; | |
581 | op_alt_regno[i][j] = regno; | |
582 | } | |
583 | j++; | |
bbbbb16a | 584 | rclass = NO_REGS; |
15e35479 KH |
585 | break; |
586 | } | |
587 | p += CONSTRAINT_LEN (c, p); | |
588 | ||
589 | if (c == '\0') | |
590 | break; | |
591 | } | |
592 | } | |
593 | } | |
594 | ||
c1057cc0 MS |
595 | /* The loop below sets alternative_order[0] but -Wmaybe-uninitialized |
596 | can't know that. Clear it here to avoid the warning. */ | |
597 | alternative_order[0] = 0; | |
598 | gcc_assert (!recog_data.n_alternatives | |
599 | || (which_alternative >= 0 | |
600 | && which_alternative < recog_data.n_alternatives)); | |
601 | ||
15e35479 KH |
602 | /* Record all alternatives which are better or equal to the currently |
603 | matching one in the alternative_order array. */ | |
604 | for (i = j = 0; i < recog_data.n_alternatives; i++) | |
605 | if (alternative_reject[i] <= alternative_reject[which_alternative]) | |
606 | alternative_order[j++] = i; | |
607 | recog_data.n_alternatives = j; | |
608 | ||
609 | /* Sort it. Given a small number of alternatives, a dumb algorithm | |
610 | won't hurt too much. */ | |
611 | for (i = 0; i < recog_data.n_alternatives - 1; i++) | |
612 | { | |
613 | int best = i; | |
614 | int best_reject = alternative_reject[alternative_order[i]]; | |
615 | int best_nregs = alternative_nregs[alternative_order[i]]; | |
15e35479 KH |
616 | |
617 | for (j = i + 1; j < recog_data.n_alternatives; j++) | |
618 | { | |
619 | int this_reject = alternative_reject[alternative_order[j]]; | |
620 | int this_nregs = alternative_nregs[alternative_order[j]]; | |
621 | ||
622 | if (this_reject < best_reject | |
8a4c09c8 | 623 | || (this_reject == best_reject && this_nregs > best_nregs)) |
15e35479 KH |
624 | { |
625 | best = j; | |
626 | best_reject = this_reject; | |
627 | best_nregs = this_nregs; | |
628 | } | |
629 | } | |
630 | ||
fab27f52 | 631 | std::swap (alternative_order[best], alternative_order[i]); |
15e35479 KH |
632 | } |
633 | ||
634 | /* Substitute the operands as determined by op_alt_regno for the best | |
635 | alternative. */ | |
636 | j = alternative_order[0]; | |
637 | ||
638 | for (i = 0; i < recog_data.n_operands; i++) | |
639 | { | |
ef4bddc2 | 640 | machine_mode mode = recog_data.operand_mode[i]; |
15e35479 KH |
641 | if (op_alt_regno[i][j] == -1) |
642 | continue; | |
643 | ||
644 | validate_change (insn, recog_data.operand_loc[i], | |
645 | gen_rtx_REG (mode, op_alt_regno[i][j]), 1); | |
646 | } | |
647 | ||
648 | for (i = recog_data.n_dups - 1; i >= 0; i--) | |
649 | { | |
650 | int op = recog_data.dup_num[i]; | |
ef4bddc2 | 651 | machine_mode mode = recog_data.operand_mode[op]; |
15e35479 KH |
652 | |
653 | if (op_alt_regno[op][j] == -1) | |
654 | continue; | |
655 | ||
656 | validate_change (insn, recog_data.dup_loc[i], | |
657 | gen_rtx_REG (mode, op_alt_regno[op][j]), 1); | |
658 | } | |
659 | ||
660 | return apply_change_group (); | |
661 | } | |
662 | \f | |
663 | /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg | |
664 | addressing now. | |
665 | This code might also be useful when reload gave up on reg+reg addressing | |
666 | because of clashes between the return register and INDEX_REG_CLASS. */ | |
667 | ||
668 | /* The maximum number of uses of a register we can keep track of to | |
669 | replace them with reg+reg addressing. */ | |
dc0d5a57 | 670 | #define RELOAD_COMBINE_MAX_USES 16 |
15e35479 | 671 | |
dc0d5a57 BS |
672 | /* Describes a recorded use of a register. */ |
673 | struct reg_use | |
674 | { | |
675 | /* The insn where a register has been used. */ | |
f90af2e0 | 676 | rtx_insn *insn; |
dc0d5a57 BS |
677 | /* Points to the memory reference enclosing the use, if any, NULL_RTX |
678 | otherwise. */ | |
679 | rtx containing_mem; | |
073a8998 | 680 | /* Location of the register within INSN. */ |
dc0d5a57 BS |
681 | rtx *usep; |
682 | /* The reverse uid of the insn. */ | |
683 | int ruid; | |
684 | }; | |
15e35479 KH |
685 | |
686 | /* If the register is used in some unknown fashion, USE_INDEX is negative. | |
687 | If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID | |
dc0d5a57 | 688 | indicates where it is first set or clobbered. |
15e35479 | 689 | Otherwise, USE_INDEX is the index of the last encountered use of the |
dc0d5a57 BS |
690 | register (which is first among these we have seen since we scan backwards). |
691 | USE_RUID indicates the first encountered, i.e. last, of these uses. | |
692 | If ALL_OFFSETS_MATCH is true, all encountered uses were inside a PLUS | |
693 | with a constant offset; OFFSET contains this constant in that case. | |
15e35479 KH |
694 | STORE_RUID is always meaningful if we only want to use a value in a |
695 | register in a different place: it denotes the next insn in the insn | |
dc0d5a57 | 696 | stream (i.e. the last encountered) that sets or clobbers the register. |
8df47bdf AH |
697 | REAL_STORE_RUID is similar, but clobbers are ignored when updating it. |
698 | EXPR is the expression used when storing the register. */ | |
15e35479 KH |
699 | static struct |
700 | { | |
701 | struct reg_use reg_use[RELOAD_COMBINE_MAX_USES]; | |
15e35479 | 702 | rtx offset; |
dc0d5a57 | 703 | int use_index; |
15e35479 | 704 | int store_ruid; |
dc0d5a57 | 705 | int real_store_ruid; |
15e35479 | 706 | int use_ruid; |
dc0d5a57 | 707 | bool all_offsets_match; |
8df47bdf | 708 | rtx expr; |
15e35479 KH |
709 | } reg_state[FIRST_PSEUDO_REGISTER]; |
710 | ||
711 | /* Reverse linear uid. This is increased in reload_combine while scanning | |
712 | the instructions from last to first. It is used to set last_label_ruid | |
713 | and the store_ruid / use_ruid fields in reg_state. */ | |
714 | static int reload_combine_ruid; | |
715 | ||
67bb0206 BS |
716 | /* The RUID of the last label we encountered in reload_combine. */ |
717 | static int last_label_ruid; | |
718 | ||
dc0d5a57 BS |
719 | /* The RUID of the last jump we encountered in reload_combine. */ |
720 | static int last_jump_ruid; | |
721 | ||
67bb0206 BS |
722 | /* The register numbers of the first and last index register. A value of |
723 | -1 in LAST_INDEX_REG indicates that we've previously computed these | |
724 | values and found no suitable index registers. */ | |
725 | static int first_index_reg = -1; | |
726 | static int last_index_reg; | |
727 | ||
15e35479 KH |
728 | #define LABEL_LIVE(LABEL) \ |
729 | (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno]) | |
730 | ||
dc0d5a57 BS |
731 | /* Subroutine of reload_combine_split_ruids, called to fix up a single |
732 | ruid pointed to by *PRUID if it is higher than SPLIT_RUID. */ | |
733 | ||
734 | static inline void | |
735 | reload_combine_split_one_ruid (int *pruid, int split_ruid) | |
736 | { | |
737 | if (*pruid > split_ruid) | |
738 | (*pruid)++; | |
739 | } | |
740 | ||
741 | /* Called when we insert a new insn in a position we've already passed in | |
742 | the scan. Examine all our state, increasing all ruids that are higher | |
743 | than SPLIT_RUID by one in order to make room for a new insn. */ | |
744 | ||
745 | static void | |
746 | reload_combine_split_ruids (int split_ruid) | |
747 | { | |
748 | unsigned i; | |
749 | ||
750 | reload_combine_split_one_ruid (&reload_combine_ruid, split_ruid); | |
751 | reload_combine_split_one_ruid (&last_label_ruid, split_ruid); | |
752 | reload_combine_split_one_ruid (&last_jump_ruid, split_ruid); | |
753 | ||
754 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
755 | { | |
756 | int j, idx = reg_state[i].use_index; | |
757 | reload_combine_split_one_ruid (®_state[i].use_ruid, split_ruid); | |
758 | reload_combine_split_one_ruid (®_state[i].store_ruid, split_ruid); | |
759 | reload_combine_split_one_ruid (®_state[i].real_store_ruid, | |
760 | split_ruid); | |
761 | if (idx < 0) | |
762 | continue; | |
763 | for (j = idx; j < RELOAD_COMBINE_MAX_USES; j++) | |
764 | { | |
765 | reload_combine_split_one_ruid (®_state[i].reg_use[j].ruid, | |
766 | split_ruid); | |
767 | } | |
768 | } | |
769 | } | |
770 | ||
771 | /* Called when we are about to rescan a previously encountered insn with | |
772 | reload_combine_note_use after modifying some part of it. This clears all | |
773 | information about uses in that particular insn. */ | |
774 | ||
775 | static void | |
f90af2e0 | 776 | reload_combine_purge_insn_uses (rtx_insn *insn) |
dc0d5a57 BS |
777 | { |
778 | unsigned i; | |
779 | ||
780 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
781 | { | |
782 | int j, k, idx = reg_state[i].use_index; | |
783 | if (idx < 0) | |
784 | continue; | |
785 | j = k = RELOAD_COMBINE_MAX_USES; | |
786 | while (j-- > idx) | |
787 | { | |
788 | if (reg_state[i].reg_use[j].insn != insn) | |
789 | { | |
790 | k--; | |
791 | if (k != j) | |
792 | reg_state[i].reg_use[k] = reg_state[i].reg_use[j]; | |
793 | } | |
794 | } | |
795 | reg_state[i].use_index = k; | |
796 | } | |
797 | } | |
798 | ||
799 | /* Called when we need to forget about all uses of REGNO after an insn | |
800 | which is identified by RUID. */ | |
801 | ||
802 | static void | |
803 | reload_combine_purge_reg_uses_after_ruid (unsigned regno, int ruid) | |
804 | { | |
805 | int j, k, idx = reg_state[regno].use_index; | |
806 | if (idx < 0) | |
807 | return; | |
808 | j = k = RELOAD_COMBINE_MAX_USES; | |
809 | while (j-- > idx) | |
810 | { | |
811 | if (reg_state[regno].reg_use[j].ruid >= ruid) | |
812 | { | |
813 | k--; | |
814 | if (k != j) | |
815 | reg_state[regno].reg_use[k] = reg_state[regno].reg_use[j]; | |
816 | } | |
817 | } | |
818 | reg_state[regno].use_index = k; | |
819 | } | |
820 | ||
821 | /* Find the use of REGNO with the ruid that is highest among those | |
822 | lower than RUID_LIMIT, and return it if it is the only use of this | |
08bd6876 | 823 | reg in the insn. Return NULL otherwise. */ |
dc0d5a57 BS |
824 | |
825 | static struct reg_use * | |
826 | reload_combine_closest_single_use (unsigned regno, int ruid_limit) | |
827 | { | |
828 | int i, best_ruid = 0; | |
829 | int use_idx = reg_state[regno].use_index; | |
830 | struct reg_use *retval; | |
831 | ||
832 | if (use_idx < 0) | |
833 | return NULL; | |
834 | retval = NULL; | |
835 | for (i = use_idx; i < RELOAD_COMBINE_MAX_USES; i++) | |
836 | { | |
b1d5eee8 BS |
837 | struct reg_use *use = reg_state[regno].reg_use + i; |
838 | int this_ruid = use->ruid; | |
dc0d5a57 BS |
839 | if (this_ruid >= ruid_limit) |
840 | continue; | |
841 | if (this_ruid > best_ruid) | |
842 | { | |
843 | best_ruid = this_ruid; | |
08bd6876 | 844 | retval = use; |
dc0d5a57 | 845 | } |
08bd6876 | 846 | else if (this_ruid == best_ruid) |
dc0d5a57 BS |
847 | retval = NULL; |
848 | } | |
849 | if (last_label_ruid >= best_ruid) | |
850 | return NULL; | |
851 | return retval; | |
852 | } | |
853 | ||
caa4a250 BS |
854 | /* After we've moved an add insn, fix up any debug insns that occur |
855 | between the old location of the add and the new location. REG is | |
856 | the destination register of the add insn; REPLACEMENT is the | |
857 | SET_SRC of the add. FROM and TO specify the range in which we | |
858 | should make this change on debug insns. */ | |
b1d5eee8 BS |
859 | |
860 | static void | |
f90af2e0 | 861 | fixup_debug_insns (rtx reg, rtx replacement, rtx_insn *from, rtx_insn *to) |
b1d5eee8 | 862 | { |
f90af2e0 | 863 | rtx_insn *insn; |
caa4a250 | 864 | for (insn = from; insn != to; insn = NEXT_INSN (insn)) |
b1d5eee8 BS |
865 | { |
866 | rtx t; | |
caa4a250 | 867 | |
65f4b875 | 868 | if (!DEBUG_BIND_INSN_P (insn)) |
b1d5eee8 | 869 | continue; |
caa4a250 BS |
870 | |
871 | t = INSN_VAR_LOCATION_LOC (insn); | |
08bd6876 | 872 | t = simplify_replace_rtx (t, reg, replacement); |
caa4a250 | 873 | validate_change (insn, &INSN_VAR_LOCATION_LOC (insn), t, 0); |
b1d5eee8 BS |
874 | } |
875 | } | |
876 | ||
a78e242c BS |
877 | /* Subroutine of reload_combine_recognize_const_pattern. Try to replace REG |
878 | with SRC in the insn described by USE, taking costs into account. Return | |
879 | true if we made the replacement. */ | |
880 | ||
881 | static bool | |
882 | try_replace_in_use (struct reg_use *use, rtx reg, rtx src) | |
883 | { | |
f90af2e0 | 884 | rtx_insn *use_insn = use->insn; |
a78e242c BS |
885 | rtx mem = use->containing_mem; |
886 | bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (use_insn)); | |
887 | ||
888 | if (mem != NULL_RTX) | |
889 | { | |
890 | addr_space_t as = MEM_ADDR_SPACE (mem); | |
891 | rtx oldaddr = XEXP (mem, 0); | |
892 | rtx newaddr = NULL_RTX; | |
893 | int old_cost = address_cost (oldaddr, GET_MODE (mem), as, speed); | |
894 | int new_cost; | |
895 | ||
896 | newaddr = simplify_replace_rtx (oldaddr, reg, src); | |
897 | if (memory_address_addr_space_p (GET_MODE (mem), newaddr, as)) | |
898 | { | |
899 | XEXP (mem, 0) = newaddr; | |
900 | new_cost = address_cost (newaddr, GET_MODE (mem), as, speed); | |
901 | XEXP (mem, 0) = oldaddr; | |
902 | if (new_cost <= old_cost | |
903 | && validate_change (use_insn, | |
904 | &XEXP (mem, 0), newaddr, 0)) | |
905 | return true; | |
906 | } | |
907 | } | |
908 | else | |
909 | { | |
910 | rtx new_set = single_set (use_insn); | |
911 | if (new_set | |
912 | && REG_P (SET_DEST (new_set)) | |
913 | && GET_CODE (SET_SRC (new_set)) == PLUS | |
914 | && REG_P (XEXP (SET_SRC (new_set), 0)) | |
915 | && CONSTANT_P (XEXP (SET_SRC (new_set), 1))) | |
916 | { | |
917 | rtx new_src; | |
e548c9df AM |
918 | machine_mode mode = GET_MODE (SET_DEST (new_set)); |
919 | int old_cost = set_src_cost (SET_SRC (new_set), mode, speed); | |
a78e242c BS |
920 | |
921 | gcc_assert (rtx_equal_p (XEXP (SET_SRC (new_set), 0), reg)); | |
922 | new_src = simplify_replace_rtx (SET_SRC (new_set), reg, src); | |
923 | ||
e548c9df | 924 | if (set_src_cost (new_src, mode, speed) <= old_cost |
a78e242c BS |
925 | && validate_change (use_insn, &SET_SRC (new_set), |
926 | new_src, 0)) | |
927 | return true; | |
928 | } | |
929 | } | |
930 | return false; | |
931 | } | |
932 | ||
dc0d5a57 BS |
933 | /* Called by reload_combine when scanning INSN. This function tries to detect |
934 | patterns where a constant is added to a register, and the result is used | |
935 | in an address. | |
936 | Return true if no further processing is needed on INSN; false if it wasn't | |
937 | recognized and should be handled normally. */ | |
938 | ||
939 | static bool | |
f90af2e0 | 940 | reload_combine_recognize_const_pattern (rtx_insn *insn) |
dc0d5a57 BS |
941 | { |
942 | int from_ruid = reload_combine_ruid; | |
943 | rtx set, pat, reg, src, addreg; | |
944 | unsigned int regno; | |
945 | struct reg_use *use; | |
946 | bool must_move_add; | |
f90af2e0 | 947 | rtx_insn *add_moved_after_insn = NULL; |
dc0d5a57 BS |
948 | int add_moved_after_ruid = 0; |
949 | int clobbered_regno = -1; | |
950 | ||
951 | set = single_set (insn); | |
952 | if (set == NULL_RTX) | |
953 | return false; | |
954 | ||
955 | reg = SET_DEST (set); | |
956 | src = SET_SRC (set); | |
957 | if (!REG_P (reg) | |
dc8afb70 | 958 | || REG_NREGS (reg) != 1 |
dc0d5a57 BS |
959 | || GET_MODE (reg) != Pmode |
960 | || reg == stack_pointer_rtx) | |
961 | return false; | |
962 | ||
963 | regno = REGNO (reg); | |
964 | ||
965 | /* We look for a REG1 = REG2 + CONSTANT insn, followed by either | |
966 | uses of REG1 inside an address, or inside another add insn. If | |
967 | possible and profitable, merge the addition into subsequent | |
968 | uses. */ | |
969 | if (GET_CODE (src) != PLUS | |
970 | || !REG_P (XEXP (src, 0)) | |
971 | || !CONSTANT_P (XEXP (src, 1))) | |
972 | return false; | |
973 | ||
974 | addreg = XEXP (src, 0); | |
975 | must_move_add = rtx_equal_p (reg, addreg); | |
976 | ||
977 | pat = PATTERN (insn); | |
978 | if (must_move_add && set != pat) | |
979 | { | |
980 | /* We have to be careful when moving the add; apart from the | |
981 | single_set there may also be clobbers. Recognize one special | |
982 | case, that of one clobber alongside the set (likely a clobber | |
983 | of the CC register). */ | |
984 | gcc_assert (GET_CODE (PATTERN (insn)) == PARALLEL); | |
985 | if (XVECLEN (pat, 0) != 2 || XVECEXP (pat, 0, 0) != set | |
986 | || GET_CODE (XVECEXP (pat, 0, 1)) != CLOBBER | |
987 | || !REG_P (XEXP (XVECEXP (pat, 0, 1), 0))) | |
988 | return false; | |
989 | clobbered_regno = REGNO (XEXP (XVECEXP (pat, 0, 1), 0)); | |
990 | } | |
991 | ||
992 | do | |
993 | { | |
994 | use = reload_combine_closest_single_use (regno, from_ruid); | |
995 | ||
996 | if (use) | |
997 | /* Start the search for the next use from here. */ | |
998 | from_ruid = use->ruid; | |
999 | ||
1000 | if (use && GET_MODE (*use->usep) == Pmode) | |
1001 | { | |
a78e242c | 1002 | bool delete_add = false; |
f90af2e0 | 1003 | rtx_insn *use_insn = use->insn; |
dc0d5a57 | 1004 | int use_ruid = use->ruid; |
dc0d5a57 BS |
1005 | |
1006 | /* Avoid moving the add insn past a jump. */ | |
b1d5eee8 | 1007 | if (must_move_add && use_ruid <= last_jump_ruid) |
dc0d5a57 BS |
1008 | break; |
1009 | ||
1010 | /* If the add clobbers another hard reg in parallel, don't move | |
1011 | it past a real set of this hard reg. */ | |
1012 | if (must_move_add && clobbered_regno >= 0 | |
1013 | && reg_state[clobbered_regno].real_store_ruid >= use_ruid) | |
1014 | break; | |
1015 | ||
3b8ff89f | 1016 | /* Do not separate cc0 setter and cc0 user on HAVE_cc0 targets. */ |
058eb3b0 | 1017 | if (HAVE_cc0 && must_move_add && sets_cc0_p (PATTERN (use_insn))) |
3b8ff89f | 1018 | break; |
3b8ff89f | 1019 | |
62036819 BS |
1020 | gcc_assert (reg_state[regno].store_ruid <= use_ruid); |
1021 | /* Avoid moving a use of ADDREG past a point where it is stored. */ | |
a78e242c | 1022 | if (reg_state[REGNO (addreg)].store_ruid > use_ruid) |
dc0d5a57 BS |
1023 | break; |
1024 | ||
a78e242c BS |
1025 | /* We also must not move the addition past an insn that sets |
1026 | the same register, unless we can combine two add insns. */ | |
1027 | if (must_move_add && reg_state[regno].store_ruid == use_ruid) | |
dc0d5a57 | 1028 | { |
a78e242c BS |
1029 | if (use->containing_mem == NULL_RTX) |
1030 | delete_add = true; | |
1031 | else | |
1032 | break; | |
dc0d5a57 | 1033 | } |
dc0d5a57 | 1034 | |
a78e242c BS |
1035 | if (try_replace_in_use (use, reg, src)) |
1036 | { | |
1037 | reload_combine_purge_insn_uses (use_insn); | |
1038 | reload_combine_note_use (&PATTERN (use_insn), use_insn, | |
1039 | use_ruid, NULL_RTX); | |
dc0d5a57 | 1040 | |
a78e242c BS |
1041 | if (delete_add) |
1042 | { | |
1043 | fixup_debug_insns (reg, src, insn, use_insn); | |
1044 | delete_insn (insn); | |
1045 | return true; | |
1046 | } | |
1047 | if (must_move_add) | |
1048 | { | |
1049 | add_moved_after_insn = use_insn; | |
1050 | add_moved_after_ruid = use_ruid; | |
dc0d5a57 | 1051 | } |
a78e242c | 1052 | continue; |
dc0d5a57 | 1053 | } |
dc0d5a57 | 1054 | } |
62036819 BS |
1055 | /* If we get here, we couldn't handle this use. */ |
1056 | if (must_move_add) | |
1057 | break; | |
dc0d5a57 BS |
1058 | } |
1059 | while (use); | |
1060 | ||
1061 | if (!must_move_add || add_moved_after_insn == NULL_RTX) | |
1062 | /* Process the add normally. */ | |
1063 | return false; | |
1064 | ||
caa4a250 BS |
1065 | fixup_debug_insns (reg, src, insn, add_moved_after_insn); |
1066 | ||
dc0d5a57 BS |
1067 | reorder_insns (insn, insn, add_moved_after_insn); |
1068 | reload_combine_purge_reg_uses_after_ruid (regno, add_moved_after_ruid); | |
1069 | reload_combine_split_ruids (add_moved_after_ruid - 1); | |
1070 | reload_combine_note_use (&PATTERN (insn), insn, | |
1071 | add_moved_after_ruid, NULL_RTX); | |
1072 | reg_state[regno].store_ruid = add_moved_after_ruid; | |
1073 | ||
1074 | return true; | |
1075 | } | |
1076 | ||
67bb0206 BS |
1077 | /* Called by reload_combine when scanning INSN. Try to detect a pattern we |
1078 | can handle and improve. Return true if no further processing is needed on | |
1079 | INSN; false if it wasn't recognized and should be handled normally. */ | |
1080 | ||
1081 | static bool | |
f90af2e0 | 1082 | reload_combine_recognize_pattern (rtx_insn *insn) |
67bb0206 BS |
1083 | { |
1084 | rtx set, reg, src; | |
67bb0206 | 1085 | |
dc0d5a57 BS |
1086 | set = single_set (insn); |
1087 | if (set == NULL_RTX) | |
1088 | return false; | |
1089 | ||
1090 | reg = SET_DEST (set); | |
1091 | src = SET_SRC (set); | |
dc8afb70 | 1092 | if (!REG_P (reg) || REG_NREGS (reg) != 1) |
dc0d5a57 BS |
1093 | return false; |
1094 | ||
201d49e9 BS |
1095 | unsigned int regno = REGNO (reg); |
1096 | machine_mode mode = GET_MODE (reg); | |
1097 | ||
1098 | if (reg_state[regno].use_index < 0 | |
1099 | || reg_state[regno].use_index >= RELOAD_COMBINE_MAX_USES) | |
1100 | return false; | |
1101 | ||
1102 | for (int i = reg_state[regno].use_index; | |
1103 | i < RELOAD_COMBINE_MAX_USES; i++) | |
1104 | { | |
1105 | struct reg_use *use = reg_state[regno].reg_use + i; | |
1106 | if (GET_MODE (*use->usep) != mode) | |
1107 | return false; | |
32667e04 JJ |
1108 | /* Don't try to adjust (use (REGX)). */ |
1109 | if (GET_CODE (PATTERN (use->insn)) == USE | |
1110 | && &XEXP (PATTERN (use->insn), 0) == use->usep) | |
1111 | return false; | |
201d49e9 | 1112 | } |
dc0d5a57 | 1113 | |
67bb0206 BS |
1114 | /* Look for (set (REGX) (CONST_INT)) |
1115 | (set (REGX) (PLUS (REGX) (REGY))) | |
1116 | ... | |
1117 | ... (MEM (REGX)) ... | |
1118 | and convert it to | |
1119 | (set (REGZ) (CONST_INT)) | |
1120 | ... | |
1121 | ... (MEM (PLUS (REGZ) (REGY)))... . | |
1122 | ||
1123 | First, check that we have (set (REGX) (PLUS (REGX) (REGY))) | |
1124 | and that we know all uses of REGX before it dies. | |
1125 | Also, explicitly check that REGX != REGY; our life information | |
1126 | does not yet show whether REGY changes in this insn. */ | |
67bb0206 BS |
1127 | |
1128 | if (GET_CODE (src) == PLUS | |
dc0d5a57 BS |
1129 | && reg_state[regno].all_offsets_match |
1130 | && last_index_reg != -1 | |
67bb0206 BS |
1131 | && REG_P (XEXP (src, 1)) |
1132 | && rtx_equal_p (XEXP (src, 0), reg) | |
1133 | && !rtx_equal_p (XEXP (src, 1), reg) | |
1134 | && last_label_ruid < reg_state[regno].use_ruid) | |
1135 | { | |
1136 | rtx base = XEXP (src, 1); | |
f90af2e0 | 1137 | rtx_insn *prev = prev_nonnote_nondebug_insn (insn); |
67bb0206 BS |
1138 | rtx prev_set = prev ? single_set (prev) : NULL_RTX; |
1139 | rtx index_reg = NULL_RTX; | |
1140 | rtx reg_sum = NULL_RTX; | |
1141 | int i; | |
1142 | ||
1143 | /* Now we need to set INDEX_REG to an index register (denoted as | |
1144 | REGZ in the illustration above) and REG_SUM to the expression | |
1145 | register+register that we want to use to substitute uses of REG | |
1146 | (typically in MEMs) with. First check REG and BASE for being | |
1147 | index registers; we can use them even if they are not dead. */ | |
1148 | if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno) | |
1149 | || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], | |
1150 | REGNO (base))) | |
1151 | { | |
1152 | index_reg = reg; | |
1153 | reg_sum = src; | |
1154 | } | |
1155 | else | |
1156 | { | |
1157 | /* Otherwise, look for a free index register. Since we have | |
1158 | checked above that neither REG nor BASE are index registers, | |
1159 | if we find anything at all, it will be different from these | |
1160 | two registers. */ | |
1161 | for (i = first_index_reg; i <= last_index_reg; i++) | |
1162 | { | |
1163 | if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i) | |
1164 | && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES | |
1165 | && reg_state[i].store_ruid <= reg_state[regno].use_ruid | |
3df28f00 RS |
1166 | && (crtl->abi->clobbers_full_reg_p (i) |
1167 | || df_regs_ever_live_p (i)) | |
08bd6876 BS |
1168 | && (!frame_pointer_needed || i != HARD_FRAME_POINTER_REGNUM) |
1169 | && !fixed_regs[i] && !global_regs[i] | |
ad474626 | 1170 | && hard_regno_nregs (i, GET_MODE (reg)) == 1 |
08bd6876 | 1171 | && targetm.hard_regno_scratch_ok (i)) |
67bb0206 BS |
1172 | { |
1173 | index_reg = gen_rtx_REG (GET_MODE (reg), i); | |
1174 | reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base); | |
1175 | break; | |
1176 | } | |
1177 | } | |
1178 | } | |
1179 | ||
1180 | /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that | |
1181 | (REGY), i.e. BASE, is not clobbered before the last use we'll | |
1182 | create. */ | |
1183 | if (reg_sum | |
1184 | && prev_set | |
1185 | && CONST_INT_P (SET_SRC (prev_set)) | |
1186 | && rtx_equal_p (SET_DEST (prev_set), reg) | |
67bb0206 BS |
1187 | && (reg_state[REGNO (base)].store_ruid |
1188 | <= reg_state[regno].use_ruid)) | |
1189 | { | |
1190 | /* Change destination register and, if necessary, the constant | |
1191 | value in PREV, the constant loading instruction. */ | |
1192 | validate_change (prev, &SET_DEST (prev_set), index_reg, 1); | |
1193 | if (reg_state[regno].offset != const0_rtx) | |
927fb0bc JJ |
1194 | { |
1195 | HOST_WIDE_INT c | |
1196 | = trunc_int_for_mode (UINTVAL (SET_SRC (prev_set)) | |
1197 | + UINTVAL (reg_state[regno].offset), | |
1198 | GET_MODE (index_reg)); | |
1199 | validate_change (prev, &SET_SRC (prev_set), GEN_INT (c), 1); | |
1200 | } | |
67bb0206 BS |
1201 | |
1202 | /* Now for every use of REG that we have recorded, replace REG | |
1203 | with REG_SUM. */ | |
1204 | for (i = reg_state[regno].use_index; | |
1205 | i < RELOAD_COMBINE_MAX_USES; i++) | |
1206 | validate_unshare_change (reg_state[regno].reg_use[i].insn, | |
1207 | reg_state[regno].reg_use[i].usep, | |
1208 | /* Each change must have its own | |
1209 | replacement. */ | |
1210 | reg_sum, 1); | |
1211 | ||
1212 | if (apply_change_group ()) | |
1213 | { | |
caa4a250 BS |
1214 | struct reg_use *lowest_ruid = NULL; |
1215 | ||
67bb0206 BS |
1216 | /* For every new use of REG_SUM, we have to record the use |
1217 | of BASE therein, i.e. operand 1. */ | |
1218 | for (i = reg_state[regno].use_index; | |
1219 | i < RELOAD_COMBINE_MAX_USES; i++) | |
caa4a250 BS |
1220 | { |
1221 | struct reg_use *use = reg_state[regno].reg_use + i; | |
1222 | reload_combine_note_use (&XEXP (*use->usep, 1), use->insn, | |
1223 | use->ruid, use->containing_mem); | |
1224 | if (lowest_ruid == NULL || use->ruid < lowest_ruid->ruid) | |
1225 | lowest_ruid = use; | |
1226 | } | |
1227 | ||
1228 | fixup_debug_insns (reg, reg_sum, insn, lowest_ruid->insn); | |
67bb0206 | 1229 | |
67bb0206 BS |
1230 | /* Delete the reg-reg addition. */ |
1231 | delete_insn (insn); | |
1232 | ||
af1634f1 JJ |
1233 | if (reg_state[regno].offset != const0_rtx) |
1234 | /* Previous REG_EQUIV / REG_EQUAL notes for PREV | |
1235 | are now invalid. */ | |
1236 | remove_reg_equal_equiv_notes (prev); | |
67bb0206 BS |
1237 | |
1238 | reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES; | |
67bb0206 BS |
1239 | return true; |
1240 | } | |
1241 | } | |
1242 | } | |
1243 | return false; | |
1244 | } | |
1245 | ||
15e35479 | 1246 | static void |
0c20a65f | 1247 | reload_combine (void) |
15e35479 | 1248 | { |
f90af2e0 | 1249 | rtx_insn *insn, *prev; |
15e35479 KH |
1250 | basic_block bb; |
1251 | unsigned int r; | |
15e35479 KH |
1252 | int min_labelno, n_labels; |
1253 | HARD_REG_SET ever_live_at_start, *label_live; | |
1254 | ||
15e35479 KH |
1255 | /* To avoid wasting too much time later searching for an index register, |
1256 | determine the minimum and maximum index register numbers. */ | |
67bb0206 BS |
1257 | if (INDEX_REG_CLASS == NO_REGS) |
1258 | last_index_reg = -1; | |
1259 | else if (first_index_reg == -1 && last_index_reg == 0) | |
1260 | { | |
1261 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) | |
1262 | if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r)) | |
1263 | { | |
1264 | if (first_index_reg == -1) | |
1265 | first_index_reg = r; | |
1266 | ||
1267 | last_index_reg = r; | |
1268 | } | |
1269 | ||
1270 | /* If no index register is available, we can quit now. Set LAST_INDEX_REG | |
1271 | to -1 so we'll know to quit early the next time we get here. */ | |
1272 | if (first_index_reg == -1) | |
1273 | { | |
1274 | last_index_reg = -1; | |
1275 | return; | |
1276 | } | |
1277 | } | |
15e35479 | 1278 | |
15e35479 KH |
1279 | /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime |
1280 | information is a bit fuzzy immediately after reload, but it's | |
1281 | still good enough to determine which registers are live at a jump | |
1282 | destination. */ | |
1283 | min_labelno = get_first_label_num (); | |
1284 | n_labels = max_label_num () - min_labelno; | |
5ed6ace5 | 1285 | label_live = XNEWVEC (HARD_REG_SET, n_labels); |
15e35479 KH |
1286 | CLEAR_HARD_REG_SET (ever_live_at_start); |
1287 | ||
4f42035e | 1288 | FOR_EACH_BB_REVERSE_FN (bb, cfun) |
15e35479 | 1289 | { |
a813c111 | 1290 | insn = BB_HEAD (bb); |
4b4bf941 | 1291 | if (LABEL_P (insn)) |
15e35479 KH |
1292 | { |
1293 | HARD_REG_SET live; | |
89a95777 | 1294 | bitmap live_in = df_get_live_in (bb); |
15e35479 | 1295 | |
89a95777 KZ |
1296 | REG_SET_TO_HARD_REG_SET (live, live_in); |
1297 | compute_use_by_pseudos (&live, live_in); | |
6576d245 | 1298 | LABEL_LIVE (insn) = live; |
44942965 | 1299 | ever_live_at_start |= live; |
15e35479 KH |
1300 | } |
1301 | } | |
1302 | ||
1303 | /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */ | |
dc0d5a57 | 1304 | last_label_ruid = last_jump_ruid = reload_combine_ruid = 0; |
15e35479 KH |
1305 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) |
1306 | { | |
dc0d5a57 BS |
1307 | reg_state[r].store_ruid = 0; |
1308 | reg_state[r].real_store_ruid = 0; | |
15e35479 KH |
1309 | if (fixed_regs[r]) |
1310 | reg_state[r].use_index = -1; | |
1311 | else | |
1312 | reg_state[r].use_index = RELOAD_COMBINE_MAX_USES; | |
1313 | } | |
1314 | ||
dc0d5a57 | 1315 | for (insn = get_last_insn (); insn; insn = prev) |
15e35479 | 1316 | { |
7ad93142 | 1317 | bool control_flow_insn; |
15e35479 KH |
1318 | rtx note; |
1319 | ||
dc0d5a57 BS |
1320 | prev = PREV_INSN (insn); |
1321 | ||
15e35479 KH |
1322 | /* We cannot do our optimization across labels. Invalidating all the use |
1323 | information we have would be costly, so we just note where the label | |
1324 | is and then later disable any optimization that would cross it. */ | |
4b4bf941 | 1325 | if (LABEL_P (insn)) |
15e35479 | 1326 | last_label_ruid = reload_combine_ruid; |
2195c9be AK |
1327 | else if (BARRIER_P (insn)) |
1328 | { | |
1329 | /* Crossing a barrier resets all the use information. */ | |
1330 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) | |
1331 | if (! fixed_regs[r]) | |
15e35479 | 1332 | reg_state[r].use_index = RELOAD_COMBINE_MAX_USES; |
2195c9be AK |
1333 | } |
1334 | else if (INSN_P (insn) && volatile_insn_p (PATTERN (insn))) | |
1335 | /* Optimizations across insns being marked as volatile must be | |
1336 | prevented. All the usage information is invalidated | |
1337 | here. */ | |
1338 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) | |
1339 | if (! fixed_regs[r] | |
1340 | && reg_state[r].use_index != RELOAD_COMBINE_MAX_USES) | |
1341 | reg_state[r].use_index = -1; | |
15e35479 | 1342 | |
caa4a250 | 1343 | if (! NONDEBUG_INSN_P (insn)) |
15e35479 KH |
1344 | continue; |
1345 | ||
1346 | reload_combine_ruid++; | |
1347 | ||
7ad93142 EB |
1348 | control_flow_insn = control_flow_insn_p (insn); |
1349 | if (control_flow_insn) | |
dc0d5a57 BS |
1350 | last_jump_ruid = reload_combine_ruid; |
1351 | ||
1352 | if (reload_combine_recognize_const_pattern (insn) | |
1353 | || reload_combine_recognize_pattern (insn)) | |
67bb0206 | 1354 | continue; |
15e35479 | 1355 | |
e8448ba5 | 1356 | note_stores (insn, reload_combine_note_store, NULL); |
15e35479 | 1357 | |
4b4bf941 | 1358 | if (CALL_P (insn)) |
15e35479 KH |
1359 | { |
1360 | rtx link; | |
5a5a3bc5 | 1361 | HARD_REG_SET used_regs = insn_callee_abi (insn).full_reg_clobbers (); |
15e35479 KH |
1362 | |
1363 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) | |
97ded4cd | 1364 | if (TEST_HARD_REG_BIT (used_regs, r)) |
15e35479 KH |
1365 | { |
1366 | reg_state[r].use_index = RELOAD_COMBINE_MAX_USES; | |
1367 | reg_state[r].store_ruid = reload_combine_ruid; | |
1368 | } | |
1369 | ||
1370 | for (link = CALL_INSN_FUNCTION_USAGE (insn); link; | |
1371 | link = XEXP (link, 1)) | |
1372 | { | |
e384e6b5 BS |
1373 | rtx setuse = XEXP (link, 0); |
1374 | rtx usage_rtx = XEXP (setuse, 0); | |
8df47bdf | 1375 | |
e8448ba5 | 1376 | if (GET_CODE (setuse) == USE && REG_P (usage_rtx)) |
15e35479 | 1377 | { |
53d1bae9 RS |
1378 | unsigned int end_regno = END_REGNO (usage_rtx); |
1379 | for (unsigned int i = REGNO (usage_rtx); i < end_regno; ++i) | |
e8448ba5 | 1380 | reg_state[i].use_index = -1; |
15e35479 KH |
1381 | } |
1382 | } | |
15e35479 | 1383 | } |
18c33e03 | 1384 | |
57895947 | 1385 | if (control_flow_insn && !ANY_RETURN_P (PATTERN (insn))) |
15e35479 KH |
1386 | { |
1387 | /* Non-spill registers might be used at the call destination in | |
1388 | some unknown fashion, so we have to mark the unknown use. */ | |
1389 | HARD_REG_SET *live; | |
1390 | ||
1391 | if ((condjump_p (insn) || condjump_in_parallel_p (insn)) | |
1392 | && JUMP_LABEL (insn)) | |
57895947 EB |
1393 | { |
1394 | if (ANY_RETURN_P (JUMP_LABEL (insn))) | |
1395 | live = NULL; | |
1396 | else | |
1397 | live = &LABEL_LIVE (JUMP_LABEL (insn)); | |
1398 | } | |
15e35479 KH |
1399 | else |
1400 | live = &ever_live_at_start; | |
1401 | ||
57895947 EB |
1402 | if (live) |
1403 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) | |
1404 | if (TEST_HARD_REG_BIT (*live, r)) | |
1405 | reg_state[r].use_index = -1; | |
15e35479 KH |
1406 | } |
1407 | ||
7ad93142 EB |
1408 | reload_combine_note_use (&PATTERN (insn), insn, reload_combine_ruid, |
1409 | NULL_RTX); | |
1410 | ||
15e35479 KH |
1411 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) |
1412 | { | |
7ad93142 | 1413 | if (REG_NOTE_KIND (note) == REG_INC && REG_P (XEXP (note, 0))) |
15e35479 KH |
1414 | { |
1415 | int regno = REGNO (XEXP (note, 0)); | |
15e35479 | 1416 | reg_state[regno].store_ruid = reload_combine_ruid; |
dc0d5a57 | 1417 | reg_state[regno].real_store_ruid = reload_combine_ruid; |
15e35479 KH |
1418 | reg_state[regno].use_index = -1; |
1419 | } | |
1420 | } | |
1421 | } | |
1422 | ||
1423 | free (label_live); | |
1424 | } | |
1425 | ||
1426 | /* Check if DST is a register or a subreg of a register; if it is, | |
dc0d5a57 BS |
1427 | update store_ruid, real_store_ruid and use_index in the reg_state |
1428 | structure accordingly. Called via note_stores from reload_combine. */ | |
15e35479 KH |
1429 | |
1430 | static void | |
7bc980e1 | 1431 | reload_combine_note_store (rtx dst, const_rtx set, void *data ATTRIBUTE_UNUSED) |
15e35479 KH |
1432 | { |
1433 | int regno = 0; | |
1434 | int i; | |
ef4bddc2 | 1435 | machine_mode mode = GET_MODE (dst); |
15e35479 KH |
1436 | |
1437 | if (GET_CODE (dst) == SUBREG) | |
1438 | { | |
1439 | regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)), | |
1440 | GET_MODE (SUBREG_REG (dst)), | |
1441 | SUBREG_BYTE (dst), | |
1442 | GET_MODE (dst)); | |
1443 | dst = SUBREG_REG (dst); | |
1444 | } | |
12c2b0ad JL |
1445 | |
1446 | /* Some targets do argument pushes without adding REG_INC notes. */ | |
1447 | ||
1448 | if (MEM_P (dst)) | |
1449 | { | |
1450 | dst = XEXP (dst, 0); | |
1451 | if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_INC | |
96676a5d JJ |
1452 | || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC |
1453 | || GET_CODE (dst) == PRE_MODIFY || GET_CODE (dst) == POST_MODIFY) | |
12c2b0ad | 1454 | { |
53d1bae9 RS |
1455 | unsigned int end_regno = END_REGNO (XEXP (dst, 0)); |
1456 | for (unsigned int i = REGNO (XEXP (dst, 0)); i < end_regno; ++i) | |
12c2b0ad JL |
1457 | { |
1458 | /* We could probably do better, but for now mark the register | |
1459 | as used in an unknown fashion and set/clobbered at this | |
1460 | insn. */ | |
1461 | reg_state[i].use_index = -1; | |
1462 | reg_state[i].store_ruid = reload_combine_ruid; | |
1463 | reg_state[i].real_store_ruid = reload_combine_ruid; | |
1464 | } | |
1465 | } | |
1466 | else | |
1467 | return; | |
1468 | } | |
1469 | ||
f8cfc6aa | 1470 | if (!REG_P (dst)) |
15e35479 KH |
1471 | return; |
1472 | regno += REGNO (dst); | |
1473 | ||
1474 | /* note_stores might have stripped a STRICT_LOW_PART, so we have to be | |
1475 | careful with registers / register parts that are not full words. | |
46d096a3 | 1476 | Similarly for ZERO_EXTRACT. */ |
dc0d5a57 | 1477 | if (GET_CODE (SET_DEST (set)) == ZERO_EXTRACT |
15e35479 KH |
1478 | || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART) |
1479 | { | |
4edd6298 | 1480 | for (i = end_hard_regno (mode, regno) - 1; i >= regno; i--) |
15e35479 KH |
1481 | { |
1482 | reg_state[i].use_index = -1; | |
1483 | reg_state[i].store_ruid = reload_combine_ruid; | |
dc0d5a57 | 1484 | reg_state[i].real_store_ruid = reload_combine_ruid; |
15e35479 KH |
1485 | } |
1486 | } | |
1487 | else | |
1488 | { | |
4edd6298 | 1489 | for (i = end_hard_regno (mode, regno) - 1; i >= regno; i--) |
15e35479 KH |
1490 | { |
1491 | reg_state[i].store_ruid = reload_combine_ruid; | |
dc0d5a57 BS |
1492 | if (GET_CODE (set) == SET) |
1493 | reg_state[i].real_store_ruid = reload_combine_ruid; | |
15e35479 KH |
1494 | reg_state[i].use_index = RELOAD_COMBINE_MAX_USES; |
1495 | } | |
1496 | } | |
1497 | } | |
1498 | ||
1499 | /* XP points to a piece of rtl that has to be checked for any uses of | |
1500 | registers. | |
1501 | *XP is the pattern of INSN, or a part of it. | |
1502 | Called from reload_combine, and recursively by itself. */ | |
1503 | static void | |
f90af2e0 | 1504 | reload_combine_note_use (rtx *xp, rtx_insn *insn, int ruid, rtx containing_mem) |
15e35479 KH |
1505 | { |
1506 | rtx x = *xp; | |
1507 | enum rtx_code code = x->code; | |
1508 | const char *fmt; | |
1509 | int i, j; | |
1510 | rtx offset = const0_rtx; /* For the REG case below. */ | |
1511 | ||
1512 | switch (code) | |
1513 | { | |
1514 | case SET: | |
f8cfc6aa | 1515 | if (REG_P (SET_DEST (x))) |
15e35479 | 1516 | { |
dc0d5a57 | 1517 | reload_combine_note_use (&SET_SRC (x), insn, ruid, NULL_RTX); |
15e35479 KH |
1518 | return; |
1519 | } | |
1520 | break; | |
1521 | ||
1522 | case USE: | |
1523 | /* If this is the USE of a return value, we can't change it. */ | |
f8cfc6aa | 1524 | if (REG_P (XEXP (x, 0)) && REG_FUNCTION_VALUE_P (XEXP (x, 0))) |
15e35479 | 1525 | { |
53d1bae9 | 1526 | /* Mark the return register as used in an unknown fashion. */ |
15e35479 | 1527 | rtx reg = XEXP (x, 0); |
53d1bae9 RS |
1528 | unsigned int end_regno = END_REGNO (reg); |
1529 | for (unsigned int regno = REGNO (reg); regno < end_regno; ++regno) | |
1530 | reg_state[regno].use_index = -1; | |
15e35479 KH |
1531 | return; |
1532 | } | |
1533 | break; | |
1534 | ||
1535 | case CLOBBER: | |
f8cfc6aa | 1536 | if (REG_P (SET_DEST (x))) |
15e35479 KH |
1537 | { |
1538 | /* No spurious CLOBBERs of pseudo registers may remain. */ | |
e16acfcd | 1539 | gcc_assert (REGNO (SET_DEST (x)) < FIRST_PSEUDO_REGISTER); |
15e35479 KH |
1540 | return; |
1541 | } | |
1542 | break; | |
1543 | ||
1544 | case PLUS: | |
1545 | /* We are interested in (plus (reg) (const_int)) . */ | |
f8cfc6aa | 1546 | if (!REG_P (XEXP (x, 0)) |
481683e1 | 1547 | || !CONST_INT_P (XEXP (x, 1))) |
15e35479 KH |
1548 | break; |
1549 | offset = XEXP (x, 1); | |
1550 | x = XEXP (x, 0); | |
1551 | /* Fall through. */ | |
1552 | case REG: | |
1553 | { | |
1554 | int regno = REGNO (x); | |
1555 | int use_index; | |
1556 | int nregs; | |
1557 | ||
1558 | /* No spurious USEs of pseudo registers may remain. */ | |
e16acfcd | 1559 | gcc_assert (regno < FIRST_PSEUDO_REGISTER); |
15e35479 | 1560 | |
dc8afb70 | 1561 | nregs = REG_NREGS (x); |
15e35479 KH |
1562 | |
1563 | /* We can't substitute into multi-hard-reg uses. */ | |
1564 | if (nregs > 1) | |
1565 | { | |
1566 | while (--nregs >= 0) | |
1567 | reg_state[regno + nregs].use_index = -1; | |
1568 | return; | |
1569 | } | |
1570 | ||
08bd6876 BS |
1571 | /* We may be called to update uses in previously seen insns. |
1572 | Don't add uses beyond the last store we saw. */ | |
1573 | if (ruid < reg_state[regno].store_ruid) | |
1574 | return; | |
1575 | ||
15e35479 KH |
1576 | /* If this register is already used in some unknown fashion, we |
1577 | can't do anything. | |
1578 | If we decrement the index from zero to -1, we can't store more | |
1579 | uses, so this register becomes used in an unknown fashion. */ | |
1580 | use_index = --reg_state[regno].use_index; | |
1581 | if (use_index < 0) | |
1582 | return; | |
1583 | ||
dc0d5a57 | 1584 | if (use_index == RELOAD_COMBINE_MAX_USES - 1) |
15e35479 KH |
1585 | { |
1586 | /* This is the first use of this register we have seen since we | |
1587 | marked it as dead. */ | |
1588 | reg_state[regno].offset = offset; | |
dc0d5a57 BS |
1589 | reg_state[regno].all_offsets_match = true; |
1590 | reg_state[regno].use_ruid = ruid; | |
15e35479 | 1591 | } |
b1d5eee8 BS |
1592 | else |
1593 | { | |
1594 | if (reg_state[regno].use_ruid > ruid) | |
1595 | reg_state[regno].use_ruid = ruid; | |
1596 | ||
1597 | if (! rtx_equal_p (offset, reg_state[regno].offset)) | |
1598 | reg_state[regno].all_offsets_match = false; | |
1599 | } | |
dc0d5a57 | 1600 | |
15e35479 | 1601 | reg_state[regno].reg_use[use_index].insn = insn; |
dc0d5a57 BS |
1602 | reg_state[regno].reg_use[use_index].ruid = ruid; |
1603 | reg_state[regno].reg_use[use_index].containing_mem = containing_mem; | |
15e35479 KH |
1604 | reg_state[regno].reg_use[use_index].usep = xp; |
1605 | return; | |
1606 | } | |
1607 | ||
dc0d5a57 BS |
1608 | case MEM: |
1609 | containing_mem = x; | |
1610 | break; | |
1611 | ||
15e35479 KH |
1612 | default: |
1613 | break; | |
1614 | } | |
1615 | ||
1616 | /* Recursively process the components of X. */ | |
1617 | fmt = GET_RTX_FORMAT (code); | |
1618 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1619 | { | |
1620 | if (fmt[i] == 'e') | |
dc0d5a57 | 1621 | reload_combine_note_use (&XEXP (x, i), insn, ruid, containing_mem); |
15e35479 KH |
1622 | else if (fmt[i] == 'E') |
1623 | { | |
1624 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
dc0d5a57 BS |
1625 | reload_combine_note_use (&XVECEXP (x, i, j), insn, ruid, |
1626 | containing_mem); | |
15e35479 KH |
1627 | } |
1628 | } | |
1629 | } | |
1630 | \f | |
1631 | /* See if we can reduce the cost of a constant by replacing a move | |
1632 | with an add. We track situations in which a register is set to a | |
1633 | constant or to a register plus a constant. */ | |
1634 | /* We cannot do our optimization across labels. Invalidating all the | |
1635 | information about register contents we have would be costly, so we | |
1636 | use move2add_last_label_luid to note where the label is and then | |
1637 | later disable any optimization that would cross it. | |
7beb0596 JZ |
1638 | reg_offset[n] / reg_base_reg[n] / reg_symbol_ref[n] / reg_mode[n] |
1639 | are only valid if reg_set_luid[n] is greater than | |
7894bc6b JR |
1640 | move2add_last_label_luid. |
1641 | For a set that established a new (potential) base register with | |
1642 | non-constant value, we use move2add_luid from the place where the | |
1643 | setting insn is encountered; registers based off that base then | |
1644 | get the same reg_set_luid. Constants all get | |
1645 | move2add_last_label_luid + 1 as their reg_set_luid. */ | |
15e35479 KH |
1646 | static int reg_set_luid[FIRST_PSEUDO_REGISTER]; |
1647 | ||
1648 | /* If reg_base_reg[n] is negative, register n has been set to | |
7beb0596 | 1649 | reg_offset[n] or reg_symbol_ref[n] + reg_offset[n] in mode reg_mode[n]. |
15e35479 KH |
1650 | If reg_base_reg[n] is non-negative, register n has been set to the |
1651 | sum of reg_offset[n] and the value of register reg_base_reg[n] | |
7894bc6b JR |
1652 | before reg_set_luid[n], calculated in mode reg_mode[n] . |
1653 | For multi-hard-register registers, all but the first one are | |
1654 | recorded as BLKmode in reg_mode. Setting reg_mode to VOIDmode | |
1655 | marks it as invalid. */ | |
15e35479 KH |
1656 | static HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER]; |
1657 | static int reg_base_reg[FIRST_PSEUDO_REGISTER]; | |
7beb0596 | 1658 | static rtx reg_symbol_ref[FIRST_PSEUDO_REGISTER]; |
ef4bddc2 | 1659 | static machine_mode reg_mode[FIRST_PSEUDO_REGISTER]; |
15e35479 KH |
1660 | |
1661 | /* move2add_luid is linearly increased while scanning the instructions | |
1662 | from first to last. It is used to set reg_set_luid in | |
1663 | reload_cse_move2add and move2add_note_store. */ | |
1664 | static int move2add_luid; | |
1665 | ||
1666 | /* move2add_last_label_luid is set whenever a label is found. Labels | |
1667 | invalidate all previously collected reg_offset data. */ | |
1668 | static int move2add_last_label_luid; | |
1669 | ||
1670 | /* ??? We don't know how zero / sign extension is handled, hence we | |
1671 | can't go from a narrower to a wider mode. */ | |
1672 | #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \ | |
1673 | (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \ | |
1674 | || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \ | |
d0edd768 | 1675 | && TRULY_NOOP_TRUNCATION_MODES_P (OUTMODE, INMODE))) |
15e35479 | 1676 | |
7894bc6b JR |
1677 | /* Record that REG is being set to a value with the mode of REG. */ |
1678 | ||
1679 | static void | |
1680 | move2add_record_mode (rtx reg) | |
1681 | { | |
1682 | int regno, nregs; | |
ef4bddc2 | 1683 | machine_mode mode = GET_MODE (reg); |
7894bc6b JR |
1684 | |
1685 | if (GET_CODE (reg) == SUBREG) | |
1686 | { | |
1687 | regno = subreg_regno (reg); | |
1688 | nregs = subreg_nregs (reg); | |
1689 | } | |
1690 | else if (REG_P (reg)) | |
1691 | { | |
1692 | regno = REGNO (reg); | |
dc8afb70 | 1693 | nregs = REG_NREGS (reg); |
7894bc6b JR |
1694 | } |
1695 | else | |
1696 | gcc_unreachable (); | |
1697 | for (int i = nregs - 1; i > 0; i--) | |
1698 | reg_mode[regno + i] = BLKmode; | |
1699 | reg_mode[regno] = mode; | |
1700 | } | |
1701 | ||
1702 | /* Record that REG is being set to the sum of SYM and OFF. */ | |
1703 | ||
1704 | static void | |
1705 | move2add_record_sym_value (rtx reg, rtx sym, rtx off) | |
1706 | { | |
1707 | int regno = REGNO (reg); | |
1708 | ||
1709 | move2add_record_mode (reg); | |
1710 | reg_set_luid[regno] = move2add_luid; | |
1711 | reg_base_reg[regno] = -1; | |
1712 | reg_symbol_ref[regno] = sym; | |
1713 | reg_offset[regno] = INTVAL (off); | |
1714 | } | |
1715 | ||
1716 | /* Check if REGNO contains a valid value in MODE. */ | |
1717 | ||
1718 | static bool | |
1e047eed | 1719 | move2add_valid_value_p (int regno, scalar_int_mode mode) |
7894bc6b | 1720 | { |
ca035367 | 1721 | if (reg_set_luid[regno] <= move2add_last_label_luid) |
7894bc6b JR |
1722 | return false; |
1723 | ||
ca035367 JR |
1724 | if (mode != reg_mode[regno]) |
1725 | { | |
6b9c3dec RS |
1726 | scalar_int_mode old_mode; |
1727 | if (!is_a <scalar_int_mode> (reg_mode[regno], &old_mode) | |
1728 | || !MODES_OK_FOR_MOVE2ADD (mode, old_mode)) | |
ca035367 JR |
1729 | return false; |
1730 | /* The value loaded into regno in reg_mode[regno] is also valid in | |
1731 | mode after truncation only if (REG:mode regno) is the lowpart of | |
1732 | (REG:reg_mode[regno] regno). Now, for big endian, the starting | |
1733 | regno of the lowpart might be different. */ | |
91914e56 | 1734 | poly_int64 s_off = subreg_lowpart_offset (mode, old_mode); |
6b9c3dec | 1735 | s_off = subreg_regno_offset (regno, old_mode, s_off, mode); |
91914e56 | 1736 | if (maybe_ne (s_off, 0)) |
ca035367 JR |
1737 | /* We could in principle adjust regno, check reg_mode[regno] to be |
1738 | BLKmode, and return s_off to the caller (vs. -1 for failure), | |
1739 | but we currently have no callers that could make use of this | |
1740 | information. */ | |
1741 | return false; | |
1742 | } | |
1743 | ||
4edd6298 RS |
1744 | for (int i = end_hard_regno (mode, regno) - 1; i > regno; i--) |
1745 | if (reg_mode[i] != BLKmode) | |
7894bc6b JR |
1746 | return false; |
1747 | return true; | |
1748 | } | |
1749 | ||
1e047eed RS |
1750 | /* This function is called with INSN that sets REG (of mode MODE) |
1751 | to (SYM + OFF), while REG is known to already have value (SYM + offset). | |
7beb0596 JZ |
1752 | This function tries to change INSN into an add instruction |
1753 | (set (REG) (plus (REG) (OFF - offset))) using the known value. | |
dc0d5a57 BS |
1754 | It also updates the information about REG's known value. |
1755 | Return true if we made a change. */ | |
7beb0596 | 1756 | |
dc0d5a57 | 1757 | static bool |
1e047eed RS |
1758 | move2add_use_add2_insn (scalar_int_mode mode, rtx reg, rtx sym, rtx off, |
1759 | rtx_insn *insn) | |
7beb0596 JZ |
1760 | { |
1761 | rtx pat = PATTERN (insn); | |
1762 | rtx src = SET_SRC (pat); | |
1763 | int regno = REGNO (reg); | |
1e047eed | 1764 | rtx new_src = gen_int_mode (UINTVAL (off) - reg_offset[regno], mode); |
7beb0596 | 1765 | bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); |
dc0d5a57 | 1766 | bool changed = false; |
7beb0596 JZ |
1767 | |
1768 | /* (set (reg) (plus (reg) (const_int 0))) is not canonical; | |
1769 | use (set (reg) (reg)) instead. | |
1770 | We don't delete this insn, nor do we convert it into a | |
1771 | note, to avoid losing register notes or the return | |
1772 | value flag. jump2 already knows how to get rid of | |
1773 | no-op moves. */ | |
1774 | if (new_src == const0_rtx) | |
1775 | { | |
1776 | /* If the constants are different, this is a | |
1777 | truncation, that, if turned into (set (reg) | |
1778 | (reg)), would be discarded. Maybe we should | |
1779 | try a truncMN pattern? */ | |
1780 | if (INTVAL (off) == reg_offset [regno]) | |
dc0d5a57 | 1781 | changed = validate_change (insn, &SET_SRC (pat), reg, 0); |
7beb0596 | 1782 | } |
22939744 | 1783 | else |
7beb0596 | 1784 | { |
22939744 | 1785 | struct full_rtx_costs oldcst, newcst; |
1e047eed | 1786 | rtx tem = gen_rtx_PLUS (mode, reg, new_src); |
22939744 | 1787 | |
d51102f3 | 1788 | get_full_set_rtx_cost (pat, &oldcst); |
22939744 | 1789 | SET_SRC (pat) = tem; |
d51102f3 | 1790 | get_full_set_rtx_cost (pat, &newcst); |
22939744 BS |
1791 | SET_SRC (pat) = src; |
1792 | ||
1793 | if (costs_lt_p (&newcst, &oldcst, speed) | |
1794 | && have_add2_insn (reg, new_src)) | |
1795 | changed = validate_change (insn, &SET_SRC (pat), tem, 0); | |
1e047eed | 1796 | else if (sym == NULL_RTX && mode != BImode) |
7beb0596 | 1797 | { |
1e047eed RS |
1798 | scalar_int_mode narrow_mode; |
1799 | FOR_EACH_MODE_UNTIL (narrow_mode, mode) | |
7beb0596 | 1800 | { |
22939744 BS |
1801 | if (have_insn_for (STRICT_LOW_PART, narrow_mode) |
1802 | && ((reg_offset[regno] & ~GET_MODE_MASK (narrow_mode)) | |
1803 | == (INTVAL (off) & ~GET_MODE_MASK (narrow_mode)))) | |
1804 | { | |
b49eefa5 | 1805 | rtx narrow_reg = gen_lowpart_common (narrow_mode, reg); |
22939744 BS |
1806 | rtx narrow_src = gen_int_mode (INTVAL (off), |
1807 | narrow_mode); | |
1808 | rtx new_set | |
f7df4a84 | 1809 | = gen_rtx_SET (gen_rtx_STRICT_LOW_PART (VOIDmode, |
22939744 BS |
1810 | narrow_reg), |
1811 | narrow_src); | |
a0f37b26 AS |
1812 | get_full_set_rtx_cost (new_set, &newcst); |
1813 | if (costs_lt_p (&newcst, &oldcst, speed)) | |
1814 | { | |
1815 | changed = validate_change (insn, &PATTERN (insn), | |
1816 | new_set, 0); | |
1817 | if (changed) | |
1818 | break; | |
1819 | } | |
22939744 | 1820 | } |
7beb0596 JZ |
1821 | } |
1822 | } | |
1823 | } | |
7894bc6b | 1824 | move2add_record_sym_value (reg, sym, off); |
dc0d5a57 | 1825 | return changed; |
7beb0596 JZ |
1826 | } |
1827 | ||
1828 | ||
1e047eed RS |
1829 | /* This function is called with INSN that sets REG (of mode MODE) to |
1830 | (SYM + OFF), but REG doesn't have known value (SYM + offset). This | |
1831 | function tries to find another register which is known to already have | |
7beb0596 JZ |
1832 | value (SYM + offset) and change INSN into an add instruction |
1833 | (set (REG) (plus (the found register) (OFF - offset))) if such | |
1834 | a register is found. It also updates the information about | |
dc0d5a57 BS |
1835 | REG's known value. |
1836 | Return true iff we made a change. */ | |
7beb0596 | 1837 | |
dc0d5a57 | 1838 | static bool |
1e047eed RS |
1839 | move2add_use_add3_insn (scalar_int_mode mode, rtx reg, rtx sym, rtx off, |
1840 | rtx_insn *insn) | |
7beb0596 JZ |
1841 | { |
1842 | rtx pat = PATTERN (insn); | |
1843 | rtx src = SET_SRC (pat); | |
1844 | int regno = REGNO (reg); | |
5676e87d | 1845 | int min_regno = 0; |
7beb0596 JZ |
1846 | bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); |
1847 | int i; | |
dc0d5a57 | 1848 | bool changed = false; |
22939744 BS |
1849 | struct full_rtx_costs oldcst, newcst, mincst; |
1850 | rtx plus_expr; | |
1851 | ||
1852 | init_costs_to_max (&mincst); | |
d51102f3 | 1853 | get_full_set_rtx_cost (pat, &oldcst); |
22939744 BS |
1854 | |
1855 | plus_expr = gen_rtx_PLUS (GET_MODE (reg), reg, const0_rtx); | |
1856 | SET_SRC (pat) = plus_expr; | |
7beb0596 JZ |
1857 | |
1858 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1e047eed | 1859 | if (move2add_valid_value_p (i, mode) |
7beb0596 JZ |
1860 | && reg_base_reg[i] < 0 |
1861 | && reg_symbol_ref[i] != NULL_RTX | |
1862 | && rtx_equal_p (sym, reg_symbol_ref[i])) | |
1863 | { | |
e15eb172 | 1864 | rtx new_src = gen_int_mode (UINTVAL (off) - reg_offset[i], |
7beb0596 JZ |
1865 | GET_MODE (reg)); |
1866 | /* (set (reg) (plus (reg) (const_int 0))) is not canonical; | |
1867 | use (set (reg) (reg)) instead. | |
1868 | We don't delete this insn, nor do we convert it into a | |
1869 | note, to avoid losing register notes or the return | |
1870 | value flag. jump2 already knows how to get rid of | |
1871 | no-op moves. */ | |
1872 | if (new_src == const0_rtx) | |
1873 | { | |
22939744 | 1874 | init_costs_to_zero (&mincst); |
7beb0596 JZ |
1875 | min_regno = i; |
1876 | break; | |
1877 | } | |
1878 | else | |
1879 | { | |
22939744 | 1880 | XEXP (plus_expr, 1) = new_src; |
d51102f3 | 1881 | get_full_set_rtx_cost (pat, &newcst); |
22939744 BS |
1882 | |
1883 | if (costs_lt_p (&newcst, &mincst, speed)) | |
7beb0596 | 1884 | { |
22939744 | 1885 | mincst = newcst; |
7beb0596 JZ |
1886 | min_regno = i; |
1887 | } | |
1888 | } | |
1889 | } | |
22939744 | 1890 | SET_SRC (pat) = src; |
7beb0596 | 1891 | |
22939744 | 1892 | if (costs_lt_p (&mincst, &oldcst, speed)) |
7beb0596 JZ |
1893 | { |
1894 | rtx tem; | |
1895 | ||
1896 | tem = gen_rtx_REG (GET_MODE (reg), min_regno); | |
1897 | if (i != min_regno) | |
1898 | { | |
e15eb172 | 1899 | rtx new_src = gen_int_mode (UINTVAL (off) - reg_offset[min_regno], |
7beb0596 JZ |
1900 | GET_MODE (reg)); |
1901 | tem = gen_rtx_PLUS (GET_MODE (reg), tem, new_src); | |
1902 | } | |
dc0d5a57 BS |
1903 | if (validate_change (insn, &SET_SRC (pat), tem, 0)) |
1904 | changed = true; | |
7beb0596 JZ |
1905 | } |
1906 | reg_set_luid[regno] = move2add_luid; | |
7894bc6b | 1907 | move2add_record_sym_value (reg, sym, off); |
dc0d5a57 | 1908 | return changed; |
7beb0596 JZ |
1909 | } |
1910 | ||
dc0d5a57 BS |
1911 | /* Convert move insns with constant inputs to additions if they are cheaper. |
1912 | Return true if any changes were made. */ | |
1913 | static bool | |
f90af2e0 | 1914 | reload_cse_move2add (rtx_insn *first) |
15e35479 KH |
1915 | { |
1916 | int i; | |
f90af2e0 | 1917 | rtx_insn *insn; |
dc0d5a57 | 1918 | bool changed = false; |
15e35479 KH |
1919 | |
1920 | for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--) | |
7beb0596 JZ |
1921 | { |
1922 | reg_set_luid[i] = 0; | |
1923 | reg_offset[i] = 0; | |
1924 | reg_base_reg[i] = 0; | |
1925 | reg_symbol_ref[i] = NULL_RTX; | |
1926 | reg_mode[i] = VOIDmode; | |
1927 | } | |
15e35479 KH |
1928 | |
1929 | move2add_last_label_luid = 0; | |
1930 | move2add_luid = 2; | |
1931 | for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++) | |
1932 | { | |
1933 | rtx pat, note; | |
1934 | ||
4b4bf941 | 1935 | if (LABEL_P (insn)) |
15e35479 KH |
1936 | { |
1937 | move2add_last_label_luid = move2add_luid; | |
1938 | /* We're going to increment move2add_luid twice after a | |
1939 | label, so that we can use move2add_last_label_luid + 1 as | |
1940 | the luid for constants. */ | |
1941 | move2add_luid++; | |
1942 | continue; | |
1943 | } | |
1944 | if (! INSN_P (insn)) | |
1945 | continue; | |
1946 | pat = PATTERN (insn); | |
1947 | /* For simplicity, we only perform this optimization on | |
1948 | straightforward SETs. */ | |
1e047eed | 1949 | scalar_int_mode mode; |
15e35479 | 1950 | if (GET_CODE (pat) == SET |
1e047eed RS |
1951 | && REG_P (SET_DEST (pat)) |
1952 | && is_a <scalar_int_mode> (GET_MODE (SET_DEST (pat)), &mode)) | |
15e35479 KH |
1953 | { |
1954 | rtx reg = SET_DEST (pat); | |
1955 | int regno = REGNO (reg); | |
1956 | rtx src = SET_SRC (pat); | |
1957 | ||
1958 | /* Check if we have valid information on the contents of this | |
1959 | register in the mode of REG. */ | |
1e047eed | 1960 | if (move2add_valid_value_p (regno, mode) |
6fb5fa3c | 1961 | && dbg_cnt (cse2_move2add)) |
15e35479 KH |
1962 | { |
1963 | /* Try to transform (set (REGX) (CONST_INT A)) | |
1964 | ... | |
1965 | (set (REGX) (CONST_INT B)) | |
1966 | to | |
1967 | (set (REGX) (CONST_INT A)) | |
1968 | ... | |
1969 | (set (REGX) (plus (REGX) (CONST_INT B-A))) | |
1970 | or | |
1971 | (set (REGX) (CONST_INT A)) | |
1972 | ... | |
1973 | (set (STRICT_LOW_PART (REGX)) (CONST_INT B)) | |
1974 | */ | |
1975 | ||
7beb0596 JZ |
1976 | if (CONST_INT_P (src) |
1977 | && reg_base_reg[regno] < 0 | |
1978 | && reg_symbol_ref[regno] == NULL_RTX) | |
15e35479 | 1979 | { |
1e047eed RS |
1980 | changed |= move2add_use_add2_insn (mode, reg, NULL_RTX, |
1981 | src, insn); | |
15e35479 KH |
1982 | continue; |
1983 | } | |
1984 | ||
1985 | /* Try to transform (set (REGX) (REGY)) | |
1986 | (set (REGX) (PLUS (REGX) (CONST_INT A))) | |
1987 | ... | |
1988 | (set (REGX) (REGY)) | |
1989 | (set (REGX) (PLUS (REGX) (CONST_INT B))) | |
1990 | to | |
1991 | (set (REGX) (REGY)) | |
1992 | (set (REGX) (PLUS (REGX) (CONST_INT A))) | |
1993 | ... | |
1994 | (set (REGX) (plus (REGX) (CONST_INT B-A))) */ | |
f8cfc6aa | 1995 | else if (REG_P (src) |
15e35479 KH |
1996 | && reg_set_luid[regno] == reg_set_luid[REGNO (src)] |
1997 | && reg_base_reg[regno] == reg_base_reg[REGNO (src)] | |
1e047eed | 1998 | && move2add_valid_value_p (REGNO (src), mode)) |
15e35479 | 1999 | { |
f90af2e0 | 2000 | rtx_insn *next = next_nonnote_nondebug_insn (insn); |
15e35479 KH |
2001 | rtx set = NULL_RTX; |
2002 | if (next) | |
2003 | set = single_set (next); | |
2004 | if (set | |
2005 | && SET_DEST (set) == reg | |
2006 | && GET_CODE (SET_SRC (set)) == PLUS | |
2007 | && XEXP (SET_SRC (set), 0) == reg | |
481683e1 | 2008 | && CONST_INT_P (XEXP (SET_SRC (set), 1))) |
15e35479 KH |
2009 | { |
2010 | rtx src3 = XEXP (SET_SRC (set), 1); | |
e15eb172 | 2011 | unsigned HOST_WIDE_INT added_offset = UINTVAL (src3); |
15e35479 KH |
2012 | HOST_WIDE_INT base_offset = reg_offset[REGNO (src)]; |
2013 | HOST_WIDE_INT regno_offset = reg_offset[regno]; | |
2014 | rtx new_src = | |
bb80db7b KH |
2015 | gen_int_mode (added_offset |
2016 | + base_offset | |
2017 | - regno_offset, | |
1e047eed | 2018 | mode); |
f40751dd JH |
2019 | bool success = false; |
2020 | bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); | |
15e35479 KH |
2021 | |
2022 | if (new_src == const0_rtx) | |
2023 | /* See above why we create (set (reg) (reg)) here. */ | |
2024 | success | |
2025 | = validate_change (next, &SET_SRC (set), reg, 0); | |
22939744 | 2026 | else |
15e35479 | 2027 | { |
22939744 BS |
2028 | rtx old_src = SET_SRC (set); |
2029 | struct full_rtx_costs oldcst, newcst; | |
1e047eed | 2030 | rtx tem = gen_rtx_PLUS (mode, reg, new_src); |
22939744 | 2031 | |
d51102f3 | 2032 | get_full_set_rtx_cost (set, &oldcst); |
22939744 | 2033 | SET_SRC (set) = tem; |
1e047eed | 2034 | get_full_set_src_cost (tem, mode, &newcst); |
22939744 BS |
2035 | SET_SRC (set) = old_src; |
2036 | costs_add_n_insns (&oldcst, 1); | |
2037 | ||
2038 | if (costs_lt_p (&newcst, &oldcst, speed) | |
2039 | && have_add2_insn (reg, new_src)) | |
2040 | { | |
f7df4a84 | 2041 | rtx newpat = gen_rtx_SET (reg, tem); |
22939744 BS |
2042 | success |
2043 | = validate_change (next, &PATTERN (next), | |
2044 | newpat, 0); | |
2045 | } | |
15e35479 KH |
2046 | } |
2047 | if (success) | |
2048 | delete_insn (insn); | |
dc0d5a57 | 2049 | changed |= success; |
15e35479 | 2050 | insn = next; |
7894bc6b JR |
2051 | move2add_record_mode (reg); |
2052 | reg_offset[regno] | |
2053 | = trunc_int_for_mode (added_offset + base_offset, | |
1e047eed | 2054 | mode); |
15e35479 KH |
2055 | continue; |
2056 | } | |
2057 | } | |
2058 | } | |
7beb0596 JZ |
2059 | |
2060 | /* Try to transform | |
2061 | (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A)))) | |
2062 | ... | |
2063 | (set (REGY) (CONST (PLUS (SYMBOL_REF) (CONST_INT B)))) | |
2064 | to | |
2065 | (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A)))) | |
2066 | ... | |
2067 | (set (REGY) (CONST (PLUS (REGX) (CONST_INT B-A)))) */ | |
2068 | if ((GET_CODE (src) == SYMBOL_REF | |
2069 | || (GET_CODE (src) == CONST | |
2070 | && GET_CODE (XEXP (src, 0)) == PLUS | |
2071 | && GET_CODE (XEXP (XEXP (src, 0), 0)) == SYMBOL_REF | |
2072 | && CONST_INT_P (XEXP (XEXP (src, 0), 1)))) | |
2073 | && dbg_cnt (cse2_move2add)) | |
2074 | { | |
2075 | rtx sym, off; | |
2076 | ||
2077 | if (GET_CODE (src) == SYMBOL_REF) | |
2078 | { | |
2079 | sym = src; | |
2080 | off = const0_rtx; | |
2081 | } | |
2082 | else | |
2083 | { | |
2084 | sym = XEXP (XEXP (src, 0), 0); | |
2085 | off = XEXP (XEXP (src, 0), 1); | |
2086 | } | |
2087 | ||
2088 | /* If the reg already contains the value which is sum of | |
2089 | sym and some constant value, we can use an add2 insn. */ | |
1e047eed | 2090 | if (move2add_valid_value_p (regno, mode) |
7beb0596 JZ |
2091 | && reg_base_reg[regno] < 0 |
2092 | && reg_symbol_ref[regno] != NULL_RTX | |
2093 | && rtx_equal_p (sym, reg_symbol_ref[regno])) | |
1e047eed | 2094 | changed |= move2add_use_add2_insn (mode, reg, sym, off, insn); |
7beb0596 JZ |
2095 | |
2096 | /* Otherwise, we have to find a register whose value is sum | |
2097 | of sym and some constant value. */ | |
2098 | else | |
1e047eed | 2099 | changed |= move2add_use_add3_insn (mode, reg, sym, off, insn); |
7beb0596 JZ |
2100 | |
2101 | continue; | |
2102 | } | |
15e35479 KH |
2103 | } |
2104 | ||
2105 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
2106 | { | |
2107 | if (REG_NOTE_KIND (note) == REG_INC | |
f8cfc6aa | 2108 | && REG_P (XEXP (note, 0))) |
15e35479 KH |
2109 | { |
2110 | /* Reset the information about this register. */ | |
2111 | int regno = REGNO (XEXP (note, 0)); | |
2112 | if (regno < FIRST_PSEUDO_REGISTER) | |
7894bc6b JR |
2113 | { |
2114 | move2add_record_mode (XEXP (note, 0)); | |
2115 | reg_mode[regno] = VOIDmode; | |
2116 | } | |
15e35479 KH |
2117 | } |
2118 | } | |
70b55b25 JJ |
2119 | |
2120 | /* There are no REG_INC notes for SP autoinc. */ | |
2121 | subrtx_var_iterator::array_type array; | |
2122 | FOR_EACH_SUBRTX_VAR (iter, array, PATTERN (insn), NONCONST) | |
2123 | { | |
2124 | rtx mem = *iter; | |
2125 | if (mem | |
2126 | && MEM_P (mem) | |
2127 | && GET_RTX_CLASS (GET_CODE (XEXP (mem, 0))) == RTX_AUTOINC) | |
2128 | { | |
2129 | if (XEXP (XEXP (mem, 0), 0) == stack_pointer_rtx) | |
2130 | reg_mode[STACK_POINTER_REGNUM] = VOIDmode; | |
2131 | } | |
2132 | } | |
2133 | ||
e8448ba5 | 2134 | note_stores (insn, move2add_note_store, insn); |
15e35479 KH |
2135 | |
2136 | /* If INSN is a conditional branch, we try to extract an | |
2137 | implicit set out of it. */ | |
c4cdb8e1 | 2138 | if (any_condjump_p (insn)) |
15e35479 KH |
2139 | { |
2140 | rtx cnd = fis_get_condition (insn); | |
2141 | ||
2142 | if (cnd != NULL_RTX | |
2143 | && GET_CODE (cnd) == NE | |
f8cfc6aa | 2144 | && REG_P (XEXP (cnd, 0)) |
c4cdb8e1 | 2145 | && !reg_set_p (XEXP (cnd, 0), insn) |
15e35479 KH |
2146 | /* The following two checks, which are also in |
2147 | move2add_note_store, are intended to reduce the | |
2148 | number of calls to gen_rtx_SET to avoid memory | |
2149 | allocation if possible. */ | |
2150 | && SCALAR_INT_MODE_P (GET_MODE (XEXP (cnd, 0))) | |
dc8afb70 | 2151 | && REG_NREGS (XEXP (cnd, 0)) == 1 |
481683e1 | 2152 | && CONST_INT_P (XEXP (cnd, 1))) |
15e35479 KH |
2153 | { |
2154 | rtx implicit_set = | |
f7df4a84 | 2155 | gen_rtx_SET (XEXP (cnd, 0), XEXP (cnd, 1)); |
7beb0596 | 2156 | move2add_note_store (SET_DEST (implicit_set), implicit_set, insn); |
15e35479 KH |
2157 | } |
2158 | } | |
2159 | ||
2160 | /* If this is a CALL_INSN, all call used registers are stored with | |
2161 | unknown values. */ | |
4b4bf941 | 2162 | if (CALL_P (insn)) |
15e35479 | 2163 | { |
3df28f00 | 2164 | function_abi callee_abi = insn_callee_abi (insn); |
15e35479 | 2165 | for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--) |
3df28f00 RS |
2166 | if (reg_mode[i] != VOIDmode |
2167 | && reg_mode[i] != BLKmode | |
2168 | && callee_abi.clobbers_reg_p (reg_mode[i], i)) | |
2169 | /* Reset the information about this register. */ | |
2170 | reg_mode[i] = VOIDmode; | |
15e35479 KH |
2171 | } |
2172 | } | |
dc0d5a57 | 2173 | return changed; |
15e35479 KH |
2174 | } |
2175 | ||
7beb0596 JZ |
2176 | /* SET is a SET or CLOBBER that sets DST. DATA is the insn which |
2177 | contains SET. | |
15e35479 KH |
2178 | Update reg_set_luid, reg_offset and reg_base_reg accordingly. |
2179 | Called from reload_cse_move2add via note_stores. */ | |
2180 | ||
2181 | static void | |
7beb0596 | 2182 | move2add_note_store (rtx dst, const_rtx set, void *data) |
15e35479 | 2183 | { |
f90af2e0 | 2184 | rtx_insn *insn = (rtx_insn *) data; |
15e35479 | 2185 | unsigned int regno = 0; |
b0567726 | 2186 | scalar_int_mode mode; |
15e35479 | 2187 | |
7894bc6b JR |
2188 | if (GET_CODE (dst) == SUBREG) |
2189 | regno = subreg_regno (dst); | |
2190 | else if (REG_P (dst)) | |
2191 | regno = REGNO (dst); | |
2192 | else | |
2193 | return; | |
15e35479 | 2194 | |
b0567726 RS |
2195 | if (!is_a <scalar_int_mode> (GET_MODE (dst), &mode)) |
2196 | goto invalidate; | |
2197 | ||
2198 | if (GET_CODE (set) == SET) | |
7beb0596 JZ |
2199 | { |
2200 | rtx note, sym = NULL_RTX; | |
7894bc6b | 2201 | rtx off; |
7beb0596 JZ |
2202 | |
2203 | note = find_reg_equal_equiv_note (insn); | |
2204 | if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF) | |
2205 | { | |
2206 | sym = XEXP (note, 0); | |
7894bc6b | 2207 | off = const0_rtx; |
7beb0596 JZ |
2208 | } |
2209 | else if (note && GET_CODE (XEXP (note, 0)) == CONST | |
2210 | && GET_CODE (XEXP (XEXP (note, 0), 0)) == PLUS | |
2211 | && GET_CODE (XEXP (XEXP (XEXP (note, 0), 0), 0)) == SYMBOL_REF | |
2212 | && CONST_INT_P (XEXP (XEXP (XEXP (note, 0), 0), 1))) | |
2213 | { | |
2214 | sym = XEXP (XEXP (XEXP (note, 0), 0), 0); | |
7894bc6b | 2215 | off = XEXP (XEXP (XEXP (note, 0), 0), 1); |
7beb0596 JZ |
2216 | } |
2217 | ||
2218 | if (sym != NULL_RTX) | |
2219 | { | |
7894bc6b | 2220 | move2add_record_sym_value (dst, sym, off); |
7beb0596 JZ |
2221 | return; |
2222 | } | |
2223 | } | |
2224 | ||
b0567726 | 2225 | if (GET_CODE (set) == SET |
15e35479 | 2226 | && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT |
15e35479 KH |
2227 | && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART) |
2228 | { | |
2229 | rtx src = SET_SRC (set); | |
2230 | rtx base_reg; | |
e15eb172 | 2231 | unsigned HOST_WIDE_INT offset; |
15e35479 | 2232 | int base_regno; |
15e35479 KH |
2233 | |
2234 | switch (GET_CODE (src)) | |
2235 | { | |
2236 | case PLUS: | |
f8cfc6aa | 2237 | if (REG_P (XEXP (src, 0))) |
15e35479 KH |
2238 | { |
2239 | base_reg = XEXP (src, 0); | |
2240 | ||
481683e1 | 2241 | if (CONST_INT_P (XEXP (src, 1))) |
e15eb172 | 2242 | offset = UINTVAL (XEXP (src, 1)); |
f8cfc6aa | 2243 | else if (REG_P (XEXP (src, 1)) |
7894bc6b | 2244 | && move2add_valid_value_p (REGNO (XEXP (src, 1)), mode)) |
15e35479 | 2245 | { |
27d5e204 CLT |
2246 | if (reg_base_reg[REGNO (XEXP (src, 1))] < 0 |
2247 | && reg_symbol_ref[REGNO (XEXP (src, 1))] == NULL_RTX) | |
15e35479 KH |
2248 | offset = reg_offset[REGNO (XEXP (src, 1))]; |
2249 | /* Maybe the first register is known to be a | |
2250 | constant. */ | |
7894bc6b | 2251 | else if (move2add_valid_value_p (REGNO (base_reg), mode) |
27d5e204 CLT |
2252 | && reg_base_reg[REGNO (base_reg)] < 0 |
2253 | && reg_symbol_ref[REGNO (base_reg)] == NULL_RTX) | |
15e35479 KH |
2254 | { |
2255 | offset = reg_offset[REGNO (base_reg)]; | |
2256 | base_reg = XEXP (src, 1); | |
2257 | } | |
2258 | else | |
2259 | goto invalidate; | |
2260 | } | |
2261 | else | |
2262 | goto invalidate; | |
2263 | ||
2264 | break; | |
2265 | } | |
2266 | ||
2267 | goto invalidate; | |
2268 | ||
2269 | case REG: | |
2270 | base_reg = src; | |
2271 | offset = 0; | |
2272 | break; | |
2273 | ||
2274 | case CONST_INT: | |
2275 | /* Start tracking the register as a constant. */ | |
2276 | reg_base_reg[regno] = -1; | |
7beb0596 | 2277 | reg_symbol_ref[regno] = NULL_RTX; |
15e35479 KH |
2278 | reg_offset[regno] = INTVAL (SET_SRC (set)); |
2279 | /* We assign the same luid to all registers set to constants. */ | |
2280 | reg_set_luid[regno] = move2add_last_label_luid + 1; | |
7894bc6b | 2281 | move2add_record_mode (dst); |
15e35479 KH |
2282 | return; |
2283 | ||
2284 | default: | |
7894bc6b | 2285 | goto invalidate; |
15e35479 KH |
2286 | } |
2287 | ||
2288 | base_regno = REGNO (base_reg); | |
2289 | /* If information about the base register is not valid, set it | |
2290 | up as a new base register, pretending its value is known | |
2291 | starting from the current insn. */ | |
7894bc6b | 2292 | if (!move2add_valid_value_p (base_regno, mode)) |
15e35479 KH |
2293 | { |
2294 | reg_base_reg[base_regno] = base_regno; | |
7beb0596 | 2295 | reg_symbol_ref[base_regno] = NULL_RTX; |
15e35479 KH |
2296 | reg_offset[base_regno] = 0; |
2297 | reg_set_luid[base_regno] = move2add_luid; | |
7894bc6b JR |
2298 | gcc_assert (GET_MODE (base_reg) == mode); |
2299 | move2add_record_mode (base_reg); | |
15e35479 | 2300 | } |
15e35479 KH |
2301 | |
2302 | /* Copy base information from our base register. */ | |
2303 | reg_set_luid[regno] = reg_set_luid[base_regno]; | |
2304 | reg_base_reg[regno] = reg_base_reg[base_regno]; | |
7beb0596 | 2305 | reg_symbol_ref[regno] = reg_symbol_ref[base_regno]; |
15e35479 KH |
2306 | |
2307 | /* Compute the sum of the offsets or constants. */ | |
7894bc6b JR |
2308 | reg_offset[regno] |
2309 | = trunc_int_for_mode (offset + reg_offset[base_regno], mode); | |
2310 | ||
2311 | move2add_record_mode (dst); | |
15e35479 KH |
2312 | } |
2313 | else | |
2314 | { | |
7894bc6b JR |
2315 | invalidate: |
2316 | /* Invalidate the contents of the register. */ | |
2317 | move2add_record_mode (dst); | |
2318 | reg_mode[regno] = VOIDmode; | |
15e35479 KH |
2319 | } |
2320 | } | |
ef330312 | 2321 | \f |
27a4cd48 DM |
2322 | namespace { |
2323 | ||
2324 | const pass_data pass_data_postreload_cse = | |
ef330312 | 2325 | { |
27a4cd48 DM |
2326 | RTL_PASS, /* type */ |
2327 | "postreload", /* name */ | |
2328 | OPTGROUP_NONE, /* optinfo_flags */ | |
27a4cd48 DM |
2329 | TV_RELOAD_CSE_REGS, /* tv_id */ |
2330 | 0, /* properties_required */ | |
2331 | 0, /* properties_provided */ | |
2332 | 0, /* properties_destroyed */ | |
2333 | 0, /* todo_flags_start */ | |
3bea341f | 2334 | TODO_df_finish, /* todo_flags_finish */ |
ef330312 | 2335 | }; |
27a4cd48 DM |
2336 | |
2337 | class pass_postreload_cse : public rtl_opt_pass | |
2338 | { | |
2339 | public: | |
c3284718 RS |
2340 | pass_postreload_cse (gcc::context *ctxt) |
2341 | : rtl_opt_pass (pass_data_postreload_cse, ctxt) | |
27a4cd48 DM |
2342 | {} |
2343 | ||
2344 | /* opt_pass methods: */ | |
1a3d085c TS |
2345 | virtual bool gate (function *) { return (optimize > 0 && reload_completed); } |
2346 | ||
be55bfe6 | 2347 | virtual unsigned int execute (function *); |
27a4cd48 DM |
2348 | |
2349 | }; // class pass_postreload_cse | |
2350 | ||
be55bfe6 TS |
2351 | unsigned int |
2352 | pass_postreload_cse::execute (function *fun) | |
2353 | { | |
2354 | if (!dbg_cnt (postreload_cse)) | |
2355 | return 0; | |
2356 | ||
2357 | /* Do a very simple CSE pass over just the hard registers. */ | |
2358 | reload_cse_regs (get_insns ()); | |
2359 | /* Reload_cse_regs can eliminate potentially-trapping MEMs. | |
2360 | Remove any EH edges associated with them. */ | |
2361 | if (fun->can_throw_non_call_exceptions | |
2362 | && purge_all_dead_edges ()) | |
2363 | cleanup_cfg (0); | |
2364 | ||
2365 | return 0; | |
2366 | } | |
2367 | ||
27a4cd48 DM |
2368 | } // anon namespace |
2369 | ||
2370 | rtl_opt_pass * | |
2371 | make_pass_postreload_cse (gcc::context *ctxt) | |
2372 | { | |
2373 | return new pass_postreload_cse (ctxt); | |
2374 | } |