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15e35479 | 1 | /* Perform simple optimizations to clean up the result of reload. |
8d9254fc | 2 | Copyright (C) 1987-2020 Free Software Foundation, Inc. |
15e35479 KH |
3 | |
4 | This file is part of GCC. | |
5 | ||
6 | GCC is free software; you can redistribute it and/or modify it under | |
7 | the terms of the GNU General Public License as published by the Free | |
9dcd6f09 | 8 | Software Foundation; either version 3, or (at your option) any later |
15e35479 KH |
9 | version. |
10 | ||
11 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
12 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
14 | for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
9dcd6f09 NC |
17 | along with GCC; see the file COPYING3. If not see |
18 | <http://www.gnu.org/licenses/>. */ | |
15e35479 KH |
19 | |
20 | #include "config.h" | |
21 | #include "system.h" | |
22 | #include "coretypes.h" | |
c7131fb2 | 23 | #include "backend.h" |
957060b5 | 24 | #include "target.h" |
15e35479 | 25 | #include "rtl.h" |
957060b5 AM |
26 | #include "tree.h" |
27 | #include "predict.h" | |
c7131fb2 | 28 | #include "df.h" |
4d0cdd0c | 29 | #include "memmodel.h" |
15e35479 | 30 | #include "tm_p.h" |
957060b5 AM |
31 | #include "optabs.h" |
32 | #include "regs.h" | |
33 | #include "emit-rtl.h" | |
34 | #include "recog.h" | |
957060b5 | 35 | |
60393bbc AM |
36 | #include "cfgrtl.h" |
37 | #include "cfgbuild.h" | |
38 | #include "cfgcleanup.h" | |
15e35479 | 39 | #include "reload.h" |
15e35479 | 40 | #include "cselib.h" |
ef330312 | 41 | #include "tree-pass.h" |
6fb5fa3c | 42 | #include "dbgcnt.h" |
5a5a3bc5 | 43 | #include "function-abi.h" |
70b55b25 | 44 | #include "rtl-iter.h" |
15e35479 | 45 | |
0c20a65f | 46 | static int reload_cse_noop_set_p (rtx); |
f90af2e0 | 47 | static bool reload_cse_simplify (rtx_insn *, rtx); |
3a15c2cf | 48 | static void reload_cse_regs_1 (void); |
f90af2e0 DM |
49 | static int reload_cse_simplify_set (rtx, rtx_insn *); |
50 | static int reload_cse_simplify_operands (rtx_insn *, rtx); | |
15e35479 | 51 | |
0c20a65f | 52 | static void reload_combine (void); |
f90af2e0 | 53 | static void reload_combine_note_use (rtx *, rtx_insn *, int, rtx); |
7bc980e1 | 54 | static void reload_combine_note_store (rtx, const_rtx, void *); |
15e35479 | 55 | |
f90af2e0 | 56 | static bool reload_cse_move2add (rtx_insn *); |
7bc980e1 | 57 | static void move2add_note_store (rtx, const_rtx, void *); |
15e35479 KH |
58 | |
59 | /* Call cse / combine like post-reload optimization phases. | |
60 | FIRST is the first instruction. */ | |
8bb91f49 SB |
61 | |
62 | static void | |
f90af2e0 | 63 | reload_cse_regs (rtx_insn *first ATTRIBUTE_UNUSED) |
15e35479 | 64 | { |
dc0d5a57 | 65 | bool moves_converted; |
3a15c2cf | 66 | reload_cse_regs_1 (); |
15e35479 | 67 | reload_combine (); |
dc0d5a57 | 68 | moves_converted = reload_cse_move2add (first); |
15e35479 | 69 | if (flag_expensive_optimizations) |
dc0d5a57 BS |
70 | { |
71 | if (moves_converted) | |
72 | reload_combine (); | |
3a15c2cf | 73 | reload_cse_regs_1 (); |
dc0d5a57 | 74 | } |
15e35479 KH |
75 | } |
76 | ||
77 | /* See whether a single set SET is a noop. */ | |
78 | static int | |
0c20a65f | 79 | reload_cse_noop_set_p (rtx set) |
15e35479 KH |
80 | { |
81 | if (cselib_reg_set_mode (SET_DEST (set)) != GET_MODE (SET_DEST (set))) | |
82 | return 0; | |
83 | ||
84 | return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set)); | |
85 | } | |
86 | ||
3a15c2cf SB |
87 | /* Try to simplify INSN. Return true if the CFG may have changed. */ |
88 | static bool | |
f90af2e0 | 89 | reload_cse_simplify (rtx_insn *insn, rtx testreg) |
15e35479 KH |
90 | { |
91 | rtx body = PATTERN (insn); | |
3a15c2cf SB |
92 | basic_block insn_bb = BLOCK_FOR_INSN (insn); |
93 | unsigned insn_bb_succs = EDGE_COUNT (insn_bb->succs); | |
15e35479 | 94 | |
d5a752eb AV |
95 | /* If NO_FUNCTION_CSE has been set by the target, then we should not try |
96 | to cse function calls. */ | |
97 | if (NO_FUNCTION_CSE && CALL_P (insn)) | |
98 | return false; | |
99 | ||
d44f14cc JJ |
100 | /* Remember if this insn has been sp += const_int. */ |
101 | rtx sp_set = set_for_reg_notes (insn); | |
102 | rtx sp_addend = NULL_RTX; | |
103 | if (sp_set | |
104 | && SET_DEST (sp_set) == stack_pointer_rtx | |
105 | && GET_CODE (SET_SRC (sp_set)) == PLUS | |
106 | && XEXP (SET_SRC (sp_set), 0) == stack_pointer_rtx | |
107 | && CONST_INT_P (XEXP (SET_SRC (sp_set), 1))) | |
108 | sp_addend = XEXP (SET_SRC (sp_set), 1); | |
109 | ||
15e35479 KH |
110 | if (GET_CODE (body) == SET) |
111 | { | |
112 | int count = 0; | |
113 | ||
114 | /* Simplify even if we may think it is a no-op. | |
115 | We may think a memory load of a value smaller than WORD_SIZE | |
116 | is redundant because we haven't taken into account possible | |
117 | implicit extension. reload_cse_simplify_set() will bring | |
118 | this out, so it's safer to simplify before we delete. */ | |
119 | count += reload_cse_simplify_set (body, insn); | |
120 | ||
121 | if (!count && reload_cse_noop_set_p (body)) | |
122 | { | |
9e582b1d JR |
123 | if (check_for_inc_dec (insn)) |
124 | delete_insn_and_edges (insn); | |
3a15c2cf SB |
125 | /* We're done with this insn. */ |
126 | goto done; | |
15e35479 KH |
127 | } |
128 | ||
129 | if (count > 0) | |
130 | apply_change_group (); | |
131 | else | |
132 | reload_cse_simplify_operands (insn, testreg); | |
133 | } | |
134 | else if (GET_CODE (body) == PARALLEL) | |
135 | { | |
136 | int i; | |
137 | int count = 0; | |
138 | rtx value = NULL_RTX; | |
139 | ||
0d87c765 RH |
140 | /* Registers mentioned in the clobber list for an asm cannot be reused |
141 | within the body of the asm. Invalidate those registers now so that | |
142 | we don't try to substitute values for them. */ | |
143 | if (asm_noperands (body) >= 0) | |
144 | { | |
145 | for (i = XVECLEN (body, 0) - 1; i >= 0; --i) | |
146 | { | |
147 | rtx part = XVECEXP (body, 0, i); | |
148 | if (GET_CODE (part) == CLOBBER && REG_P (XEXP (part, 0))) | |
149 | cselib_invalidate_rtx (XEXP (part, 0)); | |
150 | } | |
151 | } | |
152 | ||
15e35479 KH |
153 | /* If every action in a PARALLEL is a noop, we can delete |
154 | the entire PARALLEL. */ | |
155 | for (i = XVECLEN (body, 0) - 1; i >= 0; --i) | |
156 | { | |
157 | rtx part = XVECEXP (body, 0, i); | |
158 | if (GET_CODE (part) == SET) | |
159 | { | |
160 | if (! reload_cse_noop_set_p (part)) | |
161 | break; | |
162 | if (REG_P (SET_DEST (part)) | |
163 | && REG_FUNCTION_VALUE_P (SET_DEST (part))) | |
164 | { | |
165 | if (value) | |
166 | break; | |
167 | value = SET_DEST (part); | |
168 | } | |
169 | } | |
17d184e5 | 170 | else if (GET_CODE (part) != CLOBBER && GET_CODE (part) != USE) |
15e35479 KH |
171 | break; |
172 | } | |
173 | ||
174 | if (i < 0) | |
175 | { | |
9e582b1d JR |
176 | if (check_for_inc_dec (insn)) |
177 | delete_insn_and_edges (insn); | |
15e35479 | 178 | /* We're done with this insn. */ |
3a15c2cf | 179 | goto done; |
15e35479 KH |
180 | } |
181 | ||
182 | /* It's not a no-op, but we can try to simplify it. */ | |
183 | for (i = XVECLEN (body, 0) - 1; i >= 0; --i) | |
184 | if (GET_CODE (XVECEXP (body, 0, i)) == SET) | |
185 | count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn); | |
186 | ||
187 | if (count > 0) | |
188 | apply_change_group (); | |
189 | else | |
190 | reload_cse_simplify_operands (insn, testreg); | |
191 | } | |
3a15c2cf | 192 | |
d44f14cc JJ |
193 | /* If sp += const_int insn is changed into sp = reg;, add REG_EQUAL |
194 | note so that the stack_adjustments pass can undo it if beneficial. */ | |
195 | if (sp_addend | |
196 | && SET_DEST (sp_set) == stack_pointer_rtx | |
197 | && REG_P (SET_SRC (sp_set))) | |
198 | set_dst_reg_note (insn, REG_EQUAL, | |
199 | gen_rtx_PLUS (Pmode, stack_pointer_rtx, | |
200 | sp_addend), stack_pointer_rtx); | |
201 | ||
3a15c2cf SB |
202 | done: |
203 | return (EDGE_COUNT (insn_bb->succs) != insn_bb_succs); | |
15e35479 KH |
204 | } |
205 | ||
206 | /* Do a very simple CSE pass over the hard registers. | |
207 | ||
208 | This function detects no-op moves where we happened to assign two | |
209 | different pseudo-registers to the same hard register, and then | |
210 | copied one to the other. Reload will generate a useless | |
211 | instruction copying a register to itself. | |
212 | ||
213 | This function also detects cases where we load a value from memory | |
214 | into two different registers, and (if memory is more expensive than | |
215 | registers) changes it to simply copy the first register into the | |
216 | second register. | |
217 | ||
218 | Another optimization is performed that scans the operands of each | |
219 | instruction to see whether the value is already available in a | |
220 | hard register. It then replaces the operand with the hard register | |
221 | if possible, much like an optional reload would. */ | |
222 | ||
223 | static void | |
3a15c2cf | 224 | reload_cse_regs_1 (void) |
15e35479 | 225 | { |
3a15c2cf SB |
226 | bool cfg_changed = false; |
227 | basic_block bb; | |
f90af2e0 | 228 | rtx_insn *insn; |
c3dc5e66 | 229 | rtx testreg = gen_rtx_REG (word_mode, LAST_VIRTUAL_REGISTER + 1); |
15e35479 | 230 | |
457eeaae | 231 | cselib_init (CSELIB_RECORD_MEMORY); |
15e35479 KH |
232 | init_alias_analysis (); |
233 | ||
11cd3bed | 234 | FOR_EACH_BB_FN (bb, cfun) |
3a15c2cf SB |
235 | FOR_BB_INSNS (bb, insn) |
236 | { | |
237 | if (INSN_P (insn)) | |
238 | cfg_changed |= reload_cse_simplify (insn, testreg); | |
15e35479 | 239 | |
3a15c2cf SB |
240 | cselib_process_insn (insn); |
241 | } | |
15e35479 KH |
242 | |
243 | /* Clean up. */ | |
244 | end_alias_analysis (); | |
245 | cselib_finish (); | |
3a15c2cf SB |
246 | if (cfg_changed) |
247 | cleanup_cfg (0); | |
15e35479 KH |
248 | } |
249 | ||
250 | /* Try to simplify a single SET instruction. SET is the set pattern. | |
251 | INSN is the instruction it came from. | |
252 | This function only handles one case: if we set a register to a value | |
253 | which is not a register, we try to find that value in some other register | |
254 | and change the set into a register copy. */ | |
255 | ||
256 | static int | |
f90af2e0 | 257 | reload_cse_simplify_set (rtx set, rtx_insn *insn) |
15e35479 KH |
258 | { |
259 | int did_change = 0; | |
260 | int dreg; | |
261 | rtx src; | |
6f76a878 | 262 | reg_class_t dclass; |
15e35479 KH |
263 | int old_cost; |
264 | cselib_val *val; | |
265 | struct elt_loc_list *l; | |
f822d252 | 266 | enum rtx_code extend_op = UNKNOWN; |
f40751dd | 267 | bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); |
15e35479 KH |
268 | |
269 | dreg = true_regnum (SET_DEST (set)); | |
270 | if (dreg < 0) | |
271 | return 0; | |
272 | ||
273 | src = SET_SRC (set); | |
274 | if (side_effects_p (src) || true_regnum (src) >= 0) | |
275 | return 0; | |
276 | ||
277 | dclass = REGNO_REG_CLASS (dreg); | |
278 | ||
15e35479 KH |
279 | /* When replacing a memory with a register, we need to honor assumptions |
280 | that combine made wrt the contents of sign bits. We'll do this by | |
281 | generating an extend instruction instead of a reg->reg copy. Thus | |
282 | the destination must be a register that we can widen. */ | |
3c0cb5de | 283 | if (MEM_P (src) |
3712c7a3 | 284 | && (extend_op = load_extend_op (GET_MODE (src))) != UNKNOWN |
f8cfc6aa | 285 | && !REG_P (SET_DEST (set))) |
15e35479 | 286 | return 0; |
15e35479 | 287 | |
4deef538 | 288 | val = cselib_lookup (src, GET_MODE (SET_DEST (set)), 0, VOIDmode); |
b2948a2c KH |
289 | if (! val) |
290 | return 0; | |
291 | ||
15e35479 | 292 | /* If memory loads are cheaper than register copies, don't change them. */ |
3c0cb5de | 293 | if (MEM_P (src)) |
f5c21ef3 | 294 | old_cost = memory_move_cost (GET_MODE (src), dclass, true); |
f8cfc6aa | 295 | else if (REG_P (src)) |
de8f4b07 | 296 | old_cost = register_move_cost (GET_MODE (src), |
15e35479 KH |
297 | REGNO_REG_CLASS (REGNO (src)), dclass); |
298 | else | |
e548c9df | 299 | old_cost = set_src_cost (src, GET_MODE (SET_DEST (set)), speed); |
15e35479 | 300 | |
15e35479 KH |
301 | for (l = val->locs; l; l = l->next) |
302 | { | |
303 | rtx this_rtx = l->loc; | |
304 | int this_cost; | |
305 | ||
306 | if (CONSTANT_P (this_rtx) && ! references_value_p (this_rtx, 0)) | |
307 | { | |
f822d252 | 308 | if (extend_op != UNKNOWN) |
15e35479 | 309 | { |
807e902e | 310 | wide_int result; |
15e35479 | 311 | |
807e902e | 312 | if (!CONST_SCALAR_INT_P (this_rtx)) |
15e35479 KH |
313 | continue; |
314 | ||
15e35479 KH |
315 | switch (extend_op) |
316 | { | |
317 | case ZERO_EXTEND: | |
f079167a RS |
318 | result = wide_int::from (rtx_mode_t (this_rtx, |
319 | GET_MODE (src)), | |
807e902e | 320 | BITS_PER_WORD, UNSIGNED); |
15e35479 KH |
321 | break; |
322 | case SIGN_EXTEND: | |
f079167a RS |
323 | result = wide_int::from (rtx_mode_t (this_rtx, |
324 | GET_MODE (src)), | |
807e902e KZ |
325 | BITS_PER_WORD, SIGNED); |
326 | break; | |
15e35479 | 327 | default: |
e16acfcd | 328 | gcc_unreachable (); |
15e35479 | 329 | } |
807e902e | 330 | this_rtx = immed_wide_int_const (result, word_mode); |
15e35479 | 331 | } |
f1657f05 | 332 | |
e548c9df | 333 | this_cost = set_src_cost (this_rtx, GET_MODE (SET_DEST (set)), speed); |
15e35479 | 334 | } |
f8cfc6aa | 335 | else if (REG_P (this_rtx)) |
15e35479 | 336 | { |
f822d252 | 337 | if (extend_op != UNKNOWN) |
15e35479 KH |
338 | { |
339 | this_rtx = gen_rtx_fmt_e (extend_op, word_mode, this_rtx); | |
e548c9df | 340 | this_cost = set_src_cost (this_rtx, word_mode, speed); |
15e35479 KH |
341 | } |
342 | else | |
de8f4b07 | 343 | this_cost = register_move_cost (GET_MODE (this_rtx), |
15e35479 KH |
344 | REGNO_REG_CLASS (REGNO (this_rtx)), |
345 | dclass); | |
346 | } | |
347 | else | |
348 | continue; | |
349 | ||
350 | /* If equal costs, prefer registers over anything else. That | |
351 | tends to lead to smaller instructions on some machines. */ | |
352 | if (this_cost < old_cost | |
353 | || (this_cost == old_cost | |
f8cfc6aa JQ |
354 | && REG_P (this_rtx) |
355 | && !REG_P (SET_SRC (set)))) | |
15e35479 | 356 | { |
3712c7a3 | 357 | if (extend_op != UNKNOWN |
0d803030 RS |
358 | && REG_CAN_CHANGE_MODE_P (REGNO (SET_DEST (set)), |
359 | GET_MODE (SET_DEST (set)), word_mode)) | |
15e35479 KH |
360 | { |
361 | rtx wide_dest = gen_rtx_REG (word_mode, REGNO (SET_DEST (set))); | |
362 | ORIGINAL_REGNO (wide_dest) = ORIGINAL_REGNO (SET_DEST (set)); | |
363 | validate_change (insn, &SET_DEST (set), wide_dest, 1); | |
364 | } | |
15e35479 | 365 | |
95e88efd | 366 | validate_unshare_change (insn, &SET_SRC (set), this_rtx, 1); |
15e35479 KH |
367 | old_cost = this_cost, did_change = 1; |
368 | } | |
369 | } | |
370 | ||
371 | return did_change; | |
372 | } | |
373 | ||
374 | /* Try to replace operands in INSN with equivalent values that are already | |
375 | in registers. This can be viewed as optional reloading. | |
376 | ||
377 | For each non-register operand in the insn, see if any hard regs are | |
378 | known to be equivalent to that operand. Record the alternatives which | |
379 | can accept these hard registers. Among all alternatives, select the | |
380 | ones which are better or equal to the one currently matching, where | |
381 | "better" is in terms of '?' and '!' constraints. Among the remaining | |
382 | alternatives, select the one which replaces most operands with | |
383 | hard registers. */ | |
384 | ||
385 | static int | |
f90af2e0 | 386 | reload_cse_simplify_operands (rtx_insn *insn, rtx testreg) |
15e35479 KH |
387 | { |
388 | int i, j; | |
389 | ||
390 | /* For each operand, all registers that are equivalent to it. */ | |
391 | HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS]; | |
392 | ||
393 | const char *constraints[MAX_RECOG_OPERANDS]; | |
394 | ||
395 | /* Vector recording how bad an alternative is. */ | |
396 | int *alternative_reject; | |
397 | /* Vector recording how many registers can be introduced by choosing | |
398 | this alternative. */ | |
399 | int *alternative_nregs; | |
400 | /* Array of vectors recording, for each operand and each alternative, | |
401 | which hard register to substitute, or -1 if the operand should be | |
402 | left as it is. */ | |
403 | int *op_alt_regno[MAX_RECOG_OPERANDS]; | |
404 | /* Array of alternatives, sorted in order of decreasing desirability. */ | |
405 | int *alternative_order; | |
406 | ||
75d25a02 | 407 | extract_constrain_insn (insn); |
15e35479 KH |
408 | |
409 | if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0) | |
410 | return 0; | |
411 | ||
d3bfe4de KG |
412 | alternative_reject = XALLOCAVEC (int, recog_data.n_alternatives); |
413 | alternative_nregs = XALLOCAVEC (int, recog_data.n_alternatives); | |
414 | alternative_order = XALLOCAVEC (int, recog_data.n_alternatives); | |
703ad42b KG |
415 | memset (alternative_reject, 0, recog_data.n_alternatives * sizeof (int)); |
416 | memset (alternative_nregs, 0, recog_data.n_alternatives * sizeof (int)); | |
15e35479 KH |
417 | |
418 | /* For each operand, find out which regs are equivalent. */ | |
419 | for (i = 0; i < recog_data.n_operands; i++) | |
420 | { | |
421 | cselib_val *v; | |
422 | struct elt_loc_list *l; | |
115df136 | 423 | rtx op; |
15e35479 KH |
424 | |
425 | CLEAR_HARD_REG_SET (equiv_regs[i]); | |
426 | ||
427 | /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem | |
854dde43 JJ |
428 | right, so avoid the problem here. Similarly NOTE_INSN_DELETED_LABEL. |
429 | Likewise if we have a constant and the insn pattern doesn't tell us | |
430 | the mode we need. */ | |
4b4bf941 | 431 | if (LABEL_P (recog_data.operand[i]) |
854dde43 JJ |
432 | || (NOTE_P (recog_data.operand[i]) |
433 | && NOTE_KIND (recog_data.operand[i]) == NOTE_INSN_DELETED_LABEL) | |
15e35479 KH |
434 | || (CONSTANT_P (recog_data.operand[i]) |
435 | && recog_data.operand_mode[i] == VOIDmode)) | |
436 | continue; | |
437 | ||
115df136 | 438 | op = recog_data.operand[i]; |
3712c7a3 | 439 | if (MEM_P (op) && load_extend_op (GET_MODE (op)) != UNKNOWN) |
115df136 R |
440 | { |
441 | rtx set = single_set (insn); | |
442 | ||
1f52178b | 443 | /* We might have multiple sets, some of which do implicit |
115df136 R |
444 | extension. Punt on this for now. */ |
445 | if (! set) | |
446 | continue; | |
1f838355 | 447 | /* If the destination is also a MEM or a STRICT_LOW_PART, no |
115df136 R |
448 | extension applies. |
449 | Also, if there is an explicit extension, we don't have to | |
450 | worry about an implicit one. */ | |
3c0cb5de | 451 | else if (MEM_P (SET_DEST (set)) |
115df136 R |
452 | || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART |
453 | || GET_CODE (SET_SRC (set)) == ZERO_EXTEND | |
454 | || GET_CODE (SET_SRC (set)) == SIGN_EXTEND) | |
455 | ; /* Continue ordinary processing. */ | |
7be4d808 R |
456 | /* If the register cannot change mode to word_mode, it follows that |
457 | it cannot have been used in word_mode. */ | |
f8cfc6aa | 458 | else if (REG_P (SET_DEST (set)) |
0d803030 RS |
459 | && !REG_CAN_CHANGE_MODE_P (REGNO (SET_DEST (set)), |
460 | GET_MODE (SET_DEST (set)), | |
461 | word_mode)) | |
7be4d808 | 462 | ; /* Continue ordinary processing. */ |
115df136 | 463 | /* If this is a straight load, make the extension explicit. */ |
f8cfc6aa | 464 | else if (REG_P (SET_DEST (set)) |
115df136 R |
465 | && recog_data.n_operands == 2 |
466 | && SET_SRC (set) == op | |
467 | && SET_DEST (set) == recog_data.operand[1-i]) | |
468 | { | |
469 | validate_change (insn, recog_data.operand_loc[i], | |
3712c7a3 | 470 | gen_rtx_fmt_e (load_extend_op (GET_MODE (op)), |
115df136 R |
471 | word_mode, op), |
472 | 1); | |
473 | validate_change (insn, recog_data.operand_loc[1-i], | |
474 | gen_rtx_REG (word_mode, REGNO (SET_DEST (set))), | |
475 | 1); | |
476 | if (! apply_change_group ()) | |
477 | return 0; | |
478 | return reload_cse_simplify_operands (insn, testreg); | |
479 | } | |
480 | else | |
481 | /* ??? There might be arithmetic operations with memory that are | |
482 | safe to optimize, but is it worth the trouble? */ | |
483 | continue; | |
484 | } | |
f1657f05 | 485 | |
3f82421f PH |
486 | if (side_effects_p (op)) |
487 | continue; | |
4deef538 | 488 | v = cselib_lookup (op, recog_data.operand_mode[i], 0, VOIDmode); |
15e35479 KH |
489 | if (! v) |
490 | continue; | |
491 | ||
492 | for (l = v->locs; l; l = l->next) | |
f8cfc6aa | 493 | if (REG_P (l->loc)) |
15e35479 KH |
494 | SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc)); |
495 | } | |
496 | ||
9840b2fa | 497 | alternative_mask preferred = get_preferred_alternatives (insn); |
15e35479 KH |
498 | for (i = 0; i < recog_data.n_operands; i++) |
499 | { | |
ef4bddc2 | 500 | machine_mode mode; |
15e35479 KH |
501 | int regno; |
502 | const char *p; | |
503 | ||
d3bfe4de | 504 | op_alt_regno[i] = XALLOCAVEC (int, recog_data.n_alternatives); |
15e35479 KH |
505 | for (j = 0; j < recog_data.n_alternatives; j++) |
506 | op_alt_regno[i][j] = -1; | |
507 | ||
508 | p = constraints[i] = recog_data.constraints[i]; | |
509 | mode = recog_data.operand_mode[i]; | |
510 | ||
511 | /* Add the reject values for each alternative given by the constraints | |
512 | for this operand. */ | |
513 | j = 0; | |
514 | while (*p != '\0') | |
515 | { | |
516 | char c = *p++; | |
517 | if (c == ',') | |
518 | j++; | |
519 | else if (c == '?') | |
520 | alternative_reject[j] += 3; | |
521 | else if (c == '!') | |
522 | alternative_reject[j] += 300; | |
523 | } | |
524 | ||
525 | /* We won't change operands which are already registers. We | |
526 | also don't want to modify output operands. */ | |
527 | regno = true_regnum (recog_data.operand[i]); | |
528 | if (regno >= 0 | |
529 | || constraints[i][0] == '=' | |
530 | || constraints[i][0] == '+') | |
531 | continue; | |
532 | ||
533 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
534 | { | |
bbbbb16a | 535 | enum reg_class rclass = NO_REGS; |
15e35479 KH |
536 | |
537 | if (! TEST_HARD_REG_BIT (equiv_regs[i], regno)) | |
538 | continue; | |
539 | ||
8deccbb7 | 540 | set_mode_and_regno (testreg, mode, regno); |
15e35479 KH |
541 | |
542 | /* We found a register equal to this operand. Now look for all | |
543 | alternatives that can accept this register and have not been | |
544 | assigned a register they can use yet. */ | |
545 | j = 0; | |
546 | p = constraints[i]; | |
547 | for (;;) | |
548 | { | |
549 | char c = *p; | |
550 | ||
551 | switch (c) | |
552 | { | |
8677664e RS |
553 | case 'g': |
554 | rclass = reg_class_subunion[rclass][GENERAL_REGS]; | |
15e35479 KH |
555 | break; |
556 | ||
557 | default: | |
d858f359 | 558 | rclass |
15e35479 | 559 | = (reg_class_subunion |
777e635f RS |
560 | [rclass] |
561 | [reg_class_for_constraint (lookup_constraint (p))]); | |
15e35479 KH |
562 | break; |
563 | ||
564 | case ',': case '\0': | |
565 | /* See if REGNO fits this alternative, and set it up as the | |
566 | replacement register if we don't have one for this | |
567 | alternative yet and the operand being replaced is not | |
568 | a cheap CONST_INT. */ | |
569 | if (op_alt_regno[i][j] == -1 | |
9840b2fa | 570 | && TEST_BIT (preferred, j) |
d858f359 | 571 | && reg_fits_class_p (testreg, rclass, 0, mode) |
481683e1 | 572 | && (!CONST_INT_P (recog_data.operand[i]) |
e548c9df | 573 | || (set_src_cost (recog_data.operand[i], mode, |
5e8f01f4 RS |
574 | optimize_bb_for_speed_p |
575 | (BLOCK_FOR_INSN (insn))) | |
e548c9df | 576 | > set_src_cost (testreg, mode, |
5e8f01f4 RS |
577 | optimize_bb_for_speed_p |
578 | (BLOCK_FOR_INSN (insn)))))) | |
15e35479 KH |
579 | { |
580 | alternative_nregs[j]++; | |
581 | op_alt_regno[i][j] = regno; | |
582 | } | |
583 | j++; | |
bbbbb16a | 584 | rclass = NO_REGS; |
15e35479 KH |
585 | break; |
586 | } | |
587 | p += CONSTRAINT_LEN (c, p); | |
588 | ||
589 | if (c == '\0') | |
590 | break; | |
591 | } | |
592 | } | |
593 | } | |
594 | ||
595 | /* Record all alternatives which are better or equal to the currently | |
596 | matching one in the alternative_order array. */ | |
597 | for (i = j = 0; i < recog_data.n_alternatives; i++) | |
598 | if (alternative_reject[i] <= alternative_reject[which_alternative]) | |
599 | alternative_order[j++] = i; | |
600 | recog_data.n_alternatives = j; | |
601 | ||
602 | /* Sort it. Given a small number of alternatives, a dumb algorithm | |
603 | won't hurt too much. */ | |
604 | for (i = 0; i < recog_data.n_alternatives - 1; i++) | |
605 | { | |
606 | int best = i; | |
607 | int best_reject = alternative_reject[alternative_order[i]]; | |
608 | int best_nregs = alternative_nregs[alternative_order[i]]; | |
15e35479 KH |
609 | |
610 | for (j = i + 1; j < recog_data.n_alternatives; j++) | |
611 | { | |
612 | int this_reject = alternative_reject[alternative_order[j]]; | |
613 | int this_nregs = alternative_nregs[alternative_order[j]]; | |
614 | ||
615 | if (this_reject < best_reject | |
8a4c09c8 | 616 | || (this_reject == best_reject && this_nregs > best_nregs)) |
15e35479 KH |
617 | { |
618 | best = j; | |
619 | best_reject = this_reject; | |
620 | best_nregs = this_nregs; | |
621 | } | |
622 | } | |
623 | ||
fab27f52 | 624 | std::swap (alternative_order[best], alternative_order[i]); |
15e35479 KH |
625 | } |
626 | ||
627 | /* Substitute the operands as determined by op_alt_regno for the best | |
628 | alternative. */ | |
629 | j = alternative_order[0]; | |
630 | ||
631 | for (i = 0; i < recog_data.n_operands; i++) | |
632 | { | |
ef4bddc2 | 633 | machine_mode mode = recog_data.operand_mode[i]; |
15e35479 KH |
634 | if (op_alt_regno[i][j] == -1) |
635 | continue; | |
636 | ||
637 | validate_change (insn, recog_data.operand_loc[i], | |
638 | gen_rtx_REG (mode, op_alt_regno[i][j]), 1); | |
639 | } | |
640 | ||
641 | for (i = recog_data.n_dups - 1; i >= 0; i--) | |
642 | { | |
643 | int op = recog_data.dup_num[i]; | |
ef4bddc2 | 644 | machine_mode mode = recog_data.operand_mode[op]; |
15e35479 KH |
645 | |
646 | if (op_alt_regno[op][j] == -1) | |
647 | continue; | |
648 | ||
649 | validate_change (insn, recog_data.dup_loc[i], | |
650 | gen_rtx_REG (mode, op_alt_regno[op][j]), 1); | |
651 | } | |
652 | ||
653 | return apply_change_group (); | |
654 | } | |
655 | \f | |
656 | /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg | |
657 | addressing now. | |
658 | This code might also be useful when reload gave up on reg+reg addressing | |
659 | because of clashes between the return register and INDEX_REG_CLASS. */ | |
660 | ||
661 | /* The maximum number of uses of a register we can keep track of to | |
662 | replace them with reg+reg addressing. */ | |
dc0d5a57 | 663 | #define RELOAD_COMBINE_MAX_USES 16 |
15e35479 | 664 | |
dc0d5a57 BS |
665 | /* Describes a recorded use of a register. */ |
666 | struct reg_use | |
667 | { | |
668 | /* The insn where a register has been used. */ | |
f90af2e0 | 669 | rtx_insn *insn; |
dc0d5a57 BS |
670 | /* Points to the memory reference enclosing the use, if any, NULL_RTX |
671 | otherwise. */ | |
672 | rtx containing_mem; | |
073a8998 | 673 | /* Location of the register within INSN. */ |
dc0d5a57 BS |
674 | rtx *usep; |
675 | /* The reverse uid of the insn. */ | |
676 | int ruid; | |
677 | }; | |
15e35479 KH |
678 | |
679 | /* If the register is used in some unknown fashion, USE_INDEX is negative. | |
680 | If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID | |
dc0d5a57 | 681 | indicates where it is first set or clobbered. |
15e35479 | 682 | Otherwise, USE_INDEX is the index of the last encountered use of the |
dc0d5a57 BS |
683 | register (which is first among these we have seen since we scan backwards). |
684 | USE_RUID indicates the first encountered, i.e. last, of these uses. | |
685 | If ALL_OFFSETS_MATCH is true, all encountered uses were inside a PLUS | |
686 | with a constant offset; OFFSET contains this constant in that case. | |
15e35479 KH |
687 | STORE_RUID is always meaningful if we only want to use a value in a |
688 | register in a different place: it denotes the next insn in the insn | |
dc0d5a57 | 689 | stream (i.e. the last encountered) that sets or clobbers the register. |
8df47bdf AH |
690 | REAL_STORE_RUID is similar, but clobbers are ignored when updating it. |
691 | EXPR is the expression used when storing the register. */ | |
15e35479 KH |
692 | static struct |
693 | { | |
694 | struct reg_use reg_use[RELOAD_COMBINE_MAX_USES]; | |
15e35479 | 695 | rtx offset; |
dc0d5a57 | 696 | int use_index; |
15e35479 | 697 | int store_ruid; |
dc0d5a57 | 698 | int real_store_ruid; |
15e35479 | 699 | int use_ruid; |
dc0d5a57 | 700 | bool all_offsets_match; |
8df47bdf | 701 | rtx expr; |
15e35479 KH |
702 | } reg_state[FIRST_PSEUDO_REGISTER]; |
703 | ||
704 | /* Reverse linear uid. This is increased in reload_combine while scanning | |
705 | the instructions from last to first. It is used to set last_label_ruid | |
706 | and the store_ruid / use_ruid fields in reg_state. */ | |
707 | static int reload_combine_ruid; | |
708 | ||
67bb0206 BS |
709 | /* The RUID of the last label we encountered in reload_combine. */ |
710 | static int last_label_ruid; | |
711 | ||
dc0d5a57 BS |
712 | /* The RUID of the last jump we encountered in reload_combine. */ |
713 | static int last_jump_ruid; | |
714 | ||
67bb0206 BS |
715 | /* The register numbers of the first and last index register. A value of |
716 | -1 in LAST_INDEX_REG indicates that we've previously computed these | |
717 | values and found no suitable index registers. */ | |
718 | static int first_index_reg = -1; | |
719 | static int last_index_reg; | |
720 | ||
15e35479 KH |
721 | #define LABEL_LIVE(LABEL) \ |
722 | (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno]) | |
723 | ||
dc0d5a57 BS |
724 | /* Subroutine of reload_combine_split_ruids, called to fix up a single |
725 | ruid pointed to by *PRUID if it is higher than SPLIT_RUID. */ | |
726 | ||
727 | static inline void | |
728 | reload_combine_split_one_ruid (int *pruid, int split_ruid) | |
729 | { | |
730 | if (*pruid > split_ruid) | |
731 | (*pruid)++; | |
732 | } | |
733 | ||
734 | /* Called when we insert a new insn in a position we've already passed in | |
735 | the scan. Examine all our state, increasing all ruids that are higher | |
736 | than SPLIT_RUID by one in order to make room for a new insn. */ | |
737 | ||
738 | static void | |
739 | reload_combine_split_ruids (int split_ruid) | |
740 | { | |
741 | unsigned i; | |
742 | ||
743 | reload_combine_split_one_ruid (&reload_combine_ruid, split_ruid); | |
744 | reload_combine_split_one_ruid (&last_label_ruid, split_ruid); | |
745 | reload_combine_split_one_ruid (&last_jump_ruid, split_ruid); | |
746 | ||
747 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
748 | { | |
749 | int j, idx = reg_state[i].use_index; | |
750 | reload_combine_split_one_ruid (®_state[i].use_ruid, split_ruid); | |
751 | reload_combine_split_one_ruid (®_state[i].store_ruid, split_ruid); | |
752 | reload_combine_split_one_ruid (®_state[i].real_store_ruid, | |
753 | split_ruid); | |
754 | if (idx < 0) | |
755 | continue; | |
756 | for (j = idx; j < RELOAD_COMBINE_MAX_USES; j++) | |
757 | { | |
758 | reload_combine_split_one_ruid (®_state[i].reg_use[j].ruid, | |
759 | split_ruid); | |
760 | } | |
761 | } | |
762 | } | |
763 | ||
764 | /* Called when we are about to rescan a previously encountered insn with | |
765 | reload_combine_note_use after modifying some part of it. This clears all | |
766 | information about uses in that particular insn. */ | |
767 | ||
768 | static void | |
f90af2e0 | 769 | reload_combine_purge_insn_uses (rtx_insn *insn) |
dc0d5a57 BS |
770 | { |
771 | unsigned i; | |
772 | ||
773 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
774 | { | |
775 | int j, k, idx = reg_state[i].use_index; | |
776 | if (idx < 0) | |
777 | continue; | |
778 | j = k = RELOAD_COMBINE_MAX_USES; | |
779 | while (j-- > idx) | |
780 | { | |
781 | if (reg_state[i].reg_use[j].insn != insn) | |
782 | { | |
783 | k--; | |
784 | if (k != j) | |
785 | reg_state[i].reg_use[k] = reg_state[i].reg_use[j]; | |
786 | } | |
787 | } | |
788 | reg_state[i].use_index = k; | |
789 | } | |
790 | } | |
791 | ||
792 | /* Called when we need to forget about all uses of REGNO after an insn | |
793 | which is identified by RUID. */ | |
794 | ||
795 | static void | |
796 | reload_combine_purge_reg_uses_after_ruid (unsigned regno, int ruid) | |
797 | { | |
798 | int j, k, idx = reg_state[regno].use_index; | |
799 | if (idx < 0) | |
800 | return; | |
801 | j = k = RELOAD_COMBINE_MAX_USES; | |
802 | while (j-- > idx) | |
803 | { | |
804 | if (reg_state[regno].reg_use[j].ruid >= ruid) | |
805 | { | |
806 | k--; | |
807 | if (k != j) | |
808 | reg_state[regno].reg_use[k] = reg_state[regno].reg_use[j]; | |
809 | } | |
810 | } | |
811 | reg_state[regno].use_index = k; | |
812 | } | |
813 | ||
814 | /* Find the use of REGNO with the ruid that is highest among those | |
815 | lower than RUID_LIMIT, and return it if it is the only use of this | |
08bd6876 | 816 | reg in the insn. Return NULL otherwise. */ |
dc0d5a57 BS |
817 | |
818 | static struct reg_use * | |
819 | reload_combine_closest_single_use (unsigned regno, int ruid_limit) | |
820 | { | |
821 | int i, best_ruid = 0; | |
822 | int use_idx = reg_state[regno].use_index; | |
823 | struct reg_use *retval; | |
824 | ||
825 | if (use_idx < 0) | |
826 | return NULL; | |
827 | retval = NULL; | |
828 | for (i = use_idx; i < RELOAD_COMBINE_MAX_USES; i++) | |
829 | { | |
b1d5eee8 BS |
830 | struct reg_use *use = reg_state[regno].reg_use + i; |
831 | int this_ruid = use->ruid; | |
dc0d5a57 BS |
832 | if (this_ruid >= ruid_limit) |
833 | continue; | |
834 | if (this_ruid > best_ruid) | |
835 | { | |
836 | best_ruid = this_ruid; | |
08bd6876 | 837 | retval = use; |
dc0d5a57 | 838 | } |
08bd6876 | 839 | else if (this_ruid == best_ruid) |
dc0d5a57 BS |
840 | retval = NULL; |
841 | } | |
842 | if (last_label_ruid >= best_ruid) | |
843 | return NULL; | |
844 | return retval; | |
845 | } | |
846 | ||
caa4a250 BS |
847 | /* After we've moved an add insn, fix up any debug insns that occur |
848 | between the old location of the add and the new location. REG is | |
849 | the destination register of the add insn; REPLACEMENT is the | |
850 | SET_SRC of the add. FROM and TO specify the range in which we | |
851 | should make this change on debug insns. */ | |
b1d5eee8 BS |
852 | |
853 | static void | |
f90af2e0 | 854 | fixup_debug_insns (rtx reg, rtx replacement, rtx_insn *from, rtx_insn *to) |
b1d5eee8 | 855 | { |
f90af2e0 | 856 | rtx_insn *insn; |
caa4a250 | 857 | for (insn = from; insn != to; insn = NEXT_INSN (insn)) |
b1d5eee8 BS |
858 | { |
859 | rtx t; | |
caa4a250 | 860 | |
65f4b875 | 861 | if (!DEBUG_BIND_INSN_P (insn)) |
b1d5eee8 | 862 | continue; |
caa4a250 BS |
863 | |
864 | t = INSN_VAR_LOCATION_LOC (insn); | |
08bd6876 | 865 | t = simplify_replace_rtx (t, reg, replacement); |
caa4a250 | 866 | validate_change (insn, &INSN_VAR_LOCATION_LOC (insn), t, 0); |
b1d5eee8 BS |
867 | } |
868 | } | |
869 | ||
a78e242c BS |
870 | /* Subroutine of reload_combine_recognize_const_pattern. Try to replace REG |
871 | with SRC in the insn described by USE, taking costs into account. Return | |
872 | true if we made the replacement. */ | |
873 | ||
874 | static bool | |
875 | try_replace_in_use (struct reg_use *use, rtx reg, rtx src) | |
876 | { | |
f90af2e0 | 877 | rtx_insn *use_insn = use->insn; |
a78e242c BS |
878 | rtx mem = use->containing_mem; |
879 | bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (use_insn)); | |
880 | ||
881 | if (mem != NULL_RTX) | |
882 | { | |
883 | addr_space_t as = MEM_ADDR_SPACE (mem); | |
884 | rtx oldaddr = XEXP (mem, 0); | |
885 | rtx newaddr = NULL_RTX; | |
886 | int old_cost = address_cost (oldaddr, GET_MODE (mem), as, speed); | |
887 | int new_cost; | |
888 | ||
889 | newaddr = simplify_replace_rtx (oldaddr, reg, src); | |
890 | if (memory_address_addr_space_p (GET_MODE (mem), newaddr, as)) | |
891 | { | |
892 | XEXP (mem, 0) = newaddr; | |
893 | new_cost = address_cost (newaddr, GET_MODE (mem), as, speed); | |
894 | XEXP (mem, 0) = oldaddr; | |
895 | if (new_cost <= old_cost | |
896 | && validate_change (use_insn, | |
897 | &XEXP (mem, 0), newaddr, 0)) | |
898 | return true; | |
899 | } | |
900 | } | |
901 | else | |
902 | { | |
903 | rtx new_set = single_set (use_insn); | |
904 | if (new_set | |
905 | && REG_P (SET_DEST (new_set)) | |
906 | && GET_CODE (SET_SRC (new_set)) == PLUS | |
907 | && REG_P (XEXP (SET_SRC (new_set), 0)) | |
908 | && CONSTANT_P (XEXP (SET_SRC (new_set), 1))) | |
909 | { | |
910 | rtx new_src; | |
e548c9df AM |
911 | machine_mode mode = GET_MODE (SET_DEST (new_set)); |
912 | int old_cost = set_src_cost (SET_SRC (new_set), mode, speed); | |
a78e242c BS |
913 | |
914 | gcc_assert (rtx_equal_p (XEXP (SET_SRC (new_set), 0), reg)); | |
915 | new_src = simplify_replace_rtx (SET_SRC (new_set), reg, src); | |
916 | ||
e548c9df | 917 | if (set_src_cost (new_src, mode, speed) <= old_cost |
a78e242c BS |
918 | && validate_change (use_insn, &SET_SRC (new_set), |
919 | new_src, 0)) | |
920 | return true; | |
921 | } | |
922 | } | |
923 | return false; | |
924 | } | |
925 | ||
dc0d5a57 BS |
926 | /* Called by reload_combine when scanning INSN. This function tries to detect |
927 | patterns where a constant is added to a register, and the result is used | |
928 | in an address. | |
929 | Return true if no further processing is needed on INSN; false if it wasn't | |
930 | recognized and should be handled normally. */ | |
931 | ||
932 | static bool | |
f90af2e0 | 933 | reload_combine_recognize_const_pattern (rtx_insn *insn) |
dc0d5a57 BS |
934 | { |
935 | int from_ruid = reload_combine_ruid; | |
936 | rtx set, pat, reg, src, addreg; | |
937 | unsigned int regno; | |
938 | struct reg_use *use; | |
939 | bool must_move_add; | |
f90af2e0 | 940 | rtx_insn *add_moved_after_insn = NULL; |
dc0d5a57 BS |
941 | int add_moved_after_ruid = 0; |
942 | int clobbered_regno = -1; | |
943 | ||
944 | set = single_set (insn); | |
945 | if (set == NULL_RTX) | |
946 | return false; | |
947 | ||
948 | reg = SET_DEST (set); | |
949 | src = SET_SRC (set); | |
950 | if (!REG_P (reg) | |
dc8afb70 | 951 | || REG_NREGS (reg) != 1 |
dc0d5a57 BS |
952 | || GET_MODE (reg) != Pmode |
953 | || reg == stack_pointer_rtx) | |
954 | return false; | |
955 | ||
956 | regno = REGNO (reg); | |
957 | ||
958 | /* We look for a REG1 = REG2 + CONSTANT insn, followed by either | |
959 | uses of REG1 inside an address, or inside another add insn. If | |
960 | possible and profitable, merge the addition into subsequent | |
961 | uses. */ | |
962 | if (GET_CODE (src) != PLUS | |
963 | || !REG_P (XEXP (src, 0)) | |
964 | || !CONSTANT_P (XEXP (src, 1))) | |
965 | return false; | |
966 | ||
967 | addreg = XEXP (src, 0); | |
968 | must_move_add = rtx_equal_p (reg, addreg); | |
969 | ||
970 | pat = PATTERN (insn); | |
971 | if (must_move_add && set != pat) | |
972 | { | |
973 | /* We have to be careful when moving the add; apart from the | |
974 | single_set there may also be clobbers. Recognize one special | |
975 | case, that of one clobber alongside the set (likely a clobber | |
976 | of the CC register). */ | |
977 | gcc_assert (GET_CODE (PATTERN (insn)) == PARALLEL); | |
978 | if (XVECLEN (pat, 0) != 2 || XVECEXP (pat, 0, 0) != set | |
979 | || GET_CODE (XVECEXP (pat, 0, 1)) != CLOBBER | |
980 | || !REG_P (XEXP (XVECEXP (pat, 0, 1), 0))) | |
981 | return false; | |
982 | clobbered_regno = REGNO (XEXP (XVECEXP (pat, 0, 1), 0)); | |
983 | } | |
984 | ||
985 | do | |
986 | { | |
987 | use = reload_combine_closest_single_use (regno, from_ruid); | |
988 | ||
989 | if (use) | |
990 | /* Start the search for the next use from here. */ | |
991 | from_ruid = use->ruid; | |
992 | ||
993 | if (use && GET_MODE (*use->usep) == Pmode) | |
994 | { | |
a78e242c | 995 | bool delete_add = false; |
f90af2e0 | 996 | rtx_insn *use_insn = use->insn; |
dc0d5a57 | 997 | int use_ruid = use->ruid; |
dc0d5a57 BS |
998 | |
999 | /* Avoid moving the add insn past a jump. */ | |
b1d5eee8 | 1000 | if (must_move_add && use_ruid <= last_jump_ruid) |
dc0d5a57 BS |
1001 | break; |
1002 | ||
1003 | /* If the add clobbers another hard reg in parallel, don't move | |
1004 | it past a real set of this hard reg. */ | |
1005 | if (must_move_add && clobbered_regno >= 0 | |
1006 | && reg_state[clobbered_regno].real_store_ruid >= use_ruid) | |
1007 | break; | |
1008 | ||
3b8ff89f | 1009 | /* Do not separate cc0 setter and cc0 user on HAVE_cc0 targets. */ |
058eb3b0 | 1010 | if (HAVE_cc0 && must_move_add && sets_cc0_p (PATTERN (use_insn))) |
3b8ff89f | 1011 | break; |
3b8ff89f | 1012 | |
62036819 BS |
1013 | gcc_assert (reg_state[regno].store_ruid <= use_ruid); |
1014 | /* Avoid moving a use of ADDREG past a point where it is stored. */ | |
a78e242c | 1015 | if (reg_state[REGNO (addreg)].store_ruid > use_ruid) |
dc0d5a57 BS |
1016 | break; |
1017 | ||
a78e242c BS |
1018 | /* We also must not move the addition past an insn that sets |
1019 | the same register, unless we can combine two add insns. */ | |
1020 | if (must_move_add && reg_state[regno].store_ruid == use_ruid) | |
dc0d5a57 | 1021 | { |
a78e242c BS |
1022 | if (use->containing_mem == NULL_RTX) |
1023 | delete_add = true; | |
1024 | else | |
1025 | break; | |
dc0d5a57 | 1026 | } |
dc0d5a57 | 1027 | |
a78e242c BS |
1028 | if (try_replace_in_use (use, reg, src)) |
1029 | { | |
1030 | reload_combine_purge_insn_uses (use_insn); | |
1031 | reload_combine_note_use (&PATTERN (use_insn), use_insn, | |
1032 | use_ruid, NULL_RTX); | |
dc0d5a57 | 1033 | |
a78e242c BS |
1034 | if (delete_add) |
1035 | { | |
1036 | fixup_debug_insns (reg, src, insn, use_insn); | |
1037 | delete_insn (insn); | |
1038 | return true; | |
1039 | } | |
1040 | if (must_move_add) | |
1041 | { | |
1042 | add_moved_after_insn = use_insn; | |
1043 | add_moved_after_ruid = use_ruid; | |
dc0d5a57 | 1044 | } |
a78e242c | 1045 | continue; |
dc0d5a57 | 1046 | } |
dc0d5a57 | 1047 | } |
62036819 BS |
1048 | /* If we get here, we couldn't handle this use. */ |
1049 | if (must_move_add) | |
1050 | break; | |
dc0d5a57 BS |
1051 | } |
1052 | while (use); | |
1053 | ||
1054 | if (!must_move_add || add_moved_after_insn == NULL_RTX) | |
1055 | /* Process the add normally. */ | |
1056 | return false; | |
1057 | ||
caa4a250 BS |
1058 | fixup_debug_insns (reg, src, insn, add_moved_after_insn); |
1059 | ||
dc0d5a57 BS |
1060 | reorder_insns (insn, insn, add_moved_after_insn); |
1061 | reload_combine_purge_reg_uses_after_ruid (regno, add_moved_after_ruid); | |
1062 | reload_combine_split_ruids (add_moved_after_ruid - 1); | |
1063 | reload_combine_note_use (&PATTERN (insn), insn, | |
1064 | add_moved_after_ruid, NULL_RTX); | |
1065 | reg_state[regno].store_ruid = add_moved_after_ruid; | |
1066 | ||
1067 | return true; | |
1068 | } | |
1069 | ||
67bb0206 BS |
1070 | /* Called by reload_combine when scanning INSN. Try to detect a pattern we |
1071 | can handle and improve. Return true if no further processing is needed on | |
1072 | INSN; false if it wasn't recognized and should be handled normally. */ | |
1073 | ||
1074 | static bool | |
f90af2e0 | 1075 | reload_combine_recognize_pattern (rtx_insn *insn) |
67bb0206 BS |
1076 | { |
1077 | rtx set, reg, src; | |
67bb0206 | 1078 | |
dc0d5a57 BS |
1079 | set = single_set (insn); |
1080 | if (set == NULL_RTX) | |
1081 | return false; | |
1082 | ||
1083 | reg = SET_DEST (set); | |
1084 | src = SET_SRC (set); | |
dc8afb70 | 1085 | if (!REG_P (reg) || REG_NREGS (reg) != 1) |
dc0d5a57 BS |
1086 | return false; |
1087 | ||
201d49e9 BS |
1088 | unsigned int regno = REGNO (reg); |
1089 | machine_mode mode = GET_MODE (reg); | |
1090 | ||
1091 | if (reg_state[regno].use_index < 0 | |
1092 | || reg_state[regno].use_index >= RELOAD_COMBINE_MAX_USES) | |
1093 | return false; | |
1094 | ||
1095 | for (int i = reg_state[regno].use_index; | |
1096 | i < RELOAD_COMBINE_MAX_USES; i++) | |
1097 | { | |
1098 | struct reg_use *use = reg_state[regno].reg_use + i; | |
1099 | if (GET_MODE (*use->usep) != mode) | |
1100 | return false; | |
32667e04 JJ |
1101 | /* Don't try to adjust (use (REGX)). */ |
1102 | if (GET_CODE (PATTERN (use->insn)) == USE | |
1103 | && &XEXP (PATTERN (use->insn), 0) == use->usep) | |
1104 | return false; | |
201d49e9 | 1105 | } |
dc0d5a57 | 1106 | |
67bb0206 BS |
1107 | /* Look for (set (REGX) (CONST_INT)) |
1108 | (set (REGX) (PLUS (REGX) (REGY))) | |
1109 | ... | |
1110 | ... (MEM (REGX)) ... | |
1111 | and convert it to | |
1112 | (set (REGZ) (CONST_INT)) | |
1113 | ... | |
1114 | ... (MEM (PLUS (REGZ) (REGY)))... . | |
1115 | ||
1116 | First, check that we have (set (REGX) (PLUS (REGX) (REGY))) | |
1117 | and that we know all uses of REGX before it dies. | |
1118 | Also, explicitly check that REGX != REGY; our life information | |
1119 | does not yet show whether REGY changes in this insn. */ | |
67bb0206 BS |
1120 | |
1121 | if (GET_CODE (src) == PLUS | |
dc0d5a57 BS |
1122 | && reg_state[regno].all_offsets_match |
1123 | && last_index_reg != -1 | |
67bb0206 BS |
1124 | && REG_P (XEXP (src, 1)) |
1125 | && rtx_equal_p (XEXP (src, 0), reg) | |
1126 | && !rtx_equal_p (XEXP (src, 1), reg) | |
1127 | && last_label_ruid < reg_state[regno].use_ruid) | |
1128 | { | |
1129 | rtx base = XEXP (src, 1); | |
f90af2e0 | 1130 | rtx_insn *prev = prev_nonnote_nondebug_insn (insn); |
67bb0206 BS |
1131 | rtx prev_set = prev ? single_set (prev) : NULL_RTX; |
1132 | rtx index_reg = NULL_RTX; | |
1133 | rtx reg_sum = NULL_RTX; | |
1134 | int i; | |
1135 | ||
1136 | /* Now we need to set INDEX_REG to an index register (denoted as | |
1137 | REGZ in the illustration above) and REG_SUM to the expression | |
1138 | register+register that we want to use to substitute uses of REG | |
1139 | (typically in MEMs) with. First check REG and BASE for being | |
1140 | index registers; we can use them even if they are not dead. */ | |
1141 | if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno) | |
1142 | || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], | |
1143 | REGNO (base))) | |
1144 | { | |
1145 | index_reg = reg; | |
1146 | reg_sum = src; | |
1147 | } | |
1148 | else | |
1149 | { | |
1150 | /* Otherwise, look for a free index register. Since we have | |
1151 | checked above that neither REG nor BASE are index registers, | |
1152 | if we find anything at all, it will be different from these | |
1153 | two registers. */ | |
1154 | for (i = first_index_reg; i <= last_index_reg; i++) | |
1155 | { | |
1156 | if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i) | |
1157 | && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES | |
1158 | && reg_state[i].store_ruid <= reg_state[regno].use_ruid | |
3df28f00 RS |
1159 | && (crtl->abi->clobbers_full_reg_p (i) |
1160 | || df_regs_ever_live_p (i)) | |
08bd6876 BS |
1161 | && (!frame_pointer_needed || i != HARD_FRAME_POINTER_REGNUM) |
1162 | && !fixed_regs[i] && !global_regs[i] | |
ad474626 | 1163 | && hard_regno_nregs (i, GET_MODE (reg)) == 1 |
08bd6876 | 1164 | && targetm.hard_regno_scratch_ok (i)) |
67bb0206 BS |
1165 | { |
1166 | index_reg = gen_rtx_REG (GET_MODE (reg), i); | |
1167 | reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base); | |
1168 | break; | |
1169 | } | |
1170 | } | |
1171 | } | |
1172 | ||
1173 | /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that | |
1174 | (REGY), i.e. BASE, is not clobbered before the last use we'll | |
1175 | create. */ | |
1176 | if (reg_sum | |
1177 | && prev_set | |
1178 | && CONST_INT_P (SET_SRC (prev_set)) | |
1179 | && rtx_equal_p (SET_DEST (prev_set), reg) | |
67bb0206 BS |
1180 | && (reg_state[REGNO (base)].store_ruid |
1181 | <= reg_state[regno].use_ruid)) | |
1182 | { | |
1183 | /* Change destination register and, if necessary, the constant | |
1184 | value in PREV, the constant loading instruction. */ | |
1185 | validate_change (prev, &SET_DEST (prev_set), index_reg, 1); | |
1186 | if (reg_state[regno].offset != const0_rtx) | |
927fb0bc JJ |
1187 | { |
1188 | HOST_WIDE_INT c | |
1189 | = trunc_int_for_mode (UINTVAL (SET_SRC (prev_set)) | |
1190 | + UINTVAL (reg_state[regno].offset), | |
1191 | GET_MODE (index_reg)); | |
1192 | validate_change (prev, &SET_SRC (prev_set), GEN_INT (c), 1); | |
1193 | } | |
67bb0206 BS |
1194 | |
1195 | /* Now for every use of REG that we have recorded, replace REG | |
1196 | with REG_SUM. */ | |
1197 | for (i = reg_state[regno].use_index; | |
1198 | i < RELOAD_COMBINE_MAX_USES; i++) | |
1199 | validate_unshare_change (reg_state[regno].reg_use[i].insn, | |
1200 | reg_state[regno].reg_use[i].usep, | |
1201 | /* Each change must have its own | |
1202 | replacement. */ | |
1203 | reg_sum, 1); | |
1204 | ||
1205 | if (apply_change_group ()) | |
1206 | { | |
caa4a250 BS |
1207 | struct reg_use *lowest_ruid = NULL; |
1208 | ||
67bb0206 BS |
1209 | /* For every new use of REG_SUM, we have to record the use |
1210 | of BASE therein, i.e. operand 1. */ | |
1211 | for (i = reg_state[regno].use_index; | |
1212 | i < RELOAD_COMBINE_MAX_USES; i++) | |
caa4a250 BS |
1213 | { |
1214 | struct reg_use *use = reg_state[regno].reg_use + i; | |
1215 | reload_combine_note_use (&XEXP (*use->usep, 1), use->insn, | |
1216 | use->ruid, use->containing_mem); | |
1217 | if (lowest_ruid == NULL || use->ruid < lowest_ruid->ruid) | |
1218 | lowest_ruid = use; | |
1219 | } | |
1220 | ||
1221 | fixup_debug_insns (reg, reg_sum, insn, lowest_ruid->insn); | |
67bb0206 | 1222 | |
67bb0206 BS |
1223 | /* Delete the reg-reg addition. */ |
1224 | delete_insn (insn); | |
1225 | ||
af1634f1 JJ |
1226 | if (reg_state[regno].offset != const0_rtx) |
1227 | /* Previous REG_EQUIV / REG_EQUAL notes for PREV | |
1228 | are now invalid. */ | |
1229 | remove_reg_equal_equiv_notes (prev); | |
67bb0206 BS |
1230 | |
1231 | reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES; | |
67bb0206 BS |
1232 | return true; |
1233 | } | |
1234 | } | |
1235 | } | |
1236 | return false; | |
1237 | } | |
1238 | ||
15e35479 | 1239 | static void |
0c20a65f | 1240 | reload_combine (void) |
15e35479 | 1241 | { |
f90af2e0 | 1242 | rtx_insn *insn, *prev; |
15e35479 KH |
1243 | basic_block bb; |
1244 | unsigned int r; | |
15e35479 KH |
1245 | int min_labelno, n_labels; |
1246 | HARD_REG_SET ever_live_at_start, *label_live; | |
1247 | ||
15e35479 KH |
1248 | /* To avoid wasting too much time later searching for an index register, |
1249 | determine the minimum and maximum index register numbers. */ | |
67bb0206 BS |
1250 | if (INDEX_REG_CLASS == NO_REGS) |
1251 | last_index_reg = -1; | |
1252 | else if (first_index_reg == -1 && last_index_reg == 0) | |
1253 | { | |
1254 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) | |
1255 | if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r)) | |
1256 | { | |
1257 | if (first_index_reg == -1) | |
1258 | first_index_reg = r; | |
1259 | ||
1260 | last_index_reg = r; | |
1261 | } | |
1262 | ||
1263 | /* If no index register is available, we can quit now. Set LAST_INDEX_REG | |
1264 | to -1 so we'll know to quit early the next time we get here. */ | |
1265 | if (first_index_reg == -1) | |
1266 | { | |
1267 | last_index_reg = -1; | |
1268 | return; | |
1269 | } | |
1270 | } | |
15e35479 | 1271 | |
15e35479 KH |
1272 | /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime |
1273 | information is a bit fuzzy immediately after reload, but it's | |
1274 | still good enough to determine which registers are live at a jump | |
1275 | destination. */ | |
1276 | min_labelno = get_first_label_num (); | |
1277 | n_labels = max_label_num () - min_labelno; | |
5ed6ace5 | 1278 | label_live = XNEWVEC (HARD_REG_SET, n_labels); |
15e35479 KH |
1279 | CLEAR_HARD_REG_SET (ever_live_at_start); |
1280 | ||
4f42035e | 1281 | FOR_EACH_BB_REVERSE_FN (bb, cfun) |
15e35479 | 1282 | { |
a813c111 | 1283 | insn = BB_HEAD (bb); |
4b4bf941 | 1284 | if (LABEL_P (insn)) |
15e35479 KH |
1285 | { |
1286 | HARD_REG_SET live; | |
89a95777 | 1287 | bitmap live_in = df_get_live_in (bb); |
15e35479 | 1288 | |
89a95777 KZ |
1289 | REG_SET_TO_HARD_REG_SET (live, live_in); |
1290 | compute_use_by_pseudos (&live, live_in); | |
6576d245 | 1291 | LABEL_LIVE (insn) = live; |
44942965 | 1292 | ever_live_at_start |= live; |
15e35479 KH |
1293 | } |
1294 | } | |
1295 | ||
1296 | /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */ | |
dc0d5a57 | 1297 | last_label_ruid = last_jump_ruid = reload_combine_ruid = 0; |
15e35479 KH |
1298 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) |
1299 | { | |
dc0d5a57 BS |
1300 | reg_state[r].store_ruid = 0; |
1301 | reg_state[r].real_store_ruid = 0; | |
15e35479 KH |
1302 | if (fixed_regs[r]) |
1303 | reg_state[r].use_index = -1; | |
1304 | else | |
1305 | reg_state[r].use_index = RELOAD_COMBINE_MAX_USES; | |
1306 | } | |
1307 | ||
dc0d5a57 | 1308 | for (insn = get_last_insn (); insn; insn = prev) |
15e35479 | 1309 | { |
7ad93142 | 1310 | bool control_flow_insn; |
15e35479 KH |
1311 | rtx note; |
1312 | ||
dc0d5a57 BS |
1313 | prev = PREV_INSN (insn); |
1314 | ||
15e35479 KH |
1315 | /* We cannot do our optimization across labels. Invalidating all the use |
1316 | information we have would be costly, so we just note where the label | |
1317 | is and then later disable any optimization that would cross it. */ | |
4b4bf941 | 1318 | if (LABEL_P (insn)) |
15e35479 | 1319 | last_label_ruid = reload_combine_ruid; |
2195c9be AK |
1320 | else if (BARRIER_P (insn)) |
1321 | { | |
1322 | /* Crossing a barrier resets all the use information. */ | |
1323 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) | |
1324 | if (! fixed_regs[r]) | |
15e35479 | 1325 | reg_state[r].use_index = RELOAD_COMBINE_MAX_USES; |
2195c9be AK |
1326 | } |
1327 | else if (INSN_P (insn) && volatile_insn_p (PATTERN (insn))) | |
1328 | /* Optimizations across insns being marked as volatile must be | |
1329 | prevented. All the usage information is invalidated | |
1330 | here. */ | |
1331 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) | |
1332 | if (! fixed_regs[r] | |
1333 | && reg_state[r].use_index != RELOAD_COMBINE_MAX_USES) | |
1334 | reg_state[r].use_index = -1; | |
15e35479 | 1335 | |
caa4a250 | 1336 | if (! NONDEBUG_INSN_P (insn)) |
15e35479 KH |
1337 | continue; |
1338 | ||
1339 | reload_combine_ruid++; | |
1340 | ||
7ad93142 EB |
1341 | control_flow_insn = control_flow_insn_p (insn); |
1342 | if (control_flow_insn) | |
dc0d5a57 BS |
1343 | last_jump_ruid = reload_combine_ruid; |
1344 | ||
1345 | if (reload_combine_recognize_const_pattern (insn) | |
1346 | || reload_combine_recognize_pattern (insn)) | |
67bb0206 | 1347 | continue; |
15e35479 | 1348 | |
e8448ba5 | 1349 | note_stores (insn, reload_combine_note_store, NULL); |
15e35479 | 1350 | |
4b4bf941 | 1351 | if (CALL_P (insn)) |
15e35479 KH |
1352 | { |
1353 | rtx link; | |
5a5a3bc5 | 1354 | HARD_REG_SET used_regs = insn_callee_abi (insn).full_reg_clobbers (); |
15e35479 KH |
1355 | |
1356 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) | |
97ded4cd | 1357 | if (TEST_HARD_REG_BIT (used_regs, r)) |
15e35479 KH |
1358 | { |
1359 | reg_state[r].use_index = RELOAD_COMBINE_MAX_USES; | |
1360 | reg_state[r].store_ruid = reload_combine_ruid; | |
1361 | } | |
1362 | ||
1363 | for (link = CALL_INSN_FUNCTION_USAGE (insn); link; | |
1364 | link = XEXP (link, 1)) | |
1365 | { | |
e384e6b5 BS |
1366 | rtx setuse = XEXP (link, 0); |
1367 | rtx usage_rtx = XEXP (setuse, 0); | |
8df47bdf | 1368 | |
e8448ba5 | 1369 | if (GET_CODE (setuse) == USE && REG_P (usage_rtx)) |
15e35479 | 1370 | { |
53d1bae9 RS |
1371 | unsigned int end_regno = END_REGNO (usage_rtx); |
1372 | for (unsigned int i = REGNO (usage_rtx); i < end_regno; ++i) | |
e8448ba5 | 1373 | reg_state[i].use_index = -1; |
15e35479 KH |
1374 | } |
1375 | } | |
15e35479 | 1376 | } |
18c33e03 | 1377 | |
57895947 | 1378 | if (control_flow_insn && !ANY_RETURN_P (PATTERN (insn))) |
15e35479 KH |
1379 | { |
1380 | /* Non-spill registers might be used at the call destination in | |
1381 | some unknown fashion, so we have to mark the unknown use. */ | |
1382 | HARD_REG_SET *live; | |
1383 | ||
1384 | if ((condjump_p (insn) || condjump_in_parallel_p (insn)) | |
1385 | && JUMP_LABEL (insn)) | |
57895947 EB |
1386 | { |
1387 | if (ANY_RETURN_P (JUMP_LABEL (insn))) | |
1388 | live = NULL; | |
1389 | else | |
1390 | live = &LABEL_LIVE (JUMP_LABEL (insn)); | |
1391 | } | |
15e35479 KH |
1392 | else |
1393 | live = &ever_live_at_start; | |
1394 | ||
57895947 EB |
1395 | if (live) |
1396 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) | |
1397 | if (TEST_HARD_REG_BIT (*live, r)) | |
1398 | reg_state[r].use_index = -1; | |
15e35479 KH |
1399 | } |
1400 | ||
7ad93142 EB |
1401 | reload_combine_note_use (&PATTERN (insn), insn, reload_combine_ruid, |
1402 | NULL_RTX); | |
1403 | ||
15e35479 KH |
1404 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) |
1405 | { | |
7ad93142 | 1406 | if (REG_NOTE_KIND (note) == REG_INC && REG_P (XEXP (note, 0))) |
15e35479 KH |
1407 | { |
1408 | int regno = REGNO (XEXP (note, 0)); | |
15e35479 | 1409 | reg_state[regno].store_ruid = reload_combine_ruid; |
dc0d5a57 | 1410 | reg_state[regno].real_store_ruid = reload_combine_ruid; |
15e35479 KH |
1411 | reg_state[regno].use_index = -1; |
1412 | } | |
1413 | } | |
1414 | } | |
1415 | ||
1416 | free (label_live); | |
1417 | } | |
1418 | ||
1419 | /* Check if DST is a register or a subreg of a register; if it is, | |
dc0d5a57 BS |
1420 | update store_ruid, real_store_ruid and use_index in the reg_state |
1421 | structure accordingly. Called via note_stores from reload_combine. */ | |
15e35479 KH |
1422 | |
1423 | static void | |
7bc980e1 | 1424 | reload_combine_note_store (rtx dst, const_rtx set, void *data ATTRIBUTE_UNUSED) |
15e35479 KH |
1425 | { |
1426 | int regno = 0; | |
1427 | int i; | |
ef4bddc2 | 1428 | machine_mode mode = GET_MODE (dst); |
15e35479 KH |
1429 | |
1430 | if (GET_CODE (dst) == SUBREG) | |
1431 | { | |
1432 | regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)), | |
1433 | GET_MODE (SUBREG_REG (dst)), | |
1434 | SUBREG_BYTE (dst), | |
1435 | GET_MODE (dst)); | |
1436 | dst = SUBREG_REG (dst); | |
1437 | } | |
12c2b0ad JL |
1438 | |
1439 | /* Some targets do argument pushes without adding REG_INC notes. */ | |
1440 | ||
1441 | if (MEM_P (dst)) | |
1442 | { | |
1443 | dst = XEXP (dst, 0); | |
1444 | if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_INC | |
96676a5d JJ |
1445 | || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC |
1446 | || GET_CODE (dst) == PRE_MODIFY || GET_CODE (dst) == POST_MODIFY) | |
12c2b0ad | 1447 | { |
53d1bae9 RS |
1448 | unsigned int end_regno = END_REGNO (XEXP (dst, 0)); |
1449 | for (unsigned int i = REGNO (XEXP (dst, 0)); i < end_regno; ++i) | |
12c2b0ad JL |
1450 | { |
1451 | /* We could probably do better, but for now mark the register | |
1452 | as used in an unknown fashion and set/clobbered at this | |
1453 | insn. */ | |
1454 | reg_state[i].use_index = -1; | |
1455 | reg_state[i].store_ruid = reload_combine_ruid; | |
1456 | reg_state[i].real_store_ruid = reload_combine_ruid; | |
1457 | } | |
1458 | } | |
1459 | else | |
1460 | return; | |
1461 | } | |
1462 | ||
f8cfc6aa | 1463 | if (!REG_P (dst)) |
15e35479 KH |
1464 | return; |
1465 | regno += REGNO (dst); | |
1466 | ||
1467 | /* note_stores might have stripped a STRICT_LOW_PART, so we have to be | |
1468 | careful with registers / register parts that are not full words. | |
46d096a3 | 1469 | Similarly for ZERO_EXTRACT. */ |
dc0d5a57 | 1470 | if (GET_CODE (SET_DEST (set)) == ZERO_EXTRACT |
15e35479 KH |
1471 | || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART) |
1472 | { | |
4edd6298 | 1473 | for (i = end_hard_regno (mode, regno) - 1; i >= regno; i--) |
15e35479 KH |
1474 | { |
1475 | reg_state[i].use_index = -1; | |
1476 | reg_state[i].store_ruid = reload_combine_ruid; | |
dc0d5a57 | 1477 | reg_state[i].real_store_ruid = reload_combine_ruid; |
15e35479 KH |
1478 | } |
1479 | } | |
1480 | else | |
1481 | { | |
4edd6298 | 1482 | for (i = end_hard_regno (mode, regno) - 1; i >= regno; i--) |
15e35479 KH |
1483 | { |
1484 | reg_state[i].store_ruid = reload_combine_ruid; | |
dc0d5a57 BS |
1485 | if (GET_CODE (set) == SET) |
1486 | reg_state[i].real_store_ruid = reload_combine_ruid; | |
15e35479 KH |
1487 | reg_state[i].use_index = RELOAD_COMBINE_MAX_USES; |
1488 | } | |
1489 | } | |
1490 | } | |
1491 | ||
1492 | /* XP points to a piece of rtl that has to be checked for any uses of | |
1493 | registers. | |
1494 | *XP is the pattern of INSN, or a part of it. | |
1495 | Called from reload_combine, and recursively by itself. */ | |
1496 | static void | |
f90af2e0 | 1497 | reload_combine_note_use (rtx *xp, rtx_insn *insn, int ruid, rtx containing_mem) |
15e35479 KH |
1498 | { |
1499 | rtx x = *xp; | |
1500 | enum rtx_code code = x->code; | |
1501 | const char *fmt; | |
1502 | int i, j; | |
1503 | rtx offset = const0_rtx; /* For the REG case below. */ | |
1504 | ||
1505 | switch (code) | |
1506 | { | |
1507 | case SET: | |
f8cfc6aa | 1508 | if (REG_P (SET_DEST (x))) |
15e35479 | 1509 | { |
dc0d5a57 | 1510 | reload_combine_note_use (&SET_SRC (x), insn, ruid, NULL_RTX); |
15e35479 KH |
1511 | return; |
1512 | } | |
1513 | break; | |
1514 | ||
1515 | case USE: | |
1516 | /* If this is the USE of a return value, we can't change it. */ | |
f8cfc6aa | 1517 | if (REG_P (XEXP (x, 0)) && REG_FUNCTION_VALUE_P (XEXP (x, 0))) |
15e35479 | 1518 | { |
53d1bae9 | 1519 | /* Mark the return register as used in an unknown fashion. */ |
15e35479 | 1520 | rtx reg = XEXP (x, 0); |
53d1bae9 RS |
1521 | unsigned int end_regno = END_REGNO (reg); |
1522 | for (unsigned int regno = REGNO (reg); regno < end_regno; ++regno) | |
1523 | reg_state[regno].use_index = -1; | |
15e35479 KH |
1524 | return; |
1525 | } | |
1526 | break; | |
1527 | ||
1528 | case CLOBBER: | |
f8cfc6aa | 1529 | if (REG_P (SET_DEST (x))) |
15e35479 KH |
1530 | { |
1531 | /* No spurious CLOBBERs of pseudo registers may remain. */ | |
e16acfcd | 1532 | gcc_assert (REGNO (SET_DEST (x)) < FIRST_PSEUDO_REGISTER); |
15e35479 KH |
1533 | return; |
1534 | } | |
1535 | break; | |
1536 | ||
1537 | case PLUS: | |
1538 | /* We are interested in (plus (reg) (const_int)) . */ | |
f8cfc6aa | 1539 | if (!REG_P (XEXP (x, 0)) |
481683e1 | 1540 | || !CONST_INT_P (XEXP (x, 1))) |
15e35479 KH |
1541 | break; |
1542 | offset = XEXP (x, 1); | |
1543 | x = XEXP (x, 0); | |
1544 | /* Fall through. */ | |
1545 | case REG: | |
1546 | { | |
1547 | int regno = REGNO (x); | |
1548 | int use_index; | |
1549 | int nregs; | |
1550 | ||
1551 | /* No spurious USEs of pseudo registers may remain. */ | |
e16acfcd | 1552 | gcc_assert (regno < FIRST_PSEUDO_REGISTER); |
15e35479 | 1553 | |
dc8afb70 | 1554 | nregs = REG_NREGS (x); |
15e35479 KH |
1555 | |
1556 | /* We can't substitute into multi-hard-reg uses. */ | |
1557 | if (nregs > 1) | |
1558 | { | |
1559 | while (--nregs >= 0) | |
1560 | reg_state[regno + nregs].use_index = -1; | |
1561 | return; | |
1562 | } | |
1563 | ||
08bd6876 BS |
1564 | /* We may be called to update uses in previously seen insns. |
1565 | Don't add uses beyond the last store we saw. */ | |
1566 | if (ruid < reg_state[regno].store_ruid) | |
1567 | return; | |
1568 | ||
15e35479 KH |
1569 | /* If this register is already used in some unknown fashion, we |
1570 | can't do anything. | |
1571 | If we decrement the index from zero to -1, we can't store more | |
1572 | uses, so this register becomes used in an unknown fashion. */ | |
1573 | use_index = --reg_state[regno].use_index; | |
1574 | if (use_index < 0) | |
1575 | return; | |
1576 | ||
dc0d5a57 | 1577 | if (use_index == RELOAD_COMBINE_MAX_USES - 1) |
15e35479 KH |
1578 | { |
1579 | /* This is the first use of this register we have seen since we | |
1580 | marked it as dead. */ | |
1581 | reg_state[regno].offset = offset; | |
dc0d5a57 BS |
1582 | reg_state[regno].all_offsets_match = true; |
1583 | reg_state[regno].use_ruid = ruid; | |
15e35479 | 1584 | } |
b1d5eee8 BS |
1585 | else |
1586 | { | |
1587 | if (reg_state[regno].use_ruid > ruid) | |
1588 | reg_state[regno].use_ruid = ruid; | |
1589 | ||
1590 | if (! rtx_equal_p (offset, reg_state[regno].offset)) | |
1591 | reg_state[regno].all_offsets_match = false; | |
1592 | } | |
dc0d5a57 | 1593 | |
15e35479 | 1594 | reg_state[regno].reg_use[use_index].insn = insn; |
dc0d5a57 BS |
1595 | reg_state[regno].reg_use[use_index].ruid = ruid; |
1596 | reg_state[regno].reg_use[use_index].containing_mem = containing_mem; | |
15e35479 KH |
1597 | reg_state[regno].reg_use[use_index].usep = xp; |
1598 | return; | |
1599 | } | |
1600 | ||
dc0d5a57 BS |
1601 | case MEM: |
1602 | containing_mem = x; | |
1603 | break; | |
1604 | ||
15e35479 KH |
1605 | default: |
1606 | break; | |
1607 | } | |
1608 | ||
1609 | /* Recursively process the components of X. */ | |
1610 | fmt = GET_RTX_FORMAT (code); | |
1611 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1612 | { | |
1613 | if (fmt[i] == 'e') | |
dc0d5a57 | 1614 | reload_combine_note_use (&XEXP (x, i), insn, ruid, containing_mem); |
15e35479 KH |
1615 | else if (fmt[i] == 'E') |
1616 | { | |
1617 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
dc0d5a57 BS |
1618 | reload_combine_note_use (&XVECEXP (x, i, j), insn, ruid, |
1619 | containing_mem); | |
15e35479 KH |
1620 | } |
1621 | } | |
1622 | } | |
1623 | \f | |
1624 | /* See if we can reduce the cost of a constant by replacing a move | |
1625 | with an add. We track situations in which a register is set to a | |
1626 | constant or to a register plus a constant. */ | |
1627 | /* We cannot do our optimization across labels. Invalidating all the | |
1628 | information about register contents we have would be costly, so we | |
1629 | use move2add_last_label_luid to note where the label is and then | |
1630 | later disable any optimization that would cross it. | |
7beb0596 JZ |
1631 | reg_offset[n] / reg_base_reg[n] / reg_symbol_ref[n] / reg_mode[n] |
1632 | are only valid if reg_set_luid[n] is greater than | |
7894bc6b JR |
1633 | move2add_last_label_luid. |
1634 | For a set that established a new (potential) base register with | |
1635 | non-constant value, we use move2add_luid from the place where the | |
1636 | setting insn is encountered; registers based off that base then | |
1637 | get the same reg_set_luid. Constants all get | |
1638 | move2add_last_label_luid + 1 as their reg_set_luid. */ | |
15e35479 KH |
1639 | static int reg_set_luid[FIRST_PSEUDO_REGISTER]; |
1640 | ||
1641 | /* If reg_base_reg[n] is negative, register n has been set to | |
7beb0596 | 1642 | reg_offset[n] or reg_symbol_ref[n] + reg_offset[n] in mode reg_mode[n]. |
15e35479 KH |
1643 | If reg_base_reg[n] is non-negative, register n has been set to the |
1644 | sum of reg_offset[n] and the value of register reg_base_reg[n] | |
7894bc6b JR |
1645 | before reg_set_luid[n], calculated in mode reg_mode[n] . |
1646 | For multi-hard-register registers, all but the first one are | |
1647 | recorded as BLKmode in reg_mode. Setting reg_mode to VOIDmode | |
1648 | marks it as invalid. */ | |
15e35479 KH |
1649 | static HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER]; |
1650 | static int reg_base_reg[FIRST_PSEUDO_REGISTER]; | |
7beb0596 | 1651 | static rtx reg_symbol_ref[FIRST_PSEUDO_REGISTER]; |
ef4bddc2 | 1652 | static machine_mode reg_mode[FIRST_PSEUDO_REGISTER]; |
15e35479 KH |
1653 | |
1654 | /* move2add_luid is linearly increased while scanning the instructions | |
1655 | from first to last. It is used to set reg_set_luid in | |
1656 | reload_cse_move2add and move2add_note_store. */ | |
1657 | static int move2add_luid; | |
1658 | ||
1659 | /* move2add_last_label_luid is set whenever a label is found. Labels | |
1660 | invalidate all previously collected reg_offset data. */ | |
1661 | static int move2add_last_label_luid; | |
1662 | ||
1663 | /* ??? We don't know how zero / sign extension is handled, hence we | |
1664 | can't go from a narrower to a wider mode. */ | |
1665 | #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \ | |
1666 | (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \ | |
1667 | || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \ | |
d0edd768 | 1668 | && TRULY_NOOP_TRUNCATION_MODES_P (OUTMODE, INMODE))) |
15e35479 | 1669 | |
7894bc6b JR |
1670 | /* Record that REG is being set to a value with the mode of REG. */ |
1671 | ||
1672 | static void | |
1673 | move2add_record_mode (rtx reg) | |
1674 | { | |
1675 | int regno, nregs; | |
ef4bddc2 | 1676 | machine_mode mode = GET_MODE (reg); |
7894bc6b JR |
1677 | |
1678 | if (GET_CODE (reg) == SUBREG) | |
1679 | { | |
1680 | regno = subreg_regno (reg); | |
1681 | nregs = subreg_nregs (reg); | |
1682 | } | |
1683 | else if (REG_P (reg)) | |
1684 | { | |
1685 | regno = REGNO (reg); | |
dc8afb70 | 1686 | nregs = REG_NREGS (reg); |
7894bc6b JR |
1687 | } |
1688 | else | |
1689 | gcc_unreachable (); | |
1690 | for (int i = nregs - 1; i > 0; i--) | |
1691 | reg_mode[regno + i] = BLKmode; | |
1692 | reg_mode[regno] = mode; | |
1693 | } | |
1694 | ||
1695 | /* Record that REG is being set to the sum of SYM and OFF. */ | |
1696 | ||
1697 | static void | |
1698 | move2add_record_sym_value (rtx reg, rtx sym, rtx off) | |
1699 | { | |
1700 | int regno = REGNO (reg); | |
1701 | ||
1702 | move2add_record_mode (reg); | |
1703 | reg_set_luid[regno] = move2add_luid; | |
1704 | reg_base_reg[regno] = -1; | |
1705 | reg_symbol_ref[regno] = sym; | |
1706 | reg_offset[regno] = INTVAL (off); | |
1707 | } | |
1708 | ||
1709 | /* Check if REGNO contains a valid value in MODE. */ | |
1710 | ||
1711 | static bool | |
1e047eed | 1712 | move2add_valid_value_p (int regno, scalar_int_mode mode) |
7894bc6b | 1713 | { |
ca035367 | 1714 | if (reg_set_luid[regno] <= move2add_last_label_luid) |
7894bc6b JR |
1715 | return false; |
1716 | ||
ca035367 JR |
1717 | if (mode != reg_mode[regno]) |
1718 | { | |
6b9c3dec RS |
1719 | scalar_int_mode old_mode; |
1720 | if (!is_a <scalar_int_mode> (reg_mode[regno], &old_mode) | |
1721 | || !MODES_OK_FOR_MOVE2ADD (mode, old_mode)) | |
ca035367 JR |
1722 | return false; |
1723 | /* The value loaded into regno in reg_mode[regno] is also valid in | |
1724 | mode after truncation only if (REG:mode regno) is the lowpart of | |
1725 | (REG:reg_mode[regno] regno). Now, for big endian, the starting | |
1726 | regno of the lowpart might be different. */ | |
91914e56 | 1727 | poly_int64 s_off = subreg_lowpart_offset (mode, old_mode); |
6b9c3dec | 1728 | s_off = subreg_regno_offset (regno, old_mode, s_off, mode); |
91914e56 | 1729 | if (maybe_ne (s_off, 0)) |
ca035367 JR |
1730 | /* We could in principle adjust regno, check reg_mode[regno] to be |
1731 | BLKmode, and return s_off to the caller (vs. -1 for failure), | |
1732 | but we currently have no callers that could make use of this | |
1733 | information. */ | |
1734 | return false; | |
1735 | } | |
1736 | ||
4edd6298 RS |
1737 | for (int i = end_hard_regno (mode, regno) - 1; i > regno; i--) |
1738 | if (reg_mode[i] != BLKmode) | |
7894bc6b JR |
1739 | return false; |
1740 | return true; | |
1741 | } | |
1742 | ||
1e047eed RS |
1743 | /* This function is called with INSN that sets REG (of mode MODE) |
1744 | to (SYM + OFF), while REG is known to already have value (SYM + offset). | |
7beb0596 JZ |
1745 | This function tries to change INSN into an add instruction |
1746 | (set (REG) (plus (REG) (OFF - offset))) using the known value. | |
dc0d5a57 BS |
1747 | It also updates the information about REG's known value. |
1748 | Return true if we made a change. */ | |
7beb0596 | 1749 | |
dc0d5a57 | 1750 | static bool |
1e047eed RS |
1751 | move2add_use_add2_insn (scalar_int_mode mode, rtx reg, rtx sym, rtx off, |
1752 | rtx_insn *insn) | |
7beb0596 JZ |
1753 | { |
1754 | rtx pat = PATTERN (insn); | |
1755 | rtx src = SET_SRC (pat); | |
1756 | int regno = REGNO (reg); | |
1e047eed | 1757 | rtx new_src = gen_int_mode (UINTVAL (off) - reg_offset[regno], mode); |
7beb0596 | 1758 | bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); |
dc0d5a57 | 1759 | bool changed = false; |
7beb0596 JZ |
1760 | |
1761 | /* (set (reg) (plus (reg) (const_int 0))) is not canonical; | |
1762 | use (set (reg) (reg)) instead. | |
1763 | We don't delete this insn, nor do we convert it into a | |
1764 | note, to avoid losing register notes or the return | |
1765 | value flag. jump2 already knows how to get rid of | |
1766 | no-op moves. */ | |
1767 | if (new_src == const0_rtx) | |
1768 | { | |
1769 | /* If the constants are different, this is a | |
1770 | truncation, that, if turned into (set (reg) | |
1771 | (reg)), would be discarded. Maybe we should | |
1772 | try a truncMN pattern? */ | |
1773 | if (INTVAL (off) == reg_offset [regno]) | |
dc0d5a57 | 1774 | changed = validate_change (insn, &SET_SRC (pat), reg, 0); |
7beb0596 | 1775 | } |
22939744 | 1776 | else |
7beb0596 | 1777 | { |
22939744 | 1778 | struct full_rtx_costs oldcst, newcst; |
1e047eed | 1779 | rtx tem = gen_rtx_PLUS (mode, reg, new_src); |
22939744 | 1780 | |
d51102f3 | 1781 | get_full_set_rtx_cost (pat, &oldcst); |
22939744 | 1782 | SET_SRC (pat) = tem; |
d51102f3 | 1783 | get_full_set_rtx_cost (pat, &newcst); |
22939744 BS |
1784 | SET_SRC (pat) = src; |
1785 | ||
1786 | if (costs_lt_p (&newcst, &oldcst, speed) | |
1787 | && have_add2_insn (reg, new_src)) | |
1788 | changed = validate_change (insn, &SET_SRC (pat), tem, 0); | |
1e047eed | 1789 | else if (sym == NULL_RTX && mode != BImode) |
7beb0596 | 1790 | { |
1e047eed RS |
1791 | scalar_int_mode narrow_mode; |
1792 | FOR_EACH_MODE_UNTIL (narrow_mode, mode) | |
7beb0596 | 1793 | { |
22939744 BS |
1794 | if (have_insn_for (STRICT_LOW_PART, narrow_mode) |
1795 | && ((reg_offset[regno] & ~GET_MODE_MASK (narrow_mode)) | |
1796 | == (INTVAL (off) & ~GET_MODE_MASK (narrow_mode)))) | |
1797 | { | |
b49eefa5 | 1798 | rtx narrow_reg = gen_lowpart_common (narrow_mode, reg); |
22939744 BS |
1799 | rtx narrow_src = gen_int_mode (INTVAL (off), |
1800 | narrow_mode); | |
1801 | rtx new_set | |
f7df4a84 | 1802 | = gen_rtx_SET (gen_rtx_STRICT_LOW_PART (VOIDmode, |
22939744 BS |
1803 | narrow_reg), |
1804 | narrow_src); | |
a0f37b26 AS |
1805 | get_full_set_rtx_cost (new_set, &newcst); |
1806 | if (costs_lt_p (&newcst, &oldcst, speed)) | |
1807 | { | |
1808 | changed = validate_change (insn, &PATTERN (insn), | |
1809 | new_set, 0); | |
1810 | if (changed) | |
1811 | break; | |
1812 | } | |
22939744 | 1813 | } |
7beb0596 JZ |
1814 | } |
1815 | } | |
1816 | } | |
7894bc6b | 1817 | move2add_record_sym_value (reg, sym, off); |
dc0d5a57 | 1818 | return changed; |
7beb0596 JZ |
1819 | } |
1820 | ||
1821 | ||
1e047eed RS |
1822 | /* This function is called with INSN that sets REG (of mode MODE) to |
1823 | (SYM + OFF), but REG doesn't have known value (SYM + offset). This | |
1824 | function tries to find another register which is known to already have | |
7beb0596 JZ |
1825 | value (SYM + offset) and change INSN into an add instruction |
1826 | (set (REG) (plus (the found register) (OFF - offset))) if such | |
1827 | a register is found. It also updates the information about | |
dc0d5a57 BS |
1828 | REG's known value. |
1829 | Return true iff we made a change. */ | |
7beb0596 | 1830 | |
dc0d5a57 | 1831 | static bool |
1e047eed RS |
1832 | move2add_use_add3_insn (scalar_int_mode mode, rtx reg, rtx sym, rtx off, |
1833 | rtx_insn *insn) | |
7beb0596 JZ |
1834 | { |
1835 | rtx pat = PATTERN (insn); | |
1836 | rtx src = SET_SRC (pat); | |
1837 | int regno = REGNO (reg); | |
5676e87d | 1838 | int min_regno = 0; |
7beb0596 JZ |
1839 | bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); |
1840 | int i; | |
dc0d5a57 | 1841 | bool changed = false; |
22939744 BS |
1842 | struct full_rtx_costs oldcst, newcst, mincst; |
1843 | rtx plus_expr; | |
1844 | ||
1845 | init_costs_to_max (&mincst); | |
d51102f3 | 1846 | get_full_set_rtx_cost (pat, &oldcst); |
22939744 BS |
1847 | |
1848 | plus_expr = gen_rtx_PLUS (GET_MODE (reg), reg, const0_rtx); | |
1849 | SET_SRC (pat) = plus_expr; | |
7beb0596 JZ |
1850 | |
1851 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1e047eed | 1852 | if (move2add_valid_value_p (i, mode) |
7beb0596 JZ |
1853 | && reg_base_reg[i] < 0 |
1854 | && reg_symbol_ref[i] != NULL_RTX | |
1855 | && rtx_equal_p (sym, reg_symbol_ref[i])) | |
1856 | { | |
e15eb172 | 1857 | rtx new_src = gen_int_mode (UINTVAL (off) - reg_offset[i], |
7beb0596 JZ |
1858 | GET_MODE (reg)); |
1859 | /* (set (reg) (plus (reg) (const_int 0))) is not canonical; | |
1860 | use (set (reg) (reg)) instead. | |
1861 | We don't delete this insn, nor do we convert it into a | |
1862 | note, to avoid losing register notes or the return | |
1863 | value flag. jump2 already knows how to get rid of | |
1864 | no-op moves. */ | |
1865 | if (new_src == const0_rtx) | |
1866 | { | |
22939744 | 1867 | init_costs_to_zero (&mincst); |
7beb0596 JZ |
1868 | min_regno = i; |
1869 | break; | |
1870 | } | |
1871 | else | |
1872 | { | |
22939744 | 1873 | XEXP (plus_expr, 1) = new_src; |
d51102f3 | 1874 | get_full_set_rtx_cost (pat, &newcst); |
22939744 BS |
1875 | |
1876 | if (costs_lt_p (&newcst, &mincst, speed)) | |
7beb0596 | 1877 | { |
22939744 | 1878 | mincst = newcst; |
7beb0596 JZ |
1879 | min_regno = i; |
1880 | } | |
1881 | } | |
1882 | } | |
22939744 | 1883 | SET_SRC (pat) = src; |
7beb0596 | 1884 | |
22939744 | 1885 | if (costs_lt_p (&mincst, &oldcst, speed)) |
7beb0596 JZ |
1886 | { |
1887 | rtx tem; | |
1888 | ||
1889 | tem = gen_rtx_REG (GET_MODE (reg), min_regno); | |
1890 | if (i != min_regno) | |
1891 | { | |
e15eb172 | 1892 | rtx new_src = gen_int_mode (UINTVAL (off) - reg_offset[min_regno], |
7beb0596 JZ |
1893 | GET_MODE (reg)); |
1894 | tem = gen_rtx_PLUS (GET_MODE (reg), tem, new_src); | |
1895 | } | |
dc0d5a57 BS |
1896 | if (validate_change (insn, &SET_SRC (pat), tem, 0)) |
1897 | changed = true; | |
7beb0596 JZ |
1898 | } |
1899 | reg_set_luid[regno] = move2add_luid; | |
7894bc6b | 1900 | move2add_record_sym_value (reg, sym, off); |
dc0d5a57 | 1901 | return changed; |
7beb0596 JZ |
1902 | } |
1903 | ||
dc0d5a57 BS |
1904 | /* Convert move insns with constant inputs to additions if they are cheaper. |
1905 | Return true if any changes were made. */ | |
1906 | static bool | |
f90af2e0 | 1907 | reload_cse_move2add (rtx_insn *first) |
15e35479 KH |
1908 | { |
1909 | int i; | |
f90af2e0 | 1910 | rtx_insn *insn; |
dc0d5a57 | 1911 | bool changed = false; |
15e35479 KH |
1912 | |
1913 | for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--) | |
7beb0596 JZ |
1914 | { |
1915 | reg_set_luid[i] = 0; | |
1916 | reg_offset[i] = 0; | |
1917 | reg_base_reg[i] = 0; | |
1918 | reg_symbol_ref[i] = NULL_RTX; | |
1919 | reg_mode[i] = VOIDmode; | |
1920 | } | |
15e35479 KH |
1921 | |
1922 | move2add_last_label_luid = 0; | |
1923 | move2add_luid = 2; | |
1924 | for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++) | |
1925 | { | |
1926 | rtx pat, note; | |
1927 | ||
4b4bf941 | 1928 | if (LABEL_P (insn)) |
15e35479 KH |
1929 | { |
1930 | move2add_last_label_luid = move2add_luid; | |
1931 | /* We're going to increment move2add_luid twice after a | |
1932 | label, so that we can use move2add_last_label_luid + 1 as | |
1933 | the luid for constants. */ | |
1934 | move2add_luid++; | |
1935 | continue; | |
1936 | } | |
1937 | if (! INSN_P (insn)) | |
1938 | continue; | |
1939 | pat = PATTERN (insn); | |
1940 | /* For simplicity, we only perform this optimization on | |
1941 | straightforward SETs. */ | |
1e047eed | 1942 | scalar_int_mode mode; |
15e35479 | 1943 | if (GET_CODE (pat) == SET |
1e047eed RS |
1944 | && REG_P (SET_DEST (pat)) |
1945 | && is_a <scalar_int_mode> (GET_MODE (SET_DEST (pat)), &mode)) | |
15e35479 KH |
1946 | { |
1947 | rtx reg = SET_DEST (pat); | |
1948 | int regno = REGNO (reg); | |
1949 | rtx src = SET_SRC (pat); | |
1950 | ||
1951 | /* Check if we have valid information on the contents of this | |
1952 | register in the mode of REG. */ | |
1e047eed | 1953 | if (move2add_valid_value_p (regno, mode) |
6fb5fa3c | 1954 | && dbg_cnt (cse2_move2add)) |
15e35479 KH |
1955 | { |
1956 | /* Try to transform (set (REGX) (CONST_INT A)) | |
1957 | ... | |
1958 | (set (REGX) (CONST_INT B)) | |
1959 | to | |
1960 | (set (REGX) (CONST_INT A)) | |
1961 | ... | |
1962 | (set (REGX) (plus (REGX) (CONST_INT B-A))) | |
1963 | or | |
1964 | (set (REGX) (CONST_INT A)) | |
1965 | ... | |
1966 | (set (STRICT_LOW_PART (REGX)) (CONST_INT B)) | |
1967 | */ | |
1968 | ||
7beb0596 JZ |
1969 | if (CONST_INT_P (src) |
1970 | && reg_base_reg[regno] < 0 | |
1971 | && reg_symbol_ref[regno] == NULL_RTX) | |
15e35479 | 1972 | { |
1e047eed RS |
1973 | changed |= move2add_use_add2_insn (mode, reg, NULL_RTX, |
1974 | src, insn); | |
15e35479 KH |
1975 | continue; |
1976 | } | |
1977 | ||
1978 | /* Try to transform (set (REGX) (REGY)) | |
1979 | (set (REGX) (PLUS (REGX) (CONST_INT A))) | |
1980 | ... | |
1981 | (set (REGX) (REGY)) | |
1982 | (set (REGX) (PLUS (REGX) (CONST_INT B))) | |
1983 | to | |
1984 | (set (REGX) (REGY)) | |
1985 | (set (REGX) (PLUS (REGX) (CONST_INT A))) | |
1986 | ... | |
1987 | (set (REGX) (plus (REGX) (CONST_INT B-A))) */ | |
f8cfc6aa | 1988 | else if (REG_P (src) |
15e35479 KH |
1989 | && reg_set_luid[regno] == reg_set_luid[REGNO (src)] |
1990 | && reg_base_reg[regno] == reg_base_reg[REGNO (src)] | |
1e047eed | 1991 | && move2add_valid_value_p (REGNO (src), mode)) |
15e35479 | 1992 | { |
f90af2e0 | 1993 | rtx_insn *next = next_nonnote_nondebug_insn (insn); |
15e35479 KH |
1994 | rtx set = NULL_RTX; |
1995 | if (next) | |
1996 | set = single_set (next); | |
1997 | if (set | |
1998 | && SET_DEST (set) == reg | |
1999 | && GET_CODE (SET_SRC (set)) == PLUS | |
2000 | && XEXP (SET_SRC (set), 0) == reg | |
481683e1 | 2001 | && CONST_INT_P (XEXP (SET_SRC (set), 1))) |
15e35479 KH |
2002 | { |
2003 | rtx src3 = XEXP (SET_SRC (set), 1); | |
e15eb172 | 2004 | unsigned HOST_WIDE_INT added_offset = UINTVAL (src3); |
15e35479 KH |
2005 | HOST_WIDE_INT base_offset = reg_offset[REGNO (src)]; |
2006 | HOST_WIDE_INT regno_offset = reg_offset[regno]; | |
2007 | rtx new_src = | |
bb80db7b KH |
2008 | gen_int_mode (added_offset |
2009 | + base_offset | |
2010 | - regno_offset, | |
1e047eed | 2011 | mode); |
f40751dd JH |
2012 | bool success = false; |
2013 | bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); | |
15e35479 KH |
2014 | |
2015 | if (new_src == const0_rtx) | |
2016 | /* See above why we create (set (reg) (reg)) here. */ | |
2017 | success | |
2018 | = validate_change (next, &SET_SRC (set), reg, 0); | |
22939744 | 2019 | else |
15e35479 | 2020 | { |
22939744 BS |
2021 | rtx old_src = SET_SRC (set); |
2022 | struct full_rtx_costs oldcst, newcst; | |
1e047eed | 2023 | rtx tem = gen_rtx_PLUS (mode, reg, new_src); |
22939744 | 2024 | |
d51102f3 | 2025 | get_full_set_rtx_cost (set, &oldcst); |
22939744 | 2026 | SET_SRC (set) = tem; |
1e047eed | 2027 | get_full_set_src_cost (tem, mode, &newcst); |
22939744 BS |
2028 | SET_SRC (set) = old_src; |
2029 | costs_add_n_insns (&oldcst, 1); | |
2030 | ||
2031 | if (costs_lt_p (&newcst, &oldcst, speed) | |
2032 | && have_add2_insn (reg, new_src)) | |
2033 | { | |
f7df4a84 | 2034 | rtx newpat = gen_rtx_SET (reg, tem); |
22939744 BS |
2035 | success |
2036 | = validate_change (next, &PATTERN (next), | |
2037 | newpat, 0); | |
2038 | } | |
15e35479 KH |
2039 | } |
2040 | if (success) | |
2041 | delete_insn (insn); | |
dc0d5a57 | 2042 | changed |= success; |
15e35479 | 2043 | insn = next; |
7894bc6b JR |
2044 | move2add_record_mode (reg); |
2045 | reg_offset[regno] | |
2046 | = trunc_int_for_mode (added_offset + base_offset, | |
1e047eed | 2047 | mode); |
15e35479 KH |
2048 | continue; |
2049 | } | |
2050 | } | |
2051 | } | |
7beb0596 JZ |
2052 | |
2053 | /* Try to transform | |
2054 | (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A)))) | |
2055 | ... | |
2056 | (set (REGY) (CONST (PLUS (SYMBOL_REF) (CONST_INT B)))) | |
2057 | to | |
2058 | (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A)))) | |
2059 | ... | |
2060 | (set (REGY) (CONST (PLUS (REGX) (CONST_INT B-A)))) */ | |
2061 | if ((GET_CODE (src) == SYMBOL_REF | |
2062 | || (GET_CODE (src) == CONST | |
2063 | && GET_CODE (XEXP (src, 0)) == PLUS | |
2064 | && GET_CODE (XEXP (XEXP (src, 0), 0)) == SYMBOL_REF | |
2065 | && CONST_INT_P (XEXP (XEXP (src, 0), 1)))) | |
2066 | && dbg_cnt (cse2_move2add)) | |
2067 | { | |
2068 | rtx sym, off; | |
2069 | ||
2070 | if (GET_CODE (src) == SYMBOL_REF) | |
2071 | { | |
2072 | sym = src; | |
2073 | off = const0_rtx; | |
2074 | } | |
2075 | else | |
2076 | { | |
2077 | sym = XEXP (XEXP (src, 0), 0); | |
2078 | off = XEXP (XEXP (src, 0), 1); | |
2079 | } | |
2080 | ||
2081 | /* If the reg already contains the value which is sum of | |
2082 | sym and some constant value, we can use an add2 insn. */ | |
1e047eed | 2083 | if (move2add_valid_value_p (regno, mode) |
7beb0596 JZ |
2084 | && reg_base_reg[regno] < 0 |
2085 | && reg_symbol_ref[regno] != NULL_RTX | |
2086 | && rtx_equal_p (sym, reg_symbol_ref[regno])) | |
1e047eed | 2087 | changed |= move2add_use_add2_insn (mode, reg, sym, off, insn); |
7beb0596 JZ |
2088 | |
2089 | /* Otherwise, we have to find a register whose value is sum | |
2090 | of sym and some constant value. */ | |
2091 | else | |
1e047eed | 2092 | changed |= move2add_use_add3_insn (mode, reg, sym, off, insn); |
7beb0596 JZ |
2093 | |
2094 | continue; | |
2095 | } | |
15e35479 KH |
2096 | } |
2097 | ||
2098 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
2099 | { | |
2100 | if (REG_NOTE_KIND (note) == REG_INC | |
f8cfc6aa | 2101 | && REG_P (XEXP (note, 0))) |
15e35479 KH |
2102 | { |
2103 | /* Reset the information about this register. */ | |
2104 | int regno = REGNO (XEXP (note, 0)); | |
2105 | if (regno < FIRST_PSEUDO_REGISTER) | |
7894bc6b JR |
2106 | { |
2107 | move2add_record_mode (XEXP (note, 0)); | |
2108 | reg_mode[regno] = VOIDmode; | |
2109 | } | |
15e35479 KH |
2110 | } |
2111 | } | |
70b55b25 JJ |
2112 | |
2113 | /* There are no REG_INC notes for SP autoinc. */ | |
2114 | subrtx_var_iterator::array_type array; | |
2115 | FOR_EACH_SUBRTX_VAR (iter, array, PATTERN (insn), NONCONST) | |
2116 | { | |
2117 | rtx mem = *iter; | |
2118 | if (mem | |
2119 | && MEM_P (mem) | |
2120 | && GET_RTX_CLASS (GET_CODE (XEXP (mem, 0))) == RTX_AUTOINC) | |
2121 | { | |
2122 | if (XEXP (XEXP (mem, 0), 0) == stack_pointer_rtx) | |
2123 | reg_mode[STACK_POINTER_REGNUM] = VOIDmode; | |
2124 | } | |
2125 | } | |
2126 | ||
e8448ba5 | 2127 | note_stores (insn, move2add_note_store, insn); |
15e35479 KH |
2128 | |
2129 | /* If INSN is a conditional branch, we try to extract an | |
2130 | implicit set out of it. */ | |
c4cdb8e1 | 2131 | if (any_condjump_p (insn)) |
15e35479 KH |
2132 | { |
2133 | rtx cnd = fis_get_condition (insn); | |
2134 | ||
2135 | if (cnd != NULL_RTX | |
2136 | && GET_CODE (cnd) == NE | |
f8cfc6aa | 2137 | && REG_P (XEXP (cnd, 0)) |
c4cdb8e1 | 2138 | && !reg_set_p (XEXP (cnd, 0), insn) |
15e35479 KH |
2139 | /* The following two checks, which are also in |
2140 | move2add_note_store, are intended to reduce the | |
2141 | number of calls to gen_rtx_SET to avoid memory | |
2142 | allocation if possible. */ | |
2143 | && SCALAR_INT_MODE_P (GET_MODE (XEXP (cnd, 0))) | |
dc8afb70 | 2144 | && REG_NREGS (XEXP (cnd, 0)) == 1 |
481683e1 | 2145 | && CONST_INT_P (XEXP (cnd, 1))) |
15e35479 KH |
2146 | { |
2147 | rtx implicit_set = | |
f7df4a84 | 2148 | gen_rtx_SET (XEXP (cnd, 0), XEXP (cnd, 1)); |
7beb0596 | 2149 | move2add_note_store (SET_DEST (implicit_set), implicit_set, insn); |
15e35479 KH |
2150 | } |
2151 | } | |
2152 | ||
2153 | /* If this is a CALL_INSN, all call used registers are stored with | |
2154 | unknown values. */ | |
4b4bf941 | 2155 | if (CALL_P (insn)) |
15e35479 | 2156 | { |
3df28f00 | 2157 | function_abi callee_abi = insn_callee_abi (insn); |
15e35479 | 2158 | for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--) |
3df28f00 RS |
2159 | if (reg_mode[i] != VOIDmode |
2160 | && reg_mode[i] != BLKmode | |
2161 | && callee_abi.clobbers_reg_p (reg_mode[i], i)) | |
2162 | /* Reset the information about this register. */ | |
2163 | reg_mode[i] = VOIDmode; | |
15e35479 KH |
2164 | } |
2165 | } | |
dc0d5a57 | 2166 | return changed; |
15e35479 KH |
2167 | } |
2168 | ||
7beb0596 JZ |
2169 | /* SET is a SET or CLOBBER that sets DST. DATA is the insn which |
2170 | contains SET. | |
15e35479 KH |
2171 | Update reg_set_luid, reg_offset and reg_base_reg accordingly. |
2172 | Called from reload_cse_move2add via note_stores. */ | |
2173 | ||
2174 | static void | |
7beb0596 | 2175 | move2add_note_store (rtx dst, const_rtx set, void *data) |
15e35479 | 2176 | { |
f90af2e0 | 2177 | rtx_insn *insn = (rtx_insn *) data; |
15e35479 | 2178 | unsigned int regno = 0; |
b0567726 | 2179 | scalar_int_mode mode; |
15e35479 | 2180 | |
7894bc6b JR |
2181 | if (GET_CODE (dst) == SUBREG) |
2182 | regno = subreg_regno (dst); | |
2183 | else if (REG_P (dst)) | |
2184 | regno = REGNO (dst); | |
2185 | else | |
2186 | return; | |
15e35479 | 2187 | |
b0567726 RS |
2188 | if (!is_a <scalar_int_mode> (GET_MODE (dst), &mode)) |
2189 | goto invalidate; | |
2190 | ||
2191 | if (GET_CODE (set) == SET) | |
7beb0596 JZ |
2192 | { |
2193 | rtx note, sym = NULL_RTX; | |
7894bc6b | 2194 | rtx off; |
7beb0596 JZ |
2195 | |
2196 | note = find_reg_equal_equiv_note (insn); | |
2197 | if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF) | |
2198 | { | |
2199 | sym = XEXP (note, 0); | |
7894bc6b | 2200 | off = const0_rtx; |
7beb0596 JZ |
2201 | } |
2202 | else if (note && GET_CODE (XEXP (note, 0)) == CONST | |
2203 | && GET_CODE (XEXP (XEXP (note, 0), 0)) == PLUS | |
2204 | && GET_CODE (XEXP (XEXP (XEXP (note, 0), 0), 0)) == SYMBOL_REF | |
2205 | && CONST_INT_P (XEXP (XEXP (XEXP (note, 0), 0), 1))) | |
2206 | { | |
2207 | sym = XEXP (XEXP (XEXP (note, 0), 0), 0); | |
7894bc6b | 2208 | off = XEXP (XEXP (XEXP (note, 0), 0), 1); |
7beb0596 JZ |
2209 | } |
2210 | ||
2211 | if (sym != NULL_RTX) | |
2212 | { | |
7894bc6b | 2213 | move2add_record_sym_value (dst, sym, off); |
7beb0596 JZ |
2214 | return; |
2215 | } | |
2216 | } | |
2217 | ||
b0567726 | 2218 | if (GET_CODE (set) == SET |
15e35479 | 2219 | && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT |
15e35479 KH |
2220 | && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART) |
2221 | { | |
2222 | rtx src = SET_SRC (set); | |
2223 | rtx base_reg; | |
e15eb172 | 2224 | unsigned HOST_WIDE_INT offset; |
15e35479 | 2225 | int base_regno; |
15e35479 KH |
2226 | |
2227 | switch (GET_CODE (src)) | |
2228 | { | |
2229 | case PLUS: | |
f8cfc6aa | 2230 | if (REG_P (XEXP (src, 0))) |
15e35479 KH |
2231 | { |
2232 | base_reg = XEXP (src, 0); | |
2233 | ||
481683e1 | 2234 | if (CONST_INT_P (XEXP (src, 1))) |
e15eb172 | 2235 | offset = UINTVAL (XEXP (src, 1)); |
f8cfc6aa | 2236 | else if (REG_P (XEXP (src, 1)) |
7894bc6b | 2237 | && move2add_valid_value_p (REGNO (XEXP (src, 1)), mode)) |
15e35479 | 2238 | { |
27d5e204 CLT |
2239 | if (reg_base_reg[REGNO (XEXP (src, 1))] < 0 |
2240 | && reg_symbol_ref[REGNO (XEXP (src, 1))] == NULL_RTX) | |
15e35479 KH |
2241 | offset = reg_offset[REGNO (XEXP (src, 1))]; |
2242 | /* Maybe the first register is known to be a | |
2243 | constant. */ | |
7894bc6b | 2244 | else if (move2add_valid_value_p (REGNO (base_reg), mode) |
27d5e204 CLT |
2245 | && reg_base_reg[REGNO (base_reg)] < 0 |
2246 | && reg_symbol_ref[REGNO (base_reg)] == NULL_RTX) | |
15e35479 KH |
2247 | { |
2248 | offset = reg_offset[REGNO (base_reg)]; | |
2249 | base_reg = XEXP (src, 1); | |
2250 | } | |
2251 | else | |
2252 | goto invalidate; | |
2253 | } | |
2254 | else | |
2255 | goto invalidate; | |
2256 | ||
2257 | break; | |
2258 | } | |
2259 | ||
2260 | goto invalidate; | |
2261 | ||
2262 | case REG: | |
2263 | base_reg = src; | |
2264 | offset = 0; | |
2265 | break; | |
2266 | ||
2267 | case CONST_INT: | |
2268 | /* Start tracking the register as a constant. */ | |
2269 | reg_base_reg[regno] = -1; | |
7beb0596 | 2270 | reg_symbol_ref[regno] = NULL_RTX; |
15e35479 KH |
2271 | reg_offset[regno] = INTVAL (SET_SRC (set)); |
2272 | /* We assign the same luid to all registers set to constants. */ | |
2273 | reg_set_luid[regno] = move2add_last_label_luid + 1; | |
7894bc6b | 2274 | move2add_record_mode (dst); |
15e35479 KH |
2275 | return; |
2276 | ||
2277 | default: | |
7894bc6b | 2278 | goto invalidate; |
15e35479 KH |
2279 | } |
2280 | ||
2281 | base_regno = REGNO (base_reg); | |
2282 | /* If information about the base register is not valid, set it | |
2283 | up as a new base register, pretending its value is known | |
2284 | starting from the current insn. */ | |
7894bc6b | 2285 | if (!move2add_valid_value_p (base_regno, mode)) |
15e35479 KH |
2286 | { |
2287 | reg_base_reg[base_regno] = base_regno; | |
7beb0596 | 2288 | reg_symbol_ref[base_regno] = NULL_RTX; |
15e35479 KH |
2289 | reg_offset[base_regno] = 0; |
2290 | reg_set_luid[base_regno] = move2add_luid; | |
7894bc6b JR |
2291 | gcc_assert (GET_MODE (base_reg) == mode); |
2292 | move2add_record_mode (base_reg); | |
15e35479 | 2293 | } |
15e35479 KH |
2294 | |
2295 | /* Copy base information from our base register. */ | |
2296 | reg_set_luid[regno] = reg_set_luid[base_regno]; | |
2297 | reg_base_reg[regno] = reg_base_reg[base_regno]; | |
7beb0596 | 2298 | reg_symbol_ref[regno] = reg_symbol_ref[base_regno]; |
15e35479 KH |
2299 | |
2300 | /* Compute the sum of the offsets or constants. */ | |
7894bc6b JR |
2301 | reg_offset[regno] |
2302 | = trunc_int_for_mode (offset + reg_offset[base_regno], mode); | |
2303 | ||
2304 | move2add_record_mode (dst); | |
15e35479 KH |
2305 | } |
2306 | else | |
2307 | { | |
7894bc6b JR |
2308 | invalidate: |
2309 | /* Invalidate the contents of the register. */ | |
2310 | move2add_record_mode (dst); | |
2311 | reg_mode[regno] = VOIDmode; | |
15e35479 KH |
2312 | } |
2313 | } | |
ef330312 | 2314 | \f |
27a4cd48 DM |
2315 | namespace { |
2316 | ||
2317 | const pass_data pass_data_postreload_cse = | |
ef330312 | 2318 | { |
27a4cd48 DM |
2319 | RTL_PASS, /* type */ |
2320 | "postreload", /* name */ | |
2321 | OPTGROUP_NONE, /* optinfo_flags */ | |
27a4cd48 DM |
2322 | TV_RELOAD_CSE_REGS, /* tv_id */ |
2323 | 0, /* properties_required */ | |
2324 | 0, /* properties_provided */ | |
2325 | 0, /* properties_destroyed */ | |
2326 | 0, /* todo_flags_start */ | |
3bea341f | 2327 | TODO_df_finish, /* todo_flags_finish */ |
ef330312 | 2328 | }; |
27a4cd48 DM |
2329 | |
2330 | class pass_postreload_cse : public rtl_opt_pass | |
2331 | { | |
2332 | public: | |
c3284718 RS |
2333 | pass_postreload_cse (gcc::context *ctxt) |
2334 | : rtl_opt_pass (pass_data_postreload_cse, ctxt) | |
27a4cd48 DM |
2335 | {} |
2336 | ||
2337 | /* opt_pass methods: */ | |
1a3d085c TS |
2338 | virtual bool gate (function *) { return (optimize > 0 && reload_completed); } |
2339 | ||
be55bfe6 | 2340 | virtual unsigned int execute (function *); |
27a4cd48 DM |
2341 | |
2342 | }; // class pass_postreload_cse | |
2343 | ||
be55bfe6 TS |
2344 | unsigned int |
2345 | pass_postreload_cse::execute (function *fun) | |
2346 | { | |
2347 | if (!dbg_cnt (postreload_cse)) | |
2348 | return 0; | |
2349 | ||
2350 | /* Do a very simple CSE pass over just the hard registers. */ | |
2351 | reload_cse_regs (get_insns ()); | |
2352 | /* Reload_cse_regs can eliminate potentially-trapping MEMs. | |
2353 | Remove any EH edges associated with them. */ | |
2354 | if (fun->can_throw_non_call_exceptions | |
2355 | && purge_all_dead_edges ()) | |
2356 | cleanup_cfg (0); | |
2357 | ||
2358 | return 0; | |
2359 | } | |
2360 | ||
27a4cd48 DM |
2361 | } // anon namespace |
2362 | ||
2363 | rtl_opt_pass * | |
2364 | make_pass_postreload_cse (gcc::context *ctxt) | |
2365 | { | |
2366 | return new pass_postreload_cse (ctxt); | |
2367 | } |