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8f8cadbc | 1 | /* Perform simple optimizations to clean up the result of reload. |
3072d30e | 2 | Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, |
35af0188 | 3 | 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, |
fd813641 | 4 | 2010, 2011 Free Software Foundation, Inc. |
8f8cadbc | 5 | |
6 | This file is part of GCC. | |
7 | ||
8 | GCC is free software; you can redistribute it and/or modify it under | |
9 | the terms of the GNU General Public License as published by the Free | |
8c4c00c1 | 10 | Software Foundation; either version 3, or (at your option) any later |
8f8cadbc | 11 | version. |
12 | ||
13 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
14 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
8c4c00c1 | 19 | along with GCC; see the file COPYING3. If not see |
20 | <http://www.gnu.org/licenses/>. */ | |
8f8cadbc | 21 | |
22 | #include "config.h" | |
23 | #include "system.h" | |
24 | #include "coretypes.h" | |
25 | #include "tm.h" | |
26 | ||
27 | #include "machmode.h" | |
28 | #include "hard-reg-set.h" | |
29 | #include "rtl.h" | |
30 | #include "tm_p.h" | |
31 | #include "obstack.h" | |
32 | #include "insn-config.h" | |
33 | #include "flags.h" | |
34 | #include "function.h" | |
35 | #include "expr.h" | |
36 | #include "optabs.h" | |
37 | #include "regs.h" | |
38 | #include "basic-block.h" | |
39 | #include "reload.h" | |
40 | #include "recog.h" | |
8f8cadbc | 41 | #include "cselib.h" |
0b205f4c | 42 | #include "diagnostic-core.h" |
8f8cadbc | 43 | #include "except.h" |
44 | #include "tree.h" | |
727047d0 | 45 | #include "target.h" |
77fce4cd | 46 | #include "timevar.h" |
47 | #include "tree-pass.h" | |
3072d30e | 48 | #include "df.h" |
49 | #include "dbgcnt.h" | |
8f8cadbc | 50 | |
3ad4992f | 51 | static int reload_cse_noop_set_p (rtx); |
52 | static void reload_cse_simplify (rtx, rtx); | |
53 | static void reload_cse_regs_1 (rtx); | |
54 | static int reload_cse_simplify_set (rtx, rtx); | |
55 | static int reload_cse_simplify_operands (rtx, rtx); | |
8f8cadbc | 56 | |
3ad4992f | 57 | static void reload_combine (void); |
d83ccc81 | 58 | static void reload_combine_note_use (rtx *, rtx, int, rtx); |
81a410b1 | 59 | static void reload_combine_note_store (rtx, const_rtx, void *); |
8f8cadbc | 60 | |
d83ccc81 | 61 | static bool reload_cse_move2add (rtx); |
81a410b1 | 62 | static void move2add_note_store (rtx, const_rtx, void *); |
8f8cadbc | 63 | |
64 | /* Call cse / combine like post-reload optimization phases. | |
65 | FIRST is the first instruction. */ | |
98799adc | 66 | |
67 | static void | |
3ad4992f | 68 | reload_cse_regs (rtx first ATTRIBUTE_UNUSED) |
8f8cadbc | 69 | { |
d83ccc81 | 70 | bool moves_converted; |
8f8cadbc | 71 | reload_cse_regs_1 (first); |
72 | reload_combine (); | |
d83ccc81 | 73 | moves_converted = reload_cse_move2add (first); |
8f8cadbc | 74 | if (flag_expensive_optimizations) |
d83ccc81 | 75 | { |
76 | if (moves_converted) | |
77 | reload_combine (); | |
78 | reload_cse_regs_1 (first); | |
79 | } | |
8f8cadbc | 80 | } |
81 | ||
82 | /* See whether a single set SET is a noop. */ | |
83 | static int | |
3ad4992f | 84 | reload_cse_noop_set_p (rtx set) |
8f8cadbc | 85 | { |
86 | if (cselib_reg_set_mode (SET_DEST (set)) != GET_MODE (SET_DEST (set))) | |
87 | return 0; | |
88 | ||
89 | return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set)); | |
90 | } | |
91 | ||
92 | /* Try to simplify INSN. */ | |
93 | static void | |
3ad4992f | 94 | reload_cse_simplify (rtx insn, rtx testreg) |
8f8cadbc | 95 | { |
96 | rtx body = PATTERN (insn); | |
97 | ||
98 | if (GET_CODE (body) == SET) | |
99 | { | |
100 | int count = 0; | |
101 | ||
102 | /* Simplify even if we may think it is a no-op. | |
103 | We may think a memory load of a value smaller than WORD_SIZE | |
104 | is redundant because we haven't taken into account possible | |
105 | implicit extension. reload_cse_simplify_set() will bring | |
106 | this out, so it's safer to simplify before we delete. */ | |
107 | count += reload_cse_simplify_set (body, insn); | |
108 | ||
109 | if (!count && reload_cse_noop_set_p (body)) | |
110 | { | |
111 | rtx value = SET_DEST (body); | |
112 | if (REG_P (value) | |
113 | && ! REG_FUNCTION_VALUE_P (value)) | |
114 | value = 0; | |
5a9ecd4a | 115 | if (check_for_inc_dec (insn)) |
116 | delete_insn_and_edges (insn); | |
8f8cadbc | 117 | return; |
118 | } | |
119 | ||
120 | if (count > 0) | |
121 | apply_change_group (); | |
122 | else | |
123 | reload_cse_simplify_operands (insn, testreg); | |
124 | } | |
125 | else if (GET_CODE (body) == PARALLEL) | |
126 | { | |
127 | int i; | |
128 | int count = 0; | |
129 | rtx value = NULL_RTX; | |
130 | ||
17883489 | 131 | /* Registers mentioned in the clobber list for an asm cannot be reused |
132 | within the body of the asm. Invalidate those registers now so that | |
133 | we don't try to substitute values for them. */ | |
134 | if (asm_noperands (body) >= 0) | |
135 | { | |
136 | for (i = XVECLEN (body, 0) - 1; i >= 0; --i) | |
137 | { | |
138 | rtx part = XVECEXP (body, 0, i); | |
139 | if (GET_CODE (part) == CLOBBER && REG_P (XEXP (part, 0))) | |
140 | cselib_invalidate_rtx (XEXP (part, 0)); | |
141 | } | |
142 | } | |
143 | ||
8f8cadbc | 144 | /* If every action in a PARALLEL is a noop, we can delete |
145 | the entire PARALLEL. */ | |
146 | for (i = XVECLEN (body, 0) - 1; i >= 0; --i) | |
147 | { | |
148 | rtx part = XVECEXP (body, 0, i); | |
149 | if (GET_CODE (part) == SET) | |
150 | { | |
151 | if (! reload_cse_noop_set_p (part)) | |
152 | break; | |
153 | if (REG_P (SET_DEST (part)) | |
154 | && REG_FUNCTION_VALUE_P (SET_DEST (part))) | |
155 | { | |
156 | if (value) | |
157 | break; | |
158 | value = SET_DEST (part); | |
159 | } | |
160 | } | |
161 | else if (GET_CODE (part) != CLOBBER) | |
162 | break; | |
163 | } | |
164 | ||
165 | if (i < 0) | |
166 | { | |
5a9ecd4a | 167 | if (check_for_inc_dec (insn)) |
168 | delete_insn_and_edges (insn); | |
8f8cadbc | 169 | /* We're done with this insn. */ |
170 | return; | |
171 | } | |
172 | ||
173 | /* It's not a no-op, but we can try to simplify it. */ | |
174 | for (i = XVECLEN (body, 0) - 1; i >= 0; --i) | |
175 | if (GET_CODE (XVECEXP (body, 0, i)) == SET) | |
176 | count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn); | |
177 | ||
178 | if (count > 0) | |
179 | apply_change_group (); | |
180 | else | |
181 | reload_cse_simplify_operands (insn, testreg); | |
182 | } | |
183 | } | |
184 | ||
185 | /* Do a very simple CSE pass over the hard registers. | |
186 | ||
187 | This function detects no-op moves where we happened to assign two | |
188 | different pseudo-registers to the same hard register, and then | |
189 | copied one to the other. Reload will generate a useless | |
190 | instruction copying a register to itself. | |
191 | ||
192 | This function also detects cases where we load a value from memory | |
193 | into two different registers, and (if memory is more expensive than | |
194 | registers) changes it to simply copy the first register into the | |
195 | second register. | |
196 | ||
197 | Another optimization is performed that scans the operands of each | |
198 | instruction to see whether the value is already available in a | |
199 | hard register. It then replaces the operand with the hard register | |
200 | if possible, much like an optional reload would. */ | |
201 | ||
202 | static void | |
3ad4992f | 203 | reload_cse_regs_1 (rtx first) |
8f8cadbc | 204 | { |
201f6961 | 205 | rtx insn; |
8f8cadbc | 206 | rtx testreg = gen_rtx_REG (VOIDmode, -1); |
207 | ||
35af0188 | 208 | cselib_init (CSELIB_RECORD_MEMORY); |
8f8cadbc | 209 | init_alias_analysis (); |
210 | ||
201f6961 | 211 | for (insn = first; insn; insn = NEXT_INSN (insn)) |
8f8cadbc | 212 | { |
213 | if (INSN_P (insn)) | |
214 | reload_cse_simplify (insn, testreg); | |
215 | ||
216 | cselib_process_insn (insn); | |
217 | } | |
218 | ||
219 | /* Clean up. */ | |
220 | end_alias_analysis (); | |
221 | cselib_finish (); | |
222 | } | |
223 | ||
224 | /* Try to simplify a single SET instruction. SET is the set pattern. | |
225 | INSN is the instruction it came from. | |
226 | This function only handles one case: if we set a register to a value | |
227 | which is not a register, we try to find that value in some other register | |
228 | and change the set into a register copy. */ | |
229 | ||
230 | static int | |
3ad4992f | 231 | reload_cse_simplify_set (rtx set, rtx insn) |
8f8cadbc | 232 | { |
233 | int did_change = 0; | |
234 | int dreg; | |
235 | rtx src; | |
ade444a4 | 236 | reg_class_t dclass; |
8f8cadbc | 237 | int old_cost; |
238 | cselib_val *val; | |
239 | struct elt_loc_list *l; | |
240 | #ifdef LOAD_EXTEND_OP | |
21f1e711 | 241 | enum rtx_code extend_op = UNKNOWN; |
8f8cadbc | 242 | #endif |
f529eb25 | 243 | bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); |
8f8cadbc | 244 | |
245 | dreg = true_regnum (SET_DEST (set)); | |
246 | if (dreg < 0) | |
247 | return 0; | |
248 | ||
249 | src = SET_SRC (set); | |
250 | if (side_effects_p (src) || true_regnum (src) >= 0) | |
251 | return 0; | |
252 | ||
253 | dclass = REGNO_REG_CLASS (dreg); | |
254 | ||
255 | #ifdef LOAD_EXTEND_OP | |
256 | /* When replacing a memory with a register, we need to honor assumptions | |
257 | that combine made wrt the contents of sign bits. We'll do this by | |
258 | generating an extend instruction instead of a reg->reg copy. Thus | |
259 | the destination must be a register that we can widen. */ | |
e16ceb8e | 260 | if (MEM_P (src) |
8f8cadbc | 261 | && GET_MODE_BITSIZE (GET_MODE (src)) < BITS_PER_WORD |
21f1e711 | 262 | && (extend_op = LOAD_EXTEND_OP (GET_MODE (src))) != UNKNOWN |
8ad4c111 | 263 | && !REG_P (SET_DEST (set))) |
8f8cadbc | 264 | return 0; |
265 | #endif | |
266 | ||
1f864115 | 267 | val = cselib_lookup (src, GET_MODE (SET_DEST (set)), 0, VOIDmode); |
3be01943 | 268 | if (! val) |
269 | return 0; | |
270 | ||
8f8cadbc | 271 | /* If memory loads are cheaper than register copies, don't change them. */ |
e16ceb8e | 272 | if (MEM_P (src)) |
251a613e | 273 | old_cost = memory_move_cost (GET_MODE (src), dclass, true); |
8ad4c111 | 274 | else if (REG_P (src)) |
e6078fbb | 275 | old_cost = register_move_cost (GET_MODE (src), |
8f8cadbc | 276 | REGNO_REG_CLASS (REGNO (src)), dclass); |
277 | else | |
7013e87c | 278 | old_cost = set_src_cost (src, speed); |
8f8cadbc | 279 | |
8f8cadbc | 280 | for (l = val->locs; l; l = l->next) |
281 | { | |
282 | rtx this_rtx = l->loc; | |
283 | int this_cost; | |
284 | ||
285 | if (CONSTANT_P (this_rtx) && ! references_value_p (this_rtx, 0)) | |
286 | { | |
287 | #ifdef LOAD_EXTEND_OP | |
21f1e711 | 288 | if (extend_op != UNKNOWN) |
8f8cadbc | 289 | { |
290 | HOST_WIDE_INT this_val; | |
291 | ||
292 | /* ??? I'm lazy and don't wish to handle CONST_DOUBLE. Other | |
293 | constants, such as SYMBOL_REF, cannot be extended. */ | |
971ba038 | 294 | if (!CONST_INT_P (this_rtx)) |
8f8cadbc | 295 | continue; |
296 | ||
297 | this_val = INTVAL (this_rtx); | |
298 | switch (extend_op) | |
299 | { | |
300 | case ZERO_EXTEND: | |
301 | this_val &= GET_MODE_MASK (GET_MODE (src)); | |
302 | break; | |
303 | case SIGN_EXTEND: | |
304 | /* ??? In theory we're already extended. */ | |
305 | if (this_val == trunc_int_for_mode (this_val, GET_MODE (src))) | |
306 | break; | |
307 | default: | |
876760f6 | 308 | gcc_unreachable (); |
8f8cadbc | 309 | } |
310 | this_rtx = GEN_INT (this_val); | |
311 | } | |
312 | #endif | |
7013e87c | 313 | this_cost = set_src_cost (this_rtx, speed); |
8f8cadbc | 314 | } |
8ad4c111 | 315 | else if (REG_P (this_rtx)) |
8f8cadbc | 316 | { |
317 | #ifdef LOAD_EXTEND_OP | |
21f1e711 | 318 | if (extend_op != UNKNOWN) |
8f8cadbc | 319 | { |
320 | this_rtx = gen_rtx_fmt_e (extend_op, word_mode, this_rtx); | |
7013e87c | 321 | this_cost = set_src_cost (this_rtx, speed); |
8f8cadbc | 322 | } |
323 | else | |
324 | #endif | |
e6078fbb | 325 | this_cost = register_move_cost (GET_MODE (this_rtx), |
8f8cadbc | 326 | REGNO_REG_CLASS (REGNO (this_rtx)), |
327 | dclass); | |
328 | } | |
329 | else | |
330 | continue; | |
331 | ||
332 | /* If equal costs, prefer registers over anything else. That | |
333 | tends to lead to smaller instructions on some machines. */ | |
334 | if (this_cost < old_cost | |
335 | || (this_cost == old_cost | |
8ad4c111 | 336 | && REG_P (this_rtx) |
337 | && !REG_P (SET_SRC (set)))) | |
8f8cadbc | 338 | { |
339 | #ifdef LOAD_EXTEND_OP | |
340 | if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (set))) < BITS_PER_WORD | |
21f1e711 | 341 | && extend_op != UNKNOWN |
8f8cadbc | 342 | #ifdef CANNOT_CHANGE_MODE_CLASS |
343 | && !CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set)), | |
344 | word_mode, | |
345 | REGNO_REG_CLASS (REGNO (SET_DEST (set)))) | |
346 | #endif | |
347 | ) | |
348 | { | |
349 | rtx wide_dest = gen_rtx_REG (word_mode, REGNO (SET_DEST (set))); | |
350 | ORIGINAL_REGNO (wide_dest) = ORIGINAL_REGNO (SET_DEST (set)); | |
351 | validate_change (insn, &SET_DEST (set), wide_dest, 1); | |
352 | } | |
353 | #endif | |
354 | ||
11d686e2 | 355 | validate_unshare_change (insn, &SET_SRC (set), this_rtx, 1); |
8f8cadbc | 356 | old_cost = this_cost, did_change = 1; |
357 | } | |
358 | } | |
359 | ||
360 | return did_change; | |
361 | } | |
362 | ||
363 | /* Try to replace operands in INSN with equivalent values that are already | |
364 | in registers. This can be viewed as optional reloading. | |
365 | ||
366 | For each non-register operand in the insn, see if any hard regs are | |
367 | known to be equivalent to that operand. Record the alternatives which | |
368 | can accept these hard registers. Among all alternatives, select the | |
369 | ones which are better or equal to the one currently matching, where | |
370 | "better" is in terms of '?' and '!' constraints. Among the remaining | |
371 | alternatives, select the one which replaces most operands with | |
372 | hard registers. */ | |
373 | ||
374 | static int | |
3ad4992f | 375 | reload_cse_simplify_operands (rtx insn, rtx testreg) |
8f8cadbc | 376 | { |
377 | int i, j; | |
378 | ||
379 | /* For each operand, all registers that are equivalent to it. */ | |
380 | HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS]; | |
381 | ||
382 | const char *constraints[MAX_RECOG_OPERANDS]; | |
383 | ||
384 | /* Vector recording how bad an alternative is. */ | |
385 | int *alternative_reject; | |
386 | /* Vector recording how many registers can be introduced by choosing | |
387 | this alternative. */ | |
388 | int *alternative_nregs; | |
389 | /* Array of vectors recording, for each operand and each alternative, | |
390 | which hard register to substitute, or -1 if the operand should be | |
391 | left as it is. */ | |
392 | int *op_alt_regno[MAX_RECOG_OPERANDS]; | |
393 | /* Array of alternatives, sorted in order of decreasing desirability. */ | |
394 | int *alternative_order; | |
395 | ||
396 | extract_insn (insn); | |
397 | ||
398 | if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0) | |
399 | return 0; | |
400 | ||
401 | /* Figure out which alternative currently matches. */ | |
402 | if (! constrain_operands (1)) | |
403 | fatal_insn_not_found (insn); | |
404 | ||
4077bf7a | 405 | alternative_reject = XALLOCAVEC (int, recog_data.n_alternatives); |
406 | alternative_nregs = XALLOCAVEC (int, recog_data.n_alternatives); | |
407 | alternative_order = XALLOCAVEC (int, recog_data.n_alternatives); | |
f0af5a88 | 408 | memset (alternative_reject, 0, recog_data.n_alternatives * sizeof (int)); |
409 | memset (alternative_nregs, 0, recog_data.n_alternatives * sizeof (int)); | |
8f8cadbc | 410 | |
411 | /* For each operand, find out which regs are equivalent. */ | |
412 | for (i = 0; i < recog_data.n_operands; i++) | |
413 | { | |
414 | cselib_val *v; | |
415 | struct elt_loc_list *l; | |
9d9e3c81 | 416 | rtx op; |
8f8cadbc | 417 | |
418 | CLEAR_HARD_REG_SET (equiv_regs[i]); | |
419 | ||
420 | /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem | |
421 | right, so avoid the problem here. Likewise if we have a constant | |
422 | and the insn pattern doesn't tell us the mode we need. */ | |
6d7dc5b9 | 423 | if (LABEL_P (recog_data.operand[i]) |
8f8cadbc | 424 | || (CONSTANT_P (recog_data.operand[i]) |
425 | && recog_data.operand_mode[i] == VOIDmode)) | |
426 | continue; | |
427 | ||
9d9e3c81 | 428 | op = recog_data.operand[i]; |
9d9e3c81 | 429 | #ifdef LOAD_EXTEND_OP |
e16ceb8e | 430 | if (MEM_P (op) |
f018d957 | 431 | && GET_MODE_BITSIZE (GET_MODE (op)) < BITS_PER_WORD |
432 | && LOAD_EXTEND_OP (GET_MODE (op)) != UNKNOWN) | |
9d9e3c81 | 433 | { |
434 | rtx set = single_set (insn); | |
435 | ||
4885b286 | 436 | /* We might have multiple sets, some of which do implicit |
9d9e3c81 | 437 | extension. Punt on this for now. */ |
438 | if (! set) | |
439 | continue; | |
86481e89 | 440 | /* If the destination is also a MEM or a STRICT_LOW_PART, no |
9d9e3c81 | 441 | extension applies. |
442 | Also, if there is an explicit extension, we don't have to | |
443 | worry about an implicit one. */ | |
e16ceb8e | 444 | else if (MEM_P (SET_DEST (set)) |
9d9e3c81 | 445 | || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART |
446 | || GET_CODE (SET_SRC (set)) == ZERO_EXTEND | |
447 | || GET_CODE (SET_SRC (set)) == SIGN_EXTEND) | |
448 | ; /* Continue ordinary processing. */ | |
a091e4f5 | 449 | #ifdef CANNOT_CHANGE_MODE_CLASS |
450 | /* If the register cannot change mode to word_mode, it follows that | |
451 | it cannot have been used in word_mode. */ | |
8ad4c111 | 452 | else if (REG_P (SET_DEST (set)) |
a091e4f5 | 453 | && CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set)), |
454 | word_mode, | |
455 | REGNO_REG_CLASS (REGNO (SET_DEST (set))))) | |
456 | ; /* Continue ordinary processing. */ | |
457 | #endif | |
9d9e3c81 | 458 | /* If this is a straight load, make the extension explicit. */ |
8ad4c111 | 459 | else if (REG_P (SET_DEST (set)) |
9d9e3c81 | 460 | && recog_data.n_operands == 2 |
461 | && SET_SRC (set) == op | |
462 | && SET_DEST (set) == recog_data.operand[1-i]) | |
463 | { | |
464 | validate_change (insn, recog_data.operand_loc[i], | |
f018d957 | 465 | gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (op)), |
9d9e3c81 | 466 | word_mode, op), |
467 | 1); | |
468 | validate_change (insn, recog_data.operand_loc[1-i], | |
469 | gen_rtx_REG (word_mode, REGNO (SET_DEST (set))), | |
470 | 1); | |
471 | if (! apply_change_group ()) | |
472 | return 0; | |
473 | return reload_cse_simplify_operands (insn, testreg); | |
474 | } | |
475 | else | |
476 | /* ??? There might be arithmetic operations with memory that are | |
477 | safe to optimize, but is it worth the trouble? */ | |
478 | continue; | |
479 | } | |
480 | #endif /* LOAD_EXTEND_OP */ | |
017b7047 | 481 | if (side_effects_p (op)) |
482 | continue; | |
1f864115 | 483 | v = cselib_lookup (op, recog_data.operand_mode[i], 0, VOIDmode); |
8f8cadbc | 484 | if (! v) |
485 | continue; | |
486 | ||
487 | for (l = v->locs; l; l = l->next) | |
8ad4c111 | 488 | if (REG_P (l->loc)) |
8f8cadbc | 489 | SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc)); |
490 | } | |
491 | ||
492 | for (i = 0; i < recog_data.n_operands; i++) | |
493 | { | |
494 | enum machine_mode mode; | |
495 | int regno; | |
496 | const char *p; | |
497 | ||
4077bf7a | 498 | op_alt_regno[i] = XALLOCAVEC (int, recog_data.n_alternatives); |
8f8cadbc | 499 | for (j = 0; j < recog_data.n_alternatives; j++) |
500 | op_alt_regno[i][j] = -1; | |
501 | ||
502 | p = constraints[i] = recog_data.constraints[i]; | |
503 | mode = recog_data.operand_mode[i]; | |
504 | ||
505 | /* Add the reject values for each alternative given by the constraints | |
506 | for this operand. */ | |
507 | j = 0; | |
508 | while (*p != '\0') | |
509 | { | |
510 | char c = *p++; | |
511 | if (c == ',') | |
512 | j++; | |
513 | else if (c == '?') | |
514 | alternative_reject[j] += 3; | |
515 | else if (c == '!') | |
516 | alternative_reject[j] += 300; | |
517 | } | |
518 | ||
519 | /* We won't change operands which are already registers. We | |
520 | also don't want to modify output operands. */ | |
521 | regno = true_regnum (recog_data.operand[i]); | |
522 | if (regno >= 0 | |
523 | || constraints[i][0] == '=' | |
524 | || constraints[i][0] == '+') | |
525 | continue; | |
526 | ||
527 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
528 | { | |
b9c74b4d | 529 | enum reg_class rclass = NO_REGS; |
8f8cadbc | 530 | |
531 | if (! TEST_HARD_REG_BIT (equiv_regs[i], regno)) | |
532 | continue; | |
533 | ||
7f1819d3 | 534 | SET_REGNO_RAW (testreg, regno); |
8f8cadbc | 535 | PUT_MODE (testreg, mode); |
536 | ||
537 | /* We found a register equal to this operand. Now look for all | |
538 | alternatives that can accept this register and have not been | |
539 | assigned a register they can use yet. */ | |
540 | j = 0; | |
541 | p = constraints[i]; | |
542 | for (;;) | |
543 | { | |
544 | char c = *p; | |
545 | ||
546 | switch (c) | |
547 | { | |
548 | case '=': case '+': case '?': | |
549 | case '#': case '&': case '!': | |
550 | case '*': case '%': | |
551 | case '0': case '1': case '2': case '3': case '4': | |
552 | case '5': case '6': case '7': case '8': case '9': | |
e9ff93b1 | 553 | case '<': case '>': case 'V': case 'o': |
8f8cadbc | 554 | case 'E': case 'F': case 'G': case 'H': |
555 | case 's': case 'i': case 'n': | |
556 | case 'I': case 'J': case 'K': case 'L': | |
557 | case 'M': case 'N': case 'O': case 'P': | |
e9ff93b1 | 558 | case 'p': case 'X': case TARGET_MEM_CONSTRAINT: |
8f8cadbc | 559 | /* These don't say anything we care about. */ |
560 | break; | |
561 | ||
562 | case 'g': case 'r': | |
6659485c | 563 | rclass = reg_class_subunion[(int) rclass][(int) GENERAL_REGS]; |
8f8cadbc | 564 | break; |
565 | ||
566 | default: | |
6659485c | 567 | rclass |
8f8cadbc | 568 | = (reg_class_subunion |
6659485c | 569 | [(int) rclass] |
8f8cadbc | 570 | [(int) REG_CLASS_FROM_CONSTRAINT ((unsigned char) c, p)]); |
571 | break; | |
572 | ||
573 | case ',': case '\0': | |
574 | /* See if REGNO fits this alternative, and set it up as the | |
575 | replacement register if we don't have one for this | |
576 | alternative yet and the operand being replaced is not | |
577 | a cheap CONST_INT. */ | |
578 | if (op_alt_regno[i][j] == -1 | |
620047f0 | 579 | && recog_data.alternative_enabled_p[j] |
6659485c | 580 | && reg_fits_class_p (testreg, rclass, 0, mode) |
971ba038 | 581 | && (!CONST_INT_P (recog_data.operand[i]) |
7013e87c | 582 | || (set_src_cost (recog_data.operand[i], |
583 | optimize_bb_for_speed_p | |
584 | (BLOCK_FOR_INSN (insn))) | |
585 | > set_src_cost (testreg, | |
586 | optimize_bb_for_speed_p | |
587 | (BLOCK_FOR_INSN (insn)))))) | |
8f8cadbc | 588 | { |
589 | alternative_nregs[j]++; | |
590 | op_alt_regno[i][j] = regno; | |
591 | } | |
592 | j++; | |
b9c74b4d | 593 | rclass = NO_REGS; |
8f8cadbc | 594 | break; |
595 | } | |
596 | p += CONSTRAINT_LEN (c, p); | |
597 | ||
598 | if (c == '\0') | |
599 | break; | |
600 | } | |
601 | } | |
602 | } | |
603 | ||
604 | /* Record all alternatives which are better or equal to the currently | |
605 | matching one in the alternative_order array. */ | |
606 | for (i = j = 0; i < recog_data.n_alternatives; i++) | |
607 | if (alternative_reject[i] <= alternative_reject[which_alternative]) | |
608 | alternative_order[j++] = i; | |
609 | recog_data.n_alternatives = j; | |
610 | ||
611 | /* Sort it. Given a small number of alternatives, a dumb algorithm | |
612 | won't hurt too much. */ | |
613 | for (i = 0; i < recog_data.n_alternatives - 1; i++) | |
614 | { | |
615 | int best = i; | |
616 | int best_reject = alternative_reject[alternative_order[i]]; | |
617 | int best_nregs = alternative_nregs[alternative_order[i]]; | |
618 | int tmp; | |
619 | ||
620 | for (j = i + 1; j < recog_data.n_alternatives; j++) | |
621 | { | |
622 | int this_reject = alternative_reject[alternative_order[j]]; | |
623 | int this_nregs = alternative_nregs[alternative_order[j]]; | |
624 | ||
625 | if (this_reject < best_reject | |
c2d0cf41 | 626 | || (this_reject == best_reject && this_nregs > best_nregs)) |
8f8cadbc | 627 | { |
628 | best = j; | |
629 | best_reject = this_reject; | |
630 | best_nregs = this_nregs; | |
631 | } | |
632 | } | |
633 | ||
634 | tmp = alternative_order[best]; | |
635 | alternative_order[best] = alternative_order[i]; | |
636 | alternative_order[i] = tmp; | |
637 | } | |
638 | ||
639 | /* Substitute the operands as determined by op_alt_regno for the best | |
640 | alternative. */ | |
641 | j = alternative_order[0]; | |
642 | ||
643 | for (i = 0; i < recog_data.n_operands; i++) | |
644 | { | |
645 | enum machine_mode mode = recog_data.operand_mode[i]; | |
646 | if (op_alt_regno[i][j] == -1) | |
647 | continue; | |
648 | ||
649 | validate_change (insn, recog_data.operand_loc[i], | |
650 | gen_rtx_REG (mode, op_alt_regno[i][j]), 1); | |
651 | } | |
652 | ||
653 | for (i = recog_data.n_dups - 1; i >= 0; i--) | |
654 | { | |
655 | int op = recog_data.dup_num[i]; | |
656 | enum machine_mode mode = recog_data.operand_mode[op]; | |
657 | ||
658 | if (op_alt_regno[op][j] == -1) | |
659 | continue; | |
660 | ||
661 | validate_change (insn, recog_data.dup_loc[i], | |
662 | gen_rtx_REG (mode, op_alt_regno[op][j]), 1); | |
663 | } | |
664 | ||
665 | return apply_change_group (); | |
666 | } | |
667 | \f | |
668 | /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg | |
669 | addressing now. | |
670 | This code might also be useful when reload gave up on reg+reg addressing | |
671 | because of clashes between the return register and INDEX_REG_CLASS. */ | |
672 | ||
673 | /* The maximum number of uses of a register we can keep track of to | |
674 | replace them with reg+reg addressing. */ | |
d83ccc81 | 675 | #define RELOAD_COMBINE_MAX_USES 16 |
8f8cadbc | 676 | |
d83ccc81 | 677 | /* Describes a recorded use of a register. */ |
678 | struct reg_use | |
679 | { | |
680 | /* The insn where a register has been used. */ | |
681 | rtx insn; | |
682 | /* Points to the memory reference enclosing the use, if any, NULL_RTX | |
683 | otherwise. */ | |
684 | rtx containing_mem; | |
9d75589a | 685 | /* Location of the register within INSN. */ |
d83ccc81 | 686 | rtx *usep; |
687 | /* The reverse uid of the insn. */ | |
688 | int ruid; | |
689 | }; | |
8f8cadbc | 690 | |
691 | /* If the register is used in some unknown fashion, USE_INDEX is negative. | |
692 | If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID | |
d83ccc81 | 693 | indicates where it is first set or clobbered. |
8f8cadbc | 694 | Otherwise, USE_INDEX is the index of the last encountered use of the |
d83ccc81 | 695 | register (which is first among these we have seen since we scan backwards). |
696 | USE_RUID indicates the first encountered, i.e. last, of these uses. | |
697 | If ALL_OFFSETS_MATCH is true, all encountered uses were inside a PLUS | |
698 | with a constant offset; OFFSET contains this constant in that case. | |
8f8cadbc | 699 | STORE_RUID is always meaningful if we only want to use a value in a |
700 | register in a different place: it denotes the next insn in the insn | |
d83ccc81 | 701 | stream (i.e. the last encountered) that sets or clobbers the register. |
702 | REAL_STORE_RUID is similar, but clobbers are ignored when updating it. */ | |
8f8cadbc | 703 | static struct |
704 | { | |
705 | struct reg_use reg_use[RELOAD_COMBINE_MAX_USES]; | |
8f8cadbc | 706 | rtx offset; |
d83ccc81 | 707 | int use_index; |
8f8cadbc | 708 | int store_ruid; |
d83ccc81 | 709 | int real_store_ruid; |
8f8cadbc | 710 | int use_ruid; |
d83ccc81 | 711 | bool all_offsets_match; |
8f8cadbc | 712 | } reg_state[FIRST_PSEUDO_REGISTER]; |
713 | ||
714 | /* Reverse linear uid. This is increased in reload_combine while scanning | |
715 | the instructions from last to first. It is used to set last_label_ruid | |
716 | and the store_ruid / use_ruid fields in reg_state. */ | |
717 | static int reload_combine_ruid; | |
718 | ||
fb79f695 | 719 | /* The RUID of the last label we encountered in reload_combine. */ |
720 | static int last_label_ruid; | |
721 | ||
d83ccc81 | 722 | /* The RUID of the last jump we encountered in reload_combine. */ |
723 | static int last_jump_ruid; | |
724 | ||
fb79f695 | 725 | /* The register numbers of the first and last index register. A value of |
726 | -1 in LAST_INDEX_REG indicates that we've previously computed these | |
727 | values and found no suitable index registers. */ | |
728 | static int first_index_reg = -1; | |
729 | static int last_index_reg; | |
730 | ||
8f8cadbc | 731 | #define LABEL_LIVE(LABEL) \ |
732 | (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno]) | |
733 | ||
d83ccc81 | 734 | /* Subroutine of reload_combine_split_ruids, called to fix up a single |
735 | ruid pointed to by *PRUID if it is higher than SPLIT_RUID. */ | |
736 | ||
737 | static inline void | |
738 | reload_combine_split_one_ruid (int *pruid, int split_ruid) | |
739 | { | |
740 | if (*pruid > split_ruid) | |
741 | (*pruid)++; | |
742 | } | |
743 | ||
744 | /* Called when we insert a new insn in a position we've already passed in | |
745 | the scan. Examine all our state, increasing all ruids that are higher | |
746 | than SPLIT_RUID by one in order to make room for a new insn. */ | |
747 | ||
748 | static void | |
749 | reload_combine_split_ruids (int split_ruid) | |
750 | { | |
751 | unsigned i; | |
752 | ||
753 | reload_combine_split_one_ruid (&reload_combine_ruid, split_ruid); | |
754 | reload_combine_split_one_ruid (&last_label_ruid, split_ruid); | |
755 | reload_combine_split_one_ruid (&last_jump_ruid, split_ruid); | |
756 | ||
757 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
758 | { | |
759 | int j, idx = reg_state[i].use_index; | |
760 | reload_combine_split_one_ruid (®_state[i].use_ruid, split_ruid); | |
761 | reload_combine_split_one_ruid (®_state[i].store_ruid, split_ruid); | |
762 | reload_combine_split_one_ruid (®_state[i].real_store_ruid, | |
763 | split_ruid); | |
764 | if (idx < 0) | |
765 | continue; | |
766 | for (j = idx; j < RELOAD_COMBINE_MAX_USES; j++) | |
767 | { | |
768 | reload_combine_split_one_ruid (®_state[i].reg_use[j].ruid, | |
769 | split_ruid); | |
770 | } | |
771 | } | |
772 | } | |
773 | ||
774 | /* Called when we are about to rescan a previously encountered insn with | |
775 | reload_combine_note_use after modifying some part of it. This clears all | |
776 | information about uses in that particular insn. */ | |
777 | ||
778 | static void | |
779 | reload_combine_purge_insn_uses (rtx insn) | |
780 | { | |
781 | unsigned i; | |
782 | ||
783 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
784 | { | |
785 | int j, k, idx = reg_state[i].use_index; | |
786 | if (idx < 0) | |
787 | continue; | |
788 | j = k = RELOAD_COMBINE_MAX_USES; | |
789 | while (j-- > idx) | |
790 | { | |
791 | if (reg_state[i].reg_use[j].insn != insn) | |
792 | { | |
793 | k--; | |
794 | if (k != j) | |
795 | reg_state[i].reg_use[k] = reg_state[i].reg_use[j]; | |
796 | } | |
797 | } | |
798 | reg_state[i].use_index = k; | |
799 | } | |
800 | } | |
801 | ||
802 | /* Called when we need to forget about all uses of REGNO after an insn | |
803 | which is identified by RUID. */ | |
804 | ||
805 | static void | |
806 | reload_combine_purge_reg_uses_after_ruid (unsigned regno, int ruid) | |
807 | { | |
808 | int j, k, idx = reg_state[regno].use_index; | |
809 | if (idx < 0) | |
810 | return; | |
811 | j = k = RELOAD_COMBINE_MAX_USES; | |
812 | while (j-- > idx) | |
813 | { | |
814 | if (reg_state[regno].reg_use[j].ruid >= ruid) | |
815 | { | |
816 | k--; | |
817 | if (k != j) | |
818 | reg_state[regno].reg_use[k] = reg_state[regno].reg_use[j]; | |
819 | } | |
820 | } | |
821 | reg_state[regno].use_index = k; | |
822 | } | |
823 | ||
824 | /* Find the use of REGNO with the ruid that is highest among those | |
825 | lower than RUID_LIMIT, and return it if it is the only use of this | |
727047d0 | 826 | reg in the insn. Return NULL otherwise. */ |
d83ccc81 | 827 | |
828 | static struct reg_use * | |
829 | reload_combine_closest_single_use (unsigned regno, int ruid_limit) | |
830 | { | |
831 | int i, best_ruid = 0; | |
832 | int use_idx = reg_state[regno].use_index; | |
833 | struct reg_use *retval; | |
834 | ||
835 | if (use_idx < 0) | |
836 | return NULL; | |
837 | retval = NULL; | |
838 | for (i = use_idx; i < RELOAD_COMBINE_MAX_USES; i++) | |
839 | { | |
0ead6a7d | 840 | struct reg_use *use = reg_state[regno].reg_use + i; |
841 | int this_ruid = use->ruid; | |
d83ccc81 | 842 | if (this_ruid >= ruid_limit) |
843 | continue; | |
844 | if (this_ruid > best_ruid) | |
845 | { | |
846 | best_ruid = this_ruid; | |
727047d0 | 847 | retval = use; |
d83ccc81 | 848 | } |
727047d0 | 849 | else if (this_ruid == best_ruid) |
d83ccc81 | 850 | retval = NULL; |
851 | } | |
852 | if (last_label_ruid >= best_ruid) | |
853 | return NULL; | |
854 | return retval; | |
855 | } | |
856 | ||
65069495 | 857 | /* After we've moved an add insn, fix up any debug insns that occur |
858 | between the old location of the add and the new location. REG is | |
859 | the destination register of the add insn; REPLACEMENT is the | |
860 | SET_SRC of the add. FROM and TO specify the range in which we | |
861 | should make this change on debug insns. */ | |
0ead6a7d | 862 | |
863 | static void | |
65069495 | 864 | fixup_debug_insns (rtx reg, rtx replacement, rtx from, rtx to) |
0ead6a7d | 865 | { |
65069495 | 866 | rtx insn; |
867 | for (insn = from; insn != to; insn = NEXT_INSN (insn)) | |
0ead6a7d | 868 | { |
869 | rtx t; | |
65069495 | 870 | |
871 | if (!DEBUG_INSN_P (insn)) | |
0ead6a7d | 872 | continue; |
65069495 | 873 | |
874 | t = INSN_VAR_LOCATION_LOC (insn); | |
727047d0 | 875 | t = simplify_replace_rtx (t, reg, replacement); |
65069495 | 876 | validate_change (insn, &INSN_VAR_LOCATION_LOC (insn), t, 0); |
0ead6a7d | 877 | } |
878 | } | |
879 | ||
692ec7c8 | 880 | /* Subroutine of reload_combine_recognize_const_pattern. Try to replace REG |
881 | with SRC in the insn described by USE, taking costs into account. Return | |
882 | true if we made the replacement. */ | |
883 | ||
884 | static bool | |
885 | try_replace_in_use (struct reg_use *use, rtx reg, rtx src) | |
886 | { | |
887 | rtx use_insn = use->insn; | |
888 | rtx mem = use->containing_mem; | |
889 | bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (use_insn)); | |
890 | ||
891 | if (mem != NULL_RTX) | |
892 | { | |
893 | addr_space_t as = MEM_ADDR_SPACE (mem); | |
894 | rtx oldaddr = XEXP (mem, 0); | |
895 | rtx newaddr = NULL_RTX; | |
896 | int old_cost = address_cost (oldaddr, GET_MODE (mem), as, speed); | |
897 | int new_cost; | |
898 | ||
899 | newaddr = simplify_replace_rtx (oldaddr, reg, src); | |
900 | if (memory_address_addr_space_p (GET_MODE (mem), newaddr, as)) | |
901 | { | |
902 | XEXP (mem, 0) = newaddr; | |
903 | new_cost = address_cost (newaddr, GET_MODE (mem), as, speed); | |
904 | XEXP (mem, 0) = oldaddr; | |
905 | if (new_cost <= old_cost | |
906 | && validate_change (use_insn, | |
907 | &XEXP (mem, 0), newaddr, 0)) | |
908 | return true; | |
909 | } | |
910 | } | |
911 | else | |
912 | { | |
913 | rtx new_set = single_set (use_insn); | |
914 | if (new_set | |
915 | && REG_P (SET_DEST (new_set)) | |
916 | && GET_CODE (SET_SRC (new_set)) == PLUS | |
917 | && REG_P (XEXP (SET_SRC (new_set), 0)) | |
918 | && CONSTANT_P (XEXP (SET_SRC (new_set), 1))) | |
919 | { | |
920 | rtx new_src; | |
7013e87c | 921 | int old_cost = set_src_cost (SET_SRC (new_set), speed); |
692ec7c8 | 922 | |
923 | gcc_assert (rtx_equal_p (XEXP (SET_SRC (new_set), 0), reg)); | |
924 | new_src = simplify_replace_rtx (SET_SRC (new_set), reg, src); | |
925 | ||
7013e87c | 926 | if (set_src_cost (new_src, speed) <= old_cost |
692ec7c8 | 927 | && validate_change (use_insn, &SET_SRC (new_set), |
928 | new_src, 0)) | |
929 | return true; | |
930 | } | |
931 | } | |
932 | return false; | |
933 | } | |
934 | ||
d83ccc81 | 935 | /* Called by reload_combine when scanning INSN. This function tries to detect |
936 | patterns where a constant is added to a register, and the result is used | |
937 | in an address. | |
938 | Return true if no further processing is needed on INSN; false if it wasn't | |
939 | recognized and should be handled normally. */ | |
940 | ||
941 | static bool | |
942 | reload_combine_recognize_const_pattern (rtx insn) | |
943 | { | |
944 | int from_ruid = reload_combine_ruid; | |
945 | rtx set, pat, reg, src, addreg; | |
946 | unsigned int regno; | |
947 | struct reg_use *use; | |
948 | bool must_move_add; | |
949 | rtx add_moved_after_insn = NULL_RTX; | |
950 | int add_moved_after_ruid = 0; | |
951 | int clobbered_regno = -1; | |
952 | ||
953 | set = single_set (insn); | |
954 | if (set == NULL_RTX) | |
955 | return false; | |
956 | ||
957 | reg = SET_DEST (set); | |
958 | src = SET_SRC (set); | |
959 | if (!REG_P (reg) | |
960 | || hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] != 1 | |
961 | || GET_MODE (reg) != Pmode | |
962 | || reg == stack_pointer_rtx) | |
963 | return false; | |
964 | ||
965 | regno = REGNO (reg); | |
966 | ||
967 | /* We look for a REG1 = REG2 + CONSTANT insn, followed by either | |
968 | uses of REG1 inside an address, or inside another add insn. If | |
969 | possible and profitable, merge the addition into subsequent | |
970 | uses. */ | |
971 | if (GET_CODE (src) != PLUS | |
972 | || !REG_P (XEXP (src, 0)) | |
973 | || !CONSTANT_P (XEXP (src, 1))) | |
974 | return false; | |
975 | ||
976 | addreg = XEXP (src, 0); | |
977 | must_move_add = rtx_equal_p (reg, addreg); | |
978 | ||
979 | pat = PATTERN (insn); | |
980 | if (must_move_add && set != pat) | |
981 | { | |
982 | /* We have to be careful when moving the add; apart from the | |
983 | single_set there may also be clobbers. Recognize one special | |
984 | case, that of one clobber alongside the set (likely a clobber | |
985 | of the CC register). */ | |
986 | gcc_assert (GET_CODE (PATTERN (insn)) == PARALLEL); | |
987 | if (XVECLEN (pat, 0) != 2 || XVECEXP (pat, 0, 0) != set | |
988 | || GET_CODE (XVECEXP (pat, 0, 1)) != CLOBBER | |
989 | || !REG_P (XEXP (XVECEXP (pat, 0, 1), 0))) | |
990 | return false; | |
991 | clobbered_regno = REGNO (XEXP (XVECEXP (pat, 0, 1), 0)); | |
992 | } | |
993 | ||
994 | do | |
995 | { | |
996 | use = reload_combine_closest_single_use (regno, from_ruid); | |
997 | ||
998 | if (use) | |
999 | /* Start the search for the next use from here. */ | |
1000 | from_ruid = use->ruid; | |
1001 | ||
1002 | if (use && GET_MODE (*use->usep) == Pmode) | |
1003 | { | |
692ec7c8 | 1004 | bool delete_add = false; |
d83ccc81 | 1005 | rtx use_insn = use->insn; |
1006 | int use_ruid = use->ruid; | |
d83ccc81 | 1007 | |
1008 | /* Avoid moving the add insn past a jump. */ | |
0ead6a7d | 1009 | if (must_move_add && use_ruid <= last_jump_ruid) |
d83ccc81 | 1010 | break; |
1011 | ||
1012 | /* If the add clobbers another hard reg in parallel, don't move | |
1013 | it past a real set of this hard reg. */ | |
1014 | if (must_move_add && clobbered_regno >= 0 | |
1015 | && reg_state[clobbered_regno].real_store_ruid >= use_ruid) | |
1016 | break; | |
1017 | ||
33b7314b | 1018 | #ifdef HAVE_cc0 |
1019 | /* Do not separate cc0 setter and cc0 user on HAVE_cc0 targets. */ | |
1020 | if (must_move_add && sets_cc0_p (PATTERN (use_insn))) | |
1021 | break; | |
1022 | #endif | |
1023 | ||
6aba0ea1 | 1024 | gcc_assert (reg_state[regno].store_ruid <= use_ruid); |
1025 | /* Avoid moving a use of ADDREG past a point where it is stored. */ | |
692ec7c8 | 1026 | if (reg_state[REGNO (addreg)].store_ruid > use_ruid) |
d83ccc81 | 1027 | break; |
1028 | ||
692ec7c8 | 1029 | /* We also must not move the addition past an insn that sets |
1030 | the same register, unless we can combine two add insns. */ | |
1031 | if (must_move_add && reg_state[regno].store_ruid == use_ruid) | |
d83ccc81 | 1032 | { |
692ec7c8 | 1033 | if (use->containing_mem == NULL_RTX) |
1034 | delete_add = true; | |
1035 | else | |
1036 | break; | |
d83ccc81 | 1037 | } |
d83ccc81 | 1038 | |
692ec7c8 | 1039 | if (try_replace_in_use (use, reg, src)) |
1040 | { | |
1041 | reload_combine_purge_insn_uses (use_insn); | |
1042 | reload_combine_note_use (&PATTERN (use_insn), use_insn, | |
1043 | use_ruid, NULL_RTX); | |
d83ccc81 | 1044 | |
692ec7c8 | 1045 | if (delete_add) |
1046 | { | |
1047 | fixup_debug_insns (reg, src, insn, use_insn); | |
1048 | delete_insn (insn); | |
1049 | return true; | |
1050 | } | |
1051 | if (must_move_add) | |
1052 | { | |
1053 | add_moved_after_insn = use_insn; | |
1054 | add_moved_after_ruid = use_ruid; | |
d83ccc81 | 1055 | } |
692ec7c8 | 1056 | continue; |
d83ccc81 | 1057 | } |
d83ccc81 | 1058 | } |
6aba0ea1 | 1059 | /* If we get here, we couldn't handle this use. */ |
1060 | if (must_move_add) | |
1061 | break; | |
d83ccc81 | 1062 | } |
1063 | while (use); | |
1064 | ||
1065 | if (!must_move_add || add_moved_after_insn == NULL_RTX) | |
1066 | /* Process the add normally. */ | |
1067 | return false; | |
1068 | ||
65069495 | 1069 | fixup_debug_insns (reg, src, insn, add_moved_after_insn); |
1070 | ||
d83ccc81 | 1071 | reorder_insns (insn, insn, add_moved_after_insn); |
1072 | reload_combine_purge_reg_uses_after_ruid (regno, add_moved_after_ruid); | |
1073 | reload_combine_split_ruids (add_moved_after_ruid - 1); | |
1074 | reload_combine_note_use (&PATTERN (insn), insn, | |
1075 | add_moved_after_ruid, NULL_RTX); | |
1076 | reg_state[regno].store_ruid = add_moved_after_ruid; | |
1077 | ||
1078 | return true; | |
1079 | } | |
1080 | ||
fb79f695 | 1081 | /* Called by reload_combine when scanning INSN. Try to detect a pattern we |
1082 | can handle and improve. Return true if no further processing is needed on | |
1083 | INSN; false if it wasn't recognized and should be handled normally. */ | |
1084 | ||
1085 | static bool | |
1086 | reload_combine_recognize_pattern (rtx insn) | |
1087 | { | |
1088 | rtx set, reg, src; | |
1089 | unsigned int regno; | |
1090 | ||
d83ccc81 | 1091 | set = single_set (insn); |
1092 | if (set == NULL_RTX) | |
1093 | return false; | |
1094 | ||
1095 | reg = SET_DEST (set); | |
1096 | src = SET_SRC (set); | |
1097 | if (!REG_P (reg) | |
1098 | || hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] != 1) | |
1099 | return false; | |
1100 | ||
1101 | regno = REGNO (reg); | |
1102 | ||
fb79f695 | 1103 | /* Look for (set (REGX) (CONST_INT)) |
1104 | (set (REGX) (PLUS (REGX) (REGY))) | |
1105 | ... | |
1106 | ... (MEM (REGX)) ... | |
1107 | and convert it to | |
1108 | (set (REGZ) (CONST_INT)) | |
1109 | ... | |
1110 | ... (MEM (PLUS (REGZ) (REGY)))... . | |
1111 | ||
1112 | First, check that we have (set (REGX) (PLUS (REGX) (REGY))) | |
1113 | and that we know all uses of REGX before it dies. | |
1114 | Also, explicitly check that REGX != REGY; our life information | |
1115 | does not yet show whether REGY changes in this insn. */ | |
fb79f695 | 1116 | |
1117 | if (GET_CODE (src) == PLUS | |
d83ccc81 | 1118 | && reg_state[regno].all_offsets_match |
1119 | && last_index_reg != -1 | |
fb79f695 | 1120 | && REG_P (XEXP (src, 1)) |
1121 | && rtx_equal_p (XEXP (src, 0), reg) | |
1122 | && !rtx_equal_p (XEXP (src, 1), reg) | |
727047d0 | 1123 | && reg_state[regno].use_index >= 0 |
1124 | && reg_state[regno].use_index < RELOAD_COMBINE_MAX_USES | |
fb79f695 | 1125 | && last_label_ruid < reg_state[regno].use_ruid) |
1126 | { | |
1127 | rtx base = XEXP (src, 1); | |
5b8537a8 | 1128 | rtx prev = prev_nonnote_nondebug_insn (insn); |
fb79f695 | 1129 | rtx prev_set = prev ? single_set (prev) : NULL_RTX; |
1130 | rtx index_reg = NULL_RTX; | |
1131 | rtx reg_sum = NULL_RTX; | |
1132 | int i; | |
1133 | ||
1134 | /* Now we need to set INDEX_REG to an index register (denoted as | |
1135 | REGZ in the illustration above) and REG_SUM to the expression | |
1136 | register+register that we want to use to substitute uses of REG | |
1137 | (typically in MEMs) with. First check REG and BASE for being | |
1138 | index registers; we can use them even if they are not dead. */ | |
1139 | if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno) | |
1140 | || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], | |
1141 | REGNO (base))) | |
1142 | { | |
1143 | index_reg = reg; | |
1144 | reg_sum = src; | |
1145 | } | |
1146 | else | |
1147 | { | |
1148 | /* Otherwise, look for a free index register. Since we have | |
1149 | checked above that neither REG nor BASE are index registers, | |
1150 | if we find anything at all, it will be different from these | |
1151 | two registers. */ | |
1152 | for (i = first_index_reg; i <= last_index_reg; i++) | |
1153 | { | |
1154 | if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i) | |
1155 | && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES | |
1156 | && reg_state[i].store_ruid <= reg_state[regno].use_ruid | |
727047d0 | 1157 | && (call_used_regs[i] || df_regs_ever_live_p (i)) |
1158 | && (!frame_pointer_needed || i != HARD_FRAME_POINTER_REGNUM) | |
1159 | && !fixed_regs[i] && !global_regs[i] | |
1160 | && hard_regno_nregs[i][GET_MODE (reg)] == 1 | |
1161 | && targetm.hard_regno_scratch_ok (i)) | |
fb79f695 | 1162 | { |
1163 | index_reg = gen_rtx_REG (GET_MODE (reg), i); | |
1164 | reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base); | |
1165 | break; | |
1166 | } | |
1167 | } | |
1168 | } | |
1169 | ||
1170 | /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that | |
1171 | (REGY), i.e. BASE, is not clobbered before the last use we'll | |
1172 | create. */ | |
1173 | if (reg_sum | |
1174 | && prev_set | |
1175 | && CONST_INT_P (SET_SRC (prev_set)) | |
1176 | && rtx_equal_p (SET_DEST (prev_set), reg) | |
fb79f695 | 1177 | && (reg_state[REGNO (base)].store_ruid |
1178 | <= reg_state[regno].use_ruid)) | |
1179 | { | |
1180 | /* Change destination register and, if necessary, the constant | |
1181 | value in PREV, the constant loading instruction. */ | |
1182 | validate_change (prev, &SET_DEST (prev_set), index_reg, 1); | |
1183 | if (reg_state[regno].offset != const0_rtx) | |
1184 | validate_change (prev, | |
1185 | &SET_SRC (prev_set), | |
1186 | GEN_INT (INTVAL (SET_SRC (prev_set)) | |
1187 | + INTVAL (reg_state[regno].offset)), | |
1188 | 1); | |
1189 | ||
1190 | /* Now for every use of REG that we have recorded, replace REG | |
1191 | with REG_SUM. */ | |
1192 | for (i = reg_state[regno].use_index; | |
1193 | i < RELOAD_COMBINE_MAX_USES; i++) | |
1194 | validate_unshare_change (reg_state[regno].reg_use[i].insn, | |
1195 | reg_state[regno].reg_use[i].usep, | |
1196 | /* Each change must have its own | |
1197 | replacement. */ | |
1198 | reg_sum, 1); | |
1199 | ||
1200 | if (apply_change_group ()) | |
1201 | { | |
65069495 | 1202 | struct reg_use *lowest_ruid = NULL; |
1203 | ||
fb79f695 | 1204 | /* For every new use of REG_SUM, we have to record the use |
1205 | of BASE therein, i.e. operand 1. */ | |
1206 | for (i = reg_state[regno].use_index; | |
1207 | i < RELOAD_COMBINE_MAX_USES; i++) | |
65069495 | 1208 | { |
1209 | struct reg_use *use = reg_state[regno].reg_use + i; | |
1210 | reload_combine_note_use (&XEXP (*use->usep, 1), use->insn, | |
1211 | use->ruid, use->containing_mem); | |
1212 | if (lowest_ruid == NULL || use->ruid < lowest_ruid->ruid) | |
1213 | lowest_ruid = use; | |
1214 | } | |
1215 | ||
1216 | fixup_debug_insns (reg, reg_sum, insn, lowest_ruid->insn); | |
fb79f695 | 1217 | |
fb79f695 | 1218 | /* Delete the reg-reg addition. */ |
1219 | delete_insn (insn); | |
1220 | ||
1221 | if (reg_state[regno].offset != const0_rtx) | |
1222 | /* Previous REG_EQUIV / REG_EQUAL notes for PREV | |
1223 | are now invalid. */ | |
1224 | remove_reg_equal_equiv_notes (prev); | |
1225 | ||
1226 | reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES; | |
fb79f695 | 1227 | return true; |
1228 | } | |
1229 | } | |
1230 | } | |
1231 | return false; | |
1232 | } | |
1233 | ||
8f8cadbc | 1234 | static void |
3ad4992f | 1235 | reload_combine (void) |
8f8cadbc | 1236 | { |
d83ccc81 | 1237 | rtx insn, prev; |
8f8cadbc | 1238 | basic_block bb; |
1239 | unsigned int r; | |
8f8cadbc | 1240 | int min_labelno, n_labels; |
1241 | HARD_REG_SET ever_live_at_start, *label_live; | |
1242 | ||
8f8cadbc | 1243 | /* To avoid wasting too much time later searching for an index register, |
1244 | determine the minimum and maximum index register numbers. */ | |
fb79f695 | 1245 | if (INDEX_REG_CLASS == NO_REGS) |
1246 | last_index_reg = -1; | |
1247 | else if (first_index_reg == -1 && last_index_reg == 0) | |
1248 | { | |
1249 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) | |
1250 | if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r)) | |
1251 | { | |
1252 | if (first_index_reg == -1) | |
1253 | first_index_reg = r; | |
1254 | ||
1255 | last_index_reg = r; | |
1256 | } | |
1257 | ||
1258 | /* If no index register is available, we can quit now. Set LAST_INDEX_REG | |
1259 | to -1 so we'll know to quit early the next time we get here. */ | |
1260 | if (first_index_reg == -1) | |
1261 | { | |
1262 | last_index_reg = -1; | |
1263 | return; | |
1264 | } | |
1265 | } | |
8f8cadbc | 1266 | |
8f8cadbc | 1267 | /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime |
1268 | information is a bit fuzzy immediately after reload, but it's | |
1269 | still good enough to determine which registers are live at a jump | |
1270 | destination. */ | |
1271 | min_labelno = get_first_label_num (); | |
1272 | n_labels = max_label_num () - min_labelno; | |
4c36ffe6 | 1273 | label_live = XNEWVEC (HARD_REG_SET, n_labels); |
8f8cadbc | 1274 | CLEAR_HARD_REG_SET (ever_live_at_start); |
1275 | ||
1276 | FOR_EACH_BB_REVERSE (bb) | |
1277 | { | |
5496dbfc | 1278 | insn = BB_HEAD (bb); |
6d7dc5b9 | 1279 | if (LABEL_P (insn)) |
8f8cadbc | 1280 | { |
1281 | HARD_REG_SET live; | |
deb2741b | 1282 | bitmap live_in = df_get_live_in (bb); |
8f8cadbc | 1283 | |
deb2741b | 1284 | REG_SET_TO_HARD_REG_SET (live, live_in); |
1285 | compute_use_by_pseudos (&live, live_in); | |
8f8cadbc | 1286 | COPY_HARD_REG_SET (LABEL_LIVE (insn), live); |
1287 | IOR_HARD_REG_SET (ever_live_at_start, live); | |
1288 | } | |
1289 | } | |
1290 | ||
1291 | /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */ | |
d83ccc81 | 1292 | last_label_ruid = last_jump_ruid = reload_combine_ruid = 0; |
8f8cadbc | 1293 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) |
1294 | { | |
d83ccc81 | 1295 | reg_state[r].store_ruid = 0; |
1296 | reg_state[r].real_store_ruid = 0; | |
8f8cadbc | 1297 | if (fixed_regs[r]) |
1298 | reg_state[r].use_index = -1; | |
1299 | else | |
1300 | reg_state[r].use_index = RELOAD_COMBINE_MAX_USES; | |
1301 | } | |
1302 | ||
d83ccc81 | 1303 | for (insn = get_last_insn (); insn; insn = prev) |
8f8cadbc | 1304 | { |
8b52f64e | 1305 | bool control_flow_insn; |
8f8cadbc | 1306 | rtx note; |
1307 | ||
d83ccc81 | 1308 | prev = PREV_INSN (insn); |
1309 | ||
8f8cadbc | 1310 | /* We cannot do our optimization across labels. Invalidating all the use |
1311 | information we have would be costly, so we just note where the label | |
1312 | is and then later disable any optimization that would cross it. */ | |
6d7dc5b9 | 1313 | if (LABEL_P (insn)) |
8f8cadbc | 1314 | last_label_ruid = reload_combine_ruid; |
19f69355 | 1315 | else if (BARRIER_P (insn)) |
1316 | { | |
1317 | /* Crossing a barrier resets all the use information. */ | |
1318 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) | |
1319 | if (! fixed_regs[r]) | |
8f8cadbc | 1320 | reg_state[r].use_index = RELOAD_COMBINE_MAX_USES; |
19f69355 | 1321 | } |
1322 | else if (INSN_P (insn) && volatile_insn_p (PATTERN (insn))) | |
1323 | /* Optimizations across insns being marked as volatile must be | |
1324 | prevented. All the usage information is invalidated | |
1325 | here. */ | |
1326 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) | |
1327 | if (! fixed_regs[r] | |
1328 | && reg_state[r].use_index != RELOAD_COMBINE_MAX_USES) | |
1329 | reg_state[r].use_index = -1; | |
8f8cadbc | 1330 | |
65069495 | 1331 | if (! NONDEBUG_INSN_P (insn)) |
8f8cadbc | 1332 | continue; |
1333 | ||
1334 | reload_combine_ruid++; | |
1335 | ||
8b52f64e | 1336 | control_flow_insn = control_flow_insn_p (insn); |
1337 | if (control_flow_insn) | |
d83ccc81 | 1338 | last_jump_ruid = reload_combine_ruid; |
1339 | ||
1340 | if (reload_combine_recognize_const_pattern (insn) | |
1341 | || reload_combine_recognize_pattern (insn)) | |
fb79f695 | 1342 | continue; |
8f8cadbc | 1343 | |
1344 | note_stores (PATTERN (insn), reload_combine_note_store, NULL); | |
1345 | ||
6d7dc5b9 | 1346 | if (CALL_P (insn)) |
8f8cadbc | 1347 | { |
1348 | rtx link; | |
1349 | ||
1350 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) | |
1351 | if (call_used_regs[r]) | |
1352 | { | |
1353 | reg_state[r].use_index = RELOAD_COMBINE_MAX_USES; | |
1354 | reg_state[r].store_ruid = reload_combine_ruid; | |
1355 | } | |
1356 | ||
1357 | for (link = CALL_INSN_FUNCTION_USAGE (insn); link; | |
1358 | link = XEXP (link, 1)) | |
1359 | { | |
c8010b80 | 1360 | rtx setuse = XEXP (link, 0); |
1361 | rtx usage_rtx = XEXP (setuse, 0); | |
1362 | if ((GET_CODE (setuse) == USE || GET_CODE (setuse) == CLOBBER) | |
1363 | && REG_P (usage_rtx)) | |
8f8cadbc | 1364 | { |
1365 | unsigned int i; | |
1366 | unsigned int start_reg = REGNO (usage_rtx); | |
8b52f64e | 1367 | unsigned int num_regs |
1368 | = hard_regno_nregs[start_reg][GET_MODE (usage_rtx)]; | |
1369 | unsigned int end_reg = start_reg + num_regs - 1; | |
8f8cadbc | 1370 | for (i = start_reg; i <= end_reg; i++) |
1371 | if (GET_CODE (XEXP (link, 0)) == CLOBBER) | |
1372 | { | |
1373 | reg_state[i].use_index = RELOAD_COMBINE_MAX_USES; | |
1374 | reg_state[i].store_ruid = reload_combine_ruid; | |
1375 | } | |
1376 | else | |
1377 | reg_state[i].use_index = -1; | |
1378 | } | |
1379 | } | |
8f8cadbc | 1380 | } |
f4979459 | 1381 | |
8b52f64e | 1382 | if (control_flow_insn && GET_CODE (PATTERN (insn)) != RETURN) |
8f8cadbc | 1383 | { |
1384 | /* Non-spill registers might be used at the call destination in | |
1385 | some unknown fashion, so we have to mark the unknown use. */ | |
1386 | HARD_REG_SET *live; | |
1387 | ||
1388 | if ((condjump_p (insn) || condjump_in_parallel_p (insn)) | |
1389 | && JUMP_LABEL (insn)) | |
1390 | live = &LABEL_LIVE (JUMP_LABEL (insn)); | |
1391 | else | |
1392 | live = &ever_live_at_start; | |
1393 | ||
8b52f64e | 1394 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) |
1395 | if (TEST_HARD_REG_BIT (*live, r)) | |
1396 | reg_state[r].use_index = -1; | |
8f8cadbc | 1397 | } |
1398 | ||
8b52f64e | 1399 | reload_combine_note_use (&PATTERN (insn), insn, reload_combine_ruid, |
1400 | NULL_RTX); | |
1401 | ||
8f8cadbc | 1402 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) |
1403 | { | |
8b52f64e | 1404 | if (REG_NOTE_KIND (note) == REG_INC && REG_P (XEXP (note, 0))) |
8f8cadbc | 1405 | { |
1406 | int regno = REGNO (XEXP (note, 0)); | |
8f8cadbc | 1407 | reg_state[regno].store_ruid = reload_combine_ruid; |
d83ccc81 | 1408 | reg_state[regno].real_store_ruid = reload_combine_ruid; |
8f8cadbc | 1409 | reg_state[regno].use_index = -1; |
1410 | } | |
1411 | } | |
1412 | } | |
1413 | ||
1414 | free (label_live); | |
1415 | } | |
1416 | ||
1417 | /* Check if DST is a register or a subreg of a register; if it is, | |
d83ccc81 | 1418 | update store_ruid, real_store_ruid and use_index in the reg_state |
1419 | structure accordingly. Called via note_stores from reload_combine. */ | |
8f8cadbc | 1420 | |
1421 | static void | |
81a410b1 | 1422 | reload_combine_note_store (rtx dst, const_rtx set, void *data ATTRIBUTE_UNUSED) |
8f8cadbc | 1423 | { |
1424 | int regno = 0; | |
1425 | int i; | |
1426 | enum machine_mode mode = GET_MODE (dst); | |
1427 | ||
1428 | if (GET_CODE (dst) == SUBREG) | |
1429 | { | |
1430 | regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)), | |
1431 | GET_MODE (SUBREG_REG (dst)), | |
1432 | SUBREG_BYTE (dst), | |
1433 | GET_MODE (dst)); | |
1434 | dst = SUBREG_REG (dst); | |
1435 | } | |
fe6524b0 | 1436 | |
1437 | /* Some targets do argument pushes without adding REG_INC notes. */ | |
1438 | ||
1439 | if (MEM_P (dst)) | |
1440 | { | |
1441 | dst = XEXP (dst, 0); | |
1442 | if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_INC | |
a5dda0b9 | 1443 | || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC |
1444 | || GET_CODE (dst) == PRE_MODIFY || GET_CODE (dst) == POST_MODIFY) | |
fe6524b0 | 1445 | { |
1446 | regno = REGNO (XEXP (dst, 0)); | |
1447 | mode = GET_MODE (XEXP (dst, 0)); | |
1448 | for (i = hard_regno_nregs[regno][mode] - 1 + regno; i >= regno; i--) | |
1449 | { | |
1450 | /* We could probably do better, but for now mark the register | |
1451 | as used in an unknown fashion and set/clobbered at this | |
1452 | insn. */ | |
1453 | reg_state[i].use_index = -1; | |
1454 | reg_state[i].store_ruid = reload_combine_ruid; | |
1455 | reg_state[i].real_store_ruid = reload_combine_ruid; | |
1456 | } | |
1457 | } | |
1458 | else | |
1459 | return; | |
1460 | } | |
1461 | ||
8ad4c111 | 1462 | if (!REG_P (dst)) |
8f8cadbc | 1463 | return; |
1464 | regno += REGNO (dst); | |
1465 | ||
1466 | /* note_stores might have stripped a STRICT_LOW_PART, so we have to be | |
1467 | careful with registers / register parts that are not full words. | |
476d094d | 1468 | Similarly for ZERO_EXTRACT. */ |
d83ccc81 | 1469 | if (GET_CODE (SET_DEST (set)) == ZERO_EXTRACT |
8f8cadbc | 1470 | || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART) |
1471 | { | |
67d6c12b | 1472 | for (i = hard_regno_nregs[regno][mode] - 1 + regno; i >= regno; i--) |
8f8cadbc | 1473 | { |
1474 | reg_state[i].use_index = -1; | |
1475 | reg_state[i].store_ruid = reload_combine_ruid; | |
d83ccc81 | 1476 | reg_state[i].real_store_ruid = reload_combine_ruid; |
8f8cadbc | 1477 | } |
1478 | } | |
1479 | else | |
1480 | { | |
67d6c12b | 1481 | for (i = hard_regno_nregs[regno][mode] - 1 + regno; i >= regno; i--) |
8f8cadbc | 1482 | { |
1483 | reg_state[i].store_ruid = reload_combine_ruid; | |
d83ccc81 | 1484 | if (GET_CODE (set) == SET) |
1485 | reg_state[i].real_store_ruid = reload_combine_ruid; | |
8f8cadbc | 1486 | reg_state[i].use_index = RELOAD_COMBINE_MAX_USES; |
1487 | } | |
1488 | } | |
1489 | } | |
1490 | ||
1491 | /* XP points to a piece of rtl that has to be checked for any uses of | |
1492 | registers. | |
1493 | *XP is the pattern of INSN, or a part of it. | |
1494 | Called from reload_combine, and recursively by itself. */ | |
1495 | static void | |
d83ccc81 | 1496 | reload_combine_note_use (rtx *xp, rtx insn, int ruid, rtx containing_mem) |
8f8cadbc | 1497 | { |
1498 | rtx x = *xp; | |
1499 | enum rtx_code code = x->code; | |
1500 | const char *fmt; | |
1501 | int i, j; | |
1502 | rtx offset = const0_rtx; /* For the REG case below. */ | |
1503 | ||
1504 | switch (code) | |
1505 | { | |
1506 | case SET: | |
8ad4c111 | 1507 | if (REG_P (SET_DEST (x))) |
8f8cadbc | 1508 | { |
d83ccc81 | 1509 | reload_combine_note_use (&SET_SRC (x), insn, ruid, NULL_RTX); |
8f8cadbc | 1510 | return; |
1511 | } | |
1512 | break; | |
1513 | ||
1514 | case USE: | |
1515 | /* If this is the USE of a return value, we can't change it. */ | |
8ad4c111 | 1516 | if (REG_P (XEXP (x, 0)) && REG_FUNCTION_VALUE_P (XEXP (x, 0))) |
8f8cadbc | 1517 | { |
1518 | /* Mark the return register as used in an unknown fashion. */ | |
1519 | rtx reg = XEXP (x, 0); | |
1520 | int regno = REGNO (reg); | |
67d6c12b | 1521 | int nregs = hard_regno_nregs[regno][GET_MODE (reg)]; |
8f8cadbc | 1522 | |
1523 | while (--nregs >= 0) | |
1524 | reg_state[regno + nregs].use_index = -1; | |
1525 | return; | |
1526 | } | |
1527 | break; | |
1528 | ||
1529 | case CLOBBER: | |
8ad4c111 | 1530 | if (REG_P (SET_DEST (x))) |
8f8cadbc | 1531 | { |
1532 | /* No spurious CLOBBERs of pseudo registers may remain. */ | |
876760f6 | 1533 | gcc_assert (REGNO (SET_DEST (x)) < FIRST_PSEUDO_REGISTER); |
8f8cadbc | 1534 | return; |
1535 | } | |
1536 | break; | |
1537 | ||
1538 | case PLUS: | |
1539 | /* We are interested in (plus (reg) (const_int)) . */ | |
8ad4c111 | 1540 | if (!REG_P (XEXP (x, 0)) |
971ba038 | 1541 | || !CONST_INT_P (XEXP (x, 1))) |
8f8cadbc | 1542 | break; |
1543 | offset = XEXP (x, 1); | |
1544 | x = XEXP (x, 0); | |
1545 | /* Fall through. */ | |
1546 | case REG: | |
1547 | { | |
1548 | int regno = REGNO (x); | |
1549 | int use_index; | |
1550 | int nregs; | |
1551 | ||
1552 | /* No spurious USEs of pseudo registers may remain. */ | |
876760f6 | 1553 | gcc_assert (regno < FIRST_PSEUDO_REGISTER); |
8f8cadbc | 1554 | |
67d6c12b | 1555 | nregs = hard_regno_nregs[regno][GET_MODE (x)]; |
8f8cadbc | 1556 | |
1557 | /* We can't substitute into multi-hard-reg uses. */ | |
1558 | if (nregs > 1) | |
1559 | { | |
1560 | while (--nregs >= 0) | |
1561 | reg_state[regno + nregs].use_index = -1; | |
1562 | return; | |
1563 | } | |
1564 | ||
727047d0 | 1565 | /* We may be called to update uses in previously seen insns. |
1566 | Don't add uses beyond the last store we saw. */ | |
1567 | if (ruid < reg_state[regno].store_ruid) | |
1568 | return; | |
1569 | ||
8f8cadbc | 1570 | /* If this register is already used in some unknown fashion, we |
1571 | can't do anything. | |
1572 | If we decrement the index from zero to -1, we can't store more | |
1573 | uses, so this register becomes used in an unknown fashion. */ | |
1574 | use_index = --reg_state[regno].use_index; | |
1575 | if (use_index < 0) | |
1576 | return; | |
1577 | ||
d83ccc81 | 1578 | if (use_index == RELOAD_COMBINE_MAX_USES - 1) |
8f8cadbc | 1579 | { |
1580 | /* This is the first use of this register we have seen since we | |
1581 | marked it as dead. */ | |
1582 | reg_state[regno].offset = offset; | |
d83ccc81 | 1583 | reg_state[regno].all_offsets_match = true; |
1584 | reg_state[regno].use_ruid = ruid; | |
8f8cadbc | 1585 | } |
0ead6a7d | 1586 | else |
1587 | { | |
1588 | if (reg_state[regno].use_ruid > ruid) | |
1589 | reg_state[regno].use_ruid = ruid; | |
1590 | ||
1591 | if (! rtx_equal_p (offset, reg_state[regno].offset)) | |
1592 | reg_state[regno].all_offsets_match = false; | |
1593 | } | |
d83ccc81 | 1594 | |
8f8cadbc | 1595 | reg_state[regno].reg_use[use_index].insn = insn; |
d83ccc81 | 1596 | reg_state[regno].reg_use[use_index].ruid = ruid; |
1597 | reg_state[regno].reg_use[use_index].containing_mem = containing_mem; | |
8f8cadbc | 1598 | reg_state[regno].reg_use[use_index].usep = xp; |
1599 | return; | |
1600 | } | |
1601 | ||
d83ccc81 | 1602 | case MEM: |
1603 | containing_mem = x; | |
1604 | break; | |
1605 | ||
8f8cadbc | 1606 | default: |
1607 | break; | |
1608 | } | |
1609 | ||
1610 | /* Recursively process the components of X. */ | |
1611 | fmt = GET_RTX_FORMAT (code); | |
1612 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1613 | { | |
1614 | if (fmt[i] == 'e') | |
d83ccc81 | 1615 | reload_combine_note_use (&XEXP (x, i), insn, ruid, containing_mem); |
8f8cadbc | 1616 | else if (fmt[i] == 'E') |
1617 | { | |
1618 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
d83ccc81 | 1619 | reload_combine_note_use (&XVECEXP (x, i, j), insn, ruid, |
1620 | containing_mem); | |
8f8cadbc | 1621 | } |
1622 | } | |
1623 | } | |
1624 | \f | |
1625 | /* See if we can reduce the cost of a constant by replacing a move | |
1626 | with an add. We track situations in which a register is set to a | |
1627 | constant or to a register plus a constant. */ | |
1628 | /* We cannot do our optimization across labels. Invalidating all the | |
1629 | information about register contents we have would be costly, so we | |
1630 | use move2add_last_label_luid to note where the label is and then | |
1631 | later disable any optimization that would cross it. | |
6132c0d0 | 1632 | reg_offset[n] / reg_base_reg[n] / reg_symbol_ref[n] / reg_mode[n] |
1633 | are only valid if reg_set_luid[n] is greater than | |
1634 | move2add_last_label_luid. */ | |
8f8cadbc | 1635 | static int reg_set_luid[FIRST_PSEUDO_REGISTER]; |
1636 | ||
1637 | /* If reg_base_reg[n] is negative, register n has been set to | |
6132c0d0 | 1638 | reg_offset[n] or reg_symbol_ref[n] + reg_offset[n] in mode reg_mode[n]. |
8f8cadbc | 1639 | If reg_base_reg[n] is non-negative, register n has been set to the |
1640 | sum of reg_offset[n] and the value of register reg_base_reg[n] | |
1641 | before reg_set_luid[n], calculated in mode reg_mode[n] . */ | |
1642 | static HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER]; | |
1643 | static int reg_base_reg[FIRST_PSEUDO_REGISTER]; | |
6132c0d0 | 1644 | static rtx reg_symbol_ref[FIRST_PSEUDO_REGISTER]; |
8f8cadbc | 1645 | static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER]; |
1646 | ||
1647 | /* move2add_luid is linearly increased while scanning the instructions | |
1648 | from first to last. It is used to set reg_set_luid in | |
1649 | reload_cse_move2add and move2add_note_store. */ | |
1650 | static int move2add_luid; | |
1651 | ||
1652 | /* move2add_last_label_luid is set whenever a label is found. Labels | |
1653 | invalidate all previously collected reg_offset data. */ | |
1654 | static int move2add_last_label_luid; | |
1655 | ||
1656 | /* ??? We don't know how zero / sign extension is handled, hence we | |
1657 | can't go from a narrower to a wider mode. */ | |
1658 | #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \ | |
1659 | (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \ | |
1660 | || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \ | |
396f2130 | 1661 | && TRULY_NOOP_TRUNCATION_MODES_P (OUTMODE, INMODE))) |
8f8cadbc | 1662 | |
6132c0d0 | 1663 | /* This function is called with INSN that sets REG to (SYM + OFF), |
1664 | while REG is known to already have value (SYM + offset). | |
1665 | This function tries to change INSN into an add instruction | |
1666 | (set (REG) (plus (REG) (OFF - offset))) using the known value. | |
d83ccc81 | 1667 | It also updates the information about REG's known value. |
1668 | Return true if we made a change. */ | |
6132c0d0 | 1669 | |
d83ccc81 | 1670 | static bool |
6132c0d0 | 1671 | move2add_use_add2_insn (rtx reg, rtx sym, rtx off, rtx insn) |
1672 | { | |
1673 | rtx pat = PATTERN (insn); | |
1674 | rtx src = SET_SRC (pat); | |
1675 | int regno = REGNO (reg); | |
1676 | rtx new_src = gen_int_mode (INTVAL (off) - reg_offset[regno], | |
1677 | GET_MODE (reg)); | |
1678 | bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); | |
d83ccc81 | 1679 | bool changed = false; |
6132c0d0 | 1680 | |
1681 | /* (set (reg) (plus (reg) (const_int 0))) is not canonical; | |
1682 | use (set (reg) (reg)) instead. | |
1683 | We don't delete this insn, nor do we convert it into a | |
1684 | note, to avoid losing register notes or the return | |
1685 | value flag. jump2 already knows how to get rid of | |
1686 | no-op moves. */ | |
1687 | if (new_src == const0_rtx) | |
1688 | { | |
1689 | /* If the constants are different, this is a | |
1690 | truncation, that, if turned into (set (reg) | |
1691 | (reg)), would be discarded. Maybe we should | |
1692 | try a truncMN pattern? */ | |
1693 | if (INTVAL (off) == reg_offset [regno]) | |
d83ccc81 | 1694 | changed = validate_change (insn, &SET_SRC (pat), reg, 0); |
6132c0d0 | 1695 | } |
c9a03487 | 1696 | else |
6132c0d0 | 1697 | { |
c9a03487 | 1698 | struct full_rtx_costs oldcst, newcst; |
6132c0d0 | 1699 | rtx tem = gen_rtx_PLUS (GET_MODE (reg), reg, new_src); |
c9a03487 | 1700 | |
b72d459f | 1701 | get_full_set_rtx_cost (pat, &oldcst); |
c9a03487 | 1702 | SET_SRC (pat) = tem; |
b72d459f | 1703 | get_full_set_rtx_cost (pat, &newcst); |
c9a03487 | 1704 | SET_SRC (pat) = src; |
1705 | ||
1706 | if (costs_lt_p (&newcst, &oldcst, speed) | |
1707 | && have_add2_insn (reg, new_src)) | |
1708 | changed = validate_change (insn, &SET_SRC (pat), tem, 0); | |
1709 | else if (sym == NULL_RTX && GET_MODE (reg) != BImode) | |
6132c0d0 | 1710 | { |
c9a03487 | 1711 | enum machine_mode narrow_mode; |
1712 | for (narrow_mode = GET_CLASS_NARROWEST_MODE (MODE_INT); | |
1713 | narrow_mode != VOIDmode | |
1714 | && narrow_mode != GET_MODE (reg); | |
1715 | narrow_mode = GET_MODE_WIDER_MODE (narrow_mode)) | |
6132c0d0 | 1716 | { |
c9a03487 | 1717 | if (have_insn_for (STRICT_LOW_PART, narrow_mode) |
1718 | && ((reg_offset[regno] & ~GET_MODE_MASK (narrow_mode)) | |
1719 | == (INTVAL (off) & ~GET_MODE_MASK (narrow_mode)))) | |
1720 | { | |
1721 | rtx narrow_reg = gen_rtx_REG (narrow_mode, | |
1722 | REGNO (reg)); | |
1723 | rtx narrow_src = gen_int_mode (INTVAL (off), | |
1724 | narrow_mode); | |
1725 | rtx new_set | |
1726 | = gen_rtx_SET (VOIDmode, | |
1727 | gen_rtx_STRICT_LOW_PART (VOIDmode, | |
1728 | narrow_reg), | |
1729 | narrow_src); | |
1730 | changed = validate_change (insn, &PATTERN (insn), | |
1731 | new_set, 0); | |
1732 | if (changed) | |
1733 | break; | |
1734 | } | |
6132c0d0 | 1735 | } |
1736 | } | |
1737 | } | |
1738 | reg_set_luid[regno] = move2add_luid; | |
1739 | reg_base_reg[regno] = -1; | |
1740 | reg_mode[regno] = GET_MODE (reg); | |
1741 | reg_symbol_ref[regno] = sym; | |
1742 | reg_offset[regno] = INTVAL (off); | |
d83ccc81 | 1743 | return changed; |
6132c0d0 | 1744 | } |
1745 | ||
1746 | ||
1747 | /* This function is called with INSN that sets REG to (SYM + OFF), | |
1748 | but REG doesn't have known value (SYM + offset). This function | |
1749 | tries to find another register which is known to already have | |
1750 | value (SYM + offset) and change INSN into an add instruction | |
1751 | (set (REG) (plus (the found register) (OFF - offset))) if such | |
1752 | a register is found. It also updates the information about | |
d83ccc81 | 1753 | REG's known value. |
1754 | Return true iff we made a change. */ | |
6132c0d0 | 1755 | |
d83ccc81 | 1756 | static bool |
6132c0d0 | 1757 | move2add_use_add3_insn (rtx reg, rtx sym, rtx off, rtx insn) |
1758 | { | |
1759 | rtx pat = PATTERN (insn); | |
1760 | rtx src = SET_SRC (pat); | |
1761 | int regno = REGNO (reg); | |
c2130a4b | 1762 | int min_regno = 0; |
6132c0d0 | 1763 | bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); |
1764 | int i; | |
d83ccc81 | 1765 | bool changed = false; |
c9a03487 | 1766 | struct full_rtx_costs oldcst, newcst, mincst; |
1767 | rtx plus_expr; | |
1768 | ||
1769 | init_costs_to_max (&mincst); | |
b72d459f | 1770 | get_full_set_rtx_cost (pat, &oldcst); |
c9a03487 | 1771 | |
1772 | plus_expr = gen_rtx_PLUS (GET_MODE (reg), reg, const0_rtx); | |
1773 | SET_SRC (pat) = plus_expr; | |
6132c0d0 | 1774 | |
1775 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1776 | if (reg_set_luid[i] > move2add_last_label_luid | |
1777 | && reg_mode[i] == GET_MODE (reg) | |
1778 | && reg_base_reg[i] < 0 | |
1779 | && reg_symbol_ref[i] != NULL_RTX | |
1780 | && rtx_equal_p (sym, reg_symbol_ref[i])) | |
1781 | { | |
1782 | rtx new_src = gen_int_mode (INTVAL (off) - reg_offset[i], | |
1783 | GET_MODE (reg)); | |
1784 | /* (set (reg) (plus (reg) (const_int 0))) is not canonical; | |
1785 | use (set (reg) (reg)) instead. | |
1786 | We don't delete this insn, nor do we convert it into a | |
1787 | note, to avoid losing register notes or the return | |
1788 | value flag. jump2 already knows how to get rid of | |
1789 | no-op moves. */ | |
1790 | if (new_src == const0_rtx) | |
1791 | { | |
c9a03487 | 1792 | init_costs_to_zero (&mincst); |
6132c0d0 | 1793 | min_regno = i; |
1794 | break; | |
1795 | } | |
1796 | else | |
1797 | { | |
c9a03487 | 1798 | XEXP (plus_expr, 1) = new_src; |
b72d459f | 1799 | get_full_set_rtx_cost (pat, &newcst); |
c9a03487 | 1800 | |
1801 | if (costs_lt_p (&newcst, &mincst, speed)) | |
6132c0d0 | 1802 | { |
c9a03487 | 1803 | mincst = newcst; |
6132c0d0 | 1804 | min_regno = i; |
1805 | } | |
1806 | } | |
1807 | } | |
c9a03487 | 1808 | SET_SRC (pat) = src; |
6132c0d0 | 1809 | |
c9a03487 | 1810 | if (costs_lt_p (&mincst, &oldcst, speed)) |
6132c0d0 | 1811 | { |
1812 | rtx tem; | |
1813 | ||
1814 | tem = gen_rtx_REG (GET_MODE (reg), min_regno); | |
1815 | if (i != min_regno) | |
1816 | { | |
1817 | rtx new_src = gen_int_mode (INTVAL (off) - reg_offset[min_regno], | |
1818 | GET_MODE (reg)); | |
1819 | tem = gen_rtx_PLUS (GET_MODE (reg), tem, new_src); | |
1820 | } | |
d83ccc81 | 1821 | if (validate_change (insn, &SET_SRC (pat), tem, 0)) |
1822 | changed = true; | |
6132c0d0 | 1823 | } |
1824 | reg_set_luid[regno] = move2add_luid; | |
1825 | reg_base_reg[regno] = -1; | |
1826 | reg_mode[regno] = GET_MODE (reg); | |
1827 | reg_symbol_ref[regno] = sym; | |
1828 | reg_offset[regno] = INTVAL (off); | |
d83ccc81 | 1829 | return changed; |
6132c0d0 | 1830 | } |
1831 | ||
d83ccc81 | 1832 | /* Convert move insns with constant inputs to additions if they are cheaper. |
1833 | Return true if any changes were made. */ | |
1834 | static bool | |
3ad4992f | 1835 | reload_cse_move2add (rtx first) |
8f8cadbc | 1836 | { |
1837 | int i; | |
1838 | rtx insn; | |
d83ccc81 | 1839 | bool changed = false; |
8f8cadbc | 1840 | |
1841 | for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--) | |
6132c0d0 | 1842 | { |
1843 | reg_set_luid[i] = 0; | |
1844 | reg_offset[i] = 0; | |
1845 | reg_base_reg[i] = 0; | |
1846 | reg_symbol_ref[i] = NULL_RTX; | |
1847 | reg_mode[i] = VOIDmode; | |
1848 | } | |
8f8cadbc | 1849 | |
1850 | move2add_last_label_luid = 0; | |
1851 | move2add_luid = 2; | |
1852 | for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++) | |
1853 | { | |
1854 | rtx pat, note; | |
1855 | ||
6d7dc5b9 | 1856 | if (LABEL_P (insn)) |
8f8cadbc | 1857 | { |
1858 | move2add_last_label_luid = move2add_luid; | |
1859 | /* We're going to increment move2add_luid twice after a | |
1860 | label, so that we can use move2add_last_label_luid + 1 as | |
1861 | the luid for constants. */ | |
1862 | move2add_luid++; | |
1863 | continue; | |
1864 | } | |
1865 | if (! INSN_P (insn)) | |
1866 | continue; | |
1867 | pat = PATTERN (insn); | |
1868 | /* For simplicity, we only perform this optimization on | |
1869 | straightforward SETs. */ | |
1870 | if (GET_CODE (pat) == SET | |
8ad4c111 | 1871 | && REG_P (SET_DEST (pat))) |
8f8cadbc | 1872 | { |
1873 | rtx reg = SET_DEST (pat); | |
1874 | int regno = REGNO (reg); | |
1875 | rtx src = SET_SRC (pat); | |
1876 | ||
1877 | /* Check if we have valid information on the contents of this | |
1878 | register in the mode of REG. */ | |
1879 | if (reg_set_luid[regno] > move2add_last_label_luid | |
3072d30e | 1880 | && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg), reg_mode[regno]) |
1881 | && dbg_cnt (cse2_move2add)) | |
8f8cadbc | 1882 | { |
1883 | /* Try to transform (set (REGX) (CONST_INT A)) | |
1884 | ... | |
1885 | (set (REGX) (CONST_INT B)) | |
1886 | to | |
1887 | (set (REGX) (CONST_INT A)) | |
1888 | ... | |
1889 | (set (REGX) (plus (REGX) (CONST_INT B-A))) | |
1890 | or | |
1891 | (set (REGX) (CONST_INT A)) | |
1892 | ... | |
1893 | (set (STRICT_LOW_PART (REGX)) (CONST_INT B)) | |
1894 | */ | |
1895 | ||
6132c0d0 | 1896 | if (CONST_INT_P (src) |
1897 | && reg_base_reg[regno] < 0 | |
1898 | && reg_symbol_ref[regno] == NULL_RTX) | |
8f8cadbc | 1899 | { |
d83ccc81 | 1900 | changed |= move2add_use_add2_insn (reg, NULL_RTX, src, insn); |
8f8cadbc | 1901 | continue; |
1902 | } | |
1903 | ||
1904 | /* Try to transform (set (REGX) (REGY)) | |
1905 | (set (REGX) (PLUS (REGX) (CONST_INT A))) | |
1906 | ... | |
1907 | (set (REGX) (REGY)) | |
1908 | (set (REGX) (PLUS (REGX) (CONST_INT B))) | |
1909 | to | |
1910 | (set (REGX) (REGY)) | |
1911 | (set (REGX) (PLUS (REGX) (CONST_INT A))) | |
1912 | ... | |
1913 | (set (REGX) (plus (REGX) (CONST_INT B-A))) */ | |
8ad4c111 | 1914 | else if (REG_P (src) |
8f8cadbc | 1915 | && reg_set_luid[regno] == reg_set_luid[REGNO (src)] |
1916 | && reg_base_reg[regno] == reg_base_reg[REGNO (src)] | |
1917 | && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg), | |
1918 | reg_mode[REGNO (src)])) | |
1919 | { | |
5b8537a8 | 1920 | rtx next = next_nonnote_nondebug_insn (insn); |
8f8cadbc | 1921 | rtx set = NULL_RTX; |
1922 | if (next) | |
1923 | set = single_set (next); | |
1924 | if (set | |
1925 | && SET_DEST (set) == reg | |
1926 | && GET_CODE (SET_SRC (set)) == PLUS | |
1927 | && XEXP (SET_SRC (set), 0) == reg | |
971ba038 | 1928 | && CONST_INT_P (XEXP (SET_SRC (set), 1))) |
8f8cadbc | 1929 | { |
1930 | rtx src3 = XEXP (SET_SRC (set), 1); | |
1931 | HOST_WIDE_INT added_offset = INTVAL (src3); | |
1932 | HOST_WIDE_INT base_offset = reg_offset[REGNO (src)]; | |
1933 | HOST_WIDE_INT regno_offset = reg_offset[regno]; | |
1934 | rtx new_src = | |
69e41517 | 1935 | gen_int_mode (added_offset |
1936 | + base_offset | |
1937 | - regno_offset, | |
1938 | GET_MODE (reg)); | |
f529eb25 | 1939 | bool success = false; |
1940 | bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); | |
8f8cadbc | 1941 | |
1942 | if (new_src == const0_rtx) | |
1943 | /* See above why we create (set (reg) (reg)) here. */ | |
1944 | success | |
1945 | = validate_change (next, &SET_SRC (set), reg, 0); | |
c9a03487 | 1946 | else |
8f8cadbc | 1947 | { |
c9a03487 | 1948 | rtx old_src = SET_SRC (set); |
1949 | struct full_rtx_costs oldcst, newcst; | |
1950 | rtx tem = gen_rtx_PLUS (GET_MODE (reg), reg, new_src); | |
1951 | ||
b72d459f | 1952 | get_full_set_rtx_cost (set, &oldcst); |
c9a03487 | 1953 | SET_SRC (set) = tem; |
7013e87c | 1954 | get_full_set_src_cost (tem, &newcst); |
c9a03487 | 1955 | SET_SRC (set) = old_src; |
1956 | costs_add_n_insns (&oldcst, 1); | |
1957 | ||
1958 | if (costs_lt_p (&newcst, &oldcst, speed) | |
1959 | && have_add2_insn (reg, new_src)) | |
1960 | { | |
1961 | rtx newpat = gen_rtx_SET (VOIDmode, reg, tem); | |
1962 | success | |
1963 | = validate_change (next, &PATTERN (next), | |
1964 | newpat, 0); | |
1965 | } | |
8f8cadbc | 1966 | } |
1967 | if (success) | |
1968 | delete_insn (insn); | |
d83ccc81 | 1969 | changed |= success; |
8f8cadbc | 1970 | insn = next; |
1971 | reg_mode[regno] = GET_MODE (reg); | |
1972 | reg_offset[regno] = | |
1973 | trunc_int_for_mode (added_offset + base_offset, | |
1974 | GET_MODE (reg)); | |
1975 | continue; | |
1976 | } | |
1977 | } | |
1978 | } | |
6132c0d0 | 1979 | |
1980 | /* Try to transform | |
1981 | (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A)))) | |
1982 | ... | |
1983 | (set (REGY) (CONST (PLUS (SYMBOL_REF) (CONST_INT B)))) | |
1984 | to | |
1985 | (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A)))) | |
1986 | ... | |
1987 | (set (REGY) (CONST (PLUS (REGX) (CONST_INT B-A)))) */ | |
1988 | if ((GET_CODE (src) == SYMBOL_REF | |
1989 | || (GET_CODE (src) == CONST | |
1990 | && GET_CODE (XEXP (src, 0)) == PLUS | |
1991 | && GET_CODE (XEXP (XEXP (src, 0), 0)) == SYMBOL_REF | |
1992 | && CONST_INT_P (XEXP (XEXP (src, 0), 1)))) | |
1993 | && dbg_cnt (cse2_move2add)) | |
1994 | { | |
1995 | rtx sym, off; | |
1996 | ||
1997 | if (GET_CODE (src) == SYMBOL_REF) | |
1998 | { | |
1999 | sym = src; | |
2000 | off = const0_rtx; | |
2001 | } | |
2002 | else | |
2003 | { | |
2004 | sym = XEXP (XEXP (src, 0), 0); | |
2005 | off = XEXP (XEXP (src, 0), 1); | |
2006 | } | |
2007 | ||
2008 | /* If the reg already contains the value which is sum of | |
2009 | sym and some constant value, we can use an add2 insn. */ | |
2010 | if (reg_set_luid[regno] > move2add_last_label_luid | |
2011 | && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg), reg_mode[regno]) | |
2012 | && reg_base_reg[regno] < 0 | |
2013 | && reg_symbol_ref[regno] != NULL_RTX | |
2014 | && rtx_equal_p (sym, reg_symbol_ref[regno])) | |
d83ccc81 | 2015 | changed |= move2add_use_add2_insn (reg, sym, off, insn); |
6132c0d0 | 2016 | |
2017 | /* Otherwise, we have to find a register whose value is sum | |
2018 | of sym and some constant value. */ | |
2019 | else | |
d83ccc81 | 2020 | changed |= move2add_use_add3_insn (reg, sym, off, insn); |
6132c0d0 | 2021 | |
2022 | continue; | |
2023 | } | |
8f8cadbc | 2024 | } |
2025 | ||
2026 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
2027 | { | |
2028 | if (REG_NOTE_KIND (note) == REG_INC | |
8ad4c111 | 2029 | && REG_P (XEXP (note, 0))) |
8f8cadbc | 2030 | { |
2031 | /* Reset the information about this register. */ | |
2032 | int regno = REGNO (XEXP (note, 0)); | |
2033 | if (regno < FIRST_PSEUDO_REGISTER) | |
2034 | reg_set_luid[regno] = 0; | |
2035 | } | |
2036 | } | |
6132c0d0 | 2037 | note_stores (PATTERN (insn), move2add_note_store, insn); |
8f8cadbc | 2038 | |
2039 | /* If INSN is a conditional branch, we try to extract an | |
2040 | implicit set out of it. */ | |
f222bc3b | 2041 | if (any_condjump_p (insn)) |
8f8cadbc | 2042 | { |
2043 | rtx cnd = fis_get_condition (insn); | |
2044 | ||
2045 | if (cnd != NULL_RTX | |
2046 | && GET_CODE (cnd) == NE | |
8ad4c111 | 2047 | && REG_P (XEXP (cnd, 0)) |
f222bc3b | 2048 | && !reg_set_p (XEXP (cnd, 0), insn) |
8f8cadbc | 2049 | /* The following two checks, which are also in |
2050 | move2add_note_store, are intended to reduce the | |
2051 | number of calls to gen_rtx_SET to avoid memory | |
2052 | allocation if possible. */ | |
2053 | && SCALAR_INT_MODE_P (GET_MODE (XEXP (cnd, 0))) | |
67d6c12b | 2054 | && hard_regno_nregs[REGNO (XEXP (cnd, 0))][GET_MODE (XEXP (cnd, 0))] == 1 |
971ba038 | 2055 | && CONST_INT_P (XEXP (cnd, 1))) |
8f8cadbc | 2056 | { |
2057 | rtx implicit_set = | |
2058 | gen_rtx_SET (VOIDmode, XEXP (cnd, 0), XEXP (cnd, 1)); | |
6132c0d0 | 2059 | move2add_note_store (SET_DEST (implicit_set), implicit_set, insn); |
8f8cadbc | 2060 | } |
2061 | } | |
2062 | ||
2063 | /* If this is a CALL_INSN, all call used registers are stored with | |
2064 | unknown values. */ | |
6d7dc5b9 | 2065 | if (CALL_P (insn)) |
8f8cadbc | 2066 | { |
2067 | for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--) | |
2068 | { | |
2069 | if (call_used_regs[i]) | |
2070 | /* Reset the information about this register. */ | |
2071 | reg_set_luid[i] = 0; | |
2072 | } | |
2073 | } | |
2074 | } | |
d83ccc81 | 2075 | return changed; |
8f8cadbc | 2076 | } |
2077 | ||
6132c0d0 | 2078 | /* SET is a SET or CLOBBER that sets DST. DATA is the insn which |
2079 | contains SET. | |
8f8cadbc | 2080 | Update reg_set_luid, reg_offset and reg_base_reg accordingly. |
2081 | Called from reload_cse_move2add via note_stores. */ | |
2082 | ||
2083 | static void | |
6132c0d0 | 2084 | move2add_note_store (rtx dst, const_rtx set, void *data) |
8f8cadbc | 2085 | { |
6132c0d0 | 2086 | rtx insn = (rtx) data; |
8f8cadbc | 2087 | unsigned int regno = 0; |
fe2ebfc8 | 2088 | unsigned int nregs = 0; |
8f8cadbc | 2089 | unsigned int i; |
2090 | enum machine_mode mode = GET_MODE (dst); | |
2091 | ||
2092 | if (GET_CODE (dst) == SUBREG) | |
2093 | { | |
2094 | regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)), | |
2095 | GET_MODE (SUBREG_REG (dst)), | |
2096 | SUBREG_BYTE (dst), | |
2097 | GET_MODE (dst)); | |
fe2ebfc8 | 2098 | nregs = subreg_nregs (dst); |
8f8cadbc | 2099 | dst = SUBREG_REG (dst); |
2100 | } | |
2101 | ||
2102 | /* Some targets do argument pushes without adding REG_INC notes. */ | |
2103 | ||
e16ceb8e | 2104 | if (MEM_P (dst)) |
8f8cadbc | 2105 | { |
2106 | dst = XEXP (dst, 0); | |
2107 | if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_INC | |
2108 | || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC) | |
2109 | reg_set_luid[REGNO (XEXP (dst, 0))] = 0; | |
2110 | return; | |
2111 | } | |
8ad4c111 | 2112 | if (!REG_P (dst)) |
8f8cadbc | 2113 | return; |
2114 | ||
2115 | regno += REGNO (dst); | |
fe2ebfc8 | 2116 | if (!nregs) |
2117 | nregs = hard_regno_nregs[regno][mode]; | |
8f8cadbc | 2118 | |
6132c0d0 | 2119 | if (SCALAR_INT_MODE_P (GET_MODE (dst)) |
2120 | && nregs == 1 && GET_CODE (set) == SET) | |
2121 | { | |
2122 | rtx note, sym = NULL_RTX; | |
2123 | HOST_WIDE_INT off; | |
2124 | ||
2125 | note = find_reg_equal_equiv_note (insn); | |
2126 | if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF) | |
2127 | { | |
2128 | sym = XEXP (note, 0); | |
2129 | off = 0; | |
2130 | } | |
2131 | else if (note && GET_CODE (XEXP (note, 0)) == CONST | |
2132 | && GET_CODE (XEXP (XEXP (note, 0), 0)) == PLUS | |
2133 | && GET_CODE (XEXP (XEXP (XEXP (note, 0), 0), 0)) == SYMBOL_REF | |
2134 | && CONST_INT_P (XEXP (XEXP (XEXP (note, 0), 0), 1))) | |
2135 | { | |
2136 | sym = XEXP (XEXP (XEXP (note, 0), 0), 0); | |
2137 | off = INTVAL (XEXP (XEXP (XEXP (note, 0), 0), 1)); | |
2138 | } | |
2139 | ||
2140 | if (sym != NULL_RTX) | |
2141 | { | |
2142 | reg_base_reg[regno] = -1; | |
2143 | reg_symbol_ref[regno] = sym; | |
2144 | reg_offset[regno] = off; | |
2145 | reg_mode[regno] = mode; | |
2146 | reg_set_luid[regno] = move2add_luid; | |
2147 | return; | |
2148 | } | |
2149 | } | |
2150 | ||
a422e68e | 2151 | if (SCALAR_INT_MODE_P (GET_MODE (dst)) |
fe2ebfc8 | 2152 | && nregs == 1 && GET_CODE (set) == SET |
8f8cadbc | 2153 | && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT |
8f8cadbc | 2154 | && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART) |
2155 | { | |
2156 | rtx src = SET_SRC (set); | |
2157 | rtx base_reg; | |
2158 | HOST_WIDE_INT offset; | |
2159 | int base_regno; | |
2160 | /* This may be different from mode, if SET_DEST (set) is a | |
2161 | SUBREG. */ | |
2162 | enum machine_mode dst_mode = GET_MODE (dst); | |
2163 | ||
2164 | switch (GET_CODE (src)) | |
2165 | { | |
2166 | case PLUS: | |
8ad4c111 | 2167 | if (REG_P (XEXP (src, 0))) |
8f8cadbc | 2168 | { |
2169 | base_reg = XEXP (src, 0); | |
2170 | ||
971ba038 | 2171 | if (CONST_INT_P (XEXP (src, 1))) |
8f8cadbc | 2172 | offset = INTVAL (XEXP (src, 1)); |
8ad4c111 | 2173 | else if (REG_P (XEXP (src, 1)) |
8f8cadbc | 2174 | && (reg_set_luid[REGNO (XEXP (src, 1))] |
2175 | > move2add_last_label_luid) | |
2176 | && (MODES_OK_FOR_MOVE2ADD | |
2177 | (dst_mode, reg_mode[REGNO (XEXP (src, 1))]))) | |
2178 | { | |
c389f975 | 2179 | if (reg_base_reg[REGNO (XEXP (src, 1))] < 0 |
2180 | && reg_symbol_ref[REGNO (XEXP (src, 1))] == NULL_RTX) | |
8f8cadbc | 2181 | offset = reg_offset[REGNO (XEXP (src, 1))]; |
2182 | /* Maybe the first register is known to be a | |
2183 | constant. */ | |
2184 | else if (reg_set_luid[REGNO (base_reg)] | |
2185 | > move2add_last_label_luid | |
2186 | && (MODES_OK_FOR_MOVE2ADD | |
c389f975 | 2187 | (dst_mode, reg_mode[REGNO (base_reg)])) |
2188 | && reg_base_reg[REGNO (base_reg)] < 0 | |
2189 | && reg_symbol_ref[REGNO (base_reg)] == NULL_RTX) | |
8f8cadbc | 2190 | { |
2191 | offset = reg_offset[REGNO (base_reg)]; | |
2192 | base_reg = XEXP (src, 1); | |
2193 | } | |
2194 | else | |
2195 | goto invalidate; | |
2196 | } | |
2197 | else | |
2198 | goto invalidate; | |
2199 | ||
2200 | break; | |
2201 | } | |
2202 | ||
2203 | goto invalidate; | |
2204 | ||
2205 | case REG: | |
2206 | base_reg = src; | |
2207 | offset = 0; | |
2208 | break; | |
2209 | ||
2210 | case CONST_INT: | |
2211 | /* Start tracking the register as a constant. */ | |
2212 | reg_base_reg[regno] = -1; | |
6132c0d0 | 2213 | reg_symbol_ref[regno] = NULL_RTX; |
8f8cadbc | 2214 | reg_offset[regno] = INTVAL (SET_SRC (set)); |
2215 | /* We assign the same luid to all registers set to constants. */ | |
2216 | reg_set_luid[regno] = move2add_last_label_luid + 1; | |
2217 | reg_mode[regno] = mode; | |
2218 | return; | |
2219 | ||
2220 | default: | |
2221 | invalidate: | |
2222 | /* Invalidate the contents of the register. */ | |
2223 | reg_set_luid[regno] = 0; | |
2224 | return; | |
2225 | } | |
2226 | ||
2227 | base_regno = REGNO (base_reg); | |
2228 | /* If information about the base register is not valid, set it | |
2229 | up as a new base register, pretending its value is known | |
2230 | starting from the current insn. */ | |
2231 | if (reg_set_luid[base_regno] <= move2add_last_label_luid) | |
2232 | { | |
2233 | reg_base_reg[base_regno] = base_regno; | |
6132c0d0 | 2234 | reg_symbol_ref[base_regno] = NULL_RTX; |
8f8cadbc | 2235 | reg_offset[base_regno] = 0; |
2236 | reg_set_luid[base_regno] = move2add_luid; | |
2237 | reg_mode[base_regno] = mode; | |
2238 | } | |
2239 | else if (! MODES_OK_FOR_MOVE2ADD (dst_mode, | |
2240 | reg_mode[base_regno])) | |
2241 | goto invalidate; | |
2242 | ||
2243 | reg_mode[regno] = mode; | |
2244 | ||
2245 | /* Copy base information from our base register. */ | |
2246 | reg_set_luid[regno] = reg_set_luid[base_regno]; | |
2247 | reg_base_reg[regno] = reg_base_reg[base_regno]; | |
6132c0d0 | 2248 | reg_symbol_ref[regno] = reg_symbol_ref[base_regno]; |
8f8cadbc | 2249 | |
2250 | /* Compute the sum of the offsets or constants. */ | |
2251 | reg_offset[regno] = trunc_int_for_mode (offset | |
2252 | + reg_offset[base_regno], | |
2253 | dst_mode); | |
2254 | } | |
2255 | else | |
2256 | { | |
fe2ebfc8 | 2257 | unsigned int endregno = regno + nregs; |
8f8cadbc | 2258 | |
2259 | for (i = regno; i < endregno; i++) | |
2260 | /* Reset the information about this register. */ | |
2261 | reg_set_luid[i] = 0; | |
2262 | } | |
2263 | } | |
77fce4cd | 2264 | \f |
2265 | static bool | |
2266 | gate_handle_postreload (void) | |
2267 | { | |
47dd2e78 | 2268 | return (optimize > 0 && reload_completed); |
77fce4cd | 2269 | } |
2270 | ||
2271 | ||
2a1990e9 | 2272 | static unsigned int |
77fce4cd | 2273 | rest_of_handle_postreload (void) |
2274 | { | |
3072d30e | 2275 | if (!dbg_cnt (postreload_cse)) |
2276 | return 0; | |
2277 | ||
77fce4cd | 2278 | /* Do a very simple CSE pass over just the hard registers. */ |
2279 | reload_cse_regs (get_insns ()); | |
3072d30e | 2280 | /* Reload_cse_regs can eliminate potentially-trapping MEMs. |
77fce4cd | 2281 | Remove any EH edges associated with them. */ |
cbeb677e | 2282 | if (cfun->can_throw_non_call_exceptions) |
77fce4cd | 2283 | purge_all_dead_edges (); |
3072d30e | 2284 | |
2a1990e9 | 2285 | return 0; |
77fce4cd | 2286 | } |
2287 | ||
20099e35 | 2288 | struct rtl_opt_pass pass_postreload_cse = |
77fce4cd | 2289 | { |
20099e35 | 2290 | { |
2291 | RTL_PASS, | |
77fce4cd | 2292 | "postreload", /* name */ |
2293 | gate_handle_postreload, /* gate */ | |
2294 | rest_of_handle_postreload, /* execute */ | |
2295 | NULL, /* sub */ | |
2296 | NULL, /* next */ | |
2297 | 0, /* static_pass_number */ | |
2298 | TV_RELOAD_CSE_REGS, /* tv_id */ | |
2299 | 0, /* properties_required */ | |
2300 | 0, /* properties_provided */ | |
2301 | 0, /* properties_destroyed */ | |
2302 | 0, /* todo_flags_start */ | |
0806b508 | 2303 | TODO_df_finish | TODO_verify_rtl_sharing | |
771e2890 | 2304 | 0 /* todo_flags_finish */ |
20099e35 | 2305 | } |
77fce4cd | 2306 | }; |