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8f8cadbc | 1 | /* Perform simple optimizations to clean up the result of reload. |
3aea1f79 | 2 | Copyright (C) 1987-2014 Free Software Foundation, Inc. |
8f8cadbc | 3 | |
4 | This file is part of GCC. | |
5 | ||
6 | GCC is free software; you can redistribute it and/or modify it under | |
7 | the terms of the GNU General Public License as published by the Free | |
8c4c00c1 | 8 | Software Foundation; either version 3, or (at your option) any later |
8f8cadbc | 9 | version. |
10 | ||
11 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
12 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
14 | for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
8c4c00c1 | 17 | along with GCC; see the file COPYING3. If not see |
18 | <http://www.gnu.org/licenses/>. */ | |
8f8cadbc | 19 | |
20 | #include "config.h" | |
21 | #include "system.h" | |
22 | #include "coretypes.h" | |
23 | #include "tm.h" | |
24 | ||
25 | #include "machmode.h" | |
26 | #include "hard-reg-set.h" | |
27 | #include "rtl.h" | |
28 | #include "tm_p.h" | |
29 | #include "obstack.h" | |
30 | #include "insn-config.h" | |
31 | #include "flags.h" | |
32 | #include "function.h" | |
33 | #include "expr.h" | |
34 | #include "optabs.h" | |
35 | #include "regs.h" | |
36 | #include "basic-block.h" | |
37 | #include "reload.h" | |
38 | #include "recog.h" | |
8f8cadbc | 39 | #include "cselib.h" |
0b205f4c | 40 | #include "diagnostic-core.h" |
8f8cadbc | 41 | #include "except.h" |
42 | #include "tree.h" | |
727047d0 | 43 | #include "target.h" |
77fce4cd | 44 | #include "tree-pass.h" |
3072d30e | 45 | #include "df.h" |
46 | #include "dbgcnt.h" | |
8f8cadbc | 47 | |
3ad4992f | 48 | static int reload_cse_noop_set_p (rtx); |
26709122 | 49 | static bool reload_cse_simplify (rtx, rtx); |
50 | static void reload_cse_regs_1 (void); | |
3ad4992f | 51 | static int reload_cse_simplify_set (rtx, rtx); |
52 | static int reload_cse_simplify_operands (rtx, rtx); | |
8f8cadbc | 53 | |
3ad4992f | 54 | static void reload_combine (void); |
d83ccc81 | 55 | static void reload_combine_note_use (rtx *, rtx, int, rtx); |
81a410b1 | 56 | static void reload_combine_note_store (rtx, const_rtx, void *); |
8f8cadbc | 57 | |
d83ccc81 | 58 | static bool reload_cse_move2add (rtx); |
81a410b1 | 59 | static void move2add_note_store (rtx, const_rtx, void *); |
8f8cadbc | 60 | |
61 | /* Call cse / combine like post-reload optimization phases. | |
62 | FIRST is the first instruction. */ | |
98799adc | 63 | |
64 | static void | |
3ad4992f | 65 | reload_cse_regs (rtx first ATTRIBUTE_UNUSED) |
8f8cadbc | 66 | { |
d83ccc81 | 67 | bool moves_converted; |
26709122 | 68 | reload_cse_regs_1 (); |
8f8cadbc | 69 | reload_combine (); |
d83ccc81 | 70 | moves_converted = reload_cse_move2add (first); |
8f8cadbc | 71 | if (flag_expensive_optimizations) |
d83ccc81 | 72 | { |
73 | if (moves_converted) | |
74 | reload_combine (); | |
26709122 | 75 | reload_cse_regs_1 (); |
d83ccc81 | 76 | } |
8f8cadbc | 77 | } |
78 | ||
79 | /* See whether a single set SET is a noop. */ | |
80 | static int | |
3ad4992f | 81 | reload_cse_noop_set_p (rtx set) |
8f8cadbc | 82 | { |
83 | if (cselib_reg_set_mode (SET_DEST (set)) != GET_MODE (SET_DEST (set))) | |
84 | return 0; | |
85 | ||
86 | return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set)); | |
87 | } | |
88 | ||
26709122 | 89 | /* Try to simplify INSN. Return true if the CFG may have changed. */ |
90 | static bool | |
3ad4992f | 91 | reload_cse_simplify (rtx insn, rtx testreg) |
8f8cadbc | 92 | { |
93 | rtx body = PATTERN (insn); | |
26709122 | 94 | basic_block insn_bb = BLOCK_FOR_INSN (insn); |
95 | unsigned insn_bb_succs = EDGE_COUNT (insn_bb->succs); | |
8f8cadbc | 96 | |
97 | if (GET_CODE (body) == SET) | |
98 | { | |
99 | int count = 0; | |
100 | ||
101 | /* Simplify even if we may think it is a no-op. | |
102 | We may think a memory load of a value smaller than WORD_SIZE | |
103 | is redundant because we haven't taken into account possible | |
104 | implicit extension. reload_cse_simplify_set() will bring | |
105 | this out, so it's safer to simplify before we delete. */ | |
106 | count += reload_cse_simplify_set (body, insn); | |
107 | ||
108 | if (!count && reload_cse_noop_set_p (body)) | |
109 | { | |
110 | rtx value = SET_DEST (body); | |
111 | if (REG_P (value) | |
112 | && ! REG_FUNCTION_VALUE_P (value)) | |
113 | value = 0; | |
5a9ecd4a | 114 | if (check_for_inc_dec (insn)) |
115 | delete_insn_and_edges (insn); | |
26709122 | 116 | /* We're done with this insn. */ |
117 | goto done; | |
8f8cadbc | 118 | } |
119 | ||
120 | if (count > 0) | |
121 | apply_change_group (); | |
122 | else | |
123 | reload_cse_simplify_operands (insn, testreg); | |
124 | } | |
125 | else if (GET_CODE (body) == PARALLEL) | |
126 | { | |
127 | int i; | |
128 | int count = 0; | |
129 | rtx value = NULL_RTX; | |
130 | ||
17883489 | 131 | /* Registers mentioned in the clobber list for an asm cannot be reused |
132 | within the body of the asm. Invalidate those registers now so that | |
133 | we don't try to substitute values for them. */ | |
134 | if (asm_noperands (body) >= 0) | |
135 | { | |
136 | for (i = XVECLEN (body, 0) - 1; i >= 0; --i) | |
137 | { | |
138 | rtx part = XVECEXP (body, 0, i); | |
139 | if (GET_CODE (part) == CLOBBER && REG_P (XEXP (part, 0))) | |
140 | cselib_invalidate_rtx (XEXP (part, 0)); | |
141 | } | |
142 | } | |
143 | ||
8f8cadbc | 144 | /* If every action in a PARALLEL is a noop, we can delete |
145 | the entire PARALLEL. */ | |
146 | for (i = XVECLEN (body, 0) - 1; i >= 0; --i) | |
147 | { | |
148 | rtx part = XVECEXP (body, 0, i); | |
149 | if (GET_CODE (part) == SET) | |
150 | { | |
151 | if (! reload_cse_noop_set_p (part)) | |
152 | break; | |
153 | if (REG_P (SET_DEST (part)) | |
154 | && REG_FUNCTION_VALUE_P (SET_DEST (part))) | |
155 | { | |
156 | if (value) | |
157 | break; | |
158 | value = SET_DEST (part); | |
159 | } | |
160 | } | |
161 | else if (GET_CODE (part) != CLOBBER) | |
162 | break; | |
163 | } | |
164 | ||
165 | if (i < 0) | |
166 | { | |
5a9ecd4a | 167 | if (check_for_inc_dec (insn)) |
168 | delete_insn_and_edges (insn); | |
8f8cadbc | 169 | /* We're done with this insn. */ |
26709122 | 170 | goto done; |
8f8cadbc | 171 | } |
172 | ||
173 | /* It's not a no-op, but we can try to simplify it. */ | |
174 | for (i = XVECLEN (body, 0) - 1; i >= 0; --i) | |
175 | if (GET_CODE (XVECEXP (body, 0, i)) == SET) | |
176 | count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn); | |
177 | ||
178 | if (count > 0) | |
179 | apply_change_group (); | |
180 | else | |
181 | reload_cse_simplify_operands (insn, testreg); | |
182 | } | |
26709122 | 183 | |
184 | done: | |
185 | return (EDGE_COUNT (insn_bb->succs) != insn_bb_succs); | |
8f8cadbc | 186 | } |
187 | ||
188 | /* Do a very simple CSE pass over the hard registers. | |
189 | ||
190 | This function detects no-op moves where we happened to assign two | |
191 | different pseudo-registers to the same hard register, and then | |
192 | copied one to the other. Reload will generate a useless | |
193 | instruction copying a register to itself. | |
194 | ||
195 | This function also detects cases where we load a value from memory | |
196 | into two different registers, and (if memory is more expensive than | |
197 | registers) changes it to simply copy the first register into the | |
198 | second register. | |
199 | ||
200 | Another optimization is performed that scans the operands of each | |
201 | instruction to see whether the value is already available in a | |
202 | hard register. It then replaces the operand with the hard register | |
203 | if possible, much like an optional reload would. */ | |
204 | ||
205 | static void | |
26709122 | 206 | reload_cse_regs_1 (void) |
8f8cadbc | 207 | { |
26709122 | 208 | bool cfg_changed = false; |
209 | basic_block bb; | |
201f6961 | 210 | rtx insn; |
8f8cadbc | 211 | rtx testreg = gen_rtx_REG (VOIDmode, -1); |
212 | ||
35af0188 | 213 | cselib_init (CSELIB_RECORD_MEMORY); |
8f8cadbc | 214 | init_alias_analysis (); |
215 | ||
fc00614f | 216 | FOR_EACH_BB_FN (bb, cfun) |
26709122 | 217 | FOR_BB_INSNS (bb, insn) |
218 | { | |
219 | if (INSN_P (insn)) | |
220 | cfg_changed |= reload_cse_simplify (insn, testreg); | |
8f8cadbc | 221 | |
26709122 | 222 | cselib_process_insn (insn); |
223 | } | |
8f8cadbc | 224 | |
225 | /* Clean up. */ | |
226 | end_alias_analysis (); | |
227 | cselib_finish (); | |
26709122 | 228 | if (cfg_changed) |
229 | cleanup_cfg (0); | |
8f8cadbc | 230 | } |
231 | ||
232 | /* Try to simplify a single SET instruction. SET is the set pattern. | |
233 | INSN is the instruction it came from. | |
234 | This function only handles one case: if we set a register to a value | |
235 | which is not a register, we try to find that value in some other register | |
236 | and change the set into a register copy. */ | |
237 | ||
238 | static int | |
3ad4992f | 239 | reload_cse_simplify_set (rtx set, rtx insn) |
8f8cadbc | 240 | { |
241 | int did_change = 0; | |
242 | int dreg; | |
243 | rtx src; | |
ade444a4 | 244 | reg_class_t dclass; |
8f8cadbc | 245 | int old_cost; |
246 | cselib_val *val; | |
247 | struct elt_loc_list *l; | |
248 | #ifdef LOAD_EXTEND_OP | |
21f1e711 | 249 | enum rtx_code extend_op = UNKNOWN; |
8f8cadbc | 250 | #endif |
f529eb25 | 251 | bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); |
8f8cadbc | 252 | |
253 | dreg = true_regnum (SET_DEST (set)); | |
254 | if (dreg < 0) | |
255 | return 0; | |
256 | ||
257 | src = SET_SRC (set); | |
258 | if (side_effects_p (src) || true_regnum (src) >= 0) | |
259 | return 0; | |
260 | ||
261 | dclass = REGNO_REG_CLASS (dreg); | |
262 | ||
263 | #ifdef LOAD_EXTEND_OP | |
264 | /* When replacing a memory with a register, we need to honor assumptions | |
265 | that combine made wrt the contents of sign bits. We'll do this by | |
266 | generating an extend instruction instead of a reg->reg copy. Thus | |
267 | the destination must be a register that we can widen. */ | |
e16ceb8e | 268 | if (MEM_P (src) |
8f8cadbc | 269 | && GET_MODE_BITSIZE (GET_MODE (src)) < BITS_PER_WORD |
21f1e711 | 270 | && (extend_op = LOAD_EXTEND_OP (GET_MODE (src))) != UNKNOWN |
8ad4c111 | 271 | && !REG_P (SET_DEST (set))) |
8f8cadbc | 272 | return 0; |
273 | #endif | |
274 | ||
1f864115 | 275 | val = cselib_lookup (src, GET_MODE (SET_DEST (set)), 0, VOIDmode); |
3be01943 | 276 | if (! val) |
277 | return 0; | |
278 | ||
8f8cadbc | 279 | /* If memory loads are cheaper than register copies, don't change them. */ |
e16ceb8e | 280 | if (MEM_P (src)) |
251a613e | 281 | old_cost = memory_move_cost (GET_MODE (src), dclass, true); |
8ad4c111 | 282 | else if (REG_P (src)) |
e6078fbb | 283 | old_cost = register_move_cost (GET_MODE (src), |
8f8cadbc | 284 | REGNO_REG_CLASS (REGNO (src)), dclass); |
285 | else | |
7013e87c | 286 | old_cost = set_src_cost (src, speed); |
8f8cadbc | 287 | |
8f8cadbc | 288 | for (l = val->locs; l; l = l->next) |
289 | { | |
290 | rtx this_rtx = l->loc; | |
291 | int this_cost; | |
292 | ||
293 | if (CONSTANT_P (this_rtx) && ! references_value_p (this_rtx, 0)) | |
294 | { | |
295 | #ifdef LOAD_EXTEND_OP | |
21f1e711 | 296 | if (extend_op != UNKNOWN) |
8f8cadbc | 297 | { |
298 | HOST_WIDE_INT this_val; | |
299 | ||
300 | /* ??? I'm lazy and don't wish to handle CONST_DOUBLE. Other | |
301 | constants, such as SYMBOL_REF, cannot be extended. */ | |
971ba038 | 302 | if (!CONST_INT_P (this_rtx)) |
8f8cadbc | 303 | continue; |
304 | ||
305 | this_val = INTVAL (this_rtx); | |
306 | switch (extend_op) | |
307 | { | |
308 | case ZERO_EXTEND: | |
309 | this_val &= GET_MODE_MASK (GET_MODE (src)); | |
310 | break; | |
311 | case SIGN_EXTEND: | |
312 | /* ??? In theory we're already extended. */ | |
313 | if (this_val == trunc_int_for_mode (this_val, GET_MODE (src))) | |
314 | break; | |
315 | default: | |
876760f6 | 316 | gcc_unreachable (); |
8f8cadbc | 317 | } |
318 | this_rtx = GEN_INT (this_val); | |
319 | } | |
320 | #endif | |
7013e87c | 321 | this_cost = set_src_cost (this_rtx, speed); |
8f8cadbc | 322 | } |
8ad4c111 | 323 | else if (REG_P (this_rtx)) |
8f8cadbc | 324 | { |
325 | #ifdef LOAD_EXTEND_OP | |
21f1e711 | 326 | if (extend_op != UNKNOWN) |
8f8cadbc | 327 | { |
328 | this_rtx = gen_rtx_fmt_e (extend_op, word_mode, this_rtx); | |
7013e87c | 329 | this_cost = set_src_cost (this_rtx, speed); |
8f8cadbc | 330 | } |
331 | else | |
332 | #endif | |
e6078fbb | 333 | this_cost = register_move_cost (GET_MODE (this_rtx), |
8f8cadbc | 334 | REGNO_REG_CLASS (REGNO (this_rtx)), |
335 | dclass); | |
336 | } | |
337 | else | |
338 | continue; | |
339 | ||
340 | /* If equal costs, prefer registers over anything else. That | |
341 | tends to lead to smaller instructions on some machines. */ | |
342 | if (this_cost < old_cost | |
343 | || (this_cost == old_cost | |
8ad4c111 | 344 | && REG_P (this_rtx) |
345 | && !REG_P (SET_SRC (set)))) | |
8f8cadbc | 346 | { |
347 | #ifdef LOAD_EXTEND_OP | |
348 | if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (set))) < BITS_PER_WORD | |
21f1e711 | 349 | && extend_op != UNKNOWN |
8f8cadbc | 350 | #ifdef CANNOT_CHANGE_MODE_CLASS |
351 | && !CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set)), | |
352 | word_mode, | |
353 | REGNO_REG_CLASS (REGNO (SET_DEST (set)))) | |
354 | #endif | |
355 | ) | |
356 | { | |
357 | rtx wide_dest = gen_rtx_REG (word_mode, REGNO (SET_DEST (set))); | |
358 | ORIGINAL_REGNO (wide_dest) = ORIGINAL_REGNO (SET_DEST (set)); | |
359 | validate_change (insn, &SET_DEST (set), wide_dest, 1); | |
360 | } | |
361 | #endif | |
362 | ||
11d686e2 | 363 | validate_unshare_change (insn, &SET_SRC (set), this_rtx, 1); |
8f8cadbc | 364 | old_cost = this_cost, did_change = 1; |
365 | } | |
366 | } | |
367 | ||
368 | return did_change; | |
369 | } | |
370 | ||
371 | /* Try to replace operands in INSN with equivalent values that are already | |
372 | in registers. This can be viewed as optional reloading. | |
373 | ||
374 | For each non-register operand in the insn, see if any hard regs are | |
375 | known to be equivalent to that operand. Record the alternatives which | |
376 | can accept these hard registers. Among all alternatives, select the | |
377 | ones which are better or equal to the one currently matching, where | |
378 | "better" is in terms of '?' and '!' constraints. Among the remaining | |
379 | alternatives, select the one which replaces most operands with | |
380 | hard registers. */ | |
381 | ||
382 | static int | |
3ad4992f | 383 | reload_cse_simplify_operands (rtx insn, rtx testreg) |
8f8cadbc | 384 | { |
385 | int i, j; | |
386 | ||
387 | /* For each operand, all registers that are equivalent to it. */ | |
388 | HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS]; | |
389 | ||
390 | const char *constraints[MAX_RECOG_OPERANDS]; | |
391 | ||
392 | /* Vector recording how bad an alternative is. */ | |
393 | int *alternative_reject; | |
394 | /* Vector recording how many registers can be introduced by choosing | |
395 | this alternative. */ | |
396 | int *alternative_nregs; | |
397 | /* Array of vectors recording, for each operand and each alternative, | |
398 | which hard register to substitute, or -1 if the operand should be | |
399 | left as it is. */ | |
400 | int *op_alt_regno[MAX_RECOG_OPERANDS]; | |
401 | /* Array of alternatives, sorted in order of decreasing desirability. */ | |
402 | int *alternative_order; | |
403 | ||
404 | extract_insn (insn); | |
405 | ||
406 | if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0) | |
407 | return 0; | |
408 | ||
409 | /* Figure out which alternative currently matches. */ | |
410 | if (! constrain_operands (1)) | |
411 | fatal_insn_not_found (insn); | |
412 | ||
4077bf7a | 413 | alternative_reject = XALLOCAVEC (int, recog_data.n_alternatives); |
414 | alternative_nregs = XALLOCAVEC (int, recog_data.n_alternatives); | |
415 | alternative_order = XALLOCAVEC (int, recog_data.n_alternatives); | |
f0af5a88 | 416 | memset (alternative_reject, 0, recog_data.n_alternatives * sizeof (int)); |
417 | memset (alternative_nregs, 0, recog_data.n_alternatives * sizeof (int)); | |
8f8cadbc | 418 | |
419 | /* For each operand, find out which regs are equivalent. */ | |
420 | for (i = 0; i < recog_data.n_operands; i++) | |
421 | { | |
422 | cselib_val *v; | |
423 | struct elt_loc_list *l; | |
9d9e3c81 | 424 | rtx op; |
8f8cadbc | 425 | |
426 | CLEAR_HARD_REG_SET (equiv_regs[i]); | |
427 | ||
428 | /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem | |
429 | right, so avoid the problem here. Likewise if we have a constant | |
430 | and the insn pattern doesn't tell us the mode we need. */ | |
6d7dc5b9 | 431 | if (LABEL_P (recog_data.operand[i]) |
8f8cadbc | 432 | || (CONSTANT_P (recog_data.operand[i]) |
433 | && recog_data.operand_mode[i] == VOIDmode)) | |
434 | continue; | |
435 | ||
9d9e3c81 | 436 | op = recog_data.operand[i]; |
9d9e3c81 | 437 | #ifdef LOAD_EXTEND_OP |
e16ceb8e | 438 | if (MEM_P (op) |
f018d957 | 439 | && GET_MODE_BITSIZE (GET_MODE (op)) < BITS_PER_WORD |
440 | && LOAD_EXTEND_OP (GET_MODE (op)) != UNKNOWN) | |
9d9e3c81 | 441 | { |
442 | rtx set = single_set (insn); | |
443 | ||
4885b286 | 444 | /* We might have multiple sets, some of which do implicit |
9d9e3c81 | 445 | extension. Punt on this for now. */ |
446 | if (! set) | |
447 | continue; | |
86481e89 | 448 | /* If the destination is also a MEM or a STRICT_LOW_PART, no |
9d9e3c81 | 449 | extension applies. |
450 | Also, if there is an explicit extension, we don't have to | |
451 | worry about an implicit one. */ | |
e16ceb8e | 452 | else if (MEM_P (SET_DEST (set)) |
9d9e3c81 | 453 | || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART |
454 | || GET_CODE (SET_SRC (set)) == ZERO_EXTEND | |
455 | || GET_CODE (SET_SRC (set)) == SIGN_EXTEND) | |
456 | ; /* Continue ordinary processing. */ | |
a091e4f5 | 457 | #ifdef CANNOT_CHANGE_MODE_CLASS |
458 | /* If the register cannot change mode to word_mode, it follows that | |
459 | it cannot have been used in word_mode. */ | |
8ad4c111 | 460 | else if (REG_P (SET_DEST (set)) |
a091e4f5 | 461 | && CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set)), |
462 | word_mode, | |
463 | REGNO_REG_CLASS (REGNO (SET_DEST (set))))) | |
464 | ; /* Continue ordinary processing. */ | |
465 | #endif | |
9d9e3c81 | 466 | /* If this is a straight load, make the extension explicit. */ |
8ad4c111 | 467 | else if (REG_P (SET_DEST (set)) |
9d9e3c81 | 468 | && recog_data.n_operands == 2 |
469 | && SET_SRC (set) == op | |
470 | && SET_DEST (set) == recog_data.operand[1-i]) | |
471 | { | |
472 | validate_change (insn, recog_data.operand_loc[i], | |
f018d957 | 473 | gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (op)), |
9d9e3c81 | 474 | word_mode, op), |
475 | 1); | |
476 | validate_change (insn, recog_data.operand_loc[1-i], | |
477 | gen_rtx_REG (word_mode, REGNO (SET_DEST (set))), | |
478 | 1); | |
479 | if (! apply_change_group ()) | |
480 | return 0; | |
481 | return reload_cse_simplify_operands (insn, testreg); | |
482 | } | |
483 | else | |
484 | /* ??? There might be arithmetic operations with memory that are | |
485 | safe to optimize, but is it worth the trouble? */ | |
486 | continue; | |
487 | } | |
488 | #endif /* LOAD_EXTEND_OP */ | |
017b7047 | 489 | if (side_effects_p (op)) |
490 | continue; | |
1f864115 | 491 | v = cselib_lookup (op, recog_data.operand_mode[i], 0, VOIDmode); |
8f8cadbc | 492 | if (! v) |
493 | continue; | |
494 | ||
495 | for (l = v->locs; l; l = l->next) | |
8ad4c111 | 496 | if (REG_P (l->loc)) |
8f8cadbc | 497 | SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc)); |
498 | } | |
499 | ||
500 | for (i = 0; i < recog_data.n_operands; i++) | |
501 | { | |
502 | enum machine_mode mode; | |
503 | int regno; | |
504 | const char *p; | |
505 | ||
4077bf7a | 506 | op_alt_regno[i] = XALLOCAVEC (int, recog_data.n_alternatives); |
8f8cadbc | 507 | for (j = 0; j < recog_data.n_alternatives; j++) |
508 | op_alt_regno[i][j] = -1; | |
509 | ||
510 | p = constraints[i] = recog_data.constraints[i]; | |
511 | mode = recog_data.operand_mode[i]; | |
512 | ||
513 | /* Add the reject values for each alternative given by the constraints | |
514 | for this operand. */ | |
515 | j = 0; | |
516 | while (*p != '\0') | |
517 | { | |
518 | char c = *p++; | |
519 | if (c == ',') | |
520 | j++; | |
521 | else if (c == '?') | |
522 | alternative_reject[j] += 3; | |
523 | else if (c == '!') | |
524 | alternative_reject[j] += 300; | |
525 | } | |
526 | ||
527 | /* We won't change operands which are already registers. We | |
528 | also don't want to modify output operands. */ | |
529 | regno = true_regnum (recog_data.operand[i]); | |
530 | if (regno >= 0 | |
531 | || constraints[i][0] == '=' | |
532 | || constraints[i][0] == '+') | |
533 | continue; | |
534 | ||
535 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
536 | { | |
b9c74b4d | 537 | enum reg_class rclass = NO_REGS; |
8f8cadbc | 538 | |
539 | if (! TEST_HARD_REG_BIT (equiv_regs[i], regno)) | |
540 | continue; | |
541 | ||
7f1819d3 | 542 | SET_REGNO_RAW (testreg, regno); |
8f8cadbc | 543 | PUT_MODE (testreg, mode); |
544 | ||
545 | /* We found a register equal to this operand. Now look for all | |
546 | alternatives that can accept this register and have not been | |
547 | assigned a register they can use yet. */ | |
548 | j = 0; | |
549 | p = constraints[i]; | |
550 | for (;;) | |
551 | { | |
552 | char c = *p; | |
553 | ||
554 | switch (c) | |
555 | { | |
556 | case '=': case '+': case '?': | |
557 | case '#': case '&': case '!': | |
558 | case '*': case '%': | |
559 | case '0': case '1': case '2': case '3': case '4': | |
560 | case '5': case '6': case '7': case '8': case '9': | |
e9ff93b1 | 561 | case '<': case '>': case 'V': case 'o': |
8f8cadbc | 562 | case 'E': case 'F': case 'G': case 'H': |
563 | case 's': case 'i': case 'n': | |
564 | case 'I': case 'J': case 'K': case 'L': | |
565 | case 'M': case 'N': case 'O': case 'P': | |
e9ff93b1 | 566 | case 'p': case 'X': case TARGET_MEM_CONSTRAINT: |
8f8cadbc | 567 | /* These don't say anything we care about. */ |
568 | break; | |
569 | ||
570 | case 'g': case 'r': | |
6659485c | 571 | rclass = reg_class_subunion[(int) rclass][(int) GENERAL_REGS]; |
8f8cadbc | 572 | break; |
573 | ||
574 | default: | |
6659485c | 575 | rclass |
8f8cadbc | 576 | = (reg_class_subunion |
6659485c | 577 | [(int) rclass] |
8f8cadbc | 578 | [(int) REG_CLASS_FROM_CONSTRAINT ((unsigned char) c, p)]); |
579 | break; | |
580 | ||
581 | case ',': case '\0': | |
582 | /* See if REGNO fits this alternative, and set it up as the | |
583 | replacement register if we don't have one for this | |
584 | alternative yet and the operand being replaced is not | |
585 | a cheap CONST_INT. */ | |
586 | if (op_alt_regno[i][j] == -1 | |
620047f0 | 587 | && recog_data.alternative_enabled_p[j] |
6659485c | 588 | && reg_fits_class_p (testreg, rclass, 0, mode) |
971ba038 | 589 | && (!CONST_INT_P (recog_data.operand[i]) |
7013e87c | 590 | || (set_src_cost (recog_data.operand[i], |
591 | optimize_bb_for_speed_p | |
592 | (BLOCK_FOR_INSN (insn))) | |
593 | > set_src_cost (testreg, | |
594 | optimize_bb_for_speed_p | |
595 | (BLOCK_FOR_INSN (insn)))))) | |
8f8cadbc | 596 | { |
597 | alternative_nregs[j]++; | |
598 | op_alt_regno[i][j] = regno; | |
599 | } | |
600 | j++; | |
b9c74b4d | 601 | rclass = NO_REGS; |
8f8cadbc | 602 | break; |
603 | } | |
604 | p += CONSTRAINT_LEN (c, p); | |
605 | ||
606 | if (c == '\0') | |
607 | break; | |
608 | } | |
609 | } | |
610 | } | |
611 | ||
612 | /* Record all alternatives which are better or equal to the currently | |
613 | matching one in the alternative_order array. */ | |
614 | for (i = j = 0; i < recog_data.n_alternatives; i++) | |
615 | if (alternative_reject[i] <= alternative_reject[which_alternative]) | |
616 | alternative_order[j++] = i; | |
617 | recog_data.n_alternatives = j; | |
618 | ||
619 | /* Sort it. Given a small number of alternatives, a dumb algorithm | |
620 | won't hurt too much. */ | |
621 | for (i = 0; i < recog_data.n_alternatives - 1; i++) | |
622 | { | |
623 | int best = i; | |
624 | int best_reject = alternative_reject[alternative_order[i]]; | |
625 | int best_nregs = alternative_nregs[alternative_order[i]]; | |
626 | int tmp; | |
627 | ||
628 | for (j = i + 1; j < recog_data.n_alternatives; j++) | |
629 | { | |
630 | int this_reject = alternative_reject[alternative_order[j]]; | |
631 | int this_nregs = alternative_nregs[alternative_order[j]]; | |
632 | ||
633 | if (this_reject < best_reject | |
c2d0cf41 | 634 | || (this_reject == best_reject && this_nregs > best_nregs)) |
8f8cadbc | 635 | { |
636 | best = j; | |
637 | best_reject = this_reject; | |
638 | best_nregs = this_nregs; | |
639 | } | |
640 | } | |
641 | ||
642 | tmp = alternative_order[best]; | |
643 | alternative_order[best] = alternative_order[i]; | |
644 | alternative_order[i] = tmp; | |
645 | } | |
646 | ||
647 | /* Substitute the operands as determined by op_alt_regno for the best | |
648 | alternative. */ | |
649 | j = alternative_order[0]; | |
650 | ||
651 | for (i = 0; i < recog_data.n_operands; i++) | |
652 | { | |
653 | enum machine_mode mode = recog_data.operand_mode[i]; | |
654 | if (op_alt_regno[i][j] == -1) | |
655 | continue; | |
656 | ||
657 | validate_change (insn, recog_data.operand_loc[i], | |
658 | gen_rtx_REG (mode, op_alt_regno[i][j]), 1); | |
659 | } | |
660 | ||
661 | for (i = recog_data.n_dups - 1; i >= 0; i--) | |
662 | { | |
663 | int op = recog_data.dup_num[i]; | |
664 | enum machine_mode mode = recog_data.operand_mode[op]; | |
665 | ||
666 | if (op_alt_regno[op][j] == -1) | |
667 | continue; | |
668 | ||
669 | validate_change (insn, recog_data.dup_loc[i], | |
670 | gen_rtx_REG (mode, op_alt_regno[op][j]), 1); | |
671 | } | |
672 | ||
673 | return apply_change_group (); | |
674 | } | |
675 | \f | |
676 | /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg | |
677 | addressing now. | |
678 | This code might also be useful when reload gave up on reg+reg addressing | |
679 | because of clashes between the return register and INDEX_REG_CLASS. */ | |
680 | ||
681 | /* The maximum number of uses of a register we can keep track of to | |
682 | replace them with reg+reg addressing. */ | |
d83ccc81 | 683 | #define RELOAD_COMBINE_MAX_USES 16 |
8f8cadbc | 684 | |
d83ccc81 | 685 | /* Describes a recorded use of a register. */ |
686 | struct reg_use | |
687 | { | |
688 | /* The insn where a register has been used. */ | |
689 | rtx insn; | |
690 | /* Points to the memory reference enclosing the use, if any, NULL_RTX | |
691 | otherwise. */ | |
692 | rtx containing_mem; | |
9d75589a | 693 | /* Location of the register within INSN. */ |
d83ccc81 | 694 | rtx *usep; |
695 | /* The reverse uid of the insn. */ | |
696 | int ruid; | |
697 | }; | |
8f8cadbc | 698 | |
699 | /* If the register is used in some unknown fashion, USE_INDEX is negative. | |
700 | If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID | |
d83ccc81 | 701 | indicates where it is first set or clobbered. |
8f8cadbc | 702 | Otherwise, USE_INDEX is the index of the last encountered use of the |
d83ccc81 | 703 | register (which is first among these we have seen since we scan backwards). |
704 | USE_RUID indicates the first encountered, i.e. last, of these uses. | |
705 | If ALL_OFFSETS_MATCH is true, all encountered uses were inside a PLUS | |
706 | with a constant offset; OFFSET contains this constant in that case. | |
8f8cadbc | 707 | STORE_RUID is always meaningful if we only want to use a value in a |
708 | register in a different place: it denotes the next insn in the insn | |
d83ccc81 | 709 | stream (i.e. the last encountered) that sets or clobbers the register. |
710 | REAL_STORE_RUID is similar, but clobbers are ignored when updating it. */ | |
8f8cadbc | 711 | static struct |
712 | { | |
713 | struct reg_use reg_use[RELOAD_COMBINE_MAX_USES]; | |
8f8cadbc | 714 | rtx offset; |
d83ccc81 | 715 | int use_index; |
8f8cadbc | 716 | int store_ruid; |
d83ccc81 | 717 | int real_store_ruid; |
8f8cadbc | 718 | int use_ruid; |
d83ccc81 | 719 | bool all_offsets_match; |
8f8cadbc | 720 | } reg_state[FIRST_PSEUDO_REGISTER]; |
721 | ||
722 | /* Reverse linear uid. This is increased in reload_combine while scanning | |
723 | the instructions from last to first. It is used to set last_label_ruid | |
724 | and the store_ruid / use_ruid fields in reg_state. */ | |
725 | static int reload_combine_ruid; | |
726 | ||
fb79f695 | 727 | /* The RUID of the last label we encountered in reload_combine. */ |
728 | static int last_label_ruid; | |
729 | ||
d83ccc81 | 730 | /* The RUID of the last jump we encountered in reload_combine. */ |
731 | static int last_jump_ruid; | |
732 | ||
fb79f695 | 733 | /* The register numbers of the first and last index register. A value of |
734 | -1 in LAST_INDEX_REG indicates that we've previously computed these | |
735 | values and found no suitable index registers. */ | |
736 | static int first_index_reg = -1; | |
737 | static int last_index_reg; | |
738 | ||
8f8cadbc | 739 | #define LABEL_LIVE(LABEL) \ |
740 | (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno]) | |
741 | ||
d83ccc81 | 742 | /* Subroutine of reload_combine_split_ruids, called to fix up a single |
743 | ruid pointed to by *PRUID if it is higher than SPLIT_RUID. */ | |
744 | ||
745 | static inline void | |
746 | reload_combine_split_one_ruid (int *pruid, int split_ruid) | |
747 | { | |
748 | if (*pruid > split_ruid) | |
749 | (*pruid)++; | |
750 | } | |
751 | ||
752 | /* Called when we insert a new insn in a position we've already passed in | |
753 | the scan. Examine all our state, increasing all ruids that are higher | |
754 | than SPLIT_RUID by one in order to make room for a new insn. */ | |
755 | ||
756 | static void | |
757 | reload_combine_split_ruids (int split_ruid) | |
758 | { | |
759 | unsigned i; | |
760 | ||
761 | reload_combine_split_one_ruid (&reload_combine_ruid, split_ruid); | |
762 | reload_combine_split_one_ruid (&last_label_ruid, split_ruid); | |
763 | reload_combine_split_one_ruid (&last_jump_ruid, split_ruid); | |
764 | ||
765 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
766 | { | |
767 | int j, idx = reg_state[i].use_index; | |
768 | reload_combine_split_one_ruid (®_state[i].use_ruid, split_ruid); | |
769 | reload_combine_split_one_ruid (®_state[i].store_ruid, split_ruid); | |
770 | reload_combine_split_one_ruid (®_state[i].real_store_ruid, | |
771 | split_ruid); | |
772 | if (idx < 0) | |
773 | continue; | |
774 | for (j = idx; j < RELOAD_COMBINE_MAX_USES; j++) | |
775 | { | |
776 | reload_combine_split_one_ruid (®_state[i].reg_use[j].ruid, | |
777 | split_ruid); | |
778 | } | |
779 | } | |
780 | } | |
781 | ||
782 | /* Called when we are about to rescan a previously encountered insn with | |
783 | reload_combine_note_use after modifying some part of it. This clears all | |
784 | information about uses in that particular insn. */ | |
785 | ||
786 | static void | |
787 | reload_combine_purge_insn_uses (rtx insn) | |
788 | { | |
789 | unsigned i; | |
790 | ||
791 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
792 | { | |
793 | int j, k, idx = reg_state[i].use_index; | |
794 | if (idx < 0) | |
795 | continue; | |
796 | j = k = RELOAD_COMBINE_MAX_USES; | |
797 | while (j-- > idx) | |
798 | { | |
799 | if (reg_state[i].reg_use[j].insn != insn) | |
800 | { | |
801 | k--; | |
802 | if (k != j) | |
803 | reg_state[i].reg_use[k] = reg_state[i].reg_use[j]; | |
804 | } | |
805 | } | |
806 | reg_state[i].use_index = k; | |
807 | } | |
808 | } | |
809 | ||
810 | /* Called when we need to forget about all uses of REGNO after an insn | |
811 | which is identified by RUID. */ | |
812 | ||
813 | static void | |
814 | reload_combine_purge_reg_uses_after_ruid (unsigned regno, int ruid) | |
815 | { | |
816 | int j, k, idx = reg_state[regno].use_index; | |
817 | if (idx < 0) | |
818 | return; | |
819 | j = k = RELOAD_COMBINE_MAX_USES; | |
820 | while (j-- > idx) | |
821 | { | |
822 | if (reg_state[regno].reg_use[j].ruid >= ruid) | |
823 | { | |
824 | k--; | |
825 | if (k != j) | |
826 | reg_state[regno].reg_use[k] = reg_state[regno].reg_use[j]; | |
827 | } | |
828 | } | |
829 | reg_state[regno].use_index = k; | |
830 | } | |
831 | ||
832 | /* Find the use of REGNO with the ruid that is highest among those | |
833 | lower than RUID_LIMIT, and return it if it is the only use of this | |
727047d0 | 834 | reg in the insn. Return NULL otherwise. */ |
d83ccc81 | 835 | |
836 | static struct reg_use * | |
837 | reload_combine_closest_single_use (unsigned regno, int ruid_limit) | |
838 | { | |
839 | int i, best_ruid = 0; | |
840 | int use_idx = reg_state[regno].use_index; | |
841 | struct reg_use *retval; | |
842 | ||
843 | if (use_idx < 0) | |
844 | return NULL; | |
845 | retval = NULL; | |
846 | for (i = use_idx; i < RELOAD_COMBINE_MAX_USES; i++) | |
847 | { | |
0ead6a7d | 848 | struct reg_use *use = reg_state[regno].reg_use + i; |
849 | int this_ruid = use->ruid; | |
d83ccc81 | 850 | if (this_ruid >= ruid_limit) |
851 | continue; | |
852 | if (this_ruid > best_ruid) | |
853 | { | |
854 | best_ruid = this_ruid; | |
727047d0 | 855 | retval = use; |
d83ccc81 | 856 | } |
727047d0 | 857 | else if (this_ruid == best_ruid) |
d83ccc81 | 858 | retval = NULL; |
859 | } | |
860 | if (last_label_ruid >= best_ruid) | |
861 | return NULL; | |
862 | return retval; | |
863 | } | |
864 | ||
65069495 | 865 | /* After we've moved an add insn, fix up any debug insns that occur |
866 | between the old location of the add and the new location. REG is | |
867 | the destination register of the add insn; REPLACEMENT is the | |
868 | SET_SRC of the add. FROM and TO specify the range in which we | |
869 | should make this change on debug insns. */ | |
0ead6a7d | 870 | |
871 | static void | |
65069495 | 872 | fixup_debug_insns (rtx reg, rtx replacement, rtx from, rtx to) |
0ead6a7d | 873 | { |
65069495 | 874 | rtx insn; |
875 | for (insn = from; insn != to; insn = NEXT_INSN (insn)) | |
0ead6a7d | 876 | { |
877 | rtx t; | |
65069495 | 878 | |
879 | if (!DEBUG_INSN_P (insn)) | |
0ead6a7d | 880 | continue; |
65069495 | 881 | |
882 | t = INSN_VAR_LOCATION_LOC (insn); | |
727047d0 | 883 | t = simplify_replace_rtx (t, reg, replacement); |
65069495 | 884 | validate_change (insn, &INSN_VAR_LOCATION_LOC (insn), t, 0); |
0ead6a7d | 885 | } |
886 | } | |
887 | ||
692ec7c8 | 888 | /* Subroutine of reload_combine_recognize_const_pattern. Try to replace REG |
889 | with SRC in the insn described by USE, taking costs into account. Return | |
890 | true if we made the replacement. */ | |
891 | ||
892 | static bool | |
893 | try_replace_in_use (struct reg_use *use, rtx reg, rtx src) | |
894 | { | |
895 | rtx use_insn = use->insn; | |
896 | rtx mem = use->containing_mem; | |
897 | bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (use_insn)); | |
898 | ||
899 | if (mem != NULL_RTX) | |
900 | { | |
901 | addr_space_t as = MEM_ADDR_SPACE (mem); | |
902 | rtx oldaddr = XEXP (mem, 0); | |
903 | rtx newaddr = NULL_RTX; | |
904 | int old_cost = address_cost (oldaddr, GET_MODE (mem), as, speed); | |
905 | int new_cost; | |
906 | ||
907 | newaddr = simplify_replace_rtx (oldaddr, reg, src); | |
908 | if (memory_address_addr_space_p (GET_MODE (mem), newaddr, as)) | |
909 | { | |
910 | XEXP (mem, 0) = newaddr; | |
911 | new_cost = address_cost (newaddr, GET_MODE (mem), as, speed); | |
912 | XEXP (mem, 0) = oldaddr; | |
913 | if (new_cost <= old_cost | |
914 | && validate_change (use_insn, | |
915 | &XEXP (mem, 0), newaddr, 0)) | |
916 | return true; | |
917 | } | |
918 | } | |
919 | else | |
920 | { | |
921 | rtx new_set = single_set (use_insn); | |
922 | if (new_set | |
923 | && REG_P (SET_DEST (new_set)) | |
924 | && GET_CODE (SET_SRC (new_set)) == PLUS | |
925 | && REG_P (XEXP (SET_SRC (new_set), 0)) | |
926 | && CONSTANT_P (XEXP (SET_SRC (new_set), 1))) | |
927 | { | |
928 | rtx new_src; | |
7013e87c | 929 | int old_cost = set_src_cost (SET_SRC (new_set), speed); |
692ec7c8 | 930 | |
931 | gcc_assert (rtx_equal_p (XEXP (SET_SRC (new_set), 0), reg)); | |
932 | new_src = simplify_replace_rtx (SET_SRC (new_set), reg, src); | |
933 | ||
7013e87c | 934 | if (set_src_cost (new_src, speed) <= old_cost |
692ec7c8 | 935 | && validate_change (use_insn, &SET_SRC (new_set), |
936 | new_src, 0)) | |
937 | return true; | |
938 | } | |
939 | } | |
940 | return false; | |
941 | } | |
942 | ||
d83ccc81 | 943 | /* Called by reload_combine when scanning INSN. This function tries to detect |
944 | patterns where a constant is added to a register, and the result is used | |
945 | in an address. | |
946 | Return true if no further processing is needed on INSN; false if it wasn't | |
947 | recognized and should be handled normally. */ | |
948 | ||
949 | static bool | |
950 | reload_combine_recognize_const_pattern (rtx insn) | |
951 | { | |
952 | int from_ruid = reload_combine_ruid; | |
953 | rtx set, pat, reg, src, addreg; | |
954 | unsigned int regno; | |
955 | struct reg_use *use; | |
956 | bool must_move_add; | |
957 | rtx add_moved_after_insn = NULL_RTX; | |
958 | int add_moved_after_ruid = 0; | |
959 | int clobbered_regno = -1; | |
960 | ||
961 | set = single_set (insn); | |
962 | if (set == NULL_RTX) | |
963 | return false; | |
964 | ||
965 | reg = SET_DEST (set); | |
966 | src = SET_SRC (set); | |
967 | if (!REG_P (reg) | |
968 | || hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] != 1 | |
969 | || GET_MODE (reg) != Pmode | |
970 | || reg == stack_pointer_rtx) | |
971 | return false; | |
972 | ||
973 | regno = REGNO (reg); | |
974 | ||
975 | /* We look for a REG1 = REG2 + CONSTANT insn, followed by either | |
976 | uses of REG1 inside an address, or inside another add insn. If | |
977 | possible and profitable, merge the addition into subsequent | |
978 | uses. */ | |
979 | if (GET_CODE (src) != PLUS | |
980 | || !REG_P (XEXP (src, 0)) | |
981 | || !CONSTANT_P (XEXP (src, 1))) | |
982 | return false; | |
983 | ||
984 | addreg = XEXP (src, 0); | |
985 | must_move_add = rtx_equal_p (reg, addreg); | |
986 | ||
987 | pat = PATTERN (insn); | |
988 | if (must_move_add && set != pat) | |
989 | { | |
990 | /* We have to be careful when moving the add; apart from the | |
991 | single_set there may also be clobbers. Recognize one special | |
992 | case, that of one clobber alongside the set (likely a clobber | |
993 | of the CC register). */ | |
994 | gcc_assert (GET_CODE (PATTERN (insn)) == PARALLEL); | |
995 | if (XVECLEN (pat, 0) != 2 || XVECEXP (pat, 0, 0) != set | |
996 | || GET_CODE (XVECEXP (pat, 0, 1)) != CLOBBER | |
997 | || !REG_P (XEXP (XVECEXP (pat, 0, 1), 0))) | |
998 | return false; | |
999 | clobbered_regno = REGNO (XEXP (XVECEXP (pat, 0, 1), 0)); | |
1000 | } | |
1001 | ||
1002 | do | |
1003 | { | |
1004 | use = reload_combine_closest_single_use (regno, from_ruid); | |
1005 | ||
1006 | if (use) | |
1007 | /* Start the search for the next use from here. */ | |
1008 | from_ruid = use->ruid; | |
1009 | ||
1010 | if (use && GET_MODE (*use->usep) == Pmode) | |
1011 | { | |
692ec7c8 | 1012 | bool delete_add = false; |
d83ccc81 | 1013 | rtx use_insn = use->insn; |
1014 | int use_ruid = use->ruid; | |
d83ccc81 | 1015 | |
1016 | /* Avoid moving the add insn past a jump. */ | |
0ead6a7d | 1017 | if (must_move_add && use_ruid <= last_jump_ruid) |
d83ccc81 | 1018 | break; |
1019 | ||
1020 | /* If the add clobbers another hard reg in parallel, don't move | |
1021 | it past a real set of this hard reg. */ | |
1022 | if (must_move_add && clobbered_regno >= 0 | |
1023 | && reg_state[clobbered_regno].real_store_ruid >= use_ruid) | |
1024 | break; | |
1025 | ||
33b7314b | 1026 | #ifdef HAVE_cc0 |
1027 | /* Do not separate cc0 setter and cc0 user on HAVE_cc0 targets. */ | |
1028 | if (must_move_add && sets_cc0_p (PATTERN (use_insn))) | |
1029 | break; | |
1030 | #endif | |
1031 | ||
6aba0ea1 | 1032 | gcc_assert (reg_state[regno].store_ruid <= use_ruid); |
1033 | /* Avoid moving a use of ADDREG past a point where it is stored. */ | |
692ec7c8 | 1034 | if (reg_state[REGNO (addreg)].store_ruid > use_ruid) |
d83ccc81 | 1035 | break; |
1036 | ||
692ec7c8 | 1037 | /* We also must not move the addition past an insn that sets |
1038 | the same register, unless we can combine two add insns. */ | |
1039 | if (must_move_add && reg_state[regno].store_ruid == use_ruid) | |
d83ccc81 | 1040 | { |
692ec7c8 | 1041 | if (use->containing_mem == NULL_RTX) |
1042 | delete_add = true; | |
1043 | else | |
1044 | break; | |
d83ccc81 | 1045 | } |
d83ccc81 | 1046 | |
692ec7c8 | 1047 | if (try_replace_in_use (use, reg, src)) |
1048 | { | |
1049 | reload_combine_purge_insn_uses (use_insn); | |
1050 | reload_combine_note_use (&PATTERN (use_insn), use_insn, | |
1051 | use_ruid, NULL_RTX); | |
d83ccc81 | 1052 | |
692ec7c8 | 1053 | if (delete_add) |
1054 | { | |
1055 | fixup_debug_insns (reg, src, insn, use_insn); | |
1056 | delete_insn (insn); | |
1057 | return true; | |
1058 | } | |
1059 | if (must_move_add) | |
1060 | { | |
1061 | add_moved_after_insn = use_insn; | |
1062 | add_moved_after_ruid = use_ruid; | |
d83ccc81 | 1063 | } |
692ec7c8 | 1064 | continue; |
d83ccc81 | 1065 | } |
d83ccc81 | 1066 | } |
6aba0ea1 | 1067 | /* If we get here, we couldn't handle this use. */ |
1068 | if (must_move_add) | |
1069 | break; | |
d83ccc81 | 1070 | } |
1071 | while (use); | |
1072 | ||
1073 | if (!must_move_add || add_moved_after_insn == NULL_RTX) | |
1074 | /* Process the add normally. */ | |
1075 | return false; | |
1076 | ||
65069495 | 1077 | fixup_debug_insns (reg, src, insn, add_moved_after_insn); |
1078 | ||
d83ccc81 | 1079 | reorder_insns (insn, insn, add_moved_after_insn); |
1080 | reload_combine_purge_reg_uses_after_ruid (regno, add_moved_after_ruid); | |
1081 | reload_combine_split_ruids (add_moved_after_ruid - 1); | |
1082 | reload_combine_note_use (&PATTERN (insn), insn, | |
1083 | add_moved_after_ruid, NULL_RTX); | |
1084 | reg_state[regno].store_ruid = add_moved_after_ruid; | |
1085 | ||
1086 | return true; | |
1087 | } | |
1088 | ||
fb79f695 | 1089 | /* Called by reload_combine when scanning INSN. Try to detect a pattern we |
1090 | can handle and improve. Return true if no further processing is needed on | |
1091 | INSN; false if it wasn't recognized and should be handled normally. */ | |
1092 | ||
1093 | static bool | |
1094 | reload_combine_recognize_pattern (rtx insn) | |
1095 | { | |
1096 | rtx set, reg, src; | |
1097 | unsigned int regno; | |
1098 | ||
d83ccc81 | 1099 | set = single_set (insn); |
1100 | if (set == NULL_RTX) | |
1101 | return false; | |
1102 | ||
1103 | reg = SET_DEST (set); | |
1104 | src = SET_SRC (set); | |
1105 | if (!REG_P (reg) | |
1106 | || hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] != 1) | |
1107 | return false; | |
1108 | ||
1109 | regno = REGNO (reg); | |
1110 | ||
fb79f695 | 1111 | /* Look for (set (REGX) (CONST_INT)) |
1112 | (set (REGX) (PLUS (REGX) (REGY))) | |
1113 | ... | |
1114 | ... (MEM (REGX)) ... | |
1115 | and convert it to | |
1116 | (set (REGZ) (CONST_INT)) | |
1117 | ... | |
1118 | ... (MEM (PLUS (REGZ) (REGY)))... . | |
1119 | ||
1120 | First, check that we have (set (REGX) (PLUS (REGX) (REGY))) | |
1121 | and that we know all uses of REGX before it dies. | |
1122 | Also, explicitly check that REGX != REGY; our life information | |
1123 | does not yet show whether REGY changes in this insn. */ | |
fb79f695 | 1124 | |
1125 | if (GET_CODE (src) == PLUS | |
d83ccc81 | 1126 | && reg_state[regno].all_offsets_match |
1127 | && last_index_reg != -1 | |
fb79f695 | 1128 | && REG_P (XEXP (src, 1)) |
1129 | && rtx_equal_p (XEXP (src, 0), reg) | |
1130 | && !rtx_equal_p (XEXP (src, 1), reg) | |
727047d0 | 1131 | && reg_state[regno].use_index >= 0 |
1132 | && reg_state[regno].use_index < RELOAD_COMBINE_MAX_USES | |
fb79f695 | 1133 | && last_label_ruid < reg_state[regno].use_ruid) |
1134 | { | |
1135 | rtx base = XEXP (src, 1); | |
5b8537a8 | 1136 | rtx prev = prev_nonnote_nondebug_insn (insn); |
fb79f695 | 1137 | rtx prev_set = prev ? single_set (prev) : NULL_RTX; |
1138 | rtx index_reg = NULL_RTX; | |
1139 | rtx reg_sum = NULL_RTX; | |
1140 | int i; | |
1141 | ||
1142 | /* Now we need to set INDEX_REG to an index register (denoted as | |
1143 | REGZ in the illustration above) and REG_SUM to the expression | |
1144 | register+register that we want to use to substitute uses of REG | |
1145 | (typically in MEMs) with. First check REG and BASE for being | |
1146 | index registers; we can use them even if they are not dead. */ | |
1147 | if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno) | |
1148 | || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], | |
1149 | REGNO (base))) | |
1150 | { | |
1151 | index_reg = reg; | |
1152 | reg_sum = src; | |
1153 | } | |
1154 | else | |
1155 | { | |
1156 | /* Otherwise, look for a free index register. Since we have | |
1157 | checked above that neither REG nor BASE are index registers, | |
1158 | if we find anything at all, it will be different from these | |
1159 | two registers. */ | |
1160 | for (i = first_index_reg; i <= last_index_reg; i++) | |
1161 | { | |
1162 | if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i) | |
1163 | && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES | |
1164 | && reg_state[i].store_ruid <= reg_state[regno].use_ruid | |
727047d0 | 1165 | && (call_used_regs[i] || df_regs_ever_live_p (i)) |
1166 | && (!frame_pointer_needed || i != HARD_FRAME_POINTER_REGNUM) | |
1167 | && !fixed_regs[i] && !global_regs[i] | |
1168 | && hard_regno_nregs[i][GET_MODE (reg)] == 1 | |
1169 | && targetm.hard_regno_scratch_ok (i)) | |
fb79f695 | 1170 | { |
1171 | index_reg = gen_rtx_REG (GET_MODE (reg), i); | |
1172 | reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base); | |
1173 | break; | |
1174 | } | |
1175 | } | |
1176 | } | |
1177 | ||
1178 | /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that | |
1179 | (REGY), i.e. BASE, is not clobbered before the last use we'll | |
1180 | create. */ | |
1181 | if (reg_sum | |
1182 | && prev_set | |
1183 | && CONST_INT_P (SET_SRC (prev_set)) | |
1184 | && rtx_equal_p (SET_DEST (prev_set), reg) | |
fb79f695 | 1185 | && (reg_state[REGNO (base)].store_ruid |
1186 | <= reg_state[regno].use_ruid)) | |
1187 | { | |
1188 | /* Change destination register and, if necessary, the constant | |
1189 | value in PREV, the constant loading instruction. */ | |
1190 | validate_change (prev, &SET_DEST (prev_set), index_reg, 1); | |
1191 | if (reg_state[regno].offset != const0_rtx) | |
1192 | validate_change (prev, | |
1193 | &SET_SRC (prev_set), | |
1194 | GEN_INT (INTVAL (SET_SRC (prev_set)) | |
1195 | + INTVAL (reg_state[regno].offset)), | |
1196 | 1); | |
1197 | ||
1198 | /* Now for every use of REG that we have recorded, replace REG | |
1199 | with REG_SUM. */ | |
1200 | for (i = reg_state[regno].use_index; | |
1201 | i < RELOAD_COMBINE_MAX_USES; i++) | |
1202 | validate_unshare_change (reg_state[regno].reg_use[i].insn, | |
1203 | reg_state[regno].reg_use[i].usep, | |
1204 | /* Each change must have its own | |
1205 | replacement. */ | |
1206 | reg_sum, 1); | |
1207 | ||
1208 | if (apply_change_group ()) | |
1209 | { | |
65069495 | 1210 | struct reg_use *lowest_ruid = NULL; |
1211 | ||
fb79f695 | 1212 | /* For every new use of REG_SUM, we have to record the use |
1213 | of BASE therein, i.e. operand 1. */ | |
1214 | for (i = reg_state[regno].use_index; | |
1215 | i < RELOAD_COMBINE_MAX_USES; i++) | |
65069495 | 1216 | { |
1217 | struct reg_use *use = reg_state[regno].reg_use + i; | |
1218 | reload_combine_note_use (&XEXP (*use->usep, 1), use->insn, | |
1219 | use->ruid, use->containing_mem); | |
1220 | if (lowest_ruid == NULL || use->ruid < lowest_ruid->ruid) | |
1221 | lowest_ruid = use; | |
1222 | } | |
1223 | ||
1224 | fixup_debug_insns (reg, reg_sum, insn, lowest_ruid->insn); | |
fb79f695 | 1225 | |
fb79f695 | 1226 | /* Delete the reg-reg addition. */ |
1227 | delete_insn (insn); | |
1228 | ||
1229 | if (reg_state[regno].offset != const0_rtx) | |
1230 | /* Previous REG_EQUIV / REG_EQUAL notes for PREV | |
1231 | are now invalid. */ | |
1232 | remove_reg_equal_equiv_notes (prev); | |
1233 | ||
1234 | reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES; | |
fb79f695 | 1235 | return true; |
1236 | } | |
1237 | } | |
1238 | } | |
1239 | return false; | |
1240 | } | |
1241 | ||
8f8cadbc | 1242 | static void |
3ad4992f | 1243 | reload_combine (void) |
8f8cadbc | 1244 | { |
d83ccc81 | 1245 | rtx insn, prev; |
8f8cadbc | 1246 | basic_block bb; |
1247 | unsigned int r; | |
8f8cadbc | 1248 | int min_labelno, n_labels; |
1249 | HARD_REG_SET ever_live_at_start, *label_live; | |
1250 | ||
8f8cadbc | 1251 | /* To avoid wasting too much time later searching for an index register, |
1252 | determine the minimum and maximum index register numbers. */ | |
fb79f695 | 1253 | if (INDEX_REG_CLASS == NO_REGS) |
1254 | last_index_reg = -1; | |
1255 | else if (first_index_reg == -1 && last_index_reg == 0) | |
1256 | { | |
1257 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) | |
1258 | if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r)) | |
1259 | { | |
1260 | if (first_index_reg == -1) | |
1261 | first_index_reg = r; | |
1262 | ||
1263 | last_index_reg = r; | |
1264 | } | |
1265 | ||
1266 | /* If no index register is available, we can quit now. Set LAST_INDEX_REG | |
1267 | to -1 so we'll know to quit early the next time we get here. */ | |
1268 | if (first_index_reg == -1) | |
1269 | { | |
1270 | last_index_reg = -1; | |
1271 | return; | |
1272 | } | |
1273 | } | |
8f8cadbc | 1274 | |
8f8cadbc | 1275 | /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime |
1276 | information is a bit fuzzy immediately after reload, but it's | |
1277 | still good enough to determine which registers are live at a jump | |
1278 | destination. */ | |
1279 | min_labelno = get_first_label_num (); | |
1280 | n_labels = max_label_num () - min_labelno; | |
4c36ffe6 | 1281 | label_live = XNEWVEC (HARD_REG_SET, n_labels); |
8f8cadbc | 1282 | CLEAR_HARD_REG_SET (ever_live_at_start); |
1283 | ||
7a46197b | 1284 | FOR_EACH_BB_REVERSE_FN (bb, cfun) |
8f8cadbc | 1285 | { |
5496dbfc | 1286 | insn = BB_HEAD (bb); |
6d7dc5b9 | 1287 | if (LABEL_P (insn)) |
8f8cadbc | 1288 | { |
1289 | HARD_REG_SET live; | |
deb2741b | 1290 | bitmap live_in = df_get_live_in (bb); |
8f8cadbc | 1291 | |
deb2741b | 1292 | REG_SET_TO_HARD_REG_SET (live, live_in); |
1293 | compute_use_by_pseudos (&live, live_in); | |
8f8cadbc | 1294 | COPY_HARD_REG_SET (LABEL_LIVE (insn), live); |
1295 | IOR_HARD_REG_SET (ever_live_at_start, live); | |
1296 | } | |
1297 | } | |
1298 | ||
1299 | /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */ | |
d83ccc81 | 1300 | last_label_ruid = last_jump_ruid = reload_combine_ruid = 0; |
8f8cadbc | 1301 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) |
1302 | { | |
d83ccc81 | 1303 | reg_state[r].store_ruid = 0; |
1304 | reg_state[r].real_store_ruid = 0; | |
8f8cadbc | 1305 | if (fixed_regs[r]) |
1306 | reg_state[r].use_index = -1; | |
1307 | else | |
1308 | reg_state[r].use_index = RELOAD_COMBINE_MAX_USES; | |
1309 | } | |
1310 | ||
d83ccc81 | 1311 | for (insn = get_last_insn (); insn; insn = prev) |
8f8cadbc | 1312 | { |
8b52f64e | 1313 | bool control_flow_insn; |
8f8cadbc | 1314 | rtx note; |
1315 | ||
d83ccc81 | 1316 | prev = PREV_INSN (insn); |
1317 | ||
8f8cadbc | 1318 | /* We cannot do our optimization across labels. Invalidating all the use |
1319 | information we have would be costly, so we just note where the label | |
1320 | is and then later disable any optimization that would cross it. */ | |
6d7dc5b9 | 1321 | if (LABEL_P (insn)) |
8f8cadbc | 1322 | last_label_ruid = reload_combine_ruid; |
19f69355 | 1323 | else if (BARRIER_P (insn)) |
1324 | { | |
1325 | /* Crossing a barrier resets all the use information. */ | |
1326 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) | |
1327 | if (! fixed_regs[r]) | |
8f8cadbc | 1328 | reg_state[r].use_index = RELOAD_COMBINE_MAX_USES; |
19f69355 | 1329 | } |
1330 | else if (INSN_P (insn) && volatile_insn_p (PATTERN (insn))) | |
1331 | /* Optimizations across insns being marked as volatile must be | |
1332 | prevented. All the usage information is invalidated | |
1333 | here. */ | |
1334 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) | |
1335 | if (! fixed_regs[r] | |
1336 | && reg_state[r].use_index != RELOAD_COMBINE_MAX_USES) | |
1337 | reg_state[r].use_index = -1; | |
8f8cadbc | 1338 | |
65069495 | 1339 | if (! NONDEBUG_INSN_P (insn)) |
8f8cadbc | 1340 | continue; |
1341 | ||
1342 | reload_combine_ruid++; | |
1343 | ||
8b52f64e | 1344 | control_flow_insn = control_flow_insn_p (insn); |
1345 | if (control_flow_insn) | |
d83ccc81 | 1346 | last_jump_ruid = reload_combine_ruid; |
1347 | ||
1348 | if (reload_combine_recognize_const_pattern (insn) | |
1349 | || reload_combine_recognize_pattern (insn)) | |
fb79f695 | 1350 | continue; |
8f8cadbc | 1351 | |
1352 | note_stores (PATTERN (insn), reload_combine_note_store, NULL); | |
1353 | ||
6d7dc5b9 | 1354 | if (CALL_P (insn)) |
8f8cadbc | 1355 | { |
1356 | rtx link; | |
1357 | ||
1358 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) | |
1359 | if (call_used_regs[r]) | |
1360 | { | |
1361 | reg_state[r].use_index = RELOAD_COMBINE_MAX_USES; | |
1362 | reg_state[r].store_ruid = reload_combine_ruid; | |
1363 | } | |
1364 | ||
1365 | for (link = CALL_INSN_FUNCTION_USAGE (insn); link; | |
1366 | link = XEXP (link, 1)) | |
1367 | { | |
c8010b80 | 1368 | rtx setuse = XEXP (link, 0); |
1369 | rtx usage_rtx = XEXP (setuse, 0); | |
1370 | if ((GET_CODE (setuse) == USE || GET_CODE (setuse) == CLOBBER) | |
1371 | && REG_P (usage_rtx)) | |
8f8cadbc | 1372 | { |
1373 | unsigned int i; | |
1374 | unsigned int start_reg = REGNO (usage_rtx); | |
8b52f64e | 1375 | unsigned int num_regs |
1376 | = hard_regno_nregs[start_reg][GET_MODE (usage_rtx)]; | |
1377 | unsigned int end_reg = start_reg + num_regs - 1; | |
8f8cadbc | 1378 | for (i = start_reg; i <= end_reg; i++) |
1379 | if (GET_CODE (XEXP (link, 0)) == CLOBBER) | |
1380 | { | |
1381 | reg_state[i].use_index = RELOAD_COMBINE_MAX_USES; | |
1382 | reg_state[i].store_ruid = reload_combine_ruid; | |
1383 | } | |
1384 | else | |
1385 | reg_state[i].use_index = -1; | |
1386 | } | |
1387 | } | |
8f8cadbc | 1388 | } |
f4979459 | 1389 | |
7777a939 | 1390 | if (control_flow_insn && !ANY_RETURN_P (PATTERN (insn))) |
8f8cadbc | 1391 | { |
1392 | /* Non-spill registers might be used at the call destination in | |
1393 | some unknown fashion, so we have to mark the unknown use. */ | |
1394 | HARD_REG_SET *live; | |
1395 | ||
1396 | if ((condjump_p (insn) || condjump_in_parallel_p (insn)) | |
1397 | && JUMP_LABEL (insn)) | |
7777a939 | 1398 | { |
1399 | if (ANY_RETURN_P (JUMP_LABEL (insn))) | |
1400 | live = NULL; | |
1401 | else | |
1402 | live = &LABEL_LIVE (JUMP_LABEL (insn)); | |
1403 | } | |
8f8cadbc | 1404 | else |
1405 | live = &ever_live_at_start; | |
1406 | ||
7777a939 | 1407 | if (live) |
1408 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) | |
1409 | if (TEST_HARD_REG_BIT (*live, r)) | |
1410 | reg_state[r].use_index = -1; | |
8f8cadbc | 1411 | } |
1412 | ||
8b52f64e | 1413 | reload_combine_note_use (&PATTERN (insn), insn, reload_combine_ruid, |
1414 | NULL_RTX); | |
1415 | ||
8f8cadbc | 1416 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) |
1417 | { | |
8b52f64e | 1418 | if (REG_NOTE_KIND (note) == REG_INC && REG_P (XEXP (note, 0))) |
8f8cadbc | 1419 | { |
1420 | int regno = REGNO (XEXP (note, 0)); | |
8f8cadbc | 1421 | reg_state[regno].store_ruid = reload_combine_ruid; |
d83ccc81 | 1422 | reg_state[regno].real_store_ruid = reload_combine_ruid; |
8f8cadbc | 1423 | reg_state[regno].use_index = -1; |
1424 | } | |
1425 | } | |
1426 | } | |
1427 | ||
1428 | free (label_live); | |
1429 | } | |
1430 | ||
1431 | /* Check if DST is a register or a subreg of a register; if it is, | |
d83ccc81 | 1432 | update store_ruid, real_store_ruid and use_index in the reg_state |
1433 | structure accordingly. Called via note_stores from reload_combine. */ | |
8f8cadbc | 1434 | |
1435 | static void | |
81a410b1 | 1436 | reload_combine_note_store (rtx dst, const_rtx set, void *data ATTRIBUTE_UNUSED) |
8f8cadbc | 1437 | { |
1438 | int regno = 0; | |
1439 | int i; | |
1440 | enum machine_mode mode = GET_MODE (dst); | |
1441 | ||
1442 | if (GET_CODE (dst) == SUBREG) | |
1443 | { | |
1444 | regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)), | |
1445 | GET_MODE (SUBREG_REG (dst)), | |
1446 | SUBREG_BYTE (dst), | |
1447 | GET_MODE (dst)); | |
1448 | dst = SUBREG_REG (dst); | |
1449 | } | |
fe6524b0 | 1450 | |
1451 | /* Some targets do argument pushes without adding REG_INC notes. */ | |
1452 | ||
1453 | if (MEM_P (dst)) | |
1454 | { | |
1455 | dst = XEXP (dst, 0); | |
1456 | if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_INC | |
a5dda0b9 | 1457 | || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC |
1458 | || GET_CODE (dst) == PRE_MODIFY || GET_CODE (dst) == POST_MODIFY) | |
fe6524b0 | 1459 | { |
1460 | regno = REGNO (XEXP (dst, 0)); | |
1461 | mode = GET_MODE (XEXP (dst, 0)); | |
1462 | for (i = hard_regno_nregs[regno][mode] - 1 + regno; i >= regno; i--) | |
1463 | { | |
1464 | /* We could probably do better, but for now mark the register | |
1465 | as used in an unknown fashion and set/clobbered at this | |
1466 | insn. */ | |
1467 | reg_state[i].use_index = -1; | |
1468 | reg_state[i].store_ruid = reload_combine_ruid; | |
1469 | reg_state[i].real_store_ruid = reload_combine_ruid; | |
1470 | } | |
1471 | } | |
1472 | else | |
1473 | return; | |
1474 | } | |
1475 | ||
8ad4c111 | 1476 | if (!REG_P (dst)) |
8f8cadbc | 1477 | return; |
1478 | regno += REGNO (dst); | |
1479 | ||
1480 | /* note_stores might have stripped a STRICT_LOW_PART, so we have to be | |
1481 | careful with registers / register parts that are not full words. | |
476d094d | 1482 | Similarly for ZERO_EXTRACT. */ |
d83ccc81 | 1483 | if (GET_CODE (SET_DEST (set)) == ZERO_EXTRACT |
8f8cadbc | 1484 | || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART) |
1485 | { | |
67d6c12b | 1486 | for (i = hard_regno_nregs[regno][mode] - 1 + regno; i >= regno; i--) |
8f8cadbc | 1487 | { |
1488 | reg_state[i].use_index = -1; | |
1489 | reg_state[i].store_ruid = reload_combine_ruid; | |
d83ccc81 | 1490 | reg_state[i].real_store_ruid = reload_combine_ruid; |
8f8cadbc | 1491 | } |
1492 | } | |
1493 | else | |
1494 | { | |
67d6c12b | 1495 | for (i = hard_regno_nregs[regno][mode] - 1 + regno; i >= regno; i--) |
8f8cadbc | 1496 | { |
1497 | reg_state[i].store_ruid = reload_combine_ruid; | |
d83ccc81 | 1498 | if (GET_CODE (set) == SET) |
1499 | reg_state[i].real_store_ruid = reload_combine_ruid; | |
8f8cadbc | 1500 | reg_state[i].use_index = RELOAD_COMBINE_MAX_USES; |
1501 | } | |
1502 | } | |
1503 | } | |
1504 | ||
1505 | /* XP points to a piece of rtl that has to be checked for any uses of | |
1506 | registers. | |
1507 | *XP is the pattern of INSN, or a part of it. | |
1508 | Called from reload_combine, and recursively by itself. */ | |
1509 | static void | |
d83ccc81 | 1510 | reload_combine_note_use (rtx *xp, rtx insn, int ruid, rtx containing_mem) |
8f8cadbc | 1511 | { |
1512 | rtx x = *xp; | |
1513 | enum rtx_code code = x->code; | |
1514 | const char *fmt; | |
1515 | int i, j; | |
1516 | rtx offset = const0_rtx; /* For the REG case below. */ | |
1517 | ||
1518 | switch (code) | |
1519 | { | |
1520 | case SET: | |
8ad4c111 | 1521 | if (REG_P (SET_DEST (x))) |
8f8cadbc | 1522 | { |
d83ccc81 | 1523 | reload_combine_note_use (&SET_SRC (x), insn, ruid, NULL_RTX); |
8f8cadbc | 1524 | return; |
1525 | } | |
1526 | break; | |
1527 | ||
1528 | case USE: | |
1529 | /* If this is the USE of a return value, we can't change it. */ | |
8ad4c111 | 1530 | if (REG_P (XEXP (x, 0)) && REG_FUNCTION_VALUE_P (XEXP (x, 0))) |
8f8cadbc | 1531 | { |
1532 | /* Mark the return register as used in an unknown fashion. */ | |
1533 | rtx reg = XEXP (x, 0); | |
1534 | int regno = REGNO (reg); | |
67d6c12b | 1535 | int nregs = hard_regno_nregs[regno][GET_MODE (reg)]; |
8f8cadbc | 1536 | |
1537 | while (--nregs >= 0) | |
1538 | reg_state[regno + nregs].use_index = -1; | |
1539 | return; | |
1540 | } | |
1541 | break; | |
1542 | ||
1543 | case CLOBBER: | |
8ad4c111 | 1544 | if (REG_P (SET_DEST (x))) |
8f8cadbc | 1545 | { |
1546 | /* No spurious CLOBBERs of pseudo registers may remain. */ | |
876760f6 | 1547 | gcc_assert (REGNO (SET_DEST (x)) < FIRST_PSEUDO_REGISTER); |
8f8cadbc | 1548 | return; |
1549 | } | |
1550 | break; | |
1551 | ||
1552 | case PLUS: | |
1553 | /* We are interested in (plus (reg) (const_int)) . */ | |
8ad4c111 | 1554 | if (!REG_P (XEXP (x, 0)) |
971ba038 | 1555 | || !CONST_INT_P (XEXP (x, 1))) |
8f8cadbc | 1556 | break; |
1557 | offset = XEXP (x, 1); | |
1558 | x = XEXP (x, 0); | |
1559 | /* Fall through. */ | |
1560 | case REG: | |
1561 | { | |
1562 | int regno = REGNO (x); | |
1563 | int use_index; | |
1564 | int nregs; | |
1565 | ||
1566 | /* No spurious USEs of pseudo registers may remain. */ | |
876760f6 | 1567 | gcc_assert (regno < FIRST_PSEUDO_REGISTER); |
8f8cadbc | 1568 | |
67d6c12b | 1569 | nregs = hard_regno_nregs[regno][GET_MODE (x)]; |
8f8cadbc | 1570 | |
1571 | /* We can't substitute into multi-hard-reg uses. */ | |
1572 | if (nregs > 1) | |
1573 | { | |
1574 | while (--nregs >= 0) | |
1575 | reg_state[regno + nregs].use_index = -1; | |
1576 | return; | |
1577 | } | |
1578 | ||
727047d0 | 1579 | /* We may be called to update uses in previously seen insns. |
1580 | Don't add uses beyond the last store we saw. */ | |
1581 | if (ruid < reg_state[regno].store_ruid) | |
1582 | return; | |
1583 | ||
8f8cadbc | 1584 | /* If this register is already used in some unknown fashion, we |
1585 | can't do anything. | |
1586 | If we decrement the index from zero to -1, we can't store more | |
1587 | uses, so this register becomes used in an unknown fashion. */ | |
1588 | use_index = --reg_state[regno].use_index; | |
1589 | if (use_index < 0) | |
1590 | return; | |
1591 | ||
d83ccc81 | 1592 | if (use_index == RELOAD_COMBINE_MAX_USES - 1) |
8f8cadbc | 1593 | { |
1594 | /* This is the first use of this register we have seen since we | |
1595 | marked it as dead. */ | |
1596 | reg_state[regno].offset = offset; | |
d83ccc81 | 1597 | reg_state[regno].all_offsets_match = true; |
1598 | reg_state[regno].use_ruid = ruid; | |
8f8cadbc | 1599 | } |
0ead6a7d | 1600 | else |
1601 | { | |
1602 | if (reg_state[regno].use_ruid > ruid) | |
1603 | reg_state[regno].use_ruid = ruid; | |
1604 | ||
1605 | if (! rtx_equal_p (offset, reg_state[regno].offset)) | |
1606 | reg_state[regno].all_offsets_match = false; | |
1607 | } | |
d83ccc81 | 1608 | |
8f8cadbc | 1609 | reg_state[regno].reg_use[use_index].insn = insn; |
d83ccc81 | 1610 | reg_state[regno].reg_use[use_index].ruid = ruid; |
1611 | reg_state[regno].reg_use[use_index].containing_mem = containing_mem; | |
8f8cadbc | 1612 | reg_state[regno].reg_use[use_index].usep = xp; |
1613 | return; | |
1614 | } | |
1615 | ||
d83ccc81 | 1616 | case MEM: |
1617 | containing_mem = x; | |
1618 | break; | |
1619 | ||
8f8cadbc | 1620 | default: |
1621 | break; | |
1622 | } | |
1623 | ||
1624 | /* Recursively process the components of X. */ | |
1625 | fmt = GET_RTX_FORMAT (code); | |
1626 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1627 | { | |
1628 | if (fmt[i] == 'e') | |
d83ccc81 | 1629 | reload_combine_note_use (&XEXP (x, i), insn, ruid, containing_mem); |
8f8cadbc | 1630 | else if (fmt[i] == 'E') |
1631 | { | |
1632 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
d83ccc81 | 1633 | reload_combine_note_use (&XVECEXP (x, i, j), insn, ruid, |
1634 | containing_mem); | |
8f8cadbc | 1635 | } |
1636 | } | |
1637 | } | |
1638 | \f | |
1639 | /* See if we can reduce the cost of a constant by replacing a move | |
1640 | with an add. We track situations in which a register is set to a | |
1641 | constant or to a register plus a constant. */ | |
1642 | /* We cannot do our optimization across labels. Invalidating all the | |
1643 | information about register contents we have would be costly, so we | |
1644 | use move2add_last_label_luid to note where the label is and then | |
1645 | later disable any optimization that would cross it. | |
6132c0d0 | 1646 | reg_offset[n] / reg_base_reg[n] / reg_symbol_ref[n] / reg_mode[n] |
1647 | are only valid if reg_set_luid[n] is greater than | |
b6b86e87 | 1648 | move2add_last_label_luid. |
1649 | For a set that established a new (potential) base register with | |
1650 | non-constant value, we use move2add_luid from the place where the | |
1651 | setting insn is encountered; registers based off that base then | |
1652 | get the same reg_set_luid. Constants all get | |
1653 | move2add_last_label_luid + 1 as their reg_set_luid. */ | |
8f8cadbc | 1654 | static int reg_set_luid[FIRST_PSEUDO_REGISTER]; |
1655 | ||
1656 | /* If reg_base_reg[n] is negative, register n has been set to | |
6132c0d0 | 1657 | reg_offset[n] or reg_symbol_ref[n] + reg_offset[n] in mode reg_mode[n]. |
8f8cadbc | 1658 | If reg_base_reg[n] is non-negative, register n has been set to the |
1659 | sum of reg_offset[n] and the value of register reg_base_reg[n] | |
b6b86e87 | 1660 | before reg_set_luid[n], calculated in mode reg_mode[n] . |
1661 | For multi-hard-register registers, all but the first one are | |
1662 | recorded as BLKmode in reg_mode. Setting reg_mode to VOIDmode | |
1663 | marks it as invalid. */ | |
8f8cadbc | 1664 | static HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER]; |
1665 | static int reg_base_reg[FIRST_PSEUDO_REGISTER]; | |
6132c0d0 | 1666 | static rtx reg_symbol_ref[FIRST_PSEUDO_REGISTER]; |
8f8cadbc | 1667 | static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER]; |
1668 | ||
1669 | /* move2add_luid is linearly increased while scanning the instructions | |
1670 | from first to last. It is used to set reg_set_luid in | |
1671 | reload_cse_move2add and move2add_note_store. */ | |
1672 | static int move2add_luid; | |
1673 | ||
1674 | /* move2add_last_label_luid is set whenever a label is found. Labels | |
1675 | invalidate all previously collected reg_offset data. */ | |
1676 | static int move2add_last_label_luid; | |
1677 | ||
1678 | /* ??? We don't know how zero / sign extension is handled, hence we | |
1679 | can't go from a narrower to a wider mode. */ | |
1680 | #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \ | |
1681 | (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \ | |
1682 | || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \ | |
396f2130 | 1683 | && TRULY_NOOP_TRUNCATION_MODES_P (OUTMODE, INMODE))) |
8f8cadbc | 1684 | |
b6b86e87 | 1685 | /* Record that REG is being set to a value with the mode of REG. */ |
1686 | ||
1687 | static void | |
1688 | move2add_record_mode (rtx reg) | |
1689 | { | |
1690 | int regno, nregs; | |
1691 | enum machine_mode mode = GET_MODE (reg); | |
1692 | ||
1693 | if (GET_CODE (reg) == SUBREG) | |
1694 | { | |
1695 | regno = subreg_regno (reg); | |
1696 | nregs = subreg_nregs (reg); | |
1697 | } | |
1698 | else if (REG_P (reg)) | |
1699 | { | |
1700 | regno = REGNO (reg); | |
1701 | nregs = hard_regno_nregs[regno][mode]; | |
1702 | } | |
1703 | else | |
1704 | gcc_unreachable (); | |
1705 | for (int i = nregs - 1; i > 0; i--) | |
1706 | reg_mode[regno + i] = BLKmode; | |
1707 | reg_mode[regno] = mode; | |
1708 | } | |
1709 | ||
1710 | /* Record that REG is being set to the sum of SYM and OFF. */ | |
1711 | ||
1712 | static void | |
1713 | move2add_record_sym_value (rtx reg, rtx sym, rtx off) | |
1714 | { | |
1715 | int regno = REGNO (reg); | |
1716 | ||
1717 | move2add_record_mode (reg); | |
1718 | reg_set_luid[regno] = move2add_luid; | |
1719 | reg_base_reg[regno] = -1; | |
1720 | reg_symbol_ref[regno] = sym; | |
1721 | reg_offset[regno] = INTVAL (off); | |
1722 | } | |
1723 | ||
1724 | /* Check if REGNO contains a valid value in MODE. */ | |
1725 | ||
1726 | static bool | |
1727 | move2add_valid_value_p (int regno, enum machine_mode mode) | |
1728 | { | |
5bea3269 | 1729 | if (reg_set_luid[regno] <= move2add_last_label_luid) |
b6b86e87 | 1730 | return false; |
1731 | ||
5bea3269 | 1732 | if (mode != reg_mode[regno]) |
1733 | { | |
1734 | if (!MODES_OK_FOR_MOVE2ADD (mode, reg_mode[regno])) | |
1735 | return false; | |
1736 | /* The value loaded into regno in reg_mode[regno] is also valid in | |
1737 | mode after truncation only if (REG:mode regno) is the lowpart of | |
1738 | (REG:reg_mode[regno] regno). Now, for big endian, the starting | |
1739 | regno of the lowpart might be different. */ | |
1740 | int s_off = subreg_lowpart_offset (mode, reg_mode[regno]); | |
1741 | s_off = subreg_regno_offset (regno, reg_mode[regno], s_off, mode); | |
1742 | if (s_off != 0) | |
1743 | /* We could in principle adjust regno, check reg_mode[regno] to be | |
1744 | BLKmode, and return s_off to the caller (vs. -1 for failure), | |
1745 | but we currently have no callers that could make use of this | |
1746 | information. */ | |
1747 | return false; | |
1748 | } | |
1749 | ||
b6b86e87 | 1750 | for (int i = hard_regno_nregs[regno][mode] - 1; i > 0; i--) |
1751 | if (reg_mode[regno + i] != BLKmode) | |
1752 | return false; | |
1753 | return true; | |
1754 | } | |
1755 | ||
6132c0d0 | 1756 | /* This function is called with INSN that sets REG to (SYM + OFF), |
1757 | while REG is known to already have value (SYM + offset). | |
1758 | This function tries to change INSN into an add instruction | |
1759 | (set (REG) (plus (REG) (OFF - offset))) using the known value. | |
d83ccc81 | 1760 | It also updates the information about REG's known value. |
1761 | Return true if we made a change. */ | |
6132c0d0 | 1762 | |
d83ccc81 | 1763 | static bool |
6132c0d0 | 1764 | move2add_use_add2_insn (rtx reg, rtx sym, rtx off, rtx insn) |
1765 | { | |
1766 | rtx pat = PATTERN (insn); | |
1767 | rtx src = SET_SRC (pat); | |
1768 | int regno = REGNO (reg); | |
60141df0 | 1769 | rtx new_src = gen_int_mode (UINTVAL (off) - reg_offset[regno], |
6132c0d0 | 1770 | GET_MODE (reg)); |
1771 | bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); | |
d83ccc81 | 1772 | bool changed = false; |
6132c0d0 | 1773 | |
1774 | /* (set (reg) (plus (reg) (const_int 0))) is not canonical; | |
1775 | use (set (reg) (reg)) instead. | |
1776 | We don't delete this insn, nor do we convert it into a | |
1777 | note, to avoid losing register notes or the return | |
1778 | value flag. jump2 already knows how to get rid of | |
1779 | no-op moves. */ | |
1780 | if (new_src == const0_rtx) | |
1781 | { | |
1782 | /* If the constants are different, this is a | |
1783 | truncation, that, if turned into (set (reg) | |
1784 | (reg)), would be discarded. Maybe we should | |
1785 | try a truncMN pattern? */ | |
1786 | if (INTVAL (off) == reg_offset [regno]) | |
d83ccc81 | 1787 | changed = validate_change (insn, &SET_SRC (pat), reg, 0); |
6132c0d0 | 1788 | } |
c9a03487 | 1789 | else |
6132c0d0 | 1790 | { |
c9a03487 | 1791 | struct full_rtx_costs oldcst, newcst; |
6132c0d0 | 1792 | rtx tem = gen_rtx_PLUS (GET_MODE (reg), reg, new_src); |
c9a03487 | 1793 | |
b72d459f | 1794 | get_full_set_rtx_cost (pat, &oldcst); |
c9a03487 | 1795 | SET_SRC (pat) = tem; |
b72d459f | 1796 | get_full_set_rtx_cost (pat, &newcst); |
c9a03487 | 1797 | SET_SRC (pat) = src; |
1798 | ||
1799 | if (costs_lt_p (&newcst, &oldcst, speed) | |
1800 | && have_add2_insn (reg, new_src)) | |
1801 | changed = validate_change (insn, &SET_SRC (pat), tem, 0); | |
1802 | else if (sym == NULL_RTX && GET_MODE (reg) != BImode) | |
6132c0d0 | 1803 | { |
c9a03487 | 1804 | enum machine_mode narrow_mode; |
1805 | for (narrow_mode = GET_CLASS_NARROWEST_MODE (MODE_INT); | |
1806 | narrow_mode != VOIDmode | |
1807 | && narrow_mode != GET_MODE (reg); | |
1808 | narrow_mode = GET_MODE_WIDER_MODE (narrow_mode)) | |
6132c0d0 | 1809 | { |
c9a03487 | 1810 | if (have_insn_for (STRICT_LOW_PART, narrow_mode) |
1811 | && ((reg_offset[regno] & ~GET_MODE_MASK (narrow_mode)) | |
1812 | == (INTVAL (off) & ~GET_MODE_MASK (narrow_mode)))) | |
1813 | { | |
17ce39e3 | 1814 | rtx narrow_reg = gen_lowpart_common (narrow_mode, reg); |
c9a03487 | 1815 | rtx narrow_src = gen_int_mode (INTVAL (off), |
1816 | narrow_mode); | |
1817 | rtx new_set | |
1818 | = gen_rtx_SET (VOIDmode, | |
1819 | gen_rtx_STRICT_LOW_PART (VOIDmode, | |
1820 | narrow_reg), | |
1821 | narrow_src); | |
1822 | changed = validate_change (insn, &PATTERN (insn), | |
1823 | new_set, 0); | |
1824 | if (changed) | |
1825 | break; | |
1826 | } | |
6132c0d0 | 1827 | } |
1828 | } | |
1829 | } | |
b6b86e87 | 1830 | move2add_record_sym_value (reg, sym, off); |
d83ccc81 | 1831 | return changed; |
6132c0d0 | 1832 | } |
1833 | ||
1834 | ||
1835 | /* This function is called with INSN that sets REG to (SYM + OFF), | |
1836 | but REG doesn't have known value (SYM + offset). This function | |
1837 | tries to find another register which is known to already have | |
1838 | value (SYM + offset) and change INSN into an add instruction | |
1839 | (set (REG) (plus (the found register) (OFF - offset))) if such | |
1840 | a register is found. It also updates the information about | |
d83ccc81 | 1841 | REG's known value. |
1842 | Return true iff we made a change. */ | |
6132c0d0 | 1843 | |
d83ccc81 | 1844 | static bool |
6132c0d0 | 1845 | move2add_use_add3_insn (rtx reg, rtx sym, rtx off, rtx insn) |
1846 | { | |
1847 | rtx pat = PATTERN (insn); | |
1848 | rtx src = SET_SRC (pat); | |
1849 | int regno = REGNO (reg); | |
c2130a4b | 1850 | int min_regno = 0; |
6132c0d0 | 1851 | bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); |
1852 | int i; | |
d83ccc81 | 1853 | bool changed = false; |
c9a03487 | 1854 | struct full_rtx_costs oldcst, newcst, mincst; |
1855 | rtx plus_expr; | |
1856 | ||
1857 | init_costs_to_max (&mincst); | |
b72d459f | 1858 | get_full_set_rtx_cost (pat, &oldcst); |
c9a03487 | 1859 | |
1860 | plus_expr = gen_rtx_PLUS (GET_MODE (reg), reg, const0_rtx); | |
1861 | SET_SRC (pat) = plus_expr; | |
6132c0d0 | 1862 | |
1863 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
b6b86e87 | 1864 | if (move2add_valid_value_p (i, GET_MODE (reg)) |
6132c0d0 | 1865 | && reg_base_reg[i] < 0 |
1866 | && reg_symbol_ref[i] != NULL_RTX | |
1867 | && rtx_equal_p (sym, reg_symbol_ref[i])) | |
1868 | { | |
60141df0 | 1869 | rtx new_src = gen_int_mode (UINTVAL (off) - reg_offset[i], |
6132c0d0 | 1870 | GET_MODE (reg)); |
1871 | /* (set (reg) (plus (reg) (const_int 0))) is not canonical; | |
1872 | use (set (reg) (reg)) instead. | |
1873 | We don't delete this insn, nor do we convert it into a | |
1874 | note, to avoid losing register notes or the return | |
1875 | value flag. jump2 already knows how to get rid of | |
1876 | no-op moves. */ | |
1877 | if (new_src == const0_rtx) | |
1878 | { | |
c9a03487 | 1879 | init_costs_to_zero (&mincst); |
6132c0d0 | 1880 | min_regno = i; |
1881 | break; | |
1882 | } | |
1883 | else | |
1884 | { | |
c9a03487 | 1885 | XEXP (plus_expr, 1) = new_src; |
b72d459f | 1886 | get_full_set_rtx_cost (pat, &newcst); |
c9a03487 | 1887 | |
1888 | if (costs_lt_p (&newcst, &mincst, speed)) | |
6132c0d0 | 1889 | { |
c9a03487 | 1890 | mincst = newcst; |
6132c0d0 | 1891 | min_regno = i; |
1892 | } | |
1893 | } | |
1894 | } | |
c9a03487 | 1895 | SET_SRC (pat) = src; |
6132c0d0 | 1896 | |
c9a03487 | 1897 | if (costs_lt_p (&mincst, &oldcst, speed)) |
6132c0d0 | 1898 | { |
1899 | rtx tem; | |
1900 | ||
1901 | tem = gen_rtx_REG (GET_MODE (reg), min_regno); | |
1902 | if (i != min_regno) | |
1903 | { | |
60141df0 | 1904 | rtx new_src = gen_int_mode (UINTVAL (off) - reg_offset[min_regno], |
6132c0d0 | 1905 | GET_MODE (reg)); |
1906 | tem = gen_rtx_PLUS (GET_MODE (reg), tem, new_src); | |
1907 | } | |
d83ccc81 | 1908 | if (validate_change (insn, &SET_SRC (pat), tem, 0)) |
1909 | changed = true; | |
6132c0d0 | 1910 | } |
1911 | reg_set_luid[regno] = move2add_luid; | |
b6b86e87 | 1912 | move2add_record_sym_value (reg, sym, off); |
d83ccc81 | 1913 | return changed; |
6132c0d0 | 1914 | } |
1915 | ||
d83ccc81 | 1916 | /* Convert move insns with constant inputs to additions if they are cheaper. |
1917 | Return true if any changes were made. */ | |
1918 | static bool | |
3ad4992f | 1919 | reload_cse_move2add (rtx first) |
8f8cadbc | 1920 | { |
1921 | int i; | |
1922 | rtx insn; | |
d83ccc81 | 1923 | bool changed = false; |
8f8cadbc | 1924 | |
1925 | for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--) | |
6132c0d0 | 1926 | { |
1927 | reg_set_luid[i] = 0; | |
1928 | reg_offset[i] = 0; | |
1929 | reg_base_reg[i] = 0; | |
1930 | reg_symbol_ref[i] = NULL_RTX; | |
1931 | reg_mode[i] = VOIDmode; | |
1932 | } | |
8f8cadbc | 1933 | |
1934 | move2add_last_label_luid = 0; | |
1935 | move2add_luid = 2; | |
1936 | for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++) | |
1937 | { | |
1938 | rtx pat, note; | |
1939 | ||
6d7dc5b9 | 1940 | if (LABEL_P (insn)) |
8f8cadbc | 1941 | { |
1942 | move2add_last_label_luid = move2add_luid; | |
1943 | /* We're going to increment move2add_luid twice after a | |
1944 | label, so that we can use move2add_last_label_luid + 1 as | |
1945 | the luid for constants. */ | |
1946 | move2add_luid++; | |
1947 | continue; | |
1948 | } | |
1949 | if (! INSN_P (insn)) | |
1950 | continue; | |
1951 | pat = PATTERN (insn); | |
1952 | /* For simplicity, we only perform this optimization on | |
1953 | straightforward SETs. */ | |
1954 | if (GET_CODE (pat) == SET | |
8ad4c111 | 1955 | && REG_P (SET_DEST (pat))) |
8f8cadbc | 1956 | { |
1957 | rtx reg = SET_DEST (pat); | |
1958 | int regno = REGNO (reg); | |
1959 | rtx src = SET_SRC (pat); | |
1960 | ||
1961 | /* Check if we have valid information on the contents of this | |
1962 | register in the mode of REG. */ | |
b6b86e87 | 1963 | if (move2add_valid_value_p (regno, GET_MODE (reg)) |
3072d30e | 1964 | && dbg_cnt (cse2_move2add)) |
8f8cadbc | 1965 | { |
1966 | /* Try to transform (set (REGX) (CONST_INT A)) | |
1967 | ... | |
1968 | (set (REGX) (CONST_INT B)) | |
1969 | to | |
1970 | (set (REGX) (CONST_INT A)) | |
1971 | ... | |
1972 | (set (REGX) (plus (REGX) (CONST_INT B-A))) | |
1973 | or | |
1974 | (set (REGX) (CONST_INT A)) | |
1975 | ... | |
1976 | (set (STRICT_LOW_PART (REGX)) (CONST_INT B)) | |
1977 | */ | |
1978 | ||
6132c0d0 | 1979 | if (CONST_INT_P (src) |
1980 | && reg_base_reg[regno] < 0 | |
1981 | && reg_symbol_ref[regno] == NULL_RTX) | |
8f8cadbc | 1982 | { |
d83ccc81 | 1983 | changed |= move2add_use_add2_insn (reg, NULL_RTX, src, insn); |
8f8cadbc | 1984 | continue; |
1985 | } | |
1986 | ||
1987 | /* Try to transform (set (REGX) (REGY)) | |
1988 | (set (REGX) (PLUS (REGX) (CONST_INT A))) | |
1989 | ... | |
1990 | (set (REGX) (REGY)) | |
1991 | (set (REGX) (PLUS (REGX) (CONST_INT B))) | |
1992 | to | |
1993 | (set (REGX) (REGY)) | |
1994 | (set (REGX) (PLUS (REGX) (CONST_INT A))) | |
1995 | ... | |
1996 | (set (REGX) (plus (REGX) (CONST_INT B-A))) */ | |
8ad4c111 | 1997 | else if (REG_P (src) |
8f8cadbc | 1998 | && reg_set_luid[regno] == reg_set_luid[REGNO (src)] |
1999 | && reg_base_reg[regno] == reg_base_reg[REGNO (src)] | |
b6b86e87 | 2000 | && move2add_valid_value_p (REGNO (src), GET_MODE (reg))) |
8f8cadbc | 2001 | { |
5b8537a8 | 2002 | rtx next = next_nonnote_nondebug_insn (insn); |
8f8cadbc | 2003 | rtx set = NULL_RTX; |
2004 | if (next) | |
2005 | set = single_set (next); | |
2006 | if (set | |
2007 | && SET_DEST (set) == reg | |
2008 | && GET_CODE (SET_SRC (set)) == PLUS | |
2009 | && XEXP (SET_SRC (set), 0) == reg | |
971ba038 | 2010 | && CONST_INT_P (XEXP (SET_SRC (set), 1))) |
8f8cadbc | 2011 | { |
2012 | rtx src3 = XEXP (SET_SRC (set), 1); | |
60141df0 | 2013 | unsigned HOST_WIDE_INT added_offset = UINTVAL (src3); |
8f8cadbc | 2014 | HOST_WIDE_INT base_offset = reg_offset[REGNO (src)]; |
2015 | HOST_WIDE_INT regno_offset = reg_offset[regno]; | |
2016 | rtx new_src = | |
69e41517 | 2017 | gen_int_mode (added_offset |
2018 | + base_offset | |
2019 | - regno_offset, | |
2020 | GET_MODE (reg)); | |
f529eb25 | 2021 | bool success = false; |
2022 | bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); | |
8f8cadbc | 2023 | |
2024 | if (new_src == const0_rtx) | |
2025 | /* See above why we create (set (reg) (reg)) here. */ | |
2026 | success | |
2027 | = validate_change (next, &SET_SRC (set), reg, 0); | |
c9a03487 | 2028 | else |
8f8cadbc | 2029 | { |
c9a03487 | 2030 | rtx old_src = SET_SRC (set); |
2031 | struct full_rtx_costs oldcst, newcst; | |
2032 | rtx tem = gen_rtx_PLUS (GET_MODE (reg), reg, new_src); | |
2033 | ||
b72d459f | 2034 | get_full_set_rtx_cost (set, &oldcst); |
c9a03487 | 2035 | SET_SRC (set) = tem; |
7013e87c | 2036 | get_full_set_src_cost (tem, &newcst); |
c9a03487 | 2037 | SET_SRC (set) = old_src; |
2038 | costs_add_n_insns (&oldcst, 1); | |
2039 | ||
2040 | if (costs_lt_p (&newcst, &oldcst, speed) | |
2041 | && have_add2_insn (reg, new_src)) | |
2042 | { | |
2043 | rtx newpat = gen_rtx_SET (VOIDmode, reg, tem); | |
2044 | success | |
2045 | = validate_change (next, &PATTERN (next), | |
2046 | newpat, 0); | |
2047 | } | |
8f8cadbc | 2048 | } |
2049 | if (success) | |
2050 | delete_insn (insn); | |
d83ccc81 | 2051 | changed |= success; |
8f8cadbc | 2052 | insn = next; |
b6b86e87 | 2053 | move2add_record_mode (reg); |
2054 | reg_offset[regno] | |
2055 | = trunc_int_for_mode (added_offset + base_offset, | |
2056 | GET_MODE (reg)); | |
8f8cadbc | 2057 | continue; |
2058 | } | |
2059 | } | |
2060 | } | |
6132c0d0 | 2061 | |
2062 | /* Try to transform | |
2063 | (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A)))) | |
2064 | ... | |
2065 | (set (REGY) (CONST (PLUS (SYMBOL_REF) (CONST_INT B)))) | |
2066 | to | |
2067 | (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A)))) | |
2068 | ... | |
2069 | (set (REGY) (CONST (PLUS (REGX) (CONST_INT B-A)))) */ | |
2070 | if ((GET_CODE (src) == SYMBOL_REF | |
2071 | || (GET_CODE (src) == CONST | |
2072 | && GET_CODE (XEXP (src, 0)) == PLUS | |
2073 | && GET_CODE (XEXP (XEXP (src, 0), 0)) == SYMBOL_REF | |
2074 | && CONST_INT_P (XEXP (XEXP (src, 0), 1)))) | |
2075 | && dbg_cnt (cse2_move2add)) | |
2076 | { | |
2077 | rtx sym, off; | |
2078 | ||
2079 | if (GET_CODE (src) == SYMBOL_REF) | |
2080 | { | |
2081 | sym = src; | |
2082 | off = const0_rtx; | |
2083 | } | |
2084 | else | |
2085 | { | |
2086 | sym = XEXP (XEXP (src, 0), 0); | |
2087 | off = XEXP (XEXP (src, 0), 1); | |
2088 | } | |
2089 | ||
2090 | /* If the reg already contains the value which is sum of | |
2091 | sym and some constant value, we can use an add2 insn. */ | |
b6b86e87 | 2092 | if (move2add_valid_value_p (regno, GET_MODE (reg)) |
6132c0d0 | 2093 | && reg_base_reg[regno] < 0 |
2094 | && reg_symbol_ref[regno] != NULL_RTX | |
2095 | && rtx_equal_p (sym, reg_symbol_ref[regno])) | |
d83ccc81 | 2096 | changed |= move2add_use_add2_insn (reg, sym, off, insn); |
6132c0d0 | 2097 | |
2098 | /* Otherwise, we have to find a register whose value is sum | |
2099 | of sym and some constant value. */ | |
2100 | else | |
d83ccc81 | 2101 | changed |= move2add_use_add3_insn (reg, sym, off, insn); |
6132c0d0 | 2102 | |
2103 | continue; | |
2104 | } | |
8f8cadbc | 2105 | } |
2106 | ||
2107 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
2108 | { | |
2109 | if (REG_NOTE_KIND (note) == REG_INC | |
8ad4c111 | 2110 | && REG_P (XEXP (note, 0))) |
8f8cadbc | 2111 | { |
2112 | /* Reset the information about this register. */ | |
2113 | int regno = REGNO (XEXP (note, 0)); | |
2114 | if (regno < FIRST_PSEUDO_REGISTER) | |
b6b86e87 | 2115 | { |
2116 | move2add_record_mode (XEXP (note, 0)); | |
2117 | reg_mode[regno] = VOIDmode; | |
2118 | } | |
8f8cadbc | 2119 | } |
2120 | } | |
6132c0d0 | 2121 | note_stores (PATTERN (insn), move2add_note_store, insn); |
8f8cadbc | 2122 | |
2123 | /* If INSN is a conditional branch, we try to extract an | |
2124 | implicit set out of it. */ | |
f222bc3b | 2125 | if (any_condjump_p (insn)) |
8f8cadbc | 2126 | { |
2127 | rtx cnd = fis_get_condition (insn); | |
2128 | ||
2129 | if (cnd != NULL_RTX | |
2130 | && GET_CODE (cnd) == NE | |
8ad4c111 | 2131 | && REG_P (XEXP (cnd, 0)) |
f222bc3b | 2132 | && !reg_set_p (XEXP (cnd, 0), insn) |
8f8cadbc | 2133 | /* The following two checks, which are also in |
2134 | move2add_note_store, are intended to reduce the | |
2135 | number of calls to gen_rtx_SET to avoid memory | |
2136 | allocation if possible. */ | |
2137 | && SCALAR_INT_MODE_P (GET_MODE (XEXP (cnd, 0))) | |
67d6c12b | 2138 | && hard_regno_nregs[REGNO (XEXP (cnd, 0))][GET_MODE (XEXP (cnd, 0))] == 1 |
971ba038 | 2139 | && CONST_INT_P (XEXP (cnd, 1))) |
8f8cadbc | 2140 | { |
2141 | rtx implicit_set = | |
2142 | gen_rtx_SET (VOIDmode, XEXP (cnd, 0), XEXP (cnd, 1)); | |
6132c0d0 | 2143 | move2add_note_store (SET_DEST (implicit_set), implicit_set, insn); |
8f8cadbc | 2144 | } |
2145 | } | |
2146 | ||
2147 | /* If this is a CALL_INSN, all call used registers are stored with | |
2148 | unknown values. */ | |
6d7dc5b9 | 2149 | if (CALL_P (insn)) |
8f8cadbc | 2150 | { |
2151 | for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--) | |
2152 | { | |
2153 | if (call_used_regs[i]) | |
2154 | /* Reset the information about this register. */ | |
b6b86e87 | 2155 | reg_mode[i] = VOIDmode; |
8f8cadbc | 2156 | } |
2157 | } | |
2158 | } | |
d83ccc81 | 2159 | return changed; |
8f8cadbc | 2160 | } |
2161 | ||
6132c0d0 | 2162 | /* SET is a SET or CLOBBER that sets DST. DATA is the insn which |
2163 | contains SET. | |
8f8cadbc | 2164 | Update reg_set_luid, reg_offset and reg_base_reg accordingly. |
2165 | Called from reload_cse_move2add via note_stores. */ | |
2166 | ||
2167 | static void | |
6132c0d0 | 2168 | move2add_note_store (rtx dst, const_rtx set, void *data) |
8f8cadbc | 2169 | { |
6132c0d0 | 2170 | rtx insn = (rtx) data; |
8f8cadbc | 2171 | unsigned int regno = 0; |
8f8cadbc | 2172 | enum machine_mode mode = GET_MODE (dst); |
2173 | ||
8f8cadbc | 2174 | /* Some targets do argument pushes without adding REG_INC notes. */ |
2175 | ||
e16ceb8e | 2176 | if (MEM_P (dst)) |
8f8cadbc | 2177 | { |
2178 | dst = XEXP (dst, 0); | |
2179 | if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_INC | |
2180 | || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC) | |
b6b86e87 | 2181 | reg_mode[REGNO (XEXP (dst, 0))] = VOIDmode; |
8f8cadbc | 2182 | return; |
2183 | } | |
8f8cadbc | 2184 | |
b6b86e87 | 2185 | if (GET_CODE (dst) == SUBREG) |
2186 | regno = subreg_regno (dst); | |
2187 | else if (REG_P (dst)) | |
2188 | regno = REGNO (dst); | |
2189 | else | |
2190 | return; | |
8f8cadbc | 2191 | |
b6b86e87 | 2192 | if (SCALAR_INT_MODE_P (mode) |
2193 | && GET_CODE (set) == SET) | |
6132c0d0 | 2194 | { |
2195 | rtx note, sym = NULL_RTX; | |
b6b86e87 | 2196 | rtx off; |
6132c0d0 | 2197 | |
2198 | note = find_reg_equal_equiv_note (insn); | |
2199 | if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF) | |
2200 | { | |
2201 | sym = XEXP (note, 0); | |
b6b86e87 | 2202 | off = const0_rtx; |
6132c0d0 | 2203 | } |
2204 | else if (note && GET_CODE (XEXP (note, 0)) == CONST | |
2205 | && GET_CODE (XEXP (XEXP (note, 0), 0)) == PLUS | |
2206 | && GET_CODE (XEXP (XEXP (XEXP (note, 0), 0), 0)) == SYMBOL_REF | |
2207 | && CONST_INT_P (XEXP (XEXP (XEXP (note, 0), 0), 1))) | |
2208 | { | |
2209 | sym = XEXP (XEXP (XEXP (note, 0), 0), 0); | |
b6b86e87 | 2210 | off = XEXP (XEXP (XEXP (note, 0), 0), 1); |
6132c0d0 | 2211 | } |
2212 | ||
2213 | if (sym != NULL_RTX) | |
2214 | { | |
b6b86e87 | 2215 | move2add_record_sym_value (dst, sym, off); |
6132c0d0 | 2216 | return; |
2217 | } | |
2218 | } | |
2219 | ||
b6b86e87 | 2220 | if (SCALAR_INT_MODE_P (mode) |
2221 | && GET_CODE (set) == SET | |
8f8cadbc | 2222 | && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT |
8f8cadbc | 2223 | && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART) |
2224 | { | |
2225 | rtx src = SET_SRC (set); | |
2226 | rtx base_reg; | |
60141df0 | 2227 | unsigned HOST_WIDE_INT offset; |
8f8cadbc | 2228 | int base_regno; |
8f8cadbc | 2229 | |
2230 | switch (GET_CODE (src)) | |
2231 | { | |
2232 | case PLUS: | |
8ad4c111 | 2233 | if (REG_P (XEXP (src, 0))) |
8f8cadbc | 2234 | { |
2235 | base_reg = XEXP (src, 0); | |
2236 | ||
971ba038 | 2237 | if (CONST_INT_P (XEXP (src, 1))) |
60141df0 | 2238 | offset = UINTVAL (XEXP (src, 1)); |
8ad4c111 | 2239 | else if (REG_P (XEXP (src, 1)) |
b6b86e87 | 2240 | && move2add_valid_value_p (REGNO (XEXP (src, 1)), mode)) |
8f8cadbc | 2241 | { |
c389f975 | 2242 | if (reg_base_reg[REGNO (XEXP (src, 1))] < 0 |
2243 | && reg_symbol_ref[REGNO (XEXP (src, 1))] == NULL_RTX) | |
8f8cadbc | 2244 | offset = reg_offset[REGNO (XEXP (src, 1))]; |
2245 | /* Maybe the first register is known to be a | |
2246 | constant. */ | |
b6b86e87 | 2247 | else if (move2add_valid_value_p (REGNO (base_reg), mode) |
c389f975 | 2248 | && reg_base_reg[REGNO (base_reg)] < 0 |
2249 | && reg_symbol_ref[REGNO (base_reg)] == NULL_RTX) | |
8f8cadbc | 2250 | { |
2251 | offset = reg_offset[REGNO (base_reg)]; | |
2252 | base_reg = XEXP (src, 1); | |
2253 | } | |
2254 | else | |
2255 | goto invalidate; | |
2256 | } | |
2257 | else | |
2258 | goto invalidate; | |
2259 | ||
2260 | break; | |
2261 | } | |
2262 | ||
2263 | goto invalidate; | |
2264 | ||
2265 | case REG: | |
2266 | base_reg = src; | |
2267 | offset = 0; | |
2268 | break; | |
2269 | ||
2270 | case CONST_INT: | |
2271 | /* Start tracking the register as a constant. */ | |
2272 | reg_base_reg[regno] = -1; | |
6132c0d0 | 2273 | reg_symbol_ref[regno] = NULL_RTX; |
8f8cadbc | 2274 | reg_offset[regno] = INTVAL (SET_SRC (set)); |
2275 | /* We assign the same luid to all registers set to constants. */ | |
2276 | reg_set_luid[regno] = move2add_last_label_luid + 1; | |
b6b86e87 | 2277 | move2add_record_mode (dst); |
8f8cadbc | 2278 | return; |
2279 | ||
2280 | default: | |
b6b86e87 | 2281 | goto invalidate; |
8f8cadbc | 2282 | } |
2283 | ||
2284 | base_regno = REGNO (base_reg); | |
2285 | /* If information about the base register is not valid, set it | |
2286 | up as a new base register, pretending its value is known | |
2287 | starting from the current insn. */ | |
b6b86e87 | 2288 | if (!move2add_valid_value_p (base_regno, mode)) |
8f8cadbc | 2289 | { |
2290 | reg_base_reg[base_regno] = base_regno; | |
6132c0d0 | 2291 | reg_symbol_ref[base_regno] = NULL_RTX; |
8f8cadbc | 2292 | reg_offset[base_regno] = 0; |
2293 | reg_set_luid[base_regno] = move2add_luid; | |
b6b86e87 | 2294 | gcc_assert (GET_MODE (base_reg) == mode); |
2295 | move2add_record_mode (base_reg); | |
8f8cadbc | 2296 | } |
8f8cadbc | 2297 | |
2298 | /* Copy base information from our base register. */ | |
2299 | reg_set_luid[regno] = reg_set_luid[base_regno]; | |
2300 | reg_base_reg[regno] = reg_base_reg[base_regno]; | |
6132c0d0 | 2301 | reg_symbol_ref[regno] = reg_symbol_ref[base_regno]; |
8f8cadbc | 2302 | |
2303 | /* Compute the sum of the offsets or constants. */ | |
b6b86e87 | 2304 | reg_offset[regno] |
2305 | = trunc_int_for_mode (offset + reg_offset[base_regno], mode); | |
2306 | ||
2307 | move2add_record_mode (dst); | |
8f8cadbc | 2308 | } |
2309 | else | |
2310 | { | |
b6b86e87 | 2311 | invalidate: |
2312 | /* Invalidate the contents of the register. */ | |
2313 | move2add_record_mode (dst); | |
2314 | reg_mode[regno] = VOIDmode; | |
8f8cadbc | 2315 | } |
2316 | } | |
77fce4cd | 2317 | \f |
cbe8bda8 | 2318 | namespace { |
2319 | ||
2320 | const pass_data pass_data_postreload_cse = | |
77fce4cd | 2321 | { |
cbe8bda8 | 2322 | RTL_PASS, /* type */ |
2323 | "postreload", /* name */ | |
2324 | OPTGROUP_NONE, /* optinfo_flags */ | |
cbe8bda8 | 2325 | true, /* has_execute */ |
2326 | TV_RELOAD_CSE_REGS, /* tv_id */ | |
2327 | 0, /* properties_required */ | |
2328 | 0, /* properties_provided */ | |
2329 | 0, /* properties_destroyed */ | |
2330 | 0, /* todo_flags_start */ | |
2331 | ( TODO_df_finish | TODO_verify_rtl_sharing | 0 ), /* todo_flags_finish */ | |
77fce4cd | 2332 | }; |
cbe8bda8 | 2333 | |
2334 | class pass_postreload_cse : public rtl_opt_pass | |
2335 | { | |
2336 | public: | |
9af5ce0c | 2337 | pass_postreload_cse (gcc::context *ctxt) |
2338 | : rtl_opt_pass (pass_data_postreload_cse, ctxt) | |
cbe8bda8 | 2339 | {} |
2340 | ||
2341 | /* opt_pass methods: */ | |
31315c24 | 2342 | virtual bool gate (function *) { return (optimize > 0 && reload_completed); } |
2343 | ||
65b0537f | 2344 | virtual unsigned int execute (function *); |
cbe8bda8 | 2345 | |
2346 | }; // class pass_postreload_cse | |
2347 | ||
65b0537f | 2348 | unsigned int |
2349 | pass_postreload_cse::execute (function *fun) | |
2350 | { | |
2351 | if (!dbg_cnt (postreload_cse)) | |
2352 | return 0; | |
2353 | ||
2354 | /* Do a very simple CSE pass over just the hard registers. */ | |
2355 | reload_cse_regs (get_insns ()); | |
2356 | /* Reload_cse_regs can eliminate potentially-trapping MEMs. | |
2357 | Remove any EH edges associated with them. */ | |
2358 | if (fun->can_throw_non_call_exceptions | |
2359 | && purge_all_dead_edges ()) | |
2360 | cleanup_cfg (0); | |
2361 | ||
2362 | return 0; | |
2363 | } | |
2364 | ||
cbe8bda8 | 2365 | } // anon namespace |
2366 | ||
2367 | rtl_opt_pass * | |
2368 | make_pass_postreload_cse (gcc::context *ctxt) | |
2369 | { | |
2370 | return new pass_postreload_cse (ctxt); | |
2371 | } |