]>
Commit | Line | Data |
---|---|---|
8f8cadbc | 1 | /* Perform simple optimizations to clean up the result of reload. |
d353bf18 | 2 | Copyright (C) 1987-2015 Free Software Foundation, Inc. |
8f8cadbc | 3 | |
4 | This file is part of GCC. | |
5 | ||
6 | GCC is free software; you can redistribute it and/or modify it under | |
7 | the terms of the GNU General Public License as published by the Free | |
8c4c00c1 | 8 | Software Foundation; either version 3, or (at your option) any later |
8f8cadbc | 9 | version. |
10 | ||
11 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
12 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
14 | for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
8c4c00c1 | 17 | along with GCC; see the file COPYING3. If not see |
18 | <http://www.gnu.org/licenses/>. */ | |
8f8cadbc | 19 | |
20 | #include "config.h" | |
21 | #include "system.h" | |
22 | #include "coretypes.h" | |
23 | #include "tm.h" | |
24 | ||
8f8cadbc | 25 | #include "hard-reg-set.h" |
26 | #include "rtl.h" | |
27 | #include "tm_p.h" | |
28 | #include "obstack.h" | |
29 | #include "insn-config.h" | |
30 | #include "flags.h" | |
31 | #include "function.h" | |
b20a8bb4 | 32 | #include "symtab.h" |
d53441c8 | 33 | #include "alias.h" |
d53441c8 | 34 | #include "tree.h" |
35 | #include "expmed.h" | |
36 | #include "dojump.h" | |
37 | #include "explow.h" | |
38 | #include "calls.h" | |
39 | #include "emit-rtl.h" | |
40 | #include "varasm.h" | |
41 | #include "stmt.h" | |
8f8cadbc | 42 | #include "expr.h" |
34517c64 | 43 | #include "insn-codes.h" |
8f8cadbc | 44 | #include "optabs.h" |
45 | #include "regs.h" | |
94ea8568 | 46 | #include "predict.h" |
47 | #include "dominance.h" | |
48 | #include "cfg.h" | |
49 | #include "cfgrtl.h" | |
50 | #include "cfgbuild.h" | |
51 | #include "cfgcleanup.h" | |
8f8cadbc | 52 | #include "basic-block.h" |
53 | #include "reload.h" | |
54 | #include "recog.h" | |
f7d27fdc | 55 | #include "alloc-pool.h" |
8f8cadbc | 56 | #include "cselib.h" |
0b205f4c | 57 | #include "diagnostic-core.h" |
8f8cadbc | 58 | #include "except.h" |
727047d0 | 59 | #include "target.h" |
77fce4cd | 60 | #include "tree-pass.h" |
3072d30e | 61 | #include "df.h" |
62 | #include "dbgcnt.h" | |
8f8cadbc | 63 | |
3ad4992f | 64 | static int reload_cse_noop_set_p (rtx); |
3aeaa53f | 65 | static bool reload_cse_simplify (rtx_insn *, rtx); |
26709122 | 66 | static void reload_cse_regs_1 (void); |
3aeaa53f | 67 | static int reload_cse_simplify_set (rtx, rtx_insn *); |
68 | static int reload_cse_simplify_operands (rtx_insn *, rtx); | |
8f8cadbc | 69 | |
3ad4992f | 70 | static void reload_combine (void); |
3aeaa53f | 71 | static void reload_combine_note_use (rtx *, rtx_insn *, int, rtx); |
81a410b1 | 72 | static void reload_combine_note_store (rtx, const_rtx, void *); |
8f8cadbc | 73 | |
3aeaa53f | 74 | static bool reload_cse_move2add (rtx_insn *); |
81a410b1 | 75 | static void move2add_note_store (rtx, const_rtx, void *); |
8f8cadbc | 76 | |
77 | /* Call cse / combine like post-reload optimization phases. | |
78 | FIRST is the first instruction. */ | |
98799adc | 79 | |
80 | static void | |
3aeaa53f | 81 | reload_cse_regs (rtx_insn *first ATTRIBUTE_UNUSED) |
8f8cadbc | 82 | { |
d83ccc81 | 83 | bool moves_converted; |
26709122 | 84 | reload_cse_regs_1 (); |
8f8cadbc | 85 | reload_combine (); |
d83ccc81 | 86 | moves_converted = reload_cse_move2add (first); |
8f8cadbc | 87 | if (flag_expensive_optimizations) |
d83ccc81 | 88 | { |
89 | if (moves_converted) | |
90 | reload_combine (); | |
26709122 | 91 | reload_cse_regs_1 (); |
d83ccc81 | 92 | } |
8f8cadbc | 93 | } |
94 | ||
95 | /* See whether a single set SET is a noop. */ | |
96 | static int | |
3ad4992f | 97 | reload_cse_noop_set_p (rtx set) |
8f8cadbc | 98 | { |
99 | if (cselib_reg_set_mode (SET_DEST (set)) != GET_MODE (SET_DEST (set))) | |
100 | return 0; | |
101 | ||
102 | return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set)); | |
103 | } | |
104 | ||
26709122 | 105 | /* Try to simplify INSN. Return true if the CFG may have changed. */ |
106 | static bool | |
3aeaa53f | 107 | reload_cse_simplify (rtx_insn *insn, rtx testreg) |
8f8cadbc | 108 | { |
109 | rtx body = PATTERN (insn); | |
26709122 | 110 | basic_block insn_bb = BLOCK_FOR_INSN (insn); |
111 | unsigned insn_bb_succs = EDGE_COUNT (insn_bb->succs); | |
8f8cadbc | 112 | |
113 | if (GET_CODE (body) == SET) | |
114 | { | |
115 | int count = 0; | |
116 | ||
117 | /* Simplify even if we may think it is a no-op. | |
118 | We may think a memory load of a value smaller than WORD_SIZE | |
119 | is redundant because we haven't taken into account possible | |
120 | implicit extension. reload_cse_simplify_set() will bring | |
121 | this out, so it's safer to simplify before we delete. */ | |
122 | count += reload_cse_simplify_set (body, insn); | |
123 | ||
124 | if (!count && reload_cse_noop_set_p (body)) | |
125 | { | |
126 | rtx value = SET_DEST (body); | |
127 | if (REG_P (value) | |
128 | && ! REG_FUNCTION_VALUE_P (value)) | |
129 | value = 0; | |
5a9ecd4a | 130 | if (check_for_inc_dec (insn)) |
131 | delete_insn_and_edges (insn); | |
26709122 | 132 | /* We're done with this insn. */ |
133 | goto done; | |
8f8cadbc | 134 | } |
135 | ||
136 | if (count > 0) | |
137 | apply_change_group (); | |
138 | else | |
139 | reload_cse_simplify_operands (insn, testreg); | |
140 | } | |
141 | else if (GET_CODE (body) == PARALLEL) | |
142 | { | |
143 | int i; | |
144 | int count = 0; | |
145 | rtx value = NULL_RTX; | |
146 | ||
17883489 | 147 | /* Registers mentioned in the clobber list for an asm cannot be reused |
148 | within the body of the asm. Invalidate those registers now so that | |
149 | we don't try to substitute values for them. */ | |
150 | if (asm_noperands (body) >= 0) | |
151 | { | |
152 | for (i = XVECLEN (body, 0) - 1; i >= 0; --i) | |
153 | { | |
154 | rtx part = XVECEXP (body, 0, i); | |
155 | if (GET_CODE (part) == CLOBBER && REG_P (XEXP (part, 0))) | |
156 | cselib_invalidate_rtx (XEXP (part, 0)); | |
157 | } | |
158 | } | |
159 | ||
8f8cadbc | 160 | /* If every action in a PARALLEL is a noop, we can delete |
161 | the entire PARALLEL. */ | |
162 | for (i = XVECLEN (body, 0) - 1; i >= 0; --i) | |
163 | { | |
164 | rtx part = XVECEXP (body, 0, i); | |
165 | if (GET_CODE (part) == SET) | |
166 | { | |
167 | if (! reload_cse_noop_set_p (part)) | |
168 | break; | |
169 | if (REG_P (SET_DEST (part)) | |
170 | && REG_FUNCTION_VALUE_P (SET_DEST (part))) | |
171 | { | |
172 | if (value) | |
173 | break; | |
174 | value = SET_DEST (part); | |
175 | } | |
176 | } | |
177 | else if (GET_CODE (part) != CLOBBER) | |
178 | break; | |
179 | } | |
180 | ||
181 | if (i < 0) | |
182 | { | |
5a9ecd4a | 183 | if (check_for_inc_dec (insn)) |
184 | delete_insn_and_edges (insn); | |
8f8cadbc | 185 | /* We're done with this insn. */ |
26709122 | 186 | goto done; |
8f8cadbc | 187 | } |
188 | ||
189 | /* It's not a no-op, but we can try to simplify it. */ | |
190 | for (i = XVECLEN (body, 0) - 1; i >= 0; --i) | |
191 | if (GET_CODE (XVECEXP (body, 0, i)) == SET) | |
192 | count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn); | |
193 | ||
194 | if (count > 0) | |
195 | apply_change_group (); | |
196 | else | |
197 | reload_cse_simplify_operands (insn, testreg); | |
198 | } | |
26709122 | 199 | |
200 | done: | |
201 | return (EDGE_COUNT (insn_bb->succs) != insn_bb_succs); | |
8f8cadbc | 202 | } |
203 | ||
204 | /* Do a very simple CSE pass over the hard registers. | |
205 | ||
206 | This function detects no-op moves where we happened to assign two | |
207 | different pseudo-registers to the same hard register, and then | |
208 | copied one to the other. Reload will generate a useless | |
209 | instruction copying a register to itself. | |
210 | ||
211 | This function also detects cases where we load a value from memory | |
212 | into two different registers, and (if memory is more expensive than | |
213 | registers) changes it to simply copy the first register into the | |
214 | second register. | |
215 | ||
216 | Another optimization is performed that scans the operands of each | |
217 | instruction to see whether the value is already available in a | |
218 | hard register. It then replaces the operand with the hard register | |
219 | if possible, much like an optional reload would. */ | |
220 | ||
221 | static void | |
26709122 | 222 | reload_cse_regs_1 (void) |
8f8cadbc | 223 | { |
26709122 | 224 | bool cfg_changed = false; |
225 | basic_block bb; | |
3aeaa53f | 226 | rtx_insn *insn; |
dcd6d0f4 | 227 | rtx testreg = gen_rtx_REG (word_mode, LAST_VIRTUAL_REGISTER + 1); |
8f8cadbc | 228 | |
35af0188 | 229 | cselib_init (CSELIB_RECORD_MEMORY); |
8f8cadbc | 230 | init_alias_analysis (); |
231 | ||
fc00614f | 232 | FOR_EACH_BB_FN (bb, cfun) |
26709122 | 233 | FOR_BB_INSNS (bb, insn) |
234 | { | |
235 | if (INSN_P (insn)) | |
236 | cfg_changed |= reload_cse_simplify (insn, testreg); | |
8f8cadbc | 237 | |
26709122 | 238 | cselib_process_insn (insn); |
239 | } | |
8f8cadbc | 240 | |
241 | /* Clean up. */ | |
242 | end_alias_analysis (); | |
243 | cselib_finish (); | |
26709122 | 244 | if (cfg_changed) |
245 | cleanup_cfg (0); | |
8f8cadbc | 246 | } |
247 | ||
248 | /* Try to simplify a single SET instruction. SET is the set pattern. | |
249 | INSN is the instruction it came from. | |
250 | This function only handles one case: if we set a register to a value | |
251 | which is not a register, we try to find that value in some other register | |
252 | and change the set into a register copy. */ | |
253 | ||
254 | static int | |
3aeaa53f | 255 | reload_cse_simplify_set (rtx set, rtx_insn *insn) |
8f8cadbc | 256 | { |
257 | int did_change = 0; | |
258 | int dreg; | |
259 | rtx src; | |
ade444a4 | 260 | reg_class_t dclass; |
8f8cadbc | 261 | int old_cost; |
262 | cselib_val *val; | |
263 | struct elt_loc_list *l; | |
264 | #ifdef LOAD_EXTEND_OP | |
21f1e711 | 265 | enum rtx_code extend_op = UNKNOWN; |
8f8cadbc | 266 | #endif |
f529eb25 | 267 | bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); |
8f8cadbc | 268 | |
269 | dreg = true_regnum (SET_DEST (set)); | |
270 | if (dreg < 0) | |
271 | return 0; | |
272 | ||
273 | src = SET_SRC (set); | |
274 | if (side_effects_p (src) || true_regnum (src) >= 0) | |
275 | return 0; | |
276 | ||
277 | dclass = REGNO_REG_CLASS (dreg); | |
278 | ||
279 | #ifdef LOAD_EXTEND_OP | |
280 | /* When replacing a memory with a register, we need to honor assumptions | |
281 | that combine made wrt the contents of sign bits. We'll do this by | |
282 | generating an extend instruction instead of a reg->reg copy. Thus | |
283 | the destination must be a register that we can widen. */ | |
e16ceb8e | 284 | if (MEM_P (src) |
8f8cadbc | 285 | && GET_MODE_BITSIZE (GET_MODE (src)) < BITS_PER_WORD |
21f1e711 | 286 | && (extend_op = LOAD_EXTEND_OP (GET_MODE (src))) != UNKNOWN |
8ad4c111 | 287 | && !REG_P (SET_DEST (set))) |
8f8cadbc | 288 | return 0; |
289 | #endif | |
290 | ||
1f864115 | 291 | val = cselib_lookup (src, GET_MODE (SET_DEST (set)), 0, VOIDmode); |
3be01943 | 292 | if (! val) |
293 | return 0; | |
294 | ||
8f8cadbc | 295 | /* If memory loads are cheaper than register copies, don't change them. */ |
e16ceb8e | 296 | if (MEM_P (src)) |
251a613e | 297 | old_cost = memory_move_cost (GET_MODE (src), dclass, true); |
8ad4c111 | 298 | else if (REG_P (src)) |
e6078fbb | 299 | old_cost = register_move_cost (GET_MODE (src), |
8f8cadbc | 300 | REGNO_REG_CLASS (REGNO (src)), dclass); |
301 | else | |
7013e87c | 302 | old_cost = set_src_cost (src, speed); |
8f8cadbc | 303 | |
8f8cadbc | 304 | for (l = val->locs; l; l = l->next) |
305 | { | |
306 | rtx this_rtx = l->loc; | |
307 | int this_cost; | |
308 | ||
309 | if (CONSTANT_P (this_rtx) && ! references_value_p (this_rtx, 0)) | |
310 | { | |
311 | #ifdef LOAD_EXTEND_OP | |
21f1e711 | 312 | if (extend_op != UNKNOWN) |
8f8cadbc | 313 | { |
e913b5cd | 314 | wide_int result; |
8f8cadbc | 315 | |
e913b5cd | 316 | if (!CONST_SCALAR_INT_P (this_rtx)) |
8f8cadbc | 317 | continue; |
318 | ||
8f8cadbc | 319 | switch (extend_op) |
320 | { | |
321 | case ZERO_EXTEND: | |
ecc41f48 | 322 | result = wide_int::from (std::make_pair (this_rtx, |
323 | GET_MODE (src)), | |
324 | BITS_PER_WORD, UNSIGNED); | |
8f8cadbc | 325 | break; |
326 | case SIGN_EXTEND: | |
ecc41f48 | 327 | result = wide_int::from (std::make_pair (this_rtx, |
328 | GET_MODE (src)), | |
329 | BITS_PER_WORD, SIGNED); | |
e913b5cd | 330 | break; |
8f8cadbc | 331 | default: |
876760f6 | 332 | gcc_unreachable (); |
8f8cadbc | 333 | } |
ecc41f48 | 334 | this_rtx = immed_wide_int_const (result, word_mode); |
8f8cadbc | 335 | } |
336 | #endif | |
7013e87c | 337 | this_cost = set_src_cost (this_rtx, speed); |
8f8cadbc | 338 | } |
8ad4c111 | 339 | else if (REG_P (this_rtx)) |
8f8cadbc | 340 | { |
341 | #ifdef LOAD_EXTEND_OP | |
21f1e711 | 342 | if (extend_op != UNKNOWN) |
8f8cadbc | 343 | { |
344 | this_rtx = gen_rtx_fmt_e (extend_op, word_mode, this_rtx); | |
7013e87c | 345 | this_cost = set_src_cost (this_rtx, speed); |
8f8cadbc | 346 | } |
347 | else | |
348 | #endif | |
e6078fbb | 349 | this_cost = register_move_cost (GET_MODE (this_rtx), |
8f8cadbc | 350 | REGNO_REG_CLASS (REGNO (this_rtx)), |
351 | dclass); | |
352 | } | |
353 | else | |
354 | continue; | |
355 | ||
356 | /* If equal costs, prefer registers over anything else. That | |
357 | tends to lead to smaller instructions on some machines. */ | |
358 | if (this_cost < old_cost | |
359 | || (this_cost == old_cost | |
8ad4c111 | 360 | && REG_P (this_rtx) |
361 | && !REG_P (SET_SRC (set)))) | |
8f8cadbc | 362 | { |
363 | #ifdef LOAD_EXTEND_OP | |
364 | if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (set))) < BITS_PER_WORD | |
21f1e711 | 365 | && extend_op != UNKNOWN |
8f8cadbc | 366 | #ifdef CANNOT_CHANGE_MODE_CLASS |
367 | && !CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set)), | |
368 | word_mode, | |
369 | REGNO_REG_CLASS (REGNO (SET_DEST (set)))) | |
370 | #endif | |
371 | ) | |
372 | { | |
373 | rtx wide_dest = gen_rtx_REG (word_mode, REGNO (SET_DEST (set))); | |
374 | ORIGINAL_REGNO (wide_dest) = ORIGINAL_REGNO (SET_DEST (set)); | |
375 | validate_change (insn, &SET_DEST (set), wide_dest, 1); | |
376 | } | |
377 | #endif | |
378 | ||
11d686e2 | 379 | validate_unshare_change (insn, &SET_SRC (set), this_rtx, 1); |
8f8cadbc | 380 | old_cost = this_cost, did_change = 1; |
381 | } | |
382 | } | |
383 | ||
384 | return did_change; | |
385 | } | |
386 | ||
387 | /* Try to replace operands in INSN with equivalent values that are already | |
388 | in registers. This can be viewed as optional reloading. | |
389 | ||
390 | For each non-register operand in the insn, see if any hard regs are | |
391 | known to be equivalent to that operand. Record the alternatives which | |
392 | can accept these hard registers. Among all alternatives, select the | |
393 | ones which are better or equal to the one currently matching, where | |
394 | "better" is in terms of '?' and '!' constraints. Among the remaining | |
395 | alternatives, select the one which replaces most operands with | |
396 | hard registers. */ | |
397 | ||
398 | static int | |
3aeaa53f | 399 | reload_cse_simplify_operands (rtx_insn *insn, rtx testreg) |
8f8cadbc | 400 | { |
401 | int i, j; | |
402 | ||
403 | /* For each operand, all registers that are equivalent to it. */ | |
404 | HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS]; | |
405 | ||
406 | const char *constraints[MAX_RECOG_OPERANDS]; | |
407 | ||
408 | /* Vector recording how bad an alternative is. */ | |
409 | int *alternative_reject; | |
410 | /* Vector recording how many registers can be introduced by choosing | |
411 | this alternative. */ | |
412 | int *alternative_nregs; | |
413 | /* Array of vectors recording, for each operand and each alternative, | |
414 | which hard register to substitute, or -1 if the operand should be | |
415 | left as it is. */ | |
416 | int *op_alt_regno[MAX_RECOG_OPERANDS]; | |
417 | /* Array of alternatives, sorted in order of decreasing desirability. */ | |
418 | int *alternative_order; | |
419 | ||
835b8178 | 420 | extract_constrain_insn (insn); |
8f8cadbc | 421 | |
422 | if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0) | |
423 | return 0; | |
424 | ||
4077bf7a | 425 | alternative_reject = XALLOCAVEC (int, recog_data.n_alternatives); |
426 | alternative_nregs = XALLOCAVEC (int, recog_data.n_alternatives); | |
427 | alternative_order = XALLOCAVEC (int, recog_data.n_alternatives); | |
f0af5a88 | 428 | memset (alternative_reject, 0, recog_data.n_alternatives * sizeof (int)); |
429 | memset (alternative_nregs, 0, recog_data.n_alternatives * sizeof (int)); | |
8f8cadbc | 430 | |
431 | /* For each operand, find out which regs are equivalent. */ | |
432 | for (i = 0; i < recog_data.n_operands; i++) | |
433 | { | |
434 | cselib_val *v; | |
435 | struct elt_loc_list *l; | |
9d9e3c81 | 436 | rtx op; |
8f8cadbc | 437 | |
438 | CLEAR_HARD_REG_SET (equiv_regs[i]); | |
439 | ||
440 | /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem | |
441 | right, so avoid the problem here. Likewise if we have a constant | |
442 | and the insn pattern doesn't tell us the mode we need. */ | |
6d7dc5b9 | 443 | if (LABEL_P (recog_data.operand[i]) |
8f8cadbc | 444 | || (CONSTANT_P (recog_data.operand[i]) |
445 | && recog_data.operand_mode[i] == VOIDmode)) | |
446 | continue; | |
447 | ||
9d9e3c81 | 448 | op = recog_data.operand[i]; |
9d9e3c81 | 449 | #ifdef LOAD_EXTEND_OP |
e16ceb8e | 450 | if (MEM_P (op) |
f018d957 | 451 | && GET_MODE_BITSIZE (GET_MODE (op)) < BITS_PER_WORD |
452 | && LOAD_EXTEND_OP (GET_MODE (op)) != UNKNOWN) | |
9d9e3c81 | 453 | { |
454 | rtx set = single_set (insn); | |
455 | ||
4885b286 | 456 | /* We might have multiple sets, some of which do implicit |
9d9e3c81 | 457 | extension. Punt on this for now. */ |
458 | if (! set) | |
459 | continue; | |
86481e89 | 460 | /* If the destination is also a MEM or a STRICT_LOW_PART, no |
9d9e3c81 | 461 | extension applies. |
462 | Also, if there is an explicit extension, we don't have to | |
463 | worry about an implicit one. */ | |
e16ceb8e | 464 | else if (MEM_P (SET_DEST (set)) |
9d9e3c81 | 465 | || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART |
466 | || GET_CODE (SET_SRC (set)) == ZERO_EXTEND | |
467 | || GET_CODE (SET_SRC (set)) == SIGN_EXTEND) | |
468 | ; /* Continue ordinary processing. */ | |
a091e4f5 | 469 | #ifdef CANNOT_CHANGE_MODE_CLASS |
470 | /* If the register cannot change mode to word_mode, it follows that | |
471 | it cannot have been used in word_mode. */ | |
8ad4c111 | 472 | else if (REG_P (SET_DEST (set)) |
a091e4f5 | 473 | && CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set)), |
474 | word_mode, | |
475 | REGNO_REG_CLASS (REGNO (SET_DEST (set))))) | |
476 | ; /* Continue ordinary processing. */ | |
477 | #endif | |
9d9e3c81 | 478 | /* If this is a straight load, make the extension explicit. */ |
8ad4c111 | 479 | else if (REG_P (SET_DEST (set)) |
9d9e3c81 | 480 | && recog_data.n_operands == 2 |
481 | && SET_SRC (set) == op | |
482 | && SET_DEST (set) == recog_data.operand[1-i]) | |
483 | { | |
484 | validate_change (insn, recog_data.operand_loc[i], | |
f018d957 | 485 | gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (op)), |
9d9e3c81 | 486 | word_mode, op), |
487 | 1); | |
488 | validate_change (insn, recog_data.operand_loc[1-i], | |
489 | gen_rtx_REG (word_mode, REGNO (SET_DEST (set))), | |
490 | 1); | |
491 | if (! apply_change_group ()) | |
492 | return 0; | |
493 | return reload_cse_simplify_operands (insn, testreg); | |
494 | } | |
495 | else | |
496 | /* ??? There might be arithmetic operations with memory that are | |
497 | safe to optimize, but is it worth the trouble? */ | |
498 | continue; | |
499 | } | |
500 | #endif /* LOAD_EXTEND_OP */ | |
017b7047 | 501 | if (side_effects_p (op)) |
502 | continue; | |
1f864115 | 503 | v = cselib_lookup (op, recog_data.operand_mode[i], 0, VOIDmode); |
8f8cadbc | 504 | if (! v) |
505 | continue; | |
506 | ||
507 | for (l = v->locs; l; l = l->next) | |
8ad4c111 | 508 | if (REG_P (l->loc)) |
8f8cadbc | 509 | SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc)); |
510 | } | |
511 | ||
e1a797ad | 512 | alternative_mask preferred = get_preferred_alternatives (insn); |
8f8cadbc | 513 | for (i = 0; i < recog_data.n_operands; i++) |
514 | { | |
3754d046 | 515 | machine_mode mode; |
8f8cadbc | 516 | int regno; |
517 | const char *p; | |
518 | ||
4077bf7a | 519 | op_alt_regno[i] = XALLOCAVEC (int, recog_data.n_alternatives); |
8f8cadbc | 520 | for (j = 0; j < recog_data.n_alternatives; j++) |
521 | op_alt_regno[i][j] = -1; | |
522 | ||
523 | p = constraints[i] = recog_data.constraints[i]; | |
524 | mode = recog_data.operand_mode[i]; | |
525 | ||
526 | /* Add the reject values for each alternative given by the constraints | |
527 | for this operand. */ | |
528 | j = 0; | |
529 | while (*p != '\0') | |
530 | { | |
531 | char c = *p++; | |
532 | if (c == ',') | |
533 | j++; | |
534 | else if (c == '?') | |
535 | alternative_reject[j] += 3; | |
536 | else if (c == '!') | |
537 | alternative_reject[j] += 300; | |
538 | } | |
539 | ||
540 | /* We won't change operands which are already registers. We | |
541 | also don't want to modify output operands. */ | |
542 | regno = true_regnum (recog_data.operand[i]); | |
543 | if (regno >= 0 | |
544 | || constraints[i][0] == '=' | |
545 | || constraints[i][0] == '+') | |
546 | continue; | |
547 | ||
548 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
549 | { | |
b9c74b4d | 550 | enum reg_class rclass = NO_REGS; |
8f8cadbc | 551 | |
552 | if (! TEST_HARD_REG_BIT (equiv_regs[i], regno)) | |
553 | continue; | |
554 | ||
937ca48e | 555 | set_mode_and_regno (testreg, mode, regno); |
8f8cadbc | 556 | |
557 | /* We found a register equal to this operand. Now look for all | |
558 | alternatives that can accept this register and have not been | |
559 | assigned a register they can use yet. */ | |
560 | j = 0; | |
561 | p = constraints[i]; | |
562 | for (;;) | |
563 | { | |
564 | char c = *p; | |
565 | ||
566 | switch (c) | |
567 | { | |
69449463 | 568 | case 'g': |
569 | rclass = reg_class_subunion[rclass][GENERAL_REGS]; | |
8f8cadbc | 570 | break; |
571 | ||
572 | default: | |
6659485c | 573 | rclass |
8f8cadbc | 574 | = (reg_class_subunion |
79bc09fb | 575 | [rclass] |
576 | [reg_class_for_constraint (lookup_constraint (p))]); | |
8f8cadbc | 577 | break; |
578 | ||
579 | case ',': case '\0': | |
580 | /* See if REGNO fits this alternative, and set it up as the | |
581 | replacement register if we don't have one for this | |
582 | alternative yet and the operand being replaced is not | |
583 | a cheap CONST_INT. */ | |
584 | if (op_alt_regno[i][j] == -1 | |
e1a797ad | 585 | && TEST_BIT (preferred, j) |
6659485c | 586 | && reg_fits_class_p (testreg, rclass, 0, mode) |
971ba038 | 587 | && (!CONST_INT_P (recog_data.operand[i]) |
7013e87c | 588 | || (set_src_cost (recog_data.operand[i], |
589 | optimize_bb_for_speed_p | |
590 | (BLOCK_FOR_INSN (insn))) | |
591 | > set_src_cost (testreg, | |
592 | optimize_bb_for_speed_p | |
593 | (BLOCK_FOR_INSN (insn)))))) | |
8f8cadbc | 594 | { |
595 | alternative_nregs[j]++; | |
596 | op_alt_regno[i][j] = regno; | |
597 | } | |
598 | j++; | |
b9c74b4d | 599 | rclass = NO_REGS; |
8f8cadbc | 600 | break; |
601 | } | |
602 | p += CONSTRAINT_LEN (c, p); | |
603 | ||
604 | if (c == '\0') | |
605 | break; | |
606 | } | |
607 | } | |
608 | } | |
609 | ||
610 | /* Record all alternatives which are better or equal to the currently | |
611 | matching one in the alternative_order array. */ | |
612 | for (i = j = 0; i < recog_data.n_alternatives; i++) | |
613 | if (alternative_reject[i] <= alternative_reject[which_alternative]) | |
614 | alternative_order[j++] = i; | |
615 | recog_data.n_alternatives = j; | |
616 | ||
617 | /* Sort it. Given a small number of alternatives, a dumb algorithm | |
618 | won't hurt too much. */ | |
619 | for (i = 0; i < recog_data.n_alternatives - 1; i++) | |
620 | { | |
621 | int best = i; | |
622 | int best_reject = alternative_reject[alternative_order[i]]; | |
623 | int best_nregs = alternative_nregs[alternative_order[i]]; | |
8f8cadbc | 624 | |
625 | for (j = i + 1; j < recog_data.n_alternatives; j++) | |
626 | { | |
627 | int this_reject = alternative_reject[alternative_order[j]]; | |
628 | int this_nregs = alternative_nregs[alternative_order[j]]; | |
629 | ||
630 | if (this_reject < best_reject | |
c2d0cf41 | 631 | || (this_reject == best_reject && this_nregs > best_nregs)) |
8f8cadbc | 632 | { |
633 | best = j; | |
634 | best_reject = this_reject; | |
635 | best_nregs = this_nregs; | |
636 | } | |
637 | } | |
638 | ||
dfcf26a5 | 639 | std::swap (alternative_order[best], alternative_order[i]); |
8f8cadbc | 640 | } |
641 | ||
642 | /* Substitute the operands as determined by op_alt_regno for the best | |
643 | alternative. */ | |
644 | j = alternative_order[0]; | |
645 | ||
646 | for (i = 0; i < recog_data.n_operands; i++) | |
647 | { | |
3754d046 | 648 | machine_mode mode = recog_data.operand_mode[i]; |
8f8cadbc | 649 | if (op_alt_regno[i][j] == -1) |
650 | continue; | |
651 | ||
652 | validate_change (insn, recog_data.operand_loc[i], | |
653 | gen_rtx_REG (mode, op_alt_regno[i][j]), 1); | |
654 | } | |
655 | ||
656 | for (i = recog_data.n_dups - 1; i >= 0; i--) | |
657 | { | |
658 | int op = recog_data.dup_num[i]; | |
3754d046 | 659 | machine_mode mode = recog_data.operand_mode[op]; |
8f8cadbc | 660 | |
661 | if (op_alt_regno[op][j] == -1) | |
662 | continue; | |
663 | ||
664 | validate_change (insn, recog_data.dup_loc[i], | |
665 | gen_rtx_REG (mode, op_alt_regno[op][j]), 1); | |
666 | } | |
667 | ||
668 | return apply_change_group (); | |
669 | } | |
670 | \f | |
671 | /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg | |
672 | addressing now. | |
673 | This code might also be useful when reload gave up on reg+reg addressing | |
674 | because of clashes between the return register and INDEX_REG_CLASS. */ | |
675 | ||
676 | /* The maximum number of uses of a register we can keep track of to | |
677 | replace them with reg+reg addressing. */ | |
d83ccc81 | 678 | #define RELOAD_COMBINE_MAX_USES 16 |
8f8cadbc | 679 | |
d83ccc81 | 680 | /* Describes a recorded use of a register. */ |
681 | struct reg_use | |
682 | { | |
683 | /* The insn where a register has been used. */ | |
3aeaa53f | 684 | rtx_insn *insn; |
d83ccc81 | 685 | /* Points to the memory reference enclosing the use, if any, NULL_RTX |
686 | otherwise. */ | |
687 | rtx containing_mem; | |
9d75589a | 688 | /* Location of the register within INSN. */ |
d83ccc81 | 689 | rtx *usep; |
690 | /* The reverse uid of the insn. */ | |
691 | int ruid; | |
692 | }; | |
8f8cadbc | 693 | |
694 | /* If the register is used in some unknown fashion, USE_INDEX is negative. | |
695 | If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID | |
d83ccc81 | 696 | indicates where it is first set or clobbered. |
8f8cadbc | 697 | Otherwise, USE_INDEX is the index of the last encountered use of the |
d83ccc81 | 698 | register (which is first among these we have seen since we scan backwards). |
699 | USE_RUID indicates the first encountered, i.e. last, of these uses. | |
700 | If ALL_OFFSETS_MATCH is true, all encountered uses were inside a PLUS | |
701 | with a constant offset; OFFSET contains this constant in that case. | |
8f8cadbc | 702 | STORE_RUID is always meaningful if we only want to use a value in a |
703 | register in a different place: it denotes the next insn in the insn | |
d83ccc81 | 704 | stream (i.e. the last encountered) that sets or clobbers the register. |
705 | REAL_STORE_RUID is similar, but clobbers are ignored when updating it. */ | |
8f8cadbc | 706 | static struct |
707 | { | |
708 | struct reg_use reg_use[RELOAD_COMBINE_MAX_USES]; | |
8f8cadbc | 709 | rtx offset; |
d83ccc81 | 710 | int use_index; |
8f8cadbc | 711 | int store_ruid; |
d83ccc81 | 712 | int real_store_ruid; |
8f8cadbc | 713 | int use_ruid; |
d83ccc81 | 714 | bool all_offsets_match; |
8f8cadbc | 715 | } reg_state[FIRST_PSEUDO_REGISTER]; |
716 | ||
717 | /* Reverse linear uid. This is increased in reload_combine while scanning | |
718 | the instructions from last to first. It is used to set last_label_ruid | |
719 | and the store_ruid / use_ruid fields in reg_state. */ | |
720 | static int reload_combine_ruid; | |
721 | ||
fb79f695 | 722 | /* The RUID of the last label we encountered in reload_combine. */ |
723 | static int last_label_ruid; | |
724 | ||
d83ccc81 | 725 | /* The RUID of the last jump we encountered in reload_combine. */ |
726 | static int last_jump_ruid; | |
727 | ||
fb79f695 | 728 | /* The register numbers of the first and last index register. A value of |
729 | -1 in LAST_INDEX_REG indicates that we've previously computed these | |
730 | values and found no suitable index registers. */ | |
731 | static int first_index_reg = -1; | |
732 | static int last_index_reg; | |
733 | ||
8f8cadbc | 734 | #define LABEL_LIVE(LABEL) \ |
735 | (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno]) | |
736 | ||
d83ccc81 | 737 | /* Subroutine of reload_combine_split_ruids, called to fix up a single |
738 | ruid pointed to by *PRUID if it is higher than SPLIT_RUID. */ | |
739 | ||
740 | static inline void | |
741 | reload_combine_split_one_ruid (int *pruid, int split_ruid) | |
742 | { | |
743 | if (*pruid > split_ruid) | |
744 | (*pruid)++; | |
745 | } | |
746 | ||
747 | /* Called when we insert a new insn in a position we've already passed in | |
748 | the scan. Examine all our state, increasing all ruids that are higher | |
749 | than SPLIT_RUID by one in order to make room for a new insn. */ | |
750 | ||
751 | static void | |
752 | reload_combine_split_ruids (int split_ruid) | |
753 | { | |
754 | unsigned i; | |
755 | ||
756 | reload_combine_split_one_ruid (&reload_combine_ruid, split_ruid); | |
757 | reload_combine_split_one_ruid (&last_label_ruid, split_ruid); | |
758 | reload_combine_split_one_ruid (&last_jump_ruid, split_ruid); | |
759 | ||
760 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
761 | { | |
762 | int j, idx = reg_state[i].use_index; | |
763 | reload_combine_split_one_ruid (®_state[i].use_ruid, split_ruid); | |
764 | reload_combine_split_one_ruid (®_state[i].store_ruid, split_ruid); | |
765 | reload_combine_split_one_ruid (®_state[i].real_store_ruid, | |
766 | split_ruid); | |
767 | if (idx < 0) | |
768 | continue; | |
769 | for (j = idx; j < RELOAD_COMBINE_MAX_USES; j++) | |
770 | { | |
771 | reload_combine_split_one_ruid (®_state[i].reg_use[j].ruid, | |
772 | split_ruid); | |
773 | } | |
774 | } | |
775 | } | |
776 | ||
777 | /* Called when we are about to rescan a previously encountered insn with | |
778 | reload_combine_note_use after modifying some part of it. This clears all | |
779 | information about uses in that particular insn. */ | |
780 | ||
781 | static void | |
3aeaa53f | 782 | reload_combine_purge_insn_uses (rtx_insn *insn) |
d83ccc81 | 783 | { |
784 | unsigned i; | |
785 | ||
786 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
787 | { | |
788 | int j, k, idx = reg_state[i].use_index; | |
789 | if (idx < 0) | |
790 | continue; | |
791 | j = k = RELOAD_COMBINE_MAX_USES; | |
792 | while (j-- > idx) | |
793 | { | |
794 | if (reg_state[i].reg_use[j].insn != insn) | |
795 | { | |
796 | k--; | |
797 | if (k != j) | |
798 | reg_state[i].reg_use[k] = reg_state[i].reg_use[j]; | |
799 | } | |
800 | } | |
801 | reg_state[i].use_index = k; | |
802 | } | |
803 | } | |
804 | ||
805 | /* Called when we need to forget about all uses of REGNO after an insn | |
806 | which is identified by RUID. */ | |
807 | ||
808 | static void | |
809 | reload_combine_purge_reg_uses_after_ruid (unsigned regno, int ruid) | |
810 | { | |
811 | int j, k, idx = reg_state[regno].use_index; | |
812 | if (idx < 0) | |
813 | return; | |
814 | j = k = RELOAD_COMBINE_MAX_USES; | |
815 | while (j-- > idx) | |
816 | { | |
817 | if (reg_state[regno].reg_use[j].ruid >= ruid) | |
818 | { | |
819 | k--; | |
820 | if (k != j) | |
821 | reg_state[regno].reg_use[k] = reg_state[regno].reg_use[j]; | |
822 | } | |
823 | } | |
824 | reg_state[regno].use_index = k; | |
825 | } | |
826 | ||
827 | /* Find the use of REGNO with the ruid that is highest among those | |
828 | lower than RUID_LIMIT, and return it if it is the only use of this | |
727047d0 | 829 | reg in the insn. Return NULL otherwise. */ |
d83ccc81 | 830 | |
831 | static struct reg_use * | |
832 | reload_combine_closest_single_use (unsigned regno, int ruid_limit) | |
833 | { | |
834 | int i, best_ruid = 0; | |
835 | int use_idx = reg_state[regno].use_index; | |
836 | struct reg_use *retval; | |
837 | ||
838 | if (use_idx < 0) | |
839 | return NULL; | |
840 | retval = NULL; | |
841 | for (i = use_idx; i < RELOAD_COMBINE_MAX_USES; i++) | |
842 | { | |
0ead6a7d | 843 | struct reg_use *use = reg_state[regno].reg_use + i; |
844 | int this_ruid = use->ruid; | |
d83ccc81 | 845 | if (this_ruid >= ruid_limit) |
846 | continue; | |
847 | if (this_ruid > best_ruid) | |
848 | { | |
849 | best_ruid = this_ruid; | |
727047d0 | 850 | retval = use; |
d83ccc81 | 851 | } |
727047d0 | 852 | else if (this_ruid == best_ruid) |
d83ccc81 | 853 | retval = NULL; |
854 | } | |
855 | if (last_label_ruid >= best_ruid) | |
856 | return NULL; | |
857 | return retval; | |
858 | } | |
859 | ||
65069495 | 860 | /* After we've moved an add insn, fix up any debug insns that occur |
861 | between the old location of the add and the new location. REG is | |
862 | the destination register of the add insn; REPLACEMENT is the | |
863 | SET_SRC of the add. FROM and TO specify the range in which we | |
864 | should make this change on debug insns. */ | |
0ead6a7d | 865 | |
866 | static void | |
3aeaa53f | 867 | fixup_debug_insns (rtx reg, rtx replacement, rtx_insn *from, rtx_insn *to) |
0ead6a7d | 868 | { |
3aeaa53f | 869 | rtx_insn *insn; |
65069495 | 870 | for (insn = from; insn != to; insn = NEXT_INSN (insn)) |
0ead6a7d | 871 | { |
872 | rtx t; | |
65069495 | 873 | |
874 | if (!DEBUG_INSN_P (insn)) | |
0ead6a7d | 875 | continue; |
65069495 | 876 | |
877 | t = INSN_VAR_LOCATION_LOC (insn); | |
727047d0 | 878 | t = simplify_replace_rtx (t, reg, replacement); |
65069495 | 879 | validate_change (insn, &INSN_VAR_LOCATION_LOC (insn), t, 0); |
0ead6a7d | 880 | } |
881 | } | |
882 | ||
692ec7c8 | 883 | /* Subroutine of reload_combine_recognize_const_pattern. Try to replace REG |
884 | with SRC in the insn described by USE, taking costs into account. Return | |
885 | true if we made the replacement. */ | |
886 | ||
887 | static bool | |
888 | try_replace_in_use (struct reg_use *use, rtx reg, rtx src) | |
889 | { | |
3aeaa53f | 890 | rtx_insn *use_insn = use->insn; |
692ec7c8 | 891 | rtx mem = use->containing_mem; |
892 | bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (use_insn)); | |
893 | ||
894 | if (mem != NULL_RTX) | |
895 | { | |
896 | addr_space_t as = MEM_ADDR_SPACE (mem); | |
897 | rtx oldaddr = XEXP (mem, 0); | |
898 | rtx newaddr = NULL_RTX; | |
899 | int old_cost = address_cost (oldaddr, GET_MODE (mem), as, speed); | |
900 | int new_cost; | |
901 | ||
902 | newaddr = simplify_replace_rtx (oldaddr, reg, src); | |
903 | if (memory_address_addr_space_p (GET_MODE (mem), newaddr, as)) | |
904 | { | |
905 | XEXP (mem, 0) = newaddr; | |
906 | new_cost = address_cost (newaddr, GET_MODE (mem), as, speed); | |
907 | XEXP (mem, 0) = oldaddr; | |
908 | if (new_cost <= old_cost | |
909 | && validate_change (use_insn, | |
910 | &XEXP (mem, 0), newaddr, 0)) | |
911 | return true; | |
912 | } | |
913 | } | |
914 | else | |
915 | { | |
916 | rtx new_set = single_set (use_insn); | |
917 | if (new_set | |
918 | && REG_P (SET_DEST (new_set)) | |
919 | && GET_CODE (SET_SRC (new_set)) == PLUS | |
920 | && REG_P (XEXP (SET_SRC (new_set), 0)) | |
921 | && CONSTANT_P (XEXP (SET_SRC (new_set), 1))) | |
922 | { | |
923 | rtx new_src; | |
7013e87c | 924 | int old_cost = set_src_cost (SET_SRC (new_set), speed); |
692ec7c8 | 925 | |
926 | gcc_assert (rtx_equal_p (XEXP (SET_SRC (new_set), 0), reg)); | |
927 | new_src = simplify_replace_rtx (SET_SRC (new_set), reg, src); | |
928 | ||
7013e87c | 929 | if (set_src_cost (new_src, speed) <= old_cost |
692ec7c8 | 930 | && validate_change (use_insn, &SET_SRC (new_set), |
931 | new_src, 0)) | |
932 | return true; | |
933 | } | |
934 | } | |
935 | return false; | |
936 | } | |
937 | ||
d83ccc81 | 938 | /* Called by reload_combine when scanning INSN. This function tries to detect |
939 | patterns where a constant is added to a register, and the result is used | |
940 | in an address. | |
941 | Return true if no further processing is needed on INSN; false if it wasn't | |
942 | recognized and should be handled normally. */ | |
943 | ||
944 | static bool | |
3aeaa53f | 945 | reload_combine_recognize_const_pattern (rtx_insn *insn) |
d83ccc81 | 946 | { |
947 | int from_ruid = reload_combine_ruid; | |
948 | rtx set, pat, reg, src, addreg; | |
949 | unsigned int regno; | |
950 | struct reg_use *use; | |
951 | bool must_move_add; | |
3aeaa53f | 952 | rtx_insn *add_moved_after_insn = NULL; |
d83ccc81 | 953 | int add_moved_after_ruid = 0; |
954 | int clobbered_regno = -1; | |
955 | ||
956 | set = single_set (insn); | |
957 | if (set == NULL_RTX) | |
958 | return false; | |
959 | ||
960 | reg = SET_DEST (set); | |
961 | src = SET_SRC (set); | |
962 | if (!REG_P (reg) | |
0933f1d9 | 963 | || REG_NREGS (reg) != 1 |
d83ccc81 | 964 | || GET_MODE (reg) != Pmode |
965 | || reg == stack_pointer_rtx) | |
966 | return false; | |
967 | ||
968 | regno = REGNO (reg); | |
969 | ||
970 | /* We look for a REG1 = REG2 + CONSTANT insn, followed by either | |
971 | uses of REG1 inside an address, or inside another add insn. If | |
972 | possible and profitable, merge the addition into subsequent | |
973 | uses. */ | |
974 | if (GET_CODE (src) != PLUS | |
975 | || !REG_P (XEXP (src, 0)) | |
976 | || !CONSTANT_P (XEXP (src, 1))) | |
977 | return false; | |
978 | ||
979 | addreg = XEXP (src, 0); | |
980 | must_move_add = rtx_equal_p (reg, addreg); | |
981 | ||
982 | pat = PATTERN (insn); | |
983 | if (must_move_add && set != pat) | |
984 | { | |
985 | /* We have to be careful when moving the add; apart from the | |
986 | single_set there may also be clobbers. Recognize one special | |
987 | case, that of one clobber alongside the set (likely a clobber | |
988 | of the CC register). */ | |
989 | gcc_assert (GET_CODE (PATTERN (insn)) == PARALLEL); | |
990 | if (XVECLEN (pat, 0) != 2 || XVECEXP (pat, 0, 0) != set | |
991 | || GET_CODE (XVECEXP (pat, 0, 1)) != CLOBBER | |
992 | || !REG_P (XEXP (XVECEXP (pat, 0, 1), 0))) | |
993 | return false; | |
994 | clobbered_regno = REGNO (XEXP (XVECEXP (pat, 0, 1), 0)); | |
995 | } | |
996 | ||
997 | do | |
998 | { | |
999 | use = reload_combine_closest_single_use (regno, from_ruid); | |
1000 | ||
1001 | if (use) | |
1002 | /* Start the search for the next use from here. */ | |
1003 | from_ruid = use->ruid; | |
1004 | ||
1005 | if (use && GET_MODE (*use->usep) == Pmode) | |
1006 | { | |
692ec7c8 | 1007 | bool delete_add = false; |
3aeaa53f | 1008 | rtx_insn *use_insn = use->insn; |
d83ccc81 | 1009 | int use_ruid = use->ruid; |
d83ccc81 | 1010 | |
1011 | /* Avoid moving the add insn past a jump. */ | |
0ead6a7d | 1012 | if (must_move_add && use_ruid <= last_jump_ruid) |
d83ccc81 | 1013 | break; |
1014 | ||
1015 | /* If the add clobbers another hard reg in parallel, don't move | |
1016 | it past a real set of this hard reg. */ | |
1017 | if (must_move_add && clobbered_regno >= 0 | |
1018 | && reg_state[clobbered_regno].real_store_ruid >= use_ruid) | |
1019 | break; | |
1020 | ||
33b7314b | 1021 | /* Do not separate cc0 setter and cc0 user on HAVE_cc0 targets. */ |
ff900b8e | 1022 | if (HAVE_cc0 && must_move_add && sets_cc0_p (PATTERN (use_insn))) |
33b7314b | 1023 | break; |
33b7314b | 1024 | |
6aba0ea1 | 1025 | gcc_assert (reg_state[regno].store_ruid <= use_ruid); |
1026 | /* Avoid moving a use of ADDREG past a point where it is stored. */ | |
692ec7c8 | 1027 | if (reg_state[REGNO (addreg)].store_ruid > use_ruid) |
d83ccc81 | 1028 | break; |
1029 | ||
692ec7c8 | 1030 | /* We also must not move the addition past an insn that sets |
1031 | the same register, unless we can combine two add insns. */ | |
1032 | if (must_move_add && reg_state[regno].store_ruid == use_ruid) | |
d83ccc81 | 1033 | { |
692ec7c8 | 1034 | if (use->containing_mem == NULL_RTX) |
1035 | delete_add = true; | |
1036 | else | |
1037 | break; | |
d83ccc81 | 1038 | } |
d83ccc81 | 1039 | |
692ec7c8 | 1040 | if (try_replace_in_use (use, reg, src)) |
1041 | { | |
1042 | reload_combine_purge_insn_uses (use_insn); | |
1043 | reload_combine_note_use (&PATTERN (use_insn), use_insn, | |
1044 | use_ruid, NULL_RTX); | |
d83ccc81 | 1045 | |
692ec7c8 | 1046 | if (delete_add) |
1047 | { | |
1048 | fixup_debug_insns (reg, src, insn, use_insn); | |
1049 | delete_insn (insn); | |
1050 | return true; | |
1051 | } | |
1052 | if (must_move_add) | |
1053 | { | |
1054 | add_moved_after_insn = use_insn; | |
1055 | add_moved_after_ruid = use_ruid; | |
d83ccc81 | 1056 | } |
692ec7c8 | 1057 | continue; |
d83ccc81 | 1058 | } |
d83ccc81 | 1059 | } |
6aba0ea1 | 1060 | /* If we get here, we couldn't handle this use. */ |
1061 | if (must_move_add) | |
1062 | break; | |
d83ccc81 | 1063 | } |
1064 | while (use); | |
1065 | ||
1066 | if (!must_move_add || add_moved_after_insn == NULL_RTX) | |
1067 | /* Process the add normally. */ | |
1068 | return false; | |
1069 | ||
65069495 | 1070 | fixup_debug_insns (reg, src, insn, add_moved_after_insn); |
1071 | ||
d83ccc81 | 1072 | reorder_insns (insn, insn, add_moved_after_insn); |
1073 | reload_combine_purge_reg_uses_after_ruid (regno, add_moved_after_ruid); | |
1074 | reload_combine_split_ruids (add_moved_after_ruid - 1); | |
1075 | reload_combine_note_use (&PATTERN (insn), insn, | |
1076 | add_moved_after_ruid, NULL_RTX); | |
1077 | reg_state[regno].store_ruid = add_moved_after_ruid; | |
1078 | ||
1079 | return true; | |
1080 | } | |
1081 | ||
fb79f695 | 1082 | /* Called by reload_combine when scanning INSN. Try to detect a pattern we |
1083 | can handle and improve. Return true if no further processing is needed on | |
1084 | INSN; false if it wasn't recognized and should be handled normally. */ | |
1085 | ||
1086 | static bool | |
3aeaa53f | 1087 | reload_combine_recognize_pattern (rtx_insn *insn) |
fb79f695 | 1088 | { |
1089 | rtx set, reg, src; | |
1090 | unsigned int regno; | |
1091 | ||
d83ccc81 | 1092 | set = single_set (insn); |
1093 | if (set == NULL_RTX) | |
1094 | return false; | |
1095 | ||
1096 | reg = SET_DEST (set); | |
1097 | src = SET_SRC (set); | |
0933f1d9 | 1098 | if (!REG_P (reg) || REG_NREGS (reg) != 1) |
d83ccc81 | 1099 | return false; |
1100 | ||
1101 | regno = REGNO (reg); | |
1102 | ||
fb79f695 | 1103 | /* Look for (set (REGX) (CONST_INT)) |
1104 | (set (REGX) (PLUS (REGX) (REGY))) | |
1105 | ... | |
1106 | ... (MEM (REGX)) ... | |
1107 | and convert it to | |
1108 | (set (REGZ) (CONST_INT)) | |
1109 | ... | |
1110 | ... (MEM (PLUS (REGZ) (REGY)))... . | |
1111 | ||
1112 | First, check that we have (set (REGX) (PLUS (REGX) (REGY))) | |
1113 | and that we know all uses of REGX before it dies. | |
1114 | Also, explicitly check that REGX != REGY; our life information | |
1115 | does not yet show whether REGY changes in this insn. */ | |
fb79f695 | 1116 | |
1117 | if (GET_CODE (src) == PLUS | |
d83ccc81 | 1118 | && reg_state[regno].all_offsets_match |
1119 | && last_index_reg != -1 | |
fb79f695 | 1120 | && REG_P (XEXP (src, 1)) |
1121 | && rtx_equal_p (XEXP (src, 0), reg) | |
1122 | && !rtx_equal_p (XEXP (src, 1), reg) | |
727047d0 | 1123 | && reg_state[regno].use_index >= 0 |
1124 | && reg_state[regno].use_index < RELOAD_COMBINE_MAX_USES | |
fb79f695 | 1125 | && last_label_ruid < reg_state[regno].use_ruid) |
1126 | { | |
1127 | rtx base = XEXP (src, 1); | |
3aeaa53f | 1128 | rtx_insn *prev = prev_nonnote_nondebug_insn (insn); |
fb79f695 | 1129 | rtx prev_set = prev ? single_set (prev) : NULL_RTX; |
1130 | rtx index_reg = NULL_RTX; | |
1131 | rtx reg_sum = NULL_RTX; | |
1132 | int i; | |
1133 | ||
1134 | /* Now we need to set INDEX_REG to an index register (denoted as | |
1135 | REGZ in the illustration above) and REG_SUM to the expression | |
1136 | register+register that we want to use to substitute uses of REG | |
1137 | (typically in MEMs) with. First check REG and BASE for being | |
1138 | index registers; we can use them even if they are not dead. */ | |
1139 | if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno) | |
1140 | || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], | |
1141 | REGNO (base))) | |
1142 | { | |
1143 | index_reg = reg; | |
1144 | reg_sum = src; | |
1145 | } | |
1146 | else | |
1147 | { | |
1148 | /* Otherwise, look for a free index register. Since we have | |
1149 | checked above that neither REG nor BASE are index registers, | |
1150 | if we find anything at all, it will be different from these | |
1151 | two registers. */ | |
1152 | for (i = first_index_reg; i <= last_index_reg; i++) | |
1153 | { | |
1154 | if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i) | |
1155 | && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES | |
1156 | && reg_state[i].store_ruid <= reg_state[regno].use_ruid | |
727047d0 | 1157 | && (call_used_regs[i] || df_regs_ever_live_p (i)) |
1158 | && (!frame_pointer_needed || i != HARD_FRAME_POINTER_REGNUM) | |
1159 | && !fixed_regs[i] && !global_regs[i] | |
1160 | && hard_regno_nregs[i][GET_MODE (reg)] == 1 | |
1161 | && targetm.hard_regno_scratch_ok (i)) | |
fb79f695 | 1162 | { |
1163 | index_reg = gen_rtx_REG (GET_MODE (reg), i); | |
1164 | reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base); | |
1165 | break; | |
1166 | } | |
1167 | } | |
1168 | } | |
1169 | ||
1170 | /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that | |
1171 | (REGY), i.e. BASE, is not clobbered before the last use we'll | |
1172 | create. */ | |
1173 | if (reg_sum | |
1174 | && prev_set | |
1175 | && CONST_INT_P (SET_SRC (prev_set)) | |
1176 | && rtx_equal_p (SET_DEST (prev_set), reg) | |
fb79f695 | 1177 | && (reg_state[REGNO (base)].store_ruid |
1178 | <= reg_state[regno].use_ruid)) | |
1179 | { | |
1180 | /* Change destination register and, if necessary, the constant | |
1181 | value in PREV, the constant loading instruction. */ | |
1182 | validate_change (prev, &SET_DEST (prev_set), index_reg, 1); | |
1183 | if (reg_state[regno].offset != const0_rtx) | |
1184 | validate_change (prev, | |
1185 | &SET_SRC (prev_set), | |
1186 | GEN_INT (INTVAL (SET_SRC (prev_set)) | |
1187 | + INTVAL (reg_state[regno].offset)), | |
1188 | 1); | |
1189 | ||
1190 | /* Now for every use of REG that we have recorded, replace REG | |
1191 | with REG_SUM. */ | |
1192 | for (i = reg_state[regno].use_index; | |
1193 | i < RELOAD_COMBINE_MAX_USES; i++) | |
1194 | validate_unshare_change (reg_state[regno].reg_use[i].insn, | |
1195 | reg_state[regno].reg_use[i].usep, | |
1196 | /* Each change must have its own | |
1197 | replacement. */ | |
1198 | reg_sum, 1); | |
1199 | ||
1200 | if (apply_change_group ()) | |
1201 | { | |
65069495 | 1202 | struct reg_use *lowest_ruid = NULL; |
1203 | ||
fb79f695 | 1204 | /* For every new use of REG_SUM, we have to record the use |
1205 | of BASE therein, i.e. operand 1. */ | |
1206 | for (i = reg_state[regno].use_index; | |
1207 | i < RELOAD_COMBINE_MAX_USES; i++) | |
65069495 | 1208 | { |
1209 | struct reg_use *use = reg_state[regno].reg_use + i; | |
1210 | reload_combine_note_use (&XEXP (*use->usep, 1), use->insn, | |
1211 | use->ruid, use->containing_mem); | |
1212 | if (lowest_ruid == NULL || use->ruid < lowest_ruid->ruid) | |
1213 | lowest_ruid = use; | |
1214 | } | |
1215 | ||
1216 | fixup_debug_insns (reg, reg_sum, insn, lowest_ruid->insn); | |
fb79f695 | 1217 | |
fb79f695 | 1218 | /* Delete the reg-reg addition. */ |
1219 | delete_insn (insn); | |
1220 | ||
1221 | if (reg_state[regno].offset != const0_rtx) | |
1222 | /* Previous REG_EQUIV / REG_EQUAL notes for PREV | |
1223 | are now invalid. */ | |
1224 | remove_reg_equal_equiv_notes (prev); | |
1225 | ||
1226 | reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES; | |
fb79f695 | 1227 | return true; |
1228 | } | |
1229 | } | |
1230 | } | |
1231 | return false; | |
1232 | } | |
1233 | ||
8f8cadbc | 1234 | static void |
3ad4992f | 1235 | reload_combine (void) |
8f8cadbc | 1236 | { |
3aeaa53f | 1237 | rtx_insn *insn, *prev; |
8f8cadbc | 1238 | basic_block bb; |
1239 | unsigned int r; | |
8f8cadbc | 1240 | int min_labelno, n_labels; |
1241 | HARD_REG_SET ever_live_at_start, *label_live; | |
1242 | ||
8f8cadbc | 1243 | /* To avoid wasting too much time later searching for an index register, |
1244 | determine the minimum and maximum index register numbers. */ | |
fb79f695 | 1245 | if (INDEX_REG_CLASS == NO_REGS) |
1246 | last_index_reg = -1; | |
1247 | else if (first_index_reg == -1 && last_index_reg == 0) | |
1248 | { | |
1249 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) | |
1250 | if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r)) | |
1251 | { | |
1252 | if (first_index_reg == -1) | |
1253 | first_index_reg = r; | |
1254 | ||
1255 | last_index_reg = r; | |
1256 | } | |
1257 | ||
1258 | /* If no index register is available, we can quit now. Set LAST_INDEX_REG | |
1259 | to -1 so we'll know to quit early the next time we get here. */ | |
1260 | if (first_index_reg == -1) | |
1261 | { | |
1262 | last_index_reg = -1; | |
1263 | return; | |
1264 | } | |
1265 | } | |
8f8cadbc | 1266 | |
8f8cadbc | 1267 | /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime |
1268 | information is a bit fuzzy immediately after reload, but it's | |
1269 | still good enough to determine which registers are live at a jump | |
1270 | destination. */ | |
1271 | min_labelno = get_first_label_num (); | |
1272 | n_labels = max_label_num () - min_labelno; | |
4c36ffe6 | 1273 | label_live = XNEWVEC (HARD_REG_SET, n_labels); |
8f8cadbc | 1274 | CLEAR_HARD_REG_SET (ever_live_at_start); |
1275 | ||
7a46197b | 1276 | FOR_EACH_BB_REVERSE_FN (bb, cfun) |
8f8cadbc | 1277 | { |
5496dbfc | 1278 | insn = BB_HEAD (bb); |
6d7dc5b9 | 1279 | if (LABEL_P (insn)) |
8f8cadbc | 1280 | { |
1281 | HARD_REG_SET live; | |
deb2741b | 1282 | bitmap live_in = df_get_live_in (bb); |
8f8cadbc | 1283 | |
deb2741b | 1284 | REG_SET_TO_HARD_REG_SET (live, live_in); |
1285 | compute_use_by_pseudos (&live, live_in); | |
8f8cadbc | 1286 | COPY_HARD_REG_SET (LABEL_LIVE (insn), live); |
1287 | IOR_HARD_REG_SET (ever_live_at_start, live); | |
1288 | } | |
1289 | } | |
1290 | ||
1291 | /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */ | |
d83ccc81 | 1292 | last_label_ruid = last_jump_ruid = reload_combine_ruid = 0; |
8f8cadbc | 1293 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) |
1294 | { | |
d83ccc81 | 1295 | reg_state[r].store_ruid = 0; |
1296 | reg_state[r].real_store_ruid = 0; | |
8f8cadbc | 1297 | if (fixed_regs[r]) |
1298 | reg_state[r].use_index = -1; | |
1299 | else | |
1300 | reg_state[r].use_index = RELOAD_COMBINE_MAX_USES; | |
1301 | } | |
1302 | ||
d83ccc81 | 1303 | for (insn = get_last_insn (); insn; insn = prev) |
8f8cadbc | 1304 | { |
8b52f64e | 1305 | bool control_flow_insn; |
8f8cadbc | 1306 | rtx note; |
1307 | ||
d83ccc81 | 1308 | prev = PREV_INSN (insn); |
1309 | ||
8f8cadbc | 1310 | /* We cannot do our optimization across labels. Invalidating all the use |
1311 | information we have would be costly, so we just note where the label | |
1312 | is and then later disable any optimization that would cross it. */ | |
6d7dc5b9 | 1313 | if (LABEL_P (insn)) |
8f8cadbc | 1314 | last_label_ruid = reload_combine_ruid; |
19f69355 | 1315 | else if (BARRIER_P (insn)) |
1316 | { | |
1317 | /* Crossing a barrier resets all the use information. */ | |
1318 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) | |
1319 | if (! fixed_regs[r]) | |
8f8cadbc | 1320 | reg_state[r].use_index = RELOAD_COMBINE_MAX_USES; |
19f69355 | 1321 | } |
1322 | else if (INSN_P (insn) && volatile_insn_p (PATTERN (insn))) | |
1323 | /* Optimizations across insns being marked as volatile must be | |
1324 | prevented. All the usage information is invalidated | |
1325 | here. */ | |
1326 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) | |
1327 | if (! fixed_regs[r] | |
1328 | && reg_state[r].use_index != RELOAD_COMBINE_MAX_USES) | |
1329 | reg_state[r].use_index = -1; | |
8f8cadbc | 1330 | |
65069495 | 1331 | if (! NONDEBUG_INSN_P (insn)) |
8f8cadbc | 1332 | continue; |
1333 | ||
1334 | reload_combine_ruid++; | |
1335 | ||
8b52f64e | 1336 | control_flow_insn = control_flow_insn_p (insn); |
1337 | if (control_flow_insn) | |
d83ccc81 | 1338 | last_jump_ruid = reload_combine_ruid; |
1339 | ||
1340 | if (reload_combine_recognize_const_pattern (insn) | |
1341 | || reload_combine_recognize_pattern (insn)) | |
fb79f695 | 1342 | continue; |
8f8cadbc | 1343 | |
1344 | note_stores (PATTERN (insn), reload_combine_note_store, NULL); | |
1345 | ||
6d7dc5b9 | 1346 | if (CALL_P (insn)) |
8f8cadbc | 1347 | { |
1348 | rtx link; | |
30326fda | 1349 | HARD_REG_SET used_regs; |
1350 | ||
1351 | get_call_reg_set_usage (insn, &used_regs, call_used_reg_set); | |
8f8cadbc | 1352 | |
1353 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) | |
30326fda | 1354 | if (TEST_HARD_REG_BIT (used_regs, r)) |
8f8cadbc | 1355 | { |
1356 | reg_state[r].use_index = RELOAD_COMBINE_MAX_USES; | |
1357 | reg_state[r].store_ruid = reload_combine_ruid; | |
1358 | } | |
1359 | ||
1360 | for (link = CALL_INSN_FUNCTION_USAGE (insn); link; | |
1361 | link = XEXP (link, 1)) | |
1362 | { | |
c8010b80 | 1363 | rtx setuse = XEXP (link, 0); |
1364 | rtx usage_rtx = XEXP (setuse, 0); | |
1365 | if ((GET_CODE (setuse) == USE || GET_CODE (setuse) == CLOBBER) | |
1366 | && REG_P (usage_rtx)) | |
8f8cadbc | 1367 | { |
6a298741 | 1368 | unsigned int end_regno = END_REGNO (usage_rtx); |
1369 | for (unsigned int i = REGNO (usage_rtx); i < end_regno; ++i) | |
8f8cadbc | 1370 | if (GET_CODE (XEXP (link, 0)) == CLOBBER) |
1371 | { | |
1372 | reg_state[i].use_index = RELOAD_COMBINE_MAX_USES; | |
1373 | reg_state[i].store_ruid = reload_combine_ruid; | |
1374 | } | |
1375 | else | |
1376 | reg_state[i].use_index = -1; | |
1377 | } | |
1378 | } | |
8f8cadbc | 1379 | } |
f4979459 | 1380 | |
7777a939 | 1381 | if (control_flow_insn && !ANY_RETURN_P (PATTERN (insn))) |
8f8cadbc | 1382 | { |
1383 | /* Non-spill registers might be used at the call destination in | |
1384 | some unknown fashion, so we have to mark the unknown use. */ | |
1385 | HARD_REG_SET *live; | |
1386 | ||
1387 | if ((condjump_p (insn) || condjump_in_parallel_p (insn)) | |
1388 | && JUMP_LABEL (insn)) | |
7777a939 | 1389 | { |
1390 | if (ANY_RETURN_P (JUMP_LABEL (insn))) | |
1391 | live = NULL; | |
1392 | else | |
1393 | live = &LABEL_LIVE (JUMP_LABEL (insn)); | |
1394 | } | |
8f8cadbc | 1395 | else |
1396 | live = &ever_live_at_start; | |
1397 | ||
7777a939 | 1398 | if (live) |
1399 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) | |
1400 | if (TEST_HARD_REG_BIT (*live, r)) | |
1401 | reg_state[r].use_index = -1; | |
8f8cadbc | 1402 | } |
1403 | ||
8b52f64e | 1404 | reload_combine_note_use (&PATTERN (insn), insn, reload_combine_ruid, |
1405 | NULL_RTX); | |
1406 | ||
8f8cadbc | 1407 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) |
1408 | { | |
8b52f64e | 1409 | if (REG_NOTE_KIND (note) == REG_INC && REG_P (XEXP (note, 0))) |
8f8cadbc | 1410 | { |
1411 | int regno = REGNO (XEXP (note, 0)); | |
8f8cadbc | 1412 | reg_state[regno].store_ruid = reload_combine_ruid; |
d83ccc81 | 1413 | reg_state[regno].real_store_ruid = reload_combine_ruid; |
8f8cadbc | 1414 | reg_state[regno].use_index = -1; |
1415 | } | |
1416 | } | |
1417 | } | |
1418 | ||
1419 | free (label_live); | |
1420 | } | |
1421 | ||
1422 | /* Check if DST is a register or a subreg of a register; if it is, | |
d83ccc81 | 1423 | update store_ruid, real_store_ruid and use_index in the reg_state |
1424 | structure accordingly. Called via note_stores from reload_combine. */ | |
8f8cadbc | 1425 | |
1426 | static void | |
81a410b1 | 1427 | reload_combine_note_store (rtx dst, const_rtx set, void *data ATTRIBUTE_UNUSED) |
8f8cadbc | 1428 | { |
1429 | int regno = 0; | |
1430 | int i; | |
3754d046 | 1431 | machine_mode mode = GET_MODE (dst); |
8f8cadbc | 1432 | |
1433 | if (GET_CODE (dst) == SUBREG) | |
1434 | { | |
1435 | regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)), | |
1436 | GET_MODE (SUBREG_REG (dst)), | |
1437 | SUBREG_BYTE (dst), | |
1438 | GET_MODE (dst)); | |
1439 | dst = SUBREG_REG (dst); | |
1440 | } | |
fe6524b0 | 1441 | |
1442 | /* Some targets do argument pushes without adding REG_INC notes. */ | |
1443 | ||
1444 | if (MEM_P (dst)) | |
1445 | { | |
1446 | dst = XEXP (dst, 0); | |
1447 | if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_INC | |
a5dda0b9 | 1448 | || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC |
1449 | || GET_CODE (dst) == PRE_MODIFY || GET_CODE (dst) == POST_MODIFY) | |
fe6524b0 | 1450 | { |
6a298741 | 1451 | unsigned int end_regno = END_REGNO (XEXP (dst, 0)); |
1452 | for (unsigned int i = REGNO (XEXP (dst, 0)); i < end_regno; ++i) | |
fe6524b0 | 1453 | { |
1454 | /* We could probably do better, but for now mark the register | |
1455 | as used in an unknown fashion and set/clobbered at this | |
1456 | insn. */ | |
1457 | reg_state[i].use_index = -1; | |
1458 | reg_state[i].store_ruid = reload_combine_ruid; | |
1459 | reg_state[i].real_store_ruid = reload_combine_ruid; | |
1460 | } | |
1461 | } | |
1462 | else | |
1463 | return; | |
1464 | } | |
1465 | ||
8ad4c111 | 1466 | if (!REG_P (dst)) |
8f8cadbc | 1467 | return; |
1468 | regno += REGNO (dst); | |
1469 | ||
1470 | /* note_stores might have stripped a STRICT_LOW_PART, so we have to be | |
1471 | careful with registers / register parts that are not full words. | |
476d094d | 1472 | Similarly for ZERO_EXTRACT. */ |
d83ccc81 | 1473 | if (GET_CODE (SET_DEST (set)) == ZERO_EXTRACT |
8f8cadbc | 1474 | || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART) |
1475 | { | |
67d6c12b | 1476 | for (i = hard_regno_nregs[regno][mode] - 1 + regno; i >= regno; i--) |
8f8cadbc | 1477 | { |
1478 | reg_state[i].use_index = -1; | |
1479 | reg_state[i].store_ruid = reload_combine_ruid; | |
d83ccc81 | 1480 | reg_state[i].real_store_ruid = reload_combine_ruid; |
8f8cadbc | 1481 | } |
1482 | } | |
1483 | else | |
1484 | { | |
67d6c12b | 1485 | for (i = hard_regno_nregs[regno][mode] - 1 + regno; i >= regno; i--) |
8f8cadbc | 1486 | { |
1487 | reg_state[i].store_ruid = reload_combine_ruid; | |
d83ccc81 | 1488 | if (GET_CODE (set) == SET) |
1489 | reg_state[i].real_store_ruid = reload_combine_ruid; | |
8f8cadbc | 1490 | reg_state[i].use_index = RELOAD_COMBINE_MAX_USES; |
1491 | } | |
1492 | } | |
1493 | } | |
1494 | ||
1495 | /* XP points to a piece of rtl that has to be checked for any uses of | |
1496 | registers. | |
1497 | *XP is the pattern of INSN, or a part of it. | |
1498 | Called from reload_combine, and recursively by itself. */ | |
1499 | static void | |
3aeaa53f | 1500 | reload_combine_note_use (rtx *xp, rtx_insn *insn, int ruid, rtx containing_mem) |
8f8cadbc | 1501 | { |
1502 | rtx x = *xp; | |
1503 | enum rtx_code code = x->code; | |
1504 | const char *fmt; | |
1505 | int i, j; | |
1506 | rtx offset = const0_rtx; /* For the REG case below. */ | |
1507 | ||
1508 | switch (code) | |
1509 | { | |
1510 | case SET: | |
8ad4c111 | 1511 | if (REG_P (SET_DEST (x))) |
8f8cadbc | 1512 | { |
d83ccc81 | 1513 | reload_combine_note_use (&SET_SRC (x), insn, ruid, NULL_RTX); |
8f8cadbc | 1514 | return; |
1515 | } | |
1516 | break; | |
1517 | ||
1518 | case USE: | |
1519 | /* If this is the USE of a return value, we can't change it. */ | |
8ad4c111 | 1520 | if (REG_P (XEXP (x, 0)) && REG_FUNCTION_VALUE_P (XEXP (x, 0))) |
8f8cadbc | 1521 | { |
6a298741 | 1522 | /* Mark the return register as used in an unknown fashion. */ |
8f8cadbc | 1523 | rtx reg = XEXP (x, 0); |
6a298741 | 1524 | unsigned int end_regno = END_REGNO (reg); |
1525 | for (unsigned int regno = REGNO (reg); regno < end_regno; ++regno) | |
1526 | reg_state[regno].use_index = -1; | |
8f8cadbc | 1527 | return; |
1528 | } | |
1529 | break; | |
1530 | ||
1531 | case CLOBBER: | |
8ad4c111 | 1532 | if (REG_P (SET_DEST (x))) |
8f8cadbc | 1533 | { |
1534 | /* No spurious CLOBBERs of pseudo registers may remain. */ | |
876760f6 | 1535 | gcc_assert (REGNO (SET_DEST (x)) < FIRST_PSEUDO_REGISTER); |
8f8cadbc | 1536 | return; |
1537 | } | |
1538 | break; | |
1539 | ||
1540 | case PLUS: | |
1541 | /* We are interested in (plus (reg) (const_int)) . */ | |
8ad4c111 | 1542 | if (!REG_P (XEXP (x, 0)) |
971ba038 | 1543 | || !CONST_INT_P (XEXP (x, 1))) |
8f8cadbc | 1544 | break; |
1545 | offset = XEXP (x, 1); | |
1546 | x = XEXP (x, 0); | |
1547 | /* Fall through. */ | |
1548 | case REG: | |
1549 | { | |
1550 | int regno = REGNO (x); | |
1551 | int use_index; | |
1552 | int nregs; | |
1553 | ||
1554 | /* No spurious USEs of pseudo registers may remain. */ | |
876760f6 | 1555 | gcc_assert (regno < FIRST_PSEUDO_REGISTER); |
8f8cadbc | 1556 | |
0933f1d9 | 1557 | nregs = REG_NREGS (x); |
8f8cadbc | 1558 | |
1559 | /* We can't substitute into multi-hard-reg uses. */ | |
1560 | if (nregs > 1) | |
1561 | { | |
1562 | while (--nregs >= 0) | |
1563 | reg_state[regno + nregs].use_index = -1; | |
1564 | return; | |
1565 | } | |
1566 | ||
727047d0 | 1567 | /* We may be called to update uses in previously seen insns. |
1568 | Don't add uses beyond the last store we saw. */ | |
1569 | if (ruid < reg_state[regno].store_ruid) | |
1570 | return; | |
1571 | ||
8f8cadbc | 1572 | /* If this register is already used in some unknown fashion, we |
1573 | can't do anything. | |
1574 | If we decrement the index from zero to -1, we can't store more | |
1575 | uses, so this register becomes used in an unknown fashion. */ | |
1576 | use_index = --reg_state[regno].use_index; | |
1577 | if (use_index < 0) | |
1578 | return; | |
1579 | ||
d83ccc81 | 1580 | if (use_index == RELOAD_COMBINE_MAX_USES - 1) |
8f8cadbc | 1581 | { |
1582 | /* This is the first use of this register we have seen since we | |
1583 | marked it as dead. */ | |
1584 | reg_state[regno].offset = offset; | |
d83ccc81 | 1585 | reg_state[regno].all_offsets_match = true; |
1586 | reg_state[regno].use_ruid = ruid; | |
8f8cadbc | 1587 | } |
0ead6a7d | 1588 | else |
1589 | { | |
1590 | if (reg_state[regno].use_ruid > ruid) | |
1591 | reg_state[regno].use_ruid = ruid; | |
1592 | ||
1593 | if (! rtx_equal_p (offset, reg_state[regno].offset)) | |
1594 | reg_state[regno].all_offsets_match = false; | |
1595 | } | |
d83ccc81 | 1596 | |
8f8cadbc | 1597 | reg_state[regno].reg_use[use_index].insn = insn; |
d83ccc81 | 1598 | reg_state[regno].reg_use[use_index].ruid = ruid; |
1599 | reg_state[regno].reg_use[use_index].containing_mem = containing_mem; | |
8f8cadbc | 1600 | reg_state[regno].reg_use[use_index].usep = xp; |
1601 | return; | |
1602 | } | |
1603 | ||
d83ccc81 | 1604 | case MEM: |
1605 | containing_mem = x; | |
1606 | break; | |
1607 | ||
8f8cadbc | 1608 | default: |
1609 | break; | |
1610 | } | |
1611 | ||
1612 | /* Recursively process the components of X. */ | |
1613 | fmt = GET_RTX_FORMAT (code); | |
1614 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1615 | { | |
1616 | if (fmt[i] == 'e') | |
d83ccc81 | 1617 | reload_combine_note_use (&XEXP (x, i), insn, ruid, containing_mem); |
8f8cadbc | 1618 | else if (fmt[i] == 'E') |
1619 | { | |
1620 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
d83ccc81 | 1621 | reload_combine_note_use (&XVECEXP (x, i, j), insn, ruid, |
1622 | containing_mem); | |
8f8cadbc | 1623 | } |
1624 | } | |
1625 | } | |
1626 | \f | |
1627 | /* See if we can reduce the cost of a constant by replacing a move | |
1628 | with an add. We track situations in which a register is set to a | |
1629 | constant or to a register plus a constant. */ | |
1630 | /* We cannot do our optimization across labels. Invalidating all the | |
1631 | information about register contents we have would be costly, so we | |
1632 | use move2add_last_label_luid to note where the label is and then | |
1633 | later disable any optimization that would cross it. | |
6132c0d0 | 1634 | reg_offset[n] / reg_base_reg[n] / reg_symbol_ref[n] / reg_mode[n] |
1635 | are only valid if reg_set_luid[n] is greater than | |
b6b86e87 | 1636 | move2add_last_label_luid. |
1637 | For a set that established a new (potential) base register with | |
1638 | non-constant value, we use move2add_luid from the place where the | |
1639 | setting insn is encountered; registers based off that base then | |
1640 | get the same reg_set_luid. Constants all get | |
1641 | move2add_last_label_luid + 1 as their reg_set_luid. */ | |
8f8cadbc | 1642 | static int reg_set_luid[FIRST_PSEUDO_REGISTER]; |
1643 | ||
1644 | /* If reg_base_reg[n] is negative, register n has been set to | |
6132c0d0 | 1645 | reg_offset[n] or reg_symbol_ref[n] + reg_offset[n] in mode reg_mode[n]. |
8f8cadbc | 1646 | If reg_base_reg[n] is non-negative, register n has been set to the |
1647 | sum of reg_offset[n] and the value of register reg_base_reg[n] | |
b6b86e87 | 1648 | before reg_set_luid[n], calculated in mode reg_mode[n] . |
1649 | For multi-hard-register registers, all but the first one are | |
1650 | recorded as BLKmode in reg_mode. Setting reg_mode to VOIDmode | |
1651 | marks it as invalid. */ | |
8f8cadbc | 1652 | static HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER]; |
1653 | static int reg_base_reg[FIRST_PSEUDO_REGISTER]; | |
6132c0d0 | 1654 | static rtx reg_symbol_ref[FIRST_PSEUDO_REGISTER]; |
3754d046 | 1655 | static machine_mode reg_mode[FIRST_PSEUDO_REGISTER]; |
8f8cadbc | 1656 | |
1657 | /* move2add_luid is linearly increased while scanning the instructions | |
1658 | from first to last. It is used to set reg_set_luid in | |
1659 | reload_cse_move2add and move2add_note_store. */ | |
1660 | static int move2add_luid; | |
1661 | ||
1662 | /* move2add_last_label_luid is set whenever a label is found. Labels | |
1663 | invalidate all previously collected reg_offset data. */ | |
1664 | static int move2add_last_label_luid; | |
1665 | ||
1666 | /* ??? We don't know how zero / sign extension is handled, hence we | |
1667 | can't go from a narrower to a wider mode. */ | |
1668 | #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \ | |
1669 | (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \ | |
1670 | || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \ | |
396f2130 | 1671 | && TRULY_NOOP_TRUNCATION_MODES_P (OUTMODE, INMODE))) |
8f8cadbc | 1672 | |
b6b86e87 | 1673 | /* Record that REG is being set to a value with the mode of REG. */ |
1674 | ||
1675 | static void | |
1676 | move2add_record_mode (rtx reg) | |
1677 | { | |
1678 | int regno, nregs; | |
3754d046 | 1679 | machine_mode mode = GET_MODE (reg); |
b6b86e87 | 1680 | |
1681 | if (GET_CODE (reg) == SUBREG) | |
1682 | { | |
1683 | regno = subreg_regno (reg); | |
1684 | nregs = subreg_nregs (reg); | |
1685 | } | |
1686 | else if (REG_P (reg)) | |
1687 | { | |
1688 | regno = REGNO (reg); | |
0933f1d9 | 1689 | nregs = REG_NREGS (reg); |
b6b86e87 | 1690 | } |
1691 | else | |
1692 | gcc_unreachable (); | |
1693 | for (int i = nregs - 1; i > 0; i--) | |
1694 | reg_mode[regno + i] = BLKmode; | |
1695 | reg_mode[regno] = mode; | |
1696 | } | |
1697 | ||
1698 | /* Record that REG is being set to the sum of SYM and OFF. */ | |
1699 | ||
1700 | static void | |
1701 | move2add_record_sym_value (rtx reg, rtx sym, rtx off) | |
1702 | { | |
1703 | int regno = REGNO (reg); | |
1704 | ||
1705 | move2add_record_mode (reg); | |
1706 | reg_set_luid[regno] = move2add_luid; | |
1707 | reg_base_reg[regno] = -1; | |
1708 | reg_symbol_ref[regno] = sym; | |
1709 | reg_offset[regno] = INTVAL (off); | |
1710 | } | |
1711 | ||
1712 | /* Check if REGNO contains a valid value in MODE. */ | |
1713 | ||
1714 | static bool | |
3754d046 | 1715 | move2add_valid_value_p (int regno, machine_mode mode) |
b6b86e87 | 1716 | { |
5bea3269 | 1717 | if (reg_set_luid[regno] <= move2add_last_label_luid) |
b6b86e87 | 1718 | return false; |
1719 | ||
5bea3269 | 1720 | if (mode != reg_mode[regno]) |
1721 | { | |
1722 | if (!MODES_OK_FOR_MOVE2ADD (mode, reg_mode[regno])) | |
1723 | return false; | |
1724 | /* The value loaded into regno in reg_mode[regno] is also valid in | |
1725 | mode after truncation only if (REG:mode regno) is the lowpart of | |
1726 | (REG:reg_mode[regno] regno). Now, for big endian, the starting | |
1727 | regno of the lowpart might be different. */ | |
1728 | int s_off = subreg_lowpart_offset (mode, reg_mode[regno]); | |
1729 | s_off = subreg_regno_offset (regno, reg_mode[regno], s_off, mode); | |
1730 | if (s_off != 0) | |
1731 | /* We could in principle adjust regno, check reg_mode[regno] to be | |
1732 | BLKmode, and return s_off to the caller (vs. -1 for failure), | |
1733 | but we currently have no callers that could make use of this | |
1734 | information. */ | |
1735 | return false; | |
1736 | } | |
1737 | ||
b6b86e87 | 1738 | for (int i = hard_regno_nregs[regno][mode] - 1; i > 0; i--) |
1739 | if (reg_mode[regno + i] != BLKmode) | |
1740 | return false; | |
1741 | return true; | |
1742 | } | |
1743 | ||
6132c0d0 | 1744 | /* This function is called with INSN that sets REG to (SYM + OFF), |
1745 | while REG is known to already have value (SYM + offset). | |
1746 | This function tries to change INSN into an add instruction | |
1747 | (set (REG) (plus (REG) (OFF - offset))) using the known value. | |
d83ccc81 | 1748 | It also updates the information about REG's known value. |
1749 | Return true if we made a change. */ | |
6132c0d0 | 1750 | |
d83ccc81 | 1751 | static bool |
3aeaa53f | 1752 | move2add_use_add2_insn (rtx reg, rtx sym, rtx off, rtx_insn *insn) |
6132c0d0 | 1753 | { |
1754 | rtx pat = PATTERN (insn); | |
1755 | rtx src = SET_SRC (pat); | |
1756 | int regno = REGNO (reg); | |
60141df0 | 1757 | rtx new_src = gen_int_mode (UINTVAL (off) - reg_offset[regno], |
6132c0d0 | 1758 | GET_MODE (reg)); |
1759 | bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); | |
d83ccc81 | 1760 | bool changed = false; |
6132c0d0 | 1761 | |
1762 | /* (set (reg) (plus (reg) (const_int 0))) is not canonical; | |
1763 | use (set (reg) (reg)) instead. | |
1764 | We don't delete this insn, nor do we convert it into a | |
1765 | note, to avoid losing register notes or the return | |
1766 | value flag. jump2 already knows how to get rid of | |
1767 | no-op moves. */ | |
1768 | if (new_src == const0_rtx) | |
1769 | { | |
1770 | /* If the constants are different, this is a | |
1771 | truncation, that, if turned into (set (reg) | |
1772 | (reg)), would be discarded. Maybe we should | |
1773 | try a truncMN pattern? */ | |
1774 | if (INTVAL (off) == reg_offset [regno]) | |
d83ccc81 | 1775 | changed = validate_change (insn, &SET_SRC (pat), reg, 0); |
6132c0d0 | 1776 | } |
c9a03487 | 1777 | else |
6132c0d0 | 1778 | { |
c9a03487 | 1779 | struct full_rtx_costs oldcst, newcst; |
6132c0d0 | 1780 | rtx tem = gen_rtx_PLUS (GET_MODE (reg), reg, new_src); |
c9a03487 | 1781 | |
b72d459f | 1782 | get_full_set_rtx_cost (pat, &oldcst); |
c9a03487 | 1783 | SET_SRC (pat) = tem; |
b72d459f | 1784 | get_full_set_rtx_cost (pat, &newcst); |
c9a03487 | 1785 | SET_SRC (pat) = src; |
1786 | ||
1787 | if (costs_lt_p (&newcst, &oldcst, speed) | |
1788 | && have_add2_insn (reg, new_src)) | |
1789 | changed = validate_change (insn, &SET_SRC (pat), tem, 0); | |
1790 | else if (sym == NULL_RTX && GET_MODE (reg) != BImode) | |
6132c0d0 | 1791 | { |
3754d046 | 1792 | machine_mode narrow_mode; |
c9a03487 | 1793 | for (narrow_mode = GET_CLASS_NARROWEST_MODE (MODE_INT); |
1794 | narrow_mode != VOIDmode | |
1795 | && narrow_mode != GET_MODE (reg); | |
1796 | narrow_mode = GET_MODE_WIDER_MODE (narrow_mode)) | |
6132c0d0 | 1797 | { |
c9a03487 | 1798 | if (have_insn_for (STRICT_LOW_PART, narrow_mode) |
1799 | && ((reg_offset[regno] & ~GET_MODE_MASK (narrow_mode)) | |
1800 | == (INTVAL (off) & ~GET_MODE_MASK (narrow_mode)))) | |
1801 | { | |
17ce39e3 | 1802 | rtx narrow_reg = gen_lowpart_common (narrow_mode, reg); |
c9a03487 | 1803 | rtx narrow_src = gen_int_mode (INTVAL (off), |
1804 | narrow_mode); | |
1805 | rtx new_set | |
d1f9b275 | 1806 | = gen_rtx_SET (gen_rtx_STRICT_LOW_PART (VOIDmode, |
c9a03487 | 1807 | narrow_reg), |
1808 | narrow_src); | |
d4177981 | 1809 | get_full_set_rtx_cost (new_set, &newcst); |
1810 | if (costs_lt_p (&newcst, &oldcst, speed)) | |
1811 | { | |
1812 | changed = validate_change (insn, &PATTERN (insn), | |
1813 | new_set, 0); | |
1814 | if (changed) | |
1815 | break; | |
1816 | } | |
c9a03487 | 1817 | } |
6132c0d0 | 1818 | } |
1819 | } | |
1820 | } | |
b6b86e87 | 1821 | move2add_record_sym_value (reg, sym, off); |
d83ccc81 | 1822 | return changed; |
6132c0d0 | 1823 | } |
1824 | ||
1825 | ||
1826 | /* This function is called with INSN that sets REG to (SYM + OFF), | |
1827 | but REG doesn't have known value (SYM + offset). This function | |
1828 | tries to find another register which is known to already have | |
1829 | value (SYM + offset) and change INSN into an add instruction | |
1830 | (set (REG) (plus (the found register) (OFF - offset))) if such | |
1831 | a register is found. It also updates the information about | |
d83ccc81 | 1832 | REG's known value. |
1833 | Return true iff we made a change. */ | |
6132c0d0 | 1834 | |
d83ccc81 | 1835 | static bool |
3aeaa53f | 1836 | move2add_use_add3_insn (rtx reg, rtx sym, rtx off, rtx_insn *insn) |
6132c0d0 | 1837 | { |
1838 | rtx pat = PATTERN (insn); | |
1839 | rtx src = SET_SRC (pat); | |
1840 | int regno = REGNO (reg); | |
c2130a4b | 1841 | int min_regno = 0; |
6132c0d0 | 1842 | bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); |
1843 | int i; | |
d83ccc81 | 1844 | bool changed = false; |
c9a03487 | 1845 | struct full_rtx_costs oldcst, newcst, mincst; |
1846 | rtx plus_expr; | |
1847 | ||
1848 | init_costs_to_max (&mincst); | |
b72d459f | 1849 | get_full_set_rtx_cost (pat, &oldcst); |
c9a03487 | 1850 | |
1851 | plus_expr = gen_rtx_PLUS (GET_MODE (reg), reg, const0_rtx); | |
1852 | SET_SRC (pat) = plus_expr; | |
6132c0d0 | 1853 | |
1854 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
b6b86e87 | 1855 | if (move2add_valid_value_p (i, GET_MODE (reg)) |
6132c0d0 | 1856 | && reg_base_reg[i] < 0 |
1857 | && reg_symbol_ref[i] != NULL_RTX | |
1858 | && rtx_equal_p (sym, reg_symbol_ref[i])) | |
1859 | { | |
60141df0 | 1860 | rtx new_src = gen_int_mode (UINTVAL (off) - reg_offset[i], |
6132c0d0 | 1861 | GET_MODE (reg)); |
1862 | /* (set (reg) (plus (reg) (const_int 0))) is not canonical; | |
1863 | use (set (reg) (reg)) instead. | |
1864 | We don't delete this insn, nor do we convert it into a | |
1865 | note, to avoid losing register notes or the return | |
1866 | value flag. jump2 already knows how to get rid of | |
1867 | no-op moves. */ | |
1868 | if (new_src == const0_rtx) | |
1869 | { | |
c9a03487 | 1870 | init_costs_to_zero (&mincst); |
6132c0d0 | 1871 | min_regno = i; |
1872 | break; | |
1873 | } | |
1874 | else | |
1875 | { | |
c9a03487 | 1876 | XEXP (plus_expr, 1) = new_src; |
b72d459f | 1877 | get_full_set_rtx_cost (pat, &newcst); |
c9a03487 | 1878 | |
1879 | if (costs_lt_p (&newcst, &mincst, speed)) | |
6132c0d0 | 1880 | { |
c9a03487 | 1881 | mincst = newcst; |
6132c0d0 | 1882 | min_regno = i; |
1883 | } | |
1884 | } | |
1885 | } | |
c9a03487 | 1886 | SET_SRC (pat) = src; |
6132c0d0 | 1887 | |
c9a03487 | 1888 | if (costs_lt_p (&mincst, &oldcst, speed)) |
6132c0d0 | 1889 | { |
1890 | rtx tem; | |
1891 | ||
1892 | tem = gen_rtx_REG (GET_MODE (reg), min_regno); | |
1893 | if (i != min_regno) | |
1894 | { | |
60141df0 | 1895 | rtx new_src = gen_int_mode (UINTVAL (off) - reg_offset[min_regno], |
6132c0d0 | 1896 | GET_MODE (reg)); |
1897 | tem = gen_rtx_PLUS (GET_MODE (reg), tem, new_src); | |
1898 | } | |
d83ccc81 | 1899 | if (validate_change (insn, &SET_SRC (pat), tem, 0)) |
1900 | changed = true; | |
6132c0d0 | 1901 | } |
1902 | reg_set_luid[regno] = move2add_luid; | |
b6b86e87 | 1903 | move2add_record_sym_value (reg, sym, off); |
d83ccc81 | 1904 | return changed; |
6132c0d0 | 1905 | } |
1906 | ||
d83ccc81 | 1907 | /* Convert move insns with constant inputs to additions if they are cheaper. |
1908 | Return true if any changes were made. */ | |
1909 | static bool | |
3aeaa53f | 1910 | reload_cse_move2add (rtx_insn *first) |
8f8cadbc | 1911 | { |
1912 | int i; | |
3aeaa53f | 1913 | rtx_insn *insn; |
d83ccc81 | 1914 | bool changed = false; |
8f8cadbc | 1915 | |
1916 | for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--) | |
6132c0d0 | 1917 | { |
1918 | reg_set_luid[i] = 0; | |
1919 | reg_offset[i] = 0; | |
1920 | reg_base_reg[i] = 0; | |
1921 | reg_symbol_ref[i] = NULL_RTX; | |
1922 | reg_mode[i] = VOIDmode; | |
1923 | } | |
8f8cadbc | 1924 | |
1925 | move2add_last_label_luid = 0; | |
1926 | move2add_luid = 2; | |
1927 | for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++) | |
1928 | { | |
1929 | rtx pat, note; | |
1930 | ||
6d7dc5b9 | 1931 | if (LABEL_P (insn)) |
8f8cadbc | 1932 | { |
1933 | move2add_last_label_luid = move2add_luid; | |
1934 | /* We're going to increment move2add_luid twice after a | |
1935 | label, so that we can use move2add_last_label_luid + 1 as | |
1936 | the luid for constants. */ | |
1937 | move2add_luid++; | |
1938 | continue; | |
1939 | } | |
1940 | if (! INSN_P (insn)) | |
1941 | continue; | |
1942 | pat = PATTERN (insn); | |
1943 | /* For simplicity, we only perform this optimization on | |
1944 | straightforward SETs. */ | |
1945 | if (GET_CODE (pat) == SET | |
8ad4c111 | 1946 | && REG_P (SET_DEST (pat))) |
8f8cadbc | 1947 | { |
1948 | rtx reg = SET_DEST (pat); | |
1949 | int regno = REGNO (reg); | |
1950 | rtx src = SET_SRC (pat); | |
1951 | ||
1952 | /* Check if we have valid information on the contents of this | |
1953 | register in the mode of REG. */ | |
b6b86e87 | 1954 | if (move2add_valid_value_p (regno, GET_MODE (reg)) |
3072d30e | 1955 | && dbg_cnt (cse2_move2add)) |
8f8cadbc | 1956 | { |
1957 | /* Try to transform (set (REGX) (CONST_INT A)) | |
1958 | ... | |
1959 | (set (REGX) (CONST_INT B)) | |
1960 | to | |
1961 | (set (REGX) (CONST_INT A)) | |
1962 | ... | |
1963 | (set (REGX) (plus (REGX) (CONST_INT B-A))) | |
1964 | or | |
1965 | (set (REGX) (CONST_INT A)) | |
1966 | ... | |
1967 | (set (STRICT_LOW_PART (REGX)) (CONST_INT B)) | |
1968 | */ | |
1969 | ||
6132c0d0 | 1970 | if (CONST_INT_P (src) |
1971 | && reg_base_reg[regno] < 0 | |
1972 | && reg_symbol_ref[regno] == NULL_RTX) | |
8f8cadbc | 1973 | { |
d83ccc81 | 1974 | changed |= move2add_use_add2_insn (reg, NULL_RTX, src, insn); |
8f8cadbc | 1975 | continue; |
1976 | } | |
1977 | ||
1978 | /* Try to transform (set (REGX) (REGY)) | |
1979 | (set (REGX) (PLUS (REGX) (CONST_INT A))) | |
1980 | ... | |
1981 | (set (REGX) (REGY)) | |
1982 | (set (REGX) (PLUS (REGX) (CONST_INT B))) | |
1983 | to | |
1984 | (set (REGX) (REGY)) | |
1985 | (set (REGX) (PLUS (REGX) (CONST_INT A))) | |
1986 | ... | |
1987 | (set (REGX) (plus (REGX) (CONST_INT B-A))) */ | |
8ad4c111 | 1988 | else if (REG_P (src) |
8f8cadbc | 1989 | && reg_set_luid[regno] == reg_set_luid[REGNO (src)] |
1990 | && reg_base_reg[regno] == reg_base_reg[REGNO (src)] | |
b6b86e87 | 1991 | && move2add_valid_value_p (REGNO (src), GET_MODE (reg))) |
8f8cadbc | 1992 | { |
3aeaa53f | 1993 | rtx_insn *next = next_nonnote_nondebug_insn (insn); |
8f8cadbc | 1994 | rtx set = NULL_RTX; |
1995 | if (next) | |
1996 | set = single_set (next); | |
1997 | if (set | |
1998 | && SET_DEST (set) == reg | |
1999 | && GET_CODE (SET_SRC (set)) == PLUS | |
2000 | && XEXP (SET_SRC (set), 0) == reg | |
971ba038 | 2001 | && CONST_INT_P (XEXP (SET_SRC (set), 1))) |
8f8cadbc | 2002 | { |
2003 | rtx src3 = XEXP (SET_SRC (set), 1); | |
60141df0 | 2004 | unsigned HOST_WIDE_INT added_offset = UINTVAL (src3); |
8f8cadbc | 2005 | HOST_WIDE_INT base_offset = reg_offset[REGNO (src)]; |
2006 | HOST_WIDE_INT regno_offset = reg_offset[regno]; | |
2007 | rtx new_src = | |
69e41517 | 2008 | gen_int_mode (added_offset |
2009 | + base_offset | |
2010 | - regno_offset, | |
2011 | GET_MODE (reg)); | |
f529eb25 | 2012 | bool success = false; |
2013 | bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); | |
8f8cadbc | 2014 | |
2015 | if (new_src == const0_rtx) | |
2016 | /* See above why we create (set (reg) (reg)) here. */ | |
2017 | success | |
2018 | = validate_change (next, &SET_SRC (set), reg, 0); | |
c9a03487 | 2019 | else |
8f8cadbc | 2020 | { |
c9a03487 | 2021 | rtx old_src = SET_SRC (set); |
2022 | struct full_rtx_costs oldcst, newcst; | |
2023 | rtx tem = gen_rtx_PLUS (GET_MODE (reg), reg, new_src); | |
2024 | ||
b72d459f | 2025 | get_full_set_rtx_cost (set, &oldcst); |
c9a03487 | 2026 | SET_SRC (set) = tem; |
7013e87c | 2027 | get_full_set_src_cost (tem, &newcst); |
c9a03487 | 2028 | SET_SRC (set) = old_src; |
2029 | costs_add_n_insns (&oldcst, 1); | |
2030 | ||
2031 | if (costs_lt_p (&newcst, &oldcst, speed) | |
2032 | && have_add2_insn (reg, new_src)) | |
2033 | { | |
d1f9b275 | 2034 | rtx newpat = gen_rtx_SET (reg, tem); |
c9a03487 | 2035 | success |
2036 | = validate_change (next, &PATTERN (next), | |
2037 | newpat, 0); | |
2038 | } | |
8f8cadbc | 2039 | } |
2040 | if (success) | |
2041 | delete_insn (insn); | |
d83ccc81 | 2042 | changed |= success; |
8f8cadbc | 2043 | insn = next; |
b6b86e87 | 2044 | move2add_record_mode (reg); |
2045 | reg_offset[regno] | |
2046 | = trunc_int_for_mode (added_offset + base_offset, | |
2047 | GET_MODE (reg)); | |
8f8cadbc | 2048 | continue; |
2049 | } | |
2050 | } | |
2051 | } | |
6132c0d0 | 2052 | |
2053 | /* Try to transform | |
2054 | (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A)))) | |
2055 | ... | |
2056 | (set (REGY) (CONST (PLUS (SYMBOL_REF) (CONST_INT B)))) | |
2057 | to | |
2058 | (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A)))) | |
2059 | ... | |
2060 | (set (REGY) (CONST (PLUS (REGX) (CONST_INT B-A)))) */ | |
2061 | if ((GET_CODE (src) == SYMBOL_REF | |
2062 | || (GET_CODE (src) == CONST | |
2063 | && GET_CODE (XEXP (src, 0)) == PLUS | |
2064 | && GET_CODE (XEXP (XEXP (src, 0), 0)) == SYMBOL_REF | |
2065 | && CONST_INT_P (XEXP (XEXP (src, 0), 1)))) | |
2066 | && dbg_cnt (cse2_move2add)) | |
2067 | { | |
2068 | rtx sym, off; | |
2069 | ||
2070 | if (GET_CODE (src) == SYMBOL_REF) | |
2071 | { | |
2072 | sym = src; | |
2073 | off = const0_rtx; | |
2074 | } | |
2075 | else | |
2076 | { | |
2077 | sym = XEXP (XEXP (src, 0), 0); | |
2078 | off = XEXP (XEXP (src, 0), 1); | |
2079 | } | |
2080 | ||
2081 | /* If the reg already contains the value which is sum of | |
2082 | sym and some constant value, we can use an add2 insn. */ | |
b6b86e87 | 2083 | if (move2add_valid_value_p (regno, GET_MODE (reg)) |
6132c0d0 | 2084 | && reg_base_reg[regno] < 0 |
2085 | && reg_symbol_ref[regno] != NULL_RTX | |
2086 | && rtx_equal_p (sym, reg_symbol_ref[regno])) | |
d83ccc81 | 2087 | changed |= move2add_use_add2_insn (reg, sym, off, insn); |
6132c0d0 | 2088 | |
2089 | /* Otherwise, we have to find a register whose value is sum | |
2090 | of sym and some constant value. */ | |
2091 | else | |
d83ccc81 | 2092 | changed |= move2add_use_add3_insn (reg, sym, off, insn); |
6132c0d0 | 2093 | |
2094 | continue; | |
2095 | } | |
8f8cadbc | 2096 | } |
2097 | ||
2098 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
2099 | { | |
2100 | if (REG_NOTE_KIND (note) == REG_INC | |
8ad4c111 | 2101 | && REG_P (XEXP (note, 0))) |
8f8cadbc | 2102 | { |
2103 | /* Reset the information about this register. */ | |
2104 | int regno = REGNO (XEXP (note, 0)); | |
2105 | if (regno < FIRST_PSEUDO_REGISTER) | |
b6b86e87 | 2106 | { |
2107 | move2add_record_mode (XEXP (note, 0)); | |
2108 | reg_mode[regno] = VOIDmode; | |
2109 | } | |
8f8cadbc | 2110 | } |
2111 | } | |
6132c0d0 | 2112 | note_stores (PATTERN (insn), move2add_note_store, insn); |
8f8cadbc | 2113 | |
2114 | /* If INSN is a conditional branch, we try to extract an | |
2115 | implicit set out of it. */ | |
f222bc3b | 2116 | if (any_condjump_p (insn)) |
8f8cadbc | 2117 | { |
2118 | rtx cnd = fis_get_condition (insn); | |
2119 | ||
2120 | if (cnd != NULL_RTX | |
2121 | && GET_CODE (cnd) == NE | |
8ad4c111 | 2122 | && REG_P (XEXP (cnd, 0)) |
f222bc3b | 2123 | && !reg_set_p (XEXP (cnd, 0), insn) |
8f8cadbc | 2124 | /* The following two checks, which are also in |
2125 | move2add_note_store, are intended to reduce the | |
2126 | number of calls to gen_rtx_SET to avoid memory | |
2127 | allocation if possible. */ | |
2128 | && SCALAR_INT_MODE_P (GET_MODE (XEXP (cnd, 0))) | |
0933f1d9 | 2129 | && REG_NREGS (XEXP (cnd, 0)) == 1 |
971ba038 | 2130 | && CONST_INT_P (XEXP (cnd, 1))) |
8f8cadbc | 2131 | { |
2132 | rtx implicit_set = | |
d1f9b275 | 2133 | gen_rtx_SET (XEXP (cnd, 0), XEXP (cnd, 1)); |
6132c0d0 | 2134 | move2add_note_store (SET_DEST (implicit_set), implicit_set, insn); |
8f8cadbc | 2135 | } |
2136 | } | |
2137 | ||
2138 | /* If this is a CALL_INSN, all call used registers are stored with | |
2139 | unknown values. */ | |
6d7dc5b9 | 2140 | if (CALL_P (insn)) |
8f8cadbc | 2141 | { |
2142 | for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--) | |
2143 | { | |
2144 | if (call_used_regs[i]) | |
2145 | /* Reset the information about this register. */ | |
b6b86e87 | 2146 | reg_mode[i] = VOIDmode; |
8f8cadbc | 2147 | } |
2148 | } | |
2149 | } | |
d83ccc81 | 2150 | return changed; |
8f8cadbc | 2151 | } |
2152 | ||
6132c0d0 | 2153 | /* SET is a SET or CLOBBER that sets DST. DATA is the insn which |
2154 | contains SET. | |
8f8cadbc | 2155 | Update reg_set_luid, reg_offset and reg_base_reg accordingly. |
2156 | Called from reload_cse_move2add via note_stores. */ | |
2157 | ||
2158 | static void | |
6132c0d0 | 2159 | move2add_note_store (rtx dst, const_rtx set, void *data) |
8f8cadbc | 2160 | { |
3aeaa53f | 2161 | rtx_insn *insn = (rtx_insn *) data; |
8f8cadbc | 2162 | unsigned int regno = 0; |
3754d046 | 2163 | machine_mode mode = GET_MODE (dst); |
8f8cadbc | 2164 | |
8f8cadbc | 2165 | /* Some targets do argument pushes without adding REG_INC notes. */ |
2166 | ||
e16ceb8e | 2167 | if (MEM_P (dst)) |
8f8cadbc | 2168 | { |
2169 | dst = XEXP (dst, 0); | |
2170 | if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_INC | |
2171 | || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC) | |
b6b86e87 | 2172 | reg_mode[REGNO (XEXP (dst, 0))] = VOIDmode; |
8f8cadbc | 2173 | return; |
2174 | } | |
8f8cadbc | 2175 | |
b6b86e87 | 2176 | if (GET_CODE (dst) == SUBREG) |
2177 | regno = subreg_regno (dst); | |
2178 | else if (REG_P (dst)) | |
2179 | regno = REGNO (dst); | |
2180 | else | |
2181 | return; | |
8f8cadbc | 2182 | |
b6b86e87 | 2183 | if (SCALAR_INT_MODE_P (mode) |
2184 | && GET_CODE (set) == SET) | |
6132c0d0 | 2185 | { |
2186 | rtx note, sym = NULL_RTX; | |
b6b86e87 | 2187 | rtx off; |
6132c0d0 | 2188 | |
2189 | note = find_reg_equal_equiv_note (insn); | |
2190 | if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF) | |
2191 | { | |
2192 | sym = XEXP (note, 0); | |
b6b86e87 | 2193 | off = const0_rtx; |
6132c0d0 | 2194 | } |
2195 | else if (note && GET_CODE (XEXP (note, 0)) == CONST | |
2196 | && GET_CODE (XEXP (XEXP (note, 0), 0)) == PLUS | |
2197 | && GET_CODE (XEXP (XEXP (XEXP (note, 0), 0), 0)) == SYMBOL_REF | |
2198 | && CONST_INT_P (XEXP (XEXP (XEXP (note, 0), 0), 1))) | |
2199 | { | |
2200 | sym = XEXP (XEXP (XEXP (note, 0), 0), 0); | |
b6b86e87 | 2201 | off = XEXP (XEXP (XEXP (note, 0), 0), 1); |
6132c0d0 | 2202 | } |
2203 | ||
2204 | if (sym != NULL_RTX) | |
2205 | { | |
b6b86e87 | 2206 | move2add_record_sym_value (dst, sym, off); |
6132c0d0 | 2207 | return; |
2208 | } | |
2209 | } | |
2210 | ||
b6b86e87 | 2211 | if (SCALAR_INT_MODE_P (mode) |
2212 | && GET_CODE (set) == SET | |
8f8cadbc | 2213 | && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT |
8f8cadbc | 2214 | && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART) |
2215 | { | |
2216 | rtx src = SET_SRC (set); | |
2217 | rtx base_reg; | |
60141df0 | 2218 | unsigned HOST_WIDE_INT offset; |
8f8cadbc | 2219 | int base_regno; |
8f8cadbc | 2220 | |
2221 | switch (GET_CODE (src)) | |
2222 | { | |
2223 | case PLUS: | |
8ad4c111 | 2224 | if (REG_P (XEXP (src, 0))) |
8f8cadbc | 2225 | { |
2226 | base_reg = XEXP (src, 0); | |
2227 | ||
971ba038 | 2228 | if (CONST_INT_P (XEXP (src, 1))) |
60141df0 | 2229 | offset = UINTVAL (XEXP (src, 1)); |
8ad4c111 | 2230 | else if (REG_P (XEXP (src, 1)) |
b6b86e87 | 2231 | && move2add_valid_value_p (REGNO (XEXP (src, 1)), mode)) |
8f8cadbc | 2232 | { |
c389f975 | 2233 | if (reg_base_reg[REGNO (XEXP (src, 1))] < 0 |
2234 | && reg_symbol_ref[REGNO (XEXP (src, 1))] == NULL_RTX) | |
8f8cadbc | 2235 | offset = reg_offset[REGNO (XEXP (src, 1))]; |
2236 | /* Maybe the first register is known to be a | |
2237 | constant. */ | |
b6b86e87 | 2238 | else if (move2add_valid_value_p (REGNO (base_reg), mode) |
c389f975 | 2239 | && reg_base_reg[REGNO (base_reg)] < 0 |
2240 | && reg_symbol_ref[REGNO (base_reg)] == NULL_RTX) | |
8f8cadbc | 2241 | { |
2242 | offset = reg_offset[REGNO (base_reg)]; | |
2243 | base_reg = XEXP (src, 1); | |
2244 | } | |
2245 | else | |
2246 | goto invalidate; | |
2247 | } | |
2248 | else | |
2249 | goto invalidate; | |
2250 | ||
2251 | break; | |
2252 | } | |
2253 | ||
2254 | goto invalidate; | |
2255 | ||
2256 | case REG: | |
2257 | base_reg = src; | |
2258 | offset = 0; | |
2259 | break; | |
2260 | ||
2261 | case CONST_INT: | |
2262 | /* Start tracking the register as a constant. */ | |
2263 | reg_base_reg[regno] = -1; | |
6132c0d0 | 2264 | reg_symbol_ref[regno] = NULL_RTX; |
8f8cadbc | 2265 | reg_offset[regno] = INTVAL (SET_SRC (set)); |
2266 | /* We assign the same luid to all registers set to constants. */ | |
2267 | reg_set_luid[regno] = move2add_last_label_luid + 1; | |
b6b86e87 | 2268 | move2add_record_mode (dst); |
8f8cadbc | 2269 | return; |
2270 | ||
2271 | default: | |
b6b86e87 | 2272 | goto invalidate; |
8f8cadbc | 2273 | } |
2274 | ||
2275 | base_regno = REGNO (base_reg); | |
2276 | /* If information about the base register is not valid, set it | |
2277 | up as a new base register, pretending its value is known | |
2278 | starting from the current insn. */ | |
b6b86e87 | 2279 | if (!move2add_valid_value_p (base_regno, mode)) |
8f8cadbc | 2280 | { |
2281 | reg_base_reg[base_regno] = base_regno; | |
6132c0d0 | 2282 | reg_symbol_ref[base_regno] = NULL_RTX; |
8f8cadbc | 2283 | reg_offset[base_regno] = 0; |
2284 | reg_set_luid[base_regno] = move2add_luid; | |
b6b86e87 | 2285 | gcc_assert (GET_MODE (base_reg) == mode); |
2286 | move2add_record_mode (base_reg); | |
8f8cadbc | 2287 | } |
8f8cadbc | 2288 | |
2289 | /* Copy base information from our base register. */ | |
2290 | reg_set_luid[regno] = reg_set_luid[base_regno]; | |
2291 | reg_base_reg[regno] = reg_base_reg[base_regno]; | |
6132c0d0 | 2292 | reg_symbol_ref[regno] = reg_symbol_ref[base_regno]; |
8f8cadbc | 2293 | |
2294 | /* Compute the sum of the offsets or constants. */ | |
b6b86e87 | 2295 | reg_offset[regno] |
2296 | = trunc_int_for_mode (offset + reg_offset[base_regno], mode); | |
2297 | ||
2298 | move2add_record_mode (dst); | |
8f8cadbc | 2299 | } |
2300 | else | |
2301 | { | |
b6b86e87 | 2302 | invalidate: |
2303 | /* Invalidate the contents of the register. */ | |
2304 | move2add_record_mode (dst); | |
2305 | reg_mode[regno] = VOIDmode; | |
8f8cadbc | 2306 | } |
2307 | } | |
77fce4cd | 2308 | \f |
cbe8bda8 | 2309 | namespace { |
2310 | ||
2311 | const pass_data pass_data_postreload_cse = | |
77fce4cd | 2312 | { |
cbe8bda8 | 2313 | RTL_PASS, /* type */ |
2314 | "postreload", /* name */ | |
2315 | OPTGROUP_NONE, /* optinfo_flags */ | |
cbe8bda8 | 2316 | TV_RELOAD_CSE_REGS, /* tv_id */ |
2317 | 0, /* properties_required */ | |
2318 | 0, /* properties_provided */ | |
2319 | 0, /* properties_destroyed */ | |
2320 | 0, /* todo_flags_start */ | |
8b88439e | 2321 | TODO_df_finish, /* todo_flags_finish */ |
77fce4cd | 2322 | }; |
cbe8bda8 | 2323 | |
2324 | class pass_postreload_cse : public rtl_opt_pass | |
2325 | { | |
2326 | public: | |
9af5ce0c | 2327 | pass_postreload_cse (gcc::context *ctxt) |
2328 | : rtl_opt_pass (pass_data_postreload_cse, ctxt) | |
cbe8bda8 | 2329 | {} |
2330 | ||
2331 | /* opt_pass methods: */ | |
31315c24 | 2332 | virtual bool gate (function *) { return (optimize > 0 && reload_completed); } |
2333 | ||
65b0537f | 2334 | virtual unsigned int execute (function *); |
cbe8bda8 | 2335 | |
2336 | }; // class pass_postreload_cse | |
2337 | ||
65b0537f | 2338 | unsigned int |
2339 | pass_postreload_cse::execute (function *fun) | |
2340 | { | |
2341 | if (!dbg_cnt (postreload_cse)) | |
2342 | return 0; | |
2343 | ||
2344 | /* Do a very simple CSE pass over just the hard registers. */ | |
2345 | reload_cse_regs (get_insns ()); | |
2346 | /* Reload_cse_regs can eliminate potentially-trapping MEMs. | |
2347 | Remove any EH edges associated with them. */ | |
2348 | if (fun->can_throw_non_call_exceptions | |
2349 | && purge_all_dead_edges ()) | |
2350 | cleanup_cfg (0); | |
2351 | ||
2352 | return 0; | |
2353 | } | |
2354 | ||
cbe8bda8 | 2355 | } // anon namespace |
2356 | ||
2357 | rtl_opt_pass * | |
2358 | make_pass_postreload_cse (gcc::context *ctxt) | |
2359 | { | |
2360 | return new pass_postreload_cse (ctxt); | |
2361 | } |