]>
Commit | Line | Data |
---|---|---|
2055cea7 | 1 | /* Subroutines used by or related to instruction recognition. |
1f06ee8d | 2 | Copyright (C) 1987, 1988, 91-98, 1999 Free Software Foundation, Inc. |
2055cea7 RK |
3 | |
4 | This file is part of GNU CC. | |
5 | ||
6 | GNU CC is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GNU CC is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GNU CC; see the file COPYING. If not, write to | |
e99215a3 RK |
18 | the Free Software Foundation, 59 Temple Place - Suite 330, |
19 | Boston, MA 02111-1307, USA. */ | |
2055cea7 RK |
20 | |
21 | ||
22 | #include "config.h" | |
670ee920 | 23 | #include "system.h" |
38a448ca | 24 | #include "rtl.h" |
2055cea7 RK |
25 | #include "insn-config.h" |
26 | #include "insn-attr.h" | |
27 | #include "insn-flags.h" | |
28 | #include "insn-codes.h" | |
29 | #include "recog.h" | |
30 | #include "regs.h" | |
31 | #include "hard-reg-set.h" | |
49ad7cfa | 32 | #include "function.h" |
2055cea7 RK |
33 | #include "flags.h" |
34 | #include "real.h" | |
7f7f8214 | 35 | #include "toplev.h" |
ca545bb5 | 36 | #include "basic-block.h" |
ede7cd44 RH |
37 | #include "output.h" |
38 | #include "resource.h" | |
2055cea7 RK |
39 | |
40 | #ifndef STACK_PUSH_CODE | |
41 | #ifdef STACK_GROWS_DOWNWARD | |
42 | #define STACK_PUSH_CODE PRE_DEC | |
43 | #else | |
44 | #define STACK_PUSH_CODE PRE_INC | |
45 | #endif | |
46 | #endif | |
47 | ||
6fbe9bd8 RH |
48 | #ifndef STACK_POP_CODE |
49 | #ifdef STACK_GROWS_DOWNWARD | |
50 | #define STACK_POP_CODE POST_INC | |
51 | #else | |
52 | #define STACK_POP_CODE POST_DEC | |
53 | #endif | |
54 | #endif | |
55 | ||
61719ba7 BS |
56 | static void validate_replace_rtx_1 PROTO((rtx *, rtx, rtx, rtx)); |
57 | static rtx *find_single_use_1 PROTO((rtx, rtx *)); | |
58 | static rtx *find_constant_term_loc PROTO((rtx *)); | |
59 | static int insn_invalid_p PROTO((rtx)); | |
2055cea7 RK |
60 | |
61 | /* Nonzero means allow operands to be volatile. | |
62 | This should be 0 if you are generating rtl, such as if you are calling | |
63 | the functions in optabs.c and expmed.c (most of the time). | |
64 | This should be 1 if all valid insns need to be recognized, | |
65 | such as in regclass.c and final.c and reload.c. | |
66 | ||
67 | init_recog and init_recog_no_volatile are responsible for setting this. */ | |
68 | ||
69 | int volatile_ok; | |
70 | ||
1ccbefce | 71 | struct recog_data recog_data; |
0a578fee | 72 | |
f62a15e3 BS |
73 | /* Contains a vector of operand_alternative structures for every operand. |
74 | Set up by preprocess_constraints. */ | |
75 | struct operand_alternative recog_op_alt[MAX_RECOG_OPERANDS][MAX_RECOG_ALTERNATIVES]; | |
76 | ||
2055cea7 RK |
77 | /* On return from `constrain_operands', indicate which alternative |
78 | was satisfied. */ | |
79 | ||
80 | int which_alternative; | |
81 | ||
82 | /* Nonzero after end of reload pass. | |
83 | Set to 1 or 0 by toplev.c. | |
84 | Controls the significance of (SUBREG (MEM)). */ | |
85 | ||
86 | int reload_completed; | |
87 | ||
88 | /* Initialize data used by the function `recog'. | |
89 | This must be called once in the compilation of a function | |
90 | before any insn recognition may be done in the function. */ | |
91 | ||
92 | void | |
93 | init_recog_no_volatile () | |
94 | { | |
95 | volatile_ok = 0; | |
96 | } | |
97 | ||
e0069e43 | 98 | void |
2055cea7 RK |
99 | init_recog () |
100 | { | |
101 | volatile_ok = 1; | |
102 | } | |
103 | ||
104 | /* Try recognizing the instruction INSN, | |
105 | and return the code number that results. | |
9faa82d8 | 106 | Remember the code so that repeated calls do not |
2055cea7 RK |
107 | need to spend the time for actual rerecognition. |
108 | ||
109 | This function is the normal interface to instruction recognition. | |
110 | The automatically-generated function `recog' is normally called | |
111 | through this one. (The only exception is in combine.c.) */ | |
112 | ||
113 | int | |
114 | recog_memoized (insn) | |
115 | rtx insn; | |
116 | { | |
117 | if (INSN_CODE (insn) < 0) | |
9e4223f2 | 118 | INSN_CODE (insn) = recog (PATTERN (insn), insn, NULL_PTR); |
2055cea7 RK |
119 | return INSN_CODE (insn); |
120 | } | |
121 | \f | |
122 | /* Check that X is an insn-body for an `asm' with operands | |
123 | and that the operands mentioned in it are legitimate. */ | |
124 | ||
125 | int | |
126 | check_asm_operands (x) | |
127 | rtx x; | |
128 | { | |
1f06ee8d | 129 | int noperands; |
2055cea7 | 130 | rtx *operands; |
9b3142b3 | 131 | const char **constraints; |
2055cea7 RK |
132 | int i; |
133 | ||
1f06ee8d RH |
134 | /* Post-reload, be more strict with things. */ |
135 | if (reload_completed) | |
136 | { | |
137 | /* ??? Doh! We've not got the wrapping insn. Cook one up. */ | |
138 | extract_insn (make_insn_raw (x)); | |
139 | constrain_operands (1); | |
140 | return which_alternative >= 0; | |
141 | } | |
142 | ||
143 | noperands = asm_noperands (x); | |
2055cea7 RK |
144 | if (noperands < 0) |
145 | return 0; | |
146 | if (noperands == 0) | |
147 | return 1; | |
148 | ||
149 | operands = (rtx *) alloca (noperands * sizeof (rtx)); | |
9b3142b3 | 150 | constraints = (const char **) alloca (noperands * sizeof (char *)); |
1f06ee8d RH |
151 | |
152 | decode_asm_operands (x, operands, NULL_PTR, constraints, NULL_PTR); | |
2055cea7 RK |
153 | |
154 | for (i = 0; i < noperands; i++) | |
1f06ee8d | 155 | { |
9b3142b3 | 156 | const char *c = constraints[i]; |
1afbe1c4 RH |
157 | if (c[0] == '%') |
158 | c++; | |
159 | if (ISDIGIT ((unsigned char)c[0]) && c[1] == '\0') | |
1f06ee8d RH |
160 | c = constraints[c[0] - '0']; |
161 | ||
162 | if (! asm_operand_ok (operands[i], c)) | |
163 | return 0; | |
164 | } | |
2055cea7 RK |
165 | |
166 | return 1; | |
167 | } | |
168 | \f | |
41a972a9 | 169 | /* Static data for the next two routines. */ |
2055cea7 | 170 | |
41a972a9 MM |
171 | typedef struct change_t |
172 | { | |
173 | rtx object; | |
174 | int old_code; | |
175 | rtx *loc; | |
176 | rtx old; | |
177 | } change_t; | |
2055cea7 | 178 | |
41a972a9 MM |
179 | static change_t *changes; |
180 | static int changes_allocated; | |
2055cea7 RK |
181 | |
182 | static int num_changes = 0; | |
183 | ||
184 | /* Validate a proposed change to OBJECT. LOC is the location in the rtl for | |
185 | at which NEW will be placed. If OBJECT is zero, no validation is done, | |
186 | the change is simply made. | |
187 | ||
188 | Two types of objects are supported: If OBJECT is a MEM, memory_address_p | |
189 | will be called with the address and mode as parameters. If OBJECT is | |
190 | an INSN, CALL_INSN, or JUMP_INSN, the insn will be re-recognized with | |
191 | the change in place. | |
192 | ||
193 | IN_GROUP is non-zero if this is part of a group of changes that must be | |
194 | performed as a group. In that case, the changes will be stored. The | |
195 | function `apply_change_group' will validate and apply the changes. | |
196 | ||
197 | If IN_GROUP is zero, this is a single change. Try to recognize the insn | |
198 | or validate the memory reference with the change applied. If the result | |
199 | is not valid for the machine, suppress the change and return zero. | |
200 | Otherwise, perform the change and return 1. */ | |
201 | ||
202 | int | |
203 | validate_change (object, loc, new, in_group) | |
204 | rtx object; | |
205 | rtx *loc; | |
206 | rtx new; | |
207 | int in_group; | |
208 | { | |
209 | rtx old = *loc; | |
210 | ||
211 | if (old == new || rtx_equal_p (old, new)) | |
212 | return 1; | |
213 | ||
41a972a9 | 214 | if (in_group == 0 && num_changes != 0) |
2055cea7 RK |
215 | abort (); |
216 | ||
217 | *loc = new; | |
218 | ||
219 | /* Save the information describing this change. */ | |
41a972a9 MM |
220 | if (num_changes >= changes_allocated) |
221 | { | |
222 | if (changes_allocated == 0) | |
223 | /* This value allows for repeated substitutions inside complex | |
224 | indexed addresses, or changes in up to 5 insns. */ | |
225 | changes_allocated = MAX_RECOG_OPERANDS * 5; | |
226 | else | |
227 | changes_allocated *= 2; | |
228 | ||
229 | changes = | |
230 | (change_t*) xrealloc (changes, | |
231 | sizeof (change_t) * changes_allocated); | |
232 | } | |
233 | ||
234 | changes[num_changes].object = object; | |
235 | changes[num_changes].loc = loc; | |
236 | changes[num_changes].old = old; | |
2055cea7 RK |
237 | |
238 | if (object && GET_CODE (object) != MEM) | |
239 | { | |
240 | /* Set INSN_CODE to force rerecognition of insn. Save old code in | |
241 | case invalid. */ | |
41a972a9 | 242 | changes[num_changes].old_code = INSN_CODE (object); |
2055cea7 RK |
243 | INSN_CODE (object) = -1; |
244 | } | |
245 | ||
246 | num_changes++; | |
247 | ||
248 | /* If we are making a group of changes, return 1. Otherwise, validate the | |
249 | change group we made. */ | |
250 | ||
251 | if (in_group) | |
252 | return 1; | |
253 | else | |
254 | return apply_change_group (); | |
255 | } | |
256 | ||
61719ba7 BS |
257 | /* This subroutine of apply_change_group verifies whether the changes to INSN |
258 | were valid; i.e. whether INSN can still be recognized. */ | |
259 | ||
260 | static int | |
261 | insn_invalid_p (insn) | |
262 | rtx insn; | |
263 | { | |
264 | int icode = recog_memoized (insn); | |
265 | int is_asm = icode < 0 && asm_noperands (PATTERN (insn)) >= 0; | |
266 | ||
0eadeb15 BS |
267 | if (is_asm && ! check_asm_operands (PATTERN (insn))) |
268 | return 1; | |
269 | if (! is_asm && icode < 0) | |
61719ba7 BS |
270 | return 1; |
271 | ||
272 | /* After reload, verify that all constraints are satisfied. */ | |
273 | if (reload_completed) | |
274 | { | |
0eadeb15 | 275 | extract_insn (insn); |
61719ba7 | 276 | |
0eadeb15 | 277 | if (! constrain_operands (1)) |
61719ba7 BS |
278 | return 1; |
279 | } | |
280 | ||
281 | return 0; | |
282 | } | |
283 | ||
2055cea7 RK |
284 | /* Apply a group of changes previously issued with `validate_change'. |
285 | Return 1 if all changes are valid, zero otherwise. */ | |
286 | ||
287 | int | |
288 | apply_change_group () | |
289 | { | |
290 | int i; | |
291 | ||
292 | /* The changes have been applied and all INSN_CODEs have been reset to force | |
293 | rerecognition. | |
294 | ||
295 | The changes are valid if we aren't given an object, or if we are | |
296 | given a MEM and it still is a valid address, or if this is in insn | |
297 | and it is recognized. In the latter case, if reload has completed, | |
298 | we also require that the operands meet the constraints for | |
0eadeb15 | 299 | the insn. */ |
2055cea7 RK |
300 | |
301 | for (i = 0; i < num_changes; i++) | |
302 | { | |
41a972a9 | 303 | rtx object = changes[i].object; |
2055cea7 RK |
304 | |
305 | if (object == 0) | |
306 | continue; | |
307 | ||
308 | if (GET_CODE (object) == MEM) | |
309 | { | |
310 | if (! memory_address_p (GET_MODE (object), XEXP (object, 0))) | |
311 | break; | |
312 | } | |
61719ba7 | 313 | else if (insn_invalid_p (object)) |
2055cea7 RK |
314 | { |
315 | rtx pat = PATTERN (object); | |
316 | ||
317 | /* Perhaps we couldn't recognize the insn because there were | |
318 | extra CLOBBERs at the end. If so, try to re-recognize | |
319 | without the last CLOBBER (later iterations will cause each of | |
320 | them to be eliminated, in turn). But don't do this if we | |
321 | have an ASM_OPERAND. */ | |
322 | if (GET_CODE (pat) == PARALLEL | |
323 | && GET_CODE (XVECEXP (pat, 0, XVECLEN (pat, 0) - 1)) == CLOBBER | |
324 | && asm_noperands (PATTERN (object)) < 0) | |
325 | { | |
326 | rtx newpat; | |
327 | ||
328 | if (XVECLEN (pat, 0) == 2) | |
329 | newpat = XVECEXP (pat, 0, 0); | |
330 | else | |
331 | { | |
332 | int j; | |
333 | ||
c5c76735 JL |
334 | newpat |
335 | = gen_rtx_PARALLEL (VOIDmode, | |
336 | gen_rtvec (XVECLEN (pat, 0) - 1)); | |
2055cea7 RK |
337 | for (j = 0; j < XVECLEN (newpat, 0); j++) |
338 | XVECEXP (newpat, 0, j) = XVECEXP (pat, 0, j); | |
339 | } | |
340 | ||
341 | /* Add a new change to this group to replace the pattern | |
342 | with this new pattern. Then consider this change | |
343 | as having succeeded. The change we added will | |
344 | cause the entire call to fail if things remain invalid. | |
345 | ||
346 | Note that this can lose if a later change than the one | |
347 | we are processing specified &XVECEXP (PATTERN (object), 0, X) | |
348 | but this shouldn't occur. */ | |
349 | ||
350 | validate_change (object, &PATTERN (object), newpat, 1); | |
351 | } | |
352 | else if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER) | |
353 | /* If this insn is a CLOBBER or USE, it is always valid, but is | |
354 | never recognized. */ | |
355 | continue; | |
356 | else | |
357 | break; | |
358 | } | |
359 | } | |
360 | ||
361 | if (i == num_changes) | |
362 | { | |
363 | num_changes = 0; | |
364 | return 1; | |
365 | } | |
366 | else | |
367 | { | |
368 | cancel_changes (0); | |
369 | return 0; | |
370 | } | |
371 | } | |
372 | ||
373 | /* Return the number of changes so far in the current group. */ | |
374 | ||
375 | int | |
376 | num_validated_changes () | |
377 | { | |
378 | return num_changes; | |
379 | } | |
380 | ||
381 | /* Retract the changes numbered NUM and up. */ | |
382 | ||
383 | void | |
384 | cancel_changes (num) | |
385 | int num; | |
386 | { | |
387 | int i; | |
388 | ||
389 | /* Back out all the changes. Do this in the opposite order in which | |
390 | they were made. */ | |
391 | for (i = num_changes - 1; i >= num; i--) | |
392 | { | |
41a972a9 MM |
393 | *changes[i].loc = changes[i].old; |
394 | if (changes[i].object && GET_CODE (changes[i].object) != MEM) | |
395 | INSN_CODE (changes[i].object) = changes[i].old_code; | |
2055cea7 RK |
396 | } |
397 | num_changes = num; | |
398 | } | |
399 | ||
400 | /* Replace every occurrence of FROM in X with TO. Mark each change with | |
401 | validate_change passing OBJECT. */ | |
402 | ||
403 | static void | |
404 | validate_replace_rtx_1 (loc, from, to, object) | |
405 | rtx *loc; | |
406 | rtx from, to, object; | |
407 | { | |
408 | register int i, j; | |
6f7d635c | 409 | register const char *fmt; |
2055cea7 RK |
410 | register rtx x = *loc; |
411 | enum rtx_code code = GET_CODE (x); | |
412 | ||
413 | /* X matches FROM if it is the same rtx or they are both referring to the | |
414 | same register in the same mode. Avoid calling rtx_equal_p unless the | |
415 | operands look similar. */ | |
416 | ||
417 | if (x == from | |
418 | || (GET_CODE (x) == REG && GET_CODE (from) == REG | |
419 | && GET_MODE (x) == GET_MODE (from) | |
420 | && REGNO (x) == REGNO (from)) | |
421 | || (GET_CODE (x) == GET_CODE (from) && GET_MODE (x) == GET_MODE (from) | |
422 | && rtx_equal_p (x, from))) | |
423 | { | |
424 | validate_change (object, loc, to, 1); | |
425 | return; | |
426 | } | |
427 | ||
428 | /* For commutative or comparison operations, try replacing each argument | |
429 | separately and seeing if we made any changes. If so, put a constant | |
430 | argument last.*/ | |
431 | if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c') | |
432 | { | |
433 | int prev_changes = num_changes; | |
434 | ||
435 | validate_replace_rtx_1 (&XEXP (x, 0), from, to, object); | |
436 | validate_replace_rtx_1 (&XEXP (x, 1), from, to, object); | |
437 | if (prev_changes != num_changes && CONSTANT_P (XEXP (x, 0))) | |
438 | { | |
439 | validate_change (object, loc, | |
38a448ca RH |
440 | gen_rtx_fmt_ee (GET_RTX_CLASS (code) == 'c' ? code |
441 | : swap_condition (code), | |
442 | GET_MODE (x), XEXP (x, 1), | |
443 | XEXP (x, 0)), | |
2055cea7 RK |
444 | 1); |
445 | x = *loc; | |
446 | code = GET_CODE (x); | |
447 | } | |
448 | } | |
449 | ||
06140bdf RK |
450 | /* Note that if CODE's RTX_CLASS is "c" or "<" we will have already |
451 | done the substitution, otherwise we won't. */ | |
452 | ||
2055cea7 RK |
453 | switch (code) |
454 | { | |
455 | case PLUS: | |
38e01259 | 456 | /* If we have a PLUS whose second operand is now a CONST_INT, use |
2055cea7 RK |
457 | plus_constant to try to simplify it. */ |
458 | if (GET_CODE (XEXP (x, 1)) == CONST_INT && XEXP (x, 1) == to) | |
06140bdf RK |
459 | validate_change (object, loc, plus_constant (XEXP (x, 0), INTVAL (to)), |
460 | 1); | |
2055cea7 | 461 | return; |
06140bdf RK |
462 | |
463 | case MINUS: | |
464 | if (GET_CODE (to) == CONST_INT && XEXP (x, 1) == from) | |
465 | { | |
466 | validate_change (object, loc, | |
467 | plus_constant (XEXP (x, 0), - INTVAL (to)), | |
468 | 1); | |
469 | return; | |
470 | } | |
471 | break; | |
2055cea7 RK |
472 | |
473 | case ZERO_EXTEND: | |
474 | case SIGN_EXTEND: | |
475 | /* In these cases, the operation to be performed depends on the mode | |
476 | of the operand. If we are replacing the operand with a VOIDmode | |
477 | constant, we lose the information. So try to simplify the operation | |
478 | in that case. If it fails, substitute in something that we know | |
6dc42e49 | 479 | won't be recognized. */ |
2055cea7 RK |
480 | if (GET_MODE (to) == VOIDmode |
481 | && (XEXP (x, 0) == from | |
482 | || (GET_CODE (XEXP (x, 0)) == REG && GET_CODE (from) == REG | |
483 | && GET_MODE (XEXP (x, 0)) == GET_MODE (from) | |
484 | && REGNO (XEXP (x, 0)) == REGNO (from)))) | |
485 | { | |
486 | rtx new = simplify_unary_operation (code, GET_MODE (x), to, | |
487 | GET_MODE (from)); | |
488 | if (new == 0) | |
38a448ca | 489 | new = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); |
2055cea7 RK |
490 | |
491 | validate_change (object, loc, new, 1); | |
492 | return; | |
493 | } | |
494 | break; | |
495 | ||
496 | case SUBREG: | |
497 | /* If we have a SUBREG of a register that we are replacing and we are | |
498 | replacing it with a MEM, make a new MEM and try replacing the | |
499 | SUBREG with it. Don't do this if the MEM has a mode-dependent address | |
500 | or if we would be widening it. */ | |
501 | ||
502 | if (SUBREG_REG (x) == from | |
503 | && GET_CODE (from) == REG | |
504 | && GET_CODE (to) == MEM | |
505 | && ! mode_dependent_address_p (XEXP (to, 0)) | |
506 | && ! MEM_VOLATILE_P (to) | |
507 | && GET_MODE_SIZE (GET_MODE (x)) <= GET_MODE_SIZE (GET_MODE (to))) | |
508 | { | |
509 | int offset = SUBREG_WORD (x) * UNITS_PER_WORD; | |
510 | enum machine_mode mode = GET_MODE (x); | |
511 | rtx new; | |
512 | ||
f76b9db2 ILT |
513 | if (BYTES_BIG_ENDIAN) |
514 | offset += (MIN (UNITS_PER_WORD, | |
515 | GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
516 | - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))); | |
2055cea7 | 517 | |
38a448ca | 518 | new = gen_rtx_MEM (mode, plus_constant (XEXP (to, 0), offset)); |
2055cea7 | 519 | RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (to); |
c6df88cb | 520 | MEM_COPY_ATTRIBUTES (new, to); |
2055cea7 RK |
521 | validate_change (object, loc, new, 1); |
522 | return; | |
523 | } | |
524 | break; | |
525 | ||
526 | case ZERO_EXTRACT: | |
527 | case SIGN_EXTRACT: | |
528 | /* If we are replacing a register with memory, try to change the memory | |
529 | to be the mode required for memory in extract operations (this isn't | |
530 | likely to be an insertion operation; if it was, nothing bad will | |
531 | happen, we might just fail in some cases). */ | |
532 | ||
533 | if (XEXP (x, 0) == from && GET_CODE (from) == REG && GET_CODE (to) == MEM | |
534 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
535 | && GET_CODE (XEXP (x, 2)) == CONST_INT | |
536 | && ! mode_dependent_address_p (XEXP (to, 0)) | |
537 | && ! MEM_VOLATILE_P (to)) | |
538 | { | |
539 | enum machine_mode wanted_mode = VOIDmode; | |
540 | enum machine_mode is_mode = GET_MODE (to); | |
2055cea7 RK |
541 | int pos = INTVAL (XEXP (x, 2)); |
542 | ||
543 | #ifdef HAVE_extzv | |
544 | if (code == ZERO_EXTRACT) | |
0d8e55d8 | 545 | { |
a995e389 | 546 | wanted_mode = insn_data[(int) CODE_FOR_extzv].operand[1].mode; |
0d8e55d8 JL |
547 | if (wanted_mode == VOIDmode) |
548 | wanted_mode = word_mode; | |
549 | } | |
2055cea7 RK |
550 | #endif |
551 | #ifdef HAVE_extv | |
552 | if (code == SIGN_EXTRACT) | |
0d8e55d8 | 553 | { |
a995e389 | 554 | wanted_mode = insn_data[(int) CODE_FOR_extv].operand[1].mode; |
0d8e55d8 JL |
555 | if (wanted_mode == VOIDmode) |
556 | wanted_mode = word_mode; | |
557 | } | |
2055cea7 RK |
558 | #endif |
559 | ||
6dc42e49 | 560 | /* If we have a narrower mode, we can do something. */ |
2055cea7 RK |
561 | if (wanted_mode != VOIDmode |
562 | && GET_MODE_SIZE (wanted_mode) < GET_MODE_SIZE (is_mode)) | |
563 | { | |
564 | int offset = pos / BITS_PER_UNIT; | |
565 | rtx newmem; | |
566 | ||
567 | /* If the bytes and bits are counted differently, we | |
568 | must adjust the offset. */ | |
f76b9db2 ILT |
569 | if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN) |
570 | offset = (GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (wanted_mode) | |
571 | - offset); | |
2055cea7 RK |
572 | |
573 | pos %= GET_MODE_BITSIZE (wanted_mode); | |
574 | ||
38a448ca RH |
575 | newmem = gen_rtx_MEM (wanted_mode, |
576 | plus_constant (XEXP (to, 0), offset)); | |
2055cea7 | 577 | RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (to); |
c6df88cb | 578 | MEM_COPY_ATTRIBUTES (newmem, to); |
2055cea7 | 579 | |
9e4223f2 | 580 | validate_change (object, &XEXP (x, 2), GEN_INT (pos), 1); |
2055cea7 RK |
581 | validate_change (object, &XEXP (x, 0), newmem, 1); |
582 | } | |
583 | } | |
584 | ||
585 | break; | |
38a448ca RH |
586 | |
587 | default: | |
588 | break; | |
2055cea7 RK |
589 | } |
590 | ||
f745c7a2 AB |
591 | /* For commutative or comparison operations we've already performed |
592 | replacements. Don't try to perform them again. */ | |
593 | if (GET_RTX_CLASS (code) != '<' && GET_RTX_CLASS (code) != 'c') | |
2055cea7 | 594 | { |
f745c7a2 AB |
595 | fmt = GET_RTX_FORMAT (code); |
596 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
597 | { | |
598 | if (fmt[i] == 'e') | |
599 | validate_replace_rtx_1 (&XEXP (x, i), from, to, object); | |
600 | else if (fmt[i] == 'E') | |
601 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
602 | validate_replace_rtx_1 (&XVECEXP (x, i, j), from, to, object); | |
603 | } | |
2055cea7 RK |
604 | } |
605 | } | |
606 | ||
607 | /* Try replacing every occurrence of FROM in INSN with TO. After all | |
608 | changes have been made, validate by seeing if INSN is still valid. */ | |
609 | ||
610 | int | |
611 | validate_replace_rtx (from, to, insn) | |
612 | rtx from, to, insn; | |
613 | { | |
614 | validate_replace_rtx_1 (&PATTERN (insn), from, to, insn); | |
615 | return apply_change_group (); | |
616 | } | |
7506f491 | 617 | |
edfac33e JL |
618 | /* Try replacing every occurrence of FROM in INSN with TO. After all |
619 | changes have been made, validate by seeing if INSN is still valid. */ | |
620 | ||
621 | void | |
622 | validate_replace_rtx_group (from, to, insn) | |
623 | rtx from, to, insn; | |
624 | { | |
625 | validate_replace_rtx_1 (&PATTERN (insn), from, to, insn); | |
626 | } | |
627 | ||
7506f491 DE |
628 | /* Try replacing every occurrence of FROM in INSN with TO, avoiding |
629 | SET_DESTs. After all changes have been made, validate by seeing if | |
630 | INSN is still valid. */ | |
631 | ||
632 | int | |
633 | validate_replace_src (from, to, insn) | |
634 | rtx from, to, insn; | |
635 | { | |
636 | if ((GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN) | |
637 | || GET_CODE (PATTERN (insn)) != SET) | |
638 | abort (); | |
639 | ||
640 | validate_replace_rtx_1 (&SET_SRC (PATTERN (insn)), from, to, insn); | |
641 | if (GET_CODE (SET_DEST (PATTERN (insn))) == MEM) | |
642 | validate_replace_rtx_1 (&XEXP (SET_DEST (PATTERN (insn)), 0), | |
643 | from, to, insn); | |
644 | return apply_change_group (); | |
645 | } | |
2055cea7 RK |
646 | \f |
647 | #ifdef HAVE_cc0 | |
648 | /* Return 1 if the insn using CC0 set by INSN does not contain | |
649 | any ordered tests applied to the condition codes. | |
650 | EQ and NE tests do not count. */ | |
651 | ||
652 | int | |
653 | next_insn_tests_no_inequality (insn) | |
654 | rtx insn; | |
655 | { | |
656 | register rtx next = next_cc0_user (insn); | |
657 | ||
658 | /* If there is no next insn, we have to take the conservative choice. */ | |
659 | if (next == 0) | |
660 | return 0; | |
661 | ||
662 | return ((GET_CODE (next) == JUMP_INSN | |
663 | || GET_CODE (next) == INSN | |
664 | || GET_CODE (next) == CALL_INSN) | |
665 | && ! inequality_comparisons_p (PATTERN (next))); | |
666 | } | |
667 | ||
668 | #if 0 /* This is useless since the insn that sets the cc's | |
669 | must be followed immediately by the use of them. */ | |
670 | /* Return 1 if the CC value set up by INSN is not used. */ | |
671 | ||
672 | int | |
673 | next_insns_test_no_inequality (insn) | |
674 | rtx insn; | |
675 | { | |
676 | register rtx next = NEXT_INSN (insn); | |
677 | ||
678 | for (; next != 0; next = NEXT_INSN (next)) | |
679 | { | |
680 | if (GET_CODE (next) == CODE_LABEL | |
681 | || GET_CODE (next) == BARRIER) | |
682 | return 1; | |
683 | if (GET_CODE (next) == NOTE) | |
684 | continue; | |
685 | if (inequality_comparisons_p (PATTERN (next))) | |
686 | return 0; | |
687 | if (sets_cc0_p (PATTERN (next)) == 1) | |
688 | return 1; | |
689 | if (! reg_mentioned_p (cc0_rtx, PATTERN (next))) | |
690 | return 1; | |
691 | } | |
692 | return 1; | |
693 | } | |
694 | #endif | |
695 | #endif | |
696 | \f | |
697 | /* This is used by find_single_use to locate an rtx that contains exactly one | |
698 | use of DEST, which is typically either a REG or CC0. It returns a | |
699 | pointer to the innermost rtx expression containing DEST. Appearances of | |
700 | DEST that are being used to totally replace it are not counted. */ | |
701 | ||
702 | static rtx * | |
703 | find_single_use_1 (dest, loc) | |
704 | rtx dest; | |
705 | rtx *loc; | |
706 | { | |
707 | rtx x = *loc; | |
708 | enum rtx_code code = GET_CODE (x); | |
709 | rtx *result = 0; | |
710 | rtx *this_result; | |
711 | int i; | |
6f7d635c | 712 | const char *fmt; |
2055cea7 RK |
713 | |
714 | switch (code) | |
715 | { | |
716 | case CONST_INT: | |
717 | case CONST: | |
718 | case LABEL_REF: | |
719 | case SYMBOL_REF: | |
720 | case CONST_DOUBLE: | |
721 | case CLOBBER: | |
722 | return 0; | |
723 | ||
724 | case SET: | |
725 | /* If the destination is anything other than CC0, PC, a REG or a SUBREG | |
726 | of a REG that occupies all of the REG, the insn uses DEST if | |
727 | it is mentioned in the destination or the source. Otherwise, we | |
728 | need just check the source. */ | |
729 | if (GET_CODE (SET_DEST (x)) != CC0 | |
730 | && GET_CODE (SET_DEST (x)) != PC | |
731 | && GET_CODE (SET_DEST (x)) != REG | |
732 | && ! (GET_CODE (SET_DEST (x)) == SUBREG | |
733 | && GET_CODE (SUBREG_REG (SET_DEST (x))) == REG | |
734 | && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x)))) | |
735 | + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) | |
736 | == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x))) | |
737 | + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))) | |
738 | break; | |
739 | ||
740 | return find_single_use_1 (dest, &SET_SRC (x)); | |
741 | ||
742 | case MEM: | |
743 | case SUBREG: | |
744 | return find_single_use_1 (dest, &XEXP (x, 0)); | |
38a448ca RH |
745 | |
746 | default: | |
747 | break; | |
2055cea7 RK |
748 | } |
749 | ||
750 | /* If it wasn't one of the common cases above, check each expression and | |
751 | vector of this code. Look for a unique usage of DEST. */ | |
752 | ||
753 | fmt = GET_RTX_FORMAT (code); | |
754 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
755 | { | |
756 | if (fmt[i] == 'e') | |
757 | { | |
758 | if (dest == XEXP (x, i) | |
759 | || (GET_CODE (dest) == REG && GET_CODE (XEXP (x, i)) == REG | |
760 | && REGNO (dest) == REGNO (XEXP (x, i)))) | |
761 | this_result = loc; | |
762 | else | |
763 | this_result = find_single_use_1 (dest, &XEXP (x, i)); | |
764 | ||
765 | if (result == 0) | |
766 | result = this_result; | |
767 | else if (this_result) | |
768 | /* Duplicate usage. */ | |
769 | return 0; | |
770 | } | |
771 | else if (fmt[i] == 'E') | |
772 | { | |
773 | int j; | |
774 | ||
775 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
776 | { | |
777 | if (XVECEXP (x, i, j) == dest | |
778 | || (GET_CODE (dest) == REG | |
779 | && GET_CODE (XVECEXP (x, i, j)) == REG | |
780 | && REGNO (XVECEXP (x, i, j)) == REGNO (dest))) | |
781 | this_result = loc; | |
782 | else | |
783 | this_result = find_single_use_1 (dest, &XVECEXP (x, i, j)); | |
784 | ||
785 | if (result == 0) | |
786 | result = this_result; | |
787 | else if (this_result) | |
788 | return 0; | |
789 | } | |
790 | } | |
791 | } | |
792 | ||
793 | return result; | |
794 | } | |
795 | \f | |
796 | /* See if DEST, produced in INSN, is used only a single time in the | |
797 | sequel. If so, return a pointer to the innermost rtx expression in which | |
798 | it is used. | |
799 | ||
800 | If PLOC is non-zero, *PLOC is set to the insn containing the single use. | |
801 | ||
802 | This routine will return usually zero either before flow is called (because | |
803 | there will be no LOG_LINKS notes) or after reload (because the REG_DEAD | |
804 | note can't be trusted). | |
805 | ||
806 | If DEST is cc0_rtx, we look only at the next insn. In that case, we don't | |
807 | care about REG_DEAD notes or LOG_LINKS. | |
808 | ||
809 | Otherwise, we find the single use by finding an insn that has a | |
810 | LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is | |
811 | only referenced once in that insn, we know that it must be the first | |
812 | and last insn referencing DEST. */ | |
813 | ||
814 | rtx * | |
815 | find_single_use (dest, insn, ploc) | |
816 | rtx dest; | |
817 | rtx insn; | |
818 | rtx *ploc; | |
819 | { | |
820 | rtx next; | |
821 | rtx *result; | |
822 | rtx link; | |
823 | ||
824 | #ifdef HAVE_cc0 | |
825 | if (dest == cc0_rtx) | |
826 | { | |
827 | next = NEXT_INSN (insn); | |
828 | if (next == 0 | |
829 | || (GET_CODE (next) != INSN && GET_CODE (next) != JUMP_INSN)) | |
830 | return 0; | |
831 | ||
832 | result = find_single_use_1 (dest, &PATTERN (next)); | |
833 | if (result && ploc) | |
834 | *ploc = next; | |
835 | return result; | |
836 | } | |
837 | #endif | |
838 | ||
839 | if (reload_completed || reload_in_progress || GET_CODE (dest) != REG) | |
840 | return 0; | |
841 | ||
842 | for (next = next_nonnote_insn (insn); | |
843 | next != 0 && GET_CODE (next) != CODE_LABEL; | |
844 | next = next_nonnote_insn (next)) | |
845 | if (GET_RTX_CLASS (GET_CODE (next)) == 'i' && dead_or_set_p (next, dest)) | |
846 | { | |
847 | for (link = LOG_LINKS (next); link; link = XEXP (link, 1)) | |
848 | if (XEXP (link, 0) == insn) | |
849 | break; | |
850 | ||
851 | if (link) | |
852 | { | |
853 | result = find_single_use_1 (dest, &PATTERN (next)); | |
854 | if (ploc) | |
855 | *ploc = next; | |
856 | return result; | |
857 | } | |
858 | } | |
859 | ||
860 | return 0; | |
861 | } | |
862 | \f | |
863 | /* Return 1 if OP is a valid general operand for machine mode MODE. | |
864 | This is either a register reference, a memory reference, | |
865 | or a constant. In the case of a memory reference, the address | |
866 | is checked for general validity for the target machine. | |
867 | ||
868 | Register and memory references must have mode MODE in order to be valid, | |
869 | but some constants have no machine mode and are valid for any mode. | |
870 | ||
871 | If MODE is VOIDmode, OP is checked for validity for whatever mode | |
872 | it has. | |
873 | ||
874 | The main use of this function is as a predicate in match_operand | |
875 | expressions in the machine description. | |
876 | ||
6dc42e49 | 877 | For an explanation of this function's behavior for registers of |
2055cea7 RK |
878 | class NO_REGS, see the comment for `register_operand'. */ |
879 | ||
880 | int | |
881 | general_operand (op, mode) | |
882 | register rtx op; | |
883 | enum machine_mode mode; | |
884 | { | |
885 | register enum rtx_code code = GET_CODE (op); | |
886 | int mode_altering_drug = 0; | |
887 | ||
888 | if (mode == VOIDmode) | |
889 | mode = GET_MODE (op); | |
890 | ||
891 | /* Don't accept CONST_INT or anything similar | |
892 | if the caller wants something floating. */ | |
893 | if (GET_MODE (op) == VOIDmode && mode != VOIDmode | |
4bb4c82e RK |
894 | && GET_MODE_CLASS (mode) != MODE_INT |
895 | && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT) | |
2055cea7 RK |
896 | return 0; |
897 | ||
898 | if (CONSTANT_P (op)) | |
899 | return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode) | |
900 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
901 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) | |
902 | #endif | |
903 | && LEGITIMATE_CONSTANT_P (op)); | |
904 | ||
905 | /* Except for certain constants with VOIDmode, already checked for, | |
906 | OP's mode must match MODE if MODE specifies a mode. */ | |
907 | ||
908 | if (GET_MODE (op) != mode) | |
909 | return 0; | |
910 | ||
911 | if (code == SUBREG) | |
912 | { | |
913 | #ifdef INSN_SCHEDULING | |
914 | /* On machines that have insn scheduling, we want all memory | |
915 | reference to be explicit, so outlaw paradoxical SUBREGs. */ | |
916 | if (GET_CODE (SUBREG_REG (op)) == MEM | |
917 | && GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op)))) | |
918 | return 0; | |
919 | #endif | |
920 | ||
921 | op = SUBREG_REG (op); | |
922 | code = GET_CODE (op); | |
923 | #if 0 | |
924 | /* No longer needed, since (SUBREG (MEM...)) | |
925 | will load the MEM into a reload reg in the MEM's own mode. */ | |
926 | mode_altering_drug = 1; | |
927 | #endif | |
928 | } | |
929 | ||
930 | if (code == REG) | |
931 | /* A register whose class is NO_REGS is not a general operand. */ | |
932 | return (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
933 | || REGNO_REG_CLASS (REGNO (op)) != NO_REGS); | |
934 | ||
935 | if (code == MEM) | |
936 | { | |
937 | register rtx y = XEXP (op, 0); | |
938 | if (! volatile_ok && MEM_VOLATILE_P (op)) | |
939 | return 0; | |
38a448ca RH |
940 | if (GET_CODE (y) == ADDRESSOF) |
941 | return 1; | |
2055cea7 RK |
942 | /* Use the mem's mode, since it will be reloaded thus. */ |
943 | mode = GET_MODE (op); | |
944 | GO_IF_LEGITIMATE_ADDRESS (mode, y, win); | |
945 | } | |
38a448ca RH |
946 | |
947 | /* Pretend this is an operand for now; we'll run force_operand | |
948 | on its replacement in fixup_var_refs_1. */ | |
949 | if (code == ADDRESSOF) | |
950 | return 1; | |
951 | ||
2055cea7 RK |
952 | return 0; |
953 | ||
954 | win: | |
955 | if (mode_altering_drug) | |
956 | return ! mode_dependent_address_p (XEXP (op, 0)); | |
957 | return 1; | |
958 | } | |
959 | \f | |
960 | /* Return 1 if OP is a valid memory address for a memory reference | |
961 | of mode MODE. | |
962 | ||
963 | The main use of this function is as a predicate in match_operand | |
964 | expressions in the machine description. */ | |
965 | ||
966 | int | |
967 | address_operand (op, mode) | |
968 | register rtx op; | |
969 | enum machine_mode mode; | |
970 | { | |
971 | return memory_address_p (mode, op); | |
972 | } | |
973 | ||
974 | /* Return 1 if OP is a register reference of mode MODE. | |
975 | If MODE is VOIDmode, accept a register in any mode. | |
976 | ||
977 | The main use of this function is as a predicate in match_operand | |
978 | expressions in the machine description. | |
979 | ||
980 | As a special exception, registers whose class is NO_REGS are | |
981 | not accepted by `register_operand'. The reason for this change | |
982 | is to allow the representation of special architecture artifacts | |
983 | (such as a condition code register) without extending the rtl | |
984 | definitions. Since registers of class NO_REGS cannot be used | |
985 | as registers in any case where register classes are examined, | |
986 | it is most consistent to keep this function from accepting them. */ | |
987 | ||
988 | int | |
989 | register_operand (op, mode) | |
990 | register rtx op; | |
991 | enum machine_mode mode; | |
992 | { | |
993 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
994 | return 0; | |
995 | ||
996 | if (GET_CODE (op) == SUBREG) | |
997 | { | |
998 | /* Before reload, we can allow (SUBREG (MEM...)) as a register operand | |
999 | because it is guaranteed to be reloaded into one. | |
1000 | Just make sure the MEM is valid in itself. | |
1001 | (Ideally, (SUBREG (MEM)...) should not exist after reload, | |
1002 | but currently it does result from (SUBREG (REG)...) where the | |
1003 | reg went on the stack.) */ | |
1004 | if (! reload_completed && GET_CODE (SUBREG_REG (op)) == MEM) | |
1005 | return general_operand (op, mode); | |
cba057ed RK |
1006 | |
1007 | #ifdef CLASS_CANNOT_CHANGE_SIZE | |
1008 | if (GET_CODE (SUBREG_REG (op)) == REG | |
1009 | && REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER | |
1010 | && TEST_HARD_REG_BIT (reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE], | |
1011 | REGNO (SUBREG_REG (op))) | |
1012 | && (GET_MODE_SIZE (mode) | |
50dc6373 RK |
1013 | != GET_MODE_SIZE (GET_MODE (SUBREG_REG (op)))) |
1014 | && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op))) != MODE_COMPLEX_INT | |
1015 | && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op))) != MODE_COMPLEX_FLOAT) | |
cba057ed RK |
1016 | return 0; |
1017 | #endif | |
1018 | ||
2055cea7 RK |
1019 | op = SUBREG_REG (op); |
1020 | } | |
1021 | ||
1022 | /* We don't consider registers whose class is NO_REGS | |
1023 | to be a register operand. */ | |
1024 | return (GET_CODE (op) == REG | |
1025 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
1026 | || REGNO_REG_CLASS (REGNO (op)) != NO_REGS)); | |
1027 | } | |
1028 | ||
1029 | /* Return 1 if OP should match a MATCH_SCRATCH, i.e., if it is a SCRATCH | |
1030 | or a hard register. */ | |
1031 | ||
1032 | int | |
1033 | scratch_operand (op, mode) | |
1034 | register rtx op; | |
1035 | enum machine_mode mode; | |
1036 | { | |
1037 | return (GET_MODE (op) == mode | |
1038 | && (GET_CODE (op) == SCRATCH | |
1039 | || (GET_CODE (op) == REG | |
1040 | && REGNO (op) < FIRST_PSEUDO_REGISTER))); | |
1041 | } | |
1042 | ||
1043 | /* Return 1 if OP is a valid immediate operand for mode MODE. | |
1044 | ||
1045 | The main use of this function is as a predicate in match_operand | |
1046 | expressions in the machine description. */ | |
1047 | ||
1048 | int | |
1049 | immediate_operand (op, mode) | |
1050 | register rtx op; | |
1051 | enum machine_mode mode; | |
1052 | { | |
1053 | /* Don't accept CONST_INT or anything similar | |
1054 | if the caller wants something floating. */ | |
1055 | if (GET_MODE (op) == VOIDmode && mode != VOIDmode | |
4bb4c82e RK |
1056 | && GET_MODE_CLASS (mode) != MODE_INT |
1057 | && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT) | |
2055cea7 RK |
1058 | return 0; |
1059 | ||
ee5332b8 RH |
1060 | /* Accept CONSTANT_P_RTX, since it will be gone by CSE1 and |
1061 | result in 0/1. It seems a safe assumption that this is | |
1062 | in range for everyone. */ | |
1063 | if (GET_CODE (op) == CONSTANT_P_RTX) | |
1064 | return 1; | |
1065 | ||
2055cea7 RK |
1066 | return (CONSTANT_P (op) |
1067 | && (GET_MODE (op) == mode || mode == VOIDmode | |
1068 | || GET_MODE (op) == VOIDmode) | |
1069 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
1070 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) | |
1071 | #endif | |
1072 | && LEGITIMATE_CONSTANT_P (op)); | |
1073 | } | |
1074 | ||
1075 | /* Returns 1 if OP is an operand that is a CONST_INT. */ | |
1076 | ||
1077 | int | |
1078 | const_int_operand (op, mode) | |
1079 | register rtx op; | |
e51712db | 1080 | enum machine_mode mode ATTRIBUTE_UNUSED; |
2055cea7 RK |
1081 | { |
1082 | return GET_CODE (op) == CONST_INT; | |
1083 | } | |
1084 | ||
1085 | /* Returns 1 if OP is an operand that is a constant integer or constant | |
1086 | floating-point number. */ | |
1087 | ||
1088 | int | |
1089 | const_double_operand (op, mode) | |
1090 | register rtx op; | |
1091 | enum machine_mode mode; | |
1092 | { | |
1093 | /* Don't accept CONST_INT or anything similar | |
1094 | if the caller wants something floating. */ | |
1095 | if (GET_MODE (op) == VOIDmode && mode != VOIDmode | |
4bb4c82e RK |
1096 | && GET_MODE_CLASS (mode) != MODE_INT |
1097 | && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT) | |
2055cea7 RK |
1098 | return 0; |
1099 | ||
1100 | return ((GET_CODE (op) == CONST_DOUBLE || GET_CODE (op) == CONST_INT) | |
1101 | && (mode == VOIDmode || GET_MODE (op) == mode | |
1102 | || GET_MODE (op) == VOIDmode)); | |
1103 | } | |
1104 | ||
1105 | /* Return 1 if OP is a general operand that is not an immediate operand. */ | |
1106 | ||
1107 | int | |
1108 | nonimmediate_operand (op, mode) | |
1109 | register rtx op; | |
1110 | enum machine_mode mode; | |
1111 | { | |
1112 | return (general_operand (op, mode) && ! CONSTANT_P (op)); | |
1113 | } | |
1114 | ||
1115 | /* Return 1 if OP is a register reference or immediate value of mode MODE. */ | |
1116 | ||
1117 | int | |
1118 | nonmemory_operand (op, mode) | |
1119 | register rtx op; | |
1120 | enum machine_mode mode; | |
1121 | { | |
1122 | if (CONSTANT_P (op)) | |
1123 | { | |
1124 | /* Don't accept CONST_INT or anything similar | |
1125 | if the caller wants something floating. */ | |
1126 | if (GET_MODE (op) == VOIDmode && mode != VOIDmode | |
4bb4c82e RK |
1127 | && GET_MODE_CLASS (mode) != MODE_INT |
1128 | && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT) | |
2055cea7 RK |
1129 | return 0; |
1130 | ||
1131 | return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode) | |
1132 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
1133 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) | |
1134 | #endif | |
1135 | && LEGITIMATE_CONSTANT_P (op)); | |
1136 | } | |
1137 | ||
1138 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
1139 | return 0; | |
1140 | ||
1141 | if (GET_CODE (op) == SUBREG) | |
1142 | { | |
1143 | /* Before reload, we can allow (SUBREG (MEM...)) as a register operand | |
1144 | because it is guaranteed to be reloaded into one. | |
1145 | Just make sure the MEM is valid in itself. | |
1146 | (Ideally, (SUBREG (MEM)...) should not exist after reload, | |
1147 | but currently it does result from (SUBREG (REG)...) where the | |
1148 | reg went on the stack.) */ | |
1149 | if (! reload_completed && GET_CODE (SUBREG_REG (op)) == MEM) | |
1150 | return general_operand (op, mode); | |
1151 | op = SUBREG_REG (op); | |
1152 | } | |
1153 | ||
1154 | /* We don't consider registers whose class is NO_REGS | |
1155 | to be a register operand. */ | |
1156 | return (GET_CODE (op) == REG | |
1157 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
1158 | || REGNO_REG_CLASS (REGNO (op)) != NO_REGS)); | |
1159 | } | |
1160 | ||
1161 | /* Return 1 if OP is a valid operand that stands for pushing a | |
1162 | value of mode MODE onto the stack. | |
1163 | ||
1164 | The main use of this function is as a predicate in match_operand | |
1165 | expressions in the machine description. */ | |
1166 | ||
1167 | int | |
1168 | push_operand (op, mode) | |
1169 | rtx op; | |
1170 | enum machine_mode mode; | |
1171 | { | |
1172 | if (GET_CODE (op) != MEM) | |
1173 | return 0; | |
1174 | ||
aeb7ff68 | 1175 | if (mode != VOIDmode && GET_MODE (op) != mode) |
2055cea7 RK |
1176 | return 0; |
1177 | ||
1178 | op = XEXP (op, 0); | |
1179 | ||
1180 | if (GET_CODE (op) != STACK_PUSH_CODE) | |
1181 | return 0; | |
1182 | ||
1183 | return XEXP (op, 0) == stack_pointer_rtx; | |
1184 | } | |
1185 | ||
6fbe9bd8 RH |
1186 | /* Return 1 if OP is a valid operand that stands for popping a |
1187 | value of mode MODE off the stack. | |
1188 | ||
1189 | The main use of this function is as a predicate in match_operand | |
1190 | expressions in the machine description. */ | |
1191 | ||
1192 | int | |
1193 | pop_operand (op, mode) | |
1194 | rtx op; | |
1195 | enum machine_mode mode; | |
1196 | { | |
1197 | if (GET_CODE (op) != MEM) | |
1198 | return 0; | |
1199 | ||
aeb7ff68 | 1200 | if (mode != VOIDmode && GET_MODE (op) != mode) |
6fbe9bd8 RH |
1201 | return 0; |
1202 | ||
1203 | op = XEXP (op, 0); | |
1204 | ||
1205 | if (GET_CODE (op) != STACK_POP_CODE) | |
1206 | return 0; | |
1207 | ||
1208 | return XEXP (op, 0) == stack_pointer_rtx; | |
1209 | } | |
1210 | ||
2055cea7 RK |
1211 | /* Return 1 if ADDR is a valid memory address for mode MODE. */ |
1212 | ||
1213 | int | |
1214 | memory_address_p (mode, addr) | |
1215 | enum machine_mode mode; | |
1216 | register rtx addr; | |
1217 | { | |
38a448ca RH |
1218 | if (GET_CODE (addr) == ADDRESSOF) |
1219 | return 1; | |
1220 | ||
2055cea7 RK |
1221 | GO_IF_LEGITIMATE_ADDRESS (mode, addr, win); |
1222 | return 0; | |
1223 | ||
1224 | win: | |
1225 | return 1; | |
1226 | } | |
1227 | ||
1228 | /* Return 1 if OP is a valid memory reference with mode MODE, | |
1229 | including a valid address. | |
1230 | ||
1231 | The main use of this function is as a predicate in match_operand | |
1232 | expressions in the machine description. */ | |
1233 | ||
1234 | int | |
1235 | memory_operand (op, mode) | |
1236 | register rtx op; | |
1237 | enum machine_mode mode; | |
1238 | { | |
1239 | rtx inner; | |
1240 | ||
1241 | if (! reload_completed) | |
1242 | /* Note that no SUBREG is a memory operand before end of reload pass, | |
1243 | because (SUBREG (MEM...)) forces reloading into a register. */ | |
1244 | return GET_CODE (op) == MEM && general_operand (op, mode); | |
1245 | ||
1246 | if (mode != VOIDmode && GET_MODE (op) != mode) | |
1247 | return 0; | |
1248 | ||
1249 | inner = op; | |
1250 | if (GET_CODE (inner) == SUBREG) | |
1251 | inner = SUBREG_REG (inner); | |
1252 | ||
1253 | return (GET_CODE (inner) == MEM && general_operand (op, mode)); | |
1254 | } | |
1255 | ||
1256 | /* Return 1 if OP is a valid indirect memory reference with mode MODE; | |
1257 | that is, a memory reference whose address is a general_operand. */ | |
1258 | ||
1259 | int | |
1260 | indirect_operand (op, mode) | |
1261 | register rtx op; | |
1262 | enum machine_mode mode; | |
1263 | { | |
1264 | /* Before reload, a SUBREG isn't in memory (see memory_operand, above). */ | |
1265 | if (! reload_completed | |
1266 | && GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == MEM) | |
1267 | { | |
1268 | register int offset = SUBREG_WORD (op) * UNITS_PER_WORD; | |
1269 | rtx inner = SUBREG_REG (op); | |
1270 | ||
f76b9db2 ILT |
1271 | if (BYTES_BIG_ENDIAN) |
1272 | offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (op))) | |
1273 | - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (inner)))); | |
2055cea7 | 1274 | |
b0e0a0f9 RK |
1275 | if (mode != VOIDmode && GET_MODE (op) != mode) |
1276 | return 0; | |
1277 | ||
2055cea7 RK |
1278 | /* The only way that we can have a general_operand as the resulting |
1279 | address is if OFFSET is zero and the address already is an operand | |
1280 | or if the address is (plus Y (const_int -OFFSET)) and Y is an | |
1281 | operand. */ | |
1282 | ||
1283 | return ((offset == 0 && general_operand (XEXP (inner, 0), Pmode)) | |
1284 | || (GET_CODE (XEXP (inner, 0)) == PLUS | |
1285 | && GET_CODE (XEXP (XEXP (inner, 0), 1)) == CONST_INT | |
1286 | && INTVAL (XEXP (XEXP (inner, 0), 1)) == -offset | |
1287 | && general_operand (XEXP (XEXP (inner, 0), 0), Pmode))); | |
1288 | } | |
1289 | ||
1290 | return (GET_CODE (op) == MEM | |
1291 | && memory_operand (op, mode) | |
1292 | && general_operand (XEXP (op, 0), Pmode)); | |
1293 | } | |
1294 | ||
1295 | /* Return 1 if this is a comparison operator. This allows the use of | |
1296 | MATCH_OPERATOR to recognize all the branch insns. */ | |
1297 | ||
1298 | int | |
1299 | comparison_operator (op, mode) | |
1300 | register rtx op; | |
1301 | enum machine_mode mode; | |
1302 | { | |
1303 | return ((mode == VOIDmode || GET_MODE (op) == mode) | |
1304 | && GET_RTX_CLASS (GET_CODE (op)) == '<'); | |
1305 | } | |
1306 | \f | |
1307 | /* If BODY is an insn body that uses ASM_OPERANDS, | |
1308 | return the number of operands (both input and output) in the insn. | |
1309 | Otherwise return -1. */ | |
1310 | ||
1311 | int | |
1312 | asm_noperands (body) | |
1313 | rtx body; | |
1314 | { | |
1315 | if (GET_CODE (body) == ASM_OPERANDS) | |
1316 | /* No output operands: return number of input operands. */ | |
1317 | return ASM_OPERANDS_INPUT_LENGTH (body); | |
1318 | if (GET_CODE (body) == SET && GET_CODE (SET_SRC (body)) == ASM_OPERANDS) | |
1319 | /* Single output operand: BODY is (set OUTPUT (asm_operands ...)). */ | |
1320 | return ASM_OPERANDS_INPUT_LENGTH (SET_SRC (body)) + 1; | |
1321 | else if (GET_CODE (body) == PARALLEL | |
1322 | && GET_CODE (XVECEXP (body, 0, 0)) == SET | |
1323 | && GET_CODE (SET_SRC (XVECEXP (body, 0, 0))) == ASM_OPERANDS) | |
1324 | { | |
1325 | /* Multiple output operands, or 1 output plus some clobbers: | |
1326 | body is [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */ | |
1327 | int i; | |
1328 | int n_sets; | |
1329 | ||
1330 | /* Count backwards through CLOBBERs to determine number of SETs. */ | |
1331 | for (i = XVECLEN (body, 0); i > 0; i--) | |
1332 | { | |
1333 | if (GET_CODE (XVECEXP (body, 0, i - 1)) == SET) | |
1334 | break; | |
1335 | if (GET_CODE (XVECEXP (body, 0, i - 1)) != CLOBBER) | |
1336 | return -1; | |
1337 | } | |
1338 | ||
1339 | /* N_SETS is now number of output operands. */ | |
1340 | n_sets = i; | |
1341 | ||
1342 | /* Verify that all the SETs we have | |
1343 | came from a single original asm_operands insn | |
1344 | (so that invalid combinations are blocked). */ | |
1345 | for (i = 0; i < n_sets; i++) | |
1346 | { | |
1347 | rtx elt = XVECEXP (body, 0, i); | |
1348 | if (GET_CODE (elt) != SET) | |
1349 | return -1; | |
1350 | if (GET_CODE (SET_SRC (elt)) != ASM_OPERANDS) | |
1351 | return -1; | |
1352 | /* If these ASM_OPERANDS rtx's came from different original insns | |
1353 | then they aren't allowed together. */ | |
1354 | if (ASM_OPERANDS_INPUT_VEC (SET_SRC (elt)) | |
1355 | != ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (body, 0, 0)))) | |
1356 | return -1; | |
1357 | } | |
1358 | return (ASM_OPERANDS_INPUT_LENGTH (SET_SRC (XVECEXP (body, 0, 0))) | |
1359 | + n_sets); | |
1360 | } | |
1361 | else if (GET_CODE (body) == PARALLEL | |
1362 | && GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS) | |
1363 | { | |
1364 | /* 0 outputs, but some clobbers: | |
1365 | body is [(asm_operands ...) (clobber (reg ...))...]. */ | |
1366 | int i; | |
1367 | ||
1368 | /* Make sure all the other parallel things really are clobbers. */ | |
1369 | for (i = XVECLEN (body, 0) - 1; i > 0; i--) | |
1370 | if (GET_CODE (XVECEXP (body, 0, i)) != CLOBBER) | |
1371 | return -1; | |
1372 | ||
1373 | return ASM_OPERANDS_INPUT_LENGTH (XVECEXP (body, 0, 0)); | |
1374 | } | |
1375 | else | |
1376 | return -1; | |
1377 | } | |
1378 | ||
1379 | /* Assuming BODY is an insn body that uses ASM_OPERANDS, | |
1380 | copy its operands (both input and output) into the vector OPERANDS, | |
1381 | the locations of the operands within the insn into the vector OPERAND_LOCS, | |
1382 | and the constraints for the operands into CONSTRAINTS. | |
1383 | Write the modes of the operands into MODES. | |
1384 | Return the assembler-template. | |
1385 | ||
1386 | If MODES, OPERAND_LOCS, CONSTRAINTS or OPERANDS is 0, | |
1387 | we don't store that info. */ | |
1388 | ||
1389 | char * | |
1390 | decode_asm_operands (body, operands, operand_locs, constraints, modes) | |
1391 | rtx body; | |
1392 | rtx *operands; | |
1393 | rtx **operand_locs; | |
9b3142b3 | 1394 | const char **constraints; |
2055cea7 RK |
1395 | enum machine_mode *modes; |
1396 | { | |
1397 | register int i; | |
1398 | int noperands; | |
1399 | char *template = 0; | |
1400 | ||
1401 | if (GET_CODE (body) == SET && GET_CODE (SET_SRC (body)) == ASM_OPERANDS) | |
1402 | { | |
1403 | rtx asmop = SET_SRC (body); | |
1404 | /* Single output operand: BODY is (set OUTPUT (asm_operands ....)). */ | |
1405 | ||
1406 | noperands = ASM_OPERANDS_INPUT_LENGTH (asmop) + 1; | |
1407 | ||
1408 | for (i = 1; i < noperands; i++) | |
1409 | { | |
1410 | if (operand_locs) | |
1411 | operand_locs[i] = &ASM_OPERANDS_INPUT (asmop, i - 1); | |
1412 | if (operands) | |
1413 | operands[i] = ASM_OPERANDS_INPUT (asmop, i - 1); | |
1414 | if (constraints) | |
1415 | constraints[i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i - 1); | |
1416 | if (modes) | |
1417 | modes[i] = ASM_OPERANDS_INPUT_MODE (asmop, i - 1); | |
1418 | } | |
1419 | ||
1420 | /* The output is in the SET. | |
1421 | Its constraint is in the ASM_OPERANDS itself. */ | |
1422 | if (operands) | |
1423 | operands[0] = SET_DEST (body); | |
1424 | if (operand_locs) | |
1425 | operand_locs[0] = &SET_DEST (body); | |
1426 | if (constraints) | |
1427 | constraints[0] = ASM_OPERANDS_OUTPUT_CONSTRAINT (asmop); | |
1428 | if (modes) | |
1429 | modes[0] = GET_MODE (SET_DEST (body)); | |
1430 | template = ASM_OPERANDS_TEMPLATE (asmop); | |
1431 | } | |
1432 | else if (GET_CODE (body) == ASM_OPERANDS) | |
1433 | { | |
1434 | rtx asmop = body; | |
1435 | /* No output operands: BODY is (asm_operands ....). */ | |
1436 | ||
1437 | noperands = ASM_OPERANDS_INPUT_LENGTH (asmop); | |
1438 | ||
1439 | /* The input operands are found in the 1st element vector. */ | |
1440 | /* Constraints for inputs are in the 2nd element vector. */ | |
1441 | for (i = 0; i < noperands; i++) | |
1442 | { | |
1443 | if (operand_locs) | |
1444 | operand_locs[i] = &ASM_OPERANDS_INPUT (asmop, i); | |
1445 | if (operands) | |
1446 | operands[i] = ASM_OPERANDS_INPUT (asmop, i); | |
1447 | if (constraints) | |
1448 | constraints[i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i); | |
1449 | if (modes) | |
1450 | modes[i] = ASM_OPERANDS_INPUT_MODE (asmop, i); | |
1451 | } | |
1452 | template = ASM_OPERANDS_TEMPLATE (asmop); | |
1453 | } | |
1454 | else if (GET_CODE (body) == PARALLEL | |
1455 | && GET_CODE (XVECEXP (body, 0, 0)) == SET) | |
1456 | { | |
1457 | rtx asmop = SET_SRC (XVECEXP (body, 0, 0)); | |
1458 | int nparallel = XVECLEN (body, 0); /* Includes CLOBBERs. */ | |
1459 | int nin = ASM_OPERANDS_INPUT_LENGTH (asmop); | |
1460 | int nout = 0; /* Does not include CLOBBERs. */ | |
1461 | ||
1462 | /* At least one output, plus some CLOBBERs. */ | |
1463 | ||
1464 | /* The outputs are in the SETs. | |
1465 | Their constraints are in the ASM_OPERANDS itself. */ | |
1466 | for (i = 0; i < nparallel; i++) | |
1467 | { | |
1468 | if (GET_CODE (XVECEXP (body, 0, i)) == CLOBBER) | |
1469 | break; /* Past last SET */ | |
1470 | ||
1471 | if (operands) | |
1472 | operands[i] = SET_DEST (XVECEXP (body, 0, i)); | |
1473 | if (operand_locs) | |
1474 | operand_locs[i] = &SET_DEST (XVECEXP (body, 0, i)); | |
1475 | if (constraints) | |
1476 | constraints[i] = XSTR (SET_SRC (XVECEXP (body, 0, i)), 1); | |
1477 | if (modes) | |
1478 | modes[i] = GET_MODE (SET_DEST (XVECEXP (body, 0, i))); | |
1479 | nout++; | |
1480 | } | |
1481 | ||
1482 | for (i = 0; i < nin; i++) | |
1483 | { | |
1484 | if (operand_locs) | |
1485 | operand_locs[i + nout] = &ASM_OPERANDS_INPUT (asmop, i); | |
1486 | if (operands) | |
1487 | operands[i + nout] = ASM_OPERANDS_INPUT (asmop, i); | |
1488 | if (constraints) | |
1489 | constraints[i + nout] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i); | |
1490 | if (modes) | |
1491 | modes[i + nout] = ASM_OPERANDS_INPUT_MODE (asmop, i); | |
1492 | } | |
1493 | ||
1494 | template = ASM_OPERANDS_TEMPLATE (asmop); | |
1495 | } | |
1496 | else if (GET_CODE (body) == PARALLEL | |
1497 | && GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS) | |
1498 | { | |
1499 | /* No outputs, but some CLOBBERs. */ | |
1500 | ||
1501 | rtx asmop = XVECEXP (body, 0, 0); | |
1502 | int nin = ASM_OPERANDS_INPUT_LENGTH (asmop); | |
1503 | ||
1504 | for (i = 0; i < nin; i++) | |
1505 | { | |
1506 | if (operand_locs) | |
1507 | operand_locs[i] = &ASM_OPERANDS_INPUT (asmop, i); | |
1508 | if (operands) | |
1509 | operands[i] = ASM_OPERANDS_INPUT (asmop, i); | |
1510 | if (constraints) | |
1511 | constraints[i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i); | |
1512 | if (modes) | |
1513 | modes[i] = ASM_OPERANDS_INPUT_MODE (asmop, i); | |
1514 | } | |
1515 | ||
1516 | template = ASM_OPERANDS_TEMPLATE (asmop); | |
1517 | } | |
1518 | ||
1519 | return template; | |
1520 | } | |
1f06ee8d | 1521 | |
1afbe1c4 RH |
1522 | /* Check if an asm_operand matches it's constraints. |
1523 | Return > 0 if ok, = 0 if bad, < 0 if inconclusive. */ | |
1f06ee8d RH |
1524 | |
1525 | int | |
1526 | asm_operand_ok (op, constraint) | |
1527 | rtx op; | |
1528 | const char *constraint; | |
1529 | { | |
1afbe1c4 RH |
1530 | int result = 0; |
1531 | ||
1f06ee8d RH |
1532 | /* Use constrain_operands after reload. */ |
1533 | if (reload_completed) | |
1534 | abort (); | |
1535 | ||
1536 | while (*constraint) | |
1537 | { | |
1538 | switch (*constraint++) | |
1539 | { | |
1540 | case '=': | |
1541 | case '+': | |
1542 | case '*': | |
1543 | case '%': | |
1544 | case '?': | |
1545 | case '!': | |
1546 | case '#': | |
1547 | case '&': | |
1548 | case ',': | |
1549 | break; | |
1550 | ||
1551 | case '0': case '1': case '2': case '3': case '4': | |
1552 | case '5': case '6': case '7': case '8': case '9': | |
1afbe1c4 RH |
1553 | /* For best results, our caller should have given us the |
1554 | proper matching constraint, but we can't actually fail | |
1555 | the check if they didn't. Indicate that results are | |
1556 | inconclusive. */ | |
1557 | result = -1; | |
1f06ee8d RH |
1558 | break; |
1559 | ||
1560 | case 'p': | |
1561 | if (address_operand (op, VOIDmode)) | |
1562 | return 1; | |
1563 | break; | |
1564 | ||
1565 | case 'm': | |
1566 | case 'V': /* non-offsettable */ | |
1567 | if (memory_operand (op, VOIDmode)) | |
1568 | return 1; | |
1569 | break; | |
1570 | ||
1571 | case 'o': /* offsettable */ | |
1572 | if (offsettable_nonstrict_memref_p (op)) | |
1573 | return 1; | |
1574 | break; | |
1575 | ||
1576 | case '<': | |
1afbe1c4 RH |
1577 | /* ??? Before flow, auto inc/dec insns are not supposed to exist, |
1578 | excepting those that expand_call created. Further, on some | |
1579 | machines which do not have generalized auto inc/dec, an inc/dec | |
1580 | is not a memory_operand. | |
1581 | ||
1582 | Match any memory and hope things are resolved after reload. */ | |
1583 | ||
1f06ee8d | 1584 | if (GET_CODE (op) == MEM |
1afbe1c4 RH |
1585 | && (1 |
1586 | || GET_CODE (XEXP (op, 0)) == PRE_DEC | |
1f06ee8d RH |
1587 | || GET_CODE (XEXP (op, 0)) == POST_DEC)) |
1588 | return 1; | |
1589 | break; | |
1590 | ||
1591 | case '>': | |
1592 | if (GET_CODE (op) == MEM | |
1afbe1c4 RH |
1593 | && (1 |
1594 | || GET_CODE (XEXP (op, 0)) == PRE_INC | |
1f06ee8d RH |
1595 | || GET_CODE (XEXP (op, 0)) == POST_INC)) |
1596 | return 1; | |
1597 | break; | |
1598 | ||
1599 | case 'E': | |
1600 | #ifndef REAL_ARITHMETIC | |
1601 | /* Match any floating double constant, but only if | |
1602 | we can examine the bits of it reliably. */ | |
1603 | if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT | |
1604 | || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD) | |
1605 | && GET_MODE (op) != VOIDmode && ! flag_pretend_float) | |
1606 | break; | |
1607 | #endif | |
1608 | /* FALLTHRU */ | |
1609 | ||
1610 | case 'F': | |
1611 | if (GET_CODE (op) == CONST_DOUBLE) | |
1612 | return 1; | |
1613 | break; | |
1614 | ||
1615 | case 'G': | |
1616 | if (GET_CODE (op) == CONST_DOUBLE | |
1617 | && CONST_DOUBLE_OK_FOR_LETTER_P (op, 'G')) | |
1618 | return 1; | |
1619 | break; | |
1620 | case 'H': | |
1621 | if (GET_CODE (op) == CONST_DOUBLE | |
1622 | && CONST_DOUBLE_OK_FOR_LETTER_P (op, 'H')) | |
1623 | return 1; | |
1624 | break; | |
1625 | ||
1626 | case 's': | |
1627 | if (GET_CODE (op) == CONST_INT | |
1628 | || (GET_CODE (op) == CONST_DOUBLE | |
1629 | && GET_MODE (op) == VOIDmode)) | |
1630 | break; | |
1631 | /* FALLTHRU */ | |
1632 | ||
1633 | case 'i': | |
1634 | if (CONSTANT_P (op) | |
1635 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
1636 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) | |
1637 | #endif | |
1638 | ) | |
1639 | return 1; | |
1640 | break; | |
1641 | ||
1642 | case 'n': | |
1643 | if (GET_CODE (op) == CONST_INT | |
1644 | || (GET_CODE (op) == CONST_DOUBLE | |
1645 | && GET_MODE (op) == VOIDmode)) | |
1646 | return 1; | |
1647 | break; | |
1648 | ||
1649 | case 'I': | |
1650 | if (GET_CODE (op) == CONST_INT | |
1651 | && CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')) | |
1652 | return 1; | |
1653 | break; | |
1654 | case 'J': | |
1655 | if (GET_CODE (op) == CONST_INT | |
1656 | && CONST_OK_FOR_LETTER_P (INTVAL (op), 'J')) | |
1657 | return 1; | |
1658 | break; | |
1659 | case 'K': | |
1660 | if (GET_CODE (op) == CONST_INT | |
1661 | && CONST_OK_FOR_LETTER_P (INTVAL (op), 'K')) | |
1662 | return 1; | |
1663 | break; | |
1664 | case 'L': | |
1665 | if (GET_CODE (op) == CONST_INT | |
1666 | && CONST_OK_FOR_LETTER_P (INTVAL (op), 'L')) | |
1667 | return 1; | |
1668 | break; | |
1669 | case 'M': | |
1670 | if (GET_CODE (op) == CONST_INT | |
1671 | && CONST_OK_FOR_LETTER_P (INTVAL (op), 'M')) | |
1672 | return 1; | |
1673 | break; | |
1674 | case 'N': | |
1675 | if (GET_CODE (op) == CONST_INT | |
1676 | && CONST_OK_FOR_LETTER_P (INTVAL (op), 'N')) | |
1677 | return 1; | |
1678 | break; | |
1679 | case 'O': | |
1680 | if (GET_CODE (op) == CONST_INT | |
1681 | && CONST_OK_FOR_LETTER_P (INTVAL (op), 'O')) | |
1682 | return 1; | |
1683 | break; | |
1684 | case 'P': | |
1685 | if (GET_CODE (op) == CONST_INT | |
1686 | && CONST_OK_FOR_LETTER_P (INTVAL (op), 'P')) | |
1687 | return 1; | |
1688 | break; | |
1689 | ||
1690 | case 'X': | |
1691 | return 1; | |
1692 | ||
1693 | case 'g': | |
1694 | if (general_operand (op, VOIDmode)) | |
1695 | return 1; | |
1696 | break; | |
1697 | ||
1698 | #ifdef EXTRA_CONSTRAINT | |
1699 | case 'Q': | |
1700 | if (EXTRA_CONSTRAINT (op, 'Q')) | |
1701 | return 1; | |
1702 | break; | |
1703 | case 'R': | |
1704 | if (EXTRA_CONSTRAINT (op, 'R')) | |
1705 | return 1; | |
1706 | break; | |
1707 | case 'S': | |
1708 | if (EXTRA_CONSTRAINT (op, 'S')) | |
1709 | return 1; | |
1710 | break; | |
1711 | case 'T': | |
1712 | if (EXTRA_CONSTRAINT (op, 'T')) | |
1713 | return 1; | |
1714 | break; | |
1715 | case 'U': | |
1716 | if (EXTRA_CONSTRAINT (op, 'U')) | |
1717 | return 1; | |
1718 | break; | |
1719 | #endif | |
1720 | ||
1721 | case 'r': | |
1722 | default: | |
1723 | if (GET_MODE (op) == BLKmode) | |
1724 | break; | |
1725 | if (register_operand (op, VOIDmode)) | |
1726 | return 1; | |
1727 | break; | |
1728 | } | |
1729 | } | |
1730 | ||
1afbe1c4 | 1731 | return result; |
1f06ee8d | 1732 | } |
2055cea7 | 1733 | \f |
2055cea7 RK |
1734 | /* Given an rtx *P, if it is a sum containing an integer constant term, |
1735 | return the location (type rtx *) of the pointer to that constant term. | |
1736 | Otherwise, return a null pointer. */ | |
1737 | ||
1738 | static rtx * | |
1739 | find_constant_term_loc (p) | |
1740 | rtx *p; | |
1741 | { | |
1742 | register rtx *tem; | |
1743 | register enum rtx_code code = GET_CODE (*p); | |
1744 | ||
1745 | /* If *P IS such a constant term, P is its location. */ | |
1746 | ||
1747 | if (code == CONST_INT || code == SYMBOL_REF || code == LABEL_REF | |
1748 | || code == CONST) | |
1749 | return p; | |
1750 | ||
1751 | /* Otherwise, if not a sum, it has no constant term. */ | |
1752 | ||
1753 | if (GET_CODE (*p) != PLUS) | |
1754 | return 0; | |
1755 | ||
1756 | /* If one of the summands is constant, return its location. */ | |
1757 | ||
1758 | if (XEXP (*p, 0) && CONSTANT_P (XEXP (*p, 0)) | |
1759 | && XEXP (*p, 1) && CONSTANT_P (XEXP (*p, 1))) | |
1760 | return p; | |
1761 | ||
1762 | /* Otherwise, check each summand for containing a constant term. */ | |
1763 | ||
1764 | if (XEXP (*p, 0) != 0) | |
1765 | { | |
1766 | tem = find_constant_term_loc (&XEXP (*p, 0)); | |
1767 | if (tem != 0) | |
1768 | return tem; | |
1769 | } | |
1770 | ||
1771 | if (XEXP (*p, 1) != 0) | |
1772 | { | |
1773 | tem = find_constant_term_loc (&XEXP (*p, 1)); | |
1774 | if (tem != 0) | |
1775 | return tem; | |
1776 | } | |
1777 | ||
1778 | return 0; | |
1779 | } | |
1780 | \f | |
1781 | /* Return 1 if OP is a memory reference | |
1782 | whose address contains no side effects | |
1783 | and remains valid after the addition | |
1784 | of a positive integer less than the | |
1785 | size of the object being referenced. | |
1786 | ||
1787 | We assume that the original address is valid and do not check it. | |
1788 | ||
1789 | This uses strict_memory_address_p as a subroutine, so | |
1790 | don't use it before reload. */ | |
1791 | ||
1792 | int | |
1793 | offsettable_memref_p (op) | |
1794 | rtx op; | |
1795 | { | |
1796 | return ((GET_CODE (op) == MEM) | |
1797 | && offsettable_address_p (1, GET_MODE (op), XEXP (op, 0))); | |
1798 | } | |
1799 | ||
1800 | /* Similar, but don't require a strictly valid mem ref: | |
1801 | consider pseudo-regs valid as index or base regs. */ | |
1802 | ||
1803 | int | |
1804 | offsettable_nonstrict_memref_p (op) | |
1805 | rtx op; | |
1806 | { | |
1807 | return ((GET_CODE (op) == MEM) | |
1808 | && offsettable_address_p (0, GET_MODE (op), XEXP (op, 0))); | |
1809 | } | |
1810 | ||
1811 | /* Return 1 if Y is a memory address which contains no side effects | |
1812 | and would remain valid after the addition of a positive integer | |
1813 | less than the size of that mode. | |
1814 | ||
1815 | We assume that the original address is valid and do not check it. | |
1816 | We do check that it is valid for narrower modes. | |
1817 | ||
1818 | If STRICTP is nonzero, we require a strictly valid address, | |
1819 | for the sake of use in reload.c. */ | |
1820 | ||
1821 | int | |
1822 | offsettable_address_p (strictp, mode, y) | |
1823 | int strictp; | |
1824 | enum machine_mode mode; | |
1825 | register rtx y; | |
1826 | { | |
1827 | register enum rtx_code ycode = GET_CODE (y); | |
1828 | register rtx z; | |
1829 | rtx y1 = y; | |
1830 | rtx *y2; | |
1831 | int (*addressp) () = (strictp ? strict_memory_address_p : memory_address_p); | |
1832 | ||
1833 | if (CONSTANT_ADDRESS_P (y)) | |
1834 | return 1; | |
1835 | ||
1836 | /* Adjusting an offsettable address involves changing to a narrower mode. | |
1837 | Make sure that's OK. */ | |
1838 | ||
1839 | if (mode_dependent_address_p (y)) | |
1840 | return 0; | |
1841 | ||
1842 | /* If the expression contains a constant term, | |
1843 | see if it remains valid when max possible offset is added. */ | |
1844 | ||
1845 | if ((ycode == PLUS) && (y2 = find_constant_term_loc (&y1))) | |
1846 | { | |
1847 | int good; | |
1848 | ||
1849 | y1 = *y2; | |
1850 | *y2 = plus_constant (*y2, GET_MODE_SIZE (mode) - 1); | |
1851 | /* Use QImode because an odd displacement may be automatically invalid | |
1852 | for any wider mode. But it should be valid for a single byte. */ | |
1853 | good = (*addressp) (QImode, y); | |
1854 | ||
1855 | /* In any case, restore old contents of memory. */ | |
1856 | *y2 = y1; | |
1857 | return good; | |
1858 | } | |
1859 | ||
1860 | if (ycode == PRE_DEC || ycode == PRE_INC | |
1861 | || ycode == POST_DEC || ycode == POST_INC) | |
1862 | return 0; | |
1863 | ||
1864 | /* The offset added here is chosen as the maximum offset that | |
1865 | any instruction could need to add when operating on something | |
1866 | of the specified mode. We assume that if Y and Y+c are | |
1867 | valid addresses then so is Y+d for all 0<d<c. */ | |
1868 | ||
1869 | z = plus_constant_for_output (y, GET_MODE_SIZE (mode) - 1); | |
1870 | ||
1871 | /* Use QImode because an odd displacement may be automatically invalid | |
1872 | for any wider mode. But it should be valid for a single byte. */ | |
1873 | return (*addressp) (QImode, z); | |
1874 | } | |
1875 | ||
1876 | /* Return 1 if ADDR is an address-expression whose effect depends | |
1877 | on the mode of the memory reference it is used in. | |
1878 | ||
1879 | Autoincrement addressing is a typical example of mode-dependence | |
1880 | because the amount of the increment depends on the mode. */ | |
1881 | ||
1882 | int | |
1883 | mode_dependent_address_p (addr) | |
47c3ed98 | 1884 | rtx addr ATTRIBUTE_UNUSED; /* Maybe used in GO_IF_MODE_DEPENDENT_ADDRESS. */ |
2055cea7 RK |
1885 | { |
1886 | GO_IF_MODE_DEPENDENT_ADDRESS (addr, win); | |
1887 | return 0; | |
47c3ed98 KG |
1888 | /* Label `win' might (not) be used via GO_IF_MODE_DEPENDENT_ADDRESS. */ |
1889 | win: ATTRIBUTE_UNUSED_LABEL | |
2055cea7 RK |
1890 | return 1; |
1891 | } | |
1892 | ||
1893 | /* Return 1 if OP is a general operand | |
1894 | other than a memory ref with a mode dependent address. */ | |
1895 | ||
1896 | int | |
1897 | mode_independent_operand (op, mode) | |
1898 | enum machine_mode mode; | |
1899 | rtx op; | |
1900 | { | |
1901 | rtx addr; | |
1902 | ||
1903 | if (! general_operand (op, mode)) | |
1904 | return 0; | |
1905 | ||
1906 | if (GET_CODE (op) != MEM) | |
1907 | return 1; | |
1908 | ||
1909 | addr = XEXP (op, 0); | |
1910 | GO_IF_MODE_DEPENDENT_ADDRESS (addr, lose); | |
1911 | return 1; | |
47c3ed98 KG |
1912 | /* Label `lose' might (not) be used via GO_IF_MODE_DEPENDENT_ADDRESS. */ |
1913 | lose: ATTRIBUTE_UNUSED_LABEL | |
2055cea7 RK |
1914 | return 0; |
1915 | } | |
1916 | ||
1917 | /* Given an operand OP that is a valid memory reference | |
1918 | which satisfies offsettable_memref_p, | |
1919 | return a new memory reference whose address has been adjusted by OFFSET. | |
1920 | OFFSET should be positive and less than the size of the object referenced. | |
1921 | */ | |
1922 | ||
1923 | rtx | |
1924 | adj_offsettable_operand (op, offset) | |
1925 | rtx op; | |
1926 | int offset; | |
1927 | { | |
1928 | register enum rtx_code code = GET_CODE (op); | |
1929 | ||
1930 | if (code == MEM) | |
1931 | { | |
1932 | register rtx y = XEXP (op, 0); | |
1933 | register rtx new; | |
1934 | ||
1935 | if (CONSTANT_ADDRESS_P (y)) | |
1936 | { | |
c5c76735 JL |
1937 | new = gen_rtx_MEM (GET_MODE (op), |
1938 | plus_constant_for_output (y, offset)); | |
2055cea7 RK |
1939 | RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (op); |
1940 | return new; | |
1941 | } | |
1942 | ||
1943 | if (GET_CODE (y) == PLUS) | |
1944 | { | |
1945 | rtx z = y; | |
1946 | register rtx *const_loc; | |
1947 | ||
1948 | op = copy_rtx (op); | |
1949 | z = XEXP (op, 0); | |
1950 | const_loc = find_constant_term_loc (&z); | |
1951 | if (const_loc) | |
1952 | { | |
1953 | *const_loc = plus_constant_for_output (*const_loc, offset); | |
1954 | return op; | |
1955 | } | |
1956 | } | |
1957 | ||
38a448ca | 1958 | new = gen_rtx_MEM (GET_MODE (op), plus_constant_for_output (y, offset)); |
2055cea7 RK |
1959 | RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (op); |
1960 | return new; | |
1961 | } | |
1962 | abort (); | |
1963 | } | |
1964 | \f | |
1ccbefce RH |
1965 | /* Analyze INSN and fill in recog_data. */ |
1966 | ||
0a578fee BS |
1967 | void |
1968 | extract_insn (insn) | |
1969 | rtx insn; | |
1970 | { | |
1971 | int i; | |
1972 | int icode; | |
1973 | int noperands; | |
1974 | rtx body = PATTERN (insn); | |
1975 | ||
1ccbefce RH |
1976 | recog_data.n_operands = 0; |
1977 | recog_data.n_alternatives = 0; | |
1978 | recog_data.n_dups = 0; | |
0a578fee BS |
1979 | |
1980 | switch (GET_CODE (body)) | |
1981 | { | |
1982 | case USE: | |
1983 | case CLOBBER: | |
1984 | case ASM_INPUT: | |
1985 | case ADDR_VEC: | |
1986 | case ADDR_DIFF_VEC: | |
1987 | return; | |
1988 | ||
1989 | case SET: | |
1990 | case PARALLEL: | |
1991 | case ASM_OPERANDS: | |
1ccbefce | 1992 | recog_data.n_operands = noperands = asm_noperands (body); |
0a578fee BS |
1993 | if (noperands >= 0) |
1994 | { | |
0a578fee BS |
1995 | /* This insn is an `asm' with operands. */ |
1996 | ||
1997 | /* expand_asm_operands makes sure there aren't too many operands. */ | |
1998 | if (noperands > MAX_RECOG_OPERANDS) | |
1999 | abort (); | |
2000 | ||
2001 | /* Now get the operand values and constraints out of the insn. */ | |
1ccbefce RH |
2002 | decode_asm_operands (body, recog_data.operand, |
2003 | recog_data.operand_loc, | |
2004 | recog_data.constraints, | |
2005 | recog_data.operand_mode); | |
0a578fee BS |
2006 | if (noperands > 0) |
2007 | { | |
1ccbefce RH |
2008 | const char *p = recog_data.constraints[0]; |
2009 | recog_data.n_alternatives = 1; | |
0a578fee | 2010 | while (*p) |
1ccbefce | 2011 | recog_data.n_alternatives += (*p++ == ','); |
0a578fee BS |
2012 | } |
2013 | #ifndef REGISTER_CONSTRAINTS | |
1ccbefce RH |
2014 | bzero (recog_data.operand_address_p, |
2015 | sizeof recog_data.operand_address_p); | |
0a578fee BS |
2016 | #endif |
2017 | break; | |
2018 | } | |
2019 | ||
2020 | /* FALLTHROUGH */ | |
2021 | ||
2022 | default: | |
2023 | /* Ordinary insn: recognize it, get the operands via insn_extract | |
2024 | and get the constraints. */ | |
2025 | ||
2026 | icode = recog_memoized (insn); | |
2027 | if (icode < 0) | |
2028 | fatal_insn_not_found (insn); | |
2029 | ||
a995e389 RH |
2030 | recog_data.n_operands = noperands = insn_data[icode].n_operands; |
2031 | recog_data.n_alternatives = insn_data[icode].n_alternatives; | |
2032 | recog_data.n_dups = insn_data[icode].n_dups; | |
0a578fee BS |
2033 | |
2034 | insn_extract (insn); | |
2035 | ||
2036 | for (i = 0; i < noperands; i++) | |
2037 | { | |
2038 | #ifdef REGISTER_CONSTRAINTS | |
a995e389 | 2039 | recog_data.constraints[i] = insn_data[icode].operand[i].constraint; |
0a578fee | 2040 | #else |
a995e389 RH |
2041 | recog_data.operand_address_p[i] |
2042 | = insn_data[icode].operand[i].address_p; | |
0a578fee | 2043 | #endif |
a995e389 | 2044 | recog_data.operand_mode[i] = insn_data[icode].operand[i].mode; |
0a578fee BS |
2045 | } |
2046 | } | |
0eadeb15 | 2047 | for (i = 0; i < noperands; i++) |
1ccbefce RH |
2048 | recog_data.operand_type[i] |
2049 | = (recog_data.constraints[i][0] == '=' ? OP_OUT | |
2050 | : recog_data.constraints[i][0] == '+' ? OP_INOUT | |
2051 | : OP_IN); | |
f62a15e3 | 2052 | |
1ccbefce | 2053 | if (recog_data.n_alternatives > MAX_RECOG_ALTERNATIVES) |
f62a15e3 | 2054 | abort (); |
0a578fee BS |
2055 | } |
2056 | ||
f62a15e3 BS |
2057 | /* After calling extract_insn, you can use this function to extract some |
2058 | information from the constraint strings into a more usable form. | |
2059 | The collected data is stored in recog_op_alt. */ | |
2060 | void | |
2061 | preprocess_constraints () | |
2062 | { | |
2063 | int i; | |
2064 | ||
cc3dea85 | 2065 | bzero (recog_op_alt, sizeof recog_op_alt); |
1ccbefce | 2066 | for (i = 0; i < recog_data.n_operands; i++) |
f62a15e3 BS |
2067 | { |
2068 | int j; | |
2069 | struct operand_alternative *op_alt; | |
1ccbefce | 2070 | const char *p = recog_data.constraints[i]; |
f62a15e3 BS |
2071 | |
2072 | op_alt = recog_op_alt[i]; | |
2073 | ||
1ccbefce | 2074 | for (j = 0; j < recog_data.n_alternatives; j++) |
f62a15e3 BS |
2075 | { |
2076 | op_alt[j].class = NO_REGS; | |
2077 | op_alt[j].constraint = p; | |
2078 | op_alt[j].matches = -1; | |
2079 | op_alt[j].matched = -1; | |
2080 | ||
2081 | if (*p == '\0' || *p == ',') | |
2082 | { | |
2083 | op_alt[j].anything_ok = 1; | |
2084 | continue; | |
2085 | } | |
2086 | ||
2087 | for (;;) | |
2088 | { | |
2089 | char c = *p++; | |
2090 | if (c == '#') | |
2091 | do | |
2092 | c = *p++; | |
2093 | while (c != ',' && c != '\0'); | |
2094 | if (c == ',' || c == '\0') | |
2095 | break; | |
2096 | ||
2097 | switch (c) | |
2098 | { | |
2099 | case '=': case '+': case '*': case '%': | |
2100 | case 'E': case 'F': case 'G': case 'H': | |
2101 | case 's': case 'i': case 'n': | |
2102 | case 'I': case 'J': case 'K': case 'L': | |
2103 | case 'M': case 'N': case 'O': case 'P': | |
2104 | #ifdef EXTRA_CONSTRAINT | |
2105 | case 'Q': case 'R': case 'S': case 'T': case 'U': | |
2106 | #endif | |
2107 | /* These don't say anything we care about. */ | |
2108 | break; | |
2109 | ||
2110 | case '?': | |
2111 | op_alt[j].reject += 6; | |
2112 | break; | |
2113 | case '!': | |
2114 | op_alt[j].reject += 600; | |
2115 | break; | |
2116 | case '&': | |
2117 | op_alt[j].earlyclobber = 1; | |
2118 | break; | |
2119 | ||
2120 | case '0': case '1': case '2': case '3': case '4': | |
2121 | case '5': case '6': case '7': case '8': case '9': | |
2122 | op_alt[j].matches = c - '0'; | |
2123 | op_alt[op_alt[j].matches].matched = i; | |
2124 | break; | |
2125 | ||
2126 | case 'm': | |
2127 | op_alt[j].memory_ok = 1; | |
2128 | break; | |
2129 | case '<': | |
2130 | op_alt[j].decmem_ok = 1; | |
2131 | break; | |
2132 | case '>': | |
2133 | op_alt[j].incmem_ok = 1; | |
2134 | break; | |
2135 | case 'V': | |
2136 | op_alt[j].nonoffmem_ok = 1; | |
2137 | break; | |
2138 | case 'o': | |
2139 | op_alt[j].offmem_ok = 1; | |
2140 | break; | |
2141 | case 'X': | |
2142 | op_alt[j].anything_ok = 1; | |
2143 | break; | |
2144 | ||
2145 | case 'p': | |
2146 | op_alt[j].class = reg_class_subunion[(int) op_alt[j].class][(int) BASE_REG_CLASS]; | |
2147 | break; | |
2148 | ||
2149 | case 'g': case 'r': | |
2150 | op_alt[j].class = reg_class_subunion[(int) op_alt[j].class][(int) GENERAL_REGS]; | |
2151 | break; | |
2152 | ||
2153 | default: | |
973838fd | 2154 | op_alt[j].class = reg_class_subunion[(int) op_alt[j].class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c)]; |
f62a15e3 BS |
2155 | break; |
2156 | } | |
2157 | } | |
2158 | } | |
2159 | } | |
2160 | } | |
2161 | ||
2055cea7 RK |
2162 | #ifdef REGISTER_CONSTRAINTS |
2163 | ||
0eadeb15 | 2164 | /* Check the operands of an insn against the insn's operand constraints |
2055cea7 | 2165 | and return 1 if they are valid. |
0eadeb15 BS |
2166 | The information about the insn's operands, constraints, operand modes |
2167 | etc. is obtained from the global variables set up by extract_insn. | |
2055cea7 RK |
2168 | |
2169 | WHICH_ALTERNATIVE is set to a number which indicates which | |
2170 | alternative of constraints was matched: 0 for the first alternative, | |
2171 | 1 for the next, etc. | |
2172 | ||
2173 | In addition, when two operands are match | |
2174 | and it happens that the output operand is (reg) while the | |
2175 | input operand is --(reg) or ++(reg) (a pre-inc or pre-dec), | |
2176 | make the output operand look like the input. | |
2177 | This is because the output operand is the one the template will print. | |
2178 | ||
2179 | This is used in final, just before printing the assembler code and by | |
2180 | the routines that determine an insn's attribute. | |
2181 | ||
2182 | If STRICT is a positive non-zero value, it means that we have been | |
2183 | called after reload has been completed. In that case, we must | |
2184 | do all checks strictly. If it is zero, it means that we have been called | |
2185 | before reload has completed. In that case, we first try to see if we can | |
2186 | find an alternative that matches strictly. If not, we try again, this | |
2187 | time assuming that reload will fix up the insn. This provides a "best | |
2188 | guess" for the alternative and is used to compute attributes of insns prior | |
2189 | to reload. A negative value of STRICT is used for this internal call. */ | |
2190 | ||
2191 | struct funny_match | |
2192 | { | |
2193 | int this, other; | |
2194 | }; | |
2195 | ||
2196 | int | |
0eadeb15 | 2197 | constrain_operands (strict) |
2055cea7 RK |
2198 | int strict; |
2199 | { | |
9b3142b3 | 2200 | const char *constraints[MAX_RECOG_OPERANDS]; |
9e21be9d | 2201 | int matching_operands[MAX_RECOG_OPERANDS]; |
9e21be9d | 2202 | int earlyclobber[MAX_RECOG_OPERANDS]; |
2055cea7 | 2203 | register int c; |
2055cea7 RK |
2204 | |
2205 | struct funny_match funny_match[MAX_RECOG_OPERANDS]; | |
2206 | int funny_match_index; | |
2055cea7 | 2207 | |
1ccbefce | 2208 | if (recog_data.n_operands == 0 || recog_data.n_alternatives == 0) |
2055cea7 RK |
2209 | return 1; |
2210 | ||
1ccbefce | 2211 | for (c = 0; c < recog_data.n_operands; c++) |
9e21be9d | 2212 | { |
1ccbefce | 2213 | constraints[c] = recog_data.constraints[c]; |
9e21be9d | 2214 | matching_operands[c] = -1; |
9e21be9d | 2215 | } |
2055cea7 RK |
2216 | |
2217 | which_alternative = 0; | |
2218 | ||
1ccbefce | 2219 | while (which_alternative < recog_data.n_alternatives) |
2055cea7 RK |
2220 | { |
2221 | register int opno; | |
2222 | int lose = 0; | |
2223 | funny_match_index = 0; | |
2224 | ||
1ccbefce | 2225 | for (opno = 0; opno < recog_data.n_operands; opno++) |
2055cea7 | 2226 | { |
1ccbefce | 2227 | register rtx op = recog_data.operand[opno]; |
2055cea7 | 2228 | enum machine_mode mode = GET_MODE (op); |
9b3142b3 | 2229 | register const char *p = constraints[opno]; |
2055cea7 RK |
2230 | int offset = 0; |
2231 | int win = 0; | |
2232 | int val; | |
2233 | ||
9e21be9d RK |
2234 | earlyclobber[opno] = 0; |
2235 | ||
b85f21c0 | 2236 | /* A unary operator may be accepted by the predicate, but it |
38a448ca | 2237 | is irrelevant for matching constraints. */ |
b85f21c0 ILT |
2238 | if (GET_RTX_CLASS (GET_CODE (op)) == '1') |
2239 | op = XEXP (op, 0); | |
2240 | ||
2055cea7 RK |
2241 | if (GET_CODE (op) == SUBREG) |
2242 | { | |
2243 | if (GET_CODE (SUBREG_REG (op)) == REG | |
2244 | && REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER) | |
2245 | offset = SUBREG_WORD (op); | |
2246 | op = SUBREG_REG (op); | |
2247 | } | |
2248 | ||
2249 | /* An empty constraint or empty alternative | |
2250 | allows anything which matched the pattern. */ | |
2251 | if (*p == 0 || *p == ',') | |
2252 | win = 1; | |
2253 | ||
2254 | while (*p && (c = *p++) != ',') | |
2255 | switch (c) | |
2256 | { | |
c5c76735 JL |
2257 | case '?': case '!': case '*': case '%': |
2258 | case '=': case '+': | |
2055cea7 RK |
2259 | break; |
2260 | ||
4d3067db RK |
2261 | case '#': |
2262 | /* Ignore rest of this alternative as far as | |
2263 | constraint checking is concerned. */ | |
2264 | while (*p && *p != ',') | |
2265 | p++; | |
2266 | break; | |
2267 | ||
9e21be9d RK |
2268 | case '&': |
2269 | earlyclobber[opno] = 1; | |
2270 | break; | |
2271 | ||
c5c76735 JL |
2272 | case '0': case '1': case '2': case '3': case '4': |
2273 | case '5': case '6': case '7': case '8': case '9': | |
2274 | ||
2055cea7 RK |
2275 | /* This operand must be the same as a previous one. |
2276 | This kind of constraint is used for instructions such | |
2277 | as add when they take only two operands. | |
2278 | ||
2279 | Note that the lower-numbered operand is passed first. | |
2280 | ||
2281 | If we are not testing strictly, assume that this constraint | |
2282 | will be satisfied. */ | |
2283 | if (strict < 0) | |
2284 | val = 1; | |
2285 | else | |
62674ffe | 2286 | { |
1ccbefce RH |
2287 | rtx op1 = recog_data.operand[c - '0']; |
2288 | rtx op2 = recog_data.operand[opno]; | |
62674ffe JH |
2289 | |
2290 | /* A unary operator may be accepted by the predicate, | |
2291 | but it is irrelevant for matching constraints. */ | |
2292 | if (GET_RTX_CLASS (GET_CODE (op1)) == '1') | |
2293 | op1 = XEXP (op1, 0); | |
2294 | if (GET_RTX_CLASS (GET_CODE (op2)) == '1') | |
2295 | op2 = XEXP (op2, 0); | |
2296 | ||
2297 | val = operands_match_p (op1, op2); | |
2298 | } | |
2055cea7 | 2299 | |
9e21be9d RK |
2300 | matching_operands[opno] = c - '0'; |
2301 | matching_operands[c - '0'] = opno; | |
2302 | ||
2055cea7 RK |
2303 | if (val != 0) |
2304 | win = 1; | |
2305 | /* If output is *x and input is *--x, | |
2306 | arrange later to change the output to *--x as well, | |
2307 | since the output op is the one that will be printed. */ | |
2308 | if (val == 2 && strict > 0) | |
2309 | { | |
2310 | funny_match[funny_match_index].this = opno; | |
2311 | funny_match[funny_match_index++].other = c - '0'; | |
2312 | } | |
2313 | break; | |
2314 | ||
2315 | case 'p': | |
2316 | /* p is used for address_operands. When we are called by | |
a8647766 RK |
2317 | gen_reload, no one will have checked that the address is |
2318 | strictly valid, i.e., that all pseudos requiring hard regs | |
2319 | have gotten them. */ | |
2055cea7 | 2320 | if (strict <= 0 |
1ccbefce | 2321 | || (strict_memory_address_p (recog_data.operand_mode[opno], |
0eadeb15 | 2322 | op))) |
2055cea7 RK |
2323 | win = 1; |
2324 | break; | |
2325 | ||
2326 | /* No need to check general_operand again; | |
2327 | it was done in insn-recog.c. */ | |
2328 | case 'g': | |
2329 | /* Anything goes unless it is a REG and really has a hard reg | |
2330 | but the hard reg is not in the class GENERAL_REGS. */ | |
2331 | if (strict < 0 | |
2332 | || GENERAL_REGS == ALL_REGS | |
2333 | || GET_CODE (op) != REG | |
3c3eeea6 RK |
2334 | || (reload_in_progress |
2335 | && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
2055cea7 RK |
2336 | || reg_fits_class_p (op, GENERAL_REGS, offset, mode)) |
2337 | win = 1; | |
2338 | break; | |
2339 | ||
2340 | case 'r': | |
2341 | if (strict < 0 | |
2342 | || (strict == 0 | |
2343 | && GET_CODE (op) == REG | |
2344 | && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
2345 | || (strict == 0 && GET_CODE (op) == SCRATCH) | |
2346 | || (GET_CODE (op) == REG | |
5a19ad3f RK |
2347 | && ((GENERAL_REGS == ALL_REGS |
2348 | && REGNO (op) < FIRST_PSEUDO_REGISTER) | |
2055cea7 RK |
2349 | || reg_fits_class_p (op, GENERAL_REGS, |
2350 | offset, mode)))) | |
2351 | win = 1; | |
2352 | break; | |
2353 | ||
2354 | case 'X': | |
0f41302f MS |
2355 | /* This is used for a MATCH_SCRATCH in the cases when |
2356 | we don't actually need anything. So anything goes | |
2357 | any time. */ | |
2055cea7 RK |
2358 | win = 1; |
2359 | break; | |
2360 | ||
2361 | case 'm': | |
2362 | if (GET_CODE (op) == MEM | |
2363 | /* Before reload, accept what reload can turn into mem. */ | |
3c3eeea6 RK |
2364 | || (strict < 0 && CONSTANT_P (op)) |
2365 | /* During reload, accept a pseudo */ | |
2366 | || (reload_in_progress && GET_CODE (op) == REG | |
2367 | && REGNO (op) >= FIRST_PSEUDO_REGISTER)) | |
2055cea7 RK |
2368 | win = 1; |
2369 | break; | |
2370 | ||
2371 | case '<': | |
2372 | if (GET_CODE (op) == MEM | |
2373 | && (GET_CODE (XEXP (op, 0)) == PRE_DEC | |
2374 | || GET_CODE (XEXP (op, 0)) == POST_DEC)) | |
2375 | win = 1; | |
2376 | break; | |
2377 | ||
2378 | case '>': | |
2379 | if (GET_CODE (op) == MEM | |
2380 | && (GET_CODE (XEXP (op, 0)) == PRE_INC | |
2381 | || GET_CODE (XEXP (op, 0)) == POST_INC)) | |
2382 | win = 1; | |
2383 | break; | |
2384 | ||
2385 | case 'E': | |
b990f635 | 2386 | #ifndef REAL_ARITHMETIC |
2055cea7 RK |
2387 | /* Match any CONST_DOUBLE, but only if |
2388 | we can examine the bits of it reliably. */ | |
2389 | if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT | |
9e4223f2 | 2390 | || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD) |
d1b765a5 | 2391 | && GET_MODE (op) != VOIDmode && ! flag_pretend_float) |
2055cea7 | 2392 | break; |
b990f635 | 2393 | #endif |
2055cea7 RK |
2394 | if (GET_CODE (op) == CONST_DOUBLE) |
2395 | win = 1; | |
2396 | break; | |
2397 | ||
2398 | case 'F': | |
2399 | if (GET_CODE (op) == CONST_DOUBLE) | |
2400 | win = 1; | |
2401 | break; | |
2402 | ||
2403 | case 'G': | |
2404 | case 'H': | |
2405 | if (GET_CODE (op) == CONST_DOUBLE | |
2406 | && CONST_DOUBLE_OK_FOR_LETTER_P (op, c)) | |
2407 | win = 1; | |
2408 | break; | |
2409 | ||
2410 | case 's': | |
2411 | if (GET_CODE (op) == CONST_INT | |
2412 | || (GET_CODE (op) == CONST_DOUBLE | |
2413 | && GET_MODE (op) == VOIDmode)) | |
2414 | break; | |
2415 | case 'i': | |
2416 | if (CONSTANT_P (op)) | |
2417 | win = 1; | |
2418 | break; | |
2419 | ||
2420 | case 'n': | |
2421 | if (GET_CODE (op) == CONST_INT | |
2422 | || (GET_CODE (op) == CONST_DOUBLE | |
2423 | && GET_MODE (op) == VOIDmode)) | |
2424 | win = 1; | |
2425 | break; | |
2426 | ||
2427 | case 'I': | |
2428 | case 'J': | |
2429 | case 'K': | |
2430 | case 'L': | |
2431 | case 'M': | |
2432 | case 'N': | |
2433 | case 'O': | |
2434 | case 'P': | |
2435 | if (GET_CODE (op) == CONST_INT | |
2436 | && CONST_OK_FOR_LETTER_P (INTVAL (op), c)) | |
2437 | win = 1; | |
2438 | break; | |
2439 | ||
2440 | #ifdef EXTRA_CONSTRAINT | |
2441 | case 'Q': | |
2442 | case 'R': | |
2443 | case 'S': | |
2444 | case 'T': | |
2445 | case 'U': | |
2446 | if (EXTRA_CONSTRAINT (op, c)) | |
2447 | win = 1; | |
2448 | break; | |
2449 | #endif | |
2450 | ||
2451 | case 'V': | |
2452 | if (GET_CODE (op) == MEM | |
69f724c0 JL |
2453 | && ((strict > 0 && ! offsettable_memref_p (op)) |
2454 | || (strict < 0 | |
2455 | && !(CONSTANT_P (op) || GET_CODE (op) == MEM)) | |
2456 | || (reload_in_progress | |
2457 | && !(GET_CODE (op) == REG | |
2458 | && REGNO (op) >= FIRST_PSEUDO_REGISTER)))) | |
2055cea7 RK |
2459 | win = 1; |
2460 | break; | |
2461 | ||
2462 | case 'o': | |
2463 | if ((strict > 0 && offsettable_memref_p (op)) | |
2464 | || (strict == 0 && offsettable_nonstrict_memref_p (op)) | |
2465 | /* Before reload, accept what reload can handle. */ | |
2466 | || (strict < 0 | |
3c3eeea6 RK |
2467 | && (CONSTANT_P (op) || GET_CODE (op) == MEM)) |
2468 | /* During reload, accept a pseudo */ | |
2469 | || (reload_in_progress && GET_CODE (op) == REG | |
2470 | && REGNO (op) >= FIRST_PSEUDO_REGISTER)) | |
2055cea7 RK |
2471 | win = 1; |
2472 | break; | |
2473 | ||
2474 | default: | |
2475 | if (strict < 0 | |
2476 | || (strict == 0 | |
2477 | && GET_CODE (op) == REG | |
2478 | && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
2479 | || (strict == 0 && GET_CODE (op) == SCRATCH) | |
2480 | || (GET_CODE (op) == REG | |
2481 | && reg_fits_class_p (op, REG_CLASS_FROM_LETTER (c), | |
2482 | offset, mode))) | |
2483 | win = 1; | |
2484 | } | |
2485 | ||
2486 | constraints[opno] = p; | |
2487 | /* If this operand did not win somehow, | |
2488 | this alternative loses. */ | |
2489 | if (! win) | |
2490 | lose = 1; | |
2491 | } | |
2492 | /* This alternative won; the operands are ok. | |
2493 | Change whichever operands this alternative says to change. */ | |
2494 | if (! lose) | |
2495 | { | |
9e21be9d RK |
2496 | int opno, eopno; |
2497 | ||
2498 | /* See if any earlyclobber operand conflicts with some other | |
2499 | operand. */ | |
2500 | ||
2501 | if (strict > 0) | |
1ccbefce | 2502 | for (eopno = 0; eopno < recog_data.n_operands; eopno++) |
62946075 RS |
2503 | /* Ignore earlyclobber operands now in memory, |
2504 | because we would often report failure when we have | |
2505 | two memory operands, one of which was formerly a REG. */ | |
2506 | if (earlyclobber[eopno] | |
1ccbefce RH |
2507 | && GET_CODE (recog_data.operand[eopno]) == REG) |
2508 | for (opno = 0; opno < recog_data.n_operands; opno++) | |
2509 | if ((GET_CODE (recog_data.operand[opno]) == MEM | |
2510 | || recog_data.operand_type[opno] != OP_OUT) | |
9e21be9d | 2511 | && opno != eopno |
0f41302f | 2512 | /* Ignore things like match_operator operands. */ |
1ccbefce | 2513 | && *recog_data.constraints[opno] != 0 |
9e21be9d | 2514 | && ! (matching_operands[opno] == eopno |
1ccbefce RH |
2515 | && operands_match_p (recog_data.operand[opno], |
2516 | recog_data.operand[eopno])) | |
2517 | && ! safe_from_earlyclobber (recog_data.operand[opno], | |
2518 | recog_data.operand[eopno])) | |
9e21be9d RK |
2519 | lose = 1; |
2520 | ||
2521 | if (! lose) | |
2055cea7 | 2522 | { |
9e21be9d RK |
2523 | while (--funny_match_index >= 0) |
2524 | { | |
1ccbefce RH |
2525 | recog_data.operand[funny_match[funny_match_index].other] |
2526 | = recog_data.operand[funny_match[funny_match_index].this]; | |
9e21be9d RK |
2527 | } |
2528 | ||
2529 | return 1; | |
2055cea7 | 2530 | } |
2055cea7 RK |
2531 | } |
2532 | ||
2533 | which_alternative++; | |
2534 | } | |
2535 | ||
2536 | /* If we are about to reject this, but we are not to test strictly, | |
2537 | try a very loose test. Only return failure if it fails also. */ | |
2538 | if (strict == 0) | |
0eadeb15 | 2539 | return constrain_operands (-1); |
2055cea7 RK |
2540 | else |
2541 | return 0; | |
2542 | } | |
2543 | ||
2544 | /* Return 1 iff OPERAND (assumed to be a REG rtx) | |
38a448ca | 2545 | is a hard reg in class CLASS when its regno is offset by OFFSET |
2055cea7 RK |
2546 | and changed to mode MODE. |
2547 | If REG occupies multiple hard regs, all of them must be in CLASS. */ | |
2548 | ||
2549 | int | |
2550 | reg_fits_class_p (operand, class, offset, mode) | |
2551 | rtx operand; | |
2552 | register enum reg_class class; | |
2553 | int offset; | |
2554 | enum machine_mode mode; | |
2555 | { | |
2556 | register int regno = REGNO (operand); | |
2557 | if (regno < FIRST_PSEUDO_REGISTER | |
2558 | && TEST_HARD_REG_BIT (reg_class_contents[(int) class], | |
2559 | regno + offset)) | |
2560 | { | |
2561 | register int sr; | |
2562 | regno += offset; | |
2563 | for (sr = HARD_REGNO_NREGS (regno, mode) - 1; | |
2564 | sr > 0; sr--) | |
2565 | if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class], | |
2566 | regno + sr)) | |
2567 | break; | |
2568 | return sr == 0; | |
2569 | } | |
2570 | ||
2571 | return 0; | |
2572 | } | |
2573 | ||
2574 | #endif /* REGISTER_CONSTRAINTS */ | |
ca545bb5 BM |
2575 | \f |
2576 | /* Do the splitting of insns in the block B. Only try to actually split if | |
2577 | DO_SPLIT is true; otherwise, just remove nops. */ | |
2578 | ||
2579 | void | |
2580 | split_block_insns (b, do_split) | |
2581 | int b; | |
2582 | int do_split; | |
2583 | { | |
2584 | rtx insn, next; | |
2585 | ||
2586 | for (insn = BLOCK_HEAD (b);; insn = next) | |
2587 | { | |
2588 | rtx set; | |
2589 | ||
2590 | /* Can't use `next_real_insn' because that | |
2591 | might go across CODE_LABELS and short-out basic blocks. */ | |
2592 | next = NEXT_INSN (insn); | |
2593 | if (GET_CODE (insn) != INSN) | |
2594 | { | |
2595 | if (insn == BLOCK_END (b)) | |
2596 | break; | |
2597 | ||
2598 | continue; | |
2599 | } | |
2600 | ||
2601 | /* Don't split no-op move insns. These should silently disappear | |
2602 | later in final. Splitting such insns would break the code | |
2603 | that handles REG_NO_CONFLICT blocks. */ | |
2604 | set = single_set (insn); | |
2605 | if (set && rtx_equal_p (SET_SRC (set), SET_DEST (set))) | |
2606 | { | |
2607 | if (insn == BLOCK_END (b)) | |
2608 | break; | |
2609 | ||
2610 | /* Nops get in the way while scheduling, so delete them now if | |
2611 | register allocation has already been done. It is too risky | |
2612 | to try to do this before register allocation, and there are | |
2613 | unlikely to be very many nops then anyways. */ | |
2614 | if (reload_completed) | |
2615 | { | |
2616 | ||
2617 | PUT_CODE (insn, NOTE); | |
2618 | NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; | |
2619 | NOTE_SOURCE_FILE (insn) = 0; | |
2620 | } | |
2621 | ||
2622 | continue; | |
2623 | } | |
2624 | ||
2625 | if (do_split) | |
2626 | { | |
2627 | /* Split insns here to get max fine-grain parallelism. */ | |
2628 | rtx first = PREV_INSN (insn); | |
2629 | rtx notes = REG_NOTES (insn); | |
2630 | rtx last = try_split (PATTERN (insn), insn, 1); | |
2631 | ||
2632 | if (last != insn) | |
2633 | { | |
2634 | /* try_split returns the NOTE that INSN became. */ | |
2635 | first = NEXT_INSN (first); | |
3c4fc1cc | 2636 | #ifdef INSN_SCHEDULING |
f2a1bc02 | 2637 | update_life_info (notes, first, last, insn, insn); |
bbf9d88c | 2638 | #endif |
ca545bb5 BM |
2639 | PUT_CODE (insn, NOTE); |
2640 | NOTE_SOURCE_FILE (insn) = 0; | |
2641 | NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; | |
2642 | if (insn == BLOCK_HEAD (b)) | |
2643 | BLOCK_HEAD (b) = first; | |
2644 | if (insn == BLOCK_END (b)) | |
2645 | { | |
2646 | BLOCK_END (b) = last; | |
2647 | break; | |
2648 | } | |
2649 | } | |
2650 | } | |
2651 | ||
2652 | if (insn == BLOCK_END (b)) | |
2653 | break; | |
2654 | } | |
2655 | } | |
ede7cd44 RH |
2656 | \f |
2657 | #ifdef HAVE_peephole2 | |
2658 | /* Return the Nth non-note insn after INSN, or return NULL_RTX if it does | |
2659 | not exist. Used by the recognizer to find the next insn to match in a | |
2660 | multi-insn pattern. */ | |
2661 | rtx | |
2662 | recog_next_insn (insn, n) | |
2663 | rtx insn; | |
2664 | int n; | |
2665 | { | |
2666 | while (insn != NULL_RTX && n > 0) | |
2667 | { | |
2668 | insn = next_nonnote_insn (insn); | |
2669 | ||
2670 | if (insn == NULL_RTX) | |
2671 | return insn; | |
2672 | ||
2673 | if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') | |
2674 | return NULL_RTX; | |
2675 | ||
2676 | n--; | |
2677 | } | |
2678 | ||
2679 | return insn; | |
2680 | } | |
2681 | ||
2682 | /* Perform the peephole2 optimization pass. */ | |
2683 | void | |
2684 | peephole2_optimize (dump_file) | |
2685 | FILE *dump_file ATTRIBUTE_UNUSED; | |
2686 | { | |
2687 | rtx insn; | |
2688 | rtx epilogue_insn = 0; | |
2689 | ||
2690 | for (insn = get_last_insn (); insn != NULL_RTX; insn = PREV_INSN (insn)) | |
2691 | { | |
2692 | if (GET_CODE (insn) == NOTE | |
2693 | && NOTE_LINE_NUMBER (insn) == NOTE_INSN_EPILOGUE_BEG) | |
2694 | { | |
2695 | epilogue_insn = insn; | |
2696 | break; | |
2697 | } | |
2698 | } | |
2699 | ||
2700 | init_resource_info (epilogue_insn); | |
2701 | ||
2702 | for (insn = get_insns (); insn != NULL; | |
2703 | insn = next_nonnote_insn (insn)) | |
2704 | { | |
2705 | if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN) | |
2706 | { | |
2707 | rtx last_insn; | |
2708 | rtx before = PREV_INSN (insn); | |
2709 | ||
2710 | rtx try = peephole2_insns (PATTERN (insn), insn, &last_insn); | |
2711 | if (try != NULL) | |
2712 | { | |
2713 | replace_insns (insn, last_insn, try, NULL_RTX); | |
2714 | insn = NEXT_INSN (before); | |
2715 | } | |
2716 | } | |
2717 | } | |
2718 | ||
2719 | free_resource_info (); | |
2720 | } | |
2721 | #endif |