]>
Commit | Line | Data |
---|---|---|
1d4227c3 | 1 | /* Redundant Extension Elimination pass for the GNU compiler. |
3aea1f79 | 2 | Copyright (C) 2010-2014 Free Software Foundation, Inc. |
060b8c19 | 3 | Contributed by Ilya Enkovich (ilya.enkovich@intel.com) |
1d4227c3 | 4 | |
060b8c19 | 5 | Based on the Redundant Zero-extension elimination pass contributed by |
6 | Sriraman Tallam (tmsriram@google.com) and Silvius Rus (rus@google.com). | |
a5b022e7 | 7 | |
8 | This file is part of GCC. | |
9 | ||
10 | GCC is free software; you can redistribute it and/or modify it under | |
11 | the terms of the GNU General Public License as published by the Free | |
12 | Software Foundation; either version 3, or (at your option) any later | |
13 | version. | |
14 | ||
15 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
16 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
17 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
18 | for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with GCC; see the file COPYING3. If not see | |
22 | <http://www.gnu.org/licenses/>. */ | |
23 | ||
24 | ||
25 | /* Problem Description : | |
26 | -------------------- | |
1d4227c3 | 27 | This pass is intended to remove redundant extension instructions. |
28 | Such instructions appear for different reasons. We expect some of | |
29 | them due to implicit zero-extension in 64-bit registers after writing | |
30 | to their lower 32-bit half (e.g. for the x86-64 architecture). | |
31 | Another possible reason is a type cast which follows a load (for | |
32 | instance a register restore) and which can be combined into a single | |
33 | instruction, and for which earlier local passes, e.g. the combiner, | |
34 | weren't able to optimize. | |
a5b022e7 | 35 | |
36 | How does this pass work ? | |
37 | -------------------------- | |
38 | ||
39 | This pass is run after register allocation. Hence, all registers that | |
1d4227c3 | 40 | this pass deals with are hard registers. This pass first looks for an |
41 | extension instruction that could possibly be redundant. Such extension | |
42 | instructions show up in RTL with the pattern : | |
43 | (set (reg:<SWI248> x) (any_extend:<SWI248> (reg:<SWI124> x))), | |
44 | where x can be any hard register. | |
a5b022e7 | 45 | Now, this pass tries to eliminate this instruction by merging the |
1d4227c3 | 46 | extension with the definitions of register x. For instance, if |
a5b022e7 | 47 | one of the definitions of register x was : |
48 | (set (reg:SI x) (plus:SI (reg:SI z1) (reg:SI z2))), | |
1d4227c3 | 49 | followed by extension : |
50 | (set (reg:DI x) (zero_extend:DI (reg:SI x))) | |
a5b022e7 | 51 | then the combination converts this into : |
52 | (set (reg:DI x) (zero_extend:DI (plus:SI (reg:SI z1) (reg:SI z2)))). | |
53 | If all the merged definitions are recognizable assembly instructions, | |
1d4227c3 | 54 | the extension is effectively eliminated. |
55 | ||
56 | For example, for the x86-64 architecture, implicit zero-extensions | |
57 | are captured with appropriate patterns in the i386.md file. Hence, | |
58 | these merged definition can be matched to a single assembly instruction. | |
59 | The original extension instruction is then deleted if all the | |
60 | definitions can be merged. | |
a5b022e7 | 61 | |
62 | However, there are cases where the definition instruction cannot be | |
1d4227c3 | 63 | merged with an extension. Examples are CALL instructions. In such |
64 | cases, the original extension is not redundant and this pass does | |
a5b022e7 | 65 | not delete it. |
66 | ||
67 | Handling conditional moves : | |
68 | ---------------------------- | |
69 | ||
1d4227c3 | 70 | Architectures like x86-64 support conditional moves whose semantics for |
71 | extension differ from the other instructions. For instance, the | |
a5b022e7 | 72 | instruction *cmov ebx, eax* |
73 | zero-extends eax onto rax only when the move from ebx to eax happens. | |
060b8c19 | 74 | Otherwise, eax may not be zero-extended. Consider conditional moves as |
a5b022e7 | 75 | RTL instructions of the form |
76 | (set (reg:SI x) (if_then_else (cond) (reg:SI y) (reg:SI z))). | |
1d4227c3 | 77 | This pass tries to merge an extension with a conditional move by |
060b8c19 | 78 | actually merging the definitions of y and z with an extension and then |
a5b022e7 | 79 | converting the conditional move into : |
80 | (set (reg:DI x) (if_then_else (cond) (reg:DI y) (reg:DI z))). | |
1d4227c3 | 81 | Since registers y and z are extended, register x will also be extended |
82 | after the conditional move. Note that this step has to be done | |
83 | transitively since the definition of a conditional copy can be | |
a5b022e7 | 84 | another conditional copy. |
85 | ||
86 | Motivating Example I : | |
87 | --------------------- | |
88 | For this program : | |
89 | ********************************************** | |
90 | bad_code.c | |
91 | ||
92 | int mask[1000]; | |
93 | ||
94 | int foo(unsigned x) | |
95 | { | |
96 | if (x < 10) | |
97 | x = x * 45; | |
98 | else | |
99 | x = x * 78; | |
100 | return mask[x]; | |
101 | } | |
102 | ********************************************** | |
103 | ||
1d4227c3 | 104 | $ gcc -O2 bad_code.c |
a5b022e7 | 105 | ........ |
106 | 400315: b8 4e 00 00 00 mov $0x4e,%eax | |
107 | 40031a: 0f af f8 imul %eax,%edi | |
060b8c19 | 108 | 40031d: 89 ff mov %edi,%edi - useless extension |
a5b022e7 | 109 | 40031f: 8b 04 bd 60 19 40 00 mov 0x401960(,%rdi,4),%eax |
110 | 400326: c3 retq | |
111 | ...... | |
112 | 400330: ba 2d 00 00 00 mov $0x2d,%edx | |
113 | 400335: 0f af fa imul %edx,%edi | |
060b8c19 | 114 | 400338: 89 ff mov %edi,%edi - useless extension |
a5b022e7 | 115 | 40033a: 8b 04 bd 60 19 40 00 mov 0x401960(,%rdi,4),%eax |
116 | 400341: c3 retq | |
117 | ||
1d4227c3 | 118 | $ gcc -O2 -free bad_code.c |
a5b022e7 | 119 | ...... |
120 | 400315: 6b ff 4e imul $0x4e,%edi,%edi | |
121 | 400318: 8b 04 bd 40 19 40 00 mov 0x401940(,%rdi,4),%eax | |
122 | 40031f: c3 retq | |
123 | 400320: 6b ff 2d imul $0x2d,%edi,%edi | |
124 | 400323: 8b 04 bd 40 19 40 00 mov 0x401940(,%rdi,4),%eax | |
125 | 40032a: c3 retq | |
126 | ||
127 | Motivating Example II : | |
128 | --------------------- | |
129 | ||
130 | Here is an example with a conditional move. | |
131 | ||
132 | For this program : | |
133 | ********************************************** | |
134 | ||
135 | unsigned long long foo(unsigned x , unsigned y) | |
136 | { | |
137 | unsigned z; | |
138 | if (x > 100) | |
139 | z = x + y; | |
140 | else | |
141 | z = x - y; | |
142 | return (unsigned long long)(z); | |
143 | } | |
144 | ||
1d4227c3 | 145 | $ gcc -O2 bad_code.c |
a5b022e7 | 146 | ............ |
147 | 400360: 8d 14 3e lea (%rsi,%rdi,1),%edx | |
148 | 400363: 89 f8 mov %edi,%eax | |
149 | 400365: 29 f0 sub %esi,%eax | |
150 | 400367: 83 ff 65 cmp $0x65,%edi | |
151 | 40036a: 0f 43 c2 cmovae %edx,%eax | |
060b8c19 | 152 | 40036d: 89 c0 mov %eax,%eax - useless extension |
a5b022e7 | 153 | 40036f: c3 retq |
154 | ||
1d4227c3 | 155 | $ gcc -O2 -free bad_code.c |
a5b022e7 | 156 | ............. |
157 | 400360: 89 fa mov %edi,%edx | |
158 | 400362: 8d 04 3e lea (%rsi,%rdi,1),%eax | |
159 | 400365: 29 f2 sub %esi,%edx | |
160 | 400367: 83 ff 65 cmp $0x65,%edi | |
161 | 40036a: 89 d6 mov %edx,%esi | |
162 | 40036c: 48 0f 42 c6 cmovb %rsi,%rax | |
163 | 400370: c3 retq | |
164 | ||
1d4227c3 | 165 | Motivating Example III : |
166 | --------------------- | |
167 | ||
168 | Here is an example with a type cast. | |
169 | ||
170 | For this program : | |
171 | ********************************************** | |
172 | ||
173 | void test(int size, unsigned char *in, unsigned char *out) | |
174 | { | |
175 | int i; | |
176 | unsigned char xr, xg, xy=0; | |
177 | ||
178 | for (i = 0; i < size; i++) { | |
179 | xr = *in++; | |
180 | xg = *in++; | |
181 | xy = (unsigned char) ((19595*xr + 38470*xg) >> 16); | |
182 | *out++ = xy; | |
183 | } | |
184 | } | |
185 | ||
186 | $ gcc -O2 bad_code.c | |
187 | ............ | |
188 | 10: 0f b6 0e movzbl (%rsi),%ecx | |
189 | 13: 0f b6 46 01 movzbl 0x1(%rsi),%eax | |
190 | 17: 48 83 c6 02 add $0x2,%rsi | |
060b8c19 | 191 | 1b: 0f b6 c9 movzbl %cl,%ecx - useless extension |
192 | 1e: 0f b6 c0 movzbl %al,%eax - useless extension | |
1d4227c3 | 193 | 21: 69 c9 8b 4c 00 00 imul $0x4c8b,%ecx,%ecx |
194 | 27: 69 c0 46 96 00 00 imul $0x9646,%eax,%eax | |
195 | ||
196 | $ gcc -O2 -free bad_code.c | |
197 | ............. | |
198 | 10: 0f b6 0e movzbl (%rsi),%ecx | |
199 | 13: 0f b6 46 01 movzbl 0x1(%rsi),%eax | |
200 | 17: 48 83 c6 02 add $0x2,%rsi | |
201 | 1b: 69 c9 8b 4c 00 00 imul $0x4c8b,%ecx,%ecx | |
202 | 21: 69 c0 46 96 00 00 imul $0x9646,%eax,%eax | |
a5b022e7 | 203 | |
204 | Usefulness : | |
205 | ---------- | |
206 | ||
1d4227c3 | 207 | The original redundant zero-extension elimination pass reported reduction |
208 | of the dynamic instruction count of a compression benchmark by 2.8% and | |
209 | improvement of its run time by about 1%. | |
a5b022e7 | 210 | |
1d4227c3 | 211 | The additional performance gain with the enhanced pass is mostly expected |
212 | on in-order architectures where redundancy cannot be compensated by out of | |
213 | order execution. Measurements showed up to 10% performance gain (reduced | |
214 | run time) on EEMBC 2.0 benchmarks on Atom processor with geomean performance | |
215 | gain 1%. */ | |
a5b022e7 | 216 | |
217 | ||
218 | #include "config.h" | |
219 | #include "system.h" | |
220 | #include "coretypes.h" | |
221 | #include "tm.h" | |
222 | #include "rtl.h" | |
223 | #include "tree.h" | |
224 | #include "tm_p.h" | |
225 | #include "flags.h" | |
226 | #include "regs.h" | |
227 | #include "hard-reg-set.h" | |
228 | #include "basic-block.h" | |
229 | #include "insn-config.h" | |
230 | #include "function.h" | |
231 | #include "expr.h" | |
232 | #include "insn-attr.h" | |
233 | #include "recog.h" | |
0b205f4c | 234 | #include "diagnostic-core.h" |
a5b022e7 | 235 | #include "target.h" |
a5b022e7 | 236 | #include "optabs.h" |
237 | #include "insn-codes.h" | |
238 | #include "rtlhooks-def.h" | |
a5b022e7 | 239 | #include "params.h" |
a5b022e7 | 240 | #include "tree-pass.h" |
241 | #include "df.h" | |
242 | #include "cgraph.h" | |
243 | ||
060b8c19 | 244 | /* This structure represents a candidate for elimination. */ |
a5b022e7 | 245 | |
7f14f00a | 246 | typedef struct ext_cand |
a5b022e7 | 247 | { |
060b8c19 | 248 | /* The expression. */ |
249 | const_rtx expr; | |
a5b022e7 | 250 | |
060b8c19 | 251 | /* The kind of extension. */ |
252 | enum rtx_code code; | |
1d4227c3 | 253 | |
060b8c19 | 254 | /* The destination mode. */ |
255 | enum machine_mode mode; | |
256 | ||
257 | /* The instruction where it lives. */ | |
1d4227c3 | 258 | rtx insn; |
060b8c19 | 259 | } ext_cand; |
1d4227c3 | 260 | |
1d4227c3 | 261 | |
a5b022e7 | 262 | static int max_insn_uid; |
263 | ||
1d4227c3 | 264 | /* Given a insn (CURR_INSN), an extension candidate for removal (CAND) |
265 | and a pointer to the SET rtx (ORIG_SET) that needs to be modified, | |
266 | this code modifies the SET rtx to a new SET rtx that extends the | |
267 | right hand expression into a register on the left hand side. Note | |
268 | that multiple assumptions are made about the nature of the set that | |
269 | needs to be true for this to work and is called from merge_def_and_ext. | |
a5b022e7 | 270 | |
271 | Original : | |
1d4227c3 | 272 | (set (reg a) (expression)) |
a5b022e7 | 273 | |
274 | Transform : | |
060b8c19 | 275 | (set (reg a) (any_extend (expression))) |
a5b022e7 | 276 | |
277 | Special Cases : | |
060b8c19 | 278 | If the expression is a constant or another extension, then directly |
1d4227c3 | 279 | assign it to the register. */ |
a5b022e7 | 280 | |
281 | static bool | |
060b8c19 | 282 | combine_set_extension (ext_cand *cand, rtx curr_insn, rtx *orig_set) |
a5b022e7 | 283 | { |
060b8c19 | 284 | rtx orig_src = SET_SRC (*orig_set); |
285 | rtx new_reg = gen_rtx_REG (cand->mode, REGNO (SET_DEST (*orig_set))); | |
286 | rtx new_set; | |
a5b022e7 | 287 | |
060b8c19 | 288 | /* Merge constants by directly moving the constant into the register under |
289 | some conditions. Recall that RTL constants are sign-extended. */ | |
1d4227c3 | 290 | if (GET_CODE (orig_src) == CONST_INT |
060b8c19 | 291 | && HOST_BITS_PER_WIDE_INT >= GET_MODE_BITSIZE (cand->mode)) |
1d4227c3 | 292 | { |
060b8c19 | 293 | if (INTVAL (orig_src) >= 0 || cand->code == SIGN_EXTEND) |
294 | new_set = gen_rtx_SET (VOIDmode, new_reg, orig_src); | |
a5b022e7 | 295 | else |
1d4227c3 | 296 | { |
297 | /* Zero-extend the negative constant by masking out the bits outside | |
298 | the source mode. */ | |
299 | enum machine_mode src_mode = GET_MODE (SET_DEST (*orig_set)); | |
060b8c19 | 300 | rtx new_const_int |
d11aedc7 | 301 | = gen_int_mode (INTVAL (orig_src) & GET_MODE_MASK (src_mode), |
302 | GET_MODE (new_reg)); | |
060b8c19 | 303 | new_set = gen_rtx_SET (VOIDmode, new_reg, new_const_int); |
1d4227c3 | 304 | } |
305 | } | |
306 | else if (GET_MODE (orig_src) == VOIDmode) | |
307 | { | |
060b8c19 | 308 | /* This is mostly due to a call insn that should not be optimized. */ |
1d4227c3 | 309 | return false; |
a5b022e7 | 310 | } |
060b8c19 | 311 | else if (GET_CODE (orig_src) == cand->code) |
a5b022e7 | 312 | { |
060b8c19 | 313 | /* Here is a sequence of two extensions. Try to merge them. */ |
314 | rtx temp_extension | |
315 | = gen_rtx_fmt_e (cand->code, cand->mode, XEXP (orig_src, 0)); | |
316 | rtx simplified_temp_extension = simplify_rtx (temp_extension); | |
a5b022e7 | 317 | if (simplified_temp_extension) |
318 | temp_extension = simplified_temp_extension; | |
060b8c19 | 319 | new_set = gen_rtx_SET (VOIDmode, new_reg, temp_extension); |
a5b022e7 | 320 | } |
321 | else if (GET_CODE (orig_src) == IF_THEN_ELSE) | |
322 | { | |
1d4227c3 | 323 | /* Only IF_THEN_ELSE of phi-type copies are combined. Otherwise, |
a5b022e7 | 324 | in general, IF_THEN_ELSE should not be combined. */ |
a5b022e7 | 325 | return false; |
326 | } | |
327 | else | |
328 | { | |
060b8c19 | 329 | /* This is the normal case. */ |
330 | rtx temp_extension | |
331 | = gen_rtx_fmt_e (cand->code, cand->mode, orig_src); | |
332 | rtx simplified_temp_extension = simplify_rtx (temp_extension); | |
a5b022e7 | 333 | if (simplified_temp_extension) |
334 | temp_extension = simplified_temp_extension; | |
060b8c19 | 335 | new_set = gen_rtx_SET (VOIDmode, new_reg, temp_extension); |
a5b022e7 | 336 | } |
337 | ||
1d4227c3 | 338 | /* This change is a part of a group of changes. Hence, |
a5b022e7 | 339 | validate_change will not try to commit the change. */ |
a5b022e7 | 340 | if (validate_change (curr_insn, orig_set, new_set, true)) |
341 | { | |
342 | if (dump_file) | |
343 | { | |
4a77f173 | 344 | fprintf (dump_file, |
345 | "Tentatively merged extension with definition:\n"); | |
a5b022e7 | 346 | print_rtl_single (dump_file, curr_insn); |
347 | } | |
348 | return true; | |
349 | } | |
060b8c19 | 350 | |
a5b022e7 | 351 | return false; |
352 | } | |
353 | ||
a5b022e7 | 354 | /* Treat if_then_else insns, where the operands of both branches |
1d4227c3 | 355 | are registers, as copies. For instance, |
a5b022e7 | 356 | Original : |
357 | (set (reg:SI a) (if_then_else (cond) (reg:SI b) (reg:SI c))) | |
358 | Transformed : | |
359 | (set (reg:DI a) (if_then_else (cond) (reg:DI b) (reg:DI c))) | |
360 | DEF_INSN is the if_then_else insn. */ | |
361 | ||
362 | static bool | |
060b8c19 | 363 | transform_ifelse (ext_cand *cand, rtx def_insn) |
a5b022e7 | 364 | { |
365 | rtx set_insn = PATTERN (def_insn); | |
366 | rtx srcreg, dstreg, srcreg2; | |
367 | rtx map_srcreg, map_dstreg, map_srcreg2; | |
368 | rtx ifexpr; | |
369 | rtx cond; | |
370 | rtx new_set; | |
371 | ||
372 | gcc_assert (GET_CODE (set_insn) == SET); | |
060b8c19 | 373 | |
a5b022e7 | 374 | cond = XEXP (SET_SRC (set_insn), 0); |
375 | dstreg = SET_DEST (set_insn); | |
376 | srcreg = XEXP (SET_SRC (set_insn), 1); | |
377 | srcreg2 = XEXP (SET_SRC (set_insn), 2); | |
6bd23a69 | 378 | /* If the conditional move already has the right or wider mode, |
379 | there is nothing to do. */ | |
380 | if (GET_MODE_SIZE (GET_MODE (dstreg)) >= GET_MODE_SIZE (cand->mode)) | |
381 | return true; | |
382 | ||
060b8c19 | 383 | map_srcreg = gen_rtx_REG (cand->mode, REGNO (srcreg)); |
384 | map_srcreg2 = gen_rtx_REG (cand->mode, REGNO (srcreg2)); | |
385 | map_dstreg = gen_rtx_REG (cand->mode, REGNO (dstreg)); | |
386 | ifexpr = gen_rtx_IF_THEN_ELSE (cand->mode, cond, map_srcreg, map_srcreg2); | |
a5b022e7 | 387 | new_set = gen_rtx_SET (VOIDmode, map_dstreg, ifexpr); |
388 | ||
389 | if (validate_change (def_insn, &PATTERN (def_insn), new_set, true)) | |
390 | { | |
391 | if (dump_file) | |
392 | { | |
060b8c19 | 393 | fprintf (dump_file, |
394 | "Mode of conditional move instruction extended:\n"); | |
a5b022e7 | 395 | print_rtl_single (dump_file, def_insn); |
396 | } | |
397 | return true; | |
398 | } | |
060b8c19 | 399 | |
400 | return false; | |
a5b022e7 | 401 | } |
402 | ||
060b8c19 | 403 | /* Get all the reaching definitions of an instruction. The definitions are |
404 | desired for REG used in INSN. Return the definition list or NULL if a | |
405 | definition is missing. If DEST is non-NULL, additionally push the INSN | |
406 | of the definitions onto DEST. */ | |
a5b022e7 | 407 | |
060b8c19 | 408 | static struct df_link * |
f1f41a6c | 409 | get_defs (rtx insn, rtx reg, vec<rtx> *dest) |
a5b022e7 | 410 | { |
4a77f173 | 411 | df_ref reg_info, *uses; |
060b8c19 | 412 | struct df_link *ref_chain, *ref_link; |
a5b022e7 | 413 | |
a5b022e7 | 414 | reg_info = NULL; |
415 | ||
4a77f173 | 416 | for (uses = DF_INSN_USES (insn); *uses; uses++) |
a5b022e7 | 417 | { |
4a77f173 | 418 | reg_info = *uses; |
a5b022e7 | 419 | if (GET_CODE (DF_REF_REG (reg_info)) == SUBREG) |
060b8c19 | 420 | return NULL; |
421 | if (REGNO (DF_REF_REG (reg_info)) == REGNO (reg)) | |
a5b022e7 | 422 | break; |
a5b022e7 | 423 | } |
424 | ||
4a77f173 | 425 | gcc_assert (reg_info != NULL && uses != NULL); |
a5b022e7 | 426 | |
060b8c19 | 427 | ref_chain = DF_REF_CHAIN (reg_info); |
428 | ||
429 | for (ref_link = ref_chain; ref_link; ref_link = ref_link->next) | |
a5b022e7 | 430 | { |
431 | /* Problem getting some definition for this instruction. */ | |
060b8c19 | 432 | if (ref_link->ref == NULL) |
433 | return NULL; | |
434 | if (DF_REF_INSN_INFO (ref_link->ref) == NULL) | |
435 | return NULL; | |
a5b022e7 | 436 | } |
437 | ||
060b8c19 | 438 | if (dest) |
439 | for (ref_link = ref_chain; ref_link; ref_link = ref_link->next) | |
f1f41a6c | 440 | dest->safe_push (DF_REF_INSN (ref_link->ref)); |
a5b022e7 | 441 | |
060b8c19 | 442 | return ref_chain; |
a5b022e7 | 443 | } |
444 | ||
060b8c19 | 445 | /* Return true if INSN is |
446 | (SET (reg REGNO (def_reg)) (if_then_else (cond) (REG x1) (REG x2))) | |
447 | and store x1 and x2 in REG_1 and REG_2. */ | |
a5b022e7 | 448 | |
060b8c19 | 449 | static bool |
450 | is_cond_copy_insn (rtx insn, rtx *reg1, rtx *reg2) | |
a5b022e7 | 451 | { |
060b8c19 | 452 | rtx expr = single_set (insn); |
a5b022e7 | 453 | |
060b8c19 | 454 | if (expr != NULL_RTX |
455 | && GET_CODE (expr) == SET | |
a5b022e7 | 456 | && GET_CODE (SET_DEST (expr)) == REG |
a5b022e7 | 457 | && GET_CODE (SET_SRC (expr)) == IF_THEN_ELSE |
458 | && GET_CODE (XEXP (SET_SRC (expr), 1)) == REG | |
1d4227c3 | 459 | && GET_CODE (XEXP (SET_SRC (expr), 2)) == REG) |
a5b022e7 | 460 | { |
060b8c19 | 461 | *reg1 = XEXP (SET_SRC (expr), 1); |
462 | *reg2 = XEXP (SET_SRC (expr), 2); | |
463 | return true; | |
a5b022e7 | 464 | } |
465 | ||
060b8c19 | 466 | return false; |
a5b022e7 | 467 | } |
468 | ||
6bd23a69 | 469 | enum ext_modified_kind |
470 | { | |
471 | /* The insn hasn't been modified by ree pass yet. */ | |
472 | EXT_MODIFIED_NONE, | |
473 | /* Changed into zero extension. */ | |
474 | EXT_MODIFIED_ZEXT, | |
475 | /* Changed into sign extension. */ | |
476 | EXT_MODIFIED_SEXT | |
477 | }; | |
478 | ||
5f90dfbd | 479 | struct ATTRIBUTE_PACKED ext_modified |
6bd23a69 | 480 | { |
481 | /* Mode from which ree has zero or sign extended the destination. */ | |
482 | ENUM_BITFIELD(machine_mode) mode : 8; | |
483 | ||
484 | /* Kind of modification of the insn. */ | |
485 | ENUM_BITFIELD(ext_modified_kind) kind : 2; | |
486 | ||
487 | /* True if the insn is scheduled to be deleted. */ | |
488 | unsigned int deleted : 1; | |
489 | }; | |
490 | ||
491 | /* Vectors used by combine_reaching_defs and its helpers. */ | |
492 | typedef struct ext_state | |
493 | { | |
f1f41a6c | 494 | /* In order to avoid constant alloc/free, we keep these |
6bd23a69 | 495 | 4 vectors live through the entire find_and_remove_re and just |
f1f41a6c | 496 | truncate them each time. */ |
497 | vec<rtx> defs_list; | |
498 | vec<rtx> copies_list; | |
499 | vec<rtx> modified_list; | |
500 | vec<rtx> work_list; | |
6bd23a69 | 501 | |
502 | /* For instructions that have been successfully modified, this is | |
503 | the original mode from which the insn is extending and | |
504 | kind of extension. */ | |
505 | struct ext_modified *modified; | |
506 | } ext_state; | |
507 | ||
1d4227c3 | 508 | /* Reaching Definitions of the extended register could be conditional copies |
509 | or regular definitions. This function separates the two types into two | |
6bd23a69 | 510 | lists, STATE->DEFS_LIST and STATE->COPIES_LIST. This is necessary because, |
511 | if a reaching definition is a conditional copy, merging the extension with | |
512 | this definition is wrong. Conditional copies are merged by transitively | |
513 | merging their definitions. The defs_list is populated with all the reaching | |
514 | definitions of the extension instruction (EXTEND_INSN) which must be merged | |
515 | with an extension. The copies_list contains all the conditional moves that | |
516 | will later be extended into a wider mode conditional move if all the merges | |
517 | are successful. The function returns false upon failure, true upon | |
518 | success. */ | |
519 | ||
520 | static bool | |
7715a410 | 521 | make_defs_and_copies_lists (rtx extend_insn, const_rtx set_pat, |
6bd23a69 | 522 | ext_state *state) |
a5b022e7 | 523 | { |
060b8c19 | 524 | rtx src_reg = XEXP (SET_SRC (set_pat), 0); |
a5b022e7 | 525 | bool *is_insn_visited; |
6bd23a69 | 526 | bool ret = true; |
527 | ||
f1f41a6c | 528 | state->work_list.truncate (0); |
a5b022e7 | 529 | |
060b8c19 | 530 | /* Initialize the work list. */ |
6bd23a69 | 531 | if (!get_defs (extend_insn, src_reg, &state->work_list)) |
532 | gcc_unreachable (); | |
a5b022e7 | 533 | |
060b8c19 | 534 | is_insn_visited = XCNEWVEC (bool, max_insn_uid); |
a5b022e7 | 535 | |
536 | /* Perform transitive closure for conditional copies. */ | |
f1f41a6c | 537 | while (!state->work_list.is_empty ()) |
a5b022e7 | 538 | { |
f1f41a6c | 539 | rtx def_insn = state->work_list.pop (); |
060b8c19 | 540 | rtx reg1, reg2; |
541 | ||
a5b022e7 | 542 | gcc_assert (INSN_UID (def_insn) < max_insn_uid); |
543 | ||
544 | if (is_insn_visited[INSN_UID (def_insn)]) | |
060b8c19 | 545 | continue; |
a5b022e7 | 546 | is_insn_visited[INSN_UID (def_insn)] = true; |
a5b022e7 | 547 | |
060b8c19 | 548 | if (is_cond_copy_insn (def_insn, ®1, ®2)) |
549 | { | |
550 | /* Push it onto the copy list first. */ | |
f1f41a6c | 551 | state->copies_list.safe_push (def_insn); |
060b8c19 | 552 | |
553 | /* Now perform the transitive closure. */ | |
6bd23a69 | 554 | if (!get_defs (def_insn, reg1, &state->work_list) |
555 | || !get_defs (def_insn, reg2, &state->work_list)) | |
060b8c19 | 556 | { |
6bd23a69 | 557 | ret = false; |
060b8c19 | 558 | break; |
559 | } | |
a5b022e7 | 560 | } |
561 | else | |
f1f41a6c | 562 | state->defs_list.safe_push (def_insn); |
a5b022e7 | 563 | } |
564 | ||
a5b022e7 | 565 | XDELETEVEC (is_insn_visited); |
060b8c19 | 566 | |
567 | return ret; | |
a5b022e7 | 568 | } |
569 | ||
060b8c19 | 570 | /* Merge the DEF_INSN with an extension. Calls combine_set_extension |
a5b022e7 | 571 | on the SET pattern. */ |
572 | ||
573 | static bool | |
6bd23a69 | 574 | merge_def_and_ext (ext_cand *cand, rtx def_insn, ext_state *state) |
a5b022e7 | 575 | { |
1d4227c3 | 576 | enum machine_mode ext_src_mode; |
a5b022e7 | 577 | enum rtx_code code; |
a5b022e7 | 578 | rtx *sub_rtx; |
579 | rtx s_expr; | |
580 | int i; | |
581 | ||
1d4227c3 | 582 | ext_src_mode = GET_MODE (XEXP (SET_SRC (cand->expr), 0)); |
a5b022e7 | 583 | code = GET_CODE (PATTERN (def_insn)); |
584 | sub_rtx = NULL; | |
585 | ||
586 | if (code == PARALLEL) | |
587 | { | |
588 | for (i = 0; i < XVECLEN (PATTERN (def_insn), 0); i++) | |
589 | { | |
590 | s_expr = XVECEXP (PATTERN (def_insn), 0, i); | |
591 | if (GET_CODE (s_expr) != SET) | |
592 | continue; | |
593 | ||
594 | if (sub_rtx == NULL) | |
595 | sub_rtx = &XVECEXP (PATTERN (def_insn), 0, i); | |
596 | else | |
597 | { | |
598 | /* PARALLEL with multiple SETs. */ | |
599 | return false; | |
600 | } | |
601 | } | |
602 | } | |
603 | else if (code == SET) | |
604 | sub_rtx = &PATTERN (def_insn); | |
605 | else | |
606 | { | |
607 | /* It is not a PARALLEL or a SET, what could it be ? */ | |
608 | return false; | |
609 | } | |
610 | ||
611 | gcc_assert (sub_rtx != NULL); | |
612 | ||
6bd23a69 | 613 | if (REG_P (SET_DEST (*sub_rtx)) |
614 | && (GET_MODE (SET_DEST (*sub_rtx)) == ext_src_mode | |
615 | || ((state->modified[INSN_UID (def_insn)].kind | |
616 | == (cand->code == ZERO_EXTEND | |
617 | ? EXT_MODIFIED_ZEXT : EXT_MODIFIED_SEXT)) | |
618 | && state->modified[INSN_UID (def_insn)].mode | |
619 | == ext_src_mode))) | |
a5b022e7 | 620 | { |
6bd23a69 | 621 | if (GET_MODE_SIZE (GET_MODE (SET_DEST (*sub_rtx))) |
622 | >= GET_MODE_SIZE (cand->mode)) | |
623 | return true; | |
624 | /* If def_insn is already scheduled to be deleted, don't attempt | |
625 | to modify it. */ | |
626 | if (state->modified[INSN_UID (def_insn)].deleted) | |
627 | return false; | |
628 | if (combine_set_extension (cand, def_insn, sub_rtx)) | |
629 | { | |
630 | if (state->modified[INSN_UID (def_insn)].kind == EXT_MODIFIED_NONE) | |
631 | state->modified[INSN_UID (def_insn)].mode = ext_src_mode; | |
632 | return true; | |
633 | } | |
a5b022e7 | 634 | } |
1d4227c3 | 635 | |
636 | return false; | |
a5b022e7 | 637 | } |
638 | ||
639 | /* This function goes through all reaching defs of the source | |
1d4227c3 | 640 | of the candidate for elimination (CAND) and tries to combine |
641 | the extension with the definition instruction. The changes | |
642 | are made as a group so that even if one definition cannot be | |
643 | merged, all reaching definitions end up not being merged. | |
644 | When a conditional copy is encountered, merging is attempted | |
645 | transitively on its definitions. It returns true upon success | |
646 | and false upon failure. */ | |
a5b022e7 | 647 | |
648 | static bool | |
7715a410 | 649 | combine_reaching_defs (ext_cand *cand, const_rtx set_pat, ext_state *state) |
a5b022e7 | 650 | { |
651 | rtx def_insn; | |
652 | bool merge_successful = true; | |
653 | int i; | |
654 | int defs_ix; | |
6bd23a69 | 655 | bool outcome; |
a5b022e7 | 656 | |
f1f41a6c | 657 | state->defs_list.truncate (0); |
658 | state->copies_list.truncate (0); | |
a5b022e7 | 659 | |
6bd23a69 | 660 | outcome = make_defs_and_copies_lists (cand->insn, set_pat, state); |
a5b022e7 | 661 | |
6bd23a69 | 662 | if (!outcome) |
663 | return false; | |
a5b022e7 | 664 | |
559f753b | 665 | /* If cand->insn has been already modified, update cand->mode to a wider |
666 | mode if possible, or punt. */ | |
667 | if (state->modified[INSN_UID (cand->insn)].kind != EXT_MODIFIED_NONE) | |
668 | { | |
669 | enum machine_mode mode; | |
670 | rtx set; | |
671 | ||
672 | if (state->modified[INSN_UID (cand->insn)].kind | |
673 | != (cand->code == ZERO_EXTEND | |
674 | ? EXT_MODIFIED_ZEXT : EXT_MODIFIED_SEXT) | |
675 | || state->modified[INSN_UID (cand->insn)].mode != cand->mode | |
676 | || (set = single_set (cand->insn)) == NULL_RTX) | |
677 | return false; | |
678 | mode = GET_MODE (SET_DEST (set)); | |
679 | gcc_assert (GET_MODE_SIZE (mode) >= GET_MODE_SIZE (cand->mode)); | |
680 | cand->mode = mode; | |
681 | } | |
682 | ||
a5b022e7 | 683 | merge_successful = true; |
684 | ||
685 | /* Go through the defs vector and try to merge all the definitions | |
686 | in this vector. */ | |
f1f41a6c | 687 | state->modified_list.truncate (0); |
688 | FOR_EACH_VEC_ELT (state->defs_list, defs_ix, def_insn) | |
a5b022e7 | 689 | { |
6bd23a69 | 690 | if (merge_def_and_ext (cand, def_insn, state)) |
f1f41a6c | 691 | state->modified_list.safe_push (def_insn); |
a5b022e7 | 692 | else |
693 | { | |
694 | merge_successful = false; | |
695 | break; | |
696 | } | |
697 | } | |
698 | ||
699 | /* Now go through the conditional copies vector and try to merge all | |
700 | the copies in this vector. */ | |
a5b022e7 | 701 | if (merge_successful) |
702 | { | |
f1f41a6c | 703 | FOR_EACH_VEC_ELT (state->copies_list, i, def_insn) |
a5b022e7 | 704 | { |
1d4227c3 | 705 | if (transform_ifelse (cand, def_insn)) |
f1f41a6c | 706 | state->modified_list.safe_push (def_insn); |
a5b022e7 | 707 | else |
708 | { | |
709 | merge_successful = false; | |
710 | break; | |
711 | } | |
712 | } | |
713 | } | |
714 | ||
715 | if (merge_successful) | |
716 | { | |
060b8c19 | 717 | /* Commit the changes here if possible |
718 | FIXME: It's an all-or-nothing scenario. Even if only one definition | |
719 | cannot be merged, we entirely give up. In the future, we should allow | |
720 | extensions to be partially eliminated along those paths where the | |
721 | definitions could be merged. */ | |
a5b022e7 | 722 | if (apply_change_group ()) |
723 | { | |
724 | if (dump_file) | |
060b8c19 | 725 | fprintf (dump_file, "All merges were successful.\n"); |
a5b022e7 | 726 | |
f1f41a6c | 727 | FOR_EACH_VEC_ELT (state->modified_list, i, def_insn) |
6bd23a69 | 728 | if (state->modified[INSN_UID (def_insn)].kind == EXT_MODIFIED_NONE) |
729 | state->modified[INSN_UID (def_insn)].kind | |
730 | = (cand->code == ZERO_EXTEND | |
731 | ? EXT_MODIFIED_ZEXT : EXT_MODIFIED_SEXT); | |
732 | ||
a5b022e7 | 733 | return true; |
734 | } | |
735 | else | |
736 | { | |
b749ba71 | 737 | /* Changes need not be cancelled explicitly as apply_change_group |
738 | does it. Print list of definitions in the dump_file for debug | |
1d4227c3 | 739 | purposes. This extension cannot be deleted. */ |
a5b022e7 | 740 | if (dump_file) |
741 | { | |
4a77f173 | 742 | fprintf (dump_file, |
743 | "Merge cancelled, non-mergeable definitions:\n"); | |
f1f41a6c | 744 | FOR_EACH_VEC_ELT (state->modified_list, i, def_insn) |
4a77f173 | 745 | print_rtl_single (dump_file, def_insn); |
a5b022e7 | 746 | } |
747 | } | |
748 | } | |
749 | else | |
750 | { | |
751 | /* Cancel any changes that have been made so far. */ | |
752 | cancel_changes (0); | |
753 | } | |
754 | ||
a5b022e7 | 755 | return false; |
756 | } | |
757 | ||
7715a410 | 758 | /* Add an extension pattern that could be eliminated. */ |
b749ba71 | 759 | |
760 | static void | |
7715a410 | 761 | add_removable_extension (const_rtx expr, rtx insn, |
f1f41a6c | 762 | vec<ext_cand> *insn_list, |
32a07a44 | 763 | unsigned *def_map) |
b749ba71 | 764 | { |
060b8c19 | 765 | enum rtx_code code; |
766 | enum machine_mode mode; | |
32a07a44 | 767 | unsigned int idx; |
b749ba71 | 768 | rtx src, dest; |
769 | ||
060b8c19 | 770 | /* We are looking for SET (REG N) (ANY_EXTEND (REG N)). */ |
b749ba71 | 771 | if (GET_CODE (expr) != SET) |
772 | return; | |
773 | ||
774 | src = SET_SRC (expr); | |
060b8c19 | 775 | code = GET_CODE (src); |
b749ba71 | 776 | dest = SET_DEST (expr); |
060b8c19 | 777 | mode = GET_MODE (dest); |
b749ba71 | 778 | |
779 | if (REG_P (dest) | |
060b8c19 | 780 | && (code == SIGN_EXTEND || code == ZERO_EXTEND) |
b749ba71 | 781 | && REG_P (XEXP (src, 0)) |
b749ba71 | 782 | && REGNO (dest) == REGNO (XEXP (src, 0))) |
783 | { | |
060b8c19 | 784 | struct df_link *defs, *def; |
785 | ext_cand *cand; | |
786 | ||
787 | /* First, make sure we can get all the reaching definitions. */ | |
7715a410 | 788 | defs = get_defs (insn, XEXP (src, 0), NULL); |
060b8c19 | 789 | if (!defs) |
b749ba71 | 790 | { |
060b8c19 | 791 | if (dump_file) |
792 | { | |
793 | fprintf (dump_file, "Cannot eliminate extension:\n"); | |
7715a410 | 794 | print_rtl_single (dump_file, insn); |
060b8c19 | 795 | fprintf (dump_file, " because of missing definition(s)\n"); |
796 | } | |
797 | return; | |
b749ba71 | 798 | } |
060b8c19 | 799 | |
800 | /* Second, make sure the reaching definitions don't feed another and | |
801 | different extension. FIXME: this obviously can be improved. */ | |
802 | for (def = defs; def; def = def->next) | |
9af5ce0c | 803 | if ((idx = def_map[INSN_UID (DF_REF_INSN (def->ref))]) |
f1f41a6c | 804 | && (cand = &(*insn_list)[idx - 1]) |
97b533dd | 805 | && cand->code != code) |
060b8c19 | 806 | { |
807 | if (dump_file) | |
808 | { | |
809 | fprintf (dump_file, "Cannot eliminate extension:\n"); | |
7715a410 | 810 | print_rtl_single (dump_file, insn); |
060b8c19 | 811 | fprintf (dump_file, " because of other extension\n"); |
812 | } | |
813 | return; | |
814 | } | |
815 | ||
816 | /* Then add the candidate to the list and insert the reaching definitions | |
817 | into the definition map. */ | |
e82e4eb5 | 818 | ext_cand e = {expr, code, mode, insn}; |
f1f41a6c | 819 | insn_list->safe_push (e); |
820 | idx = insn_list->length (); | |
060b8c19 | 821 | |
822 | for (def = defs; def; def = def->next) | |
9af5ce0c | 823 | def_map[INSN_UID (DF_REF_INSN (def->ref))] = idx; |
b749ba71 | 824 | } |
825 | } | |
826 | ||
1d4227c3 | 827 | /* Traverse the instruction stream looking for extensions and return the |
b749ba71 | 828 | list of candidates. */ |
a5b022e7 | 829 | |
f1f41a6c | 830 | static vec<ext_cand> |
1d4227c3 | 831 | find_removable_extensions (void) |
a5b022e7 | 832 | { |
1e094109 | 833 | vec<ext_cand> insn_list = vNULL; |
b749ba71 | 834 | basic_block bb; |
7715a410 | 835 | rtx insn, set; |
32a07a44 | 836 | unsigned *def_map = XCNEWVEC (unsigned, max_insn_uid); |
a5b022e7 | 837 | |
fc00614f | 838 | FOR_EACH_BB_FN (bb, cfun) |
b749ba71 | 839 | FOR_BB_INSNS (bb, insn) |
840 | { | |
841 | if (!NONDEBUG_INSN_P (insn)) | |
842 | continue; | |
a5b022e7 | 843 | |
7715a410 | 844 | set = single_set (insn); |
845 | if (set == NULL_RTX) | |
846 | continue; | |
847 | add_removable_extension (set, insn, &insn_list, def_map); | |
b749ba71 | 848 | } |
849 | ||
7715a410 | 850 | XDELETEVEC (def_map); |
060b8c19 | 851 | |
7715a410 | 852 | return insn_list; |
a5b022e7 | 853 | } |
854 | ||
855 | /* This is the main function that checks the insn stream for redundant | |
1d4227c3 | 856 | extensions and tries to remove them if possible. */ |
a5b022e7 | 857 | |
060b8c19 | 858 | static void |
1d4227c3 | 859 | find_and_remove_re (void) |
a5b022e7 | 860 | { |
060b8c19 | 861 | ext_cand *curr_cand; |
a5b022e7 | 862 | rtx curr_insn = NULL_RTX; |
060b8c19 | 863 | int num_re_opportunities = 0, num_realized = 0, i; |
f1f41a6c | 864 | vec<ext_cand> reinsn_list; |
c2078b80 | 865 | auto_vec<rtx> reinsn_del_list; |
6bd23a69 | 866 | ext_state state; |
a5b022e7 | 867 | |
868 | /* Construct DU chain to get all reaching definitions of each | |
1d4227c3 | 869 | extension instruction. */ |
ea9538fb | 870 | df_set_flags (DF_RD_PRUNE_DEAD_DEFS); |
a5b022e7 | 871 | df_chain_add_problem (DF_UD_CHAIN + DF_DU_CHAIN); |
872 | df_analyze (); | |
6bd23a69 | 873 | df_set_flags (DF_DEFER_INSN_RESCAN); |
a5b022e7 | 874 | |
875 | max_insn_uid = get_max_uid (); | |
1d4227c3 | 876 | reinsn_list = find_removable_extensions (); |
f1f41a6c | 877 | state.defs_list.create (0); |
878 | state.copies_list.create (0); | |
879 | state.modified_list.create (0); | |
880 | state.work_list.create (0); | |
881 | if (reinsn_list.is_empty ()) | |
6bd23a69 | 882 | state.modified = NULL; |
883 | else | |
884 | state.modified = XCNEWVEC (struct ext_modified, max_insn_uid); | |
a5b022e7 | 885 | |
f1f41a6c | 886 | FOR_EACH_VEC_ELT (reinsn_list, i, curr_cand) |
a5b022e7 | 887 | { |
1d4227c3 | 888 | num_re_opportunities++; |
a5b022e7 | 889 | |
060b8c19 | 890 | /* Try to combine the extension with the definition. */ |
a5b022e7 | 891 | if (dump_file) |
892 | { | |
060b8c19 | 893 | fprintf (dump_file, "Trying to eliminate extension:\n"); |
894 | print_rtl_single (dump_file, curr_cand->insn); | |
a5b022e7 | 895 | } |
896 | ||
7715a410 | 897 | if (combine_reaching_defs (curr_cand, curr_cand->expr, &state)) |
a5b022e7 | 898 | { |
899 | if (dump_file) | |
060b8c19 | 900 | fprintf (dump_file, "Eliminated the extension.\n"); |
a5b022e7 | 901 | num_realized++; |
f1f41a6c | 902 | reinsn_del_list.safe_push (curr_cand->insn); |
6bd23a69 | 903 | state.modified[INSN_UID (curr_cand->insn)].deleted = 1; |
a5b022e7 | 904 | } |
905 | } | |
906 | ||
1d4227c3 | 907 | /* Delete all useless extensions here in one sweep. */ |
f1f41a6c | 908 | FOR_EACH_VEC_ELT (reinsn_del_list, i, curr_insn) |
b749ba71 | 909 | delete_insn (curr_insn); |
a5b022e7 | 910 | |
f1f41a6c | 911 | reinsn_list.release (); |
f1f41a6c | 912 | state.defs_list.release (); |
913 | state.copies_list.release (); | |
914 | state.modified_list.release (); | |
915 | state.work_list.release (); | |
6bd23a69 | 916 | XDELETEVEC (state.modified); |
a5b022e7 | 917 | |
1d4227c3 | 918 | if (dump_file && num_re_opportunities > 0) |
060b8c19 | 919 | fprintf (dump_file, "Elimination opportunities = %d realized = %d\n", |
920 | num_re_opportunities, num_realized); | |
a5b022e7 | 921 | } |
922 | ||
1d4227c3 | 923 | /* Find and remove redundant extensions. */ |
a5b022e7 | 924 | |
925 | static unsigned int | |
1d4227c3 | 926 | rest_of_handle_ree (void) |
a5b022e7 | 927 | { |
1d4227c3 | 928 | timevar_push (TV_REE); |
929 | find_and_remove_re (); | |
930 | timevar_pop (TV_REE); | |
a5b022e7 | 931 | return 0; |
932 | } | |
933 | ||
1d4227c3 | 934 | /* Run REE pass when flag_ree is set at optimization level > 0. */ |
a5b022e7 | 935 | |
936 | static bool | |
1d4227c3 | 937 | gate_handle_ree (void) |
a5b022e7 | 938 | { |
1d4227c3 | 939 | return (optimize > 0 && flag_ree); |
a5b022e7 | 940 | } |
941 | ||
cbe8bda8 | 942 | namespace { |
943 | ||
944 | const pass_data pass_data_ree = | |
a5b022e7 | 945 | { |
cbe8bda8 | 946 | RTL_PASS, /* type */ |
947 | "ree", /* name */ | |
948 | OPTGROUP_NONE, /* optinfo_flags */ | |
949 | true, /* has_gate */ | |
950 | true, /* has_execute */ | |
951 | TV_REE, /* tv_id */ | |
952 | 0, /* properties_required */ | |
953 | 0, /* properties_provided */ | |
954 | 0, /* properties_destroyed */ | |
955 | 0, /* todo_flags_start */ | |
956 | ( TODO_df_finish | TODO_verify_rtl_sharing ), /* todo_flags_finish */ | |
a5b022e7 | 957 | }; |
cbe8bda8 | 958 | |
959 | class pass_ree : public rtl_opt_pass | |
960 | { | |
961 | public: | |
9af5ce0c | 962 | pass_ree (gcc::context *ctxt) |
963 | : rtl_opt_pass (pass_data_ree, ctxt) | |
cbe8bda8 | 964 | {} |
965 | ||
966 | /* opt_pass methods: */ | |
967 | bool gate () { return gate_handle_ree (); } | |
968 | unsigned int execute () { return rest_of_handle_ree (); } | |
969 | ||
970 | }; // class pass_ree | |
971 | ||
972 | } // anon namespace | |
973 | ||
974 | rtl_opt_pass * | |
975 | make_pass_ree (gcc::context *ctxt) | |
976 | { | |
977 | return new pass_ree (ctxt); | |
978 | } |