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26cd9add | 1 | /* Redundant Extension Elimination pass for the GNU compiler. |
5624e564 | 2 | Copyright (C) 2010-2015 Free Software Foundation, Inc. |
282bc7b4 | 3 | Contributed by Ilya Enkovich (ilya.enkovich@intel.com) |
26cd9add | 4 | |
282bc7b4 EB |
5 | Based on the Redundant Zero-extension elimination pass contributed by |
6 | Sriraman Tallam (tmsriram@google.com) and Silvius Rus (rus@google.com). | |
87a0ebfd ST |
7 | |
8 | This file is part of GCC. | |
9 | ||
10 | GCC is free software; you can redistribute it and/or modify it under | |
11 | the terms of the GNU General Public License as published by the Free | |
12 | Software Foundation; either version 3, or (at your option) any later | |
13 | version. | |
14 | ||
15 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
16 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
17 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
18 | for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with GCC; see the file COPYING3. If not see | |
22 | <http://www.gnu.org/licenses/>. */ | |
23 | ||
24 | ||
25 | /* Problem Description : | |
26 | -------------------- | |
26cd9add EI |
27 | This pass is intended to remove redundant extension instructions. |
28 | Such instructions appear for different reasons. We expect some of | |
29 | them due to implicit zero-extension in 64-bit registers after writing | |
30 | to their lower 32-bit half (e.g. for the x86-64 architecture). | |
31 | Another possible reason is a type cast which follows a load (for | |
32 | instance a register restore) and which can be combined into a single | |
33 | instruction, and for which earlier local passes, e.g. the combiner, | |
34 | weren't able to optimize. | |
87a0ebfd ST |
35 | |
36 | How does this pass work ? | |
37 | -------------------------- | |
38 | ||
39 | This pass is run after register allocation. Hence, all registers that | |
26cd9add EI |
40 | this pass deals with are hard registers. This pass first looks for an |
41 | extension instruction that could possibly be redundant. Such extension | |
42 | instructions show up in RTL with the pattern : | |
43 | (set (reg:<SWI248> x) (any_extend:<SWI248> (reg:<SWI124> x))), | |
44 | where x can be any hard register. | |
87a0ebfd | 45 | Now, this pass tries to eliminate this instruction by merging the |
26cd9add | 46 | extension with the definitions of register x. For instance, if |
87a0ebfd ST |
47 | one of the definitions of register x was : |
48 | (set (reg:SI x) (plus:SI (reg:SI z1) (reg:SI z2))), | |
26cd9add EI |
49 | followed by extension : |
50 | (set (reg:DI x) (zero_extend:DI (reg:SI x))) | |
87a0ebfd ST |
51 | then the combination converts this into : |
52 | (set (reg:DI x) (zero_extend:DI (plus:SI (reg:SI z1) (reg:SI z2)))). | |
53 | If all the merged definitions are recognizable assembly instructions, | |
26cd9add EI |
54 | the extension is effectively eliminated. |
55 | ||
56 | For example, for the x86-64 architecture, implicit zero-extensions | |
57 | are captured with appropriate patterns in the i386.md file. Hence, | |
58 | these merged definition can be matched to a single assembly instruction. | |
59 | The original extension instruction is then deleted if all the | |
60 | definitions can be merged. | |
87a0ebfd ST |
61 | |
62 | However, there are cases where the definition instruction cannot be | |
26cd9add EI |
63 | merged with an extension. Examples are CALL instructions. In such |
64 | cases, the original extension is not redundant and this pass does | |
87a0ebfd ST |
65 | not delete it. |
66 | ||
67 | Handling conditional moves : | |
68 | ---------------------------- | |
69 | ||
26cd9add EI |
70 | Architectures like x86-64 support conditional moves whose semantics for |
71 | extension differ from the other instructions. For instance, the | |
87a0ebfd ST |
72 | instruction *cmov ebx, eax* |
73 | zero-extends eax onto rax only when the move from ebx to eax happens. | |
282bc7b4 | 74 | Otherwise, eax may not be zero-extended. Consider conditional moves as |
87a0ebfd ST |
75 | RTL instructions of the form |
76 | (set (reg:SI x) (if_then_else (cond) (reg:SI y) (reg:SI z))). | |
26cd9add | 77 | This pass tries to merge an extension with a conditional move by |
282bc7b4 | 78 | actually merging the definitions of y and z with an extension and then |
87a0ebfd ST |
79 | converting the conditional move into : |
80 | (set (reg:DI x) (if_then_else (cond) (reg:DI y) (reg:DI z))). | |
26cd9add EI |
81 | Since registers y and z are extended, register x will also be extended |
82 | after the conditional move. Note that this step has to be done | |
83 | transitively since the definition of a conditional copy can be | |
87a0ebfd ST |
84 | another conditional copy. |
85 | ||
86 | Motivating Example I : | |
87 | --------------------- | |
88 | For this program : | |
89 | ********************************************** | |
90 | bad_code.c | |
91 | ||
92 | int mask[1000]; | |
93 | ||
94 | int foo(unsigned x) | |
95 | { | |
96 | if (x < 10) | |
97 | x = x * 45; | |
98 | else | |
99 | x = x * 78; | |
100 | return mask[x]; | |
101 | } | |
102 | ********************************************** | |
103 | ||
26cd9add | 104 | $ gcc -O2 bad_code.c |
87a0ebfd ST |
105 | ........ |
106 | 400315: b8 4e 00 00 00 mov $0x4e,%eax | |
107 | 40031a: 0f af f8 imul %eax,%edi | |
282bc7b4 | 108 | 40031d: 89 ff mov %edi,%edi - useless extension |
87a0ebfd ST |
109 | 40031f: 8b 04 bd 60 19 40 00 mov 0x401960(,%rdi,4),%eax |
110 | 400326: c3 retq | |
111 | ...... | |
112 | 400330: ba 2d 00 00 00 mov $0x2d,%edx | |
113 | 400335: 0f af fa imul %edx,%edi | |
282bc7b4 | 114 | 400338: 89 ff mov %edi,%edi - useless extension |
87a0ebfd ST |
115 | 40033a: 8b 04 bd 60 19 40 00 mov 0x401960(,%rdi,4),%eax |
116 | 400341: c3 retq | |
117 | ||
26cd9add | 118 | $ gcc -O2 -free bad_code.c |
87a0ebfd ST |
119 | ...... |
120 | 400315: 6b ff 4e imul $0x4e,%edi,%edi | |
121 | 400318: 8b 04 bd 40 19 40 00 mov 0x401940(,%rdi,4),%eax | |
122 | 40031f: c3 retq | |
123 | 400320: 6b ff 2d imul $0x2d,%edi,%edi | |
124 | 400323: 8b 04 bd 40 19 40 00 mov 0x401940(,%rdi,4),%eax | |
125 | 40032a: c3 retq | |
126 | ||
127 | Motivating Example II : | |
128 | --------------------- | |
129 | ||
130 | Here is an example with a conditional move. | |
131 | ||
132 | For this program : | |
133 | ********************************************** | |
134 | ||
135 | unsigned long long foo(unsigned x , unsigned y) | |
136 | { | |
137 | unsigned z; | |
138 | if (x > 100) | |
139 | z = x + y; | |
140 | else | |
141 | z = x - y; | |
142 | return (unsigned long long)(z); | |
143 | } | |
144 | ||
26cd9add | 145 | $ gcc -O2 bad_code.c |
87a0ebfd ST |
146 | ............ |
147 | 400360: 8d 14 3e lea (%rsi,%rdi,1),%edx | |
148 | 400363: 89 f8 mov %edi,%eax | |
149 | 400365: 29 f0 sub %esi,%eax | |
150 | 400367: 83 ff 65 cmp $0x65,%edi | |
151 | 40036a: 0f 43 c2 cmovae %edx,%eax | |
282bc7b4 | 152 | 40036d: 89 c0 mov %eax,%eax - useless extension |
87a0ebfd ST |
153 | 40036f: c3 retq |
154 | ||
26cd9add | 155 | $ gcc -O2 -free bad_code.c |
87a0ebfd ST |
156 | ............. |
157 | 400360: 89 fa mov %edi,%edx | |
158 | 400362: 8d 04 3e lea (%rsi,%rdi,1),%eax | |
159 | 400365: 29 f2 sub %esi,%edx | |
160 | 400367: 83 ff 65 cmp $0x65,%edi | |
161 | 40036a: 89 d6 mov %edx,%esi | |
162 | 40036c: 48 0f 42 c6 cmovb %rsi,%rax | |
163 | 400370: c3 retq | |
164 | ||
26cd9add EI |
165 | Motivating Example III : |
166 | --------------------- | |
167 | ||
168 | Here is an example with a type cast. | |
169 | ||
170 | For this program : | |
171 | ********************************************** | |
172 | ||
173 | void test(int size, unsigned char *in, unsigned char *out) | |
174 | { | |
175 | int i; | |
176 | unsigned char xr, xg, xy=0; | |
177 | ||
178 | for (i = 0; i < size; i++) { | |
179 | xr = *in++; | |
180 | xg = *in++; | |
181 | xy = (unsigned char) ((19595*xr + 38470*xg) >> 16); | |
182 | *out++ = xy; | |
183 | } | |
184 | } | |
185 | ||
186 | $ gcc -O2 bad_code.c | |
187 | ............ | |
188 | 10: 0f b6 0e movzbl (%rsi),%ecx | |
189 | 13: 0f b6 46 01 movzbl 0x1(%rsi),%eax | |
190 | 17: 48 83 c6 02 add $0x2,%rsi | |
282bc7b4 EB |
191 | 1b: 0f b6 c9 movzbl %cl,%ecx - useless extension |
192 | 1e: 0f b6 c0 movzbl %al,%eax - useless extension | |
26cd9add EI |
193 | 21: 69 c9 8b 4c 00 00 imul $0x4c8b,%ecx,%ecx |
194 | 27: 69 c0 46 96 00 00 imul $0x9646,%eax,%eax | |
195 | ||
196 | $ gcc -O2 -free bad_code.c | |
197 | ............. | |
198 | 10: 0f b6 0e movzbl (%rsi),%ecx | |
199 | 13: 0f b6 46 01 movzbl 0x1(%rsi),%eax | |
200 | 17: 48 83 c6 02 add $0x2,%rsi | |
201 | 1b: 69 c9 8b 4c 00 00 imul $0x4c8b,%ecx,%ecx | |
202 | 21: 69 c0 46 96 00 00 imul $0x9646,%eax,%eax | |
87a0ebfd ST |
203 | |
204 | Usefulness : | |
205 | ---------- | |
206 | ||
26cd9add EI |
207 | The original redundant zero-extension elimination pass reported reduction |
208 | of the dynamic instruction count of a compression benchmark by 2.8% and | |
209 | improvement of its run time by about 1%. | |
87a0ebfd | 210 | |
26cd9add EI |
211 | The additional performance gain with the enhanced pass is mostly expected |
212 | on in-order architectures where redundancy cannot be compensated by out of | |
213 | order execution. Measurements showed up to 10% performance gain (reduced | |
214 | run time) on EEMBC 2.0 benchmarks on Atom processor with geomean performance | |
215 | gain 1%. */ | |
87a0ebfd ST |
216 | |
217 | ||
218 | #include "config.h" | |
219 | #include "system.h" | |
220 | #include "coretypes.h" | |
221 | #include "tm.h" | |
222 | #include "rtl.h" | |
40e23961 MC |
223 | #include "alias.h" |
224 | #include "symtab.h" | |
87a0ebfd ST |
225 | #include "tree.h" |
226 | #include "tm_p.h" | |
227 | #include "flags.h" | |
228 | #include "regs.h" | |
229 | #include "hard-reg-set.h" | |
60393bbc | 230 | #include "predict.h" |
87a0ebfd | 231 | #include "function.h" |
60393bbc AM |
232 | #include "dominance.h" |
233 | #include "cfg.h" | |
234 | #include "cfgrtl.h" | |
235 | #include "basic-block.h" | |
236 | #include "insn-config.h" | |
36566b39 PK |
237 | #include "expmed.h" |
238 | #include "dojump.h" | |
239 | #include "explow.h" | |
240 | #include "calls.h" | |
241 | #include "emit-rtl.h" | |
242 | #include "varasm.h" | |
243 | #include "stmt.h" | |
87a0ebfd ST |
244 | #include "expr.h" |
245 | #include "insn-attr.h" | |
246 | #include "recog.h" | |
718f9c0f | 247 | #include "diagnostic-core.h" |
87a0ebfd | 248 | #include "target.h" |
87a0ebfd | 249 | #include "insn-codes.h" |
b0710fe1 | 250 | #include "optabs.h" |
87a0ebfd | 251 | #include "rtlhooks-def.h" |
87a0ebfd | 252 | #include "params.h" |
87a0ebfd ST |
253 | #include "tree-pass.h" |
254 | #include "df.h" | |
255 | #include "cgraph.h" | |
256 | ||
282bc7b4 | 257 | /* This structure represents a candidate for elimination. */ |
87a0ebfd | 258 | |
8a1239ac | 259 | typedef struct ext_cand |
87a0ebfd | 260 | { |
282bc7b4 EB |
261 | /* The expression. */ |
262 | const_rtx expr; | |
87a0ebfd | 263 | |
282bc7b4 EB |
264 | /* The kind of extension. */ |
265 | enum rtx_code code; | |
26cd9add | 266 | |
282bc7b4 | 267 | /* The destination mode. */ |
ef4bddc2 | 268 | machine_mode mode; |
282bc7b4 EB |
269 | |
270 | /* The instruction where it lives. */ | |
59a0c032 | 271 | rtx_insn *insn; |
282bc7b4 | 272 | } ext_cand; |
26cd9add | 273 | |
26cd9add | 274 | |
87a0ebfd ST |
275 | static int max_insn_uid; |
276 | ||
73c49bf5 JJ |
277 | /* Update or remove REG_EQUAL or REG_EQUIV notes for INSN. */ |
278 | ||
279 | static bool | |
280 | update_reg_equal_equiv_notes (rtx_insn *insn, machine_mode new_mode, | |
281 | machine_mode old_mode, enum rtx_code code) | |
282 | { | |
283 | rtx *loc = ®_NOTES (insn); | |
284 | while (*loc) | |
285 | { | |
286 | enum reg_note kind = REG_NOTE_KIND (*loc); | |
287 | if (kind == REG_EQUAL || kind == REG_EQUIV) | |
288 | { | |
289 | rtx orig_src = XEXP (*loc, 0); | |
290 | /* Update equivalency constants. Recall that RTL constants are | |
291 | sign-extended. */ | |
292 | if (GET_CODE (orig_src) == CONST_INT | |
293 | && HOST_BITS_PER_WIDE_INT >= GET_MODE_BITSIZE (new_mode)) | |
294 | { | |
295 | if (INTVAL (orig_src) >= 0 || code == SIGN_EXTEND) | |
296 | /* Nothing needed. */; | |
297 | else | |
298 | { | |
299 | /* Zero-extend the negative constant by masking out the | |
300 | bits outside the source mode. */ | |
301 | rtx new_const_int | |
302 | = gen_int_mode (INTVAL (orig_src) | |
303 | & GET_MODE_MASK (old_mode), | |
304 | new_mode); | |
305 | if (!validate_change (insn, &XEXP (*loc, 0), | |
306 | new_const_int, true)) | |
307 | return false; | |
308 | } | |
309 | loc = &XEXP (*loc, 1); | |
310 | } | |
311 | /* Drop all other notes, they assume a wrong mode. */ | |
312 | else if (!validate_change (insn, loc, XEXP (*loc, 1), true)) | |
313 | return false; | |
314 | } | |
315 | else | |
316 | loc = &XEXP (*loc, 1); | |
317 | } | |
318 | return true; | |
319 | } | |
320 | ||
26cd9add EI |
321 | /* Given a insn (CURR_INSN), an extension candidate for removal (CAND) |
322 | and a pointer to the SET rtx (ORIG_SET) that needs to be modified, | |
323 | this code modifies the SET rtx to a new SET rtx that extends the | |
324 | right hand expression into a register on the left hand side. Note | |
325 | that multiple assumptions are made about the nature of the set that | |
326 | needs to be true for this to work and is called from merge_def_and_ext. | |
87a0ebfd ST |
327 | |
328 | Original : | |
26cd9add | 329 | (set (reg a) (expression)) |
87a0ebfd ST |
330 | |
331 | Transform : | |
282bc7b4 | 332 | (set (reg a) (any_extend (expression))) |
87a0ebfd ST |
333 | |
334 | Special Cases : | |
282bc7b4 | 335 | If the expression is a constant or another extension, then directly |
26cd9add | 336 | assign it to the register. */ |
87a0ebfd ST |
337 | |
338 | static bool | |
59a0c032 | 339 | combine_set_extension (ext_cand *cand, rtx_insn *curr_insn, rtx *orig_set) |
87a0ebfd | 340 | { |
282bc7b4 | 341 | rtx orig_src = SET_SRC (*orig_set); |
73c49bf5 | 342 | machine_mode orig_mode = GET_MODE (SET_DEST (*orig_set)); |
282bc7b4 | 343 | rtx new_set; |
3c92da90 JL |
344 | rtx cand_pat = PATTERN (cand->insn); |
345 | ||
346 | /* If the extension's source/destination registers are not the same | |
347 | then we need to change the original load to reference the destination | |
348 | of the extension. Then we need to emit a copy from that destination | |
349 | to the original destination of the load. */ | |
350 | rtx new_reg; | |
351 | bool copy_needed | |
352 | = (REGNO (SET_DEST (cand_pat)) != REGNO (XEXP (SET_SRC (cand_pat), 0))); | |
353 | if (copy_needed) | |
354 | new_reg = gen_rtx_REG (cand->mode, REGNO (SET_DEST (cand_pat))); | |
355 | else | |
356 | new_reg = gen_rtx_REG (cand->mode, REGNO (SET_DEST (*orig_set))); | |
87a0ebfd | 357 | |
2043135a JL |
358 | #if 0 |
359 | /* Rethinking test. Temporarily disabled. */ | |
a6a2d67b JL |
360 | /* We're going to be widening the result of DEF_INSN, ensure that doing so |
361 | doesn't change the number of hard registers needed for the result. */ | |
362 | if (HARD_REGNO_NREGS (REGNO (new_reg), cand->mode) | |
2043135a JL |
363 | != HARD_REGNO_NREGS (REGNO (SET_DEST (*orig_set)), |
364 | GET_MODE (SET_DEST (*orig_set)))) | |
a6a2d67b | 365 | return false; |
2043135a | 366 | #endif |
a6a2d67b | 367 | |
282bc7b4 EB |
368 | /* Merge constants by directly moving the constant into the register under |
369 | some conditions. Recall that RTL constants are sign-extended. */ | |
26cd9add | 370 | if (GET_CODE (orig_src) == CONST_INT |
282bc7b4 | 371 | && HOST_BITS_PER_WIDE_INT >= GET_MODE_BITSIZE (cand->mode)) |
26cd9add | 372 | { |
282bc7b4 | 373 | if (INTVAL (orig_src) >= 0 || cand->code == SIGN_EXTEND) |
f7df4a84 | 374 | new_set = gen_rtx_SET (new_reg, orig_src); |
87a0ebfd | 375 | else |
26cd9add EI |
376 | { |
377 | /* Zero-extend the negative constant by masking out the bits outside | |
378 | the source mode. */ | |
282bc7b4 | 379 | rtx new_const_int |
73c49bf5 | 380 | = gen_int_mode (INTVAL (orig_src) & GET_MODE_MASK (orig_mode), |
69db2d57 | 381 | GET_MODE (new_reg)); |
f7df4a84 | 382 | new_set = gen_rtx_SET (new_reg, new_const_int); |
26cd9add EI |
383 | } |
384 | } | |
385 | else if (GET_MODE (orig_src) == VOIDmode) | |
386 | { | |
282bc7b4 | 387 | /* This is mostly due to a call insn that should not be optimized. */ |
26cd9add | 388 | return false; |
87a0ebfd | 389 | } |
282bc7b4 | 390 | else if (GET_CODE (orig_src) == cand->code) |
87a0ebfd | 391 | { |
282bc7b4 EB |
392 | /* Here is a sequence of two extensions. Try to merge them. */ |
393 | rtx temp_extension | |
394 | = gen_rtx_fmt_e (cand->code, cand->mode, XEXP (orig_src, 0)); | |
395 | rtx simplified_temp_extension = simplify_rtx (temp_extension); | |
87a0ebfd ST |
396 | if (simplified_temp_extension) |
397 | temp_extension = simplified_temp_extension; | |
f7df4a84 | 398 | new_set = gen_rtx_SET (new_reg, temp_extension); |
87a0ebfd ST |
399 | } |
400 | else if (GET_CODE (orig_src) == IF_THEN_ELSE) | |
401 | { | |
26cd9add | 402 | /* Only IF_THEN_ELSE of phi-type copies are combined. Otherwise, |
87a0ebfd | 403 | in general, IF_THEN_ELSE should not be combined. */ |
87a0ebfd ST |
404 | return false; |
405 | } | |
406 | else | |
407 | { | |
282bc7b4 EB |
408 | /* This is the normal case. */ |
409 | rtx temp_extension | |
410 | = gen_rtx_fmt_e (cand->code, cand->mode, orig_src); | |
411 | rtx simplified_temp_extension = simplify_rtx (temp_extension); | |
87a0ebfd ST |
412 | if (simplified_temp_extension) |
413 | temp_extension = simplified_temp_extension; | |
f7df4a84 | 414 | new_set = gen_rtx_SET (new_reg, temp_extension); |
87a0ebfd ST |
415 | } |
416 | ||
26cd9add | 417 | /* This change is a part of a group of changes. Hence, |
87a0ebfd | 418 | validate_change will not try to commit the change. */ |
73c49bf5 JJ |
419 | if (validate_change (curr_insn, orig_set, new_set, true) |
420 | && update_reg_equal_equiv_notes (curr_insn, cand->mode, orig_mode, | |
421 | cand->code)) | |
87a0ebfd ST |
422 | { |
423 | if (dump_file) | |
424 | { | |
ca10595c | 425 | fprintf (dump_file, |
3c92da90 JL |
426 | "Tentatively merged extension with definition %s:\n", |
427 | (copy_needed) ? "(copy needed)" : ""); | |
87a0ebfd ST |
428 | print_rtl_single (dump_file, curr_insn); |
429 | } | |
430 | return true; | |
431 | } | |
282bc7b4 | 432 | |
87a0ebfd ST |
433 | return false; |
434 | } | |
435 | ||
87a0ebfd | 436 | /* Treat if_then_else insns, where the operands of both branches |
26cd9add | 437 | are registers, as copies. For instance, |
87a0ebfd ST |
438 | Original : |
439 | (set (reg:SI a) (if_then_else (cond) (reg:SI b) (reg:SI c))) | |
440 | Transformed : | |
441 | (set (reg:DI a) (if_then_else (cond) (reg:DI b) (reg:DI c))) | |
442 | DEF_INSN is the if_then_else insn. */ | |
443 | ||
444 | static bool | |
59a0c032 | 445 | transform_ifelse (ext_cand *cand, rtx_insn *def_insn) |
87a0ebfd ST |
446 | { |
447 | rtx set_insn = PATTERN (def_insn); | |
448 | rtx srcreg, dstreg, srcreg2; | |
449 | rtx map_srcreg, map_dstreg, map_srcreg2; | |
450 | rtx ifexpr; | |
451 | rtx cond; | |
452 | rtx new_set; | |
453 | ||
454 | gcc_assert (GET_CODE (set_insn) == SET); | |
282bc7b4 | 455 | |
87a0ebfd ST |
456 | cond = XEXP (SET_SRC (set_insn), 0); |
457 | dstreg = SET_DEST (set_insn); | |
458 | srcreg = XEXP (SET_SRC (set_insn), 1); | |
459 | srcreg2 = XEXP (SET_SRC (set_insn), 2); | |
b57cca0b JJ |
460 | /* If the conditional move already has the right or wider mode, |
461 | there is nothing to do. */ | |
462 | if (GET_MODE_SIZE (GET_MODE (dstreg)) >= GET_MODE_SIZE (cand->mode)) | |
463 | return true; | |
464 | ||
282bc7b4 EB |
465 | map_srcreg = gen_rtx_REG (cand->mode, REGNO (srcreg)); |
466 | map_srcreg2 = gen_rtx_REG (cand->mode, REGNO (srcreg2)); | |
467 | map_dstreg = gen_rtx_REG (cand->mode, REGNO (dstreg)); | |
468 | ifexpr = gen_rtx_IF_THEN_ELSE (cand->mode, cond, map_srcreg, map_srcreg2); | |
f7df4a84 | 469 | new_set = gen_rtx_SET (map_dstreg, ifexpr); |
87a0ebfd | 470 | |
73c49bf5 JJ |
471 | if (validate_change (def_insn, &PATTERN (def_insn), new_set, true) |
472 | && update_reg_equal_equiv_notes (def_insn, cand->mode, GET_MODE (dstreg), | |
473 | cand->code)) | |
87a0ebfd ST |
474 | { |
475 | if (dump_file) | |
476 | { | |
282bc7b4 EB |
477 | fprintf (dump_file, |
478 | "Mode of conditional move instruction extended:\n"); | |
87a0ebfd ST |
479 | print_rtl_single (dump_file, def_insn); |
480 | } | |
481 | return true; | |
482 | } | |
282bc7b4 EB |
483 | |
484 | return false; | |
87a0ebfd ST |
485 | } |
486 | ||
282bc7b4 EB |
487 | /* Get all the reaching definitions of an instruction. The definitions are |
488 | desired for REG used in INSN. Return the definition list or NULL if a | |
489 | definition is missing. If DEST is non-NULL, additionally push the INSN | |
490 | of the definitions onto DEST. */ | |
87a0ebfd | 491 | |
282bc7b4 | 492 | static struct df_link * |
59a0c032 | 493 | get_defs (rtx_insn *insn, rtx reg, vec<rtx_insn *> *dest) |
87a0ebfd | 494 | { |
bfac633a | 495 | df_ref use; |
282bc7b4 | 496 | struct df_link *ref_chain, *ref_link; |
87a0ebfd | 497 | |
bfac633a | 498 | FOR_EACH_INSN_USE (use, insn) |
87a0ebfd | 499 | { |
bfac633a | 500 | if (GET_CODE (DF_REF_REG (use)) == SUBREG) |
282bc7b4 | 501 | return NULL; |
bfac633a RS |
502 | if (REGNO (DF_REF_REG (use)) == REGNO (reg)) |
503 | break; | |
87a0ebfd ST |
504 | } |
505 | ||
bfac633a | 506 | gcc_assert (use != NULL); |
87a0ebfd | 507 | |
bfac633a | 508 | ref_chain = DF_REF_CHAIN (use); |
282bc7b4 EB |
509 | |
510 | for (ref_link = ref_chain; ref_link; ref_link = ref_link->next) | |
87a0ebfd ST |
511 | { |
512 | /* Problem getting some definition for this instruction. */ | |
282bc7b4 EB |
513 | if (ref_link->ref == NULL) |
514 | return NULL; | |
515 | if (DF_REF_INSN_INFO (ref_link->ref) == NULL) | |
516 | return NULL; | |
87a0ebfd ST |
517 | } |
518 | ||
282bc7b4 EB |
519 | if (dest) |
520 | for (ref_link = ref_chain; ref_link; ref_link = ref_link->next) | |
9771b263 | 521 | dest->safe_push (DF_REF_INSN (ref_link->ref)); |
87a0ebfd | 522 | |
282bc7b4 | 523 | return ref_chain; |
87a0ebfd ST |
524 | } |
525 | ||
282bc7b4 EB |
526 | /* Return true if INSN is |
527 | (SET (reg REGNO (def_reg)) (if_then_else (cond) (REG x1) (REG x2))) | |
528 | and store x1 and x2 in REG_1 and REG_2. */ | |
87a0ebfd | 529 | |
282bc7b4 | 530 | static bool |
59a0c032 | 531 | is_cond_copy_insn (rtx_insn *insn, rtx *reg1, rtx *reg2) |
87a0ebfd | 532 | { |
282bc7b4 | 533 | rtx expr = single_set (insn); |
87a0ebfd | 534 | |
282bc7b4 EB |
535 | if (expr != NULL_RTX |
536 | && GET_CODE (expr) == SET | |
87a0ebfd | 537 | && GET_CODE (SET_DEST (expr)) == REG |
87a0ebfd ST |
538 | && GET_CODE (SET_SRC (expr)) == IF_THEN_ELSE |
539 | && GET_CODE (XEXP (SET_SRC (expr), 1)) == REG | |
26cd9add | 540 | && GET_CODE (XEXP (SET_SRC (expr), 2)) == REG) |
87a0ebfd | 541 | { |
282bc7b4 EB |
542 | *reg1 = XEXP (SET_SRC (expr), 1); |
543 | *reg2 = XEXP (SET_SRC (expr), 2); | |
544 | return true; | |
87a0ebfd ST |
545 | } |
546 | ||
282bc7b4 | 547 | return false; |
87a0ebfd ST |
548 | } |
549 | ||
b57cca0b JJ |
550 | enum ext_modified_kind |
551 | { | |
552 | /* The insn hasn't been modified by ree pass yet. */ | |
553 | EXT_MODIFIED_NONE, | |
554 | /* Changed into zero extension. */ | |
555 | EXT_MODIFIED_ZEXT, | |
556 | /* Changed into sign extension. */ | |
557 | EXT_MODIFIED_SEXT | |
558 | }; | |
559 | ||
925e30ff | 560 | struct ATTRIBUTE_PACKED ext_modified |
b57cca0b JJ |
561 | { |
562 | /* Mode from which ree has zero or sign extended the destination. */ | |
563 | ENUM_BITFIELD(machine_mode) mode : 8; | |
564 | ||
565 | /* Kind of modification of the insn. */ | |
566 | ENUM_BITFIELD(ext_modified_kind) kind : 2; | |
567 | ||
0d732cca JL |
568 | unsigned int do_not_reextend : 1; |
569 | ||
b57cca0b JJ |
570 | /* True if the insn is scheduled to be deleted. */ |
571 | unsigned int deleted : 1; | |
572 | }; | |
573 | ||
574 | /* Vectors used by combine_reaching_defs and its helpers. */ | |
575 | typedef struct ext_state | |
576 | { | |
9771b263 | 577 | /* In order to avoid constant alloc/free, we keep these |
b57cca0b | 578 | 4 vectors live through the entire find_and_remove_re and just |
9771b263 | 579 | truncate them each time. */ |
59a0c032 DM |
580 | vec<rtx_insn *> defs_list; |
581 | vec<rtx_insn *> copies_list; | |
582 | vec<rtx_insn *> modified_list; | |
583 | vec<rtx_insn *> work_list; | |
b57cca0b JJ |
584 | |
585 | /* For instructions that have been successfully modified, this is | |
586 | the original mode from which the insn is extending and | |
587 | kind of extension. */ | |
588 | struct ext_modified *modified; | |
589 | } ext_state; | |
590 | ||
26cd9add EI |
591 | /* Reaching Definitions of the extended register could be conditional copies |
592 | or regular definitions. This function separates the two types into two | |
b57cca0b JJ |
593 | lists, STATE->DEFS_LIST and STATE->COPIES_LIST. This is necessary because, |
594 | if a reaching definition is a conditional copy, merging the extension with | |
595 | this definition is wrong. Conditional copies are merged by transitively | |
596 | merging their definitions. The defs_list is populated with all the reaching | |
597 | definitions of the extension instruction (EXTEND_INSN) which must be merged | |
598 | with an extension. The copies_list contains all the conditional moves that | |
599 | will later be extended into a wider mode conditional move if all the merges | |
600 | are successful. The function returns false upon failure, true upon | |
601 | success. */ | |
602 | ||
603 | static bool | |
59a0c032 | 604 | make_defs_and_copies_lists (rtx_insn *extend_insn, const_rtx set_pat, |
b57cca0b | 605 | ext_state *state) |
87a0ebfd | 606 | { |
282bc7b4 | 607 | rtx src_reg = XEXP (SET_SRC (set_pat), 0); |
87a0ebfd | 608 | bool *is_insn_visited; |
b57cca0b JJ |
609 | bool ret = true; |
610 | ||
9771b263 | 611 | state->work_list.truncate (0); |
87a0ebfd | 612 | |
282bc7b4 | 613 | /* Initialize the work list. */ |
b57cca0b JJ |
614 | if (!get_defs (extend_insn, src_reg, &state->work_list)) |
615 | gcc_unreachable (); | |
87a0ebfd | 616 | |
282bc7b4 | 617 | is_insn_visited = XCNEWVEC (bool, max_insn_uid); |
87a0ebfd ST |
618 | |
619 | /* Perform transitive closure for conditional copies. */ | |
9771b263 | 620 | while (!state->work_list.is_empty ()) |
87a0ebfd | 621 | { |
59a0c032 | 622 | rtx_insn *def_insn = state->work_list.pop (); |
282bc7b4 EB |
623 | rtx reg1, reg2; |
624 | ||
87a0ebfd ST |
625 | gcc_assert (INSN_UID (def_insn) < max_insn_uid); |
626 | ||
627 | if (is_insn_visited[INSN_UID (def_insn)]) | |
282bc7b4 | 628 | continue; |
87a0ebfd | 629 | is_insn_visited[INSN_UID (def_insn)] = true; |
87a0ebfd | 630 | |
282bc7b4 EB |
631 | if (is_cond_copy_insn (def_insn, ®1, ®2)) |
632 | { | |
633 | /* Push it onto the copy list first. */ | |
9771b263 | 634 | state->copies_list.safe_push (def_insn); |
282bc7b4 EB |
635 | |
636 | /* Now perform the transitive closure. */ | |
b57cca0b JJ |
637 | if (!get_defs (def_insn, reg1, &state->work_list) |
638 | || !get_defs (def_insn, reg2, &state->work_list)) | |
282bc7b4 | 639 | { |
b57cca0b | 640 | ret = false; |
282bc7b4 EB |
641 | break; |
642 | } | |
87a0ebfd ST |
643 | } |
644 | else | |
9771b263 | 645 | state->defs_list.safe_push (def_insn); |
87a0ebfd ST |
646 | } |
647 | ||
87a0ebfd | 648 | XDELETEVEC (is_insn_visited); |
282bc7b4 EB |
649 | |
650 | return ret; | |
87a0ebfd ST |
651 | } |
652 | ||
650c4c85 JL |
653 | /* If DEF_INSN has single SET expression, possibly buried inside |
654 | a PARALLEL, return the address of the SET expression, else | |
655 | return NULL. This is similar to single_set, except that | |
656 | single_set allows multiple SETs when all but one is dead. */ | |
657 | static rtx * | |
59a0c032 | 658 | get_sub_rtx (rtx_insn *def_insn) |
87a0ebfd | 659 | { |
650c4c85 JL |
660 | enum rtx_code code = GET_CODE (PATTERN (def_insn)); |
661 | rtx *sub_rtx = NULL; | |
87a0ebfd ST |
662 | |
663 | if (code == PARALLEL) | |
664 | { | |
650c4c85 | 665 | for (int i = 0; i < XVECLEN (PATTERN (def_insn), 0); i++) |
87a0ebfd | 666 | { |
650c4c85 | 667 | rtx s_expr = XVECEXP (PATTERN (def_insn), 0, i); |
87a0ebfd ST |
668 | if (GET_CODE (s_expr) != SET) |
669 | continue; | |
670 | ||
671 | if (sub_rtx == NULL) | |
672 | sub_rtx = &XVECEXP (PATTERN (def_insn), 0, i); | |
673 | else | |
674 | { | |
675 | /* PARALLEL with multiple SETs. */ | |
650c4c85 | 676 | return NULL; |
87a0ebfd ST |
677 | } |
678 | } | |
679 | } | |
680 | else if (code == SET) | |
681 | sub_rtx = &PATTERN (def_insn); | |
682 | else | |
683 | { | |
684 | /* It is not a PARALLEL or a SET, what could it be ? */ | |
650c4c85 | 685 | return NULL; |
87a0ebfd ST |
686 | } |
687 | ||
688 | gcc_assert (sub_rtx != NULL); | |
650c4c85 JL |
689 | return sub_rtx; |
690 | } | |
691 | ||
692 | /* Merge the DEF_INSN with an extension. Calls combine_set_extension | |
693 | on the SET pattern. */ | |
694 | ||
695 | static bool | |
59a0c032 | 696 | merge_def_and_ext (ext_cand *cand, rtx_insn *def_insn, ext_state *state) |
650c4c85 | 697 | { |
ef4bddc2 | 698 | machine_mode ext_src_mode; |
650c4c85 JL |
699 | rtx *sub_rtx; |
700 | ||
701 | ext_src_mode = GET_MODE (XEXP (SET_SRC (cand->expr), 0)); | |
702 | sub_rtx = get_sub_rtx (def_insn); | |
703 | ||
704 | if (sub_rtx == NULL) | |
705 | return false; | |
87a0ebfd | 706 | |
b57cca0b JJ |
707 | if (REG_P (SET_DEST (*sub_rtx)) |
708 | && (GET_MODE (SET_DEST (*sub_rtx)) == ext_src_mode | |
709 | || ((state->modified[INSN_UID (def_insn)].kind | |
710 | == (cand->code == ZERO_EXTEND | |
711 | ? EXT_MODIFIED_ZEXT : EXT_MODIFIED_SEXT)) | |
712 | && state->modified[INSN_UID (def_insn)].mode | |
713 | == ext_src_mode))) | |
87a0ebfd | 714 | { |
b57cca0b JJ |
715 | if (GET_MODE_SIZE (GET_MODE (SET_DEST (*sub_rtx))) |
716 | >= GET_MODE_SIZE (cand->mode)) | |
717 | return true; | |
718 | /* If def_insn is already scheduled to be deleted, don't attempt | |
719 | to modify it. */ | |
720 | if (state->modified[INSN_UID (def_insn)].deleted) | |
721 | return false; | |
722 | if (combine_set_extension (cand, def_insn, sub_rtx)) | |
723 | { | |
724 | if (state->modified[INSN_UID (def_insn)].kind == EXT_MODIFIED_NONE) | |
725 | state->modified[INSN_UID (def_insn)].mode = ext_src_mode; | |
726 | return true; | |
727 | } | |
87a0ebfd | 728 | } |
26cd9add EI |
729 | |
730 | return false; | |
87a0ebfd ST |
731 | } |
732 | ||
059742a4 JL |
733 | /* Given SRC, which should be one or more extensions of a REG, strip |
734 | away the extensions and return the REG. */ | |
735 | ||
736 | static inline rtx | |
737 | get_extended_src_reg (rtx src) | |
738 | { | |
739 | while (GET_CODE (src) == SIGN_EXTEND || GET_CODE (src) == ZERO_EXTEND) | |
740 | src = XEXP (src, 0); | |
741 | gcc_assert (REG_P (src)); | |
742 | return src; | |
743 | } | |
744 | ||
87a0ebfd | 745 | /* This function goes through all reaching defs of the source |
26cd9add EI |
746 | of the candidate for elimination (CAND) and tries to combine |
747 | the extension with the definition instruction. The changes | |
748 | are made as a group so that even if one definition cannot be | |
749 | merged, all reaching definitions end up not being merged. | |
750 | When a conditional copy is encountered, merging is attempted | |
751 | transitively on its definitions. It returns true upon success | |
752 | and false upon failure. */ | |
87a0ebfd ST |
753 | |
754 | static bool | |
089dacc5 | 755 | combine_reaching_defs (ext_cand *cand, const_rtx set_pat, ext_state *state) |
87a0ebfd | 756 | { |
59a0c032 | 757 | rtx_insn *def_insn; |
87a0ebfd ST |
758 | bool merge_successful = true; |
759 | int i; | |
760 | int defs_ix; | |
b57cca0b | 761 | bool outcome; |
87a0ebfd | 762 | |
9771b263 DN |
763 | state->defs_list.truncate (0); |
764 | state->copies_list.truncate (0); | |
87a0ebfd | 765 | |
b57cca0b | 766 | outcome = make_defs_and_copies_lists (cand->insn, set_pat, state); |
87a0ebfd | 767 | |
b57cca0b JJ |
768 | if (!outcome) |
769 | return false; | |
87a0ebfd | 770 | |
3c92da90 JL |
771 | /* If the destination operand of the extension is a different |
772 | register than the source operand, then additional restrictions | |
059742a4 JL |
773 | are needed. Note we have to handle cases where we have nested |
774 | extensions in the source operand. */ | |
0d732cca JL |
775 | bool copy_needed |
776 | = (REGNO (SET_DEST (PATTERN (cand->insn))) | |
777 | != REGNO (get_extended_src_reg (SET_SRC (PATTERN (cand->insn))))); | |
778 | if (copy_needed) | |
3c92da90 | 779 | { |
860dadcb JJ |
780 | /* Considering transformation of |
781 | (set (reg1) (expression)) | |
782 | ... | |
783 | (set (reg2) (any_extend (reg1))) | |
784 | ||
785 | into | |
786 | ||
787 | (set (reg2) (any_extend (expression))) | |
788 | (set (reg1) (reg2)) | |
789 | ... */ | |
790 | ||
3c92da90 JL |
791 | /* In theory we could handle more than one reaching def, it |
792 | just makes the code to update the insn stream more complex. */ | |
793 | if (state->defs_list.length () != 1) | |
794 | return false; | |
795 | ||
059742a4 JL |
796 | /* We require the candidate not already be modified. It may, |
797 | for example have been changed from a (sign_extend (reg)) | |
0d732cca | 798 | into (zero_extend (sign_extend (reg))). |
059742a4 JL |
799 | |
800 | Handling that case shouldn't be terribly difficult, but the code | |
801 | here and the code to emit copies would need auditing. Until | |
802 | we see a need, this is the safe thing to do. */ | |
3c92da90 JL |
803 | if (state->modified[INSN_UID (cand->insn)].kind != EXT_MODIFIED_NONE) |
804 | return false; | |
805 | ||
ef4bddc2 | 806 | machine_mode dst_mode = GET_MODE (SET_DEST (PATTERN (cand->insn))); |
e533e26c WD |
807 | rtx src_reg = get_extended_src_reg (SET_SRC (PATTERN (cand->insn))); |
808 | ||
809 | /* Ensure the number of hard registers of the copy match. */ | |
810 | if (HARD_REGNO_NREGS (REGNO (src_reg), dst_mode) | |
811 | != HARD_REGNO_NREGS (REGNO (src_reg), GET_MODE (src_reg))) | |
812 | return false; | |
813 | ||
3c92da90 | 814 | /* There's only one reaching def. */ |
59a0c032 | 815 | rtx_insn *def_insn = state->defs_list[0]; |
3c92da90 JL |
816 | |
817 | /* The defining statement must not have been modified either. */ | |
818 | if (state->modified[INSN_UID (def_insn)].kind != EXT_MODIFIED_NONE) | |
819 | return false; | |
820 | ||
821 | /* The defining statement and candidate insn must be in the same block. | |
822 | This is merely to keep the test for safety and updating the insn | |
7e41c852 JL |
823 | stream simple. Also ensure that within the block the candidate |
824 | follows the defining insn. */ | |
daca1a96 RS |
825 | basic_block bb = BLOCK_FOR_INSN (cand->insn); |
826 | if (bb != BLOCK_FOR_INSN (def_insn) | |
7e41c852 | 827 | || DF_INSN_LUID (def_insn) > DF_INSN_LUID (cand->insn)) |
3c92da90 JL |
828 | return false; |
829 | ||
830 | /* If there is an overlap between the destination of DEF_INSN and | |
831 | CAND->insn, then this transformation is not safe. Note we have | |
832 | to test in the widened mode. */ | |
650c4c85 JL |
833 | rtx *dest_sub_rtx = get_sub_rtx (def_insn); |
834 | if (dest_sub_rtx == NULL | |
835 | || !REG_P (SET_DEST (*dest_sub_rtx))) | |
836 | return false; | |
837 | ||
3c92da90 | 838 | rtx tmp_reg = gen_rtx_REG (GET_MODE (SET_DEST (PATTERN (cand->insn))), |
650c4c85 | 839 | REGNO (SET_DEST (*dest_sub_rtx))); |
3c92da90 JL |
840 | if (reg_overlap_mentioned_p (tmp_reg, SET_DEST (PATTERN (cand->insn)))) |
841 | return false; | |
842 | ||
843 | /* The destination register of the extension insn must not be | |
844 | used or set between the def_insn and cand->insn exclusive. */ | |
845 | if (reg_used_between_p (SET_DEST (PATTERN (cand->insn)), | |
846 | def_insn, cand->insn) | |
847 | || reg_set_between_p (SET_DEST (PATTERN (cand->insn)), | |
848 | def_insn, cand->insn)) | |
849 | return false; | |
0d732cca JL |
850 | |
851 | /* We must be able to copy between the two registers. Generate, | |
852 | recognize and verify constraints of the copy. Also fail if this | |
853 | generated more than one insn. | |
854 | ||
855 | This generates garbage since we throw away the insn when we're | |
c7ece684 JL |
856 | done, only to recreate it later if this test was successful. |
857 | ||
858 | Make sure to get the mode from the extension (cand->insn). This | |
859 | is different than in the code to emit the copy as we have not | |
860 | modified the defining insn yet. */ | |
0d732cca | 861 | start_sequence (); |
0d732cca | 862 | rtx pat = PATTERN (cand->insn); |
c7ece684 | 863 | rtx new_dst = gen_rtx_REG (GET_MODE (SET_DEST (pat)), |
e533e26c | 864 | REGNO (get_extended_src_reg (SET_SRC (pat)))); |
c7ece684 | 865 | rtx new_src = gen_rtx_REG (GET_MODE (SET_DEST (pat)), |
0d732cca JL |
866 | REGNO (SET_DEST (pat))); |
867 | emit_move_insn (new_dst, new_src); | |
868 | ||
b32d5189 | 869 | rtx_insn *insn = get_insns(); |
0d732cca JL |
870 | end_sequence (); |
871 | if (NEXT_INSN (insn)) | |
872 | return false; | |
873 | if (recog_memoized (insn) == -1) | |
874 | return false; | |
875 | extract_insn (insn); | |
daca1a96 | 876 | if (!constrain_operands (1, get_preferred_alternatives (insn, bb))) |
0d732cca | 877 | return false; |
3c92da90 JL |
878 | } |
879 | ||
880 | ||
6aae324c JJ |
881 | /* If cand->insn has been already modified, update cand->mode to a wider |
882 | mode if possible, or punt. */ | |
883 | if (state->modified[INSN_UID (cand->insn)].kind != EXT_MODIFIED_NONE) | |
884 | { | |
ef4bddc2 | 885 | machine_mode mode; |
6aae324c JJ |
886 | rtx set; |
887 | ||
888 | if (state->modified[INSN_UID (cand->insn)].kind | |
889 | != (cand->code == ZERO_EXTEND | |
890 | ? EXT_MODIFIED_ZEXT : EXT_MODIFIED_SEXT) | |
891 | || state->modified[INSN_UID (cand->insn)].mode != cand->mode | |
892 | || (set = single_set (cand->insn)) == NULL_RTX) | |
893 | return false; | |
894 | mode = GET_MODE (SET_DEST (set)); | |
895 | gcc_assert (GET_MODE_SIZE (mode) >= GET_MODE_SIZE (cand->mode)); | |
896 | cand->mode = mode; | |
897 | } | |
898 | ||
87a0ebfd ST |
899 | merge_successful = true; |
900 | ||
901 | /* Go through the defs vector and try to merge all the definitions | |
902 | in this vector. */ | |
9771b263 DN |
903 | state->modified_list.truncate (0); |
904 | FOR_EACH_VEC_ELT (state->defs_list, defs_ix, def_insn) | |
87a0ebfd | 905 | { |
b57cca0b | 906 | if (merge_def_and_ext (cand, def_insn, state)) |
9771b263 | 907 | state->modified_list.safe_push (def_insn); |
87a0ebfd ST |
908 | else |
909 | { | |
910 | merge_successful = false; | |
911 | break; | |
912 | } | |
913 | } | |
914 | ||
915 | /* Now go through the conditional copies vector and try to merge all | |
916 | the copies in this vector. */ | |
87a0ebfd ST |
917 | if (merge_successful) |
918 | { | |
9771b263 | 919 | FOR_EACH_VEC_ELT (state->copies_list, i, def_insn) |
87a0ebfd | 920 | { |
26cd9add | 921 | if (transform_ifelse (cand, def_insn)) |
9771b263 | 922 | state->modified_list.safe_push (def_insn); |
87a0ebfd ST |
923 | else |
924 | { | |
925 | merge_successful = false; | |
926 | break; | |
927 | } | |
928 | } | |
929 | } | |
930 | ||
931 | if (merge_successful) | |
932 | { | |
282bc7b4 EB |
933 | /* Commit the changes here if possible |
934 | FIXME: It's an all-or-nothing scenario. Even if only one definition | |
935 | cannot be merged, we entirely give up. In the future, we should allow | |
936 | extensions to be partially eliminated along those paths where the | |
937 | definitions could be merged. */ | |
87a0ebfd ST |
938 | if (apply_change_group ()) |
939 | { | |
940 | if (dump_file) | |
282bc7b4 | 941 | fprintf (dump_file, "All merges were successful.\n"); |
87a0ebfd | 942 | |
9771b263 | 943 | FOR_EACH_VEC_ELT (state->modified_list, i, def_insn) |
0d732cca JL |
944 | { |
945 | ext_modified *modified = &state->modified[INSN_UID (def_insn)]; | |
946 | if (modified->kind == EXT_MODIFIED_NONE) | |
947 | modified->kind = (cand->code == ZERO_EXTEND ? EXT_MODIFIED_ZEXT | |
948 | : EXT_MODIFIED_SEXT); | |
b57cca0b | 949 | |
0d732cca JL |
950 | if (copy_needed) |
951 | modified->do_not_reextend = 1; | |
952 | } | |
87a0ebfd ST |
953 | return true; |
954 | } | |
955 | else | |
956 | { | |
0acba2b4 EB |
957 | /* Changes need not be cancelled explicitly as apply_change_group |
958 | does it. Print list of definitions in the dump_file for debug | |
26cd9add | 959 | purposes. This extension cannot be deleted. */ |
87a0ebfd ST |
960 | if (dump_file) |
961 | { | |
ca10595c EB |
962 | fprintf (dump_file, |
963 | "Merge cancelled, non-mergeable definitions:\n"); | |
9771b263 | 964 | FOR_EACH_VEC_ELT (state->modified_list, i, def_insn) |
ca10595c | 965 | print_rtl_single (dump_file, def_insn); |
87a0ebfd ST |
966 | } |
967 | } | |
968 | } | |
969 | else | |
970 | { | |
971 | /* Cancel any changes that have been made so far. */ | |
972 | cancel_changes (0); | |
973 | } | |
974 | ||
87a0ebfd ST |
975 | return false; |
976 | } | |
977 | ||
089dacc5 | 978 | /* Add an extension pattern that could be eliminated. */ |
0acba2b4 EB |
979 | |
980 | static void | |
59a0c032 | 981 | add_removable_extension (const_rtx expr, rtx_insn *insn, |
9771b263 | 982 | vec<ext_cand> *insn_list, |
68c8a824 | 983 | unsigned *def_map) |
0acba2b4 | 984 | { |
282bc7b4 | 985 | enum rtx_code code; |
ef4bddc2 | 986 | machine_mode mode; |
68c8a824 | 987 | unsigned int idx; |
0acba2b4 EB |
988 | rtx src, dest; |
989 | ||
282bc7b4 | 990 | /* We are looking for SET (REG N) (ANY_EXTEND (REG N)). */ |
0acba2b4 EB |
991 | if (GET_CODE (expr) != SET) |
992 | return; | |
993 | ||
994 | src = SET_SRC (expr); | |
282bc7b4 | 995 | code = GET_CODE (src); |
0acba2b4 | 996 | dest = SET_DEST (expr); |
282bc7b4 | 997 | mode = GET_MODE (dest); |
0acba2b4 EB |
998 | |
999 | if (REG_P (dest) | |
282bc7b4 | 1000 | && (code == SIGN_EXTEND || code == ZERO_EXTEND) |
3c92da90 | 1001 | && REG_P (XEXP (src, 0))) |
0acba2b4 | 1002 | { |
282bc7b4 EB |
1003 | struct df_link *defs, *def; |
1004 | ext_cand *cand; | |
1005 | ||
1006 | /* First, make sure we can get all the reaching definitions. */ | |
089dacc5 | 1007 | defs = get_defs (insn, XEXP (src, 0), NULL); |
282bc7b4 | 1008 | if (!defs) |
0acba2b4 | 1009 | { |
282bc7b4 EB |
1010 | if (dump_file) |
1011 | { | |
1012 | fprintf (dump_file, "Cannot eliminate extension:\n"); | |
089dacc5 | 1013 | print_rtl_single (dump_file, insn); |
282bc7b4 EB |
1014 | fprintf (dump_file, " because of missing definition(s)\n"); |
1015 | } | |
1016 | return; | |
0acba2b4 | 1017 | } |
282bc7b4 EB |
1018 | |
1019 | /* Second, make sure the reaching definitions don't feed another and | |
1020 | different extension. FIXME: this obviously can be improved. */ | |
1021 | for (def = defs; def; def = def->next) | |
c3284718 | 1022 | if ((idx = def_map[INSN_UID (DF_REF_INSN (def->ref))]) |
860dadcb | 1023 | && idx != -1U |
9771b263 | 1024 | && (cand = &(*insn_list)[idx - 1]) |
ca3f371f | 1025 | && cand->code != code) |
282bc7b4 EB |
1026 | { |
1027 | if (dump_file) | |
1028 | { | |
1029 | fprintf (dump_file, "Cannot eliminate extension:\n"); | |
089dacc5 | 1030 | print_rtl_single (dump_file, insn); |
282bc7b4 EB |
1031 | fprintf (dump_file, " because of other extension\n"); |
1032 | } | |
1033 | return; | |
1034 | } | |
860dadcb JJ |
1035 | /* For vector mode extensions, ensure that all uses of the |
1036 | XEXP (src, 0) register are the same extension (both code | |
1037 | and to which mode), as unlike integral extensions lowpart | |
1038 | subreg of the sign/zero extended register are not equal | |
1039 | to the original register, so we have to change all uses or | |
1040 | none. */ | |
1041 | else if (VECTOR_MODE_P (GET_MODE (XEXP (src, 0)))) | |
1042 | { | |
1043 | if (idx == 0) | |
1044 | { | |
1045 | struct df_link *ref_chain, *ref_link; | |
1046 | ||
1047 | ref_chain = DF_REF_CHAIN (def->ref); | |
1048 | for (ref_link = ref_chain; ref_link; ref_link = ref_link->next) | |
1049 | { | |
1050 | if (ref_link->ref == NULL | |
1051 | || DF_REF_INSN_INFO (ref_link->ref) == NULL) | |
1052 | { | |
1053 | idx = -1U; | |
1054 | break; | |
1055 | } | |
1056 | rtx_insn *use_insn = DF_REF_INSN (ref_link->ref); | |
1057 | const_rtx use_set; | |
1058 | if (use_insn == insn || DEBUG_INSN_P (use_insn)) | |
1059 | continue; | |
1060 | if (!(use_set = single_set (use_insn)) | |
1061 | || !REG_P (SET_DEST (use_set)) | |
1062 | || GET_MODE (SET_DEST (use_set)) != GET_MODE (dest) | |
1063 | || GET_CODE (SET_SRC (use_set)) != code | |
1064 | || !rtx_equal_p (XEXP (SET_SRC (use_set), 0), | |
1065 | XEXP (src, 0))) | |
1066 | { | |
1067 | idx = -1U; | |
1068 | break; | |
1069 | } | |
1070 | } | |
1071 | if (idx == -1U) | |
1072 | def_map[INSN_UID (DF_REF_INSN (def->ref))] = idx; | |
1073 | } | |
1074 | if (idx == -1U) | |
1075 | { | |
1076 | if (dump_file) | |
1077 | { | |
1078 | fprintf (dump_file, "Cannot eliminate extension:\n"); | |
1079 | print_rtl_single (dump_file, insn); | |
1080 | fprintf (dump_file, | |
1081 | " because some vector uses aren't extension\n"); | |
1082 | } | |
1083 | return; | |
1084 | } | |
1085 | } | |
282bc7b4 EB |
1086 | |
1087 | /* Then add the candidate to the list and insert the reaching definitions | |
1088 | into the definition map. */ | |
f32682ca | 1089 | ext_cand e = {expr, code, mode, insn}; |
9771b263 DN |
1090 | insn_list->safe_push (e); |
1091 | idx = insn_list->length (); | |
282bc7b4 EB |
1092 | |
1093 | for (def = defs; def; def = def->next) | |
c3284718 | 1094 | def_map[INSN_UID (DF_REF_INSN (def->ref))] = idx; |
0acba2b4 EB |
1095 | } |
1096 | } | |
1097 | ||
26cd9add | 1098 | /* Traverse the instruction stream looking for extensions and return the |
0acba2b4 | 1099 | list of candidates. */ |
87a0ebfd | 1100 | |
9771b263 | 1101 | static vec<ext_cand> |
26cd9add | 1102 | find_removable_extensions (void) |
87a0ebfd | 1103 | { |
6e1aa848 | 1104 | vec<ext_cand> insn_list = vNULL; |
0acba2b4 | 1105 | basic_block bb; |
59a0c032 DM |
1106 | rtx_insn *insn; |
1107 | rtx set; | |
68c8a824 | 1108 | unsigned *def_map = XCNEWVEC (unsigned, max_insn_uid); |
87a0ebfd | 1109 | |
11cd3bed | 1110 | FOR_EACH_BB_FN (bb, cfun) |
0acba2b4 EB |
1111 | FOR_BB_INSNS (bb, insn) |
1112 | { | |
1113 | if (!NONDEBUG_INSN_P (insn)) | |
1114 | continue; | |
87a0ebfd | 1115 | |
089dacc5 JJ |
1116 | set = single_set (insn); |
1117 | if (set == NULL_RTX) | |
1118 | continue; | |
1119 | add_removable_extension (set, insn, &insn_list, def_map); | |
0acba2b4 EB |
1120 | } |
1121 | ||
089dacc5 | 1122 | XDELETEVEC (def_map); |
282bc7b4 | 1123 | |
089dacc5 | 1124 | return insn_list; |
87a0ebfd ST |
1125 | } |
1126 | ||
1127 | /* This is the main function that checks the insn stream for redundant | |
26cd9add | 1128 | extensions and tries to remove them if possible. */ |
87a0ebfd | 1129 | |
282bc7b4 | 1130 | static void |
26cd9add | 1131 | find_and_remove_re (void) |
87a0ebfd | 1132 | { |
282bc7b4 | 1133 | ext_cand *curr_cand; |
59a0c032 | 1134 | rtx_insn *curr_insn = NULL; |
282bc7b4 | 1135 | int num_re_opportunities = 0, num_realized = 0, i; |
9771b263 | 1136 | vec<ext_cand> reinsn_list; |
59a0c032 DM |
1137 | auto_vec<rtx_insn *> reinsn_del_list; |
1138 | auto_vec<rtx_insn *> reinsn_copy_list; | |
b57cca0b | 1139 | ext_state state; |
87a0ebfd ST |
1140 | |
1141 | /* Construct DU chain to get all reaching definitions of each | |
26cd9add | 1142 | extension instruction. */ |
7b19209f | 1143 | df_set_flags (DF_RD_PRUNE_DEAD_DEFS); |
87a0ebfd ST |
1144 | df_chain_add_problem (DF_UD_CHAIN + DF_DU_CHAIN); |
1145 | df_analyze (); | |
b57cca0b | 1146 | df_set_flags (DF_DEFER_INSN_RESCAN); |
87a0ebfd ST |
1147 | |
1148 | max_insn_uid = get_max_uid (); | |
26cd9add | 1149 | reinsn_list = find_removable_extensions (); |
9771b263 DN |
1150 | state.defs_list.create (0); |
1151 | state.copies_list.create (0); | |
1152 | state.modified_list.create (0); | |
1153 | state.work_list.create (0); | |
1154 | if (reinsn_list.is_empty ()) | |
b57cca0b JJ |
1155 | state.modified = NULL; |
1156 | else | |
1157 | state.modified = XCNEWVEC (struct ext_modified, max_insn_uid); | |
87a0ebfd | 1158 | |
9771b263 | 1159 | FOR_EACH_VEC_ELT (reinsn_list, i, curr_cand) |
87a0ebfd | 1160 | { |
26cd9add | 1161 | num_re_opportunities++; |
87a0ebfd | 1162 | |
282bc7b4 | 1163 | /* Try to combine the extension with the definition. */ |
87a0ebfd ST |
1164 | if (dump_file) |
1165 | { | |
282bc7b4 EB |
1166 | fprintf (dump_file, "Trying to eliminate extension:\n"); |
1167 | print_rtl_single (dump_file, curr_cand->insn); | |
87a0ebfd ST |
1168 | } |
1169 | ||
089dacc5 | 1170 | if (combine_reaching_defs (curr_cand, curr_cand->expr, &state)) |
87a0ebfd ST |
1171 | { |
1172 | if (dump_file) | |
282bc7b4 | 1173 | fprintf (dump_file, "Eliminated the extension.\n"); |
87a0ebfd | 1174 | num_realized++; |
059742a4 JL |
1175 | /* If the RHS of the current candidate is not (extend (reg)), then |
1176 | we do not allow the optimization of extensions where | |
1177 | the source and destination registers do not match. Thus | |
1178 | checking REG_P here is correct. */ | |
1179 | if (REG_P (XEXP (SET_SRC (PATTERN (curr_cand->insn)), 0)) | |
1180 | && (REGNO (SET_DEST (PATTERN (curr_cand->insn))) | |
1181 | != REGNO (XEXP (SET_SRC (PATTERN (curr_cand->insn)), 0)))) | |
3c92da90 JL |
1182 | { |
1183 | reinsn_copy_list.safe_push (curr_cand->insn); | |
1184 | reinsn_copy_list.safe_push (state.defs_list[0]); | |
1185 | } | |
1186 | reinsn_del_list.safe_push (curr_cand->insn); | |
b57cca0b | 1187 | state.modified[INSN_UID (curr_cand->insn)].deleted = 1; |
87a0ebfd ST |
1188 | } |
1189 | } | |
1190 | ||
3c92da90 JL |
1191 | /* The copy list contains pairs of insns which describe copies we |
1192 | need to insert into the INSN stream. | |
1193 | ||
1194 | The first insn in each pair is the extension insn, from which | |
1195 | we derive the source and destination of the copy. | |
1196 | ||
1197 | The second insn in each pair is the memory reference where the | |
1198 | extension will ultimately happen. We emit the new copy | |
1199 | immediately after this insn. | |
1200 | ||
1201 | It may first appear that the arguments for the copy are reversed. | |
1202 | Remember that the memory reference will be changed to refer to the | |
1203 | destination of the extention. So we're actually emitting a copy | |
1204 | from the new destination to the old destination. */ | |
1205 | for (unsigned int i = 0; i < reinsn_copy_list.length (); i += 2) | |
1206 | { | |
59a0c032 DM |
1207 | rtx_insn *curr_insn = reinsn_copy_list[i]; |
1208 | rtx_insn *def_insn = reinsn_copy_list[i + 1]; | |
a6a2d67b JL |
1209 | |
1210 | /* Use the mode of the destination of the defining insn | |
1211 | for the mode of the copy. This is necessary if the | |
1212 | defining insn was used to eliminate a second extension | |
1213 | that was wider than the first. */ | |
1214 | rtx sub_rtx = *get_sub_rtx (def_insn); | |
3c92da90 | 1215 | rtx pat = PATTERN (curr_insn); |
a6a2d67b | 1216 | rtx new_dst = gen_rtx_REG (GET_MODE (SET_DEST (sub_rtx)), |
3c92da90 | 1217 | REGNO (XEXP (SET_SRC (pat), 0))); |
a6a2d67b JL |
1218 | rtx new_src = gen_rtx_REG (GET_MODE (SET_DEST (sub_rtx)), |
1219 | REGNO (SET_DEST (pat))); | |
f7df4a84 | 1220 | rtx set = gen_rtx_SET (new_dst, new_src); |
a6a2d67b | 1221 | emit_insn_after (set, def_insn); |
3c92da90 JL |
1222 | } |
1223 | ||
26cd9add | 1224 | /* Delete all useless extensions here in one sweep. */ |
9771b263 | 1225 | FOR_EACH_VEC_ELT (reinsn_del_list, i, curr_insn) |
0acba2b4 | 1226 | delete_insn (curr_insn); |
87a0ebfd | 1227 | |
9771b263 | 1228 | reinsn_list.release (); |
9771b263 DN |
1229 | state.defs_list.release (); |
1230 | state.copies_list.release (); | |
1231 | state.modified_list.release (); | |
1232 | state.work_list.release (); | |
b57cca0b | 1233 | XDELETEVEC (state.modified); |
87a0ebfd | 1234 | |
26cd9add | 1235 | if (dump_file && num_re_opportunities > 0) |
282bc7b4 EB |
1236 | fprintf (dump_file, "Elimination opportunities = %d realized = %d\n", |
1237 | num_re_opportunities, num_realized); | |
87a0ebfd ST |
1238 | } |
1239 | ||
26cd9add | 1240 | /* Find and remove redundant extensions. */ |
87a0ebfd ST |
1241 | |
1242 | static unsigned int | |
26cd9add | 1243 | rest_of_handle_ree (void) |
87a0ebfd | 1244 | { |
26cd9add EI |
1245 | timevar_push (TV_REE); |
1246 | find_and_remove_re (); | |
1247 | timevar_pop (TV_REE); | |
87a0ebfd ST |
1248 | return 0; |
1249 | } | |
1250 | ||
27a4cd48 DM |
1251 | namespace { |
1252 | ||
1253 | const pass_data pass_data_ree = | |
87a0ebfd | 1254 | { |
27a4cd48 DM |
1255 | RTL_PASS, /* type */ |
1256 | "ree", /* name */ | |
1257 | OPTGROUP_NONE, /* optinfo_flags */ | |
27a4cd48 DM |
1258 | TV_REE, /* tv_id */ |
1259 | 0, /* properties_required */ | |
1260 | 0, /* properties_provided */ | |
1261 | 0, /* properties_destroyed */ | |
1262 | 0, /* todo_flags_start */ | |
3bea341f | 1263 | TODO_df_finish, /* todo_flags_finish */ |
87a0ebfd | 1264 | }; |
27a4cd48 DM |
1265 | |
1266 | class pass_ree : public rtl_opt_pass | |
1267 | { | |
1268 | public: | |
c3284718 RS |
1269 | pass_ree (gcc::context *ctxt) |
1270 | : rtl_opt_pass (pass_data_ree, ctxt) | |
27a4cd48 DM |
1271 | {} |
1272 | ||
1273 | /* opt_pass methods: */ | |
1a3d085c | 1274 | virtual bool gate (function *) { return (optimize > 0 && flag_ree); } |
be55bfe6 | 1275 | virtual unsigned int execute (function *) { return rest_of_handle_ree (); } |
27a4cd48 DM |
1276 | |
1277 | }; // class pass_ree | |
1278 | ||
1279 | } // anon namespace | |
1280 | ||
1281 | rtl_opt_pass * | |
1282 | make_pass_ree (gcc::context *ctxt) | |
1283 | { | |
1284 | return new pass_ree (ctxt); | |
1285 | } |