]>
Commit | Line | Data |
---|---|---|
48227150 | 1 | /* Register to Stack convert for GNU compiler. |
23a5b65a | 2 | Copyright (C) 1992-2014 Free Software Foundation, Inc. |
48227150 | 3 | |
1322177d | 4 | This file is part of GCC. |
48227150 | 5 | |
1322177d LB |
6 | GCC is free software; you can redistribute it and/or modify it |
7 | under the terms of the GNU General Public License as published by | |
9dcd6f09 | 8 | the Free Software Foundation; either version 3, or (at your option) |
a05924f9 | 9 | any later version. |
48227150 | 10 | |
1322177d LB |
11 | GCC is distributed in the hope that it will be useful, but WITHOUT |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
14 | License for more details. | |
48227150 | 15 | |
a05924f9 | 16 | You should have received a copy of the GNU General Public License |
9dcd6f09 NC |
17 | along with GCC; see the file COPYING3. If not see |
18 | <http://www.gnu.org/licenses/>. */ | |
48227150 JVA |
19 | |
20 | /* This pass converts stack-like registers from the "flat register | |
21 | file" model that gcc uses, to a stack convention that the 387 uses. | |
22 | ||
23 | * The form of the input: | |
24 | ||
25 | On input, the function consists of insn that have had their | |
26 | registers fully allocated to a set of "virtual" registers. Note that | |
27 | the word "virtual" is used differently here than elsewhere in gcc: for | |
28 | each virtual stack reg, there is a hard reg, but the mapping between | |
29 | them is not known until this pass is run. On output, hard register | |
30 | numbers have been substituted, and various pop and exchange insns have | |
31 | been emitted. The hard register numbers and the virtual register | |
32 | numbers completely overlap - before this pass, all stack register | |
114cbee6 | 33 | numbers are virtual, and afterward they are all hard. |
48227150 JVA |
34 | |
35 | The virtual registers can be manipulated normally by gcc, and their | |
36 | semantics are the same as for normal registers. After the hard | |
37 | register numbers are substituted, the semantics of an insn containing | |
38 | stack-like regs are not the same as for an insn with normal regs: for | |
39 | instance, it is not safe to delete an insn that appears to be a no-op | |
40 | move. In general, no insn containing hard regs should be changed | |
41 | after this pass is done. | |
42 | ||
43 | * The form of the output: | |
44 | ||
45 | After this pass, hard register numbers represent the distance from | |
46 | the current top of stack to the desired register. A reference to | |
47 | FIRST_STACK_REG references the top of stack, FIRST_STACK_REG + 1, | |
48 | represents the register just below that, and so forth. Also, REG_DEAD | |
49 | notes indicate whether or not a stack register should be popped. | |
50 | ||
51 | A "swap" insn looks like a parallel of two patterns, where each | |
52 | pattern is a SET: one sets A to B, the other B to A. | |
53 | ||
54 | A "push" or "load" insn is a SET whose SET_DEST is FIRST_STACK_REG | |
55 | and whose SET_DEST is REG or MEM. Any other SET_DEST, such as PLUS, | |
56 | will replace the existing stack top, not push a new value. | |
57 | ||
58 | A store insn is a SET whose SET_DEST is FIRST_STACK_REG, and whose | |
59 | SET_SRC is REG or MEM. | |
60 | ||
3f5cfed6 | 61 | The case where the SET_SRC and SET_DEST are both FIRST_STACK_REG |
48227150 JVA |
62 | appears ambiguous. As a special case, the presence of a REG_DEAD note |
63 | for FIRST_STACK_REG differentiates between a load insn and a pop. | |
64 | ||
65 | If a REG_DEAD is present, the insn represents a "pop" that discards | |
66 | the top of the register stack. If there is no REG_DEAD note, then the | |
67 | insn represents a "dup" or a push of the current top of stack onto the | |
68 | stack. | |
69 | ||
70 | * Methodology: | |
71 | ||
72 | Existing REG_DEAD and REG_UNUSED notes for stack registers are | |
73 | deleted and recreated from scratch. REG_DEAD is never created for a | |
74 | SET_DEST, only REG_UNUSED. | |
75 | ||
114cbee6 | 76 | * asm_operands: |
48227150 | 77 | |
114cbee6 RS |
78 | There are several rules on the usage of stack-like regs in |
79 | asm_operands insns. These rules apply only to the operands that are | |
80 | stack-like regs: | |
81 | ||
82 | 1. Given a set of input regs that die in an asm_operands, it is | |
83 | necessary to know which are implicitly popped by the asm, and | |
84 | which must be explicitly popped by gcc. | |
85 | ||
86 | An input reg that is implicitly popped by the asm must be | |
87 | explicitly clobbered, unless it is constrained to match an | |
88 | output operand. | |
89 | ||
90 | 2. For any input reg that is implicitly popped by an asm, it is | |
91 | necessary to know how to adjust the stack to compensate for the pop. | |
92 | If any non-popped input is closer to the top of the reg-stack than | |
93 | the implicitly popped reg, it would not be possible to know what the | |
94 | stack looked like - it's not clear how the rest of the stack "slides | |
95 | up". | |
96 | ||
97 | All implicitly popped input regs must be closer to the top of | |
98 | the reg-stack than any input that is not implicitly popped. | |
99 | ||
100 | 3. It is possible that if an input dies in an insn, reload might | |
101 | use the input reg for an output reload. Consider this example: | |
102 | ||
103 | asm ("foo" : "=t" (a) : "f" (b)); | |
104 | ||
105 | This asm says that input B is not popped by the asm, and that | |
454ff5cb | 106 | the asm pushes a result onto the reg-stack, i.e., the stack is one |
114cbee6 RS |
107 | deeper after the asm than it was before. But, it is possible that |
108 | reload will think that it can use the same reg for both the input and | |
109 | the output, if input B dies in this insn. | |
110 | ||
111 | If any input operand uses the "f" constraint, all output reg | |
112 | constraints must use the "&" earlyclobber. | |
113 | ||
114 | The asm above would be written as | |
115 | ||
116 | asm ("foo" : "=&t" (a) : "f" (b)); | |
117 | ||
118 | 4. Some operands need to be in particular places on the stack. All | |
119 | output operands fall in this category - there is no other way to | |
120 | know which regs the outputs appear in unless the user indicates | |
121 | this in the constraints. | |
122 | ||
123 | Output operands must specifically indicate which reg an output | |
124 | appears in after an asm. "=f" is not allowed: the operand | |
125 | constraints must select a class with a single reg. | |
126 | ||
127 | 5. Output operands may not be "inserted" between existing stack regs. | |
128 | Since no 387 opcode uses a read/write operand, all output operands | |
129 | are dead before the asm_operands, and are pushed by the asm_operands. | |
130 | It makes no sense to push anywhere but the top of the reg-stack. | |
131 | ||
132 | Output operands must start at the top of the reg-stack: output | |
133 | operands may not "skip" a reg. | |
134 | ||
135 | 6. Some asm statements may need extra stack space for internal | |
136 | calculations. This can be guaranteed by clobbering stack registers | |
137 | unrelated to the inputs and outputs. | |
138 | ||
139 | Here are a couple of reasonable asms to want to write. This asm | |
140 | takes one input, which is internally popped, and produces two outputs. | |
141 | ||
142 | asm ("fsincos" : "=t" (cos), "=u" (sin) : "0" (inp)); | |
143 | ||
144 | This asm takes two inputs, which are popped by the fyl2xp1 opcode, | |
145 | and replaces them with one output. The user must code the "st(1)" | |
146 | clobber for reg-stack.c to know that fyl2xp1 pops both inputs. | |
147 | ||
148 | asm ("fyl2xp1" : "=t" (result) : "0" (x), "u" (y) : "st(1)"); | |
149 | ||
a05924f9 | 150 | */ |
48227150 | 151 | \f |
48227150 | 152 | #include "config.h" |
670ee920 | 153 | #include "system.h" |
4977bab6 ZW |
154 | #include "coretypes.h" |
155 | #include "tm.h" | |
48227150 | 156 | #include "tree.h" |
d8a2d370 | 157 | #include "varasm.h" |
0cbd9993 | 158 | #include "rtl-error.h" |
6baf1cc8 | 159 | #include "tm_p.h" |
49ad7cfa | 160 | #include "function.h" |
114cbee6 | 161 | #include "insn-config.h" |
48227150 JVA |
162 | #include "regs.h" |
163 | #include "hard-reg-set.h" | |
164 | #include "flags.h" | |
e075ae69 | 165 | #include "recog.h" |
a05924f9 | 166 | #include "basic-block.h" |
2840aebf | 167 | #include "reload.h" |
e2500fed | 168 | #include "ggc.h" |
ef330312 | 169 | #include "tree-pass.h" |
1d636cc6 | 170 | #include "target.h" |
6fb5fa3c | 171 | #include "df.h" |
5936d944 | 172 | #include "emit-rtl.h" /* FIXME: Can go away once crtl is moved to rtl.h. */ |
e4881f23 | 173 | |
5b94780f KH |
174 | #ifdef STACK_REGS |
175 | ||
e2500fed GK |
176 | /* We use this array to cache info about insns, because otherwise we |
177 | spend too much time in stack_regs_mentioned_p. | |
178 | ||
179 | Indexed by insn UIDs. A value of zero is uninitialized, one indicates | |
180 | the insn uses stack registers, two indicates the insn does not use | |
181 | stack registers. */ | |
9771b263 | 182 | static vec<char> stack_regs_mentioned_data; |
48227150 | 183 | |
48227150 JVA |
184 | #define REG_STACK_SIZE (LAST_STACK_REG - FIRST_STACK_REG + 1) |
185 | ||
23249ac4 DB |
186 | int regstack_completed = 0; |
187 | ||
48227150 JVA |
188 | /* This is the basic stack record. TOP is an index into REG[] such |
189 | that REG[TOP] is the top of stack. If TOP is -1 the stack is empty. | |
190 | ||
eca31501 JVA |
191 | If TOP is -2, REG[] is not yet initialized. Stack initialization |
192 | consists of placing each live reg in array `reg' and setting `top' | |
193 | appropriately. | |
194 | ||
195 | REG_SET indicates which registers are live. */ | |
48227150 JVA |
196 | |
197 | typedef struct stack_def | |
198 | { | |
199 | int top; /* index to top stack element */ | |
200 | HARD_REG_SET reg_set; /* set of live registers */ | |
b00b2cc2 | 201 | unsigned char reg[REG_STACK_SIZE];/* register - stack mapping */ |
0823efed | 202 | } *stack_ptr; |
48227150 | 203 | |
a6a2274a | 204 | /* This is used to carry information about basic blocks. It is |
a05924f9 | 205 | attached to the AUX field of the standard CFG block. */ |
48227150 | 206 | |
a05924f9 JH |
207 | typedef struct block_info_def |
208 | { | |
209 | struct stack_def stack_in; /* Input stack configuration. */ | |
0ecf09f9 | 210 | struct stack_def stack_out; /* Output stack configuration. */ |
a05924f9 JH |
211 | HARD_REG_SET out_reg_set; /* Stack regs live on output. */ |
212 | int done; /* True if block already converted. */ | |
579e4a82 | 213 | int predecessors; /* Number of predecessors that need |
0ecf09f9 | 214 | to be visited. */ |
a05924f9 | 215 | } *block_info; |
48227150 | 216 | |
a05924f9 | 217 | #define BLOCK_INFO(B) ((block_info) (B)->aux) |
48227150 | 218 | |
a05924f9 JH |
219 | /* Passed to change_stack to indicate where to emit insns. */ |
220 | enum emit_where | |
221 | { | |
222 | EMIT_AFTER, | |
223 | EMIT_BEFORE | |
224 | }; | |
48227150 | 225 | |
a05924f9 JH |
226 | /* The block we're currently working on. */ |
227 | static basic_block current_block; | |
228 | ||
385e0e08 | 229 | /* In the current_block, whether we're processing the first register |
2e48874f | 230 | stack or call instruction, i.e. the regstack is currently the |
385e0e08 RS |
231 | same as BLOCK_INFO(current_block)->stack_in. */ |
232 | static bool starting_stack_p; | |
233 | ||
3eae4643 | 234 | /* This is the register file for all register after conversion. */ |
99a59310 RK |
235 | static rtx |
236 | FP_mode_reg[LAST_STACK_REG+1-FIRST_STACK_REG][(int) MAX_MACHINE_MODE]; | |
237 | ||
238 | #define FP_MODE_REG(regno,mode) \ | |
f4f4d0f8 | 239 | (FP_mode_reg[(regno)-FIRST_STACK_REG][(int) (mode)]) |
48227150 | 240 | |
a05924f9 | 241 | /* Used to initialize uninitialized registers. */ |
d2032ad8 | 242 | static rtx not_a_num; |
48227150 | 243 | |
48227150 JVA |
244 | /* Forward declarations */ |
245 | ||
9678086d | 246 | static int stack_regs_mentioned_p (const_rtx pat); |
0823efed | 247 | static void pop_stack (stack_ptr, int); |
0c20a65f AJ |
248 | static rtx *get_true_reg (rtx *); |
249 | ||
250 | static int check_asm_stack_operands (rtx); | |
1c384bf1 | 251 | static void get_asm_operands_in_out (rtx, int *, int *); |
0c20a65f AJ |
252 | static rtx stack_result (tree); |
253 | static void replace_reg (rtx *, int); | |
254 | static void remove_regno_note (rtx, enum reg_note, unsigned int); | |
0823efed DN |
255 | static int get_hard_regnum (stack_ptr, rtx); |
256 | static rtx emit_pop_insn (rtx, stack_ptr, rtx, enum emit_where); | |
c3284718 | 257 | static void swap_to_top (rtx, stack_ptr, rtx, rtx); |
0823efed DN |
258 | static bool move_for_stack_reg (rtx, stack_ptr, rtx); |
259 | static bool move_nan_for_stack_reg (rtx, stack_ptr, rtx); | |
0c20a65f AJ |
260 | static int swap_rtx_condition_1 (rtx); |
261 | static int swap_rtx_condition (rtx); | |
0823efed DN |
262 | static void compare_for_stack_reg (rtx, stack_ptr, rtx); |
263 | static bool subst_stack_regs_pat (rtx, stack_ptr, rtx); | |
264 | static void subst_asm_stack_regs (rtx, stack_ptr); | |
265 | static bool subst_stack_regs (rtx, stack_ptr); | |
266 | static void change_stack (rtx, stack_ptr, stack_ptr, enum emit_where); | |
267 | static void print_stack (FILE *, stack_ptr); | |
0c20a65f | 268 | static rtx next_flags_user (rtx); |
21b2cd73 | 269 | \f |
40f03658 | 270 | /* Return nonzero if any stack register is mentioned somewhere within PAT. */ |
21b2cd73 JH |
271 | |
272 | static int | |
9678086d | 273 | stack_regs_mentioned_p (const_rtx pat) |
21b2cd73 | 274 | { |
b3694847 SS |
275 | const char *fmt; |
276 | int i; | |
e075ae69 RH |
277 | |
278 | if (STACK_REG_P (pat)) | |
279 | return 1; | |
280 | ||
281 | fmt = GET_RTX_FORMAT (GET_CODE (pat)); | |
282 | for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0; i--) | |
21b2cd73 | 283 | { |
e075ae69 RH |
284 | if (fmt[i] == 'E') |
285 | { | |
b3694847 | 286 | int j; |
e075ae69 RH |
287 | |
288 | for (j = XVECLEN (pat, i) - 1; j >= 0; j--) | |
289 | if (stack_regs_mentioned_p (XVECEXP (pat, i, j))) | |
290 | return 1; | |
291 | } | |
292 | else if (fmt[i] == 'e' && stack_regs_mentioned_p (XEXP (pat, i))) | |
293 | return 1; | |
21b2cd73 | 294 | } |
e075ae69 | 295 | |
21b2cd73 JH |
296 | return 0; |
297 | } | |
298 | ||
e075ae69 | 299 | /* Return nonzero if INSN mentions stacked registers, else return zero. */ |
21b2cd73 JH |
300 | |
301 | int | |
9678086d | 302 | stack_regs_mentioned (const_rtx insn) |
21b2cd73 | 303 | { |
e075ae69 RH |
304 | unsigned int uid, max; |
305 | int test; | |
306 | ||
9771b263 | 307 | if (! INSN_P (insn) || !stack_regs_mentioned_data.exists ()) |
21b2cd73 | 308 | return 0; |
e075ae69 | 309 | |
21b2cd73 | 310 | uid = INSN_UID (insn); |
9771b263 | 311 | max = stack_regs_mentioned_data.length (); |
e075ae69 RH |
312 | if (uid >= max) |
313 | { | |
314 | /* Allocate some extra size to avoid too many reallocs, but | |
315 | do not grow too quickly. */ | |
e4881f23 | 316 | max = uid + uid / 20 + 1; |
9771b263 | 317 | stack_regs_mentioned_data.safe_grow_cleared (max); |
e075ae69 RH |
318 | } |
319 | ||
9771b263 | 320 | test = stack_regs_mentioned_data[uid]; |
e075ae69 RH |
321 | if (test == 0) |
322 | { | |
323 | /* This insn has yet to be examined. Do so now. */ | |
324 | test = stack_regs_mentioned_p (PATTERN (insn)) ? 1 : 2; | |
9771b263 | 325 | stack_regs_mentioned_data[uid] = test; |
e075ae69 RH |
326 | } |
327 | ||
328 | return test == 1; | |
21b2cd73 | 329 | } |
e075ae69 RH |
330 | \f |
331 | static rtx ix86_flags_rtx; | |
21b2cd73 | 332 | |
e075ae69 | 333 | static rtx |
0c20a65f | 334 | next_flags_user (rtx insn) |
e075ae69 | 335 | { |
a6a2274a | 336 | /* Search forward looking for the first use of this value. |
e075ae69 | 337 | Stop at block boundaries. */ |
e075ae69 | 338 | |
a813c111 | 339 | while (insn != BB_END (current_block)) |
e075ae69 RH |
340 | { |
341 | insn = NEXT_INSN (insn); | |
e075ae69 | 342 | |
2c3c49de | 343 | if (INSN_P (insn) && reg_mentioned_p (ix86_flags_rtx, PATTERN (insn))) |
a6a2274a | 344 | return insn; |
e075ae69 | 345 | |
4b4bf941 | 346 | if (CALL_P (insn)) |
e075ae69 RH |
347 | return NULL_RTX; |
348 | } | |
0eac0e81 | 349 | return NULL_RTX; |
e075ae69 | 350 | } |
48227150 | 351 | \f |
385e0e08 | 352 | /* Reorganize the stack into ascending numbers, before this insn. */ |
99a59310 RK |
353 | |
354 | static void | |
0823efed | 355 | straighten_stack (rtx insn, stack_ptr regstack) |
99a59310 RK |
356 | { |
357 | struct stack_def temp_stack; | |
358 | int top; | |
359 | ||
8feb7351 JL |
360 | /* If there is only a single register on the stack, then the stack is |
361 | already in increasing order and no reorganization is needed. | |
362 | ||
363 | Similarly if the stack is empty. */ | |
364 | if (regstack->top <= 0) | |
365 | return; | |
366 | ||
d25cf633 | 367 | COPY_HARD_REG_SET (temp_stack.reg_set, regstack->reg_set); |
99a59310 RK |
368 | |
369 | for (top = temp_stack.top = regstack->top; top >= 0; top--) | |
e075ae69 | 370 | temp_stack.reg[top] = FIRST_STACK_REG + temp_stack.top - top; |
a6a2274a | 371 | |
385e0e08 | 372 | change_stack (insn, regstack, &temp_stack, EMIT_BEFORE); |
99a59310 | 373 | } |
7aa74e4c | 374 | |
3eae4643 | 375 | /* Pop a register from the stack. */ |
7aa74e4c SC |
376 | |
377 | static void | |
0823efed | 378 | pop_stack (stack_ptr regstack, int regno) |
7aa74e4c SC |
379 | { |
380 | int top = regstack->top; | |
381 | ||
382 | CLEAR_HARD_REG_BIT (regstack->reg_set, regno); | |
383 | regstack->top--; | |
3eae4643 | 384 | /* If regno was not at the top of stack then adjust stack. */ |
7aa74e4c SC |
385 | if (regstack->reg [top] != regno) |
386 | { | |
387 | int i; | |
388 | for (i = regstack->top; i >= 0; i--) | |
389 | if (regstack->reg [i] == regno) | |
390 | { | |
391 | int j; | |
392 | for (j = i; j < top; j++) | |
393 | regstack->reg [j] = regstack->reg [j + 1]; | |
394 | break; | |
395 | } | |
396 | } | |
397 | } | |
48227150 JVA |
398 | \f |
399 | /* Return a pointer to the REG expression within PAT. If PAT is not a | |
400 | REG, possible enclosed by a conversion rtx, return the inner part of | |
0f41302f | 401 | PAT that stopped the search. */ |
48227150 JVA |
402 | |
403 | static rtx * | |
0c20a65f | 404 | get_true_reg (rtx *pat) |
48227150 | 405 | { |
99a59310 | 406 | for (;;) |
e075ae69 | 407 | switch (GET_CODE (*pat)) |
99a59310 | 408 | { |
e075ae69 | 409 | case SUBREG: |
8d9afc4e | 410 | /* Eliminate FP subregister accesses in favor of the |
e075ae69 RH |
411 | actual FP register in use. */ |
412 | { | |
413 | rtx subreg; | |
66aaf16f | 414 | if (STACK_REG_P (subreg = SUBREG_REG (*pat))) |
99a59310 | 415 | { |
ddef6bc7 JJ |
416 | int regno_off = subreg_regno_offset (REGNO (subreg), |
417 | GET_MODE (subreg), | |
418 | SUBREG_BYTE (*pat), | |
419 | GET_MODE (*pat)); | |
420 | *pat = FP_MODE_REG (REGNO (subreg) + regno_off, | |
99a59310 | 421 | GET_MODE (subreg)); |
99a59310 RK |
422 | return pat; |
423 | } | |
e075ae69 RH |
424 | } |
425 | case FLOAT: | |
426 | case FIX: | |
427 | case FLOAT_EXTEND: | |
428 | pat = & XEXP (*pat, 0); | |
0c5faf29 RS |
429 | break; |
430 | ||
01302104 | 431 | case UNSPEC: |
09ad58e6 UB |
432 | if (XINT (*pat, 1) == UNSPEC_TRUNC_NOOP |
433 | || XINT (*pat, 1) == UNSPEC_LDA) | |
56d8eb62 UB |
434 | pat = & XVECEXP (*pat, 0, 0); |
435 | return pat; | |
01302104 | 436 | |
0c5faf29 RS |
437 | case FLOAT_TRUNCATE: |
438 | if (!flag_unsafe_math_optimizations) | |
439 | return pat; | |
440 | pat = & XEXP (*pat, 0); | |
441 | break; | |
c8e2516c SB |
442 | |
443 | default: | |
444 | return pat; | |
99a59310 | 445 | } |
48227150 | 446 | } |
48227150 | 447 | \f |
d6fc0492 RH |
448 | /* Set if we find any malformed asms in a block. */ |
449 | static bool any_malformed_asm; | |
450 | ||
a05924f9 | 451 | /* There are many rules that an asm statement for stack-like regs must |
114cbee6 | 452 | follow. Those rules are explained at the top of this file: the rule |
0f41302f | 453 | numbers below refer to that explanation. */ |
114cbee6 | 454 | |
a05924f9 | 455 | static int |
0c20a65f | 456 | check_asm_stack_operands (rtx insn) |
114cbee6 RS |
457 | { |
458 | int i; | |
114cbee6 RS |
459 | int n_clobbers; |
460 | int malformed_asm = 0; | |
461 | rtx body = PATTERN (insn); | |
462 | ||
a05924f9 JH |
463 | char reg_used_as_output[FIRST_PSEUDO_REGISTER]; |
464 | char implicitly_dies[FIRST_PSEUDO_REGISTER]; | |
f62a15e3 | 465 | int alt; |
114cbee6 | 466 | |
a544cfd2 | 467 | rtx *clobber_reg = 0; |
f62a15e3 | 468 | int n_inputs, n_outputs; |
114cbee6 | 469 | |
0e7d0eb9 | 470 | /* Find out what the constraints require. If no constraint |
854dfdff | 471 | alternative matches, this asm is malformed. */ |
f62a15e3 BS |
472 | extract_insn (insn); |
473 | constrain_operands (1); | |
474 | alt = which_alternative; | |
475 | ||
476 | preprocess_constraints (); | |
477 | ||
1c384bf1 | 478 | get_asm_operands_in_out (body, &n_outputs, &n_inputs); |
f62a15e3 BS |
479 | |
480 | if (alt < 0) | |
481 | { | |
482 | malformed_asm = 1; | |
483 | /* Avoid further trouble with this insn. */ | |
484 | PATTERN (insn) = gen_rtx_USE (VOIDmode, const0_rtx); | |
a05924f9 | 485 | return 0; |
f62a15e3 | 486 | } |
114cbee6 | 487 | |
0f41302f | 488 | /* Strip SUBREGs here to make the following code simpler. */ |
1ccbefce RH |
489 | for (i = 0; i < recog_data.n_operands; i++) |
490 | if (GET_CODE (recog_data.operand[i]) == SUBREG | |
f8cfc6aa | 491 | && REG_P (SUBREG_REG (recog_data.operand[i]))) |
1ccbefce | 492 | recog_data.operand[i] = SUBREG_REG (recog_data.operand[i]); |
114cbee6 RS |
493 | |
494 | /* Set up CLOBBER_REG. */ | |
495 | ||
496 | n_clobbers = 0; | |
114cbee6 RS |
497 | |
498 | if (GET_CODE (body) == PARALLEL) | |
3f5cfed6 | 499 | { |
1634b18f | 500 | clobber_reg = XALLOCAVEC (rtx, XVECLEN (body, 0)); |
114cbee6 | 501 | |
3f5cfed6 JVA |
502 | for (i = 0; i < XVECLEN (body, 0); i++) |
503 | if (GET_CODE (XVECEXP (body, 0, i)) == CLOBBER) | |
504 | { | |
505 | rtx clobber = XVECEXP (body, 0, i); | |
506 | rtx reg = XEXP (clobber, 0); | |
114cbee6 | 507 | |
f8cfc6aa | 508 | if (GET_CODE (reg) == SUBREG && REG_P (SUBREG_REG (reg))) |
3f5cfed6 JVA |
509 | reg = SUBREG_REG (reg); |
510 | ||
511 | if (STACK_REG_P (reg)) | |
512 | { | |
513 | clobber_reg[n_clobbers] = reg; | |
514 | n_clobbers++; | |
515 | } | |
516 | } | |
517 | } | |
114cbee6 RS |
518 | |
519 | /* Enforce rule #4: Output operands must specifically indicate which | |
520 | reg an output appears in after an asm. "=f" is not allowed: the | |
521 | operand constraints must select a class with a single reg. | |
522 | ||
523 | Also enforce rule #5: Output operands must start at the top of | |
0f41302f | 524 | the reg-stack: output operands may not "skip" a reg. */ |
114cbee6 | 525 | |
a05924f9 | 526 | memset (reg_used_as_output, 0, sizeof (reg_used_as_output)); |
114cbee6 | 527 | for (i = 0; i < n_outputs; i++) |
1ccbefce | 528 | if (STACK_REG_P (recog_data.operand[i])) |
9c318306 | 529 | { |
e3a64162 | 530 | if (reg_class_size[(int) recog_op_alt[i][alt].cl] != 1) |
9c318306 | 531 | { |
1f978f5f | 532 | error_for_asm (insn, "output constraint %d must specify a single register", i); |
9c318306 MH |
533 | malformed_asm = 1; |
534 | } | |
a6a2274a | 535 | else |
d40cd80a JJ |
536 | { |
537 | int j; | |
538 | ||
539 | for (j = 0; j < n_clobbers; j++) | |
540 | if (REGNO (recog_data.operand[i]) == REGNO (clobber_reg[j])) | |
541 | { | |
1f978f5f | 542 | error_for_asm (insn, "output constraint %d cannot be specified together with \"%s\" clobber", |
d40cd80a JJ |
543 | i, reg_names [REGNO (clobber_reg[j])]); |
544 | malformed_asm = 1; | |
545 | break; | |
546 | } | |
547 | if (j == n_clobbers) | |
548 | reg_used_as_output[REGNO (recog_data.operand[i])] = 1; | |
549 | } | |
9c318306 | 550 | } |
114cbee6 RS |
551 | |
552 | ||
553 | /* Search for first non-popped reg. */ | |
554 | for (i = FIRST_STACK_REG; i < LAST_STACK_REG + 1; i++) | |
555 | if (! reg_used_as_output[i]) | |
556 | break; | |
557 | ||
558 | /* If there are any other popped regs, that's an error. */ | |
559 | for (; i < LAST_STACK_REG + 1; i++) | |
560 | if (reg_used_as_output[i]) | |
561 | break; | |
562 | ||
563 | if (i != LAST_STACK_REG + 1) | |
564 | { | |
1f978f5f | 565 | error_for_asm (insn, "output regs must be grouped at top of stack"); |
114cbee6 RS |
566 | malformed_asm = 1; |
567 | } | |
568 | ||
569 | /* Enforce rule #2: All implicitly popped input regs must be closer | |
570 | to the top of the reg-stack than any input that is not implicitly | |
0f41302f | 571 | popped. */ |
114cbee6 | 572 | |
a05924f9 | 573 | memset (implicitly_dies, 0, sizeof (implicitly_dies)); |
f62a15e3 | 574 | for (i = n_outputs; i < n_outputs + n_inputs; i++) |
1ccbefce | 575 | if (STACK_REG_P (recog_data.operand[i])) |
114cbee6 RS |
576 | { |
577 | /* An input reg is implicitly popped if it is tied to an | |
0f41302f | 578 | output, or if there is a CLOBBER for it. */ |
114cbee6 RS |
579 | int j; |
580 | ||
581 | for (j = 0; j < n_clobbers; j++) | |
1ccbefce | 582 | if (operands_match_p (clobber_reg[j], recog_data.operand[i])) |
114cbee6 RS |
583 | break; |
584 | ||
f62a15e3 | 585 | if (j < n_clobbers || recog_op_alt[i][alt].matches >= 0) |
1ccbefce | 586 | implicitly_dies[REGNO (recog_data.operand[i])] = 1; |
114cbee6 RS |
587 | } |
588 | ||
589 | /* Search for first non-popped reg. */ | |
590 | for (i = FIRST_STACK_REG; i < LAST_STACK_REG + 1; i++) | |
591 | if (! implicitly_dies[i]) | |
592 | break; | |
593 | ||
594 | /* If there are any other popped regs, that's an error. */ | |
595 | for (; i < LAST_STACK_REG + 1; i++) | |
596 | if (implicitly_dies[i]) | |
597 | break; | |
598 | ||
599 | if (i != LAST_STACK_REG + 1) | |
600 | { | |
601 | error_for_asm (insn, | |
1f978f5f | 602 | "implicitly popped regs must be grouped at top of stack"); |
114cbee6 RS |
603 | malformed_asm = 1; |
604 | } | |
605 | ||
06d42c22 | 606 | /* Enforce rule #3: If any input operand uses the "f" constraint, all |
114cbee6 RS |
607 | output constraints must use the "&" earlyclobber. |
608 | ||
a05924f9 | 609 | ??? Detect this more deterministically by having constrain_asm_operands |
0f41302f | 610 | record any earlyclobber. */ |
114cbee6 | 611 | |
f62a15e3 BS |
612 | for (i = n_outputs; i < n_outputs + n_inputs; i++) |
613 | if (recog_op_alt[i][alt].matches == -1) | |
114cbee6 RS |
614 | { |
615 | int j; | |
616 | ||
617 | for (j = 0; j < n_outputs; j++) | |
1ccbefce | 618 | if (operands_match_p (recog_data.operand[j], recog_data.operand[i])) |
114cbee6 RS |
619 | { |
620 | error_for_asm (insn, | |
9e637a26 | 621 | "output operand %d must use %<&%> constraint", j); |
114cbee6 RS |
622 | malformed_asm = 1; |
623 | } | |
624 | } | |
625 | ||
626 | if (malformed_asm) | |
627 | { | |
628 | /* Avoid further trouble with this insn. */ | |
38a448ca | 629 | PATTERN (insn) = gen_rtx_USE (VOIDmode, const0_rtx); |
d6fc0492 | 630 | any_malformed_asm = true; |
a05924f9 | 631 | return 0; |
0e7d0eb9 | 632 | } |
48227150 | 633 | |
a05924f9 | 634 | return 1; |
48227150 JVA |
635 | } |
636 | \f | |
114cbee6 RS |
637 | /* Calculate the number of inputs and outputs in BODY, an |
638 | asm_operands. N_OPERANDS is the total number of operands, and | |
639 | N_INPUTS and N_OUTPUTS are pointers to ints into which the results are | |
0f41302f | 640 | placed. */ |
114cbee6 | 641 | |
1c384bf1 RH |
642 | static void |
643 | get_asm_operands_in_out (rtx body, int *pout, int *pin) | |
114cbee6 | 644 | { |
1c384bf1 RH |
645 | rtx asmop = extract_asm_operands (body); |
646 | ||
647 | *pin = ASM_OPERANDS_INPUT_LENGTH (asmop); | |
648 | *pout = (recog_data.n_operands | |
649 | - ASM_OPERANDS_INPUT_LENGTH (asmop) | |
650 | - ASM_OPERANDS_LABEL_LENGTH (asmop)); | |
114cbee6 | 651 | } |
0ab759e4 | 652 | |
96237362 | 653 | /* If current function returns its result in an fp stack register, |
9f9ed50a | 654 | return the REG. Otherwise, return 0. */ |
96237362 | 655 | |
99a59310 | 656 | static rtx |
0c20a65f | 657 | stack_result (tree decl) |
96237362 | 658 | { |
f099b1c9 | 659 | rtx result; |
96237362 | 660 | |
f099b1c9 JL |
661 | /* If the value is supposed to be returned in memory, then clearly |
662 | it is not returned in a stack register. */ | |
61f71b34 | 663 | if (aggregate_value_p (DECL_RESULT (decl), decl)) |
f099b1c9 JL |
664 | return 0; |
665 | ||
19e7881c | 666 | result = DECL_RTL_IF_SET (DECL_RESULT (decl)); |
9cf218a3 | 667 | if (result != 0) |
1d636cc6 RG |
668 | result = targetm.calls.function_value (TREE_TYPE (DECL_RESULT (decl)), |
669 | decl, true); | |
96237362 | 670 | |
9f9ed50a | 671 | return result != 0 && STACK_REG_P (result) ? result : 0; |
96237362 | 672 | } |
48227150 | 673 | \f |
48227150 | 674 | |
e075ae69 RH |
675 | /* |
676 | * This section deals with stack register substitution, and forms the second | |
677 | * pass over the RTL. | |
678 | */ | |
48227150 JVA |
679 | |
680 | /* Replace REG, which is a pointer to a stack reg RTX, with an RTX for | |
0f41302f | 681 | the desired hard REGNO. */ |
48227150 JVA |
682 | |
683 | static void | |
0c20a65f | 684 | replace_reg (rtx *reg, int regno) |
48227150 | 685 | { |
8dde5924 | 686 | gcc_assert (IN_RANGE (regno, FIRST_STACK_REG, LAST_STACK_REG)); |
41374e13 | 687 | gcc_assert (STACK_REG_P (*reg)); |
48227150 | 688 | |
3d8bf70f | 689 | gcc_assert (SCALAR_FLOAT_MODE_P (GET_MODE (*reg)) |
41374e13 | 690 | || GET_MODE_CLASS (GET_MODE (*reg)) == MODE_COMPLEX_FLOAT); |
7d0e3dd4 | 691 | |
99a59310 | 692 | *reg = FP_MODE_REG (regno, GET_MODE (*reg)); |
48227150 JVA |
693 | } |
694 | ||
695 | /* Remove a note of type NOTE, which must be found, for register | |
0f41302f | 696 | number REGNO from INSN. Remove only one such note. */ |
48227150 JVA |
697 | |
698 | static void | |
0c20a65f | 699 | remove_regno_note (rtx insn, enum reg_note note, unsigned int regno) |
48227150 | 700 | { |
d858f359 | 701 | rtx *note_link, this_rtx; |
48227150 | 702 | |
8e2e89f7 | 703 | note_link = ®_NOTES (insn); |
d858f359 KG |
704 | for (this_rtx = *note_link; this_rtx; this_rtx = XEXP (this_rtx, 1)) |
705 | if (REG_NOTE_KIND (this_rtx) == note | |
706 | && REG_P (XEXP (this_rtx, 0)) && REGNO (XEXP (this_rtx, 0)) == regno) | |
48227150 | 707 | { |
d858f359 | 708 | *note_link = XEXP (this_rtx, 1); |
48227150 JVA |
709 | return; |
710 | } | |
711 | else | |
d858f359 | 712 | note_link = &XEXP (this_rtx, 1); |
48227150 | 713 | |
41374e13 | 714 | gcc_unreachable (); |
48227150 JVA |
715 | } |
716 | ||
717 | /* Find the hard register number of virtual register REG in REGSTACK. | |
718 | The hard register number is relative to the top of the stack. -1 is | |
0f41302f | 719 | returned if the register is not found. */ |
48227150 JVA |
720 | |
721 | static int | |
0823efed | 722 | get_hard_regnum (stack_ptr regstack, rtx reg) |
48227150 JVA |
723 | { |
724 | int i; | |
725 | ||
41374e13 | 726 | gcc_assert (STACK_REG_P (reg)); |
48227150 JVA |
727 | |
728 | for (i = regstack->top; i >= 0; i--) | |
729 | if (regstack->reg[i] == REGNO (reg)) | |
730 | break; | |
731 | ||
732 | return i >= 0 ? (FIRST_STACK_REG + regstack->top - i) : -1; | |
733 | } | |
48227150 JVA |
734 | \f |
735 | /* Emit an insn to pop virtual register REG before or after INSN. | |
736 | REGSTACK is the stack state after INSN and is updated to reflect this | |
e075ae69 RH |
737 | pop. WHEN is either emit_insn_before or emit_insn_after. A pop insn |
738 | is represented as a SET whose destination is the register to be popped | |
739 | and source is the top of stack. A death note for the top of stack | |
0f41302f | 740 | cases the movdf pattern to pop. */ |
48227150 JVA |
741 | |
742 | static rtx | |
0823efed | 743 | emit_pop_insn (rtx insn, stack_ptr regstack, rtx reg, enum emit_where where) |
48227150 JVA |
744 | { |
745 | rtx pop_insn, pop_rtx; | |
746 | int hard_regno; | |
747 | ||
037f20f1 JH |
748 | /* For complex types take care to pop both halves. These may survive in |
749 | CLOBBER and USE expressions. */ | |
750 | if (COMPLEX_MODE_P (GET_MODE (reg))) | |
751 | { | |
752 | rtx reg1 = FP_MODE_REG (REGNO (reg), DFmode); | |
753 | rtx reg2 = FP_MODE_REG (REGNO (reg) + 1, DFmode); | |
754 | ||
755 | pop_insn = NULL_RTX; | |
756 | if (get_hard_regnum (regstack, reg1) >= 0) | |
a6a2274a | 757 | pop_insn = emit_pop_insn (insn, regstack, reg1, where); |
037f20f1 | 758 | if (get_hard_regnum (regstack, reg2) >= 0) |
a6a2274a | 759 | pop_insn = emit_pop_insn (insn, regstack, reg2, where); |
41374e13 | 760 | gcc_assert (pop_insn); |
037f20f1 JH |
761 | return pop_insn; |
762 | } | |
763 | ||
48227150 JVA |
764 | hard_regno = get_hard_regnum (regstack, reg); |
765 | ||
41374e13 | 766 | gcc_assert (hard_regno >= FIRST_STACK_REG); |
48227150 | 767 | |
e075ae69 RH |
768 | pop_rtx = gen_rtx_SET (VOIDmode, FP_MODE_REG (hard_regno, DFmode), |
769 | FP_MODE_REG (FIRST_STACK_REG, DFmode)); | |
48227150 | 770 | |
a05924f9 | 771 | if (where == EMIT_AFTER) |
3c030e88 | 772 | pop_insn = emit_insn_after (pop_rtx, insn); |
a05924f9 | 773 | else |
3c030e88 | 774 | pop_insn = emit_insn_before (pop_rtx, insn); |
48227150 | 775 | |
65c5f2a6 | 776 | add_reg_note (pop_insn, REG_DEAD, FP_MODE_REG (FIRST_STACK_REG, DFmode)); |
48227150 JVA |
777 | |
778 | regstack->reg[regstack->top - (hard_regno - FIRST_STACK_REG)] | |
779 | = regstack->reg[regstack->top]; | |
780 | regstack->top -= 1; | |
781 | CLEAR_HARD_REG_BIT (regstack->reg_set, REGNO (reg)); | |
782 | ||
783 | return pop_insn; | |
784 | } | |
785 | \f | |
a05924f9 JH |
786 | /* Emit an insn before or after INSN to swap virtual register REG with |
787 | the top of stack. REGSTACK is the stack state before the swap, and | |
788 | is updated to reflect the swap. A swap insn is represented as a | |
789 | PARALLEL of two patterns: each pattern moves one reg to the other. | |
48227150 | 790 | |
0f41302f | 791 | If REG is already at the top of the stack, no insn is emitted. */ |
48227150 JVA |
792 | |
793 | static void | |
0823efed | 794 | emit_swap_insn (rtx insn, stack_ptr regstack, rtx reg) |
48227150 | 795 | { |
eca31501 | 796 | int hard_regno; |
a05924f9 | 797 | rtx swap_rtx; |
eca31501 JVA |
798 | int tmp, other_reg; /* swap regno temps */ |
799 | rtx i1; /* the stack-reg insn prior to INSN */ | |
800 | rtx i1set = NULL_RTX; /* the SET rtx within I1 */ | |
48227150 | 801 | |
eca31501 JVA |
802 | hard_regno = get_hard_regnum (regstack, reg); |
803 | ||
48227150 JVA |
804 | if (hard_regno == FIRST_STACK_REG) |
805 | return; | |
7476f086 RH |
806 | if (hard_regno == -1) |
807 | { | |
808 | /* Something failed if the register wasn't on the stack. If we had | |
809 | malformed asms, we zapped the instruction itself, but that didn't | |
810 | produce the same pattern of register sets as before. To prevent | |
811 | further failure, adjust REGSTACK to include REG at TOP. */ | |
812 | gcc_assert (any_malformed_asm); | |
813 | regstack->reg[++regstack->top] = REGNO (reg); | |
814 | return; | |
815 | } | |
816 | gcc_assert (hard_regno >= FIRST_STACK_REG); | |
48227150 | 817 | |
eca31501 | 818 | other_reg = regstack->top - (hard_regno - FIRST_STACK_REG); |
48227150 | 819 | |
eca31501 JVA |
820 | tmp = regstack->reg[other_reg]; |
821 | regstack->reg[other_reg] = regstack->reg[regstack->top]; | |
48227150 | 822 | regstack->reg[regstack->top] = tmp; |
48227150 | 823 | |
a05924f9 JH |
824 | /* Find the previous insn involving stack regs, but don't pass a |
825 | block boundary. */ | |
826 | i1 = NULL; | |
a813c111 | 827 | if (current_block && insn != BB_HEAD (current_block)) |
eca31501 | 828 | { |
a05924f9 | 829 | rtx tmp = PREV_INSN (insn); |
a813c111 | 830 | rtx limit = PREV_INSN (BB_HEAD (current_block)); |
3a6cc978 | 831 | while (tmp != limit) |
a05924f9 | 832 | { |
4b4bf941 JQ |
833 | if (LABEL_P (tmp) |
834 | || CALL_P (tmp) | |
589ca5cb | 835 | || NOTE_INSN_BASIC_BLOCK_P (tmp) |
4b4bf941 | 836 | || (NONJUMP_INSN_P (tmp) |
a05924f9 JH |
837 | && stack_regs_mentioned (tmp))) |
838 | { | |
839 | i1 = tmp; | |
840 | break; | |
841 | } | |
842 | tmp = PREV_INSN (tmp); | |
843 | } | |
844 | } | |
845 | ||
846 | if (i1 != NULL_RTX | |
847 | && (i1set = single_set (i1)) != NULL_RTX) | |
848 | { | |
849 | rtx i1src = *get_true_reg (&SET_SRC (i1set)); | |
eca31501 | 850 | rtx i1dest = *get_true_reg (&SET_DEST (i1set)); |
48227150 | 851 | |
eca31501 | 852 | /* If the previous register stack push was from the reg we are to |
0f41302f | 853 | swap with, omit the swap. */ |
eca31501 | 854 | |
f8cfc6aa JQ |
855 | if (REG_P (i1dest) && REGNO (i1dest) == FIRST_STACK_REG |
856 | && REG_P (i1src) | |
ae0ed63a | 857 | && REGNO (i1src) == (unsigned) hard_regno - 1 |
eca31501 JVA |
858 | && find_regno_note (i1, REG_DEAD, FIRST_STACK_REG) == NULL_RTX) |
859 | return; | |
860 | ||
861 | /* If the previous insn wrote to the reg we are to swap with, | |
862 | omit the swap. */ | |
863 | ||
f8cfc6aa JQ |
864 | if (REG_P (i1dest) && REGNO (i1dest) == (unsigned) hard_regno |
865 | && REG_P (i1src) && REGNO (i1src) == FIRST_STACK_REG | |
eca31501 JVA |
866 | && find_regno_note (i1, REG_DEAD, FIRST_STACK_REG) == NULL_RTX) |
867 | return; | |
868 | } | |
869 | ||
385e0e08 RS |
870 | /* Avoid emitting the swap if this is the first register stack insn |
871 | of the current_block. Instead update the current_block's stack_in | |
872 | and let compensate edges take care of this for us. */ | |
873 | if (current_block && starting_stack_p) | |
874 | { | |
875 | BLOCK_INFO (current_block)->stack_in = *regstack; | |
876 | starting_stack_p = false; | |
877 | return; | |
878 | } | |
879 | ||
e075ae69 RH |
880 | swap_rtx = gen_swapxf (FP_MODE_REG (hard_regno, XFmode), |
881 | FP_MODE_REG (FIRST_STACK_REG, XFmode)); | |
a05924f9 JH |
882 | |
883 | if (i1) | |
3c030e88 | 884 | emit_insn_after (swap_rtx, i1); |
a05924f9 | 885 | else if (current_block) |
a813c111 | 886 | emit_insn_before (swap_rtx, BB_HEAD (current_block)); |
a05924f9 JH |
887 | else |
888 | emit_insn_before (swap_rtx, insn); | |
48227150 JVA |
889 | } |
890 | \f | |
f964bd29 UB |
891 | /* Emit an insns before INSN to swap virtual register SRC1 with |
892 | the top of stack and virtual register SRC2 with second stack | |
893 | slot. REGSTACK is the stack state before the swaps, and | |
894 | is updated to reflect the swaps. A swap insn is represented as a | |
895 | PARALLEL of two patterns: each pattern moves one reg to the other. | |
896 | ||
897 | If SRC1 and/or SRC2 are already at the right place, no swap insn | |
898 | is emitted. */ | |
899 | ||
900 | static void | |
0823efed | 901 | swap_to_top (rtx insn, stack_ptr regstack, rtx src1, rtx src2) |
f964bd29 UB |
902 | { |
903 | struct stack_def temp_stack; | |
904 | int regno, j, k, temp; | |
905 | ||
906 | temp_stack = *regstack; | |
907 | ||
908 | /* Place operand 1 at the top of stack. */ | |
909 | regno = get_hard_regnum (&temp_stack, src1); | |
41374e13 | 910 | gcc_assert (regno >= 0); |
f964bd29 UB |
911 | if (regno != FIRST_STACK_REG) |
912 | { | |
913 | k = temp_stack.top - (regno - FIRST_STACK_REG); | |
914 | j = temp_stack.top; | |
915 | ||
916 | temp = temp_stack.reg[k]; | |
917 | temp_stack.reg[k] = temp_stack.reg[j]; | |
918 | temp_stack.reg[j] = temp; | |
919 | } | |
920 | ||
921 | /* Place operand 2 next on the stack. */ | |
922 | regno = get_hard_regnum (&temp_stack, src2); | |
41374e13 | 923 | gcc_assert (regno >= 0); |
f964bd29 UB |
924 | if (regno != FIRST_STACK_REG + 1) |
925 | { | |
926 | k = temp_stack.top - (regno - FIRST_STACK_REG); | |
927 | j = temp_stack.top - 1; | |
928 | ||
929 | temp = temp_stack.reg[k]; | |
930 | temp_stack.reg[k] = temp_stack.reg[j]; | |
931 | temp_stack.reg[j] = temp; | |
932 | } | |
933 | ||
934 | change_stack (insn, regstack, &temp_stack, EMIT_BEFORE); | |
935 | } | |
936 | \f | |
48227150 | 937 | /* Handle a move to or from a stack register in PAT, which is in INSN. |
ecb63641 EB |
938 | REGSTACK is the current stack. Return whether a control flow insn |
939 | was deleted in the process. */ | |
48227150 | 940 | |
ecb63641 | 941 | static bool |
0823efed | 942 | move_for_stack_reg (rtx insn, stack_ptr regstack, rtx pat) |
48227150 | 943 | { |
99a59310 RK |
944 | rtx *psrc = get_true_reg (&SET_SRC (pat)); |
945 | rtx *pdest = get_true_reg (&SET_DEST (pat)); | |
946 | rtx src, dest; | |
48227150 | 947 | rtx note; |
ecb63641 | 948 | bool control_flow_insn_deleted = false; |
48227150 | 949 | |
99a59310 RK |
950 | src = *psrc; dest = *pdest; |
951 | ||
952 | if (STACK_REG_P (src) && STACK_REG_P (dest)) | |
48227150 JVA |
953 | { |
954 | /* Write from one stack reg to another. If SRC dies here, then | |
0f41302f | 955 | just change the register mapping and delete the insn. */ |
48227150 | 956 | |
99a59310 | 957 | note = find_regno_note (insn, REG_DEAD, REGNO (src)); |
48227150 JVA |
958 | if (note) |
959 | { | |
960 | int i; | |
961 | ||
0f41302f | 962 | /* If this is a no-op move, there must not be a REG_DEAD note. */ |
41374e13 | 963 | gcc_assert (REGNO (src) != REGNO (dest)); |
48227150 JVA |
964 | |
965 | for (i = regstack->top; i >= 0; i--) | |
99a59310 | 966 | if (regstack->reg[i] == REGNO (src)) |
48227150 JVA |
967 | break; |
968 | ||
5ad85f7d | 969 | /* The destination must be dead, or life analysis is borked. */ |
41374e13 | 970 | gcc_assert (get_hard_regnum (regstack, dest) < FIRST_STACK_REG); |
48227150 | 971 | |
5ad85f7d RH |
972 | /* If the source is not live, this is yet another case of |
973 | uninitialized variables. Load up a NaN instead. */ | |
974 | if (i < 0) | |
975 | return move_nan_for_stack_reg (insn, regstack, dest); | |
976 | ||
48227150 | 977 | /* It is possible that the dest is unused after this insn. |
0f41302f | 978 | If so, just pop the src. */ |
48227150 | 979 | |
99a59310 | 980 | if (find_regno_note (insn, REG_UNUSED, REGNO (dest))) |
ecb63641 EB |
981 | emit_pop_insn (insn, regstack, src, EMIT_AFTER); |
982 | else | |
48227150 | 983 | { |
ecb63641 EB |
984 | regstack->reg[i] = REGNO (dest); |
985 | SET_HARD_REG_BIT (regstack->reg_set, REGNO (dest)); | |
986 | CLEAR_HARD_REG_BIT (regstack->reg_set, REGNO (src)); | |
48227150 JVA |
987 | } |
988 | ||
ecb63641 | 989 | control_flow_insn_deleted |= control_flow_insn_p (insn); |
53c17031 | 990 | delete_insn (insn); |
ecb63641 | 991 | return control_flow_insn_deleted; |
48227150 JVA |
992 | } |
993 | ||
0f41302f | 994 | /* The source reg does not die. */ |
48227150 JVA |
995 | |
996 | /* If this appears to be a no-op move, delete it, or else it | |
997 | will confuse the machine description output patterns. But if | |
998 | it is REG_UNUSED, we must pop the reg now, as per-insn processing | |
0f41302f | 999 | for REG_UNUSED will not work for deleted insns. */ |
48227150 | 1000 | |
99a59310 | 1001 | if (REGNO (src) == REGNO (dest)) |
48227150 | 1002 | { |
99a59310 | 1003 | if (find_regno_note (insn, REG_UNUSED, REGNO (dest))) |
a05924f9 | 1004 | emit_pop_insn (insn, regstack, dest, EMIT_AFTER); |
48227150 | 1005 | |
ecb63641 | 1006 | control_flow_insn_deleted |= control_flow_insn_p (insn); |
53c17031 | 1007 | delete_insn (insn); |
ecb63641 | 1008 | return control_flow_insn_deleted; |
48227150 JVA |
1009 | } |
1010 | ||
3eae4643 | 1011 | /* The destination ought to be dead. */ |
41374e13 | 1012 | gcc_assert (get_hard_regnum (regstack, dest) < FIRST_STACK_REG); |
48227150 | 1013 | |
99a59310 | 1014 | replace_reg (psrc, get_hard_regnum (regstack, src)); |
48227150 | 1015 | |
99a59310 RK |
1016 | regstack->reg[++regstack->top] = REGNO (dest); |
1017 | SET_HARD_REG_BIT (regstack->reg_set, REGNO (dest)); | |
1018 | replace_reg (pdest, FIRST_STACK_REG); | |
48227150 | 1019 | } |
99a59310 | 1020 | else if (STACK_REG_P (src)) |
48227150 JVA |
1021 | { |
1022 | /* Save from a stack reg to MEM, or possibly integer reg. Since | |
1023 | only top of stack may be saved, emit an exchange first if | |
0f41302f | 1024 | needs be. */ |
48227150 | 1025 | |
99a59310 | 1026 | emit_swap_insn (insn, regstack, src); |
48227150 | 1027 | |
99a59310 | 1028 | note = find_regno_note (insn, REG_DEAD, REGNO (src)); |
48227150 JVA |
1029 | if (note) |
1030 | { | |
1031 | replace_reg (&XEXP (note, 0), FIRST_STACK_REG); | |
1032 | regstack->top--; | |
99a59310 | 1033 | CLEAR_HARD_REG_BIT (regstack->reg_set, REGNO (src)); |
48227150 | 1034 | } |
f8a1ebc6 | 1035 | else if ((GET_MODE (src) == XFmode) |
cadcffb3 | 1036 | && regstack->top < REG_STACK_SIZE - 1) |
b40b8b06 JVA |
1037 | { |
1038 | /* A 387 cannot write an XFmode value to a MEM without | |
1039 | clobbering the source reg. The output code can handle | |
1040 | this by reading back the value from the MEM. | |
1041 | But it is more efficient to use a temp register if one is | |
1042 | available. Push the source value here if the register | |
1043 | stack is not full, and then write the value to memory via | |
1044 | a pop. */ | |
f7448d50 | 1045 | rtx push_rtx; |
037f20f1 | 1046 | rtx top_stack_reg = FP_MODE_REG (FIRST_STACK_REG, GET_MODE (src)); |
b40b8b06 | 1047 | |
f8a1ebc6 | 1048 | push_rtx = gen_movxf (top_stack_reg, top_stack_reg); |
f7448d50 | 1049 | emit_insn_before (push_rtx, insn); |
65c5f2a6 | 1050 | add_reg_note (insn, REG_DEAD, top_stack_reg); |
b40b8b06 | 1051 | } |
48227150 | 1052 | |
99a59310 | 1053 | replace_reg (psrc, FIRST_STACK_REG); |
48227150 | 1054 | } |
41374e13 | 1055 | else |
48227150 | 1056 | { |
d85c7550 UB |
1057 | rtx pat = PATTERN (insn); |
1058 | ||
41374e13 NS |
1059 | gcc_assert (STACK_REG_P (dest)); |
1060 | ||
48227150 JVA |
1061 | /* Load from MEM, or possibly integer REG or constant, into the |
1062 | stack regs. The actual target is always the top of the | |
1063 | stack. The stack mapping is changed to reflect that DEST is | |
1064 | now at top of stack. */ | |
1065 | ||
d85c7550 UB |
1066 | /* The destination ought to be dead. However, there is a |
1067 | special case with i387 UNSPEC_TAN, where destination is live | |
1068 | (an argument to fptan) but inherent load of 1.0 is modelled | |
1069 | as a load from a constant. */ | |
590e9a42 UB |
1070 | if (GET_CODE (pat) == PARALLEL |
1071 | && XVECLEN (pat, 0) == 2 | |
1072 | && GET_CODE (XVECEXP (pat, 0, 1)) == SET | |
1073 | && GET_CODE (SET_SRC (XVECEXP (pat, 0, 1))) == UNSPEC | |
1074 | && XINT (SET_SRC (XVECEXP (pat, 0, 1)), 1) == UNSPEC_TAN) | |
1075 | emit_swap_insn (insn, regstack, dest); | |
1076 | else | |
d85c7550 | 1077 | gcc_assert (get_hard_regnum (regstack, dest) < FIRST_STACK_REG); |
48227150 | 1078 | |
41374e13 | 1079 | gcc_assert (regstack->top < REG_STACK_SIZE); |
48227150 | 1080 | |
99a59310 RK |
1081 | regstack->reg[++regstack->top] = REGNO (dest); |
1082 | SET_HARD_REG_BIT (regstack->reg_set, REGNO (dest)); | |
1083 | replace_reg (pdest, FIRST_STACK_REG); | |
48227150 | 1084 | } |
ecb63641 EB |
1085 | |
1086 | return control_flow_insn_deleted; | |
48227150 | 1087 | } |
5ad85f7d RH |
1088 | |
1089 | /* A helper function which replaces INSN with a pattern that loads up | |
1090 | a NaN into DEST, then invokes move_for_stack_reg. */ | |
1091 | ||
1092 | static bool | |
0823efed | 1093 | move_nan_for_stack_reg (rtx insn, stack_ptr regstack, rtx dest) |
5ad85f7d RH |
1094 | { |
1095 | rtx pat; | |
1096 | ||
1097 | dest = FP_MODE_REG (REGNO (dest), SFmode); | |
1098 | pat = gen_rtx_SET (VOIDmode, dest, not_a_num); | |
1099 | PATTERN (insn) = pat; | |
1100 | INSN_CODE (insn) = -1; | |
1101 | ||
1102 | return move_for_stack_reg (insn, regstack, pat); | |
1103 | } | |
48227150 | 1104 | \f |
e075ae69 RH |
1105 | /* Swap the condition on a branch, if there is one. Return true if we |
1106 | found a condition to swap. False if the condition was not used as | |
dc297297 | 1107 | such. */ |
e075ae69 RH |
1108 | |
1109 | static int | |
0c20a65f | 1110 | swap_rtx_condition_1 (rtx pat) |
eca31501 | 1111 | { |
b3694847 SS |
1112 | const char *fmt; |
1113 | int i, r = 0; | |
eca31501 | 1114 | |
ec8e098d | 1115 | if (COMPARISON_P (pat)) |
eca31501 JVA |
1116 | { |
1117 | PUT_CODE (pat, swap_condition (GET_CODE (pat))); | |
e075ae69 | 1118 | r = 1; |
eca31501 | 1119 | } |
e075ae69 | 1120 | else |
eca31501 | 1121 | { |
e075ae69 RH |
1122 | fmt = GET_RTX_FORMAT (GET_CODE (pat)); |
1123 | for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0; i--) | |
eca31501 | 1124 | { |
e075ae69 RH |
1125 | if (fmt[i] == 'E') |
1126 | { | |
b3694847 | 1127 | int j; |
eca31501 | 1128 | |
e075ae69 RH |
1129 | for (j = XVECLEN (pat, i) - 1; j >= 0; j--) |
1130 | r |= swap_rtx_condition_1 (XVECEXP (pat, i, j)); | |
1131 | } | |
1132 | else if (fmt[i] == 'e') | |
1133 | r |= swap_rtx_condition_1 (XEXP (pat, i)); | |
eca31501 | 1134 | } |
eca31501 | 1135 | } |
e075ae69 RH |
1136 | |
1137 | return r; | |
1138 | } | |
1139 | ||
1140 | static int | |
0c20a65f | 1141 | swap_rtx_condition (rtx insn) |
e075ae69 RH |
1142 | { |
1143 | rtx pat = PATTERN (insn); | |
1144 | ||
1145 | /* We're looking for a single set to cc0 or an HImode temporary. */ | |
1146 | ||
1147 | if (GET_CODE (pat) == SET | |
f8cfc6aa | 1148 | && REG_P (SET_DEST (pat)) |
e075ae69 RH |
1149 | && REGNO (SET_DEST (pat)) == FLAGS_REG) |
1150 | { | |
1151 | insn = next_flags_user (insn); | |
1152 | if (insn == NULL_RTX) | |
1153 | return 0; | |
1154 | pat = PATTERN (insn); | |
1155 | } | |
1156 | ||
383898f7 JJ |
1157 | /* See if this is, or ends in, a fnstsw. If so, we're not doing anything |
1158 | with the cc value right now. We may be able to search for one | |
1159 | though. */ | |
e075ae69 RH |
1160 | |
1161 | if (GET_CODE (pat) == SET | |
1162 | && GET_CODE (SET_SRC (pat)) == UNSPEC | |
35a76aac | 1163 | && XINT (SET_SRC (pat), 1) == UNSPEC_FNSTSW) |
e075ae69 RH |
1164 | { |
1165 | rtx dest = SET_DEST (pat); | |
1166 | ||
a6a2274a | 1167 | /* Search forward looking for the first use of this value. |
e075ae69 | 1168 | Stop at block boundaries. */ |
a813c111 | 1169 | while (insn != BB_END (current_block)) |
e075ae69 RH |
1170 | { |
1171 | insn = NEXT_INSN (insn); | |
2c3c49de | 1172 | if (INSN_P (insn) && reg_mentioned_p (dest, insn)) |
e075ae69 | 1173 | break; |
4b4bf941 | 1174 | if (CALL_P (insn)) |
e075ae69 RH |
1175 | return 0; |
1176 | } | |
1177 | ||
383898f7 JJ |
1178 | /* We haven't found it. */ |
1179 | if (insn == BB_END (current_block)) | |
1180 | return 0; | |
1181 | ||
e075ae69 | 1182 | /* So we've found the insn using this value. If it is anything |
383898f7 JJ |
1183 | other than sahf or the value does not die (meaning we'd have |
1184 | to search further), then we must give up. */ | |
e075ae69 RH |
1185 | pat = PATTERN (insn); |
1186 | if (GET_CODE (pat) != SET | |
1187 | || GET_CODE (SET_SRC (pat)) != UNSPEC | |
35a76aac | 1188 | || XINT (SET_SRC (pat), 1) != UNSPEC_SAHF |
e075ae69 RH |
1189 | || ! dead_or_set_p (insn, dest)) |
1190 | return 0; | |
1191 | ||
1192 | /* Now we are prepared to handle this as a normal cc0 setter. */ | |
1193 | insn = next_flags_user (insn); | |
1194 | if (insn == NULL_RTX) | |
1195 | return 0; | |
1196 | pat = PATTERN (insn); | |
1197 | } | |
1198 | ||
90a74703 JH |
1199 | if (swap_rtx_condition_1 (pat)) |
1200 | { | |
0eac0e81 | 1201 | int fail = 0; |
90a74703 JH |
1202 | INSN_CODE (insn) = -1; |
1203 | if (recog_memoized (insn) == -1) | |
0eac0e81 JH |
1204 | fail = 1; |
1205 | /* In case the flags don't die here, recurse to try fix | |
1206 | following user too. */ | |
1207 | else if (! dead_or_set_p (insn, ix86_flags_rtx)) | |
1208 | { | |
1209 | insn = next_flags_user (insn); | |
1210 | if (!insn || !swap_rtx_condition (insn)) | |
1211 | fail = 1; | |
1212 | } | |
1213 | if (fail) | |
90a74703 JH |
1214 | { |
1215 | swap_rtx_condition_1 (pat); | |
1216 | return 0; | |
1217 | } | |
1218 | return 1; | |
1219 | } | |
1220 | return 0; | |
eca31501 JVA |
1221 | } |
1222 | ||
48227150 JVA |
1223 | /* Handle a comparison. Special care needs to be taken to avoid |
1224 | causing comparisons that a 387 cannot do correctly, such as EQ. | |
1225 | ||
e075ae69 | 1226 | Also, a pop insn may need to be emitted. The 387 does have an |
48227150 JVA |
1227 | `fcompp' insn that can pop two regs, but it is sometimes too expensive |
1228 | to do this - a `fcomp' followed by a `fstpl %st(0)' may be easier to | |
e075ae69 | 1229 | set up. */ |
48227150 JVA |
1230 | |
1231 | static void | |
0823efed | 1232 | compare_for_stack_reg (rtx insn, stack_ptr regstack, rtx pat_src) |
48227150 JVA |
1233 | { |
1234 | rtx *src1, *src2; | |
1235 | rtx src1_note, src2_note; | |
914ec131 | 1236 | |
e075ae69 RH |
1237 | src1 = get_true_reg (&XEXP (pat_src, 0)); |
1238 | src2 = get_true_reg (&XEXP (pat_src, 1)); | |
48227150 | 1239 | |
eca31501 | 1240 | /* ??? If fxch turns out to be cheaper than fstp, give priority to |
0f41302f | 1241 | registers that die in this insn - move those to stack top first. */ |
e075ae69 RH |
1242 | if ((! STACK_REG_P (*src1) |
1243 | || (STACK_REG_P (*src2) | |
1244 | && get_hard_regnum (regstack, *src2) == FIRST_STACK_REG)) | |
1245 | && swap_rtx_condition (insn)) | |
eca31501 | 1246 | { |
e075ae69 RH |
1247 | rtx temp; |
1248 | temp = XEXP (pat_src, 0); | |
1249 | XEXP (pat_src, 0) = XEXP (pat_src, 1); | |
1250 | XEXP (pat_src, 1) = temp; | |
48227150 | 1251 | |
e075ae69 RH |
1252 | src1 = get_true_reg (&XEXP (pat_src, 0)); |
1253 | src2 = get_true_reg (&XEXP (pat_src, 1)); | |
dc78213e | 1254 | |
b9342cdf | 1255 | INSN_CODE (insn) = -1; |
eca31501 | 1256 | } |
48227150 | 1257 | |
0f41302f | 1258 | /* We will fix any death note later. */ |
48227150 JVA |
1259 | |
1260 | src1_note = find_regno_note (insn, REG_DEAD, REGNO (*src1)); | |
1261 | ||
1262 | if (STACK_REG_P (*src2)) | |
1263 | src2_note = find_regno_note (insn, REG_DEAD, REGNO (*src2)); | |
1264 | else | |
eca31501 | 1265 | src2_note = NULL_RTX; |
48227150 | 1266 | |
e075ae69 | 1267 | emit_swap_insn (insn, regstack, *src1); |
48227150 JVA |
1268 | |
1269 | replace_reg (src1, FIRST_STACK_REG); | |
1270 | ||
1271 | if (STACK_REG_P (*src2)) | |
e075ae69 | 1272 | replace_reg (src2, get_hard_regnum (regstack, *src2)); |
48227150 JVA |
1273 | |
1274 | if (src1_note) | |
1275 | { | |
7aa74e4c | 1276 | pop_stack (regstack, REGNO (XEXP (src1_note, 0))); |
48227150 | 1277 | replace_reg (&XEXP (src1_note, 0), FIRST_STACK_REG); |
48227150 JVA |
1278 | } |
1279 | ||
1280 | /* If the second operand dies, handle that. But if the operands are | |
1281 | the same stack register, don't bother, because only one death is | |
0f41302f | 1282 | needed, and it was just handled. */ |
48227150 JVA |
1283 | |
1284 | if (src2_note | |
eca31501 | 1285 | && ! (STACK_REG_P (*src1) && STACK_REG_P (*src2) |
48227150 JVA |
1286 | && REGNO (*src1) == REGNO (*src2))) |
1287 | { | |
1288 | /* As a special case, two regs may die in this insn if src2 is | |
1289 | next to top of stack and the top of stack also dies. Since | |
1290 | we have already popped src1, "next to top of stack" is really | |
0f41302f | 1291 | at top (FIRST_STACK_REG) now. */ |
48227150 JVA |
1292 | |
1293 | if (get_hard_regnum (regstack, XEXP (src2_note, 0)) == FIRST_STACK_REG | |
1294 | && src1_note) | |
1295 | { | |
7aa74e4c | 1296 | pop_stack (regstack, REGNO (XEXP (src2_note, 0))); |
48227150 | 1297 | replace_reg (&XEXP (src2_note, 0), FIRST_STACK_REG + 1); |
48227150 JVA |
1298 | } |
1299 | else | |
1300 | { | |
e075ae69 RH |
1301 | /* The 386 can only represent death of the first operand in |
1302 | the case handled above. In all other cases, emit a separate | |
1303 | pop and remove the death note from here. */ | |
e075ae69 | 1304 | remove_regno_note (insn, REG_DEAD, REGNO (XEXP (src2_note, 0))); |
e075ae69 | 1305 | emit_pop_insn (insn, regstack, XEXP (src2_note, 0), |
a05924f9 | 1306 | EMIT_AFTER); |
48227150 JVA |
1307 | } |
1308 | } | |
1309 | } | |
1310 | \f | |
b5b8b0ac AO |
1311 | /* Substitute new registers in LOC, which is part of a debug insn. |
1312 | REGSTACK is the current register layout. */ | |
1313 | ||
1314 | static int | |
1315 | subst_stack_regs_in_debug_insn (rtx *loc, void *data) | |
1316 | { | |
0823efed | 1317 | stack_ptr regstack = (stack_ptr)data; |
b5b8b0ac AO |
1318 | int hard_regno; |
1319 | ||
bd0ba05d | 1320 | if (!STACK_REG_P (*loc)) |
b5b8b0ac AO |
1321 | return 0; |
1322 | ||
1323 | hard_regno = get_hard_regnum (regstack, *loc); | |
a7a110bb AO |
1324 | |
1325 | /* If we can't find an active register, reset this debug insn. */ | |
1326 | if (hard_regno == -1) | |
1327 | return 1; | |
1328 | ||
b5b8b0ac AO |
1329 | gcc_assert (hard_regno >= FIRST_STACK_REG); |
1330 | ||
1331 | replace_reg (loc, hard_regno); | |
1332 | ||
1333 | return -1; | |
1334 | } | |
1335 | ||
a7a110bb AO |
1336 | /* Substitute hardware stack regs in debug insn INSN, using stack |
1337 | layout REGSTACK. If we can't find a hardware stack reg for any of | |
1338 | the REGs in it, reset the debug insn. */ | |
1339 | ||
1340 | static void | |
1341 | subst_all_stack_regs_in_debug_insn (rtx insn, struct stack_def *regstack) | |
1342 | { | |
1343 | int ret = for_each_rtx (&INSN_VAR_LOCATION_LOC (insn), | |
1344 | subst_stack_regs_in_debug_insn, | |
1345 | regstack); | |
1346 | ||
1347 | if (ret == 1) | |
1348 | INSN_VAR_LOCATION_LOC (insn) = gen_rtx_UNKNOWN_VAR_LOC (); | |
1349 | else | |
1350 | gcc_checking_assert (ret == 0); | |
1351 | } | |
1352 | ||
48227150 | 1353 | /* Substitute new registers in PAT, which is part of INSN. REGSTACK |
ecb63641 EB |
1354 | is the current register layout. Return whether a control flow insn |
1355 | was deleted in the process. */ | |
48227150 | 1356 | |
ecb63641 | 1357 | static bool |
0823efed | 1358 | subst_stack_regs_pat (rtx insn, stack_ptr regstack, rtx pat) |
48227150 JVA |
1359 | { |
1360 | rtx *dest, *src; | |
ecb63641 | 1361 | bool control_flow_insn_deleted = false; |
48227150 | 1362 | |
a05924f9 JH |
1363 | switch (GET_CODE (pat)) |
1364 | { | |
1365 | case USE: | |
1366 | /* Deaths in USE insns can happen in non optimizing compilation. | |
1367 | Handle them by popping the dying register. */ | |
1368 | src = get_true_reg (&XEXP (pat, 0)); | |
a6a2274a KH |
1369 | if (STACK_REG_P (*src) |
1370 | && find_regno_note (insn, REG_DEAD, REGNO (*src))) | |
1371 | { | |
6fb5fa3c DB |
1372 | /* USEs are ignored for liveness information so USEs of dead |
1373 | register might happen. */ | |
1374 | if (TEST_HARD_REG_BIT (regstack->reg_set, REGNO (*src))) | |
1375 | emit_pop_insn (insn, regstack, *src, EMIT_AFTER); | |
ecb63641 | 1376 | return control_flow_insn_deleted; |
a6a2274a | 1377 | } |
6fb5fa3c DB |
1378 | /* Uninitialized USE might happen for functions returning uninitialized |
1379 | value. We will properly initialize the USE on the edge to EXIT_BLOCK, | |
cea618ac | 1380 | so it is safe to ignore the use here. This is consistent with behavior |
b8698a0f | 1381 | of dataflow analyzer that ignores USE too. (This also imply that |
cea618ac | 1382 | forcibly initializing the register to NaN here would lead to ICE later, |
6fb5fa3c | 1383 | since the REG_DEAD notes are not issued.) */ |
a05924f9 | 1384 | break; |
48227150 | 1385 | |
b5b8b0ac AO |
1386 | case VAR_LOCATION: |
1387 | gcc_unreachable (); | |
1388 | ||
a05924f9 JH |
1389 | case CLOBBER: |
1390 | { | |
1391 | rtx note; | |
48227150 | 1392 | |
a05924f9 JH |
1393 | dest = get_true_reg (&XEXP (pat, 0)); |
1394 | if (STACK_REG_P (*dest)) | |
1395 | { | |
1396 | note = find_reg_note (insn, REG_DEAD, *dest); | |
bd695e1e RH |
1397 | |
1398 | if (pat != PATTERN (insn)) | |
1399 | { | |
83a6ac60 VM |
1400 | /* The fix_truncdi_1 pattern wants to be able to |
1401 | allocate its own scratch register. It does this by | |
1402 | clobbering an fp reg so that it is assured of an | |
1403 | empty reg-stack register. If the register is live, | |
1404 | kill it now. Remove the DEAD/UNUSED note so we | |
1405 | don't try to kill it later too. | |
1406 | ||
1407 | In reality the UNUSED note can be absent in some | |
1408 | complicated cases when the register is reused for | |
1409 | partially set variable. */ | |
bd695e1e RH |
1410 | |
1411 | if (note) | |
1412 | emit_pop_insn (insn, regstack, *dest, EMIT_BEFORE); | |
1413 | else | |
83a6ac60 VM |
1414 | note = find_reg_note (insn, REG_UNUSED, *dest); |
1415 | if (note) | |
1416 | remove_note (insn, note); | |
cb0bc263 | 1417 | replace_reg (dest, FIRST_STACK_REG + 1); |
bd695e1e | 1418 | } |
a05924f9 JH |
1419 | else |
1420 | { | |
bd695e1e RH |
1421 | /* A top-level clobber with no REG_DEAD, and no hard-regnum |
1422 | indicates an uninitialized value. Because reload removed | |
a6a2274a | 1423 | all other clobbers, this must be due to a function |
bd695e1e RH |
1424 | returning without a value. Load up a NaN. */ |
1425 | ||
5ad85f7d | 1426 | if (!note) |
037f20f1 | 1427 | { |
5ad85f7d | 1428 | rtx t = *dest; |
5ad85f7d RH |
1429 | if (COMPLEX_MODE_P (GET_MODE (t))) |
1430 | { | |
190e9534 PB |
1431 | rtx u = FP_MODE_REG (REGNO (t) + 1, SFmode); |
1432 | if (get_hard_regnum (regstack, u) == -1) | |
1433 | { | |
1434 | rtx pat2 = gen_rtx_CLOBBER (VOIDmode, u); | |
1435 | rtx insn2 = emit_insn_before (pat2, insn); | |
1436 | control_flow_insn_deleted | |
1437 | |= move_nan_for_stack_reg (insn2, regstack, u); | |
1438 | } | |
5ad85f7d | 1439 | } |
190e9534 PB |
1440 | if (get_hard_regnum (regstack, t) == -1) |
1441 | control_flow_insn_deleted | |
1442 | |= move_nan_for_stack_reg (insn, regstack, t); | |
037f20f1 | 1443 | } |
a05924f9 | 1444 | } |
a05924f9 | 1445 | } |
48227150 | 1446 | break; |
a05924f9 | 1447 | } |
48227150 | 1448 | |
a05924f9 JH |
1449 | case SET: |
1450 | { | |
6496a589 | 1451 | rtx *src1 = (rtx *) 0, *src2; |
a05924f9 JH |
1452 | rtx src1_note, src2_note; |
1453 | rtx pat_src; | |
1454 | ||
1455 | dest = get_true_reg (&SET_DEST (pat)); | |
1456 | src = get_true_reg (&SET_SRC (pat)); | |
1457 | pat_src = SET_SRC (pat); | |
1458 | ||
1459 | /* See if this is a `movM' pattern, and handle elsewhere if so. */ | |
1460 | if (STACK_REG_P (*src) | |
1461 | || (STACK_REG_P (*dest) | |
3c0cb5de | 1462 | && (REG_P (*src) || MEM_P (*src) |
48175537 | 1463 | || CONST_DOUBLE_P (*src)))) |
a05924f9 | 1464 | { |
ecb63641 | 1465 | control_flow_insn_deleted |= move_for_stack_reg (insn, regstack, pat); |
a05924f9 JH |
1466 | break; |
1467 | } | |
48227150 | 1468 | |
a05924f9 JH |
1469 | switch (GET_CODE (pat_src)) |
1470 | { | |
1471 | case COMPARE: | |
1472 | compare_for_stack_reg (insn, regstack, pat_src); | |
1473 | break; | |
48227150 | 1474 | |
a05924f9 JH |
1475 | case CALL: |
1476 | { | |
1477 | int count; | |
66fd46b6 | 1478 | for (count = hard_regno_nregs[REGNO (*dest)][GET_MODE (*dest)]; |
a05924f9 JH |
1479 | --count >= 0;) |
1480 | { | |
1481 | regstack->reg[++regstack->top] = REGNO (*dest) + count; | |
1482 | SET_HARD_REG_BIT (regstack->reg_set, REGNO (*dest) + count); | |
1483 | } | |
1484 | } | |
1485 | replace_reg (dest, FIRST_STACK_REG); | |
1486 | break; | |
48227150 | 1487 | |
a05924f9 JH |
1488 | case REG: |
1489 | /* This is a `tstM2' case. */ | |
41374e13 | 1490 | gcc_assert (*dest == cc0_rtx); |
a05924f9 | 1491 | src1 = src; |
48227150 | 1492 | |
a05924f9 | 1493 | /* Fall through. */ |
48227150 | 1494 | |
a05924f9 JH |
1495 | case FLOAT_TRUNCATE: |
1496 | case SQRT: | |
1497 | case ABS: | |
1498 | case NEG: | |
1499 | /* These insns only operate on the top of the stack. DEST might | |
1500 | be cc0_rtx if we're processing a tstM pattern. Also, it's | |
1501 | possible that the tstM case results in a REG_DEAD note on the | |
1502 | source. */ | |
48227150 | 1503 | |
a05924f9 JH |
1504 | if (src1 == 0) |
1505 | src1 = get_true_reg (&XEXP (pat_src, 0)); | |
48227150 | 1506 | |
a05924f9 | 1507 | emit_swap_insn (insn, regstack, *src1); |
48227150 | 1508 | |
a05924f9 | 1509 | src1_note = find_regno_note (insn, REG_DEAD, REGNO (*src1)); |
48227150 | 1510 | |
a05924f9 JH |
1511 | if (STACK_REG_P (*dest)) |
1512 | replace_reg (dest, FIRST_STACK_REG); | |
48227150 | 1513 | |
a05924f9 JH |
1514 | if (src1_note) |
1515 | { | |
1516 | replace_reg (&XEXP (src1_note, 0), FIRST_STACK_REG); | |
1517 | regstack->top--; | |
1518 | CLEAR_HARD_REG_BIT (regstack->reg_set, REGNO (*src1)); | |
1519 | } | |
48227150 | 1520 | |
a05924f9 JH |
1521 | replace_reg (src1, FIRST_STACK_REG); |
1522 | break; | |
48227150 | 1523 | |
a05924f9 JH |
1524 | case MINUS: |
1525 | case DIV: | |
1526 | /* On i386, reversed forms of subM3 and divM3 exist for | |
1527 | MODE_FLOAT, so the same code that works for addM3 and mulM3 | |
1528 | can be used. */ | |
1529 | case MULT: | |
1530 | case PLUS: | |
1531 | /* These insns can accept the top of stack as a destination | |
1532 | from a stack reg or mem, or can use the top of stack as a | |
1533 | source and some other stack register (possibly top of stack) | |
1534 | as a destination. */ | |
1535 | ||
1536 | src1 = get_true_reg (&XEXP (pat_src, 0)); | |
1537 | src2 = get_true_reg (&XEXP (pat_src, 1)); | |
1538 | ||
1539 | /* We will fix any death note later. */ | |
1540 | ||
1541 | if (STACK_REG_P (*src1)) | |
1542 | src1_note = find_regno_note (insn, REG_DEAD, REGNO (*src1)); | |
1543 | else | |
1544 | src1_note = NULL_RTX; | |
1545 | if (STACK_REG_P (*src2)) | |
1546 | src2_note = find_regno_note (insn, REG_DEAD, REGNO (*src2)); | |
1547 | else | |
1548 | src2_note = NULL_RTX; | |
48227150 | 1549 | |
a05924f9 JH |
1550 | /* If either operand is not a stack register, then the dest |
1551 | must be top of stack. */ | |
48227150 | 1552 | |
a05924f9 | 1553 | if (! STACK_REG_P (*src1) || ! STACK_REG_P (*src2)) |
eca31501 | 1554 | emit_swap_insn (insn, regstack, *dest); |
a05924f9 JH |
1555 | else |
1556 | { | |
1557 | /* Both operands are REG. If neither operand is already | |
34e4536e UB |
1558 | at the top of stack, choose to make the one that is the |
1559 | dest the new top of stack. */ | |
48227150 | 1560 | |
a05924f9 | 1561 | int src1_hard_regnum, src2_hard_regnum; |
48227150 | 1562 | |
a05924f9 JH |
1563 | src1_hard_regnum = get_hard_regnum (regstack, *src1); |
1564 | src2_hard_regnum = get_hard_regnum (regstack, *src2); | |
34e4536e UB |
1565 | |
1566 | /* If the source is not live, this is yet another case of | |
1567 | uninitialized variables. Load up a NaN instead. */ | |
1568 | if (src1_hard_regnum == -1) | |
1569 | { | |
1570 | rtx pat2 = gen_rtx_CLOBBER (VOIDmode, *src1); | |
1571 | rtx insn2 = emit_insn_before (pat2, insn); | |
1572 | control_flow_insn_deleted | |
1573 | |= move_nan_for_stack_reg (insn2, regstack, *src1); | |
1574 | } | |
1575 | if (src2_hard_regnum == -1) | |
1576 | { | |
1577 | rtx pat2 = gen_rtx_CLOBBER (VOIDmode, *src2); | |
1578 | rtx insn2 = emit_insn_before (pat2, insn); | |
1579 | control_flow_insn_deleted | |
1580 | |= move_nan_for_stack_reg (insn2, regstack, *src2); | |
1581 | } | |
48227150 | 1582 | |
a05924f9 JH |
1583 | if (src1_hard_regnum != FIRST_STACK_REG |
1584 | && src2_hard_regnum != FIRST_STACK_REG) | |
1585 | emit_swap_insn (insn, regstack, *dest); | |
48227150 | 1586 | } |
a05924f9 JH |
1587 | |
1588 | if (STACK_REG_P (*src1)) | |
1589 | replace_reg (src1, get_hard_regnum (regstack, *src1)); | |
1590 | if (STACK_REG_P (*src2)) | |
1591 | replace_reg (src2, get_hard_regnum (regstack, *src2)); | |
1592 | ||
1593 | if (src1_note) | |
48227150 | 1594 | { |
a05924f9 | 1595 | rtx src1_reg = XEXP (src1_note, 0); |
48227150 | 1596 | |
a05924f9 JH |
1597 | /* If the register that dies is at the top of stack, then |
1598 | the destination is somewhere else - merely substitute it. | |
1599 | But if the reg that dies is not at top of stack, then | |
1600 | move the top of stack to the dead reg, as though we had | |
1601 | done the insn and then a store-with-pop. */ | |
48227150 | 1602 | |
a05924f9 JH |
1603 | if (REGNO (src1_reg) == regstack->reg[regstack->top]) |
1604 | { | |
1605 | SET_HARD_REG_BIT (regstack->reg_set, REGNO (*dest)); | |
1606 | replace_reg (dest, get_hard_regnum (regstack, *dest)); | |
1607 | } | |
1608 | else | |
1609 | { | |
1610 | int regno = get_hard_regnum (regstack, src1_reg); | |
48227150 | 1611 | |
a05924f9 JH |
1612 | SET_HARD_REG_BIT (regstack->reg_set, REGNO (*dest)); |
1613 | replace_reg (dest, regno); | |
1614 | ||
1615 | regstack->reg[regstack->top - (regno - FIRST_STACK_REG)] | |
1616 | = regstack->reg[regstack->top]; | |
1617 | } | |
1618 | ||
1619 | CLEAR_HARD_REG_BIT (regstack->reg_set, | |
1620 | REGNO (XEXP (src1_note, 0))); | |
1621 | replace_reg (&XEXP (src1_note, 0), FIRST_STACK_REG); | |
1622 | regstack->top--; | |
1623 | } | |
1624 | else if (src2_note) | |
48227150 | 1625 | { |
a05924f9 JH |
1626 | rtx src2_reg = XEXP (src2_note, 0); |
1627 | if (REGNO (src2_reg) == regstack->reg[regstack->top]) | |
1628 | { | |
1629 | SET_HARD_REG_BIT (regstack->reg_set, REGNO (*dest)); | |
1630 | replace_reg (dest, get_hard_regnum (regstack, *dest)); | |
1631 | } | |
1632 | else | |
1633 | { | |
1634 | int regno = get_hard_regnum (regstack, src2_reg); | |
1635 | ||
1636 | SET_HARD_REG_BIT (regstack->reg_set, REGNO (*dest)); | |
1637 | replace_reg (dest, regno); | |
1638 | ||
1639 | regstack->reg[regstack->top - (regno - FIRST_STACK_REG)] | |
1640 | = regstack->reg[regstack->top]; | |
1641 | } | |
1642 | ||
1643 | CLEAR_HARD_REG_BIT (regstack->reg_set, | |
1644 | REGNO (XEXP (src2_note, 0))); | |
1645 | replace_reg (&XEXP (src2_note, 0), FIRST_STACK_REG); | |
1646 | regstack->top--; | |
48227150 JVA |
1647 | } |
1648 | else | |
1649 | { | |
48227150 | 1650 | SET_HARD_REG_BIT (regstack->reg_set, REGNO (*dest)); |
a05924f9 | 1651 | replace_reg (dest, get_hard_regnum (regstack, *dest)); |
48227150 | 1652 | } |
caa6ec8d | 1653 | |
d55d8fc7 | 1654 | /* Keep operand 1 matching with destination. */ |
ec8e098d | 1655 | if (COMMUTATIVE_ARITH_P (pat_src) |
caa6ec8d JH |
1656 | && REG_P (*src1) && REG_P (*src2) |
1657 | && REGNO (*src1) != REGNO (*dest)) | |
1658 | { | |
0b9aaeee JH |
1659 | int tmp = REGNO (*src1); |
1660 | replace_reg (src1, REGNO (*src2)); | |
1661 | replace_reg (src2, tmp); | |
caa6ec8d | 1662 | } |
a05924f9 | 1663 | break; |
48227150 | 1664 | |
a05924f9 JH |
1665 | case UNSPEC: |
1666 | switch (XINT (pat_src, 1)) | |
1667 | { | |
09ad58e6 | 1668 | case UNSPEC_STA: |
6e858d45 | 1669 | case UNSPEC_FIST: |
4a927664 UB |
1670 | |
1671 | case UNSPEC_FIST_FLOOR: | |
1672 | case UNSPEC_FIST_CEIL: | |
1673 | ||
6e858d45 UB |
1674 | /* These insns only operate on the top of the stack. */ |
1675 | ||
1676 | src1 = get_true_reg (&XVECEXP (pat_src, 0, 0)); | |
1677 | emit_swap_insn (insn, regstack, *src1); | |
1678 | ||
1679 | src1_note = find_regno_note (insn, REG_DEAD, REGNO (*src1)); | |
1680 | ||
1681 | if (STACK_REG_P (*dest)) | |
1682 | replace_reg (dest, FIRST_STACK_REG); | |
1683 | ||
1684 | if (src1_note) | |
1685 | { | |
1686 | replace_reg (&XEXP (src1_note, 0), FIRST_STACK_REG); | |
1687 | regstack->top--; | |
1688 | CLEAR_HARD_REG_BIT (regstack->reg_set, REGNO (*src1)); | |
1689 | } | |
1690 | ||
1691 | replace_reg (src1, FIRST_STACK_REG); | |
1692 | break; | |
1693 | ||
9ed4207f UB |
1694 | case UNSPEC_FXAM: |
1695 | ||
1696 | /* This insn only operate on the top of the stack. */ | |
1697 | ||
1698 | src1 = get_true_reg (&XVECEXP (pat_src, 0, 0)); | |
1699 | emit_swap_insn (insn, regstack, *src1); | |
1700 | ||
1701 | src1_note = find_regno_note (insn, REG_DEAD, REGNO (*src1)); | |
1702 | ||
1703 | replace_reg (src1, FIRST_STACK_REG); | |
1704 | ||
1705 | if (src1_note) | |
1706 | { | |
1707 | remove_regno_note (insn, REG_DEAD, | |
1708 | REGNO (XEXP (src1_note, 0))); | |
1709 | emit_pop_insn (insn, regstack, XEXP (src1_note, 0), | |
1710 | EMIT_AFTER); | |
1711 | } | |
1712 | ||
1713 | break; | |
1714 | ||
35a76aac RH |
1715 | case UNSPEC_SIN: |
1716 | case UNSPEC_COS: | |
9d5b9dae RS |
1717 | case UNSPEC_FRNDINT: |
1718 | case UNSPEC_F2XM1: | |
edeacc14 UB |
1719 | |
1720 | case UNSPEC_FRNDINT_FLOOR: | |
1721 | case UNSPEC_FRNDINT_CEIL: | |
1722 | case UNSPEC_FRNDINT_TRUNC: | |
1723 | case UNSPEC_FRNDINT_MASK_PM: | |
1724 | ||
d85c7550 UB |
1725 | /* Above insns operate on the top of the stack. */ |
1726 | ||
1727 | case UNSPEC_SINCOS_COS: | |
1728 | case UNSPEC_XTRACT_FRACT: | |
1729 | ||
1730 | /* Above insns operate on the top two stack slots, | |
1731 | first part of one input, double output insn. */ | |
0e7d0eb9 | 1732 | |
a05924f9 | 1733 | src1 = get_true_reg (&XVECEXP (pat_src, 0, 0)); |
0e7d0eb9 | 1734 | |
a05924f9 | 1735 | emit_swap_insn (insn, regstack, *src1); |
0e7d0eb9 | 1736 | |
d85c7550 | 1737 | /* Input should never die, it is replaced with output. */ |
a05924f9 | 1738 | src1_note = find_regno_note (insn, REG_DEAD, REGNO (*src1)); |
41374e13 | 1739 | gcc_assert (!src1_note); |
0e7d0eb9 | 1740 | |
a05924f9 JH |
1741 | if (STACK_REG_P (*dest)) |
1742 | replace_reg (dest, FIRST_STACK_REG); | |
0e7d0eb9 | 1743 | |
a05924f9 JH |
1744 | replace_reg (src1, FIRST_STACK_REG); |
1745 | break; | |
0e7d0eb9 | 1746 | |
d85c7550 UB |
1747 | case UNSPEC_SINCOS_SIN: |
1748 | case UNSPEC_XTRACT_EXP: | |
1749 | ||
1750 | /* These insns operate on the top two stack slots, | |
1751 | second part of one input, double output insn. */ | |
1752 | ||
1753 | regstack->top++; | |
1754 | /* FALLTHRU */ | |
1755 | ||
1756 | case UNSPEC_TAN: | |
1757 | ||
1758 | /* For UNSPEC_TAN, regstack->top is already increased | |
1759 | by inherent load of constant 1.0. */ | |
1760 | ||
1761 | /* Output value is generated in the second stack slot. | |
1762 | Move current value from second slot to the top. */ | |
1763 | regstack->reg[regstack->top] | |
1764 | = regstack->reg[regstack->top - 1]; | |
1765 | ||
1766 | gcc_assert (STACK_REG_P (*dest)); | |
1767 | ||
1768 | regstack->reg[regstack->top - 1] = REGNO (*dest); | |
1769 | SET_HARD_REG_BIT (regstack->reg_set, REGNO (*dest)); | |
1770 | replace_reg (dest, FIRST_STACK_REG + 1); | |
1771 | ||
1772 | src1 = get_true_reg (&XVECEXP (pat_src, 0, 0)); | |
1773 | ||
1774 | replace_reg (src1, FIRST_STACK_REG); | |
1775 | break; | |
1776 | ||
1fb54135 | 1777 | case UNSPEC_FPATAN: |
358997e2 | 1778 | case UNSPEC_FYL2X: |
c2fcfa4f | 1779 | case UNSPEC_FYL2XP1: |
1fb54135 RS |
1780 | /* These insns operate on the top two stack slots. */ |
1781 | ||
1782 | src1 = get_true_reg (&XVECEXP (pat_src, 0, 0)); | |
1783 | src2 = get_true_reg (&XVECEXP (pat_src, 0, 1)); | |
1784 | ||
1785 | src1_note = find_regno_note (insn, REG_DEAD, REGNO (*src1)); | |
1786 | src2_note = find_regno_note (insn, REG_DEAD, REGNO (*src2)); | |
1787 | ||
f964bd29 | 1788 | swap_to_top (insn, regstack, *src1, *src2); |
1fb54135 RS |
1789 | |
1790 | replace_reg (src1, FIRST_STACK_REG); | |
1791 | replace_reg (src2, FIRST_STACK_REG + 1); | |
1792 | ||
1793 | if (src1_note) | |
1794 | replace_reg (&XEXP (src1_note, 0), FIRST_STACK_REG); | |
1795 | if (src2_note) | |
1796 | replace_reg (&XEXP (src2_note, 0), FIRST_STACK_REG + 1); | |
1797 | ||
1798 | /* Pop both input operands from the stack. */ | |
1799 | CLEAR_HARD_REG_BIT (regstack->reg_set, | |
1800 | regstack->reg[regstack->top]); | |
1801 | CLEAR_HARD_REG_BIT (regstack->reg_set, | |
1802 | regstack->reg[regstack->top - 1]); | |
1803 | regstack->top -= 2; | |
1804 | ||
1805 | /* Push the result back onto the stack. */ | |
1806 | regstack->reg[++regstack->top] = REGNO (*dest); | |
1807 | SET_HARD_REG_BIT (regstack->reg_set, REGNO (*dest)); | |
1808 | replace_reg (dest, FIRST_STACK_REG); | |
1809 | break; | |
1810 | ||
f964bd29 | 1811 | case UNSPEC_FSCALE_FRACT: |
5ae27cfa UB |
1812 | case UNSPEC_FPREM_F: |
1813 | case UNSPEC_FPREM1_F: | |
79cd820a | 1814 | /* These insns operate on the top two stack slots, |
f964bd29 UB |
1815 | first part of double input, double output insn. */ |
1816 | ||
1817 | src1 = get_true_reg (&XVECEXP (pat_src, 0, 0)); | |
1818 | src2 = get_true_reg (&XVECEXP (pat_src, 0, 1)); | |
1819 | ||
1820 | src1_note = find_regno_note (insn, REG_DEAD, REGNO (*src1)); | |
1821 | src2_note = find_regno_note (insn, REG_DEAD, REGNO (*src2)); | |
1822 | ||
1823 | /* Inputs should never die, they are | |
1824 | replaced with outputs. */ | |
41374e13 NS |
1825 | gcc_assert (!src1_note); |
1826 | gcc_assert (!src2_note); | |
f964bd29 UB |
1827 | |
1828 | swap_to_top (insn, regstack, *src1, *src2); | |
1829 | ||
1830 | /* Push the result back onto stack. Empty stack slot | |
9cf737f8 | 1831 | will be filled in second part of insn. */ |
428aba16 RS |
1832 | if (STACK_REG_P (*dest)) |
1833 | { | |
1834 | regstack->reg[regstack->top] = REGNO (*dest); | |
1835 | SET_HARD_REG_BIT (regstack->reg_set, REGNO (*dest)); | |
1836 | replace_reg (dest, FIRST_STACK_REG); | |
1837 | } | |
f964bd29 UB |
1838 | |
1839 | replace_reg (src1, FIRST_STACK_REG); | |
1840 | replace_reg (src2, FIRST_STACK_REG + 1); | |
1841 | break; | |
1842 | ||
1843 | case UNSPEC_FSCALE_EXP: | |
5ae27cfa UB |
1844 | case UNSPEC_FPREM_U: |
1845 | case UNSPEC_FPREM1_U: | |
79cd820a | 1846 | /* These insns operate on the top two stack slots, |
f964bd29 UB |
1847 | second part of double input, double output insn. */ |
1848 | ||
1849 | src1 = get_true_reg (&XVECEXP (pat_src, 0, 0)); | |
1850 | src2 = get_true_reg (&XVECEXP (pat_src, 0, 1)); | |
1851 | ||
f964bd29 UB |
1852 | /* Push the result back onto stack. Fill empty slot from |
1853 | first part of insn and fix top of stack pointer. */ | |
428aba16 RS |
1854 | if (STACK_REG_P (*dest)) |
1855 | { | |
1856 | regstack->reg[regstack->top - 1] = REGNO (*dest); | |
1857 | SET_HARD_REG_BIT (regstack->reg_set, REGNO (*dest)); | |
1858 | replace_reg (dest, FIRST_STACK_REG + 1); | |
1859 | } | |
f964bd29 UB |
1860 | |
1861 | replace_reg (src1, FIRST_STACK_REG); | |
1862 | replace_reg (src2, FIRST_STACK_REG + 1); | |
1863 | break; | |
1864 | ||
79cd820a UB |
1865 | case UNSPEC_C2_FLAG: |
1866 | /* This insn operates on the top two stack slots, | |
1867 | third part of C2 setting double input insn. */ | |
1868 | ||
1869 | src1 = get_true_reg (&XVECEXP (pat_src, 0, 0)); | |
1870 | src2 = get_true_reg (&XVECEXP (pat_src, 0, 1)); | |
1871 | ||
1872 | replace_reg (src1, FIRST_STACK_REG); | |
1873 | replace_reg (src2, FIRST_STACK_REG + 1); | |
1874 | break; | |
1875 | ||
35a76aac RH |
1876 | case UNSPEC_SAHF: |
1877 | /* (unspec [(unspec [(compare)] UNSPEC_FNSTSW)] UNSPEC_SAHF) | |
1878 | The combination matches the PPRO fcomi instruction. */ | |
0e7d0eb9 | 1879 | |
a05924f9 | 1880 | pat_src = XVECEXP (pat_src, 0, 0); |
41374e13 NS |
1881 | gcc_assert (GET_CODE (pat_src) == UNSPEC); |
1882 | gcc_assert (XINT (pat_src, 1) == UNSPEC_FNSTSW); | |
5d3cc252 | 1883 | /* Fall through. */ |
e075ae69 | 1884 | |
35a76aac | 1885 | case UNSPEC_FNSTSW: |
a05924f9 JH |
1886 | /* Combined fcomp+fnstsw generated for doing well with |
1887 | CSE. When optimizing this would have been broken | |
1888 | up before now. */ | |
e075ae69 | 1889 | |
a05924f9 | 1890 | pat_src = XVECEXP (pat_src, 0, 0); |
41374e13 | 1891 | gcc_assert (GET_CODE (pat_src) == COMPARE); |
e075ae69 | 1892 | |
a05924f9 JH |
1893 | compare_for_stack_reg (insn, regstack, pat_src); |
1894 | break; | |
e075ae69 | 1895 | |
a05924f9 | 1896 | default: |
41374e13 | 1897 | gcc_unreachable (); |
a05924f9 | 1898 | } |
e075ae69 RH |
1899 | break; |
1900 | ||
a05924f9 | 1901 | case IF_THEN_ELSE: |
dc297297 | 1902 | /* This insn requires the top of stack to be the destination. */ |
0e7d0eb9 | 1903 | |
2ab0437e JH |
1904 | src1 = get_true_reg (&XEXP (pat_src, 1)); |
1905 | src2 = get_true_reg (&XEXP (pat_src, 2)); | |
1906 | ||
1907 | src1_note = find_regno_note (insn, REG_DEAD, REGNO (*src1)); | |
1908 | src2_note = find_regno_note (insn, REG_DEAD, REGNO (*src2)); | |
1909 | ||
a05924f9 JH |
1910 | /* If the comparison operator is an FP comparison operator, |
1911 | it is handled correctly by compare_for_stack_reg () who | |
1912 | will move the destination to the top of stack. But if the | |
1913 | comparison operator is not an FP comparison operator, we | |
dc297297 | 1914 | have to handle it here. */ |
a05924f9 JH |
1915 | if (get_hard_regnum (regstack, *dest) >= FIRST_STACK_REG |
1916 | && REGNO (*dest) != regstack->reg[regstack->top]) | |
2ab0437e JH |
1917 | { |
1918 | /* In case one of operands is the top of stack and the operands | |
35a76aac RH |
1919 | dies, it is safe to make it the destination operand by |
1920 | reversing the direction of cmove and avoid fxch. */ | |
2ab0437e JH |
1921 | if ((REGNO (*src1) == regstack->reg[regstack->top] |
1922 | && src1_note) | |
1923 | || (REGNO (*src2) == regstack->reg[regstack->top] | |
1924 | && src2_note)) | |
1925 | { | |
b74cf1ce JH |
1926 | int idx1 = (get_hard_regnum (regstack, *src1) |
1927 | - FIRST_STACK_REG); | |
1928 | int idx2 = (get_hard_regnum (regstack, *src2) | |
1929 | - FIRST_STACK_REG); | |
1930 | ||
1931 | /* Make reg-stack believe that the operands are already | |
1932 | swapped on the stack */ | |
1933 | regstack->reg[regstack->top - idx1] = REGNO (*src2); | |
1934 | regstack->reg[regstack->top - idx2] = REGNO (*src1); | |
1935 | ||
1936 | /* Reverse condition to compensate the operand swap. | |
1937 | i386 do have comparison always reversible. */ | |
2ab0437e JH |
1938 | PUT_CODE (XEXP (pat_src, 0), |
1939 | reversed_comparison_code (XEXP (pat_src, 0), insn)); | |
1940 | } | |
1941 | else | |
a6a2274a | 1942 | emit_swap_insn (insn, regstack, *dest); |
2ab0437e | 1943 | } |
4e97601f | 1944 | |
a05924f9 JH |
1945 | { |
1946 | rtx src_note [3]; | |
1947 | int i; | |
4e97601f | 1948 | |
a05924f9 JH |
1949 | src_note[0] = 0; |
1950 | src_note[1] = src1_note; | |
1951 | src_note[2] = src2_note; | |
54552651 | 1952 | |
a05924f9 JH |
1953 | if (STACK_REG_P (*src1)) |
1954 | replace_reg (src1, get_hard_regnum (regstack, *src1)); | |
1955 | if (STACK_REG_P (*src2)) | |
1956 | replace_reg (src2, get_hard_regnum (regstack, *src2)); | |
4e97601f | 1957 | |
a05924f9 JH |
1958 | for (i = 1; i <= 2; i++) |
1959 | if (src_note [i]) | |
4e97601f | 1960 | { |
a05924f9 JH |
1961 | int regno = REGNO (XEXP (src_note[i], 0)); |
1962 | ||
1963 | /* If the register that dies is not at the top of | |
41374e13 NS |
1964 | stack, then move the top of stack to the dead reg. |
1965 | Top of stack should never die, as it is the | |
1966 | destination. */ | |
1967 | gcc_assert (regno != regstack->reg[regstack->top]); | |
1968 | remove_regno_note (insn, REG_DEAD, regno); | |
1969 | emit_pop_insn (insn, regstack, XEXP (src_note[i], 0), | |
1970 | EMIT_AFTER); | |
4e97601f | 1971 | } |
a05924f9 | 1972 | } |
4e97601f | 1973 | |
a05924f9 | 1974 | /* Make dest the top of stack. Add dest to regstack if |
dc297297 | 1975 | not present. */ |
a05924f9 | 1976 | if (get_hard_regnum (regstack, *dest) < FIRST_STACK_REG) |
a6a2274a | 1977 | regstack->reg[++regstack->top] = REGNO (*dest); |
a05924f9 JH |
1978 | SET_HARD_REG_BIT (regstack->reg_set, REGNO (*dest)); |
1979 | replace_reg (dest, FIRST_STACK_REG); | |
1980 | break; | |
914ec131 | 1981 | |
a05924f9 | 1982 | default: |
41374e13 | 1983 | gcc_unreachable (); |
a05924f9 | 1984 | } |
4e97601f | 1985 | break; |
48227150 | 1986 | } |
a05924f9 JH |
1987 | |
1988 | default: | |
1989 | break; | |
1990 | } | |
ecb63641 EB |
1991 | |
1992 | return control_flow_insn_deleted; | |
48227150 JVA |
1993 | } |
1994 | \f | |
114cbee6 RS |
1995 | /* Substitute hard regnums for any stack regs in INSN, which has |
1996 | N_INPUTS inputs and N_OUTPUTS outputs. REGSTACK is the stack info | |
f62a15e3 | 1997 | before the insn, and is updated with changes made here. |
114cbee6 RS |
1998 | |
1999 | There are several requirements and assumptions about the use of | |
2000 | stack-like regs in asm statements. These rules are enforced by | |
2001 | record_asm_stack_regs; see comments there for details. Any | |
2002 | asm_operands left in the RTL at this point may be assume to meet the | |
561cf7b1 | 2003 | requirements, since record_asm_stack_regs removes any problem asm. */ |
114cbee6 | 2004 | |
561cf7b1 | 2005 | static void |
0823efed | 2006 | subst_asm_stack_regs (rtx insn, stack_ptr regstack) |
114cbee6 | 2007 | { |
114cbee6 | 2008 | rtx body = PATTERN (insn); |
f62a15e3 | 2009 | int alt; |
114cbee6 RS |
2010 | |
2011 | rtx *note_reg; /* Array of note contents */ | |
2012 | rtx **note_loc; /* Address of REG field of each note */ | |
2013 | enum reg_note *note_kind; /* The type of each note */ | |
2014 | ||
a544cfd2 KG |
2015 | rtx *clobber_reg = 0; |
2016 | rtx **clobber_loc = 0; | |
114cbee6 RS |
2017 | |
2018 | struct stack_def temp_stack; | |
2019 | int n_notes; | |
2020 | int n_clobbers; | |
2021 | rtx note; | |
2022 | int i; | |
f62a15e3 | 2023 | int n_inputs, n_outputs; |
114cbee6 | 2024 | |
a05924f9 JH |
2025 | if (! check_asm_stack_operands (insn)) |
2026 | return; | |
2027 | ||
114cbee6 RS |
2028 | /* Find out what the constraints required. If no constraint |
2029 | alternative matches, that is a compiler bug: we should have caught | |
a05924f9 | 2030 | such an insn in check_asm_stack_operands. */ |
f62a15e3 BS |
2031 | extract_insn (insn); |
2032 | constrain_operands (1); | |
2033 | alt = which_alternative; | |
2034 | ||
2035 | preprocess_constraints (); | |
114cbee6 | 2036 | |
1c384bf1 | 2037 | get_asm_operands_in_out (body, &n_outputs, &n_inputs); |
a6a2274a | 2038 | |
41374e13 | 2039 | gcc_assert (alt >= 0); |
114cbee6 | 2040 | |
0f41302f | 2041 | /* Strip SUBREGs here to make the following code simpler. */ |
1ccbefce RH |
2042 | for (i = 0; i < recog_data.n_operands; i++) |
2043 | if (GET_CODE (recog_data.operand[i]) == SUBREG | |
f8cfc6aa | 2044 | && REG_P (SUBREG_REG (recog_data.operand[i]))) |
114cbee6 | 2045 | { |
1ccbefce RH |
2046 | recog_data.operand_loc[i] = & SUBREG_REG (recog_data.operand[i]); |
2047 | recog_data.operand[i] = SUBREG_REG (recog_data.operand[i]); | |
114cbee6 RS |
2048 | } |
2049 | ||
2050 | /* Set up NOTE_REG, NOTE_LOC and NOTE_KIND. */ | |
2051 | ||
2052 | for (i = 0, note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
2053 | i++; | |
2054 | ||
1634b18f KG |
2055 | note_reg = XALLOCAVEC (rtx, i); |
2056 | note_loc = XALLOCAVEC (rtx *, i); | |
2057 | note_kind = XALLOCAVEC (enum reg_note, i); | |
114cbee6 RS |
2058 | |
2059 | n_notes = 0; | |
2060 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
2061 | { | |
e5af9ddd RS |
2062 | if (GET_CODE (note) != EXPR_LIST) |
2063 | continue; | |
114cbee6 RS |
2064 | rtx reg = XEXP (note, 0); |
2065 | rtx *loc = & XEXP (note, 0); | |
2066 | ||
f8cfc6aa | 2067 | if (GET_CODE (reg) == SUBREG && REG_P (SUBREG_REG (reg))) |
114cbee6 RS |
2068 | { |
2069 | loc = & SUBREG_REG (reg); | |
2070 | reg = SUBREG_REG (reg); | |
2071 | } | |
2072 | ||
2073 | if (STACK_REG_P (reg) | |
2074 | && (REG_NOTE_KIND (note) == REG_DEAD | |
2075 | || REG_NOTE_KIND (note) == REG_UNUSED)) | |
2076 | { | |
2077 | note_reg[n_notes] = reg; | |
2078 | note_loc[n_notes] = loc; | |
2079 | note_kind[n_notes] = REG_NOTE_KIND (note); | |
2080 | n_notes++; | |
2081 | } | |
2082 | } | |
2083 | ||
2084 | /* Set up CLOBBER_REG and CLOBBER_LOC. */ | |
2085 | ||
2086 | n_clobbers = 0; | |
114cbee6 RS |
2087 | |
2088 | if (GET_CODE (body) == PARALLEL) | |
3f5cfed6 | 2089 | { |
1634b18f KG |
2090 | clobber_reg = XALLOCAVEC (rtx, XVECLEN (body, 0)); |
2091 | clobber_loc = XALLOCAVEC (rtx *, XVECLEN (body, 0)); | |
114cbee6 | 2092 | |
3f5cfed6 JVA |
2093 | for (i = 0; i < XVECLEN (body, 0); i++) |
2094 | if (GET_CODE (XVECEXP (body, 0, i)) == CLOBBER) | |
2095 | { | |
2096 | rtx clobber = XVECEXP (body, 0, i); | |
2097 | rtx reg = XEXP (clobber, 0); | |
2098 | rtx *loc = & XEXP (clobber, 0); | |
114cbee6 | 2099 | |
f8cfc6aa | 2100 | if (GET_CODE (reg) == SUBREG && REG_P (SUBREG_REG (reg))) |
3f5cfed6 JVA |
2101 | { |
2102 | loc = & SUBREG_REG (reg); | |
2103 | reg = SUBREG_REG (reg); | |
2104 | } | |
2105 | ||
2106 | if (STACK_REG_P (reg)) | |
2107 | { | |
2108 | clobber_reg[n_clobbers] = reg; | |
2109 | clobber_loc[n_clobbers] = loc; | |
2110 | n_clobbers++; | |
2111 | } | |
2112 | } | |
2113 | } | |
114cbee6 | 2114 | |
a05924f9 | 2115 | temp_stack = *regstack; |
114cbee6 RS |
2116 | |
2117 | /* Put the input regs into the desired place in TEMP_STACK. */ | |
2118 | ||
f62a15e3 | 2119 | for (i = n_outputs; i < n_outputs + n_inputs; i++) |
1ccbefce | 2120 | if (STACK_REG_P (recog_data.operand[i]) |
e3a64162 | 2121 | && reg_class_subset_p (recog_op_alt[i][alt].cl, |
f62a15e3 | 2122 | FLOAT_REGS) |
e3a64162 | 2123 | && recog_op_alt[i][alt].cl != FLOAT_REGS) |
114cbee6 RS |
2124 | { |
2125 | /* If an operand needs to be in a particular reg in | |
2126 | FLOAT_REGS, the constraint was either 't' or 'u'. Since | |
1ccbefce RH |
2127 | these constraints are for single register classes, and |
2128 | reload guaranteed that operand[i] is already in that class, | |
2129 | we can just use REGNO (recog_data.operand[i]) to know which | |
2130 | actual reg this operand needs to be in. */ | |
114cbee6 | 2131 | |
1ccbefce | 2132 | int regno = get_hard_regnum (&temp_stack, recog_data.operand[i]); |
114cbee6 | 2133 | |
41374e13 | 2134 | gcc_assert (regno >= 0); |
114cbee6 | 2135 | |
ae0ed63a | 2136 | if ((unsigned int) regno != REGNO (recog_data.operand[i])) |
114cbee6 | 2137 | { |
1ccbefce RH |
2138 | /* recog_data.operand[i] is not in the right place. Find |
2139 | it and swap it with whatever is already in I's place. | |
2140 | K is where recog_data.operand[i] is now. J is where it | |
2141 | should be. */ | |
114cbee6 RS |
2142 | int j, k, temp; |
2143 | ||
2144 | k = temp_stack.top - (regno - FIRST_STACK_REG); | |
2145 | j = (temp_stack.top | |
1ccbefce | 2146 | - (REGNO (recog_data.operand[i]) - FIRST_STACK_REG)); |
114cbee6 RS |
2147 | |
2148 | temp = temp_stack.reg[k]; | |
2149 | temp_stack.reg[k] = temp_stack.reg[j]; | |
2150 | temp_stack.reg[j] = temp; | |
2151 | } | |
2152 | } | |
2153 | ||
a05924f9 | 2154 | /* Emit insns before INSN to make sure the reg-stack is in the right |
114cbee6 RS |
2155 | order. */ |
2156 | ||
a05924f9 | 2157 | change_stack (insn, regstack, &temp_stack, EMIT_BEFORE); |
114cbee6 RS |
2158 | |
2159 | /* Make the needed input register substitutions. Do death notes and | |
0f41302f | 2160 | clobbers too, because these are for inputs, not outputs. */ |
114cbee6 | 2161 | |
f62a15e3 | 2162 | for (i = n_outputs; i < n_outputs + n_inputs; i++) |
1ccbefce | 2163 | if (STACK_REG_P (recog_data.operand[i])) |
114cbee6 | 2164 | { |
1ccbefce | 2165 | int regnum = get_hard_regnum (regstack, recog_data.operand[i]); |
114cbee6 | 2166 | |
41374e13 | 2167 | gcc_assert (regnum >= 0); |
114cbee6 | 2168 | |
1ccbefce | 2169 | replace_reg (recog_data.operand_loc[i], regnum); |
114cbee6 RS |
2170 | } |
2171 | ||
2172 | for (i = 0; i < n_notes; i++) | |
2173 | if (note_kind[i] == REG_DEAD) | |
2174 | { | |
2175 | int regnum = get_hard_regnum (regstack, note_reg[i]); | |
2176 | ||
41374e13 | 2177 | gcc_assert (regnum >= 0); |
114cbee6 RS |
2178 | |
2179 | replace_reg (note_loc[i], regnum); | |
2180 | } | |
2181 | ||
2182 | for (i = 0; i < n_clobbers; i++) | |
2183 | { | |
2184 | /* It's OK for a CLOBBER to reference a reg that is not live. | |
2185 | Don't try to replace it in that case. */ | |
2186 | int regnum = get_hard_regnum (regstack, clobber_reg[i]); | |
2187 | ||
2188 | if (regnum >= 0) | |
2189 | { | |
2190 | /* Sigh - clobbers always have QImode. But replace_reg knows | |
41374e13 | 2191 | that these regs can't be MODE_INT and will assert. Just put |
114cbee6 RS |
2192 | the right reg there without calling replace_reg. */ |
2193 | ||
99a59310 | 2194 | *clobber_loc[i] = FP_MODE_REG (regnum, DFmode); |
114cbee6 RS |
2195 | } |
2196 | } | |
2197 | ||
0f41302f | 2198 | /* Now remove from REGSTACK any inputs that the asm implicitly popped. */ |
114cbee6 | 2199 | |
f62a15e3 | 2200 | for (i = n_outputs; i < n_outputs + n_inputs; i++) |
1ccbefce | 2201 | if (STACK_REG_P (recog_data.operand[i])) |
114cbee6 RS |
2202 | { |
2203 | /* An input reg is implicitly popped if it is tied to an | |
0f41302f | 2204 | output, or if there is a CLOBBER for it. */ |
114cbee6 RS |
2205 | int j; |
2206 | ||
2207 | for (j = 0; j < n_clobbers; j++) | |
1ccbefce | 2208 | if (operands_match_p (clobber_reg[j], recog_data.operand[i])) |
114cbee6 RS |
2209 | break; |
2210 | ||
f62a15e3 | 2211 | if (j < n_clobbers || recog_op_alt[i][alt].matches >= 0) |
114cbee6 | 2212 | { |
1ccbefce RH |
2213 | /* recog_data.operand[i] might not be at the top of stack. |
2214 | But that's OK, because all we need to do is pop the | |
2215 | right number of regs off of the top of the reg-stack. | |
2216 | record_asm_stack_regs guaranteed that all implicitly | |
2217 | popped regs were grouped at the top of the reg-stack. */ | |
114cbee6 RS |
2218 | |
2219 | CLEAR_HARD_REG_BIT (regstack->reg_set, | |
2220 | regstack->reg[regstack->top]); | |
2221 | regstack->top--; | |
2222 | } | |
2223 | } | |
2224 | ||
2225 | /* Now add to REGSTACK any outputs that the asm implicitly pushed. | |
2226 | Note that there isn't any need to substitute register numbers. | |
0f41302f | 2227 | ??? Explain why this is true. */ |
114cbee6 RS |
2228 | |
2229 | for (i = LAST_STACK_REG; i >= FIRST_STACK_REG; i--) | |
2230 | { | |
2231 | /* See if there is an output for this hard reg. */ | |
2232 | int j; | |
2233 | ||
2234 | for (j = 0; j < n_outputs; j++) | |
1ccbefce | 2235 | if (STACK_REG_P (recog_data.operand[j]) |
ae0ed63a | 2236 | && REGNO (recog_data.operand[j]) == (unsigned) i) |
114cbee6 RS |
2237 | { |
2238 | regstack->reg[++regstack->top] = i; | |
2239 | SET_HARD_REG_BIT (regstack->reg_set, i); | |
2240 | break; | |
2241 | } | |
2242 | } | |
2243 | ||
2244 | /* Now emit a pop insn for any REG_UNUSED output, or any REG_DEAD | |
2245 | input that the asm didn't implicitly pop. If the asm didn't | |
3f5cfed6 | 2246 | implicitly pop an input reg, that reg will still be live. |
114cbee6 RS |
2247 | |
2248 | Note that we can't use find_regno_note here: the register numbers | |
2249 | in the death notes have already been substituted. */ | |
2250 | ||
3f5cfed6 | 2251 | for (i = 0; i < n_outputs; i++) |
1ccbefce | 2252 | if (STACK_REG_P (recog_data.operand[i])) |
3f5cfed6 JVA |
2253 | { |
2254 | int j; | |
2255 | ||
2256 | for (j = 0; j < n_notes; j++) | |
1ccbefce | 2257 | if (REGNO (recog_data.operand[i]) == REGNO (note_reg[j]) |
3f5cfed6 JVA |
2258 | && note_kind[j] == REG_UNUSED) |
2259 | { | |
1ccbefce | 2260 | insn = emit_pop_insn (insn, regstack, recog_data.operand[i], |
a05924f9 | 2261 | EMIT_AFTER); |
3f5cfed6 JVA |
2262 | break; |
2263 | } | |
2264 | } | |
2265 | ||
f62a15e3 | 2266 | for (i = n_outputs; i < n_outputs + n_inputs; i++) |
1ccbefce | 2267 | if (STACK_REG_P (recog_data.operand[i])) |
114cbee6 RS |
2268 | { |
2269 | int j; | |
2270 | ||
2271 | for (j = 0; j < n_notes; j++) | |
1ccbefce | 2272 | if (REGNO (recog_data.operand[i]) == REGNO (note_reg[j]) |
3f5cfed6 | 2273 | && note_kind[j] == REG_DEAD |
f62a15e3 | 2274 | && TEST_HARD_REG_BIT (regstack->reg_set, |
1ccbefce | 2275 | REGNO (recog_data.operand[i]))) |
114cbee6 | 2276 | { |
1ccbefce | 2277 | insn = emit_pop_insn (insn, regstack, recog_data.operand[i], |
a05924f9 | 2278 | EMIT_AFTER); |
114cbee6 RS |
2279 | break; |
2280 | } | |
2281 | } | |
2282 | } | |
2283 | \f | |
48227150 JVA |
2284 | /* Substitute stack hard reg numbers for stack virtual registers in |
2285 | INSN. Non-stack register numbers are not changed. REGSTACK is the | |
2286 | current stack content. Insns may be emitted as needed to arrange the | |
ecb63641 EB |
2287 | stack for the 387 based on the contents of the insn. Return whether |
2288 | a control flow insn was deleted in the process. */ | |
f37eb5cb | 2289 | |
ecb63641 | 2290 | static bool |
0823efed | 2291 | subst_stack_regs (rtx insn, stack_ptr regstack) |
48227150 | 2292 | { |
b3694847 | 2293 | rtx *note_link, note; |
ecb63641 | 2294 | bool control_flow_insn_deleted = false; |
b3694847 | 2295 | int i; |
48227150 | 2296 | |
4b4bf941 | 2297 | if (CALL_P (insn)) |
e075ae69 RH |
2298 | { |
2299 | int top = regstack->top; | |
48227150 | 2300 | |
e075ae69 RH |
2301 | /* If there are any floating point parameters to be passed in |
2302 | registers for this call, make sure they are in the right | |
2303 | order. */ | |
48227150 | 2304 | |
e075ae69 RH |
2305 | if (top >= 0) |
2306 | { | |
385e0e08 | 2307 | straighten_stack (insn, regstack); |
99a59310 | 2308 | |
e075ae69 | 2309 | /* Now mark the arguments as dead after the call. */ |
99a59310 | 2310 | |
e075ae69 RH |
2311 | while (regstack->top >= 0) |
2312 | { | |
2313 | CLEAR_HARD_REG_BIT (regstack->reg_set, FIRST_STACK_REG + regstack->top); | |
2314 | regstack->top--; | |
2315 | } | |
2316 | } | |
2317 | } | |
48227150 JVA |
2318 | |
2319 | /* Do the actual substitution if any stack regs are mentioned. | |
2320 | Since we only record whether entire insn mentions stack regs, and | |
2321 | subst_stack_regs_pat only works for patterns that contain stack regs, | |
2322 | we must check each pattern in a parallel here. A call_value_pop could | |
0f41302f | 2323 | fail otherwise. */ |
48227150 | 2324 | |
21b2cd73 | 2325 | if (stack_regs_mentioned (insn)) |
48227150 | 2326 | { |
f62a15e3 | 2327 | int n_operands = asm_noperands (PATTERN (insn)); |
114cbee6 RS |
2328 | if (n_operands >= 0) |
2329 | { | |
2330 | /* This insn is an `asm' with operands. Decode the operands, | |
2331 | decide how many are inputs, and do register substitution. | |
0f41302f | 2332 | Any REG_UNUSED notes will be handled by subst_asm_stack_regs. */ |
114cbee6 | 2333 | |
f62a15e3 | 2334 | subst_asm_stack_regs (insn, regstack); |
ecb63641 | 2335 | return control_flow_insn_deleted; |
114cbee6 RS |
2336 | } |
2337 | ||
48227150 | 2338 | if (GET_CODE (PATTERN (insn)) == PARALLEL) |
c166a311 | 2339 | for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++) |
48227150 JVA |
2340 | { |
2341 | if (stack_regs_mentioned_p (XVECEXP (PATTERN (insn), 0, i))) | |
736b64dd JH |
2342 | { |
2343 | if (GET_CODE (XVECEXP (PATTERN (insn), 0, i)) == CLOBBER) | |
2344 | XVECEXP (PATTERN (insn), 0, i) | |
2345 | = shallow_copy_rtx (XVECEXP (PATTERN (insn), 0, i)); | |
2346 | control_flow_insn_deleted | |
2347 | |= subst_stack_regs_pat (insn, regstack, | |
2348 | XVECEXP (PATTERN (insn), 0, i)); | |
2349 | } | |
48227150 JVA |
2350 | } |
2351 | else | |
ecb63641 EB |
2352 | control_flow_insn_deleted |
2353 | |= subst_stack_regs_pat (insn, regstack, PATTERN (insn)); | |
48227150 JVA |
2354 | } |
2355 | ||
2356 | /* subst_stack_regs_pat may have deleted a no-op insn. If so, any | |
0f41302f | 2357 | REG_UNUSED will already have been dealt with, so just return. */ |
48227150 | 2358 | |
4b4bf941 | 2359 | if (NOTE_P (insn) || INSN_DELETED_P (insn)) |
ecb63641 | 2360 | return control_flow_insn_deleted; |
48227150 | 2361 | |
2d0df1f9 RS |
2362 | /* If this a noreturn call, we can't insert pop insns after it. |
2363 | Instead, reset the stack state to empty. */ | |
2364 | if (CALL_P (insn) | |
2365 | && find_reg_note (insn, REG_NORETURN, NULL)) | |
2366 | { | |
2367 | regstack->top = -1; | |
2368 | CLEAR_HARD_REG_SET (regstack->reg_set); | |
2369 | return control_flow_insn_deleted; | |
2370 | } | |
2371 | ||
48227150 JVA |
2372 | /* If there is a REG_UNUSED note on a stack register on this insn, |
2373 | the indicated reg must be popped. The REG_UNUSED note is removed, | |
2374 | since the form of the newly emitted pop insn references the reg, | |
0f41302f | 2375 | making it no longer `unset'. */ |
48227150 | 2376 | |
8e2e89f7 | 2377 | note_link = ®_NOTES (insn); |
48227150 JVA |
2378 | for (note = *note_link; note; note = XEXP (note, 1)) |
2379 | if (REG_NOTE_KIND (note) == REG_UNUSED && STACK_REG_P (XEXP (note, 0))) | |
2380 | { | |
2381 | *note_link = XEXP (note, 1); | |
a05924f9 | 2382 | insn = emit_pop_insn (insn, regstack, XEXP (note, 0), EMIT_AFTER); |
48227150 JVA |
2383 | } |
2384 | else | |
2385 | note_link = &XEXP (note, 1); | |
ecb63641 EB |
2386 | |
2387 | return control_flow_insn_deleted; | |
48227150 JVA |
2388 | } |
2389 | \f | |
2390 | /* Change the organization of the stack so that it fits a new basic | |
2391 | block. Some registers might have to be popped, but there can never be | |
2392 | a register live in the new block that is not now live. | |
2393 | ||
a05924f9 JH |
2394 | Insert any needed insns before or after INSN, as indicated by |
2395 | WHERE. OLD is the original stack layout, and NEW is the desired | |
454ff5cb | 2396 | form. OLD is updated to reflect the code emitted, i.e., it will be |
a05924f9 | 2397 | the same as NEW upon return. |
48227150 JVA |
2398 | |
2399 | This function will not preserve block_end[]. But that information | |
0f41302f | 2400 | is no longer needed once this has executed. */ |
48227150 JVA |
2401 | |
2402 | static void | |
0823efed | 2403 | change_stack (rtx insn, stack_ptr old, stack_ptr new_stack, enum emit_where where) |
48227150 JVA |
2404 | { |
2405 | int reg; | |
a05924f9 | 2406 | int update_end = 0; |
6fb5fa3c | 2407 | int i; |
48227150 | 2408 | |
385e0e08 RS |
2409 | /* Stack adjustments for the first insn in a block update the |
2410 | current_block's stack_in instead of inserting insns directly. | |
2411 | compensate_edges will add the necessary code later. */ | |
2412 | if (current_block | |
2413 | && starting_stack_p | |
2414 | && where == EMIT_BEFORE) | |
2415 | { | |
d858f359 | 2416 | BLOCK_INFO (current_block)->stack_in = *new_stack; |
385e0e08 | 2417 | starting_stack_p = false; |
d858f359 | 2418 | *old = *new_stack; |
385e0e08 RS |
2419 | return; |
2420 | } | |
2421 | ||
a05924f9 JH |
2422 | /* We will be inserting new insns "backwards". If we are to insert |
2423 | after INSN, find the next insn, and insert before it. */ | |
48227150 | 2424 | |
a05924f9 JH |
2425 | if (where == EMIT_AFTER) |
2426 | { | |
a813c111 | 2427 | if (current_block && BB_END (current_block) == insn) |
a05924f9 JH |
2428 | update_end = 1; |
2429 | insn = NEXT_INSN (insn); | |
2430 | } | |
48227150 | 2431 | |
6fb5fa3c DB |
2432 | /* Initialize partially dead variables. */ |
2433 | for (i = FIRST_STACK_REG; i < LAST_STACK_REG + 1; i++) | |
d858f359 | 2434 | if (TEST_HARD_REG_BIT (new_stack->reg_set, i) |
6fb5fa3c DB |
2435 | && !TEST_HARD_REG_BIT (old->reg_set, i)) |
2436 | { | |
2437 | old->reg[++old->top] = i; | |
2438 | SET_HARD_REG_BIT (old->reg_set, i); | |
2439 | emit_insn_before (gen_rtx_SET (VOIDmode, | |
2440 | FP_MODE_REG (i, SFmode), not_a_num), insn); | |
2441 | } | |
2442 | ||
0f41302f | 2443 | /* Pop any registers that are not needed in the new block. */ |
48227150 | 2444 | |
0cc5dec1 RS |
2445 | /* If the destination block's stack already has a specified layout |
2446 | and contains two or more registers, use a more intelligent algorithm | |
2447 | to pop registers that minimizes the number number of fxchs below. */ | |
d858f359 | 2448 | if (new_stack->top > 0) |
0cc5dec1 RS |
2449 | { |
2450 | bool slots[REG_STACK_SIZE]; | |
2451 | int pops[REG_STACK_SIZE]; | |
00fc055e | 2452 | int next, dest, topsrc; |
0cc5dec1 RS |
2453 | |
2454 | /* First pass to determine the free slots. */ | |
d858f359 KG |
2455 | for (reg = 0; reg <= new_stack->top; reg++) |
2456 | slots[reg] = TEST_HARD_REG_BIT (new_stack->reg_set, old->reg[reg]); | |
0cc5dec1 RS |
2457 | |
2458 | /* Second pass to allocate preferred slots. */ | |
00fc055e | 2459 | topsrc = -1; |
d858f359 KG |
2460 | for (reg = old->top; reg > new_stack->top; reg--) |
2461 | if (TEST_HARD_REG_BIT (new_stack->reg_set, old->reg[reg])) | |
0cc5dec1 RS |
2462 | { |
2463 | dest = -1; | |
d858f359 KG |
2464 | for (next = 0; next <= new_stack->top; next++) |
2465 | if (!slots[next] && new_stack->reg[next] == old->reg[reg]) | |
0cc5dec1 | 2466 | { |
00fc055e RS |
2467 | /* If this is a preference for the new top of stack, record |
2468 | the fact by remembering it's old->reg in topsrc. */ | |
d858f359 | 2469 | if (next == new_stack->top) |
00fc055e | 2470 | topsrc = reg; |
0cc5dec1 RS |
2471 | slots[next] = true; |
2472 | dest = next; | |
2473 | break; | |
2474 | } | |
2475 | pops[reg] = dest; | |
2476 | } | |
2477 | else | |
2478 | pops[reg] = reg; | |
2479 | ||
00fc055e RS |
2480 | /* Intentionally, avoid placing the top of stack in it's correct |
2481 | location, if we still need to permute the stack below and we | |
2482 | can usefully place it somewhere else. This is the case if any | |
2483 | slot is still unallocated, in which case we should place the | |
2484 | top of stack there. */ | |
2485 | if (topsrc != -1) | |
d858f359 | 2486 | for (reg = 0; reg < new_stack->top; reg++) |
00fc055e RS |
2487 | if (!slots[reg]) |
2488 | { | |
2489 | pops[topsrc] = reg; | |
d858f359 | 2490 | slots[new_stack->top] = false; |
00fc055e RS |
2491 | slots[reg] = true; |
2492 | break; | |
2493 | } | |
2494 | ||
0cc5dec1 | 2495 | /* Third pass allocates remaining slots and emits pop insns. */ |
d858f359 KG |
2496 | next = new_stack->top; |
2497 | for (reg = old->top; reg > new_stack->top; reg--) | |
0cc5dec1 RS |
2498 | { |
2499 | dest = pops[reg]; | |
2500 | if (dest == -1) | |
2501 | { | |
2502 | /* Find next free slot. */ | |
2503 | while (slots[next]) | |
00fc055e RS |
2504 | next--; |
2505 | dest = next--; | |
0cc5dec1 RS |
2506 | } |
2507 | emit_pop_insn (insn, old, FP_MODE_REG (old->reg[dest], DFmode), | |
2508 | EMIT_BEFORE); | |
2509 | } | |
2510 | } | |
2511 | else | |
00fc055e RS |
2512 | { |
2513 | /* The following loop attempts to maximize the number of times we | |
2514 | pop the top of the stack, as this permits the use of the faster | |
2515 | ffreep instruction on platforms that support it. */ | |
2516 | int live, next; | |
2517 | ||
2518 | live = 0; | |
2519 | for (reg = 0; reg <= old->top; reg++) | |
d858f359 | 2520 | if (TEST_HARD_REG_BIT (new_stack->reg_set, old->reg[reg])) |
00fc055e RS |
2521 | live++; |
2522 | ||
2523 | next = live; | |
2524 | while (old->top >= live) | |
d858f359 | 2525 | if (TEST_HARD_REG_BIT (new_stack->reg_set, old->reg[old->top])) |
00fc055e | 2526 | { |
d858f359 | 2527 | while (TEST_HARD_REG_BIT (new_stack->reg_set, old->reg[next])) |
00fc055e RS |
2528 | next--; |
2529 | emit_pop_insn (insn, old, FP_MODE_REG (old->reg[next], DFmode), | |
0cc5dec1 | 2530 | EMIT_BEFORE); |
00fc055e RS |
2531 | } |
2532 | else | |
2533 | emit_pop_insn (insn, old, FP_MODE_REG (old->reg[old->top], DFmode), | |
0cc5dec1 | 2534 | EMIT_BEFORE); |
00fc055e | 2535 | } |
48227150 | 2536 | |
d858f359 | 2537 | if (new_stack->top == -2) |
48227150 JVA |
2538 | { |
2539 | /* If the new block has never been processed, then it can inherit | |
0f41302f | 2540 | the old stack order. */ |
48227150 | 2541 | |
d858f359 KG |
2542 | new_stack->top = old->top; |
2543 | memcpy (new_stack->reg, old->reg, sizeof (new_stack->reg)); | |
48227150 JVA |
2544 | } |
2545 | else | |
2546 | { | |
2547 | /* This block has been entered before, and we must match the | |
0f41302f | 2548 | previously selected stack order. */ |
48227150 JVA |
2549 | |
2550 | /* By now, the only difference should be the order of the stack, | |
0f41302f | 2551 | not their depth or liveliness. */ |
48227150 | 2552 | |
d858f359 KG |
2553 | gcc_assert (hard_reg_set_equal_p (old->reg_set, new_stack->reg_set)); |
2554 | gcc_assert (old->top == new_stack->top); | |
48227150 | 2555 | |
d858f359 | 2556 | /* If the stack is not empty (new_stack->top != -1), loop here emitting |
a6a2274a | 2557 | swaps until the stack is correct. |
80832cf2 HB |
2558 | |
2559 | The worst case number of swaps emitted is N + 2, where N is the | |
48227150 JVA |
2560 | depth of the stack. In some cases, the reg at the top of |
2561 | stack may be correct, but swapped anyway in order to fix | |
2562 | other regs. But since we never swap any other reg away from | |
0f41302f | 2563 | its correct slot, this algorithm will converge. */ |
48227150 | 2564 | |
d858f359 | 2565 | if (new_stack->top != -1) |
80832cf2 HB |
2566 | do |
2567 | { | |
2568 | /* Swap the reg at top of stack into the position it is | |
2569 | supposed to be in, until the correct top of stack appears. */ | |
48227150 | 2570 | |
d858f359 | 2571 | while (old->reg[old->top] != new_stack->reg[new_stack->top]) |
80832cf2 | 2572 | { |
d858f359 KG |
2573 | for (reg = new_stack->top; reg >= 0; reg--) |
2574 | if (new_stack->reg[reg] == old->reg[old->top]) | |
80832cf2 | 2575 | break; |
48227150 | 2576 | |
41374e13 | 2577 | gcc_assert (reg != -1); |
48227150 | 2578 | |
80832cf2 HB |
2579 | emit_swap_insn (insn, old, |
2580 | FP_MODE_REG (old->reg[reg], DFmode)); | |
2581 | } | |
48227150 | 2582 | |
80832cf2 | 2583 | /* See if any regs remain incorrect. If so, bring an |
48227150 | 2584 | incorrect reg to the top of stack, and let the while loop |
0f41302f | 2585 | above fix it. */ |
48227150 | 2586 | |
d858f359 KG |
2587 | for (reg = new_stack->top; reg >= 0; reg--) |
2588 | if (new_stack->reg[reg] != old->reg[reg]) | |
80832cf2 HB |
2589 | { |
2590 | emit_swap_insn (insn, old, | |
2591 | FP_MODE_REG (old->reg[reg], DFmode)); | |
2592 | break; | |
2593 | } | |
2594 | } while (reg >= 0); | |
48227150 | 2595 | |
0f41302f | 2596 | /* At this point there must be no differences. */ |
48227150 JVA |
2597 | |
2598 | for (reg = old->top; reg >= 0; reg--) | |
d858f359 | 2599 | gcc_assert (old->reg[reg] == new_stack->reg[reg]); |
48227150 | 2600 | } |
a05924f9 JH |
2601 | |
2602 | if (update_end) | |
a813c111 | 2603 | BB_END (current_block) = PREV_INSN (insn); |
48227150 JVA |
2604 | } |
2605 | \f | |
a05924f9 | 2606 | /* Print stack configuration. */ |
48227150 JVA |
2607 | |
2608 | static void | |
0823efed | 2609 | print_stack (FILE *file, stack_ptr s) |
48227150 | 2610 | { |
a05924f9 JH |
2611 | if (! file) |
2612 | return; | |
48227150 | 2613 | |
a05924f9 JH |
2614 | if (s->top == -2) |
2615 | fprintf (file, "uninitialized\n"); | |
2616 | else if (s->top == -1) | |
2617 | fprintf (file, "empty\n"); | |
2618 | else | |
e075ae69 | 2619 | { |
a05924f9 JH |
2620 | int i; |
2621 | fputs ("[ ", file); | |
2622 | for (i = 0; i <= s->top; ++i) | |
2623 | fprintf (file, "%d ", s->reg[i]); | |
2624 | fputs ("]\n", file); | |
e075ae69 | 2625 | } |
a05924f9 JH |
2626 | } |
2627 | \f | |
2628 | /* This function was doing life analysis. We now let the regular live | |
a6a2274a | 2629 | code do it's job, so we only need to check some extra invariants |
a05924f9 JH |
2630 | that reg-stack expects. Primary among these being that all registers |
2631 | are initialized before use. | |
48227150 | 2632 | |
a05924f9 JH |
2633 | The function returns true when code was emitted to CFG edges and |
2634 | commit_edge_insertions needs to be called. */ | |
48227150 | 2635 | |
a05924f9 | 2636 | static int |
0c20a65f | 2637 | convert_regs_entry (void) |
a05924f9 | 2638 | { |
e0082a72 | 2639 | int inserted = 0; |
a05924f9 | 2640 | edge e; |
628f6a4e | 2641 | edge_iterator ei; |
48227150 | 2642 | |
fa283935 | 2643 | /* Load something into each stack register live at function entry. |
a05924f9 | 2644 | Such live registers can be caused by uninitialized variables or |
a6a2274a | 2645 | functions not returning values on all paths. In order to keep |
a05924f9 | 2646 | the push/pop code happy, and to not scrog the register stack, we |
a6a2274a | 2647 | must put something in these registers. Use a QNaN. |
48227150 | 2648 | |
d55d8fc7 | 2649 | Note that we are inserting converted code here. This code is |
a05924f9 | 2650 | never seen by the convert_regs pass. */ |
48227150 | 2651 | |
fefa31b5 | 2652 | FOR_EACH_EDGE (e, ei, ENTRY_BLOCK_PTR_FOR_FN (cfun)->succs) |
a05924f9 JH |
2653 | { |
2654 | basic_block block = e->dest; | |
2655 | block_info bi = BLOCK_INFO (block); | |
2656 | int reg, top = -1; | |
48227150 | 2657 | |
a05924f9 | 2658 | for (reg = LAST_STACK_REG; reg >= FIRST_STACK_REG; --reg) |
fa283935 | 2659 | if (TEST_HARD_REG_BIT (bi->stack_in.reg_set, reg)) |
a05924f9 JH |
2660 | { |
2661 | rtx init; | |
48227150 | 2662 | |
a05924f9 | 2663 | bi->stack_in.reg[++top] = reg; |
48227150 | 2664 | |
a05924f9 JH |
2665 | init = gen_rtx_SET (VOIDmode, |
2666 | FP_MODE_REG (FIRST_STACK_REG, SFmode), | |
d2032ad8 | 2667 | not_a_num); |
a05924f9 JH |
2668 | insert_insn_on_edge (init, e); |
2669 | inserted = 1; | |
2670 | } | |
48227150 | 2671 | |
a05924f9 JH |
2672 | bi->stack_in.top = top; |
2673 | } | |
48227150 | 2674 | |
a05924f9 JH |
2675 | return inserted; |
2676 | } | |
48227150 | 2677 | |
a05924f9 JH |
2678 | /* Construct the desired stack for function exit. This will either |
2679 | be `empty', or the function return value at top-of-stack. */ | |
48227150 | 2680 | |
a05924f9 | 2681 | static void |
0c20a65f | 2682 | convert_regs_exit (void) |
a05924f9 JH |
2683 | { |
2684 | int value_reg_low, value_reg_high; | |
0823efed | 2685 | stack_ptr output_stack; |
a05924f9 | 2686 | rtx retvalue; |
48227150 | 2687 | |
a05924f9 JH |
2688 | retvalue = stack_result (current_function_decl); |
2689 | value_reg_low = value_reg_high = -1; | |
2690 | if (retvalue) | |
2691 | { | |
2692 | value_reg_low = REGNO (retvalue); | |
09e18274 | 2693 | value_reg_high = END_HARD_REGNO (retvalue) - 1; |
a05924f9 | 2694 | } |
48227150 | 2695 | |
fefa31b5 | 2696 | output_stack = &BLOCK_INFO (EXIT_BLOCK_PTR_FOR_FN (cfun))->stack_in; |
a05924f9 JH |
2697 | if (value_reg_low == -1) |
2698 | output_stack->top = -1; | |
2699 | else | |
2700 | { | |
2701 | int reg; | |
48227150 | 2702 | |
a05924f9 JH |
2703 | output_stack->top = value_reg_high - value_reg_low; |
2704 | for (reg = value_reg_low; reg <= value_reg_high; ++reg) | |
2705 | { | |
bc9c2952 | 2706 | output_stack->reg[value_reg_high - reg] = reg; |
a05924f9 JH |
2707 | SET_HARD_REG_BIT (output_stack->reg_set, reg); |
2708 | } | |
2709 | } | |
48227150 | 2710 | } |
48227150 | 2711 | |
0ac2a27a RS |
2712 | /* Copy the stack info from the end of edge E's source block to the |
2713 | start of E's destination block. */ | |
1c320f82 RS |
2714 | |
2715 | static void | |
2716 | propagate_stack (edge e) | |
2717 | { | |
0823efed DN |
2718 | stack_ptr src_stack = &BLOCK_INFO (e->src)->stack_out; |
2719 | stack_ptr dest_stack = &BLOCK_INFO (e->dest)->stack_in; | |
0ac2a27a | 2720 | int reg; |
1c320f82 | 2721 | |
0ac2a27a RS |
2722 | /* Preserve the order of the original stack, but check whether |
2723 | any pops are needed. */ | |
2724 | dest_stack->top = -1; | |
2725 | for (reg = 0; reg <= src_stack->top; ++reg) | |
2726 | if (TEST_HARD_REG_BIT (dest_stack->reg_set, src_stack->reg[reg])) | |
2727 | dest_stack->reg[++dest_stack->top] = src_stack->reg[reg]; | |
6fb5fa3c DB |
2728 | |
2729 | /* Push in any partially dead values. */ | |
2730 | for (reg = FIRST_STACK_REG; reg < LAST_STACK_REG + 1; reg++) | |
2731 | if (TEST_HARD_REG_BIT (dest_stack->reg_set, reg) | |
2732 | && !TEST_HARD_REG_BIT (src_stack->reg_set, reg)) | |
2733 | dest_stack->reg[++dest_stack->top] = reg; | |
1c320f82 RS |
2734 | } |
2735 | ||
2736 | ||
2737 | /* Adjust the stack of edge E's source block on exit to match the stack | |
2738 | of it's target block upon input. The stack layouts of both blocks | |
2739 | should have been defined by now. */ | |
2740 | ||
0ecf09f9 | 2741 | static bool |
10d22567 | 2742 | compensate_edge (edge e) |
0ecf09f9 | 2743 | { |
579e4a82 | 2744 | basic_block source = e->src, target = e->dest; |
0823efed DN |
2745 | stack_ptr target_stack = &BLOCK_INFO (target)->stack_in; |
2746 | stack_ptr source_stack = &BLOCK_INFO (source)->stack_out; | |
579e4a82 | 2747 | struct stack_def regstack; |
0ecf09f9 JH |
2748 | int reg; |
2749 | ||
10d22567 ZD |
2750 | if (dump_file) |
2751 | fprintf (dump_file, "Edge %d->%d: ", source->index, target->index); | |
0ecf09f9 | 2752 | |
1c320f82 RS |
2753 | gcc_assert (target_stack->top != -2); |
2754 | ||
2755 | /* Check whether stacks are identical. */ | |
579e4a82 | 2756 | if (target_stack->top == source_stack->top) |
0ecf09f9 | 2757 | { |
1c320f82 | 2758 | for (reg = target_stack->top; reg >= 0; --reg) |
579e4a82 | 2759 | if (target_stack->reg[reg] != source_stack->reg[reg]) |
0ecf09f9 JH |
2760 | break; |
2761 | ||
2762 | if (reg == -1) | |
2763 | { | |
10d22567 ZD |
2764 | if (dump_file) |
2765 | fprintf (dump_file, "no changes needed\n"); | |
a6a2274a | 2766 | return false; |
0ecf09f9 | 2767 | } |
0ecf09f9 | 2768 | } |
0ecf09f9 | 2769 | |
10d22567 | 2770 | if (dump_file) |
1c320f82 | 2771 | { |
10d22567 ZD |
2772 | fprintf (dump_file, "correcting stack to "); |
2773 | print_stack (dump_file, target_stack); | |
0ecf09f9 JH |
2774 | } |
2775 | ||
579e4a82 | 2776 | /* Abnormal calls may appear to have values live in st(0), but the |
0ecf09f9 | 2777 | abnormal return path will not have actually loaded the values. */ |
579e4a82 | 2778 | if (e->flags & EDGE_ABNORMAL_CALL) |
0ecf09f9 JH |
2779 | { |
2780 | /* Assert that the lifetimes are as we expect -- one value | |
2781 | live at st(0) on the end of the source block, and no | |
6f7e2c0c RS |
2782 | values live at the beginning of the destination block. |
2783 | For complex return values, we may have st(1) live as well. */ | |
2784 | gcc_assert (source_stack->top == 0 || source_stack->top == 1); | |
579e4a82 RS |
2785 | gcc_assert (target_stack->top == -1); |
2786 | return false; | |
2787 | } | |
0ecf09f9 | 2788 | |
579e4a82 RS |
2789 | /* Handle non-call EH edges specially. The normal return path have |
2790 | values in registers. These will be popped en masse by the unwind | |
2791 | library. */ | |
2792 | if (e->flags & EDGE_EH) | |
2793 | { | |
2794 | gcc_assert (target_stack->top == -1); | |
2795 | return false; | |
0ecf09f9 JH |
2796 | } |
2797 | ||
579e4a82 RS |
2798 | /* We don't support abnormal edges. Global takes care to |
2799 | avoid any live register across them, so we should never | |
2800 | have to insert instructions on such edges. */ | |
2801 | gcc_assert (! (e->flags & EDGE_ABNORMAL)); | |
2802 | ||
2803 | /* Make a copy of source_stack as change_stack is destructive. */ | |
2804 | regstack = *source_stack; | |
2805 | ||
0ecf09f9 JH |
2806 | /* It is better to output directly to the end of the block |
2807 | instead of to the edge, because emit_swap can do minimal | |
2808 | insn scheduling. We can do this when there is only one | |
2809 | edge out, and it is not abnormal. */ | |
579e4a82 | 2810 | if (EDGE_COUNT (source->succs) == 1) |
0ecf09f9 | 2811 | { |
579e4a82 RS |
2812 | current_block = source; |
2813 | change_stack (BB_END (source), ®stack, target_stack, | |
2814 | (JUMP_P (BB_END (source)) ? EMIT_BEFORE : EMIT_AFTER)); | |
0ecf09f9 JH |
2815 | } |
2816 | else | |
2817 | { | |
2818 | rtx seq, after; | |
2819 | ||
0ecf09f9 JH |
2820 | current_block = NULL; |
2821 | start_sequence (); | |
2822 | ||
2f937369 | 2823 | /* ??? change_stack needs some point to emit insns after. */ |
2e040219 | 2824 | after = emit_note (NOTE_INSN_DELETED); |
0ecf09f9 | 2825 | |
579e4a82 | 2826 | change_stack (after, ®stack, target_stack, EMIT_BEFORE); |
0ecf09f9 | 2827 | |
2f937369 | 2828 | seq = get_insns (); |
0ecf09f9 JH |
2829 | end_sequence (); |
2830 | ||
2831 | insert_insn_on_edge (seq, e); | |
2832 | return true; | |
2833 | } | |
2834 | return false; | |
2835 | } | |
2836 | ||
1c320f82 RS |
2837 | /* Traverse all non-entry edges in the CFG, and emit the necessary |
2838 | edge compensation code to change the stack from stack_out of the | |
2839 | source block to the stack_in of the destination block. */ | |
2840 | ||
2841 | static bool | |
10d22567 | 2842 | compensate_edges (void) |
1c320f82 RS |
2843 | { |
2844 | bool inserted = false; | |
2845 | basic_block bb; | |
2846 | ||
385e0e08 RS |
2847 | starting_stack_p = false; |
2848 | ||
11cd3bed | 2849 | FOR_EACH_BB_FN (bb, cfun) |
fefa31b5 | 2850 | if (bb != ENTRY_BLOCK_PTR_FOR_FN (cfun)) |
1c320f82 RS |
2851 | { |
2852 | edge e; | |
2853 | edge_iterator ei; | |
2854 | ||
2855 | FOR_EACH_EDGE (e, ei, bb->succs) | |
10d22567 | 2856 | inserted |= compensate_edge (e); |
1c320f82 RS |
2857 | } |
2858 | return inserted; | |
2859 | } | |
2860 | ||
0ac2a27a RS |
2861 | /* Select the better of two edges E1 and E2 to use to determine the |
2862 | stack layout for their shared destination basic block. This is | |
2863 | typically the more frequently executed. The edge E1 may be NULL | |
2864 | (in which case E2 is returned), but E2 is always non-NULL. */ | |
2865 | ||
2866 | static edge | |
2867 | better_edge (edge e1, edge e2) | |
2868 | { | |
2869 | if (!e1) | |
2870 | return e2; | |
2871 | ||
2872 | if (EDGE_FREQUENCY (e1) > EDGE_FREQUENCY (e2)) | |
2873 | return e1; | |
2874 | if (EDGE_FREQUENCY (e1) < EDGE_FREQUENCY (e2)) | |
2875 | return e2; | |
2876 | ||
2877 | if (e1->count > e2->count) | |
2878 | return e1; | |
2879 | if (e1->count < e2->count) | |
2880 | return e2; | |
2881 | ||
2882 | /* Prefer critical edges to minimize inserting compensation code on | |
2883 | critical edges. */ | |
2884 | ||
2885 | if (EDGE_CRITICAL_P (e1) != EDGE_CRITICAL_P (e2)) | |
2886 | return EDGE_CRITICAL_P (e1) ? e1 : e2; | |
2887 | ||
a4d05547 | 2888 | /* Avoid non-deterministic behavior. */ |
0ac2a27a RS |
2889 | return (e1->src->index < e2->src->index) ? e1 : e2; |
2890 | } | |
2891 | ||
12929514 EB |
2892 | /* Convert stack register references in one block. Return true if the CFG |
2893 | has been modified in the process. */ | |
a05924f9 | 2894 | |
12929514 | 2895 | static bool |
10d22567 | 2896 | convert_regs_1 (basic_block block) |
48227150 | 2897 | { |
0ecf09f9 | 2898 | struct stack_def regstack; |
a05924f9 | 2899 | block_info bi = BLOCK_INFO (block); |
1c320f82 | 2900 | int reg; |
a05924f9 | 2901 | rtx insn, next; |
ecb63641 | 2902 | bool control_flow_insn_deleted = false; |
12929514 | 2903 | bool cfg_altered = false; |
b5b8b0ac | 2904 | int debug_insns_with_starting_stack = 0; |
48227150 | 2905 | |
d6fc0492 | 2906 | any_malformed_asm = false; |
0ecf09f9 | 2907 | |
0ac2a27a | 2908 | /* Choose an initial stack layout, if one hasn't already been chosen. */ |
0ecf09f9 | 2909 | if (bi->stack_in.top == -2) |
b3cd99cd | 2910 | { |
0ac2a27a RS |
2911 | edge e, beste = NULL; |
2912 | edge_iterator ei; | |
2913 | ||
2914 | /* Select the best incoming edge (typically the most frequent) to | |
2915 | use as a template for this basic block. */ | |
2916 | FOR_EACH_EDGE (e, ei, block->preds) | |
2917 | if (BLOCK_INFO (e->src)->done) | |
2918 | beste = better_edge (beste, e); | |
2919 | ||
b3cd99cd | 2920 | if (beste) |
1c320f82 | 2921 | propagate_stack (beste); |
b3cd99cd EB |
2922 | else |
2923 | { | |
2924 | /* No predecessors. Create an arbitrary input stack. */ | |
b3cd99cd EB |
2925 | bi->stack_in.top = -1; |
2926 | for (reg = LAST_STACK_REG; reg >= FIRST_STACK_REG; --reg) | |
2927 | if (TEST_HARD_REG_BIT (bi->stack_in.reg_set, reg)) | |
2928 | bi->stack_in.reg[++bi->stack_in.top] = reg; | |
2929 | } | |
2930 | } | |
a6a2274a | 2931 | |
10d22567 | 2932 | if (dump_file) |
48227150 | 2933 | { |
10d22567 ZD |
2934 | fprintf (dump_file, "\nBasic block %d\nInput stack: ", block->index); |
2935 | print_stack (dump_file, &bi->stack_in); | |
a05924f9 | 2936 | } |
48227150 | 2937 | |
a05924f9 JH |
2938 | /* Process all insns in this block. Keep track of NEXT so that we |
2939 | don't process insns emitted while substituting in INSN. */ | |
385e0e08 | 2940 | current_block = block; |
a813c111 | 2941 | next = BB_HEAD (block); |
a05924f9 | 2942 | regstack = bi->stack_in; |
385e0e08 RS |
2943 | starting_stack_p = true; |
2944 | ||
a05924f9 JH |
2945 | do |
2946 | { | |
2947 | insn = next; | |
2948 | next = NEXT_INSN (insn); | |
48227150 | 2949 | |
a05924f9 | 2950 | /* Ensure we have not missed a block boundary. */ |
41374e13 | 2951 | gcc_assert (next); |
a813c111 | 2952 | if (insn == BB_END (block)) |
a05924f9 JH |
2953 | next = NULL; |
2954 | ||
2955 | /* Don't bother processing unless there is a stack reg | |
2956 | mentioned or if it's a CALL_INSN. */ | |
b5b8b0ac AO |
2957 | if (DEBUG_INSN_P (insn)) |
2958 | { | |
2959 | if (starting_stack_p) | |
2960 | debug_insns_with_starting_stack++; | |
2961 | else | |
2962 | { | |
a7a110bb | 2963 | subst_all_stack_regs_in_debug_insn (insn, ®stack); |
b5b8b0ac AO |
2964 | |
2965 | /* Nothing must ever die at a debug insn. If something | |
2966 | is referenced in it that becomes dead, it should have | |
2967 | died before and the reference in the debug insn | |
2968 | should have been removed so as to avoid changing code | |
2969 | generation. */ | |
2970 | gcc_assert (!find_reg_note (insn, REG_DEAD, NULL)); | |
2971 | } | |
2972 | } | |
2973 | else if (stack_regs_mentioned (insn) | |
2974 | || CALL_P (insn)) | |
a05924f9 | 2975 | { |
10d22567 | 2976 | if (dump_file) |
a05924f9 | 2977 | { |
10d22567 | 2978 | fprintf (dump_file, " insn %d input stack: ", |
a05924f9 | 2979 | INSN_UID (insn)); |
10d22567 | 2980 | print_stack (dump_file, ®stack); |
a05924f9 | 2981 | } |
ecb63641 | 2982 | control_flow_insn_deleted |= subst_stack_regs (insn, ®stack); |
385e0e08 | 2983 | starting_stack_p = false; |
48227150 | 2984 | } |
a05924f9 JH |
2985 | } |
2986 | while (next); | |
48227150 | 2987 | |
b5b8b0ac AO |
2988 | if (debug_insns_with_starting_stack) |
2989 | { | |
2990 | /* Since it's the first non-debug instruction that determines | |
2991 | the stack requirements of the current basic block, we refrain | |
2992 | from updating debug insns before it in the loop above, and | |
2993 | fix them up here. */ | |
2994 | for (insn = BB_HEAD (block); debug_insns_with_starting_stack; | |
2995 | insn = NEXT_INSN (insn)) | |
2996 | { | |
2997 | if (!DEBUG_INSN_P (insn)) | |
2998 | continue; | |
2999 | ||
3000 | debug_insns_with_starting_stack--; | |
a7a110bb | 3001 | subst_all_stack_regs_in_debug_insn (insn, &bi->stack_in); |
b5b8b0ac AO |
3002 | } |
3003 | } | |
3004 | ||
10d22567 | 3005 | if (dump_file) |
a05924f9 | 3006 | { |
10d22567 | 3007 | fprintf (dump_file, "Expected live registers ["); |
a05924f9 JH |
3008 | for (reg = FIRST_STACK_REG; reg <= LAST_STACK_REG; ++reg) |
3009 | if (TEST_HARD_REG_BIT (bi->out_reg_set, reg)) | |
10d22567 ZD |
3010 | fprintf (dump_file, " %d", reg); |
3011 | fprintf (dump_file, " ]\nOutput stack: "); | |
3012 | print_stack (dump_file, ®stack); | |
a05924f9 | 3013 | } |
48227150 | 3014 | |
a813c111 | 3015 | insn = BB_END (block); |
4b4bf941 | 3016 | if (JUMP_P (insn)) |
a05924f9 JH |
3017 | insn = PREV_INSN (insn); |
3018 | ||
3019 | /* If the function is declared to return a value, but it returns one | |
3020 | in only some cases, some registers might come live here. Emit | |
3021 | necessary moves for them. */ | |
3022 | ||
3023 | for (reg = FIRST_STACK_REG; reg <= LAST_STACK_REG; ++reg) | |
3024 | { | |
3025 | if (TEST_HARD_REG_BIT (bi->out_reg_set, reg) | |
3026 | && ! TEST_HARD_REG_BIT (regstack.reg_set, reg)) | |
48227150 | 3027 | { |
a05924f9 | 3028 | rtx set; |
48227150 | 3029 | |
10d22567 ZD |
3030 | if (dump_file) |
3031 | fprintf (dump_file, "Emitting insn initializing reg %d\n", reg); | |
48227150 | 3032 | |
5ad85f7d | 3033 | set = gen_rtx_SET (VOIDmode, FP_MODE_REG (reg, SFmode), not_a_num); |
3c030e88 | 3034 | insn = emit_insn_after (set, insn); |
ecb63641 | 3035 | control_flow_insn_deleted |= subst_stack_regs (insn, ®stack); |
a05924f9 JH |
3036 | } |
3037 | } | |
b8698a0f | 3038 | |
de582cfb EB |
3039 | /* Amongst the insns possibly deleted during the substitution process above, |
3040 | might have been the only trapping insn in the block. We purge the now | |
3041 | possibly dead EH edges here to avoid an ICE from fixup_abnormal_edges, | |
3042 | called at the end of convert_regs. The order in which we process the | |
3043 | blocks ensures that we never delete an already processed edge. | |
3044 | ||
ecb63641 EB |
3045 | Note that, at this point, the CFG may have been damaged by the emission |
3046 | of instructions after an abnormal call, which moves the basic block end | |
3047 | (and is the reason why we call fixup_abnormal_edges later). So we must | |
3048 | be sure that the trapping insn has been deleted before trying to purge | |
3049 | dead edges, otherwise we risk purging valid edges. | |
3050 | ||
de582cfb EB |
3051 | ??? We are normally supposed not to delete trapping insns, so we pretend |
3052 | that the insns deleted above don't actually trap. It would have been | |
3053 | better to detect this earlier and avoid creating the EH edge in the first | |
3054 | place, still, but we don't have enough information at that time. */ | |
3055 | ||
ecb63641 | 3056 | if (control_flow_insn_deleted) |
12929514 | 3057 | cfg_altered |= purge_dead_edges (block); |
48227150 | 3058 | |
d6fc0492 RH |
3059 | /* Something failed if the stack lives don't match. If we had malformed |
3060 | asms, we zapped the instruction itself, but that didn't produce the | |
3061 | same pattern of register kills as before. */ | |
b8698a0f | 3062 | |
56b138ae RS |
3063 | gcc_assert (hard_reg_set_equal_p (regstack.reg_set, bi->out_reg_set) |
3064 | || any_malformed_asm); | |
0ecf09f9 | 3065 | bi->stack_out = regstack; |
579e4a82 | 3066 | bi->done = true; |
12929514 EB |
3067 | |
3068 | return cfg_altered; | |
48227150 | 3069 | } |
48227150 | 3070 | |
12929514 EB |
3071 | /* Convert registers in all blocks reachable from BLOCK. Return true if the |
3072 | CFG has been modified in the process. */ | |
a05924f9 | 3073 | |
12929514 | 3074 | static bool |
10d22567 | 3075 | convert_regs_2 (basic_block block) |
48227150 | 3076 | { |
a05924f9 | 3077 | basic_block *stack, *sp; |
12929514 | 3078 | bool cfg_altered = false; |
48227150 | 3079 | |
de582cfb EB |
3080 | /* We process the blocks in a top-down manner, in a way such that one block |
3081 | is only processed after all its predecessors. The number of predecessors | |
b8698a0f | 3082 | of every block has already been computed. */ |
de582cfb | 3083 | |
0cae8d31 | 3084 | stack = XNEWVEC (basic_block, n_basic_blocks_for_fn (cfun)); |
a05924f9 | 3085 | sp = stack; |
48227150 | 3086 | |
a05924f9 | 3087 | *sp++ = block; |
48227150 | 3088 | |
a05924f9 JH |
3089 | do |
3090 | { | |
3091 | edge e; | |
628f6a4e | 3092 | edge_iterator ei; |
48227150 | 3093 | |
a05924f9 | 3094 | block = *--sp; |
48227150 | 3095 | |
b3cd99cd EB |
3096 | /* Processing BLOCK is achieved by convert_regs_1, which may purge |
3097 | some dead EH outgoing edge after the deletion of the trapping | |
3098 | insn inside the block. Since the number of predecessors of | |
3099 | BLOCK's successors was computed based on the initial edge set, | |
3100 | we check the necessity to process some of these successors | |
3101 | before such an edge deletion may happen. However, there is | |
3102 | a pitfall: if BLOCK is the only predecessor of a successor and | |
3103 | the edge between them happens to be deleted, the successor | |
3104 | becomes unreachable and should not be processed. The problem | |
3105 | is that there is no way to preventively detect this case so we | |
3106 | stack the successor in all cases and hand over the task of | |
3107 | fixing up the discrepancy to convert_regs_1. */ | |
3108 | ||
628f6a4e | 3109 | FOR_EACH_EDGE (e, ei, block->succs) |
0ecf09f9 | 3110 | if (! (e->flags & EDGE_DFS_BACK)) |
a05924f9 | 3111 | { |
754d9299 JM |
3112 | BLOCK_INFO (e->dest)->predecessors--; |
3113 | if (!BLOCK_INFO (e->dest)->predecessors) | |
628f6a4e | 3114 | *sp++ = e->dest; |
a05924f9 | 3115 | } |
de582cfb | 3116 | |
12929514 | 3117 | cfg_altered |= convert_regs_1 (block); |
48227150 | 3118 | } |
a05924f9 JH |
3119 | while (sp != stack); |
3120 | ||
3d5eef4c | 3121 | free (stack); |
12929514 EB |
3122 | |
3123 | return cfg_altered; | |
48227150 | 3124 | } |
841fc5a1 | 3125 | |
a05924f9 JH |
3126 | /* Traverse all basic blocks in a function, converting the register |
3127 | references in each insn from the "flat" register file that gcc uses, | |
3128 | to the stack-like registers the 387 uses. */ | |
3129 | ||
00b9ce5c | 3130 | static void |
10d22567 | 3131 | convert_regs (void) |
48227150 | 3132 | { |
12929514 | 3133 | bool cfg_altered = false; |
e0082a72 ZD |
3134 | int inserted; |
3135 | basic_block b; | |
a05924f9 | 3136 | edge e; |
628f6a4e | 3137 | edge_iterator ei; |
48227150 | 3138 | |
a05924f9 JH |
3139 | /* Initialize uninitialized registers on function entry. */ |
3140 | inserted = convert_regs_entry (); | |
48227150 | 3141 | |
a05924f9 JH |
3142 | /* Construct the desired stack for function exit. */ |
3143 | convert_regs_exit (); | |
fefa31b5 | 3144 | BLOCK_INFO (EXIT_BLOCK_PTR_FOR_FN (cfun))->done = 1; |
48227150 | 3145 | |
a05924f9 JH |
3146 | /* ??? Future: process inner loops first, and give them arbitrary |
3147 | initial stacks which emit_swap_insn can modify. This ought to | |
1ae58c30 | 3148 | prevent double fxch that often appears at the head of a loop. */ |
48227150 | 3149 | |
a05924f9 | 3150 | /* Process all blocks reachable from all entry points. */ |
fefa31b5 | 3151 | FOR_EACH_EDGE (e, ei, ENTRY_BLOCK_PTR_FOR_FN (cfun)->succs) |
12929514 | 3152 | cfg_altered |= convert_regs_2 (e->dest); |
a6a2274a KH |
3153 | |
3154 | /* ??? Process all unreachable blocks. Though there's no excuse | |
a05924f9 | 3155 | for keeping these even when not optimizing. */ |
11cd3bed | 3156 | FOR_EACH_BB_FN (b, cfun) |
a05924f9 | 3157 | { |
a05924f9 | 3158 | block_info bi = BLOCK_INFO (b); |
48227150 | 3159 | |
a05924f9 | 3160 | if (! bi->done) |
12929514 | 3161 | cfg_altered |= convert_regs_2 (b); |
a05924f9 | 3162 | } |
1c320f82 | 3163 | |
ba5e9aca EB |
3164 | /* We must fix up abnormal edges before inserting compensation code |
3165 | because both mechanisms insert insns on edges. */ | |
3166 | inserted |= fixup_abnormal_edges (); | |
3167 | ||
10d22567 | 3168 | inserted |= compensate_edges (); |
1c320f82 | 3169 | |
9dca2ad5 | 3170 | clear_aux_for_blocks (); |
48227150 | 3171 | |
a05924f9 JH |
3172 | if (inserted) |
3173 | commit_edge_insertions (); | |
48227150 | 3174 | |
12929514 EB |
3175 | if (cfg_altered) |
3176 | cleanup_cfg (0); | |
3177 | ||
10d22567 ZD |
3178 | if (dump_file) |
3179 | fputc ('\n', dump_file); | |
00b9ce5c RS |
3180 | } |
3181 | \f | |
3182 | /* Convert register usage from "flat" register file usage to a "stack | |
3183 | register file. FILE is the dump file, if used. | |
48227150 | 3184 | |
00b9ce5c RS |
3185 | Construct a CFG and run life analysis. Then convert each insn one |
3186 | by one. Run a last cleanup_cfg pass, if optimizing, to eliminate | |
3187 | code duplication created when the converter inserts pop insns on | |
3188 | the edges. */ | |
3189 | ||
cf4d5c75 | 3190 | static bool |
10d22567 | 3191 | reg_to_stack (void) |
00b9ce5c RS |
3192 | { |
3193 | basic_block bb; | |
3194 | int i; | |
3195 | int max_uid; | |
3196 | ||
3197 | /* Clean up previous run. */ | |
9771b263 | 3198 | stack_regs_mentioned_data.release (); |
00b9ce5c RS |
3199 | |
3200 | /* See if there is something to do. Flow analysis is quite | |
3201 | expensive so we might save some compilation time. */ | |
3202 | for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++) | |
6fb5fa3c | 3203 | if (df_regs_ever_live_p (i)) |
00b9ce5c RS |
3204 | break; |
3205 | if (i > LAST_STACK_REG) | |
3206 | return false; | |
3207 | ||
6fb5fa3c DB |
3208 | df_note_add_problem (); |
3209 | df_analyze (); | |
3210 | ||
00b9ce5c RS |
3211 | mark_dfs_back_edges (); |
3212 | ||
3213 | /* Set up block info for each basic block. */ | |
3214 | alloc_aux_for_blocks (sizeof (struct block_info_def)); | |
11cd3bed | 3215 | FOR_EACH_BB_FN (bb, cfun) |
00b9ce5c RS |
3216 | { |
3217 | block_info bi = BLOCK_INFO (bb); | |
3218 | edge_iterator ei; | |
3219 | edge e; | |
3220 | int reg; | |
3221 | ||
3222 | FOR_EACH_EDGE (e, ei, bb->preds) | |
3223 | if (!(e->flags & EDGE_DFS_BACK) | |
fefa31b5 | 3224 | && e->src != ENTRY_BLOCK_PTR_FOR_FN (cfun)) |
00b9ce5c RS |
3225 | bi->predecessors++; |
3226 | ||
3227 | /* Set current register status at last instruction `uninitialized'. */ | |
3228 | bi->stack_in.top = -2; | |
3229 | ||
3230 | /* Copy live_at_end and live_at_start into temporaries. */ | |
3231 | for (reg = FIRST_STACK_REG; reg <= LAST_STACK_REG; reg++) | |
3232 | { | |
6fb5fa3c | 3233 | if (REGNO_REG_SET_P (DF_LR_OUT (bb), reg)) |
00b9ce5c | 3234 | SET_HARD_REG_BIT (bi->out_reg_set, reg); |
6fb5fa3c | 3235 | if (REGNO_REG_SET_P (DF_LR_IN (bb), reg)) |
00b9ce5c RS |
3236 | SET_HARD_REG_BIT (bi->stack_in.reg_set, reg); |
3237 | } | |
3238 | } | |
3239 | ||
3240 | /* Create the replacement registers up front. */ | |
3241 | for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++) | |
3242 | { | |
3243 | enum machine_mode mode; | |
3244 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); | |
3245 | mode != VOIDmode; | |
3246 | mode = GET_MODE_WIDER_MODE (mode)) | |
3247 | FP_MODE_REG (i, mode) = gen_rtx_REG (mode, i); | |
3248 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_COMPLEX_FLOAT); | |
3249 | mode != VOIDmode; | |
3250 | mode = GET_MODE_WIDER_MODE (mode)) | |
3251 | FP_MODE_REG (i, mode) = gen_rtx_REG (mode, i); | |
3252 | } | |
3253 | ||
3254 | ix86_flags_rtx = gen_rtx_REG (CCmode, FLAGS_REG); | |
3255 | ||
3256 | /* A QNaN for initializing uninitialized variables. | |
3257 | ||
3258 | ??? We can't load from constant memory in PIC mode, because | |
3259 | we're inserting these instructions before the prologue and | |
3260 | the PIC register hasn't been set up. In that case, fall back | |
11f48903 | 3261 | on zero, which we can get from `fldz'. */ |
00b9ce5c | 3262 | |
dc4d7240 JH |
3263 | if ((flag_pic && !TARGET_64BIT) |
3264 | || ix86_cmodel == CM_LARGE || ix86_cmodel == CM_LARGE_PIC) | |
00b9ce5c RS |
3265 | not_a_num = CONST0_RTX (SFmode); |
3266 | else | |
3267 | { | |
11f48903 UB |
3268 | REAL_VALUE_TYPE r; |
3269 | ||
3270 | real_nan (&r, "", 1, SFmode); | |
3271 | not_a_num = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode); | |
00b9ce5c RS |
3272 | not_a_num = force_const_mem (SFmode, not_a_num); |
3273 | } | |
3274 | ||
3275 | /* Allocate a cache for stack_regs_mentioned. */ | |
3276 | max_uid = get_max_uid (); | |
9771b263 DN |
3277 | stack_regs_mentioned_data.create (max_uid + 1); |
3278 | memset (stack_regs_mentioned_data.address (), | |
0a83b1b0 | 3279 | 0, sizeof (char) * (max_uid + 1)); |
00b9ce5c | 3280 | |
10d22567 | 3281 | convert_regs (); |
00b9ce5c RS |
3282 | |
3283 | free_aux_for_blocks (); | |
3284 | return true; | |
48227150 | 3285 | } |
48227150 | 3286 | #endif /* STACK_REGS */ |
ef330312 PB |
3287 | \f |
3288 | static bool | |
3289 | gate_handle_stack_regs (void) | |
3290 | { | |
3291 | #ifdef STACK_REGS | |
3292 | return 1; | |
3293 | #else | |
3294 | return 0; | |
3295 | #endif | |
3296 | } | |
3297 | ||
27a4cd48 DM |
3298 | namespace { |
3299 | ||
3300 | const pass_data pass_data_stack_regs = | |
6fb5fa3c | 3301 | { |
27a4cd48 DM |
3302 | RTL_PASS, /* type */ |
3303 | "*stack_regs", /* name */ | |
3304 | OPTGROUP_NONE, /* optinfo_flags */ | |
3305 | true, /* has_gate */ | |
3306 | false, /* has_execute */ | |
3307 | TV_REG_STACK, /* tv_id */ | |
3308 | 0, /* properties_required */ | |
3309 | 0, /* properties_provided */ | |
3310 | 0, /* properties_destroyed */ | |
3311 | 0, /* todo_flags_start */ | |
3312 | 0, /* todo_flags_finish */ | |
6fb5fa3c DB |
3313 | }; |
3314 | ||
27a4cd48 DM |
3315 | class pass_stack_regs : public rtl_opt_pass |
3316 | { | |
3317 | public: | |
c3284718 RS |
3318 | pass_stack_regs (gcc::context *ctxt) |
3319 | : rtl_opt_pass (pass_data_stack_regs, ctxt) | |
27a4cd48 DM |
3320 | {} |
3321 | ||
3322 | /* opt_pass methods: */ | |
3323 | bool gate () { return gate_handle_stack_regs (); } | |
3324 | ||
3325 | }; // class pass_stack_regs | |
3326 | ||
3327 | } // anon namespace | |
3328 | ||
3329 | rtl_opt_pass * | |
3330 | make_pass_stack_regs (gcc::context *ctxt) | |
3331 | { | |
3332 | return new pass_stack_regs (ctxt); | |
3333 | } | |
3334 | ||
ef330312 PB |
3335 | /* Convert register usage from flat register file usage to a stack |
3336 | register file. */ | |
c2924966 | 3337 | static unsigned int |
ef330312 PB |
3338 | rest_of_handle_stack_regs (void) |
3339 | { | |
3340 | #ifdef STACK_REGS | |
6fb5fa3c DB |
3341 | reg_to_stack (); |
3342 | regstack_completed = 1; | |
ef330312 | 3343 | #endif |
c2924966 | 3344 | return 0; |
ef330312 PB |
3345 | } |
3346 | ||
27a4cd48 DM |
3347 | namespace { |
3348 | ||
3349 | const pass_data pass_data_stack_regs_run = | |
ef330312 | 3350 | { |
27a4cd48 DM |
3351 | RTL_PASS, /* type */ |
3352 | "stack", /* name */ | |
3353 | OPTGROUP_NONE, /* optinfo_flags */ | |
3354 | false, /* has_gate */ | |
3355 | true, /* has_execute */ | |
3356 | TV_REG_STACK, /* tv_id */ | |
3357 | 0, /* properties_required */ | |
3358 | 0, /* properties_provided */ | |
3359 | 0, /* properties_destroyed */ | |
3360 | 0, /* todo_flags_start */ | |
3361 | ( TODO_df_finish | TODO_verify_rtl_sharing ), /* todo_flags_finish */ | |
ef330312 | 3362 | }; |
27a4cd48 DM |
3363 | |
3364 | class pass_stack_regs_run : public rtl_opt_pass | |
3365 | { | |
3366 | public: | |
c3284718 RS |
3367 | pass_stack_regs_run (gcc::context *ctxt) |
3368 | : rtl_opt_pass (pass_data_stack_regs_run, ctxt) | |
27a4cd48 DM |
3369 | {} |
3370 | ||
3371 | /* opt_pass methods: */ | |
3372 | unsigned int execute () { return rest_of_handle_stack_regs (); } | |
3373 | ||
3374 | }; // class pass_stack_regs_run | |
3375 | ||
3376 | } // anon namespace | |
3377 | ||
3378 | rtl_opt_pass * | |
3379 | make_pass_stack_regs_run (gcc::context *ctxt) | |
3380 | { | |
3381 | return new pass_stack_regs_run (ctxt); | |
3382 | } |