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48227150 | 1 | /* Register to Stack convert for GNU compiler. |
818ab71a | 2 | Copyright (C) 1992-2016 Free Software Foundation, Inc. |
48227150 | 3 | |
1322177d | 4 | This file is part of GCC. |
48227150 | 5 | |
1322177d LB |
6 | GCC is free software; you can redistribute it and/or modify it |
7 | under the terms of the GNU General Public License as published by | |
9dcd6f09 | 8 | the Free Software Foundation; either version 3, or (at your option) |
a05924f9 | 9 | any later version. |
48227150 | 10 | |
1322177d LB |
11 | GCC is distributed in the hope that it will be useful, but WITHOUT |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
14 | License for more details. | |
48227150 | 15 | |
a05924f9 | 16 | You should have received a copy of the GNU General Public License |
9dcd6f09 NC |
17 | along with GCC; see the file COPYING3. If not see |
18 | <http://www.gnu.org/licenses/>. */ | |
48227150 JVA |
19 | |
20 | /* This pass converts stack-like registers from the "flat register | |
21 | file" model that gcc uses, to a stack convention that the 387 uses. | |
22 | ||
23 | * The form of the input: | |
24 | ||
25 | On input, the function consists of insn that have had their | |
26 | registers fully allocated to a set of "virtual" registers. Note that | |
27 | the word "virtual" is used differently here than elsewhere in gcc: for | |
28 | each virtual stack reg, there is a hard reg, but the mapping between | |
29 | them is not known until this pass is run. On output, hard register | |
30 | numbers have been substituted, and various pop and exchange insns have | |
31 | been emitted. The hard register numbers and the virtual register | |
32 | numbers completely overlap - before this pass, all stack register | |
114cbee6 | 33 | numbers are virtual, and afterward they are all hard. |
48227150 JVA |
34 | |
35 | The virtual registers can be manipulated normally by gcc, and their | |
36 | semantics are the same as for normal registers. After the hard | |
37 | register numbers are substituted, the semantics of an insn containing | |
38 | stack-like regs are not the same as for an insn with normal regs: for | |
39 | instance, it is not safe to delete an insn that appears to be a no-op | |
40 | move. In general, no insn containing hard regs should be changed | |
41 | after this pass is done. | |
42 | ||
43 | * The form of the output: | |
44 | ||
45 | After this pass, hard register numbers represent the distance from | |
46 | the current top of stack to the desired register. A reference to | |
47 | FIRST_STACK_REG references the top of stack, FIRST_STACK_REG + 1, | |
48 | represents the register just below that, and so forth. Also, REG_DEAD | |
49 | notes indicate whether or not a stack register should be popped. | |
50 | ||
51 | A "swap" insn looks like a parallel of two patterns, where each | |
52 | pattern is a SET: one sets A to B, the other B to A. | |
53 | ||
54 | A "push" or "load" insn is a SET whose SET_DEST is FIRST_STACK_REG | |
55 | and whose SET_DEST is REG or MEM. Any other SET_DEST, such as PLUS, | |
56 | will replace the existing stack top, not push a new value. | |
57 | ||
58 | A store insn is a SET whose SET_DEST is FIRST_STACK_REG, and whose | |
59 | SET_SRC is REG or MEM. | |
60 | ||
3f5cfed6 | 61 | The case where the SET_SRC and SET_DEST are both FIRST_STACK_REG |
48227150 JVA |
62 | appears ambiguous. As a special case, the presence of a REG_DEAD note |
63 | for FIRST_STACK_REG differentiates between a load insn and a pop. | |
64 | ||
65 | If a REG_DEAD is present, the insn represents a "pop" that discards | |
66 | the top of the register stack. If there is no REG_DEAD note, then the | |
67 | insn represents a "dup" or a push of the current top of stack onto the | |
68 | stack. | |
69 | ||
70 | * Methodology: | |
71 | ||
72 | Existing REG_DEAD and REG_UNUSED notes for stack registers are | |
73 | deleted and recreated from scratch. REG_DEAD is never created for a | |
74 | SET_DEST, only REG_UNUSED. | |
75 | ||
114cbee6 | 76 | * asm_operands: |
48227150 | 77 | |
114cbee6 RS |
78 | There are several rules on the usage of stack-like regs in |
79 | asm_operands insns. These rules apply only to the operands that are | |
80 | stack-like regs: | |
81 | ||
82 | 1. Given a set of input regs that die in an asm_operands, it is | |
83 | necessary to know which are implicitly popped by the asm, and | |
84 | which must be explicitly popped by gcc. | |
85 | ||
86 | An input reg that is implicitly popped by the asm must be | |
87 | explicitly clobbered, unless it is constrained to match an | |
88 | output operand. | |
89 | ||
90 | 2. For any input reg that is implicitly popped by an asm, it is | |
91 | necessary to know how to adjust the stack to compensate for the pop. | |
92 | If any non-popped input is closer to the top of the reg-stack than | |
93 | the implicitly popped reg, it would not be possible to know what the | |
94 | stack looked like - it's not clear how the rest of the stack "slides | |
95 | up". | |
96 | ||
97 | All implicitly popped input regs must be closer to the top of | |
98 | the reg-stack than any input that is not implicitly popped. | |
99 | ||
ad551c07 BE |
100 | All explicitly referenced input operands may not "skip" a reg. |
101 | Otherwise we can have holes in the stack. | |
102 | ||
114cbee6 RS |
103 | 3. It is possible that if an input dies in an insn, reload might |
104 | use the input reg for an output reload. Consider this example: | |
105 | ||
106 | asm ("foo" : "=t" (a) : "f" (b)); | |
107 | ||
108 | This asm says that input B is not popped by the asm, and that | |
454ff5cb | 109 | the asm pushes a result onto the reg-stack, i.e., the stack is one |
114cbee6 RS |
110 | deeper after the asm than it was before. But, it is possible that |
111 | reload will think that it can use the same reg for both the input and | |
112 | the output, if input B dies in this insn. | |
113 | ||
114 | If any input operand uses the "f" constraint, all output reg | |
115 | constraints must use the "&" earlyclobber. | |
116 | ||
117 | The asm above would be written as | |
118 | ||
119 | asm ("foo" : "=&t" (a) : "f" (b)); | |
120 | ||
121 | 4. Some operands need to be in particular places on the stack. All | |
122 | output operands fall in this category - there is no other way to | |
123 | know which regs the outputs appear in unless the user indicates | |
124 | this in the constraints. | |
125 | ||
126 | Output operands must specifically indicate which reg an output | |
127 | appears in after an asm. "=f" is not allowed: the operand | |
128 | constraints must select a class with a single reg. | |
129 | ||
130 | 5. Output operands may not be "inserted" between existing stack regs. | |
131 | Since no 387 opcode uses a read/write operand, all output operands | |
132 | are dead before the asm_operands, and are pushed by the asm_operands. | |
133 | It makes no sense to push anywhere but the top of the reg-stack. | |
134 | ||
135 | Output operands must start at the top of the reg-stack: output | |
136 | operands may not "skip" a reg. | |
137 | ||
138 | 6. Some asm statements may need extra stack space for internal | |
139 | calculations. This can be guaranteed by clobbering stack registers | |
140 | unrelated to the inputs and outputs. | |
141 | ||
142 | Here are a couple of reasonable asms to want to write. This asm | |
143 | takes one input, which is internally popped, and produces two outputs. | |
144 | ||
145 | asm ("fsincos" : "=t" (cos), "=u" (sin) : "0" (inp)); | |
146 | ||
147 | This asm takes two inputs, which are popped by the fyl2xp1 opcode, | |
148 | and replaces them with one output. The user must code the "st(1)" | |
149 | clobber for reg-stack.c to know that fyl2xp1 pops both inputs. | |
150 | ||
151 | asm ("fyl2xp1" : "=t" (result) : "0" (x), "u" (y) : "st(1)"); | |
152 | ||
a05924f9 | 153 | */ |
48227150 | 154 | \f |
48227150 | 155 | #include "config.h" |
670ee920 | 156 | #include "system.h" |
4977bab6 | 157 | #include "coretypes.h" |
c7131fb2 | 158 | #include "backend.h" |
957060b5 | 159 | #include "target.h" |
c7131fb2 | 160 | #include "rtl.h" |
957060b5 | 161 | #include "tree.h" |
c7131fb2 | 162 | #include "df.h" |
114cbee6 | 163 | #include "insn-config.h" |
4d0cdd0c | 164 | #include "memmodel.h" |
957060b5 | 165 | #include "emit-rtl.h" /* FIXME: Can go away once crtl is moved to rtl.h. */ |
e075ae69 | 166 | #include "recog.h" |
957060b5 AM |
167 | #include "varasm.h" |
168 | #include "rtl-error.h" | |
60393bbc AM |
169 | #include "cfgrtl.h" |
170 | #include "cfganal.h" | |
171 | #include "cfgbuild.h" | |
172 | #include "cfgcleanup.h" | |
2840aebf | 173 | #include "reload.h" |
ef330312 | 174 | #include "tree-pass.h" |
6c0cda91 | 175 | #include "rtl-iter.h" |
e4881f23 | 176 | |
5b94780f KH |
177 | #ifdef STACK_REGS |
178 | ||
e2500fed GK |
179 | /* We use this array to cache info about insns, because otherwise we |
180 | spend too much time in stack_regs_mentioned_p. | |
181 | ||
182 | Indexed by insn UIDs. A value of zero is uninitialized, one indicates | |
183 | the insn uses stack registers, two indicates the insn does not use | |
184 | stack registers. */ | |
9771b263 | 185 | static vec<char> stack_regs_mentioned_data; |
48227150 | 186 | |
48227150 JVA |
187 | #define REG_STACK_SIZE (LAST_STACK_REG - FIRST_STACK_REG + 1) |
188 | ||
23249ac4 DB |
189 | int regstack_completed = 0; |
190 | ||
48227150 JVA |
191 | /* This is the basic stack record. TOP is an index into REG[] such |
192 | that REG[TOP] is the top of stack. If TOP is -1 the stack is empty. | |
193 | ||
eca31501 JVA |
194 | If TOP is -2, REG[] is not yet initialized. Stack initialization |
195 | consists of placing each live reg in array `reg' and setting `top' | |
196 | appropriately. | |
197 | ||
198 | REG_SET indicates which registers are live. */ | |
48227150 JVA |
199 | |
200 | typedef struct stack_def | |
201 | { | |
202 | int top; /* index to top stack element */ | |
203 | HARD_REG_SET reg_set; /* set of live registers */ | |
b00b2cc2 | 204 | unsigned char reg[REG_STACK_SIZE];/* register - stack mapping */ |
0823efed | 205 | } *stack_ptr; |
48227150 | 206 | |
a6a2274a | 207 | /* This is used to carry information about basic blocks. It is |
a05924f9 | 208 | attached to the AUX field of the standard CFG block. */ |
48227150 | 209 | |
a05924f9 JH |
210 | typedef struct block_info_def |
211 | { | |
212 | struct stack_def stack_in; /* Input stack configuration. */ | |
0ecf09f9 | 213 | struct stack_def stack_out; /* Output stack configuration. */ |
a05924f9 JH |
214 | HARD_REG_SET out_reg_set; /* Stack regs live on output. */ |
215 | int done; /* True if block already converted. */ | |
579e4a82 | 216 | int predecessors; /* Number of predecessors that need |
0ecf09f9 | 217 | to be visited. */ |
a05924f9 | 218 | } *block_info; |
48227150 | 219 | |
a05924f9 | 220 | #define BLOCK_INFO(B) ((block_info) (B)->aux) |
48227150 | 221 | |
a05924f9 JH |
222 | /* Passed to change_stack to indicate where to emit insns. */ |
223 | enum emit_where | |
224 | { | |
225 | EMIT_AFTER, | |
226 | EMIT_BEFORE | |
227 | }; | |
48227150 | 228 | |
a05924f9 JH |
229 | /* The block we're currently working on. */ |
230 | static basic_block current_block; | |
231 | ||
385e0e08 | 232 | /* In the current_block, whether we're processing the first register |
2e48874f | 233 | stack or call instruction, i.e. the regstack is currently the |
385e0e08 RS |
234 | same as BLOCK_INFO(current_block)->stack_in. */ |
235 | static bool starting_stack_p; | |
236 | ||
3eae4643 | 237 | /* This is the register file for all register after conversion. */ |
99a59310 RK |
238 | static rtx |
239 | FP_mode_reg[LAST_STACK_REG+1-FIRST_STACK_REG][(int) MAX_MACHINE_MODE]; | |
240 | ||
241 | #define FP_MODE_REG(regno,mode) \ | |
f4f4d0f8 | 242 | (FP_mode_reg[(regno)-FIRST_STACK_REG][(int) (mode)]) |
48227150 | 243 | |
a05924f9 | 244 | /* Used to initialize uninitialized registers. */ |
d2032ad8 | 245 | static rtx not_a_num; |
48227150 | 246 | |
48227150 JVA |
247 | /* Forward declarations */ |
248 | ||
9678086d | 249 | static int stack_regs_mentioned_p (const_rtx pat); |
0823efed | 250 | static void pop_stack (stack_ptr, int); |
0c20a65f AJ |
251 | static rtx *get_true_reg (rtx *); |
252 | ||
d8aeaba0 | 253 | static int check_asm_stack_operands (rtx_insn *); |
1c384bf1 | 254 | static void get_asm_operands_in_out (rtx, int *, int *); |
0c20a65f AJ |
255 | static rtx stack_result (tree); |
256 | static void replace_reg (rtx *, int); | |
d8aeaba0 | 257 | static void remove_regno_note (rtx_insn *, enum reg_note, unsigned int); |
0823efed | 258 | static int get_hard_regnum (stack_ptr, rtx); |
d8aeaba0 DM |
259 | static rtx_insn *emit_pop_insn (rtx_insn *, stack_ptr, rtx, enum emit_where); |
260 | static void swap_to_top (rtx_insn *, stack_ptr, rtx, rtx); | |
261 | static bool move_for_stack_reg (rtx_insn *, stack_ptr, rtx); | |
262 | static bool move_nan_for_stack_reg (rtx_insn *, stack_ptr, rtx); | |
0c20a65f | 263 | static int swap_rtx_condition_1 (rtx); |
d8aeaba0 DM |
264 | static int swap_rtx_condition (rtx_insn *); |
265 | static void compare_for_stack_reg (rtx_insn *, stack_ptr, rtx); | |
266 | static bool subst_stack_regs_pat (rtx_insn *, stack_ptr, rtx); | |
267 | static void subst_asm_stack_regs (rtx_insn *, stack_ptr); | |
268 | static bool subst_stack_regs (rtx_insn *, stack_ptr); | |
269 | static void change_stack (rtx_insn *, stack_ptr, stack_ptr, enum emit_where); | |
0823efed | 270 | static void print_stack (FILE *, stack_ptr); |
d8aeaba0 | 271 | static rtx_insn *next_flags_user (rtx_insn *); |
21b2cd73 | 272 | \f |
40f03658 | 273 | /* Return nonzero if any stack register is mentioned somewhere within PAT. */ |
21b2cd73 JH |
274 | |
275 | static int | |
9678086d | 276 | stack_regs_mentioned_p (const_rtx pat) |
21b2cd73 | 277 | { |
b3694847 SS |
278 | const char *fmt; |
279 | int i; | |
e075ae69 RH |
280 | |
281 | if (STACK_REG_P (pat)) | |
282 | return 1; | |
283 | ||
284 | fmt = GET_RTX_FORMAT (GET_CODE (pat)); | |
285 | for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0; i--) | |
21b2cd73 | 286 | { |
e075ae69 RH |
287 | if (fmt[i] == 'E') |
288 | { | |
b3694847 | 289 | int j; |
e075ae69 RH |
290 | |
291 | for (j = XVECLEN (pat, i) - 1; j >= 0; j--) | |
292 | if (stack_regs_mentioned_p (XVECEXP (pat, i, j))) | |
293 | return 1; | |
294 | } | |
295 | else if (fmt[i] == 'e' && stack_regs_mentioned_p (XEXP (pat, i))) | |
296 | return 1; | |
21b2cd73 | 297 | } |
e075ae69 | 298 | |
21b2cd73 JH |
299 | return 0; |
300 | } | |
301 | ||
e075ae69 | 302 | /* Return nonzero if INSN mentions stacked registers, else return zero. */ |
21b2cd73 JH |
303 | |
304 | int | |
9678086d | 305 | stack_regs_mentioned (const_rtx insn) |
21b2cd73 | 306 | { |
e075ae69 RH |
307 | unsigned int uid, max; |
308 | int test; | |
309 | ||
9771b263 | 310 | if (! INSN_P (insn) || !stack_regs_mentioned_data.exists ()) |
21b2cd73 | 311 | return 0; |
e075ae69 | 312 | |
21b2cd73 | 313 | uid = INSN_UID (insn); |
9771b263 | 314 | max = stack_regs_mentioned_data.length (); |
e075ae69 RH |
315 | if (uid >= max) |
316 | { | |
317 | /* Allocate some extra size to avoid too many reallocs, but | |
318 | do not grow too quickly. */ | |
e4881f23 | 319 | max = uid + uid / 20 + 1; |
9771b263 | 320 | stack_regs_mentioned_data.safe_grow_cleared (max); |
e075ae69 RH |
321 | } |
322 | ||
9771b263 | 323 | test = stack_regs_mentioned_data[uid]; |
e075ae69 RH |
324 | if (test == 0) |
325 | { | |
326 | /* This insn has yet to be examined. Do so now. */ | |
327 | test = stack_regs_mentioned_p (PATTERN (insn)) ? 1 : 2; | |
9771b263 | 328 | stack_regs_mentioned_data[uid] = test; |
e075ae69 RH |
329 | } |
330 | ||
331 | return test == 1; | |
21b2cd73 | 332 | } |
e075ae69 RH |
333 | \f |
334 | static rtx ix86_flags_rtx; | |
21b2cd73 | 335 | |
d8aeaba0 DM |
336 | static rtx_insn * |
337 | next_flags_user (rtx_insn *insn) | |
e075ae69 | 338 | { |
a6a2274a | 339 | /* Search forward looking for the first use of this value. |
e075ae69 | 340 | Stop at block boundaries. */ |
e075ae69 | 341 | |
a813c111 | 342 | while (insn != BB_END (current_block)) |
e075ae69 RH |
343 | { |
344 | insn = NEXT_INSN (insn); | |
e075ae69 | 345 | |
2c3c49de | 346 | if (INSN_P (insn) && reg_mentioned_p (ix86_flags_rtx, PATTERN (insn))) |
a6a2274a | 347 | return insn; |
e075ae69 | 348 | |
4b4bf941 | 349 | if (CALL_P (insn)) |
d8aeaba0 | 350 | return NULL; |
e075ae69 | 351 | } |
d8aeaba0 | 352 | return NULL; |
e075ae69 | 353 | } |
48227150 | 354 | \f |
385e0e08 | 355 | /* Reorganize the stack into ascending numbers, before this insn. */ |
99a59310 RK |
356 | |
357 | static void | |
d8aeaba0 | 358 | straighten_stack (rtx_insn *insn, stack_ptr regstack) |
99a59310 RK |
359 | { |
360 | struct stack_def temp_stack; | |
361 | int top; | |
362 | ||
8feb7351 JL |
363 | /* If there is only a single register on the stack, then the stack is |
364 | already in increasing order and no reorganization is needed. | |
365 | ||
366 | Similarly if the stack is empty. */ | |
367 | if (regstack->top <= 0) | |
368 | return; | |
369 | ||
d25cf633 | 370 | COPY_HARD_REG_SET (temp_stack.reg_set, regstack->reg_set); |
99a59310 RK |
371 | |
372 | for (top = temp_stack.top = regstack->top; top >= 0; top--) | |
e075ae69 | 373 | temp_stack.reg[top] = FIRST_STACK_REG + temp_stack.top - top; |
a6a2274a | 374 | |
385e0e08 | 375 | change_stack (insn, regstack, &temp_stack, EMIT_BEFORE); |
99a59310 | 376 | } |
7aa74e4c | 377 | |
3eae4643 | 378 | /* Pop a register from the stack. */ |
7aa74e4c SC |
379 | |
380 | static void | |
0823efed | 381 | pop_stack (stack_ptr regstack, int regno) |
7aa74e4c SC |
382 | { |
383 | int top = regstack->top; | |
384 | ||
385 | CLEAR_HARD_REG_BIT (regstack->reg_set, regno); | |
386 | regstack->top--; | |
3eae4643 | 387 | /* If regno was not at the top of stack then adjust stack. */ |
7aa74e4c SC |
388 | if (regstack->reg [top] != regno) |
389 | { | |
390 | int i; | |
391 | for (i = regstack->top; i >= 0; i--) | |
392 | if (regstack->reg [i] == regno) | |
393 | { | |
394 | int j; | |
395 | for (j = i; j < top; j++) | |
396 | regstack->reg [j] = regstack->reg [j + 1]; | |
397 | break; | |
398 | } | |
399 | } | |
400 | } | |
48227150 JVA |
401 | \f |
402 | /* Return a pointer to the REG expression within PAT. If PAT is not a | |
403 | REG, possible enclosed by a conversion rtx, return the inner part of | |
0f41302f | 404 | PAT that stopped the search. */ |
48227150 JVA |
405 | |
406 | static rtx * | |
0c20a65f | 407 | get_true_reg (rtx *pat) |
48227150 | 408 | { |
99a59310 | 409 | for (;;) |
e075ae69 | 410 | switch (GET_CODE (*pat)) |
99a59310 | 411 | { |
e075ae69 | 412 | case SUBREG: |
8d9afc4e | 413 | /* Eliminate FP subregister accesses in favor of the |
e075ae69 RH |
414 | actual FP register in use. */ |
415 | { | |
416 | rtx subreg; | |
66aaf16f | 417 | if (STACK_REG_P (subreg = SUBREG_REG (*pat))) |
99a59310 | 418 | { |
ddef6bc7 JJ |
419 | int regno_off = subreg_regno_offset (REGNO (subreg), |
420 | GET_MODE (subreg), | |
421 | SUBREG_BYTE (*pat), | |
422 | GET_MODE (*pat)); | |
423 | *pat = FP_MODE_REG (REGNO (subreg) + regno_off, | |
99a59310 | 424 | GET_MODE (subreg)); |
99a59310 RK |
425 | return pat; |
426 | } | |
f0bc3323 MP |
427 | pat = &XEXP (*pat, 0); |
428 | break; | |
e075ae69 RH |
429 | } |
430 | case FLOAT: | |
431 | case FIX: | |
432 | case FLOAT_EXTEND: | |
f0bc3323 | 433 | pat = &XEXP (*pat, 0); |
0c5faf29 RS |
434 | break; |
435 | ||
01302104 | 436 | case UNSPEC: |
09ad58e6 | 437 | if (XINT (*pat, 1) == UNSPEC_TRUNC_NOOP |
a8caf351 | 438 | || XINT (*pat, 1) == UNSPEC_FILD_ATOMIC) |
f0bc3323 | 439 | pat = &XVECEXP (*pat, 0, 0); |
56d8eb62 | 440 | return pat; |
01302104 | 441 | |
0c5faf29 RS |
442 | case FLOAT_TRUNCATE: |
443 | if (!flag_unsafe_math_optimizations) | |
444 | return pat; | |
f0bc3323 | 445 | pat = &XEXP (*pat, 0); |
0c5faf29 | 446 | break; |
c8e2516c SB |
447 | |
448 | default: | |
449 | return pat; | |
99a59310 | 450 | } |
48227150 | 451 | } |
48227150 | 452 | \f |
d6fc0492 RH |
453 | /* Set if we find any malformed asms in a block. */ |
454 | static bool any_malformed_asm; | |
455 | ||
a05924f9 | 456 | /* There are many rules that an asm statement for stack-like regs must |
114cbee6 | 457 | follow. Those rules are explained at the top of this file: the rule |
0f41302f | 458 | numbers below refer to that explanation. */ |
114cbee6 | 459 | |
a05924f9 | 460 | static int |
d8aeaba0 | 461 | check_asm_stack_operands (rtx_insn *insn) |
114cbee6 RS |
462 | { |
463 | int i; | |
114cbee6 RS |
464 | int n_clobbers; |
465 | int malformed_asm = 0; | |
466 | rtx body = PATTERN (insn); | |
467 | ||
a05924f9 JH |
468 | char reg_used_as_output[FIRST_PSEUDO_REGISTER]; |
469 | char implicitly_dies[FIRST_PSEUDO_REGISTER]; | |
ad551c07 | 470 | char explicitly_used[FIRST_PSEUDO_REGISTER]; |
114cbee6 | 471 | |
a544cfd2 | 472 | rtx *clobber_reg = 0; |
f62a15e3 | 473 | int n_inputs, n_outputs; |
114cbee6 | 474 | |
0e7d0eb9 | 475 | /* Find out what the constraints require. If no constraint |
854dfdff | 476 | alternative matches, this asm is malformed. */ |
75d25a02 | 477 | extract_constrain_insn (insn); |
f62a15e3 | 478 | |
1145837d | 479 | preprocess_constraints (insn); |
f62a15e3 | 480 | |
1c384bf1 | 481 | get_asm_operands_in_out (body, &n_outputs, &n_inputs); |
f62a15e3 | 482 | |
29d70a0f | 483 | if (which_alternative < 0) |
f62a15e3 BS |
484 | { |
485 | malformed_asm = 1; | |
486 | /* Avoid further trouble with this insn. */ | |
487 | PATTERN (insn) = gen_rtx_USE (VOIDmode, const0_rtx); | |
a05924f9 | 488 | return 0; |
f62a15e3 | 489 | } |
5efe5dec | 490 | const operand_alternative *op_alt = which_op_alt (); |
114cbee6 | 491 | |
0f41302f | 492 | /* Strip SUBREGs here to make the following code simpler. */ |
1ccbefce RH |
493 | for (i = 0; i < recog_data.n_operands; i++) |
494 | if (GET_CODE (recog_data.operand[i]) == SUBREG | |
f8cfc6aa | 495 | && REG_P (SUBREG_REG (recog_data.operand[i]))) |
1ccbefce | 496 | recog_data.operand[i] = SUBREG_REG (recog_data.operand[i]); |
114cbee6 RS |
497 | |
498 | /* Set up CLOBBER_REG. */ | |
499 | ||
500 | n_clobbers = 0; | |
114cbee6 RS |
501 | |
502 | if (GET_CODE (body) == PARALLEL) | |
3f5cfed6 | 503 | { |
1634b18f | 504 | clobber_reg = XALLOCAVEC (rtx, XVECLEN (body, 0)); |
114cbee6 | 505 | |
3f5cfed6 JVA |
506 | for (i = 0; i < XVECLEN (body, 0); i++) |
507 | if (GET_CODE (XVECEXP (body, 0, i)) == CLOBBER) | |
508 | { | |
509 | rtx clobber = XVECEXP (body, 0, i); | |
510 | rtx reg = XEXP (clobber, 0); | |
114cbee6 | 511 | |
f8cfc6aa | 512 | if (GET_CODE (reg) == SUBREG && REG_P (SUBREG_REG (reg))) |
3f5cfed6 JVA |
513 | reg = SUBREG_REG (reg); |
514 | ||
515 | if (STACK_REG_P (reg)) | |
516 | { | |
517 | clobber_reg[n_clobbers] = reg; | |
518 | n_clobbers++; | |
519 | } | |
520 | } | |
521 | } | |
114cbee6 RS |
522 | |
523 | /* Enforce rule #4: Output operands must specifically indicate which | |
524 | reg an output appears in after an asm. "=f" is not allowed: the | |
525 | operand constraints must select a class with a single reg. | |
526 | ||
527 | Also enforce rule #5: Output operands must start at the top of | |
0f41302f | 528 | the reg-stack: output operands may not "skip" a reg. */ |
114cbee6 | 529 | |
a05924f9 | 530 | memset (reg_used_as_output, 0, sizeof (reg_used_as_output)); |
114cbee6 | 531 | for (i = 0; i < n_outputs; i++) |
1ccbefce | 532 | if (STACK_REG_P (recog_data.operand[i])) |
9c318306 | 533 | { |
29d70a0f | 534 | if (reg_class_size[(int) op_alt[i].cl] != 1) |
9c318306 | 535 | { |
1f978f5f | 536 | error_for_asm (insn, "output constraint %d must specify a single register", i); |
9c318306 MH |
537 | malformed_asm = 1; |
538 | } | |
a6a2274a | 539 | else |
d40cd80a JJ |
540 | { |
541 | int j; | |
542 | ||
543 | for (j = 0; j < n_clobbers; j++) | |
544 | if (REGNO (recog_data.operand[i]) == REGNO (clobber_reg[j])) | |
545 | { | |
1f978f5f | 546 | error_for_asm (insn, "output constraint %d cannot be specified together with \"%s\" clobber", |
d40cd80a JJ |
547 | i, reg_names [REGNO (clobber_reg[j])]); |
548 | malformed_asm = 1; | |
549 | break; | |
550 | } | |
551 | if (j == n_clobbers) | |
552 | reg_used_as_output[REGNO (recog_data.operand[i])] = 1; | |
553 | } | |
9c318306 | 554 | } |
114cbee6 RS |
555 | |
556 | ||
557 | /* Search for first non-popped reg. */ | |
558 | for (i = FIRST_STACK_REG; i < LAST_STACK_REG + 1; i++) | |
559 | if (! reg_used_as_output[i]) | |
560 | break; | |
561 | ||
562 | /* If there are any other popped regs, that's an error. */ | |
563 | for (; i < LAST_STACK_REG + 1; i++) | |
564 | if (reg_used_as_output[i]) | |
565 | break; | |
566 | ||
567 | if (i != LAST_STACK_REG + 1) | |
568 | { | |
1f978f5f | 569 | error_for_asm (insn, "output regs must be grouped at top of stack"); |
114cbee6 RS |
570 | malformed_asm = 1; |
571 | } | |
572 | ||
573 | /* Enforce rule #2: All implicitly popped input regs must be closer | |
574 | to the top of the reg-stack than any input that is not implicitly | |
0f41302f | 575 | popped. */ |
114cbee6 | 576 | |
a05924f9 | 577 | memset (implicitly_dies, 0, sizeof (implicitly_dies)); |
ad551c07 | 578 | memset (explicitly_used, 0, sizeof (explicitly_used)); |
f62a15e3 | 579 | for (i = n_outputs; i < n_outputs + n_inputs; i++) |
1ccbefce | 580 | if (STACK_REG_P (recog_data.operand[i])) |
114cbee6 RS |
581 | { |
582 | /* An input reg is implicitly popped if it is tied to an | |
0f41302f | 583 | output, or if there is a CLOBBER for it. */ |
114cbee6 RS |
584 | int j; |
585 | ||
586 | for (j = 0; j < n_clobbers; j++) | |
1ccbefce | 587 | if (operands_match_p (clobber_reg[j], recog_data.operand[i])) |
114cbee6 RS |
588 | break; |
589 | ||
29d70a0f | 590 | if (j < n_clobbers || op_alt[i].matches >= 0) |
1ccbefce | 591 | implicitly_dies[REGNO (recog_data.operand[i])] = 1; |
ad551c07 BE |
592 | else if (reg_class_size[(int) op_alt[i].cl] == 1) |
593 | explicitly_used[REGNO (recog_data.operand[i])] = 1; | |
114cbee6 RS |
594 | } |
595 | ||
596 | /* Search for first non-popped reg. */ | |
597 | for (i = FIRST_STACK_REG; i < LAST_STACK_REG + 1; i++) | |
598 | if (! implicitly_dies[i]) | |
599 | break; | |
600 | ||
601 | /* If there are any other popped regs, that's an error. */ | |
602 | for (; i < LAST_STACK_REG + 1; i++) | |
603 | if (implicitly_dies[i]) | |
604 | break; | |
605 | ||
606 | if (i != LAST_STACK_REG + 1) | |
607 | { | |
608 | error_for_asm (insn, | |
1f978f5f | 609 | "implicitly popped regs must be grouped at top of stack"); |
114cbee6 RS |
610 | malformed_asm = 1; |
611 | } | |
612 | ||
ad551c07 BE |
613 | /* Search for first not-explicitly used reg. */ |
614 | for (i = FIRST_STACK_REG; i < LAST_STACK_REG + 1; i++) | |
615 | if (! implicitly_dies[i] && ! explicitly_used[i]) | |
616 | break; | |
617 | ||
618 | /* If there are any other explicitly used regs, that's an error. */ | |
619 | for (; i < LAST_STACK_REG + 1; i++) | |
620 | if (explicitly_used[i]) | |
621 | break; | |
622 | ||
623 | if (i != LAST_STACK_REG + 1) | |
624 | { | |
625 | error_for_asm (insn, | |
626 | "explicitly used regs must be grouped at top of stack"); | |
627 | malformed_asm = 1; | |
628 | } | |
629 | ||
06d42c22 | 630 | /* Enforce rule #3: If any input operand uses the "f" constraint, all |
114cbee6 RS |
631 | output constraints must use the "&" earlyclobber. |
632 | ||
a05924f9 | 633 | ??? Detect this more deterministically by having constrain_asm_operands |
0f41302f | 634 | record any earlyclobber. */ |
114cbee6 | 635 | |
f62a15e3 | 636 | for (i = n_outputs; i < n_outputs + n_inputs; i++) |
ad551c07 | 637 | if (STACK_REG_P (recog_data.operand[i]) && op_alt[i].matches == -1) |
114cbee6 RS |
638 | { |
639 | int j; | |
640 | ||
641 | for (j = 0; j < n_outputs; j++) | |
1ccbefce | 642 | if (operands_match_p (recog_data.operand[j], recog_data.operand[i])) |
114cbee6 RS |
643 | { |
644 | error_for_asm (insn, | |
9e637a26 | 645 | "output operand %d must use %<&%> constraint", j); |
114cbee6 RS |
646 | malformed_asm = 1; |
647 | } | |
648 | } | |
649 | ||
650 | if (malformed_asm) | |
651 | { | |
652 | /* Avoid further trouble with this insn. */ | |
38a448ca | 653 | PATTERN (insn) = gen_rtx_USE (VOIDmode, const0_rtx); |
d6fc0492 | 654 | any_malformed_asm = true; |
a05924f9 | 655 | return 0; |
0e7d0eb9 | 656 | } |
48227150 | 657 | |
a05924f9 | 658 | return 1; |
48227150 JVA |
659 | } |
660 | \f | |
114cbee6 RS |
661 | /* Calculate the number of inputs and outputs in BODY, an |
662 | asm_operands. N_OPERANDS is the total number of operands, and | |
663 | N_INPUTS and N_OUTPUTS are pointers to ints into which the results are | |
0f41302f | 664 | placed. */ |
114cbee6 | 665 | |
1c384bf1 RH |
666 | static void |
667 | get_asm_operands_in_out (rtx body, int *pout, int *pin) | |
114cbee6 | 668 | { |
1c384bf1 RH |
669 | rtx asmop = extract_asm_operands (body); |
670 | ||
671 | *pin = ASM_OPERANDS_INPUT_LENGTH (asmop); | |
672 | *pout = (recog_data.n_operands | |
673 | - ASM_OPERANDS_INPUT_LENGTH (asmop) | |
674 | - ASM_OPERANDS_LABEL_LENGTH (asmop)); | |
114cbee6 | 675 | } |
0ab759e4 | 676 | |
96237362 | 677 | /* If current function returns its result in an fp stack register, |
9f9ed50a | 678 | return the REG. Otherwise, return 0. */ |
96237362 | 679 | |
99a59310 | 680 | static rtx |
0c20a65f | 681 | stack_result (tree decl) |
96237362 | 682 | { |
f099b1c9 | 683 | rtx result; |
96237362 | 684 | |
f099b1c9 JL |
685 | /* If the value is supposed to be returned in memory, then clearly |
686 | it is not returned in a stack register. */ | |
61f71b34 | 687 | if (aggregate_value_p (DECL_RESULT (decl), decl)) |
f099b1c9 JL |
688 | return 0; |
689 | ||
19e7881c | 690 | result = DECL_RTL_IF_SET (DECL_RESULT (decl)); |
9cf218a3 | 691 | if (result != 0) |
1d636cc6 RG |
692 | result = targetm.calls.function_value (TREE_TYPE (DECL_RESULT (decl)), |
693 | decl, true); | |
96237362 | 694 | |
9f9ed50a | 695 | return result != 0 && STACK_REG_P (result) ? result : 0; |
96237362 | 696 | } |
48227150 | 697 | \f |
48227150 | 698 | |
e075ae69 RH |
699 | /* |
700 | * This section deals with stack register substitution, and forms the second | |
701 | * pass over the RTL. | |
702 | */ | |
48227150 JVA |
703 | |
704 | /* Replace REG, which is a pointer to a stack reg RTX, with an RTX for | |
0f41302f | 705 | the desired hard REGNO. */ |
48227150 JVA |
706 | |
707 | static void | |
0c20a65f | 708 | replace_reg (rtx *reg, int regno) |
48227150 | 709 | { |
8dde5924 | 710 | gcc_assert (IN_RANGE (regno, FIRST_STACK_REG, LAST_STACK_REG)); |
41374e13 | 711 | gcc_assert (STACK_REG_P (*reg)); |
48227150 | 712 | |
3d8bf70f | 713 | gcc_assert (SCALAR_FLOAT_MODE_P (GET_MODE (*reg)) |
41374e13 | 714 | || GET_MODE_CLASS (GET_MODE (*reg)) == MODE_COMPLEX_FLOAT); |
7d0e3dd4 | 715 | |
99a59310 | 716 | *reg = FP_MODE_REG (regno, GET_MODE (*reg)); |
48227150 JVA |
717 | } |
718 | ||
719 | /* Remove a note of type NOTE, which must be found, for register | |
0f41302f | 720 | number REGNO from INSN. Remove only one such note. */ |
48227150 JVA |
721 | |
722 | static void | |
d8aeaba0 | 723 | remove_regno_note (rtx_insn *insn, enum reg_note note, unsigned int regno) |
48227150 | 724 | { |
d858f359 | 725 | rtx *note_link, this_rtx; |
48227150 | 726 | |
8e2e89f7 | 727 | note_link = ®_NOTES (insn); |
d858f359 KG |
728 | for (this_rtx = *note_link; this_rtx; this_rtx = XEXP (this_rtx, 1)) |
729 | if (REG_NOTE_KIND (this_rtx) == note | |
730 | && REG_P (XEXP (this_rtx, 0)) && REGNO (XEXP (this_rtx, 0)) == regno) | |
48227150 | 731 | { |
d858f359 | 732 | *note_link = XEXP (this_rtx, 1); |
48227150 JVA |
733 | return; |
734 | } | |
735 | else | |
d858f359 | 736 | note_link = &XEXP (this_rtx, 1); |
48227150 | 737 | |
41374e13 | 738 | gcc_unreachable (); |
48227150 JVA |
739 | } |
740 | ||
741 | /* Find the hard register number of virtual register REG in REGSTACK. | |
742 | The hard register number is relative to the top of the stack. -1 is | |
0f41302f | 743 | returned if the register is not found. */ |
48227150 JVA |
744 | |
745 | static int | |
0823efed | 746 | get_hard_regnum (stack_ptr regstack, rtx reg) |
48227150 JVA |
747 | { |
748 | int i; | |
749 | ||
41374e13 | 750 | gcc_assert (STACK_REG_P (reg)); |
48227150 JVA |
751 | |
752 | for (i = regstack->top; i >= 0; i--) | |
753 | if (regstack->reg[i] == REGNO (reg)) | |
754 | break; | |
755 | ||
756 | return i >= 0 ? (FIRST_STACK_REG + regstack->top - i) : -1; | |
757 | } | |
48227150 JVA |
758 | \f |
759 | /* Emit an insn to pop virtual register REG before or after INSN. | |
760 | REGSTACK is the stack state after INSN and is updated to reflect this | |
e075ae69 RH |
761 | pop. WHEN is either emit_insn_before or emit_insn_after. A pop insn |
762 | is represented as a SET whose destination is the register to be popped | |
763 | and source is the top of stack. A death note for the top of stack | |
0f41302f | 764 | cases the movdf pattern to pop. */ |
48227150 | 765 | |
d8aeaba0 DM |
766 | static rtx_insn * |
767 | emit_pop_insn (rtx_insn *insn, stack_ptr regstack, rtx reg, enum emit_where where) | |
48227150 | 768 | { |
d8aeaba0 DM |
769 | rtx_insn *pop_insn; |
770 | rtx pop_rtx; | |
48227150 JVA |
771 | int hard_regno; |
772 | ||
037f20f1 JH |
773 | /* For complex types take care to pop both halves. These may survive in |
774 | CLOBBER and USE expressions. */ | |
775 | if (COMPLEX_MODE_P (GET_MODE (reg))) | |
776 | { | |
777 | rtx reg1 = FP_MODE_REG (REGNO (reg), DFmode); | |
778 | rtx reg2 = FP_MODE_REG (REGNO (reg) + 1, DFmode); | |
779 | ||
d8aeaba0 | 780 | pop_insn = NULL; |
037f20f1 | 781 | if (get_hard_regnum (regstack, reg1) >= 0) |
a6a2274a | 782 | pop_insn = emit_pop_insn (insn, regstack, reg1, where); |
037f20f1 | 783 | if (get_hard_regnum (regstack, reg2) >= 0) |
a6a2274a | 784 | pop_insn = emit_pop_insn (insn, regstack, reg2, where); |
41374e13 | 785 | gcc_assert (pop_insn); |
037f20f1 JH |
786 | return pop_insn; |
787 | } | |
788 | ||
48227150 JVA |
789 | hard_regno = get_hard_regnum (regstack, reg); |
790 | ||
41374e13 | 791 | gcc_assert (hard_regno >= FIRST_STACK_REG); |
48227150 | 792 | |
f7df4a84 | 793 | pop_rtx = gen_rtx_SET (FP_MODE_REG (hard_regno, DFmode), |
e075ae69 | 794 | FP_MODE_REG (FIRST_STACK_REG, DFmode)); |
48227150 | 795 | |
a05924f9 | 796 | if (where == EMIT_AFTER) |
3c030e88 | 797 | pop_insn = emit_insn_after (pop_rtx, insn); |
a05924f9 | 798 | else |
3c030e88 | 799 | pop_insn = emit_insn_before (pop_rtx, insn); |
48227150 | 800 | |
65c5f2a6 | 801 | add_reg_note (pop_insn, REG_DEAD, FP_MODE_REG (FIRST_STACK_REG, DFmode)); |
48227150 JVA |
802 | |
803 | regstack->reg[regstack->top - (hard_regno - FIRST_STACK_REG)] | |
804 | = regstack->reg[regstack->top]; | |
805 | regstack->top -= 1; | |
806 | CLEAR_HARD_REG_BIT (regstack->reg_set, REGNO (reg)); | |
807 | ||
808 | return pop_insn; | |
809 | } | |
810 | \f | |
a05924f9 JH |
811 | /* Emit an insn before or after INSN to swap virtual register REG with |
812 | the top of stack. REGSTACK is the stack state before the swap, and | |
813 | is updated to reflect the swap. A swap insn is represented as a | |
814 | PARALLEL of two patterns: each pattern moves one reg to the other. | |
48227150 | 815 | |
0f41302f | 816 | If REG is already at the top of the stack, no insn is emitted. */ |
48227150 JVA |
817 | |
818 | static void | |
d8aeaba0 | 819 | emit_swap_insn (rtx_insn *insn, stack_ptr regstack, rtx reg) |
48227150 | 820 | { |
eca31501 | 821 | int hard_regno; |
a05924f9 | 822 | rtx swap_rtx; |
fab27f52 | 823 | int other_reg; /* swap regno temps */ |
d8aeaba0 | 824 | rtx_insn *i1; /* the stack-reg insn prior to INSN */ |
eca31501 | 825 | rtx i1set = NULL_RTX; /* the SET rtx within I1 */ |
48227150 | 826 | |
eca31501 JVA |
827 | hard_regno = get_hard_regnum (regstack, reg); |
828 | ||
48227150 JVA |
829 | if (hard_regno == FIRST_STACK_REG) |
830 | return; | |
7476f086 RH |
831 | if (hard_regno == -1) |
832 | { | |
833 | /* Something failed if the register wasn't on the stack. If we had | |
834 | malformed asms, we zapped the instruction itself, but that didn't | |
835 | produce the same pattern of register sets as before. To prevent | |
836 | further failure, adjust REGSTACK to include REG at TOP. */ | |
837 | gcc_assert (any_malformed_asm); | |
838 | regstack->reg[++regstack->top] = REGNO (reg); | |
839 | return; | |
840 | } | |
841 | gcc_assert (hard_regno >= FIRST_STACK_REG); | |
48227150 | 842 | |
eca31501 | 843 | other_reg = regstack->top - (hard_regno - FIRST_STACK_REG); |
fab27f52 | 844 | std::swap (regstack->reg[regstack->top], regstack->reg[other_reg]); |
48227150 | 845 | |
a05924f9 JH |
846 | /* Find the previous insn involving stack regs, but don't pass a |
847 | block boundary. */ | |
848 | i1 = NULL; | |
a813c111 | 849 | if (current_block && insn != BB_HEAD (current_block)) |
eca31501 | 850 | { |
d8aeaba0 DM |
851 | rtx_insn *tmp = PREV_INSN (insn); |
852 | rtx_insn *limit = PREV_INSN (BB_HEAD (current_block)); | |
3a6cc978 | 853 | while (tmp != limit) |
a05924f9 | 854 | { |
4b4bf941 JQ |
855 | if (LABEL_P (tmp) |
856 | || CALL_P (tmp) | |
589ca5cb | 857 | || NOTE_INSN_BASIC_BLOCK_P (tmp) |
4b4bf941 | 858 | || (NONJUMP_INSN_P (tmp) |
a05924f9 JH |
859 | && stack_regs_mentioned (tmp))) |
860 | { | |
861 | i1 = tmp; | |
862 | break; | |
863 | } | |
864 | tmp = PREV_INSN (tmp); | |
865 | } | |
866 | } | |
867 | ||
868 | if (i1 != NULL_RTX | |
869 | && (i1set = single_set (i1)) != NULL_RTX) | |
870 | { | |
871 | rtx i1src = *get_true_reg (&SET_SRC (i1set)); | |
eca31501 | 872 | rtx i1dest = *get_true_reg (&SET_DEST (i1set)); |
48227150 | 873 | |
eca31501 | 874 | /* If the previous register stack push was from the reg we are to |
0f41302f | 875 | swap with, omit the swap. */ |
eca31501 | 876 | |
f8cfc6aa JQ |
877 | if (REG_P (i1dest) && REGNO (i1dest) == FIRST_STACK_REG |
878 | && REG_P (i1src) | |
ae0ed63a | 879 | && REGNO (i1src) == (unsigned) hard_regno - 1 |
eca31501 JVA |
880 | && find_regno_note (i1, REG_DEAD, FIRST_STACK_REG) == NULL_RTX) |
881 | return; | |
882 | ||
883 | /* If the previous insn wrote to the reg we are to swap with, | |
884 | omit the swap. */ | |
885 | ||
f8cfc6aa JQ |
886 | if (REG_P (i1dest) && REGNO (i1dest) == (unsigned) hard_regno |
887 | && REG_P (i1src) && REGNO (i1src) == FIRST_STACK_REG | |
eca31501 JVA |
888 | && find_regno_note (i1, REG_DEAD, FIRST_STACK_REG) == NULL_RTX) |
889 | return; | |
890 | } | |
891 | ||
385e0e08 RS |
892 | /* Avoid emitting the swap if this is the first register stack insn |
893 | of the current_block. Instead update the current_block's stack_in | |
894 | and let compensate edges take care of this for us. */ | |
895 | if (current_block && starting_stack_p) | |
896 | { | |
897 | BLOCK_INFO (current_block)->stack_in = *regstack; | |
898 | starting_stack_p = false; | |
899 | return; | |
900 | } | |
901 | ||
e075ae69 RH |
902 | swap_rtx = gen_swapxf (FP_MODE_REG (hard_regno, XFmode), |
903 | FP_MODE_REG (FIRST_STACK_REG, XFmode)); | |
a05924f9 JH |
904 | |
905 | if (i1) | |
3c030e88 | 906 | emit_insn_after (swap_rtx, i1); |
a05924f9 | 907 | else if (current_block) |
a813c111 | 908 | emit_insn_before (swap_rtx, BB_HEAD (current_block)); |
a05924f9 JH |
909 | else |
910 | emit_insn_before (swap_rtx, insn); | |
48227150 JVA |
911 | } |
912 | \f | |
f964bd29 UB |
913 | /* Emit an insns before INSN to swap virtual register SRC1 with |
914 | the top of stack and virtual register SRC2 with second stack | |
915 | slot. REGSTACK is the stack state before the swaps, and | |
916 | is updated to reflect the swaps. A swap insn is represented as a | |
917 | PARALLEL of two patterns: each pattern moves one reg to the other. | |
918 | ||
919 | If SRC1 and/or SRC2 are already at the right place, no swap insn | |
920 | is emitted. */ | |
921 | ||
922 | static void | |
d8aeaba0 | 923 | swap_to_top (rtx_insn *insn, stack_ptr regstack, rtx src1, rtx src2) |
f964bd29 UB |
924 | { |
925 | struct stack_def temp_stack; | |
fab27f52 | 926 | int regno, j, k; |
f964bd29 UB |
927 | |
928 | temp_stack = *regstack; | |
929 | ||
930 | /* Place operand 1 at the top of stack. */ | |
931 | regno = get_hard_regnum (&temp_stack, src1); | |
41374e13 | 932 | gcc_assert (regno >= 0); |
f964bd29 UB |
933 | if (regno != FIRST_STACK_REG) |
934 | { | |
935 | k = temp_stack.top - (regno - FIRST_STACK_REG); | |
936 | j = temp_stack.top; | |
937 | ||
fab27f52 | 938 | std::swap (temp_stack.reg[j], temp_stack.reg[k]); |
f964bd29 UB |
939 | } |
940 | ||
941 | /* Place operand 2 next on the stack. */ | |
942 | regno = get_hard_regnum (&temp_stack, src2); | |
41374e13 | 943 | gcc_assert (regno >= 0); |
f964bd29 UB |
944 | if (regno != FIRST_STACK_REG + 1) |
945 | { | |
946 | k = temp_stack.top - (regno - FIRST_STACK_REG); | |
947 | j = temp_stack.top - 1; | |
948 | ||
fab27f52 | 949 | std::swap (temp_stack.reg[j], temp_stack.reg[k]); |
f964bd29 UB |
950 | } |
951 | ||
952 | change_stack (insn, regstack, &temp_stack, EMIT_BEFORE); | |
953 | } | |
954 | \f | |
48227150 | 955 | /* Handle a move to or from a stack register in PAT, which is in INSN. |
ecb63641 EB |
956 | REGSTACK is the current stack. Return whether a control flow insn |
957 | was deleted in the process. */ | |
48227150 | 958 | |
ecb63641 | 959 | static bool |
d8aeaba0 | 960 | move_for_stack_reg (rtx_insn *insn, stack_ptr regstack, rtx pat) |
48227150 | 961 | { |
99a59310 RK |
962 | rtx *psrc = get_true_reg (&SET_SRC (pat)); |
963 | rtx *pdest = get_true_reg (&SET_DEST (pat)); | |
964 | rtx src, dest; | |
48227150 | 965 | rtx note; |
ecb63641 | 966 | bool control_flow_insn_deleted = false; |
48227150 | 967 | |
99a59310 RK |
968 | src = *psrc; dest = *pdest; |
969 | ||
970 | if (STACK_REG_P (src) && STACK_REG_P (dest)) | |
48227150 JVA |
971 | { |
972 | /* Write from one stack reg to another. If SRC dies here, then | |
0f41302f | 973 | just change the register mapping and delete the insn. */ |
48227150 | 974 | |
99a59310 | 975 | note = find_regno_note (insn, REG_DEAD, REGNO (src)); |
48227150 JVA |
976 | if (note) |
977 | { | |
978 | int i; | |
979 | ||
0f41302f | 980 | /* If this is a no-op move, there must not be a REG_DEAD note. */ |
41374e13 | 981 | gcc_assert (REGNO (src) != REGNO (dest)); |
48227150 JVA |
982 | |
983 | for (i = regstack->top; i >= 0; i--) | |
99a59310 | 984 | if (regstack->reg[i] == REGNO (src)) |
48227150 JVA |
985 | break; |
986 | ||
5ad85f7d | 987 | /* The destination must be dead, or life analysis is borked. */ |
41374e13 | 988 | gcc_assert (get_hard_regnum (regstack, dest) < FIRST_STACK_REG); |
48227150 | 989 | |
5ad85f7d RH |
990 | /* If the source is not live, this is yet another case of |
991 | uninitialized variables. Load up a NaN instead. */ | |
992 | if (i < 0) | |
993 | return move_nan_for_stack_reg (insn, regstack, dest); | |
994 | ||
48227150 | 995 | /* It is possible that the dest is unused after this insn. |
0f41302f | 996 | If so, just pop the src. */ |
48227150 | 997 | |
99a59310 | 998 | if (find_regno_note (insn, REG_UNUSED, REGNO (dest))) |
ecb63641 EB |
999 | emit_pop_insn (insn, regstack, src, EMIT_AFTER); |
1000 | else | |
48227150 | 1001 | { |
ecb63641 EB |
1002 | regstack->reg[i] = REGNO (dest); |
1003 | SET_HARD_REG_BIT (regstack->reg_set, REGNO (dest)); | |
1004 | CLEAR_HARD_REG_BIT (regstack->reg_set, REGNO (src)); | |
48227150 JVA |
1005 | } |
1006 | ||
ecb63641 | 1007 | control_flow_insn_deleted |= control_flow_insn_p (insn); |
53c17031 | 1008 | delete_insn (insn); |
ecb63641 | 1009 | return control_flow_insn_deleted; |
48227150 JVA |
1010 | } |
1011 | ||
0f41302f | 1012 | /* The source reg does not die. */ |
48227150 JVA |
1013 | |
1014 | /* If this appears to be a no-op move, delete it, or else it | |
1015 | will confuse the machine description output patterns. But if | |
1016 | it is REG_UNUSED, we must pop the reg now, as per-insn processing | |
0f41302f | 1017 | for REG_UNUSED will not work for deleted insns. */ |
48227150 | 1018 | |
99a59310 | 1019 | if (REGNO (src) == REGNO (dest)) |
48227150 | 1020 | { |
99a59310 | 1021 | if (find_regno_note (insn, REG_UNUSED, REGNO (dest))) |
a05924f9 | 1022 | emit_pop_insn (insn, regstack, dest, EMIT_AFTER); |
48227150 | 1023 | |
ecb63641 | 1024 | control_flow_insn_deleted |= control_flow_insn_p (insn); |
53c17031 | 1025 | delete_insn (insn); |
ecb63641 | 1026 | return control_flow_insn_deleted; |
48227150 JVA |
1027 | } |
1028 | ||
3eae4643 | 1029 | /* The destination ought to be dead. */ |
41374e13 | 1030 | gcc_assert (get_hard_regnum (regstack, dest) < FIRST_STACK_REG); |
48227150 | 1031 | |
99a59310 | 1032 | replace_reg (psrc, get_hard_regnum (regstack, src)); |
48227150 | 1033 | |
99a59310 RK |
1034 | regstack->reg[++regstack->top] = REGNO (dest); |
1035 | SET_HARD_REG_BIT (regstack->reg_set, REGNO (dest)); | |
1036 | replace_reg (pdest, FIRST_STACK_REG); | |
48227150 | 1037 | } |
99a59310 | 1038 | else if (STACK_REG_P (src)) |
48227150 JVA |
1039 | { |
1040 | /* Save from a stack reg to MEM, or possibly integer reg. Since | |
1041 | only top of stack may be saved, emit an exchange first if | |
0f41302f | 1042 | needs be. */ |
48227150 | 1043 | |
99a59310 | 1044 | emit_swap_insn (insn, regstack, src); |
48227150 | 1045 | |
99a59310 | 1046 | note = find_regno_note (insn, REG_DEAD, REGNO (src)); |
48227150 JVA |
1047 | if (note) |
1048 | { | |
1049 | replace_reg (&XEXP (note, 0), FIRST_STACK_REG); | |
1050 | regstack->top--; | |
99a59310 | 1051 | CLEAR_HARD_REG_BIT (regstack->reg_set, REGNO (src)); |
48227150 | 1052 | } |
f8a1ebc6 | 1053 | else if ((GET_MODE (src) == XFmode) |
cadcffb3 | 1054 | && regstack->top < REG_STACK_SIZE - 1) |
b40b8b06 JVA |
1055 | { |
1056 | /* A 387 cannot write an XFmode value to a MEM without | |
1057 | clobbering the source reg. The output code can handle | |
1058 | this by reading back the value from the MEM. | |
1059 | But it is more efficient to use a temp register if one is | |
1060 | available. Push the source value here if the register | |
1061 | stack is not full, and then write the value to memory via | |
1062 | a pop. */ | |
f7448d50 | 1063 | rtx push_rtx; |
037f20f1 | 1064 | rtx top_stack_reg = FP_MODE_REG (FIRST_STACK_REG, GET_MODE (src)); |
b40b8b06 | 1065 | |
f8a1ebc6 | 1066 | push_rtx = gen_movxf (top_stack_reg, top_stack_reg); |
f7448d50 | 1067 | emit_insn_before (push_rtx, insn); |
65c5f2a6 | 1068 | add_reg_note (insn, REG_DEAD, top_stack_reg); |
b40b8b06 | 1069 | } |
48227150 | 1070 | |
99a59310 | 1071 | replace_reg (psrc, FIRST_STACK_REG); |
48227150 | 1072 | } |
41374e13 | 1073 | else |
48227150 | 1074 | { |
d85c7550 UB |
1075 | rtx pat = PATTERN (insn); |
1076 | ||
41374e13 NS |
1077 | gcc_assert (STACK_REG_P (dest)); |
1078 | ||
48227150 JVA |
1079 | /* Load from MEM, or possibly integer REG or constant, into the |
1080 | stack regs. The actual target is always the top of the | |
1081 | stack. The stack mapping is changed to reflect that DEST is | |
1082 | now at top of stack. */ | |
1083 | ||
d85c7550 UB |
1084 | /* The destination ought to be dead. However, there is a |
1085 | special case with i387 UNSPEC_TAN, where destination is live | |
1086 | (an argument to fptan) but inherent load of 1.0 is modelled | |
1087 | as a load from a constant. */ | |
590e9a42 UB |
1088 | if (GET_CODE (pat) == PARALLEL |
1089 | && XVECLEN (pat, 0) == 2 | |
1090 | && GET_CODE (XVECEXP (pat, 0, 1)) == SET | |
1091 | && GET_CODE (SET_SRC (XVECEXP (pat, 0, 1))) == UNSPEC | |
1092 | && XINT (SET_SRC (XVECEXP (pat, 0, 1)), 1) == UNSPEC_TAN) | |
1093 | emit_swap_insn (insn, regstack, dest); | |
1094 | else | |
d85c7550 | 1095 | gcc_assert (get_hard_regnum (regstack, dest) < FIRST_STACK_REG); |
48227150 | 1096 | |
41374e13 | 1097 | gcc_assert (regstack->top < REG_STACK_SIZE); |
48227150 | 1098 | |
99a59310 RK |
1099 | regstack->reg[++regstack->top] = REGNO (dest); |
1100 | SET_HARD_REG_BIT (regstack->reg_set, REGNO (dest)); | |
1101 | replace_reg (pdest, FIRST_STACK_REG); | |
48227150 | 1102 | } |
ecb63641 EB |
1103 | |
1104 | return control_flow_insn_deleted; | |
48227150 | 1105 | } |
5ad85f7d RH |
1106 | |
1107 | /* A helper function which replaces INSN with a pattern that loads up | |
1108 | a NaN into DEST, then invokes move_for_stack_reg. */ | |
1109 | ||
1110 | static bool | |
d8aeaba0 | 1111 | move_nan_for_stack_reg (rtx_insn *insn, stack_ptr regstack, rtx dest) |
5ad85f7d RH |
1112 | { |
1113 | rtx pat; | |
1114 | ||
1115 | dest = FP_MODE_REG (REGNO (dest), SFmode); | |
f7df4a84 | 1116 | pat = gen_rtx_SET (dest, not_a_num); |
5ad85f7d RH |
1117 | PATTERN (insn) = pat; |
1118 | INSN_CODE (insn) = -1; | |
1119 | ||
1120 | return move_for_stack_reg (insn, regstack, pat); | |
1121 | } | |
48227150 | 1122 | \f |
e075ae69 RH |
1123 | /* Swap the condition on a branch, if there is one. Return true if we |
1124 | found a condition to swap. False if the condition was not used as | |
dc297297 | 1125 | such. */ |
e075ae69 RH |
1126 | |
1127 | static int | |
0c20a65f | 1128 | swap_rtx_condition_1 (rtx pat) |
eca31501 | 1129 | { |
b3694847 SS |
1130 | const char *fmt; |
1131 | int i, r = 0; | |
eca31501 | 1132 | |
ec8e098d | 1133 | if (COMPARISON_P (pat)) |
eca31501 JVA |
1134 | { |
1135 | PUT_CODE (pat, swap_condition (GET_CODE (pat))); | |
e075ae69 | 1136 | r = 1; |
eca31501 | 1137 | } |
e075ae69 | 1138 | else |
eca31501 | 1139 | { |
e075ae69 RH |
1140 | fmt = GET_RTX_FORMAT (GET_CODE (pat)); |
1141 | for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0; i--) | |
eca31501 | 1142 | { |
e075ae69 RH |
1143 | if (fmt[i] == 'E') |
1144 | { | |
b3694847 | 1145 | int j; |
eca31501 | 1146 | |
e075ae69 RH |
1147 | for (j = XVECLEN (pat, i) - 1; j >= 0; j--) |
1148 | r |= swap_rtx_condition_1 (XVECEXP (pat, i, j)); | |
1149 | } | |
1150 | else if (fmt[i] == 'e') | |
1151 | r |= swap_rtx_condition_1 (XEXP (pat, i)); | |
eca31501 | 1152 | } |
eca31501 | 1153 | } |
e075ae69 RH |
1154 | |
1155 | return r; | |
1156 | } | |
1157 | ||
1158 | static int | |
d8aeaba0 | 1159 | swap_rtx_condition (rtx_insn *insn) |
e075ae69 RH |
1160 | { |
1161 | rtx pat = PATTERN (insn); | |
1162 | ||
1163 | /* We're looking for a single set to cc0 or an HImode temporary. */ | |
1164 | ||
1165 | if (GET_CODE (pat) == SET | |
f8cfc6aa | 1166 | && REG_P (SET_DEST (pat)) |
e075ae69 RH |
1167 | && REGNO (SET_DEST (pat)) == FLAGS_REG) |
1168 | { | |
1169 | insn = next_flags_user (insn); | |
1170 | if (insn == NULL_RTX) | |
1171 | return 0; | |
1172 | pat = PATTERN (insn); | |
1173 | } | |
1174 | ||
383898f7 JJ |
1175 | /* See if this is, or ends in, a fnstsw. If so, we're not doing anything |
1176 | with the cc value right now. We may be able to search for one | |
1177 | though. */ | |
e075ae69 RH |
1178 | |
1179 | if (GET_CODE (pat) == SET | |
1180 | && GET_CODE (SET_SRC (pat)) == UNSPEC | |
35a76aac | 1181 | && XINT (SET_SRC (pat), 1) == UNSPEC_FNSTSW) |
e075ae69 RH |
1182 | { |
1183 | rtx dest = SET_DEST (pat); | |
1184 | ||
a6a2274a | 1185 | /* Search forward looking for the first use of this value. |
e075ae69 | 1186 | Stop at block boundaries. */ |
a813c111 | 1187 | while (insn != BB_END (current_block)) |
e075ae69 RH |
1188 | { |
1189 | insn = NEXT_INSN (insn); | |
2c3c49de | 1190 | if (INSN_P (insn) && reg_mentioned_p (dest, insn)) |
e075ae69 | 1191 | break; |
4b4bf941 | 1192 | if (CALL_P (insn)) |
e075ae69 RH |
1193 | return 0; |
1194 | } | |
1195 | ||
383898f7 JJ |
1196 | /* We haven't found it. */ |
1197 | if (insn == BB_END (current_block)) | |
1198 | return 0; | |
1199 | ||
e075ae69 | 1200 | /* So we've found the insn using this value. If it is anything |
383898f7 JJ |
1201 | other than sahf or the value does not die (meaning we'd have |
1202 | to search further), then we must give up. */ | |
e075ae69 RH |
1203 | pat = PATTERN (insn); |
1204 | if (GET_CODE (pat) != SET | |
1205 | || GET_CODE (SET_SRC (pat)) != UNSPEC | |
35a76aac | 1206 | || XINT (SET_SRC (pat), 1) != UNSPEC_SAHF |
e075ae69 RH |
1207 | || ! dead_or_set_p (insn, dest)) |
1208 | return 0; | |
1209 | ||
1210 | /* Now we are prepared to handle this as a normal cc0 setter. */ | |
1211 | insn = next_flags_user (insn); | |
1212 | if (insn == NULL_RTX) | |
1213 | return 0; | |
1214 | pat = PATTERN (insn); | |
1215 | } | |
1216 | ||
90a74703 JH |
1217 | if (swap_rtx_condition_1 (pat)) |
1218 | { | |
0eac0e81 | 1219 | int fail = 0; |
90a74703 JH |
1220 | INSN_CODE (insn) = -1; |
1221 | if (recog_memoized (insn) == -1) | |
0eac0e81 JH |
1222 | fail = 1; |
1223 | /* In case the flags don't die here, recurse to try fix | |
1224 | following user too. */ | |
1225 | else if (! dead_or_set_p (insn, ix86_flags_rtx)) | |
1226 | { | |
1227 | insn = next_flags_user (insn); | |
1228 | if (!insn || !swap_rtx_condition (insn)) | |
1229 | fail = 1; | |
1230 | } | |
1231 | if (fail) | |
90a74703 JH |
1232 | { |
1233 | swap_rtx_condition_1 (pat); | |
1234 | return 0; | |
1235 | } | |
1236 | return 1; | |
1237 | } | |
1238 | return 0; | |
eca31501 JVA |
1239 | } |
1240 | ||
48227150 JVA |
1241 | /* Handle a comparison. Special care needs to be taken to avoid |
1242 | causing comparisons that a 387 cannot do correctly, such as EQ. | |
1243 | ||
e075ae69 | 1244 | Also, a pop insn may need to be emitted. The 387 does have an |
48227150 JVA |
1245 | `fcompp' insn that can pop two regs, but it is sometimes too expensive |
1246 | to do this - a `fcomp' followed by a `fstpl %st(0)' may be easier to | |
e075ae69 | 1247 | set up. */ |
48227150 JVA |
1248 | |
1249 | static void | |
d8aeaba0 | 1250 | compare_for_stack_reg (rtx_insn *insn, stack_ptr regstack, rtx pat_src) |
48227150 JVA |
1251 | { |
1252 | rtx *src1, *src2; | |
1253 | rtx src1_note, src2_note; | |
914ec131 | 1254 | |
e075ae69 RH |
1255 | src1 = get_true_reg (&XEXP (pat_src, 0)); |
1256 | src2 = get_true_reg (&XEXP (pat_src, 1)); | |
48227150 | 1257 | |
eca31501 | 1258 | /* ??? If fxch turns out to be cheaper than fstp, give priority to |
0f41302f | 1259 | registers that die in this insn - move those to stack top first. */ |
e075ae69 RH |
1260 | if ((! STACK_REG_P (*src1) |
1261 | || (STACK_REG_P (*src2) | |
1262 | && get_hard_regnum (regstack, *src2) == FIRST_STACK_REG)) | |
1263 | && swap_rtx_condition (insn)) | |
eca31501 | 1264 | { |
fab27f52 | 1265 | std::swap (XEXP (pat_src, 0), XEXP (pat_src, 1)); |
48227150 | 1266 | |
e075ae69 RH |
1267 | src1 = get_true_reg (&XEXP (pat_src, 0)); |
1268 | src2 = get_true_reg (&XEXP (pat_src, 1)); | |
dc78213e | 1269 | |
b9342cdf | 1270 | INSN_CODE (insn) = -1; |
eca31501 | 1271 | } |
48227150 | 1272 | |
0f41302f | 1273 | /* We will fix any death note later. */ |
48227150 JVA |
1274 | |
1275 | src1_note = find_regno_note (insn, REG_DEAD, REGNO (*src1)); | |
1276 | ||
1277 | if (STACK_REG_P (*src2)) | |
1278 | src2_note = find_regno_note (insn, REG_DEAD, REGNO (*src2)); | |
1279 | else | |
eca31501 | 1280 | src2_note = NULL_RTX; |
48227150 | 1281 | |
e075ae69 | 1282 | emit_swap_insn (insn, regstack, *src1); |
48227150 JVA |
1283 | |
1284 | replace_reg (src1, FIRST_STACK_REG); | |
1285 | ||
1286 | if (STACK_REG_P (*src2)) | |
e075ae69 | 1287 | replace_reg (src2, get_hard_regnum (regstack, *src2)); |
48227150 JVA |
1288 | |
1289 | if (src1_note) | |
1290 | { | |
7aa74e4c | 1291 | pop_stack (regstack, REGNO (XEXP (src1_note, 0))); |
48227150 | 1292 | replace_reg (&XEXP (src1_note, 0), FIRST_STACK_REG); |
48227150 JVA |
1293 | } |
1294 | ||
1295 | /* If the second operand dies, handle that. But if the operands are | |
1296 | the same stack register, don't bother, because only one death is | |
0f41302f | 1297 | needed, and it was just handled. */ |
48227150 JVA |
1298 | |
1299 | if (src2_note | |
eca31501 | 1300 | && ! (STACK_REG_P (*src1) && STACK_REG_P (*src2) |
48227150 JVA |
1301 | && REGNO (*src1) == REGNO (*src2))) |
1302 | { | |
1303 | /* As a special case, two regs may die in this insn if src2 is | |
1304 | next to top of stack and the top of stack also dies. Since | |
1305 | we have already popped src1, "next to top of stack" is really | |
0f41302f | 1306 | at top (FIRST_STACK_REG) now. */ |
48227150 JVA |
1307 | |
1308 | if (get_hard_regnum (regstack, XEXP (src2_note, 0)) == FIRST_STACK_REG | |
1309 | && src1_note) | |
1310 | { | |
7aa74e4c | 1311 | pop_stack (regstack, REGNO (XEXP (src2_note, 0))); |
48227150 | 1312 | replace_reg (&XEXP (src2_note, 0), FIRST_STACK_REG + 1); |
48227150 JVA |
1313 | } |
1314 | else | |
1315 | { | |
e075ae69 RH |
1316 | /* The 386 can only represent death of the first operand in |
1317 | the case handled above. In all other cases, emit a separate | |
1318 | pop and remove the death note from here. */ | |
e075ae69 | 1319 | remove_regno_note (insn, REG_DEAD, REGNO (XEXP (src2_note, 0))); |
e075ae69 | 1320 | emit_pop_insn (insn, regstack, XEXP (src2_note, 0), |
a05924f9 | 1321 | EMIT_AFTER); |
48227150 JVA |
1322 | } |
1323 | } | |
1324 | } | |
1325 | \f | |
a7a110bb AO |
1326 | /* Substitute hardware stack regs in debug insn INSN, using stack |
1327 | layout REGSTACK. If we can't find a hardware stack reg for any of | |
1328 | the REGs in it, reset the debug insn. */ | |
1329 | ||
1330 | static void | |
d8aeaba0 | 1331 | subst_all_stack_regs_in_debug_insn (rtx_insn *insn, struct stack_def *regstack) |
a7a110bb | 1332 | { |
6c0cda91 RS |
1333 | subrtx_ptr_iterator::array_type array; |
1334 | FOR_EACH_SUBRTX_PTR (iter, array, &INSN_VAR_LOCATION_LOC (insn), NONCONST) | |
1335 | { | |
1336 | rtx *loc = *iter; | |
1337 | rtx x = *loc; | |
1338 | if (STACK_REG_P (x)) | |
1339 | { | |
1340 | int hard_regno = get_hard_regnum (regstack, x); | |
a7a110bb | 1341 | |
6c0cda91 RS |
1342 | /* If we can't find an active register, reset this debug insn. */ |
1343 | if (hard_regno == -1) | |
1344 | { | |
1345 | INSN_VAR_LOCATION_LOC (insn) = gen_rtx_UNKNOWN_VAR_LOC (); | |
1346 | return; | |
1347 | } | |
1348 | ||
1349 | gcc_assert (hard_regno >= FIRST_STACK_REG); | |
1350 | replace_reg (loc, hard_regno); | |
1351 | iter.skip_subrtxes (); | |
1352 | } | |
1353 | } | |
a7a110bb AO |
1354 | } |
1355 | ||
48227150 | 1356 | /* Substitute new registers in PAT, which is part of INSN. REGSTACK |
ecb63641 EB |
1357 | is the current register layout. Return whether a control flow insn |
1358 | was deleted in the process. */ | |
48227150 | 1359 | |
ecb63641 | 1360 | static bool |
d8aeaba0 | 1361 | subst_stack_regs_pat (rtx_insn *insn, stack_ptr regstack, rtx pat) |
48227150 JVA |
1362 | { |
1363 | rtx *dest, *src; | |
ecb63641 | 1364 | bool control_flow_insn_deleted = false; |
48227150 | 1365 | |
a05924f9 JH |
1366 | switch (GET_CODE (pat)) |
1367 | { | |
1368 | case USE: | |
1369 | /* Deaths in USE insns can happen in non optimizing compilation. | |
1370 | Handle them by popping the dying register. */ | |
1371 | src = get_true_reg (&XEXP (pat, 0)); | |
a6a2274a KH |
1372 | if (STACK_REG_P (*src) |
1373 | && find_regno_note (insn, REG_DEAD, REGNO (*src))) | |
1374 | { | |
6fb5fa3c DB |
1375 | /* USEs are ignored for liveness information so USEs of dead |
1376 | register might happen. */ | |
1377 | if (TEST_HARD_REG_BIT (regstack->reg_set, REGNO (*src))) | |
1378 | emit_pop_insn (insn, regstack, *src, EMIT_AFTER); | |
ecb63641 | 1379 | return control_flow_insn_deleted; |
a6a2274a | 1380 | } |
6fb5fa3c DB |
1381 | /* Uninitialized USE might happen for functions returning uninitialized |
1382 | value. We will properly initialize the USE on the edge to EXIT_BLOCK, | |
cea618ac | 1383 | so it is safe to ignore the use here. This is consistent with behavior |
b8698a0f | 1384 | of dataflow analyzer that ignores USE too. (This also imply that |
cea618ac | 1385 | forcibly initializing the register to NaN here would lead to ICE later, |
6fb5fa3c | 1386 | since the REG_DEAD notes are not issued.) */ |
a05924f9 | 1387 | break; |
48227150 | 1388 | |
b5b8b0ac AO |
1389 | case VAR_LOCATION: |
1390 | gcc_unreachable (); | |
1391 | ||
a05924f9 JH |
1392 | case CLOBBER: |
1393 | { | |
1394 | rtx note; | |
48227150 | 1395 | |
a05924f9 JH |
1396 | dest = get_true_reg (&XEXP (pat, 0)); |
1397 | if (STACK_REG_P (*dest)) | |
1398 | { | |
1399 | note = find_reg_note (insn, REG_DEAD, *dest); | |
bd695e1e RH |
1400 | |
1401 | if (pat != PATTERN (insn)) | |
1402 | { | |
83a6ac60 VM |
1403 | /* The fix_truncdi_1 pattern wants to be able to |
1404 | allocate its own scratch register. It does this by | |
1405 | clobbering an fp reg so that it is assured of an | |
1406 | empty reg-stack register. If the register is live, | |
1407 | kill it now. Remove the DEAD/UNUSED note so we | |
1408 | don't try to kill it later too. | |
1409 | ||
1410 | In reality the UNUSED note can be absent in some | |
1411 | complicated cases when the register is reused for | |
1412 | partially set variable. */ | |
bd695e1e RH |
1413 | |
1414 | if (note) | |
1415 | emit_pop_insn (insn, regstack, *dest, EMIT_BEFORE); | |
1416 | else | |
83a6ac60 VM |
1417 | note = find_reg_note (insn, REG_UNUSED, *dest); |
1418 | if (note) | |
1419 | remove_note (insn, note); | |
cb0bc263 | 1420 | replace_reg (dest, FIRST_STACK_REG + 1); |
bd695e1e | 1421 | } |
a05924f9 JH |
1422 | else |
1423 | { | |
bd695e1e RH |
1424 | /* A top-level clobber with no REG_DEAD, and no hard-regnum |
1425 | indicates an uninitialized value. Because reload removed | |
a6a2274a | 1426 | all other clobbers, this must be due to a function |
bd695e1e RH |
1427 | returning without a value. Load up a NaN. */ |
1428 | ||
5ad85f7d | 1429 | if (!note) |
037f20f1 | 1430 | { |
5ad85f7d | 1431 | rtx t = *dest; |
5ad85f7d RH |
1432 | if (COMPLEX_MODE_P (GET_MODE (t))) |
1433 | { | |
190e9534 PB |
1434 | rtx u = FP_MODE_REG (REGNO (t) + 1, SFmode); |
1435 | if (get_hard_regnum (regstack, u) == -1) | |
1436 | { | |
1437 | rtx pat2 = gen_rtx_CLOBBER (VOIDmode, u); | |
d8aeaba0 | 1438 | rtx_insn *insn2 = emit_insn_before (pat2, insn); |
190e9534 PB |
1439 | control_flow_insn_deleted |
1440 | |= move_nan_for_stack_reg (insn2, regstack, u); | |
1441 | } | |
5ad85f7d | 1442 | } |
190e9534 PB |
1443 | if (get_hard_regnum (regstack, t) == -1) |
1444 | control_flow_insn_deleted | |
1445 | |= move_nan_for_stack_reg (insn, regstack, t); | |
037f20f1 | 1446 | } |
a05924f9 | 1447 | } |
a05924f9 | 1448 | } |
48227150 | 1449 | break; |
a05924f9 | 1450 | } |
48227150 | 1451 | |
a05924f9 JH |
1452 | case SET: |
1453 | { | |
6496a589 | 1454 | rtx *src1 = (rtx *) 0, *src2; |
a05924f9 JH |
1455 | rtx src1_note, src2_note; |
1456 | rtx pat_src; | |
1457 | ||
1458 | dest = get_true_reg (&SET_DEST (pat)); | |
1459 | src = get_true_reg (&SET_SRC (pat)); | |
1460 | pat_src = SET_SRC (pat); | |
1461 | ||
1462 | /* See if this is a `movM' pattern, and handle elsewhere if so. */ | |
1463 | if (STACK_REG_P (*src) | |
1464 | || (STACK_REG_P (*dest) | |
3c0cb5de | 1465 | && (REG_P (*src) || MEM_P (*src) |
48175537 | 1466 | || CONST_DOUBLE_P (*src)))) |
a05924f9 | 1467 | { |
ecb63641 | 1468 | control_flow_insn_deleted |= move_for_stack_reg (insn, regstack, pat); |
a05924f9 JH |
1469 | break; |
1470 | } | |
48227150 | 1471 | |
a05924f9 JH |
1472 | switch (GET_CODE (pat_src)) |
1473 | { | |
1474 | case COMPARE: | |
1475 | compare_for_stack_reg (insn, regstack, pat_src); | |
1476 | break; | |
48227150 | 1477 | |
a05924f9 JH |
1478 | case CALL: |
1479 | { | |
1480 | int count; | |
dc8afb70 | 1481 | for (count = REG_NREGS (*dest); --count >= 0;) |
a05924f9 JH |
1482 | { |
1483 | regstack->reg[++regstack->top] = REGNO (*dest) + count; | |
1484 | SET_HARD_REG_BIT (regstack->reg_set, REGNO (*dest) + count); | |
1485 | } | |
1486 | } | |
1487 | replace_reg (dest, FIRST_STACK_REG); | |
1488 | break; | |
48227150 | 1489 | |
a05924f9 JH |
1490 | case REG: |
1491 | /* This is a `tstM2' case. */ | |
41374e13 | 1492 | gcc_assert (*dest == cc0_rtx); |
a05924f9 | 1493 | src1 = src; |
48227150 | 1494 | |
a05924f9 | 1495 | /* Fall through. */ |
48227150 | 1496 | |
a05924f9 JH |
1497 | case FLOAT_TRUNCATE: |
1498 | case SQRT: | |
1499 | case ABS: | |
1500 | case NEG: | |
1501 | /* These insns only operate on the top of the stack. DEST might | |
1502 | be cc0_rtx if we're processing a tstM pattern. Also, it's | |
1503 | possible that the tstM case results in a REG_DEAD note on the | |
1504 | source. */ | |
48227150 | 1505 | |
a05924f9 JH |
1506 | if (src1 == 0) |
1507 | src1 = get_true_reg (&XEXP (pat_src, 0)); | |
48227150 | 1508 | |
a05924f9 | 1509 | emit_swap_insn (insn, regstack, *src1); |
48227150 | 1510 | |
a05924f9 | 1511 | src1_note = find_regno_note (insn, REG_DEAD, REGNO (*src1)); |
48227150 | 1512 | |
a05924f9 JH |
1513 | if (STACK_REG_P (*dest)) |
1514 | replace_reg (dest, FIRST_STACK_REG); | |
48227150 | 1515 | |
a05924f9 JH |
1516 | if (src1_note) |
1517 | { | |
1518 | replace_reg (&XEXP (src1_note, 0), FIRST_STACK_REG); | |
1519 | regstack->top--; | |
1520 | CLEAR_HARD_REG_BIT (regstack->reg_set, REGNO (*src1)); | |
1521 | } | |
48227150 | 1522 | |
a05924f9 JH |
1523 | replace_reg (src1, FIRST_STACK_REG); |
1524 | break; | |
48227150 | 1525 | |
a05924f9 JH |
1526 | case MINUS: |
1527 | case DIV: | |
1528 | /* On i386, reversed forms of subM3 and divM3 exist for | |
1529 | MODE_FLOAT, so the same code that works for addM3 and mulM3 | |
1530 | can be used. */ | |
1531 | case MULT: | |
1532 | case PLUS: | |
1533 | /* These insns can accept the top of stack as a destination | |
1534 | from a stack reg or mem, or can use the top of stack as a | |
1535 | source and some other stack register (possibly top of stack) | |
1536 | as a destination. */ | |
1537 | ||
1538 | src1 = get_true_reg (&XEXP (pat_src, 0)); | |
1539 | src2 = get_true_reg (&XEXP (pat_src, 1)); | |
1540 | ||
1541 | /* We will fix any death note later. */ | |
1542 | ||
1543 | if (STACK_REG_P (*src1)) | |
1544 | src1_note = find_regno_note (insn, REG_DEAD, REGNO (*src1)); | |
1545 | else | |
1546 | src1_note = NULL_RTX; | |
1547 | if (STACK_REG_P (*src2)) | |
1548 | src2_note = find_regno_note (insn, REG_DEAD, REGNO (*src2)); | |
1549 | else | |
1550 | src2_note = NULL_RTX; | |
48227150 | 1551 | |
a05924f9 JH |
1552 | /* If either operand is not a stack register, then the dest |
1553 | must be top of stack. */ | |
48227150 | 1554 | |
a05924f9 | 1555 | if (! STACK_REG_P (*src1) || ! STACK_REG_P (*src2)) |
eca31501 | 1556 | emit_swap_insn (insn, regstack, *dest); |
a05924f9 JH |
1557 | else |
1558 | { | |
1559 | /* Both operands are REG. If neither operand is already | |
34e4536e UB |
1560 | at the top of stack, choose to make the one that is the |
1561 | dest the new top of stack. */ | |
48227150 | 1562 | |
a05924f9 | 1563 | int src1_hard_regnum, src2_hard_regnum; |
48227150 | 1564 | |
a05924f9 JH |
1565 | src1_hard_regnum = get_hard_regnum (regstack, *src1); |
1566 | src2_hard_regnum = get_hard_regnum (regstack, *src2); | |
34e4536e UB |
1567 | |
1568 | /* If the source is not live, this is yet another case of | |
1569 | uninitialized variables. Load up a NaN instead. */ | |
1570 | if (src1_hard_regnum == -1) | |
1571 | { | |
1572 | rtx pat2 = gen_rtx_CLOBBER (VOIDmode, *src1); | |
d8aeaba0 | 1573 | rtx_insn *insn2 = emit_insn_before (pat2, insn); |
34e4536e UB |
1574 | control_flow_insn_deleted |
1575 | |= move_nan_for_stack_reg (insn2, regstack, *src1); | |
1576 | } | |
1577 | if (src2_hard_regnum == -1) | |
1578 | { | |
1579 | rtx pat2 = gen_rtx_CLOBBER (VOIDmode, *src2); | |
d8aeaba0 | 1580 | rtx_insn *insn2 = emit_insn_before (pat2, insn); |
34e4536e UB |
1581 | control_flow_insn_deleted |
1582 | |= move_nan_for_stack_reg (insn2, regstack, *src2); | |
1583 | } | |
48227150 | 1584 | |
a05924f9 JH |
1585 | if (src1_hard_regnum != FIRST_STACK_REG |
1586 | && src2_hard_regnum != FIRST_STACK_REG) | |
1587 | emit_swap_insn (insn, regstack, *dest); | |
48227150 | 1588 | } |
a05924f9 JH |
1589 | |
1590 | if (STACK_REG_P (*src1)) | |
1591 | replace_reg (src1, get_hard_regnum (regstack, *src1)); | |
1592 | if (STACK_REG_P (*src2)) | |
1593 | replace_reg (src2, get_hard_regnum (regstack, *src2)); | |
1594 | ||
1595 | if (src1_note) | |
48227150 | 1596 | { |
a05924f9 | 1597 | rtx src1_reg = XEXP (src1_note, 0); |
48227150 | 1598 | |
a05924f9 JH |
1599 | /* If the register that dies is at the top of stack, then |
1600 | the destination is somewhere else - merely substitute it. | |
1601 | But if the reg that dies is not at top of stack, then | |
1602 | move the top of stack to the dead reg, as though we had | |
1603 | done the insn and then a store-with-pop. */ | |
48227150 | 1604 | |
a05924f9 JH |
1605 | if (REGNO (src1_reg) == regstack->reg[regstack->top]) |
1606 | { | |
1607 | SET_HARD_REG_BIT (regstack->reg_set, REGNO (*dest)); | |
1608 | replace_reg (dest, get_hard_regnum (regstack, *dest)); | |
1609 | } | |
1610 | else | |
1611 | { | |
1612 | int regno = get_hard_regnum (regstack, src1_reg); | |
48227150 | 1613 | |
a05924f9 JH |
1614 | SET_HARD_REG_BIT (regstack->reg_set, REGNO (*dest)); |
1615 | replace_reg (dest, regno); | |
1616 | ||
1617 | regstack->reg[regstack->top - (regno - FIRST_STACK_REG)] | |
1618 | = regstack->reg[regstack->top]; | |
1619 | } | |
1620 | ||
1621 | CLEAR_HARD_REG_BIT (regstack->reg_set, | |
1622 | REGNO (XEXP (src1_note, 0))); | |
1623 | replace_reg (&XEXP (src1_note, 0), FIRST_STACK_REG); | |
1624 | regstack->top--; | |
1625 | } | |
1626 | else if (src2_note) | |
48227150 | 1627 | { |
a05924f9 JH |
1628 | rtx src2_reg = XEXP (src2_note, 0); |
1629 | if (REGNO (src2_reg) == regstack->reg[regstack->top]) | |
1630 | { | |
1631 | SET_HARD_REG_BIT (regstack->reg_set, REGNO (*dest)); | |
1632 | replace_reg (dest, get_hard_regnum (regstack, *dest)); | |
1633 | } | |
1634 | else | |
1635 | { | |
1636 | int regno = get_hard_regnum (regstack, src2_reg); | |
1637 | ||
1638 | SET_HARD_REG_BIT (regstack->reg_set, REGNO (*dest)); | |
1639 | replace_reg (dest, regno); | |
1640 | ||
1641 | regstack->reg[regstack->top - (regno - FIRST_STACK_REG)] | |
1642 | = regstack->reg[regstack->top]; | |
1643 | } | |
1644 | ||
1645 | CLEAR_HARD_REG_BIT (regstack->reg_set, | |
1646 | REGNO (XEXP (src2_note, 0))); | |
1647 | replace_reg (&XEXP (src2_note, 0), FIRST_STACK_REG); | |
1648 | regstack->top--; | |
48227150 JVA |
1649 | } |
1650 | else | |
1651 | { | |
48227150 | 1652 | SET_HARD_REG_BIT (regstack->reg_set, REGNO (*dest)); |
a05924f9 | 1653 | replace_reg (dest, get_hard_regnum (regstack, *dest)); |
48227150 | 1654 | } |
caa6ec8d | 1655 | |
d55d8fc7 | 1656 | /* Keep operand 1 matching with destination. */ |
ec8e098d | 1657 | if (COMMUTATIVE_ARITH_P (pat_src) |
caa6ec8d JH |
1658 | && REG_P (*src1) && REG_P (*src2) |
1659 | && REGNO (*src1) != REGNO (*dest)) | |
1660 | { | |
0b9aaeee JH |
1661 | int tmp = REGNO (*src1); |
1662 | replace_reg (src1, REGNO (*src2)); | |
1663 | replace_reg (src2, tmp); | |
caa6ec8d | 1664 | } |
a05924f9 | 1665 | break; |
48227150 | 1666 | |
a05924f9 JH |
1667 | case UNSPEC: |
1668 | switch (XINT (pat_src, 1)) | |
1669 | { | |
6e858d45 | 1670 | case UNSPEC_FIST: |
a8caf351 | 1671 | case UNSPEC_FIST_ATOMIC: |
4a927664 UB |
1672 | |
1673 | case UNSPEC_FIST_FLOOR: | |
1674 | case UNSPEC_FIST_CEIL: | |
1675 | ||
6e858d45 UB |
1676 | /* These insns only operate on the top of the stack. */ |
1677 | ||
1678 | src1 = get_true_reg (&XVECEXP (pat_src, 0, 0)); | |
1679 | emit_swap_insn (insn, regstack, *src1); | |
1680 | ||
1681 | src1_note = find_regno_note (insn, REG_DEAD, REGNO (*src1)); | |
1682 | ||
1683 | if (STACK_REG_P (*dest)) | |
1684 | replace_reg (dest, FIRST_STACK_REG); | |
1685 | ||
1686 | if (src1_note) | |
1687 | { | |
1688 | replace_reg (&XEXP (src1_note, 0), FIRST_STACK_REG); | |
1689 | regstack->top--; | |
1690 | CLEAR_HARD_REG_BIT (regstack->reg_set, REGNO (*src1)); | |
1691 | } | |
1692 | ||
1693 | replace_reg (src1, FIRST_STACK_REG); | |
1694 | break; | |
1695 | ||
9ed4207f UB |
1696 | case UNSPEC_FXAM: |
1697 | ||
1698 | /* This insn only operate on the top of the stack. */ | |
1699 | ||
1700 | src1 = get_true_reg (&XVECEXP (pat_src, 0, 0)); | |
1701 | emit_swap_insn (insn, regstack, *src1); | |
1702 | ||
1703 | src1_note = find_regno_note (insn, REG_DEAD, REGNO (*src1)); | |
1704 | ||
1705 | replace_reg (src1, FIRST_STACK_REG); | |
1706 | ||
1707 | if (src1_note) | |
1708 | { | |
1709 | remove_regno_note (insn, REG_DEAD, | |
1710 | REGNO (XEXP (src1_note, 0))); | |
1711 | emit_pop_insn (insn, regstack, XEXP (src1_note, 0), | |
1712 | EMIT_AFTER); | |
1713 | } | |
1714 | ||
1715 | break; | |
1716 | ||
35a76aac RH |
1717 | case UNSPEC_SIN: |
1718 | case UNSPEC_COS: | |
9d5b9dae RS |
1719 | case UNSPEC_FRNDINT: |
1720 | case UNSPEC_F2XM1: | |
edeacc14 UB |
1721 | |
1722 | case UNSPEC_FRNDINT_FLOOR: | |
1723 | case UNSPEC_FRNDINT_CEIL: | |
1724 | case UNSPEC_FRNDINT_TRUNC: | |
1725 | case UNSPEC_FRNDINT_MASK_PM: | |
1726 | ||
d85c7550 UB |
1727 | /* Above insns operate on the top of the stack. */ |
1728 | ||
1729 | case UNSPEC_SINCOS_COS: | |
1730 | case UNSPEC_XTRACT_FRACT: | |
1731 | ||
1732 | /* Above insns operate on the top two stack slots, | |
1733 | first part of one input, double output insn. */ | |
0e7d0eb9 | 1734 | |
a05924f9 | 1735 | src1 = get_true_reg (&XVECEXP (pat_src, 0, 0)); |
0e7d0eb9 | 1736 | |
a05924f9 | 1737 | emit_swap_insn (insn, regstack, *src1); |
0e7d0eb9 | 1738 | |
d85c7550 | 1739 | /* Input should never die, it is replaced with output. */ |
a05924f9 | 1740 | src1_note = find_regno_note (insn, REG_DEAD, REGNO (*src1)); |
41374e13 | 1741 | gcc_assert (!src1_note); |
0e7d0eb9 | 1742 | |
a05924f9 JH |
1743 | if (STACK_REG_P (*dest)) |
1744 | replace_reg (dest, FIRST_STACK_REG); | |
0e7d0eb9 | 1745 | |
a05924f9 JH |
1746 | replace_reg (src1, FIRST_STACK_REG); |
1747 | break; | |
0e7d0eb9 | 1748 | |
d85c7550 UB |
1749 | case UNSPEC_SINCOS_SIN: |
1750 | case UNSPEC_XTRACT_EXP: | |
1751 | ||
1752 | /* These insns operate on the top two stack slots, | |
1753 | second part of one input, double output insn. */ | |
1754 | ||
1755 | regstack->top++; | |
1756 | /* FALLTHRU */ | |
1757 | ||
1758 | case UNSPEC_TAN: | |
1759 | ||
1760 | /* For UNSPEC_TAN, regstack->top is already increased | |
1761 | by inherent load of constant 1.0. */ | |
1762 | ||
1763 | /* Output value is generated in the second stack slot. | |
1764 | Move current value from second slot to the top. */ | |
1765 | regstack->reg[regstack->top] | |
1766 | = regstack->reg[regstack->top - 1]; | |
1767 | ||
1768 | gcc_assert (STACK_REG_P (*dest)); | |
1769 | ||
1770 | regstack->reg[regstack->top - 1] = REGNO (*dest); | |
1771 | SET_HARD_REG_BIT (regstack->reg_set, REGNO (*dest)); | |
1772 | replace_reg (dest, FIRST_STACK_REG + 1); | |
1773 | ||
1774 | src1 = get_true_reg (&XVECEXP (pat_src, 0, 0)); | |
1775 | ||
1776 | replace_reg (src1, FIRST_STACK_REG); | |
1777 | break; | |
1778 | ||
1fb54135 | 1779 | case UNSPEC_FPATAN: |
358997e2 | 1780 | case UNSPEC_FYL2X: |
c2fcfa4f | 1781 | case UNSPEC_FYL2XP1: |
1fb54135 RS |
1782 | /* These insns operate on the top two stack slots. */ |
1783 | ||
1784 | src1 = get_true_reg (&XVECEXP (pat_src, 0, 0)); | |
1785 | src2 = get_true_reg (&XVECEXP (pat_src, 0, 1)); | |
1786 | ||
1787 | src1_note = find_regno_note (insn, REG_DEAD, REGNO (*src1)); | |
1788 | src2_note = find_regno_note (insn, REG_DEAD, REGNO (*src2)); | |
1789 | ||
f964bd29 | 1790 | swap_to_top (insn, regstack, *src1, *src2); |
1fb54135 RS |
1791 | |
1792 | replace_reg (src1, FIRST_STACK_REG); | |
1793 | replace_reg (src2, FIRST_STACK_REG + 1); | |
1794 | ||
1795 | if (src1_note) | |
1796 | replace_reg (&XEXP (src1_note, 0), FIRST_STACK_REG); | |
1797 | if (src2_note) | |
1798 | replace_reg (&XEXP (src2_note, 0), FIRST_STACK_REG + 1); | |
1799 | ||
1800 | /* Pop both input operands from the stack. */ | |
1801 | CLEAR_HARD_REG_BIT (regstack->reg_set, | |
1802 | regstack->reg[regstack->top]); | |
1803 | CLEAR_HARD_REG_BIT (regstack->reg_set, | |
1804 | regstack->reg[regstack->top - 1]); | |
1805 | regstack->top -= 2; | |
1806 | ||
1807 | /* Push the result back onto the stack. */ | |
1808 | regstack->reg[++regstack->top] = REGNO (*dest); | |
1809 | SET_HARD_REG_BIT (regstack->reg_set, REGNO (*dest)); | |
1810 | replace_reg (dest, FIRST_STACK_REG); | |
1811 | break; | |
1812 | ||
f964bd29 | 1813 | case UNSPEC_FSCALE_FRACT: |
5ae27cfa UB |
1814 | case UNSPEC_FPREM_F: |
1815 | case UNSPEC_FPREM1_F: | |
79cd820a | 1816 | /* These insns operate on the top two stack slots, |
f964bd29 UB |
1817 | first part of double input, double output insn. */ |
1818 | ||
1819 | src1 = get_true_reg (&XVECEXP (pat_src, 0, 0)); | |
1820 | src2 = get_true_reg (&XVECEXP (pat_src, 0, 1)); | |
1821 | ||
1822 | src1_note = find_regno_note (insn, REG_DEAD, REGNO (*src1)); | |
1823 | src2_note = find_regno_note (insn, REG_DEAD, REGNO (*src2)); | |
1824 | ||
1825 | /* Inputs should never die, they are | |
1826 | replaced with outputs. */ | |
41374e13 NS |
1827 | gcc_assert (!src1_note); |
1828 | gcc_assert (!src2_note); | |
f964bd29 UB |
1829 | |
1830 | swap_to_top (insn, regstack, *src1, *src2); | |
1831 | ||
1832 | /* Push the result back onto stack. Empty stack slot | |
9cf737f8 | 1833 | will be filled in second part of insn. */ |
428aba16 RS |
1834 | if (STACK_REG_P (*dest)) |
1835 | { | |
1836 | regstack->reg[regstack->top] = REGNO (*dest); | |
1837 | SET_HARD_REG_BIT (regstack->reg_set, REGNO (*dest)); | |
1838 | replace_reg (dest, FIRST_STACK_REG); | |
1839 | } | |
f964bd29 UB |
1840 | |
1841 | replace_reg (src1, FIRST_STACK_REG); | |
1842 | replace_reg (src2, FIRST_STACK_REG + 1); | |
1843 | break; | |
1844 | ||
1845 | case UNSPEC_FSCALE_EXP: | |
5ae27cfa UB |
1846 | case UNSPEC_FPREM_U: |
1847 | case UNSPEC_FPREM1_U: | |
79cd820a | 1848 | /* These insns operate on the top two stack slots, |
f964bd29 UB |
1849 | second part of double input, double output insn. */ |
1850 | ||
1851 | src1 = get_true_reg (&XVECEXP (pat_src, 0, 0)); | |
1852 | src2 = get_true_reg (&XVECEXP (pat_src, 0, 1)); | |
1853 | ||
f964bd29 UB |
1854 | /* Push the result back onto stack. Fill empty slot from |
1855 | first part of insn and fix top of stack pointer. */ | |
428aba16 RS |
1856 | if (STACK_REG_P (*dest)) |
1857 | { | |
1858 | regstack->reg[regstack->top - 1] = REGNO (*dest); | |
1859 | SET_HARD_REG_BIT (regstack->reg_set, REGNO (*dest)); | |
1860 | replace_reg (dest, FIRST_STACK_REG + 1); | |
1861 | } | |
f964bd29 UB |
1862 | |
1863 | replace_reg (src1, FIRST_STACK_REG); | |
1864 | replace_reg (src2, FIRST_STACK_REG + 1); | |
1865 | break; | |
1866 | ||
79cd820a UB |
1867 | case UNSPEC_C2_FLAG: |
1868 | /* This insn operates on the top two stack slots, | |
1869 | third part of C2 setting double input insn. */ | |
1870 | ||
1871 | src1 = get_true_reg (&XVECEXP (pat_src, 0, 0)); | |
1872 | src2 = get_true_reg (&XVECEXP (pat_src, 0, 1)); | |
1873 | ||
1874 | replace_reg (src1, FIRST_STACK_REG); | |
1875 | replace_reg (src2, FIRST_STACK_REG + 1); | |
1876 | break; | |
1877 | ||
35a76aac RH |
1878 | case UNSPEC_SAHF: |
1879 | /* (unspec [(unspec [(compare)] UNSPEC_FNSTSW)] UNSPEC_SAHF) | |
1880 | The combination matches the PPRO fcomi instruction. */ | |
0e7d0eb9 | 1881 | |
a05924f9 | 1882 | pat_src = XVECEXP (pat_src, 0, 0); |
41374e13 NS |
1883 | gcc_assert (GET_CODE (pat_src) == UNSPEC); |
1884 | gcc_assert (XINT (pat_src, 1) == UNSPEC_FNSTSW); | |
5d3cc252 | 1885 | /* Fall through. */ |
e075ae69 | 1886 | |
35a76aac | 1887 | case UNSPEC_FNSTSW: |
a05924f9 JH |
1888 | /* Combined fcomp+fnstsw generated for doing well with |
1889 | CSE. When optimizing this would have been broken | |
1890 | up before now. */ | |
e075ae69 | 1891 | |
a05924f9 | 1892 | pat_src = XVECEXP (pat_src, 0, 0); |
41374e13 | 1893 | gcc_assert (GET_CODE (pat_src) == COMPARE); |
e075ae69 | 1894 | |
a05924f9 JH |
1895 | compare_for_stack_reg (insn, regstack, pat_src); |
1896 | break; | |
e075ae69 | 1897 | |
a05924f9 | 1898 | default: |
41374e13 | 1899 | gcc_unreachable (); |
a05924f9 | 1900 | } |
e075ae69 RH |
1901 | break; |
1902 | ||
a05924f9 | 1903 | case IF_THEN_ELSE: |
dc297297 | 1904 | /* This insn requires the top of stack to be the destination. */ |
0e7d0eb9 | 1905 | |
2ab0437e JH |
1906 | src1 = get_true_reg (&XEXP (pat_src, 1)); |
1907 | src2 = get_true_reg (&XEXP (pat_src, 2)); | |
1908 | ||
1909 | src1_note = find_regno_note (insn, REG_DEAD, REGNO (*src1)); | |
1910 | src2_note = find_regno_note (insn, REG_DEAD, REGNO (*src2)); | |
1911 | ||
a05924f9 JH |
1912 | /* If the comparison operator is an FP comparison operator, |
1913 | it is handled correctly by compare_for_stack_reg () who | |
1914 | will move the destination to the top of stack. But if the | |
1915 | comparison operator is not an FP comparison operator, we | |
dc297297 | 1916 | have to handle it here. */ |
a05924f9 JH |
1917 | if (get_hard_regnum (regstack, *dest) >= FIRST_STACK_REG |
1918 | && REGNO (*dest) != regstack->reg[regstack->top]) | |
2ab0437e JH |
1919 | { |
1920 | /* In case one of operands is the top of stack and the operands | |
35a76aac RH |
1921 | dies, it is safe to make it the destination operand by |
1922 | reversing the direction of cmove and avoid fxch. */ | |
2ab0437e JH |
1923 | if ((REGNO (*src1) == regstack->reg[regstack->top] |
1924 | && src1_note) | |
1925 | || (REGNO (*src2) == regstack->reg[regstack->top] | |
1926 | && src2_note)) | |
1927 | { | |
b74cf1ce JH |
1928 | int idx1 = (get_hard_regnum (regstack, *src1) |
1929 | - FIRST_STACK_REG); | |
1930 | int idx2 = (get_hard_regnum (regstack, *src2) | |
1931 | - FIRST_STACK_REG); | |
1932 | ||
1933 | /* Make reg-stack believe that the operands are already | |
1934 | swapped on the stack */ | |
1935 | regstack->reg[regstack->top - idx1] = REGNO (*src2); | |
1936 | regstack->reg[regstack->top - idx2] = REGNO (*src1); | |
1937 | ||
1938 | /* Reverse condition to compensate the operand swap. | |
1939 | i386 do have comparison always reversible. */ | |
2ab0437e JH |
1940 | PUT_CODE (XEXP (pat_src, 0), |
1941 | reversed_comparison_code (XEXP (pat_src, 0), insn)); | |
1942 | } | |
1943 | else | |
a6a2274a | 1944 | emit_swap_insn (insn, regstack, *dest); |
2ab0437e | 1945 | } |
4e97601f | 1946 | |
a05924f9 JH |
1947 | { |
1948 | rtx src_note [3]; | |
1949 | int i; | |
4e97601f | 1950 | |
a05924f9 JH |
1951 | src_note[0] = 0; |
1952 | src_note[1] = src1_note; | |
1953 | src_note[2] = src2_note; | |
54552651 | 1954 | |
a05924f9 JH |
1955 | if (STACK_REG_P (*src1)) |
1956 | replace_reg (src1, get_hard_regnum (regstack, *src1)); | |
1957 | if (STACK_REG_P (*src2)) | |
1958 | replace_reg (src2, get_hard_regnum (regstack, *src2)); | |
4e97601f | 1959 | |
a05924f9 JH |
1960 | for (i = 1; i <= 2; i++) |
1961 | if (src_note [i]) | |
4e97601f | 1962 | { |
a05924f9 JH |
1963 | int regno = REGNO (XEXP (src_note[i], 0)); |
1964 | ||
1965 | /* If the register that dies is not at the top of | |
41374e13 NS |
1966 | stack, then move the top of stack to the dead reg. |
1967 | Top of stack should never die, as it is the | |
1968 | destination. */ | |
1969 | gcc_assert (regno != regstack->reg[regstack->top]); | |
1970 | remove_regno_note (insn, REG_DEAD, regno); | |
1971 | emit_pop_insn (insn, regstack, XEXP (src_note[i], 0), | |
1972 | EMIT_AFTER); | |
4e97601f | 1973 | } |
a05924f9 | 1974 | } |
4e97601f | 1975 | |
a05924f9 | 1976 | /* Make dest the top of stack. Add dest to regstack if |
dc297297 | 1977 | not present. */ |
a05924f9 | 1978 | if (get_hard_regnum (regstack, *dest) < FIRST_STACK_REG) |
a6a2274a | 1979 | regstack->reg[++regstack->top] = REGNO (*dest); |
a05924f9 JH |
1980 | SET_HARD_REG_BIT (regstack->reg_set, REGNO (*dest)); |
1981 | replace_reg (dest, FIRST_STACK_REG); | |
1982 | break; | |
914ec131 | 1983 | |
a05924f9 | 1984 | default: |
41374e13 | 1985 | gcc_unreachable (); |
a05924f9 | 1986 | } |
4e97601f | 1987 | break; |
48227150 | 1988 | } |
a05924f9 JH |
1989 | |
1990 | default: | |
1991 | break; | |
1992 | } | |
ecb63641 EB |
1993 | |
1994 | return control_flow_insn_deleted; | |
48227150 JVA |
1995 | } |
1996 | \f | |
114cbee6 RS |
1997 | /* Substitute hard regnums for any stack regs in INSN, which has |
1998 | N_INPUTS inputs and N_OUTPUTS outputs. REGSTACK is the stack info | |
f62a15e3 | 1999 | before the insn, and is updated with changes made here. |
114cbee6 RS |
2000 | |
2001 | There are several requirements and assumptions about the use of | |
2002 | stack-like regs in asm statements. These rules are enforced by | |
2003 | record_asm_stack_regs; see comments there for details. Any | |
2004 | asm_operands left in the RTL at this point may be assume to meet the | |
561cf7b1 | 2005 | requirements, since record_asm_stack_regs removes any problem asm. */ |
114cbee6 | 2006 | |
561cf7b1 | 2007 | static void |
d8aeaba0 | 2008 | subst_asm_stack_regs (rtx_insn *insn, stack_ptr regstack) |
114cbee6 | 2009 | { |
114cbee6 | 2010 | rtx body = PATTERN (insn); |
114cbee6 RS |
2011 | |
2012 | rtx *note_reg; /* Array of note contents */ | |
2013 | rtx **note_loc; /* Address of REG field of each note */ | |
2014 | enum reg_note *note_kind; /* The type of each note */ | |
2015 | ||
a544cfd2 KG |
2016 | rtx *clobber_reg = 0; |
2017 | rtx **clobber_loc = 0; | |
114cbee6 RS |
2018 | |
2019 | struct stack_def temp_stack; | |
2020 | int n_notes; | |
2021 | int n_clobbers; | |
2022 | rtx note; | |
2023 | int i; | |
f62a15e3 | 2024 | int n_inputs, n_outputs; |
114cbee6 | 2025 | |
a05924f9 JH |
2026 | if (! check_asm_stack_operands (insn)) |
2027 | return; | |
2028 | ||
114cbee6 RS |
2029 | /* Find out what the constraints required. If no constraint |
2030 | alternative matches, that is a compiler bug: we should have caught | |
a05924f9 | 2031 | such an insn in check_asm_stack_operands. */ |
75d25a02 | 2032 | extract_constrain_insn (insn); |
f62a15e3 | 2033 | |
1145837d | 2034 | preprocess_constraints (insn); |
5efe5dec | 2035 | const operand_alternative *op_alt = which_op_alt (); |
114cbee6 | 2036 | |
1c384bf1 | 2037 | get_asm_operands_in_out (body, &n_outputs, &n_inputs); |
a6a2274a | 2038 | |
0f41302f | 2039 | /* Strip SUBREGs here to make the following code simpler. */ |
1ccbefce RH |
2040 | for (i = 0; i < recog_data.n_operands; i++) |
2041 | if (GET_CODE (recog_data.operand[i]) == SUBREG | |
f8cfc6aa | 2042 | && REG_P (SUBREG_REG (recog_data.operand[i]))) |
114cbee6 | 2043 | { |
1ccbefce RH |
2044 | recog_data.operand_loc[i] = & SUBREG_REG (recog_data.operand[i]); |
2045 | recog_data.operand[i] = SUBREG_REG (recog_data.operand[i]); | |
114cbee6 RS |
2046 | } |
2047 | ||
2048 | /* Set up NOTE_REG, NOTE_LOC and NOTE_KIND. */ | |
2049 | ||
2050 | for (i = 0, note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
2051 | i++; | |
2052 | ||
1634b18f KG |
2053 | note_reg = XALLOCAVEC (rtx, i); |
2054 | note_loc = XALLOCAVEC (rtx *, i); | |
2055 | note_kind = XALLOCAVEC (enum reg_note, i); | |
114cbee6 RS |
2056 | |
2057 | n_notes = 0; | |
2058 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
2059 | { | |
e5af9ddd RS |
2060 | if (GET_CODE (note) != EXPR_LIST) |
2061 | continue; | |
114cbee6 RS |
2062 | rtx reg = XEXP (note, 0); |
2063 | rtx *loc = & XEXP (note, 0); | |
2064 | ||
f8cfc6aa | 2065 | if (GET_CODE (reg) == SUBREG && REG_P (SUBREG_REG (reg))) |
114cbee6 RS |
2066 | { |
2067 | loc = & SUBREG_REG (reg); | |
2068 | reg = SUBREG_REG (reg); | |
2069 | } | |
2070 | ||
2071 | if (STACK_REG_P (reg) | |
2072 | && (REG_NOTE_KIND (note) == REG_DEAD | |
2073 | || REG_NOTE_KIND (note) == REG_UNUSED)) | |
2074 | { | |
2075 | note_reg[n_notes] = reg; | |
2076 | note_loc[n_notes] = loc; | |
2077 | note_kind[n_notes] = REG_NOTE_KIND (note); | |
2078 | n_notes++; | |
2079 | } | |
2080 | } | |
2081 | ||
2082 | /* Set up CLOBBER_REG and CLOBBER_LOC. */ | |
2083 | ||
2084 | n_clobbers = 0; | |
114cbee6 RS |
2085 | |
2086 | if (GET_CODE (body) == PARALLEL) | |
3f5cfed6 | 2087 | { |
1634b18f KG |
2088 | clobber_reg = XALLOCAVEC (rtx, XVECLEN (body, 0)); |
2089 | clobber_loc = XALLOCAVEC (rtx *, XVECLEN (body, 0)); | |
114cbee6 | 2090 | |
3f5cfed6 JVA |
2091 | for (i = 0; i < XVECLEN (body, 0); i++) |
2092 | if (GET_CODE (XVECEXP (body, 0, i)) == CLOBBER) | |
2093 | { | |
2094 | rtx clobber = XVECEXP (body, 0, i); | |
2095 | rtx reg = XEXP (clobber, 0); | |
2096 | rtx *loc = & XEXP (clobber, 0); | |
114cbee6 | 2097 | |
f8cfc6aa | 2098 | if (GET_CODE (reg) == SUBREG && REG_P (SUBREG_REG (reg))) |
3f5cfed6 JVA |
2099 | { |
2100 | loc = & SUBREG_REG (reg); | |
2101 | reg = SUBREG_REG (reg); | |
2102 | } | |
2103 | ||
2104 | if (STACK_REG_P (reg)) | |
2105 | { | |
2106 | clobber_reg[n_clobbers] = reg; | |
2107 | clobber_loc[n_clobbers] = loc; | |
2108 | n_clobbers++; | |
2109 | } | |
2110 | } | |
2111 | } | |
114cbee6 | 2112 | |
a05924f9 | 2113 | temp_stack = *regstack; |
114cbee6 RS |
2114 | |
2115 | /* Put the input regs into the desired place in TEMP_STACK. */ | |
2116 | ||
f62a15e3 | 2117 | for (i = n_outputs; i < n_outputs + n_inputs; i++) |
1ccbefce | 2118 | if (STACK_REG_P (recog_data.operand[i]) |
29d70a0f RS |
2119 | && reg_class_subset_p (op_alt[i].cl, FLOAT_REGS) |
2120 | && op_alt[i].cl != FLOAT_REGS) | |
114cbee6 RS |
2121 | { |
2122 | /* If an operand needs to be in a particular reg in | |
2123 | FLOAT_REGS, the constraint was either 't' or 'u'. Since | |
1ccbefce RH |
2124 | these constraints are for single register classes, and |
2125 | reload guaranteed that operand[i] is already in that class, | |
2126 | we can just use REGNO (recog_data.operand[i]) to know which | |
2127 | actual reg this operand needs to be in. */ | |
114cbee6 | 2128 | |
1ccbefce | 2129 | int regno = get_hard_regnum (&temp_stack, recog_data.operand[i]); |
114cbee6 | 2130 | |
41374e13 | 2131 | gcc_assert (regno >= 0); |
114cbee6 | 2132 | |
ae0ed63a | 2133 | if ((unsigned int) regno != REGNO (recog_data.operand[i])) |
114cbee6 | 2134 | { |
1ccbefce RH |
2135 | /* recog_data.operand[i] is not in the right place. Find |
2136 | it and swap it with whatever is already in I's place. | |
2137 | K is where recog_data.operand[i] is now. J is where it | |
2138 | should be. */ | |
fab27f52 | 2139 | int j, k; |
114cbee6 RS |
2140 | |
2141 | k = temp_stack.top - (regno - FIRST_STACK_REG); | |
2142 | j = (temp_stack.top | |
1ccbefce | 2143 | - (REGNO (recog_data.operand[i]) - FIRST_STACK_REG)); |
114cbee6 | 2144 | |
fab27f52 | 2145 | std::swap (temp_stack.reg[j], temp_stack.reg[k]); |
114cbee6 RS |
2146 | } |
2147 | } | |
2148 | ||
a05924f9 | 2149 | /* Emit insns before INSN to make sure the reg-stack is in the right |
114cbee6 RS |
2150 | order. */ |
2151 | ||
a05924f9 | 2152 | change_stack (insn, regstack, &temp_stack, EMIT_BEFORE); |
114cbee6 RS |
2153 | |
2154 | /* Make the needed input register substitutions. Do death notes and | |
0f41302f | 2155 | clobbers too, because these are for inputs, not outputs. */ |
114cbee6 | 2156 | |
f62a15e3 | 2157 | for (i = n_outputs; i < n_outputs + n_inputs; i++) |
1ccbefce | 2158 | if (STACK_REG_P (recog_data.operand[i])) |
114cbee6 | 2159 | { |
1ccbefce | 2160 | int regnum = get_hard_regnum (regstack, recog_data.operand[i]); |
114cbee6 | 2161 | |
41374e13 | 2162 | gcc_assert (regnum >= 0); |
114cbee6 | 2163 | |
1ccbefce | 2164 | replace_reg (recog_data.operand_loc[i], regnum); |
114cbee6 RS |
2165 | } |
2166 | ||
2167 | for (i = 0; i < n_notes; i++) | |
2168 | if (note_kind[i] == REG_DEAD) | |
2169 | { | |
2170 | int regnum = get_hard_regnum (regstack, note_reg[i]); | |
2171 | ||
41374e13 | 2172 | gcc_assert (regnum >= 0); |
114cbee6 RS |
2173 | |
2174 | replace_reg (note_loc[i], regnum); | |
2175 | } | |
2176 | ||
2177 | for (i = 0; i < n_clobbers; i++) | |
2178 | { | |
2179 | /* It's OK for a CLOBBER to reference a reg that is not live. | |
2180 | Don't try to replace it in that case. */ | |
2181 | int regnum = get_hard_regnum (regstack, clobber_reg[i]); | |
2182 | ||
2183 | if (regnum >= 0) | |
2184 | { | |
2185 | /* Sigh - clobbers always have QImode. But replace_reg knows | |
41374e13 | 2186 | that these regs can't be MODE_INT and will assert. Just put |
114cbee6 RS |
2187 | the right reg there without calling replace_reg. */ |
2188 | ||
99a59310 | 2189 | *clobber_loc[i] = FP_MODE_REG (regnum, DFmode); |
114cbee6 RS |
2190 | } |
2191 | } | |
2192 | ||
0f41302f | 2193 | /* Now remove from REGSTACK any inputs that the asm implicitly popped. */ |
114cbee6 | 2194 | |
f62a15e3 | 2195 | for (i = n_outputs; i < n_outputs + n_inputs; i++) |
1ccbefce | 2196 | if (STACK_REG_P (recog_data.operand[i])) |
114cbee6 RS |
2197 | { |
2198 | /* An input reg is implicitly popped if it is tied to an | |
0f41302f | 2199 | output, or if there is a CLOBBER for it. */ |
114cbee6 RS |
2200 | int j; |
2201 | ||
2202 | for (j = 0; j < n_clobbers; j++) | |
1ccbefce | 2203 | if (operands_match_p (clobber_reg[j], recog_data.operand[i])) |
114cbee6 RS |
2204 | break; |
2205 | ||
29d70a0f | 2206 | if (j < n_clobbers || op_alt[i].matches >= 0) |
114cbee6 | 2207 | { |
1ccbefce RH |
2208 | /* recog_data.operand[i] might not be at the top of stack. |
2209 | But that's OK, because all we need to do is pop the | |
2210 | right number of regs off of the top of the reg-stack. | |
2211 | record_asm_stack_regs guaranteed that all implicitly | |
2212 | popped regs were grouped at the top of the reg-stack. */ | |
114cbee6 RS |
2213 | |
2214 | CLEAR_HARD_REG_BIT (regstack->reg_set, | |
2215 | regstack->reg[regstack->top]); | |
2216 | regstack->top--; | |
2217 | } | |
2218 | } | |
2219 | ||
2220 | /* Now add to REGSTACK any outputs that the asm implicitly pushed. | |
2221 | Note that there isn't any need to substitute register numbers. | |
0f41302f | 2222 | ??? Explain why this is true. */ |
114cbee6 RS |
2223 | |
2224 | for (i = LAST_STACK_REG; i >= FIRST_STACK_REG; i--) | |
2225 | { | |
2226 | /* See if there is an output for this hard reg. */ | |
2227 | int j; | |
2228 | ||
2229 | for (j = 0; j < n_outputs; j++) | |
1ccbefce | 2230 | if (STACK_REG_P (recog_data.operand[j]) |
ae0ed63a | 2231 | && REGNO (recog_data.operand[j]) == (unsigned) i) |
114cbee6 RS |
2232 | { |
2233 | regstack->reg[++regstack->top] = i; | |
2234 | SET_HARD_REG_BIT (regstack->reg_set, i); | |
2235 | break; | |
2236 | } | |
2237 | } | |
2238 | ||
2239 | /* Now emit a pop insn for any REG_UNUSED output, or any REG_DEAD | |
2240 | input that the asm didn't implicitly pop. If the asm didn't | |
3f5cfed6 | 2241 | implicitly pop an input reg, that reg will still be live. |
114cbee6 RS |
2242 | |
2243 | Note that we can't use find_regno_note here: the register numbers | |
2244 | in the death notes have already been substituted. */ | |
2245 | ||
3f5cfed6 | 2246 | for (i = 0; i < n_outputs; i++) |
1ccbefce | 2247 | if (STACK_REG_P (recog_data.operand[i])) |
3f5cfed6 JVA |
2248 | { |
2249 | int j; | |
2250 | ||
2251 | for (j = 0; j < n_notes; j++) | |
1ccbefce | 2252 | if (REGNO (recog_data.operand[i]) == REGNO (note_reg[j]) |
3f5cfed6 JVA |
2253 | && note_kind[j] == REG_UNUSED) |
2254 | { | |
1ccbefce | 2255 | insn = emit_pop_insn (insn, regstack, recog_data.operand[i], |
a05924f9 | 2256 | EMIT_AFTER); |
3f5cfed6 JVA |
2257 | break; |
2258 | } | |
2259 | } | |
2260 | ||
f62a15e3 | 2261 | for (i = n_outputs; i < n_outputs + n_inputs; i++) |
1ccbefce | 2262 | if (STACK_REG_P (recog_data.operand[i])) |
114cbee6 RS |
2263 | { |
2264 | int j; | |
2265 | ||
2266 | for (j = 0; j < n_notes; j++) | |
1ccbefce | 2267 | if (REGNO (recog_data.operand[i]) == REGNO (note_reg[j]) |
3f5cfed6 | 2268 | && note_kind[j] == REG_DEAD |
f62a15e3 | 2269 | && TEST_HARD_REG_BIT (regstack->reg_set, |
1ccbefce | 2270 | REGNO (recog_data.operand[i]))) |
114cbee6 | 2271 | { |
1ccbefce | 2272 | insn = emit_pop_insn (insn, regstack, recog_data.operand[i], |
a05924f9 | 2273 | EMIT_AFTER); |
114cbee6 RS |
2274 | break; |
2275 | } | |
2276 | } | |
2277 | } | |
2278 | \f | |
48227150 JVA |
2279 | /* Substitute stack hard reg numbers for stack virtual registers in |
2280 | INSN. Non-stack register numbers are not changed. REGSTACK is the | |
2281 | current stack content. Insns may be emitted as needed to arrange the | |
ecb63641 EB |
2282 | stack for the 387 based on the contents of the insn. Return whether |
2283 | a control flow insn was deleted in the process. */ | |
f37eb5cb | 2284 | |
ecb63641 | 2285 | static bool |
d8aeaba0 | 2286 | subst_stack_regs (rtx_insn *insn, stack_ptr regstack) |
48227150 | 2287 | { |
b3694847 | 2288 | rtx *note_link, note; |
ecb63641 | 2289 | bool control_flow_insn_deleted = false; |
b3694847 | 2290 | int i; |
48227150 | 2291 | |
4b4bf941 | 2292 | if (CALL_P (insn)) |
e075ae69 RH |
2293 | { |
2294 | int top = regstack->top; | |
48227150 | 2295 | |
e075ae69 RH |
2296 | /* If there are any floating point parameters to be passed in |
2297 | registers for this call, make sure they are in the right | |
2298 | order. */ | |
48227150 | 2299 | |
e075ae69 RH |
2300 | if (top >= 0) |
2301 | { | |
385e0e08 | 2302 | straighten_stack (insn, regstack); |
99a59310 | 2303 | |
e075ae69 | 2304 | /* Now mark the arguments as dead after the call. */ |
99a59310 | 2305 | |
e075ae69 RH |
2306 | while (regstack->top >= 0) |
2307 | { | |
2308 | CLEAR_HARD_REG_BIT (regstack->reg_set, FIRST_STACK_REG + regstack->top); | |
2309 | regstack->top--; | |
2310 | } | |
2311 | } | |
2312 | } | |
48227150 JVA |
2313 | |
2314 | /* Do the actual substitution if any stack regs are mentioned. | |
2315 | Since we only record whether entire insn mentions stack regs, and | |
2316 | subst_stack_regs_pat only works for patterns that contain stack regs, | |
2317 | we must check each pattern in a parallel here. A call_value_pop could | |
0f41302f | 2318 | fail otherwise. */ |
48227150 | 2319 | |
21b2cd73 | 2320 | if (stack_regs_mentioned (insn)) |
48227150 | 2321 | { |
f62a15e3 | 2322 | int n_operands = asm_noperands (PATTERN (insn)); |
114cbee6 RS |
2323 | if (n_operands >= 0) |
2324 | { | |
2325 | /* This insn is an `asm' with operands. Decode the operands, | |
2326 | decide how many are inputs, and do register substitution. | |
0f41302f | 2327 | Any REG_UNUSED notes will be handled by subst_asm_stack_regs. */ |
114cbee6 | 2328 | |
f62a15e3 | 2329 | subst_asm_stack_regs (insn, regstack); |
ecb63641 | 2330 | return control_flow_insn_deleted; |
114cbee6 RS |
2331 | } |
2332 | ||
48227150 | 2333 | if (GET_CODE (PATTERN (insn)) == PARALLEL) |
c166a311 | 2334 | for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++) |
48227150 JVA |
2335 | { |
2336 | if (stack_regs_mentioned_p (XVECEXP (PATTERN (insn), 0, i))) | |
736b64dd JH |
2337 | { |
2338 | if (GET_CODE (XVECEXP (PATTERN (insn), 0, i)) == CLOBBER) | |
2339 | XVECEXP (PATTERN (insn), 0, i) | |
2340 | = shallow_copy_rtx (XVECEXP (PATTERN (insn), 0, i)); | |
2341 | control_flow_insn_deleted | |
2342 | |= subst_stack_regs_pat (insn, regstack, | |
2343 | XVECEXP (PATTERN (insn), 0, i)); | |
2344 | } | |
48227150 JVA |
2345 | } |
2346 | else | |
ecb63641 EB |
2347 | control_flow_insn_deleted |
2348 | |= subst_stack_regs_pat (insn, regstack, PATTERN (insn)); | |
48227150 JVA |
2349 | } |
2350 | ||
2351 | /* subst_stack_regs_pat may have deleted a no-op insn. If so, any | |
0f41302f | 2352 | REG_UNUSED will already have been dealt with, so just return. */ |
48227150 | 2353 | |
4654c0cf | 2354 | if (NOTE_P (insn) || insn->deleted ()) |
ecb63641 | 2355 | return control_flow_insn_deleted; |
48227150 | 2356 | |
2d0df1f9 RS |
2357 | /* If this a noreturn call, we can't insert pop insns after it. |
2358 | Instead, reset the stack state to empty. */ | |
2359 | if (CALL_P (insn) | |
2360 | && find_reg_note (insn, REG_NORETURN, NULL)) | |
2361 | { | |
2362 | regstack->top = -1; | |
2363 | CLEAR_HARD_REG_SET (regstack->reg_set); | |
2364 | return control_flow_insn_deleted; | |
2365 | } | |
2366 | ||
48227150 JVA |
2367 | /* If there is a REG_UNUSED note on a stack register on this insn, |
2368 | the indicated reg must be popped. The REG_UNUSED note is removed, | |
2369 | since the form of the newly emitted pop insn references the reg, | |
0f41302f | 2370 | making it no longer `unset'. */ |
48227150 | 2371 | |
8e2e89f7 | 2372 | note_link = ®_NOTES (insn); |
48227150 JVA |
2373 | for (note = *note_link; note; note = XEXP (note, 1)) |
2374 | if (REG_NOTE_KIND (note) == REG_UNUSED && STACK_REG_P (XEXP (note, 0))) | |
2375 | { | |
2376 | *note_link = XEXP (note, 1); | |
a05924f9 | 2377 | insn = emit_pop_insn (insn, regstack, XEXP (note, 0), EMIT_AFTER); |
48227150 JVA |
2378 | } |
2379 | else | |
2380 | note_link = &XEXP (note, 1); | |
ecb63641 EB |
2381 | |
2382 | return control_flow_insn_deleted; | |
48227150 JVA |
2383 | } |
2384 | \f | |
2385 | /* Change the organization of the stack so that it fits a new basic | |
2386 | block. Some registers might have to be popped, but there can never be | |
2387 | a register live in the new block that is not now live. | |
2388 | ||
a05924f9 JH |
2389 | Insert any needed insns before or after INSN, as indicated by |
2390 | WHERE. OLD is the original stack layout, and NEW is the desired | |
454ff5cb | 2391 | form. OLD is updated to reflect the code emitted, i.e., it will be |
a05924f9 | 2392 | the same as NEW upon return. |
48227150 JVA |
2393 | |
2394 | This function will not preserve block_end[]. But that information | |
0f41302f | 2395 | is no longer needed once this has executed. */ |
48227150 JVA |
2396 | |
2397 | static void | |
d8aeaba0 DM |
2398 | change_stack (rtx_insn *insn, stack_ptr old, stack_ptr new_stack, |
2399 | enum emit_where where) | |
48227150 JVA |
2400 | { |
2401 | int reg; | |
a05924f9 | 2402 | int update_end = 0; |
6fb5fa3c | 2403 | int i; |
48227150 | 2404 | |
385e0e08 RS |
2405 | /* Stack adjustments for the first insn in a block update the |
2406 | current_block's stack_in instead of inserting insns directly. | |
2407 | compensate_edges will add the necessary code later. */ | |
2408 | if (current_block | |
2409 | && starting_stack_p | |
2410 | && where == EMIT_BEFORE) | |
2411 | { | |
d858f359 | 2412 | BLOCK_INFO (current_block)->stack_in = *new_stack; |
385e0e08 | 2413 | starting_stack_p = false; |
d858f359 | 2414 | *old = *new_stack; |
385e0e08 RS |
2415 | return; |
2416 | } | |
2417 | ||
a05924f9 JH |
2418 | /* We will be inserting new insns "backwards". If we are to insert |
2419 | after INSN, find the next insn, and insert before it. */ | |
48227150 | 2420 | |
a05924f9 JH |
2421 | if (where == EMIT_AFTER) |
2422 | { | |
a813c111 | 2423 | if (current_block && BB_END (current_block) == insn) |
a05924f9 JH |
2424 | update_end = 1; |
2425 | insn = NEXT_INSN (insn); | |
2426 | } | |
48227150 | 2427 | |
6fb5fa3c DB |
2428 | /* Initialize partially dead variables. */ |
2429 | for (i = FIRST_STACK_REG; i < LAST_STACK_REG + 1; i++) | |
d858f359 | 2430 | if (TEST_HARD_REG_BIT (new_stack->reg_set, i) |
6fb5fa3c DB |
2431 | && !TEST_HARD_REG_BIT (old->reg_set, i)) |
2432 | { | |
2433 | old->reg[++old->top] = i; | |
2434 | SET_HARD_REG_BIT (old->reg_set, i); | |
f7df4a84 RS |
2435 | emit_insn_before (gen_rtx_SET (FP_MODE_REG (i, SFmode), not_a_num), |
2436 | insn); | |
6fb5fa3c DB |
2437 | } |
2438 | ||
0f41302f | 2439 | /* Pop any registers that are not needed in the new block. */ |
48227150 | 2440 | |
0cc5dec1 RS |
2441 | /* If the destination block's stack already has a specified layout |
2442 | and contains two or more registers, use a more intelligent algorithm | |
026c3cfd | 2443 | to pop registers that minimizes the number of fxchs below. */ |
d858f359 | 2444 | if (new_stack->top > 0) |
0cc5dec1 RS |
2445 | { |
2446 | bool slots[REG_STACK_SIZE]; | |
2447 | int pops[REG_STACK_SIZE]; | |
00fc055e | 2448 | int next, dest, topsrc; |
0cc5dec1 RS |
2449 | |
2450 | /* First pass to determine the free slots. */ | |
d858f359 KG |
2451 | for (reg = 0; reg <= new_stack->top; reg++) |
2452 | slots[reg] = TEST_HARD_REG_BIT (new_stack->reg_set, old->reg[reg]); | |
0cc5dec1 RS |
2453 | |
2454 | /* Second pass to allocate preferred slots. */ | |
00fc055e | 2455 | topsrc = -1; |
d858f359 KG |
2456 | for (reg = old->top; reg > new_stack->top; reg--) |
2457 | if (TEST_HARD_REG_BIT (new_stack->reg_set, old->reg[reg])) | |
0cc5dec1 RS |
2458 | { |
2459 | dest = -1; | |
d858f359 KG |
2460 | for (next = 0; next <= new_stack->top; next++) |
2461 | if (!slots[next] && new_stack->reg[next] == old->reg[reg]) | |
0cc5dec1 | 2462 | { |
00fc055e RS |
2463 | /* If this is a preference for the new top of stack, record |
2464 | the fact by remembering it's old->reg in topsrc. */ | |
d858f359 | 2465 | if (next == new_stack->top) |
00fc055e | 2466 | topsrc = reg; |
0cc5dec1 RS |
2467 | slots[next] = true; |
2468 | dest = next; | |
2469 | break; | |
2470 | } | |
2471 | pops[reg] = dest; | |
2472 | } | |
2473 | else | |
2474 | pops[reg] = reg; | |
2475 | ||
00fc055e RS |
2476 | /* Intentionally, avoid placing the top of stack in it's correct |
2477 | location, if we still need to permute the stack below and we | |
2478 | can usefully place it somewhere else. This is the case if any | |
2479 | slot is still unallocated, in which case we should place the | |
2480 | top of stack there. */ | |
2481 | if (topsrc != -1) | |
d858f359 | 2482 | for (reg = 0; reg < new_stack->top; reg++) |
00fc055e RS |
2483 | if (!slots[reg]) |
2484 | { | |
2485 | pops[topsrc] = reg; | |
d858f359 | 2486 | slots[new_stack->top] = false; |
00fc055e RS |
2487 | slots[reg] = true; |
2488 | break; | |
2489 | } | |
2490 | ||
0cc5dec1 | 2491 | /* Third pass allocates remaining slots and emits pop insns. */ |
d858f359 KG |
2492 | next = new_stack->top; |
2493 | for (reg = old->top; reg > new_stack->top; reg--) | |
0cc5dec1 RS |
2494 | { |
2495 | dest = pops[reg]; | |
2496 | if (dest == -1) | |
2497 | { | |
2498 | /* Find next free slot. */ | |
2499 | while (slots[next]) | |
00fc055e RS |
2500 | next--; |
2501 | dest = next--; | |
0cc5dec1 RS |
2502 | } |
2503 | emit_pop_insn (insn, old, FP_MODE_REG (old->reg[dest], DFmode), | |
2504 | EMIT_BEFORE); | |
2505 | } | |
2506 | } | |
2507 | else | |
00fc055e RS |
2508 | { |
2509 | /* The following loop attempts to maximize the number of times we | |
2510 | pop the top of the stack, as this permits the use of the faster | |
2511 | ffreep instruction on platforms that support it. */ | |
2512 | int live, next; | |
2513 | ||
2514 | live = 0; | |
2515 | for (reg = 0; reg <= old->top; reg++) | |
d858f359 | 2516 | if (TEST_HARD_REG_BIT (new_stack->reg_set, old->reg[reg])) |
00fc055e RS |
2517 | live++; |
2518 | ||
2519 | next = live; | |
2520 | while (old->top >= live) | |
d858f359 | 2521 | if (TEST_HARD_REG_BIT (new_stack->reg_set, old->reg[old->top])) |
00fc055e | 2522 | { |
d858f359 | 2523 | while (TEST_HARD_REG_BIT (new_stack->reg_set, old->reg[next])) |
00fc055e RS |
2524 | next--; |
2525 | emit_pop_insn (insn, old, FP_MODE_REG (old->reg[next], DFmode), | |
0cc5dec1 | 2526 | EMIT_BEFORE); |
00fc055e RS |
2527 | } |
2528 | else | |
2529 | emit_pop_insn (insn, old, FP_MODE_REG (old->reg[old->top], DFmode), | |
0cc5dec1 | 2530 | EMIT_BEFORE); |
00fc055e | 2531 | } |
48227150 | 2532 | |
d858f359 | 2533 | if (new_stack->top == -2) |
48227150 JVA |
2534 | { |
2535 | /* If the new block has never been processed, then it can inherit | |
0f41302f | 2536 | the old stack order. */ |
48227150 | 2537 | |
d858f359 KG |
2538 | new_stack->top = old->top; |
2539 | memcpy (new_stack->reg, old->reg, sizeof (new_stack->reg)); | |
48227150 JVA |
2540 | } |
2541 | else | |
2542 | { | |
2543 | /* This block has been entered before, and we must match the | |
0f41302f | 2544 | previously selected stack order. */ |
48227150 JVA |
2545 | |
2546 | /* By now, the only difference should be the order of the stack, | |
0f41302f | 2547 | not their depth or liveliness. */ |
48227150 | 2548 | |
d858f359 KG |
2549 | gcc_assert (hard_reg_set_equal_p (old->reg_set, new_stack->reg_set)); |
2550 | gcc_assert (old->top == new_stack->top); | |
48227150 | 2551 | |
d858f359 | 2552 | /* If the stack is not empty (new_stack->top != -1), loop here emitting |
a6a2274a | 2553 | swaps until the stack is correct. |
80832cf2 HB |
2554 | |
2555 | The worst case number of swaps emitted is N + 2, where N is the | |
48227150 JVA |
2556 | depth of the stack. In some cases, the reg at the top of |
2557 | stack may be correct, but swapped anyway in order to fix | |
2558 | other regs. But since we never swap any other reg away from | |
0f41302f | 2559 | its correct slot, this algorithm will converge. */ |
48227150 | 2560 | |
d858f359 | 2561 | if (new_stack->top != -1) |
80832cf2 HB |
2562 | do |
2563 | { | |
2564 | /* Swap the reg at top of stack into the position it is | |
2565 | supposed to be in, until the correct top of stack appears. */ | |
48227150 | 2566 | |
d858f359 | 2567 | while (old->reg[old->top] != new_stack->reg[new_stack->top]) |
80832cf2 | 2568 | { |
d858f359 KG |
2569 | for (reg = new_stack->top; reg >= 0; reg--) |
2570 | if (new_stack->reg[reg] == old->reg[old->top]) | |
80832cf2 | 2571 | break; |
48227150 | 2572 | |
41374e13 | 2573 | gcc_assert (reg != -1); |
48227150 | 2574 | |
80832cf2 HB |
2575 | emit_swap_insn (insn, old, |
2576 | FP_MODE_REG (old->reg[reg], DFmode)); | |
2577 | } | |
48227150 | 2578 | |
80832cf2 | 2579 | /* See if any regs remain incorrect. If so, bring an |
48227150 | 2580 | incorrect reg to the top of stack, and let the while loop |
0f41302f | 2581 | above fix it. */ |
48227150 | 2582 | |
d858f359 KG |
2583 | for (reg = new_stack->top; reg >= 0; reg--) |
2584 | if (new_stack->reg[reg] != old->reg[reg]) | |
80832cf2 HB |
2585 | { |
2586 | emit_swap_insn (insn, old, | |
2587 | FP_MODE_REG (old->reg[reg], DFmode)); | |
2588 | break; | |
2589 | } | |
2590 | } while (reg >= 0); | |
48227150 | 2591 | |
0f41302f | 2592 | /* At this point there must be no differences. */ |
48227150 JVA |
2593 | |
2594 | for (reg = old->top; reg >= 0; reg--) | |
d858f359 | 2595 | gcc_assert (old->reg[reg] == new_stack->reg[reg]); |
48227150 | 2596 | } |
a05924f9 JH |
2597 | |
2598 | if (update_end) | |
1130d5e3 | 2599 | BB_END (current_block) = PREV_INSN (insn); |
48227150 JVA |
2600 | } |
2601 | \f | |
a05924f9 | 2602 | /* Print stack configuration. */ |
48227150 JVA |
2603 | |
2604 | static void | |
0823efed | 2605 | print_stack (FILE *file, stack_ptr s) |
48227150 | 2606 | { |
a05924f9 JH |
2607 | if (! file) |
2608 | return; | |
48227150 | 2609 | |
a05924f9 JH |
2610 | if (s->top == -2) |
2611 | fprintf (file, "uninitialized\n"); | |
2612 | else if (s->top == -1) | |
2613 | fprintf (file, "empty\n"); | |
2614 | else | |
e075ae69 | 2615 | { |
a05924f9 JH |
2616 | int i; |
2617 | fputs ("[ ", file); | |
2618 | for (i = 0; i <= s->top; ++i) | |
2619 | fprintf (file, "%d ", s->reg[i]); | |
2620 | fputs ("]\n", file); | |
e075ae69 | 2621 | } |
a05924f9 JH |
2622 | } |
2623 | \f | |
2624 | /* This function was doing life analysis. We now let the regular live | |
a6a2274a | 2625 | code do it's job, so we only need to check some extra invariants |
a05924f9 JH |
2626 | that reg-stack expects. Primary among these being that all registers |
2627 | are initialized before use. | |
48227150 | 2628 | |
a05924f9 JH |
2629 | The function returns true when code was emitted to CFG edges and |
2630 | commit_edge_insertions needs to be called. */ | |
48227150 | 2631 | |
a05924f9 | 2632 | static int |
0c20a65f | 2633 | convert_regs_entry (void) |
a05924f9 | 2634 | { |
e0082a72 | 2635 | int inserted = 0; |
a05924f9 | 2636 | edge e; |
628f6a4e | 2637 | edge_iterator ei; |
48227150 | 2638 | |
fa283935 | 2639 | /* Load something into each stack register live at function entry. |
a05924f9 | 2640 | Such live registers can be caused by uninitialized variables or |
a6a2274a | 2641 | functions not returning values on all paths. In order to keep |
a05924f9 | 2642 | the push/pop code happy, and to not scrog the register stack, we |
a6a2274a | 2643 | must put something in these registers. Use a QNaN. |
48227150 | 2644 | |
d55d8fc7 | 2645 | Note that we are inserting converted code here. This code is |
a05924f9 | 2646 | never seen by the convert_regs pass. */ |
48227150 | 2647 | |
fefa31b5 | 2648 | FOR_EACH_EDGE (e, ei, ENTRY_BLOCK_PTR_FOR_FN (cfun)->succs) |
a05924f9 JH |
2649 | { |
2650 | basic_block block = e->dest; | |
2651 | block_info bi = BLOCK_INFO (block); | |
2652 | int reg, top = -1; | |
48227150 | 2653 | |
a05924f9 | 2654 | for (reg = LAST_STACK_REG; reg >= FIRST_STACK_REG; --reg) |
fa283935 | 2655 | if (TEST_HARD_REG_BIT (bi->stack_in.reg_set, reg)) |
a05924f9 JH |
2656 | { |
2657 | rtx init; | |
48227150 | 2658 | |
a05924f9 | 2659 | bi->stack_in.reg[++top] = reg; |
48227150 | 2660 | |
f7df4a84 | 2661 | init = gen_rtx_SET (FP_MODE_REG (FIRST_STACK_REG, SFmode), |
d2032ad8 | 2662 | not_a_num); |
a05924f9 JH |
2663 | insert_insn_on_edge (init, e); |
2664 | inserted = 1; | |
2665 | } | |
48227150 | 2666 | |
a05924f9 JH |
2667 | bi->stack_in.top = top; |
2668 | } | |
48227150 | 2669 | |
a05924f9 JH |
2670 | return inserted; |
2671 | } | |
48227150 | 2672 | |
a05924f9 JH |
2673 | /* Construct the desired stack for function exit. This will either |
2674 | be `empty', or the function return value at top-of-stack. */ | |
48227150 | 2675 | |
a05924f9 | 2676 | static void |
0c20a65f | 2677 | convert_regs_exit (void) |
a05924f9 JH |
2678 | { |
2679 | int value_reg_low, value_reg_high; | |
0823efed | 2680 | stack_ptr output_stack; |
a05924f9 | 2681 | rtx retvalue; |
48227150 | 2682 | |
a05924f9 JH |
2683 | retvalue = stack_result (current_function_decl); |
2684 | value_reg_low = value_reg_high = -1; | |
2685 | if (retvalue) | |
2686 | { | |
2687 | value_reg_low = REGNO (retvalue); | |
72d19505 | 2688 | value_reg_high = END_REGNO (retvalue) - 1; |
a05924f9 | 2689 | } |
48227150 | 2690 | |
fefa31b5 | 2691 | output_stack = &BLOCK_INFO (EXIT_BLOCK_PTR_FOR_FN (cfun))->stack_in; |
a05924f9 JH |
2692 | if (value_reg_low == -1) |
2693 | output_stack->top = -1; | |
2694 | else | |
2695 | { | |
2696 | int reg; | |
48227150 | 2697 | |
a05924f9 JH |
2698 | output_stack->top = value_reg_high - value_reg_low; |
2699 | for (reg = value_reg_low; reg <= value_reg_high; ++reg) | |
2700 | { | |
bc9c2952 | 2701 | output_stack->reg[value_reg_high - reg] = reg; |
a05924f9 JH |
2702 | SET_HARD_REG_BIT (output_stack->reg_set, reg); |
2703 | } | |
2704 | } | |
48227150 | 2705 | } |
48227150 | 2706 | |
0ac2a27a RS |
2707 | /* Copy the stack info from the end of edge E's source block to the |
2708 | start of E's destination block. */ | |
1c320f82 RS |
2709 | |
2710 | static void | |
2711 | propagate_stack (edge e) | |
2712 | { | |
0823efed DN |
2713 | stack_ptr src_stack = &BLOCK_INFO (e->src)->stack_out; |
2714 | stack_ptr dest_stack = &BLOCK_INFO (e->dest)->stack_in; | |
0ac2a27a | 2715 | int reg; |
1c320f82 | 2716 | |
0ac2a27a RS |
2717 | /* Preserve the order of the original stack, but check whether |
2718 | any pops are needed. */ | |
2719 | dest_stack->top = -1; | |
2720 | for (reg = 0; reg <= src_stack->top; ++reg) | |
2721 | if (TEST_HARD_REG_BIT (dest_stack->reg_set, src_stack->reg[reg])) | |
2722 | dest_stack->reg[++dest_stack->top] = src_stack->reg[reg]; | |
6fb5fa3c DB |
2723 | |
2724 | /* Push in any partially dead values. */ | |
2725 | for (reg = FIRST_STACK_REG; reg < LAST_STACK_REG + 1; reg++) | |
2726 | if (TEST_HARD_REG_BIT (dest_stack->reg_set, reg) | |
2727 | && !TEST_HARD_REG_BIT (src_stack->reg_set, reg)) | |
2728 | dest_stack->reg[++dest_stack->top] = reg; | |
1c320f82 RS |
2729 | } |
2730 | ||
2731 | ||
2732 | /* Adjust the stack of edge E's source block on exit to match the stack | |
2733 | of it's target block upon input. The stack layouts of both blocks | |
2734 | should have been defined by now. */ | |
2735 | ||
0ecf09f9 | 2736 | static bool |
10d22567 | 2737 | compensate_edge (edge e) |
0ecf09f9 | 2738 | { |
579e4a82 | 2739 | basic_block source = e->src, target = e->dest; |
0823efed DN |
2740 | stack_ptr target_stack = &BLOCK_INFO (target)->stack_in; |
2741 | stack_ptr source_stack = &BLOCK_INFO (source)->stack_out; | |
579e4a82 | 2742 | struct stack_def regstack; |
0ecf09f9 JH |
2743 | int reg; |
2744 | ||
10d22567 ZD |
2745 | if (dump_file) |
2746 | fprintf (dump_file, "Edge %d->%d: ", source->index, target->index); | |
0ecf09f9 | 2747 | |
1c320f82 RS |
2748 | gcc_assert (target_stack->top != -2); |
2749 | ||
2750 | /* Check whether stacks are identical. */ | |
579e4a82 | 2751 | if (target_stack->top == source_stack->top) |
0ecf09f9 | 2752 | { |
1c320f82 | 2753 | for (reg = target_stack->top; reg >= 0; --reg) |
579e4a82 | 2754 | if (target_stack->reg[reg] != source_stack->reg[reg]) |
0ecf09f9 JH |
2755 | break; |
2756 | ||
2757 | if (reg == -1) | |
2758 | { | |
10d22567 ZD |
2759 | if (dump_file) |
2760 | fprintf (dump_file, "no changes needed\n"); | |
a6a2274a | 2761 | return false; |
0ecf09f9 | 2762 | } |
0ecf09f9 | 2763 | } |
0ecf09f9 | 2764 | |
10d22567 | 2765 | if (dump_file) |
1c320f82 | 2766 | { |
10d22567 ZD |
2767 | fprintf (dump_file, "correcting stack to "); |
2768 | print_stack (dump_file, target_stack); | |
0ecf09f9 JH |
2769 | } |
2770 | ||
579e4a82 | 2771 | /* Abnormal calls may appear to have values live in st(0), but the |
0ecf09f9 | 2772 | abnormal return path will not have actually loaded the values. */ |
579e4a82 | 2773 | if (e->flags & EDGE_ABNORMAL_CALL) |
0ecf09f9 JH |
2774 | { |
2775 | /* Assert that the lifetimes are as we expect -- one value | |
2776 | live at st(0) on the end of the source block, and no | |
6f7e2c0c RS |
2777 | values live at the beginning of the destination block. |
2778 | For complex return values, we may have st(1) live as well. */ | |
2779 | gcc_assert (source_stack->top == 0 || source_stack->top == 1); | |
579e4a82 RS |
2780 | gcc_assert (target_stack->top == -1); |
2781 | return false; | |
2782 | } | |
0ecf09f9 | 2783 | |
579e4a82 RS |
2784 | /* Handle non-call EH edges specially. The normal return path have |
2785 | values in registers. These will be popped en masse by the unwind | |
2786 | library. */ | |
2787 | if (e->flags & EDGE_EH) | |
2788 | { | |
2789 | gcc_assert (target_stack->top == -1); | |
2790 | return false; | |
0ecf09f9 JH |
2791 | } |
2792 | ||
579e4a82 RS |
2793 | /* We don't support abnormal edges. Global takes care to |
2794 | avoid any live register across them, so we should never | |
2795 | have to insert instructions on such edges. */ | |
2796 | gcc_assert (! (e->flags & EDGE_ABNORMAL)); | |
2797 | ||
2798 | /* Make a copy of source_stack as change_stack is destructive. */ | |
2799 | regstack = *source_stack; | |
2800 | ||
0ecf09f9 JH |
2801 | /* It is better to output directly to the end of the block |
2802 | instead of to the edge, because emit_swap can do minimal | |
2803 | insn scheduling. We can do this when there is only one | |
2804 | edge out, and it is not abnormal. */ | |
579e4a82 | 2805 | if (EDGE_COUNT (source->succs) == 1) |
0ecf09f9 | 2806 | { |
579e4a82 RS |
2807 | current_block = source; |
2808 | change_stack (BB_END (source), ®stack, target_stack, | |
2809 | (JUMP_P (BB_END (source)) ? EMIT_BEFORE : EMIT_AFTER)); | |
0ecf09f9 JH |
2810 | } |
2811 | else | |
2812 | { | |
66e8df53 DM |
2813 | rtx_insn *seq; |
2814 | rtx_note *after; | |
0ecf09f9 | 2815 | |
0ecf09f9 JH |
2816 | current_block = NULL; |
2817 | start_sequence (); | |
2818 | ||
2f937369 | 2819 | /* ??? change_stack needs some point to emit insns after. */ |
2e040219 | 2820 | after = emit_note (NOTE_INSN_DELETED); |
0ecf09f9 | 2821 | |
579e4a82 | 2822 | change_stack (after, ®stack, target_stack, EMIT_BEFORE); |
0ecf09f9 | 2823 | |
2f937369 | 2824 | seq = get_insns (); |
0ecf09f9 JH |
2825 | end_sequence (); |
2826 | ||
2827 | insert_insn_on_edge (seq, e); | |
2828 | return true; | |
2829 | } | |
2830 | return false; | |
2831 | } | |
2832 | ||
1c320f82 RS |
2833 | /* Traverse all non-entry edges in the CFG, and emit the necessary |
2834 | edge compensation code to change the stack from stack_out of the | |
2835 | source block to the stack_in of the destination block. */ | |
2836 | ||
2837 | static bool | |
10d22567 | 2838 | compensate_edges (void) |
1c320f82 RS |
2839 | { |
2840 | bool inserted = false; | |
2841 | basic_block bb; | |
2842 | ||
385e0e08 RS |
2843 | starting_stack_p = false; |
2844 | ||
11cd3bed | 2845 | FOR_EACH_BB_FN (bb, cfun) |
fefa31b5 | 2846 | if (bb != ENTRY_BLOCK_PTR_FOR_FN (cfun)) |
1c320f82 RS |
2847 | { |
2848 | edge e; | |
2849 | edge_iterator ei; | |
2850 | ||
2851 | FOR_EACH_EDGE (e, ei, bb->succs) | |
10d22567 | 2852 | inserted |= compensate_edge (e); |
1c320f82 RS |
2853 | } |
2854 | return inserted; | |
2855 | } | |
2856 | ||
0ac2a27a RS |
2857 | /* Select the better of two edges E1 and E2 to use to determine the |
2858 | stack layout for their shared destination basic block. This is | |
2859 | typically the more frequently executed. The edge E1 may be NULL | |
2860 | (in which case E2 is returned), but E2 is always non-NULL. */ | |
2861 | ||
2862 | static edge | |
2863 | better_edge (edge e1, edge e2) | |
2864 | { | |
2865 | if (!e1) | |
2866 | return e2; | |
2867 | ||
2868 | if (EDGE_FREQUENCY (e1) > EDGE_FREQUENCY (e2)) | |
2869 | return e1; | |
2870 | if (EDGE_FREQUENCY (e1) < EDGE_FREQUENCY (e2)) | |
2871 | return e2; | |
2872 | ||
2873 | if (e1->count > e2->count) | |
2874 | return e1; | |
2875 | if (e1->count < e2->count) | |
2876 | return e2; | |
2877 | ||
2878 | /* Prefer critical edges to minimize inserting compensation code on | |
2879 | critical edges. */ | |
2880 | ||
2881 | if (EDGE_CRITICAL_P (e1) != EDGE_CRITICAL_P (e2)) | |
2882 | return EDGE_CRITICAL_P (e1) ? e1 : e2; | |
2883 | ||
a4d05547 | 2884 | /* Avoid non-deterministic behavior. */ |
0ac2a27a RS |
2885 | return (e1->src->index < e2->src->index) ? e1 : e2; |
2886 | } | |
2887 | ||
12929514 EB |
2888 | /* Convert stack register references in one block. Return true if the CFG |
2889 | has been modified in the process. */ | |
a05924f9 | 2890 | |
12929514 | 2891 | static bool |
10d22567 | 2892 | convert_regs_1 (basic_block block) |
48227150 | 2893 | { |
0ecf09f9 | 2894 | struct stack_def regstack; |
a05924f9 | 2895 | block_info bi = BLOCK_INFO (block); |
1c320f82 | 2896 | int reg; |
d8aeaba0 | 2897 | rtx_insn *insn, *next; |
ecb63641 | 2898 | bool control_flow_insn_deleted = false; |
12929514 | 2899 | bool cfg_altered = false; |
b5b8b0ac | 2900 | int debug_insns_with_starting_stack = 0; |
48227150 | 2901 | |
d6fc0492 | 2902 | any_malformed_asm = false; |
0ecf09f9 | 2903 | |
0ac2a27a | 2904 | /* Choose an initial stack layout, if one hasn't already been chosen. */ |
0ecf09f9 | 2905 | if (bi->stack_in.top == -2) |
b3cd99cd | 2906 | { |
0ac2a27a RS |
2907 | edge e, beste = NULL; |
2908 | edge_iterator ei; | |
2909 | ||
2910 | /* Select the best incoming edge (typically the most frequent) to | |
2911 | use as a template for this basic block. */ | |
2912 | FOR_EACH_EDGE (e, ei, block->preds) | |
2913 | if (BLOCK_INFO (e->src)->done) | |
2914 | beste = better_edge (beste, e); | |
2915 | ||
b3cd99cd | 2916 | if (beste) |
1c320f82 | 2917 | propagate_stack (beste); |
b3cd99cd EB |
2918 | else |
2919 | { | |
2920 | /* No predecessors. Create an arbitrary input stack. */ | |
b3cd99cd EB |
2921 | bi->stack_in.top = -1; |
2922 | for (reg = LAST_STACK_REG; reg >= FIRST_STACK_REG; --reg) | |
2923 | if (TEST_HARD_REG_BIT (bi->stack_in.reg_set, reg)) | |
2924 | bi->stack_in.reg[++bi->stack_in.top] = reg; | |
2925 | } | |
2926 | } | |
a6a2274a | 2927 | |
10d22567 | 2928 | if (dump_file) |
48227150 | 2929 | { |
10d22567 ZD |
2930 | fprintf (dump_file, "\nBasic block %d\nInput stack: ", block->index); |
2931 | print_stack (dump_file, &bi->stack_in); | |
a05924f9 | 2932 | } |
48227150 | 2933 | |
a05924f9 JH |
2934 | /* Process all insns in this block. Keep track of NEXT so that we |
2935 | don't process insns emitted while substituting in INSN. */ | |
385e0e08 | 2936 | current_block = block; |
a813c111 | 2937 | next = BB_HEAD (block); |
a05924f9 | 2938 | regstack = bi->stack_in; |
385e0e08 RS |
2939 | starting_stack_p = true; |
2940 | ||
a05924f9 JH |
2941 | do |
2942 | { | |
2943 | insn = next; | |
2944 | next = NEXT_INSN (insn); | |
48227150 | 2945 | |
a05924f9 | 2946 | /* Ensure we have not missed a block boundary. */ |
41374e13 | 2947 | gcc_assert (next); |
a813c111 | 2948 | if (insn == BB_END (block)) |
a05924f9 JH |
2949 | next = NULL; |
2950 | ||
2951 | /* Don't bother processing unless there is a stack reg | |
2952 | mentioned or if it's a CALL_INSN. */ | |
b5b8b0ac AO |
2953 | if (DEBUG_INSN_P (insn)) |
2954 | { | |
2955 | if (starting_stack_p) | |
2956 | debug_insns_with_starting_stack++; | |
2957 | else | |
2958 | { | |
a7a110bb | 2959 | subst_all_stack_regs_in_debug_insn (insn, ®stack); |
b5b8b0ac AO |
2960 | |
2961 | /* Nothing must ever die at a debug insn. If something | |
2962 | is referenced in it that becomes dead, it should have | |
2963 | died before and the reference in the debug insn | |
2964 | should have been removed so as to avoid changing code | |
2965 | generation. */ | |
2966 | gcc_assert (!find_reg_note (insn, REG_DEAD, NULL)); | |
2967 | } | |
2968 | } | |
2969 | else if (stack_regs_mentioned (insn) | |
2970 | || CALL_P (insn)) | |
a05924f9 | 2971 | { |
10d22567 | 2972 | if (dump_file) |
a05924f9 | 2973 | { |
10d22567 | 2974 | fprintf (dump_file, " insn %d input stack: ", |
a05924f9 | 2975 | INSN_UID (insn)); |
10d22567 | 2976 | print_stack (dump_file, ®stack); |
a05924f9 | 2977 | } |
ecb63641 | 2978 | control_flow_insn_deleted |= subst_stack_regs (insn, ®stack); |
385e0e08 | 2979 | starting_stack_p = false; |
48227150 | 2980 | } |
a05924f9 JH |
2981 | } |
2982 | while (next); | |
48227150 | 2983 | |
b5b8b0ac AO |
2984 | if (debug_insns_with_starting_stack) |
2985 | { | |
2986 | /* Since it's the first non-debug instruction that determines | |
2987 | the stack requirements of the current basic block, we refrain | |
2988 | from updating debug insns before it in the loop above, and | |
2989 | fix them up here. */ | |
2990 | for (insn = BB_HEAD (block); debug_insns_with_starting_stack; | |
2991 | insn = NEXT_INSN (insn)) | |
2992 | { | |
2993 | if (!DEBUG_INSN_P (insn)) | |
2994 | continue; | |
2995 | ||
2996 | debug_insns_with_starting_stack--; | |
a7a110bb | 2997 | subst_all_stack_regs_in_debug_insn (insn, &bi->stack_in); |
b5b8b0ac AO |
2998 | } |
2999 | } | |
3000 | ||
10d22567 | 3001 | if (dump_file) |
a05924f9 | 3002 | { |
10d22567 | 3003 | fprintf (dump_file, "Expected live registers ["); |
a05924f9 JH |
3004 | for (reg = FIRST_STACK_REG; reg <= LAST_STACK_REG; ++reg) |
3005 | if (TEST_HARD_REG_BIT (bi->out_reg_set, reg)) | |
10d22567 ZD |
3006 | fprintf (dump_file, " %d", reg); |
3007 | fprintf (dump_file, " ]\nOutput stack: "); | |
3008 | print_stack (dump_file, ®stack); | |
a05924f9 | 3009 | } |
48227150 | 3010 | |
a813c111 | 3011 | insn = BB_END (block); |
4b4bf941 | 3012 | if (JUMP_P (insn)) |
a05924f9 JH |
3013 | insn = PREV_INSN (insn); |
3014 | ||
3015 | /* If the function is declared to return a value, but it returns one | |
3016 | in only some cases, some registers might come live here. Emit | |
3017 | necessary moves for them. */ | |
3018 | ||
3019 | for (reg = FIRST_STACK_REG; reg <= LAST_STACK_REG; ++reg) | |
3020 | { | |
3021 | if (TEST_HARD_REG_BIT (bi->out_reg_set, reg) | |
3022 | && ! TEST_HARD_REG_BIT (regstack.reg_set, reg)) | |
48227150 | 3023 | { |
a05924f9 | 3024 | rtx set; |
48227150 | 3025 | |
10d22567 ZD |
3026 | if (dump_file) |
3027 | fprintf (dump_file, "Emitting insn initializing reg %d\n", reg); | |
48227150 | 3028 | |
f7df4a84 | 3029 | set = gen_rtx_SET (FP_MODE_REG (reg, SFmode), not_a_num); |
3c030e88 | 3030 | insn = emit_insn_after (set, insn); |
ecb63641 | 3031 | control_flow_insn_deleted |= subst_stack_regs (insn, ®stack); |
a05924f9 JH |
3032 | } |
3033 | } | |
b8698a0f | 3034 | |
de582cfb EB |
3035 | /* Amongst the insns possibly deleted during the substitution process above, |
3036 | might have been the only trapping insn in the block. We purge the now | |
3037 | possibly dead EH edges here to avoid an ICE from fixup_abnormal_edges, | |
3038 | called at the end of convert_regs. The order in which we process the | |
3039 | blocks ensures that we never delete an already processed edge. | |
3040 | ||
ecb63641 EB |
3041 | Note that, at this point, the CFG may have been damaged by the emission |
3042 | of instructions after an abnormal call, which moves the basic block end | |
3043 | (and is the reason why we call fixup_abnormal_edges later). So we must | |
3044 | be sure that the trapping insn has been deleted before trying to purge | |
3045 | dead edges, otherwise we risk purging valid edges. | |
3046 | ||
de582cfb EB |
3047 | ??? We are normally supposed not to delete trapping insns, so we pretend |
3048 | that the insns deleted above don't actually trap. It would have been | |
3049 | better to detect this earlier and avoid creating the EH edge in the first | |
3050 | place, still, but we don't have enough information at that time. */ | |
3051 | ||
ecb63641 | 3052 | if (control_flow_insn_deleted) |
12929514 | 3053 | cfg_altered |= purge_dead_edges (block); |
48227150 | 3054 | |
d6fc0492 RH |
3055 | /* Something failed if the stack lives don't match. If we had malformed |
3056 | asms, we zapped the instruction itself, but that didn't produce the | |
3057 | same pattern of register kills as before. */ | |
b8698a0f | 3058 | |
56b138ae RS |
3059 | gcc_assert (hard_reg_set_equal_p (regstack.reg_set, bi->out_reg_set) |
3060 | || any_malformed_asm); | |
0ecf09f9 | 3061 | bi->stack_out = regstack; |
579e4a82 | 3062 | bi->done = true; |
12929514 EB |
3063 | |
3064 | return cfg_altered; | |
48227150 | 3065 | } |
48227150 | 3066 | |
12929514 EB |
3067 | /* Convert registers in all blocks reachable from BLOCK. Return true if the |
3068 | CFG has been modified in the process. */ | |
a05924f9 | 3069 | |
12929514 | 3070 | static bool |
10d22567 | 3071 | convert_regs_2 (basic_block block) |
48227150 | 3072 | { |
a05924f9 | 3073 | basic_block *stack, *sp; |
12929514 | 3074 | bool cfg_altered = false; |
48227150 | 3075 | |
de582cfb EB |
3076 | /* We process the blocks in a top-down manner, in a way such that one block |
3077 | is only processed after all its predecessors. The number of predecessors | |
b8698a0f | 3078 | of every block has already been computed. */ |
de582cfb | 3079 | |
0cae8d31 | 3080 | stack = XNEWVEC (basic_block, n_basic_blocks_for_fn (cfun)); |
a05924f9 | 3081 | sp = stack; |
48227150 | 3082 | |
a05924f9 | 3083 | *sp++ = block; |
48227150 | 3084 | |
a05924f9 JH |
3085 | do |
3086 | { | |
3087 | edge e; | |
628f6a4e | 3088 | edge_iterator ei; |
48227150 | 3089 | |
a05924f9 | 3090 | block = *--sp; |
48227150 | 3091 | |
b3cd99cd EB |
3092 | /* Processing BLOCK is achieved by convert_regs_1, which may purge |
3093 | some dead EH outgoing edge after the deletion of the trapping | |
3094 | insn inside the block. Since the number of predecessors of | |
3095 | BLOCK's successors was computed based on the initial edge set, | |
3096 | we check the necessity to process some of these successors | |
3097 | before such an edge deletion may happen. However, there is | |
3098 | a pitfall: if BLOCK is the only predecessor of a successor and | |
3099 | the edge between them happens to be deleted, the successor | |
3100 | becomes unreachable and should not be processed. The problem | |
3101 | is that there is no way to preventively detect this case so we | |
3102 | stack the successor in all cases and hand over the task of | |
3103 | fixing up the discrepancy to convert_regs_1. */ | |
3104 | ||
628f6a4e | 3105 | FOR_EACH_EDGE (e, ei, block->succs) |
0ecf09f9 | 3106 | if (! (e->flags & EDGE_DFS_BACK)) |
a05924f9 | 3107 | { |
754d9299 JM |
3108 | BLOCK_INFO (e->dest)->predecessors--; |
3109 | if (!BLOCK_INFO (e->dest)->predecessors) | |
628f6a4e | 3110 | *sp++ = e->dest; |
a05924f9 | 3111 | } |
de582cfb | 3112 | |
12929514 | 3113 | cfg_altered |= convert_regs_1 (block); |
48227150 | 3114 | } |
a05924f9 JH |
3115 | while (sp != stack); |
3116 | ||
3d5eef4c | 3117 | free (stack); |
12929514 EB |
3118 | |
3119 | return cfg_altered; | |
48227150 | 3120 | } |
841fc5a1 | 3121 | |
a05924f9 JH |
3122 | /* Traverse all basic blocks in a function, converting the register |
3123 | references in each insn from the "flat" register file that gcc uses, | |
3124 | to the stack-like registers the 387 uses. */ | |
3125 | ||
00b9ce5c | 3126 | static void |
10d22567 | 3127 | convert_regs (void) |
48227150 | 3128 | { |
12929514 | 3129 | bool cfg_altered = false; |
e0082a72 ZD |
3130 | int inserted; |
3131 | basic_block b; | |
a05924f9 | 3132 | edge e; |
628f6a4e | 3133 | edge_iterator ei; |
48227150 | 3134 | |
a05924f9 JH |
3135 | /* Initialize uninitialized registers on function entry. */ |
3136 | inserted = convert_regs_entry (); | |
48227150 | 3137 | |
a05924f9 JH |
3138 | /* Construct the desired stack for function exit. */ |
3139 | convert_regs_exit (); | |
fefa31b5 | 3140 | BLOCK_INFO (EXIT_BLOCK_PTR_FOR_FN (cfun))->done = 1; |
48227150 | 3141 | |
a05924f9 JH |
3142 | /* ??? Future: process inner loops first, and give them arbitrary |
3143 | initial stacks which emit_swap_insn can modify. This ought to | |
1ae58c30 | 3144 | prevent double fxch that often appears at the head of a loop. */ |
48227150 | 3145 | |
a05924f9 | 3146 | /* Process all blocks reachable from all entry points. */ |
fefa31b5 | 3147 | FOR_EACH_EDGE (e, ei, ENTRY_BLOCK_PTR_FOR_FN (cfun)->succs) |
12929514 | 3148 | cfg_altered |= convert_regs_2 (e->dest); |
a6a2274a KH |
3149 | |
3150 | /* ??? Process all unreachable blocks. Though there's no excuse | |
a05924f9 | 3151 | for keeping these even when not optimizing. */ |
11cd3bed | 3152 | FOR_EACH_BB_FN (b, cfun) |
a05924f9 | 3153 | { |
a05924f9 | 3154 | block_info bi = BLOCK_INFO (b); |
48227150 | 3155 | |
a05924f9 | 3156 | if (! bi->done) |
12929514 | 3157 | cfg_altered |= convert_regs_2 (b); |
a05924f9 | 3158 | } |
1c320f82 | 3159 | |
ba5e9aca EB |
3160 | /* We must fix up abnormal edges before inserting compensation code |
3161 | because both mechanisms insert insns on edges. */ | |
3162 | inserted |= fixup_abnormal_edges (); | |
3163 | ||
10d22567 | 3164 | inserted |= compensate_edges (); |
1c320f82 | 3165 | |
9dca2ad5 | 3166 | clear_aux_for_blocks (); |
48227150 | 3167 | |
a05924f9 JH |
3168 | if (inserted) |
3169 | commit_edge_insertions (); | |
48227150 | 3170 | |
12929514 EB |
3171 | if (cfg_altered) |
3172 | cleanup_cfg (0); | |
3173 | ||
10d22567 ZD |
3174 | if (dump_file) |
3175 | fputc ('\n', dump_file); | |
00b9ce5c RS |
3176 | } |
3177 | \f | |
3178 | /* Convert register usage from "flat" register file usage to a "stack | |
3179 | register file. FILE is the dump file, if used. | |
48227150 | 3180 | |
00b9ce5c RS |
3181 | Construct a CFG and run life analysis. Then convert each insn one |
3182 | by one. Run a last cleanup_cfg pass, if optimizing, to eliminate | |
3183 | code duplication created when the converter inserts pop insns on | |
3184 | the edges. */ | |
3185 | ||
cf4d5c75 | 3186 | static bool |
10d22567 | 3187 | reg_to_stack (void) |
00b9ce5c RS |
3188 | { |
3189 | basic_block bb; | |
3190 | int i; | |
3191 | int max_uid; | |
3192 | ||
3193 | /* Clean up previous run. */ | |
9771b263 | 3194 | stack_regs_mentioned_data.release (); |
00b9ce5c RS |
3195 | |
3196 | /* See if there is something to do. Flow analysis is quite | |
3197 | expensive so we might save some compilation time. */ | |
3198 | for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++) | |
6fb5fa3c | 3199 | if (df_regs_ever_live_p (i)) |
00b9ce5c RS |
3200 | break; |
3201 | if (i > LAST_STACK_REG) | |
3202 | return false; | |
3203 | ||
6fb5fa3c DB |
3204 | df_note_add_problem (); |
3205 | df_analyze (); | |
3206 | ||
00b9ce5c RS |
3207 | mark_dfs_back_edges (); |
3208 | ||
3209 | /* Set up block info for each basic block. */ | |
3210 | alloc_aux_for_blocks (sizeof (struct block_info_def)); | |
11cd3bed | 3211 | FOR_EACH_BB_FN (bb, cfun) |
00b9ce5c RS |
3212 | { |
3213 | block_info bi = BLOCK_INFO (bb); | |
3214 | edge_iterator ei; | |
3215 | edge e; | |
3216 | int reg; | |
3217 | ||
3218 | FOR_EACH_EDGE (e, ei, bb->preds) | |
3219 | if (!(e->flags & EDGE_DFS_BACK) | |
fefa31b5 | 3220 | && e->src != ENTRY_BLOCK_PTR_FOR_FN (cfun)) |
00b9ce5c RS |
3221 | bi->predecessors++; |
3222 | ||
3223 | /* Set current register status at last instruction `uninitialized'. */ | |
3224 | bi->stack_in.top = -2; | |
3225 | ||
3226 | /* Copy live_at_end and live_at_start into temporaries. */ | |
3227 | for (reg = FIRST_STACK_REG; reg <= LAST_STACK_REG; reg++) | |
3228 | { | |
6fb5fa3c | 3229 | if (REGNO_REG_SET_P (DF_LR_OUT (bb), reg)) |
00b9ce5c | 3230 | SET_HARD_REG_BIT (bi->out_reg_set, reg); |
6fb5fa3c | 3231 | if (REGNO_REG_SET_P (DF_LR_IN (bb), reg)) |
00b9ce5c RS |
3232 | SET_HARD_REG_BIT (bi->stack_in.reg_set, reg); |
3233 | } | |
3234 | } | |
3235 | ||
3236 | /* Create the replacement registers up front. */ | |
3237 | for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++) | |
3238 | { | |
ef4bddc2 | 3239 | machine_mode mode; |
00b9ce5c RS |
3240 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); |
3241 | mode != VOIDmode; | |
3242 | mode = GET_MODE_WIDER_MODE (mode)) | |
3243 | FP_MODE_REG (i, mode) = gen_rtx_REG (mode, i); | |
3244 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_COMPLEX_FLOAT); | |
3245 | mode != VOIDmode; | |
3246 | mode = GET_MODE_WIDER_MODE (mode)) | |
3247 | FP_MODE_REG (i, mode) = gen_rtx_REG (mode, i); | |
3248 | } | |
3249 | ||
3250 | ix86_flags_rtx = gen_rtx_REG (CCmode, FLAGS_REG); | |
3251 | ||
3252 | /* A QNaN for initializing uninitialized variables. | |
3253 | ||
3254 | ??? We can't load from constant memory in PIC mode, because | |
3255 | we're inserting these instructions before the prologue and | |
3256 | the PIC register hasn't been set up. In that case, fall back | |
11f48903 | 3257 | on zero, which we can get from `fldz'. */ |
00b9ce5c | 3258 | |
dc4d7240 JH |
3259 | if ((flag_pic && !TARGET_64BIT) |
3260 | || ix86_cmodel == CM_LARGE || ix86_cmodel == CM_LARGE_PIC) | |
00b9ce5c RS |
3261 | not_a_num = CONST0_RTX (SFmode); |
3262 | else | |
3263 | { | |
11f48903 UB |
3264 | REAL_VALUE_TYPE r; |
3265 | ||
3266 | real_nan (&r, "", 1, SFmode); | |
555affd7 | 3267 | not_a_num = const_double_from_real_value (r, SFmode); |
00b9ce5c RS |
3268 | not_a_num = force_const_mem (SFmode, not_a_num); |
3269 | } | |
3270 | ||
3271 | /* Allocate a cache for stack_regs_mentioned. */ | |
3272 | max_uid = get_max_uid (); | |
9771b263 DN |
3273 | stack_regs_mentioned_data.create (max_uid + 1); |
3274 | memset (stack_regs_mentioned_data.address (), | |
0a83b1b0 | 3275 | 0, sizeof (char) * (max_uid + 1)); |
00b9ce5c | 3276 | |
10d22567 | 3277 | convert_regs (); |
00b9ce5c RS |
3278 | |
3279 | free_aux_for_blocks (); | |
3280 | return true; | |
48227150 | 3281 | } |
48227150 | 3282 | #endif /* STACK_REGS */ |
ef330312 | 3283 | \f |
27a4cd48 DM |
3284 | namespace { |
3285 | ||
3286 | const pass_data pass_data_stack_regs = | |
6fb5fa3c | 3287 | { |
27a4cd48 DM |
3288 | RTL_PASS, /* type */ |
3289 | "*stack_regs", /* name */ | |
3290 | OPTGROUP_NONE, /* optinfo_flags */ | |
27a4cd48 DM |
3291 | TV_REG_STACK, /* tv_id */ |
3292 | 0, /* properties_required */ | |
3293 | 0, /* properties_provided */ | |
3294 | 0, /* properties_destroyed */ | |
3295 | 0, /* todo_flags_start */ | |
3296 | 0, /* todo_flags_finish */ | |
6fb5fa3c DB |
3297 | }; |
3298 | ||
27a4cd48 DM |
3299 | class pass_stack_regs : public rtl_opt_pass |
3300 | { | |
3301 | public: | |
c3284718 RS |
3302 | pass_stack_regs (gcc::context *ctxt) |
3303 | : rtl_opt_pass (pass_data_stack_regs, ctxt) | |
27a4cd48 DM |
3304 | {} |
3305 | ||
3306 | /* opt_pass methods: */ | |
1a3d085c TS |
3307 | virtual bool gate (function *) |
3308 | { | |
3309 | #ifdef STACK_REGS | |
3310 | return true; | |
3311 | #else | |
3312 | return false; | |
3313 | #endif | |
3314 | } | |
27a4cd48 DM |
3315 | |
3316 | }; // class pass_stack_regs | |
3317 | ||
3318 | } // anon namespace | |
3319 | ||
3320 | rtl_opt_pass * | |
3321 | make_pass_stack_regs (gcc::context *ctxt) | |
3322 | { | |
3323 | return new pass_stack_regs (ctxt); | |
3324 | } | |
3325 | ||
ef330312 PB |
3326 | /* Convert register usage from flat register file usage to a stack |
3327 | register file. */ | |
c2924966 | 3328 | static unsigned int |
ef330312 PB |
3329 | rest_of_handle_stack_regs (void) |
3330 | { | |
3331 | #ifdef STACK_REGS | |
6fb5fa3c DB |
3332 | reg_to_stack (); |
3333 | regstack_completed = 1; | |
ef330312 | 3334 | #endif |
c2924966 | 3335 | return 0; |
ef330312 PB |
3336 | } |
3337 | ||
27a4cd48 DM |
3338 | namespace { |
3339 | ||
3340 | const pass_data pass_data_stack_regs_run = | |
ef330312 | 3341 | { |
27a4cd48 DM |
3342 | RTL_PASS, /* type */ |
3343 | "stack", /* name */ | |
3344 | OPTGROUP_NONE, /* optinfo_flags */ | |
27a4cd48 DM |
3345 | TV_REG_STACK, /* tv_id */ |
3346 | 0, /* properties_required */ | |
3347 | 0, /* properties_provided */ | |
3348 | 0, /* properties_destroyed */ | |
3349 | 0, /* todo_flags_start */ | |
3bea341f | 3350 | TODO_df_finish, /* todo_flags_finish */ |
ef330312 | 3351 | }; |
27a4cd48 DM |
3352 | |
3353 | class pass_stack_regs_run : public rtl_opt_pass | |
3354 | { | |
3355 | public: | |
c3284718 RS |
3356 | pass_stack_regs_run (gcc::context *ctxt) |
3357 | : rtl_opt_pass (pass_data_stack_regs_run, ctxt) | |
27a4cd48 DM |
3358 | {} |
3359 | ||
3360 | /* opt_pass methods: */ | |
be55bfe6 TS |
3361 | virtual unsigned int execute (function *) |
3362 | { | |
3363 | return rest_of_handle_stack_regs (); | |
3364 | } | |
27a4cd48 DM |
3365 | |
3366 | }; // class pass_stack_regs_run | |
3367 | ||
3368 | } // anon namespace | |
3369 | ||
3370 | rtl_opt_pass * | |
3371 | make_pass_stack_regs_run (gcc::context *ctxt) | |
3372 | { | |
3373 | return new pass_stack_regs_run (ctxt); | |
3374 | } |