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54dac99e | 1 | /* Compute register class preferences for pseudo-registers. |
517cbe13 | 2 | Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996 |
e146f815 KH |
3 | 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 |
4 | Free Software Foundation, Inc. | |
54dac99e | 5 | |
1322177d | 6 | This file is part of GCC. |
54dac99e | 7 | |
1322177d LB |
8 | GCC is free software; you can redistribute it and/or modify it under |
9 | the terms of the GNU General Public License as published by the Free | |
10 | Software Foundation; either version 2, or (at your option) any later | |
11 | version. | |
54dac99e | 12 | |
1322177d LB |
13 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
14 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | for more details. | |
54dac99e RK |
17 | |
18 | You should have received a copy of the GNU General Public License | |
1322177d LB |
19 | along with GCC; see the file COPYING. If not, write to the Free |
20 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
21 | 02111-1307, USA. */ | |
54dac99e RK |
22 | |
23 | ||
24 | /* This file contains two passes of the compiler: reg_scan and reg_class. | |
25 | It also defines some tables of information about the hardware registers | |
26 | and a function init_reg_sets to initialize the tables. */ | |
27 | ||
28 | #include "config.h" | |
670ee920 | 29 | #include "system.h" |
4977bab6 ZW |
30 | #include "coretypes.h" |
31 | #include "tm.h" | |
cff9f8d5 | 32 | #include "hard-reg-set.h" |
54dac99e | 33 | #include "rtl.h" |
0829d244 | 34 | #include "expr.h" |
6baf1cc8 | 35 | #include "tm_p.h" |
54dac99e RK |
36 | #include "flags.h" |
37 | #include "basic-block.h" | |
38 | #include "regs.h" | |
49ad7cfa | 39 | #include "function.h" |
54dac99e RK |
40 | #include "insn-config.h" |
41 | #include "recog.h" | |
e4600702 RK |
42 | #include "reload.h" |
43 | #include "real.h" | |
10f0ad3d | 44 | #include "toplev.h" |
d6f4ec51 | 45 | #include "output.h" |
8b0212ca | 46 | #include "ggc.h" |
0d446150 | 47 | #include "timevar.h" |
54dac99e | 48 | |
0c20a65f | 49 | static void init_reg_sets_1 (void); |
0c20a65f | 50 | static void init_reg_autoinc (void); |
24deb20a | 51 | |
533d0835 RK |
52 | /* If we have auto-increment or auto-decrement and we can have secondary |
53 | reloads, we are not allowed to use classes requiring secondary | |
9faa82d8 | 54 | reloads for pseudos auto-incremented since reload can't handle it. */ |
533d0835 RK |
55 | |
56 | #ifdef AUTO_INC_DEC | |
dd9f0e8f | 57 | #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS) |
533d0835 RK |
58 | #define FORBIDDEN_INC_DEC_CLASSES |
59 | #endif | |
60 | #endif | |
54dac99e RK |
61 | \f |
62 | /* Register tables used by many passes. */ | |
63 | ||
64 | /* Indexed by hard register number, contains 1 for registers | |
65 | that are fixed use (stack pointer, pc, frame pointer, etc.). | |
66 | These are the registers that cannot be used to allocate | |
252f342a | 67 | a pseudo reg for general use. */ |
54dac99e RK |
68 | |
69 | char fixed_regs[FIRST_PSEUDO_REGISTER]; | |
70 | ||
71 | /* Same info as a HARD_REG_SET. */ | |
72 | ||
73 | HARD_REG_SET fixed_reg_set; | |
74 | ||
75 | /* Data for initializing the above. */ | |
76 | ||
8b60264b | 77 | static const char initial_fixed_regs[] = FIXED_REGISTERS; |
54dac99e RK |
78 | |
79 | /* Indexed by hard register number, contains 1 for registers | |
80 | that are fixed use or are clobbered by function calls. | |
81 | These are the registers that cannot be used to allocate | |
252f342a MH |
82 | a pseudo reg whose life crosses calls unless we are able |
83 | to save/restore them across the calls. */ | |
54dac99e RK |
84 | |
85 | char call_used_regs[FIRST_PSEUDO_REGISTER]; | |
86 | ||
87 | /* Same info as a HARD_REG_SET. */ | |
88 | ||
89 | HARD_REG_SET call_used_reg_set; | |
90 | ||
6cad67d2 JL |
91 | /* HARD_REG_SET of registers we want to avoid caller saving. */ |
92 | HARD_REG_SET losing_caller_save_reg_set; | |
93 | ||
54dac99e RK |
94 | /* Data for initializing the above. */ |
95 | ||
8b60264b | 96 | static const char initial_call_used_regs[] = CALL_USED_REGISTERS; |
fc1296b7 AM |
97 | |
98 | /* This is much like call_used_regs, except it doesn't have to | |
99 | be a superset of FIXED_REGISTERS. This vector indicates | |
a6a2274a | 100 | what is really call clobbered, and is used when defining |
fc1296b7 AM |
101 | regs_invalidated_by_call. */ |
102 | ||
fc1296b7 | 103 | #ifdef CALL_REALLY_USED_REGISTERS |
d3259baa | 104 | char call_really_used_regs[] = CALL_REALLY_USED_REGISTERS; |
fc1296b7 | 105 | #endif |
a6a2274a | 106 | |
54dac99e | 107 | /* Indexed by hard register number, contains 1 for registers that are |
252f342a MH |
108 | fixed use or call used registers that cannot hold quantities across |
109 | calls even if we are willing to save and restore them. call fixed | |
110 | registers are a subset of call used registers. */ | |
54dac99e RK |
111 | |
112 | char call_fixed_regs[FIRST_PSEUDO_REGISTER]; | |
113 | ||
114 | /* The same info as a HARD_REG_SET. */ | |
115 | ||
116 | HARD_REG_SET call_fixed_reg_set; | |
117 | ||
118 | /* Number of non-fixed registers. */ | |
119 | ||
120 | int n_non_fixed_regs; | |
121 | ||
122 | /* Indexed by hard register number, contains 1 for registers | |
123 | that are being used for global register decls. | |
124 | These must be exempt from ordinary flow analysis | |
125 | and are also considered fixed. */ | |
126 | ||
127 | char global_regs[FIRST_PSEUDO_REGISTER]; | |
4e2db584 RH |
128 | |
129 | /* Contains 1 for registers that are set or clobbered by calls. */ | |
130 | /* ??? Ideally, this would be just call_used_regs plus global_regs, but | |
131 | for someone's bright idea to have call_used_regs strictly include | |
132 | fixed_regs. Which leaves us guessing as to the set of fixed_regs | |
133 | that are actually preserved. We know for sure that those associated | |
134 | with the local stack frame are safe, but scant others. */ | |
135 | ||
136 | HARD_REG_SET regs_invalidated_by_call; | |
137 | ||
54dac99e RK |
138 | /* Table of register numbers in the order in which to try to use them. */ |
139 | #ifdef REG_ALLOC_ORDER | |
140 | int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER; | |
f5d8c9f4 BS |
141 | |
142 | /* The inverse of reg_alloc_order. */ | |
143 | int inv_reg_alloc_order[FIRST_PSEUDO_REGISTER]; | |
54dac99e RK |
144 | #endif |
145 | ||
146 | /* For each reg class, a HARD_REG_SET saying which registers are in it. */ | |
147 | ||
2e0e2b76 CH |
148 | HARD_REG_SET reg_class_contents[N_REG_CLASSES]; |
149 | ||
089e575b RS |
150 | /* The same information, but as an array of unsigned ints. We copy from |
151 | these unsigned ints to the table above. We do this so the tm.h files | |
d4845339 RH |
152 | do not have to be aware of the wordsize for machines with <= 64 regs. |
153 | Note that we hard-code 32 here, not HOST_BITS_PER_INT. */ | |
2e0e2b76 CH |
154 | |
155 | #define N_REG_INTS \ | |
d4845339 | 156 | ((FIRST_PSEUDO_REGISTER + (32 - 1)) / 32) |
2e0e2b76 | 157 | |
a6a2274a | 158 | static const unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS] |
2e0e2b76 | 159 | = REG_CLASS_CONTENTS; |
54dac99e RK |
160 | |
161 | /* For each reg class, number of regs it contains. */ | |
162 | ||
770ae6cc | 163 | unsigned int reg_class_size[N_REG_CLASSES]; |
54dac99e RK |
164 | |
165 | /* For each reg class, table listing all the containing classes. */ | |
166 | ||
167 | enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES]; | |
168 | ||
169 | /* For each reg class, table listing all the classes contained in it. */ | |
170 | ||
171 | enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES]; | |
172 | ||
173 | /* For each pair of reg classes, | |
174 | a largest reg class contained in their union. */ | |
175 | ||
176 | enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES]; | |
177 | ||
178 | /* For each pair of reg classes, | |
179 | the smallest reg class containing their union. */ | |
180 | ||
181 | enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES]; | |
182 | ||
94134f42 | 183 | /* Array containing all of the register names. */ |
d05c8ee7 | 184 | |
e087aeb2 | 185 | const char * reg_names[] = REGISTER_NAMES; |
d05c8ee7 | 186 | |
ca4aac00 DE |
187 | /* For each hard register, the widest mode object that it can contain. |
188 | This will be a MODE_INT mode if the register can hold integers. Otherwise | |
189 | it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the | |
190 | register. */ | |
191 | ||
192 | enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER]; | |
193 | ||
6df26b8f JH |
194 | /* 1 if class does contain register of given mode. */ |
195 | ||
196 | static char contains_reg_of_mode [N_REG_CLASSES] [MAX_MACHINE_MODE]; | |
197 | ||
e4600702 RK |
198 | /* Maximum cost of moving from a register in one class to a register in |
199 | another class. Based on REGISTER_MOVE_COST. */ | |
200 | ||
e56b4594 | 201 | static int move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES]; |
e4600702 RK |
202 | |
203 | /* Similar, but here we don't have to move if the first index is a subset | |
204 | of the second so in that case the cost is zero. */ | |
205 | ||
e56b4594 | 206 | static int may_move_in_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES]; |
ee59f29b JH |
207 | |
208 | /* Similar, but here we don't have to move if the first index is a superset | |
209 | of the second so in that case the cost is zero. */ | |
210 | ||
e56b4594 | 211 | static int may_move_out_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES]; |
e4600702 | 212 | |
533d0835 RK |
213 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
214 | ||
215 | /* These are the classes that regs which are auto-incremented or decremented | |
216 | cannot be put in. */ | |
217 | ||
218 | static int forbidden_inc_dec_class[N_REG_CLASSES]; | |
219 | ||
40f03658 | 220 | /* Indexed by n, is nonzero if (REG n) is used in an auto-inc or auto-dec |
533d0835 RK |
221 | context. */ |
222 | ||
223 | static char *in_inc_dec; | |
224 | ||
5fcb671c | 225 | #endif /* FORBIDDEN_INC_DEC_CLASSES */ |
533d0835 | 226 | |
cff9f8d5 | 227 | #ifdef CANNOT_CHANGE_MODE_CLASS |
10a3fdd9 JH |
228 | /* All registers that have been subreged. Indexed by regno * MAX_MACHINE_MODE |
229 | + mode. */ | |
230 | bitmap_head subregs_of_mode; | |
cff9f8d5 | 231 | #endif |
e79f71f7 | 232 | |
473fe49b KR |
233 | /* Sample MEM values for use by memory_move_secondary_cost. */ |
234 | ||
e2500fed | 235 | static GTY(()) rtx top_of_stack[MAX_MACHINE_MODE]; |
473fe49b | 236 | |
6feacd09 MM |
237 | /* Linked list of reg_info structures allocated for reg_n_info array. |
238 | Grouping all of the allocated structures together in one lump | |
239 | means only one call to bzero to clear them, rather than n smaller | |
240 | calls. */ | |
241 | struct reg_info_data { | |
242 | struct reg_info_data *next; /* next set of reg_info structures */ | |
243 | size_t min_index; /* minimum index # */ | |
244 | size_t max_index; /* maximum index # */ | |
40f03658 | 245 | char used_p; /* nonzero if this has been used previously */ |
6feacd09 MM |
246 | reg_info data[1]; /* beginning of the reg_info data */ |
247 | }; | |
248 | ||
249 | static struct reg_info_data *reg_info_head; | |
250 | ||
c07c7c9d | 251 | /* No more global register variables may be declared; true once |
dc297297 | 252 | regclass has been initialized. */ |
6c85df69 AH |
253 | |
254 | static int no_global_reg_vars = 0; | |
255 | ||
66fd46b6 JH |
256 | /* Specify number of hard registers given machine mode occupy. */ |
257 | unsigned char hard_regno_nregs[FIRST_PSEUDO_REGISTER][MAX_MACHINE_MODE]; | |
6feacd09 | 258 | |
54dac99e RK |
259 | /* Function called only once to initialize the above data on reg usage. |
260 | Once this is done, various switches may override. */ | |
261 | ||
262 | void | |
0c20a65f | 263 | init_reg_sets (void) |
54dac99e | 264 | { |
b3694847 | 265 | int i, j; |
54dac99e | 266 | |
2e0e2b76 CH |
267 | /* First copy the register information from the initial int form into |
268 | the regsets. */ | |
269 | ||
270 | for (i = 0; i < N_REG_CLASSES; i++) | |
271 | { | |
272 | CLEAR_HARD_REG_SET (reg_class_contents[i]); | |
273 | ||
b85946fc | 274 | /* Note that we hard-code 32 here, not HOST_BITS_PER_INT. */ |
2e0e2b76 | 275 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) |
b85946fc RH |
276 | if (int_reg_class_contents[i][j / 32] |
277 | & ((unsigned) 1 << (j % 32))) | |
2e0e2b76 CH |
278 | SET_HARD_REG_BIT (reg_class_contents[i], j); |
279 | } | |
280 | ||
4e135bdd KG |
281 | memcpy (fixed_regs, initial_fixed_regs, sizeof fixed_regs); |
282 | memcpy (call_used_regs, initial_call_used_regs, sizeof call_used_regs); | |
961192e1 | 283 | memset (global_regs, 0, sizeof global_regs); |
54dac99e | 284 | |
3eae4643 | 285 | /* Do any additional initialization regsets may need. */ |
910bc42d | 286 | INIT_ONCE_REG_SET (); |
f5d8c9f4 BS |
287 | |
288 | #ifdef REG_ALLOC_ORDER | |
289 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
290 | inv_reg_alloc_order[reg_alloc_order[i]] = i; | |
291 | #endif | |
910bc42d R |
292 | } |
293 | ||
294 | /* After switches have been processed, which perhaps alter | |
295 | `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */ | |
296 | ||
297 | static void | |
0c20a65f | 298 | init_reg_sets_1 (void) |
910bc42d | 299 | { |
b3694847 SS |
300 | unsigned int i, j; |
301 | unsigned int /* enum machine_mode */ m; | |
6836e024 | 302 | char allocatable_regs_of_mode [MAX_MACHINE_MODE]; |
910bc42d R |
303 | |
304 | /* This macro allows the fixed or call-used registers | |
305 | and the register classes to depend on target flags. */ | |
306 | ||
307 | #ifdef CONDITIONAL_REGISTER_USAGE | |
308 | CONDITIONAL_REGISTER_USAGE; | |
309 | #endif | |
310 | ||
54dac99e RK |
311 | /* Compute number of hard regs in each class. */ |
312 | ||
703ad42b | 313 | memset (reg_class_size, 0, sizeof reg_class_size); |
54dac99e RK |
314 | for (i = 0; i < N_REG_CLASSES; i++) |
315 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
316 | if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) | |
317 | reg_class_size[i]++; | |
318 | ||
319 | /* Initialize the table of subunions. | |
320 | reg_class_subunion[I][J] gets the largest-numbered reg-class | |
321 | that is contained in the union of classes I and J. */ | |
322 | ||
323 | for (i = 0; i < N_REG_CLASSES; i++) | |
324 | { | |
325 | for (j = 0; j < N_REG_CLASSES; j++) | |
326 | { | |
49a27995 | 327 | HARD_REG_SET c; |
b3694847 | 328 | int k; |
54dac99e RK |
329 | |
330 | COPY_HARD_REG_SET (c, reg_class_contents[i]); | |
331 | IOR_HARD_REG_SET (c, reg_class_contents[j]); | |
332 | for (k = 0; k < N_REG_CLASSES; k++) | |
333 | { | |
334 | GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c, | |
335 | subclass1); | |
336 | continue; | |
337 | ||
338 | subclass1: | |
938d968e | 339 | /* Keep the largest subclass. */ /* SPEE 900308 */ |
54dac99e RK |
340 | GO_IF_HARD_REG_SUBSET (reg_class_contents[k], |
341 | reg_class_contents[(int) reg_class_subunion[i][j]], | |
342 | subclass2); | |
343 | reg_class_subunion[i][j] = (enum reg_class) k; | |
344 | subclass2: | |
345 | ; | |
346 | } | |
347 | } | |
348 | } | |
349 | ||
350 | /* Initialize the table of superunions. | |
351 | reg_class_superunion[I][J] gets the smallest-numbered reg-class | |
352 | containing the union of classes I and J. */ | |
353 | ||
354 | for (i = 0; i < N_REG_CLASSES; i++) | |
355 | { | |
356 | for (j = 0; j < N_REG_CLASSES; j++) | |
357 | { | |
49a27995 | 358 | HARD_REG_SET c; |
b3694847 | 359 | int k; |
54dac99e RK |
360 | |
361 | COPY_HARD_REG_SET (c, reg_class_contents[i]); | |
362 | IOR_HARD_REG_SET (c, reg_class_contents[j]); | |
363 | for (k = 0; k < N_REG_CLASSES; k++) | |
364 | GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass); | |
365 | ||
366 | superclass: | |
367 | reg_class_superunion[i][j] = (enum reg_class) k; | |
368 | } | |
369 | } | |
370 | ||
371 | /* Initialize the tables of subclasses and superclasses of each reg class. | |
372 | First clear the whole table, then add the elements as they are found. */ | |
373 | ||
374 | for (i = 0; i < N_REG_CLASSES; i++) | |
375 | { | |
376 | for (j = 0; j < N_REG_CLASSES; j++) | |
377 | { | |
378 | reg_class_superclasses[i][j] = LIM_REG_CLASSES; | |
379 | reg_class_subclasses[i][j] = LIM_REG_CLASSES; | |
380 | } | |
381 | } | |
382 | ||
383 | for (i = 0; i < N_REG_CLASSES; i++) | |
384 | { | |
385 | if (i == (int) NO_REGS) | |
386 | continue; | |
387 | ||
388 | for (j = i + 1; j < N_REG_CLASSES; j++) | |
389 | { | |
390 | enum reg_class *p; | |
391 | ||
392 | GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j], | |
393 | subclass); | |
394 | continue; | |
395 | subclass: | |
396 | /* Reg class I is a subclass of J. | |
397 | Add J to the table of superclasses of I. */ | |
398 | p = ®_class_superclasses[i][0]; | |
399 | while (*p != LIM_REG_CLASSES) p++; | |
400 | *p = (enum reg_class) j; | |
401 | /* Add I to the table of superclasses of J. */ | |
402 | p = ®_class_subclasses[j][0]; | |
403 | while (*p != LIM_REG_CLASSES) p++; | |
404 | *p = (enum reg_class) i; | |
405 | } | |
406 | } | |
e4600702 | 407 | |
54dac99e RK |
408 | /* Initialize "constant" tables. */ |
409 | ||
410 | CLEAR_HARD_REG_SET (fixed_reg_set); | |
411 | CLEAR_HARD_REG_SET (call_used_reg_set); | |
412 | CLEAR_HARD_REG_SET (call_fixed_reg_set); | |
4e2db584 | 413 | CLEAR_HARD_REG_SET (regs_invalidated_by_call); |
54dac99e | 414 | |
4e135bdd | 415 | memcpy (call_fixed_regs, fixed_regs, sizeof call_fixed_regs); |
54dac99e RK |
416 | |
417 | n_non_fixed_regs = 0; | |
418 | ||
419 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
420 | { | |
54dac99e RK |
421 | if (fixed_regs[i]) |
422 | SET_HARD_REG_BIT (fixed_reg_set, i); | |
423 | else | |
424 | n_non_fixed_regs++; | |
425 | ||
426 | if (call_used_regs[i]) | |
427 | SET_HARD_REG_BIT (call_used_reg_set, i); | |
428 | if (call_fixed_regs[i]) | |
429 | SET_HARD_REG_BIT (call_fixed_reg_set, i); | |
6cad67d2 JL |
430 | if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i))) |
431 | SET_HARD_REG_BIT (losing_caller_save_reg_set, i); | |
4e2db584 RH |
432 | |
433 | /* There are a couple of fixed registers that we know are safe to | |
434 | exclude from being clobbered by calls: | |
435 | ||
436 | The frame pointer is always preserved across calls. The arg pointer | |
437 | is if it is fixed. The stack pointer usually is, unless | |
438 | RETURN_POPS_ARGS, in which case an explicit CLOBBER will be present. | |
439 | If we are generating PIC code, the PIC offset table register is | |
440 | preserved across calls, though the target can override that. */ | |
a6a2274a | 441 | |
4e2db584 RH |
442 | if (i == STACK_POINTER_REGNUM || i == FRAME_POINTER_REGNUM) |
443 | ; | |
444 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM | |
445 | else if (i == HARD_FRAME_POINTER_REGNUM) | |
446 | ; | |
447 | #endif | |
448 | #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM | |
449 | else if (i == ARG_POINTER_REGNUM && fixed_regs[i]) | |
450 | ; | |
451 | #endif | |
452 | #ifndef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED | |
fc555370 | 453 | else if (i == (unsigned) PIC_OFFSET_TABLE_REGNUM && fixed_regs[i]) |
4e2db584 RH |
454 | ; |
455 | #endif | |
d3259baa | 456 | else if (0 |
6ca3c22f | 457 | #ifdef CALL_REALLY_USED_REGISTERS |
d3259baa RH |
458 | || call_really_used_regs[i] |
459 | #else | |
460 | || call_used_regs[i] | |
461 | #endif | |
462 | || global_regs[i]) | |
4e2db584 | 463 | SET_HARD_REG_BIT (regs_invalidated_by_call, i); |
54dac99e | 464 | } |
4e2db584 | 465 | |
6836e024 JH |
466 | memset (contains_reg_of_mode, 0, sizeof (contains_reg_of_mode)); |
467 | memset (allocatable_regs_of_mode, 0, sizeof (allocatable_regs_of_mode)); | |
dbbbbf3b | 468 | for (m = 0; m < (unsigned int) MAX_MACHINE_MODE; m++) |
6836e024 | 469 | for (i = 0; i < N_REG_CLASSES; i++) |
f7043461 | 470 | if ((unsigned) CLASS_MAX_NREGS (i, m) <= reg_class_size[i]) |
6df26b8f JH |
471 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) |
472 | if (!fixed_regs [j] && TEST_HARD_REG_BIT (reg_class_contents[i], j) | |
473 | && HARD_REGNO_MODE_OK (j, m)) | |
474 | { | |
475 | contains_reg_of_mode [i][m] = 1; | |
476 | allocatable_regs_of_mode [m] = 1; | |
477 | break; | |
478 | } | |
acbce667 KR |
479 | |
480 | /* Initialize the move cost table. Find every subset of each class | |
481 | and take the maximum cost of moving any subset to any other. */ | |
482 | ||
dbbbbf3b | 483 | for (m = 0; m < (unsigned int) MAX_MACHINE_MODE; m++) |
6836e024 JH |
484 | if (allocatable_regs_of_mode [m]) |
485 | { | |
486 | for (i = 0; i < N_REG_CLASSES; i++) | |
487 | if (contains_reg_of_mode [i][m]) | |
488 | for (j = 0; j < N_REG_CLASSES; j++) | |
489 | { | |
490 | int cost; | |
491 | enum reg_class *p1, *p2; | |
492 | ||
493 | if (!contains_reg_of_mode [j][m]) | |
494 | { | |
495 | move_cost[m][i][j] = 65536; | |
496 | may_move_in_cost[m][i][j] = 65536; | |
497 | may_move_out_cost[m][i][j] = 65536; | |
498 | } | |
499 | else | |
500 | { | |
26a952a8 | 501 | cost = REGISTER_MOVE_COST (m, i, j); |
6836e024 JH |
502 | |
503 | for (p2 = ®_class_subclasses[j][0]; | |
504 | *p2 != LIM_REG_CLASSES; | |
505 | p2++) | |
506 | if (*p2 != i && contains_reg_of_mode [*p2][m]) | |
507 | cost = MAX (cost, move_cost [m][i][*p2]); | |
508 | ||
509 | for (p1 = ®_class_subclasses[i][0]; | |
510 | *p1 != LIM_REG_CLASSES; | |
511 | p1++) | |
512 | if (*p1 != j && contains_reg_of_mode [*p1][m]) | |
513 | cost = MAX (cost, move_cost [m][*p1][j]); | |
514 | ||
515 | move_cost[m][i][j] = cost; | |
516 | ||
517 | if (reg_class_subset_p (i, j)) | |
518 | may_move_in_cost[m][i][j] = 0; | |
519 | else | |
520 | may_move_in_cost[m][i][j] = cost; | |
521 | ||
522 | if (reg_class_subset_p (j, i)) | |
523 | may_move_out_cost[m][i][j] = 0; | |
524 | else | |
525 | may_move_out_cost[m][i][j] = cost; | |
526 | } | |
527 | } | |
1464632b | 528 | else |
6836e024 JH |
529 | for (j = 0; j < N_REG_CLASSES; j++) |
530 | { | |
531 | move_cost[m][i][j] = 65536; | |
532 | may_move_in_cost[m][i][j] = 65536; | |
533 | may_move_out_cost[m][i][j] = 65536; | |
534 | } | |
535 | } | |
c27c5281 DE |
536 | } |
537 | ||
538 | /* Compute the table of register modes. | |
539 | These values are used to record death information for individual registers | |
540 | (as opposed to a multi-register mode). */ | |
ca4aac00 | 541 | |
28420116 PB |
542 | void |
543 | init_reg_modes_once (void) | |
c27c5281 | 544 | { |
66fd46b6 JH |
545 | int i, j; |
546 | ||
547 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
548 | for (j = 0; j < MAX_MACHINE_MODE; j++) | |
549 | hard_regno_nregs[i][j] = HARD_REGNO_NREGS(i, (enum machine_mode)j); | |
ca4aac00 DE |
550 | |
551 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
7f21d440 | 552 | { |
fee226d2 | 553 | reg_raw_mode[i] = choose_hard_reg_mode (i, 1, false); |
7f21d440 | 554 | |
066c2fea | 555 | /* If we couldn't find a valid mode, just use the previous mode. |
7f21d440 DE |
556 | ??? One situation in which we need to do this is on the mips where |
557 | HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like | |
558 | to use DF mode for the even registers and VOIDmode for the odd | |
9faa82d8 | 559 | (for the cpu models where the odd ones are inaccessible). */ |
7f21d440 | 560 | if (reg_raw_mode[i] == VOIDmode) |
066c2fea | 561 | reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1]; |
7f21d440 | 562 | } |
ca4aac00 DE |
563 | } |
564 | ||
c27c5281 DE |
565 | /* Finish initializing the register sets and |
566 | initialize the register modes. */ | |
567 | ||
568 | void | |
0c20a65f | 569 | init_regs (void) |
c27c5281 DE |
570 | { |
571 | /* This finishes what was started by init_reg_sets, but couldn't be done | |
572 | until after register usage was specified. */ | |
b93a436e | 573 | init_reg_sets_1 (); |
c27c5281 | 574 | |
1f80c9ef | 575 | init_reg_autoinc (); |
6cde4876 JL |
576 | } |
577 | ||
578 | /* Initialize some fake stack-frame MEM references for use in | |
579 | memory_move_secondary_cost. */ | |
473fe49b | 580 | |
6cde4876 | 581 | void |
0c20a65f | 582 | init_fake_stack_mems (void) |
6cde4876 | 583 | { |
473fe49b KR |
584 | #ifdef HAVE_SECONDARY_RELOADS |
585 | { | |
473fe49b | 586 | int i; |
d067e2aa | 587 | |
473fe49b | 588 | for (i = 0; i < MAX_MACHINE_MODE; i++) |
9ec36da5 | 589 | top_of_stack[i] = gen_rtx_MEM (i, stack_pointer_rtx); |
473fe49b KR |
590 | } |
591 | #endif | |
c27c5281 DE |
592 | } |
593 | ||
cbd5b9a2 | 594 | #ifdef HAVE_SECONDARY_RELOADS |
473fe49b | 595 | |
cbd5b9a2 KR |
596 | /* Compute extra cost of moving registers to/from memory due to reloads. |
597 | Only needed if secondary reloads are required for memory moves. */ | |
473fe49b | 598 | |
cbd5b9a2 | 599 | int |
0c20a65f | 600 | memory_move_secondary_cost (enum machine_mode mode, enum reg_class class, int in) |
cbd5b9a2 KR |
601 | { |
602 | enum reg_class altclass; | |
603 | int partial_cost = 0; | |
cbd5b9a2 | 604 | /* We need a memory reference to feed to SECONDARY... macros. */ |
dc297297 | 605 | /* mem may be unused even if the SECONDARY_ macros are defined. */ |
272df862 KG |
606 | rtx mem ATTRIBUTE_UNUSED = top_of_stack[(int) mode]; |
607 | ||
cbd5b9a2 KR |
608 | |
609 | if (in) | |
473fe49b | 610 | { |
321c0828 | 611 | #ifdef SECONDARY_INPUT_RELOAD_CLASS |
473fe49b | 612 | altclass = SECONDARY_INPUT_RELOAD_CLASS (class, mode, mem); |
321c0828 | 613 | #else |
473fe49b | 614 | altclass = NO_REGS; |
321c0828 | 615 | #endif |
473fe49b | 616 | } |
cbd5b9a2 | 617 | else |
473fe49b | 618 | { |
321c0828 | 619 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS |
473fe49b | 620 | altclass = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, mem); |
321c0828 | 621 | #else |
473fe49b | 622 | altclass = NO_REGS; |
321c0828 | 623 | #endif |
473fe49b KR |
624 | } |
625 | ||
cbd5b9a2 KR |
626 | if (altclass == NO_REGS) |
627 | return 0; | |
628 | ||
629 | if (in) | |
e56b4594 | 630 | partial_cost = REGISTER_MOVE_COST (mode, altclass, class); |
cbd5b9a2 | 631 | else |
e56b4594 | 632 | partial_cost = REGISTER_MOVE_COST (mode, class, altclass); |
cbd5b9a2 KR |
633 | |
634 | if (class == altclass) | |
635 | /* This isn't simply a copy-to-temporary situation. Can't guess | |
636 | what it is, so MEMORY_MOVE_COST really ought not to be calling | |
637 | here in that case. | |
638 | ||
639 | I'm tempted to put in an abort here, but returning this will | |
640 | probably only give poor estimates, which is what we would've | |
641 | had before this code anyways. */ | |
642 | return partial_cost; | |
643 | ||
644 | /* Check if the secondary reload register will also need a | |
645 | secondary reload. */ | |
646 | return memory_move_secondary_cost (mode, altclass, in) + partial_cost; | |
647 | } | |
648 | #endif | |
649 | ||
ca4aac00 | 650 | /* Return a machine mode that is legitimate for hard reg REGNO and large |
fee226d2 R |
651 | enough to save nregs. If we can't find one, return VOIDmode. |
652 | If CALL_SAVED is true, only consider modes that are call saved. */ | |
ca4aac00 DE |
653 | |
654 | enum machine_mode | |
0c20a65f | 655 | choose_hard_reg_mode (unsigned int regno ATTRIBUTE_UNUSED, |
fee226d2 | 656 | unsigned int nregs, bool call_saved) |
ca4aac00 | 657 | { |
dbbbbf3b | 658 | unsigned int /* enum machine_mode */ m; |
ca4aac00 DE |
659 | enum machine_mode found_mode = VOIDmode, mode; |
660 | ||
661 | /* We first look for the largest integer mode that can be validly | |
662 | held in REGNO. If none, we look for the largest floating-point mode. | |
663 | If we still didn't find a valid mode, try CCmode. */ | |
664 | ||
665 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); | |
666 | mode != VOIDmode; | |
667 | mode = GET_MODE_WIDER_MODE (mode)) | |
66fd46b6 | 668 | if ((unsigned) hard_regno_nregs[regno][mode] == nregs |
fee226d2 R |
669 | && HARD_REGNO_MODE_OK (regno, mode) |
670 | && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))) | |
ca4aac00 DE |
671 | found_mode = mode; |
672 | ||
673 | if (found_mode != VOIDmode) | |
674 | return found_mode; | |
675 | ||
676 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); | |
677 | mode != VOIDmode; | |
678 | mode = GET_MODE_WIDER_MODE (mode)) | |
66fd46b6 | 679 | if ((unsigned) hard_regno_nregs[regno][mode] == nregs |
fee226d2 R |
680 | && HARD_REGNO_MODE_OK (regno, mode) |
681 | && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))) | |
ca4aac00 DE |
682 | found_mode = mode; |
683 | ||
684 | if (found_mode != VOIDmode) | |
685 | return found_mode; | |
686 | ||
78b583fe AH |
687 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_FLOAT); |
688 | mode != VOIDmode; | |
689 | mode = GET_MODE_WIDER_MODE (mode)) | |
66fd46b6 | 690 | if ((unsigned) hard_regno_nregs[regno][mode] == nregs |
fee226d2 R |
691 | && HARD_REGNO_MODE_OK (regno, mode) |
692 | && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))) | |
78b583fe AH |
693 | found_mode = mode; |
694 | ||
695 | if (found_mode != VOIDmode) | |
696 | return found_mode; | |
697 | ||
698 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_INT); | |
699 | mode != VOIDmode; | |
700 | mode = GET_MODE_WIDER_MODE (mode)) | |
66fd46b6 | 701 | if ((unsigned) hard_regno_nregs[regno][mode] == nregs |
fee226d2 R |
702 | && HARD_REGNO_MODE_OK (regno, mode) |
703 | && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))) | |
78b583fe AH |
704 | found_mode = mode; |
705 | ||
706 | if (found_mode != VOIDmode) | |
707 | return found_mode; | |
708 | ||
0548a9df | 709 | /* Iterate over all of the CCmodes. */ |
dbbbbf3b JDA |
710 | for (m = (unsigned int) CCmode; m < (unsigned int) NUM_MACHINE_MODES; ++m) |
711 | { | |
712 | mode = (enum machine_mode) m; | |
66fd46b6 | 713 | if ((unsigned) hard_regno_nregs[regno][mode] == nregs |
fee226d2 R |
714 | && HARD_REGNO_MODE_OK (regno, mode) |
715 | && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))) | |
dbbbbf3b JDA |
716 | return mode; |
717 | } | |
ca4aac00 DE |
718 | |
719 | /* We can't find a mode valid for this register. */ | |
720 | return VOIDmode; | |
54dac99e RK |
721 | } |
722 | ||
723 | /* Specify the usage characteristics of the register named NAME. | |
724 | It should be a fixed register if FIXED and a | |
725 | call-used register if CALL_USED. */ | |
726 | ||
727 | void | |
0c20a65f | 728 | fix_register (const char *name, int fixed, int call_used) |
54dac99e RK |
729 | { |
730 | int i; | |
731 | ||
732 | /* Decode the name and update the primary form of | |
733 | the register info. */ | |
734 | ||
e5c90c23 TW |
735 | if ((i = decode_reg_name (name)) >= 0) |
736 | { | |
cb2fdc84 GRK |
737 | if ((i == STACK_POINTER_REGNUM |
738 | #ifdef HARD_FRAME_POINTER_REGNUM | |
739 | || i == HARD_FRAME_POINTER_REGNUM | |
740 | #else | |
741 | || i == FRAME_POINTER_REGNUM | |
742 | #endif | |
743 | ) | |
744 | && (fixed == 0 || call_used == 0)) | |
745 | { | |
6f7d635c | 746 | static const char * const what_option[2][2] = { |
7f7f8214 KG |
747 | { "call-saved", "call-used" }, |
748 | { "no-such-option", "fixed" }}; | |
a6a2274a KH |
749 | |
750 | error ("can't use '%s' as a %s register", name, | |
cb2fdc84 GRK |
751 | what_option[fixed][call_used]); |
752 | } | |
753 | else | |
754 | { | |
755 | fixed_regs[i] = fixed; | |
756 | call_used_regs[i] = call_used; | |
ec523c2f | 757 | #ifdef CALL_REALLY_USED_REGISTERS |
fc1296b7 AM |
758 | if (fixed == 0) |
759 | call_really_used_regs[i] = call_used; | |
d3259baa | 760 | #endif |
cb2fdc84 | 761 | } |
e5c90c23 TW |
762 | } |
763 | else | |
54dac99e RK |
764 | { |
765 | warning ("unknown register name: %s", name); | |
54dac99e RK |
766 | } |
767 | } | |
614f68e2 RK |
768 | |
769 | /* Mark register number I as global. */ | |
770 | ||
771 | void | |
0c20a65f | 772 | globalize_reg (int i) |
614f68e2 | 773 | { |
c07c7c9d | 774 | if (fixed_regs[i] == 0 && no_global_reg_vars) |
6c85df69 AH |
775 | error ("global register variable follows a function definition"); |
776 | ||
614f68e2 RK |
777 | if (global_regs[i]) |
778 | { | |
779 | warning ("register used for two global register variables"); | |
780 | return; | |
781 | } | |
782 | ||
783 | if (call_used_regs[i] && ! fixed_regs[i]) | |
784 | warning ("call-clobbered register used for global register variable"); | |
785 | ||
786 | global_regs[i] = 1; | |
787 | ||
788 | /* If already fixed, nothing else to do. */ | |
789 | if (fixed_regs[i]) | |
790 | return; | |
791 | ||
792 | fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1; | |
793 | n_non_fixed_regs--; | |
794 | ||
795 | SET_HARD_REG_BIT (fixed_reg_set, i); | |
796 | SET_HARD_REG_BIT (call_used_reg_set, i); | |
797 | SET_HARD_REG_BIT (call_fixed_reg_set, i); | |
caecc099 | 798 | SET_HARD_REG_BIT (regs_invalidated_by_call, i); |
614f68e2 | 799 | } |
54dac99e RK |
800 | \f |
801 | /* Now the data and code for the `regclass' pass, which happens | |
802 | just before local-alloc. */ | |
803 | ||
e4600702 RK |
804 | /* The `costs' struct records the cost of using a hard register of each class |
805 | and of using memory for each pseudo. We use this data to set up | |
806 | register class preferences. */ | |
54dac99e | 807 | |
e4600702 | 808 | struct costs |
54dac99e | 809 | { |
e4600702 RK |
810 | int cost[N_REG_CLASSES]; |
811 | int mem_cost; | |
54dac99e RK |
812 | }; |
813 | ||
d55d8fc7 | 814 | /* Structure used to record preferences of given pseudo. */ |
9ffc5a70 JH |
815 | struct reg_pref |
816 | { | |
817 | /* (enum reg_class) prefclass is the preferred class. */ | |
818 | char prefclass; | |
819 | ||
820 | /* altclass is a register class that we should use for allocating | |
821 | pseudo if no register in the preferred class is available. | |
822 | If no register in this class is available, memory is preferred. | |
823 | ||
824 | It might appear to be more general to have a bitmask of classes here, | |
825 | but since it is recommended that there be a class corresponding to the | |
826 | union of most major pair of classes, that generality is not required. */ | |
827 | char altclass; | |
828 | }; | |
829 | ||
e4600702 RK |
830 | /* Record the cost of each class for each pseudo. */ |
831 | ||
832 | static struct costs *costs; | |
833 | ||
61719ba7 BS |
834 | /* Initialized once, and used to initialize cost values for each insn. */ |
835 | ||
836 | static struct costs init_cost; | |
837 | ||
d55d8fc7 | 838 | /* Record preferences of each pseudo. |
54dac99e RK |
839 | This is available after `regclass' is run. */ |
840 | ||
9ffc5a70 | 841 | static struct reg_pref *reg_pref; |
54d23420 | 842 | |
dc297297 | 843 | /* Allocated buffers for reg_pref. */ |
54dac99e | 844 | |
9ffc5a70 | 845 | static struct reg_pref *reg_pref_buffer; |
6feacd09 | 846 | |
9401afe3 | 847 | /* Frequency of executions of current insn. */ |
54d23420 | 848 | |
9401afe3 | 849 | static int frequency; |
54d23420 | 850 | |
0c20a65f AJ |
851 | static rtx scan_one_insn (rtx, int); |
852 | static void record_operand_costs (rtx, struct costs *, struct reg_pref *); | |
853 | static void dump_regclass (FILE *); | |
854 | static void record_reg_classes (int, int, rtx *, enum machine_mode *, | |
855 | const char **, rtx, struct costs *, | |
856 | struct reg_pref *); | |
857 | static int copy_cost (rtx, enum machine_mode, enum reg_class, int); | |
858 | static void record_address_regs (rtx, enum reg_class, int); | |
1d300e19 | 859 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
0c20a65f | 860 | static int auto_inc_dec_reg_p (rtx, enum machine_mode); |
1d300e19 | 861 | #endif |
0c20a65f | 862 | static void reg_scan_mark_refs (rtx, rtx, int, unsigned int); |
54dac99e RK |
863 | |
864 | /* Return the reg_class in which pseudo reg number REGNO is best allocated. | |
865 | This function is sometimes called before the info has been computed. | |
866 | When that happens, just return GENERAL_REGS, which is innocuous. */ | |
867 | ||
868 | enum reg_class | |
0c20a65f | 869 | reg_preferred_class (int regno) |
54dac99e | 870 | { |
9ffc5a70 | 871 | if (reg_pref == 0) |
54dac99e | 872 | return GENERAL_REGS; |
9ffc5a70 | 873 | return (enum reg_class) reg_pref[regno].prefclass; |
54dac99e RK |
874 | } |
875 | ||
e4600702 | 876 | enum reg_class |
0c20a65f | 877 | reg_alternate_class (int regno) |
54dac99e | 878 | { |
9ffc5a70 | 879 | if (reg_pref == 0) |
e4600702 RK |
880 | return ALL_REGS; |
881 | ||
9ffc5a70 | 882 | return (enum reg_class) reg_pref[regno].altclass; |
54dac99e RK |
883 | } |
884 | ||
61719ba7 | 885 | /* Initialize some global data for this pass. */ |
54dac99e RK |
886 | |
887 | void | |
0c20a65f | 888 | regclass_init (void) |
54dac99e | 889 | { |
61719ba7 BS |
890 | int i; |
891 | ||
892 | init_cost.mem_cost = 10000; | |
893 | for (i = 0; i < N_REG_CLASSES; i++) | |
894 | init_cost.cost[i] = 10000; | |
895 | ||
896 | /* This prevents dump_flow_info from losing if called | |
897 | before regclass is run. */ | |
9ffc5a70 | 898 | reg_pref = NULL; |
6c85df69 | 899 | |
dc297297 | 900 | /* No more global register variables may be declared. */ |
6c85df69 | 901 | no_global_reg_vars = 1; |
54dac99e | 902 | } |
246fd41f JH |
903 | \f |
904 | /* Dump register costs. */ | |
915b80ed | 905 | static void |
0c20a65f | 906 | dump_regclass (FILE *dump) |
246fd41f JH |
907 | { |
908 | static const char *const reg_class_names[] = REG_CLASS_NAMES; | |
909 | int i; | |
910 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
911 | { | |
dbbbbf3b | 912 | int /* enum reg_class */ class; |
246fd41f JH |
913 | if (REG_N_REFS (i)) |
914 | { | |
f741a71c | 915 | fprintf (dump, " Register %i costs:", i); |
dbbbbf3b JDA |
916 | for (class = 0; class < (int) N_REG_CLASSES; class++) |
917 | if (contains_reg_of_mode [(enum reg_class) class][PSEUDO_REGNO_MODE (i)] | |
6df26b8f | 918 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
dbbbbf3b JDA |
919 | && (!in_inc_dec[i] |
920 | || !forbidden_inc_dec_class[(enum reg_class) class]) | |
6df26b8f | 921 | #endif |
cff9f8d5 AH |
922 | #ifdef CANNOT_CHANGE_MODE_CLASS |
923 | && ! invalid_mode_change_p (i, (enum reg_class) class, | |
924 | PSEUDO_REGNO_MODE (i)) | |
6df26b8f JH |
925 | #endif |
926 | ) | |
dbbbbf3b JDA |
927 | fprintf (dump, " %s:%i", reg_class_names[class], |
928 | costs[i].cost[(enum reg_class) class]); | |
f741a71c | 929 | fprintf (dump, " MEM:%i\n", costs[i].mem_cost); |
246fd41f JH |
930 | } |
931 | } | |
932 | } | |
f741a71c JH |
933 | \f |
934 | ||
935 | /* Calculate the costs of insn operands. */ | |
936 | ||
937 | static void | |
0c20a65f AJ |
938 | record_operand_costs (rtx insn, struct costs *op_costs, |
939 | struct reg_pref *reg_pref) | |
f741a71c JH |
940 | { |
941 | const char *constraints[MAX_RECOG_OPERANDS]; | |
942 | enum machine_mode modes[MAX_RECOG_OPERANDS]; | |
f741a71c JH |
943 | int i; |
944 | ||
945 | for (i = 0; i < recog_data.n_operands; i++) | |
946 | { | |
947 | constraints[i] = recog_data.constraints[i]; | |
948 | modes[i] = recog_data.operand_mode[i]; | |
949 | } | |
f741a71c JH |
950 | |
951 | /* If we get here, we are set up to record the costs of all the | |
952 | operands for this insn. Start by initializing the costs. | |
953 | Then handle any address registers. Finally record the desired | |
954 | classes for any pseudos, doing it twice if some pair of | |
955 | operands are commutative. */ | |
a6a2274a | 956 | |
f741a71c JH |
957 | for (i = 0; i < recog_data.n_operands; i++) |
958 | { | |
959 | op_costs[i] = init_cost; | |
960 | ||
961 | if (GET_CODE (recog_data.operand[i]) == SUBREG) | |
cff9f8d5 | 962 | recog_data.operand[i] = SUBREG_REG (recog_data.operand[i]); |
f741a71c JH |
963 | |
964 | if (GET_CODE (recog_data.operand[i]) == MEM) | |
965 | record_address_regs (XEXP (recog_data.operand[i], 0), | |
3dcc68a4 | 966 | MODE_BASE_REG_CLASS (modes[i]), frequency * 2); |
ccfc6cc8 | 967 | else if (constraints[i][0] == 'p' |
97488870 | 968 | || EXTRA_ADDRESS_CONSTRAINT (constraints[i][0], constraints[i])) |
f741a71c | 969 | record_address_regs (recog_data.operand[i], |
3dcc68a4 | 970 | MODE_BASE_REG_CLASS (modes[i]), frequency * 2); |
f741a71c JH |
971 | } |
972 | ||
973 | /* Check for commutative in a separate loop so everything will | |
974 | have been initialized. We must do this even if one operand | |
975 | is a constant--see addsi3 in m68k.md. */ | |
976 | ||
977 | for (i = 0; i < (int) recog_data.n_operands - 1; i++) | |
978 | if (constraints[i][0] == '%') | |
979 | { | |
980 | const char *xconstraints[MAX_RECOG_OPERANDS]; | |
981 | int j; | |
246fd41f | 982 | |
f741a71c JH |
983 | /* Handle commutative operands by swapping the constraints. |
984 | We assume the modes are the same. */ | |
985 | ||
986 | for (j = 0; j < recog_data.n_operands; j++) | |
987 | xconstraints[j] = constraints[j]; | |
988 | ||
989 | xconstraints[i] = constraints[i+1]; | |
990 | xconstraints[i+1] = constraints[i]; | |
991 | record_reg_classes (recog_data.n_alternatives, recog_data.n_operands, | |
a6a2274a | 992 | recog_data.operand, modes, |
f741a71c JH |
993 | xconstraints, insn, op_costs, reg_pref); |
994 | } | |
995 | ||
996 | record_reg_classes (recog_data.n_alternatives, recog_data.n_operands, | |
a6a2274a | 997 | recog_data.operand, modes, |
f741a71c JH |
998 | constraints, insn, op_costs, reg_pref); |
999 | } | |
54dac99e | 1000 | \f |
61719ba7 BS |
1001 | /* Subroutine of regclass, processes one insn INSN. Scan it and record each |
1002 | time it would save code to put a certain register in a certain class. | |
1003 | PASS, when nonzero, inhibits some optimizations which need only be done | |
1004 | once. | |
1005 | Return the last insn processed, so that the scan can be continued from | |
1006 | there. */ | |
1007 | ||
1008 | static rtx | |
0c20a65f | 1009 | scan_one_insn (rtx insn, int pass) |
61719ba7 | 1010 | { |
61719ba7 | 1011 | enum rtx_code pat_code; |
0eadeb15 | 1012 | rtx set, note; |
61719ba7 | 1013 | int i, j; |
f741a71c | 1014 | struct costs op_costs[MAX_RECOG_OPERANDS]; |
61719ba7 | 1015 | |
ec8e098d | 1016 | if (!INSN_P (insn)) |
61719ba7 BS |
1017 | return insn; |
1018 | ||
1019 | pat_code = GET_CODE (PATTERN (insn)); | |
1020 | if (pat_code == USE | |
1021 | || pat_code == CLOBBER | |
1022 | || pat_code == ASM_INPUT | |
1023 | || pat_code == ADDR_VEC | |
1024 | || pat_code == ADDR_DIFF_VEC) | |
1025 | return insn; | |
1026 | ||
0eadeb15 BS |
1027 | set = single_set (insn); |
1028 | extract_insn (insn); | |
1029 | ||
0eadeb15 BS |
1030 | /* If this insn loads a parameter from its stack slot, then |
1031 | it represents a savings, rather than a cost, if the | |
1032 | parameter is stored in memory. Record this fact. */ | |
61719ba7 | 1033 | |
0eadeb15 BS |
1034 | if (set != 0 && GET_CODE (SET_DEST (set)) == REG |
1035 | && GET_CODE (SET_SRC (set)) == MEM | |
1036 | && (note = find_reg_note (insn, REG_EQUIV, | |
1037 | NULL_RTX)) != 0 | |
1038 | && GET_CODE (XEXP (note, 0)) == MEM) | |
1039 | { | |
1040 | costs[REGNO (SET_DEST (set))].mem_cost | |
1041 | -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)), | |
1042 | GENERAL_REGS, 1) | |
9401afe3 | 1043 | * frequency); |
0eadeb15 | 1044 | record_address_regs (XEXP (SET_SRC (set), 0), |
3dcc68a4 | 1045 | MODE_BASE_REG_CLASS (VOIDmode), frequency * 2); |
0eadeb15 BS |
1046 | return insn; |
1047 | } | |
61719ba7 | 1048 | |
0eadeb15 BS |
1049 | /* Improve handling of two-address insns such as |
1050 | (set X (ashift CONST Y)) where CONST must be made to | |
1051 | match X. Change it into two insns: (set X CONST) | |
1052 | (set X (ashift X Y)). If we left this for reloading, it | |
1053 | would probably get three insns because X and Y might go | |
1054 | in the same place. This prevents X and Y from receiving | |
1055 | the same hard reg. | |
1056 | ||
1057 | We can only do this if the modes of operands 0 and 1 | |
1058 | (which might not be the same) are tieable and we only need | |
1059 | do this during our first pass. */ | |
1060 | ||
1061 | if (pass == 0 && optimize | |
1ccbefce RH |
1062 | && recog_data.n_operands >= 3 |
1063 | && recog_data.constraints[1][0] == '0' | |
1064 | && recog_data.constraints[1][1] == 0 | |
1065 | && CONSTANT_P (recog_data.operand[1]) | |
1066 | && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[1]) | |
1067 | && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[2]) | |
1068 | && GET_CODE (recog_data.operand[0]) == REG | |
1069 | && MODES_TIEABLE_P (GET_MODE (recog_data.operand[0]), | |
1070 | recog_data.operand_mode[1])) | |
0eadeb15 BS |
1071 | { |
1072 | rtx previnsn = prev_real_insn (insn); | |
1073 | rtx dest | |
1ccbefce RH |
1074 | = gen_lowpart (recog_data.operand_mode[1], |
1075 | recog_data.operand[0]); | |
0eadeb15 | 1076 | rtx newinsn |
1ccbefce | 1077 | = emit_insn_before (gen_move_insn (dest, recog_data.operand[1]), insn); |
61719ba7 | 1078 | |
0eadeb15 BS |
1079 | /* If this insn was the start of a basic block, |
1080 | include the new insn in that block. | |
1081 | We need not check for code_label here; | |
1082 | while a basic block can start with a code_label, | |
1083 | INSN could not be at the beginning of that block. */ | |
1084 | if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN) | |
61719ba7 | 1085 | { |
e0082a72 ZD |
1086 | basic_block b; |
1087 | FOR_EACH_BB (b) | |
a813c111 SB |
1088 | if (insn == BB_HEAD (b)) |
1089 | BB_HEAD (b) = newinsn; | |
61719ba7 BS |
1090 | } |
1091 | ||
0eadeb15 | 1092 | /* This makes one more setting of new insns's dest. */ |
1ccbefce | 1093 | REG_N_SETS (REGNO (recog_data.operand[0]))++; |
d3c7d45e | 1094 | REG_N_REFS (REGNO (recog_data.operand[0]))++; |
9401afe3 | 1095 | REG_FREQ (REGNO (recog_data.operand[0])) += frequency; |
61719ba7 | 1096 | |
1ccbefce | 1097 | *recog_data.operand_loc[1] = recog_data.operand[0]; |
d3c7d45e | 1098 | REG_N_REFS (REGNO (recog_data.operand[0]))++; |
9401afe3 | 1099 | REG_FREQ (REGNO (recog_data.operand[0])) += frequency; |
1ccbefce RH |
1100 | for (i = recog_data.n_dups - 1; i >= 0; i--) |
1101 | if (recog_data.dup_num[i] == 1) | |
d3c7d45e AO |
1102 | { |
1103 | *recog_data.dup_loc[i] = recog_data.operand[0]; | |
1104 | REG_N_REFS (REGNO (recog_data.operand[0]))++; | |
9401afe3 | 1105 | REG_FREQ (REGNO (recog_data.operand[0])) += frequency; |
d3c7d45e | 1106 | } |
61719ba7 | 1107 | |
0eadeb15 | 1108 | return PREV_INSN (newinsn); |
61719ba7 BS |
1109 | } |
1110 | ||
4963c995 | 1111 | record_operand_costs (insn, op_costs, reg_pref); |
61719ba7 BS |
1112 | |
1113 | /* Now add the cost for each operand to the total costs for | |
1114 | its register. */ | |
1115 | ||
1ccbefce RH |
1116 | for (i = 0; i < recog_data.n_operands; i++) |
1117 | if (GET_CODE (recog_data.operand[i]) == REG | |
1118 | && REGNO (recog_data.operand[i]) >= FIRST_PSEUDO_REGISTER) | |
61719ba7 | 1119 | { |
1ccbefce | 1120 | int regno = REGNO (recog_data.operand[i]); |
61719ba7 BS |
1121 | struct costs *p = &costs[regno], *q = &op_costs[i]; |
1122 | ||
9401afe3 | 1123 | p->mem_cost += q->mem_cost * frequency; |
61719ba7 | 1124 | for (j = 0; j < N_REG_CLASSES; j++) |
9401afe3 | 1125 | p->cost[j] += q->cost[j] * frequency; |
61719ba7 BS |
1126 | } |
1127 | ||
1128 | return insn; | |
1129 | } | |
1130 | ||
1f80c9ef MS |
1131 | /* Initialize information about which register classes can be used for |
1132 | pseudos that are auto-incremented or auto-decremented. */ | |
54dac99e | 1133 | |
1f80c9ef | 1134 | static void |
0c20a65f | 1135 | init_reg_autoinc (void) |
54dac99e | 1136 | { |
533d0835 | 1137 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
1f80c9ef | 1138 | int i; |
533d0835 RK |
1139 | |
1140 | for (i = 0; i < N_REG_CLASSES; i++) | |
1141 | { | |
1f80c9ef | 1142 | rtx r = gen_rtx_raw_REG (VOIDmode, 0); |
533d0835 | 1143 | enum machine_mode m; |
b3694847 | 1144 | int j; |
533d0835 RK |
1145 | |
1146 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
1147 | if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) | |
1148 | { | |
1149 | REGNO (r) = j; | |
1150 | ||
1151 | for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE; | |
808043ed | 1152 | m = (enum machine_mode) ((int) m + 1)) |
533d0835 RK |
1153 | if (HARD_REGNO_MODE_OK (j, m)) |
1154 | { | |
1155 | PUT_MODE (r, m); | |
08d95f91 RK |
1156 | |
1157 | /* If a register is not directly suitable for an | |
1158 | auto-increment or decrement addressing mode and | |
1159 | requires secondary reloads, disallow its class from | |
1160 | being used in such addresses. */ | |
1161 | ||
1162 | if ((0 | |
041d7180 | 1163 | #ifdef SECONDARY_RELOAD_CLASS |
3dcc68a4 | 1164 | || (SECONDARY_RELOAD_CLASS (MODE_BASE_REG_CLASS (VOIDmode), m, r) |
041d7180 JL |
1165 | != NO_REGS) |
1166 | #else | |
533d0835 | 1167 | #ifdef SECONDARY_INPUT_RELOAD_CLASS |
3dcc68a4 | 1168 | || (SECONDARY_INPUT_RELOAD_CLASS (MODE_BASE_REG_CLASS (VOIDmode), m, r) |
08d95f91 | 1169 | != NO_REGS) |
533d0835 RK |
1170 | #endif |
1171 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS | |
3dcc68a4 | 1172 | || (SECONDARY_OUTPUT_RELOAD_CLASS (MODE_BASE_REG_CLASS (VOIDmode), m, r) |
08d95f91 | 1173 | != NO_REGS) |
041d7180 | 1174 | #endif |
533d0835 | 1175 | #endif |
08d95f91 RK |
1176 | ) |
1177 | && ! auto_inc_dec_reg_p (r, m)) | |
533d0835 RK |
1178 | forbidden_inc_dec_class[i] = 1; |
1179 | } | |
1180 | } | |
1181 | } | |
1f80c9ef MS |
1182 | #endif /* FORBIDDEN_INC_DEC_CLASSES */ |
1183 | } | |
1184 | ||
1185 | /* This is a pass of the compiler that scans all instructions | |
1186 | and calculates the preferred class for each pseudo-register. | |
1187 | This information can be accessed later by calling `reg_preferred_class'. | |
1188 | This pass comes just before local register allocation. */ | |
1189 | ||
1190 | void | |
0c20a65f | 1191 | regclass (rtx f, int nregs, FILE *dump) |
1f80c9ef MS |
1192 | { |
1193 | rtx insn; | |
1194 | int i; | |
1195 | int pass; | |
1196 | ||
1197 | init_recog (); | |
1198 | ||
703ad42b | 1199 | costs = xmalloc (nregs * sizeof (struct costs)); |
1f80c9ef MS |
1200 | |
1201 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
1202 | ||
703ad42b | 1203 | in_inc_dec = xmalloc (nregs); |
1f80c9ef | 1204 | |
533d0835 RK |
1205 | #endif /* FORBIDDEN_INC_DEC_CLASSES */ |
1206 | ||
e4600702 RK |
1207 | /* Normally we scan the insns once and determine the best class to use for |
1208 | each register. However, if -fexpensive_optimizations are on, we do so | |
1209 | twice, the second time using the tentative best classes to guide the | |
1210 | selection. */ | |
54dac99e | 1211 | |
e4600702 RK |
1212 | for (pass = 0; pass <= flag_expensive_optimizations; pass++) |
1213 | { | |
e0082a72 | 1214 | basic_block bb; |
f741a71c JH |
1215 | |
1216 | if (dump) | |
a6a2274a | 1217 | fprintf (dump, "\n\nPass %i\n\n",pass); |
e4600702 | 1218 | /* Zero out our accumulation of the cost of each class for each reg. */ |
54dac99e | 1219 | |
703ad42b | 1220 | memset (costs, 0, nregs * sizeof (struct costs)); |
54dac99e | 1221 | |
533d0835 | 1222 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
961192e1 | 1223 | memset (in_inc_dec, 0, nregs); |
533d0835 RK |
1224 | #endif |
1225 | ||
e4600702 RK |
1226 | /* Scan the instructions and record each time it would |
1227 | save code to put a certain register in a certain class. */ | |
1228 | ||
1f01879e | 1229 | if (!optimize) |
54dac99e | 1230 | { |
a08b2604 | 1231 | frequency = REG_FREQ_MAX; |
1f01879e JH |
1232 | for (insn = f; insn; insn = NEXT_INSN (insn)) |
1233 | insn = scan_one_insn (insn, pass); | |
54dac99e | 1234 | } |
1f01879e | 1235 | else |
e0082a72 | 1236 | FOR_EACH_BB (bb) |
1f01879e | 1237 | { |
1f01879e | 1238 | /* Show that an insn inside a loop is likely to be executed three |
9b15c17f RH |
1239 | times more than insns outside a loop. This is much more |
1240 | aggressive than the assumptions made elsewhere and is being | |
1241 | tried as an experiment. */ | |
a08b2604 | 1242 | frequency = REG_FREQ_FROM_BB (bb); |
a813c111 | 1243 | for (insn = BB_HEAD (bb); ; insn = NEXT_INSN (insn)) |
1f01879e JH |
1244 | { |
1245 | insn = scan_one_insn (insn, pass); | |
a813c111 | 1246 | if (insn == BB_END (bb)) |
1f01879e JH |
1247 | break; |
1248 | } | |
1249 | } | |
a6a2274a | 1250 | |
e4600702 RK |
1251 | /* Now for each register look at how desirable each class is |
1252 | and find which class is preferred. Store that in | |
9ffc5a70 | 1253 | `prefclass'. Record in `altclass' the largest register |
e4600702 | 1254 | class any of whose registers is better than memory. */ |
a6a2274a | 1255 | |
e4600702 | 1256 | if (pass == 0) |
9ffc5a70 | 1257 | reg_pref = reg_pref_buffer; |
54dac99e | 1258 | |
f741a71c | 1259 | if (dump) |
a6a2274a | 1260 | { |
f741a71c | 1261 | dump_regclass (dump); |
4963c995 | 1262 | fprintf (dump,"\n"); |
f741a71c | 1263 | } |
e4600702 | 1264 | for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++) |
54dac99e | 1265 | { |
b3694847 | 1266 | int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1; |
e4600702 RK |
1267 | enum reg_class best = ALL_REGS, alt = NO_REGS; |
1268 | /* This is an enum reg_class, but we call it an int | |
1269 | to save lots of casts. */ | |
b3694847 SS |
1270 | int class; |
1271 | struct costs *p = &costs[i]; | |
e4600702 | 1272 | |
64615302 JH |
1273 | /* In non-optimizing compilation REG_N_REFS is not initialized |
1274 | yet. */ | |
ed8d2920 | 1275 | if (optimize && !REG_N_REFS (i) && !REG_N_SETS (i)) |
f741a71c JH |
1276 | continue; |
1277 | ||
e4600702 | 1278 | for (class = (int) ALL_REGS - 1; class > 0; class--) |
54dac99e | 1279 | { |
533d0835 | 1280 | /* Ignore classes that are too small for this operand or |
4fe9b91c | 1281 | invalid for an operand that was auto-incremented. */ |
6df26b8f | 1282 | if (!contains_reg_of_mode [class][PSEUDO_REGNO_MODE (i)] |
533d0835 RK |
1283 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
1284 | || (in_inc_dec[i] && forbidden_inc_dec_class[class]) | |
e79f71f7 | 1285 | #endif |
cff9f8d5 AH |
1286 | #ifdef CANNOT_CHANGE_MODE_CLASS |
1287 | || invalid_mode_change_p (i, (enum reg_class) class, | |
1288 | PSEUDO_REGNO_MODE (i)) | |
533d0835 RK |
1289 | #endif |
1290 | ) | |
e4600702 RK |
1291 | ; |
1292 | else if (p->cost[class] < best_cost) | |
1293 | { | |
1294 | best_cost = p->cost[class]; | |
1295 | best = (enum reg_class) class; | |
1296 | } | |
1297 | else if (p->cost[class] == best_cost) | |
8e2e89f7 | 1298 | best = reg_class_subunion[(int) best][class]; |
54dac99e | 1299 | } |
54dac99e | 1300 | |
e4600702 RK |
1301 | /* Record the alternate register class; i.e., a class for which |
1302 | every register in it is better than using memory. If adding a | |
1303 | class would make a smaller class (i.e., no union of just those | |
1304 | classes exists), skip that class. The major unions of classes | |
1305 | should be provided as a register class. Don't do this if we | |
1306 | will be doing it again later. */ | |
1307 | ||
f741a71c | 1308 | if ((pass == 1 || dump) || ! flag_expensive_optimizations) |
e4600702 RK |
1309 | for (class = 0; class < N_REG_CLASSES; class++) |
1310 | if (p->cost[class] < p->mem_cost | |
77edb222 | 1311 | && (reg_class_size[(int) reg_class_subunion[(int) alt][class]] |
533d0835 RK |
1312 | > reg_class_size[(int) alt]) |
1313 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
1314 | && ! (in_inc_dec[i] && forbidden_inc_dec_class[class]) | |
e79f71f7 | 1315 | #endif |
cff9f8d5 AH |
1316 | #ifdef CANNOT_CHANGE_MODE_CLASS |
1317 | && ! invalid_mode_change_p (i, (enum reg_class) class, | |
1318 | PSEUDO_REGNO_MODE (i)) | |
533d0835 RK |
1319 | #endif |
1320 | ) | |
e4600702 | 1321 | alt = reg_class_subunion[(int) alt][class]; |
a6a2274a | 1322 | |
e4600702 RK |
1323 | /* If we don't add any classes, nothing to try. */ |
1324 | if (alt == best) | |
995d54dd | 1325 | alt = NO_REGS; |
e4600702 | 1326 | |
a6a2274a | 1327 | if (dump |
f741a71c JH |
1328 | && (reg_pref[i].prefclass != (int) best |
1329 | || reg_pref[i].altclass != (int) alt)) | |
1330 | { | |
1331 | static const char *const reg_class_names[] = REG_CLASS_NAMES; | |
4963c995 | 1332 | fprintf (dump, " Register %i", i); |
f741a71c JH |
1333 | if (alt == ALL_REGS || best == ALL_REGS) |
1334 | fprintf (dump, " pref %s\n", reg_class_names[(int) best]); | |
1335 | else if (alt == NO_REGS) | |
1336 | fprintf (dump, " pref %s or none\n", reg_class_names[(int) best]); | |
1337 | else | |
1338 | fprintf (dump, " pref %s, else %s\n", | |
1339 | reg_class_names[(int) best], | |
1340 | reg_class_names[(int) alt]); | |
1341 | } | |
1342 | ||
e4600702 | 1343 | /* We cast to (int) because (char) hits bugs in some compilers. */ |
9ffc5a70 JH |
1344 | reg_pref[i].prefclass = (int) best; |
1345 | reg_pref[i].altclass = (int) alt; | |
e4600702 | 1346 | } |
54dac99e | 1347 | } |
56a65848 | 1348 | |
4da896b2 MM |
1349 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
1350 | free (in_inc_dec); | |
1351 | #endif | |
56a65848 | 1352 | free (costs); |
54dac99e RK |
1353 | } |
1354 | \f | |
e4600702 RK |
1355 | /* Record the cost of using memory or registers of various classes for |
1356 | the operands in INSN. | |
54dac99e | 1357 | |
e4600702 | 1358 | N_ALTS is the number of alternatives. |
54dac99e | 1359 | |
e4600702 RK |
1360 | N_OPS is the number of operands. |
1361 | ||
1362 | OPS is an array of the operands. | |
1363 | ||
1364 | MODES are the modes of the operands, in case any are VOIDmode. | |
1365 | ||
1366 | CONSTRAINTS are the constraints to use for the operands. This array | |
1367 | is modified by this procedure. | |
1368 | ||
1369 | This procedure works alternative by alternative. For each alternative | |
1370 | we assume that we will be able to allocate all pseudos to their ideal | |
1371 | register class and calculate the cost of using that alternative. Then | |
a6a2274a | 1372 | we compute for each operand that is a pseudo-register, the cost of |
e4600702 RK |
1373 | having the pseudo allocated to each register class and using it in that |
1374 | alternative. To this cost is added the cost of the alternative. | |
1375 | ||
1376 | The cost of each class for this insn is its lowest cost among all the | |
1377 | alternatives. */ | |
1378 | ||
1379 | static void | |
0c20a65f AJ |
1380 | record_reg_classes (int n_alts, int n_ops, rtx *ops, |
1381 | enum machine_mode *modes, const char **constraints, | |
1382 | rtx insn, struct costs *op_costs, | |
1383 | struct reg_pref *reg_pref) | |
54dac99e | 1384 | { |
e4600702 | 1385 | int alt; |
e4600702 | 1386 | int i, j; |
ec2d92af | 1387 | rtx set; |
e4600702 | 1388 | |
e4600702 RK |
1389 | /* Process each alternative, each time minimizing an operand's cost with |
1390 | the cost for each operand in that alternative. */ | |
54dac99e | 1391 | |
e4600702 | 1392 | for (alt = 0; alt < n_alts; alt++) |
54dac99e | 1393 | { |
e4600702 RK |
1394 | struct costs this_op_costs[MAX_RECOG_OPERANDS]; |
1395 | int alt_fail = 0; | |
1396 | int alt_cost = 0; | |
1397 | enum reg_class classes[MAX_RECOG_OPERANDS]; | |
da2c0219 | 1398 | int allows_mem[MAX_RECOG_OPERANDS]; |
e4600702 | 1399 | int class; |
54dac99e | 1400 | |
e4600702 RK |
1401 | for (i = 0; i < n_ops; i++) |
1402 | { | |
9b3142b3 | 1403 | const char *p = constraints[i]; |
e4600702 RK |
1404 | rtx op = ops[i]; |
1405 | enum machine_mode mode = modes[i]; | |
94e6f783 | 1406 | int allows_addr = 0; |
e4600702 | 1407 | int win = 0; |
e51712db | 1408 | unsigned char c; |
54dac99e | 1409 | |
7405d9a1 DE |
1410 | /* Initially show we know nothing about the register class. */ |
1411 | classes[i] = NO_REGS; | |
da2c0219 | 1412 | allows_mem[i] = 0; |
7405d9a1 | 1413 | |
a6a2274a | 1414 | /* If this operand has no constraints at all, we can conclude |
e4600702 | 1415 | nothing about it since anything is valid. */ |
54dac99e | 1416 | |
e4600702 RK |
1417 | if (*p == 0) |
1418 | { | |
1419 | if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
703ad42b | 1420 | memset (&this_op_costs[i], 0, sizeof this_op_costs[i]); |
54dac99e | 1421 | |
e4600702 RK |
1422 | continue; |
1423 | } | |
54dac99e | 1424 | |
7405d9a1 DE |
1425 | /* If this alternative is only relevant when this operand |
1426 | matches a previous operand, we do different things depending | |
1427 | on whether this operand is a pseudo-reg or not. We must process | |
1428 | any modifiers for the operand before we can make this test. */ | |
1429 | ||
8c368ee2 | 1430 | while (*p == '%' || *p == '=' || *p == '+' || *p == '&') |
0eadeb15 | 1431 | p++; |
8c368ee2 | 1432 | |
e4600702 RK |
1433 | if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0)) |
1434 | { | |
da2c0219 RK |
1435 | /* Copy class and whether memory is allowed from the matching |
1436 | alternative. Then perform any needed cost computations | |
1437 | and/or adjustments. */ | |
e4600702 RK |
1438 | j = p[0] - '0'; |
1439 | classes[i] = classes[j]; | |
da2c0219 | 1440 | allows_mem[i] = allows_mem[j]; |
e4600702 RK |
1441 | |
1442 | if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER) | |
1443 | { | |
1444 | /* If this matches the other operand, we have no added | |
dc903608 | 1445 | cost and we win. */ |
e4600702 | 1446 | if (rtx_equal_p (ops[j], op)) |
dc903608 | 1447 | win = 1; |
e4600702 | 1448 | |
77e67eac RK |
1449 | /* If we can put the other operand into a register, add to |
1450 | the cost of this alternative the cost to copy this | |
1451 | operand to the register used for the other operand. */ | |
e4600702 | 1452 | |
dc903608 | 1453 | else if (classes[j] != NO_REGS) |
77e67eac | 1454 | alt_cost += copy_cost (op, mode, classes[j], 1), win = 1; |
e4600702 | 1455 | } |
07d8ca2d RS |
1456 | else if (GET_CODE (ops[j]) != REG |
1457 | || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER) | |
1458 | { | |
1459 | /* This op is a pseudo but the one it matches is not. */ | |
a6a2274a | 1460 | |
07d8ca2d RS |
1461 | /* If we can't put the other operand into a register, this |
1462 | alternative can't be used. */ | |
1463 | ||
1464 | if (classes[j] == NO_REGS) | |
1465 | alt_fail = 1; | |
e4600702 | 1466 | |
07d8ca2d RS |
1467 | /* Otherwise, add to the cost of this alternative the cost |
1468 | to copy the other operand to the register used for this | |
1469 | operand. */ | |
1470 | ||
1471 | else | |
1472 | alt_cost += copy_cost (ops[j], mode, classes[j], 1); | |
1473 | } | |
e4600702 RK |
1474 | else |
1475 | { | |
da2c0219 RK |
1476 | /* The costs of this operand are not the same as the other |
1477 | operand since move costs are not symmetric. Moreover, | |
1478 | if we cannot tie them, this alternative needs to do a | |
1479 | copy, which is one instruction. */ | |
1480 | ||
1481 | struct costs *pp = &this_op_costs[i]; | |
1482 | ||
1483 | for (class = 0; class < N_REG_CLASSES; class++) | |
1484 | pp->cost[class] | |
d5e2075d | 1485 | = ((recog_data.operand_type[i] != OP_OUT |
e56b4594 | 1486 | ? may_move_in_cost[mode][class][(int) classes[i]] |
d5e2075d JH |
1487 | : 0) |
1488 | + (recog_data.operand_type[i] != OP_IN | |
e56b4594 | 1489 | ? may_move_out_cost[mode][(int) classes[i]][class] |
d5e2075d | 1490 | : 0)); |
a6a2274a | 1491 | |
da2c0219 RK |
1492 | /* If the alternative actually allows memory, make things |
1493 | a bit cheaper since we won't need an extra insn to | |
1494 | load it. */ | |
1495 | ||
1496 | pp->mem_cost | |
d5e2075d JH |
1497 | = ((recog_data.operand_type[i] != OP_IN |
1498 | ? MEMORY_MOVE_COST (mode, classes[i], 0) | |
1499 | : 0) | |
1500 | + (recog_data.operand_type[i] != OP_OUT | |
1501 | ? MEMORY_MOVE_COST (mode, classes[i], 1) | |
1502 | : 0) - allows_mem[i]); | |
da2c0219 RK |
1503 | |
1504 | /* If we have assigned a class to this register in our | |
1505 | first pass, add a cost to this alternative corresponding | |
1506 | to what we would add if this register were not in the | |
1507 | appropriate class. */ | |
1508 | ||
9ffc5a70 | 1509 | if (reg_pref) |
da2c0219 | 1510 | alt_cost |
e56b4594 AO |
1511 | += (may_move_in_cost[mode] |
1512 | [(unsigned char) reg_pref[REGNO (op)].prefclass] | |
da2c0219 | 1513 | [(int) classes[i]]); |
e4600702 | 1514 | |
37747c82 RK |
1515 | if (REGNO (ops[i]) != REGNO (ops[j]) |
1516 | && ! find_reg_note (insn, REG_DEAD, op)) | |
1517 | alt_cost += 2; | |
e4600702 | 1518 | |
347099d6 | 1519 | /* This is in place of ordinary cost computation |
1ddb342a RK |
1520 | for this operand, so skip to the end of the |
1521 | alternative (should be just one character). */ | |
1522 | while (*p && *p++ != ',') | |
1523 | ; | |
1524 | ||
1525 | constraints[i] = p; | |
347099d6 RS |
1526 | continue; |
1527 | } | |
e4600702 RK |
1528 | } |
1529 | ||
1530 | /* Scan all the constraint letters. See if the operand matches | |
1531 | any of the constraints. Collect the valid register classes | |
1532 | and see if this operand accepts memory. */ | |
1533 | ||
97488870 R |
1534 | while ((c = *p)) |
1535 | { | |
1536 | switch (c) | |
1537 | { | |
1538 | case ',': | |
1539 | break; | |
1540 | case '*': | |
1541 | /* Ignore the next letter for this pass. */ | |
1542 | c = *++p; | |
1543 | break; | |
94e6f783 | 1544 | |
97488870 R |
1545 | case '?': |
1546 | alt_cost += 2; | |
1547 | case '!': case '#': case '&': | |
1548 | case '0': case '1': case '2': case '3': case '4': | |
1549 | case '5': case '6': case '7': case '8': case '9': | |
1550 | break; | |
e4600702 | 1551 | |
97488870 R |
1552 | case 'p': |
1553 | allows_addr = 1; | |
1554 | win = address_operand (op, GET_MODE (op)); | |
1555 | /* We know this operand is an address, so we want it to be | |
1556 | allocated to a register that can be the base of an | |
1557 | address, ie BASE_REG_CLASS. */ | |
1558 | classes[i] | |
1559 | = reg_class_subunion[(int) classes[i]] | |
1560 | [(int) MODE_BASE_REG_CLASS (VOIDmode)]; | |
1561 | break; | |
e4600702 | 1562 | |
97488870 R |
1563 | case 'm': case 'o': case 'V': |
1564 | /* It doesn't seem worth distinguishing between offsettable | |
1565 | and non-offsettable addresses here. */ | |
1566 | allows_mem[i] = 1; | |
1567 | if (GET_CODE (op) == MEM) | |
1568 | win = 1; | |
1569 | break; | |
e4600702 | 1570 | |
97488870 R |
1571 | case '<': |
1572 | if (GET_CODE (op) == MEM | |
1573 | && (GET_CODE (XEXP (op, 0)) == PRE_DEC | |
1574 | || GET_CODE (XEXP (op, 0)) == POST_DEC)) | |
1575 | win = 1; | |
1576 | break; | |
e4600702 | 1577 | |
97488870 R |
1578 | case '>': |
1579 | if (GET_CODE (op) == MEM | |
1580 | && (GET_CODE (XEXP (op, 0)) == PRE_INC | |
1581 | || GET_CODE (XEXP (op, 0)) == POST_INC)) | |
1582 | win = 1; | |
1583 | break; | |
e4600702 | 1584 | |
97488870 R |
1585 | case 'E': |
1586 | case 'F': | |
1587 | if (GET_CODE (op) == CONST_DOUBLE | |
1588 | || (GET_CODE (op) == CONST_VECTOR | |
1589 | && (GET_MODE_CLASS (GET_MODE (op)) | |
1590 | == MODE_VECTOR_FLOAT))) | |
1591 | win = 1; | |
1592 | break; | |
e4600702 | 1593 | |
97488870 R |
1594 | case 'G': |
1595 | case 'H': | |
1596 | if (GET_CODE (op) == CONST_DOUBLE | |
1597 | && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, c, p)) | |
1598 | win = 1; | |
e4600702 | 1599 | break; |
97488870 R |
1600 | |
1601 | case 's': | |
1602 | if (GET_CODE (op) == CONST_INT | |
1603 | || (GET_CODE (op) == CONST_DOUBLE | |
1604 | && GET_MODE (op) == VOIDmode)) | |
1605 | break; | |
1606 | case 'i': | |
1607 | if (CONSTANT_P (op) | |
e4600702 | 1608 | #ifdef LEGITIMATE_PIC_OPERAND_P |
97488870 | 1609 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) |
e4600702 | 1610 | #endif |
97488870 R |
1611 | ) |
1612 | win = 1; | |
1613 | break; | |
e4600702 | 1614 | |
97488870 R |
1615 | case 'n': |
1616 | if (GET_CODE (op) == CONST_INT | |
1617 | || (GET_CODE (op) == CONST_DOUBLE | |
1618 | && GET_MODE (op) == VOIDmode)) | |
1619 | win = 1; | |
1620 | break; | |
e4600702 | 1621 | |
97488870 R |
1622 | case 'I': |
1623 | case 'J': | |
1624 | case 'K': | |
1625 | case 'L': | |
1626 | case 'M': | |
1627 | case 'N': | |
1628 | case 'O': | |
1629 | case 'P': | |
1630 | if (GET_CODE (op) == CONST_INT | |
1631 | && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), c, p)) | |
1632 | win = 1; | |
1633 | break; | |
e4600702 | 1634 | |
97488870 R |
1635 | case 'X': |
1636 | win = 1; | |
1637 | break; | |
54dac99e | 1638 | |
97488870 R |
1639 | case 'g': |
1640 | if (GET_CODE (op) == MEM | |
1641 | || (CONSTANT_P (op) | |
e4600702 | 1642 | #ifdef LEGITIMATE_PIC_OPERAND_P |
97488870 | 1643 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) |
54dac99e | 1644 | #endif |
97488870 R |
1645 | )) |
1646 | win = 1; | |
1647 | allows_mem[i] = 1; | |
1648 | case 'r': | |
c2cba7a9 | 1649 | classes[i] |
97488870 R |
1650 | = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS]; |
1651 | break; | |
ccfc6cc8 | 1652 | |
97488870 R |
1653 | default: |
1654 | if (REG_CLASS_FROM_CONSTRAINT (c, p) != NO_REGS) | |
ccfc6cc8 UW |
1655 | classes[i] |
1656 | = reg_class_subunion[(int) classes[i]] | |
97488870 R |
1657 | [(int) REG_CLASS_FROM_CONSTRAINT (c, p)]; |
1658 | #ifdef EXTRA_CONSTRAINT_STR | |
1659 | else if (EXTRA_CONSTRAINT_STR (op, c, p)) | |
1660 | win = 1; | |
1661 | ||
1662 | if (EXTRA_MEMORY_CONSTRAINT (c, p)) | |
1663 | { | |
1664 | /* Every MEM can be reloaded to fit. */ | |
1665 | allows_mem[i] = 1; | |
1666 | if (GET_CODE (op) == MEM) | |
1667 | win = 1; | |
1668 | } | |
1669 | if (EXTRA_ADDRESS_CONSTRAINT (c, p)) | |
1670 | { | |
1671 | /* Every address can be reloaded to fit. */ | |
1672 | allows_addr = 1; | |
1673 | if (address_operand (op, GET_MODE (op))) | |
1674 | win = 1; | |
1675 | /* We know this operand is an address, so we want it to | |
1676 | be allocated to a register that can be the base of an | |
1677 | address, ie BASE_REG_CLASS. */ | |
1678 | classes[i] | |
1679 | = reg_class_subunion[(int) classes[i]] | |
1680 | [(int) MODE_BASE_REG_CLASS (VOIDmode)]; | |
1681 | } | |
c2cba7a9 | 1682 | #endif |
97488870 R |
1683 | break; |
1684 | } | |
1685 | p += CONSTRAINT_LEN (c, p); | |
1686 | if (c == ',') | |
c2cba7a9 | 1687 | break; |
97488870 | 1688 | } |
e4600702 RK |
1689 | |
1690 | constraints[i] = p; | |
1691 | ||
1692 | /* How we account for this operand now depends on whether it is a | |
1693 | pseudo register or not. If it is, we first check if any | |
1694 | register classes are valid. If not, we ignore this alternative, | |
1695 | since we want to assume that all pseudos get allocated for | |
1696 | register preferencing. If some register class is valid, compute | |
1697 | the costs of moving the pseudo into that class. */ | |
1698 | ||
1699 | if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
4db18574 | 1700 | { |
e4600702 | 1701 | if (classes[i] == NO_REGS) |
94e6f783 | 1702 | { |
e79f71f7 GK |
1703 | /* We must always fail if the operand is a REG, but |
1704 | we did not find a suitable class. | |
a6a2274a | 1705 | |
e79f71f7 GK |
1706 | Otherwise we may perform an uninitialized read |
1707 | from this_op_costs after the `continue' statement | |
1708 | below. */ | |
1709 | alt_fail = 1; | |
94e6f783 | 1710 | } |
e4600702 RK |
1711 | else |
1712 | { | |
1713 | struct costs *pp = &this_op_costs[i]; | |
1714 | ||
1715 | for (class = 0; class < N_REG_CLASSES; class++) | |
14a774a9 | 1716 | pp->cost[class] |
d5e2075d | 1717 | = ((recog_data.operand_type[i] != OP_OUT |
e56b4594 | 1718 | ? may_move_in_cost[mode][class][(int) classes[i]] |
d5e2075d JH |
1719 | : 0) |
1720 | + (recog_data.operand_type[i] != OP_IN | |
e56b4594 | 1721 | ? may_move_out_cost[mode][(int) classes[i]][class] |
d5e2075d | 1722 | : 0)); |
e4600702 RK |
1723 | |
1724 | /* If the alternative actually allows memory, make things | |
1725 | a bit cheaper since we won't need an extra insn to | |
1726 | load it. */ | |
1727 | ||
14a774a9 | 1728 | pp->mem_cost |
d5e2075d JH |
1729 | = ((recog_data.operand_type[i] != OP_IN |
1730 | ? MEMORY_MOVE_COST (mode, classes[i], 0) | |
1731 | : 0) | |
1732 | + (recog_data.operand_type[i] != OP_OUT | |
1733 | ? MEMORY_MOVE_COST (mode, classes[i], 1) | |
1734 | : 0) - allows_mem[i]); | |
e4600702 RK |
1735 | |
1736 | /* If we have assigned a class to this register in our | |
1737 | first pass, add a cost to this alternative corresponding | |
1738 | to what we would add if this register were not in the | |
1739 | appropriate class. */ | |
1740 | ||
9ffc5a70 | 1741 | if (reg_pref) |
e4600702 | 1742 | alt_cost |
e56b4594 AO |
1743 | += (may_move_in_cost[mode] |
1744 | [(unsigned char) reg_pref[REGNO (op)].prefclass] | |
14a774a9 | 1745 | [(int) classes[i]]); |
e4600702 | 1746 | } |
4db18574 | 1747 | } |
54dac99e | 1748 | |
e4600702 RK |
1749 | /* Otherwise, if this alternative wins, either because we |
1750 | have already determined that or if we have a hard register of | |
1751 | the proper class, there is no cost for this alternative. */ | |
54dac99e | 1752 | |
e4600702 RK |
1753 | else if (win |
1754 | || (GET_CODE (op) == REG | |
6f654776 | 1755 | && reg_fits_class_p (op, classes[i], 0, GET_MODE (op)))) |
e4600702 | 1756 | ; |
54dac99e | 1757 | |
e4600702 RK |
1758 | /* If registers are valid, the cost of this alternative includes |
1759 | copying the object to and/or from a register. */ | |
54dac99e | 1760 | |
e4600702 RK |
1761 | else if (classes[i] != NO_REGS) |
1762 | { | |
1ccbefce | 1763 | if (recog_data.operand_type[i] != OP_OUT) |
e4600702 | 1764 | alt_cost += copy_cost (op, mode, classes[i], 1); |
54dac99e | 1765 | |
1ccbefce | 1766 | if (recog_data.operand_type[i] != OP_IN) |
e4600702 RK |
1767 | alt_cost += copy_cost (op, mode, classes[i], 0); |
1768 | } | |
54dac99e | 1769 | |
e4600702 RK |
1770 | /* The only other way this alternative can be used is if this is a |
1771 | constant that could be placed into memory. */ | |
1772 | ||
da2c0219 | 1773 | else if (CONSTANT_P (op) && (allows_addr || allows_mem[i])) |
cbd5b9a2 | 1774 | alt_cost += MEMORY_MOVE_COST (mode, classes[i], 1); |
e4600702 RK |
1775 | else |
1776 | alt_fail = 1; | |
1777 | } | |
1778 | ||
1779 | if (alt_fail) | |
1780 | continue; | |
1781 | ||
1782 | /* Finally, update the costs with the information we've calculated | |
1783 | about this alternative. */ | |
1784 | ||
1785 | for (i = 0; i < n_ops; i++) | |
1786 | if (GET_CODE (ops[i]) == REG | |
1787 | && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) | |
54dac99e | 1788 | { |
e4600702 | 1789 | struct costs *pp = &op_costs[i], *qq = &this_op_costs[i]; |
1ccbefce | 1790 | int scale = 1 + (recog_data.operand_type[i] == OP_INOUT); |
54dac99e | 1791 | |
e4600702 RK |
1792 | pp->mem_cost = MIN (pp->mem_cost, |
1793 | (qq->mem_cost + alt_cost) * scale); | |
54dac99e | 1794 | |
e4600702 RK |
1795 | for (class = 0; class < N_REG_CLASSES; class++) |
1796 | pp->cost[class] = MIN (pp->cost[class], | |
1797 | (qq->cost[class] + alt_cost) * scale); | |
1798 | } | |
1799 | } | |
ec2d92af RK |
1800 | |
1801 | /* If this insn is a single set copying operand 1 to operand 0 | |
accef103 JL |
1802 | and one operand is a pseudo with the other a hard reg or a pseudo |
1803 | that prefers a register that is in its own register class then | |
1804 | we may want to adjust the cost of that register class to -1. | |
a6a2274a | 1805 | |
accef103 | 1806 | Avoid the adjustment if the source does not die to avoid stressing of |
4d6922ee | 1807 | register allocator by preferrencing two colliding registers into single |
accef103 JL |
1808 | class. |
1809 | ||
1810 | Also avoid the adjustment if a copy between registers of the class | |
1811 | is expensive (ten times the cost of a default copy is considered | |
1812 | arbitrarily expensive). This avoids losing when the preferred class | |
1813 | is very expensive as the source of a copy instruction. */ | |
ec2d92af RK |
1814 | |
1815 | if ((set = single_set (insn)) != 0 | |
1816 | && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set) | |
0dc0641b JH |
1817 | && GET_CODE (ops[0]) == REG && GET_CODE (ops[1]) == REG |
1818 | && find_regno_note (insn, REG_DEAD, REGNO (ops[1]))) | |
ec2d92af RK |
1819 | for (i = 0; i <= 1; i++) |
1820 | if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) | |
1821 | { | |
770ae6cc | 1822 | unsigned int regno = REGNO (ops[!i]); |
ec2d92af RK |
1823 | enum machine_mode mode = GET_MODE (ops[!i]); |
1824 | int class; | |
770ae6cc | 1825 | unsigned int nr; |
ec2d92af | 1826 | |
accef103 JL |
1827 | if (regno >= FIRST_PSEUDO_REGISTER && reg_pref != 0) |
1828 | { | |
1829 | enum reg_class pref = reg_pref[regno].prefclass; | |
1830 | ||
1831 | if ((reg_class_size[(unsigned char) pref] | |
f7043461 | 1832 | == (unsigned) CLASS_MAX_NREGS (pref, mode)) |
e56b4594 | 1833 | && REGISTER_MOVE_COST (mode, pref, pref) < 10 * 2) |
accef103 JL |
1834 | op_costs[i].cost[(unsigned char) pref] = -1; |
1835 | } | |
ec2d92af RK |
1836 | else if (regno < FIRST_PSEUDO_REGISTER) |
1837 | for (class = 0; class < N_REG_CLASSES; class++) | |
1838 | if (TEST_HARD_REG_BIT (reg_class_contents[class], regno) | |
f7043461 | 1839 | && reg_class_size[class] == (unsigned) CLASS_MAX_NREGS (class, mode)) |
4841ba4b RK |
1840 | { |
1841 | if (reg_class_size[class] == 1) | |
1842 | op_costs[i].cost[class] = -1; | |
1843 | else | |
1844 | { | |
66fd46b6 | 1845 | for (nr = 0; nr < (unsigned) hard_regno_nregs[regno][mode]; nr++) |
4841ba4b | 1846 | { |
770ae6cc RK |
1847 | if (! TEST_HARD_REG_BIT (reg_class_contents[class], |
1848 | regno + nr)) | |
4841ba4b RK |
1849 | break; |
1850 | } | |
1851 | ||
66fd46b6 | 1852 | if (nr == (unsigned) hard_regno_nregs[regno][mode]) |
4841ba4b RK |
1853 | op_costs[i].cost[class] = -1; |
1854 | } | |
1855 | } | |
ec2d92af | 1856 | } |
54dac99e | 1857 | } |
e4600702 | 1858 | \f |
40f03658 | 1859 | /* Compute the cost of loading X into (if TO_P is nonzero) or from (if |
e4600702 RK |
1860 | TO_P is zero) a register of class CLASS in mode MODE. |
1861 | ||
1862 | X must not be a pseudo. */ | |
1863 | ||
1864 | static int | |
0c20a65f AJ |
1865 | copy_cost (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED, |
1866 | enum reg_class class, int to_p ATTRIBUTE_UNUSED) | |
e4600702 | 1867 | { |
29a82058 | 1868 | #ifdef HAVE_SECONDARY_RELOADS |
e4600702 | 1869 | enum reg_class secondary_class = NO_REGS; |
29a82058 | 1870 | #endif |
e4600702 RK |
1871 | |
1872 | /* If X is a SCRATCH, there is actually nothing to move since we are | |
1873 | assuming optimal allocation. */ | |
1874 | ||
1875 | if (GET_CODE (x) == SCRATCH) | |
1876 | return 0; | |
1877 | ||
1878 | /* Get the class we will actually use for a reload. */ | |
1879 | class = PREFERRED_RELOAD_CLASS (x, class); | |
1880 | ||
1881 | #ifdef HAVE_SECONDARY_RELOADS | |
a6a2274a | 1882 | /* If we need a secondary reload (we assume here that we are using |
e4600702 RK |
1883 | the secondary reload as an intermediate, not a scratch register), the |
1884 | cost is that to load the input into the intermediate register, then | |
1885 | to copy them. We use a special value of TO_P to avoid recursion. */ | |
1886 | ||
1887 | #ifdef SECONDARY_INPUT_RELOAD_CLASS | |
1888 | if (to_p == 1) | |
1889 | secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x); | |
1890 | #endif | |
1891 | ||
dd9f0e8f | 1892 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS |
e4600702 RK |
1893 | if (! to_p) |
1894 | secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x); | |
1895 | #endif | |
1896 | ||
1897 | if (secondary_class != NO_REGS) | |
e56b4594 | 1898 | return (move_cost[mode][(int) secondary_class][(int) class] |
e4600702 | 1899 | + copy_cost (x, mode, secondary_class, 2)); |
dd9f0e8f | 1900 | #endif /* HAVE_SECONDARY_RELOADS */ |
e4600702 RK |
1901 | |
1902 | /* For memory, use the memory move cost, for (hard) registers, use the | |
1903 | cost to move between the register classes, and use 2 for everything | |
1904 | else (constants). */ | |
1905 | ||
1906 | if (GET_CODE (x) == MEM || class == NO_REGS) | |
cbd5b9a2 | 1907 | return MEMORY_MOVE_COST (mode, class, to_p); |
54dac99e | 1908 | |
e4600702 | 1909 | else if (GET_CODE (x) == REG) |
e56b4594 | 1910 | return move_cost[mode][(int) REGNO_REG_CLASS (REGNO (x))][(int) class]; |
e4600702 RK |
1911 | |
1912 | else | |
1913 | /* If this is a constant, we may eventually want to call rtx_cost here. */ | |
b437f1a7 | 1914 | return COSTS_N_INSNS (1); |
e4600702 RK |
1915 | } |
1916 | \f | |
54dac99e RK |
1917 | /* Record the pseudo registers we must reload into hard registers |
1918 | in a subexpression of a memory address, X. | |
e4600702 RK |
1919 | |
1920 | CLASS is the class that the register needs to be in and is either | |
1921 | BASE_REG_CLASS or INDEX_REG_CLASS. | |
1922 | ||
1923 | SCALE is twice the amount to multiply the cost by (it is twice so we | |
1924 | can represent half-cost adjustments). */ | |
54dac99e | 1925 | |
197d6480 | 1926 | static void |
0c20a65f | 1927 | record_address_regs (rtx x, enum reg_class class, int scale) |
54dac99e | 1928 | { |
b3694847 | 1929 | enum rtx_code code = GET_CODE (x); |
54dac99e RK |
1930 | |
1931 | switch (code) | |
1932 | { | |
1933 | case CONST_INT: | |
1934 | case CONST: | |
1935 | case CC0: | |
1936 | case PC: | |
1937 | case SYMBOL_REF: | |
1938 | case LABEL_REF: | |
1939 | return; | |
1940 | ||
1941 | case PLUS: | |
1942 | /* When we have an address that is a sum, | |
1943 | we must determine whether registers are "base" or "index" regs. | |
1944 | If there is a sum of two registers, we must choose one to be | |
3502dc9c JDA |
1945 | the "base". Luckily, we can use the REG_POINTER to make a good |
1946 | choice most of the time. We only need to do this on machines | |
1947 | that can have two registers in an address and where the base | |
1948 | and index register classes are different. | |
e4600702 RK |
1949 | |
1950 | ??? This code used to set REGNO_POINTER_FLAG in some cases, but | |
1951 | that seems bogus since it should only be set when we are sure | |
1952 | the register is being used as a pointer. */ | |
1953 | ||
54dac99e RK |
1954 | { |
1955 | rtx arg0 = XEXP (x, 0); | |
1956 | rtx arg1 = XEXP (x, 1); | |
b3694847 SS |
1957 | enum rtx_code code0 = GET_CODE (arg0); |
1958 | enum rtx_code code1 = GET_CODE (arg1); | |
54dac99e RK |
1959 | |
1960 | /* Look inside subregs. */ | |
e4600702 | 1961 | if (code0 == SUBREG) |
54dac99e | 1962 | arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0); |
e4600702 | 1963 | if (code1 == SUBREG) |
54dac99e RK |
1964 | arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1); |
1965 | ||
e4600702 RK |
1966 | /* If this machine only allows one register per address, it must |
1967 | be in the first operand. */ | |
1968 | ||
1969 | if (MAX_REGS_PER_ADDRESS == 1) | |
1970 | record_address_regs (arg0, class, scale); | |
1971 | ||
1972 | /* If index and base registers are the same on this machine, just | |
1973 | record registers in any non-constant operands. We assume here, | |
a6a2274a | 1974 | as well as in the tests below, that all addresses are in |
e4600702 RK |
1975 | canonical form. */ |
1976 | ||
3dcc68a4 | 1977 | else if (INDEX_REG_CLASS == MODE_BASE_REG_CLASS (VOIDmode)) |
54dac99e | 1978 | { |
e4600702 RK |
1979 | record_address_regs (arg0, class, scale); |
1980 | if (! CONSTANT_P (arg1)) | |
1981 | record_address_regs (arg1, class, scale); | |
54dac99e | 1982 | } |
e4600702 RK |
1983 | |
1984 | /* If the second operand is a constant integer, it doesn't change | |
1985 | what class the first operand must be. */ | |
1986 | ||
1987 | else if (code1 == CONST_INT || code1 == CONST_DOUBLE) | |
1988 | record_address_regs (arg0, class, scale); | |
1989 | ||
1990 | /* If the second operand is a symbolic constant, the first operand | |
1991 | must be an index register. */ | |
1992 | ||
1993 | else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF) | |
1994 | record_address_regs (arg0, INDEX_REG_CLASS, scale); | |
1995 | ||
956d6950 JL |
1996 | /* If both operands are registers but one is already a hard register |
1997 | of index or base class, give the other the class that the hard | |
1998 | register is not. */ | |
1999 | ||
3f9e9508 | 2000 | #ifdef REG_OK_FOR_BASE_P |
956d6950 JL |
2001 | else if (code0 == REG && code1 == REG |
2002 | && REGNO (arg0) < FIRST_PSEUDO_REGISTER | |
2003 | && (REG_OK_FOR_BASE_P (arg0) || REG_OK_FOR_INDEX_P (arg0))) | |
2004 | record_address_regs (arg1, | |
2005 | REG_OK_FOR_BASE_P (arg0) | |
3dcc68a4 | 2006 | ? INDEX_REG_CLASS : MODE_BASE_REG_CLASS (VOIDmode), |
956d6950 JL |
2007 | scale); |
2008 | else if (code0 == REG && code1 == REG | |
2009 | && REGNO (arg1) < FIRST_PSEUDO_REGISTER | |
2010 | && (REG_OK_FOR_BASE_P (arg1) || REG_OK_FOR_INDEX_P (arg1))) | |
2011 | record_address_regs (arg0, | |
2012 | REG_OK_FOR_BASE_P (arg1) | |
3dcc68a4 | 2013 | ? INDEX_REG_CLASS : MODE_BASE_REG_CLASS (VOIDmode), |
956d6950 | 2014 | scale); |
3f9e9508 | 2015 | #endif |
956d6950 | 2016 | |
e9a25f70 JL |
2017 | /* If one operand is known to be a pointer, it must be the base |
2018 | with the other operand the index. Likewise if the other operand | |
2019 | is a MULT. */ | |
f22376c7 | 2020 | |
3502dc9c | 2021 | else if ((code0 == REG && REG_POINTER (arg0)) |
e9a25f70 | 2022 | || code1 == MULT) |
f22376c7 | 2023 | { |
3dcc68a4 | 2024 | record_address_regs (arg0, MODE_BASE_REG_CLASS (VOIDmode), scale); |
f22376c7 CI |
2025 | record_address_regs (arg1, INDEX_REG_CLASS, scale); |
2026 | } | |
3502dc9c | 2027 | else if ((code1 == REG && REG_POINTER (arg1)) |
e9a25f70 | 2028 | || code0 == MULT) |
f22376c7 CI |
2029 | { |
2030 | record_address_regs (arg0, INDEX_REG_CLASS, scale); | |
3dcc68a4 | 2031 | record_address_regs (arg1, MODE_BASE_REG_CLASS (VOIDmode), scale); |
f22376c7 CI |
2032 | } |
2033 | ||
e9a25f70 | 2034 | /* Otherwise, count equal chances that each might be a base |
e4600702 RK |
2035 | or index register. This case should be rare. */ |
2036 | ||
e9a25f70 | 2037 | else |
54dac99e | 2038 | { |
3dcc68a4 NC |
2039 | record_address_regs (arg0, MODE_BASE_REG_CLASS (VOIDmode), |
2040 | scale / 2); | |
e4600702 | 2041 | record_address_regs (arg0, INDEX_REG_CLASS, scale / 2); |
3dcc68a4 NC |
2042 | record_address_regs (arg1, MODE_BASE_REG_CLASS (VOIDmode), |
2043 | scale / 2); | |
e4600702 | 2044 | record_address_regs (arg1, INDEX_REG_CLASS, scale / 2); |
54dac99e | 2045 | } |
54dac99e RK |
2046 | } |
2047 | break; | |
2048 | ||
4b983fdc RH |
2049 | /* Double the importance of a pseudo register that is incremented |
2050 | or decremented, since it would take two extra insns | |
2051 | if it ends up in the wrong place. */ | |
2052 | case POST_MODIFY: | |
2053 | case PRE_MODIFY: | |
3dcc68a4 NC |
2054 | record_address_regs (XEXP (x, 0), MODE_BASE_REG_CLASS (VOIDmode), |
2055 | 2 * scale); | |
4b983fdc RH |
2056 | if (REG_P (XEXP (XEXP (x, 1), 1))) |
2057 | record_address_regs (XEXP (XEXP (x, 1), 1), | |
2058 | INDEX_REG_CLASS, 2 * scale); | |
2059 | break; | |
2060 | ||
54dac99e RK |
2061 | case POST_INC: |
2062 | case PRE_INC: | |
2063 | case POST_DEC: | |
2064 | case PRE_DEC: | |
2065 | /* Double the importance of a pseudo register that is incremented | |
2066 | or decremented, since it would take two extra insns | |
533d0835 RK |
2067 | if it ends up in the wrong place. If the operand is a pseudo, |
2068 | show it is being used in an INC_DEC context. */ | |
2069 | ||
2070 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
2071 | if (GET_CODE (XEXP (x, 0)) == REG | |
2072 | && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER) | |
2073 | in_inc_dec[REGNO (XEXP (x, 0))] = 1; | |
2074 | #endif | |
e4600702 RK |
2075 | |
2076 | record_address_regs (XEXP (x, 0), class, 2 * scale); | |
54dac99e RK |
2077 | break; |
2078 | ||
2079 | case REG: | |
2080 | { | |
b3694847 SS |
2081 | struct costs *pp = &costs[REGNO (x)]; |
2082 | int i; | |
54dac99e | 2083 | |
cbd5b9a2 | 2084 | pp->mem_cost += (MEMORY_MOVE_COST (Pmode, class, 1) * scale) / 2; |
54dac99e | 2085 | |
e4600702 | 2086 | for (i = 0; i < N_REG_CLASSES; i++) |
e56b4594 | 2087 | pp->cost[i] += (may_move_in_cost[Pmode][i][(int) class] * scale) / 2; |
54dac99e RK |
2088 | } |
2089 | break; | |
2090 | ||
2091 | default: | |
2092 | { | |
b3694847 SS |
2093 | const char *fmt = GET_RTX_FORMAT (code); |
2094 | int i; | |
54dac99e RK |
2095 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
2096 | if (fmt[i] == 'e') | |
e4600702 | 2097 | record_address_regs (XEXP (x, i), class, scale); |
54dac99e RK |
2098 | } |
2099 | } | |
2100 | } | |
08d95f91 RK |
2101 | \f |
2102 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
2103 | ||
2104 | /* Return 1 if REG is valid as an auto-increment memory reference | |
2105 | to an object of MODE. */ | |
2106 | ||
1d300e19 | 2107 | static int |
0c20a65f | 2108 | auto_inc_dec_reg_p (rtx reg, enum machine_mode mode) |
08d95f91 | 2109 | { |
940da324 JL |
2110 | if (HAVE_POST_INCREMENT |
2111 | && memory_address_p (mode, gen_rtx_POST_INC (Pmode, reg))) | |
08d95f91 | 2112 | return 1; |
08d95f91 | 2113 | |
940da324 JL |
2114 | if (HAVE_POST_DECREMENT |
2115 | && memory_address_p (mode, gen_rtx_POST_DEC (Pmode, reg))) | |
08d95f91 | 2116 | return 1; |
08d95f91 | 2117 | |
940da324 JL |
2118 | if (HAVE_PRE_INCREMENT |
2119 | && memory_address_p (mode, gen_rtx_PRE_INC (Pmode, reg))) | |
08d95f91 | 2120 | return 1; |
08d95f91 | 2121 | |
940da324 JL |
2122 | if (HAVE_PRE_DECREMENT |
2123 | && memory_address_p (mode, gen_rtx_PRE_DEC (Pmode, reg))) | |
08d95f91 | 2124 | return 1; |
08d95f91 RK |
2125 | |
2126 | return 0; | |
2127 | } | |
2128 | #endif | |
b1f21e0a | 2129 | \f |
da668e9c MM |
2130 | static short *renumber; |
2131 | static size_t regno_allocated; | |
2132 | static unsigned int reg_n_max; | |
ed396e68 | 2133 | |
b1f21e0a MM |
2134 | /* Allocate enough space to hold NUM_REGS registers for the tables used for |
2135 | reg_scan and flow_analysis that are indexed by the register number. If | |
88cad84b | 2136 | NEW_P is nonzero, initialize all of the registers, otherwise only |
39379e67 MM |
2137 | initialize the new registers allocated. The same table is kept from |
2138 | function to function, only reallocating it when we need more room. If | |
88cad84b | 2139 | RENUMBER_P is nonzero, allocate the reg_renumber array also. */ |
b1f21e0a MM |
2140 | |
2141 | void | |
0c20a65f | 2142 | allocate_reg_info (size_t num_regs, int new_p, int renumber_p) |
b1f21e0a | 2143 | { |
6feacd09 MM |
2144 | size_t size_info; |
2145 | size_t size_renumber; | |
2146 | size_t min = (new_p) ? 0 : reg_n_max; | |
2147 | struct reg_info_data *reg_data; | |
39379e67 | 2148 | |
b1f21e0a MM |
2149 | if (num_regs > regno_allocated) |
2150 | { | |
6feacd09 MM |
2151 | size_t old_allocated = regno_allocated; |
2152 | ||
938d968e | 2153 | regno_allocated = num_regs + (num_regs / 20); /* Add some slop space. */ |
39379e67 MM |
2154 | size_renumber = regno_allocated * sizeof (short); |
2155 | ||
2156 | if (!reg_n_info) | |
2157 | { | |
6feacd09 | 2158 | VARRAY_REG_INIT (reg_n_info, regno_allocated, "reg_n_info"); |
703ad42b KG |
2159 | renumber = xmalloc (size_renumber); |
2160 | reg_pref_buffer = xmalloc (regno_allocated | |
2161 | * sizeof (struct reg_pref)); | |
39379e67 MM |
2162 | } |
2163 | ||
2164 | else | |
2165 | { | |
6feacd09 MM |
2166 | VARRAY_GROW (reg_n_info, regno_allocated); |
2167 | ||
938d968e | 2168 | if (new_p) /* If we're zapping everything, no need to realloc. */ |
6feacd09 | 2169 | { |
8e2e89f7 KH |
2170 | free ((char *) renumber); |
2171 | free ((char *) reg_pref); | |
703ad42b KG |
2172 | renumber = xmalloc (size_renumber); |
2173 | reg_pref_buffer = xmalloc (regno_allocated | |
2174 | * sizeof (struct reg_pref)); | |
6feacd09 MM |
2175 | } |
2176 | ||
2177 | else | |
2178 | { | |
703ad42b KG |
2179 | renumber = xrealloc (renumber, size_renumber); |
2180 | reg_pref_buffer = xrealloc (reg_pref_buffer, | |
2181 | regno_allocated | |
2182 | * sizeof (struct reg_pref)); | |
6feacd09 | 2183 | } |
39379e67 | 2184 | } |
6feacd09 MM |
2185 | |
2186 | size_info = (regno_allocated - old_allocated) * sizeof (reg_info) | |
2187 | + sizeof (struct reg_info_data) - sizeof (reg_info); | |
703ad42b | 2188 | reg_data = xcalloc (size_info, 1); |
6feacd09 MM |
2189 | reg_data->min_index = old_allocated; |
2190 | reg_data->max_index = regno_allocated - 1; | |
2191 | reg_data->next = reg_info_head; | |
2192 | reg_info_head = reg_data; | |
b1f21e0a MM |
2193 | } |
2194 | ||
6feacd09 | 2195 | reg_n_max = num_regs; |
b1f21e0a MM |
2196 | if (min < num_regs) |
2197 | { | |
6feacd09 MM |
2198 | /* Loop through each of the segments allocated for the actual |
2199 | reg_info pages, and set up the pointers, zero the pages, etc. */ | |
a6a2274a | 2200 | for (reg_data = reg_info_head; |
da668e9c MM |
2201 | reg_data && reg_data->max_index >= min; |
2202 | reg_data = reg_data->next) | |
39379e67 | 2203 | { |
6feacd09 MM |
2204 | size_t min_index = reg_data->min_index; |
2205 | size_t max_index = reg_data->max_index; | |
da668e9c MM |
2206 | size_t max = MIN (max_index, num_regs); |
2207 | size_t local_min = min - min_index; | |
2208 | size_t i; | |
6feacd09 | 2209 | |
da668e9c MM |
2210 | if (reg_data->min_index > num_regs) |
2211 | continue; | |
6feacd09 | 2212 | |
da668e9c MM |
2213 | if (min < min_index) |
2214 | local_min = 0; | |
2215 | if (!reg_data->used_p) /* page just allocated with calloc */ | |
2216 | reg_data->used_p = 1; /* no need to zero */ | |
2217 | else | |
703ad42b KG |
2218 | memset (®_data->data[local_min], 0, |
2219 | sizeof (reg_info) * (max - min_index - local_min + 1)); | |
da668e9c MM |
2220 | |
2221 | for (i = min_index+local_min; i <= max; i++) | |
2222 | { | |
2223 | VARRAY_REG (reg_n_info, i) = ®_data->data[i-min_index]; | |
2224 | REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN; | |
2225 | renumber[i] = -1; | |
2226 | reg_pref_buffer[i].prefclass = (char) NO_REGS; | |
2227 | reg_pref_buffer[i].altclass = (char) NO_REGS; | |
6feacd09 | 2228 | } |
39379e67 | 2229 | } |
b1f21e0a MM |
2230 | } |
2231 | ||
6feacd09 MM |
2232 | /* If {pref,alt}class have already been allocated, update the pointers to |
2233 | the newly realloced ones. */ | |
9ffc5a70 JH |
2234 | if (reg_pref) |
2235 | reg_pref = reg_pref_buffer; | |
6feacd09 | 2236 | |
39379e67 MM |
2237 | if (renumber_p) |
2238 | reg_renumber = renumber; | |
2239 | ||
3eae4643 | 2240 | /* Tell the regset code about the new number of registers. */ |
73b76448 | 2241 | MAX_REGNO_REG_SET (num_regs, new_p, renumber_p); |
b1f21e0a MM |
2242 | } |
2243 | ||
ed396e68 BS |
2244 | /* Free up the space allocated by allocate_reg_info. */ |
2245 | void | |
0c20a65f | 2246 | free_reg_info (void) |
ed396e68 BS |
2247 | { |
2248 | if (reg_n_info) | |
2249 | { | |
2250 | struct reg_info_data *reg_data; | |
2251 | struct reg_info_data *reg_next; | |
2252 | ||
2253 | VARRAY_FREE (reg_n_info); | |
2254 | for (reg_data = reg_info_head; reg_data; reg_data = reg_next) | |
2255 | { | |
2256 | reg_next = reg_data->next; | |
8e2e89f7 | 2257 | free ((char *) reg_data); |
ed396e68 BS |
2258 | } |
2259 | ||
9ffc5a70 | 2260 | free (reg_pref_buffer); |
f4f4d0f8 KH |
2261 | reg_pref_buffer = (struct reg_pref *) 0; |
2262 | reg_info_head = (struct reg_info_data *) 0; | |
2263 | renumber = (short *) 0; | |
ed396e68 BS |
2264 | } |
2265 | regno_allocated = 0; | |
2266 | reg_n_max = 0; | |
2267 | } | |
54dac99e RK |
2268 | \f |
2269 | /* This is the `regscan' pass of the compiler, run just before cse | |
2270 | and again just before loop. | |
2271 | ||
2272 | It finds the first and last use of each pseudo-register | |
2273 | and records them in the vectors regno_first_uid, regno_last_uid | |
2274 | and counts the number of sets in the vector reg_n_sets. | |
2275 | ||
2276 | REPEAT is nonzero the second time this is called. */ | |
2277 | ||
54dac99e | 2278 | /* Maximum number of parallel sets and clobbers in any insn in this fn. |
d22d5f34 | 2279 | Always at least 3, since the combiner could put that many together |
79b9ec0d RK |
2280 | and we want this to remain correct for all the remaining passes. |
2281 | This corresponds to the maximum number of times note_stores will call | |
2282 | a function for any insn. */ | |
54dac99e RK |
2283 | |
2284 | int max_parallel; | |
2285 | ||
a6a2274a | 2286 | /* Used as a temporary to record the largest number of registers in |
79b9ec0d RK |
2287 | PARALLEL in a SET_DEST. This is added to max_parallel. */ |
2288 | ||
2289 | static int max_set_parallel; | |
2290 | ||
54dac99e | 2291 | void |
0c20a65f | 2292 | reg_scan (rtx f, unsigned int nregs, int repeat ATTRIBUTE_UNUSED) |
54dac99e | 2293 | { |
b3694847 | 2294 | rtx insn; |
54dac99e | 2295 | |
28cb2b14 RS |
2296 | timevar_push (TV_REG_SCAN); |
2297 | ||
39379e67 | 2298 | allocate_reg_info (nregs, TRUE, FALSE); |
54dac99e | 2299 | max_parallel = 3; |
79b9ec0d | 2300 | max_set_parallel = 0; |
54dac99e RK |
2301 | |
2302 | for (insn = f; insn; insn = NEXT_INSN (insn)) | |
28cb2b14 | 2303 | if (INSN_P (insn)) |
54dac99e | 2304 | { |
28cb2b14 RS |
2305 | rtx pat = PATTERN (insn); |
2306 | if (GET_CODE (pat) == PARALLEL | |
2307 | && XVECLEN (pat, 0) > max_parallel) | |
2308 | max_parallel = XVECLEN (pat, 0); | |
2309 | reg_scan_mark_refs (pat, insn, 0, 0); | |
01565a55 RK |
2310 | |
2311 | if (REG_NOTES (insn)) | |
f903b91f DM |
2312 | reg_scan_mark_refs (REG_NOTES (insn), insn, 1, 0); |
2313 | } | |
79b9ec0d RK |
2314 | |
2315 | max_parallel += max_set_parallel; | |
0d446150 JH |
2316 | |
2317 | timevar_pop (TV_REG_SCAN); | |
f903b91f DM |
2318 | } |
2319 | ||
2320 | /* Update 'regscan' information by looking at the insns | |
2321 | from FIRST to LAST. Some new REGs have been created, | |
2322 | and any REG with number greater than OLD_MAX_REGNO is | |
2323 | such a REG. We only update information for those. */ | |
2324 | ||
2325 | void | |
0c20a65f | 2326 | reg_scan_update (rtx first, rtx last, unsigned int old_max_regno) |
f903b91f | 2327 | { |
b3694847 | 2328 | rtx insn; |
f903b91f DM |
2329 | |
2330 | allocate_reg_info (max_reg_num (), FALSE, FALSE); | |
2331 | ||
2332 | for (insn = first; insn != last; insn = NEXT_INSN (insn)) | |
28cb2b14 | 2333 | if (INSN_P (insn)) |
f903b91f | 2334 | { |
28cb2b14 RS |
2335 | rtx pat = PATTERN (insn); |
2336 | if (GET_CODE (pat) == PARALLEL | |
2337 | && XVECLEN (pat, 0) > max_parallel) | |
2338 | max_parallel = XVECLEN (pat, 0); | |
2339 | reg_scan_mark_refs (pat, insn, 0, old_max_regno); | |
f903b91f DM |
2340 | |
2341 | if (REG_NOTES (insn)) | |
2342 | reg_scan_mark_refs (REG_NOTES (insn), insn, 1, old_max_regno); | |
54dac99e RK |
2343 | } |
2344 | } | |
2345 | ||
1ebecb64 | 2346 | /* X is the expression to scan. INSN is the insn it appears in. |
f903b91f DM |
2347 | NOTE_FLAG is nonzero if X is from INSN's notes rather than its body. |
2348 | We should only record information for REGs with numbers | |
2349 | greater than or equal to MIN_REGNO. */ | |
1ebecb64 | 2350 | |
08d95f91 | 2351 | static void |
0c20a65f | 2352 | reg_scan_mark_refs (rtx x, rtx insn, int note_flag, unsigned int min_regno) |
54dac99e | 2353 | { |
b3694847 SS |
2354 | enum rtx_code code; |
2355 | rtx dest; | |
2356 | rtx note; | |
54dac99e | 2357 | |
ed8d2920 MM |
2358 | if (!x) |
2359 | return; | |
fa23c636 | 2360 | code = GET_CODE (x); |
54dac99e RK |
2361 | switch (code) |
2362 | { | |
54dac99e | 2363 | case CONST: |
185ebd6c | 2364 | case CONST_INT: |
54dac99e | 2365 | case CONST_DOUBLE: |
69ef87e2 | 2366 | case CONST_VECTOR: |
54dac99e RK |
2367 | case CC0: |
2368 | case PC: | |
2369 | case SYMBOL_REF: | |
2370 | case LABEL_REF: | |
2371 | case ADDR_VEC: | |
2372 | case ADDR_DIFF_VEC: | |
2373 | return; | |
2374 | ||
2375 | case REG: | |
2376 | { | |
770ae6cc | 2377 | unsigned int regno = REGNO (x); |
54dac99e | 2378 | |
f903b91f DM |
2379 | if (regno >= min_regno) |
2380 | { | |
2381 | REGNO_LAST_NOTE_UID (regno) = INSN_UID (insn); | |
2382 | if (!note_flag) | |
2383 | REGNO_LAST_UID (regno) = INSN_UID (insn); | |
2384 | if (REGNO_FIRST_UID (regno) == 0) | |
2385 | REGNO_FIRST_UID (regno) = INSN_UID (insn); | |
ed8d2920 MM |
2386 | /* If we are called by reg_scan_update() (indicated by min_regno |
2387 | being set), we also need to update the reference count. */ | |
2388 | if (min_regno) | |
2389 | REG_N_REFS (regno)++; | |
f903b91f | 2390 | } |
54dac99e RK |
2391 | } |
2392 | break; | |
2393 | ||
01565a55 | 2394 | case EXPR_LIST: |
7b18c3db | 2395 | if (XEXP (x, 0)) |
f903b91f | 2396 | reg_scan_mark_refs (XEXP (x, 0), insn, note_flag, min_regno); |
01565a55 | 2397 | if (XEXP (x, 1)) |
f903b91f | 2398 | reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno); |
01565a55 RK |
2399 | break; |
2400 | ||
2401 | case INSN_LIST: | |
2402 | if (XEXP (x, 1)) | |
f903b91f | 2403 | reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno); |
01565a55 RK |
2404 | break; |
2405 | ||
ed8d2920 MM |
2406 | case CLOBBER: |
2407 | { | |
2408 | rtx reg = XEXP (x, 0); | |
2409 | if (REG_P (reg) | |
2410 | && REGNO (reg) >= min_regno) | |
2411 | { | |
2412 | REG_N_SETS (REGNO (reg))++; | |
2413 | REG_N_REFS (REGNO (reg))++; | |
2414 | } | |
aaf3ce3e DJ |
2415 | else if (GET_CODE (reg) == MEM) |
2416 | reg_scan_mark_refs (XEXP (reg, 0), insn, note_flag, min_regno); | |
ed8d2920 MM |
2417 | } |
2418 | break; | |
2419 | ||
54dac99e RK |
2420 | case SET: |
2421 | /* Count a set of the destination if it is a register. */ | |
2422 | for (dest = SET_DEST (x); | |
2423 | GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART | |
2424 | || GET_CODE (dest) == ZERO_EXTEND; | |
2425 | dest = XEXP (dest, 0)) | |
2426 | ; | |
2427 | ||
79b9ec0d RK |
2428 | /* For a PARALLEL, record the number of things (less the usual one for a |
2429 | SET) that are set. */ | |
2430 | if (GET_CODE (dest) == PARALLEL) | |
2431 | max_set_parallel = MAX (max_set_parallel, XVECLEN (dest, 0) - 1); | |
2432 | ||
f903b91f DM |
2433 | if (GET_CODE (dest) == REG |
2434 | && REGNO (dest) >= min_regno) | |
b2d57793 DB |
2435 | { |
2436 | REG_N_SETS (REGNO (dest))++; | |
2437 | REG_N_REFS (REGNO (dest))++; | |
2438 | } | |
54dac99e | 2439 | |
be8dcd74 RK |
2440 | /* If this is setting a pseudo from another pseudo or the sum of a |
2441 | pseudo and a constant integer and the other pseudo is known to be | |
2442 | a pointer, set the destination to be a pointer as well. | |
2443 | ||
2444 | Likewise if it is setting the destination from an address or from a | |
2445 | value equivalent to an address or to the sum of an address and | |
2446 | something else. | |
a6a2274a | 2447 | |
be8dcd74 RK |
2448 | But don't do any of this if the pseudo corresponds to a user |
2449 | variable since it should have already been set as a pointer based | |
2450 | on the type. */ | |
2451 | ||
2452 | if (GET_CODE (SET_DEST (x)) == REG | |
2453 | && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER | |
f903b91f | 2454 | && REGNO (SET_DEST (x)) >= min_regno |
64d3b4ca JL |
2455 | /* If the destination pseudo is set more than once, then other |
2456 | sets might not be to a pointer value (consider access to a | |
d55d8fc7 | 2457 | union in two threads of control in the presence of global |
3502dc9c | 2458 | optimizations). So only set REG_POINTER on the destination |
64d3b4ca JL |
2459 | pseudo if this is the only set of that pseudo. */ |
2460 | && REG_N_SETS (REGNO (SET_DEST (x))) == 1 | |
be8dcd74 | 2461 | && ! REG_USERVAR_P (SET_DEST (x)) |
3502dc9c | 2462 | && ! REG_POINTER (SET_DEST (x)) |
be8dcd74 | 2463 | && ((GET_CODE (SET_SRC (x)) == REG |
3502dc9c | 2464 | && REG_POINTER (SET_SRC (x))) |
be8dcd74 RK |
2465 | || ((GET_CODE (SET_SRC (x)) == PLUS |
2466 | || GET_CODE (SET_SRC (x)) == LO_SUM) | |
2467 | && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT | |
2468 | && GET_CODE (XEXP (SET_SRC (x), 0)) == REG | |
3502dc9c | 2469 | && REG_POINTER (XEXP (SET_SRC (x), 0))) |
be8dcd74 RK |
2470 | || GET_CODE (SET_SRC (x)) == CONST |
2471 | || GET_CODE (SET_SRC (x)) == SYMBOL_REF | |
2472 | || GET_CODE (SET_SRC (x)) == LABEL_REF | |
2473 | || (GET_CODE (SET_SRC (x)) == HIGH | |
2474 | && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST | |
2475 | || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF | |
2476 | || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF)) | |
2477 | || ((GET_CODE (SET_SRC (x)) == PLUS | |
2478 | || GET_CODE (SET_SRC (x)) == LO_SUM) | |
2479 | && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST | |
2480 | || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF | |
2481 | || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF)) | |
2482 | || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0 | |
2483 | && (GET_CODE (XEXP (note, 0)) == CONST | |
2484 | || GET_CODE (XEXP (note, 0)) == SYMBOL_REF | |
2485 | || GET_CODE (XEXP (note, 0)) == LABEL_REF)))) | |
3502dc9c | 2486 | REG_POINTER (SET_DEST (x)) = 1; |
be8dcd74 | 2487 | |
0d4903b8 | 2488 | /* If this is setting a register from a register or from a simple |
a560d4d4 | 2489 | conversion of a register, propagate REG_EXPR. */ |
0d4903b8 RK |
2490 | if (GET_CODE (dest) == REG) |
2491 | { | |
2492 | rtx src = SET_SRC (x); | |
2493 | ||
2494 | while (GET_CODE (src) == SIGN_EXTEND | |
2495 | || GET_CODE (src) == ZERO_EXTEND | |
2496 | || GET_CODE (src) == TRUNCATE | |
2497 | || (GET_CODE (src) == SUBREG && subreg_lowpart_p (src))) | |
2498 | src = XEXP (src, 0); | |
2499 | ||
a560d4d4 JH |
2500 | if (!REG_ATTRS (dest) && REG_P (src)) |
2501 | REG_ATTRS (dest) = REG_ATTRS (src); | |
2502 | if (!REG_ATTRS (dest) && GET_CODE (src) == MEM) | |
2503 | set_reg_attrs_from_mem (dest, src); | |
0d4903b8 RK |
2504 | } |
2505 | ||
0f41302f | 2506 | /* ... fall through ... */ |
54dac99e RK |
2507 | |
2508 | default: | |
2509 | { | |
b3694847 SS |
2510 | const char *fmt = GET_RTX_FORMAT (code); |
2511 | int i; | |
54dac99e RK |
2512 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
2513 | { | |
2514 | if (fmt[i] == 'e') | |
f903b91f | 2515 | reg_scan_mark_refs (XEXP (x, i), insn, note_flag, min_regno); |
54dac99e RK |
2516 | else if (fmt[i] == 'E' && XVEC (x, i) != 0) |
2517 | { | |
b3694847 | 2518 | int j; |
54dac99e | 2519 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
f903b91f | 2520 | reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag, min_regno); |
54dac99e RK |
2521 | } |
2522 | } | |
2523 | } | |
2524 | } | |
2525 | } | |
2526 | \f | |
2527 | /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1 | |
2528 | is also in C2. */ | |
2529 | ||
2530 | int | |
0c20a65f | 2531 | reg_class_subset_p (enum reg_class c1, enum reg_class c2) |
54dac99e RK |
2532 | { |
2533 | if (c1 == c2) return 1; | |
2534 | ||
2535 | if (c2 == ALL_REGS) | |
2536 | win: | |
2537 | return 1; | |
8e2e89f7 KH |
2538 | GO_IF_HARD_REG_SUBSET (reg_class_contents[(int) c1], |
2539 | reg_class_contents[(int) c2], | |
54dac99e RK |
2540 | win); |
2541 | return 0; | |
2542 | } | |
2543 | ||
2544 | /* Return nonzero if there is a register that is in both C1 and C2. */ | |
2545 | ||
2546 | int | |
0c20a65f | 2547 | reg_classes_intersect_p (enum reg_class c1, enum reg_class c2) |
54dac99e | 2548 | { |
49a27995 | 2549 | HARD_REG_SET c; |
54dac99e RK |
2550 | |
2551 | if (c1 == c2) return 1; | |
2552 | ||
2553 | if (c1 == ALL_REGS || c2 == ALL_REGS) | |
2554 | return 1; | |
2555 | ||
2556 | COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]); | |
2557 | AND_HARD_REG_SET (c, reg_class_contents[(int) c2]); | |
2558 | ||
2559 | GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose); | |
2560 | return 1; | |
2561 | ||
2562 | lose: | |
2563 | return 0; | |
2564 | } | |
2565 | ||
73b76448 RK |
2566 | /* Release any memory allocated by register sets. */ |
2567 | ||
2568 | void | |
0c20a65f | 2569 | regset_release_memory (void) |
73b76448 | 2570 | { |
73b76448 RK |
2571 | bitmap_release_memory (); |
2572 | } | |
e2500fed | 2573 | |
cff9f8d5 AH |
2574 | #ifdef CANNOT_CHANGE_MODE_CLASS |
2575 | /* Set bits in *USED which correspond to registers which can't change | |
2576 | their mode from FROM to any mode in which REGNO was encountered. */ | |
2577 | ||
2578 | void | |
0c20a65f AJ |
2579 | cannot_change_mode_set_regs (HARD_REG_SET *used, enum machine_mode from, |
2580 | unsigned int regno) | |
cff9f8d5 AH |
2581 | { |
2582 | enum machine_mode to; | |
10a3fdd9 JH |
2583 | int n, i; |
2584 | int start = regno * MAX_MACHINE_MODE; | |
cff9f8d5 | 2585 | |
10a3fdd9 JH |
2586 | EXECUTE_IF_SET_IN_BITMAP (&subregs_of_mode, start, n, |
2587 | if (n >= MAX_MACHINE_MODE + start) | |
2588 | return; | |
2589 | to = n - start; | |
2590 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
2591 | if (! TEST_HARD_REG_BIT (*used, i) | |
2592 | && REG_CANNOT_CHANGE_MODE_P (i, from, to)) | |
2593 | SET_HARD_REG_BIT (*used, i); | |
2594 | ); | |
cff9f8d5 AH |
2595 | } |
2596 | ||
2597 | /* Return 1 if REGNO has had an invalid mode change in CLASS from FROM | |
2598 | mode. */ | |
2599 | ||
2600 | bool | |
0c20a65f AJ |
2601 | invalid_mode_change_p (unsigned int regno, enum reg_class class, |
2602 | enum machine_mode from_mode) | |
cff9f8d5 AH |
2603 | { |
2604 | enum machine_mode to_mode; | |
10a3fdd9 JH |
2605 | int n; |
2606 | int start = regno * MAX_MACHINE_MODE; | |
2607 | ||
2608 | EXECUTE_IF_SET_IN_BITMAP (&subregs_of_mode, start, n, | |
2609 | if (n >= MAX_MACHINE_MODE + start) | |
2610 | return 0; | |
2611 | to_mode = n - start; | |
2612 | if (CANNOT_CHANGE_MODE_CLASS (from_mode, to_mode, class)) | |
cff9f8d5 | 2613 | return 1; |
10a3fdd9 | 2614 | ); |
cff9f8d5 AH |
2615 | return 0; |
2616 | } | |
2617 | #endif /* CANNOT_CHANGE_MODE_CLASS */ | |
2618 | ||
e2500fed | 2619 | #include "gt-regclass.h" |